diff options
Diffstat (limited to 'include/asm-i386')
| -rw-r--r-- | include/asm-i386/atomic.h | 1 | ||||
| -rw-r--r-- | include/asm-i386/bitops.h | 27 | ||||
| -rw-r--r-- | include/asm-i386/bugs.h | 23 | ||||
| -rw-r--r-- | include/asm-i386/cacheflush.h | 4 | ||||
| -rw-r--r-- | include/asm-i386/desc.h | 8 | ||||
| -rw-r--r-- | include/asm-i386/mach-bigsmp/mach_apic.h | 79 | ||||
| -rw-r--r-- | include/asm-i386/mach-bigsmp/mach_apicdef.h | 4 | ||||
| -rw-r--r-- | include/asm-i386/mman.h | 1 | ||||
| -rw-r--r-- | include/asm-i386/mmzone.h | 5 | ||||
| -rw-r--r-- | include/asm-i386/module.h | 4 | ||||
| -rw-r--r-- | include/asm-i386/mpspec_def.h | 2 | ||||
| -rw-r--r-- | include/asm-i386/segment.h | 14 | ||||
| -rw-r--r-- | include/asm-i386/system.h | 31 | ||||
| -rw-r--r-- | include/asm-i386/unistd.h | 2 |
14 files changed, 103 insertions, 102 deletions
diff --git a/include/asm-i386/atomic.h b/include/asm-i386/atomic.h index c68557a..7a5472d 100644 --- a/include/asm-i386/atomic.h +++ b/include/asm-i386/atomic.h @@ -254,4 +254,5 @@ __asm__ __volatile__(LOCK "orl %0,%1" \ #define smp_mb__before_atomic_inc() barrier() #define smp_mb__after_atomic_inc() barrier() +#include <asm-generic/atomic.h> #endif diff --git a/include/asm-i386/bitops.h b/include/asm-i386/bitops.h index ddf1739..65679ac 100644 --- a/include/asm-i386/bitops.h +++ b/include/asm-i386/bitops.h @@ -332,9 +332,9 @@ static inline unsigned long __ffs(unsigned long word) * Returns the bit-number of the first set bit, not the number of the byte * containing a bit. */ -static inline int find_first_bit(const unsigned long *addr, unsigned size) +static inline unsigned find_first_bit(const unsigned long *addr, unsigned size) { - int x = 0; + unsigned x = 0; while (x < size) { unsigned long val = *addr++; @@ -367,11 +367,7 @@ static inline unsigned long ffz(unsigned long word) return word; } -/* - * fls: find last bit set. - */ - -#define fls(x) generic_fls(x) +#define fls64(x) generic_fls64(x) #ifdef __KERNEL__ @@ -414,6 +410,23 @@ static inline int ffs(int x) } /** + * fls - find last bit set + * @x: the word to search + * + * This is defined the same way as ffs. + */ +static inline int fls(int x) +{ + int r; + + __asm__("bsrl %1,%0\n\t" + "jnz 1f\n\t" + "movl $-1,%0\n" + "1:" : "=r" (r) : "rm" (x)); + return r+1; +} + +/** * hweightN - returns the hamming weight of a N-bit word * @x: the word to weigh * diff --git a/include/asm-i386/bugs.h b/include/asm-i386/bugs.h index ea54540..50233e0 100644 --- a/include/asm-i386/bugs.h +++ b/include/asm-i386/bugs.h @@ -8,9 +8,6 @@ * <rreilova@ececs.uc.edu> * - Channing Corn (tests & fixes), * - Andrew D. Balsa (code cleanup). - * - * Pentium III FXSR, SSE support - * Gareth Hughes <gareth@valinux.com>, May 2000 */ /* @@ -76,25 +73,7 @@ static void __init check_fpu(void) return; } -/* Enable FXSR and company _before_ testing for FP problems. */ - /* - * Verify that the FXSAVE/FXRSTOR data will be 16-byte aligned. - */ - if (offsetof(struct task_struct, thread.i387.fxsave) & 15) { - extern void __buggy_fxsr_alignment(void); - __buggy_fxsr_alignment(); - } - if (cpu_has_fxsr) { - printk(KERN_INFO "Enabling fast FPU save and restore... "); - set_in_cr4(X86_CR4_OSFXSR); - printk("done.\n"); - } - if (cpu_has_xmm) { - printk(KERN_INFO "Enabling unmasked SIMD FPU exception support... "); - set_in_cr4(X86_CR4_OSXMMEXCPT); - printk("done.\n"); - } - +/* trap_init() enabled FXSR and company _before_ testing for FP problems here. */ /* Test for the divl bug.. */ __asm__("fninit\n\t" "fldl %1\n\t" diff --git a/include/asm-i386/cacheflush.h b/include/asm-i386/cacheflush.h index 2ea36de..7199f7b 100644 --- a/include/asm-i386/cacheflush.h +++ b/include/asm-i386/cacheflush.h @@ -31,4 +31,8 @@ int change_page_attr(struct page *page, int numpages, pgprot_t prot); void kernel_map_pages(struct page *page, int numpages, int enable); #endif +#ifdef CONFIG_DEBUG_RODATA +void mark_rodata_ro(void); +#endif + #endif /* _I386_CACHEFLUSH_H */ diff --git a/include/asm-i386/desc.h b/include/asm-i386/desc.h index 29b851a..494e73b 100644 --- a/include/asm-i386/desc.h +++ b/include/asm-i386/desc.h @@ -15,9 +15,6 @@ #include <asm/mmu.h> extern struct desc_struct cpu_gdt_table[GDT_ENTRIES]; -DECLARE_PER_CPU(struct desc_struct, cpu_gdt_table[GDT_ENTRIES]); - -#define get_cpu_gdt_table(_cpu) (per_cpu(cpu_gdt_table,_cpu)) DECLARE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]); @@ -29,6 +26,11 @@ struct Xgt_desc_struct { extern struct Xgt_desc_struct idt_descr, cpu_gdt_descr[NR_CPUS]; +static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu) +{ + return ((struct desc_struct *)cpu_gdt_descr[cpu].address); +} + #define load_TR_desc() __asm__ __volatile__("ltr %w0"::"q" (GDT_ENTRY_TSS*8)) #define load_LDT_desc() __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) diff --git a/include/asm-i386/mach-bigsmp/mach_apic.h b/include/asm-i386/mach-bigsmp/mach_apic.h index ba936d4..18b19a7 100644 --- a/include/asm-i386/mach-bigsmp/mach_apic.h +++ b/include/asm-i386/mach-bigsmp/mach_apic.h @@ -1,17 +1,10 @@ #ifndef __ASM_MACH_APIC_H #define __ASM_MACH_APIC_H -#include <asm/smp.h> - -#define SEQUENTIAL_APICID -#ifdef SEQUENTIAL_APICID -#define xapic_phys_to_log_apicid(phys_apic) ( (1ul << ((phys_apic) & 0x3)) |\ - ((phys_apic<<2) & (~0xf)) ) -#elif CLUSTERED_APICID -#define xapic_phys_to_log_apicid(phys_apic) ( (1ul << ((phys_apic) & 0x3)) |\ - ((phys_apic) & (~0xf)) ) -#endif - -#define NO_BALANCE_IRQ (1) + + +extern u8 bios_cpu_apicid[]; + +#define xapic_phys_to_log_apicid(cpu) (bios_cpu_apicid[cpu]) #define esr_disable (1) static inline int apic_id_registered(void) @@ -19,7 +12,6 @@ static inline int apic_id_registered(void) return (1); } -#define APIC_DFR_VALUE (APIC_DFR_CLUSTER) /* Round robin the irqs amoung the online cpus */ static inline cpumask_t target_cpus(void) { @@ -32,29 +24,34 @@ static inline cpumask_t target_cpus(void) } while (cpu >= NR_CPUS); return cpumask_of_cpu(cpu); } -#define TARGET_CPUS (target_cpus()) -#define INT_DELIVERY_MODE dest_Fixed -#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ +#undef APIC_DEST_LOGICAL +#define APIC_DEST_LOGICAL 0 +#define TARGET_CPUS (target_cpus()) +#define APIC_DFR_VALUE (APIC_DFR_FLAT) +#define INT_DELIVERY_MODE (dest_Fixed) +#define INT_DEST_MODE (0) /* phys delivery to target proc */ +#define NO_BALANCE_IRQ (0) +#define WAKE_SECONDARY_VIA_INIT + static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) { - return 0; + return (0); } -/* we don't use the phys_cpu_present_map to indicate apicid presence */ -static inline unsigned long check_apicid_present(int bit) +static inline unsigned long check_apicid_present(int bit) { - return 1; + return (1); } -#define apicid_cluster(apicid) (apicid & 0xF0) - -static inline unsigned long calculate_ldr(unsigned long old) +static inline unsigned long calculate_ldr(int cpu) { - unsigned long id; - id = xapic_phys_to_log_apicid(hard_smp_processor_id()); - return ((old & ~APIC_LDR_MASK) | SET_APIC_LOGICAL_ID(id)); + unsigned long val, id; + val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; + id = xapic_phys_to_log_apicid(cpu); + val |= SET_APIC_LOGICAL_ID(id); + return val; } /* @@ -67,37 +64,35 @@ static inline unsigned long calculate_ldr(unsigned long old) static inline void init_apic_ldr(void) { unsigned long val; + int cpu = smp_processor_id(); apic_write_around(APIC_DFR, APIC_DFR_VALUE); - val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; - val = calculate_ldr(val); + val = calculate_ldr(cpu); apic_write_around(APIC_LDR, val); } static inline void clustered_apic_check(void) { printk("Enabling APIC mode: %s. Using %d I/O APICs\n", - "Cluster", nr_ioapics); + "Physflat", nr_ioapics); } static inline int multi_timer_check(int apic, int irq) { - return 0; + return (0); } static inline int apicid_to_node(int logical_apicid) { - return 0; + return (0); } -extern u8 bios_cpu_apicid[]; - static inline int cpu_present_to_apicid(int mps_cpu) { if (mps_cpu < NR_CPUS) - return (int)bios_cpu_apicid[mps_cpu]; - else - return BAD_APICID; + return (int) bios_cpu_apicid[mps_cpu]; + + return BAD_APICID; } static inline physid_mask_t apicid_to_cpu_present(int phys_apicid) @@ -109,10 +104,10 @@ extern u8 cpu_2_logical_apicid[]; /* Mapping from cpu number to logical apicid */ static inline int cpu_to_logical_apicid(int cpu) { - if (cpu >= NR_CPUS) - return BAD_APICID; - return (int)cpu_2_logical_apicid[cpu]; - } + if (cpu >= NR_CPUS) + return BAD_APICID; + return cpu_physical_id(cpu); +} static inline int mpc_apic_id(struct mpc_config_processor *m, struct mpc_config_translation *translation_record) @@ -128,11 +123,9 @@ static inline int mpc_apic_id(struct mpc_config_processor *m, static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map) { /* For clustered we don't have a good way to do this yet - hack */ - return physids_promote(0xFUL); + return physids_promote(0xFFL); } -#define WAKE_SECONDARY_VIA_INIT - static inline void setup_portio_remap(void) { } diff --git a/include/asm-i386/mach-bigsmp/mach_apicdef.h b/include/asm-i386/mach-bigsmp/mach_apicdef.h index 23e58b3..a58ab5a 100644 --- a/include/asm-i386/mach-bigsmp/mach_apicdef.h +++ b/include/asm-i386/mach-bigsmp/mach_apicdef.h @@ -1,11 +1,11 @@ #ifndef __ASM_MACH_APICDEF_H #define __ASM_MACH_APICDEF_H -#define APIC_ID_MASK (0x0F<<24) +#define APIC_ID_MASK (0xFF<<24) static inline unsigned get_apic_id(unsigned long x) { - return (((x)>>24)&0x0F); + return (((x)>>24)&0xFF); } #define GET_APIC_ID(x) get_apic_id(x) diff --git a/include/asm-i386/mman.h b/include/asm-i386/mman.h index 196619a..ba4941e 100644 --- a/include/asm-i386/mman.h +++ b/include/asm-i386/mman.h @@ -35,6 +35,7 @@ #define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */ #define MADV_WILLNEED 0x3 /* pre-fault pages */ #define MADV_DONTNEED 0x4 /* discard these pages */ +#define MADV_REMOVE 0x5 /* remove these pages & resources */ /* compatibility flags */ #define MAP_ANON MAP_ANONYMOUS diff --git a/include/asm-i386/mmzone.h b/include/asm-i386/mmzone.h index 620a906..74f595d 100644 --- a/include/asm-i386/mmzone.h +++ b/include/asm-i386/mmzone.h @@ -76,11 +76,6 @@ static inline int pfn_to_nid(unsigned long pfn) * Following are macros that each numa implmentation must define. */ -/* - * Given a kernel address, find the home node of the underlying memory. - */ -#define kvaddr_to_nid(kaddr) pfn_to_nid(__pa(kaddr) >> PAGE_SHIFT) - #define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn) #define node_end_pfn(nid) \ ({ \ diff --git a/include/asm-i386/module.h b/include/asm-i386/module.h index eb7f2b4..424661d 100644 --- a/include/asm-i386/module.h +++ b/include/asm-i386/module.h @@ -52,8 +52,10 @@ struct mod_arch_specific #define MODULE_PROC_FAMILY "CYRIXIII " #elif defined CONFIG_MVIAC3_2 #define MODULE_PROC_FAMILY "VIAC3-2 " -#elif CONFIG_MGEODEGX1 +#elif defined CONFIG_MGEODEGX1 #define MODULE_PROC_FAMILY "GEODEGX1 " +#elif defined CONFIG_MGEODE_LX +#define MODULE_PROC_FAMILY "GEODE " #else #error unknown processor family #endif diff --git a/include/asm-i386/mpspec_def.h b/include/asm-i386/mpspec_def.h index a961093..76feedf 100644 --- a/include/asm-i386/mpspec_def.h +++ b/include/asm-i386/mpspec_def.h @@ -75,7 +75,7 @@ struct mpc_config_bus { unsigned char mpc_type; unsigned char mpc_busid; - unsigned char mpc_bustype[6] __attribute((packed)); + unsigned char mpc_bustype[6]; }; /* List of Bus Type string values, Intel MP Spec. */ diff --git a/include/asm-i386/segment.h b/include/asm-i386/segment.h index bb5ff5b..faf9953 100644 --- a/include/asm-i386/segment.h +++ b/include/asm-i386/segment.h @@ -91,6 +91,20 @@ #define GDT_ENTRY_BOOT_DS (GDT_ENTRY_BOOT_CS + 1) #define __BOOT_DS (GDT_ENTRY_BOOT_DS * 8) +/* The PnP BIOS entries in the GDT */ +#define GDT_ENTRY_PNPBIOS_CS32 (GDT_ENTRY_PNPBIOS_BASE + 0) +#define GDT_ENTRY_PNPBIOS_CS16 (GDT_ENTRY_PNPBIOS_BASE + 1) +#define GDT_ENTRY_PNPBIOS_DS (GDT_ENTRY_PNPBIOS_BASE + 2) +#define GDT_ENTRY_PNPBIOS_TS1 (GDT_ENTRY_PNPBIOS_BASE + 3) +#define GDT_ENTRY_PNPBIOS_TS2 (GDT_ENTRY_PNPBIOS_BASE + 4) + +/* The PnP BIOS selectors */ +#define PNP_CS32 (GDT_ENTRY_PNPBIOS_CS32 * 8) /* segment for calling fn */ +#define PNP_CS16 (GDT_ENTRY_PNPBIOS_CS16 * 8) /* code segment for BIOS */ +#define PNP_DS (GDT_ENTRY_PNPBIOS_DS * 8) /* data segment for BIOS */ +#define PNP_TS1 (GDT_ENTRY_PNPBIOS_TS1 * 8) /* transfer data segment */ +#define PNP_TS2 (GDT_ENTRY_PNPBIOS_TS2 * 8) /* another data segment */ + /* * The interrupt descriptor table has room for 256 idt's, * the global descriptor table is dependent on the number diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h index 772f85d..9c0593b 100644 --- a/include/asm-i386/system.h +++ b/include/asm-i386/system.h @@ -54,23 +54,7 @@ __asm__ __volatile__ ("movw %%dx,%1\n\t" \ ); } while(0) #define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) ) -#define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1)>>12 ) - -static inline unsigned long _get_base(char * addr) -{ - unsigned long __base; - __asm__("movb %3,%%dh\n\t" - "movb %2,%%dl\n\t" - "shll $16,%%edx\n\t" - "movw %1,%%dx" - :"=&d" (__base) - :"m" (*((addr)+2)), - "m" (*((addr)+4)), - "m" (*((addr)+7))); - return __base; -} - -#define get_base(ldt) _get_base( ((char *)&(ldt)) ) +#define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1) ) /* * Load a segment. Fall back on loading the zero @@ -140,6 +124,19 @@ static inline unsigned long _get_base(char * addr) :"=r" (__dummy)); \ __dummy; \ }) + +#define read_cr4_safe() ({ \ + unsigned int __dummy; \ + /* This could fault if %cr4 does not exist */ \ + __asm__("1: movl %%cr4, %0 \n" \ + "2: \n" \ + ".section __ex_table,\"a\" \n" \ + ".long 1b,2b \n" \ + ".previous \n" \ + : "=r" (__dummy): "0" (0)); \ + __dummy; \ +}) + #define write_cr4(x) \ __asm__ __volatile__("movl %0,%%cr4": :"r" (x)); #define stts() write_cr0(8 | read_cr0()) diff --git a/include/asm-i386/unistd.h b/include/asm-i386/unistd.h index 0f92e78..fe38b9a 100644 --- a/include/asm-i386/unistd.h +++ b/include/asm-i386/unistd.h @@ -256,7 +256,7 @@ #define __NR_io_submit 248 #define __NR_io_cancel 249 #define __NR_fadvise64 250 -#define __NR_set_zone_reclaim 251 +/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */ #define __NR_exit_group 252 #define __NR_lookup_dcookie 253 #define __NR_epoll_create 254 |
