diff options
Diffstat (limited to 'include/asm-arm/arch-sa1100')
30 files changed, 0 insertions, 5237 deletions
diff --git a/include/asm-arm/arch-sa1100/SA-1100.h b/include/asm-arm/arch-sa1100/SA-1100.h deleted file mode 100644 index 62aaf04..0000000 --- a/include/asm-arm/arch-sa1100/SA-1100.h +++ /dev/null @@ -1,2072 +0,0 @@ -/* - * FILE SA-1100.h - * - * Version 1.2 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date January 1998 (April 1997) - * System StrongARM SA-1100 - * Language C or ARM Assembly - * Purpose Definition of constants related to the StrongARM - * SA-1100 microprocessor (Advanced RISC Machine (ARM) - * architecture version 4). This file is based on the - * StrongARM SA-1100 data sheet version 2.2. - * - */ - - -/* Be sure that virtual mapping is defined right */ -#ifndef __ASM_ARCH_HARDWARE_H -#error You must include hardware.h not SA-1100.h -#endif - -#include "bitfield.h" - -/* - * SA1100 CS line to physical address - */ - -#define SA1100_CS0_PHYS 0x00000000 -#define SA1100_CS1_PHYS 0x08000000 -#define SA1100_CS2_PHYS 0x10000000 -#define SA1100_CS3_PHYS 0x18000000 -#define SA1100_CS4_PHYS 0x40000000 -#define SA1100_CS5_PHYS 0x48000000 - -/* - * Personal Computer Memory Card International Association (PCMCIA) sockets - */ - -#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ -#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ -#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ -#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ -#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ - -#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ -#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ -#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ -#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ - -#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ -#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ -#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ -#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ - -#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ - (0x20000000 + (Nb)*PCMCIASp) -#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ -#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ - (_PCMCIA (Nb) + 2*PCMCIAPrtSp) -#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ - (_PCMCIA (Nb) + 3*PCMCIAPrtSp) - -#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ -#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ -#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ -#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ - -#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ -#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ -#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ -#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ - - -/* - * Universal Serial Bus (USB) Device Controller (UDC) control registers - * - * Registers - * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control Register (read/write). - * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Address Register (read/write). - * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Output Maximum Packet size register - * (read/write). - * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Input Maximum Packet size register - * (read/write). - * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 0 - * (read/write). - * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 1 - * (output, read/write). - * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 2 - * (input, read/write). - * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Data register end-point 0 - * (read/write). - * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Write Count register end-point 0 - * (read). - * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Data Register (read/write). - * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Status Register (read/write). - */ - -#define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */ -#define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */ -#define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */ -#define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */ -#define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */ -#define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */ -#define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */ -#define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */ -#define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */ -#define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */ -#define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */ - -#define UDCCR_UDD 0x00000001 /* UDC Disable */ -#define UDCCR_UDA 0x00000002 /* UDC Active (read) */ -#define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ -#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ - /* (disable) */ -#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ - /* (disable) */ -#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ - /* (disable) */ -#define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ - /* (disable) */ -#define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ -#define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ - -#define UDCAR_ADD Fld (7, 0) /* function ADDress */ - -#define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ - /* [byte] */ -#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ - /* [1..256 byte] */ \ - (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) - -#define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ - /* [byte] */ -#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ - /* [1..256 byte] */ \ - (((Size) - 1) << FShft (UDCIMP_INMAXP)) - -#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ -#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ -#define UDCCS0_SST 0x00000004 /* Sent STall */ -#define UDCCS0_FST 0x00000008 /* Force STall */ -#define UDCCS0_DE 0x00000010 /* Data End */ -#define UDCCS0_SE 0x00000020 /* Setup End (read) */ -#define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ - /* (write) */ -#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ - -#define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ - /* Service request (read) */ -#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ -#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ -#define UDCCS1_SST 0x00000008 /* Sent STall */ -#define UDCCS1_FST 0x00000010 /* Force STall */ -#define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ - -#define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ - /* Service request (read) */ -#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ -#define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ -#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ -#define UDCCS2_SST 0x00000010 /* Sent STall */ -#define UDCCS2_FST 0x00000020 /* Force STall */ - -#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ - -#define UDCWC_WC Fld (4, 0) /* Write Count */ - -#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ - -#define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ -#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ -#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ -#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ -#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ -#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ - - -/* - * Universal Asynchronous Receiver/Transmitter (UART) control registers - * - * Registers - * Ser1UTCR0 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser1UTCR1 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser1UTCR2 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser1UTCR3 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser1UTDR Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser1UTSR0 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser1UTSR1 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). - * - * Ser2UTCR0 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser2UTCR1 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser2UTCR2 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser2UTCR3 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser2UTCR4 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 4 - * (read/write). - * Ser2UTDR Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser2UTSR0 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser2UTSR1 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). - * - * Ser3UTCR0 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser3UTCR1 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser3UTCR2 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser3UTCR3 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser3UTDR Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser3UTSR0 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser3UTSR1 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). - * - * Clocks - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fua, Tua Frequency, period of the UART communication. - */ - -#define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */ -#define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */ -#define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */ -#define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */ -#define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */ -#define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */ -#define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */ -#define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */ - -#define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ -#define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ -#define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ -#define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ -#define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ -#define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ -#define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ - -#define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ -#define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ -#define Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ -#define Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ -#define Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ -#define Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ -#define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ -#define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ - -#define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ -#define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ -#define Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ -#define Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ -#define Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ -#define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ -#define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ - -/* Those are still used in some places */ -#define _Ser1UTCR0 __PREG(Ser1UTCR0) -#define _Ser2UTCR0 __PREG(Ser2UTCR0) -#define _Ser3UTCR0 __PREG(Ser3UTCR0) - -/* Register offsets */ -#define UTCR0 0x00 -#define UTCR1 0x04 -#define UTCR2 0x08 -#define UTCR3 0x0c -#define UTDR 0x14 -#define UTSR0 0x1c -#define UTSR1 0x20 - -#define UTCR0_PE 0x00000001 /* Parity Enable */ -#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ -#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ -#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ -#define UTCR0_SBS 0x00000004 /* Stop Bit Select */ -#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ -#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ -#define UTCR0_DSS 0x00000008 /* Data Size Select */ -#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ -#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ -#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ - /* (ser. port 1: GPIO [18], */ - /* ser. port 3: GPIO [20]) */ -#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ -#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ -#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ -#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ -#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ -#define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ -#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ - (UTCR0_1StpBit + UTCR0_8BitData) - -#define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ -#define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ - /* fua = fxtl/(16*(BRD[11:0] + 1)) */ - /* Tua = 16*(BRD [11:0] + 1)*Txtl */ -#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ - FShft (UTCR1_BRD)) -#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ - FShft (UTCR2_BRD)) - /* fua = fxtl/(16*Floor (Div/16)) */ - /* Tua = 16*Floor (Div/16)*Txtl */ -#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ - FShft (UTCR1_BRD)) -#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ - FShft (UTCR2_BRD)) - /* fua = fxtl/(16*Ceil (Div/16)) */ - /* Tua = 16*Ceil (Div/16)*Txtl */ - -#define UTCR3_RXE 0x00000001 /* Receive Enable */ -#define UTCR3_TXE 0x00000002 /* Transmit Enable */ -#define UTCR3_BRK 0x00000004 /* BReaK mode */ -#define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Interrupt Enable */ -#define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define UTCR3_LBM 0x00000020 /* Look-Back Mode */ -#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ - /* TIE, LBM can be set or cleared) */ \ - (UTCR3_RXE + UTCR3_TXE) - -#define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ - /* (HP-SIR) modulation Enable */ -#define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ -#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ -#define UTCR4_LPM 0x00000002 /* Low-Power Mode */ -#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ -#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ - -#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ -#define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ -#define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ -#define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ -#endif /* 0 */ - -#define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ -#define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Service request (read) */ -#define UTSR0_RID 0x00000004 /* Receiver IDle */ -#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ -#define UTSR0_REB 0x00000010 /* Receive End of Break */ -#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ - -#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ -#define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ -#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ -#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ -#define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ -#define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ - - -/* - * Synchronous Data Link Controller (SDLC) control registers - * - * Registers - * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 0 (read/write). - * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 1 (read/write). - * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 2 (read/write). - * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 3 (read/write). - * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 4 (read/write). - * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) - * Data Register (read/write). - * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) - * Status Register 0 (read/write). - * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) - * Status Register 1 (read/write). - * - * Clocks - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fsd, Tsd Frequency, period of the SDLC communication. - */ - -#define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */ -#define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */ -#define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */ -#define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */ -#define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */ -#define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */ -#define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */ -#define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */ - -#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ -#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ -#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ -#define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ -#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ -#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ -#define SDCR0_LBM 0x00000004 /* Look-Back Mode */ -#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ -#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ -#define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ -#define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ -#define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ - /* (GPIO [16]) */ -#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ -#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ -#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ -#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ -#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ -#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ -#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ -#define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ - -#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ - /* (GPIO [17]) */ -#define SDCR1_TXE 0x00000002 /* Transmit Enable */ -#define SDCR1_RXE 0x00000004 /* Receive Enable */ -#define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Interrupt Enable */ -#define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define SDCR1_AME 0x00000020 /* Address Match Enable */ -#define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ -#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ -#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ -#define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ - -#define SDCR2_AMV Fld (8, 0) /* Address Match Value */ - -#define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ -#define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ - /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ - /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ -#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ - FShft (SDCR3_BRD)) -#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ - FShft (SDCR4_BRD)) - /* fsd = fxtl/(16*Floor (Div/16)) */ - /* Tsd = 16*Floor (Div/16)*Txtl */ -#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ - FShft (SDCR3_BRD)) -#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ - FShft (SDCR4_BRD)) - /* fsd = fxtl/(16*Ceil (Div/16)) */ - /* Tsd = 16*Ceil (Div/16)*Txtl */ - -#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ -#define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ -#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ -#define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ -#endif /* 0 */ - -#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ -#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ -#define SDSR0_RAB 0x00000004 /* Receive ABort */ -#define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ -#define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Service request (read) */ - -#define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ -#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ -#define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ -#define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ -#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ -#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ -#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ -#define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ - - -/* - * High-Speed Serial to Parallel controller (HSSP) control registers - * - * Registers - * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 0 (read/write). - * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 1 (read/write). - * Ser2HSDR Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Data Register (read/write). - * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Status Register 0 (read/write). - * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Status Register 1 (read). - * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 2 (read/write). - * [The HSCR2 register is only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] - */ - -#define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */ -#define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */ -#define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */ -#define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */ -#define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */ -#define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */ - -#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ -#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ -#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ -#define HSCR0_LBM 0x00000002 /* Look-Back Mode */ -#define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ -#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ -#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ -#define HSCR0_TXE 0x00000008 /* Transmit Enable */ -#define HSCR0_RXE 0x00000010 /* Receive Enable */ -#define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ - /* more Interrupt Enable */ -#define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define HSCR0_AME 0x00000080 /* Address Match Enable */ - -#define HSCR1_AMV Fld (8, 0) /* Address Match Value */ - -#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ -#define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ -#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ -#define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ -#endif /* 0 */ - -#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ -#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ -#define HSSR0_RAB 0x00000004 /* Receive ABort */ -#define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ -#define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ - /* more Service request (read) */ -#define HSSR0_FRE 0x00000020 /* receive FRaming Error */ - -#define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ -#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ -#define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ -#define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ -#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ -#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ -#define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ - -#define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ -#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ - /* (inverted) */ -#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ - /* (non-inverted) */ -#define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ -#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ - /* (inverted) */ -#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ - /* (non-inverted) */ - - -/* - * Multi-media Communications Port (MCP) control registers - * - * Registers - * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) - * Control Register 0 (read/write). - * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 0 (audio, read/write). - * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 1 (telecom, read/write). - * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 2 (CODEC registers, read/write). - * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) - * Status Register (read/write). - * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) - * Control Register 1 (read/write). - * [The MCCR1 register is only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] - * - * Clocks - * fmc, Tmc Frequency, period of the MCP communication (10 MHz, - * 12 MHz, or GPIO [21]). - * faud, Taud Frequency, period of the audio sampling. - * ftcm, Ttcm Frequency, period of the telecom sampling. - */ - -#define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */ -#define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */ -#define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */ -#define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */ -#define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */ -#define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */ - -#define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ - /* [6..127] */ - /* faud = fmc/(32*ASD) */ - /* Taud = 32*ASD*Tmc */ -#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ - /* [192..4064] */ \ - ((Div)/32 << FShft (MCCR0_ASD)) - /* faud = fmc/(32*Floor (Div/32)) */ - /* Taud = 32*Floor (Div/32)*Tmc */ -#define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \ - (((Div) + 31)/32 << FShft (MCCR0_ASD)) - /* faud = fmc/(32*Ceil (Div/32)) */ - /* Taud = 32*Ceil (Div/32)*Tmc */ -#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ - /* Divisor/32 [16..127] */ - /* ftcm = fmc/(32*TSD) */ - /* Ttcm = 32*TSD*Tmc */ -#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ - /* [512..4064] */ \ - ((Div)/32 << FShft (MCCR0_TSD)) - /* ftcm = fmc/(32*Floor (Div/32)) */ - /* Ttcm = 32*Floor (Div/32)*Tmc */ -#define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \ - (((Div) + 31)/32 << FShft (MCCR0_TSD)) - /* ftcm = fmc/(32*Ceil (Div/32)) */ - /* Ttcm = 32*Ceil (Div/32)*Tmc */ -#define MCCR0_MCE 0x00010000 /* MCP Enable */ -#define MCCR0_ECS 0x00020000 /* External Clock Select */ -#define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ -#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ -#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ - /* sampling/storing Mode */ -#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ -#define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ -#define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ - /* or less interrupt Enable */ -#define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ - /* or more interrupt Enable */ -#define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ - /* or less interrupt Enable */ -#define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ - /* more interrupt Enable */ -#define MCCR0_LBM 0x00800000 /* Look-Back Mode */ -#define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ -#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ - (((Div) - 1) << FShft (MCCR0_ECP)) - -#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ - /* FIFOs */ - -#define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ - /* FIFOs */ - - /* receive/transmit CODEC reg. */ - /* FIFOs: */ -#define MCDR2_DATA Fld (16, 0) /* reg. DATA */ -#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ -#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ -#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ -#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ - -#define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ - /* or less Service request (read) */ -#define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ - /* more Service request (read) */ -#define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ - /* or less Service request (read) */ -#define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ - /* or more Service request (read) */ -#define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ -#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ -#define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ -#define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ -#define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ - /* (read) */ -#define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ - /* (read) */ -#define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ - /* (read) */ -#define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ - /* (read) */ -#define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ - /* (read) */ -#define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ - /* (read) */ -#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ -#define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ - -#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ -#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ - /* (11.981 MHz) */ -#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ - /* (9.585 MHz) */ - - -/* - * Synchronous Serial Port (SSP) control registers - * - * Registers - * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control - * Register 0 (read/write). - * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control - * Register 1 (read/write). - * [Bits SPO and SP are only implemented in versions 2.0 - * (rev. = 8) and higher of the StrongARM SA-1100.] - * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data - * Register (read/write). - * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status - * Register (read/write). - * - * Clocks - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fss, Tss Frequency, period of the SSP communication. - */ - -#define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */ -#define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */ -#define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */ -#define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */ - -#define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ -#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ - (((Size) - 1) << FShft (SSCR0_DSS)) -#define SSCR0_FRF Fld (2, 4) /* FRame Format */ -#define SSCR0_Motorola /* Motorola Serial Peripheral */ \ - /* Interface (SPI) format */ \ - (0 << FShft (SSCR0_FRF)) -#define SSCR0_TI /* Texas Instruments Synchronous */ \ - /* Serial format */ \ - (1 << FShft (SSCR0_FRF)) -#define SSCR0_National /* National Microwire format */ \ - (2 << FShft (SSCR0_FRF)) -#define SSCR0_SSE 0x00000080 /* SSP Enable */ -#define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ - /* fss = fxtl/(2*(SCR + 1)) */ - /* Tss = 2*(SCR + 1)*Txtl */ -#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ - (((Div) - 2)/2 << FShft (SSCR0_SCR)) - /* fss = fxtl/(2*Floor (Div/2)) */ - /* Tss = 2*Floor (Div/2)*Txtl */ -#define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ - (((Div) - 1)/2 << FShft (SSCR0_SCR)) - /* fss = fxtl/(2*Ceil (Div/2)) */ - /* Tss = 2*Ceil (Div/2)*Txtl */ - -#define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ - /* Interrupt Enable */ -#define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define SSCR1_LBM 0x00000004 /* Look-Back Mode */ -#define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ -#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ -#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ -#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ -#define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ - /* after frame (SFRM, 1st edge) */ -#define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ - /* after frame (SFRM, 1st edge) */ -#define SSCR1_ECS 0x00000020 /* External Clock Select */ -#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ -#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ - -#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ - -#define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ -#define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ -#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ -#define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ -#define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ - /* Service request (read) */ -#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ - - -/* - * Operating System (OS) timer control registers - * - * Registers - * OSMR0 Operating System (OS) timer Match Register 0 - * (read/write). - * OSMR1 Operating System (OS) timer Match Register 1 - * (read/write). - * OSMR2 Operating System (OS) timer Match Register 2 - * (read/write). - * OSMR3 Operating System (OS) timer Match Register 3 - * (read/write). - * OSCR Operating System (OS) timer Counter Register - * (read/write). - * OSSR Operating System (OS) timer Status Register - * (read/write). - * OWER Operating System (OS) timer Watch-dog Enable Register - * (read/write). - * OIER Operating System (OS) timer Interrupt Enable Register - * (read/write). - */ - -#define OSMR0 __REG(0x90000000) /* OS timer Match Reg. 0 */ -#define OSMR1 __REG(0x90000004) /* OS timer Match Reg. 1 */ -#define OSMR2 __REG(0x90000008) /* OS timer Match Reg. 2 */ -#define OSMR3 __REG(0x9000000c) /* OS timer Match Reg. 3 */ -#define OSCR __REG(0x90000010) /* OS timer Counter Reg. */ -#define OSSR __REG(0x90000014 ) /* OS timer Status Reg. */ -#define OWER __REG(0x90000018 ) /* OS timer Watch-dog Enable Reg. */ -#define OIER __REG(0x9000001C ) /* OS timer Interrupt Enable Reg. */ - -#define OSSR_M(Nb) /* Match detected [0..3] */ \ - (0x00000001 << (Nb)) -#define OSSR_M0 OSSR_M (0) /* Match detected 0 */ -#define OSSR_M1 OSSR_M (1) /* Match detected 1 */ -#define OSSR_M2 OSSR_M (2) /* Match detected 2 */ -#define OSSR_M3 OSSR_M (3) /* Match detected 3 */ - -#define OWER_WME 0x00000001 /* Watch-dog Match Enable */ - /* (set only) */ - -#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ - (0x00000001 << (Nb)) -#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ -#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ -#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ -#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ - - -/* - * Real-Time Clock (RTC) control registers - * - * Registers - * RTAR Real-Time Clock (RTC) Alarm Register (read/write). - * RCNR Real-Time Clock (RTC) CouNt Register (read/write). - * RTTR Real-Time Clock (RTC) Trim Register (read/write). - * RTSR Real-Time Clock (RTC) Status Register (read/write). - * - * Clocks - * frtx, Trtx Frequency, period of the real-time clock crystal - * (32.768 kHz nominal). - * frtc, Trtc Frequency, period of the real-time clock counter - * (1 Hz nominal). - */ - -#define RTAR __REG(0x90010000) /* RTC Alarm Reg. */ -#define RCNR __REG(0x90010004) /* RTC CouNt Reg. */ -#define RTTR __REG(0x90010008) /* RTC Trim Reg. */ -#define RTSR __REG(0x90010010) /* RTC Status Reg. */ - -#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ -#define RTTR_D Fld (10, 16) /* trim Delete count */ - /* frtc = (1023*(C + 1) - D)*frtx/ */ - /* (1023*(C + 1)^2) */ - /* Trtc = (1023*(C + 1)^2)*Trtx/ */ - /* (1023*(C + 1) - D) */ - -#define RTSR_AL 0x00000001 /* ALarm detected */ -#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ -#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ -#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ - - -/* - * Power Manager (PM) control registers - * - * Registers - * PMCR Power Manager (PM) Control Register (read/write). - * PSSR Power Manager (PM) Sleep Status Register (read/write). - * PSPR Power Manager (PM) Scratch-Pad Register (read/write). - * PWER Power Manager (PM) Wake-up Enable Register - * (read/write). - * PCFR Power Manager (PM) general ConFiguration Register - * (read/write). - * PPCR Power Manager (PM) Phase-Locked Loop (PLL) - * Configuration Register (read/write). - * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) - * Sleep state Register (read/write, see GPIO pins). - * POSR Power Manager (PM) Oscillator Status Register (read). - * - * Clocks - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - */ - -#define PMCR __REG(0x90020000) /* PM Control Reg. */ -#define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */ -#define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */ -#define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */ -#define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */ -#define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */ -#define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */ -#define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */ - -#define PMCR_SF 0x00000001 /* Sleep Force (set only) */ - -#define PSSR_SS 0x00000001 /* Software Sleep */ -#define PSSR_BFS 0x00000002 /* Battery Fault Status */ - /* (BATT_FAULT) */ -#define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ -#define PSSR_DH 0x00000008 /* DRAM control Hold */ -#define PSSR_PH 0x00000010 /* Peripheral control Hold */ - -#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ -#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ -#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ -#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ -#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ -#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ -#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ -#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ -#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ -#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ -#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ -#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ -#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ -#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ -#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ -#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ -#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ -#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ -#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ -#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ -#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ -#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ -#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ -#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ -#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ -#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ -#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ -#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ -#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ -#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ - -#define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ -#define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ -#define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ -#define PCFR_FP 0x00000002 /* Float PCMCIA pins */ -#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ -#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ -#define PCFR_FS 0x00000004 /* Float Static memory pins */ -#define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ -#define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ -#define PCFR_FO 0x00000008 /* Force RTC oscillator */ - /* (32.768 kHz) enable On */ - -#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ -#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ - (0x00 << FShft (PPCR_CCF)) -#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ - (0x01 << FShft (PPCR_CCF)) -#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ - (0x02 << FShft (PPCR_CCF)) -#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ - (0x03 << FShft (PPCR_CCF)) -#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ - (0x04 << FShft (PPCR_CCF)) -#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ - (0x05 << FShft (PPCR_CCF)) -#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ - (0x06 << FShft (PPCR_CCF)) -#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ - (0x07 << FShft (PPCR_CCF)) -#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ - (0x08 << FShft (PPCR_CCF)) -#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ - (0x09 << FShft (PPCR_CCF)) -#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ - (0x0A << FShft (PPCR_CCF)) -#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ - (0x0B << FShft (PPCR_CCF)) -#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ - (0x0C << FShft (PPCR_CCF)) -#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ - (0x0D << FShft (PPCR_CCF)) -#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ - (0x0E << FShft (PPCR_CCF)) -#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ - (0x0F << FShft (PPCR_CCF)) - /* 3.6864 MHz crystal (fxtl): */ -#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ -#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ -#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ -#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ -#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ -#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ -#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ -#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ -#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ -#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ -#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ -#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ -#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ -#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ -#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ -#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ - /* 3.5795 MHz crystal (fxtl): */ -#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ -#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ -#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ -#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ -#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ -#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ -#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ -#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ -#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ -#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ -#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ -#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ -#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ -#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ -#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ -#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ - -#define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ - - -/* - * Reset Controller (RC) control registers - * - * Registers - * RSRR Reset Controller (RC) Software Reset Register - * (read/write). - * RCSR Reset Controller (RC) Status Register (read/write). - */ - -#define RSRR __REG(0x90030000) /* RC Software Reset Reg. */ -#define RCSR __REG(0x90030004) /* RC Status Reg. */ - -#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ - -#define RCSR_HWR 0x00000001 /* HardWare Reset */ -#define RCSR_SWR 0x00000002 /* SoftWare Reset */ -#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ -#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ - - -/* - * Test unit control registers - * - * Registers - * TUCR Test Unit Control Register (read/write). - */ - -#define TUCR __REG(0x90030008) /* Test Unit Control Reg. */ - -#define TUCR_TIC 0x00000040 /* TIC mode */ -#define TUCR_TTST 0x00000080 /* Trim TeST mode */ -#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ - /* Check */ -#define TUCR_PMD 0x00000200 /* Power Management Disable */ -#define TUCR_MR 0x00000400 /* Memory Request mode */ -#define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ -#define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ - /* grant (MBGNT) on GPIO [22:21] */ -#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ -#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ -#define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ -#define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ -#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ -#define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ -#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ - (0 << FShft (TUCR_TSEL)) -#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ - (1 << FShft (TUCR_TSEL)) -#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ - (2 << FShft (TUCR_TSEL)) -#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ - (3 << FShft (TUCR_TSEL)) -#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ - /* Clocks on GPIO [26:27] */ \ - (4 << FShft (TUCR_TSEL)) -#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ - /* (Alternative) */ \ - (5 << FShft (TUCR_TSEL)) -#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ - (6 << FShft (TUCR_TSEL)) -#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ - (7 << FShft (TUCR_TSEL)) - - -/* - * General-Purpose Input/Output (GPIO) control registers - * - * Registers - * GPLR General-Purpose Input/Output (GPIO) Pin Level - * Register (read). - * GPDR General-Purpose Input/Output (GPIO) Pin Direction - * Register (read/write). - * GPSR General-Purpose Input/Output (GPIO) Pin output Set - * Register (write). - * GPCR General-Purpose Input/Output (GPIO) Pin output Clear - * Register (write). - * GRER General-Purpose Input/Output (GPIO) Rising-Edge - * detect Register (read/write). - * GFER General-Purpose Input/Output (GPIO) Falling-Edge - * detect Register (read/write). - * GEDR General-Purpose Input/Output (GPIO) Edge Detect - * status Register (read/write). - * GAFR General-Purpose Input/Output (GPIO) Alternate - * Function Register (read/write). - * - * Clock - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - */ - -#define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */ -#define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */ -#define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */ -#define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */ -#define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */ -#define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */ -#define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */ -#define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */ - -#define GPIO_MIN (0) -#define GPIO_MAX (27) - -#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ - (0x00000001 << (Nb)) -#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ -#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ -#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ -#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ -#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ -#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ -#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ -#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ -#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ -#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ -#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ -#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ -#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ -#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ -#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ -#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ -#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ -#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ -#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ -#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ -#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ -#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ -#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ -#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ -#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ -#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ -#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ -#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ - -#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ - GPIO_GPIO ((Nb) - 6) -#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ -#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ -#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ -#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ -#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ -#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ -#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ -#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ - /* ser. port 4: */ -#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ -#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ -#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ -#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ - /* ser. port 1: */ -#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ -#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ -#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ -#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ -#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ - /* ser. port 4: */ -#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ - /* ser. port 3: */ -#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ - /* ser. port 4: */ -#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ - /* test controller: */ -#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ -#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ -#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ -#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ -#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ -#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ -#define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ -#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ - -#define GPDR_In 0 /* Input */ -#define GPDR_Out 1 /* Output */ - - -/* - * Interrupt Controller (IC) control registers - * - * Registers - * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) - * Pending register (read). - * ICMR Interrupt Controller (IC) Mask Register (read/write). - * ICLR Interrupt Controller (IC) Level Register (read/write). - * ICCR Interrupt Controller (IC) Control Register - * (read/write). - * [The ICCR register is only implemented in versions 2.0 - * (rev. = 8) and higher of the StrongARM SA-1100.] - * ICFP Interrupt Controller (IC) Fast Interrupt reQuest - * (FIQ) Pending register (read). - * ICPR Interrupt Controller (IC) Pending Register (read). - * [The ICPR register is active low (inverted) in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it is active high (non-inverted) in - * versions 2.0 (rev. = 8) and higher.] - */ - -#define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */ -#define ICMR __REG(0x90050004) /* IC Mask Reg. */ -#define ICLR __REG(0x90050008) /* IC Level Reg. */ -#define ICCR __REG(0x9005000C) /* IC Control Reg. */ -#define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */ -#define ICPR __REG(0x90050020) /* IC Pending Reg. */ - -#define IC_GPIO(Nb) /* GPIO [0..10] */ \ - (0x00000001 << (Nb)) -#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ -#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ -#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ -#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ -#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ -#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ -#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ -#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ -#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ -#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ -#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ -#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ -#define IC_LCD 0x00001000 /* LCD controller */ -#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ -#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ -#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ -#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ -#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ -#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ -#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ -#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ - (0x00100000 << (Nb)) -#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ -#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ -#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ -#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ -#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ -#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ -#define IC_OST(Nb) /* OS Timer match [0..3] */ \ - (0x04000000 << (Nb)) -#define IC_OST0 IC_OST (0) /* OS Timer match 0 */ -#define IC_OST1 IC_OST (1) /* OS Timer match 1 */ -#define IC_OST2 IC_OST (2) /* OS Timer match 2 */ -#define IC_OST3 IC_OST (3) /* OS Timer match 3 */ -#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ -#define IC_RTCAlrm 0x80000000 /* RTC Alarm */ - -#define ICLR_IRQ 0 /* Interrupt ReQuest */ -#define ICLR_FIQ 1 /* Fast Interrupt reQuest */ - -#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ - /* Mask */ -#define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ - /* (ICMR ignored) */ -#define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ - /* enable (ICMR used) */ - - -/* - * Peripheral Pin Controller (PPC) control registers - * - * Registers - * PPDR Peripheral Pin Controller (PPC) Pin Direction - * Register (read/write). - * PPSR Peripheral Pin Controller (PPC) Pin State Register - * (read/write). - * PPAR Peripheral Pin Controller (PPC) Pin Assignment - * Register (read/write). - * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin - * Direction Register (read/write). - * PPFR Peripheral Pin Controller (PPC) Pin Flag Register - * (read). - */ - -#define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */ -#define PPSR __REG(0x90060004) /* PPC Pin State Reg. */ -#define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */ -#define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */ -#define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */ - -#define PPC_LDD(Nb) /* LCD Data [0..7] */ \ - (0x00000001 << (Nb)) -#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ -#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ -#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ -#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ -#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ -#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ -#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ -#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ -#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ -#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ -#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ -#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ - /* ser. port 1: */ -#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ -#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ - /* ser. port 2: */ -#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ -#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ - /* ser. port 3: */ -#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ -#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ - /* ser. port 4: */ -#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ -#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ -#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ -#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ - -#define PPDR_In 0 /* Input */ -#define PPDR_Out 1 /* Output */ - - /* ser. port 1: */ -#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ -#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ -#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ - /* ser. port 4: */ -#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ -#define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ - /* & SFRM_C */ -#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ - -#define PSDR_OutL 0 /* Output Low in sleep mode */ -#define PSDR_Flt 1 /* Floating (input) in sleep mode */ - -#define PPFR_LCD 0x00000001 /* LCD controller */ -#define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ -#define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ -#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ -#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ -#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ -#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ -#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ -#define PPFR_PerEn 0 /* Peripheral Enabled */ -#define PPFR_PPCEn 1 /* PPC Enabled */ - - -/* - * Dynamic Random-Access Memory (DRAM) control registers - * - * Registers - * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) - * CoNFiGuration register (read/write). - * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 0 - * (read/write). - * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 1 - * (read/write). - * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 2 - * (read/write). - * - * Clocks - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). - * fcas, Tcas Frequency, period of the DRAM CAS shift registers. - */ - -#define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */ -#define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */ -#define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */ -#define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */ - -/* SA1100 MDCNFG values */ -#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ - (0x00000001 << (Nb)) -#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ -#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ -#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ -#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ -#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ -#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ - (((Add) - 9) << FShft (MDCNFG_DRAC)) -#define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ - /* (fcas = fcpu/2) */ -#define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ -#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ - (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) -#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ - (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) -#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ -#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ - (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) -#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ - (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) -#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ -#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ - ((Tcpu) << FShft (MDCNFG_TDL)) -#define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ - /* [Tmem] */ -#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ - /* [0..262136 Tcpu] */ \ - ((Tcpu)/8 << FShft (MDCNFG_DRI)) - -/* SA1110 MDCNFG values */ -#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ -#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ -#define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ -#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ -#define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ - /* bank 0/1 */ -#define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ -#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ -#define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ - /* deassertion 0/1 */ -#define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ -#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ -#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ -#define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ -#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ -#define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ - /* bank 0/1 */ -#define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ -#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ -#define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ - /* deassertion 0/1 */ -#define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ - - -/* - * Static memory control registers - * - * Registers - * MSC0 Memory system: Static memory Control register 0 - * (read/write). - * MSC1 Memory system: Static memory Control register 1 - * (read/write). - * - * Clocks - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). - */ - -#define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */ -#define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */ -#define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */ - -#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ - Fld (16, ((Nb) Modulo 2)*16) -#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ -#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ -#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ -#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ - -#define MSC_RT Fld (2, 0) /* ROM/static memory Type */ -#define MSC_NonBrst /* Non-Burst static memory */ \ - (0 << FShft (MSC_RT)) -#define MSC_SRAM /* 32-bit byte-writable SRAM */ \ - (1 << FShft (MSC_RT)) -#define MSC_Brst4 /* Burst-of-4 static memory */ \ - (2 << FShft (MSC_RT)) -#define MSC_Brst8 /* Burst-of-8 static memory */ \ - (3 << FShft (MSC_RT)) -#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ -#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ -#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ -#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ - /* First access - 1(.5) [Tmem] */ -#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ - /* static memory) [3..65 Tcpu] */ \ - ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) -#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) -#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ - /* static memory) [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) -#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) -#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ - /* Next access - 1 [Tmem] */ -#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ - /* static memory) [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) -#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) -#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ - /* static memory) [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) -#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) -#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ - /* time/2 [Tmem] */ -#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ - (((Tcpu)/4) << FShft (MSC_RRR)) -#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ - ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) - - -/* - * Personal Computer Memory Card International Association (PCMCIA) control - * register - * - * Register - * MECR Memory system: Expansion memory bus (PCMCIA) - * Configuration Register (read/write). - * - * Clocks - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). - * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). - */ - - /* Memory system: */ -#define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */ - -#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ - Fld (15, (Nb)*16) -#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ -#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ - -#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ -#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) -#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) -#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ - /* [Tmem] */ -#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) -#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) -#define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ -#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) -#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) - -/* - * On SA1110 only - */ - -#define MDREFR __REG(0xA000001C) - -#define MDREFR_TRASR Fld (4, 0) -#define MDREFR_DRI Fld (12, 4) -#define MDREFR_E0PIN (1 << 16) -#define MDREFR_K0RUN (1 << 17) -#define MDREFR_K0DB2 (1 << 18) -#define MDREFR_E1PIN (1 << 20) -#define MDREFR_K1RUN (1 << 21) -#define MDREFR_K1DB2 (1 << 22) -#define MDREFR_K2RUN (1 << 25) -#define MDREFR_K2DB2 (1 << 26) -#define MDREFR_EAPD (1 << 28) -#define MDREFR_KAPD (1 << 29) -#define MDREFR_SLFRSH (1 << 31) - - -/* - * Direct Memory Access (DMA) control registers - * - * Registers - * DDAR0 Direct Memory Access (DMA) Device Address Register - * channel 0 (read/write). - * DCSR0 Direct Memory Access (DMA) Control and Status - * Register channel 0 (read/write). - * DBSA0 Direct Memory Access (DMA) Buffer Start address - * register A channel 0 (read/write). - * DBTA0 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 0 (read/write). - * DBSB0 Direct Memory Access (DMA) Buffer Start address - * register B channel 0 (read/write). - * DBTB0 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 0 (read/write). - * - * DDAR1 Direct Memory Access (DMA) Device Address Register - * channel 1 (read/write). - * DCSR1 Direct Memory Access (DMA) Control and Status - * Register channel 1 (read/write). - * DBSA1 Direct Memory Access (DMA) Buffer Start address - * register A channel 1 (read/write). - * DBTA1 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 1 (read/write). - * DBSB1 Direct Memory Access (DMA) Buffer Start address - * register B channel 1 (read/write). - * DBTB1 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 1 (read/write). - * - * DDAR2 Direct Memory Access (DMA) Device Address Register - * channel 2 (read/write). - * DCSR2 Direct Memory Access (DMA) Control and Status - * Register channel 2 (read/write). - * DBSA2 Direct Memory Access (DMA) Buffer Start address - * register A channel 2 (read/write). - * DBTA2 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 2 (read/write). - * DBSB2 Direct Memory Access (DMA) Buffer Start address - * register B channel 2 (read/write). - * DBTB2 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 2 (read/write). - * - * DDAR3 Direct Memory Access (DMA) Device Address Register - * channel 3 (read/write). - * DCSR3 Direct Memory Access (DMA) Control and Status - * Register channel 3 (read/write). - * DBSA3 Direct Memory Access (DMA) Buffer Start address - * register A channel 3 (read/write). - * DBTA3 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 3 (read/write). - * DBSB3 Direct Memory Access (DMA) Buffer Start address - * register B channel 3 (read/write). - * DBTB3 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 3 (read/write). - * - * DDAR4 Direct Memory Access (DMA) Device Address Register - * channel 4 (read/write). - * DCSR4 Direct Memory Access (DMA) Control and Status - * Register channel 4 (read/write). - * DBSA4 Direct Memory Access (DMA) Buffer Start address - * register A channel 4 (read/write). - * DBTA4 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 4 (read/write). - * DBSB4 Direct Memory Access (DMA) Buffer Start address - * register B channel 4 (read/write). - * DBTB4 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 4 (read/write). - * - * DDAR5 Direct Memory Access (DMA) Device Address Register - * channel 5 (read/write). - * DCSR5 Direct Memory Access (DMA) Control and Status - * Register channel 5 (read/write). - * DBSA5 Direct Memory Access (DMA) Buffer Start address - * register A channel 5 (read/write). - * DBTA5 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 5 (read/write). - * DBSB5 Direct Memory Access (DMA) Buffer Start address - * register B channel 5 (read/write). - * DBTB5 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 5 (read/write). - */ - -#define DMASp 0x00000020 /* DMA control reg. Space [byte] */ - -#define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */ -#define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5] (write) */ -#define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..5] (write) */ -#define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (read) */ -#define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] */ -#define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5] */ -#define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] */ -#define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5] */ - -#define DDAR_RW 0x00000001 /* device data Read/Write */ -#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ - /* (memory -> device) */ -#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ - /* (device -> memory) */ -#define DDAR_E 0x00000002 /* big/little Endian device */ -#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ -#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ -#define DDAR_BS 0x00000004 /* device Burst Size */ -#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ -#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ -#define DDAR_DW 0x00000008 /* device Data Width */ -#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ -#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ -#define DDAR_DS Fld (4, 4) /* Device Select */ -#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ - (0x0 << FShft (DDAR_DS)) -#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ - (0x1 << FShft (DDAR_DS)) -#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ - (0x2 << FShft (DDAR_DS)) -#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ - (0x3 << FShft (DDAR_DS)) -#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ - (0x4 << FShft (DDAR_DS)) -#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ - (0x5 << FShft (DDAR_DS)) -#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ - (0x6 << FShft (DDAR_DS)) -#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ - (0x7 << FShft (DDAR_DS)) -#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ - (0x8 << FShft (DDAR_DS)) -#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ - (0x9 << FShft (DDAR_DS)) -#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ - /* (audio) */ \ - (0xA << FShft (DDAR_DS)) -#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ - /* (audio) */ \ - (0xB << FShft (DDAR_DS)) -#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ - /* (telecom) */ \ - (0xC << FShft (DDAR_DS)) -#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ - /* (telecom) */ \ - (0xD << FShft (DDAR_DS)) -#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ - (0xE << FShft (DDAR_DS)) -#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ - (0xF << FShft (DDAR_DS)) -#define DDAR_DA Fld (24, 8) /* Device Address */ -#define DDAR_DevAdd(Add) /* Device Address */ \ - (((Add) & 0xF0000000) | \ - (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) -#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ - (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR))) -#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ - (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR))) -#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR))) -#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR))) -#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR))) -#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR))) -#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR))) -#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR))) -#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ - (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR))) -#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ - (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR))) -#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR))) -#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR))) -#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0))) -#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0))) -#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ - /* (telecom) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1))) -#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ - /* (telecom) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1))) -#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR))) -#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR))) - -#define DCSR_RUN 0x00000001 /* DMA RUNing */ -#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ -#define DCSR_ERROR 0x00000004 /* DMA ERROR */ -#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ -#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */ -#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ -#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */ -#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ -#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ -#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ - -#define DBT_TC Fld (13, 0) /* Transfer Count */ -#define DBTA_TCA DBT_TC /* Transfer Count buffer A */ -#define DBTB_TCB DBT_TC /* Transfer Count buffer B */ - - -/* - * Liquid Crystal Display (LCD) control registers - * - * Registers - * LCCR0 Liquid Crystal Display (LCD) Control Register 0 - * (read/write). - * [Bits LDM, BAM, and ERM are only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] - * LCSR Liquid Crystal Display (LCD) Status Register - * (read/write). - * [Bit LDD can be only read in versions 1.0 (rev. = 1) - * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be - * read and written (cleared) in versions 2.0 (rev. = 8) - * and higher.] - * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Base Address Register channel 1 (read/write). - * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Current Address Register channel 1 (read). - * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Base Address Register channel 2 (read/write). - * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Current Address Register channel 2 (read). - * LCCR1 Liquid Crystal Display (LCD) Control Register 1 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher.] - * LCCR2 Liquid Crystal Display (LCD) Control Register 2 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher.] - * LCCR3 Liquid Crystal Display (LCD) Control Register 3 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher. Bit PCP is only - * implemented in versions 2.0 (rev. = 8) and higher of - * the StrongARM SA-1100.] - * - * Clocks - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). - * fpix, Tpix Frequency, period of the pixel clock. - * fln, Tln Frequency, period of the line clock. - * fac, Tac Frequency, period of the AC bias clock. - */ - -#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ -#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ - /* [byte] */ \ - (16*LCD_PEntrySp) -#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ - /* [byte] */ \ - (256*LCD_PEntrySp) -#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ - /* dummy-Palette Space [byte] */ \ - (16*LCD_PEntrySp) - -#define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ -#define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ -#define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ -#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ -#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ -#define LCD_4Bit /* LCD 4-Bit pixel mode */ \ - (0 << FShft (LCD_PBS)) -#define LCD_8Bit /* LCD 8-Bit pixel mode */ \ - (1 << FShft (LCD_PBS)) -#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ - (2 << FShft (LCD_PBS)) - -#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ -#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ -#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ -#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ -#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ -#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ -#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ -#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ -#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ -#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ -#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ -#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ -#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ -#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ -#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ -#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ - /* (Alternative) */ - -#define LCCR0 __REG(0xB0100000) /* LCD Control Reg. 0 */ -#define LCSR __REG(0xB0100004) /* LCD Status Reg. */ -#define DBAR1 __REG(0xB0100010) /* LCD DMA Base Address Reg. channel 1 */ -#define DCAR1 __REG(0xB0100014) /* LCD DMA Current Address Reg. channel 1 */ -#define DBAR2 __REG(0xB0100018) /* LCD DMA Base Address Reg. channel 2 */ -#define DCAR2 __REG(0xB010001C) /* LCD DMA Current Address Reg. channel 2 */ -#define LCCR1 __REG(0xB0100020) /* LCD Control Reg. 1 */ -#define LCCR2 __REG(0xB0100024) /* LCD Control Reg. 2 */ -#define LCCR3 __REG(0xB0100028) /* LCD Control Reg. 3 */ - -#define LCCR0_LEN 0x00000001 /* LCD ENable */ -#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ -#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ -#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ -#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ - /* Select */ -#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ -#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ -#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ - /* interrupt Mask (disable) */ -#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ - /* interrupt Mask (disable) */ -#define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ - /* IUU, OOL, OUL, OOU, and OUU) */ - /* interrupt Mask (disable) */ -#define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ -#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ -#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ -#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ -#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ -#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ -#define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ - /* display mode) */ -#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ - /* display */ -#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ - /* display */ -#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ - /* [Tmem] */ -#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ - /* [0..510 Tcpu] */ \ - ((Tcpu)/2 << FShft (LCCR0_PDD)) - -#define LCSR_LDD 0x00000001 /* LCD Disable Done */ -#define LCSR_BAU 0x00000002 /* Base Address Update (read) */ -#define LCSR_BER 0x00000004 /* Bus ERror */ -#define LCSR_ABC 0x00000008 /* AC Bias clock Count */ -#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ - /* panel */ -#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ - /* panel */ -#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ - /* panel */ -#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ - /* panel */ -#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ - /* panel */ -#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ - /* panel */ -#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ - /* panel */ -#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ - /* panel */ - -#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ -#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ - (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) -#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ - /* pulse Width - 1 [Tpix] (L_LCLK) */ -#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ - /* pulse Width [1..64 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_HSW)) -#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ - /* count - 1 [Tpix] */ -#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_ELW)) -#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ - /* Wait count - 1 [Tpix] */ -#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_BLW)) - -#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ -#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ - (((Line) - 1) << FShft (LCCR2_LPP)) -#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ - /* Width - 1 [Tln] (L_FCLK) */ -#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ - /* Width [1..64 Tln] */ \ - (((Tln) - 1) << FShft (LCCR2_VSW)) -#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ - /* count [Tln] */ -#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_EFW)) -#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ - /* Wait count [Tln] */ -#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_BFW)) - -#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ - /* [1..255] (L_PCLK) */ - /* fpix = fcpu/(2*(PCD + 2)) */ - /* Tpix = 2*(PCD + 2)*Tcpu */ -#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ - (((Div) - 4)/2 << FShft (LCCR3_PCD)) - /* fpix = fcpu/(2*Floor (Div/2)) */ - /* Tpix = 2*Floor (Div/2)*Tcpu */ -#define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ - (((Div) - 3)/2 << FShft (LCCR3_PCD)) - /* fpix = fcpu/(2*Ceil (Div/2)) */ - /* Tpix = 2*Ceil (Div/2)*Tcpu */ -#define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ - /* [Tln] (L_BIAS) */ -#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ - (((Div) - 2)/2 << FShft (LCCR3_ACB)) - /* fac = fln/(2*Floor (Div/2)) */ - /* Tac = 2*Floor (Div/2)*Tln */ -#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ - (((Div) - 1)/2 << FShft (LCCR3_ACB)) - /* fac = fln/(2*Ceil (Div/2)) */ - /* Tac = 2*Ceil (Div/2)*Tln */ -#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ - /* Interrupt */ -#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ - /* Off */ \ - (0 << FShft (LCCR3_API)) -#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ - /* [1..15] */ \ - ((Trans) << FShft (LCCR3_API)) -#define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ - /* Polarity (L_FCLK) */ -#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ - /* active High */ -#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ - /* active Low */ -#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ - /* pulse Polarity (L_LCLK) */ -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ - /* pulse active High */ -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ - /* pulse active Low */ -#define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ -#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ -#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ -#define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ - /* active display mode) */ -#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ -#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ - -#ifndef __ASSEMBLY__ -extern unsigned int processor_id; -#endif - -#define CPU_REVISION (processor_id & 15) -#define CPU_SA1110_A0 (0) -#define CPU_SA1110_B0 (4) -#define CPU_SA1110_B1 (5) -#define CPU_SA1110_B2 (6) -#define CPU_SA1110_B4 (8) - -#define CPU_SA1100_ID (0x4401a110) -#define CPU_SA1100_MASK (0xfffffff0) -#define CPU_SA1110_ID (0x6901b110) -#define CPU_SA1110_MASK (0xfffffff0) diff --git a/include/asm-arm/arch-sa1100/SA-1101.h b/include/asm-arm/arch-sa1100/SA-1101.h deleted file mode 100644 index 65ca8c7..0000000 --- a/include/asm-arm/arch-sa1100/SA-1101.h +++ /dev/null @@ -1,925 +0,0 @@ -/* - * SA-1101.h - * - * Copyright (c) Peter Danielsson 1999 - * - * Definition of constants related to the sa1101 - * support chip for the sa1100 - * - */ - - -/* Be sure that virtual mapping is defined right */ -#ifndef __ASM_ARCH_HARDWARE_H -#error You must include hardware.h not SA-1101.h -#endif - -#ifndef SA1101_BASE -#error You must define SA-1101 physical base address -#endif - -#ifndef LANGUAGE -# ifdef __ASSEMBLY__ -# define LANGUAGE Assembly -# else -# define LANGUAGE C -# endif -#endif - -/* - * We have mapped the sa1101 depending on the value of SA1101_BASE. - * It then appears from 0xf4000000. - */ - -#define SA1101_p2v( x ) ((x) - SA1101_BASE + 0xf4000000) -#define SA1101_v2p( x ) ((x) - 0xf4000000 + SA1101_BASE) - -#ifndef SA1101_p2v -#define SA1101_p2v(PhAdd) (PhAdd) -#endif - -#include <asm/arch/bitfield.h> - -#define C 0 -#define Assembly 1 - - -/* - * Memory map - */ - -#define __SHMEM_CONTROL0 0x00000000 -#define __SYSTEM_CONTROL1 0x00000400 -#define __ARBITER 0x00020000 -#define __SYSTEM_CONTROL2 0x00040000 -#define __SYSTEM_CONTROL3 0x00060000 -#define __PARALLEL_PORT 0x00080000 -#define __VIDMEM_CONTROL 0x00100000 -#define __UPDATE_FIFO 0x00120000 -#define __SHMEM_CONTROL1 0x00140000 -#define __INTERRUPT_CONTROL 0x00160000 -#define __USB_CONTROL 0x00180000 -#define __TRACK_INTERFACE 0x001a0000 -#define __MOUSE_INTERFACE 0x001b0000 -#define __KEYPAD_INTERFACE 0x001c0000 -#define __PCMCIA_INTERFACE 0x001e0000 -#define __VGA_CONTROL 0x00200000 -#define __GPIO_INTERFACE 0x00300000 - -/* - * Macro that calculates real address for registers in the SA-1101 - */ - -#define _SA1101( x ) ((x) + SA1101_BASE) - -/* - * Interface and shared memory controller registers - * - * Registers - * SKCR SA-1101 control register (read/write) - * SMCR Shared Memory Controller Register - * SNPR Snoop Register - */ - -#define _SKCR _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */ -#define _SMCR _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */ -#define _SNPR _SA1101( 0x00140400 ) /* Snoop Reg. */ - -#if LANGUAGE == C -#define SKCR (*((volatile Word *) SA1101_p2v (_SKCR))) -#define SMCR (*((volatile Word *) SA1101_p2v (_SMCR))) -#define SNPR (*((volatile Word *) SA1101_p2v (_SNPR))) - -#define SKCR_PLLEn 0x0001 /* Enable On-Chip PLL */ -#define SKCR_BCLKEn 0x0002 /* Enables BCLK */ -#define SKCR_Sleep 0x0004 /* Sleep Mode */ -#define SKCR_IRefEn 0x0008 /* DAC Iref input enable */ -#define SKCR_VCOON 0x0010 /* VCO bias */ -#define SKCR_ScanTestEn 0x0020 /* Enables scan test */ -#define SKCR_ClockTestEn 0x0040 /* Enables clock test */ - -#define SMCR_DCAC Fld(2,0) /* Number of column address bits */ -#define SMCR_DRAC Fld(2,2) /* Number of row address bits */ -#define SMCR_ArbiterBias 0x0008 /* favor video or USB */ -#define SMCR_TopVidMem Fld(4,5) /* Top 4 bits of vidmem addr. */ - -#define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \ - (( (x) - 8 ) << FShft (SMCR_DCAC)) -#define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\ - (( (x) - 9 ) << FShft (SMCR_DRAC)) - -#define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */ -#define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */ -#define SNPR_WholeBank (1 << 23) /* Whole bank bit */ -#define SNPR_BankSelect Fld(2,27) /* Bank select */ -#define SNPR_SnoopEn (1 << 31) /* Enable snoop operation */ - -#define SNPR_Set_VFBsize( x ) /* set frame buffer size (in kb) */ \ - ( (x) << FShft (SNPR_VFBsize)) -#define SNPR_Select_Bank(x) /* select bank 0 or 1 */ \ - (( (x) + 1 ) << FShft (SNPR_BankSelect )) - -#endif /* LANGUAGE == C */ - -/* - * Video Memory Controller - * - * Registers - * VMCCR Configuration register - * VMCAR VMC address register - * VMCDR VMC data register - * - */ - -#define _VMCCR _SA1101( 0x00100000 ) /* Configuration register */ -#define _VMCAR _SA1101( 0x00101000 ) /* VMC address register */ -#define _VMCDR _SA1101( 0x00101400 ) /* VMC data register */ - -#if LANGUAGE == C -#define VMCCR (*((volatile Word *) SA1101_p2v (_VMCCR))) -#define VMCAR (*((volatile Word *) SA1101_p2v (_VMCAR))) -#define VMCDR (*((volatile Word *) SA1101_p2v (_VMCDR))) - -#define VMCCR_RefreshEn 0x0000 /* Enable memory refresh */ -#define VMCCR_Config 0x0001 /* DRAM size */ -#define VMCCR_RefPeriod Fld(2,3) /* Refresh period */ -#define VMCCR_StaleDataWait Fld(4,5) /* Stale FIFO data timeout counter */ -#define VMCCR_SleepState (1<<9) /* State of interface pins in sleep*/ -#define VMCCR_RefTest (1<<10) /* refresh test */ -#define VMCCR_RefLow Fld(6,11) /* refresh low counter */ -#define VMCCR_RefHigh Fld(7,17) /* refresh high counter */ -#define VMCCR_SDTCTest Fld(7,24) /* stale data timeout counter */ -#define VMCCR_ForceSelfRef (1<<31) /* Force self refresh */ - -#endif LANGUAGE == C - - -/* Update FIFO - * - * Registers - * UFCR Update FIFO Control Register - * UFSR Update FIFO Status Register - * UFLVLR update FIFO level register - * UFDR update FIFO data register - */ - -#define _UFCR _SA1101(0x00120000) /* Update FIFO Control Reg. */ -#define _UFSR _SA1101(0x00120400) /* Update FIFO Status Reg. */ -#define _UFLVLR _SA1101(0x00120800) /* Update FIFO level reg. */ -#define _UFDR _SA1101(0x00120c00) /* Update FIFO data reg. */ - -#if LANGUAGE == C - -#define UFCR (*((volatile Word *) SA1101_p2v (_UFCR))) -#define UFSR (*((volatile Word *) SA1101_p2v (_UFSR))) -#define UFLVLR (*((volatile Word *) SA1101_p2v (_UFLVLR))) -#define UFDR (*((volatile Word *) SA1101_p2v (_UFDR))) - - -#define UFCR_FifoThreshhold Fld(7,0) /* Level for FifoGTn flag */ - -#define UFSR_FifoGTnFlag 0x01 /* FifoGTn flag */#define UFSR_FifoEmpty 0x80 /* FIFO is empty */ - -#endif /* LANGUAGE == C */ - -/* System Controller - * - * Registers - * SKPCR Power Control Register - * SKCDR Clock Divider Register - * DACDR1 DAC1 Data register - * DACDR2 DAC2 Data register - */ - -#define _SKPCR _SA1101(0x00000400) -#define _SKCDR _SA1101(0x00040000) -#define _DACDR1 _SA1101(0x00060000) -#define _DACDR2 _SA1101(0x00060400) - -#if LANGUAGE == C -#define SKPCR (*((volatile Word *) SA1101_p2v (_SKPCR))) -#define SKCDR (*((volatile Word *) SA1101_p2v (_SKCDR))) -#define DACDR1 (*((volatile Word *) SA1101_p2v (_DACDR1))) -#define DACDR2 (*((volatile Word *) SA1101_p2v (_DACDR2))) - -#define SKPCR_UCLKEn 0x01 /* USB Enable */ -#define SKPCR_PCLKEn 0x02 /* PS/2 Enable */ -#define SKPCR_ICLKEn 0x04 /* Interrupt Controller Enable */ -#define SKPCR_VCLKEn 0x08 /* Video Controller Enable */ -#define SKPCR_PICLKEn 0x10 /* parallel port Enable */ -#define SKPCR_DCLKEn 0x20 /* DACs Enable */ -#define SKPCR_nKPADEn 0x40 /* Multiplexer */ - -#define SKCDR_PLLMul Fld(7,0) /* PLL Multiplier */ -#define SKCDR_VCLKEn Fld(2,7) /* Video controller clock divider */ -#define SKDCR_BCLKEn (1<<9) /* BCLK Divider */ -#define SKDCR_UTESTCLKEn (1<<10) /* Route USB clock during test mode */ -#define SKDCR_DivRValue Fld(6,11) /* Input clock divider for PLL */ -#define SKDCR_DivNValue Fld(5,17) /* Output clock divider for PLL */ -#define SKDCR_PLLRSH Fld(3,22) /* PLL bandwidth control */ -#define SKDCR_ChargePump (1<<25) /* Charge pump control */ -#define SKDCR_ClkTestMode (1<<26) /* Clock output test mode */ -#define SKDCR_ClkTestEn (1<<27) /* Test clock generator */ -#define SKDCR_ClkJitterCntl Fld(3,28) /* video clock jitter compensation */ - -#define DACDR_DACCount Fld(8,0) /* Count value */ -#define DACDR1_DACCount DACDR_DACCount -#define DACDR2_DACCount DACDR_DACCount - -#endif /* LANGUAGE == C */ - -/* - * Parallel Port Interface - * - * Registers - * IEEE_Config IEEE mode selection and programmable attributes - * IEEE_Control Controls the states of IEEE port control outputs - * IEEE_Data Forward transfer data register - * IEEE_Addr Forward transfer address register - * IEEE_Status Port IO signal status register - * IEEE_IntStatus Port interrupts status register - * IEEE_FifoLevels Rx and Tx FIFO interrupt generation levels - * IEEE_InitTime Forward timeout counter initial value - * IEEE_TimerStatus Forward timeout counter current value - * IEEE_FifoReset Reset forward transfer FIFO - * IEEE_ReloadValue Counter reload value - * IEEE_TestControl Control testmode - * IEEE_TestDataIn Test data register - * IEEE_TestDataInEn Enable test data - * IEEE_TestCtrlIn Test control signals - * IEEE_TestCtrlInEn Enable test control signals - * IEEE_TestDataStat Current data bus value - * - */ - -/* - * The control registers are defined as offsets from a base address - */ - -#define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT ) - -#define _IEEE_Config _IEEE( 0x0000 ) -#define _IEEE_Control _IEEE( 0x0400 ) -#define _IEEE_Data _IEEE( 0x4000 ) -#define _IEEE_Addr _IEEE( 0x0800 ) -#define _IEEE_Status _IEEE( 0x0c00 ) -#define _IEEE_IntStatus _IEEE( 0x1000 ) -#define _IEEE_FifoLevels _IEEE( 0x1400 ) -#define _IEEE_InitTime _IEEE( 0x1800 ) -#define _IEEE_TimerStatus _IEEE( 0x1c00 ) -#define _IEEE_FifoReset _IEEE( 0x2000 ) -#define _IEEE_ReloadValue _IEEE( 0x3c00 ) -#define _IEEE_TestControl _IEEE( 0x2400 ) -#define _IEEE_TestDataIn _IEEE( 0x2800 ) -#define _IEEE_TestDataInEn _IEEE( 0x2c00 ) -#define _IEEE_TestCtrlIn _IEEE( 0x3000 ) -#define _IEEE_TestCtrlInEn _IEEE( 0x3400 ) -#define _IEEE_TestDataStat _IEEE( 0x3800 ) - - -#if LANGUAGE == C -#define IEEE_Config (*((volatile Word *) SA1101_p2v (_IEEE_Config))) -#define IEEE_Control (*((volatile Word *) SA1101_p2v (_IEEE_Control))) -#define IEEE_Data (*((volatile Word *) SA1101_p2v (_IEEE_Data))) -#define IEEE_Addr (*((volatile Word *) SA1101_p2v (_IEEE_Addr))) -#define IEEE_Status (*((volatile Word *) SA1101_p2v (_IEEE_Status))) -#define IEEE_IntStatus (*((volatile Word *) SA1101_p2v (_IEEE_IntStatus))) -#define IEEE_FifoLevels (*((volatile Word *) SA1101_p2v (_IEEE_FifoLevels))) -#define IEEE_InitTime (*((volatile Word *) SA1101_p2v (_IEEE_InitTime))) -#define IEEE_TimerStatus (*((volatile Word *) SA1101_p2v (_IEEE_TimerStatus))) -#define IEEE_FifoReset (*((volatile Word *) SA1101_p2v (_IEEE_FifoReset))) -#define IEEE_ReloadValue (*((volatile Word *) SA1101_p2v (_IEEE_ReloadValue))) -#define IEEE_TestControl (*((volatile Word *) SA1101_p2v (_IEEE_TestControl))) -#define IEEE_TestDataIn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataIn))) -#define IEEE_TestDataInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataInEn))) -#define IEEE_TestCtrlIn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlIn))) -#define IEEE_TestCtrlInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlInEn))) -#define IEEE_TestDataStat (*((volatile Word *) SA1101_p2v (_IEEE_TestDataStat))) - - -#define IEEE_Config_M Fld(3,0) /* Mode select */ -#define IEEE_Config_D 0x04 /* FIFO access enable */ -#define IEEE_Config_B 0x08 /* 9-bit word enable */ -#define IEEE_Config_T 0x10 /* Data transfer enable */ -#define IEEE_Config_A 0x20 /* Data transfer direction */ -#define IEEE_Config_E 0x40 /* Timer enable */ -#define IEEE_Control_A 0x08 /* AutoFd output */ -#define IEEE_Control_E 0x04 /* Selectin output */ -#define IEEE_Control_T 0x02 /* Strobe output */ -#define IEEE_Control_I 0x01 /* Port init output */ -#define IEEE_Data_C (1<<31) /* Byte count */ -#define IEEE_Data_Db Fld(9,16) /* Data byte 2 */ -#define IEEE_Data_Da Fld(9,0) /* Data byte 1 */ -#define IEEE_Addr_A Fld(8,0) /* forward address transfer byte */ -#define IEEE_Status_A 0x0100 /* nAutoFd port output status */ -#define IEEE_Status_E 0x0080 /* nSelectIn port output status */ -#define IEEE_Status_T 0x0040 /* nStrobe port output status */ -#define IEEE_Status_I 0x0020 /* nInit port output status */ -#define IEEE_Status_B 0x0010 /* Busy port inout status */ -#define IEEE_Status_S 0x0008 /* Select port input status */ -#define IEEE_Status_K 0x0004 /* nAck port input status */ -#define IEEE_Status_F 0x0002 /* nFault port input status */ -#define IEEE_Status_R 0x0001 /* pError port input status */ - -#define IEEE_IntStatus_IntReqDat 0x0100 -#define IEEE_IntStatus_IntReqEmp 0x0080 -#define IEEE_IntStatus_IntReqInt 0x0040 -#define IEEE_IntStatus_IntReqRav 0x0020 -#define IEEE_IntStatus_IntReqTim 0x0010 -#define IEEE_IntStatus_RevAddrComp 0x0008 -#define IEEE_IntStatus_RevDataComp 0x0004 -#define IEEE_IntStatus_FwdAddrComp 0x0002 -#define IEEE_IntStatus_FwdDataComp 0x0001 -#define IEEE_FifoLevels_RevFifoLevel 2 -#define IEEE_FifoLevels_FwdFifoLevel 1 -#define IEEE_InitTime_TimValInit Fld(22,0) -#define IEEE_TimerStatus_TimValStat Fld(22,0) -#define IEEE_ReloadValue_Reload Fld(4,0) - -#define IEEE_TestControl_RegClk 0x04 -#define IEEE_TestControl_ClockSelect Fld(2,1) -#define IEEE_TestControl_TimerTestModeEn 0x01 -#define IEEE_TestCtrlIn_PError 0x10 -#define IEEE_TestCtrlIn_nFault 0x08 -#define IEEE_TestCtrlIn_nAck 0x04 -#define IEEE_TestCtrlIn_PSel 0x02 -#define IEEE_TestCtrlIn_Busy 0x01 - -#endif /* LANGUAGE == C */ - -/* - * VGA Controller - * - * Registers - * VideoControl Video Control Register - * VgaTiming0 VGA Timing Register 0 - * VgaTiming1 VGA Timing Register 1 - * VgaTiming2 VGA Timing Register 2 - * VgaTiming3 VGA Timing Register 3 - * VgaBorder VGA Border Color Register - * VgaDBAR VGADMA Base Address Register - * VgaDCAR VGADMA Channel Current Address Register - * VgaStatus VGA Status Register - * VgaInterruptMask VGA Interrupt Mask Register - * VgaPalette VGA Palette Registers - * DacControl DAC Control Register - * VgaTest VGA Controller Test Register - */ - -#define _VGA( x ) _SA1101( ( x ) + __VGA_CONTROL ) - -#define _VideoControl _VGA( 0x0000 ) -#define _VgaTiming0 _VGA( 0x0400 ) -#define _VgaTiming1 _VGA( 0x0800 ) -#define _VgaTiming2 _VGA( 0x0c00 ) -#define _VgaTiming3 _VGA( 0x1000 ) -#define _VgaBorder _VGA( 0x1400 ) -#define _VgaDBAR _VGA( 0x1800 ) -#define _VgaDCAR _VGA( 0x1c00 ) -#define _VgaStatus _VGA( 0x2000 ) -#define _VgaInterruptMask _VGA( 0x2400 ) -#define _VgaPalette _VGA( 0x40000 ) -#define _DacControl _VGA( 0x3000 ) -#define _VgaTest _VGA( 0x2c00 ) - -#if (LANGUAGE == C) -#define VideoControl (*((volatile Word *) SA1101_p2v (_VideoControl))) -#define VgaTiming0 (*((volatile Word *) SA1101_p2v (_VgaTiming0))) -#define VgaTiming1 (*((volatile Word *) SA1101_p2v (_VgaTiming1))) -#define VgaTiming2 (*((volatile Word *) SA1101_p2v (_VgaTiming2))) -#define VgaTiming3 (*((volatile Word *) SA1101_p2v (_VgaTiming3))) -#define VgaBorder (*((volatile Word *) SA1101_p2v (_VgaBorder))) -#define VgaDBAR (*((volatile Word *) SA1101_p2v (_VgaDBAR))) -#define VgaDCAR (*((volatile Word *) SA1101_p2v (_VgaDCAR))) -#define VgaStatus (*((volatile Word *) SA1101_p2v (_VgaStatus))) -#define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask))) -#define VgaPalette (*((volatile Word *) SA1101_p2v (_VgaPalette))) -#define DacControl (*((volatile Word *) SA1101_p2v (_DacControl))) -#define VgaTest (*((volatile Word *) SA1101_p2v (_VgaTest))) - -#define VideoControl_VgaEn 0x00000000 -#define VideoControl_BGR 0x00000001 -#define VideoControl_VCompVal Fld(2,2) -#define VideoControl_VgaReq Fld(4,4) -#define VideoControl_VBurstL Fld(4,8) -#define VideoControl_VMode (1<<12) -#define VideoControl_PalRead (1<<13) - -#define VgaTiming0_PPL Fld(6,2) -#define VgaTiming0_HSW Fld(8,8) -#define VgaTiming0_HFP Fld(8,16) -#define VgaTiming0_HBP Fld(8,24) - -#define VgaTiming1_LPS Fld(10,0) -#define VgaTiming1_VSW Fld(6,10) -#define VgaTiming1_VFP Fld(8,16) -#define VgaTiming1_VBP Fld(8,24) - -#define VgaTiming2_IVS 0x01 -#define VgaTiming2_IHS 0x02 -#define VgaTiming2_CVS 0x04 -#define VgaTiming2_CHS 0x08 - -#define VgaTiming3_HBS Fld(8,0) -#define VgaTiming3_HBE Fld(8,8) -#define VgaTiming3_VBS Fld(8,16) -#define VgaTiming3_VBE Fld(8,24) - -#define VgaBorder_BCOL Fld(24,0) - -#define VgaStatus_VFUF 0x01 -#define VgaStatus_VNext 0x02 -#define VgaStatus_VComp 0x04 - -#define VgaInterruptMask_VFUFMask 0x00 -#define VgaInterruptMask_VNextMask 0x01 -#define VgaInterruptMask_VCompMask 0x02 - -#define VgaPalette_R Fld(8,0) -#define VgaPalette_G Fld(8,8) -#define VgaPalette_B Fld(8,16) - -#define DacControl_DACON 0x0001 -#define DacControl_COMPON 0x0002 -#define DacControl_PEDON 0x0004 -#define DacControl_RTrim Fld(5,4) -#define DacControl_GTrim Fld(5,9) -#define DacControl_BTrim Fld(5,14) - -#define VgaTest_TDAC 0x00 -#define VgaTest_Datatest Fld(4,1) -#define VgaTest_DACTESTDAC 0x10 -#define VgaTest_DACTESTOUT Fld(3,5) - -#endif /* LANGUAGE == C */ - -/* - * USB Host Interface Controller - * - * Registers - * Revision - * Control - * CommandStatus - * InterruptStatus - * InterruptEnable - * HCCA - * PeriodCurrentED - * ControlHeadED - * BulkHeadED - * BulkCurrentED - * DoneHead - * FmInterval - * FmRemaining - * FmNumber - * PeriodicStart - * LSThreshold - * RhDescriptorA - * RhDescriptorB - * RhStatus - * RhPortStatus - * USBStatus - * USBReset - * USTAR - * USWER - * USRFR - * USNFR - * USTCSR - * USSR - * - */ - -#define _USB( x ) _SA1101( ( x ) + __USB_CONTROL ) - - -#define _Revision _USB( 0x0000 ) -#define _Control _USB( 0x0888 ) -#define _CommandStatus _USB( 0x0c00 ) -#define _InterruptStatus _USB( 0x1000 ) -#define _InterruptEnable _USB( 0x1400 ) -#define _HCCA _USB( 0x1800 ) -#define _PeriodCurrentED _USB( 0x1c00 ) -#define _ControlHeadED _USB( 0x2000 ) -#define _BulkHeadED _USB( 0x2800 ) -#define _BulkCurrentED _USB( 0x2c00 ) -#define _DoneHead _USB( 0x3000 ) -#define _FmInterval _USB( 0x3400 ) -#define _FmRemaining _USB( 0x3800 ) -#define _FmNumber _USB( 0x3c00 ) -#define _PeriodicStart _USB( 0x4000 ) -#define _LSThreshold _USB( 0x4400 ) -#define _RhDescriptorA _USB( 0x4800 ) -#define _RhDescriptorB _USB( 0x4c00 ) -#define _RhStatus _USB( 0x5000 ) -#define _RhPortStatus _USB( 0x5400 ) -#define _USBStatus _USB( 0x11800 ) -#define _USBReset _USB( 0x11c00 ) - -#define _USTAR _USB( 0x10400 ) -#define _USWER _USB( 0x10800 ) -#define _USRFR _USB( 0x10c00 ) -#define _USNFR _USB( 0x11000 ) -#define _USTCSR _USB( 0x11400 ) -#define _USSR _USB( 0x11800 ) - - -#if (LANGUAGE == C) - -#define Revision (*((volatile Word *) SA1101_p2v (_Revision))) -#define Control (*((volatile Word *) SA1101_p2v (_Control))) -#define CommandStatus (*((volatile Word *) SA1101_p2v (_CommandStatus))) -#define InterruptStatus (*((volatile Word *) SA1101_p2v (_InterruptStatus))) -#define InterruptEnable (*((volatile Word *) SA1101_p2v (_InterruptEnable))) -#define HCCA (*((volatile Word *) SA1101_p2v (_HCCA))) -#define PeriodCurrentED (*((volatile Word *) SA1101_p2v (_PeriodCurrentED))) -#define ControlHeadED (*((volatile Word *) SA1101_p2v (_ControlHeadED))) -#define BulkHeadED (*((volatile Word *) SA1101_p2v (_BulkHeadED))) -#define BulkCurrentED (*((volatile Word *) SA1101_p2v (_BulkCurrentED))) -#define DoneHead (*((volatile Word *) SA1101_p2v (_DoneHead))) -#define FmInterval (*((volatile Word *) SA1101_p2v (_FmInterval))) -#define FmRemaining (*((volatile Word *) SA1101_p2v (_FmRemaining))) -#define FmNumber (*((volatile Word *) SA1101_p2v (_FmNumber))) -#define PeriodicStart (*((volatile Word *) SA1101_p2v (_PeriodicStart))) -#define LSThreshold (*((volatile Word *) SA1101_p2v (_LSThreshold))) -#define RhDescriptorA (*((volatile Word *) SA1101_p2v (_RhDescriptorA))) -#define RhDescriptorB (*((volatile Word *) SA1101_p2v (_RhDescriptorB))) -#define RhStatus (*((volatile Word *) SA1101_p2v (_RhStatus))) -#define RhPortStatus (*((volatile Word *) SA1101_p2v (_RhPortStatus))) -#define USBStatus (*((volatile Word *) SA1101_p2v (_USBStatus))) -#define USBReset (*((volatile Word *) SA1101_p2v (_USBReset))) -#define USTAR (*((volatile Word *) SA1101_p2v (_USTAR))) -#define USWER (*((volatile Word *) SA1101_p2v (_USWER))) -#define USRFR (*((volatile Word *) SA1101_p2v (_USRFR))) -#define USNFR (*((volatile Word *) SA1101_p2v (_USNFR))) -#define USTCSR (*((volatile Word *) SA1101_p2v (_USTCSR))) -#define USSR (*((volatile Word *) SA1101_p2v (_USSR))) - - -#define USBStatus_IrqHciRmtWkp (1<<7) -#define USBStatus_IrqHciBuffAcc (1<<8) -#define USBStatus_nIrqHciM (1<<9) -#define USBStatus_nHciMFClr (1<<10) - -#define USBReset_ForceIfReset 0x01 -#define USBReset_ForceHcReset 0x02 -#define USBReset_ClkGenReset 0x04 - -#define USTCR_RdBstCntrl Fld(3,0) -#define USTCR_ByteEnable Fld(4,3) -#define USTCR_WriteEn (1<<7) -#define USTCR_FifoCir (1<<8) -#define USTCR_TestXferSel (1<<9) -#define USTCR_FifoCirAtEnd (1<<10) -#define USTCR_nSimScaleDownClk (1<<11) - -#define USSR_nAppMDEmpty 0x01 -#define USSR_nAppMDFirst 0x02 -#define USSR_nAppMDLast 0x04 -#define USSR_nAppMDFull 0x08 -#define USSR_nAppMAFull 0x10 -#define USSR_XferReq 0x20 -#define USSR_XferEnd 0x40 - -#endif /* LANGUAGE == C */ - - -/* - * Interrupt Controller - * - * Registers - * INTTEST0 Test register 0 - * INTTEST1 Test register 1 - * INTENABLE0 Interrupt Enable register 0 - * INTENABLE1 Interrupt Enable register 1 - * INTPOL0 Interrupt Polarity selection 0 - * INTPOL1 Interrupt Polarity selection 1 - * INTTSTSEL Interrupt source selection - * INTSTATCLR0 Interrupt Status 0 - * INTSTATCLR1 Interrupt Status 1 - * INTSET0 Interrupt Set 0 - * INTSET1 Interrupt Set 1 - */ - -#define _INT( x ) _SA1101( ( x ) + __INTERRUPT_CONTROL) - -#define _INTTEST0 _INT( 0x1000 ) -#define _INTTEST1 _INT( 0x1400 ) -#define _INTENABLE0 _INT( 0x2000 ) -#define _INTENABLE1 _INT( 0x2400 ) -#define _INTPOL0 _INT( 0x3000 ) -#define _INTPOL1 _INT( 0x3400 ) -#define _INTTSTSEL _INT( 0x5000 ) -#define _INTSTATCLR0 _INT( 0x6000 ) -#define _INTSTATCLR1 _INT( 0x6400 ) -#define _INTSET0 _INT( 0x7000 ) -#define _INTSET1 _INT( 0x7400 ) - -#if ( LANGUAGE == C ) -#define INTTEST0 (*((volatile Word *) SA1101_p2v (_INTTEST0))) -#define INTTEST1 (*((volatile Word *) SA1101_p2v (_INTTEST1))) -#define INTENABLE0 (*((volatile Word *) SA1101_p2v (_INTENABLE0))) -#define INTENABLE1 (*((volatile Word *) SA1101_p2v (_INTENABLE1))) -#define INTPOL0 (*((volatile Word *) SA1101_p2v (_INTPOL0))) -#define INTPOL1 (*((volatile Word *) SA1101_p2v (_INTPOL1))) -#define INTTSTSEL (*((volatile Word *) SA1101_p2v (_INTTSTSEL))) -#define INTSTATCLR0 (*((volatile Word *) SA1101_p2v (_INTSTATCLR0))) -#define INTSTATCLR1 (*((volatile Word *) SA1101_p2v (_INTSTATCLR1))) -#define INTSET0 (*((volatile Word *) SA1101_p2v (_INTSET0))) -#define INTSET1 (*((volatile Word *) SA1101_p2v (_INTSET1))) - -#endif /* LANGUAGE == C */ - -/* - * PS/2 Trackpad and Mouse Interfaces - * - * Registers (prefix kbd applies to trackpad interface, mse to mouse) - * KBDCR Control Register - * KBDSTAT Status Register - * KBDDATA Transmit/Receive Data register - * KBDCLKDIV Clock Division Register - * KBDPRECNT Clock Precount Register - * KBDTEST1 Test register 1 - * KBDTEST2 Test register 2 - * KBDTEST3 Test register 3 - * KBDTEST4 Test register 4 - * MSECR - * MSESTAT - * MSEDATA - * MSECLKDIV - * MSEPRECNT - * MSETEST1 - * MSETEST2 - * MSETEST3 - * MSETEST4 - * - */ - -#define _KBD( x ) _SA1101( ( x ) + __TRACK_INTERFACE ) -#define _MSE( x ) _SA1101( ( x ) + __MOUSE_INTERFACE ) - -#define _KBDCR _KBD( 0x0000 ) -#define _KBDSTAT _KBD( 0x0400 ) -#define _KBDDATA _KBD( 0x0800 ) -#define _KBDCLKDIV _KBD( 0x0c00 ) -#define _KBDPRECNT _KBD( 0x1000 ) -#define _KBDTEST1 _KBD( 0x2000 ) -#define _KBDTEST2 _KBD( 0x2400 ) -#define _KBDTEST3 _KBD( 0x2800 ) -#define _KBDTEST4 _KBD( 0x2c00 ) -#define _MSECR _MSE( 0x0000 ) -#define _MSESTAT _MSE( 0x0400 ) -#define _MSEDATA _MSE( 0x0800 ) -#define _MSECLKDIV _MSE( 0x0c00 ) -#define _MSEPRECNT _MSE( 0x1000 ) -#define _MSETEST1 _MSE( 0x2000 ) -#define _MSETEST2 _MSE( 0x2400 ) -#define _MSETEST3 _MSE( 0x2800 ) -#define _MSETEST4 _MSE( 0x2c00 ) - -#if ( LANGUAGE == C ) - -#define KBDCR (*((volatile Word *) SA1101_p2v (_KBDCR))) -#define KBDSTAT (*((volatile Word *) SA1101_p2v (_KBDSTAT))) -#define KBDDATA (*((volatile Word *) SA1101_p2v (_KBDDATA))) -#define KBDCLKDIV (*((volatile Word *) SA1101_p2v (_KBDCLKDIV))) -#define KBDPRECNT (*((volatile Word *) SA1101_p2v (_KBDPRECNT))) -#define KBDTEST1 (*((volatile Word *) SA1101_p2v (_KBDTEST1))) -#define KBDTEST2 (*((volatile Word *) SA1101_p2v (_KBDTEST2))) -#define KBDTEST3 (*((volatile Word *) SA1101_p2v (_KBDTEST3))) -#define KBDTEST4 (*((volatile Word *) SA1101_p2v (_KBDTEST4))) -#define MSECR (*((volatile Word *) SA1101_p2v (_MSECR))) -#define MSESTAT (*((volatile Word *) SA1101_p2v (_MSESTAT))) -#define MSEDATA (*((volatile Word *) SA1101_p2v (_MSEDATA))) -#define MSECLKDIV (*((volatile Word *) SA1101_p2v (_MSECLKDIV))) -#define MSEPRECNT (*((volatile Word *) SA1101_p2v (_MSEPRECNT))) -#define MSETEST1 (*((volatile Word *) SA1101_p2v (_MSETEST1))) -#define MSETEST2 (*((volatile Word *) SA1101_p2v (_MSETEST2))) -#define MSETEST3 (*((volatile Word *) SA1101_p2v (_MSETEST3))) -#define MSETEST4 (*((volatile Word *) SA1101_p2v (_MSETEST4))) - - -#define KBDCR_ENA 0x08 -#define KBDCR_FKD 0x02 -#define KBDCR_FKC 0x01 - -#define KBDSTAT_TXE 0x80 -#define KBDSTAT_TXB 0x40 -#define KBDSTAT_RXF 0x20 -#define KBDSTAT_RXB 0x10 -#define KBDSTAT_ENA 0x08 -#define KBDSTAT_RXP 0x04 -#define KBDSTAT_KBD 0x02 -#define KBDSTAT_KBC 0x01 - -#define KBDCLKDIV_DivVal Fld(4,0) - -#define MSECR_ENA 0x08 -#define MSECR_FKD 0x02 -#define MSECR_FKC 0x01 - -#define MSESTAT_TXE 0x80 -#define MSESTAT_TXB 0x40 -#define MSESTAT_RXF 0x20 -#define MSESTAT_RXB 0x10 -#define MSESTAT_ENA 0x08 -#define MSESTAT_RXP 0x04 -#define MSESTAT_MSD 0x02 -#define MSESTAT_MSC 0x01 - -#define MSECLKDIV_DivVal Fld(4,0) - -#define KBDTEST1_CD 0x80 -#define KBDTEST1_RC1 0x40 -#define KBDTEST1_MC 0x20 -#define KBDTEST1_C Fld(2,3) -#define KBDTEST1_T2 0x40 -#define KBDTEST1_T1 0x20 -#define KBDTEST1_T0 0x10 -#define KBDTEST2_TICBnRES 0x08 -#define KBDTEST2_RKC 0x04 -#define KBDTEST2_RKD 0x02 -#define KBDTEST2_SEL 0x01 -#define KBDTEST3_ms_16 0x80 -#define KBDTEST3_us_64 0x40 -#define KBDTEST3_us_16 0x20 -#define KBDTEST3_DIV8 0x10 -#define KBDTEST3_DIn 0x08 -#define KBDTEST3_CIn 0x04 -#define KBDTEST3_KD 0x02 -#define KBDTEST3_KC 0x01 -#define KBDTEST4_BC12 0x80 -#define KBDTEST4_BC11 0x40 -#define KBDTEST4_TRES 0x20 -#define KBDTEST4_CLKOE 0x10 -#define KBDTEST4_CRES 0x08 -#define KBDTEST4_RXB 0x04 -#define KBDTEST4_TXB 0x02 -#define KBDTEST4_SRX 0x01 - -#define MSETEST1_CD 0x80 -#define MSETEST1_RC1 0x40 -#define MSETEST1_MC 0x20 -#define MSETEST1_C Fld(2,3) -#define MSETEST1_T2 0x40 -#define MSETEST1_T1 0x20 -#define MSETEST1_T0 0x10 -#define MSETEST2_TICBnRES 0x08 -#define MSETEST2_RKC 0x04 -#define MSETEST2_RKD 0x02 -#define MSETEST2_SEL 0x01 -#define MSETEST3_ms_16 0x80 -#define MSETEST3_us_64 0x40 -#define MSETEST3_us_16 0x20 -#define MSETEST3_DIV8 0x10 -#define MSETEST3_DIn 0x08 -#define MSETEST3_CIn 0x04 -#define MSETEST3_KD 0x02 -#define MSETEST3_KC 0x01 -#define MSETEST4_BC12 0x80 -#define MSETEST4_BC11 0x40 -#define MSETEST4_TRES 0x20 -#define MSETEST4_CLKOE 0x10 -#define MSETEST4_CRES 0x08 -#define MSETEST4_RXB 0x04 -#define MSETEST4_TXB 0x02 -#define MSETEST4_SRX 0x01 - -#endif /* LANGUAGE == C */ - - -/* - * General-Purpose I/O Interface - * - * Registers - * PADWR Port A Data Write Register - * PBDWR Port B Data Write Register - * PADRR Port A Data Read Register - * PBDRR Port B Data Read Register - * PADDR Port A Data Direction Register - * PBDDR Port B Data Direction Register - * PASSR Port A Sleep State Register - * PBSSR Port B Sleep State Register - * - */ - -#define _PIO( x ) _SA1101( ( x ) + __GPIO_INTERFACE ) - -#define _PADWR _PIO( 0x0000 ) -#define _PBDWR _PIO( 0x0400 ) -#define _PADRR _PIO( 0x0000 ) -#define _PBDRR _PIO( 0x0400 ) -#define _PADDR _PIO( 0x0800 ) -#define _PBDDR _PIO( 0x0c00 ) -#define _PASSR _PIO( 0x1000 ) -#define _PBSSR _PIO( 0x1400 ) - - -#if ( LANGUAGE == C ) - - -#define PADWR (*((volatile Word *) SA1101_p2v (_PADWR))) -#define PBDWR (*((volatile Word *) SA1101_p2v (_PBDWR))) -#define PADRR (*((volatile Word *) SA1101_p2v (_PADRR))) -#define PBDRR (*((volatile Word *) SA1101_p2v (_PBDRR))) -#define PADDR (*((volatile Word *) SA1101_p2v (_PADDR))) -#define PBDDR (*((volatile Word *) SA1101_p2v (_PBDDR))) -#define PASSR (*((volatile Word *) SA1101_p2v (_PASSR))) -#define PBSSR (*((volatile Word *) SA1101_p2v (_PBSSR))) - -#endif - - - -/* - * Keypad Interface - * - * Registers - * PXDWR - * PXDRR - * PYDWR - * PYDRR - * - */ - -#define _KEYPAD( x ) _SA1101( ( x ) + __KEYPAD_INTERFACE ) - -#define _PXDWR _KEYPAD( 0x0000 ) -#define _PXDRR _KEYPAD( 0x0000 ) -#define _PYDWR _KEYPAD( 0x0400 ) -#define _PYDRR _KEYPAD( 0x0400 ) - -#if ( LANGUAGE == C ) - - -#define PXDWR (*((volatile Word *) SA1101_p2v (_PXDWR))) -#define PXDRR (*((volatile Word *) SA1101_p2v (_PXDRR))) -#define PYDWR (*((volatile Word *) SA1101_p2v (_PYDWR))) -#define PYDRR (*((volatile Word *) SA1101_p2v (_PYDRR))) - -#endif - - - -/* - * PCMCIA Interface - * - * Registers - * PCSR Status Register - * PCCR Control Register - * PCSSR Sleep State Register - * - */ - -#define _CARD( x ) _SA1101( ( x ) + __PCMCIA_INTERFACE ) - -#define _PCSR _CARD( 0x0000 ) -#define _PCCR _CARD( 0x0400 ) -#define _PCSSR _CARD( 0x0800 ) - -#if ( LANGUAGE == C ) -#define PCSR (*((volatile Word *) SA1101_p2v (_PCSR))) -#define PCCR (*((volatile Word *) SA1101_p2v (_PCCR))) -#define PCSSR (*((volatile Word *) SA1101_p2v (_PCSSR))) - -#define PCSR_S0_ready 0x0001 -#define PCSR_S1_ready 0x0002 -#define PCSR_S0_detected 0x0004 -#define PCSR_S1_detected 0x0008 -#define PCSR_S0_VS1 0x0010 -#define PCSR_S0_VS2 0x0020 -#define PCSR_S1_VS1 0x0040 -#define PCSR_S1_VS2 0x0080 -#define PCSR_S0_WP 0x0100 -#define PCSR_S1_WP 0x0200 -#define PCSR_S0_BVD1_nSTSCHG 0x0400 -#define PCSR_S0_BVD2_nSPKR 0x0800 -#define PCSR_S1_BVD1_nSTSCHG 0x1000 -#define PCSR_S1_BVD2_nSPKR 0x2000 - -#define PCCR_S0_VPP0 0x0001 -#define PCCR_S0_VPP1 0x0002 -#define PCCR_S0_VCC0 0x0004 -#define PCCR_S0_VCC1 0x0008 -#define PCCR_S1_VPP0 0x0010 -#define PCCR_S1_VPP1 0x0020 -#define PCCR_S1_VCC0 0x0040 -#define PCCR_S1_VCC1 0x0080 -#define PCCR_S0_reset 0x0100 -#define PCCR_S1_reset 0x0200 -#define PCCR_S0_float 0x0400 -#define PCCR_S1_float 0x0800 - -#define PCSSR_S0_VCC0 0x0001 -#define PCSSR_S0_VCC1 0x0002 -#define PCSSR_S0_VPP0 0x0004 -#define PCSSR_S0_VPP1 0x0008 -#define PCSSR_S0_control 0x0010 -#define PCSSR_S1_VCC0 0x0020 -#define PCSSR_S1_VCC1 0x0040 -#define PCSSR_S1_VPP0 0x0080 -#define PCSSR_S1_VPP1 0x0100 -#define PCSSR_S1_control 0x0200 - -#endif - -#undef C -#undef Assembly diff --git a/include/asm-arm/arch-sa1100/SA-1111.h b/include/asm-arm/arch-sa1100/SA-1111.h deleted file mode 100644 index c38f609..0000000 --- a/include/asm-arm/arch-sa1100/SA-1111.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Moved to new location - */ -#warning using old SA-1111.h - update to <asm/hardware/sa1111.h> -#include <asm/hardware/sa1111.h> diff --git a/include/asm-arm/arch-sa1100/assabet.h b/include/asm-arm/arch-sa1100/assabet.h deleted file mode 100644 index d6a1bb5..0000000 --- a/include/asm-arm/arch-sa1100/assabet.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/assabet.h - * - * Created 2000/06/05 by Nicolas Pitre <nico@cam.org> - * - * This file contains the hardware specific definitions for Assabet - * Only include this file from SA1100-specific files. - * - * 2000/05/23 John Dorsey <john+@cs.cmu.edu> - * Definitions for Neponset added. - */ -#ifndef __ASM_ARCH_ASSABET_H -#define __ASM_ARCH_ASSABET_H - - -/* System Configuration Register flags */ - -#define ASSABET_SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */ -#define ASSABET_SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */ -#define ASSABET_SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */ -#define ASSABET_SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */ -#define ASSABET_SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */ -#define ASSABET_SCR_SA1111 (1<<9) /* Neponset (0 = present) */ - -#define ASSABET_SCR_INIT -1 - -extern unsigned long SCR_value; - -#ifdef CONFIG_ASSABET_NEPONSET -#define machine_has_neponset() ((SCR_value & ASSABET_SCR_SA1111) == 0) -#else -#define machine_has_neponset() (0) -#endif - -/* Board Control Register */ - -#define ASSABET_BCR_BASE 0xf1000000 -#define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE)) - -#define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */ -#define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */ -#define ASSABET_BCR_GFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */ -#define ASSABET_BCR_CODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */ -#define ASSABET_BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */ -#define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */ -#define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */ -#define ASSABET_BCR_STEREO_LB (1<<6) /* Stereo Loopback */ -#define ASSABET_BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */ -#define ASSABET_BCR_AUDIO_ON (1<<8) /* Audio power on */ -#define ASSABET_BCR_LIGHT_ON (1<<9) /* Backlight */ -#define ASSABET_BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */ -#define ASSABET_BCR_LCD_ON (1<<11) /* LCD power on */ -#define ASSABET_BCR_RS232EN (1<<12) /* RS232 transceiver enable */ -#define ASSABET_BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */ -#define ASSABET_BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */ -#define ASSABET_BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */ -#define ASSABET_BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */ -#define ASSABET_BCR_COM_RTS (1<<17) /* COMport Request To Send */ -#define ASSABET_BCR_RAD_WU (1<<18) /* Radio wake up interrupt */ -#define ASSABET_BCR_SMB_EN (1<<19) /* System management bus enable */ -#define ASSABET_BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable (not implemented) */ -#define ASSABET_BCR_QMUTE (1<<21) /* Quick Mute */ -#define ASSABET_BCR_RAD_ON (1<<22) /* Radio Power On */ -#define ASSABET_BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */ - -#ifdef CONFIG_SA1100_ASSABET -extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set); -#else -#define ASSABET_BCR_frob(x,y) do { } while (0) -#endif - -#define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x)) -#define ASSABET_BCR_clear(x) ASSABET_BCR_frob((x), 0) - -#define ASSABET_BSR_BASE 0xf1000000 -#define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE)) - -#define ASSABET_BSR_RS232_VALID (1 << 24) -#define ASSABET_BSR_COM_DCD (1 << 25) -#define ASSABET_BSR_COM_CTS (1 << 26) -#define ASSABET_BSR_COM_DSR (1 << 27) -#define ASSABET_BSR_RAD_CTS (1 << 28) -#define ASSABET_BSR_RAD_DSR (1 << 29) -#define ASSABET_BSR_RAD_DCD (1 << 30) -#define ASSABET_BSR_RAD_RI (1 << 31) - - -/* GPIOs for which the generic definition doesn't say much */ -#define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */ -#define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */ -#define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */ -#define ASSABET_GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */ -#define ASSABET_GPIO_CF_CD GPIO_GPIO (22) /* CF CD */ -#define ASSABET_GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */ -#define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */ -#define ASSABET_GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */ -#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */ -#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */ - -#define ASSABET_IRQ_GPIO_CF_IRQ IRQ_GPIO21 -#define ASSABET_IRQ_GPIO_CF_CD IRQ_GPIO22 -#define ASSABET_IRQ_GPIO_CF_BVD2 IRQ_GPIO24 -#define ASSABET_IRQ_GPIO_CF_BVD1 IRQ_GPIO25 - -#endif diff --git a/include/asm-arm/arch-sa1100/badge4.h b/include/asm-arm/arch-sa1100/badge4.h deleted file mode 100644 index 8d7a671..0000000 --- a/include/asm-arm/arch-sa1100/badge4.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/badge4.h - * - * Tim Connors <connors@hpl.hp.com> - * Christopher Hoover <ch@hpl.hp.com> - * - * Copyright (C) 2002 Hewlett-Packard Company - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#error "include <asm/hardware.h> instead" -#endif - -#define BADGE4_SA1111_BASE (0x48000000) - -/* GPIOs on the BadgePAD 4 */ -#define BADGE4_GPIO_INT_1111 GPIO_GPIO0 /* SA-1111 IRQ */ - -#define BADGE4_GPIO_INT_VID GPIO_GPIO1 /* Video expansion */ -#define BADGE4_GPIO_LGP2 GPIO_GPIO2 /* GPIO_LDD8 */ -#define BADGE4_GPIO_LGP3 GPIO_GPIO3 /* GPIO_LDD9 */ -#define BADGE4_GPIO_LGP4 GPIO_GPIO4 /* GPIO_LDD10 */ -#define BADGE4_GPIO_LGP5 GPIO_GPIO5 /* GPIO_LDD11 */ -#define BADGE4_GPIO_LGP6 GPIO_GPIO6 /* GPIO_LDD12 */ -#define BADGE4_GPIO_LGP7 GPIO_GPIO7 /* GPIO_LDD13 */ -#define BADGE4_GPIO_LGP8 GPIO_GPIO8 /* GPIO_LDD14 */ -#define BADGE4_GPIO_LGP9 GPIO_GPIO9 /* GPIO_LDD15 */ -#define BADGE4_GPIO_GPA_VID GPIO_GPIO10 /* Video expansion */ -#define BADGE4_GPIO_GPB_VID GPIO_GPIO11 /* Video expansion */ -#define BADGE4_GPIO_GPC_VID GPIO_GPIO12 /* Video expansion */ - -#define BADGE4_GPIO_UART_HS1 GPIO_GPIO13 -#define BADGE4_GPIO_UART_HS2 GPIO_GPIO14 - -#define BADGE4_GPIO_MUXSEL0 GPIO_GPIO15 -#define BADGE4_GPIO_TESTPT_J7 GPIO_GPIO16 - -#define BADGE4_GPIO_SDSDA GPIO_GPIO17 /* SDRAM SPD Data */ -#define BADGE4_GPIO_SDSCL GPIO_GPIO18 /* SDRAM SPD Clock */ -#define BADGE4_GPIO_SDTYP0 GPIO_GPIO19 /* SDRAM Type Control */ -#define BADGE4_GPIO_SDTYP1 GPIO_GPIO20 /* SDRAM Type Control */ - -#define BADGE4_GPIO_BGNT_1111 GPIO_GPIO21 /* GPIO_MBGNT */ -#define BADGE4_GPIO_BREQ_1111 GPIO_GPIO22 /* GPIO_TREQA */ - -#define BADGE4_GPIO_TESTPT_J6 GPIO_GPIO23 - -#define BADGE4_GPIO_PCMEN5V GPIO_GPIO24 /* 5V power */ - -#define BADGE4_GPIO_SA1111_NRST GPIO_GPIO25 /* SA-1111 nRESET */ - -#define BADGE4_GPIO_TESTPT_J5 GPIO_GPIO26 - -#define BADGE4_GPIO_CLK_1111 GPIO_GPIO27 /* GPIO_32_768kHz */ - -/* Interrupts on the BadgePAD 4 */ -#define BADGE4_IRQ_GPIO_SA1111 IRQ_GPIO0 /* SA-1111 interrupt */ - - -/* PCM5ENV Usage tracking */ - -#define BADGE4_5V_PCMCIA_SOCK0 (1<<0) -#define BADGE4_5V_PCMCIA_SOCK1 (1<<1) -#define BADGE4_5V_PCMCIA_SOCK(n) (1<<(n)) -#define BADGE4_5V_USB (1<<2) -#define BADGE4_5V_INITIALLY (1<<3) - -#ifndef __ASSEMBLY__ -extern void badge4_set_5V(unsigned subsystem, int on); -#endif diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/include/asm-arm/arch-sa1100/bitfield.h deleted file mode 100644 index f1f0e33..0000000 --- a/include/asm-arm/arch-sa1100/bitfield.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * FILE bitfield.h - * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) - * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. - */ - - - -#ifndef __BITFIELD_H -#define __BITFIELD_H - -#ifndef __ASSEMBLY__ -#define UData(Data) ((unsigned long) (Data)) -#else -#define UData(Data) (Data) -#endif - - -/* - * MACRO: Fld - * - * Purpose - * The macro "Fld" encodes a bit field, given its size and its shift value - * with respect to bit 0. - * - * Note - * A more intuitive way to encode bit fields would have been to use their - * mask. However, extracting size and shift value information from a bit - * field's mask is cumbersome and might break the assembler (255-character - * line-size limit). - * - * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. - * - * Output - * Fld Encoded bit field. - */ - -#define Fld(Size, Shft) (((Size) << 16) + (Shft)) - - -/* - * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit - * - * Purpose - * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return - * the size, shift value, mask, aligned mask, and first bit of a - * bit field. - * - * Input - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. - */ - -#define FSize(Field) ((Field) >> 16) -#define FShft(Field) ((Field) & 0x0000FFFF) -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) -#define F1stBit(Field) (UData (1) << FShft (Field)) - - -/* - * MACRO: FInsrt - * - * Purpose - * The macro "FInsrt" inserts a value into a bit field by shifting the - * former appropriately. - * - * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FInsrt Bit-field value positioned appropriately. - */ - -#define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) - - -/* - * MACRO: FExtr - * - * Purpose - * The macro "FExtr" extracts the value of a bit field by masking and - * shifting it appropriately. - * - * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FExtr Bit-field value. - */ - -#define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) - - -#endif /* __BITFIELD_H */ diff --git a/include/asm-arm/arch-sa1100/cerf.h b/include/asm-arm/arch-sa1100/cerf.h deleted file mode 100644 index 9a19c3d0..0000000 --- a/include/asm-arm/arch-sa1100/cerf.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * include/asm-arm/arch-sa1100/cerf.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Apr-2003 : Removed some old PDA crud [FB] - */ -#ifndef _INCLUDE_CERF_H_ -#define _INCLUDE_CERF_H_ - - -#define CERF_ETH_IO 0xf0000000 -#define CERF_ETH_IRQ IRQ_GPIO26 - -#define CERF_GPIO_CF_BVD2 GPIO_GPIO (19) -#define CERF_GPIO_CF_BVD1 GPIO_GPIO (20) -#define CERF_GPIO_CF_RESET GPIO_GPIO (21) -#define CERF_GPIO_CF_IRQ GPIO_GPIO (22) -#define CERF_GPIO_CF_CD GPIO_GPIO (23) - -#define CERF_IRQ_GPIO_CF_BVD2 IRQ_GPIO19 -#define CERF_IRQ_GPIO_CF_BVD1 IRQ_GPIO20 -#define CERF_IRQ_GPIO_CF_IRQ IRQ_GPIO22 -#define CERF_IRQ_GPIO_CF_CD IRQ_GPIO23 - -#endif // _INCLUDE_CERF_H_ diff --git a/include/asm-arm/arch-sa1100/collie.h b/include/asm-arm/arch-sa1100/collie.h deleted file mode 100644 index 762eba53..0000000 --- a/include/asm-arm/arch-sa1100/collie.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/collie.h - * - * This file contains the hardware specific definitions for Assabet - * Only include this file from SA1100-specific files. - * - * ChangeLog: - * 04-06-2001 Lineo Japan, Inc. - * 04-16-2001 SHARP Corporation - * 07-07-2002 Chris Larson <clarson@digi.com> - * - */ -#ifndef __ASM_ARCH_COLLIE_H -#define __ASM_ARCH_COLLIE_H - - -#define COLLIE_SCP_CHARGE_ON SCOOP_GPCR_PA11 -#define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12 -#define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13 -#define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14 -#define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15 -#define COLLIE_SCP_5VON SCOOP_GPCR_PA16 -#define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17 -#define COLLIE_SCP_VPEN SCOOP_GPCR_PA18 -#define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19 - -#define COLLIE_SCOOP_IO_DIR ( COLLIE_SCP_CHARGE_ON | COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \ - COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | COLLIE_SCP_VPEN | \ - COLLIE_SCP_LB_VOL_CHG ) -#define COLLIE_SCOOP_IO_OUT ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | COLLIE_SCP_VPEN | \ - COLLIE_SCP_CHARGE_ON ) - -/* GPIOs for which the generic definition doesn't say much */ - -#define COLLIE_GPIO_ON_KEY GPIO_GPIO (0) -#define COLLIE_GPIO_AC_IN GPIO_GPIO (1) -#define COLLIE_GPIO_SDIO_INT GPIO_GPIO (11) -#define COLLIE_GPIO_CF_IRQ GPIO_GPIO (14) -#define COLLIE_GPIO_nREMOCON_INT GPIO_GPIO (15) -#define COLLIE_GPIO_UCB1x00_RESET GPIO_GPIO (16) -#define COLLIE_GPIO_nMIC_ON GPIO_GPIO (17) -#define COLLIE_GPIO_nREMOCON_ON GPIO_GPIO (18) -#define COLLIE_GPIO_CO GPIO_GPIO (20) -#define COLLIE_GPIO_MCP_CLK GPIO_GPIO (21) -#define COLLIE_GPIO_CF_CD GPIO_GPIO (22) -#define COLLIE_GPIO_UCB1x00_IRQ GPIO_GPIO (23) -#define COLLIE_GPIO_WAKEUP GPIO_GPIO (24) -#define COLLIE_GPIO_GA_INT GPIO_GPIO (25) -#define COLLIE_GPIO_MAIN_BAT_LOW GPIO_GPIO (26) - -/* Interrupts */ - -#define COLLIE_IRQ_GPIO_ON_KEY IRQ_GPIO0 -#define COLLIE_IRQ_GPIO_AC_IN IRQ_GPIO1 -#define COLLIE_IRQ_GPIO_SDIO_IRQ IRQ_GPIO11 -#define COLLIE_IRQ_GPIO_CF_IRQ IRQ_GPIO14 -#define COLLIE_IRQ_GPIO_nREMOCON_INT IRQ_GPIO15 -#define COLLIE_IRQ_GPIO_CO IRQ_GPIO20 -#define COLLIE_IRQ_GPIO_CF_CD IRQ_GPIO22 -#define COLLIE_IRQ_GPIO_UCB1x00_IRQ IRQ_GPIO23 -#define COLLIE_IRQ_GPIO_WAKEUP IRQ_GPIO24 -#define COLLIE_IRQ_GPIO_GA_INT IRQ_GPIO25 -#define COLLIE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO26 - -#define COLLIE_LCM_IRQ_GPIO_RTS IRQ_LOCOMO_GPIO0 -#define COLLIE_LCM_IRQ_GPIO_CTS IRQ_LOCOMO_GPIO1 -#define COLLIE_LCM_IRQ_GPIO_DSR IRQ_LOCOMO_GPIO2 -#define COLLIE_LCM_IRQ_GPIO_DTR IRQ_LOCOMO_GPIO3 -#define COLLIE_LCM_IRQ_GPIO_nSD_DETECT IRQ_LOCOMO_GPIO13 -#define COLLIE_LCM_IRQ_GPIO_nSD_WP IRQ_LOCOMO_GPIO14 - -/* GPIO's on the TC35143AF (Toshiba Analog Frontend) */ -#define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0 /* GPIO0=Version */ -#define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1 /* GPIO1=TBL_CHK */ -#define COLLIE_TC35143_GPIO_VPEN_ON UCB_IO_2 /* GPIO2=VPNE_ON */ -#define COLLIE_TC35143_GPIO_IR_ON UCB_IO_3 /* GPIO3=IR_ON */ -#define COLLIE_TC35143_GPIO_AMP_ON UCB_IO_4 /* GPIO4=AMP_ON */ -#define COLLIE_TC35143_GPIO_VERSION1 UCB_IO_5 /* GPIO5=Version */ -#define COLLIE_TC35143_GPIO_FS8KLPF UCB_IO_5 /* GPIO5=fs 8k LPF */ -#define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6 /* GPIO6=BUZZER BIAS */ -#define COLLIE_TC35143_GPIO_MBAT_ON UCB_IO_7 /* GPIO7=MBAT_ON */ -#define COLLIE_TC35143_GPIO_BBAT_ON UCB_IO_8 /* GPIO8=BBAT_ON */ -#define COLLIE_TC35143_GPIO_TMP_ON UCB_IO_9 /* GPIO9=TMP_ON */ -#define COLLIE_TC35143_GPIO_IN ( UCB_IO_0 | UCB_IO_2 | UCB_IO_5 ) -#define COLLIE_TC35143_GPIO_OUT ( UCB_IO_1 | UCB_IO_3 | UCB_IO_4 | UCB_IO_6 | \ - UCB_IO_7 | UCB_IO_8 | UCB_IO_9 ) - -#endif diff --git a/include/asm-arm/arch-sa1100/debug-macro.S b/include/asm-arm/arch-sa1100/debug-macro.S deleted file mode 100644 index 267c317..0000000 --- a/include/asm-arm/arch-sa1100/debug-macro.S +++ /dev/null @@ -1,58 +0,0 @@ -/* linux/include/asm-arm/arch-sa1100/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ -#include <asm/hardware.h> - - .macro addruart,rx - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - moveq \rx, #0x80000000 @ physical base address - movne \rx, #0xf8000000 @ virtual address - - @ We probe for the active serial port here, coherently with - @ the comment in include/asm-arm/arch-sa1100/uncompress.h. - @ We assume r1 can be clobbered. - - @ see if Ser3 is active - add \rx, \rx, #0x00050000 - ldr r1, [\rx, #UTCR3] - tst r1, #UTCR3_TXE - - @ if Ser3 is inactive, then try Ser1 - addeq \rx, \rx, #(0x00010000 - 0x00050000) - ldreq r1, [\rx, #UTCR3] - tsteq r1, #UTCR3_TXE - - @ if Ser1 is inactive, then try Ser2 - addeq \rx, \rx, #(0x00030000 - 0x00010000) - ldreq r1, [\rx, #UTCR3] - tsteq r1, #UTCR3_TXE - - @ if all ports are inactive, then there is nothing we can do - moveq pc, lr - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #UTDR] - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #UTSR1] - tst \rd, #UTSR1_TNF - beq 1001b - .endm - - .macro busyuart,rd,rx -1001: ldr \rd, [\rx, #UTSR1] - tst \rd, #UTSR1_TBY - bne 1001b - .endm diff --git a/include/asm-arm/arch-sa1100/dma.h b/include/asm-arm/arch-sa1100/dma.h deleted file mode 100644 index 6b7917a..0000000 --- a/include/asm-arm/arch-sa1100/dma.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/dma.h - * - * Generic SA1100 DMA support - * - * Copyright (C) 2000 Nicolas Pitre - * - */ - -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H - -#include "hardware.h" - - -/* - * The SA1100 has six internal DMA channels. - */ -#define SA1100_DMA_CHANNELS 6 - -/* - * Maximum physical DMA buffer size - */ -#define MAX_DMA_SIZE 0x1fff -#define CUT_DMA_SIZE 0x1000 - -/* - * All possible SA1100 devices a DMA channel can be attached to. - */ -typedef enum { - DMA_Ser0UDCWr = DDAR_Ser0UDCWr, /* Ser. port 0 UDC Write */ - DMA_Ser0UDCRd = DDAR_Ser0UDCRd, /* Ser. port 0 UDC Read */ - DMA_Ser1UARTWr = DDAR_Ser1UARTWr, /* Ser. port 1 UART Write */ - DMA_Ser1UARTRd = DDAR_Ser1UARTRd, /* Ser. port 1 UART Read */ - DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr, /* Ser. port 1 SDLC Write */ - DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd, /* Ser. port 1 SDLC Read */ - DMA_Ser2UARTWr = DDAR_Ser2UARTWr, /* Ser. port 2 UART Write */ - DMA_Ser2UARTRd = DDAR_Ser2UARTRd, /* Ser. port 2 UART Read */ - DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr, /* Ser. port 2 HSSP Write */ - DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd, /* Ser. port 2 HSSP Read */ - DMA_Ser3UARTWr = DDAR_Ser3UARTWr, /* Ser. port 3 UART Write */ - DMA_Ser3UARTRd = DDAR_Ser3UARTRd, /* Ser. port 3 UART Read */ - DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr, /* Ser. port 4 MCP 0 Write (audio) */ - DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd, /* Ser. port 4 MCP 0 Read (audio) */ - DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr, /* Ser. port 4 MCP 1 Write */ - DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd, /* Ser. port 4 MCP 1 Read */ - DMA_Ser4SSPWr = DDAR_Ser4SSPWr, /* Ser. port 4 SSP Write (16 bits) */ - DMA_Ser4SSPRd = DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ -} dma_device_t; - -typedef struct { - volatile u_long DDAR; - volatile u_long SetDCSR; - volatile u_long ClrDCSR; - volatile u_long RdDCSR; - volatile dma_addr_t DBSA; - volatile u_long DBTA; - volatile dma_addr_t DBSB; - volatile u_long DBTB; -} dma_regs_t; - -typedef void (*dma_callback_t)(void *data); - -/* - * DMA function prototypes - */ - -extern int sa1100_request_dma( dma_device_t device, const char *device_id, - dma_callback_t callback, void *data, - dma_regs_t **regs ); -extern void sa1100_free_dma( dma_regs_t *regs ); -extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size ); -extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs); -extern void sa1100_reset_dma(dma_regs_t *regs); - -/** - * sa1100_stop_dma - stop DMA in progress - * @regs: identifier for the channel to use - * - * This stops DMA without clearing buffer pointers. Unlike - * sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma() - * or sa1100_get_dma_pos(). - * - * The @regs identifier is provided by a successful call to - * sa1100_request_dma(). - **/ - -#define sa1100_stop_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN) - -/** - * sa1100_resume_dma - resume DMA on a stopped channel - * @regs: identifier for the channel to use - * - * This resumes DMA on a channel previously stopped with - * sa1100_stop_dma(). - * - * The @regs identifier is provided by a successful call to - * sa1100_request_dma(). - **/ - -#define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN) - -/** - * sa1100_clear_dma - clear DMA pointers - * @regs: identifier for the channel to use - * - * This clear any DMA state so the DMA engine is ready to restart - * with new buffers through sa1100_start_dma(). Any buffers in flight - * are discarded. - * - * The @regs identifier is provided by a successful call to - * sa1100_request_dma(). - **/ - -#define sa1100_clear_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB) - -#endif /* _ASM_ARCH_DMA_H */ diff --git a/include/asm-arm/arch-sa1100/entry-macro.S b/include/asm-arm/arch-sa1100/entry-macro.S deleted file mode 100644 index 127db4a..0000000 --- a/include/asm-arm/arch-sa1100/entry-macro.S +++ /dev/null @@ -1,47 +0,0 @@ -/* - * include/asm-arm/arch-sa1100/entry-macro.S - * - * Low-level IRQ helper macros for SA1100-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - mov \base, #0xfa000000 @ ICIP = 0xfa050000 - add \base, \base, #0x00050000 - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, [\base] @ get irqs - ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004 - ands \irqstat, \irqstat, \irqnr - mov \irqnr, #0 - beq 1001f - tst \irqstat, #0xff - moveq \irqstat, \irqstat, lsr #8 - addeq \irqnr, \irqnr, #8 - tsteq \irqstat, #0xff - moveq \irqstat, \irqstat, lsr #8 - addeq \irqnr, \irqnr, #8 - tsteq \irqstat, #0xff - moveq \irqstat, \irqstat, lsr #8 - addeq \irqnr, \irqnr, #8 - tst \irqstat, #0x0f - moveq \irqstat, \irqstat, lsr #4 - addeq \irqnr, \irqnr, #4 - tst \irqstat, #0x03 - moveq \irqstat, \irqstat, lsr #2 - addeq \irqnr, \irqnr, #2 - tst \irqstat, #0x01 - addeqs \irqnr, \irqnr, #1 -1001: - .endm - diff --git a/include/asm-arm/arch-sa1100/gpio.h b/include/asm-arm/arch-sa1100/gpio.h deleted file mode 100644 index 93d3395..0000000 --- a/include/asm-arm/arch-sa1100/gpio.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/gpio.h - * - * SA1100 GPIO wrappers for arch-neutral GPIO calls - * - * Written by Philipp Zabel <philipp.zabel@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARCH_SA1100_GPIO_H -#define __ASM_ARCH_SA1100_GPIO_H - -#include <asm/hardware.h> -#include <asm/irq.h> -#include <asm-generic/gpio.h> - -static inline int gpio_get_value(unsigned gpio) -{ - if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) - return GPLR & GPIO_GPIO(gpio); - else - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) - if (value) - GPSR = GPIO_GPIO(gpio); - else - GPCR = GPIO_GPIO(gpio); - else - __gpio_set_value(gpio, value); -} - -#define gpio_cansleep __gpio_cansleep - -static inline unsigned gpio_to_irq(unsigned gpio) -{ - if (gpio < 11) - return IRQ_GPIO0 + gpio; - else - return IRQ_GPIO11 - 11 + gpio; -} - -static inline unsigned irq_to_gpio(unsigned irq) -{ - if (irq < IRQ_GPIO11_27) - return irq - IRQ_GPIO0; - else - return irq - IRQ_GPIO11 + 11; -} - -#endif diff --git a/include/asm-arm/arch-sa1100/h3600.h b/include/asm-arm/arch-sa1100/h3600.h deleted file mode 100644 index 3ca0ecf..0000000 --- a/include/asm-arm/arch-sa1100/h3600.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * - * Definitions for H3600 Handheld Computer - * - * Copyright 2000 Compaq Computer Corporation. - * - * Use consistent with the GNU GPL is permitted, - * provided that this copyright notice is - * preserved in its entirety in all copies and derived works. - * - * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, - * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS - * FITNESS FOR ANY PARTICULAR PURPOSE. - * - * Author: Jamey Hicks. - * - * History: - * - * 2001-10-?? Andrew Christian Added support for iPAQ H3800 - * - */ - -#ifndef _INCLUDE_H3600_H_ -#define _INCLUDE_H3600_H_ - -typedef int __bitwise pm_request_t; - -#define PM_SUSPEND ((__force pm_request_t) 1) /* enter D1-D3 */ -#define PM_RESUME ((__force pm_request_t) 2) /* enter D0 */ - -/* generalized support for H3xxx series Compaq Pocket PC's */ -#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800()) - -/* Physical memory regions corresponding to chip selects */ -#define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) -#define H3600_BANK_2_PHYS SA1100_CS2_PHYS -#define H3600_BANK_4_PHYS SA1100_CS4_PHYS - -/* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */ -#define H3600_EGPIO_VIRT 0xf0000000 -#define H3600_BANK_2_VIRT 0xf1000000 -#define H3600_BANK_4_VIRT 0xf3800000 - -/* - Machine-independent GPIO definitions - --- these are common across all current iPAQ platforms -*/ - -#define GPIO_H3600_NPOWER_BUTTON GPIO_GPIO (0) /* Also known as the "off button" */ - -#define GPIO_H3600_PCMCIA_CD1 GPIO_GPIO (10) -#define GPIO_H3600_PCMCIA_IRQ1 GPIO_GPIO (11) - -/* UDA1341 L3 Interface */ -#define GPIO_H3600_L3_DATA GPIO_GPIO (14) -#define GPIO_H3600_L3_MODE GPIO_GPIO (15) -#define GPIO_H3600_L3_CLOCK GPIO_GPIO (16) - -#define GPIO_H3600_PCMCIA_CD0 GPIO_GPIO (17) -#define GPIO_H3600_SYS_CLK GPIO_GPIO (19) -#define GPIO_H3600_PCMCIA_IRQ0 GPIO_GPIO (21) - -#define GPIO_H3600_COM_DCD GPIO_GPIO (23) -#define GPIO_H3600_OPT_IRQ GPIO_GPIO (24) -#define GPIO_H3600_COM_CTS GPIO_GPIO (25) -#define GPIO_H3600_COM_RTS GPIO_GPIO (26) - -#define IRQ_GPIO_H3600_NPOWER_BUTTON IRQ_GPIO0 -#define IRQ_GPIO_H3600_PCMCIA_CD1 IRQ_GPIO10 -#define IRQ_GPIO_H3600_PCMCIA_IRQ1 IRQ_GPIO11 -#define IRQ_GPIO_H3600_PCMCIA_CD0 IRQ_GPIO17 -#define IRQ_GPIO_H3600_PCMCIA_IRQ0 IRQ_GPIO21 -#define IRQ_GPIO_H3600_COM_DCD IRQ_GPIO23 -#define IRQ_GPIO_H3600_OPT_IRQ IRQ_GPIO24 -#define IRQ_GPIO_H3600_COM_CTS IRQ_GPIO25 - - -#ifndef __ASSEMBLY__ - -enum ipaq_egpio_type { - IPAQ_EGPIO_LCD_POWER, /* Power to the LCD panel */ - IPAQ_EGPIO_CODEC_NRESET, /* Clear to reset the audio codec (remember to return high) */ - IPAQ_EGPIO_AUDIO_ON, /* Audio power */ - IPAQ_EGPIO_QMUTE, /* Audio muting */ - IPAQ_EGPIO_OPT_NVRAM_ON, /* Non-volatile RAM on extension sleeves (SPI interface) */ - IPAQ_EGPIO_OPT_ON, /* Power to extension sleeves */ - IPAQ_EGPIO_CARD_RESET, /* Reset PCMCIA cards on extension sleeve (???) */ - IPAQ_EGPIO_OPT_RESET, /* Reset option pack (???) */ - IPAQ_EGPIO_IR_ON, /* IR sensor/emitter power */ - IPAQ_EGPIO_IR_FSEL, /* IR speed selection 1->fast, 0->slow */ - IPAQ_EGPIO_RS232_ON, /* Maxim RS232 chip power */ - IPAQ_EGPIO_VPP_ON, /* Turn on power to flash programming */ - IPAQ_EGPIO_LCD_ENABLE, /* Enable/disable LCD controller */ -}; - -struct ipaq_model_ops { - const char *generic_name; - void (*control)(enum ipaq_egpio_type, int); - unsigned long (*read)(void); - void (*blank_callback)(int blank); - int (*pm_callback)(int req); /* Primary model callback */ - int (*pm_callback_aux)(int req); /* Secondary callback (used by HAL modules) */ -}; - -extern struct ipaq_model_ops ipaq_model_ops; - -static __inline__ const char * h3600_generic_name(void) -{ - return ipaq_model_ops.generic_name; -} - -static __inline__ void assign_h3600_egpio(enum ipaq_egpio_type x, int level) -{ - if (ipaq_model_ops.control) - ipaq_model_ops.control(x,level); -} - -static __inline__ void clr_h3600_egpio(enum ipaq_egpio_type x) -{ - if (ipaq_model_ops.control) - ipaq_model_ops.control(x,0); -} - -static __inline__ void set_h3600_egpio(enum ipaq_egpio_type x) -{ - if (ipaq_model_ops.control) - ipaq_model_ops.control(x,1); -} - -static __inline__ unsigned long read_h3600_egpio(void) -{ - if (ipaq_model_ops.read) - return ipaq_model_ops.read(); - return 0; -} - -static __inline__ int h3600_register_blank_callback(void (*f)(int)) -{ - ipaq_model_ops.blank_callback = f; - return 0; -} - -static __inline__ void h3600_unregister_blank_callback(void (*f)(int)) -{ - ipaq_model_ops.blank_callback = NULL; -} - - -static __inline__ int h3600_register_pm_callback(int (*f)(int)) -{ - ipaq_model_ops.pm_callback_aux = f; - return 0; -} - -static __inline__ void h3600_unregister_pm_callback(int (*f)(int)) -{ - ipaq_model_ops.pm_callback_aux = NULL; -} - -static __inline__ int h3600_power_management(int req) -{ - if (ipaq_model_ops.pm_callback) - return ipaq_model_ops.pm_callback(req); - return 0; -} - -#endif /* ASSEMBLY */ - -#endif /* _INCLUDE_H3600_H_ */ diff --git a/include/asm-arm/arch-sa1100/h3600_gpio.h b/include/asm-arm/arch-sa1100/h3600_gpio.h deleted file mode 100644 index 62b0b78..0000000 --- a/include/asm-arm/arch-sa1100/h3600_gpio.h +++ /dev/null @@ -1,540 +0,0 @@ -/* - * - * Definitions for H3600 Handheld Computer - * - * Copyright 2000 Compaq Computer Corporation. - * - * Use consistent with the GNU GPL is permitted, - * provided that this copyright notice is - * preserved in its entirety in all copies and derived works. - * - * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, - * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS - * FITNESS FOR ANY PARTICULAR PURPOSE. - * - * Author: Jamey Hicks. - * - * History: - * - * 2001-10-?? Andrew Christian Added support for iPAQ H3800 - * - */ - -#ifndef _INCLUDE_H3600_GPIO_H_ -#define _INCLUDE_H3600_GPIO_H_ - -/* - * GPIO lines that are common across ALL iPAQ models are in "h3600.h" - * This file contains machine-specific definitions - */ - -#define GPIO_H3600_SUSPEND GPIO_GPIO (0) -/* GPIO[2:9] used by LCD on H3600/3800, used as GPIO on H3100 */ -#define GPIO_H3100_BT_ON GPIO_GPIO (2) -#define GPIO_H3100_GPIO3 GPIO_GPIO (3) -#define GPIO_H3100_QMUTE GPIO_GPIO (4) -#define GPIO_H3100_LCD_3V_ON GPIO_GPIO (5) -#define GPIO_H3100_AUD_ON GPIO_GPIO (6) -#define GPIO_H3100_AUD_PWR_ON GPIO_GPIO (7) -#define GPIO_H3100_IR_ON GPIO_GPIO (8) -#define GPIO_H3100_IR_FSEL GPIO_GPIO (9) - -/* for H3600, audio sample rate clock generator */ -#define GPIO_H3600_CLK_SET0 GPIO_GPIO (12) -#define GPIO_H3600_CLK_SET1 GPIO_GPIO (13) - -#define GPIO_H3600_ACTION_BUTTON GPIO_GPIO (18) -#define GPIO_H3600_SOFT_RESET GPIO_GPIO (20) /* Also known as BATT_FAULT */ -#define GPIO_H3600_OPT_LOCK GPIO_GPIO (22) -#define GPIO_H3600_OPT_DET GPIO_GPIO (27) - -/* H3800 specific pins */ -#define GPIO_H3800_AC_IN GPIO_GPIO (12) -#define GPIO_H3800_COM_DSR GPIO_GPIO (13) -#define GPIO_H3800_MMC_INT GPIO_GPIO (18) -#define GPIO_H3800_NOPT_IND GPIO_GPIO (20) /* Almost exactly the same as GPIO_H3600_OPT_DET */ -#define GPIO_H3800_OPT_BAT_FAULT GPIO_GPIO (22) -#define GPIO_H3800_CLK_OUT GPIO_GPIO (27) - -/****************************************************/ - -#define IRQ_GPIO_H3600_ACTION_BUTTON IRQ_GPIO18 -#define IRQ_GPIO_H3600_OPT_DET IRQ_GPIO27 - -#define IRQ_GPIO_H3800_MMC_INT IRQ_GPIO18 -#define IRQ_GPIO_H3800_NOPT_IND IRQ_GPIO20 /* almost same as OPT_DET */ - -/* H3100 / 3600 EGPIO pins */ -#define EGPIO_H3600_VPP_ON (1 << 0) -#define EGPIO_H3600_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */ -#define EGPIO_H3600_OPT_RESET (1 << 2) /* reset the attached option pack. active high. */ -#define EGPIO_H3600_CODEC_NRESET (1 << 3) /* reset the onboard UDA1341. active low. */ -#define EGPIO_H3600_OPT_NVRAM_ON (1 << 4) /* apply power to optionpack nvram, active high. */ -#define EGPIO_H3600_OPT_ON (1 << 5) /* full power to option pack. active high. */ -#define EGPIO_H3600_LCD_ON (1 << 6) /* enable 3.3V to LCD. active high. */ -#define EGPIO_H3600_RS232_ON (1 << 7) /* UART3 transceiver force on. Active high. */ - -/* H3600 only EGPIO pins */ -#define EGPIO_H3600_LCD_PCI (1 << 8) /* LCD control IC enable. active high. */ -#define EGPIO_H3600_IR_ON (1 << 9) /* apply power to IR module. active high. */ -#define EGPIO_H3600_AUD_AMP_ON (1 << 10) /* apply power to audio power amp. active high. */ -#define EGPIO_H3600_AUD_PWR_ON (1 << 11) /* apply power to reset of audio circuit. active high. */ -#define EGPIO_H3600_QMUTE (1 << 12) /* mute control for onboard UDA1341. active high. */ -#define EGPIO_H3600_IR_FSEL (1 << 13) /* IR speed select: 1->fast, 0->slow */ -#define EGPIO_H3600_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */ -#define EGPIO_H3600_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */ - -/********************* H3800, ASIC #2 ********************/ - -#define _H3800_ASIC2_Base (H3600_EGPIO_VIRT) -#define H3800_ASIC2_OFFSET(s,x,y) \ - (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) -#define H3800_ASIC2_NOFFSET(s,x,n,y) \ - (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) - -#define _H3800_ASIC2_GPIO_Base 0x0000 -#define _H3800_ASIC2_GPIO_Direction 0x0000 /* R/W, 16 bits 1:input, 0:output */ -#define _H3800_ASIC2_GPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ -#define _H3800_ASIC2_GPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ -#define _H3800_ASIC2_GPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ -#define _H3800_ASIC2_GPIO_InterruptClear 0x0010 /* W, 12 bits */ -#define _H3800_ASIC2_GPIO_InterruptFlag 0x0010 /* R, 12 bits - reads int status */ -#define _H3800_ASIC2_GPIO_Data 0x0014 /* R/W, 16 bits */ -#define _H3800_ASIC2_GPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ -#define _H3800_ASIC2_GPIO_InterruptEnable 0x001c /* R/W, 12 bits 1:enable interrupt */ -#define _H3800_ASIC2_GPIO_Alternate 0x003c /* R/W, 12+1 bits - set alternate functions */ - -#define H3800_ASIC2_GPIO_Direction H3800_ASIC2_OFFSET( u16, GPIO, Direction ) -#define H3800_ASIC2_GPIO_InterruptType H3800_ASIC2_OFFSET( u16, GPIO, InterruptType ) -#define H3800_ASIC2_GPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType ) -#define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType ) -#define H3800_ASIC2_GPIO_InterruptClear H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear ) -#define H3800_ASIC2_GPIO_InterruptFlag H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag ) -#define H3800_ASIC2_GPIO_Data H3800_ASIC2_OFFSET( u16, GPIO, Data ) -#define H3800_ASIC2_GPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut ) -#define H3800_ASIC2_GPIO_InterruptEnable H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable ) -#define H3800_ASIC2_GPIO_Alternate H3800_ASIC2_OFFSET( u16, GPIO, Alternate ) - -#define GPIO_H3800_ASIC2_IN_Y1_N (1 << 0) /* Output: Touchscreen Y1 */ -#define GPIO_H3800_ASIC2_IN_X0 (1 << 1) /* Output: Touchscreen X0 */ -#define GPIO_H3800_ASIC2_IN_Y0 (1 << 2) /* Output: Touchscreen Y0 */ -#define GPIO_H3800_ASIC2_IN_X1_N (1 << 3) /* Output: Touchscreen X1 */ -#define GPIO_H3800_ASIC2_BT_RST (1 << 4) /* Output: Bluetooth reset */ -#define GPIO_H3800_ASIC2_PEN_IRQ (1 << 5) /* Input : Pen down */ -#define GPIO_H3800_ASIC2_SD_DETECT (1 << 6) /* Input : SD detect */ -#define GPIO_H3800_ASIC2_EAR_IN_N (1 << 7) /* Input : Audio jack plug inserted */ -#define GPIO_H3800_ASIC2_OPT_PCM_RESET (1 << 8) /* Output: */ -#define GPIO_H3800_ASIC2_OPT_RESET (1 << 9) /* Output: */ -#define GPIO_H3800_ASIC2_USB_DETECT_N (1 << 10) /* Input : */ -#define GPIO_H3800_ASIC2_SD_CON_SLT (1 << 11) /* Input : */ - -#define _H3800_ASIC2_KPIO_Base 0x0200 -#define _H3800_ASIC2_KPIO_Direction 0x0000 /* R/W, 12 bits 1:input, 0:output */ -#define _H3800_ASIC2_KPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ -#define _H3800_ASIC2_KPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ -#define _H3800_ASIC2_KPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ -#define _H3800_ASIC2_KPIO_InterruptClear 0x0010 /* W, 20 bits - 8 special */ -#define _H3800_ASIC2_KPIO_InterruptFlag 0x0010 /* R, 20 bits - 8 special - reads int status */ -#define _H3800_ASIC2_KPIO_Data 0x0014 /* R/W, 16 bits */ -#define _H3800_ASIC2_KPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ -#define _H3800_ASIC2_KPIO_InterruptEnable 0x001c /* R/W, 20 bits - 8 special */ -#define _H3800_ASIC2_KPIO_Alternate 0x003c /* R/W, 6 bits */ - -#define H3800_ASIC2_KPIO_Direction H3800_ASIC2_OFFSET( u16, KPIO, Direction ) -#define H3800_ASIC2_KPIO_InterruptType H3800_ASIC2_OFFSET( u16, KPIO, InterruptType ) -#define H3800_ASIC2_KPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType ) -#define H3800_ASIC2_KPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType ) -#define H3800_ASIC2_KPIO_InterruptClear H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear ) -#define H3800_ASIC2_KPIO_InterruptFlag H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag ) -#define H3800_ASIC2_KPIO_Data H3800_ASIC2_OFFSET( u16, KPIO, Data ) -#define H3800_ASIC2_KPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut ) -#define H3800_ASIC2_KPIO_InterruptEnable H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable ) -#define H3800_ASIC2_KPIO_Alternate H3800_ASIC2_OFFSET( u16, KPIO, Alternate ) - -#define H3800_ASIC2_KPIO_SPI_INT ( 1 << 16 ) -#define H3800_ASIC2_KPIO_OWM_INT ( 1 << 17 ) -#define H3800_ASIC2_KPIO_ADC_INT ( 1 << 18 ) -#define H3800_ASIC2_KPIO_UART_0_INT ( 1 << 19 ) -#define H3800_ASIC2_KPIO_UART_1_INT ( 1 << 20 ) -#define H3800_ASIC2_KPIO_TIMER_0_INT ( 1 << 21 ) -#define H3800_ASIC2_KPIO_TIMER_1_INT ( 1 << 22 ) -#define H3800_ASIC2_KPIO_TIMER_2_INT ( 1 << 23 ) - -#define KPIO_H3800_ASIC2_RECORD_BTN_N (1 << 0) /* Record button */ -#define KPIO_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Keypad */ -#define KPIO_H3800_ASIC2_KEY_5W2_N (1 << 2) /* */ -#define KPIO_H3800_ASIC2_KEY_5W3_N (1 << 3) /* */ -#define KPIO_H3800_ASIC2_KEY_5W4_N (1 << 4) /* */ -#define KPIO_H3800_ASIC2_KEY_5W5_N (1 << 5) /* */ -#define KPIO_H3800_ASIC2_KEY_LEFT_N (1 << 6) /* */ -#define KPIO_H3800_ASIC2_KEY_RIGHT_N (1 << 7) /* */ -#define KPIO_H3800_ASIC2_KEY_AP1_N (1 << 8) /* Old "Calendar" */ -#define KPIO_H3800_ASIC2_KEY_AP2_N (1 << 9) /* Old "Schedule" */ -#define KPIO_H3800_ASIC2_KEY_AP3_N (1 << 10) /* Old "Q" */ -#define KPIO_H3800_ASIC2_KEY_AP4_N (1 << 11) /* Old "Undo" */ - -/* Alternate KPIO functions (set by default) */ -#define KPIO_ALT_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Action key */ -#define KPIO_ALT_H3800_ASIC2_KEY_5W2_N (1 << 2) /* J1 of keypad input */ -#define KPIO_ALT_H3800_ASIC2_KEY_5W3_N (1 << 3) /* J2 of keypad input */ -#define KPIO_ALT_H3800_ASIC2_KEY_5W4_N (1 << 4) /* J3 of keypad input */ -#define KPIO_ALT_H3800_ASIC2_KEY_5W5_N (1 << 5) /* J4 of keypad input */ - -#define _H3800_ASIC2_SPI_Base 0x0400 -#define _H3800_ASIC2_SPI_Control 0x0000 /* R/W 8 bits */ -#define _H3800_ASIC2_SPI_Data 0x0004 /* R/W 8 bits */ -#define _H3800_ASIC2_SPI_ChipSelectDisabled 0x0008 /* W 8 bits */ - -#define H3800_ASIC2_SPI_Control H3800_ASIC2_OFFSET( u8, SPI, Control ) -#define H3800_ASIC2_SPI_Data H3800_ASIC2_OFFSET( u8, SPI, Data ) -#define H3800_ASIC2_SPI_ChipSelectDisabled H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled ) - -#define _H3800_ASIC2_PWM_0_Base 0x0600 -#define _H3800_ASIC2_PWM_1_Base 0x0700 -#define _H3800_ASIC2_PWM_TimeBase 0x0000 /* R/W 6 bits */ -#define _H3800_ASIC2_PWM_PeriodTime 0x0004 /* R/W 12 bits */ -#define _H3800_ASIC2_PWM_DutyTime 0x0008 /* R/W 12 bits */ - -#define H3800_ASIC2_PWM_0_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 0, TimeBase ) -#define H3800_ASIC2_PWM_0_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime ) -#define H3800_ASIC2_PWM_0_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime ) - -#define H3800_ASIC2_PWM_1_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 1, TimeBase ) -#define H3800_ASIC2_PWM_1_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime ) -#define H3800_ASIC2_PWM_1_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime ) - -#define H3800_ASIC2_PWM_TIMEBASE_MASK 0xf /* Low 4 bits sets time base, max = 8 */ -#define H3800_ASIC2_PWM_TIMEBASE_ENABLE ( 1 << 4 ) /* Enable clock */ -#define H3800_ASIC2_PWM_TIMEBASE_CLEAR ( 1 << 5 ) /* Clear the PWM */ - -#define _H3800_ASIC2_LED_0_Base 0x0800 -#define _H3800_ASIC2_LED_1_Base 0x0880 -#define _H3800_ASIC2_LED_2_Base 0x0900 -#define _H3800_ASIC2_LED_TimeBase 0x0000 /* R/W 7 bits */ -#define _H3800_ASIC2_LED_PeriodTime 0x0004 /* R/W 12 bits */ -#define _H3800_ASIC2_LED_DutyTime 0x0008 /* R/W 12 bits */ -#define _H3800_ASIC2_LED_AutoStopCount 0x000c /* R/W 16 bits */ - -#define H3800_ASIC2_LED_0_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 0, TimeBase ) -#define H3800_ASIC2_LED_0_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime ) -#define H3800_ASIC2_LED_0_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime ) -#define H3800_ASIC2_LED_0_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock ) - -#define H3800_ASIC2_LED_1_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 1, TimeBase ) -#define H3800_ASIC2_LED_1_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime ) -#define H3800_ASIC2_LED_1_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime ) -#define H3800_ASIC2_LED_1_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock ) - -#define H3800_ASIC2_LED_2_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 2, TimeBase ) -#define H3800_ASIC2_LED_2_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime ) -#define H3800_ASIC2_LED_2_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime ) -#define H3800_ASIC2_LED_2_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock ) - -#define H3800_ASIC2_LED_TIMEBASE_MASK 0x0f /* Low 4 bits sets time base, max = 13 */ -#define H3800_ASIC2_LED_TIMEBASE_BLINK ( 1 << 4 ) /* Enable blinking */ -#define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP ( 1 << 5 ) -#define H3800_ASIC2_LED_TIMEBASE_ALWAYS ( 1 << 6 ) /* Enable blink always */ - -#define _H3800_ASIC2_UART_0_Base 0x0A00 -#define _H3800_ASIC2_UART_1_Base 0x0C00 -#define _H3800_ASIC2_UART_Receive 0x0000 /* R 8 bits */ -#define _H3800_ASIC2_UART_Transmit 0x0000 /* W 8 bits */ -#define _H3800_ASIC2_UART_IntEnable 0x0004 /* R/W 8 bits */ -#define _H3800_ASIC2_UART_IntVerify 0x0008 /* R/W 8 bits */ -#define _H3800_ASIC2_UART_FIFOControl 0x000c /* R/W 8 bits */ -#define _H3800_ASIC2_UART_LineControl 0x0010 /* R/W 8 bits */ -#define _H3800_ASIC2_UART_ModemStatus 0x0014 /* R/W 8 bits */ -#define _H3800_ASIC2_UART_LineStatus 0x0018 /* R/W 8 bits */ -#define _H3800_ASIC2_UART_ScratchPad 0x001c /* R/W 8 bits */ -#define _H3800_ASIC2_UART_DivisorLatchL 0x0020 /* R/W 8 bits */ -#define _H3800_ASIC2_UART_DivisorLatchH 0x0024 /* R/W 8 bits */ - -#define H3800_ASIC2_UART_0_Receive H3800_ASIC2_NOFFSET( u8, UART, 0, Receive ) -#define H3800_ASIC2_UART_0_Transmit H3800_ASIC2_NOFFSET( u8, UART, 0, Transmit ) -#define H3800_ASIC2_UART_0_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 0, IntEnable ) -#define H3800_ASIC2_UART_0_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 0, IntVerify ) -#define H3800_ASIC2_UART_0_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 0, FIFOControl ) -#define H3800_ASIC2_UART_0_LineControl H3800_ASIC2_NOFFSET( u8, UART, 0, LineControl ) -#define H3800_ASIC2_UART_0_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 0, ModemStatus ) -#define H3800_ASIC2_UART_0_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 0, LineStatus ) -#define H3800_ASIC2_UART_0_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 0, ScratchPad ) -#define H3800_ASIC2_UART_0_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchL ) -#define H3800_ASIC2_UART_0_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchH ) - -#define H3800_ASIC2_UART_1_Receive H3800_ASIC2_NOFFSET( u8, UART, 1, Receive ) -#define H3800_ASIC2_UART_1_Transmit H3800_ASIC2_NOFFSET( u8, UART, 1, Transmit ) -#define H3800_ASIC2_UART_1_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 1, IntEnable ) -#define H3800_ASIC2_UART_1_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 1, IntVerify ) -#define H3800_ASIC2_UART_1_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 1, FIFOControl ) -#define H3800_ASIC2_UART_1_LineControl H3800_ASIC2_NOFFSET( u8, UART, 1, LineControl ) -#define H3800_ASIC2_UART_1_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 1, ModemStatus ) -#define H3800_ASIC2_UART_1_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 1, LineStatus ) -#define H3800_ASIC2_UART_1_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 1, ScratchPad ) -#define H3800_ASIC2_UART_1_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchL ) -#define H3800_ASIC2_UART_1_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchH ) - -#define _H3800_ASIC2_TIMER_Base 0x0E00 -#define _H3800_ASIC2_TIMER_Command 0x0000 /* R/W 8 bits */ - -#define H3800_ASIC2_TIMER_Command H3800_ASIC2_OFFSET( u8, Timer, Command ) - -#define H3800_ASIC2_TIMER_GAT_0 ( 1 << 0 ) /* Gate enable, counter 0 */ -#define H3800_ASIC2_TIMER_GAT_1 ( 1 << 1 ) /* Gate enable, counter 1 */ -#define H3800_ASIC2_TIMER_GAT_2 ( 1 << 2 ) /* Gate enable, counter 2 */ -#define H3800_ASIC2_TIMER_CLK_0 ( 1 << 3 ) /* Clock enable, counter 0 */ -#define H3800_ASIC2_TIMER_CLK_1 ( 1 << 4 ) /* Clock enable, counter 1 */ -#define H3800_ASIC2_TIMER_CLK_2 ( 1 << 5 ) /* Clock enable, counter 2 */ -#define H3800_ASIC2_TIMER_MODE_0 ( 1 << 6 ) /* Mode 0 enable, counter 0 */ -#define H3800_ASIC2_TIMER_MODE_1 ( 1 << 7 ) /* Mode 0 enable, counter 1 */ - -#define _H3800_ASIC2_CLOCK_Base 0x1000 -#define _H3800_ASIC2_CLOCK_Enable 0x0000 /* R/W 18 bits */ - -#define H3800_ASIC2_CLOCK_Enable H3800_ASIC2_OFFSET( u32, CLOCK, Enable ) - -#define H3800_ASIC2_CLOCK_AUDIO_1 0x0001 /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */ -#define H3800_ASIC2_CLOCK_AUDIO_2 0x0002 /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */ -#define H3800_ASIC2_CLOCK_AUDIO_3 0x0004 /* Enable 5.6 MHz clock for 11 kHZ sample rate */ -#define H3800_ASIC2_CLOCK_AUDIO_4 0x0008 /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */ -#define H3800_ASIC2_CLOCK_ADC ( 1 << 4 ) /* 1.024 MHz clock to ADC */ -#define H3800_ASIC2_CLOCK_SPI ( 1 << 5 ) /* 4.096 MHz clock to SPI */ -#define H3800_ASIC2_CLOCK_OWM ( 1 << 6 ) /* 4.096 MHz clock to OWM */ -#define H3800_ASIC2_CLOCK_PWM ( 1 << 7 ) /* 2.048 MHz clock to PWM */ -#define H3800_ASIC2_CLOCK_UART_1 ( 1 << 8 ) /* 24.576 MHz clock to UART1 (turn off bit 16) */ -#define H3800_ASIC2_CLOCK_UART_0 ( 1 << 9 ) /* 24.576 MHz clock to UART0 (turn off bit 17) */ -#define H3800_ASIC2_CLOCK_SD_1 ( 1 << 10 ) /* 16.934 MHz to SD */ -#define H3800_ASIC2_CLOCK_SD_2 ( 2 << 10 ) /* 24.576 MHz to SD */ -#define H3800_ASIC2_CLOCK_SD_3 ( 3 << 10 ) /* 33.869 MHz to SD */ -#define H3800_ASIC2_CLOCK_SD_4 ( 4 << 10 ) /* 49.152 MHz to SD */ -#define H3800_ASIC2_CLOCK_EX0 ( 1 << 13 ) /* Enable 32.768 kHz crystal */ -#define H3800_ASIC2_CLOCK_EX1 ( 1 << 14 ) /* Enable 24.576 MHz crystal */ -#define H3800_ASIC2_CLOCK_EX2 ( 1 << 15 ) /* Enable 33.869 MHz crystal */ -#define H3800_ASIC2_CLOCK_SLOW_UART_1 ( 1 << 16 ) /* Enable 3.686 MHz to UART1 (turn off bit 8) */ -#define H3800_ASIC2_CLOCK_SLOW_UART_0 ( 1 << 17 ) /* Enable 3.686 MHz to UART0 (turn off bit 9) */ - -#define _H3800_ASIC2_ADC_Base 0x1200 -#define _H3800_ASIC2_ADC_Multiplexer 0x0000 /* R/W 4 bits - low 3 bits set channel */ -#define _H3800_ASIC2_ADC_ControlStatus 0x0004 /* R/W 8 bits */ -#define _H3800_ASIC2_ADC_Data 0x0008 /* R 10 bits */ - -#define H3800_ASIC2_ADC_Multiplexer H3800_ASIC2_OFFSET( u8, ADC, Multiplexer ) -#define H3800_ASIC2_ADC_ControlStatus H3800_ASIC2_OFFSET( u8, ADC, ControlStatus ) -#define H3800_ASIC2_ADC_Data H3800_ASIC2_OFFSET( u16, ADC, Data ) - -#define H3600_ASIC2_ADC_MUX_CHANNEL_MASK 0x07 /* Low 3 bits sets channel. max = 4 */ -#define H3600_ASIC2_ADC_MUX_CLKEN ( 1 << 3 ) /* Enable clock */ - -#define H3600_ASIC2_ADC_CSR_ADPS_MASK 0x0f /* Low 4 bits sets prescale, max = 8 */ -#define H3600_ASIC2_ADC_CSR_FREE_RUN ( 1 << 4 ) -#define H3600_ASIC2_ADC_CSR_INT_ENABLE ( 1 << 5 ) -#define H3600_ASIC2_ADC_CSR_START ( 1 << 6 ) /* Set to start conversion. Goes to 0 when done */ -#define H3600_ASIC2_ADC_CSR_ENABLE ( 1 << 7 ) /* 1:power up ADC, 0:power down */ - - -#define _H3800_ASIC2_INTR_Base 0x1600 -#define _H3800_ASIC2_INTR_MaskAndFlag 0x0000 /* R/(W) 8bits */ -#define _H3800_ASIC2_INTR_ClockPrescale 0x0004 /* R/(W) 5bits */ -#define _H3800_ASIC2_INTR_TimerSet 0x0008 /* R/(W) 8bits */ - -#define H3800_ASIC2_INTR_MaskAndFlag H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag ) -#define H3800_ASIC2_INTR_ClockPrescale H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale ) -#define H3800_ASIC2_INTR_TimerSet H3800_ASIC2_OFFSET( u8, INTR, TimerSet ) - -#define H3800_ASIC2_INTR_GLOBAL_MASK ( 1 << 0 ) /* Global interrupt mask */ -#define H3800_ASIC2_INTR_POWER_ON_RESET ( 1 << 1 ) /* 01: Power on reset (bits 1 & 2 ) */ -#define H3800_ASIC2_INTR_EXTERNAL_RESET ( 2 << 1 ) /* 10: External reset (bits 1 & 2 ) */ -#define H3800_ASIC2_INTR_MASK_UART_0 ( 1 << 4 ) -#define H3800_ASIC2_INTR_MASK_UART_1 ( 1 << 5 ) -#define H3800_ASIC2_INTR_MASK_TIMER ( 1 << 6 ) -#define H3800_ASIC2_INTR_MASK_OWM ( 1 << 7 ) - -#define H3800_ASIC2_INTR_CLOCK_PRESCALE 0x0f /* 4 bits, max 14 */ -#define H3800_ASIC2_INTR_SET ( 1 << 4 ) /* Time base enable */ - - -#define _H3800_ASIC2_OWM_Base 0x1800 -#define _H3800_ASIC2_OWM_Command 0x0000 /* R/W 4 bits command register */ -#define _H3800_ASIC2_OWM_Data 0x0004 /* R/W 8 bits, transmit / receive buffer */ -#define _H3800_ASIC2_OWM_Interrupt 0x0008 /* R/W Command register */ -#define _H3800_ASIC2_OWM_InterruptEnable 0x000c /* R/W Command register */ -#define _H3800_ASIC2_OWM_ClockDivisor 0x0010 /* R/W 5 bits of divisor and pre-scale */ - -#define H3800_ASIC2_OWM_Command H3800_ASIC2_OFFSET( u8, OWM, Command ) -#define H3800_ASIC2_OWM_Data H3800_ASIC2_OFFSET( u8, OWM, Data ) -#define H3800_ASIC2_OWM_Interrupt H3800_ASIC2_OFFSET( u8, OWM, Interrupt ) -#define H3800_ASIC2_OWM_InterruptEnable H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable ) -#define H3800_ASIC2_OWM_ClockDivisor H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor ) - -#define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 ) /* Set to force reset on 1-wire bus */ -#define H3800_ASIC2_OWM_CMD_SRA ( 1 << 1 ) /* Set to switch to Search ROM accelerator mode */ -#define H3800_ASIC2_OWM_CMD_DQ_OUTPUT ( 1 << 2 ) /* Write only - forces bus low */ -#define H3800_ASIC2_OWM_CMD_DQ_INPUT ( 1 << 3 ) /* Read only - reflects state of bus */ - -#define H3800_ASIC2_OWM_INT_PD ( 1 << 0 ) /* Presence detect */ -#define H3800_ASIC2_OWM_INT_PDR ( 1 << 1 ) /* Presence detect result */ -#define H3800_ASIC2_OWM_INT_TBE ( 1 << 2 ) /* Transmit buffer empty */ -#define H3800_ASIC2_OWM_INT_TEMT ( 1 << 3 ) /* Transmit shift register empty */ -#define H3800_ASIC2_OWM_INT_RBF ( 1 << 4 ) /* Receive buffer full */ - -#define H3800_ASIC2_OWM_INTEN_EPD ( 1 << 0 ) /* Enable receive buffer full interrupt */ -#define H3800_ASIC2_OWM_INTEN_IAS ( 1 << 1 ) /* Enable transmit shift register empty interrupt */ -#define H3800_ASIC2_OWM_INTEN_ETBE ( 1 << 2 ) /* Enable transmit buffer empty interrupt */ -#define H3800_ASIC2_OWM_INTEN_ETMT ( 1 << 3 ) /* INTR active state */ -#define H3800_ASIC2_OWM_INTEN_ERBF ( 1 << 4 ) /* Enable presence detect interrupt */ - -#define _H3800_ASIC2_FlashCtl_Base 0x1A00 - -/****************************************************/ -/* H3800, ASIC #1 - * This ASIC is accesed through ASIC #2, and - * mapped into the 1c00 - 1f00 region - */ - -#define H3800_ASIC1_OFFSET(s,x,y) \ - (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1)))) - -#define _H3800_ASIC1_MMC_Base 0x1c00 - -#define _H3800_ASIC1_MMC_StartStopClock 0x00 /* R/W 8bit */ -#define _H3800_ASIC1_MMC_Status 0x02 /* R See below, default 0x0040 */ -#define _H3800_ASIC1_MMC_ClockRate 0x04 /* R/W 8bit, low 3 bits are clock divisor */ -#define _H3800_ASIC1_MMC_SPIRegister 0x08 /* R/W 8bit, see below */ -#define _H3800_ASIC1_MMC_CmdDataCont 0x0a /* R/W 8bit, write to start MMC adapter */ -#define _H3800_ASIC1_MMC_ResponseTimeout 0x0c /* R/W 8bit, clocks before response timeout */ -#define _H3800_ASIC1_MMC_ReadTimeout 0x0e /* R/W 16bit, clocks before received data timeout */ -#define _H3800_ASIC1_MMC_BlockLength 0x10 /* R/W 10bit */ -#define _H3800_ASIC1_MMC_NumOfBlocks 0x12 /* R/W 16bit, in block mode, number of blocks */ -#define _H3800_ASIC1_MMC_InterruptMask 0x1a /* R/W 8bit */ -#define _H3800_ASIC1_MMC_CommandNumber 0x1c /* R/W 6 bits */ -#define _H3800_ASIC1_MMC_ArgumentH 0x1e /* R/W 16 bits */ -#define _H3800_ASIC1_MMC_ArgumentL 0x20 /* R/W 16 bits */ -#define _H3800_ASIC1_MMC_ResFifo 0x22 /* R 8 x 16 bits - contains response FIFO */ -#define _H3800_ASIC1_MMC_BufferPartFull 0x28 /* R/W 8 bits */ - -#define H3800_ASIC1_MMC_StartStopClock H3800_ASIC1_OFFSET( u8, MMC, StartStopClock ) -#define H3800_ASIC1_MMC_Status H3800_ASIC1_OFFSET( u16, MMC, Status ) -#define H3800_ASIC1_MMC_ClockRate H3800_ASIC1_OFFSET( u8, MMC, ClockRate ) -#define H3800_ASIC1_MMC_SPIRegister H3800_ASIC1_OFFSET( u8, MMC, SPIRegister ) -#define H3800_ASIC1_MMC_CmdDataCont H3800_ASIC1_OFFSET( u8, MMC, CmdDataCont ) -#define H3800_ASIC1_MMC_ResponseTimeout H3800_ASIC1_OFFSET( u8, MMC, ResponseTimeout ) -#define H3800_ASIC1_MMC_ReadTimeout H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout ) -#define H3800_ASIC1_MMC_BlockLength H3800_ASIC1_OFFSET( u16, MMC, BlockLength ) -#define H3800_ASIC1_MMC_NumOfBlocks H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks ) -#define H3800_ASIC1_MMC_InterruptMask H3800_ASIC1_OFFSET( u8, MMC, InterruptMask ) -#define H3800_ASIC1_MMC_CommandNumber H3800_ASIC1_OFFSET( u8, MMC, CommandNumber ) -#define H3800_ASIC1_MMC_ArgumentH H3800_ASIC1_OFFSET( u16, MMC, ArgumentH ) -#define H3800_ASIC1_MMC_ArgumentL H3800_ASIC1_OFFSET( u16, MMC, ArgumentL ) -#define H3800_ASIC1_MMC_ResFifo H3800_ASIC1_OFFSET( u16, MMC, ResFifo ) -#define H3800_ASIC1_MMC_BufferPartFull H3800_ASIC1_OFFSET( u8, MMC, BufferPartFull ) - -#define H3800_ASIC1_MMC_STOP_CLOCK (1 << 0) /* Write to "StartStopClock" register */ -#define H3800_ASIC1_MMC_START_CLOCK (1 << 1) - -#define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT (1 << 0) -#define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT (1 << 1) -#define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR (1 << 2) -#define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR (1 << 3) -#define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR (1 << 4) /* SPI data token error received */ -#define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR (1 << 5) -#define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY (1 << 6) -#define H3800_ASIC1_MMC_STATUS_FIFO_FULL (1 << 7) -#define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE (1 << 8) /* MultiMediaCard clock stopped */ -#define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE (1 << 11) /* Write operation, indicates transfer finished */ -#define H3800_ASIC1_MMC_STATUS_END_PROGRAM (1 << 12) /* End write and read operations */ -#define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE (1 << 13) /* End command response */ - -#define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE (1 << 0) /* Enables SPI mode */ -#define H3800_ASIC1_MMC_SPI_REG_CRC_ON (1 << 1) /* 1:turn on CRC */ -#define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE (1 << 2) /* 1:turn on SPI CS */ -#define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK 0x38 /* Bits 3,4,5 are the SPI CS relative address */ - -#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE 0x00 -#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1 0x01 -#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2 0x02 -#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3 0x03 -#define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE (1 << 2) /* This command contains a data transfer */ -#define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE (1 << 3) /* This data transfer is a write */ -#define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE (1 << 4) /* This data transfer is in stream mode */ -#define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT (1 << 5) /* Busy signal expected after current cmd */ -#define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE (1 << 6) /* Enables the 80 bits for initializing card */ - -#define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE (1 << 0) -#define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE (1 << 1) -#define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE (1 << 2) -#define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY (1 << 3) - -#define H3800_ASIC1_MMC_BUFFER_PART_FULL (1 << 0) - -/********* GPIO **********/ - -#define _H3800_ASIC1_GPIO_Base 0x1e00 - -#define _H3800_ASIC1_GPIO_Mask 0x30 /* R/W 0:don't mask, 1:mask interrupt */ -#define _H3800_ASIC1_GPIO_Direction 0x32 /* R/W 0:input, 1:output */ -#define _H3800_ASIC1_GPIO_Out 0x34 /* R/W 0:output low, 1:output high */ -#define _H3800_ASIC1_GPIO_TriggerType 0x36 /* R/W 0:level, 1:edge */ -#define _H3800_ASIC1_GPIO_EdgeTrigger 0x38 /* R/W 0:falling, 1:rising */ -#define _H3800_ASIC1_GPIO_LevelTrigger 0x3A /* R/W 0:low, 1:high level detect */ -#define _H3800_ASIC1_GPIO_LevelStatus 0x3C /* R/W 0:none, 1:detect */ -#define _H3800_ASIC1_GPIO_EdgeStatus 0x3E /* R/W 0:none, 1:detect */ -#define _H3800_ASIC1_GPIO_State 0x40 /* R See masks below (default 0) */ -#define _H3800_ASIC1_GPIO_Reset 0x42 /* R/W See masks below (default 0x04) */ -#define _H3800_ASIC1_GPIO_SleepMask 0x44 /* R/W 0:don't mask, 1:mask trigger in sleep mode */ -#define _H3800_ASIC1_GPIO_SleepDir 0x46 /* R/W direction 0:input, 1:output in sleep mode */ -#define _H3800_ASIC1_GPIO_SleepOut 0x48 /* R/W level 0:low, 1:high in sleep mode */ -#define _H3800_ASIC1_GPIO_Status 0x4A /* R Pin status */ -#define _H3800_ASIC1_GPIO_BattFaultDir 0x4C /* R/W direction 0:input, 1:output in batt_fault */ -#define _H3800_ASIC1_GPIO_BattFaultOut 0x4E /* R/W level 0:low, 1:high in batt_fault */ - -#define H3800_ASIC1_GPIO_Mask H3800_ASIC1_OFFSET( u16, GPIO, Mask ) -#define H3800_ASIC1_GPIO_Direction H3800_ASIC1_OFFSET( u16, GPIO, Direction ) -#define H3800_ASIC1_GPIO_Out H3800_ASIC1_OFFSET( u16, GPIO, Out ) -#define H3800_ASIC1_GPIO_TriggerType H3800_ASIC1_OFFSET( u16, GPIO, TriggerType ) -#define H3800_ASIC1_GPIO_EdgeTrigger H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger ) -#define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger ) -#define H3800_ASIC1_GPIO_LevelStatus H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus ) -#define H3800_ASIC1_GPIO_EdgeStatus H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus ) -#define H3800_ASIC1_GPIO_State H3800_ASIC1_OFFSET( u8, GPIO, State ) -#define H3800_ASIC1_GPIO_Reset H3800_ASIC1_OFFSET( u8, GPIO, Reset ) -#define H3800_ASIC1_GPIO_SleepMask H3800_ASIC1_OFFSET( u16, GPIO, SleepMask ) -#define H3800_ASIC1_GPIO_SleepDir H3800_ASIC1_OFFSET( u16, GPIO, SleepDir ) -#define H3800_ASIC1_GPIO_SleepOut H3800_ASIC1_OFFSET( u16, GPIO, SleepOut ) -#define H3800_ASIC1_GPIO_Status H3800_ASIC1_OFFSET( u16, GPIO, Status ) -#define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir ) -#define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut ) - -#define H3800_ASIC1_GPIO_STATE_MASK (1 << 0) -#define H3800_ASIC1_GPIO_STATE_DIRECTION (1 << 1) -#define H3800_ASIC1_GPIO_STATE_OUT (1 << 2) -#define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE (1 << 3) -#define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER (1 << 4) -#define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER (1 << 5) - -#define H3800_ASIC1_GPIO_RESET_SOFTWARE (1 << 0) -#define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP (1 << 1) -#define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON (1 << 2) - -/* These are all outputs */ -#define GPIO_H3800_ASIC1_IR_ON_N (1 << 0) /* Apply power to the IR Module */ -#define GPIO_H3800_ASIC1_SD_PWR_ON (1 << 1) /* Secure Digital power on */ -#define GPIO_H3800_ASIC1_RS232_ON (1 << 2) /* Turn on power to the RS232 chip ? */ -#define GPIO_H3800_ASIC1_PULSE_GEN (1 << 3) /* Goes to speaker / earphone */ -#define GPIO_H3800_ASIC1_CH_TIMER (1 << 4) /* */ -#define GPIO_H3800_ASIC1_LCD_5V_ON (1 << 5) /* Enables LCD_5V */ -#define GPIO_H3800_ASIC1_LCD_ON (1 << 6) /* Enables LCD_3V */ -#define GPIO_H3800_ASIC1_LCD_PCI (1 << 7) /* Connects to PDWN on LCD controller */ -#define GPIO_H3800_ASIC1_VGH_ON (1 << 8) /* Drives VGH on the LCD (+9??) */ -#define GPIO_H3800_ASIC1_VGL_ON (1 << 9) /* Drivers VGL on the LCD (-6??) */ -#define GPIO_H3800_ASIC1_FL_PWR_ON (1 << 10) /* Frontlight power on */ -#define GPIO_H3800_ASIC1_BT_PWR_ON (1 << 11) /* Bluetooth power on */ -#define GPIO_H3800_ASIC1_SPK_ON (1 << 12) /* */ -#define GPIO_H3800_ASIC1_EAR_ON_N (1 << 13) /* */ -#define GPIO_H3800_ASIC1_AUD_PWR_ON (1 << 14) /* */ - -/* Write enable for the flash */ - -#define _H3800_ASIC1_FlashWP_Base 0x1F00 -#define _H3800_ASIC1_FlashWP_VPP_ON 0x00 /* R 1: write, 0: protect */ -#define H3800_ASIC1_FlashWP_VPP_ON H3800_ASIC1_OFFSET( u8, FlashWP, VPP_ON ) - -#endif /* _INCLUDE_H3600_GPIO_H_ */ diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h deleted file mode 100644 index 1abd7cf..0000000 --- a/include/asm-arm/arch-sa1100/hardware.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/hardware.h - * - * Copyright (C) 1998 Nicolas Pitre <nico@cam.org> - * - * This file contains the hardware definitions for SA1100 architecture - * - * 2000/05/23 John Dorsey <john+@cs.cmu.edu> - * Definitions for SA1111 added. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - - -#define UNCACHEABLE_ADDR 0xfa050000 - - -/* - * SA1100 internal I/O mappings - * - * We have the following mapping: - * phys virt - * 80000000 f8000000 - * 90000000 fa000000 - * a0000000 fc000000 - * b0000000 fe000000 - */ - -#define VIO_BASE 0xf8000000 /* virtual start of IO space */ -#define VIO_SHIFT 3 /* x = IO space shrink power */ -#define PIO_START 0x80000000 /* physical start of IO space */ - -#define io_p2v( x ) \ - ( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE ) -#define io_v2p( x ) \ - ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START ) - -#ifndef __ASSEMBLY__ - -# define __REG(x) (*((volatile unsigned long *)io_p2v(x))) -# define __PREG(x) (io_v2p((unsigned long)&(x))) - -#else - -# define __REG(x) io_p2v(x) -# define __PREG(x) io_v2p(x) - -#endif - -#include "SA-1100.h" - -#ifdef CONFIG_SA1101 -#include "SA-1101.h" -#endif - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-sa1100/ide.h b/include/asm-arm/arch-sa1100/ide.h deleted file mode 100644 index 193f6c1..0000000 --- a/include/asm-arm/arch-sa1100/ide.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/ide.h - * - * Copyright (c) 1998 Hugo Fiennes & Nicolas Pitre - * - * 18-aug-2000: Cleanup by Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * Get rid of the special ide_init_hwif_ports() functions - * and make a generalised function that can be used by all - * architectures. - */ - -#include <asm/irq.h> -#include <asm/hardware.h> -#include <asm/mach-types.h> - -#error "This code is broken and needs update to match with current ide support" - - -/* - * Set up a hw structure for a specified data port, control port and IRQ. - * This should follow whatever the default interface uses. - */ -static inline void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, - unsigned long ctrl_port, int *irq) -{ - unsigned long reg = data_port; - int i; - int regincr = 1; - - /* The Empeg board has the first two address lines unused */ - if (machine_is_empeg()) - regincr = 1 << 2; - - /* The LART doesn't use A0 for IDE */ - if (machine_is_lart()) - regincr = 1 << 1; - - memset(hw, 0, sizeof(*hw)); - - for (i = 0; i <= 7; i++) { - hw->io_ports_array[i] = reg; - reg += regincr; - } - - hw->io_ports.ctl_addr = ctrl_port; - - if (irq) - *irq = 0; -} - -/* - * This registers the standard ports for this architecture with the IDE - * driver. - */ -static __inline__ void -ide_init_default_hwifs(void) -{ - if (machine_is_lart()) { -#ifdef CONFIG_SA1100_LART - hw_regs_t hw; - - /* Enable GPIO as interrupt line */ - GPDR &= ~LART_GPIO_IDE; - set_irq_type(LART_IRQ_IDE, IRQ_TYPE_EDGE_RISING); - - /* set PCMCIA interface timing */ - MECR = 0x00060006; - - /* init the interface */ - ide_init_hwif_ports(&hw, PCMCIA_IO_0_BASE + 0x0000, PCMCIA_IO_0_BASE + 0x1000, NULL); - hw.irq = LART_IRQ_IDE; - ide_register_hw(&hw); -#endif - } -} diff --git a/include/asm-arm/arch-sa1100/io.h b/include/asm-arm/arch-sa1100/io.h deleted file mode 100644 index 0756269..0000000 --- a/include/asm-arm/arch-sa1100/io.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/io.h - * - * Copyright (C) 1997-1999 Russell King - * - * Modifications: - * 06-12-1997 RMK Created. - * 07-04-1999 RMK Major cleanup - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * We don't actually have real ISA nor PCI buses, but there is so many - * drivers out there that might just work if we fake them... - */ -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)addr; -} -#define __io(a) __io(a) -#define __mem_pci(a) (a) - -#endif diff --git a/include/asm-arm/arch-sa1100/irqs.h b/include/asm-arm/arch-sa1100/irqs.h deleted file mode 100644 index 7bf8048..0000000 --- a/include/asm-arm/arch-sa1100/irqs.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/irqs.h - * - * Copyright (C) 1996 Russell King - * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus). - * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation) - * - * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs. - */ - -#define IRQ_GPIO0 0 -#define IRQ_GPIO1 1 -#define IRQ_GPIO2 2 -#define IRQ_GPIO3 3 -#define IRQ_GPIO4 4 -#define IRQ_GPIO5 5 -#define IRQ_GPIO6 6 -#define IRQ_GPIO7 7 -#define IRQ_GPIO8 8 -#define IRQ_GPIO9 9 -#define IRQ_GPIO10 10 -#define IRQ_GPIO11_27 11 -#define IRQ_LCD 12 /* LCD controller */ -#define IRQ_Ser0UDC 13 /* Ser. port 0 UDC */ -#define IRQ_Ser1SDLC 14 /* Ser. port 1 SDLC */ -#define IRQ_Ser1UART 15 /* Ser. port 1 UART */ -#define IRQ_Ser2ICP 16 /* Ser. port 2 ICP */ -#define IRQ_Ser3UART 17 /* Ser. port 3 UART */ -#define IRQ_Ser4MCP 18 /* Ser. port 4 MCP */ -#define IRQ_Ser4SSP 19 /* Ser. port 4 SSP */ -#define IRQ_DMA0 20 /* DMA controller channel 0 */ -#define IRQ_DMA1 21 /* DMA controller channel 1 */ -#define IRQ_DMA2 22 /* DMA controller channel 2 */ -#define IRQ_DMA3 23 /* DMA controller channel 3 */ -#define IRQ_DMA4 24 /* DMA controller channel 4 */ -#define IRQ_DMA5 25 /* DMA controller channel 5 */ -#define IRQ_OST0 26 /* OS Timer match 0 */ -#define IRQ_OST1 27 /* OS Timer match 1 */ -#define IRQ_OST2 28 /* OS Timer match 2 */ -#define IRQ_OST3 29 /* OS Timer match 3 */ -#define IRQ_RTC1Hz 30 /* RTC 1 Hz clock */ -#define IRQ_RTCAlrm 31 /* RTC Alarm */ - -#define IRQ_GPIO11 32 -#define IRQ_GPIO12 33 -#define IRQ_GPIO13 34 -#define IRQ_GPIO14 35 -#define IRQ_GPIO15 36 -#define IRQ_GPIO16 37 -#define IRQ_GPIO17 38 -#define IRQ_GPIO18 39 -#define IRQ_GPIO19 40 -#define IRQ_GPIO20 41 -#define IRQ_GPIO21 42 -#define IRQ_GPIO22 43 -#define IRQ_GPIO23 44 -#define IRQ_GPIO24 45 -#define IRQ_GPIO25 46 -#define IRQ_GPIO26 47 -#define IRQ_GPIO27 48 - -/* - * The next 16 interrupts are for board specific purposes. Since - * the kernel can only run on one machine at a time, we can re-use - * these. If you need more, increase IRQ_BOARD_END, but keep it - * within sensible limits. IRQs 49 to 64 are available. - */ -#define IRQ_BOARD_START 49 -#define IRQ_BOARD_END 65 - -#define IRQ_SA1111_START (IRQ_BOARD_END) -#define IRQ_GPAIN0 (IRQ_BOARD_END + 0) -#define IRQ_GPAIN1 (IRQ_BOARD_END + 1) -#define IRQ_GPAIN2 (IRQ_BOARD_END + 2) -#define IRQ_GPAIN3 (IRQ_BOARD_END + 3) -#define IRQ_GPBIN0 (IRQ_BOARD_END + 4) -#define IRQ_GPBIN1 (IRQ_BOARD_END + 5) -#define IRQ_GPBIN2 (IRQ_BOARD_END + 6) -#define IRQ_GPBIN3 (IRQ_BOARD_END + 7) -#define IRQ_GPBIN4 (IRQ_BOARD_END + 8) -#define IRQ_GPBIN5 (IRQ_BOARD_END + 9) -#define IRQ_GPCIN0 (IRQ_BOARD_END + 10) -#define IRQ_GPCIN1 (IRQ_BOARD_END + 11) -#define IRQ_GPCIN2 (IRQ_BOARD_END + 12) -#define IRQ_GPCIN3 (IRQ_BOARD_END + 13) -#define IRQ_GPCIN4 (IRQ_BOARD_END + 14) -#define IRQ_GPCIN5 (IRQ_BOARD_END + 15) -#define IRQ_GPCIN6 (IRQ_BOARD_END + 16) -#define IRQ_GPCIN7 (IRQ_BOARD_END + 17) -#define IRQ_MSTXINT (IRQ_BOARD_END + 18) -#define IRQ_MSRXINT (IRQ_BOARD_END + 19) -#define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20) -#define IRQ_TPTXINT (IRQ_BOARD_END + 21) -#define IRQ_TPRXINT (IRQ_BOARD_END + 22) -#define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23) -#define SSPXMTINT (IRQ_BOARD_END + 24) -#define SSPRCVINT (IRQ_BOARD_END + 25) -#define SSPROR (IRQ_BOARD_END + 26) -#define AUDXMTDMADONEA (IRQ_BOARD_END + 32) -#define AUDRCVDMADONEA (IRQ_BOARD_END + 33) -#define AUDXMTDMADONEB (IRQ_BOARD_END + 34) -#define AUDRCVDMADONEB (IRQ_BOARD_END + 35) -#define AUDTFSR (IRQ_BOARD_END + 36) -#define AUDRFSR (IRQ_BOARD_END + 37) -#define AUDTUR (IRQ_BOARD_END + 38) -#define AUDROR (IRQ_BOARD_END + 39) -#define AUDDTS (IRQ_BOARD_END + 40) -#define AUDRDD (IRQ_BOARD_END + 41) -#define AUDSTO (IRQ_BOARD_END + 42) -#define IRQ_USBPWR (IRQ_BOARD_END + 43) -#define IRQ_HCIM (IRQ_BOARD_END + 44) -#define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45) -#define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46) -#define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47) -#define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48) -#define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49) -#define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50) -#define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51) -#define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52) -#define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53) -#define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54) - -#define IRQ_LOCOMO_START (IRQ_BOARD_END) -#define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0) -#define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1) -#define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2) -#define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3) -#define IRQ_LOCOMO_GPIO3 (IRQ_BOARD_END + 4) -#define IRQ_LOCOMO_GPIO4 (IRQ_BOARD_END + 5) -#define IRQ_LOCOMO_GPIO5 (IRQ_BOARD_END + 6) -#define IRQ_LOCOMO_GPIO6 (IRQ_BOARD_END + 7) -#define IRQ_LOCOMO_GPIO7 (IRQ_BOARD_END + 8) -#define IRQ_LOCOMO_GPIO8 (IRQ_BOARD_END + 9) -#define IRQ_LOCOMO_GPIO9 (IRQ_BOARD_END + 10) -#define IRQ_LOCOMO_GPIO10 (IRQ_BOARD_END + 11) -#define IRQ_LOCOMO_GPIO11 (IRQ_BOARD_END + 12) -#define IRQ_LOCOMO_GPIO12 (IRQ_BOARD_END + 13) -#define IRQ_LOCOMO_GPIO13 (IRQ_BOARD_END + 14) -#define IRQ_LOCOMO_GPIO14 (IRQ_BOARD_END + 15) -#define IRQ_LOCOMO_GPIO15 (IRQ_BOARD_END + 16) -#define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17) -#define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18) -#define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19) -#define IRQ_LOCOMO_SPI_REND (IRQ_BOARD_END + 20) -#define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21) - -/* - * Figure out the MAX IRQ number. - * - * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1. - * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1 - * Otherwise, we have the standard IRQs only. - */ -#ifdef CONFIG_SA1111 -#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) -#elif defined(CONFIG_SA1100_H3800) -#define NR_IRQS (IRQ_BOARD_END) -#elif defined(CONFIG_SHARP_LOCOMO) -#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) -#else -#define NR_IRQS (IRQ_BOARD_START) -#endif - -/* - * Board specific IRQs. Define them here. - * Do not surround them with ifdefs. - */ -#define IRQ_NEPONSET_SMC9196 (IRQ_BOARD_START + 0) -#define IRQ_NEPONSET_USAR (IRQ_BOARD_START + 1) -#define IRQ_NEPONSET_SA1111 (IRQ_BOARD_START + 2) - -/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */ -#define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0) -#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) -#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) -#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) - -/* H3800-specific IRQs (CONFIG_SA1100_H3800) */ -#define H3800_KPIO_IRQ_START (IRQ_BOARD_START) -#define IRQ_H3800_KEY (IRQ_BOARD_START + 0) -#define IRQ_H3800_SPI (IRQ_BOARD_START + 1) -#define IRQ_H3800_OWM (IRQ_BOARD_START + 2) -#define IRQ_H3800_ADC (IRQ_BOARD_START + 3) -#define IRQ_H3800_UART_0 (IRQ_BOARD_START + 4) -#define IRQ_H3800_UART_1 (IRQ_BOARD_START + 5) -#define IRQ_H3800_TIMER_0 (IRQ_BOARD_START + 6) -#define IRQ_H3800_TIMER_1 (IRQ_BOARD_START + 7) -#define IRQ_H3800_TIMER_2 (IRQ_BOARD_START + 8) -#define H3800_KPIO_IRQ_COUNT 9 - -#define H3800_GPIO_IRQ_START (IRQ_BOARD_START + 9) -#define IRQ_H3800_PEN (IRQ_BOARD_START + 9) -#define IRQ_H3800_SD_DETECT (IRQ_BOARD_START + 10) -#define IRQ_H3800_EAR_IN (IRQ_BOARD_START + 11) -#define IRQ_H3800_USB_DETECT (IRQ_BOARD_START + 12) -#define IRQ_H3800_SD_CON_SLT (IRQ_BOARD_START + 13) -#define H3800_GPIO_IRQ_COUNT 5 diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h deleted file mode 100644 index 45d2bb5..0000000 --- a/include/asm-arm/arch-sa1100/jornada720.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * include/asm-arm/arch-sa1100/jornada720.h - * - * This file contains SSP/MCU communication definitions for HP Jornada 710/720/728 - * - * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> - * Copyright (C) 2000 John Ankcorn <jca@lcs.mit.edu> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - - /* HP Jornada 7xx microprocessor commands */ -#define GETBATTERYDATA 0xc0 -#define GETSCANKEYCODE 0x90 -#define GETTOUCHSAMPLES 0xa0 -#define GETCONTRAST 0xD0 -#define SETCONTRAST 0xD1 -#define GETBRIGHTNESS 0xD2 -#define SETBRIGHTNESS 0xD3 -#define CONTRASTOFF 0xD8 -#define BRIGHTNESSOFF 0xD9 -#define PWMOFF 0xDF -#define TXDUMMY 0x11 -#define ERRORCODE 0x00 diff --git a/include/asm-arm/arch-sa1100/lart.h b/include/asm-arm/arch-sa1100/lart.h deleted file mode 100644 index 8a5482d..0000000 --- a/include/asm-arm/arch-sa1100/lart.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _INCLUDE_LART_H -#define _INCLUDE_LART_H - -#define LART_GPIO_ETH0 GPIO_GPIO0 -#define LART_IRQ_ETH0 IRQ_GPIO0 - -#define LART_GPIO_IDE GPIO_GPIO1 -#define LART_IRQ_IDE IRQ_GPIO1 - -#define LART_GPIO_UCB1200 GPIO_GPIO18 -#define LART_IRQ_UCB1200 IRQ_GPIO18 - -#endif diff --git a/include/asm-arm/arch-sa1100/mcp.h b/include/asm-arm/arch-sa1100/mcp.h deleted file mode 100644 index f58a227..0000000 --- a/include/asm-arm/arch-sa1100/mcp.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/mcp.h - * - * Copyright (C) 2005 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_ARM_ARCH_MCP_H -#define __ASM_ARM_ARCH_MCP_H - -#include <linux/types.h> - -struct mcp_plat_data { - u32 mccr0; - u32 mccr1; - unsigned int sclk_rate; -}; - -#endif diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h deleted file mode 100644 index 0e907fc..0000000 --- a/include/asm-arm/arch-sa1100/memory.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/memory.h - * - * Copyright (C) 1999-2000 Nicolas Pitre <nico@cam.org> - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#include <asm/sizes.h> - -/* - * Physical DRAM offset is 0xc0000000 on the SA1100 - */ -#define PHYS_OFFSET UL(0xc0000000) - -#ifndef __ASSEMBLY__ - -#ifdef CONFIG_SA1111 -void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes); - -#define arch_adjust_zones(node, size, holes) \ - sa1111_adjust_zones(node, size, holes) - -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1) - -#endif -#endif - -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - * - * On the SA1100, bus addresses are equivalent to physical addresses. - */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - -/* - * Because of the wide memory address space between physical RAM banks on the - * SA1100, it's much convenient to use Linux's NUMA support to implement our - * memory map representation. Assuming all memory nodes have equal access - * characteristics, we then have generic discontiguous memory support. - * - * Of course, all this isn't mandatory for SA1100 implementations with only - * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. - * - * The nodes are matched with the physical memory bank addresses which are - * incidentally the same as virtual addresses. - * - * node 0: 0xc0000000 - 0xc7ffffff - * node 1: 0xc8000000 - 0xcfffffff - * node 2: 0xd0000000 - 0xd7ffffff - * node 3: 0xd8000000 - 0xdfffffff - */ -#define NODE_MEM_SIZE_BITS 27 - -/* - * Cache flushing area - SA1100 zero bank - */ -#define FLUSH_BASE_PHYS 0xe0000000 -#define FLUSH_BASE 0xf5000000 -#define FLUSH_BASE_MINICACHE 0xf5100000 - -#endif diff --git a/include/asm-arm/arch-sa1100/mtd-xip.h b/include/asm-arm/arch-sa1100/mtd-xip.h deleted file mode 100644 index 80cfdac..0000000 --- a/include/asm-arm/arch-sa1100/mtd-xip.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * MTD primitives for XIP support. Architecture specific functions - * - * Do not include this file directly. It's included from linux/mtd/xip.h - * - * Author: Nicolas Pitre - * Created: Nov 2, 2004 - * Copyright: (C) 2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $ - */ - -#ifndef __ARCH_SA1100_MTD_XIP_H__ -#define __ARCH_SA1100_MTD_XIP_H__ - -#define xip_irqpending() (ICIP & ICMR) - -/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */ -#define xip_currtime() (OSCR) -#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4) - -#endif /* __ARCH_SA1100_MTD_XIP_H__ */ diff --git a/include/asm-arm/arch-sa1100/neponset.h b/include/asm-arm/arch-sa1100/neponset.h deleted file mode 100644 index 09ec9e2..0000000 --- a/include/asm-arm/arch-sa1100/neponset.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/neponset.h - * - * Created 2000/06/05 by Nicolas Pitre <nico@cam.org> - * - * This file contains the hardware specific definitions for Assabet - * Only include this file from SA1100-specific files. - * - * 2000/05/23 John Dorsey <john+@cs.cmu.edu> - * Definitions for Neponset added. - */ -#ifndef __ASM_ARCH_NEPONSET_H -#define __ASM_ARCH_NEPONSET_H - -/* - * Neponset definitions: - */ - -#define NEPONSET_CPLD_BASE (0x10000000) -#define Nep_p2v( x ) ((x) - NEPONSET_CPLD_BASE + 0xf3000000) -#define Nep_v2p( x ) ((x) - 0xf3000000 + NEPONSET_CPLD_BASE) - -#define _IRR 0x10000024 /* Interrupt Reason Register */ -#define _AUD_CTL 0x100000c0 /* Audio controls (RW) */ -#define _MDM_CTL_0 0x100000b0 /* Modem control 0 (RW) */ -#define _MDM_CTL_1 0x100000b4 /* Modem control 1 (RW) */ -#define _NCR_0 0x100000a0 /* Control Register (RW) */ -#define _KP_X_OUT 0x10000090 /* Keypad row write (RW) */ -#define _KP_Y_IN 0x10000080 /* Keypad column read (RO) */ -#define _SWPK 0x10000020 /* Switch pack (RO) */ -#define _WHOAMI 0x10000000 /* System ID Register (RO) */ - -#define _LEDS 0x10000010 /* LEDs [31:0] (WO) */ - -#define IRR (*((volatile u_char *) Nep_p2v(_IRR))) -#define AUD_CTL (*((volatile u_char *) Nep_p2v(_AUD_CTL))) -#define MDM_CTL_0 (*((volatile u_char *) Nep_p2v(_MDM_CTL_0))) -#define MDM_CTL_1 (*((volatile u_char *) Nep_p2v(_MDM_CTL_1))) -#define NCR_0 (*((volatile u_char *) Nep_p2v(_NCR_0))) -#define KP_X_OUT (*((volatile u_char *) Nep_p2v(_KP_X_OUT))) -#define KP_Y_IN (*((volatile u_char *) Nep_p2v(_KP_Y_IN))) -#define SWPK (*((volatile u_char *) Nep_p2v(_SWPK))) -#define WHOAMI (*((volatile u_char *) Nep_p2v(_WHOAMI))) - -#define LEDS (*((volatile Word *) Nep_p2v(_LEDS))) - -#define IRR_ETHERNET (1<<0) -#define IRR_USAR (1<<1) -#define IRR_SA1111 (1<<2) - -#define AUD_SEL_1341 (1<<0) -#define AUD_MUTE_1341 (1<<1) - -#define MDM_CTL0_RTS1 (1 << 0) -#define MDM_CTL0_DTR1 (1 << 1) -#define MDM_CTL0_RTS2 (1 << 2) -#define MDM_CTL0_DTR2 (1 << 3) - -#define MDM_CTL1_CTS1 (1 << 0) -#define MDM_CTL1_DSR1 (1 << 1) -#define MDM_CTL1_DCD1 (1 << 2) -#define MDM_CTL1_CTS2 (1 << 3) -#define MDM_CTL1_DSR2 (1 << 4) -#define MDM_CTL1_DCD2 (1 << 5) - -#define NCR_GP01_OFF (1<<0) -#define NCR_TP_PWR_EN (1<<1) -#define NCR_MS_PWR_EN (1<<2) -#define NCR_ENET_OSC_EN (1<<3) -#define NCR_SPI_KB_WK_UP (1<<4) -#define NCR_A0VPP (1<<5) -#define NCR_A1VPP (1<<6) - -#endif diff --git a/include/asm-arm/arch-sa1100/shannon.h b/include/asm-arm/arch-sa1100/shannon.h deleted file mode 100644 index ec27d6e..0000000 --- a/include/asm-arm/arch-sa1100/shannon.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef _INCLUDE_SHANNON_H -#define _INCLUDE_SHANNON_H - -/* taken from comp.os.inferno Tue, 12 Sep 2000 09:21:50 GMT, - * written by <forsyth@vitanuova.com> */ - -#define SHANNON_GPIO_SPI_FLASH GPIO_GPIO (0) /* Output - Driven low, enables SPI to flash */ -#define SHANNON_GPIO_SPI_DSP GPIO_GPIO (1) /* Output - Driven low, enables SPI to DSP */ -/* lcd lower = GPIO 2-9 */ -#define SHANNON_GPIO_SPI_OUTPUT GPIO_GPIO (10) /* Output - SPI output to DSP */ -#define SHANNON_GPIO_SPI_INPUT GPIO_GPIO (11) /* Input - SPI input from DSP */ -#define SHANNON_GPIO_SPI_CLOCK GPIO_GPIO (12) /* Output - Clock for SPI */ -#define SHANNON_GPIO_SPI_FRAME GPIO_GPIO (13) /* Output - Frame marker - not used */ -#define SHANNON_GPIO_SPI_RTS GPIO_GPIO (14) /* Input - SPI Ready to Send */ -#define SHANNON_IRQ_GPIO_SPI_RTS IRQ_GPIO14 -#define SHANNON_GPIO_SPI_CTS GPIO_GPIO (15) /* Output - SPI Clear to Send */ -#define SHANNON_GPIO_IRQ_CODEC GPIO_GPIO (16) /* in, irq from ucb1200 */ -#define SHANNON_IRQ_GPIO_IRQ_CODEC IRQ_GPIO16 -#define SHANNON_GPIO_DSP_RESET GPIO_GPIO (17) /* Output - Drive low to reset the DSP */ -#define SHANNON_GPIO_CODEC_RESET GPIO_GPIO (18) /* Output - Drive low to reset the UCB1x00 */ -#define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */ -#define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */ -#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ -#define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */ -/* XXX GPIO 23 unaccounted for */ -#define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */ -#define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24 -#define SHANNON_GPIO_EJECT_1 GPIO_GPIO (25) /* in */ -#define SHANNON_IRQ_GPIO_EJECT_1 IRQ_GPIO25 -#define SHANNON_GPIO_RDY_0 GPIO_GPIO (26) /* in */ -#define SHANNON_IRQ_GPIO_RDY_0 IRQ_GPIO26 -#define SHANNON_GPIO_RDY_1 GPIO_GPIO (27) /* in */ -#define SHANNON_IRQ_GPIO_RDY_1 IRQ_GPIO27 - -/* MCP UCB codec GPIO pins... */ - -#define SHANNON_UCB_GPIO_BACKLIGHT 9 -#define SHANNON_UCB_GPIO_BRIGHT_MASK 7 -#define SHANNON_UCB_GPIO_BRIGHT 6 -#define SHANNON_UCB_GPIO_CONTRAST_MASK 0x3f -#define SHANNON_UCB_GPIO_CONTRAST 0 - -#endif diff --git a/include/asm-arm/arch-sa1100/simpad.h b/include/asm-arm/arch-sa1100/simpad.h deleted file mode 100644 index 034301d..0000000 --- a/include/asm-arm/arch-sa1100/simpad.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/simpad.h - * - * based of assabet.h same as HUW_Webpanel - * - * This file contains the hardware specific definitions for SIMpad - * - * 2001/05/14 Juergen Messerer <juergen.messerer@freesurf.ch> - */ - -#ifndef __ASM_ARCH_SIMPAD_H -#define __ASM_ARCH_SIMPAD_H - - -#define GPIO_UART1_RTS GPIO_GPIO14 -#define GPIO_UART1_DTR GPIO_GPIO7 -#define GPIO_UART1_CTS GPIO_GPIO8 -#define GPIO_UART1_DCD GPIO_GPIO23 -#define GPIO_UART1_DSR GPIO_GPIO6 - -#define GPIO_UART3_RTS GPIO_GPIO12 -#define GPIO_UART3_DTR GPIO_GPIO16 -#define GPIO_UART3_CTS GPIO_GPIO13 -#define GPIO_UART3_DCD GPIO_GPIO18 -#define GPIO_UART3_DSR GPIO_GPIO17 - -#define GPIO_POWER_BUTTON GPIO_GPIO0 -#define GPIO_UCB1300_IRQ GPIO_GPIO22 /* UCB GPIO and touchscreen */ - -#define IRQ_UART1_CTS IRQ_GPIO15 -#define IRQ_UART1_DCD GPIO_GPIO23 -#define IRQ_UART1_DSR GPIO_GPIO6 -#define IRQ_UART3_CTS GPIO_GPIO13 -#define IRQ_UART3_DCD GPIO_GPIO18 -#define IRQ_UART3_DSR GPIO_GPIO17 - -#define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO22 -#define IRQ_GPIO_POWER_BUTTON IRQ_GPIO0 - - -/*--- PCMCIA ---*/ -#define GPIO_CF_CD GPIO_GPIO24 -#define GPIO_CF_IRQ GPIO_GPIO1 -#define IRQ_GPIO_CF_IRQ IRQ_GPIO1 -#define IRQ_GPIO_CF_CD IRQ_GPIO24 - -/*--- SmartCard ---*/ -#define GPIO_SMART_CARD GPIO_GPIO10 -#define IRQ_GPIO_SMARD_CARD IRQ_GPIO10 - -// CS3 Latch is write only, a shadow is necessary - -#define CS3BUSTYPE unsigned volatile long -#define CS3_BASE 0xf1000000 - -#define VCC_5V_EN 0x0001 // For 5V PCMCIA -#define VCC_3V_EN 0x0002 // FOR 3.3V PCMCIA -#define EN1 0x0004 // This is only for EPROM's -#define EN0 0x0008 // Both should be enable for 3.3V or 5V -#define DISPLAY_ON 0x0010 -#define PCMCIA_BUFF_DIS 0x0020 -#define MQ_RESET 0x0040 -#define PCMCIA_RESET 0x0080 -#define DECT_POWER_ON 0x0100 -#define IRDA_SD 0x0200 // Shutdown for powersave -#define RS232_ON 0x0400 -#define SD_MEDIAQ 0x0800 // Shutdown for powersave -#define LED2_ON 0x1000 -#define IRDA_MODE 0x2000 // Fast/Slow IrDA mode -#define ENABLE_5V 0x4000 // Enable 5V circuit -#define RESET_SIMCARD 0x8000 - -#define RS232_ENABLE 0x0440 -#define PCMCIAMASK 0x402f - - -struct simpad_battery { - unsigned char ac_status; /* line connected yes/no */ - unsigned char status; /* battery loading yes/no */ - unsigned char percentage; /* percentage loaded */ - unsigned short life; /* life till empty */ -}; - -/* These should match the apm_bios.h definitions */ -#define SIMPAD_AC_STATUS_AC_OFFLINE 0x00 -#define SIMPAD_AC_STATUS_AC_ONLINE 0x01 -#define SIMPAD_AC_STATUS_AC_BACKUP 0x02 /* What does this mean? */ -#define SIMPAD_AC_STATUS_AC_UNKNOWN 0xff - -/* These bitfields are rarely "or'd" together */ -#define SIMPAD_BATT_STATUS_HIGH 0x01 -#define SIMPAD_BATT_STATUS_LOW 0x02 -#define SIMPAD_BATT_STATUS_CRITICAL 0x04 -#define SIMPAD_BATT_STATUS_CHARGING 0x08 -#define SIMPAD_BATT_STATUS_CHARGE_MAIN 0x10 -#define SIMPAD_BATT_STATUS_DEAD 0x20 /* Battery will not charge */ -#define SIMPAD_BATT_NOT_INSTALLED 0x20 /* For expansion pack batteries */ -#define SIMPAD_BATT_STATUS_FULL 0x40 /* Battery fully charged (and connected to AC) */ -#define SIMPAD_BATT_STATUS_NOBATT 0x80 -#define SIMPAD_BATT_STATUS_UNKNOWN 0xff - -extern int simpad_get_battery(struct simpad_battery* ); - -#endif // __ASM_ARCH_SIMPAD_H - - - - - - - - diff --git a/include/asm-arm/arch-sa1100/system.h b/include/asm-arm/arch-sa1100/system.h deleted file mode 100644 index aef91e3..0000000 --- a/include/asm-arm/arch-sa1100/system.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/system.h - * - * Copyright (c) 1999 Nicolas Pitre <nico@cam.org> - */ -#include <asm/hardware.h> - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void arch_reset(char mode) -{ - if (mode == 's') { - /* Jump into ROM at address 0 */ - cpu_reset(0); - } else { - /* Use on-chip reset capability */ - RSRR = RSRR_SWR; - } -} diff --git a/include/asm-arm/arch-sa1100/timex.h b/include/asm-arm/arch-sa1100/timex.h deleted file mode 100644 index 837be9b..0000000 --- a/include/asm-arm/arch-sa1100/timex.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/timex.h - * - * SA1100 architecture timex specifications - * - * Copyright (C) 1998 - */ - -/* - * SA1100 timer - */ -#define CLOCK_TICK_RATE 3686400 diff --git a/include/asm-arm/arch-sa1100/uncompress.h b/include/asm-arm/arch-sa1100/uncompress.h deleted file mode 100644 index 17e64d2..0000000 --- a/include/asm-arm/arch-sa1100/uncompress.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/uncompress.h - * - * (C) 1999 Nicolas Pitre <nico@cam.org> - * - * Reorganised to be machine independent. - */ - -#include "hardware.h" - -/* - * The following code assumes the serial port has already been - * initialized by the bootloader. We search for the first enabled - * port in the most probable order. If you didn't setup a port in - * your bootloader then nothing will appear (which might be desired). - */ - -#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) - -static void putc(int c) -{ - unsigned long serial_port; - - do { - serial_port = _Ser3UTCR0; - if (UART(UTCR3) & UTCR3_TXE) break; - serial_port = _Ser1UTCR0; - if (UART(UTCR3) & UTCR3_TXE) break; - serial_port = _Ser2UTCR0; - if (UART(UTCR3) & UTCR3_TXE) break; - return; - } while (0); - - /* wait for space in the UART's transmitter */ - while (!(UART(UTSR1) & UTSR1_TNF)) - barrier(); - - /* send the character out. */ - UART(UTDR) = c; -} - -static inline void flush(void) -{ -} - -/* - * Nothing to do for these - */ -#define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-sa1100/vmalloc.h b/include/asm-arm/arch-sa1100/vmalloc.h deleted file mode 100644 index 2fb1c6f..0000000 --- a/include/asm-arm/arch-sa1100/vmalloc.h +++ /dev/null @@ -1,4 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/vmalloc.h - */ -#define VMALLOC_END (0xe8000000) |
