diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/Makefile | 1 | ||||
| -rw-r--r-- | drivers/clk/clk-prima2.c | 1171 | ||||
| -rw-r--r-- | drivers/i2c/busses/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/i2c/busses/i2c-iop3xx.c | 121 | ||||
| -rw-r--r-- | drivers/mtd/nand/bcm_umi_nand.c | 12 | ||||
| -rw-r--r-- | drivers/mtd/nand/nand_bcm_umi.h | 73 | ||||
| -rw-r--r-- | drivers/pinctrl/pinctrl-coh901.c | 220 | ||||
| -rw-r--r-- | drivers/usb/Kconfig | 1 | ||||
| -rw-r--r-- | drivers/usb/host/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/usb/host/ohci-hcd.c | 2 | ||||
| -rw-r--r-- | drivers/usb/host/ohci-nxp.c | 84 | ||||
| -rw-r--r-- | drivers/watchdog/Kconfig | 6 |
12 files changed, 1325 insertions, 370 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 5869ea3..d4c7253 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_U300) += clk-u300.o obj-$(CONFIG_ARCH_INTEGRATOR) += versatile/ +obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o # Chip specific obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o diff --git a/drivers/clk/clk-prima2.c b/drivers/clk/clk-prima2.c new file mode 100644 index 0000000..517874f --- /dev/null +++ b/drivers/clk/clk-prima2.c @@ -0,0 +1,1171 @@ +/* + * Clock tree for CSR SiRFprimaII + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/module.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/syscore_ops.h> + +#define SIRFSOC_CLKC_CLK_EN0 0x0000 +#define SIRFSOC_CLKC_CLK_EN1 0x0004 +#define SIRFSOC_CLKC_REF_CFG 0x0014 +#define SIRFSOC_CLKC_CPU_CFG 0x0018 +#define SIRFSOC_CLKC_MEM_CFG 0x001c +#define SIRFSOC_CLKC_SYS_CFG 0x0020 +#define SIRFSOC_CLKC_IO_CFG 0x0024 +#define SIRFSOC_CLKC_DSP_CFG 0x0028 +#define SIRFSOC_CLKC_GFX_CFG 0x002c +#define SIRFSOC_CLKC_MM_CFG 0x0030 +#define SIRFSOC_CLKC_LCD_CFG 0x0034 +#define SIRFSOC_CLKC_MMC_CFG 0x0038 +#define SIRFSOC_CLKC_PLL1_CFG0 0x0040 +#define SIRFSOC_CLKC_PLL2_CFG0 0x0044 +#define SIRFSOC_CLKC_PLL3_CFG0 0x0048 +#define SIRFSOC_CLKC_PLL1_CFG1 0x004c +#define SIRFSOC_CLKC_PLL2_CFG1 0x0050 +#define SIRFSOC_CLKC_PLL3_CFG1 0x0054 +#define SIRFSOC_CLKC_PLL1_CFG2 0x0058 +#define SIRFSOC_CLKC_PLL2_CFG2 0x005c +#define SIRFSOC_CLKC_PLL3_CFG2 0x0060 +#define SIRFSOC_USBPHY_PLL_CTRL 0x0008 +#define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1) +#define SIRFSOC_USBPHY_PLL_BYPASS BIT(2) +#define SIRFSOC_USBPHY_PLL_LOCK BIT(3) + +static void *sirfsoc_clk_vbase, *sirfsoc_rsc_vbase; + +#define KHZ 1000 +#define MHZ (KHZ * KHZ) + +/* + * SiRFprimaII clock controller + * - 2 oscillators: osc-26MHz, rtc-32.768KHz + * - 3 standard configurable plls: pll1, pll2 & pll3 + * - 2 exclusive plls: usb phy pll and sata phy pll + * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia, + * display and sdphy. + * Each clock domain can select its own clock source from five clock sources, + * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source + * clock of the group clock. + * - dsp domain: gps, mf + * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse + * - sys domain: security + */ + +struct clk_pll { + struct clk_hw hw; + unsigned short regofs; /* register offset */ +}; + +#define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw) + +struct clk_dmn { + struct clk_hw hw; + signed char enable_bit; /* enable bit: 0 ~ 63 */ + unsigned short regofs; /* register offset */ +}; + +#define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw) + +struct clk_std { + struct clk_hw hw; + signed char enable_bit; /* enable bit: 0 ~ 63 */ +}; + +#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw) + +static int std_clk_is_enabled(struct clk_hw *hw); +static int std_clk_enable(struct clk_hw *hw); +static void std_clk_disable(struct clk_hw *hw); + +static inline unsigned long clkc_readl(unsigned reg) +{ + return readl(sirfsoc_clk_vbase + reg); +} + +static inline void clkc_writel(u32 val, unsigned reg) +{ + writel(val, sirfsoc_clk_vbase + reg); +} + +/* + * std pll + */ + +static unsigned long pll_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long fin = parent_rate; + struct clk_pll *clk = to_pllclk(hw); + u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - + SIRFSOC_CLKC_PLL1_CFG0; + + if (clkc_readl(regcfg2) & BIT(2)) { + /* pll bypass mode */ + return fin; + } else { + /* fout = fin * nf / nr / od */ + u32 cfg0 = clkc_readl(clk->regofs); + u32 nf = (cfg0 & (BIT(13) - 1)) + 1; + u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; + u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; + WARN_ON(fin % MHZ); + return fin / MHZ * nf / nr / od * MHZ; + } +} + +static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + unsigned long fin, nf, nr, od; + + /* + * fout = fin * nf / (nr * od); + * set od = 1, nr = fin/MHz, so fout = nf * MHz + */ + rate = rate - rate % MHZ; + + nf = rate / MHZ; + if (nf > BIT(13)) + nf = BIT(13); + if (nf < 1) + nf = 1; + + fin = *parent_rate; + + nr = fin / MHZ; + if (nr > BIT(6)) + nr = BIT(6); + od = 1; + + return fin * nf / (nr * od); +} + +static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pll *clk = to_pllclk(hw); + unsigned long fin, nf, nr, od, reg; + + /* + * fout = fin * nf / (nr * od); + * set od = 1, nr = fin/MHz, so fout = nf * MHz + */ + + nf = rate / MHZ; + if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) + return -EINVAL; + + fin = parent_rate; + BUG_ON(fin < MHZ); + + nr = fin / MHZ; + BUG_ON((fin % MHZ) || nr > BIT(6)); + + od = 1; + + reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19); + clkc_writel(reg, clk->regofs); + + reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; + clkc_writel((nf >> 1) - 1, reg); + + reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; + while (!(clkc_readl(reg) & BIT(6))) + cpu_relax(); + + return 0; +} + +static struct clk_ops std_pll_ops = { + .recalc_rate = pll_clk_recalc_rate, + .round_rate = pll_clk_round_rate, + .set_rate = pll_clk_set_rate, +}; + +static const char *pll_clk_parents[] = { + "osc", +}; + +static struct clk_init_data clk_pll1_init = { + .name = "pll1", + .ops = &std_pll_ops, + .parent_names = pll_clk_parents, + .num_parents = ARRAY_SIZE(pll_clk_parents), +}; + +static struct clk_init_data clk_pll2_init = { + .name = "pll2", + .ops = &std_pll_ops, + .parent_names = pll_clk_parents, + .num_parents = ARRAY_SIZE(pll_clk_parents), +}; + +static struct clk_init_data clk_pll3_init = { + .name = "pll3", + .ops = &std_pll_ops, + .parent_names = pll_clk_parents, + .num_parents = ARRAY_SIZE(pll_clk_parents), +}; + +static struct clk_pll clk_pll1 = { + .regofs = SIRFSOC_CLKC_PLL1_CFG0, + .hw = { + .init = &clk_pll1_init, + }, +}; + +static struct clk_pll clk_pll2 = { + .regofs = SIRFSOC_CLKC_PLL2_CFG0, + .hw = { + .init = &clk_pll2_init, + }, +}; + +static struct clk_pll clk_pll3 = { + .regofs = SIRFSOC_CLKC_PLL3_CFG0, + .hw = { + .init = &clk_pll3_init, + }, +}; + +/* + * usb uses specified pll + */ + +static int usb_pll_clk_enable(struct clk_hw *hw) +{ + u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); + reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); + writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); + while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) & + SIRFSOC_USBPHY_PLL_LOCK)) + cpu_relax(); + + return 0; +} + +static void usb_pll_clk_disable(struct clk_hw *clk) +{ + u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); + reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); + writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); +} + +static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); + return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ; +} + +static struct clk_ops usb_pll_ops = { + .enable = usb_pll_clk_enable, + .disable = usb_pll_clk_disable, + .recalc_rate = usb_pll_clk_recalc_rate, +}; + +static struct clk_init_data clk_usb_pll_init = { + .name = "usb_pll", + .ops = &usb_pll_ops, + .parent_names = pll_clk_parents, + .num_parents = ARRAY_SIZE(pll_clk_parents), +}; + +static struct clk_hw usb_pll_clk_hw = { + .init = &clk_usb_pll_init, +}; + +/* + * clock domains - cpu, mem, sys/io, dsp, gfx + */ + +static const char *dmn_clk_parents[] = { + "rtc", + "osc", + "pll1", + "pll2", + "pll3", +}; + +static u8 dmn_clk_get_parent(struct clk_hw *hw) +{ + struct clk_dmn *clk = to_dmnclk(hw); + u32 cfg = clkc_readl(clk->regofs); + + /* parent of io domain can only be pll3 */ + if (strcmp(hw->init->name, "io") == 0) + return 4; + + WARN_ON((cfg & (BIT(3) - 1)) > 4); + + return cfg & (BIT(3) - 1); +} + +static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent) +{ + struct clk_dmn *clk = to_dmnclk(hw); + u32 cfg = clkc_readl(clk->regofs); + + /* parent of io domain can only be pll3 */ + if (strcmp(hw->init->name, "io") == 0) + return -EINVAL; + + cfg &= ~(BIT(3) - 1); + clkc_writel(cfg | parent, clk->regofs); + /* BIT(3) - switching status: 1 - busy, 0 - done */ + while (clkc_readl(clk->regofs) & BIT(3)) + cpu_relax(); + + return 0; +} + +static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) + +{ + unsigned long fin = parent_rate; + struct clk_dmn *clk = to_dmnclk(hw); + + u32 cfg = clkc_readl(clk->regofs); + + if (cfg & BIT(24)) { + /* fcd bypass mode */ + return fin; + } else { + /* + * wait count: bit[19:16], hold count: bit[23:20] + */ + u32 wait = (cfg >> 16) & (BIT(4) - 1); + u32 hold = (cfg >> 20) & (BIT(4) - 1); + + return fin / (wait + hold + 2); + } +} + +static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + unsigned long fin; + unsigned ratio, wait, hold; + unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4; + + fin = *parent_rate; + ratio = fin / rate; + + if (ratio < 2) + ratio = 2; + if (ratio > BIT(bits + 1)) + ratio = BIT(bits + 1); + + wait = (ratio >> 1) - 1; + hold = ratio - wait - 2; + + return fin / (wait + hold + 2); +} + +static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_dmn *clk = to_dmnclk(hw); + unsigned long fin; + unsigned ratio, wait, hold, reg; + unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4; + + fin = parent_rate; + ratio = fin / rate; + + if (unlikely(ratio < 2 || ratio > BIT(bits + 1))) + return -EINVAL; + + WARN_ON(fin % rate); + + wait = (ratio >> 1) - 1; + hold = ratio - wait - 2; + + reg = clkc_readl(clk->regofs); + reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20)); + reg |= (wait << 16) | (hold << 20) | BIT(25); + clkc_writel(reg, clk->regofs); + + /* waiting FCD been effective */ + while (clkc_readl(clk->regofs) & BIT(25)) + cpu_relax(); + + return 0; +} + +static struct clk_ops msi_ops = { + .set_rate = dmn_clk_set_rate, + .round_rate = dmn_clk_round_rate, + .recalc_rate = dmn_clk_recalc_rate, + .set_parent = dmn_clk_set_parent, + .get_parent = dmn_clk_get_parent, +}; + +static struct clk_init_data clk_mem_init = { + .name = "mem", + .ops = &msi_ops, + .parent_names = dmn_clk_parents, + .num_parents = ARRAY_SIZE(dmn_clk_parents), +}; + +static struct clk_dmn clk_mem = { + .regofs = SIRFSOC_CLKC_MEM_CFG, + .hw = { + .init = &clk_mem_init, + }, +}; + +static struct clk_init_data clk_sys_init = { + .name = "sys", + .ops = &msi_ops, + .parent_names = dmn_clk_parents, + .num_parents = ARRAY_SIZE(dmn_clk_parents), + .flags = CLK_SET_RATE_GATE, +}; + +static struct clk_dmn clk_sys = { + .regofs = SIRFSOC_CLKC_SYS_CFG, + .hw = { + .init = &clk_sys_init, + }, +}; + +static struct clk_init_data clk_io_init = { + .name = "io", + .ops = &msi_ops, + .parent_names = dmn_clk_parents, + .num_parents = ARRAY_SIZE(dmn_clk_parents), +}; + +static struct clk_dmn clk_io = { + .regofs = SIRFSOC_CLKC_IO_CFG, + .hw = { + .init = &clk_io_init, + }, +}; + +static struct clk_ops cpu_ops = { + .set_parent = dmn_clk_set_parent, + .get_parent = dmn_clk_get_parent, +}; + +static struct clk_init_data clk_cpu_init = { + .name = "cpu", + .ops = &cpu_ops, + .parent_names = dmn_clk_parents, + .num_parents = ARRAY_SIZE(dmn_clk_parents), + .flags = CLK_SET_RATE_PARENT, +}; + +static struct clk_dmn clk_cpu = { + .regofs = SIRFSOC_CLKC_CPU_CFG, + .hw = { + .init = &clk_cpu_init, + }, +}; + +static struct clk_ops dmn_ops = { + .is_enabled = std_clk_is_enabled, + .enable = std_clk_enable, + .disable = std_clk_disable, + .set_rate = dmn_clk_set_rate, + .round_rate = dmn_clk_round_rate, + .recalc_rate = dmn_clk_recalc_rate, + .set_parent = dmn_clk_set_parent, + .get_parent = dmn_clk_get_parent, +}; + +/* dsp, gfx, mm, lcd and vpp domain */ + +static struct clk_init_data clk_dsp_init = { + .name = "dsp", + .ops = &dmn_ops, + .parent_names = dmn_clk_parents, + .num_parents = ARRAY_SIZE(dmn_clk_parents), +}; + +static struct clk_dmn clk_dsp = { + .regofs = SIRFSOC_CLKC_DSP_CFG, + .enable_bit = 0, + .hw = { + .init = &clk_dsp_init, + }, +}; + +static struct clk_init_data clk_gfx_init = { + .name = "gfx", + .ops = &dmn_ops, + .parent_names = dmn_clk_parents, + .num_parents = ARRAY_SIZE(dmn_clk_parents), +}; + +static struct clk_dmn clk_gfx = { + .regofs = SIRFSOC_CLKC_GFX_CFG, + .enable_bit = 8, + .hw = { + .init = &clk_gfx_init, + }, +}; + +static struct clk_init_data clk_mm_init = { + .name = "mm", + .ops = &dmn_ops, + .parent_names = dmn_clk_parents, + .num_parents = ARRAY_SIZE(dmn_clk_parents), +}; + +static struct clk_dmn clk_mm = { + .regofs = SIRFSOC_CLKC_MM_CFG, + .enable_bit = 9, + .hw = { + .init = &clk_mm_init, + }, +}; + +static struct clk_init_data clk_lcd_init = { + .name = "lcd", + .ops = &dmn_ops, + .parent_names = dmn_clk_parents, + .num_parents = ARRAY_SIZE(dmn_clk_parents), +}; + +static struct clk_dmn clk_lcd = { + .regofs = SIRFSOC_CLKC_LCD_CFG, + .enable_bit = 10, + .hw = { + .init = &clk_lcd_init, + }, +}; + +static struct clk_init_data clk_vpp_init = { + .name = "vpp", + .ops = &dmn_ops, + .parent_names = dmn_clk_parents, + .num_parents = ARRAY_SIZE(dmn_clk_parents), +}; + +static struct clk_dmn clk_vpp = { + .regofs = SIRFSOC_CLKC_LCD_CFG, + .enable_bit = 11, + .hw = { + .init = &clk_vpp_init, + }, +}; + +static struct clk_init_data clk_mmc01_init = { + .name = "mmc01", + .ops = &dmn_ops, + .parent_names = dmn_clk_parents, + .num_parents = ARRAY_SIZE(dmn_clk_parents), +}; + +static struct clk_dmn clk_mmc01 = { + .regofs = SIRFSOC_CLKC_MMC_CFG, + .enable_bit = 59, + .hw = { + .init = &clk_mmc01_init, + }, +}; + +static struct clk_init_data clk_mmc23_init = { + .name = "mmc23", + .ops = &dmn_ops, + .parent_names = dmn_clk_parents, + .num_parents = ARRAY_SIZE(dmn_clk_parents), +}; + +static struct clk_dmn clk_mmc23 = { + .regofs = SIRFSOC_CLKC_MMC_CFG, + .enable_bit = 60, + .hw = { + .init = &clk_mmc23_init, + }, +}; + +static struct clk_init_data clk_mmc45_init = { + .name = "mmc45", + .ops = &dmn_ops, + .parent_names = dmn_clk_parents, + .num_parents = ARRAY_SIZE(dmn_clk_parents), +}; + +static struct clk_dmn clk_mmc45 = { + .regofs = SIRFSOC_CLKC_MMC_CFG, + .enable_bit = 61, + .hw = { + .init = &clk_mmc45_init, + }, +}; + +/* + * peripheral controllers in io domain + */ + +static int std_clk_is_enabled(struct clk_hw *hw) +{ + u32 reg; + int bit; + struct clk_std *clk = to_stdclk(hw); + + bit = clk->enable_bit % 32; + reg = clk->enable_bit / 32; + reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); + + return !!(clkc_readl(reg) & BIT(bit)); +} + +static int std_clk_enable(struct clk_hw *hw) +{ + u32 val, reg; + int bit; + struct clk_std *clk = to_stdclk(hw); + + BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); + + bit = clk->enable_bit % 32; + reg = clk->enable_bit / 32; + reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); + + val = clkc_readl(reg) | BIT(bit); + clkc_writel(val, reg); + return 0; +} + +static void std_clk_disable(struct clk_hw *hw) +{ + u32 val, reg; + int bit; + struct clk_std *clk = to_stdclk(hw); + + BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); + + bit = clk->enable_bit % 32; + reg = clk->enable_bit / 32; + reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); + + val = clkc_readl(reg) & ~BIT(bit); + clkc_writel(val, reg); +} + +static const char *std_clk_io_parents[] = { + "io", +}; + +static struct clk_ops ios_ops = { + .is_enabled = std_clk_is_enabled, + .enable = std_clk_enable, + .disable = std_clk_disable, +}; + +static struct clk_init_data clk_dmac0_init = { + .name = "dmac0", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_dmac0 = { + .enable_bit = 32, + .hw = { + .init = &clk_dmac0_init, + }, +}; + +static struct clk_init_data clk_dmac1_init = { + .name = "dmac1", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_dmac1 = { + .enable_bit = 33, + .hw = { + .init = &clk_dmac1_init, + }, +}; + +static struct clk_init_data clk_nand_init = { + .name = "nand", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_nand = { + .enable_bit = 34, + .hw = { + .init = &clk_nand_init, + }, +}; + +static struct clk_init_data clk_audio_init = { + .name = "audio", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_audio = { + .enable_bit = 35, + .hw = { + .init = &clk_audio_init, + }, +}; + +static struct clk_init_data clk_uart0_init = { + .name = "uart0", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_uart0 = { + .enable_bit = 36, + .hw = { + .init = &clk_uart0_init, + }, +}; + +static struct clk_init_data clk_uart1_init = { + .name = "uart1", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_uart1 = { + .enable_bit = 37, + .hw = { + .init = &clk_uart1_init, + }, +}; + +static struct clk_init_data clk_uart2_init = { + .name = "uart2", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_uart2 = { + .enable_bit = 38, + .hw = { + .init = &clk_uart2_init, + }, +}; + +static struct clk_init_data clk_usp0_init = { + .name = "usp0", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_usp0 = { + .enable_bit = 39, + .hw = { + .init = &clk_usp0_init, + }, +}; + +static struct clk_init_data clk_usp1_init = { + .name = "usp1", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_usp1 = { + .enable_bit = 40, + .hw = { + .init = &clk_usp1_init, + }, +}; + +static struct clk_init_data clk_usp2_init = { + .name = "usp2", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_usp2 = { + .enable_bit = 41, + .hw = { + .init = &clk_usp2_init, + }, +}; + +static struct clk_init_data clk_vip_init = { + .name = "vip", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_vip = { + .enable_bit = 42, + .hw = { + .init = &clk_vip_init, + }, +}; + +static struct clk_init_data clk_spi0_init = { + .name = "spi0", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_spi0 = { + .enable_bit = 43, + .hw = { + .init = &clk_spi0_init, + }, +}; + +static struct clk_init_data clk_spi1_init = { + .name = "spi1", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_spi1 = { + .enable_bit = 44, + .hw = { + .init = &clk_spi1_init, + }, +}; + +static struct clk_init_data clk_tsc_init = { + .name = "tsc", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_tsc = { + .enable_bit = 45, + .hw = { + .init = &clk_tsc_init, + }, +}; + +static struct clk_init_data clk_i2c0_init = { + .name = "i2c0", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_i2c0 = { + .enable_bit = 46, + .hw = { + .init = &clk_i2c0_init, + }, +}; + +static struct clk_init_data clk_i2c1_init = { + .name = "i2c1", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_i2c1 = { + .enable_bit = 47, + .hw = { + .init = &clk_i2c1_init, + }, +}; + +static struct clk_init_data clk_pwmc_init = { + .name = "pwmc", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_pwmc = { + .enable_bit = 48, + .hw = { + .init = &clk_pwmc_init, + }, +}; + +static struct clk_init_data clk_efuse_init = { + .name = "efuse", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_efuse = { + .enable_bit = 49, + .hw = { + .init = &clk_efuse_init, + }, +}; + +static struct clk_init_data clk_pulse_init = { + .name = "pulse", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_pulse = { + .enable_bit = 50, + .hw = { + .init = &clk_pulse_init, + }, +}; + +static const char *std_clk_dsp_parents[] = { + "dsp", +}; + +static struct clk_init_data clk_gps_init = { + .name = "gps", + .ops = &ios_ops, + .parent_names = std_clk_dsp_parents, + .num_parents = ARRAY_SIZE(std_clk_dsp_parents), +}; + +static struct clk_std clk_gps = { + .enable_bit = 1, + .hw = { + .init = &clk_gps_init, + }, +}; + +static struct clk_init_data clk_mf_init = { + .name = "mf", + .ops = &ios_ops, + .parent_names = std_clk_io_parents, + .num_parents = ARRAY_SIZE(std_clk_io_parents), +}; + +static struct clk_std clk_mf = { + .enable_bit = 2, + .hw = { + .init = &clk_mf_init, + }, +}; + +static const char *std_clk_sys_parents[] = { + "sys", +}; + +static struct clk_init_data clk_security_init = { + .name = "mf", + .ops = &ios_ops, + .parent_names = std_clk_sys_parents, + .num_parents = ARRAY_SIZE(std_clk_sys_parents), +}; + +static struct clk_std clk_security = { + .enable_bit = 19, + .hw = { + .init = &clk_security_init, + }, +}; + +static const char *std_clk_usb_parents[] = { + "usb_pll", +}; + +static struct clk_init_data clk_usb0_init = { + .name = "usb0", + .ops = &ios_ops, + .parent_names = std_clk_usb_parents, + .num_parents = ARRAY_SIZE(std_clk_usb_parents), +}; + +static struct clk_std clk_usb0 = { + .enable_bit = 16, + .hw = { + .init = &clk_usb0_init, + }, +}; + +static struct clk_init_data clk_usb1_init = { + .name = "usb1", + .ops = &ios_ops, + .parent_names = std_clk_usb_parents, + .num_parents = ARRAY_SIZE(std_clk_usb_parents), +}; + +static struct clk_std clk_usb1 = { + .enable_bit = 17, + .hw = { + .init = &clk_usb1_init, + }, +}; + +static struct of_device_id clkc_ids[] = { + { .compatible = "sirf,prima2-clkc" }, + {}, +}; + +static struct of_device_id rsc_ids[] = { + { .compatible = "sirf,prima2-rsc" }, + {}, +}; + +void __init sirfsoc_of_clk_init(void) +{ + struct clk *clk; + struct device_node *np; + + np = of_find_matching_node(NULL, clkc_ids); + if (!np) + panic("unable to find compatible clkc node in dtb\n"); + + sirfsoc_clk_vbase = of_iomap(np, 0); + if (!sirfsoc_clk_vbase) + panic("unable to map clkc registers\n"); + + of_node_put(np); + + np = of_find_matching_node(NULL, rsc_ids); + if (!np) + panic("unable to find compatible rsc node in dtb\n"); + + sirfsoc_rsc_vbase = of_iomap(np, 0); + if (!sirfsoc_rsc_vbase) + panic("unable to map rsc registers\n"); + + of_node_put(np); + + + /* These are always available (RTC and 26MHz OSC)*/ + clk = clk_register_fixed_rate(NULL, "rtc", NULL, + CLK_IS_ROOT, 32768); + BUG_ON(!clk); + clk = clk_register_fixed_rate(NULL, "osc", NULL, + CLK_IS_ROOT, 26000000); + BUG_ON(!clk); + + clk = clk_register(NULL, &clk_pll1.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_pll2.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_pll3.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_mem.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_sys.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_security.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b8030000.security"); + clk = clk_register(NULL, &clk_dsp.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_gps.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "a8010000.gps"); + clk = clk_register(NULL, &clk_mf.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_io.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "io"); + clk = clk_register(NULL, &clk_cpu.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "cpu"); + clk = clk_register(NULL, &clk_uart0.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b0050000.uart"); + clk = clk_register(NULL, &clk_uart1.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b0060000.uart"); + clk = clk_register(NULL, &clk_uart2.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b0070000.uart"); + clk = clk_register(NULL, &clk_tsc.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b0110000.tsc"); + clk = clk_register(NULL, &clk_i2c0.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b00e0000.i2c"); + clk = clk_register(NULL, &clk_i2c1.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b00f0000.i2c"); + clk = clk_register(NULL, &clk_spi0.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b00d0000.spi"); + clk = clk_register(NULL, &clk_spi1.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b0170000.spi"); + clk = clk_register(NULL, &clk_pwmc.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b0130000.pwm"); + clk = clk_register(NULL, &clk_efuse.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b0140000.efusesys"); + clk = clk_register(NULL, &clk_pulse.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b0150000.pulsec"); + clk = clk_register(NULL, &clk_dmac0.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b00b0000.dma-controller"); + clk = clk_register(NULL, &clk_dmac1.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b0160000.dma-controller"); + clk = clk_register(NULL, &clk_nand.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b0030000.nand"); + clk = clk_register(NULL, &clk_audio.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b0040000.audio"); + clk = clk_register(NULL, &clk_usp0.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b0080000.usp"); + clk = clk_register(NULL, &clk_usp1.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b0090000.usp"); + clk = clk_register(NULL, &clk_usp2.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b00a0000.usp"); + clk = clk_register(NULL, &clk_vip.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b00c0000.vip"); + clk = clk_register(NULL, &clk_gfx.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "98000000.graphics"); + clk = clk_register(NULL, &clk_mm.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "a0000000.multimedia"); + clk = clk_register(NULL, &clk_lcd.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "90010000.display"); + clk = clk_register(NULL, &clk_vpp.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "90020000.vpp"); + clk = clk_register(NULL, &clk_mmc01.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_mmc23.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_mmc45.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &usb_pll_clk_hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_usb0.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b00e0000.usb"); + clk = clk_register(NULL, &clk_usb1.hw); + BUG_ON(!clk); + clk_register_clkdev(clk, NULL, "b00f0000.usb"); +} diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index b4aaa1b..2025adf 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -545,7 +545,7 @@ config I2C_PMCMSP config I2C_PNX tristate "I2C bus support for Philips PNX and NXP LPC targets" - depends on ARCH_PNX4008 || ARCH_LPC32XX + depends on ARCH_LPC32XX help This driver supports the Philips IP3204 I2C IP block master and/or slave controller diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c index 93f147a..2f99613 100644 --- a/drivers/i2c/busses/i2c-iop3xx.c +++ b/drivers/i2c/busses/i2c-iop3xx.c @@ -4,13 +4,13 @@ /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd * <Peter dot Milne at D hyphen TACQ dot com> * - * With acknowledgements to i2c-algo-ibm_ocp.c by + * With acknowledgements to i2c-algo-ibm_ocp.c by * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com * * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund: * * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund - * + * * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>, * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com> * @@ -39,14 +39,15 @@ #include <linux/platform_device.h> #include <linux/i2c.h> #include <linux/io.h> +#include <linux/gpio.h> #include "i2c-iop3xx.h" /* global unit counter */ static int i2c_id; -static inline unsigned char -iic_cook_addr(struct i2c_msg *msg) +static inline unsigned char +iic_cook_addr(struct i2c_msg *msg) { unsigned char addr; @@ -55,38 +56,38 @@ iic_cook_addr(struct i2c_msg *msg) if (msg->flags & I2C_M_RD) addr |= 1; - return addr; + return addr; } -static void +static void iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap) { /* Follows devman 9.3 */ __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET); __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET); __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET); -} +} -static void +static void iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap) { u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE; - /* + /* * Every time unit enable is asserted, GPOD needs to be cleared * on IOP3XX to avoid data corruption on the bus. */ #if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X) if (iop3xx_adap->id == 0) { - gpio_line_set(IOP3XX_GPIO_LINE(7), GPIO_LOW); - gpio_line_set(IOP3XX_GPIO_LINE(6), GPIO_LOW); + gpio_set_value(7, 0); + gpio_set_value(6, 0); } else { - gpio_line_set(IOP3XX_GPIO_LINE(5), GPIO_LOW); - gpio_line_set(IOP3XX_GPIO_LINE(4), GPIO_LOW); + gpio_set_value(5, 0); + gpio_set_value(4, 0); } #endif /* NB SR bits not same position as CR IE bits :-( */ - iop3xx_adap->SR_enabled = + iop3xx_adap->SR_enabled = IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD | IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY; @@ -96,23 +97,23 @@ iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap) __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); } -static void +static void iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap) { unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); - - cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | + + cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN); __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); } -/* - * NB: the handler has to clear the source of the interrupt! +/* + * NB: the handler has to clear the source of the interrupt! * Then it passes the SR flags of interest to BH via adap data */ -static irqreturn_t -iop3xx_i2c_irq_handler(int this_irq, void *dev_id) +static irqreturn_t +iop3xx_i2c_irq_handler(int this_irq, void *dev_id) { struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id; u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET); @@ -126,7 +127,7 @@ iop3xx_i2c_irq_handler(int this_irq, void *dev_id) } /* check all error conditions, clear them , report most important */ -static int +static int iop3xx_i2c_error(u32 sr) { int rc = 0; @@ -135,12 +136,12 @@ iop3xx_i2c_error(u32 sr) if ( !rc ) rc = -I2C_ERR_BERR; } if ((sr & IOP3XX_ISR_ALD)) { - if ( !rc ) rc = -I2C_ERR_ALD; + if ( !rc ) rc = -I2C_ERR_ALD; } - return rc; + return rc; } -static inline u32 +static inline u32 iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap) { unsigned long flags; @@ -161,8 +162,8 @@ iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap) typedef int (* compare_func)(unsigned test, unsigned mask); /* returns 1 on correct comparison */ -static int -iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, +static int +iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, unsigned flags, unsigned* status, compare_func compare) { @@ -192,47 +193,47 @@ iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, } /* - * Concrete compare_funcs + * Concrete compare_funcs */ -static int +static int all_bits_clear(unsigned test, unsigned mask) { return (test & mask) == 0; } -static int +static int any_bits_set(unsigned test, unsigned mask) { return (test & mask) != 0; } -static int +static int iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) { - return iop3xx_i2c_wait_event( - iop3xx_adap, + return iop3xx_i2c_wait_event( + iop3xx_adap, IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD, status, any_bits_set); } -static int +static int iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) { - return iop3xx_i2c_wait_event( - iop3xx_adap, + return iop3xx_i2c_wait_event( + iop3xx_adap, IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD, status, any_bits_set); } -static int +static int iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) { - return iop3xx_i2c_wait_event( + return iop3xx_i2c_wait_event( iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear); } -static int -iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, +static int +iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, struct i2c_msg* msg) { unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); @@ -247,7 +248,7 @@ iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, } __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET); - + cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK); cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE; @@ -257,8 +258,8 @@ iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, return rc; } -static int -iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, +static int +iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, int stop) { unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); @@ -277,10 +278,10 @@ iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status); return rc; -} +} -static int -iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, +static int +iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, int stop) { unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); @@ -304,19 +305,19 @@ iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, return rc; } -static int +static int iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count) { struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; int ii; int rc = 0; - for (ii = 0; rc == 0 && ii != count; ++ii) + for (ii = 0; rc == 0 && ii != count; ++ii) rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1); return rc; } -static int +static int iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count) { struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; @@ -325,7 +326,7 @@ iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count) for (ii = 0; rc == 0 && ii != count; ++ii) rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1); - + return rc; } @@ -336,8 +337,8 @@ iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count) * Each transfer (i.e. a read or a write) is separated by a repeated start * condition. */ -static int -iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) +static int +iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) { struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; int rc; @@ -357,8 +358,8 @@ iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) /* * master_xfer() - main read/write entry */ -static int -iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, +static int +iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) { struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; @@ -375,14 +376,14 @@ iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, } iop3xx_i2c_transaction_cleanup(iop3xx_adap); - + if(ret) return ret; - return im; + return im; } -static u32 +static u32 iop3xx_i2c_func(struct i2c_adapter *adap) { return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; @@ -393,11 +394,11 @@ static const struct i2c_algorithm iop3xx_i2c_algo = { .functionality = iop3xx_i2c_func, }; -static int +static int iop3xx_i2c_remove(struct platform_device *pdev) { struct i2c_adapter *padapter = platform_get_drvdata(pdev); - struct i2c_algo_iop3xx_data *adapter_data = + struct i2c_algo_iop3xx_data *adapter_data = (struct i2c_algo_iop3xx_data *)padapter->algo_data; struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET); @@ -419,7 +420,7 @@ iop3xx_i2c_remove(struct platform_device *pdev) return 0; } -static int +static int iop3xx_i2c_probe(struct platform_device *pdev) { struct resource *res; diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c index c855e7c..d0d1bd4 100644 --- a/drivers/mtd/nand/bcm_umi_nand.c +++ b/drivers/mtd/nand/bcm_umi_nand.c @@ -249,20 +249,20 @@ static int nand_dev_ready(struct mtd_info *mtd) int bcm_umi_nand_inithw(void) { /* Configure nand timing parameters */ - REG_UMI_NAND_TCR &= ~0x7ffff; - REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR; + writel(readl(®_UMI_NAND_TCR) & ~0x7ffff, ®_UMI_NAND_TCR); + writel(readl(®_UMI_NAND_TCR) | HW_CFG_NAND_TCR, ®_UMI_NAND_TCR); #if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS) /* enable software control of CS */ - REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL; + writel(readl(®_UMI_NAND_TCR) | REG_UMI_NAND_TCR_CS_SWCTRL, ®_UMI_NAND_TCR); #endif /* keep NAND chip select asserted */ - REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED; + writel(readl(®_UMI_NAND_RCSR) | REG_UMI_NAND_RCSR_CS_ASSERTED, ®_UMI_NAND_RCSR); - REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16; + writel(readl(®_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, ®_UMI_NAND_TCR); /* enable writes to flash */ - REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP; + writel(readl(®_UMI_MMD_ICR) | REG_UMI_MMD_ICR_FLASH_WP, ®_UMI_MMD_ICR); writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET); nand_bcm_umi_wait_till_ready(); diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h index 198b304..d901866 100644 --- a/drivers/mtd/nand/nand_bcm_umi.h +++ b/drivers/mtd/nand/nand_bcm_umi.h @@ -17,7 +17,7 @@ /* ---- Include Files ---------------------------------------------------- */ #include <mach/reg_umi.h> #include <mach/reg_nand.h> -#include <cfg_global.h> +#include <mach/cfg_global.h> /* ---- Constants and Types ---------------------------------------------- */ #if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING) @@ -48,7 +48,7 @@ int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData, /* Check in device is ready */ static inline int nand_bcm_umi_dev_ready(void) { - return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY; + return readl(®_UMI_NAND_RCSR) & REG_UMI_NAND_RCSR_RDY; } /* Wait until device is ready */ @@ -62,10 +62,11 @@ static inline void nand_bcm_umi_wait_till_ready(void) static inline void nand_bcm_umi_hamming_enable_hwecc(void) { /* disable and reset ECC, 512 byte page */ - REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE | - REG_UMI_NAND_ECC_CSR_256BYTE); + writel(readl(®_UMI_NAND_ECC_CSR) & ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE | + REG_UMI_NAND_ECC_CSR_256BYTE), ®_UMI_NAND_ECC_CSR); /* enable ECC */ - REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE; + writel(readl(®_UMI_NAND_ECC_CSR) | REG_UMI_NAND_ECC_CSR_ECC_ENABLE, + ®_UMI_NAND_ECC_CSR); } #if NAND_ECC_BCH @@ -76,18 +77,18 @@ static inline void nand_bcm_umi_hamming_enable_hwecc(void) static inline void nand_bcm_umi_bch_enable_read_hwecc(void) { /* disable and reset ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; + writel(REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, ®_UMI_BCH_CTRL_STATUS); /* Turn on ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; + writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, ®_UMI_BCH_CTRL_STATUS); } /* Enable BCH Write ECC */ static inline void nand_bcm_umi_bch_enable_write_hwecc(void) { /* disable and reset ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID; + writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID, ®_UMI_BCH_CTRL_STATUS); /* Turn on ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN; + writel(REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN, ®_UMI_BCH_CTRL_STATUS); } /* Config number of BCH ECC bytes */ @@ -99,9 +100,9 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes) uint32_t numBits = numEccBytes * 8; /* disable and reset ECC */ - REG_UMI_BCH_CTRL_STATUS = - REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID | - REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; + writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID | + REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, + ®_UMI_BCH_CTRL_STATUS); /* Every correctible bit requires 13 ECC bits */ tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT); @@ -113,23 +114,21 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes) kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT); /* Write the settings */ - REG_UMI_BCH_N = nValue; - REG_UMI_BCH_T = tValue; - REG_UMI_BCH_K = kValue; + writel(nValue, ®_UMI_BCH_N); + writel(tValue, ®_UMI_BCH_T); + writel(kValue, ®_UMI_BCH_K); } /* Pause during ECC read calculation to skip bytes in OOB */ static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void) { - REG_UMI_BCH_CTRL_STATUS = - REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | - REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC; + writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC, ®_UMI_BCH_CTRL_STATUS); } /* Resume during ECC read calculation after skipping bytes in OOB */ static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void) { - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; + writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, ®_UMI_BCH_CTRL_STATUS); } /* Poll read ECC calc to check when hardware completes */ @@ -139,7 +138,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void) do { /* wait for ECC to be valid */ - regVal = REG_UMI_BCH_CTRL_STATUS; + regVal = readl(®_UMI_BCH_CTRL_STATUS); } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0); return regVal; @@ -149,7 +148,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void) static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void) { /* wait for ECC to be valid */ - while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID) + while ((readl(®_UMI_BCH_CTRL_STATUS) & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID) == 0) ; } @@ -170,9 +169,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, if (pageSize != NAND_DATA_ACCESS_SIZE) { /* skip BI */ #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp++ = REG_NAND_DATA8; + *oobp++ = readb(®_NAND_DATA8); #else - REG_NAND_DATA8; + readb(®_NAND_DATA8); #endif numToRead--; } @@ -180,9 +179,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, while (numToRead > numEccBytes) { /* skip free oob region */ #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp++ = REG_NAND_DATA8; + *oobp++ = readb(®_NAND_DATA8); #else - REG_NAND_DATA8; + readb(®_NAND_DATA8); #endif numToRead--; } @@ -193,11 +192,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, while (numToRead > 11) { #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp = REG_NAND_DATA8; + *oobp = readb(®_NAND_DATA8); eccCalc[eccPos++] = *oobp; oobp++; #else - eccCalc[eccPos++] = REG_NAND_DATA8; + eccCalc[eccPos++] = readb(®_NAND_DATA8); #endif numToRead--; } @@ -207,9 +206,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, if (numToRead == 11) { /* read BI */ #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp++ = REG_NAND_DATA8; + *oobp++ = readb(®_NAND_DATA8); #else - REG_NAND_DATA8; + readb(®_NAND_DATA8); #endif numToRead--; } @@ -219,11 +218,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, nand_bcm_umi_bch_resume_read_ecc_calc(); while (numToRead) { #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp = REG_NAND_DATA8; + *oobp = readb(®_NAND_DATA8); eccCalc[eccPos++] = *oobp; oobp++; #else - eccCalc[eccPos++] = REG_NAND_DATA8; + eccCalc[eccPos++] = readb(®_NAND_DATA8); #endif numToRead--; } @@ -255,7 +254,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, if (pageSize == NAND_DATA_ACCESS_SIZE) { /* Now fill in the ECC bytes */ if (numEccBytes >= 13) - eccVal = REG_UMI_BCH_WR_ECC_3; + eccVal = readl(®_UMI_BCH_WR_ECC_3); /* Usually we skip CM in oob[0,1] */ NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0], @@ -268,7 +267,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, eccVal & 0xff); /* ECC 12 */ if (numEccBytes >= 9) - eccVal = REG_UMI_BCH_WR_ECC_2; + eccVal = readl(®_UMI_BCH_WR_ECC_2); NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3], (eccVal >> 24) & 0xff); /* ECC11 */ @@ -281,7 +280,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, /* Now fill in the ECC bytes */ if (numEccBytes >= 13) - eccVal = REG_UMI_BCH_WR_ECC_3; + eccVal = readl(®_UMI_BCH_WR_ECC_3); /* Usually skip CM in oob[1,2] */ NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1], @@ -294,7 +293,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, eccVal & 0xff); /* ECC12 */ if (numEccBytes >= 9) - eccVal = REG_UMI_BCH_WR_ECC_2; + eccVal = readl(®_UMI_BCH_WR_ECC_2); NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4], (eccVal >> 24) & 0xff); /* ECC11 */ @@ -309,7 +308,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, eccVal & 0xff); /* ECC8 */ if (numEccBytes >= 5) - eccVal = REG_UMI_BCH_WR_ECC_1; + eccVal = readl(®_UMI_BCH_WR_ECC_1); NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8], (eccVal >> 24) & 0xff); /* ECC7 */ @@ -321,7 +320,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, eccVal & 0xff); /* ECC4 */ if (numEccBytes >= 1) - eccVal = REG_UMI_BCH_WR_ECC_0; + eccVal = readl(®_UMI_BCH_WR_ECC_0); NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12], (eccVal >> 24) & 0xff); /* ECC3 */ diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index cc0f00d..b446c96 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -1,11 +1,8 @@ /* * U300 GPIO module. * - * Copyright (C) 2007-2011 ST-Ericsson AB + * Copyright (C) 2007-2012 ST-Ericsson AB * License terms: GNU General Public License (GPL) version 2 - * This can driver either of the two basic GPIO cores - * available in the U300 platforms: - * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0) * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) * Author: Linus Walleij <linus.walleij@linaro.org> * Author: Jonas Aaberg <jonas.aberg@stericsson.com> @@ -24,19 +21,22 @@ #include <linux/slab.h> #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf-generic.h> -#include <mach/gpio-u300.h> +#include <linux/platform_data/pinctrl-coh901.h> #include "pinctrl-coh901.h" +#define U300_GPIO_PORT_STRIDE (0x30) /* - * Register definitions for COH 901 335 variant + * Control Register 32bit (R/W) + * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores + * gives the number of GPIO pins. + * bit 8-2 (mask 0x000001FC) contains the core version ID. */ -#define U300_335_PORT_STRIDE (0x1C) -/* Port X Pin Data Register 32bit, this is both input and output (R/W) */ -#define U300_335_PXPDIR (0x00) -#define U300_335_PXPDOR (0x00) -/* Port X Pin Config Register 32bit (R/W) */ -#define U300_335_PXPCR (0x04) -/* This register layout is the same in both blocks */ +#define U300_GPIO_CR (0x00) +#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL) +#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL) +#define U300_GPIO_PXPDIR (0x04) +#define U300_GPIO_PXPDOR (0x08) +#define U300_GPIO_PXPCR (0x0C) #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL) #define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL) #define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL) @@ -44,53 +44,17 @@ #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL) #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL) #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL) -/* Port X Interrupt Event Register 32bit (R/W) */ -#define U300_335_PXIEV (0x08) -/* Port X Interrupt Enable Register 32bit (R/W) */ -#define U300_335_PXIEN (0x0C) -/* Port X Interrupt Force Register 32bit (R/W) */ -#define U300_335_PXIFR (0x10) -/* Port X Interrupt Config Register 32bit (R/W) */ -#define U300_335_PXICR (0x14) -/* This register layout is the same in both blocks */ +#define U300_GPIO_PXPER (0x10) +#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL) +#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL) +#define U300_GPIO_PXIEV (0x14) +#define U300_GPIO_PXIEN (0x18) +#define U300_GPIO_PXIFR (0x1C) +#define U300_GPIO_PXICR (0x20) #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL) #define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL) #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL) #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) -/* Port X Pull-up Enable Register 32bit (R/W) */ -#define U300_335_PXPER (0x18) -/* This register layout is the same in both blocks */ -#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL) -#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL) -/* Control Register 32bit (R/W) */ -#define U300_335_CR (0x54) -#define U300_335_CR_BLOCK_CLOCK_ENABLE (0x00000001UL) - -/* - * Register definitions for COH 901 571 / 3 variant - */ -#define U300_571_PORT_STRIDE (0x30) -/* - * Control Register 32bit (R/W) - * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores - * gives the number of GPIO pins. - * bit 8-2 (mask 0x000001FC) contains the core version ID. - */ -#define U300_571_CR (0x00) -#define U300_571_CR_SYNC_SEL_ENABLE (0x00000002UL) -#define U300_571_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL) -/* - * These registers have the same layout and function as the corresponding - * COH 901 335 registers, just at different offset. - */ -#define U300_571_PXPDIR (0x04) -#define U300_571_PXPDOR (0x08) -#define U300_571_PXPCR (0x0C) -#define U300_571_PXPER (0x10) -#define U300_571_PXIEV (0x14) -#define U300_571_PXIEN (0x18) -#define U300_571_PXIFR (0x1C) -#define U300_571_PXICR (0x20) /* 8 bits per port, no version has more than 7 ports */ #define U300_GPIO_PINS_PER_PORT 8 @@ -149,8 +113,6 @@ struct u300_gpio_confdata { /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */ #define BS335_GPIO_NUM_PORTS 7 -/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */ -#define BS365_GPIO_NUM_PORTS 5 #define U300_FLOATING_INPUT { \ .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ @@ -172,7 +134,6 @@ struct u300_gpio_confdata { .outval = 1, \ } - /* Initial configuration */ static const struct __initconst u300_gpio_confdata bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { @@ -255,66 +216,6 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { } }; -static const struct __initconst u300_gpio_confdata -bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { - /* Port 0, pins 0-7 */ - { - U300_FLOATING_INPUT, - U300_OUTPUT_LOW, - U300_FLOATING_INPUT, - U300_OUTPUT_LOW, - U300_OUTPUT_LOW, - U300_OUTPUT_LOW, - U300_PULL_UP_INPUT, - U300_FLOATING_INPUT, - }, - /* Port 1, pins 0-7 */ - { - U300_OUTPUT_LOW, - U300_FLOATING_INPUT, - U300_OUTPUT_LOW, - U300_FLOATING_INPUT, - U300_FLOATING_INPUT, - U300_OUTPUT_HIGH, - U300_OUTPUT_LOW, - U300_OUTPUT_LOW, - }, - /* Port 2, pins 0-7 */ - { - U300_FLOATING_INPUT, - U300_PULL_UP_INPUT, - U300_OUTPUT_LOW, - U300_OUTPUT_LOW, - U300_PULL_UP_INPUT, - U300_PULL_UP_INPUT, - U300_PULL_UP_INPUT, - U300_PULL_UP_INPUT, - }, - /* Port 3, pins 0-7 */ - { - U300_PULL_UP_INPUT, - U300_PULL_UP_INPUT, - U300_PULL_UP_INPUT, - U300_PULL_UP_INPUT, - U300_PULL_UP_INPUT, - U300_PULL_UP_INPUT, - U300_PULL_UP_INPUT, - U300_PULL_UP_INPUT, - }, - /* Port 4, pins 0-7 */ - { - U300_PULL_UP_INPUT, - U300_PULL_UP_INPUT, - U300_PULL_UP_INPUT, - U300_PULL_UP_INPUT, - /* These 4 pins doesn't exist on DB3210 */ - U300_OUTPUT_LOW, - U300_OUTPUT_LOW, - U300_OUTPUT_LOW, - U300_OUTPUT_LOW, - } -}; - /** * to_u300_gpio() - get the pointer to u300_gpio * @chip: the gpio chip member of the structure u300_gpio @@ -716,13 +617,7 @@ static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio, const struct u300_gpio_confdata *conf; int offset = (i*8) + j; - if (plat->variant == U300_GPIO_COH901571_3_BS335) - conf = &bs335_gpio_config[i][j]; - else if (plat->variant == U300_GPIO_COH901571_3_BS365) - conf = &bs365_gpio_config[i][j]; - else - break; - + conf = &bs335_gpio_config[i][j]; u300_gpio_init_pin(gpio, offset, conf); } } @@ -796,50 +691,27 @@ static int __init u300_gpio_probe(struct platform_device *pdev) goto err_no_ioremap; } - if (plat->variant == U300_GPIO_COH901335) { - dev_info(gpio->dev, - "initializing GPIO Controller COH 901 335\n"); - gpio->stride = U300_335_PORT_STRIDE; - gpio->pcr = U300_335_PXPCR; - gpio->dor = U300_335_PXPDOR; - gpio->dir = U300_335_PXPDIR; - gpio->per = U300_335_PXPER; - gpio->icr = U300_335_PXICR; - gpio->ien = U300_335_PXIEN; - gpio->iev = U300_335_PXIEV; - ifr = U300_335_PXIFR; - - /* Turn on the GPIO block */ - writel(U300_335_CR_BLOCK_CLOCK_ENABLE, - gpio->base + U300_335_CR); - } else if (plat->variant == U300_GPIO_COH901571_3_BS335 || - plat->variant == U300_GPIO_COH901571_3_BS365) { - dev_info(gpio->dev, - "initializing GPIO Controller COH 901 571/3\n"); - gpio->stride = U300_571_PORT_STRIDE; - gpio->pcr = U300_571_PXPCR; - gpio->dor = U300_571_PXPDOR; - gpio->dir = U300_571_PXPDIR; - gpio->per = U300_571_PXPER; - gpio->icr = U300_571_PXICR; - gpio->ien = U300_571_PXIEN; - gpio->iev = U300_571_PXIEV; - ifr = U300_571_PXIFR; - - val = readl(gpio->base + U300_571_CR); - dev_info(gpio->dev, "COH901571/3 block version: %d, " \ - "number of cores: %d totalling %d pins\n", - ((val & 0x000001FC) >> 2), - ((val & 0x0000FE00) >> 9), - ((val & 0x0000FE00) >> 9) * 8); - writel(U300_571_CR_BLOCK_CLKRQ_ENABLE, - gpio->base + U300_571_CR); - u300_gpio_init_coh901571(gpio, plat); - } else { - dev_err(gpio->dev, "unknown block variant\n"); - err = -ENODEV; - goto err_unknown_variant; - } + dev_info(gpio->dev, + "initializing GPIO Controller COH 901 571/3\n"); + gpio->stride = U300_GPIO_PORT_STRIDE; + gpio->pcr = U300_GPIO_PXPCR; + gpio->dor = U300_GPIO_PXPDOR; + gpio->dir = U300_GPIO_PXPDIR; + gpio->per = U300_GPIO_PXPER; + gpio->icr = U300_GPIO_PXICR; + gpio->ien = U300_GPIO_PXIEN; + gpio->iev = U300_GPIO_PXIEV; + ifr = U300_GPIO_PXIFR; + + val = readl(gpio->base + U300_GPIO_CR); + dev_info(gpio->dev, "COH901571/3 block version: %d, " \ + "number of cores: %d totalling %d pins\n", + ((val & 0x000001FC) >> 2), + ((val & 0x0000FE00) >> 9), + ((val & 0x0000FE00) >> 9) * 8); + writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, + gpio->base + U300_GPIO_CR); + u300_gpio_init_coh901571(gpio, plat); /* Add each port with its IRQ separately */ INIT_LIST_HEAD(&gpio->port_list); @@ -906,7 +778,6 @@ err_no_pinctrl: err_no_chip: err_no_port: u300_gpio_free_ports(gpio); -err_unknown_variant: iounmap(gpio->base); err_no_ioremap: release_mem_region(gpio->memres->start, resource_size(gpio->memres)); @@ -923,16 +794,11 @@ err_no_clk: static int __exit u300_gpio_remove(struct platform_device *pdev) { - struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev); struct u300_gpio *gpio = platform_get_drvdata(pdev); int err; /* Turn off the GPIO block */ - if (plat->variant == U300_GPIO_COH901335) - writel(0x00000000U, gpio->base + U300_335_CR); - if (plat->variant == U300_GPIO_COH901571_3_BS335 || - plat->variant == U300_GPIO_COH901571_3_BS365) - writel(0x00000000U, gpio->base + U300_571_CR); + writel(0x00000000U, gpio->base + U300_GPIO_CR); err = gpiochip_remove(&gpio->chip); if (err < 0) { diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 7065df6..7de2285 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -13,7 +13,6 @@ config USB_ARCH_HAS_OHCI default y if PXA3xx default y if ARCH_EP93XX default y if ARCH_AT91 - default y if ARCH_PNX4008 default y if MFD_TC6393XB default y if ARCH_W90X900 default y if ARCH_DAVINCI_DA8XX diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 075d2ec..276add2 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -292,7 +292,7 @@ config USB_OHCI_HCD depends on USB && USB_ARCH_HAS_OHCI select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3 select USB_OTG_UTILS if ARCH_OMAP - select USB_ISP1301 if ARCH_LPC32XX || ARCH_PNX4008 + select USB_ISP1301 if ARCH_LPC32XX ---help--- The Open Host Controller Interface (OHCI) is a standard for accessing USB 1.1 host controller hardware. It does more in hardware than Intel's diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 2b1e8d8..6780010 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1049,7 +1049,7 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_hcd_at91_driver #endif -#if defined(CONFIG_ARCH_PNX4008) || defined(CONFIG_ARCH_LPC32XX) +#ifdef CONFIG_ARCH_LPC32XX #include "ohci-nxp.c" #define PLATFORM_DRIVER usb_hcd_nxp_driver #endif diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c index a446386..1199666 100644 --- a/drivers/usb/host/ohci-nxp.c +++ b/drivers/usb/host/ohci-nxp.c @@ -2,7 +2,6 @@ * driver for NXP USB Host devices * * Currently supported OHCI host devices: - * - Philips PNX4008 * - NXP LPC32xx * * Authors: Dmitry Chigirev <source@mvista.com> @@ -66,38 +65,6 @@ static struct clk *usb_pll_clk; static struct clk *usb_dev_clk; static struct clk *usb_otg_clk; -static void isp1301_configure_pnx4008(void) -{ - /* PNX4008 only supports DAT_SE0 USB mode */ - /* PNX4008 R2A requires setting the MAX603 to output 3.6V */ - /* Power up externel charge-pump */ - - i2c_smbus_write_byte_data(isp1301_i2c_client, - ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0 | MC1_SPEED_REG); - i2c_smbus_write_byte_data(isp1301_i2c_client, - ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, - ~(MC1_DAT_SE0 | MC1_SPEED_REG)); - i2c_smbus_write_byte_data(isp1301_i2c_client, - ISP1301_I2C_MODE_CONTROL_2, - MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL); - i2c_smbus_write_byte_data(isp1301_i2c_client, - ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR, - ~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL)); - i2c_smbus_write_byte_data(isp1301_i2c_client, - ISP1301_I2C_OTG_CONTROL_1, OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN); - i2c_smbus_write_byte_data(isp1301_i2c_client, - ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, - ~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN)); - i2c_smbus_write_byte_data(isp1301_i2c_client, - ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, 0xFF); - i2c_smbus_write_byte_data(isp1301_i2c_client, - ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, - 0xFF); - i2c_smbus_write_byte_data(isp1301_i2c_client, - ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, - 0xFF); -} - static void isp1301_configure_lpc32xx(void) { /* LPC32XX only supports DAT_SE0 USB mode */ @@ -149,10 +116,7 @@ static void isp1301_configure_lpc32xx(void) static void isp1301_configure(void) { - if (machine_is_pnx4008()) - isp1301_configure_pnx4008(); - else - isp1301_configure_lpc32xx(); + isp1301_configure_lpc32xx(); } static inline void isp1301_vbus_on(void) @@ -241,47 +205,6 @@ static const struct hc_driver ohci_nxp_hc_driver = { .start_port_reset = ohci_start_port_reset, }; -static void nxp_set_usb_bits(void) -{ - if (machine_is_pnx4008()) { - start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N); - start_int_ack(SE_USB_OTG_ATX_INT_N); - start_int_umask(SE_USB_OTG_ATX_INT_N); - - start_int_set_rising_edge(SE_USB_OTG_TIMER_INT); - start_int_ack(SE_USB_OTG_TIMER_INT); - start_int_umask(SE_USB_OTG_TIMER_INT); - - start_int_set_rising_edge(SE_USB_I2C_INT); - start_int_ack(SE_USB_I2C_INT); - start_int_umask(SE_USB_I2C_INT); - - start_int_set_rising_edge(SE_USB_INT); - start_int_ack(SE_USB_INT); - start_int_umask(SE_USB_INT); - - start_int_set_rising_edge(SE_USB_NEED_CLK_INT); - start_int_ack(SE_USB_NEED_CLK_INT); - start_int_umask(SE_USB_NEED_CLK_INT); - - start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT); - start_int_ack(SE_USB_AHB_NEED_CLK_INT); - start_int_umask(SE_USB_AHB_NEED_CLK_INT); - } -} - -static void nxp_unset_usb_bits(void) -{ - if (machine_is_pnx4008()) { - start_int_mask(SE_USB_OTG_ATX_INT_N); - start_int_mask(SE_USB_OTG_TIMER_INT); - start_int_mask(SE_USB_I2C_INT); - start_int_mask(SE_USB_INT); - start_int_mask(SE_USB_NEED_CLK_INT); - start_int_mask(SE_USB_AHB_NEED_CLK_INT); - } -} - static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev) { struct usb_hcd *hcd = 0; @@ -376,9 +299,6 @@ static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev) goto out8; } - /* Set all USB bits in the Start Enable register */ - nxp_set_usb_bits(); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "Failed to get MEM resource\n"); @@ -413,7 +333,6 @@ static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev) nxp_stop_hc(); out8: - nxp_unset_usb_bits(); usb_put_hcd(hcd); out7: clk_disable(usb_otg_clk); @@ -441,7 +360,6 @@ static int usb_hcd_nxp_remove(struct platform_device *pdev) nxp_stop_hc(); release_mem_region(hcd->rsrc_start, hcd->rsrc_len); usb_put_hcd(hcd); - nxp_unset_usb_bits(); clk_disable(usb_pll_clk); clk_put(usb_pll_clk); clk_disable(usb_dev_clk); diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 53d7571..ad1bb93 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -237,12 +237,12 @@ config OMAP_WATCHDOG here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog timer. config PNX4008_WATCHDOG - tristate "PNX4008 and LPC32XX Watchdog" - depends on ARCH_PNX4008 || ARCH_LPC32XX + tristate "LPC32XX Watchdog" + depends on ARCH_LPC32XX select WATCHDOG_CORE help Say Y here if to include support for the watchdog timer - in the PNX4008 or LPC32XX processor. + in the LPC32XX processor. This driver can be built as a module by choosing M. The module will be called pnx4008_wdt. |
