diff options
Diffstat (limited to 'drivers')
112 files changed, 6809 insertions, 547 deletions
diff --git a/drivers/acpi/acpica/hwxface.c b/drivers/acpi/acpica/hwxface.c index ab513a9..a716fed 100644 --- a/drivers/acpi/acpica/hwxface.c +++ b/drivers/acpi/acpica/hwxface.c @@ -74,7 +74,8 @@ acpi_status acpi_reset(void) /* Check if the reset register is supported */ - if (!reset_reg->address) { + if (!(acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER) || + !reset_reg->address) { return_ACPI_STATUS(AE_NOT_EXIST); } diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index ba14fb9..c3881b2 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c @@ -607,8 +607,7 @@ acpi_os_install_interrupt_handler(u32 gsi, acpi_osd_handler handler, acpi_irq_handler = handler; acpi_irq_context = context; - if (request_threaded_irq(irq, NULL, acpi_irq, IRQF_SHARED, "acpi", - acpi_irq)) { + if (request_irq(irq, acpi_irq, IRQF_SHARED, "acpi", acpi_irq)) { printk(KERN_ERR PREFIX "SCI (IRQ%d) allocation failed\n", irq); acpi_irq_handler = NULL; return AE_NOT_ACQUIRED; diff --git a/drivers/acpi/reboot.c b/drivers/acpi/reboot.c index c1d6124..a6c77e8b 100644 --- a/drivers/acpi/reboot.c +++ b/drivers/acpi/reboot.c @@ -23,7 +23,8 @@ void acpi_reboot(void) /* Is the reset register supported? The spec says we should be * checking the bit width and bit offset, but Windows ignores * these fields */ - /* Ignore also acpi_gbl_FADT.flags.ACPI_FADT_RESET_REGISTER */ + if (!(acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER)) + return; reset_value = acpi_gbl_FADT.reset_value; diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c index 68013f9..7857e8f 100644 --- a/drivers/ata/ata_piix.c +++ b/drivers/ata/ata_piix.c @@ -329,6 +329,8 @@ static const struct pci_device_id piix_pci_tbl[] = { { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, /* SATA Controller IDE (Lynx Point) */ { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, + /* SATA Controller IDE (DH89xxCC) */ + { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, { } /* terminate list */ }; diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index e0bda9f..28db50b 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -95,7 +95,7 @@ static unsigned int ata_dev_set_xfermode(struct ata_device *dev); static void ata_dev_xfermask(struct ata_device *dev); static unsigned long ata_dev_blacklisted(const struct ata_device *dev); -unsigned int ata_print_id = 1; +atomic_t ata_print_id = ATOMIC_INIT(1); struct ata_force_param { const char *name; @@ -6029,7 +6029,7 @@ int ata_host_register(struct ata_host *host, struct scsi_host_template *sht) /* give ports names and add SCSI hosts */ for (i = 0; i < host->n_ports; i++) - host->ports[i]->print_id = ata_print_id++; + host->ports[i]->print_id = atomic_inc_return(&ata_print_id); /* Create associated sysfs transport objects */ diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c index 1ee00c8..93dabdc 100644 --- a/drivers/ata/libata-scsi.c +++ b/drivers/ata/libata-scsi.c @@ -3843,7 +3843,7 @@ int ata_sas_async_port_init(struct ata_port *ap) int rc = ap->ops->port_start(ap); if (!rc) { - ap->print_id = ata_print_id++; + ap->print_id = atomic_inc_return(&ata_print_id); __ata_port_probe(ap); } @@ -3867,7 +3867,7 @@ int ata_sas_port_init(struct ata_port *ap) int rc = ap->ops->port_start(ap); if (!rc) { - ap->print_id = ata_print_id++; + ap->print_id = atomic_inc_return(&ata_print_id); rc = ata_port_probe(ap); } diff --git a/drivers/ata/libata-transport.c b/drivers/ata/libata-transport.c index 74aaee3..c341904 100644 --- a/drivers/ata/libata-transport.c +++ b/drivers/ata/libata-transport.c @@ -294,6 +294,7 @@ int ata_tport_add(struct device *parent, device_enable_async_suspend(dev); pm_runtime_set_active(dev); pm_runtime_enable(dev); + pm_runtime_forbid(dev); transport_add_device(dev); transport_configure_device(dev); diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h index 2e26fca..9d0fd0b 100644 --- a/drivers/ata/libata.h +++ b/drivers/ata/libata.h @@ -53,7 +53,7 @@ enum { ATA_DNXFER_QUIET = (1 << 31), }; -extern unsigned int ata_print_id; +extern atomic_t ata_print_id; extern int atapi_passthru16; extern int libata_fua; extern int libata_noacpi; diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 38950ea..7336d4a 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -4025,7 +4025,8 @@ static int mv_platform_probe(struct platform_device *pdev) struct ata_host *host; struct mv_host_priv *hpriv; struct resource *res; - int n_ports, rc; + int n_ports = 0; + int rc; ata_print_version_once(&pdev->dev, DRV_VERSION); diff --git a/drivers/block/virtio_blk.c b/drivers/block/virtio_blk.c index 0e4ef3d..0d39f2f 100644 --- a/drivers/block/virtio_blk.c +++ b/drivers/block/virtio_blk.c @@ -375,6 +375,34 @@ static int init_vq(struct virtio_blk *vblk) return err; } +/* + * Legacy naming scheme used for virtio devices. We are stuck with it for + * virtio blk but don't ever use it for any new driver. + */ +static int virtblk_name_format(char *prefix, int index, char *buf, int buflen) +{ + const int base = 'z' - 'a' + 1; + char *begin = buf + strlen(prefix); + char *end = buf + buflen; + char *p; + int unit; + + p = end - 1; + *p = '\0'; + unit = base; + do { + if (p == begin) + return -EINVAL; + *--p = 'a' + (index % unit); + index = (index / unit) - 1; + } while (index >= 0); + + memmove(begin, p, end - p); + memcpy(buf, prefix, strlen(prefix)); + + return 0; +} + static int __devinit virtblk_probe(struct virtio_device *vdev) { struct virtio_blk *vblk; @@ -443,18 +471,7 @@ static int __devinit virtblk_probe(struct virtio_device *vdev) q->queuedata = vblk; - if (index < 26) { - sprintf(vblk->disk->disk_name, "vd%c", 'a' + index % 26); - } else if (index < (26 + 1) * 26) { - sprintf(vblk->disk->disk_name, "vd%c%c", - 'a' + index / 26 - 1, 'a' + index % 26); - } else { - const unsigned int m1 = (index / 26 - 1) / 26 - 1; - const unsigned int m2 = (index / 26 - 1) % 26; - const unsigned int m3 = index % 26; - sprintf(vblk->disk->disk_name, "vd%c%c%c", - 'a' + m1, 'a' + m2, 'a' + m3); - } + virtblk_name_format("vd", index, vblk->disk->disk_name, DISK_NAME_LEN); vblk->disk->major = major; vblk->disk->first_minor = index_to_minor(index); diff --git a/drivers/block/xen-blkback/xenbus.c b/drivers/block/xen-blkback/xenbus.c index 89860f3..4f66171 100644 --- a/drivers/block/xen-blkback/xenbus.c +++ b/drivers/block/xen-blkback/xenbus.c @@ -416,7 +416,7 @@ static void xen_blkbk_discard(struct xenbus_transaction xbt, struct backend_info "discard-secure", "%d", blkif->vbd.discard_secure); if (err) { - dev_warn(dev-dev, "writing discard-secure (%d)", err); + dev_warn(&dev->dev, "writing discard-secure (%d)", err); return; } } diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c index 0053d7e..8f3f74c 100644 --- a/drivers/crypto/ixp4xx_crypto.c +++ b/drivers/crypto/ixp4xx_crypto.c @@ -18,6 +18,7 @@ #include <linux/interrupt.h> #include <linux/spinlock.h> #include <linux/gfp.h> +#include <linux/module.h> #include <crypto/ctr.h> #include <crypto/des.h> diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c index dc641c7..921039e 100644 --- a/drivers/crypto/talitos.c +++ b/drivers/crypto/talitos.c @@ -124,6 +124,9 @@ struct talitos_private { void __iomem *reg; int irq[2]; + /* SEC global registers lock */ + spinlock_t reg_lock ____cacheline_aligned; + /* SEC version geometry (from device tree node) */ unsigned int num_channels; unsigned int chfifo_len; @@ -412,6 +415,7 @@ static void talitos_done_##name(unsigned long data) \ { \ struct device *dev = (struct device *)data; \ struct talitos_private *priv = dev_get_drvdata(dev); \ + unsigned long flags; \ \ if (ch_done_mask & 1) \ flush_channel(dev, 0, 0, 0); \ @@ -427,8 +431,10 @@ static void talitos_done_##name(unsigned long data) \ out: \ /* At this point, all completed channels have been processed */ \ /* Unmask done interrupts for channels completed later on. */ \ + spin_lock_irqsave(&priv->reg_lock, flags); \ setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \ setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT); \ + spin_unlock_irqrestore(&priv->reg_lock, flags); \ } DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE) DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE) @@ -619,22 +625,28 @@ static irqreturn_t talitos_interrupt_##name(int irq, void *data) \ struct device *dev = data; \ struct talitos_private *priv = dev_get_drvdata(dev); \ u32 isr, isr_lo; \ + unsigned long flags; \ \ + spin_lock_irqsave(&priv->reg_lock, flags); \ isr = in_be32(priv->reg + TALITOS_ISR); \ isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \ /* Acknowledge interrupt */ \ out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \ out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \ \ - if (unlikely((isr & ~TALITOS_ISR_4CHDONE) & ch_err_mask || isr_lo)) \ - talitos_error(dev, isr, isr_lo); \ - else \ + if (unlikely(isr & ch_err_mask || isr_lo)) { \ + spin_unlock_irqrestore(&priv->reg_lock, flags); \ + talitos_error(dev, isr & ch_err_mask, isr_lo); \ + } \ + else { \ if (likely(isr & ch_done_mask)) { \ /* mask further done interrupts. */ \ clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \ /* done_task will unmask done interrupts at exit */ \ tasklet_schedule(&priv->done_task[tlet]); \ } \ + spin_unlock_irqrestore(&priv->reg_lock, flags); \ + } \ \ return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \ IRQ_NONE; \ @@ -2719,6 +2731,8 @@ static int talitos_probe(struct platform_device *ofdev) priv->ofdev = ofdev; + spin_lock_init(&priv->reg_lock); + err = talitos_probe_irq(ofdev); if (err) goto err_out; diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index cf9da36..ef378b5 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -91,11 +91,10 @@ config DW_DMAC config AT_HDMAC tristate "Atmel AHB DMA support" - depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 + depends on ARCH_AT91 select DMA_ENGINE help - Support the Atmel AHB DMA controller. This can be integrated in - chips such as the Atmel AT91SAM9RL. + Support the Atmel AHB DMA controller. config FSL_DMA tristate "Freescale Elo and Elo Plus DMA support" diff --git a/drivers/gpio/gpio-nomadik.c b/drivers/gpio/gpio-nomadik.c index 839624f..9b126b6d 100644 --- a/drivers/gpio/gpio-nomadik.c +++ b/drivers/gpio/gpio-nomadik.c @@ -22,14 +22,13 @@ #include <linux/spinlock.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/irqdomain.h> #include <linux/slab.h> #include <asm/mach/irq.h> #include <plat/pincfg.h> #include <plat/gpio-nomadik.h> -#include <mach/hardware.h> -#include <asm/gpio.h> /* * The GPIO module in the Nomadik family of Systems-on-Chip is an @@ -43,6 +42,7 @@ struct nmk_gpio_chip { struct gpio_chip chip; + struct irq_domain *domain; void __iomem *addr; struct clk *clk; unsigned int bank; @@ -58,8 +58,10 @@ struct nmk_gpio_chip { u32 real_wake; u32 rwimsc; u32 fwimsc; - u32 slpm; + u32 rimsc; + u32 fimsc; u32 pull_up; + u32 lowemi; }; static struct nmk_gpio_chip * @@ -124,6 +126,24 @@ static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, } } +static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, + unsigned offset, bool lowemi) +{ + u32 bit = BIT(offset); + bool enabled = nmk_chip->lowemi & bit; + + if (lowemi == enabled) + return; + + if (lowemi) + nmk_chip->lowemi |= bit; + else + nmk_chip->lowemi &= ~bit; + + writel_relaxed(nmk_chip->lowemi, + nmk_chip->addr + NMK_GPIO_LOWEMI); +} + static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, unsigned offset) { @@ -150,8 +170,8 @@ static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, unsigned offset, int gpio_mode, bool glitch) { - u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC); - u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC); + u32 rwimsc = nmk_chip->rwimsc; + u32 fwimsc = nmk_chip->fwimsc; if (glitch && nmk_chip->set_ioforce) { u32 bit = BIT(offset); @@ -173,6 +193,36 @@ static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, } } +static void +nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) +{ + u32 falling = nmk_chip->fimsc & BIT(offset); + u32 rising = nmk_chip->rimsc & BIT(offset); + int gpio = nmk_chip->chip.base + offset; + int irq = NOMADIK_GPIO_TO_IRQ(gpio); + struct irq_data *d = irq_get_irq_data(irq); + + if (!rising && !falling) + return; + + if (!d || !irqd_irq_disabled(d)) + return; + + if (rising) { + nmk_chip->rimsc &= ~BIT(offset); + writel_relaxed(nmk_chip->rimsc, + nmk_chip->addr + NMK_GPIO_RIMSC); + } + + if (falling) { + nmk_chip->fimsc &= ~BIT(offset); + writel_relaxed(nmk_chip->fimsc, + nmk_chip->addr + NMK_GPIO_FIMSC); + } + + dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); +} + static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) { @@ -238,6 +288,17 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, __nmk_gpio_set_pull(nmk_chip, offset, pull); } + __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg)); + + /* + * If the pin is switching to altfunc, and there was an interrupt + * installed on it which has been lazy disabled, actually mask the + * interrupt to prevent spurious interrupts that would occur while the + * pin is under control of the peripheral. Only SKE does this. + */ + if (af != NMK_GPIO_ALT_GPIO) + nmk_gpio_disable_lazy_irq(nmk_chip, offset); + /* * If we've backed up the SLPM registers (glitch workaround), modify * the backups since they will be restored. @@ -334,7 +395,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) struct nmk_gpio_chip *nmk_chip; int pin = PIN_NUM(cfgs[i]); - nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); + nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP]; if (!nmk_chip) { ret = -EINVAL; break; @@ -342,7 +403,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) clk_enable(nmk_chip->clk); spin_lock(&nmk_chip->lock); - __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base, + __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP, cfgs[i], sleep, glitch ? slpm : NULL); spin_unlock(&nmk_chip->lock); clk_disable(nmk_chip->clk); @@ -426,7 +487,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; if (!nmk_chip) return -EINVAL; @@ -434,7 +495,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); spin_lock(&nmk_chip->lock); - __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); + __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode); spin_unlock(&nmk_chip->lock); spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); @@ -461,13 +522,13 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; if (!nmk_chip) return -EINVAL; clk_enable(nmk_chip->clk); spin_lock_irqsave(&nmk_chip->lock, flags); - __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); + __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull); spin_unlock_irqrestore(&nmk_chip->lock, flags); clk_disable(nmk_chip->clk); @@ -489,13 +550,13 @@ int nmk_gpio_set_mode(int gpio, int gpio_mode) struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; if (!nmk_chip) return -EINVAL; clk_enable(nmk_chip->clk); spin_lock_irqsave(&nmk_chip->lock, flags); - __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); + __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode); spin_unlock_irqrestore(&nmk_chip->lock, flags); clk_disable(nmk_chip->clk); @@ -508,11 +569,11 @@ int nmk_gpio_get_mode(int gpio) struct nmk_gpio_chip *nmk_chip; u32 afunc, bfunc, bit; - nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; if (!nmk_chip) return -EINVAL; - bit = 1 << (gpio - nmk_chip->chip.base); + bit = 1 << (gpio % NMK_GPIO_PER_CHIP); clk_enable(nmk_chip->clk); @@ -529,21 +590,19 @@ EXPORT_SYMBOL(nmk_gpio_get_mode); /* IRQ functions */ static inline int nmk_gpio_get_bitmask(int gpio) { - return 1 << (gpio % 32); + return 1 << (gpio % NMK_GPIO_PER_CHIP); } static void nmk_gpio_irq_ack(struct irq_data *d) { - int gpio; struct nmk_gpio_chip *nmk_chip; - gpio = NOMADIK_IRQ_TO_GPIO(d->irq); nmk_chip = irq_data_get_irq_chip_data(d); if (!nmk_chip) return; clk_enable(nmk_chip->clk); - writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); + writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); clk_disable(nmk_chip->clk); } @@ -556,37 +615,52 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, int gpio, enum nmk_gpio_irq_type which, bool enable) { - u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC; - u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC; u32 bitmask = nmk_gpio_get_bitmask(gpio); - u32 reg; + u32 *rimscval; + u32 *fimscval; + u32 rimscreg; + u32 fimscreg; + + if (which == NORMAL) { + rimscreg = NMK_GPIO_RIMSC; + fimscreg = NMK_GPIO_FIMSC; + rimscval = &nmk_chip->rimsc; + fimscval = &nmk_chip->fimsc; + } else { + rimscreg = NMK_GPIO_RWIMSC; + fimscreg = NMK_GPIO_FWIMSC; + rimscval = &nmk_chip->rwimsc; + fimscval = &nmk_chip->fwimsc; + } /* we must individually set/clear the two edges */ if (nmk_chip->edge_rising & bitmask) { - reg = readl(nmk_chip->addr + rimsc); if (enable) - reg |= bitmask; + *rimscval |= bitmask; else - reg &= ~bitmask; - writel(reg, nmk_chip->addr + rimsc); + *rimscval &= ~bitmask; + writel(*rimscval, nmk_chip->addr + rimscreg); } if (nmk_chip->edge_falling & bitmask) { - reg = readl(nmk_chip->addr + fimsc); if (enable) - reg |= bitmask; + *fimscval |= bitmask; else - reg &= ~bitmask; - writel(reg, nmk_chip->addr + fimsc); + *fimscval &= ~bitmask; + writel(*fimscval, nmk_chip->addr + fimscreg); } } static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, int gpio, bool on) { - if (nmk_chip->sleepmode) { - __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, - on ? NMK_GPIO_SLPM_WAKEUP_ENABLE - : NMK_GPIO_SLPM_WAKEUP_DISABLE); + /* + * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is + * disabled, since setting SLPM to 1 increases power consumption, and + * wakeup is anyhow controlled by the RIMSC and FIMSC registers. + */ + if (nmk_chip->sleepmode && on) { + __nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base, + NMK_GPIO_SLPM_WAKEUP_ENABLE); } __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); @@ -594,14 +668,12 @@ static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) { - int gpio; struct nmk_gpio_chip *nmk_chip; unsigned long flags; u32 bitmask; - gpio = NOMADIK_IRQ_TO_GPIO(d->irq); nmk_chip = irq_data_get_irq_chip_data(d); - bitmask = nmk_gpio_get_bitmask(gpio); + bitmask = nmk_gpio_get_bitmask(d->hwirq); if (!nmk_chip) return -EINVAL; @@ -609,10 +681,10 @@ static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); spin_lock(&nmk_chip->lock); - __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable); + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); if (!(nmk_chip->real_wake & bitmask)) - __nmk_gpio_set_wake(nmk_chip, gpio, enable); + __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); spin_unlock(&nmk_chip->lock); spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); @@ -636,20 +708,18 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) struct nmk_gpio_chip *nmk_chip; unsigned long flags; u32 bitmask; - int gpio; - gpio = NOMADIK_IRQ_TO_GPIO(d->irq); nmk_chip = irq_data_get_irq_chip_data(d); if (!nmk_chip) return -EINVAL; - bitmask = nmk_gpio_get_bitmask(gpio); + bitmask = nmk_gpio_get_bitmask(d->hwirq); clk_enable(nmk_chip->clk); spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); spin_lock(&nmk_chip->lock); if (irqd_irq_disabled(d)) - __nmk_gpio_set_wake(nmk_chip, gpio, on); + __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); if (on) nmk_chip->real_wake |= bitmask; @@ -667,17 +737,14 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) { bool enabled = !irqd_irq_disabled(d); bool wake = irqd_is_wakeup_set(d); - int gpio; struct nmk_gpio_chip *nmk_chip; unsigned long flags; u32 bitmask; - gpio = NOMADIK_IRQ_TO_GPIO(d->irq); nmk_chip = irq_data_get_irq_chip_data(d); - bitmask = nmk_gpio_get_bitmask(gpio); + bitmask = nmk_gpio_get_bitmask(d->hwirq); if (!nmk_chip) return -EINVAL; - if (type & IRQ_TYPE_LEVEL_HIGH) return -EINVAL; if (type & IRQ_TYPE_LEVEL_LOW) @@ -687,10 +754,10 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) spin_lock_irqsave(&nmk_chip->lock, flags); if (enabled) - __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); if (enabled || wake) - __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); nmk_chip->edge_rising &= ~bitmask; if (type & IRQ_TYPE_EDGE_RISING) @@ -701,10 +768,10 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) nmk_chip->edge_falling |= bitmask; if (enabled) - __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); if (enabled || wake) - __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); spin_unlock_irqrestore(&nmk_chip->lock, flags); clk_disable(nmk_chip->clk); @@ -750,7 +817,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, chained_irq_enter(host_chip, desc); nmk_chip = irq_get_handler_data(irq); - first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); + first_irq = nmk_chip->domain->revmap_data.legacy.first_irq; while (status) { int bit = __ffs(status); @@ -784,18 +851,6 @@ static void nmk_gpio_secondary_irq_handler(unsigned int irq, static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) { - unsigned int first_irq; - int i; - - first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); - for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { - irq_set_chip_and_handler(i, &nmk_gpio_irq_chip, - handle_edge_irq); - set_irq_flags(i, IRQF_VALID); - irq_set_chip_data(i, nmk_chip); - irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); - } - irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); @@ -872,7 +927,7 @@ static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; + return irq_find_mapping(nmk_chip->domain, offset); } #ifdef CONFIG_DEBUG_FS @@ -1008,21 +1063,11 @@ void nmk_gpio_wakeups_suspend(void) clk_enable(chip->clk); - chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC); - chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC); - writel(chip->rwimsc & chip->real_wake, chip->addr + NMK_GPIO_RWIMSC); writel(chip->fwimsc & chip->real_wake, chip->addr + NMK_GPIO_FWIMSC); - if (chip->sleepmode) { - chip->slpm = readl(chip->addr + NMK_GPIO_SLPC); - - /* 0 -> wakeup enable */ - writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC); - } - clk_disable(chip->clk); } } @@ -1042,9 +1087,6 @@ void nmk_gpio_wakeups_resume(void) writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); - if (chip->sleepmode) - writel(chip->slpm, chip->addr + NMK_GPIO_SLPC); - clk_disable(chip->clk); } } @@ -1068,19 +1110,62 @@ void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) } } +int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct nmk_gpio_chip *nmk_chip = d->host_data; + + if (!nmk_chip) + return -EINVAL; + + irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); + set_irq_flags(irq, IRQF_VALID); + irq_set_chip_data(irq, nmk_chip); + irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); + + return 0; +} + +const struct irq_domain_ops nmk_gpio_irq_simple_ops = { + .map = nmk_gpio_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + static int __devinit nmk_gpio_probe(struct platform_device *dev) { struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; + struct device_node *np = dev->dev.of_node; struct nmk_gpio_chip *nmk_chip; struct gpio_chip *chip; struct resource *res; struct clk *clk; int secondary_irq; + void __iomem *base; int irq; int ret; - if (!pdata) + if (!pdata && !np) { + dev_err(&dev->dev, "No platform data or device tree found\n"); return -ENODEV; + } + + if (np) { + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + if (of_get_property(np, "supports-sleepmode", NULL)) + pdata->supports_sleepmode = true; + + if (of_property_read_u32(np, "gpio-bank", &dev->id)) { + dev_err(&dev->dev, "gpio-bank property not found\n"); + ret = -EINVAL; + goto out; + } + + pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; + pdata->num_gpio = NMK_GPIO_PER_CHIP; + } res = platform_get_resource(dev, IORESOURCE_MEM, 0); if (!res) { @@ -1106,10 +1191,16 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) goto out; } + base = ioremap(res->start, resource_size(res)); + if (!base) { + ret = -ENOMEM; + goto out_release; + } + clk = clk_get(&dev->dev, NULL); if (IS_ERR(clk)) { ret = PTR_ERR(clk); - goto out_release; + goto out_unmap; } nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); @@ -1117,13 +1208,14 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) ret = -ENOMEM; goto out_clk; } + /* * The virt address in nmk_chip->addr is in the nomadik register space, * so we can simply convert the resource address, without remapping */ nmk_chip->bank = dev->id; nmk_chip->clk = clk; - nmk_chip->addr = io_p2v(res->start); + nmk_chip->addr = base; nmk_chip->chip = nmk_gpio_template; nmk_chip->parent_irq = irq; nmk_chip->secondary_parent_irq = secondary_irq; @@ -1139,6 +1231,12 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) chip->dev = &dev->dev; chip->owner = THIS_MODULE; + clk_enable(nmk_chip->clk); + nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); + clk_disable(nmk_chip->clk); + + chip->of_node = np; + ret = gpiochip_add(&nmk_chip->chip); if (ret) goto out_free; @@ -1146,12 +1244,22 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); nmk_gpio_chips[nmk_chip->bank] = nmk_chip; + platform_set_drvdata(dev, nmk_chip); + nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP, + NOMADIK_GPIO_TO_IRQ(pdata->first_gpio), + 0, &nmk_gpio_irq_simple_ops, nmk_chip); + if (!nmk_chip->domain) { + pr_err("%s: Failed to create irqdomain\n", np->full_name); + ret = -ENOSYS; + goto out_free; + } + nmk_gpio_init_irq(nmk_chip); - dev_info(&dev->dev, "at address %p\n", - nmk_chip->addr); + dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); + return 0; out_free: @@ -1159,18 +1267,29 @@ out_free: out_clk: clk_disable(clk); clk_put(clk); +out_unmap: + iounmap(base); out_release: release_mem_region(res->start, resource_size(res)); out: dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, pdata->first_gpio, pdata->first_gpio+31); + if (np) + kfree(pdata); + return ret; } +static const struct of_device_id nmk_gpio_match[] = { + { .compatible = "st,nomadik-gpio", }, + {} +}; + static struct platform_driver nmk_gpio_driver = { .driver = { .owner = THIS_MODULE, .name = "gpio", + .of_match_table = nmk_gpio_match, }, .probe = nmk_gpio_probe, }; diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c index 30372f7..348b367 100644 --- a/drivers/gpu/drm/drm_bufs.c +++ b/drivers/gpu/drm/drm_bufs.c @@ -1510,8 +1510,8 @@ int drm_freebufs(struct drm_device *dev, void *data, * \param arg pointer to a drm_buf_map structure. * \return zero on success or a negative number on failure. * - * Maps the AGP, SG or PCI buffer region with do_mmap(), and copies information - * about each buffer into user space. For PCI buffers, it calls do_mmap() with + * Maps the AGP, SG or PCI buffer region with vm_mmap(), and copies information + * about each buffer into user space. For PCI buffers, it calls vm_mmap() with * offset equal to 0, which drm_mmap() interpretes as PCI buffers and calls * drm_mmap_dma(). */ @@ -1553,18 +1553,14 @@ int drm_mapbufs(struct drm_device *dev, void *data, retcode = -EINVAL; goto done; } - down_write(¤t->mm->mmap_sem); - virtual = do_mmap(file_priv->filp, 0, map->size, + virtual = vm_mmap(file_priv->filp, 0, map->size, PROT_READ | PROT_WRITE, MAP_SHARED, token); - up_write(¤t->mm->mmap_sem); } else { - down_write(¤t->mm->mmap_sem); - virtual = do_mmap(file_priv->filp, 0, dma->byte_count, + virtual = vm_mmap(file_priv->filp, 0, dma->byte_count, PROT_READ | PROT_WRITE, MAP_SHARED, 0); - up_write(¤t->mm->mmap_sem); } if (virtual > -1024UL) { /* Real error */ diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index d3aaeb6..c79870a 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -3335,10 +3335,12 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev, ret = crtc->funcs->page_flip(crtc, fb, e); if (ret) { - spin_lock_irqsave(&dev->event_lock, flags); - file_priv->event_space += sizeof e->event; - spin_unlock_irqrestore(&dev->event_lock, flags); - kfree(e); + if (page_flip->flags & DRM_MODE_PAGE_FLIP_EVENT) { + spin_lock_irqsave(&dev->event_lock, flags); + file_priv->event_space += sizeof e->event; + spin_unlock_irqrestore(&dev->event_lock, flags); + kfree(e); + } } out: diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c index cdfbf27..123de28 100644 --- a/drivers/gpu/drm/drm_fops.c +++ b/drivers/gpu/drm/drm_fops.c @@ -507,12 +507,12 @@ int drm_release(struct inode *inode, struct file *filp) drm_events_release(file_priv); - if (dev->driver->driver_features & DRIVER_GEM) - drm_gem_release(dev, file_priv); - if (dev->driver->driver_features & DRIVER_MODESET) drm_fb_release(file_priv); + if (dev->driver->driver_features & DRIVER_GEM) + drm_gem_release(dev, file_priv); + mutex_lock(&dev->ctxlist_mutex); if (!list_empty(&dev->ctxlist)) { struct drm_ctx_list *pos, *n; diff --git a/drivers/gpu/drm/drm_usb.c b/drivers/gpu/drm/drm_usb.c index c8c83da..37c9a52 100644 --- a/drivers/gpu/drm/drm_usb.c +++ b/drivers/gpu/drm/drm_usb.c @@ -1,6 +1,6 @@ #include "drmP.h" #include <linux/usb.h> -#include <linux/export.h> +#include <linux/module.h> int drm_get_usb_dev(struct usb_interface *interface, const struct usb_device_id *id, @@ -114,3 +114,7 @@ void drm_usb_exit(struct drm_driver *driver, usb_deregister(udriver); } EXPORT_SYMBOL(drm_usb_exit); + +MODULE_AUTHOR("David Airlie"); +MODULE_DESCRIPTION("USB DRM support"); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c index 26d5197..392ce71 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c @@ -581,10 +581,8 @@ int exynos_drm_gem_mmap_ioctl(struct drm_device *dev, void *data, obj->filp->f_op = &exynos_drm_gem_fops; obj->filp->private_data = obj; - down_write(¤t->mm->mmap_sem); - addr = do_mmap(obj->filp, 0, args->size, + addr = vm_mmap(obj->filp, 0, args->size, PROT_READ | PROT_WRITE, MAP_SHARED, 0); - up_write(¤t->mm->mmap_sem); drm_gem_object_unreference_unlocked(obj); diff --git a/drivers/gpu/drm/gma500/mdfld_dsi_output.h b/drivers/gpu/drm/gma500/mdfld_dsi_output.h index 21071ce..36eb074 100644 --- a/drivers/gpu/drm/gma500/mdfld_dsi_output.h +++ b/drivers/gpu/drm/gma500/mdfld_dsi_output.h @@ -29,7 +29,6 @@ #define __MDFLD_DSI_OUTPUT_H__ #include <linux/backlight.h> -#include <linux/version.h> #include <drm/drmP.h> #include <drm/drm.h> #include <drm/drm_crtc.h> diff --git a/drivers/gpu/drm/i810/i810_dma.c b/drivers/gpu/drm/i810/i810_dma.c index 2c8a60c..f920fb5 100644 --- a/drivers/gpu/drm/i810/i810_dma.c +++ b/drivers/gpu/drm/i810/i810_dma.c @@ -129,6 +129,7 @@ static int i810_map_buffer(struct drm_buf *buf, struct drm_file *file_priv) if (buf_priv->currently_mapped == I810_BUF_MAPPED) return -EINVAL; + /* This is all entirely broken */ down_write(¤t->mm->mmap_sem); old_fops = file_priv->filp->f_op; file_priv->filp->f_op = &i810_buffer_fops; @@ -157,11 +158,8 @@ static int i810_unmap_buffer(struct drm_buf *buf) if (buf_priv->currently_mapped != I810_BUF_MAPPED) return -EINVAL; - down_write(¤t->mm->mmap_sem); - retcode = do_munmap(current->mm, - (unsigned long)buf_priv->virtual, + retcode = vm_munmap((unsigned long)buf_priv->virtual, (size_t) buf->total); - up_write(¤t->mm->mmap_sem); buf_priv->currently_mapped = I810_BUF_UNMAPPED; buf_priv->virtual = NULL; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 0e3c6ac..0d1e4b7 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1087,11 +1087,9 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data, if (obj == NULL) return -ENOENT; - down_write(¤t->mm->mmap_sem); - addr = do_mmap(obj->filp, 0, args->size, + addr = vm_mmap(obj->filp, 0, args->size, PROT_READ | PROT_WRITE, MAP_SHARED, args->offset); - up_write(¤t->mm->mmap_sem); drm_gem_object_unreference_unlocked(obj); if (IS_ERR((void *)addr)) return addr; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index bae38ac..5908cd5 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3478,8 +3478,11 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, return false; } - /* All interlaced capable intel hw wants timings in frames. */ - drm_mode_set_crtcinfo(adjusted_mode, 0); + /* All interlaced capable intel hw wants timings in frames. Note though + * that intel_lvds_mode_fixup does some funny tricks with the crtc + * timings, so we need to be careful not to clobber these.*/ + if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) + drm_mode_set_crtcinfo(adjusted_mode, 0); return true; } @@ -7465,7 +7468,13 @@ static int intel_gen6_queue_flip(struct drm_device *dev, OUT_RING(fb->pitches[0] | obj->tiling_mode); OUT_RING(obj->gtt_offset); - pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; + /* Contrary to the suggestions in the documentation, + * "Enable Panel Fitter" does not seem to be required when page + * flipping with a non-native mode, and worse causes a normal + * modeset to fail. + * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; + */ + pf = 0; pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; OUT_RING(pf | pipesrc); ADVANCE_LP_RING(); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 5a14149..715afa1 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -105,6 +105,10 @@ #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) #define INTEL_MODE_DP_FORCE_6BPC (0x10) +/* This flag must be set by the encoder's mode_fixup if it changes the crtc + * timings in the mode to prevent the crtc fixup from overwriting them. + * Currently only lvds needs that. */ +#define INTEL_MODE_CRTC_TIMINGS_SET (0x20) static inline void intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c index 19ecd78..6e9ee33 100644 --- a/drivers/gpu/drm/i915/intel_fb.c +++ b/drivers/gpu/drm/i915/intel_fb.c @@ -279,6 +279,8 @@ void intel_fb_restore_mode(struct drm_device *dev) struct drm_mode_config *config = &dev->mode_config; struct drm_plane *plane; + mutex_lock(&dev->mode_config.mutex); + ret = drm_fb_helper_restore_fbdev_mode(&dev_priv->fbdev->helper); if (ret) DRM_DEBUG("failed to restore crtc mode\n"); @@ -286,4 +288,6 @@ void intel_fb_restore_mode(struct drm_device *dev) /* Be sure to shut off any planes that may be active */ list_for_each_entry(plane, &config->plane_list, head) plane->funcs->disable_plane(plane); + + mutex_unlock(&dev->mode_config.mutex); } diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 95db2e9..30e2c82 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -187,6 +187,8 @@ centre_horizontally(struct drm_display_mode *mode, mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; + + mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET; } static void @@ -208,6 +210,8 @@ centre_vertically(struct drm_display_mode *mode, mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; + + mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET; } static inline u32 panel_fitter_scaling(u32 source, u32 target) @@ -283,6 +287,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, for_each_pipe(pipe) I915_WRITE(BCLRPAT(pipe), 0); + drm_mode_set_crtcinfo(adjusted_mode, 0); + switch (intel_lvds->fitting_mode) { case DRM_MODE_SCALE_CENTER: /* diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 230a141..48177ec 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -47,8 +47,6 @@ intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, adjusted_mode->vtotal = fixed_mode->vtotal; adjusted_mode->clock = fixed_mode->clock; - - drm_mode_set_crtcinfo(adjusted_mode, 0); } /* adjusted_mode has been preset to be the panel's fixed mode */ diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c b/drivers/gpu/drm/nouveau/nouveau_pm.c index 34d591b..da3e7c3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_pm.c +++ b/drivers/gpu/drm/nouveau/nouveau_pm.c @@ -235,6 +235,7 @@ nouveau_pm_profile_set(struct drm_device *dev, const char *profile) return -EPERM; strncpy(string, profile, sizeof(string)); + string[sizeof(string) - 1] = 0; if ((ptr = strchr(string, '\n'))) *ptr = '\0'; diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c index a7844ab..2746402 100644 --- a/drivers/gpu/drm/nouveau/nv50_sor.c +++ b/drivers/gpu/drm/nouveau/nv50_sor.c @@ -42,7 +42,7 @@ nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane) struct drm_nouveau_private *dev_priv = dev->dev_private; static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */ static const u8 nv50[] = { 16, 8, 0, 24 }; - if (dev_priv->card_type == 0xaf) + if (dev_priv->chipset == 0xaf) return nvaf[lane]; return nv50[lane]; } diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index de71243..c8187c4 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -1135,7 +1135,7 @@ static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc } if (rdev->flags & RADEON_IS_AGP) { size_bf = mc->gtt_start; - size_af = 0xFFFFFFFF - mc->gtt_end + 1; + size_af = 0xFFFFFFFF - mc->gtt_end; if (size_bf > size_af) { if (mc->mc_vram_size > size_bf) { dev_warn(rdev->dev, "limiting VRAM\n"); @@ -1149,7 +1149,7 @@ static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc mc->real_vram_size = size_af; mc->mc_vram_size = size_af; } - mc->vram_start = mc->gtt_end; + mc->vram_start = mc->gtt_end + 1; } mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index bd05156..3c2e7a0 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c @@ -970,7 +970,7 @@ radeon_dvi_detect(struct drm_connector *connector, bool force) encoder = obj_to_encoder(obj); - if (encoder->encoder_type != DRM_MODE_ENCODER_DAC || + if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) continue; @@ -1000,6 +1000,7 @@ radeon_dvi_detect(struct drm_connector *connector, bool force) * cases the DVI port is actually a virtual KVM port connected to the service * processor. */ +out: if ((!rdev->is_atom_bios) && (ret == connector_status_disconnected) && rdev->mode_info.bios_hardcoded_edid_size) { @@ -1007,7 +1008,6 @@ radeon_dvi_detect(struct drm_connector *connector, bool force) ret = connector_status_connected; } -out: /* updated in get modes as well since we need to know if it's analog or digital */ radeon_connector_update_scratch_regs(connector, ret); return ret; diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c index 66d5fe1..65060b7 100644 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c @@ -147,6 +147,12 @@ static bool radeon_msi_ok(struct radeon_device *rdev) (rdev->pdev->subsystem_device == 0x01fd)) return true; + /* RV515 seems to have MSI issues where it loses + * MSI rearms occasionally. This leads to lockups and freezes. + * disable it by default. + */ + if (rdev->family == CHIP_RV515) + return false; if (rdev->flags & RADEON_IS_IGP) { /* APUs work fine with MSIs */ if (rdev->family >= CHIP_PALM) diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index c62ae4b..cdab1ae 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -969,7 +969,7 @@ void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) } if (rdev->flags & RADEON_IS_AGP) { size_bf = mc->gtt_start; - size_af = 0xFFFFFFFF - mc->gtt_end + 1; + size_af = 0xFFFFFFFF - mc->gtt_end; if (size_bf > size_af) { if (mc->mc_vram_size > size_bf) { dev_warn(rdev->dev, "limiting VRAM\n"); @@ -983,7 +983,7 @@ void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) mc->real_vram_size = size_af; mc->mc_vram_size = size_af; } - mc->vram_start = mc->gtt_end; + mc->vram_start = mc->gtt_end + 1; } mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index ac7a199..27bda98 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -2999,8 +2999,8 @@ int si_rlc_init(struct radeon_device *rdev) } r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM, &rdev->rlc.save_restore_gpu_addr); + radeon_bo_unreserve(rdev->rlc.save_restore_obj); if (r) { - radeon_bo_unreserve(rdev->rlc.save_restore_obj); dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r); si_rlc_fini(rdev); return r; @@ -3023,9 +3023,8 @@ int si_rlc_init(struct radeon_device *rdev) } r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM, &rdev->rlc.clear_state_gpu_addr); + radeon_bo_unreserve(rdev->rlc.clear_state_obj); if (r) { - - radeon_bo_unreserve(rdev->rlc.clear_state_obj); dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r); si_rlc_fini(rdev); return r; diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig index a3d0332..ffddcba 100644 --- a/drivers/hid/Kconfig +++ b/drivers/hid/Kconfig @@ -34,7 +34,7 @@ config HID config HID_BATTERY_STRENGTH bool depends on HID && POWER_SUPPLY && HID = POWER_SUPPLY - default y + default n config HIDRAW bool "/dev/hidraw raw HID device support" diff --git a/drivers/hid/hid-tivo.c b/drivers/hid/hid-tivo.c index de47039..9f85f82 100644 --- a/drivers/hid/hid-tivo.c +++ b/drivers/hid/hid-tivo.c @@ -62,7 +62,7 @@ static int tivo_input_mapping(struct hid_device *hdev, struct hid_input *hi, static const struct hid_device_id tivo_devices[] = { /* TiVo Slide Bluetooth remote, pairs with a Broadcom dongle */ - { HID_USB_DEVICE(USB_VENDOR_ID_TIVO, USB_DEVICE_ID_TIVO_SLIDE_BT) }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_TIVO, USB_DEVICE_ID_TIVO_SLIDE_BT) }, { HID_USB_DEVICE(USB_VENDOR_ID_TIVO, USB_DEVICE_ID_TIVO_SLIDE) }, { } }; diff --git a/drivers/hwmon/ads1015.c b/drivers/hwmon/ads1015.c index 7765e4f..1958f03 100644 --- a/drivers/hwmon/ads1015.c +++ b/drivers/hwmon/ads1015.c @@ -59,14 +59,11 @@ struct ads1015_data { struct ads1015_channel_data channel_data[ADS1015_CHANNELS]; }; -static int ads1015_read_value(struct i2c_client *client, unsigned int channel, - int *value) +static int ads1015_read_adc(struct i2c_client *client, unsigned int channel) { u16 config; - s16 conversion; struct ads1015_data *data = i2c_get_clientdata(client); unsigned int pga = data->channel_data[channel].pga; - int fullscale; unsigned int data_rate = data->channel_data[channel].data_rate; unsigned int conversion_time_ms; int res; @@ -78,7 +75,6 @@ static int ads1015_read_value(struct i2c_client *client, unsigned int channel, if (res < 0) goto err_unlock; config = res; - fullscale = fullscale_table[pga]; conversion_time_ms = DIV_ROUND_UP(1000, data_rate_table[data_rate]); /* setup and start single conversion */ @@ -105,33 +101,36 @@ static int ads1015_read_value(struct i2c_client *client, unsigned int channel, } res = i2c_smbus_read_word_swapped(client, ADS1015_CONVERSION); - if (res < 0) - goto err_unlock; - conversion = res; - - mutex_unlock(&data->update_lock); - - *value = DIV_ROUND_CLOSEST(conversion * fullscale, 0x7ff0); - - return 0; err_unlock: mutex_unlock(&data->update_lock); return res; } +static int ads1015_reg_to_mv(struct i2c_client *client, unsigned int channel, + s16 reg) +{ + struct ads1015_data *data = i2c_get_clientdata(client); + unsigned int pga = data->channel_data[channel].pga; + int fullscale = fullscale_table[pga]; + + return DIV_ROUND_CLOSEST(reg * fullscale, 0x7ff0); +} + /* sysfs callback function */ static ssize_t show_in(struct device *dev, struct device_attribute *da, char *buf) { struct sensor_device_attribute *attr = to_sensor_dev_attr(da); struct i2c_client *client = to_i2c_client(dev); - int in; int res; + int index = attr->index; - res = ads1015_read_value(client, attr->index, &in); + res = ads1015_read_adc(client, index); + if (res < 0) + return res; - return (res < 0) ? res : sprintf(buf, "%d\n", in); + return sprintf(buf, "%d\n", ads1015_reg_to_mv(client, index, res)); } static const struct sensor_device_attribute ads1015_in[] = { diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon/fam15h_power.c index b7494af..37a8fc9 100644 --- a/drivers/hwmon/fam15h_power.c +++ b/drivers/hwmon/fam15h_power.c @@ -122,6 +122,38 @@ static bool __devinit fam15h_power_is_internal_node0(struct pci_dev *f4) return true; } +/* + * Newer BKDG versions have an updated recommendation on how to properly + * initialize the running average range (was: 0xE, now: 0x9). This avoids + * counter saturations resulting in bogus power readings. + * We correct this value ourselves to cope with older BIOSes. + */ +static void __devinit tweak_runavg_range(struct pci_dev *pdev) +{ + u32 val; + const struct pci_device_id affected_device = { + PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) }; + + /* + * let this quirk apply only to the current version of the + * northbridge, since future versions may change the behavior + */ + if (!pci_match_id(&affected_device, pdev)) + return; + + pci_bus_read_config_dword(pdev->bus, + PCI_DEVFN(PCI_SLOT(pdev->devfn), 5), + REG_TDP_RUNNING_AVERAGE, &val); + if ((val & 0xf) != 0xe) + return; + + val &= ~0xf; + val |= 0x9; + pci_bus_write_config_dword(pdev->bus, + PCI_DEVFN(PCI_SLOT(pdev->devfn), 5), + REG_TDP_RUNNING_AVERAGE, val); +} + static void __devinit fam15h_power_init_data(struct pci_dev *f4, struct fam15h_power_data *data) { @@ -155,6 +187,13 @@ static int __devinit fam15h_power_probe(struct pci_dev *pdev, struct device *dev; int err; + /* + * though we ignore every other northbridge, we still have to + * do the tweaking on _each_ node in MCM processors as the counters + * are working hand-in-hand + */ + tweak_runavg_range(pdev); + if (!fam15h_power_is_internal_node0(pdev)) { err = -ENODEV; goto exit; diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 2d78779..7faf4a7 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -380,8 +380,7 @@ config INPUT_TWL4030_VIBRA config INPUT_TWL6040_VIBRA tristate "Support for TWL6040 Vibrator" - depends on TWL4030_CORE - select TWL6040_CORE + depends on TWL6040_CORE select INPUT_FF_MEMLESS help This option enables support for TWL6040 Vibrator Driver. diff --git a/drivers/input/misc/twl6040-vibra.c b/drivers/input/misc/twl6040-vibra.c index 45874fe..14e94f5 100644 --- a/drivers/input/misc/twl6040-vibra.c +++ b/drivers/input/misc/twl6040-vibra.c @@ -28,7 +28,7 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/workqueue.h> -#include <linux/i2c/twl.h> +#include <linux/input.h> #include <linux/mfd/twl6040.h> #include <linux/slab.h> #include <linux/delay.h> @@ -257,7 +257,7 @@ static SIMPLE_DEV_PM_OPS(twl6040_vibra_pm_ops, twl6040_vibra_suspend, NULL); static int __devinit twl6040_vibra_probe(struct platform_device *pdev) { - struct twl4030_vibra_data *pdata = pdev->dev.platform_data; + struct twl6040_vibra_data *pdata = pdev->dev.platform_data; struct vibra_info *info; int ret; diff --git a/drivers/leds/leds-atmel-pwm.c b/drivers/leds/leds-atmel-pwm.c index 800243b..64ad702 100644 --- a/drivers/leds/leds-atmel-pwm.c +++ b/drivers/leds/leds-atmel-pwm.c @@ -35,7 +35,7 @@ static void pwmled_brightness(struct led_classdev *cdev, enum led_brightness b) * NOTE: we reuse the platform_data structure of GPIO leds, * but repurpose its "gpio" number as a PWM channel number. */ -static int __init pwmled_probe(struct platform_device *pdev) +static int __devinit pwmled_probe(struct platform_device *pdev) { const struct gpio_led_platform_data *pdata; struct pwmled *leds; diff --git a/drivers/media/common/tuners/xc5000.c b/drivers/media/common/tuners/xc5000.c index 7f98984..eab2ea4 100644 --- a/drivers/media/common/tuners/xc5000.c +++ b/drivers/media/common/tuners/xc5000.c @@ -54,6 +54,7 @@ struct xc5000_priv { struct list_head hybrid_tuner_instance_list; u32 if_khz; + u32 xtal_khz; u32 freq_hz; u32 bandwidth; u8 video_standard; @@ -214,9 +215,9 @@ static const struct xc5000_fw_cfg xc5000a_1_6_114 = { .size = 12401, }; -static const struct xc5000_fw_cfg xc5000c_41_024_5_31875 = { - .name = "dvb-fe-xc5000c-41.024.5-31875.fw", - .size = 16503, +static const struct xc5000_fw_cfg xc5000c_41_024_5 = { + .name = "dvb-fe-xc5000c-41.024.5.fw", + .size = 16497, }; static inline const struct xc5000_fw_cfg *xc5000_assign_firmware(int chip_id) @@ -226,7 +227,7 @@ static inline const struct xc5000_fw_cfg *xc5000_assign_firmware(int chip_id) case XC5000A: return &xc5000a_1_6_114; case XC5000C: - return &xc5000c_41_024_5_31875; + return &xc5000c_41_024_5; } } @@ -572,6 +573,31 @@ static int xc_tune_channel(struct xc5000_priv *priv, u32 freq_hz, int mode) return found; } +static int xc_set_xtal(struct dvb_frontend *fe) +{ + struct xc5000_priv *priv = fe->tuner_priv; + int ret = XC_RESULT_SUCCESS; + + switch (priv->chip_id) { + default: + case XC5000A: + /* 32.000 MHz xtal is default */ + break; + case XC5000C: + switch (priv->xtal_khz) { + default: + case 32000: + /* 32.000 MHz xtal is default */ + break; + case 31875: + /* 31.875 MHz xtal configuration */ + ret = xc_write_reg(priv, 0x000f, 0x8081); + break; + } + break; + } + return ret; +} static int xc5000_fwupload(struct dvb_frontend *fe) { @@ -603,6 +629,8 @@ static int xc5000_fwupload(struct dvb_frontend *fe) } else { printk(KERN_INFO "xc5000: firmware uploading...\n"); ret = xc_load_i2c_sequence(fe, fw->data); + if (XC_RESULT_SUCCESS == ret) + ret = xc_set_xtal(fe); printk(KERN_INFO "xc5000: firmware upload complete...\n"); } @@ -1164,6 +1192,9 @@ struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe, priv->if_khz = cfg->if_khz; } + if (priv->xtal_khz == 0) + priv->xtal_khz = cfg->xtal_khz; + if (priv->radio_input == 0) priv->radio_input = cfg->radio_input; diff --git a/drivers/media/common/tuners/xc5000.h b/drivers/media/common/tuners/xc5000.h index 3396f8e..39a73bf 100644 --- a/drivers/media/common/tuners/xc5000.h +++ b/drivers/media/common/tuners/xc5000.h @@ -34,6 +34,7 @@ struct xc5000_config { u8 i2c_address; u32 if_khz; u8 radio_input; + u32 xtal_khz; int chip_id; }; diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c index 39696c6..0f64d71 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb/dvb-core/dvb_frontend.c @@ -1446,6 +1446,28 @@ static int set_delivery_system(struct dvb_frontend *fe, u32 desired_system) __func__); return -EINVAL; } + /* + * Get a delivery system that is compatible with DVBv3 + * NOTE: in order for this to work with softwares like Kaffeine that + * uses a DVBv5 call for DVB-S2 and a DVBv3 call to go back to + * DVB-S, drivers that support both should put the SYS_DVBS entry + * before the SYS_DVBS2, otherwise it won't switch back to DVB-S. + * The real fix is that userspace applications should not use DVBv3 + * and not trust on calling FE_SET_FRONTEND to switch the delivery + * system. + */ + ncaps = 0; + while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { + if (fe->ops.delsys[ncaps] == desired_system) { + delsys = desired_system; + break; + } + ncaps++; + } + if (delsys == SYS_UNDEFINED) { + dprintk("%s() Couldn't find a delivery system that matches %d\n", + __func__, desired_system); + } } else { /* * This is a DVBv5 call. So, it likely knows the supported @@ -1494,9 +1516,10 @@ static int set_delivery_system(struct dvb_frontend *fe, u32 desired_system) __func__); return -EINVAL; } - c->delivery_system = delsys; } + c->delivery_system = delsys; + /* * The DVBv3 or DVBv5 call is requesting a different system. So, * emulation is needed. diff --git a/drivers/media/dvb/frontends/drxk_hard.c b/drivers/media/dvb/frontends/drxk_hard.c index 36d1175..a414b1f 100644 --- a/drivers/media/dvb/frontends/drxk_hard.c +++ b/drivers/media/dvb/frontends/drxk_hard.c @@ -1520,8 +1520,10 @@ static int scu_command(struct drxk_state *state, dprintk(1, "\n"); if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || - ((resultLen > 0) && (result == NULL))) - goto error; + ((resultLen > 0) && (result == NULL))) { + printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); + return status; + } mutex_lock(&state->mutex); diff --git a/drivers/media/rc/winbond-cir.c b/drivers/media/rc/winbond-cir.c index b09c5fa..af52658 100644 --- a/drivers/media/rc/winbond-cir.c +++ b/drivers/media/rc/winbond-cir.c @@ -1046,6 +1046,7 @@ wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id) goto exit_unregister_led; } + data->dev->driver_type = RC_DRIVER_IR_RAW; data->dev->driver_name = WBCIR_NAME; data->dev->input_name = WBCIR_NAME; data->dev->input_phys = "wbcir/cir0"; diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig index f2479c5..ce1e7ba 100644 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig @@ -492,7 +492,7 @@ config VIDEO_VS6624 config VIDEO_MT9M032 tristate "MT9M032 camera sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API select VIDEO_APTINA_PLL ---help--- This driver supports MT9M032 camera sensors from Aptina, monochrome diff --git a/drivers/media/video/mt9m032.c b/drivers/media/video/mt9m032.c index 7636672..645973c 100644 --- a/drivers/media/video/mt9m032.c +++ b/drivers/media/video/mt9m032.c @@ -392,10 +392,11 @@ static int mt9m032_set_pad_format(struct v4l2_subdev *subdev, } /* Scaling is not supported, the format is thus fixed. */ - ret = mt9m032_get_pad_format(subdev, fh, fmt); + fmt->format = *__mt9m032_get_pad_format(sensor, fh, fmt->which); + ret = 0; done: - mutex_lock(&sensor->lock); + mutex_unlock(&sensor->lock); return ret; } diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 29f463c..11e44386 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -268,10 +268,17 @@ config TWL6030_PWM This is used to control charging LED brightness. config TWL6040_CORE - bool - depends on TWL4030_CORE && GENERIC_HARDIRQS + bool "Support for TWL6040 audio codec" + depends on I2C=y && GENERIC_HARDIRQS select MFD_CORE + select REGMAP_I2C default n + help + Say yes here if you want support for Texas Instruments TWL6040 audio + codec. + This driver provides common support for accessing the device, + additional drivers must be enabled in order to use the + functionality of the device (audio, vibra). config MFD_STMPE bool "Support STMicroelectronics STMPE" diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c index 1895cf9..1582c3d 100644 --- a/drivers/mfd/asic3.c +++ b/drivers/mfd/asic3.c @@ -527,7 +527,9 @@ static void asic3_gpio_set(struct gpio_chip *chip, static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset) { - return (offset < ASIC3_NUM_GPIOS) ? IRQ_BOARD_START + offset : -ENXIO; + struct asic3 *asic = container_of(chip, struct asic3, gpio); + + return (offset < ASIC3_NUM_GPIOS) ? asic->irq_base + offset : -ENXIO; } static __init int asic3_gpio_probe(struct platform_device *pdev, diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c index 95a2e54..c8aae66 100644 --- a/drivers/mfd/omap-usb-host.c +++ b/drivers/mfd/omap-usb-host.c @@ -25,7 +25,6 @@ #include <linux/clk.h> #include <linux/dma-mapping.h> #include <linux/spinlock.h> -#include <linux/gpio.h> #include <plat/usb.h> #include <linux/pm_runtime.h> @@ -502,19 +501,6 @@ static void omap_usbhs_init(struct device *dev) pm_runtime_get_sync(dev); spin_lock_irqsave(&omap->lock, flags); - if (pdata->ehci_data->phy_reset) { - if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) - gpio_request_one(pdata->ehci_data->reset_gpio_port[0], - GPIOF_OUT_INIT_LOW, "USB1 PHY reset"); - - if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) - gpio_request_one(pdata->ehci_data->reset_gpio_port[1], - GPIOF_OUT_INIT_LOW, "USB2 PHY reset"); - - /* Hold the PHY in RESET for enough time till DIR is high */ - udelay(10); - } - omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev); @@ -593,39 +579,10 @@ static void omap_usbhs_init(struct device *dev) usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT); } - if (pdata->ehci_data->phy_reset) { - /* Hold the PHY in RESET for enough time till - * PHY is settled and ready - */ - udelay(10); - - if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) - gpio_set_value - (pdata->ehci_data->reset_gpio_port[0], 1); - - if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) - gpio_set_value - (pdata->ehci_data->reset_gpio_port[1], 1); - } - spin_unlock_irqrestore(&omap->lock, flags); pm_runtime_put_sync(dev); } -static void omap_usbhs_deinit(struct device *dev) -{ - struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); - struct usbhs_omap_platform_data *pdata = &omap->platdata; - - if (pdata->ehci_data->phy_reset) { - if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) - gpio_free(pdata->ehci_data->reset_gpio_port[0]); - - if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) - gpio_free(pdata->ehci_data->reset_gpio_port[1]); - } -} - /** * usbhs_omap_probe - initialize TI-based HCDs @@ -860,7 +817,6 @@ static int __devexit usbhs_omap_remove(struct platform_device *pdev) { struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev); - omap_usbhs_deinit(&pdev->dev); iounmap(omap->tll_base); iounmap(omap->uhh_base); clk_put(omap->init_60m_fclk); diff --git a/drivers/mfd/rc5t583.c b/drivers/mfd/rc5t583.c index 99ef944..44afae0 100644 --- a/drivers/mfd/rc5t583.c +++ b/drivers/mfd/rc5t583.c @@ -80,44 +80,6 @@ static struct mfd_cell rc5t583_subdevs[] = { {.name = "rc5t583-key", } }; -int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val) -{ - struct rc5t583 *rc5t583 = dev_get_drvdata(dev); - return regmap_write(rc5t583->regmap, reg, val); -} - -int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val) -{ - struct rc5t583 *rc5t583 = dev_get_drvdata(dev); - unsigned int ival; - int ret; - ret = regmap_read(rc5t583->regmap, reg, &ival); - if (!ret) - *val = (uint8_t)ival; - return ret; -} - -int rc5t583_set_bits(struct device *dev, unsigned int reg, - unsigned int bit_mask) -{ - struct rc5t583 *rc5t583 = dev_get_drvdata(dev); - return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask); -} - -int rc5t583_clear_bits(struct device *dev, unsigned int reg, - unsigned int bit_mask) -{ - struct rc5t583 *rc5t583 = dev_get_drvdata(dev); - return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0); -} - -int rc5t583_update(struct device *dev, unsigned int reg, - unsigned int val, unsigned int mask) -{ - struct rc5t583 *rc5t583 = dev_get_drvdata(dev); - return regmap_update_bits(rc5t583->regmap, reg, mask, val); -} - static int __rc5t583_set_ext_pwrreq1_control(struct device *dev, int id, int ext_pwr, int slots) { @@ -197,6 +159,7 @@ int rc5t583_ext_power_req_config(struct device *dev, int ds_id, ds_id, ext_pwr_req); return 0; } +EXPORT_SYMBOL(rc5t583_ext_power_req_config); static int rc5t583_clear_ext_power_req(struct rc5t583 *rc5t583, struct rc5t583_platform_data *pdata) diff --git a/drivers/mfd/twl6040-core.c b/drivers/mfd/twl6040-core.c index b2d8e51..2d6beda 100644 --- a/drivers/mfd/twl6040-core.c +++ b/drivers/mfd/twl6040-core.c @@ -30,7 +30,9 @@ #include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/delay.h> -#include <linux/i2c/twl.h> +#include <linux/i2c.h> +#include <linux/regmap.h> +#include <linux/err.h> #include <linux/mfd/core.h> #include <linux/mfd/twl6040.h> @@ -39,7 +41,7 @@ int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg) { int ret; - u8 val = 0; + unsigned int val; mutex_lock(&twl6040->io_mutex); /* Vibra control registers from cache */ @@ -47,7 +49,7 @@ int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg) reg == TWL6040_REG_VIBCTLR)) { val = twl6040->vibra_ctrl_cache[VIBRACTRL_MEMBER(reg)]; } else { - ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg); + ret = regmap_read(twl6040->regmap, reg, &val); if (ret < 0) { mutex_unlock(&twl6040->io_mutex); return ret; @@ -64,7 +66,7 @@ int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val) int ret; mutex_lock(&twl6040->io_mutex); - ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg); + ret = regmap_write(twl6040->regmap, reg, val); /* Cache the vibra control registers */ if (reg == TWL6040_REG_VIBCTLL || reg == TWL6040_REG_VIBCTLR) twl6040->vibra_ctrl_cache[VIBRACTRL_MEMBER(reg)] = val; @@ -77,16 +79,9 @@ EXPORT_SYMBOL(twl6040_reg_write); int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask) { int ret; - u8 val; mutex_lock(&twl6040->io_mutex); - ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg); - if (ret) - goto out; - - val |= mask; - ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg); -out: + ret = regmap_update_bits(twl6040->regmap, reg, mask, mask); mutex_unlock(&twl6040->io_mutex); return ret; } @@ -95,16 +90,9 @@ EXPORT_SYMBOL(twl6040_set_bits); int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask) { int ret; - u8 val; mutex_lock(&twl6040->io_mutex); - ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg); - if (ret) - goto out; - - val &= ~mask; - ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg); -out: + ret = regmap_update_bits(twl6040->regmap, reg, mask, 0); mutex_unlock(&twl6040->io_mutex); return ret; } @@ -494,32 +482,58 @@ static struct resource twl6040_codec_rsrc[] = { }, }; -static int __devinit twl6040_probe(struct platform_device *pdev) +static bool twl6040_readable_reg(struct device *dev, unsigned int reg) { - struct twl4030_audio_data *pdata = pdev->dev.platform_data; + /* Register 0 is not readable */ + if (!reg) + return false; + return true; +} + +static struct regmap_config twl6040_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = TWL6040_REG_STATUS, /* 0x2e */ + + .readable_reg = twl6040_readable_reg, +}; + +static int __devinit twl6040_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct twl6040_platform_data *pdata = client->dev.platform_data; struct twl6040 *twl6040; struct mfd_cell *cell = NULL; int ret, children = 0; if (!pdata) { - dev_err(&pdev->dev, "Platform data is missing\n"); + dev_err(&client->dev, "Platform data is missing\n"); return -EINVAL; } /* In order to operate correctly we need valid interrupt config */ - if (!pdata->naudint_irq || !pdata->irq_base) { - dev_err(&pdev->dev, "Invalid IRQ configuration\n"); + if (!client->irq || !pdata->irq_base) { + dev_err(&client->dev, "Invalid IRQ configuration\n"); return -EINVAL; } - twl6040 = kzalloc(sizeof(struct twl6040), GFP_KERNEL); - if (!twl6040) - return -ENOMEM; + twl6040 = devm_kzalloc(&client->dev, sizeof(struct twl6040), + GFP_KERNEL); + if (!twl6040) { + ret = -ENOMEM; + goto err; + } + + twl6040->regmap = regmap_init_i2c(client, &twl6040_regmap_config); + if (IS_ERR(twl6040->regmap)) { + ret = PTR_ERR(twl6040->regmap); + goto err; + } - platform_set_drvdata(pdev, twl6040); + i2c_set_clientdata(client, twl6040); - twl6040->dev = &pdev->dev; - twl6040->irq = pdata->naudint_irq; + twl6040->dev = &client->dev; + twl6040->irq = client->irq; twl6040->irq_base = pdata->irq_base; mutex_init(&twl6040->mutex); @@ -588,12 +602,12 @@ static int __devinit twl6040_probe(struct platform_device *pdev) } if (children) { - ret = mfd_add_devices(&pdev->dev, pdev->id, twl6040->cells, + ret = mfd_add_devices(&client->dev, -1, twl6040->cells, children, NULL, 0); if (ret) goto mfd_err; } else { - dev_err(&pdev->dev, "No platform data found for children\n"); + dev_err(&client->dev, "No platform data found for children\n"); ret = -ENODEV; goto mfd_err; } @@ -608,14 +622,15 @@ gpio2_err: if (gpio_is_valid(twl6040->audpwron)) gpio_free(twl6040->audpwron); gpio1_err: - platform_set_drvdata(pdev, NULL); - kfree(twl6040); + i2c_set_clientdata(client, NULL); + regmap_exit(twl6040->regmap); +err: return ret; } -static int __devexit twl6040_remove(struct platform_device *pdev) +static int __devexit twl6040_remove(struct i2c_client *client) { - struct twl6040 *twl6040 = platform_get_drvdata(pdev); + struct twl6040 *twl6040 = i2c_get_clientdata(client); if (twl6040->power_count) twl6040_power(twl6040, 0); @@ -626,23 +641,30 @@ static int __devexit twl6040_remove(struct platform_device *pdev) free_irq(twl6040->irq_base + TWL6040_IRQ_READY, twl6040); twl6040_irq_exit(twl6040); - mfd_remove_devices(&pdev->dev); - platform_set_drvdata(pdev, NULL); - kfree(twl6040); + mfd_remove_devices(&client->dev); + i2c_set_clientdata(client, NULL); + regmap_exit(twl6040->regmap); return 0; } -static struct platform_driver twl6040_driver = { +static const struct i2c_device_id twl6040_i2c_id[] = { + { "twl6040", 0, }, + { }, +}; +MODULE_DEVICE_TABLE(i2c, twl6040_i2c_id); + +static struct i2c_driver twl6040_driver = { + .driver = { + .name = "twl6040", + .owner = THIS_MODULE, + }, .probe = twl6040_probe, .remove = __devexit_p(twl6040_remove), - .driver = { - .owner = THIS_MODULE, - .name = "twl6040", - }, + .id_table = twl6040_i2c_id, }; -module_platform_driver(twl6040_driver); +module_i2c_driver(twl6040_driver); MODULE_DESCRIPTION("TWL6040 MFD"); MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>"); diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c index b180965..dabec55 100644 --- a/drivers/mmc/card/block.c +++ b/drivers/mmc/card/block.c @@ -873,7 +873,7 @@ static int mmc_blk_issue_secdiscard_rq(struct mmc_queue *mq, { struct mmc_blk_data *md = mq->data; struct mmc_card *card = md->queue.card; - unsigned int from, nr, arg; + unsigned int from, nr, arg, trim_arg, erase_arg; int err = 0, type = MMC_BLK_SECDISCARD; if (!(mmc_can_secure_erase_trim(card) || mmc_can_sanitize(card))) { @@ -881,20 +881,26 @@ static int mmc_blk_issue_secdiscard_rq(struct mmc_queue *mq, goto out; } + from = blk_rq_pos(req); + nr = blk_rq_sectors(req); + /* The sanitize operation is supported at v4.5 only */ if (mmc_can_sanitize(card)) { - err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, - EXT_CSD_SANITIZE_START, 1, 0); - goto out; + erase_arg = MMC_ERASE_ARG; + trim_arg = MMC_TRIM_ARG; + } else { + erase_arg = MMC_SECURE_ERASE_ARG; + trim_arg = MMC_SECURE_TRIM1_ARG; } - from = blk_rq_pos(req); - nr = blk_rq_sectors(req); - - if (mmc_can_trim(card) && !mmc_erase_group_aligned(card, from, nr)) - arg = MMC_SECURE_TRIM1_ARG; - else - arg = MMC_SECURE_ERASE_ARG; + if (mmc_erase_group_aligned(card, from, nr)) + arg = erase_arg; + else if (mmc_can_trim(card)) + arg = trim_arg; + else { + err = -EINVAL; + goto out; + } retry: if (card->quirks & MMC_QUIRK_INAND_CMD38) { err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, @@ -904,25 +910,41 @@ retry: INAND_CMD38_ARG_SECERASE, 0); if (err) - goto out; + goto out_retry; } + err = mmc_erase(card, from, nr, arg); - if (!err && arg == MMC_SECURE_TRIM1_ARG) { + if (err == -EIO) + goto out_retry; + if (err) + goto out; + + if (arg == MMC_SECURE_TRIM1_ARG) { if (card->quirks & MMC_QUIRK_INAND_CMD38) { err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, INAND_CMD38_ARG_EXT_CSD, INAND_CMD38_ARG_SECTRIM2, 0); if (err) - goto out; + goto out_retry; } + err = mmc_erase(card, from, nr, MMC_SECURE_TRIM2_ARG); + if (err == -EIO) + goto out_retry; + if (err) + goto out; } -out: - if (err == -EIO && !mmc_blk_reset(md, card->host, type)) + + if (mmc_can_sanitize(card)) + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_SANITIZE_START, 1, 0); +out_retry: + if (err && !mmc_blk_reset(md, card->host, type)) goto retry; if (!err) mmc_blk_reset_success(md, type); +out: spin_lock_irq(&md->lock); __blk_end_request(req, err, blk_rq_bytes(req)); spin_unlock_irq(&md->lock); @@ -1802,7 +1824,7 @@ static void mmc_blk_remove(struct mmc_card *card) } #ifdef CONFIG_PM -static int mmc_blk_suspend(struct mmc_card *card, pm_message_t state) +static int mmc_blk_suspend(struct mmc_card *card) { struct mmc_blk_data *part_md; struct mmc_blk_data *md = mmc_get_drvdata(card); diff --git a/drivers/mmc/card/queue.c b/drivers/mmc/card/queue.c index 2517547..996f8e3 100644 --- a/drivers/mmc/card/queue.c +++ b/drivers/mmc/card/queue.c @@ -139,7 +139,7 @@ static void mmc_queue_setup_discard(struct request_queue *q, queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, q); q->limits.max_discard_sectors = max_discard; - if (card->erased_byte == 0) + if (card->erased_byte == 0 && !mmc_can_discard(card)) q->limits.discard_zeroes_data = 1; q->limits.discard_granularity = card->pref_erase << 9; /* granularity must not be greater than max. discard */ diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c index 3f60606..c60cee9 100644 --- a/drivers/mmc/core/bus.c +++ b/drivers/mmc/core/bus.c @@ -122,14 +122,14 @@ static int mmc_bus_remove(struct device *dev) return 0; } -static int mmc_bus_suspend(struct device *dev, pm_message_t state) +static int mmc_bus_suspend(struct device *dev) { struct mmc_driver *drv = to_mmc_driver(dev->driver); struct mmc_card *card = mmc_dev_to_card(dev); int ret = 0; if (dev->driver && drv->suspend) - ret = drv->suspend(card, state); + ret = drv->suspend(card); return ret; } @@ -165,20 +165,14 @@ static int mmc_runtime_idle(struct device *dev) return pm_runtime_suspend(dev); } +#endif /* !CONFIG_PM_RUNTIME */ + static const struct dev_pm_ops mmc_bus_pm_ops = { - .runtime_suspend = mmc_runtime_suspend, - .runtime_resume = mmc_runtime_resume, - .runtime_idle = mmc_runtime_idle, + SET_RUNTIME_PM_OPS(mmc_runtime_suspend, mmc_runtime_resume, + mmc_runtime_idle) + SET_SYSTEM_SLEEP_PM_OPS(mmc_bus_suspend, mmc_bus_resume) }; -#define MMC_PM_OPS_PTR (&mmc_bus_pm_ops) - -#else /* !CONFIG_PM_RUNTIME */ - -#define MMC_PM_OPS_PTR NULL - -#endif /* !CONFIG_PM_RUNTIME */ - static struct bus_type mmc_bus_type = { .name = "mmc", .dev_attrs = mmc_dev_attrs, @@ -186,9 +180,7 @@ static struct bus_type mmc_bus_type = { .uevent = mmc_bus_uevent, .probe = mmc_bus_probe, .remove = mmc_bus_remove, - .suspend = mmc_bus_suspend, - .resume = mmc_bus_resume, - .pm = MMC_PM_OPS_PTR, + .pm = &mmc_bus_pm_ops, }; int mmc_register_bus(void) diff --git a/drivers/mmc/core/cd-gpio.c b/drivers/mmc/core/cd-gpio.c index 29de31e..2c14be7 100644 --- a/drivers/mmc/core/cd-gpio.c +++ b/drivers/mmc/core/cd-gpio.c @@ -12,6 +12,7 @@ #include <linux/gpio.h> #include <linux/interrupt.h> #include <linux/jiffies.h> +#include <linux/mmc/cd-gpio.h> #include <linux/mmc/host.h> #include <linux/module.h> #include <linux/slab.h> diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 7474c47..ba821fe 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -1409,7 +1409,10 @@ static unsigned int mmc_mmc_erase_timeout(struct mmc_card *card, { unsigned int erase_timeout; - if (card->ext_csd.erase_group_def & 1) { + if (arg == MMC_DISCARD_ARG || + (arg == MMC_TRIM_ARG && card->ext_csd.rev >= 6)) { + erase_timeout = card->ext_csd.trim_timeout; + } else if (card->ext_csd.erase_group_def & 1) { /* High Capacity Erase Group Size uses HC timeouts */ if (arg == MMC_TRIM_ARG) erase_timeout = card->ext_csd.trim_timeout; @@ -1681,8 +1684,6 @@ int mmc_can_trim(struct mmc_card *card) { if (card->ext_csd.sec_feature_support & EXT_CSD_SEC_GB_CL_EN) return 1; - if (mmc_can_discard(card)) - return 1; return 0; } EXPORT_SYMBOL(mmc_can_trim); @@ -1701,6 +1702,8 @@ EXPORT_SYMBOL(mmc_can_discard); int mmc_can_sanitize(struct mmc_card *card) { + if (!mmc_can_trim(card) && !mmc_can_erase(card)) + return 0; if (card->ext_csd.sec_feature_support & EXT_CSD_SEC_SANITIZE) return 1; return 0; @@ -2235,6 +2238,7 @@ int mmc_cache_ctrl(struct mmc_host *host, u8 enable) mmc_card_is_removable(host)) return err; + mmc_claim_host(host); if (card && mmc_card_mmc(card) && (card->ext_csd.cache_size > 0)) { enable = !!enable; @@ -2252,6 +2256,7 @@ int mmc_cache_ctrl(struct mmc_host *host, u8 enable) card->ext_csd.cache_ctrl = enable; } } + mmc_release_host(host); return err; } @@ -2269,49 +2274,32 @@ int mmc_suspend_host(struct mmc_host *host) cancel_delayed_work(&host->detect); mmc_flush_scheduled_work(); - if (mmc_try_claim_host(host)) { - err = mmc_cache_ctrl(host, 0); - mmc_release_host(host); - } else { - err = -EBUSY; - } + err = mmc_cache_ctrl(host, 0); if (err) goto out; mmc_bus_get(host); if (host->bus_ops && !host->bus_dead) { - /* - * A long response time is not acceptable for device drivers - * when doing suspend. Prevent mmc_claim_host in the suspend - * sequence, to potentially wait "forever" by trying to - * pre-claim the host. - */ - if (mmc_try_claim_host(host)) { - if (host->bus_ops->suspend) { - err = host->bus_ops->suspend(host); - } - mmc_release_host(host); + if (host->bus_ops->suspend) + err = host->bus_ops->suspend(host); - if (err == -ENOSYS || !host->bus_ops->resume) { - /* - * We simply "remove" the card in this case. - * It will be redetected on resume. (Calling - * bus_ops->remove() with a claimed host can - * deadlock.) - */ - if (host->bus_ops->remove) - host->bus_ops->remove(host); - mmc_claim_host(host); - mmc_detach_bus(host); - mmc_power_off(host); - mmc_release_host(host); - host->pm_flags = 0; - err = 0; - } - } else { - err = -EBUSY; + if (err == -ENOSYS || !host->bus_ops->resume) { + /* + * We simply "remove" the card in this case. + * It will be redetected on resume. (Calling + * bus_ops->remove() with a claimed host can + * deadlock.) + */ + if (host->bus_ops->remove) + host->bus_ops->remove(host); + mmc_claim_host(host); + mmc_detach_bus(host); + mmc_power_off(host); + mmc_release_host(host); + host->pm_flags = 0; + err = 0; } } mmc_bus_put(host); diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index bf3c9b4..ab3fc46 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -526,8 +526,10 @@ static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) return -ENODEV; sg_len = dw_mci_pre_dma_transfer(host, data, 0); - if (sg_len < 0) + if (sg_len < 0) { + host->dma_ops->stop(host); return sg_len; + } host->using_dma = 1; @@ -1879,7 +1881,8 @@ static void dw_mci_init_dma(struct dw_mci *host) if (!host->dma_ops) goto no_dma; - if (host->dma_ops->init) { + if (host->dma_ops->init && host->dma_ops->start && + host->dma_ops->stop && host->dma_ops->cleanup) { if (host->dma_ops->init(host)) { dev_err(&host->dev, "%s: Unable to initialize " "DMA Controller.\n", __func__); diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 5c2b1c1..56d4499 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -249,7 +249,7 @@ static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, * the pbias cell programming support is still missing when * booting with Device tree */ - if (of_have_populated_dt() && !vdd) + if (dev->of_node && !vdd) return 0; if (mmc_slot(host).before_set_reg) @@ -1549,7 +1549,7 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) * can't be allowed when booting with device * tree. */ - (!of_have_populated_dt())) { + !host->dev->of_node) { /* * The mmc_select_voltage fn of the core does * not seem to set the power_mode to @@ -1741,7 +1741,7 @@ static const struct of_device_id omap_mmc_of_match[] = { .data = &omap4_reg_offset, }, {}, -} +}; MODULE_DEVICE_TABLE(of, omap_mmc_of_match); static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 6193a0d..8abdaf6 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -467,8 +467,7 @@ static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev) clk_prepare_enable(clk); pltfm_host->clk = clk; - if (!is_imx25_esdhc(imx_data)) - host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; + host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 9aa77f3..ccefdeb 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -147,7 +147,7 @@ static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) u32 present, irqs; if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || - !mmc_card_is_removable(host->mmc)) + (host->mmc->caps & MMC_CAP_NONREMOVABLE)) return; present = sdhci_readl(host, SDHCI_PRESENT_STATE) & diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d20f133..111569c 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -991,8 +991,8 @@ static void pci_restore_config_dword(struct pci_dev *pdev, int offset, } } -static void pci_restore_config_space(struct pci_dev *pdev, int start, int end, - int retry) +static void pci_restore_config_space_range(struct pci_dev *pdev, + int start, int end, int retry) { int index; @@ -1002,6 +1002,18 @@ static void pci_restore_config_space(struct pci_dev *pdev, int start, int end, retry); } +static void pci_restore_config_space(struct pci_dev *pdev) +{ + if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { + pci_restore_config_space_range(pdev, 10, 15, 0); + /* Restore BARs before the command register. */ + pci_restore_config_space_range(pdev, 4, 9, 10); + pci_restore_config_space_range(pdev, 0, 3, 0); + } else { + pci_restore_config_space_range(pdev, 0, 15, 0); + } +} + /** * pci_restore_state - Restore the saved state of a PCI device * @dev: - PCI device that we're dealing with @@ -1015,13 +1027,7 @@ void pci_restore_state(struct pci_dev *dev) pci_restore_pcie_state(dev); pci_restore_ats_state(dev); - pci_restore_config_space(dev, 10, 15, 0); - /* - * The Base Address register should be programmed before the command - * register(s) - */ - pci_restore_config_space(dev, 4, 9, 10); - pci_restore_config_space(dev, 0, 3, 0); + pci_restore_config_space(dev); pci_restore_pcix_state(dev); pci_restore_msi_state(dev); diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f73a5ea..de6e684 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -83,6 +83,8 @@ config PINCTRL_COH901 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 ports of 8 GPIO pins each. +source "drivers/pinctrl/spear/Kconfig" + endmenu endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 8e3c95a..03c97e2 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -19,3 +19,5 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o + +obj-$(CONFIG_PLAT_SPEAR) += spear/ diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig new file mode 100644 index 0000000..6a2596b --- /dev/null +++ b/drivers/pinctrl/spear/Kconfig @@ -0,0 +1,34 @@ +# +# ST Microelectronics SPEAr PINCTRL drivers +# + +if PLAT_SPEAR + +config PINCTRL_SPEAR + bool + depends on OF + select PINMUX + help + This enables pin control drivers for SPEAr Platform + +config PINCTRL_SPEAR3XX + bool + depends on ARCH_SPEAR3XX + select PINCTRL_SPEAR + +config PINCTRL_SPEAR300 + bool "ST Microelectronics SPEAr300 SoC pin controller driver" + depends on MACH_SPEAR300 + select PINCTRL_SPEAR3XX + +config PINCTRL_SPEAR310 + bool "ST Microelectronics SPEAr310 SoC pin controller driver" + depends on MACH_SPEAR310 + select PINCTRL_SPEAR3XX + +config PINCTRL_SPEAR320 + bool "ST Microelectronics SPEAr320 SoC pin controller driver" + depends on MACH_SPEAR320 + select PINCTRL_SPEAR3XX + +endif diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile new file mode 100644 index 0000000..15dcb85 --- /dev/null +++ b/drivers/pinctrl/spear/Makefile @@ -0,0 +1,7 @@ +# SPEAr pinmux support + +obj-$(CONFIG_PINCTRL_SPEAR) += pinctrl-spear.o +obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o +obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o +obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o +obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c new file mode 100644 index 0000000..5ae50aa --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear.c @@ -0,0 +1,354 @@ +/* + * Driver for the ST Microelectronics SPEAr pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * Inspired from: + * - U300 Pinctl drivers + * - Tegra Pinctl drivers + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "pinctrl-spear.h" + +#define DRIVER_NAME "spear-pinmux" + +static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg) +{ + return readl_relaxed(pmx->vbase + reg); +} + +static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) +{ + writel_relaxed(val, pmx->vbase + reg); +} + +static int set_mode(struct spear_pmx *pmx, int mode) +{ + struct spear_pmx_mode *pmx_mode = NULL; + int i; + u32 val; + + if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes) + return -EINVAL; + + for (i = 0; i < pmx->machdata->npmx_modes; i++) { + if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) { + pmx_mode = pmx->machdata->pmx_modes[i]; + break; + } + } + + if (!pmx_mode) + return -EINVAL; + + val = pmx_readl(pmx, pmx_mode->reg); + val &= ~pmx_mode->mask; + val |= pmx_mode->val; + pmx_writel(pmx, val, pmx_mode->reg); + + pmx->machdata->mode = pmx_mode->mode; + dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n", + pmx_mode->name ? pmx_mode->name : "no_name", + pmx_mode->reg); + + return 0; +} + +void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg) +{ + struct spear_pingroup *pgroup; + struct spear_modemux *modemux; + int i, j, group; + + for (group = 0; group < machdata->ngroups; group++) { + pgroup = machdata->groups[group]; + + for (i = 0; i < pgroup->nmodemuxs; i++) { + modemux = &pgroup->modemuxs[i]; + + for (j = 0; j < modemux->nmuxregs; j++) + if (modemux->muxregs[j].reg == 0xFFFF) + modemux->muxregs[j].reg = reg; + } + } +} + +static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->machdata->ngroups; +} + +static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->machdata->groups[group]->name; +} + +static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, const unsigned **pins, unsigned *num_pins) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + *pins = pmx->machdata->groups[group]->pins; + *num_pins = pmx->machdata->groups[group]->npins; + + return 0; +} + +static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned offset) +{ + seq_printf(s, " " DRIVER_NAME); +} + +int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct device_node *np; + struct property *prop; + const char *function, *group; + int ret, index = 0, count = 0; + + /* calculate number of maps required */ + for_each_child_of_node(np_config, np) { + ret = of_property_read_string(np, "st,function", &function); + if (ret < 0) + return ret; + + ret = of_property_count_strings(np, "st,pins"); + if (ret < 0) + return ret; + + count += ret; + } + + if (!count) { + dev_err(pmx->dev, "No child nodes passed via DT\n"); + return -ENODEV; + } + + *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); + if (!*map) + return -ENOMEM; + + for_each_child_of_node(np_config, np) { + of_property_read_string(np, "st,function", &function); + of_property_for_each_string(np, "st,pins", prop, group) { + (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[index].data.mux.group = group; + (*map)[index].data.mux.function = function; + index++; + } + } + + *num_maps = count; + + return 0; +} + +void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + kfree(map); +} + +static struct pinctrl_ops spear_pinctrl_ops = { + .get_groups_count = spear_pinctrl_get_groups_cnt, + .get_group_name = spear_pinctrl_get_group_name, + .get_group_pins = spear_pinctrl_get_group_pins, + .pin_dbg_show = spear_pinctrl_pin_dbg_show, + .dt_node_to_map = spear_pinctrl_dt_node_to_map, + .dt_free_map = spear_pinctrl_dt_free_map, +}; + +static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->machdata->nfunctions; +} + +static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->machdata->functions[function]->name; +} + +static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, const char *const **groups, + unsigned * const ngroups) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + *groups = pmx->machdata->functions[function]->groups; + *ngroups = pmx->machdata->functions[function]->ngroups; + + return 0; +} + +static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev, + unsigned function, unsigned group, bool enable) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct spear_pingroup *pgroup; + const struct spear_modemux *modemux; + struct spear_muxreg *muxreg; + u32 val, temp; + int i, j; + bool found = false; + + pgroup = pmx->machdata->groups[group]; + + for (i = 0; i < pgroup->nmodemuxs; i++) { + modemux = &pgroup->modemuxs[i]; + + /* SoC have any modes */ + if (pmx->machdata->modes_supported) { + if (!(pmx->machdata->mode & modemux->modes)) + continue; + } + + found = true; + for (j = 0; j < modemux->nmuxregs; j++) { + muxreg = &modemux->muxregs[j]; + + val = pmx_readl(pmx, muxreg->reg); + val &= ~muxreg->mask; + + if (enable) + temp = muxreg->val; + else + temp = ~muxreg->val; + + val |= temp; + pmx_writel(pmx, val, muxreg->reg); + } + } + + if (!found) { + dev_err(pmx->dev, "pinmux group: %s not supported\n", + pgroup->name); + return -ENODEV; + } + + return 0; +} + +static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, + unsigned group) +{ + return spear_pinctrl_endisable(pctldev, function, group, true); +} + +static void spear_pinctrl_disable(struct pinctrl_dev *pctldev, + unsigned function, unsigned group) +{ + spear_pinctrl_endisable(pctldev, function, group, false); +} + +static struct pinmux_ops spear_pinmux_ops = { + .get_functions_count = spear_pinctrl_get_funcs_count, + .get_function_name = spear_pinctrl_get_func_name, + .get_function_groups = spear_pinctrl_get_func_groups, + .enable = spear_pinctrl_enable, + .disable = spear_pinctrl_disable, +}; + +static struct pinctrl_desc spear_pinctrl_desc = { + .name = DRIVER_NAME, + .pctlops = &spear_pinctrl_ops, + .pmxops = &spear_pinmux_ops, + .owner = THIS_MODULE, +}; + +int __devinit spear_pinctrl_probe(struct platform_device *pdev, + struct spear_pinctrl_machdata *machdata) +{ + struct device_node *np = pdev->dev.of_node; + struct resource *res; + struct spear_pmx *pmx; + + if (!machdata) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) { + dev_err(&pdev->dev, "Can't alloc spear_pmx\n"); + return -ENOMEM; + } + + pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!pmx->vbase) { + dev_err(&pdev->dev, "Couldn't ioremap at index 0\n"); + return -ENODEV; + } + + pmx->dev = &pdev->dev; + pmx->machdata = machdata; + + /* configure mode, if supported by SoC */ + if (machdata->modes_supported) { + int mode = 0; + + if (of_property_read_u32(np, "st,pinmux-mode", &mode)) { + dev_err(&pdev->dev, "OF: pinmux mode not passed\n"); + return -EINVAL; + } + + if (set_mode(pmx, mode)) { + dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n", + mode); + return -EINVAL; + } + } + + platform_set_drvdata(pdev, pmx); + + spear_pinctrl_desc.pins = machdata->pins; + spear_pinctrl_desc.npins = machdata->npins; + + pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx); + if (IS_ERR(pmx->pctl)) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return PTR_ERR(pmx->pctl); + } + + return 0; +} + +int __devexit spear_pinctrl_remove(struct platform_device *pdev) +{ + struct spear_pmx *pmx = platform_get_drvdata(pdev); + + pinctrl_unregister(pmx->pctl); + + return 0; +} diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h new file mode 100644 index 0000000..47a6b5b --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear.h @@ -0,0 +1,142 @@ +/* + * Driver header file for the ST Microelectronics SPEAr pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PINMUX_SPEAR_H__ +#define __PINMUX_SPEAR_H__ + +#include <linux/pinctrl/pinctrl.h> +#include <linux/types.h> + +struct platform_device; +struct device; + +/** + * struct spear_pmx_mode - SPEAr pmx mode + * @name: name of pmx mode + * @mode: mode id + * @reg: register for configuring this mode + * @mask: mask of this mode in reg + * @val: val to be configured at reg after doing (val & mask) + */ +struct spear_pmx_mode { + const char *const name; + u16 mode; + u16 reg; + u16 mask; + u32 val; +}; + +/** + * struct spear_muxreg - SPEAr mux reg configuration + * @reg: register offset + * @mask: mask bits + * @val: val to be written on mask bits + */ +struct spear_muxreg { + u16 reg; + u32 mask; + u32 val; +}; + +/** + * struct spear_modemux - SPEAr mode mux configuration + * @modes: mode ids supported by this group of muxregs + * @nmuxregs: number of muxreg configurations to be done for modes + * @muxregs: array of muxreg configurations to be done for modes + */ +struct spear_modemux { + u16 modes; + u8 nmuxregs; + struct spear_muxreg *muxregs; +}; + +/** + * struct spear_pingroup - SPEAr pin group configurations + * @name: name of pin group + * @pins: array containing pin numbers + * @npins: size of pins array + * @modemuxs: array of modemux configurations for this pin group + * @nmodemuxs: size of array modemuxs + * + * A representation of a group of pins in the SPEAr pin controller. Each group + * allows some parameter or parameters to be configured. + */ +struct spear_pingroup { + const char *name; + const unsigned *pins; + unsigned npins; + struct spear_modemux *modemuxs; + unsigned nmodemuxs; +}; + +/** + * struct spear_function - SPEAr pinctrl mux function + * @name: The name of the function, exported to pinctrl core. + * @groups: An array of pin groups that may select this function. + * @ngroups: The number of entries in @groups. + */ +struct spear_function { + const char *name; + const char *const *groups; + unsigned ngroups; +}; + +/** + * struct spear_pinctrl_machdata - SPEAr pin controller machine driver + * configuration + * @pins: An array describing all pins the pin controller affects. + * All pins which are also GPIOs must be listed first within the *array, + * and be numbered identically to the GPIO controller's *numbering. + * @npins: The numbmer of entries in @pins. + * @functions: An array describing all mux functions the SoC supports. + * @nfunctions: The numbmer of entries in @functions. + * @groups: An array describing all pin groups the pin SoC supports. + * @ngroups: The numbmer of entries in @groups. + * + * @modes_supported: Does SoC support modes + * @mode: mode configured from probe + * @pmx_modes: array of modes supported by SoC + * @npmx_modes: number of entries in pmx_modes. + */ +struct spear_pinctrl_machdata { + const struct pinctrl_pin_desc *pins; + unsigned npins; + struct spear_function **functions; + unsigned nfunctions; + struct spear_pingroup **groups; + unsigned ngroups; + + bool modes_supported; + u16 mode; + struct spear_pmx_mode **pmx_modes; + unsigned npmx_modes; +}; + +/** + * struct spear_pmx - SPEAr pinctrl mux + * @dev: pointer to struct dev of platform_device registered + * @pctl: pointer to struct pinctrl_dev + * @machdata: pointer to SoC or machine specific structure + * @vbase: virtual base address of pinmux controller + */ +struct spear_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + struct spear_pinctrl_machdata *machdata; + void __iomem *vbase; +}; + +/* exported routines */ +void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg); +int __devinit spear_pinctrl_probe(struct platform_device *pdev, + struct spear_pinctrl_machdata *machdata); +int __devexit spear_pinctrl_remove(struct platform_device *pdev); +#endif /* __PINMUX_SPEAR_H__ */ diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c new file mode 100644 index 0000000..9c82a35 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear300.c @@ -0,0 +1,708 @@ +/* + * Driver for the ST Microelectronics SPEAr300 pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include "pinctrl-spear3xx.h" + +#define DRIVER_NAME "spear300-pinmux" + +/* addresses */ +#define PMX_CONFIG_REG 0x00 +#define MODE_CONFIG_REG 0x04 + +/* modes */ +#define NAND_MODE (1 << 0) +#define NOR_MODE (1 << 1) +#define PHOTO_FRAME_MODE (1 << 2) +#define LEND_IP_PHONE_MODE (1 << 3) +#define HEND_IP_PHONE_MODE (1 << 4) +#define LEND_WIFI_PHONE_MODE (1 << 5) +#define HEND_WIFI_PHONE_MODE (1 << 6) +#define ATA_PABX_WI2S_MODE (1 << 7) +#define ATA_PABX_I2S_MODE (1 << 8) +#define CAML_LCDW_MODE (1 << 9) +#define CAMU_LCD_MODE (1 << 10) +#define CAMU_WLCD_MODE (1 << 11) +#define CAML_LCD_MODE (1 << 12) + +static struct spear_pmx_mode pmx_mode_nand = { + .name = "nand", + .mode = NAND_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x00, +}; + +static struct spear_pmx_mode pmx_mode_nor = { + .name = "nor", + .mode = NOR_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x01, +}; + +static struct spear_pmx_mode pmx_mode_photo_frame = { + .name = "photo frame mode", + .mode = PHOTO_FRAME_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x02, +}; + +static struct spear_pmx_mode pmx_mode_lend_ip_phone = { + .name = "lend ip phone mode", + .mode = LEND_IP_PHONE_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x03, +}; + +static struct spear_pmx_mode pmx_mode_hend_ip_phone = { + .name = "hend ip phone mode", + .mode = HEND_IP_PHONE_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x04, +}; + +static struct spear_pmx_mode pmx_mode_lend_wifi_phone = { + .name = "lend wifi phone mode", + .mode = LEND_WIFI_PHONE_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x05, +}; + +static struct spear_pmx_mode pmx_mode_hend_wifi_phone = { + .name = "hend wifi phone mode", + .mode = HEND_WIFI_PHONE_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x06, +}; + +static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = { + .name = "ata pabx wi2s mode", + .mode = ATA_PABX_WI2S_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x07, +}; + +static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = { + .name = "ata pabx i2s mode", + .mode = ATA_PABX_I2S_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x08, +}; + +static struct spear_pmx_mode pmx_mode_caml_lcdw = { + .name = "caml lcdw mode", + .mode = CAML_LCDW_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x0C, +}; + +static struct spear_pmx_mode pmx_mode_camu_lcd = { + .name = "camu lcd mode", + .mode = CAMU_LCD_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x0D, +}; + +static struct spear_pmx_mode pmx_mode_camu_wlcd = { + .name = "camu wlcd mode", + .mode = CAMU_WLCD_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0xE, +}; + +static struct spear_pmx_mode pmx_mode_caml_lcd = { + .name = "caml lcd mode", + .mode = CAML_LCD_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x0F, +}; + +static struct spear_pmx_mode *spear300_pmx_modes[] = { + &pmx_mode_nand, + &pmx_mode_nor, + &pmx_mode_photo_frame, + &pmx_mode_lend_ip_phone, + &pmx_mode_hend_ip_phone, + &pmx_mode_lend_wifi_phone, + &pmx_mode_hend_wifi_phone, + &pmx_mode_ata_pabx_wi2s, + &pmx_mode_ata_pabx_i2s, + &pmx_mode_caml_lcdw, + &pmx_mode_camu_lcd, + &pmx_mode_camu_wlcd, + &pmx_mode_caml_lcd, +}; + +/* fsmc_2chips_pins */ +static const unsigned fsmc_2chips_pins[] = { 1, 97 }; +static struct spear_muxreg fsmc_2chips_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_FIRDA_MASK, + .val = 0, + }, +}; + +static struct spear_modemux fsmc_2chips_modemux[] = { + { + .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, + .muxregs = fsmc_2chips_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg), + }, +}; + +static struct spear_pingroup fsmc_2chips_pingroup = { + .name = "fsmc_2chips_grp", + .pins = fsmc_2chips_pins, + .npins = ARRAY_SIZE(fsmc_2chips_pins), + .modemuxs = fsmc_2chips_modemux, + .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux), +}; + +/* fsmc_4chips_pins */ +static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 }; +static struct spear_muxreg fsmc_4chips_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_FIRDA_MASK | PMX_UART0_MASK, + .val = 0, + }, +}; + +static struct spear_modemux fsmc_4chips_modemux[] = { + { + .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, + .muxregs = fsmc_4chips_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg), + }, +}; + +static struct spear_pingroup fsmc_4chips_pingroup = { + .name = "fsmc_4chips_grp", + .pins = fsmc_4chips_pins, + .npins = ARRAY_SIZE(fsmc_4chips_pins), + .modemuxs = fsmc_4chips_modemux, + .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux), +}; + +static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp" +}; +static struct spear_function fsmc_function = { + .name = "fsmc", + .groups = fsmc_grps, + .ngroups = ARRAY_SIZE(fsmc_grps), +}; + +/* clcd_lcdmode_pins */ +static const unsigned clcd_lcdmode_pins[] = { 49, 50 }; +static struct spear_muxreg clcd_lcdmode_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_modemux clcd_lcdmode_modemux[] = { + { + .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE | + CAMU_LCD_MODE | CAML_LCD_MODE, + .muxregs = clcd_lcdmode_muxreg, + .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg), + }, +}; + +static struct spear_pingroup clcd_lcdmode_pingroup = { + .name = "clcd_lcdmode_grp", + .pins = clcd_lcdmode_pins, + .npins = ARRAY_SIZE(clcd_lcdmode_pins), + .modemuxs = clcd_lcdmode_modemux, + .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux), +}; + +/* clcd_pfmode_pins */ +static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 }; +static struct spear_muxreg clcd_pfmode_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_modemux clcd_pfmode_modemux[] = { + { + .modes = PHOTO_FRAME_MODE, + .muxregs = clcd_pfmode_muxreg, + .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg), + }, +}; + +static struct spear_pingroup clcd_pfmode_pingroup = { + .name = "clcd_pfmode_grp", + .pins = clcd_pfmode_pins, + .npins = ARRAY_SIZE(clcd_pfmode_pins), + .modemuxs = clcd_pfmode_modemux, + .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux), +}; + +static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp" +}; +static struct spear_function clcd_function = { + .name = "clcd", + .groups = clcd_grps, + .ngroups = ARRAY_SIZE(clcd_grps), +}; + +/* tdm_pins */ +static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 }; +static struct spear_muxreg tdm_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_modemux tdm_modemux[] = { + { + .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE + | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE + | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .muxregs = tdm_muxreg, + .nmuxregs = ARRAY_SIZE(tdm_muxreg), + }, +}; + +static struct spear_pingroup tdm_pingroup = { + .name = "tdm_grp", + .pins = tdm_pins, + .npins = ARRAY_SIZE(tdm_pins), + .modemuxs = tdm_modemux, + .nmodemuxs = ARRAY_SIZE(tdm_modemux), +}; + +static const char *const tdm_grps[] = { "tdm_grp" }; +static struct spear_function tdm_function = { + .name = "tdm", + .groups = tdm_grps, + .ngroups = ARRAY_SIZE(tdm_grps), +}; + +/* i2c_clk_pins */ +static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 }; +static struct spear_muxreg i2c_clk_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_modemux i2c_clk_modemux[] = { + { + .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | + LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE + | CAML_LCD_MODE, + .muxregs = i2c_clk_muxreg, + .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg), + }, +}; + +static struct spear_pingroup i2c_clk_pingroup = { + .name = "i2c_clk_grp_grp", + .pins = i2c_clk_pins, + .npins = ARRAY_SIZE(i2c_clk_pins), + .modemuxs = i2c_clk_modemux, + .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux), +}; + +static const char *const i2c_grps[] = { "i2c_clk_grp" }; +static struct spear_function i2c_function = { + .name = "i2c1", + .groups = i2c_grps, + .ngroups = ARRAY_SIZE(i2c_grps), +}; + +/* caml_pins */ +static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 }; +static struct spear_muxreg caml_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_modemux caml_modemux[] = { + { + .modes = CAML_LCDW_MODE | CAML_LCD_MODE, + .muxregs = caml_muxreg, + .nmuxregs = ARRAY_SIZE(caml_muxreg), + }, +}; + +static struct spear_pingroup caml_pingroup = { + .name = "caml_grp", + .pins = caml_pins, + .npins = ARRAY_SIZE(caml_pins), + .modemuxs = caml_modemux, + .nmodemuxs = ARRAY_SIZE(caml_modemux), +}; + +/* camu_pins */ +static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 }; +static struct spear_muxreg camu_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_modemux camu_modemux[] = { + { + .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE, + .muxregs = camu_muxreg, + .nmuxregs = ARRAY_SIZE(camu_muxreg), + }, +}; + +static struct spear_pingroup camu_pingroup = { + .name = "camu_grp", + .pins = camu_pins, + .npins = ARRAY_SIZE(camu_pins), + .modemuxs = camu_modemux, + .nmodemuxs = ARRAY_SIZE(camu_modemux), +}; + +static const char *const cam_grps[] = { "caml_grp", "camu_grp" }; +static struct spear_function cam_function = { + .name = "cam", + .groups = cam_grps, + .ngroups = ARRAY_SIZE(cam_grps), +}; + +/* dac_pins */ +static const unsigned dac_pins[] = { 43, 44 }; +static struct spear_muxreg dac_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK, + .val = 0, + }, +}; + +static struct spear_modemux dac_modemux[] = { + { + .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .muxregs = dac_muxreg, + .nmuxregs = ARRAY_SIZE(dac_muxreg), + }, +}; + +static struct spear_pingroup dac_pingroup = { + .name = "dac_grp", + .pins = dac_pins, + .npins = ARRAY_SIZE(dac_pins), + .modemuxs = dac_modemux, + .nmodemuxs = ARRAY_SIZE(dac_modemux), +}; + +static const char *const dac_grps[] = { "dac_grp" }; +static struct spear_function dac_function = { + .name = "dac", + .groups = dac_grps, + .ngroups = ARRAY_SIZE(dac_grps), +}; + +/* i2s_pins */ +static const unsigned i2s_pins[] = { 39, 40, 41, 42 }; +static struct spear_muxreg i2s_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_modemux i2s_modemux[] = { + { + .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE + | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | + ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .muxregs = i2s_muxreg, + .nmuxregs = ARRAY_SIZE(i2s_muxreg), + }, +}; + +static struct spear_pingroup i2s_pingroup = { + .name = "i2s_grp", + .pins = i2s_pins, + .npins = ARRAY_SIZE(i2s_pins), + .modemuxs = i2s_modemux, + .nmodemuxs = ARRAY_SIZE(i2s_modemux), +}; + +static const char *const i2s_grps[] = { "i2s_grp" }; +static struct spear_function i2s_function = { + .name = "i2s", + .groups = i2s_grps, + .ngroups = ARRAY_SIZE(i2s_grps), +}; + +/* sdhci_4bit_pins */ +static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 }; +static struct spear_muxreg sdhci_4bit_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | + PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, + .val = 0, + }, +}; + +static struct spear_modemux sdhci_4bit_modemux[] = { + { + .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | + HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | + CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE, + .muxregs = sdhci_4bit_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg), + }, +}; + +static struct spear_pingroup sdhci_4bit_pingroup = { + .name = "sdhci_4bit_grp", + .pins = sdhci_4bit_pins, + .npins = ARRAY_SIZE(sdhci_4bit_pins), + .modemuxs = sdhci_4bit_modemux, + .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux), +}; + +/* sdhci_8bit_pins */ +static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32, + 33 }; +static struct spear_muxreg sdhci_8bit_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | + PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_modemux sdhci_8bit_modemux[] = { + { + .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | + HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | + CAMU_WLCD_MODE | CAML_LCD_MODE, + .muxregs = sdhci_8bit_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg), + }, +}; + +static struct spear_pingroup sdhci_8bit_pingroup = { + .name = "sdhci_8bit_grp", + .pins = sdhci_8bit_pins, + .npins = ARRAY_SIZE(sdhci_8bit_pins), + .modemuxs = sdhci_8bit_modemux, + .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux), +}; + +static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" }; +static struct spear_function sdhci_function = { + .name = "sdhci", + .groups = sdhci_grps, + .ngroups = ARRAY_SIZE(sdhci_grps), +}; + +/* gpio1_0_to_3_pins */ +static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 }; +static struct spear_muxreg gpio1_0_to_3_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_modemux gpio1_0_to_3_modemux[] = { + { + .modes = PHOTO_FRAME_MODE, + .muxregs = gpio1_0_to_3_muxreg, + .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg), + }, +}; + +static struct spear_pingroup gpio1_0_to_3_pingroup = { + .name = "gpio1_0_to_3_grp", + .pins = gpio1_0_to_3_pins, + .npins = ARRAY_SIZE(gpio1_0_to_3_pins), + .modemuxs = gpio1_0_to_3_modemux, + .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux), +}; + +/* gpio1_4_to_7_pins */ +static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 }; + +static struct spear_muxreg gpio1_4_to_7_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_modemux gpio1_4_to_7_modemux[] = { + { + .modes = PHOTO_FRAME_MODE, + .muxregs = gpio1_4_to_7_muxreg, + .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg), + }, +}; + +static struct spear_pingroup gpio1_4_to_7_pingroup = { + .name = "gpio1_4_to_7_grp", + .pins = gpio1_4_to_7_pins, + .npins = ARRAY_SIZE(gpio1_4_to_7_pins), + .modemuxs = gpio1_4_to_7_modemux, + .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux), +}; + +static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp" +}; +static struct spear_function gpio1_function = { + .name = "gpio1", + .groups = gpio1_grps, + .ngroups = ARRAY_SIZE(gpio1_grps), +}; + +/* pingroups */ +static struct spear_pingroup *spear300_pingroups[] = { + SPEAR3XX_COMMON_PINGROUPS, + &fsmc_2chips_pingroup, + &fsmc_4chips_pingroup, + &clcd_lcdmode_pingroup, + &clcd_pfmode_pingroup, + &tdm_pingroup, + &i2c_clk_pingroup, + &caml_pingroup, + &camu_pingroup, + &dac_pingroup, + &i2s_pingroup, + &sdhci_4bit_pingroup, + &sdhci_8bit_pingroup, + &gpio1_0_to_3_pingroup, + &gpio1_4_to_7_pingroup, +}; + +/* functions */ +static struct spear_function *spear300_functions[] = { + SPEAR3XX_COMMON_FUNCTIONS, + &fsmc_function, + &clcd_function, + &tdm_function, + &i2c_function, + &cam_function, + &dac_function, + &i2s_function, + &sdhci_function, + &gpio1_function, +}; + +static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = { + { + .compatible = "st,spear300-pinmux", + }, + {}, +}; + +static int __devinit spear300_pinctrl_probe(struct platform_device *pdev) +{ + int ret; + + spear3xx_machdata.groups = spear300_pingroups; + spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups); + spear3xx_machdata.functions = spear300_functions; + spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions); + + spear3xx_machdata.modes_supported = true; + spear3xx_machdata.pmx_modes = spear300_pmx_modes; + spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes); + + pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); + + ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); + if (ret) + return ret; + + return 0; +} + +static int __devexit spear300_pinctrl_remove(struct platform_device *pdev) +{ + return spear_pinctrl_remove(pdev); +} + +static struct platform_driver spear300_pinctrl_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = spear300_pinctrl_of_match, + }, + .probe = spear300_pinctrl_probe, + .remove = __devexit_p(spear300_pinctrl_remove), +}; + +static int __init spear300_pinctrl_init(void) +{ + return platform_driver_register(&spear300_pinctrl_driver); +} +arch_initcall(spear300_pinctrl_init); + +static void __exit spear300_pinctrl_exit(void) +{ + platform_driver_unregister(&spear300_pinctrl_driver); +} +module_exit(spear300_pinctrl_exit); + +MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>"); +MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match); diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c new file mode 100644 index 0000000..1a97076 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear310.c @@ -0,0 +1,431 @@ +/* + * Driver for the ST Microelectronics SPEAr310 pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include "pinctrl-spear3xx.h" + +#define DRIVER_NAME "spear310-pinmux" + +/* addresses */ +#define PMX_CONFIG_REG 0x08 + +/* emi_cs_0_to_5_pins */ +static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 }; +static struct spear_muxreg emi_cs_0_to_5_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_modemux emi_cs_0_to_5_modemux[] = { + { + .muxregs = emi_cs_0_to_5_muxreg, + .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg), + }, +}; + +static struct spear_pingroup emi_cs_0_to_5_pingroup = { + .name = "emi_cs_0_to_5_grp", + .pins = emi_cs_0_to_5_pins, + .npins = ARRAY_SIZE(emi_cs_0_to_5_pins), + .modemuxs = emi_cs_0_to_5_modemux, + .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux), +}; + +static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" }; +static struct spear_function emi_cs_0_to_5_function = { + .name = "emi", + .groups = emi_cs_0_to_5_grps, + .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps), +}; + +/* uart1_pins */ +static const unsigned uart1_pins[] = { 0, 1 }; +static struct spear_muxreg uart1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_FIRDA_MASK, + .val = 0, + }, +}; + +static struct spear_modemux uart1_modemux[] = { + { + .muxregs = uart1_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_muxreg), + }, +}; + +static struct spear_pingroup uart1_pingroup = { + .name = "uart1_grp", + .pins = uart1_pins, + .npins = ARRAY_SIZE(uart1_pins), + .modemuxs = uart1_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_modemux), +}; + +static const char *const uart1_grps[] = { "uart1_grp" }; +static struct spear_function uart1_function = { + .name = "uart1", + .groups = uart1_grps, + .ngroups = ARRAY_SIZE(uart1_grps), +}; + +/* uart2_pins */ +static const unsigned uart2_pins[] = { 43, 44 }; +static struct spear_muxreg uart2_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK, + .val = 0, + }, +}; + +static struct spear_modemux uart2_modemux[] = { + { + .muxregs = uart2_muxreg, + .nmuxregs = ARRAY_SIZE(uart2_muxreg), + }, +}; + +static struct spear_pingroup uart2_pingroup = { + .name = "uart2_grp", + .pins = uart2_pins, + .npins = ARRAY_SIZE(uart2_pins), + .modemuxs = uart2_modemux, + .nmodemuxs = ARRAY_SIZE(uart2_modemux), +}; + +static const char *const uart2_grps[] = { "uart2_grp" }; +static struct spear_function uart2_function = { + .name = "uart2", + .groups = uart2_grps, + .ngroups = ARRAY_SIZE(uart2_grps), +}; + +/* uart3_pins */ +static const unsigned uart3_pins[] = { 37, 38 }; +static struct spear_muxreg uart3_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_modemux uart3_modemux[] = { + { + .muxregs = uart3_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_muxreg), + }, +}; + +static struct spear_pingroup uart3_pingroup = { + .name = "uart3_grp", + .pins = uart3_pins, + .npins = ARRAY_SIZE(uart3_pins), + .modemuxs = uart3_modemux, + .nmodemuxs = ARRAY_SIZE(uart3_modemux), +}; + +static const char *const uart3_grps[] = { "uart3_grp" }; +static struct spear_function uart3_function = { + .name = "uart3", + .groups = uart3_grps, + .ngroups = ARRAY_SIZE(uart3_grps), +}; + +/* uart4_pins */ +static const unsigned uart4_pins[] = { 39, 40 }; +static struct spear_muxreg uart4_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_modemux uart4_modemux[] = { + { + .muxregs = uart4_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_muxreg), + }, +}; + +static struct spear_pingroup uart4_pingroup = { + .name = "uart4_grp", + .pins = uart4_pins, + .npins = ARRAY_SIZE(uart4_pins), + .modemuxs = uart4_modemux, + .nmodemuxs = ARRAY_SIZE(uart4_modemux), +}; + +static const char *const uart4_grps[] = { "uart4_grp" }; +static struct spear_function uart4_function = { + .name = "uart4", + .groups = uart4_grps, + .ngroups = ARRAY_SIZE(uart4_grps), +}; + +/* uart5_pins */ +static const unsigned uart5_pins[] = { 41, 42 }; +static struct spear_muxreg uart5_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_modemux uart5_modemux[] = { + { + .muxregs = uart5_muxreg, + .nmuxregs = ARRAY_SIZE(uart5_muxreg), + }, +}; + +static struct spear_pingroup uart5_pingroup = { + .name = "uart5_grp", + .pins = uart5_pins, + .npins = ARRAY_SIZE(uart5_pins), + .modemuxs = uart5_modemux, + .nmodemuxs = ARRAY_SIZE(uart5_modemux), +}; + +static const char *const uart5_grps[] = { "uart5_grp" }; +static struct spear_function uart5_function = { + .name = "uart5", + .groups = uart5_grps, + .ngroups = ARRAY_SIZE(uart5_grps), +}; + +/* fsmc_pins */ +static const unsigned fsmc_pins[] = { 34, 35, 36 }; +static struct spear_muxreg fsmc_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_modemux fsmc_modemux[] = { + { + .muxregs = fsmc_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_muxreg), + }, +}; + +static struct spear_pingroup fsmc_pingroup = { + .name = "fsmc_grp", + .pins = fsmc_pins, + .npins = ARRAY_SIZE(fsmc_pins), + .modemuxs = fsmc_modemux, + .nmodemuxs = ARRAY_SIZE(fsmc_modemux), +}; + +static const char *const fsmc_grps[] = { "fsmc_grp" }; +static struct spear_function fsmc_function = { + .name = "fsmc", + .groups = fsmc_grps, + .ngroups = ARRAY_SIZE(fsmc_grps), +}; + +/* rs485_0_pins */ +static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 }; +static struct spear_muxreg rs485_0_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_modemux rs485_0_modemux[] = { + { + .muxregs = rs485_0_muxreg, + .nmuxregs = ARRAY_SIZE(rs485_0_muxreg), + }, +}; + +static struct spear_pingroup rs485_0_pingroup = { + .name = "rs485_0_grp", + .pins = rs485_0_pins, + .npins = ARRAY_SIZE(rs485_0_pins), + .modemuxs = rs485_0_modemux, + .nmodemuxs = ARRAY_SIZE(rs485_0_modemux), +}; + +static const char *const rs485_0_grps[] = { "rs485_0" }; +static struct spear_function rs485_0_function = { + .name = "rs485_0", + .groups = rs485_0_grps, + .ngroups = ARRAY_SIZE(rs485_0_grps), +}; + +/* rs485_1_pins */ +static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 }; +static struct spear_muxreg rs485_1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_modemux rs485_1_modemux[] = { + { + .muxregs = rs485_1_muxreg, + .nmuxregs = ARRAY_SIZE(rs485_1_muxreg), + }, +}; + +static struct spear_pingroup rs485_1_pingroup = { + .name = "rs485_1_grp", + .pins = rs485_1_pins, + .npins = ARRAY_SIZE(rs485_1_pins), + .modemuxs = rs485_1_modemux, + .nmodemuxs = ARRAY_SIZE(rs485_1_modemux), +}; + +static const char *const rs485_1_grps[] = { "rs485_1" }; +static struct spear_function rs485_1_function = { + .name = "rs485_1", + .groups = rs485_1_grps, + .ngroups = ARRAY_SIZE(rs485_1_grps), +}; + +/* tdm_pins */ +static const unsigned tdm_pins[] = { 10, 11, 12, 13 }; +static struct spear_muxreg tdm_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_modemux tdm_modemux[] = { + { + .muxregs = tdm_muxreg, + .nmuxregs = ARRAY_SIZE(tdm_muxreg), + }, +}; + +static struct spear_pingroup tdm_pingroup = { + .name = "tdm_grp", + .pins = tdm_pins, + .npins = ARRAY_SIZE(tdm_pins), + .modemuxs = tdm_modemux, + .nmodemuxs = ARRAY_SIZE(tdm_modemux), +}; + +static const char *const tdm_grps[] = { "tdm_grp" }; +static struct spear_function tdm_function = { + .name = "tdm", + .groups = tdm_grps, + .ngroups = ARRAY_SIZE(tdm_grps), +}; + +/* pingroups */ +static struct spear_pingroup *spear310_pingroups[] = { + SPEAR3XX_COMMON_PINGROUPS, + &emi_cs_0_to_5_pingroup, + &uart1_pingroup, + &uart2_pingroup, + &uart3_pingroup, + &uart4_pingroup, + &uart5_pingroup, + &fsmc_pingroup, + &rs485_0_pingroup, + &rs485_1_pingroup, + &tdm_pingroup, +}; + +/* functions */ +static struct spear_function *spear310_functions[] = { + SPEAR3XX_COMMON_FUNCTIONS, + &emi_cs_0_to_5_function, + &uart1_function, + &uart2_function, + &uart3_function, + &uart4_function, + &uart5_function, + &fsmc_function, + &rs485_0_function, + &rs485_1_function, + &tdm_function, +}; + +static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = { + { + .compatible = "st,spear310-pinmux", + }, + {}, +}; + +static int __devinit spear310_pinctrl_probe(struct platform_device *pdev) +{ + int ret; + + spear3xx_machdata.groups = spear310_pingroups; + spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups); + spear3xx_machdata.functions = spear310_functions; + spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions); + + pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); + + spear3xx_machdata.modes_supported = false; + + ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); + if (ret) + return ret; + + return 0; +} + +static int __devexit spear310_pinctrl_remove(struct platform_device *pdev) +{ + return spear_pinctrl_remove(pdev); +} + +static struct platform_driver spear310_pinctrl_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = spear310_pinctrl_of_match, + }, + .probe = spear310_pinctrl_probe, + .remove = __devexit_p(spear310_pinctrl_remove), +}; + +static int __init spear310_pinctrl_init(void) +{ + return platform_driver_register(&spear310_pinctrl_driver); +} +arch_initcall(spear310_pinctrl_init); + +static void __exit spear310_pinctrl_exit(void) +{ + platform_driver_unregister(&spear310_pinctrl_driver); +} +module_exit(spear310_pinctrl_exit); + +MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>"); +MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match); diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c new file mode 100644 index 0000000..de726e6 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear320.c @@ -0,0 +1,3468 @@ +/* + * Driver for the ST Microelectronics SPEAr320 pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include "pinctrl-spear3xx.h" + +#define DRIVER_NAME "spear320-pinmux" + +/* addresses */ +#define PMX_CONFIG_REG 0x0C +#define MODE_CONFIG_REG 0x10 +#define MODE_EXT_CONFIG_REG 0x18 + +/* modes */ +#define AUTO_NET_SMII_MODE (1 << 0) +#define AUTO_NET_MII_MODE (1 << 1) +#define AUTO_EXP_MODE (1 << 2) +#define SMALL_PRINTERS_MODE (1 << 3) +#define EXTENDED_MODE (1 << 4) + +static struct spear_pmx_mode pmx_mode_auto_net_smii = { + .name = "Automation Networking SMII mode", + .mode = AUTO_NET_SMII_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x00000007, + .val = 0x0, +}; + +static struct spear_pmx_mode pmx_mode_auto_net_mii = { + .name = "Automation Networking MII mode", + .mode = AUTO_NET_MII_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x00000007, + .val = 0x1, +}; + +static struct spear_pmx_mode pmx_mode_auto_exp = { + .name = "Automation Expanded mode", + .mode = AUTO_EXP_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x00000007, + .val = 0x2, +}; + +static struct spear_pmx_mode pmx_mode_small_printers = { + .name = "Small Printers mode", + .mode = SMALL_PRINTERS_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x00000007, + .val = 0x3, +}; + +static struct spear_pmx_mode pmx_mode_extended = { + .name = "extended mode", + .mode = EXTENDED_MODE, + .reg = MODE_EXT_CONFIG_REG, + .mask = 0x00000001, + .val = 0x1, +}; + +static struct spear_pmx_mode *spear320_pmx_modes[] = { + &pmx_mode_auto_net_smii, + &pmx_mode_auto_net_mii, + &pmx_mode_auto_exp, + &pmx_mode_small_printers, + &pmx_mode_extended, +}; + +/* Extended mode registers and their offsets */ +#define EXT_CTRL_REG 0x0018 + #define MII_MDIO_MASK (1 << 4) + #define MII_MDIO_10_11_VAL 0 + #define MII_MDIO_81_VAL (1 << 4) + #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5) + #define MAC_MODE_MII 0 + #define MAC_MODE_RMII 1 + #define MAC_MODE_SMII 2 + #define MAC_MODE_SS_SMII 3 + #define MAC_MODE_MASK 0x3 + #define MAC1_MODE_SHIFT 16 + #define MAC2_MODE_SHIFT 18 + +#define IP_SEL_PAD_0_9_REG 0x00A4 + #define PMX_PL_0_1_MASK (0x3F << 0) + #define PMX_UART2_PL_0_1_VAL 0x0 + #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3)) + + #define PMX_PL_2_3_MASK (0x3F << 6) + #define PMX_I2C2_PL_2_3_VAL 0x0 + #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9)) + #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9)) + + #define PMX_PL_4_5_MASK (0x3F << 12) + #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15)) + #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15)) + #define PMX_PL_5_MASK (0x7 << 15) + #define PMX_TOUCH_Y_PL_5_VAL 0x0 + + #define PMX_PL_6_7_MASK (0x3F << 18) + #define PMX_PL_6_MASK (0x7 << 18) + #define PMX_PL_7_MASK (0x7 << 21) + #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21)) + #define PMX_PWM_3_PL_6_VAL (0x2 << 18) + #define PMX_PWM_2_PL_7_VAL (0x2 << 21) + #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21)) + + #define PMX_PL_8_9_MASK (0x3F << 24) + #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27)) + #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27)) + #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27)) + +#define IP_SEL_PAD_10_19_REG 0x00A8 + #define PMX_PL_10_11_MASK (0x3F << 0) + #define PMX_SMII_PL_10_11_VAL 0 + #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3)) + + #define PMX_PL_12_MASK (0x7 << 6) + #define PMX_PWM3_PL_12_VAL 0 + #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6) + + #define PMX_PL_13_14_MASK (0x3F << 9) + #define PMX_PL_13_MASK (0x7 << 9) + #define PMX_PL_14_MASK (0x7 << 12) + #define PMX_SSP2_PL_13_14_15_16_VAL 0 + #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12)) + #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12)) + #define PMX_PWM2_PL_13_VAL (0x2 << 9) + #define PMX_PWM1_PL_14_VAL (0x2 << 12) + + #define PMX_PL_15_MASK (0x7 << 15) + #define PMX_PWM0_PL_15_VAL (0x2 << 15) + #define PMX_PL_15_16_MASK (0x3F << 15) + #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18)) + #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18)) + + #define PMX_PL_17_18_MASK (0x3F << 21) + #define PMX_SSP1_PL_17_18_19_20_VAL 0 + #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24)) + + #define PMX_PL_19_MASK (0x7 << 27) + #define PMX_I2C2_PL_19_VAL (0x1 << 27) + #define PMX_RMII_PL_19_VAL (0x4 << 27) + +#define IP_SEL_PAD_20_29_REG 0x00AC + #define PMX_PL_20_MASK (0x7 << 0) + #define PMX_I2C2_PL_20_VAL (0x1 << 0) + #define PMX_RMII_PL_20_VAL (0x4 << 0) + + #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3) + #define PMX_SMII_PL_21_TO_27_VAL 0 + #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21)) + + #define PMX_PL_28_29_MASK (0x3F << 24) + #define PMX_PL_28_MASK (0x7 << 24) + #define PMX_PL_29_MASK (0x7 << 27) + #define PMX_UART1_PL_28_29_VAL 0 + #define PMX_PWM_3_PL_28_VAL (0x4 << 24) + #define PMX_PWM_2_PL_29_VAL (0x4 << 27) + +#define IP_SEL_PAD_30_39_REG 0x00B0 + #define PMX_PL_30_31_MASK (0x3F << 0) + #define PMX_CAN1_PL_30_31_VAL (0) + #define PMX_PL_30_MASK (0x7 << 0) + #define PMX_PL_31_MASK (0x7 << 3) + #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0) + #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3) + #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3) + + #define PMX_PL_32_33_MASK (0x3F << 6) + #define PMX_CAN0_PL_32_33_VAL 0 + #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9)) + #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9)) + + #define PMX_PL_34_MASK (0x7 << 12) + #define PMX_PWM2_PL_34_VAL 0 + #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12) + #define PMX_SSP2_PL_34_VAL (0x4 << 12) + + #define PMX_PL_35_MASK (0x7 << 15) + #define PMX_I2S_REF_CLK_PL_35_VAL 0 + #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15) + #define PMX_SSP2_PL_35_VAL (0x4 << 15) + + #define PMX_PL_36_MASK (0x7 << 18) + #define PMX_TOUCH_X_PL_36_VAL 0 + #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18) + #define PMX_SSP1_PL_36_VAL (0x4 << 18) + + #define PMX_PL_37_38_MASK (0x3F << 21) + #define PMX_PWM0_1_PL_37_38_VAL 0 + #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24)) + #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24)) + + #define PMX_PL_39_MASK (0x7 << 27) + #define PMX_I2S_PL_39_VAL 0 + #define PMX_UART4_PL_39_VAL (0x2 << 27) + #define PMX_SSP1_PL_39_VAL (0x4 << 27) + +#define IP_SEL_PAD_40_49_REG 0x00B4 + #define PMX_PL_40_MASK (0x7 << 0) + #define PMX_I2S_PL_40_VAL 0 + #define PMX_UART4_PL_40_VAL (0x2 << 0) + #define PMX_PWM3_PL_40_VAL (0x4 << 0) + + #define PMX_PL_41_42_MASK (0x3F << 3) + #define PMX_PL_41_MASK (0x7 << 3) + #define PMX_PL_42_MASK (0x7 << 6) + #define PMX_I2S_PL_41_42_VAL 0 + #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6)) + #define PMX_PWM2_PL_41_VAL (0x4 << 3) + #define PMX_PWM1_PL_42_VAL (0x4 << 6) + + #define PMX_PL_43_MASK (0x7 << 9) + #define PMX_SDHCI_PL_43_VAL 0 + #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9) + #define PMX_PWM0_PL_43_VAL (0x4 << 9) + + #define PMX_PL_44_45_MASK (0x3F << 12) + #define PMX_SDHCI_PL_44_45_VAL 0 + #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15)) + #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15)) + + #define PMX_PL_46_47_MASK (0x3F << 18) + #define PMX_SDHCI_PL_46_47_VAL 0 + #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21)) + #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21)) + + #define PMX_PL_48_49_MASK (0x3F << 24) + #define PMX_SDHCI_PL_48_49_VAL 0 + #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27)) + #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27)) + +#define IP_SEL_PAD_50_59_REG 0x00B8 + #define PMX_PL_50_51_MASK (0x3F << 0) + #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3)) + #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3)) + #define PMX_PL_50_MASK (0x7 << 0) + #define PMX_PL_51_MASK (0x7 << 3) + #define PMX_SDHCI_PL_50_VAL 0 + #define PMX_SDHCI_CD_PL_51_VAL 0 + + #define PMX_PL_52_53_MASK (0x3F << 6) + #define PMX_FSMC_PL_52_53_VAL 0 + #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9)) + #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9)) + + #define PMX_PL_54_55_56_MASK (0x1FF << 12) + #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18)) + + #define PMX_PL_57_MASK (0x7 << 21) + #define PMX_FSMC_PL_57_VAL 0 + #define PMX_PWM3_PL_57_VAL (0x4 << 21) + + #define PMX_PL_58_59_MASK (0x3F << 24) + #define PMX_PL_58_MASK (0x7 << 24) + #define PMX_PL_59_MASK (0x7 << 27) + #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27)) + #define PMX_PWM2_PL_58_VAL (0x4 << 24) + #define PMX_PWM1_PL_59_VAL (0x4 << 27) + +#define IP_SEL_PAD_60_69_REG 0x00BC + #define PMX_PL_60_MASK (0x7 << 0) + #define PMX_FSMC_PL_60_VAL 0 + #define PMX_PWM0_PL_60_VAL (0x4 << 0) + + #define PMX_PL_61_TO_64_MASK (0xFFF << 3) + #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12)) + #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12)) + + #define PMX_PL_65_TO_68_MASK (0xFFF << 15) + #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24)) + #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24)) + + #define PMX_PL_69_MASK (0x7 << 27) + #define PMX_CLCD_PL_69_VAL (0) + #define PMX_EMI_PL_69_VAL (0x2 << 27) + #define PMX_SPP_PL_69_VAL (0x3 << 27) + #define PMX_UART5_PL_69_VAL (0x4 << 27) + +#define IP_SEL_PAD_70_79_REG 0x00C0 + #define PMX_PL_70_MASK (0x7 << 0) + #define PMX_CLCD_PL_70_VAL (0) + #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0) + #define PMX_SPP_PL_70_VAL (0x3 << 0) + #define PMX_UART5_PL_70_VAL (0x4 << 0) + + #define PMX_PL_71_72_MASK (0x3F << 3) + #define PMX_CLCD_PL_71_72_VAL (0) + #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6)) + #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6)) + #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6)) + + #define PMX_PL_73_MASK (0x7 << 9) + #define PMX_CLCD_PL_73_VAL (0) + #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9) + #define PMX_SPP_PL_73_VAL (0x3 << 9) + #define PMX_UART3_PL_73_VAL (0x4 << 9) + + #define PMX_PL_74_MASK (0x7 << 12) + #define PMX_CLCD_PL_74_VAL (0) + #define PMX_EMI_PL_74_VAL (0x2 << 12) + #define PMX_SPP_PL_74_VAL (0x3 << 12) + #define PMX_UART3_PL_74_VAL (0x4 << 12) + + #define PMX_PL_75_76_MASK (0x3F << 15) + #define PMX_CLCD_PL_75_76_VAL (0) + #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18)) + #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18)) + #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18)) + + #define PMX_PL_77_78_79_MASK (0x1FF << 21) + #define PMX_CLCD_PL_77_78_79_VAL (0) + #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27)) + #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27)) + #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27)) + +#define IP_SEL_PAD_80_89_REG 0x00C4 + #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0) + #define PMX_CLCD_PL_80_TO_85_VAL 0 + #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15)) + #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15)) + #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15)) + #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15)) + + #define PMX_PL_86_87_MASK (0x3F << 18) + #define PMX_PL_86_MASK (0x7 << 18) + #define PMX_PL_87_MASK (0x7 << 21) + #define PMX_CLCD_PL_86_87_VAL 0 + #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21)) + #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21)) + #define PMX_PWM3_PL_86_VAL (0x4 << 18) + #define PMX_PWM2_PL_87_VAL (0x4 << 21) + + #define PMX_PL_88_89_MASK (0x3F << 24) + #define PMX_CLCD_PL_88_89_VAL 0 + #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27)) + #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27)) + #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27)) + #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27)) + +#define IP_SEL_PAD_90_99_REG 0x00C8 + #define PMX_PL_90_91_MASK (0x3F << 0) + #define PMX_CLCD_PL_90_91_VAL 0 + #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3)) + #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3)) + #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3)) + #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3)) + + #define PMX_PL_92_93_MASK (0x3F << 6) + #define PMX_CLCD_PL_92_93_VAL 0 + #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9)) + #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9)) + #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9)) + #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9)) + + #define PMX_PL_94_95_MASK (0x3F << 12) + #define PMX_CLCD_PL_94_95_VAL 0 + #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15)) + #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15)) + #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15)) + #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15)) + + #define PMX_PL_96_97_MASK (0x3F << 18) + #define PMX_CLCD_PL_96_97_VAL 0 + #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21)) + #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21)) + #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21)) + #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21)) + + #define PMX_PL_98_MASK (0x7 << 24) + #define PMX_CLCD_PL_98_VAL 0 + #define PMX_I2C1_PL_98_VAL (0x2 << 24) + #define PMX_UART3_PL_98_VAL (0x4 << 24) + + #define PMX_PL_99_MASK (0x7 << 27) + #define PMX_SDHCI_PL_99_VAL 0 + #define PMX_I2C1_PL_99_VAL (0x2 << 27) + #define PMX_UART3_PL_99_VAL (0x4 << 27) + +#define IP_SEL_MIX_PAD_REG 0x00CC + #define PMX_PL_100_101_MASK (0x3F << 0) + #define PMX_SDHCI_PL_100_101_VAL 0 + #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3)) + + #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8) + #define PMX_SSP1_PORT_94_TO_97_VAL 0 + #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8) + #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8) + #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8) + #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8) + + #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11) + #define PMX_SSP2_PORT_90_TO_93_VAL 0 + #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11) + #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11) + #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11) + #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11) + + #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14) + #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0 + #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14) + #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14) + #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14) + + #define PMX_UART3_PORT_SEL_MASK (0x7 << 16) + #define PMX_UART3_PORT_94_VAL 0 + #define PMX_UART3_PORT_73_VAL (0x1 << 16) + #define PMX_UART3_PORT_52_VAL (0x2 << 16) + #define PMX_UART3_PORT_41_VAL (0x3 << 16) + #define PMX_UART3_PORT_15_VAL (0x4 << 16) + #define PMX_UART3_PORT_8_VAL (0x5 << 16) + #define PMX_UART3_PORT_99_VAL (0x6 << 16) + + #define PMX_UART4_PORT_SEL_MASK (0x7 << 19) + #define PMX_UART4_PORT_92_VAL 0 + #define PMX_UART4_PORT_71_VAL (0x1 << 19) + #define PMX_UART4_PORT_39_VAL (0x2 << 19) + #define PMX_UART4_PORT_13_VAL (0x3 << 19) + #define PMX_UART4_PORT_6_VAL (0x4 << 19) + #define PMX_UART4_PORT_101_VAL (0x5 << 19) + + #define PMX_UART5_PORT_SEL_MASK (0x3 << 22) + #define PMX_UART5_PORT_90_VAL 0 + #define PMX_UART5_PORT_69_VAL (0x1 << 22) + #define PMX_UART5_PORT_37_VAL (0x2 << 22) + #define PMX_UART5_PORT_4_VAL (0x3 << 22) + + #define PMX_UART6_PORT_SEL_MASK (0x1 << 24) + #define PMX_UART6_PORT_88_VAL 0 + #define PMX_UART6_PORT_2_VAL (0x1 << 24) + + #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25) + #define PMX_I2C1_PORT_8_9_VAL 0 + #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25) + + #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26) + #define PMX_I2C2_PORT_96_97_VAL 0 + #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26) + #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26) + #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26) + #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26) + + #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29) + #define PMX_SDHCI_CD_PORT_12_VAL 0 + #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29) + +/* Pad multiplexing for CLCD device */ +static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, + 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, + 97 }; +static struct spear_muxreg clcd_muxreg[] = { + { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_69_MASK, + .val = PMX_CLCD_PL_69_VAL, + }, { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | + PMX_PL_74_MASK | PMX_PL_75_76_MASK | + PMX_PL_77_78_79_MASK, + .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL | + PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL | + PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL, + }, { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | + PMX_PL_88_89_MASK, + .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL | + PMX_CLCD_PL_88_89_VAL, + }, { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | + PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK, + .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL | + PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL | + PMX_CLCD_PL_98_VAL, + }, +}; + +static struct spear_modemux clcd_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = clcd_muxreg, + .nmuxregs = ARRAY_SIZE(clcd_muxreg), + }, +}; + +static struct spear_pingroup clcd_pingroup = { + .name = "clcd_grp", + .pins = clcd_pins, + .npins = ARRAY_SIZE(clcd_pins), + .modemuxs = clcd_modemux, + .nmodemuxs = ARRAY_SIZE(clcd_modemux), +}; + +static const char *const clcd_grps[] = { "clcd_grp" }; +static struct spear_function clcd_function = { + .name = "clcd", + .groups = clcd_grps, + .ngroups = ARRAY_SIZE(clcd_grps), +}; + +/* Pad multiplexing for EMI (Parallel NOR flash) device */ +static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, + 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, + 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, + 93, 94, 95, 96, 97 }; +static struct spear_muxreg emi_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg emi_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, + .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, + }, { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK | + PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK, + .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL | + PMX_FSMC_EMI_PL_54_55_56_VAL | + PMX_FSMC_EMI_PL_58_59_VAL, + }, { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_69_MASK, + .val = PMX_EMI_PL_69_VAL, + }, { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | + PMX_PL_74_MASK | PMX_PL_75_76_MASK | + PMX_PL_77_78_79_MASK, + .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | + PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL | + PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL, + }, { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | + PMX_PL_88_89_MASK, + .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL | + PMX_EMI_PL_88_89_VAL, + }, { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | + PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, + .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL | + PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL, + }, { + .reg = EXT_CTRL_REG, + .mask = EMI_FSMC_DYNAMIC_MUX_MASK, + .val = EMI_FSMC_DYNAMIC_MUX_MASK, + }, +}; + +static struct spear_modemux emi_modemux[] = { + { + .modes = AUTO_EXP_MODE | EXTENDED_MODE, + .muxregs = emi_muxreg, + .nmuxregs = ARRAY_SIZE(emi_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = emi_ext_muxreg, + .nmuxregs = ARRAY_SIZE(emi_ext_muxreg), + }, +}; + +static struct spear_pingroup emi_pingroup = { + .name = "emi_grp", + .pins = emi_pins, + .npins = ARRAY_SIZE(emi_pins), + .modemuxs = emi_modemux, + .nmodemuxs = ARRAY_SIZE(emi_modemux), +}; + +static const char *const emi_grps[] = { "emi_grp" }; +static struct spear_function emi_function = { + .name = "emi", + .groups = emi_grps, + .ngroups = ARRAY_SIZE(emi_grps), +}; + +/* Pad multiplexing for FSMC (NAND flash) device */ +static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60, + 61, 62, 63, 64, 65, 66, 67, 68 }; +static struct spear_muxreg fsmc_8bit_muxreg[] = { + { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK | + PMX_PL_57_MASK | PMX_PL_58_59_MASK, + .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL | + PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL, + }, { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK | + PMX_PL_65_TO_68_MASK, + .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL | + PMX_FSMC_PL_65_TO_68_VAL, + }, { + .reg = EXT_CTRL_REG, + .mask = EMI_FSMC_DYNAMIC_MUX_MASK, + .val = EMI_FSMC_DYNAMIC_MUX_MASK, + }, +}; + +static struct spear_modemux fsmc_8bit_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = fsmc_8bit_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), + }, +}; + +static struct spear_pingroup fsmc_8bit_pingroup = { + .name = "fsmc_8bit_grp", + .pins = fsmc_8bit_pins, + .npins = ARRAY_SIZE(fsmc_8bit_pins), + .modemuxs = fsmc_8bit_modemux, + .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux), +}; + +static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56, + 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 }; +static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg fsmc_16bit_muxreg[] = { + { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, + .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, + }, { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK, + .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | + PMX_FSMC_EMI_PL_73_VAL, + } +}; + +static struct spear_modemux fsmc_16bit_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = fsmc_8bit_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), + }, { + .modes = AUTO_EXP_MODE | EXTENDED_MODE, + .muxregs = fsmc_16bit_autoexp_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = fsmc_16bit_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg), + }, +}; + +static struct spear_pingroup fsmc_16bit_pingroup = { + .name = "fsmc_16bit_grp", + .pins = fsmc_16bit_pins, + .npins = ARRAY_SIZE(fsmc_16bit_pins), + .modemuxs = fsmc_16bit_modemux, + .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux), +}; + +static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" }; +static struct spear_function fsmc_function = { + .name = "fsmc", + .groups = fsmc_grps, + .ngroups = ARRAY_SIZE(fsmc_grps), +}; + +/* Pad multiplexing for SPP device */ +static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85 }; +static struct spear_muxreg spp_muxreg[] = { + { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_69_MASK, + .val = PMX_SPP_PL_69_VAL, + }, { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | + PMX_PL_74_MASK | PMX_PL_75_76_MASK | + PMX_PL_77_78_79_MASK, + .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL | + PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL | + PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL, + }, { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_80_TO_85_MASK, + .val = PMX_SPP_PL_80_TO_85_VAL, + }, +}; + +static struct spear_modemux spp_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = spp_muxreg, + .nmuxregs = ARRAY_SIZE(spp_muxreg), + }, +}; + +static struct spear_pingroup spp_pingroup = { + .name = "spp_grp", + .pins = spp_pins, + .npins = ARRAY_SIZE(spp_pins), + .modemuxs = spp_modemux, + .nmodemuxs = ARRAY_SIZE(spp_modemux), +}; + +static const char *const spp_grps[] = { "spp_grp" }; +static struct spear_function spp_function = { + .name = "spp", + .groups = spp_grps, + .ngroups = ARRAY_SIZE(spp_grps), +}; + +/* Pad multiplexing for SDHCI device */ +static const unsigned sdhci_led_pins[] = { 34 }; +static struct spear_muxreg sdhci_led_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg sdhci_led_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_34_MASK, + .val = PMX_PWM2_PL_34_VAL, + }, +}; + +static struct spear_modemux sdhci_led_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, + .muxregs = sdhci_led_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = sdhci_led_ext_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg), + }, +}; + +static struct spear_pingroup sdhci_led_pingroup = { + .name = "sdhci_led_grp", + .pins = sdhci_led_pins, + .npins = ARRAY_SIZE(sdhci_led_pins), + .modemuxs = sdhci_led_modemux, + .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux), +}; + +static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49, + 50}; +static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51 +}; +static struct spear_muxreg sdhci_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg sdhci_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK | + PMX_PL_48_49_MASK, + .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL | + PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL, + }, { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_50_MASK, + .val = PMX_SDHCI_PL_50_VAL, + }, { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_99_MASK, + .val = PMX_SDHCI_PL_99_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_PL_100_101_MASK, + .val = PMX_SDHCI_PL_100_101_VAL, + }, +}; + +static struct spear_muxreg sdhci_cd_12_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_12_MASK, + .val = PMX_SDHCI_CD_PL_12_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SDHCI_CD_PORT_SEL_MASK, + .val = PMX_SDHCI_CD_PORT_12_VAL, + }, +}; + +static struct spear_muxreg sdhci_cd_51_muxreg[] = { + { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_51_MASK, + .val = PMX_SDHCI_CD_PL_51_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SDHCI_CD_PORT_SEL_MASK, + .val = PMX_SDHCI_CD_PORT_51_VAL, + }, +}; + +#define pmx_sdhci_common_modemux \ + { \ + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \ + SMALL_PRINTERS_MODE | EXTENDED_MODE, \ + .muxregs = sdhci_muxreg, \ + .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \ + }, { \ + .modes = EXTENDED_MODE, \ + .muxregs = sdhci_ext_muxreg, \ + .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \ + } + +static struct spear_modemux sdhci_modemux[][3] = { + { + /* select pin 12 for cd */ + pmx_sdhci_common_modemux, + { + .modes = EXTENDED_MODE, + .muxregs = sdhci_cd_12_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg), + }, + }, { + /* select pin 51 for cd */ + pmx_sdhci_common_modemux, + { + .modes = EXTENDED_MODE, + .muxregs = sdhci_cd_51_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg), + }, + } +}; + +static struct spear_pingroup sdhci_pingroup[] = { + { + .name = "sdhci_cd_12_grp", + .pins = sdhci_cd_12_pins, + .npins = ARRAY_SIZE(sdhci_cd_12_pins), + .modemuxs = sdhci_modemux[0], + .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]), + }, { + .name = "sdhci_cd_51_grp", + .pins = sdhci_cd_51_pins, + .npins = ARRAY_SIZE(sdhci_cd_51_pins), + .modemuxs = sdhci_modemux[1], + .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]), + }, +}; + +static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp", + "sdhci_led_grp" }; + +static struct spear_function sdhci_function = { + .name = "sdhci", + .groups = sdhci_grps, + .ngroups = ARRAY_SIZE(sdhci_grps), +}; + +/* Pad multiplexing for I2S device */ +static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 }; +static struct spear_muxreg i2s_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK, + .val = 0, + }, { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg i2s_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_35_MASK | PMX_PL_39_MASK, + .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK, + .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL, + }, +}; + +static struct spear_modemux i2s_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, + .muxregs = i2s_muxreg, + .nmuxregs = ARRAY_SIZE(i2s_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = i2s_ext_muxreg, + .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg), + }, +}; + +static struct spear_pingroup i2s_pingroup = { + .name = "i2s_grp", + .pins = i2s_pins, + .npins = ARRAY_SIZE(i2s_pins), + .modemuxs = i2s_modemux, + .nmodemuxs = ARRAY_SIZE(i2s_modemux), +}; + +static const char *const i2s_grps[] = { "i2s_grp" }; +static struct spear_function i2s_function = { + .name = "i2s", + .groups = i2s_grps, + .ngroups = ARRAY_SIZE(i2s_grps), +}; + +/* Pad multiplexing for UART1 device */ +static const unsigned uart1_pins[] = { 28, 29 }; +static struct spear_muxreg uart1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg uart1_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_28_29_MASK, + .val = PMX_UART1_PL_28_29_VAL, + }, +}; + +static struct spear_modemux uart1_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE + | SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = uart1_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = uart1_ext_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg), + }, +}; + +static struct spear_pingroup uart1_pingroup = { + .name = "uart1_grp", + .pins = uart1_pins, + .npins = ARRAY_SIZE(uart1_pins), + .modemuxs = uart1_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_modemux), +}; + +static const char *const uart1_grps[] = { "uart1_grp" }; +static struct spear_function uart1_function = { + .name = "uart1", + .groups = uart1_grps, + .ngroups = ARRAY_SIZE(uart1_grps), +}; + +/* Pad multiplexing for UART1 Modem device */ +static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 }; +static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 }; +static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 }; +static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 }; + +static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK, + .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL | + PMX_UART1_ENH_PL_6_7_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART1_ENH_PORT_SEL_MASK, + .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL, + }, +}; + +static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | + PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK | + PMX_PL_35_MASK | PMX_PL_36_MASK, + .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL | + PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | + PMX_UART1_ENH_PL_36_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART1_ENH_PORT_SEL_MASK, + .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL, + }, +}; + +static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | + PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK, + .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | + PMX_UART1_ENH_PL_36_VAL, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, + .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART1_ENH_PORT_SEL_MASK, + .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL, + }, +}; + +static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = { + { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_80_TO_85_MASK, + .val = PMX_UART1_ENH_PL_80_TO_85_VAL, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, + .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART1_ENH_PORT_SEL_MASK, + .val = PMX_UART1_ENH_PORT_81_TO_85_VAL, + }, +}; + +static struct spear_modemux uart1_modem_2_to_7_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = uart1_modem_ext_2_to_7_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg), + }, +}; + +static struct spear_modemux uart1_modem_31_to_36_modemux[] = { + { + .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = uart1_modem_31_to_36_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = uart1_modem_ext_31_to_36_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg), + }, +}; + +static struct spear_modemux uart1_modem_34_to_45_modemux[] = { + { + .modes = AUTO_EXP_MODE | EXTENDED_MODE, + .muxregs = uart1_modem_34_to_45_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = uart1_modem_ext_34_to_45_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg), + }, +}; + +static struct spear_modemux uart1_modem_80_to_85_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = uart1_modem_ext_80_to_85_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg), + }, +}; + +static struct spear_pingroup uart1_modem_pingroup[] = { + { + .name = "uart1_modem_2_to_7_grp", + .pins = uart1_modem_2_to_7_pins, + .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins), + .modemuxs = uart1_modem_2_to_7_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux), + }, { + .name = "uart1_modem_31_to_36_grp", + .pins = uart1_modem_31_to_36_pins, + .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins), + .modemuxs = uart1_modem_31_to_36_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux), + }, { + .name = "uart1_modem_34_to_45_grp", + .pins = uart1_modem_34_to_45_pins, + .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins), + .modemuxs = uart1_modem_34_to_45_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux), + }, { + .name = "uart1_modem_80_to_85_grp", + .pins = uart1_modem_80_to_85_pins, + .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins), + .modemuxs = uart1_modem_80_to_85_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux), + }, +}; + +static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp", + "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp", + "uart1_modem_80_to_85_grp" }; +static struct spear_function uart1_modem_function = { + .name = "uart1_modem", + .groups = uart1_modem_grps, + .ngroups = ARRAY_SIZE(uart1_modem_grps), +}; + +/* Pad multiplexing for UART2 device */ +static const unsigned uart2_pins[] = { 0, 1 }; +static struct spear_muxreg uart2_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_FIRDA_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg uart2_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_0_1_MASK, + .val = PMX_UART2_PL_0_1_VAL, + }, +}; + +static struct spear_modemux uart2_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE + | SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = uart2_muxreg, + .nmuxregs = ARRAY_SIZE(uart2_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = uart2_ext_muxreg, + .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg), + }, +}; + +static struct spear_pingroup uart2_pingroup = { + .name = "uart2_grp", + .pins = uart2_pins, + .npins = ARRAY_SIZE(uart2_pins), + .modemuxs = uart2_modemux, + .nmodemuxs = ARRAY_SIZE(uart2_modemux), +}; + +static const char *const uart2_grps[] = { "uart2_grp" }; +static struct spear_function uart2_function = { + .name = "uart2", + .groups = uart2_grps, + .ngroups = ARRAY_SIZE(uart2_grps), +}; + +/* Pad multiplexing for uart3 device */ +static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 }, + { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } }; + +static struct spear_muxreg uart3_ext_8_9_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_8_9_MASK, + .val = PMX_UART3_PL_8_9_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_8_VAL, + }, +}; + +static struct spear_muxreg uart3_ext_15_16_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_15_16_MASK, + .val = PMX_UART3_PL_15_16_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_15_VAL, + }, +}; + +static struct spear_muxreg uart3_ext_41_42_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_41_42_MASK, + .val = PMX_UART3_PL_41_42_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_41_VAL, + }, +}; + +static struct spear_muxreg uart3_ext_52_53_muxreg[] = { + { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_52_53_MASK, + .val = PMX_UART3_PL_52_53_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_52_VAL, + }, +}; + +static struct spear_muxreg uart3_ext_73_74_muxreg[] = { + { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_73_MASK | PMX_PL_74_MASK, + .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_73_VAL, + }, +}; + +static struct spear_muxreg uart3_ext_94_95_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_94_95_MASK, + .val = PMX_UART3_PL_94_95_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_94_VAL, + }, +}; + +static struct spear_muxreg uart3_ext_98_99_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, + .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_99_VAL, + }, +}; + +static struct spear_modemux uart3_modemux[][1] = { + { + /* Select signals on pins 8_9 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_8_9_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg), + }, + }, { + /* Select signals on pins 15_16 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_15_16_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg), + }, + }, { + /* Select signals on pins 41_42 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_41_42_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg), + }, + }, { + /* Select signals on pins 52_53 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_52_53_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg), + }, + }, { + /* Select signals on pins 73_74 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_73_74_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg), + }, + }, { + /* Select signals on pins 94_95 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_94_95_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg), + }, + }, { + /* Select signals on pins 98_99 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_98_99_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg), + }, + }, +}; + +static struct spear_pingroup uart3_pingroup[] = { + { + .name = "uart3_8_9_grp", + .pins = uart3_pins[0], + .npins = ARRAY_SIZE(uart3_pins[0]), + .modemuxs = uart3_modemux[0], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]), + }, { + .name = "uart3_15_16_grp", + .pins = uart3_pins[1], + .npins = ARRAY_SIZE(uart3_pins[1]), + .modemuxs = uart3_modemux[1], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]), + }, { + .name = "uart3_41_42_grp", + .pins = uart3_pins[2], + .npins = ARRAY_SIZE(uart3_pins[2]), + .modemuxs = uart3_modemux[2], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]), + }, { + .name = "uart3_52_53_grp", + .pins = uart3_pins[3], + .npins = ARRAY_SIZE(uart3_pins[3]), + .modemuxs = uart3_modemux[3], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]), + }, { + .name = "uart3_73_74_grp", + .pins = uart3_pins[4], + .npins = ARRAY_SIZE(uart3_pins[4]), + .modemuxs = uart3_modemux[4], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]), + }, { + .name = "uart3_94_95_grp", + .pins = uart3_pins[5], + .npins = ARRAY_SIZE(uart3_pins[5]), + .modemuxs = uart3_modemux[5], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]), + }, { + .name = "uart3_98_99_grp", + .pins = uart3_pins[6], + .npins = ARRAY_SIZE(uart3_pins[6]), + .modemuxs = uart3_modemux[6], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]), + }, +}; + +static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp", + "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp", + "uart3_94_95_grp", "uart3_98_99_grp" }; + +static struct spear_function uart3_function = { + .name = "uart3", + .groups = uart3_grps, + .ngroups = ARRAY_SIZE(uart3_grps), +}; + +/* Pad multiplexing for uart4 device */ +static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 }, + { 71, 72 }, { 92, 93 }, { 100, 101 } }; + +static struct spear_muxreg uart4_ext_6_7_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_6_7_MASK, + .val = PMX_UART4_PL_6_7_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART4_PORT_SEL_MASK, + .val = PMX_UART4_PORT_6_VAL, + }, +}; + +static struct spear_muxreg uart4_ext_13_14_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_13_14_MASK, + .val = PMX_UART4_PL_13_14_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART4_PORT_SEL_MASK, + .val = PMX_UART4_PORT_13_VAL, + }, +}; + +static struct spear_muxreg uart4_ext_39_40_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_39_MASK, + .val = PMX_UART4_PL_39_VAL, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_40_MASK, + .val = PMX_UART4_PL_40_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART4_PORT_SEL_MASK, + .val = PMX_UART4_PORT_39_VAL, + }, +}; + +static struct spear_muxreg uart4_ext_71_72_muxreg[] = { + { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_71_72_MASK, + .val = PMX_UART4_PL_71_72_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART4_PORT_SEL_MASK, + .val = PMX_UART4_PORT_71_VAL, + }, +}; + +static struct spear_muxreg uart4_ext_92_93_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_92_93_MASK, + .val = PMX_UART4_PL_92_93_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART4_PORT_SEL_MASK, + .val = PMX_UART4_PORT_92_VAL, + }, +}; + +static struct spear_muxreg uart4_ext_100_101_muxreg[] = { + { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_PL_100_101_MASK | + PMX_UART4_PORT_SEL_MASK, + .val = PMX_UART4_PL_100_101_VAL | + PMX_UART4_PORT_101_VAL, + }, +}; + +static struct spear_modemux uart4_modemux[][1] = { + { + /* Select signals on pins 6_7 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart4_ext_6_7_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg), + }, + }, { + /* Select signals on pins 13_14 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart4_ext_13_14_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg), + }, + }, { + /* Select signals on pins 39_40 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart4_ext_39_40_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg), + }, + }, { + /* Select signals on pins 71_72 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart4_ext_71_72_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg), + }, + }, { + /* Select signals on pins 92_93 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart4_ext_92_93_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg), + }, + }, { + /* Select signals on pins 100_101_ */ + { + .modes = EXTENDED_MODE, + .muxregs = uart4_ext_100_101_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg), + }, + }, +}; + +static struct spear_pingroup uart4_pingroup[] = { + { + .name = "uart4_6_7_grp", + .pins = uart4_pins[0], + .npins = ARRAY_SIZE(uart4_pins[0]), + .modemuxs = uart4_modemux[0], + .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]), + }, { + .name = "uart4_13_14_grp", + .pins = uart4_pins[1], + .npins = ARRAY_SIZE(uart4_pins[1]), + .modemuxs = uart4_modemux[1], + .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]), + }, { + .name = "uart4_39_40_grp", + .pins = uart4_pins[2], + .npins = ARRAY_SIZE(uart4_pins[2]), + .modemuxs = uart4_modemux[2], + .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]), + }, { + .name = "uart4_71_72_grp", + .pins = uart4_pins[3], + .npins = ARRAY_SIZE(uart4_pins[3]), + .modemuxs = uart4_modemux[3], + .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]), + }, { + .name = "uart4_92_93_grp", + .pins = uart4_pins[4], + .npins = ARRAY_SIZE(uart4_pins[4]), + .modemuxs = uart4_modemux[4], + .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]), + }, { + .name = "uart4_100_101_grp", + .pins = uart4_pins[5], + .npins = ARRAY_SIZE(uart4_pins[5]), + .modemuxs = uart4_modemux[5], + .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]), + }, +}; + +static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp", + "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp", + "uart4_100_101_grp" }; + +static struct spear_function uart4_function = { + .name = "uart4", + .groups = uart4_grps, + .ngroups = ARRAY_SIZE(uart4_grps), +}; + +/* Pad multiplexing for uart5 device */ +static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 }, + { 90, 91 } }; + +static struct spear_muxreg uart5_ext_4_5_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_I2C_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_4_5_MASK, + .val = PMX_UART5_PL_4_5_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART5_PORT_SEL_MASK, + .val = PMX_UART5_PORT_4_VAL, + }, +}; + +static struct spear_muxreg uart5_ext_37_38_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_37_38_MASK, + .val = PMX_UART5_PL_37_38_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART5_PORT_SEL_MASK, + .val = PMX_UART5_PORT_37_VAL, + }, +}; + +static struct spear_muxreg uart5_ext_69_70_muxreg[] = { + { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_69_MASK, + .val = PMX_UART5_PL_69_VAL, + }, { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_70_MASK, + .val = PMX_UART5_PL_70_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART5_PORT_SEL_MASK, + .val = PMX_UART5_PORT_69_VAL, + }, +}; + +static struct spear_muxreg uart5_ext_90_91_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_90_91_MASK, + .val = PMX_UART5_PL_90_91_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART5_PORT_SEL_MASK, + .val = PMX_UART5_PORT_90_VAL, + }, +}; + +static struct spear_modemux uart5_modemux[][1] = { + { + /* Select signals on pins 4_5 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart5_ext_4_5_muxreg, + .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg), + }, + }, { + /* Select signals on pins 37_38 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart5_ext_37_38_muxreg, + .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg), + }, + }, { + /* Select signals on pins 69_70 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart5_ext_69_70_muxreg, + .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg), + }, + }, { + /* Select signals on pins 90_91 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart5_ext_90_91_muxreg, + .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg), + }, + }, +}; + +static struct spear_pingroup uart5_pingroup[] = { + { + .name = "uart5_4_5_grp", + .pins = uart5_pins[0], + .npins = ARRAY_SIZE(uart5_pins[0]), + .modemuxs = uart5_modemux[0], + .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]), + }, { + .name = "uart5_37_38_grp", + .pins = uart5_pins[1], + .npins = ARRAY_SIZE(uart5_pins[1]), + .modemuxs = uart5_modemux[1], + .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]), + }, { + .name = "uart5_69_70_grp", + .pins = uart5_pins[2], + .npins = ARRAY_SIZE(uart5_pins[2]), + .modemuxs = uart5_modemux[2], + .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]), + }, { + .name = "uart5_90_91_grp", + .pins = uart5_pins[3], + .npins = ARRAY_SIZE(uart5_pins[3]), + .modemuxs = uart5_modemux[3], + .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]), + }, +}; + +static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp", + "uart5_69_70_grp", "uart5_90_91_grp" }; +static struct spear_function uart5_function = { + .name = "uart5", + .groups = uart5_grps, + .ngroups = ARRAY_SIZE(uart5_grps), +}; + +/* Pad multiplexing for uart6 device */ +static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } }; +static struct spear_muxreg uart6_ext_2_3_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_2_3_MASK, + .val = PMX_UART6_PL_2_3_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART6_PORT_SEL_MASK, + .val = PMX_UART6_PORT_2_VAL, + }, +}; + +static struct spear_muxreg uart6_ext_88_89_muxreg[] = { + { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_88_89_MASK, + .val = PMX_UART6_PL_88_89_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART6_PORT_SEL_MASK, + .val = PMX_UART6_PORT_88_VAL, + }, +}; + +static struct spear_modemux uart6_modemux[][1] = { + { + /* Select signals on pins 2_3 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart6_ext_2_3_muxreg, + .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg), + }, + }, { + /* Select signals on pins 88_89 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart6_ext_88_89_muxreg, + .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg), + }, + }, +}; + +static struct spear_pingroup uart6_pingroup[] = { + { + .name = "uart6_2_3_grp", + .pins = uart6_pins[0], + .npins = ARRAY_SIZE(uart6_pins[0]), + .modemuxs = uart6_modemux[0], + .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]), + }, { + .name = "uart6_88_89_grp", + .pins = uart6_pins[1], + .npins = ARRAY_SIZE(uart6_pins[1]), + .modemuxs = uart6_modemux[1], + .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]), + }, +}; + +static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" }; +static struct spear_function uart6_function = { + .name = "uart6", + .groups = uart6_grps, + .ngroups = ARRAY_SIZE(uart6_grps), +}; + +/* UART - RS485 pmx */ +static const unsigned rs485_pins[] = { 77, 78, 79 }; +static struct spear_muxreg rs485_muxreg[] = { + { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_77_78_79_MASK, + .val = PMX_RS485_PL_77_78_79_VAL, + }, +}; + +static struct spear_modemux rs485_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = rs485_muxreg, + .nmuxregs = ARRAY_SIZE(rs485_muxreg), + }, +}; + +static struct spear_pingroup rs485_pingroup = { + .name = "rs485_grp", + .pins = rs485_pins, + .npins = ARRAY_SIZE(rs485_pins), + .modemuxs = rs485_modemux, + .nmodemuxs = ARRAY_SIZE(rs485_modemux), +}; + +static const char *const rs485_grps[] = { "rs485_grp" }; +static struct spear_function rs485_function = { + .name = "rs485", + .groups = rs485_grps, + .ngroups = ARRAY_SIZE(rs485_grps), +}; + +/* Pad multiplexing for Touchscreen device */ +static const unsigned touchscreen_pins[] = { 5, 36 }; +static struct spear_muxreg touchscreen_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg touchscreen_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_5_MASK, + .val = PMX_TOUCH_Y_PL_5_VAL, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_36_MASK, + .val = PMX_TOUCH_X_PL_36_VAL, + }, +}; + +static struct spear_modemux touchscreen_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, + .muxregs = touchscreen_muxreg, + .nmuxregs = ARRAY_SIZE(touchscreen_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = touchscreen_ext_muxreg, + .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg), + }, +}; + +static struct spear_pingroup touchscreen_pingroup = { + .name = "touchscreen_grp", + .pins = touchscreen_pins, + .npins = ARRAY_SIZE(touchscreen_pins), + .modemuxs = touchscreen_modemux, + .nmodemuxs = ARRAY_SIZE(touchscreen_modemux), +}; + +static const char *const touchscreen_grps[] = { "touchscreen_grp" }; +static struct spear_function touchscreen_function = { + .name = "touchscreen", + .groups = touchscreen_grps, + .ngroups = ARRAY_SIZE(touchscreen_grps), +}; + +/* Pad multiplexing for CAN device */ +static const unsigned can0_pins[] = { 32, 33 }; +static struct spear_muxreg can0_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg can0_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_32_33_MASK, + .val = PMX_CAN0_PL_32_33_VAL, + }, +}; + +static struct spear_modemux can0_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE + | EXTENDED_MODE, + .muxregs = can0_muxreg, + .nmuxregs = ARRAY_SIZE(can0_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = can0_ext_muxreg, + .nmuxregs = ARRAY_SIZE(can0_ext_muxreg), + }, +}; + +static struct spear_pingroup can0_pingroup = { + .name = "can0_grp", + .pins = can0_pins, + .npins = ARRAY_SIZE(can0_pins), + .modemuxs = can0_modemux, + .nmodemuxs = ARRAY_SIZE(can0_modemux), +}; + +static const char *const can0_grps[] = { "can0_grp" }; +static struct spear_function can0_function = { + .name = "can0", + .groups = can0_grps, + .ngroups = ARRAY_SIZE(can0_grps), +}; + +static const unsigned can1_pins[] = { 30, 31 }; +static struct spear_muxreg can1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg can1_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_30_31_MASK, + .val = PMX_CAN1_PL_30_31_VAL, + }, +}; + +static struct spear_modemux can1_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE + | EXTENDED_MODE, + .muxregs = can1_muxreg, + .nmuxregs = ARRAY_SIZE(can1_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = can1_ext_muxreg, + .nmuxregs = ARRAY_SIZE(can1_ext_muxreg), + }, +}; + +static struct spear_pingroup can1_pingroup = { + .name = "can1_grp", + .pins = can1_pins, + .npins = ARRAY_SIZE(can1_pins), + .modemuxs = can1_modemux, + .nmodemuxs = ARRAY_SIZE(can1_modemux), +}; + +static const char *const can1_grps[] = { "can1_grp" }; +static struct spear_function can1_function = { + .name = "can1", + .groups = can1_grps, + .ngroups = ARRAY_SIZE(can1_grps), +}; + +/* Pad multiplexing for PWM0_1 device */ +static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 }, + { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } }; + +static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_8_9_MASK, + .val = PMX_PWM_0_1_PL_8_9_VAL, + }, +}; + +static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_14_MASK | PMX_PL_15_MASK, + .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL, + }, +}; + +static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_30_MASK | PMX_PL_31_MASK, + .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL, + }, +}; + +static struct spear_muxreg pwm0_1_net_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_37_38_MASK, + .val = PMX_PWM0_1_PL_37_38_VAL, + }, +}; + +static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK , + .val = 0, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_42_MASK | PMX_PL_43_MASK, + .val = PMX_PWM1_PL_42_VAL | + PMX_PWM0_PL_43_VAL, + }, +}; + +static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = { + { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_59_MASK, + .val = PMX_PWM1_PL_59_VAL, + }, { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_60_MASK, + .val = PMX_PWM0_PL_60_VAL, + }, +}; + +static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = { + { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_88_89_MASK, + .val = PMX_PWM0_1_PL_88_89_VAL, + }, +}; + +static struct spear_modemux pwm0_1_pin_8_9_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_8_9_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg), + }, +}; + +static struct spear_modemux pwm0_1_pin_14_15_modemux[] = { + { + .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = pwm0_1_autoexpsmallpri_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_14_15_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg), + }, +}; + +static struct spear_modemux pwm0_1_pin_30_31_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_30_31_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg), + }, +}; + +static struct spear_modemux pwm0_1_pin_37_38_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, + .muxregs = pwm0_1_net_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_37_38_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg), + }, +}; + +static struct spear_modemux pwm0_1_pin_42_43_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_42_43_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg), + }, +}; + +static struct spear_modemux pwm0_1_pin_59_60_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_59_60_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg), + }, +}; + +static struct spear_modemux pwm0_1_pin_88_89_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_88_89_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg), + }, +}; + +static struct spear_pingroup pwm0_1_pingroup[] = { + { + .name = "pwm0_1_pin_8_9_grp", + .pins = pwm0_1_pins[0], + .npins = ARRAY_SIZE(pwm0_1_pins[0]), + .modemuxs = pwm0_1_pin_8_9_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux), + }, { + .name = "pwm0_1_pin_14_15_grp", + .pins = pwm0_1_pins[1], + .npins = ARRAY_SIZE(pwm0_1_pins[1]), + .modemuxs = pwm0_1_pin_14_15_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux), + }, { + .name = "pwm0_1_pin_30_31_grp", + .pins = pwm0_1_pins[2], + .npins = ARRAY_SIZE(pwm0_1_pins[2]), + .modemuxs = pwm0_1_pin_30_31_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux), + }, { + .name = "pwm0_1_pin_37_38_grp", + .pins = pwm0_1_pins[3], + .npins = ARRAY_SIZE(pwm0_1_pins[3]), + .modemuxs = pwm0_1_pin_37_38_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux), + }, { + .name = "pwm0_1_pin_42_43_grp", + .pins = pwm0_1_pins[4], + .npins = ARRAY_SIZE(pwm0_1_pins[4]), + .modemuxs = pwm0_1_pin_42_43_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux), + }, { + .name = "pwm0_1_pin_59_60_grp", + .pins = pwm0_1_pins[5], + .npins = ARRAY_SIZE(pwm0_1_pins[5]), + .modemuxs = pwm0_1_pin_59_60_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux), + }, { + .name = "pwm0_1_pin_88_89_grp", + .pins = pwm0_1_pins[6], + .npins = ARRAY_SIZE(pwm0_1_pins[6]), + .modemuxs = pwm0_1_pin_88_89_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux), + }, +}; + +static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp", + "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", + "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp" +}; + +static struct spear_function pwm0_1_function = { + .name = "pwm0_1", + .groups = pwm0_1_grps, + .ngroups = ARRAY_SIZE(pwm0_1_grps), +}; + +/* Pad multiplexing for PWM2 device */ +static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 }, + { 58 }, { 87 } }; +static struct spear_muxreg pwm2_net_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg pwm2_pin_7_muxreg[] = { + { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_7_MASK, + .val = PMX_PWM_2_PL_7_VAL, + }, +}; + +static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg pwm2_pin_13_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_13_MASK, + .val = PMX_PWM2_PL_13_VAL, + }, +}; + +static struct spear_muxreg pwm2_pin_29_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN1_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_29_MASK, + .val = PMX_PWM_2_PL_29_VAL, + }, +}; + +static struct spear_muxreg pwm2_pin_34_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_34_MASK, + .val = PMX_PWM2_PL_34_VAL, + }, +}; + +static struct spear_muxreg pwm2_pin_41_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_41_MASK, + .val = PMX_PWM2_PL_41_VAL, + }, +}; + +static struct spear_muxreg pwm2_pin_58_muxreg[] = { + { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_58_MASK, + .val = PMX_PWM2_PL_58_VAL, + }, +}; + +static struct spear_muxreg pwm2_pin_87_muxreg[] = { + { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_87_MASK, + .val = PMX_PWM2_PL_87_VAL, + }, +}; + +static struct spear_modemux pwm2_pin_7_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, + .muxregs = pwm2_net_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_7_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg), + }, +}; +static struct spear_modemux pwm2_pin_13_modemux[] = { + { + .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = pwm2_autoexpsmallpri_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_13_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg), + }, +}; +static struct spear_modemux pwm2_pin_29_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_29_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg), + }, +}; +static struct spear_modemux pwm2_pin_34_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_34_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg), + }, +}; + +static struct spear_modemux pwm2_pin_41_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_41_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg), + }, +}; + +static struct spear_modemux pwm2_pin_58_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_58_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg), + }, +}; + +static struct spear_modemux pwm2_pin_87_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_87_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg), + }, +}; + +static struct spear_pingroup pwm2_pingroup[] = { + { + .name = "pwm2_pin_7_grp", + .pins = pwm2_pins[0], + .npins = ARRAY_SIZE(pwm2_pins[0]), + .modemuxs = pwm2_pin_7_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux), + }, { + .name = "pwm2_pin_13_grp", + .pins = pwm2_pins[1], + .npins = ARRAY_SIZE(pwm2_pins[1]), + .modemuxs = pwm2_pin_13_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux), + }, { + .name = "pwm2_pin_29_grp", + .pins = pwm2_pins[2], + .npins = ARRAY_SIZE(pwm2_pins[2]), + .modemuxs = pwm2_pin_29_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux), + }, { + .name = "pwm2_pin_34_grp", + .pins = pwm2_pins[3], + .npins = ARRAY_SIZE(pwm2_pins[3]), + .modemuxs = pwm2_pin_34_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux), + }, { + .name = "pwm2_pin_41_grp", + .pins = pwm2_pins[4], + .npins = ARRAY_SIZE(pwm2_pins[4]), + .modemuxs = pwm2_pin_41_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux), + }, { + .name = "pwm2_pin_58_grp", + .pins = pwm2_pins[5], + .npins = ARRAY_SIZE(pwm2_pins[5]), + .modemuxs = pwm2_pin_58_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux), + }, { + .name = "pwm2_pin_87_grp", + .pins = pwm2_pins[6], + .npins = ARRAY_SIZE(pwm2_pins[6]), + .modemuxs = pwm2_pin_87_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux), + }, +}; + +static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp", + "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp", + "pwm2_pin_58_grp", "pwm2_pin_87_grp" }; +static struct spear_function pwm2_function = { + .name = "pwm2", + .groups = pwm2_grps, + .ngroups = ARRAY_SIZE(pwm2_grps), +}; + +/* Pad multiplexing for PWM3 device */ +static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 }, + { 86 } }; +static struct spear_muxreg pwm3_pin_6_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_6_MASK, + .val = PMX_PWM_3_PL_6_VAL, + }, +}; + +static struct spear_muxreg pwm3_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg pwm3_pin_12_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_12_MASK, + .val = PMX_PWM3_PL_12_VAL, + }, +}; + +static struct spear_muxreg pwm3_pin_28_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN0_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_28_MASK, + .val = PMX_PWM_3_PL_28_VAL, + }, +}; + +static struct spear_muxreg pwm3_pin_40_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_40_MASK, + .val = PMX_PWM3_PL_40_VAL, + }, +}; + +static struct spear_muxreg pwm3_pin_57_muxreg[] = { + { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_57_MASK, + .val = PMX_PWM3_PL_57_VAL, + }, +}; + +static struct spear_muxreg pwm3_pin_86_muxreg[] = { + { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_86_MASK, + .val = PMX_PWM3_PL_86_VAL, + }, +}; + +static struct spear_modemux pwm3_pin_6_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm3_pin_6_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg), + }, +}; + +static struct spear_modemux pwm3_pin_12_modemux[] = { + { + .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | + AUTO_NET_SMII_MODE | EXTENDED_MODE, + .muxregs = pwm3_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = pwm3_pin_12_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg), + }, +}; + +static struct spear_modemux pwm3_pin_28_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm3_pin_28_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg), + }, +}; + +static struct spear_modemux pwm3_pin_40_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm3_pin_40_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg), + }, +}; + +static struct spear_modemux pwm3_pin_57_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm3_pin_57_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg), + }, +}; + +static struct spear_modemux pwm3_pin_86_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm3_pin_86_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg), + }, +}; + +static struct spear_pingroup pwm3_pingroup[] = { + { + .name = "pwm3_pin_6_grp", + .pins = pwm3_pins[0], + .npins = ARRAY_SIZE(pwm3_pins[0]), + .modemuxs = pwm3_pin_6_modemux, + .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux), + }, { + .name = "pwm3_pin_12_grp", + .pins = pwm3_pins[1], + .npins = ARRAY_SIZE(pwm3_pins[1]), + .modemuxs = pwm3_pin_12_modemux, + .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux), + }, { + .name = "pwm3_pin_28_grp", + .pins = pwm3_pins[2], + .npins = ARRAY_SIZE(pwm3_pins[2]), + .modemuxs = pwm3_pin_28_modemux, + .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux), + }, { + .name = "pwm3_pin_40_grp", + .pins = pwm3_pins[3], + .npins = ARRAY_SIZE(pwm3_pins[3]), + .modemuxs = pwm3_pin_40_modemux, + .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux), + }, { + .name = "pwm3_pin_57_grp", + .pins = pwm3_pins[4], + .npins = ARRAY_SIZE(pwm3_pins[4]), + .modemuxs = pwm3_pin_57_modemux, + .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux), + }, { + .name = "pwm3_pin_86_grp", + .pins = pwm3_pins[5], + .npins = ARRAY_SIZE(pwm3_pins[5]), + .modemuxs = pwm3_pin_86_modemux, + .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux), + }, +}; + +static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp", + "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp", + "pwm3_pin_86_grp" }; +static struct spear_function pwm3_function = { + .name = "pwm3", + .groups = pwm3_grps, + .ngroups = ARRAY_SIZE(pwm3_grps), +}; + +/* Pad multiplexing for SSP1 device */ +static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 }, + { 65, 68 }, { 94, 97 } }; +static struct spear_muxreg ssp1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg ssp1_ext_17_20_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK, + .val = PMX_SSP1_PL_17_18_19_20_VAL, + }, { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_20_MASK, + .val = PMX_SSP1_PL_17_18_19_20_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP1_PORT_SEL_MASK, + .val = PMX_SSP1_PORT_17_TO_20_VAL, + }, +}; + +static struct spear_muxreg ssp1_ext_36_39_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK, + .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL | + PMX_SSP1_PL_39_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP1_PORT_SEL_MASK, + .val = PMX_SSP1_PORT_36_TO_39_VAL, + }, +}; + +static struct spear_muxreg ssp1_ext_48_51_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_48_49_MASK, + .val = PMX_SSP1_PL_48_49_VAL, + }, { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_50_51_MASK, + .val = PMX_SSP1_PL_50_51_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP1_PORT_SEL_MASK, + .val = PMX_SSP1_PORT_48_TO_51_VAL, + }, +}; + +static struct spear_muxreg ssp1_ext_65_68_muxreg[] = { + { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_65_TO_68_MASK, + .val = PMX_SSP1_PL_65_TO_68_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP1_PORT_SEL_MASK, + .val = PMX_SSP1_PORT_65_TO_68_VAL, + }, +}; + +static struct spear_muxreg ssp1_ext_94_97_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, + .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP1_PORT_SEL_MASK, + .val = PMX_SSP1_PORT_94_TO_97_VAL, + }, +}; + +static struct spear_modemux ssp1_17_20_modemux[] = { + { + .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE | + EXTENDED_MODE, + .muxregs = ssp1_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = ssp1_ext_17_20_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg), + }, +}; + +static struct spear_modemux ssp1_36_39_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp1_ext_36_39_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg), + }, +}; + +static struct spear_modemux ssp1_48_51_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp1_ext_48_51_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg), + }, +}; +static struct spear_modemux ssp1_65_68_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp1_ext_65_68_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg), + }, +}; + +static struct spear_modemux ssp1_94_97_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp1_ext_94_97_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg), + }, +}; + +static struct spear_pingroup ssp1_pingroup[] = { + { + .name = "ssp1_17_20_grp", + .pins = ssp1_pins[0], + .npins = ARRAY_SIZE(ssp1_pins[0]), + .modemuxs = ssp1_17_20_modemux, + .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux), + }, { + .name = "ssp1_36_39_grp", + .pins = ssp1_pins[1], + .npins = ARRAY_SIZE(ssp1_pins[1]), + .modemuxs = ssp1_36_39_modemux, + .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux), + }, { + .name = "ssp1_48_51_grp", + .pins = ssp1_pins[2], + .npins = ARRAY_SIZE(ssp1_pins[2]), + .modemuxs = ssp1_48_51_modemux, + .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux), + }, { + .name = "ssp1_65_68_grp", + .pins = ssp1_pins[3], + .npins = ARRAY_SIZE(ssp1_pins[3]), + .modemuxs = ssp1_65_68_modemux, + .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux), + }, { + .name = "ssp1_94_97_grp", + .pins = ssp1_pins[4], + .npins = ARRAY_SIZE(ssp1_pins[4]), + .modemuxs = ssp1_94_97_modemux, + .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux), + }, +}; + +static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp", + "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp" +}; +static struct spear_function ssp1_function = { + .name = "ssp1", + .groups = ssp1_grps, + .ngroups = ARRAY_SIZE(ssp1_grps), +}; + +/* Pad multiplexing for SSP2 device */ +static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 }, + { 61, 64 }, { 90, 93 } }; +static struct spear_muxreg ssp2_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg ssp2_ext_13_16_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK, + .val = PMX_SSP2_PL_13_14_15_16_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP2_PORT_SEL_MASK, + .val = PMX_SSP2_PORT_13_TO_16_VAL, + }, +}; + +static struct spear_muxreg ssp2_ext_32_35_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK | + PMX_GPIO_PIN5_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK, + .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL | + PMX_SSP2_PL_35_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP2_PORT_SEL_MASK, + .val = PMX_SSP2_PORT_32_TO_35_VAL, + }, +}; + +static struct spear_muxreg ssp2_ext_44_47_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK, + .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP2_PORT_SEL_MASK, + .val = PMX_SSP2_PORT_44_TO_47_VAL, + }, +}; + +static struct spear_muxreg ssp2_ext_61_64_muxreg[] = { + { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_61_TO_64_MASK, + .val = PMX_SSP2_PL_61_TO_64_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP2_PORT_SEL_MASK, + .val = PMX_SSP2_PORT_61_TO_64_VAL, + }, +}; + +static struct spear_muxreg ssp2_ext_90_93_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK, + .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP2_PORT_SEL_MASK, + .val = PMX_SSP2_PORT_90_TO_93_VAL, + }, +}; + +static struct spear_modemux ssp2_13_16_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, + .muxregs = ssp2_muxreg, + .nmuxregs = ARRAY_SIZE(ssp2_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = ssp2_ext_13_16_muxreg, + .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg), + }, +}; + +static struct spear_modemux ssp2_32_35_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp2_ext_32_35_muxreg, + .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg), + }, +}; + +static struct spear_modemux ssp2_44_47_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp2_ext_44_47_muxreg, + .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg), + }, +}; + +static struct spear_modemux ssp2_61_64_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp2_ext_61_64_muxreg, + .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg), + }, +}; + +static struct spear_modemux ssp2_90_93_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp2_ext_90_93_muxreg, + .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg), + }, +}; + +static struct spear_pingroup ssp2_pingroup[] = { + { + .name = "ssp2_13_16_grp", + .pins = ssp2_pins[0], + .npins = ARRAY_SIZE(ssp2_pins[0]), + .modemuxs = ssp2_13_16_modemux, + .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux), + }, { + .name = "ssp2_32_35_grp", + .pins = ssp2_pins[1], + .npins = ARRAY_SIZE(ssp2_pins[1]), + .modemuxs = ssp2_32_35_modemux, + .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux), + }, { + .name = "ssp2_44_47_grp", + .pins = ssp2_pins[2], + .npins = ARRAY_SIZE(ssp2_pins[2]), + .modemuxs = ssp2_44_47_modemux, + .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux), + }, { + .name = "ssp2_61_64_grp", + .pins = ssp2_pins[3], + .npins = ARRAY_SIZE(ssp2_pins[3]), + .modemuxs = ssp2_61_64_modemux, + .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux), + }, { + .name = "ssp2_90_93_grp", + .pins = ssp2_pins[4], + .npins = ARRAY_SIZE(ssp2_pins[4]), + .modemuxs = ssp2_90_93_modemux, + .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux), + }, +}; + +static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp", + "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" }; +static struct spear_function ssp2_function = { + .name = "ssp2", + .groups = ssp2_grps, + .ngroups = ARRAY_SIZE(ssp2_grps), +}; + +/* Pad multiplexing for cadence mii2 as mii device */ +static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, + 90, 91, 92, 93, 94, 95, 96, 97 }; +static struct spear_muxreg mii2_muxreg[] = { + { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | + PMX_PL_88_89_MASK, + .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL | + PMX_MII2_PL_88_89_VAL, + }, { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | + PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, + .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL | + PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL, + }, { + .reg = EXT_CTRL_REG, + .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | + (MAC_MODE_MASK << MAC1_MODE_SHIFT) | + MII_MDIO_MASK, + .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) | + (MAC_MODE_MII << MAC1_MODE_SHIFT) | + MII_MDIO_81_VAL, + }, +}; + +static struct spear_modemux mii2_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = mii2_muxreg, + .nmuxregs = ARRAY_SIZE(mii2_muxreg), + }, +}; + +static struct spear_pingroup mii2_pingroup = { + .name = "mii2_grp", + .pins = mii2_pins, + .npins = ARRAY_SIZE(mii2_pins), + .modemuxs = mii2_modemux, + .nmodemuxs = ARRAY_SIZE(mii2_modemux), +}; + +static const char *const mii2_grps[] = { "mii2_grp" }; +static struct spear_function mii2_function = { + .name = "mii2", + .groups = mii2_grps, + .ngroups = ARRAY_SIZE(mii2_grps), +}; + +/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */ +static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27 }; +static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 }; +static struct spear_muxreg mii0_1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg smii0_1_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_10_11_MASK, + .val = PMX_SMII_PL_10_11_VAL, + }, { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_21_TO_27_MASK, + .val = PMX_SMII_PL_21_TO_27_VAL, + }, { + .reg = EXT_CTRL_REG, + .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | + (MAC_MODE_MASK << MAC1_MODE_SHIFT) | + MII_MDIO_MASK, + .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT) + | (MAC_MODE_SMII << MAC1_MODE_SHIFT) + | MII_MDIO_10_11_VAL, + }, +}; + +static struct spear_muxreg rmii0_1_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK | + PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK, + .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL | + PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL | + PMX_RMII_PL_19_VAL, + }, { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK, + .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL, + }, { + .reg = EXT_CTRL_REG, + .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | + (MAC_MODE_MASK << MAC1_MODE_SHIFT) | + MII_MDIO_MASK, + .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT) + | (MAC_MODE_RMII << MAC1_MODE_SHIFT) + | MII_MDIO_10_11_VAL, + }, +}; + +static struct spear_modemux mii0_1_modemux[][2] = { + { + /* configure as smii */ + { + .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | + SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = mii0_1_muxreg, + .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = smii0_1_ext_muxreg, + .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg), + }, + }, { + /* configure as rmii */ + { + .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | + SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = mii0_1_muxreg, + .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = rmii0_1_ext_muxreg, + .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg), + }, + }, +}; + +static struct spear_pingroup mii0_1_pingroup[] = { + { + .name = "smii0_1_grp", + .pins = smii0_1_pins, + .npins = ARRAY_SIZE(smii0_1_pins), + .modemuxs = mii0_1_modemux[0], + .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]), + }, { + .name = "rmii0_1_grp", + .pins = rmii0_1_pins, + .npins = ARRAY_SIZE(rmii0_1_pins), + .modemuxs = mii0_1_modemux[1], + .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]), + }, +}; + +static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" }; +static struct spear_function mii0_1_function = { + .name = "mii0_1", + .groups = mii0_1_grps, + .ngroups = ARRAY_SIZE(mii0_1_grps), +}; + +/* Pad multiplexing for i2c1 device */ +static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } }; +static struct spear_muxreg i2c1_ext_8_9_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_8_9_MASK, + .val = PMX_I2C1_PL_8_9_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C1_PORT_SEL_MASK, + .val = PMX_I2C1_PORT_8_9_VAL, + }, +}; + +static struct spear_muxreg i2c1_ext_98_99_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, + .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C1_PORT_SEL_MASK, + .val = PMX_I2C1_PORT_98_99_VAL, + }, +}; + +static struct spear_modemux i2c1_modemux[][1] = { + { + /* Select signals on pins 8-9 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c1_ext_8_9_muxreg, + .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg), + }, + }, { + /* Select signals on pins 98-99 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c1_ext_98_99_muxreg, + .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg), + }, + }, +}; + +static struct spear_pingroup i2c1_pingroup[] = { + { + .name = "i2c1_8_9_grp", + .pins = i2c1_pins[0], + .npins = ARRAY_SIZE(i2c1_pins[0]), + .modemuxs = i2c1_modemux[0], + .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]), + }, { + .name = "i2c1_98_99_grp", + .pins = i2c1_pins[1], + .npins = ARRAY_SIZE(i2c1_pins[1]), + .modemuxs = i2c1_modemux[1], + .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]), + }, +}; + +static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" }; +static struct spear_function i2c1_function = { + .name = "i2c1", + .groups = i2c1_grps, + .ngroups = ARRAY_SIZE(i2c1_grps), +}; + +/* Pad multiplexing for i2c2 device */ +static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 }, + { 75, 76 }, { 96, 97 } }; +static struct spear_muxreg i2c2_ext_0_1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_FIRDA_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_0_1_MASK, + .val = PMX_I2C2_PL_0_1_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C2_PORT_SEL_MASK, + .val = PMX_I2C2_PORT_0_1_VAL, + }, +}; + +static struct spear_muxreg i2c2_ext_2_3_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_2_3_MASK, + .val = PMX_I2C2_PL_2_3_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C2_PORT_SEL_MASK, + .val = PMX_I2C2_PORT_2_3_VAL, + }, +}; + +static struct spear_muxreg i2c2_ext_19_20_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_19_MASK, + .val = PMX_I2C2_PL_19_VAL, + }, { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_20_MASK, + .val = PMX_I2C2_PL_20_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C2_PORT_SEL_MASK, + .val = PMX_I2C2_PORT_19_20_VAL, + }, +}; + +static struct spear_muxreg i2c2_ext_75_76_muxreg[] = { + { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_75_76_MASK, + .val = PMX_I2C2_PL_75_76_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C2_PORT_SEL_MASK, + .val = PMX_I2C2_PORT_75_76_VAL, + }, +}; + +static struct spear_muxreg i2c2_ext_96_97_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_96_97_MASK, + .val = PMX_I2C2_PL_96_97_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C2_PORT_SEL_MASK, + .val = PMX_I2C2_PORT_96_97_VAL, + }, +}; + +static struct spear_modemux i2c2_modemux[][1] = { + { + /* Select signals on pins 0_1 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c2_ext_0_1_muxreg, + .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg), + }, + }, { + /* Select signals on pins 2_3 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c2_ext_2_3_muxreg, + .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg), + }, + }, { + /* Select signals on pins 19_20 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c2_ext_19_20_muxreg, + .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg), + }, + }, { + /* Select signals on pins 75_76 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c2_ext_75_76_muxreg, + .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg), + }, + }, { + /* Select signals on pins 96_97 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c2_ext_96_97_muxreg, + .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg), + }, + }, +}; + +static struct spear_pingroup i2c2_pingroup[] = { + { + .name = "i2c2_0_1_grp", + .pins = i2c2_pins[0], + .npins = ARRAY_SIZE(i2c2_pins[0]), + .modemuxs = i2c2_modemux[0], + .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]), + }, { + .name = "i2c2_2_3_grp", + .pins = i2c2_pins[1], + .npins = ARRAY_SIZE(i2c2_pins[1]), + .modemuxs = i2c2_modemux[1], + .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]), + }, { + .name = "i2c2_19_20_grp", + .pins = i2c2_pins[2], + .npins = ARRAY_SIZE(i2c2_pins[2]), + .modemuxs = i2c2_modemux[2], + .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]), + }, { + .name = "i2c2_75_76_grp", + .pins = i2c2_pins[3], + .npins = ARRAY_SIZE(i2c2_pins[3]), + .modemuxs = i2c2_modemux[3], + .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]), + }, { + .name = "i2c2_96_97_grp", + .pins = i2c2_pins[4], + .npins = ARRAY_SIZE(i2c2_pins[4]), + .modemuxs = i2c2_modemux[4], + .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]), + }, +}; + +static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp", + "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" }; +static struct spear_function i2c2_function = { + .name = "i2c2", + .groups = i2c2_grps, + .ngroups = ARRAY_SIZE(i2c2_grps), +}; + +/* pingroups */ +static struct spear_pingroup *spear320_pingroups[] = { + SPEAR3XX_COMMON_PINGROUPS, + &clcd_pingroup, + &emi_pingroup, + &fsmc_8bit_pingroup, + &fsmc_16bit_pingroup, + &spp_pingroup, + &sdhci_led_pingroup, + &sdhci_pingroup[0], + &sdhci_pingroup[1], + &i2s_pingroup, + &uart1_pingroup, + &uart1_modem_pingroup[0], + &uart1_modem_pingroup[1], + &uart1_modem_pingroup[2], + &uart1_modem_pingroup[3], + &uart2_pingroup, + &uart3_pingroup[0], + &uart3_pingroup[1], + &uart3_pingroup[2], + &uart3_pingroup[3], + &uart3_pingroup[4], + &uart3_pingroup[5], + &uart3_pingroup[6], + &uart4_pingroup[0], + &uart4_pingroup[1], + &uart4_pingroup[2], + &uart4_pingroup[3], + &uart4_pingroup[4], + &uart4_pingroup[5], + &uart5_pingroup[0], + &uart5_pingroup[1], + &uart5_pingroup[2], + &uart5_pingroup[3], + &uart6_pingroup[0], + &uart6_pingroup[1], + &rs485_pingroup, + &touchscreen_pingroup, + &can0_pingroup, + &can1_pingroup, + &pwm0_1_pingroup[0], + &pwm0_1_pingroup[1], + &pwm0_1_pingroup[2], + &pwm0_1_pingroup[3], + &pwm0_1_pingroup[4], + &pwm0_1_pingroup[5], + &pwm0_1_pingroup[6], + &pwm2_pingroup[0], + &pwm2_pingroup[1], + &pwm2_pingroup[2], + &pwm2_pingroup[3], + &pwm2_pingroup[4], + &pwm2_pingroup[5], + &pwm2_pingroup[6], + &pwm3_pingroup[0], + &pwm3_pingroup[1], + &pwm3_pingroup[2], + &pwm3_pingroup[3], + &pwm3_pingroup[4], + &pwm3_pingroup[5], + &ssp1_pingroup[0], + &ssp1_pingroup[1], + &ssp1_pingroup[2], + &ssp1_pingroup[3], + &ssp1_pingroup[4], + &ssp2_pingroup[0], + &ssp2_pingroup[1], + &ssp2_pingroup[2], + &ssp2_pingroup[3], + &ssp2_pingroup[4], + &mii2_pingroup, + &mii0_1_pingroup[0], + &mii0_1_pingroup[1], + &i2c1_pingroup[0], + &i2c1_pingroup[1], + &i2c2_pingroup[0], + &i2c2_pingroup[1], + &i2c2_pingroup[2], + &i2c2_pingroup[3], + &i2c2_pingroup[4], +}; + +/* functions */ +static struct spear_function *spear320_functions[] = { + SPEAR3XX_COMMON_FUNCTIONS, + &clcd_function, + &emi_function, + &fsmc_function, + &spp_function, + &sdhci_function, + &i2s_function, + &uart1_function, + &uart1_modem_function, + &uart2_function, + &uart3_function, + &uart4_function, + &uart5_function, + &uart6_function, + &rs485_function, + &touchscreen_function, + &can0_function, + &can1_function, + &pwm0_1_function, + &pwm2_function, + &pwm3_function, + &ssp1_function, + &ssp2_function, + &mii2_function, + &mii0_1_function, + &i2c1_function, + &i2c2_function, +}; + +static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = { + { + .compatible = "st,spear320-pinmux", + }, + {}, +}; + +static int __devinit spear320_pinctrl_probe(struct platform_device *pdev) +{ + int ret; + + spear3xx_machdata.groups = spear320_pingroups; + spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups); + spear3xx_machdata.functions = spear320_functions; + spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions); + + spear3xx_machdata.modes_supported = true; + spear3xx_machdata.pmx_modes = spear320_pmx_modes; + spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes); + + pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); + + ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); + if (ret) + return ret; + + return 0; +} + +static int __devexit spear320_pinctrl_remove(struct platform_device *pdev) +{ + return spear_pinctrl_remove(pdev); +} + +static struct platform_driver spear320_pinctrl_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = spear320_pinctrl_of_match, + }, + .probe = spear320_pinctrl_probe, + .remove = __devexit_p(spear320_pinctrl_remove), +}; + +static int __init spear320_pinctrl_init(void) +{ + return platform_driver_register(&spear320_pinctrl_driver); +} +arch_initcall(spear320_pinctrl_init); + +static void __exit spear320_pinctrl_exit(void) +{ + platform_driver_unregister(&spear320_pinctrl_driver); +} +module_exit(spear320_pinctrl_exit); + +MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>"); +MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match); diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.c b/drivers/pinctrl/spear/pinctrl-spear3xx.c new file mode 100644 index 0000000..832049a --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear3xx.c @@ -0,0 +1,588 @@ +/* + * Driver for the ST Microelectronics SPEAr3xx pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-spear3xx.h" + +/* pins */ +static const struct pinctrl_pin_desc spear3xx_pins[] = { + PINCTRL_PIN(0, "PLGPIO0"), + PINCTRL_PIN(1, "PLGPIO1"), + PINCTRL_PIN(2, "PLGPIO2"), + PINCTRL_PIN(3, "PLGPIO3"), + PINCTRL_PIN(4, "PLGPIO4"), + PINCTRL_PIN(5, "PLGPIO5"), + PINCTRL_PIN(6, "PLGPIO6"), + PINCTRL_PIN(7, "PLGPIO7"), + PINCTRL_PIN(8, "PLGPIO8"), + PINCTRL_PIN(9, "PLGPIO9"), + PINCTRL_PIN(10, "PLGPIO10"), + PINCTRL_PIN(11, "PLGPIO11"), + PINCTRL_PIN(12, "PLGPIO12"), + PINCTRL_PIN(13, "PLGPIO13"), + PINCTRL_PIN(14, "PLGPIO14"), + PINCTRL_PIN(15, "PLGPIO15"), + PINCTRL_PIN(16, "PLGPIO16"), + PINCTRL_PIN(17, "PLGPIO17"), + PINCTRL_PIN(18, "PLGPIO18"), + PINCTRL_PIN(19, "PLGPIO19"), + PINCTRL_PIN(20, "PLGPIO20"), + PINCTRL_PIN(21, "PLGPIO21"), + PINCTRL_PIN(22, "PLGPIO22"), + PINCTRL_PIN(23, "PLGPIO23"), + PINCTRL_PIN(24, "PLGPIO24"), + PINCTRL_PIN(25, "PLGPIO25"), + PINCTRL_PIN(26, "PLGPIO26"), + PINCTRL_PIN(27, "PLGPIO27"), + PINCTRL_PIN(28, "PLGPIO28"), + PINCTRL_PIN(29, "PLGPIO29"), + PINCTRL_PIN(30, "PLGPIO30"), + PINCTRL_PIN(31, "PLGPIO31"), + PINCTRL_PIN(32, "PLGPIO32"), + PINCTRL_PIN(33, "PLGPIO33"), + PINCTRL_PIN(34, "PLGPIO34"), + PINCTRL_PIN(35, "PLGPIO35"), + PINCTRL_PIN(36, "PLGPIO36"), + PINCTRL_PIN(37, "PLGPIO37"), + PINCTRL_PIN(38, "PLGPIO38"), + PINCTRL_PIN(39, "PLGPIO39"), + PINCTRL_PIN(40, "PLGPIO40"), + PINCTRL_PIN(41, "PLGPIO41"), + PINCTRL_PIN(42, "PLGPIO42"), + PINCTRL_PIN(43, "PLGPIO43"), + PINCTRL_PIN(44, "PLGPIO44"), + PINCTRL_PIN(45, "PLGPIO45"), + PINCTRL_PIN(46, "PLGPIO46"), + PINCTRL_PIN(47, "PLGPIO47"), + PINCTRL_PIN(48, "PLGPIO48"), + PINCTRL_PIN(49, "PLGPIO49"), + PINCTRL_PIN(50, "PLGPIO50"), + PINCTRL_PIN(51, "PLGPIO51"), + PINCTRL_PIN(52, "PLGPIO52"), + PINCTRL_PIN(53, "PLGPIO53"), + PINCTRL_PIN(54, "PLGPIO54"), + PINCTRL_PIN(55, "PLGPIO55"), + PINCTRL_PIN(56, "PLGPIO56"), + PINCTRL_PIN(57, "PLGPIO57"), + PINCTRL_PIN(58, "PLGPIO58"), + PINCTRL_PIN(59, "PLGPIO59"), + PINCTRL_PIN(60, "PLGPIO60"), + PINCTRL_PIN(61, "PLGPIO61"), + PINCTRL_PIN(62, "PLGPIO62"), + PINCTRL_PIN(63, "PLGPIO63"), + PINCTRL_PIN(64, "PLGPIO64"), + PINCTRL_PIN(65, "PLGPIO65"), + PINCTRL_PIN(66, "PLGPIO66"), + PINCTRL_PIN(67, "PLGPIO67"), + PINCTRL_PIN(68, "PLGPIO68"), + PINCTRL_PIN(69, "PLGPIO69"), + PINCTRL_PIN(70, "PLGPIO70"), + PINCTRL_PIN(71, "PLGPIO71"), + PINCTRL_PIN(72, "PLGPIO72"), + PINCTRL_PIN(73, "PLGPIO73"), + PINCTRL_PIN(74, "PLGPIO74"), + PINCTRL_PIN(75, "PLGPIO75"), + PINCTRL_PIN(76, "PLGPIO76"), + PINCTRL_PIN(77, "PLGPIO77"), + PINCTRL_PIN(78, "PLGPIO78"), + PINCTRL_PIN(79, "PLGPIO79"), + PINCTRL_PIN(80, "PLGPIO80"), + PINCTRL_PIN(81, "PLGPIO81"), + PINCTRL_PIN(82, "PLGPIO82"), + PINCTRL_PIN(83, "PLGPIO83"), + PINCTRL_PIN(84, "PLGPIO84"), + PINCTRL_PIN(85, "PLGPIO85"), + PINCTRL_PIN(86, "PLGPIO86"), + PINCTRL_PIN(87, "PLGPIO87"), + PINCTRL_PIN(88, "PLGPIO88"), + PINCTRL_PIN(89, "PLGPIO89"), + PINCTRL_PIN(90, "PLGPIO90"), + PINCTRL_PIN(91, "PLGPIO91"), + PINCTRL_PIN(92, "PLGPIO92"), + PINCTRL_PIN(93, "PLGPIO93"), + PINCTRL_PIN(94, "PLGPIO94"), + PINCTRL_PIN(95, "PLGPIO95"), + PINCTRL_PIN(96, "PLGPIO96"), + PINCTRL_PIN(97, "PLGPIO97"), + PINCTRL_PIN(98, "PLGPIO98"), + PINCTRL_PIN(99, "PLGPIO99"), + PINCTRL_PIN(100, "PLGPIO100"), + PINCTRL_PIN(101, "PLGPIO101"), +}; + +/* firda_pins */ +static const unsigned firda_pins[] = { 0, 1 }; +static struct spear_muxreg firda_muxreg[] = { + { + .reg = -1, + .mask = PMX_FIRDA_MASK, + .val = PMX_FIRDA_MASK, + }, +}; + +static struct spear_modemux firda_modemux[] = { + { + .modes = ~0, + .muxregs = firda_muxreg, + .nmuxregs = ARRAY_SIZE(firda_muxreg), + }, +}; + +struct spear_pingroup spear3xx_firda_pingroup = { + .name = "firda_grp", + .pins = firda_pins, + .npins = ARRAY_SIZE(firda_pins), + .modemuxs = firda_modemux, + .nmodemuxs = ARRAY_SIZE(firda_modemux), +}; + +static const char *const firda_grps[] = { "firda_grp" }; +struct spear_function spear3xx_firda_function = { + .name = "firda", + .groups = firda_grps, + .ngroups = ARRAY_SIZE(firda_grps), +}; + +/* i2c_pins */ +static const unsigned i2c_pins[] = { 4, 5 }; +static struct spear_muxreg i2c_muxreg[] = { + { + .reg = -1, + .mask = PMX_I2C_MASK, + .val = PMX_I2C_MASK, + }, +}; + +static struct spear_modemux i2c_modemux[] = { + { + .modes = ~0, + .muxregs = i2c_muxreg, + .nmuxregs = ARRAY_SIZE(i2c_muxreg), + }, +}; + +struct spear_pingroup spear3xx_i2c_pingroup = { + .name = "i2c0_grp", + .pins = i2c_pins, + .npins = ARRAY_SIZE(i2c_pins), + .modemuxs = i2c_modemux, + .nmodemuxs = ARRAY_SIZE(i2c_modemux), +}; + +static const char *const i2c_grps[] = { "i2c0_grp" }; +struct spear_function spear3xx_i2c_function = { + .name = "i2c0", + .groups = i2c_grps, + .ngroups = ARRAY_SIZE(i2c_grps), +}; + +/* ssp_cs_pins */ +static const unsigned ssp_cs_pins[] = { 34, 35, 36 }; +static struct spear_muxreg ssp_cs_muxreg[] = { + { + .reg = -1, + .mask = PMX_SSP_CS_MASK, + .val = PMX_SSP_CS_MASK, + }, +}; + +static struct spear_modemux ssp_cs_modemux[] = { + { + .modes = ~0, + .muxregs = ssp_cs_muxreg, + .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg), + }, +}; + +struct spear_pingroup spear3xx_ssp_cs_pingroup = { + .name = "ssp_cs_grp", + .pins = ssp_cs_pins, + .npins = ARRAY_SIZE(ssp_cs_pins), + .modemuxs = ssp_cs_modemux, + .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux), +}; + +static const char *const ssp_cs_grps[] = { "ssp_cs_grp" }; +struct spear_function spear3xx_ssp_cs_function = { + .name = "ssp_cs", + .groups = ssp_cs_grps, + .ngroups = ARRAY_SIZE(ssp_cs_grps), +}; + +/* ssp_pins */ +static const unsigned ssp_pins[] = { 6, 7, 8, 9 }; +static struct spear_muxreg ssp_muxreg[] = { + { + .reg = -1, + .mask = PMX_SSP_MASK, + .val = PMX_SSP_MASK, + }, +}; + +static struct spear_modemux ssp_modemux[] = { + { + .modes = ~0, + .muxregs = ssp_muxreg, + .nmuxregs = ARRAY_SIZE(ssp_muxreg), + }, +}; + +struct spear_pingroup spear3xx_ssp_pingroup = { + .name = "ssp0_grp", + .pins = ssp_pins, + .npins = ARRAY_SIZE(ssp_pins), + .modemuxs = ssp_modemux, + .nmodemuxs = ARRAY_SIZE(ssp_modemux), +}; + +static const char *const ssp_grps[] = { "ssp0_grp" }; +struct spear_function spear3xx_ssp_function = { + .name = "ssp0", + .groups = ssp_grps, + .ngroups = ARRAY_SIZE(ssp_grps), +}; + +/* mii_pins */ +static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27 }; +static struct spear_muxreg mii_muxreg[] = { + { + .reg = -1, + .mask = PMX_MII_MASK, + .val = PMX_MII_MASK, + }, +}; + +static struct spear_modemux mii_modemux[] = { + { + .modes = ~0, + .muxregs = mii_muxreg, + .nmuxregs = ARRAY_SIZE(mii_muxreg), + }, +}; + +struct spear_pingroup spear3xx_mii_pingroup = { + .name = "mii0_grp", + .pins = mii_pins, + .npins = ARRAY_SIZE(mii_pins), + .modemuxs = mii_modemux, + .nmodemuxs = ARRAY_SIZE(mii_modemux), +}; + +static const char *const mii_grps[] = { "mii0_grp" }; +struct spear_function spear3xx_mii_function = { + .name = "mii0", + .groups = mii_grps, + .ngroups = ARRAY_SIZE(mii_grps), +}; + +/* gpio0_pin0_pins */ +static const unsigned gpio0_pin0_pins[] = { 28 }; +static struct spear_muxreg gpio0_pin0_muxreg[] = { + { + .reg = -1, + .mask = PMX_GPIO_PIN0_MASK, + .val = PMX_GPIO_PIN0_MASK, + }, +}; + +static struct spear_modemux gpio0_pin0_modemux[] = { + { + .modes = ~0, + .muxregs = gpio0_pin0_muxreg, + .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg), + }, +}; + +struct spear_pingroup spear3xx_gpio0_pin0_pingroup = { + .name = "gpio0_pin0_grp", + .pins = gpio0_pin0_pins, + .npins = ARRAY_SIZE(gpio0_pin0_pins), + .modemuxs = gpio0_pin0_modemux, + .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux), +}; + +/* gpio0_pin1_pins */ +static const unsigned gpio0_pin1_pins[] = { 29 }; +static struct spear_muxreg gpio0_pin1_muxreg[] = { + { + .reg = -1, + .mask = PMX_GPIO_PIN1_MASK, + .val = PMX_GPIO_PIN1_MASK, + }, +}; + +static struct spear_modemux gpio0_pin1_modemux[] = { + { + .modes = ~0, + .muxregs = gpio0_pin1_muxreg, + .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg), + }, +}; + +struct spear_pingroup spear3xx_gpio0_pin1_pingroup = { + .name = "gpio0_pin1_grp", + .pins = gpio0_pin1_pins, + .npins = ARRAY_SIZE(gpio0_pin1_pins), + .modemuxs = gpio0_pin1_modemux, + .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux), +}; + +/* gpio0_pin2_pins */ +static const unsigned gpio0_pin2_pins[] = { 30 }; +static struct spear_muxreg gpio0_pin2_muxreg[] = { + { + .reg = -1, + .mask = PMX_GPIO_PIN2_MASK, + .val = PMX_GPIO_PIN2_MASK, + }, +}; + +static struct spear_modemux gpio0_pin2_modemux[] = { + { + .modes = ~0, + .muxregs = gpio0_pin2_muxreg, + .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg), + }, +}; + +struct spear_pingroup spear3xx_gpio0_pin2_pingroup = { + .name = "gpio0_pin2_grp", + .pins = gpio0_pin2_pins, + .npins = ARRAY_SIZE(gpio0_pin2_pins), + .modemuxs = gpio0_pin2_modemux, + .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux), +}; + +/* gpio0_pin3_pins */ +static const unsigned gpio0_pin3_pins[] = { 31 }; +static struct spear_muxreg gpio0_pin3_muxreg[] = { + { + .reg = -1, + .mask = PMX_GPIO_PIN3_MASK, + .val = PMX_GPIO_PIN3_MASK, + }, +}; + +static struct spear_modemux gpio0_pin3_modemux[] = { + { + .modes = ~0, + .muxregs = gpio0_pin3_muxreg, + .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg), + }, +}; + +struct spear_pingroup spear3xx_gpio0_pin3_pingroup = { + .name = "gpio0_pin3_grp", + .pins = gpio0_pin3_pins, + .npins = ARRAY_SIZE(gpio0_pin3_pins), + .modemuxs = gpio0_pin3_modemux, + .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux), +}; + +/* gpio0_pin4_pins */ +static const unsigned gpio0_pin4_pins[] = { 32 }; +static struct spear_muxreg gpio0_pin4_muxreg[] = { + { + .reg = -1, + .mask = PMX_GPIO_PIN4_MASK, + .val = PMX_GPIO_PIN4_MASK, + }, +}; + +static struct spear_modemux gpio0_pin4_modemux[] = { + { + .modes = ~0, + .muxregs = gpio0_pin4_muxreg, + .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg), + }, +}; + +struct spear_pingroup spear3xx_gpio0_pin4_pingroup = { + .name = "gpio0_pin4_grp", + .pins = gpio0_pin4_pins, + .npins = ARRAY_SIZE(gpio0_pin4_pins), + .modemuxs = gpio0_pin4_modemux, + .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux), +}; + +/* gpio0_pin5_pins */ +static const unsigned gpio0_pin5_pins[] = { 33 }; +static struct spear_muxreg gpio0_pin5_muxreg[] = { + { + .reg = -1, + .mask = PMX_GPIO_PIN5_MASK, + .val = PMX_GPIO_PIN5_MASK, + }, +}; + +static struct spear_modemux gpio0_pin5_modemux[] = { + { + .modes = ~0, + .muxregs = gpio0_pin5_muxreg, + .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg), + }, +}; + +struct spear_pingroup spear3xx_gpio0_pin5_pingroup = { + .name = "gpio0_pin5_grp", + .pins = gpio0_pin5_pins, + .npins = ARRAY_SIZE(gpio0_pin5_pins), + .modemuxs = gpio0_pin5_modemux, + .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux), +}; + +static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp", + "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp", +}; +struct spear_function spear3xx_gpio0_function = { + .name = "gpio0", + .groups = gpio0_grps, + .ngroups = ARRAY_SIZE(gpio0_grps), +}; + +/* uart0_ext_pins */ +static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 }; +static struct spear_muxreg uart0_ext_muxreg[] = { + { + .reg = -1, + .mask = PMX_UART0_MODEM_MASK, + .val = PMX_UART0_MODEM_MASK, + }, +}; + +static struct spear_modemux uart0_ext_modemux[] = { + { + .modes = ~0, + .muxregs = uart0_ext_muxreg, + .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg), + }, +}; + +struct spear_pingroup spear3xx_uart0_ext_pingroup = { + .name = "uart0_ext_grp", + .pins = uart0_ext_pins, + .npins = ARRAY_SIZE(uart0_ext_pins), + .modemuxs = uart0_ext_modemux, + .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux), +}; + +static const char *const uart0_ext_grps[] = { "uart0_ext_grp" }; +struct spear_function spear3xx_uart0_ext_function = { + .name = "uart0_ext", + .groups = uart0_ext_grps, + .ngroups = ARRAY_SIZE(uart0_ext_grps), +}; + +/* uart0_pins */ +static const unsigned uart0_pins[] = { 2, 3 }; +static struct spear_muxreg uart0_muxreg[] = { + { + .reg = -1, + .mask = PMX_UART0_MASK, + .val = PMX_UART0_MASK, + }, +}; + +static struct spear_modemux uart0_modemux[] = { + { + .modes = ~0, + .muxregs = uart0_muxreg, + .nmuxregs = ARRAY_SIZE(uart0_muxreg), + }, +}; + +struct spear_pingroup spear3xx_uart0_pingroup = { + .name = "uart0_grp", + .pins = uart0_pins, + .npins = ARRAY_SIZE(uart0_pins), + .modemuxs = uart0_modemux, + .nmodemuxs = ARRAY_SIZE(uart0_modemux), +}; + +static const char *const uart0_grps[] = { "uart0_grp" }; +struct spear_function spear3xx_uart0_function = { + .name = "uart0", + .groups = uart0_grps, + .ngroups = ARRAY_SIZE(uart0_grps), +}; + +/* timer_0_1_pins */ +static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 }; +static struct spear_muxreg timer_0_1_muxreg[] = { + { + .reg = -1, + .mask = PMX_TIMER_0_1_MASK, + .val = PMX_TIMER_0_1_MASK, + }, +}; + +static struct spear_modemux timer_0_1_modemux[] = { + { + .modes = ~0, + .muxregs = timer_0_1_muxreg, + .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg), + }, +}; + +struct spear_pingroup spear3xx_timer_0_1_pingroup = { + .name = "timer_0_1_grp", + .pins = timer_0_1_pins, + .npins = ARRAY_SIZE(timer_0_1_pins), + .modemuxs = timer_0_1_modemux, + .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux), +}; + +static const char *const timer_0_1_grps[] = { "timer_0_1_grp" }; +struct spear_function spear3xx_timer_0_1_function = { + .name = "timer_0_1", + .groups = timer_0_1_grps, + .ngroups = ARRAY_SIZE(timer_0_1_grps), +}; + +/* timer_2_3_pins */ +static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 }; +static struct spear_muxreg timer_2_3_muxreg[] = { + { + .reg = -1, + .mask = PMX_TIMER_2_3_MASK, + .val = PMX_TIMER_2_3_MASK, + }, +}; + +static struct spear_modemux timer_2_3_modemux[] = { + { + .modes = ~0, + .muxregs = timer_2_3_muxreg, + .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg), + }, +}; + +struct spear_pingroup spear3xx_timer_2_3_pingroup = { + .name = "timer_2_3_grp", + .pins = timer_2_3_pins, + .npins = ARRAY_SIZE(timer_2_3_pins), + .modemuxs = timer_2_3_modemux, + .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux), +}; + +static const char *const timer_2_3_grps[] = { "timer_2_3_grp" }; +struct spear_function spear3xx_timer_2_3_function = { + .name = "timer_2_3", + .groups = timer_2_3_grps, + .ngroups = ARRAY_SIZE(timer_2_3_grps), +}; + +struct spear_pinctrl_machdata spear3xx_machdata = { + .pins = spear3xx_pins, + .npins = ARRAY_SIZE(spear3xx_pins), +}; diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.h b/drivers/pinctrl/spear/pinctrl-spear3xx.h new file mode 100644 index 0000000..5d5fdd8 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear3xx.h @@ -0,0 +1,92 @@ +/* + * Header file for the ST Microelectronics SPEAr3xx pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PINMUX_SPEAR3XX_H__ +#define __PINMUX_SPEAR3XX_H__ + +#include "pinctrl-spear.h" + +/* pad mux declarations */ +#define PMX_FIRDA_MASK (1 << 14) +#define PMX_I2C_MASK (1 << 13) +#define PMX_SSP_CS_MASK (1 << 12) +#define PMX_SSP_MASK (1 << 11) +#define PMX_MII_MASK (1 << 10) +#define PMX_GPIO_PIN0_MASK (1 << 9) +#define PMX_GPIO_PIN1_MASK (1 << 8) +#define PMX_GPIO_PIN2_MASK (1 << 7) +#define PMX_GPIO_PIN3_MASK (1 << 6) +#define PMX_GPIO_PIN4_MASK (1 << 5) +#define PMX_GPIO_PIN5_MASK (1 << 4) +#define PMX_UART0_MODEM_MASK (1 << 3) +#define PMX_UART0_MASK (1 << 2) +#define PMX_TIMER_2_3_MASK (1 << 1) +#define PMX_TIMER_0_1_MASK (1 << 0) + +extern struct spear_pingroup spear3xx_firda_pingroup; +extern struct spear_pingroup spear3xx_gpio0_pin0_pingroup; +extern struct spear_pingroup spear3xx_gpio0_pin1_pingroup; +extern struct spear_pingroup spear3xx_gpio0_pin2_pingroup; +extern struct spear_pingroup spear3xx_gpio0_pin3_pingroup; +extern struct spear_pingroup spear3xx_gpio0_pin4_pingroup; +extern struct spear_pingroup spear3xx_gpio0_pin5_pingroup; +extern struct spear_pingroup spear3xx_i2c_pingroup; +extern struct spear_pingroup spear3xx_mii_pingroup; +extern struct spear_pingroup spear3xx_ssp_cs_pingroup; +extern struct spear_pingroup spear3xx_ssp_pingroup; +extern struct spear_pingroup spear3xx_timer_0_1_pingroup; +extern struct spear_pingroup spear3xx_timer_2_3_pingroup; +extern struct spear_pingroup spear3xx_uart0_ext_pingroup; +extern struct spear_pingroup spear3xx_uart0_pingroup; + +#define SPEAR3XX_COMMON_PINGROUPS \ + &spear3xx_firda_pingroup, \ + &spear3xx_gpio0_pin0_pingroup, \ + &spear3xx_gpio0_pin1_pingroup, \ + &spear3xx_gpio0_pin2_pingroup, \ + &spear3xx_gpio0_pin3_pingroup, \ + &spear3xx_gpio0_pin4_pingroup, \ + &spear3xx_gpio0_pin5_pingroup, \ + &spear3xx_i2c_pingroup, \ + &spear3xx_mii_pingroup, \ + &spear3xx_ssp_cs_pingroup, \ + &spear3xx_ssp_pingroup, \ + &spear3xx_timer_0_1_pingroup, \ + &spear3xx_timer_2_3_pingroup, \ + &spear3xx_uart0_ext_pingroup, \ + &spear3xx_uart0_pingroup + +extern struct spear_function spear3xx_firda_function; +extern struct spear_function spear3xx_gpio0_function; +extern struct spear_function spear3xx_i2c_function; +extern struct spear_function spear3xx_mii_function; +extern struct spear_function spear3xx_ssp_cs_function; +extern struct spear_function spear3xx_ssp_function; +extern struct spear_function spear3xx_timer_0_1_function; +extern struct spear_function spear3xx_timer_2_3_function; +extern struct spear_function spear3xx_uart0_ext_function; +extern struct spear_function spear3xx_uart0_function; + +#define SPEAR3XX_COMMON_FUNCTIONS \ + &spear3xx_firda_function, \ + &spear3xx_gpio0_function, \ + &spear3xx_i2c_function, \ + &spear3xx_mii_function, \ + &spear3xx_ssp_cs_function, \ + &spear3xx_ssp_function, \ + &spear3xx_timer_0_1_function, \ + &spear3xx_timer_2_3_function, \ + &spear3xx_uart0_ext_function, \ + &spear3xx_uart0_function + +extern struct spear_pinctrl_machdata spear3xx_machdata; + +#endif /* __PINMUX_SPEAR3XX_H__ */ diff --git a/drivers/s390/block/dasd_eckd.c b/drivers/s390/block/dasd_eckd.c index c21871a..bc2e8a7 100644 --- a/drivers/s390/block/dasd_eckd.c +++ b/drivers/s390/block/dasd_eckd.c @@ -2844,6 +2844,7 @@ static struct dasd_ccw_req *dasd_eckd_build_cp_tpm_track( sector_t recid, trkid; unsigned int offs; unsigned int count, count_to_trk_end; + int ret; basedev = block->base; if (rq_data_dir(req) == READ) { @@ -2884,8 +2885,8 @@ static struct dasd_ccw_req *dasd_eckd_build_cp_tpm_track( itcw = itcw_init(cqr->data, itcw_size, itcw_op, 0, ctidaw, 0); if (IS_ERR(itcw)) { - dasd_sfree_request(cqr, startdev); - return ERR_PTR(-EINVAL); + ret = -EINVAL; + goto out_error; } cqr->cpaddr = itcw_get_tcw(itcw); if (prepare_itcw(itcw, first_trk, last_trk, @@ -2897,8 +2898,8 @@ static struct dasd_ccw_req *dasd_eckd_build_cp_tpm_track( /* Clock not in sync and XRC is enabled. * Try again later. */ - dasd_sfree_request(cqr, startdev); - return ERR_PTR(-EAGAIN); + ret = -EAGAIN; + goto out_error; } len_to_track_end = 0; /* @@ -2937,8 +2938,10 @@ static struct dasd_ccw_req *dasd_eckd_build_cp_tpm_track( tidaw_flags = 0; last_tidaw = itcw_add_tidaw(itcw, tidaw_flags, dst, part_len); - if (IS_ERR(last_tidaw)) - return ERR_PTR(-EINVAL); + if (IS_ERR(last_tidaw)) { + ret = -EINVAL; + goto out_error; + } dst += part_len; } } @@ -2947,8 +2950,10 @@ static struct dasd_ccw_req *dasd_eckd_build_cp_tpm_track( dst = page_address(bv->bv_page) + bv->bv_offset; last_tidaw = itcw_add_tidaw(itcw, 0x00, dst, bv->bv_len); - if (IS_ERR(last_tidaw)) - return ERR_PTR(-EINVAL); + if (IS_ERR(last_tidaw)) { + ret = -EINVAL; + goto out_error; + } } } last_tidaw->flags |= TIDAW_FLAGS_LAST; @@ -2968,6 +2973,9 @@ static struct dasd_ccw_req *dasd_eckd_build_cp_tpm_track( cqr->buildclk = get_clock(); cqr->status = DASD_CQR_FILLED; return cqr; +out_error: + dasd_sfree_request(cqr, startdev); + return ERR_PTR(ret); } static struct dasd_ccw_req *dasd_eckd_build_cp(struct dasd_device *startdev, diff --git a/drivers/s390/char/vmur.c b/drivers/s390/char/vmur.c index 85f4a9a..73bef0b 100644 --- a/drivers/s390/char/vmur.c +++ b/drivers/s390/char/vmur.c @@ -903,7 +903,7 @@ static int ur_set_online(struct ccw_device *cdev) goto fail_urdev_put; } - cdev_init(urd->char_device, &ur_fops); + urd->char_device->ops = &ur_fops; urd->char_device->dev = MKDEV(major, minor); urd->char_device->owner = ur_fops.owner; diff --git a/drivers/tty/amiserial.c b/drivers/tty/amiserial.c index 24145c3..6cc4358 100644 --- a/drivers/tty/amiserial.c +++ b/drivers/tty/amiserial.c @@ -1073,8 +1073,10 @@ static int set_serial_info(struct tty_struct *tty, struct serial_state *state, (new_serial.close_delay != port->close_delay) || (new_serial.xmit_fifo_size != state->xmit_fifo_size) || ((new_serial.flags & ~ASYNC_USR_MASK) != - (port->flags & ~ASYNC_USR_MASK))) + (port->flags & ~ASYNC_USR_MASK))) { + tty_unlock(); return -EPERM; + } port->flags = ((port->flags & ~ASYNC_USR_MASK) | (new_serial.flags & ASYNC_USR_MASK)); state->custom_divisor = new_serial.custom_divisor; diff --git a/drivers/tty/serial/clps711x.c b/drivers/tty/serial/clps711x.c index e6c3dbd..836fe273 100644 --- a/drivers/tty/serial/clps711x.c +++ b/drivers/tty/serial/clps711x.c @@ -154,10 +154,9 @@ static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id) port->x_char = 0; return IRQ_HANDLED; } - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { - clps711xuart_stop_tx(port); - return IRQ_HANDLED; - } + + if (uart_circ_empty(xmit) || uart_tx_stopped(port)) + goto disable_tx_irq; count = port->fifosize >> 1; do { @@ -171,8 +170,11 @@ static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) uart_write_wakeup(port); - if (uart_circ_empty(xmit)) - clps711xuart_stop_tx(port); + if (uart_circ_empty(xmit)) { + disable_tx_irq: + disable_irq_nosync(TX_IRQ(port)); + tx_enabled(port) = 0; + } return IRQ_HANDLED; } diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c index bbbec4a..c2816f4 100644 --- a/drivers/tty/serial/pch_uart.c +++ b/drivers/tty/serial/pch_uart.c @@ -1447,9 +1447,11 @@ static int pch_uart_verify_port(struct uart_port *port, __func__); return -EOPNOTSUPP; #endif - priv->use_dma = 1; priv->use_dma_flag = 1; dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); + if (!priv->use_dma) + pch_request_dma(port); + priv->use_dma = 1; } return 0; diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index a2aa9d6..ec6c97d 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -1667,7 +1667,6 @@ void usb_disconnect(struct usb_device **pdev) { struct usb_device *udev = *pdev; int i; - struct usb_hcd *hcd = bus_to_hcd(udev->bus); /* mark the device as inactive, so any further urb submissions for * this device (and any of its children) will fail immediately. @@ -1690,9 +1689,7 @@ void usb_disconnect(struct usb_device **pdev) * so that the hardware is now fully quiesced. */ dev_dbg (&udev->dev, "unregistering device\n"); - mutex_lock(hcd->bandwidth_mutex); usb_disable_device(udev, 0); - mutex_unlock(hcd->bandwidth_mutex); usb_hcd_synchronize_unlinks(udev); usb_remove_ep_devs(&udev->ep0); diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c index aed3e07..ca717da 100644 --- a/drivers/usb/core/message.c +++ b/drivers/usb/core/message.c @@ -1136,8 +1136,6 @@ void usb_disable_interface(struct usb_device *dev, struct usb_interface *intf, * Deallocates hcd/hardware state for the endpoints (nuking all or most * pending urbs) and usbcore state for the interfaces, so that usbcore * must usb_set_configuration() before any interfaces could be used. - * - * Must be called with hcd->bandwidth_mutex held. */ void usb_disable_device(struct usb_device *dev, int skip_ep0) { @@ -1190,7 +1188,9 @@ void usb_disable_device(struct usb_device *dev, int skip_ep0) usb_disable_endpoint(dev, i + USB_DIR_IN, false); } /* Remove endpoints from the host controller internal state */ + mutex_lock(hcd->bandwidth_mutex); usb_hcd_alloc_bandwidth(dev, NULL, NULL, NULL); + mutex_unlock(hcd->bandwidth_mutex); /* Second pass: remove endpoint pointers */ } for (i = skip_ep0; i < 16; ++i) { @@ -1750,7 +1750,6 @@ free_interfaces: /* if it's already configured, clear out old state first. * getting rid of old interfaces means unbinding their drivers. */ - mutex_lock(hcd->bandwidth_mutex); if (dev->state != USB_STATE_ADDRESS) usb_disable_device(dev, 1); /* Skip ep0 */ @@ -1763,6 +1762,7 @@ free_interfaces: * host controller will not allow submissions to dropped endpoints. If * this call fails, the device state is unchanged. */ + mutex_lock(hcd->bandwidth_mutex); ret = usb_hcd_alloc_bandwidth(dev, cp, NULL, NULL); if (ret < 0) { mutex_unlock(hcd->bandwidth_mutex); diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 7bd815a..99b58d84 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -206,11 +206,11 @@ static void dwc3_free_event_buffers(struct dwc3 *dwc) for (i = 0; i < dwc->num_event_buffers; i++) { evt = dwc->ev_buffs[i]; - if (evt) { + if (evt) dwc3_free_one_event_buffer(dwc, evt); - dwc->ev_buffs[i] = NULL; - } } + + kfree(dwc->ev_buffs); } /** diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 25910e2..3584a16 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -353,6 +353,9 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc, dwc->test_mode_nr = wIndex >> 8; dwc->test_mode = true; + break; + default: + return -EINVAL; } break; @@ -559,15 +562,20 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc, length = trb->size & DWC3_TRB_SIZE_MASK; if (dwc->ep0_bounced) { + unsigned transfer_size = ur->length; + unsigned maxp = ep0->endpoint.maxpacket; + + transfer_size += (maxp - (transfer_size % maxp)); transferred = min_t(u32, ur->length, - ep0->endpoint.maxpacket - length); + transfer_size - length); memcpy(ur->buf, dwc->ep0_bounce, transferred); dwc->ep0_bounced = false; } else { transferred = ur->length - length; - ur->actual += transferred; } + ur->actual += transferred; + if ((epnum & 1) && ur->actual < ur->length) { /* for some reason we did not get everything out */ diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c index 0c935d7..9d7bcd9 100644 --- a/drivers/usb/gadget/at91_udc.c +++ b/drivers/usb/gadget/at91_udc.c @@ -1863,8 +1863,8 @@ static int __devinit at91udc_probe(struct platform_device *pdev) mod_timer(&udc->vbus_timer, jiffies + VBUS_POLL_TIMEOUT); } else { - if (request_irq(udc->board.vbus_pin, at91_vbus_irq, - 0, driver_name, udc)) { + if (request_irq(gpio_to_irq(udc->board.vbus_pin), + at91_vbus_irq, 0, driver_name, udc)) { DBG("request vbus irq %d failed\n", udc->board.vbus_pin); retval = -EBUSY; @@ -1886,7 +1886,7 @@ static int __devinit at91udc_probe(struct platform_device *pdev) return 0; fail4: if (gpio_is_valid(udc->board.vbus_pin) && !udc->board.vbus_polled) - free_irq(udc->board.vbus_pin, udc); + free_irq(gpio_to_irq(udc->board.vbus_pin), udc); fail3: if (gpio_is_valid(udc->board.vbus_pin)) gpio_free(udc->board.vbus_pin); @@ -1924,7 +1924,7 @@ static int __exit at91udc_remove(struct platform_device *pdev) device_init_wakeup(&pdev->dev, 0); remove_debug_file(udc); if (gpio_is_valid(udc->board.vbus_pin)) { - free_irq(udc->board.vbus_pin, udc); + free_irq(gpio_to_irq(udc->board.vbus_pin), udc); gpio_free(udc->board.vbus_pin); } free_irq(udc->udp_irq, udc); diff --git a/drivers/usb/gadget/f_fs.c b/drivers/usb/gadget/f_fs.c index 1cbba70..f52cb1a 100644 --- a/drivers/usb/gadget/f_fs.c +++ b/drivers/usb/gadget/f_fs.c @@ -712,7 +712,7 @@ static long ffs_ep0_ioctl(struct file *file, unsigned code, unsigned long value) if (code == FUNCTIONFS_INTERFACE_REVMAP) { struct ffs_function *func = ffs->func; ret = func ? ffs_func_revmap_intf(func, value) : -ENODEV; - } else if (gadget->ops->ioctl) { + } else if (gadget && gadget->ops->ioctl) { ret = gadget->ops->ioctl(gadget, code, value); } else { ret = -ENOTTY; @@ -1382,6 +1382,7 @@ static void functionfs_unbind(struct ffs_data *ffs) ffs->ep0req = NULL; ffs->gadget = NULL; ffs_data_put(ffs); + clear_bit(FFS_FL_BOUND, &ffs->flags); } } diff --git a/drivers/usb/gadget/f_rndis.c b/drivers/usb/gadget/f_rndis.c index 7b1cf18..5234365 100644 --- a/drivers/usb/gadget/f_rndis.c +++ b/drivers/usb/gadget/f_rndis.c @@ -500,6 +500,7 @@ rndis_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) if (buf) { memcpy(req->buf, buf, n); req->complete = rndis_response_complete; + req->context = rndis; rndis_free_response(rndis->config, buf); value = n; } diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c index 5f94e79..55abfb6 100644 --- a/drivers/usb/gadget/fsl_udc_core.c +++ b/drivers/usb/gadget/fsl_udc_core.c @@ -730,7 +730,7 @@ static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req) : (1 << (ep_index(ep))); /* check if the pipe is empty */ - if (!(list_empty(&ep->queue))) { + if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) { /* Add td to the end */ struct fsl_req *lastreq; lastreq = list_entry(ep->queue.prev, struct fsl_req, queue); @@ -918,10 +918,6 @@ fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) return -ENOMEM; } - /* Update ep0 state */ - if ((ep_index(ep) == 0)) - udc->ep0_state = DATA_STATE_XMIT; - /* irq handler advances the queue */ if (req != NULL) list_add_tail(&req->queue, &ep->queue); @@ -1279,7 +1275,8 @@ static int ep0_prime_status(struct fsl_udc *udc, int direction) udc->ep0_dir = USB_DIR_OUT; ep = &udc->eps[0]; - udc->ep0_state = WAIT_FOR_OUT_STATUS; + if (udc->ep0_state != DATA_STATE_XMIT) + udc->ep0_state = WAIT_FOR_OUT_STATUS; req->ep = ep; req->req.length = 0; @@ -1384,6 +1381,9 @@ static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value, list_add_tail(&req->queue, &ep->queue); udc->ep0_state = DATA_STATE_XMIT; + if (ep0_prime_status(udc, EP_DIR_OUT)) + ep0stall(udc); + return; stall: ep0stall(udc); @@ -1492,6 +1492,14 @@ static void setup_received_irq(struct fsl_udc *udc, spin_lock(&udc->lock); udc->ep0_state = (setup->bRequestType & USB_DIR_IN) ? DATA_STATE_XMIT : DATA_STATE_RECV; + /* + * If the data stage is IN, send status prime immediately. + * See 2.0 Spec chapter 8.5.3.3 for detail. + */ + if (udc->ep0_state == DATA_STATE_XMIT) + if (ep0_prime_status(udc, EP_DIR_OUT)) + ep0stall(udc); + } else { /* No data phase, IN status from gadget */ udc->ep0_dir = USB_DIR_IN; @@ -1520,9 +1528,8 @@ static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0, switch (udc->ep0_state) { case DATA_STATE_XMIT: - /* receive status phase */ - if (ep0_prime_status(udc, EP_DIR_OUT)) - ep0stall(udc); + /* already primed at setup_received_irq */ + udc->ep0_state = WAIT_FOR_OUT_STATUS; break; case DATA_STATE_RECV: /* send status phase */ diff --git a/drivers/usb/gadget/g_ffs.c b/drivers/usb/gadget/g_ffs.c index 331cd67..a85eaf4 100644 --- a/drivers/usb/gadget/g_ffs.c +++ b/drivers/usb/gadget/g_ffs.c @@ -161,7 +161,7 @@ static struct usb_composite_driver gfs_driver = { static struct ffs_data *gfs_ffs_data; static unsigned long gfs_registered; -static int gfs_init(void) +static int __init gfs_init(void) { ENTER(); @@ -169,7 +169,7 @@ static int gfs_init(void) } module_init(gfs_init); -static void gfs_exit(void) +static void __exit gfs_exit(void) { ENTER(); diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c index 69295ba..105b206 100644 --- a/drivers/usb/gadget/s3c-hsotg.c +++ b/drivers/usb/gadget/s3c-hsotg.c @@ -340,7 +340,7 @@ static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg) /* currently we allocate TX FIFOs for all possible endpoints, * and assume that they are all the same size. */ - for (ep = 0; ep <= 15; ep++) { + for (ep = 1; ep <= 15; ep++) { val = addr; val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT; addr += size; @@ -741,7 +741,7 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg, /* write size / packets */ writel(epsize, hsotg->regs + epsize_reg); - if (using_dma(hsotg)) { + if (using_dma(hsotg) && !continuing) { unsigned int dma_reg; /* write DMA address to control register, buffer already @@ -1696,10 +1696,12 @@ static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg, reg |= mpsval; writel(reg, regs + S3C_DIEPCTL(ep)); - reg = readl(regs + S3C_DOEPCTL(ep)); - reg &= ~S3C_DxEPCTL_MPS_MASK; - reg |= mpsval; - writel(reg, regs + S3C_DOEPCTL(ep)); + if (ep) { + reg = readl(regs + S3C_DOEPCTL(ep)); + reg &= ~S3C_DxEPCTL_MPS_MASK; + reg |= mpsval; + writel(reg, regs + S3C_DOEPCTL(ep)); + } return; @@ -1919,7 +1921,8 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx, ints & S3C_DIEPMSK_TxFIFOEmpty) { dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", __func__, idx); - s3c_hsotg_trytx(hsotg, hs_ep); + if (!using_dma(hsotg)) + s3c_hsotg_trytx(hsotg, hs_ep); } } } diff --git a/drivers/usb/gadget/udc-core.c b/drivers/usb/gadget/udc-core.c index 56da49f..2fa9865 100644 --- a/drivers/usb/gadget/udc-core.c +++ b/drivers/usb/gadget/udc-core.c @@ -264,8 +264,8 @@ static void usb_gadget_remove_driver(struct usb_udc *udc) if (udc_is_newstyle(udc)) { udc->driver->disconnect(udc->gadget); udc->driver->unbind(udc->gadget); - usb_gadget_udc_stop(udc->gadget, udc->driver); usb_gadget_disconnect(udc->gadget); + usb_gadget_udc_stop(udc->gadget, udc->driver); } else { usb_gadget_stop(udc->gadget, udc->driver); } @@ -411,8 +411,12 @@ static ssize_t usb_udc_softconn_store(struct device *dev, struct usb_udc *udc = container_of(dev, struct usb_udc, dev); if (sysfs_streq(buf, "connect")) { + if (udc_is_newstyle(udc)) + usb_gadget_udc_start(udc->gadget, udc->driver); usb_gadget_connect(udc->gadget); } else if (sysfs_streq(buf, "disconnect")) { + if (udc_is_newstyle(udc)) + usb_gadget_udc_stop(udc->gadget, udc->driver); usb_gadget_disconnect(udc->gadget); } else { dev_err(dev, "unsupported command '%s'\n", buf); diff --git a/drivers/usb/gadget/uvc_queue.c b/drivers/usb/gadget/uvc_queue.c index d776adb..0cdf89d 100644 --- a/drivers/usb/gadget/uvc_queue.c +++ b/drivers/usb/gadget/uvc_queue.c @@ -543,11 +543,11 @@ done: return ret; } +/* called with queue->irqlock held.. */ static struct uvc_buffer * uvc_queue_next_buffer(struct uvc_video_queue *queue, struct uvc_buffer *buf) { struct uvc_buffer *nextbuf; - unsigned long flags; if ((queue->flags & UVC_QUEUE_DROP_INCOMPLETE) && buf->buf.length != buf->buf.bytesused) { @@ -556,14 +556,12 @@ uvc_queue_next_buffer(struct uvc_video_queue *queue, struct uvc_buffer *buf) return buf; } - spin_lock_irqsave(&queue->irqlock, flags); list_del(&buf->queue); if (!list_empty(&queue->irqqueue)) nextbuf = list_first_entry(&queue->irqqueue, struct uvc_buffer, queue); else nextbuf = NULL; - spin_unlock_irqrestore(&queue->irqlock, flags); buf->buf.sequence = queue->sequence++; do_gettimeofday(&buf->buf.timestamp); diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 3e73451..d0a84bd 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -218,6 +218,9 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci, u32 portsc; struct usb_hcd *hcd = ehci_to_hcd(ehci); void __iomem *non_ehci = hcd->regs; + struct fsl_usb2_platform_data *pdata; + + pdata = hcd->self.controller->platform_data; portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]); portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); @@ -234,7 +237,9 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci, /* fall through */ case FSL_USB2_PHY_UTMI: /* enable UTMI PHY */ - setbits32(non_ehci + FSL_SOC_USB_CTRL, CTRL_UTMI_PHY_EN); + if (pdata->have_sysif_regs) + setbits32(non_ehci + FSL_SOC_USB_CTRL, + CTRL_UTMI_PHY_EN); portsc |= PORT_PTS_UTMI; break; case FSL_USB2_PHY_NONE: diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 806cc95..4a3bc5b 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -858,8 +858,13 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd) goto dead; } + /* + * We don't use STS_FLR, but some controllers don't like it to + * remain on, so mask it out along with the other status bits. + */ + masked_status = status & (INTR_MASK | STS_FLR); + /* Shared IRQ? */ - masked_status = status & INTR_MASK; if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) { spin_unlock(&ehci->lock); return IRQ_NONE; @@ -910,7 +915,7 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd) pcd_status = status; /* resume root hub? */ - if (!(cmd & CMD_RUN)) + if (ehci->rh_state == EHCI_RH_SUSPENDED) usb_hcd_resume_root_hub(hcd); /* get per-port change detect bits */ diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index bba9850..5c78f9e 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -42,6 +42,7 @@ #include <plat/usb.h> #include <linux/regulator/consumer.h> #include <linux/pm_runtime.h> +#include <linux/gpio.h> /* EHCI Register Set */ #define EHCI_INSNREG04 (0xA0) @@ -191,6 +192,19 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev) } } + if (pdata->phy_reset) { + if (gpio_is_valid(pdata->reset_gpio_port[0])) + gpio_request_one(pdata->reset_gpio_port[0], + GPIOF_OUT_INIT_LOW, "USB1 PHY reset"); + + if (gpio_is_valid(pdata->reset_gpio_port[1])) + gpio_request_one(pdata->reset_gpio_port[1], + GPIOF_OUT_INIT_LOW, "USB2 PHY reset"); + + /* Hold the PHY in RESET for enough time till DIR is high */ + udelay(10); + } + pm_runtime_enable(dev); pm_runtime_get_sync(dev); @@ -237,6 +251,19 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev) /* root ports should always stay powered */ ehci_port_power(omap_ehci, 1); + if (pdata->phy_reset) { + /* Hold the PHY in RESET for enough time till + * PHY is settled and ready + */ + udelay(10); + + if (gpio_is_valid(pdata->reset_gpio_port[0])) + gpio_set_value(pdata->reset_gpio_port[0], 1); + + if (gpio_is_valid(pdata->reset_gpio_port[1])) + gpio_set_value(pdata->reset_gpio_port[1], 1); + } + return 0; err_add_hcd: @@ -259,8 +286,9 @@ err_io: */ static int ehci_hcd_omap_remove(struct platform_device *pdev) { - struct device *dev = &pdev->dev; - struct usb_hcd *hcd = dev_get_drvdata(dev); + struct device *dev = &pdev->dev; + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct ehci_hcd_omap_platform_data *pdata = dev->platform_data; usb_remove_hcd(hcd); disable_put_regulator(dev->platform_data); @@ -269,6 +297,13 @@ static int ehci_hcd_omap_remove(struct platform_device *pdev) pm_runtime_put_sync(dev); pm_runtime_disable(dev); + if (pdata->phy_reset) { + if (gpio_is_valid(pdata->reset_gpio_port[0])) + gpio_free(pdata->reset_gpio_port[0]); + + if (gpio_is_valid(pdata->reset_gpio_port[1])) + gpio_free(pdata->reset_gpio_port[1]); + } return 0; } diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 9692bef..826c2fd 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -732,7 +732,6 @@ static int tegra_ehci_probe(struct platform_device *pdev) err = -ENODEV; goto fail; } - set_irq_flags(irq, IRQF_VALID); #ifdef CONFIG_USB_OTG_UTILS if (pdata->operating_mode == TEGRA_USB_OTG) { diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 09f597a..13ebeca 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -94,7 +94,7 @@ static void at91_stop_hc(struct platform_device *pdev) /*-------------------------------------------------------------------------*/ -static void usb_hcd_at91_remove (struct usb_hcd *, struct platform_device *); +static void __devexit usb_hcd_at91_remove (struct usb_hcd *, struct platform_device *); /* configure so an HC device and id are always provided */ /* always called with process context; sleeping is OK */ @@ -108,7 +108,7 @@ static void usb_hcd_at91_remove (struct usb_hcd *, struct platform_device *); * then invokes the start() method for the HCD associated with it * through the hotplug entry's driver_data. */ -static int usb_hcd_at91_probe(const struct hc_driver *driver, +static int __devinit usb_hcd_at91_probe(const struct hc_driver *driver, struct platform_device *pdev) { int retval; @@ -203,7 +203,7 @@ static int usb_hcd_at91_probe(const struct hc_driver *driver, * context, "rmmod" or something similar. * */ -static void usb_hcd_at91_remove(struct usb_hcd *hcd, +static void __devexit usb_hcd_at91_remove(struct usb_hcd *hcd, struct platform_device *pdev) { usb_remove_hcd(hcd); @@ -545,7 +545,7 @@ static int __devinit ohci_at91_of_init(struct platform_device *pdev) /*-------------------------------------------------------------------------*/ -static int ohci_hcd_at91_drv_probe(struct platform_device *pdev) +static int __devinit ohci_hcd_at91_drv_probe(struct platform_device *pdev) { struct at91_usbh_data *pdata; int i; @@ -620,7 +620,7 @@ static int ohci_hcd_at91_drv_probe(struct platform_device *pdev) return usb_hcd_at91_probe(&ohci_at91_hc_driver, pdev); } -static int ohci_hcd_at91_drv_remove(struct platform_device *pdev) +static int __devexit ohci_hcd_at91_drv_remove(struct platform_device *pdev) { struct at91_usbh_data *pdata = pdev->dev.platform_data; int i; @@ -696,7 +696,7 @@ MODULE_ALIAS("platform:at91_ohci"); static struct platform_driver ohci_hcd_at91_driver = { .probe = ohci_hcd_at91_drv_probe, - .remove = ohci_hcd_at91_drv_remove, + .remove = __devexit_p(ohci_hcd_at91_drv_remove), .shutdown = usb_hcd_platform_shutdown, .suspend = ohci_hcd_at91_drv_suspend, .resume = ohci_hcd_at91_drv_resume, diff --git a/drivers/usb/misc/usbtest.c b/drivers/usb/misc/usbtest.c index 959145b..9dcb68f 100644 --- a/drivers/usb/misc/usbtest.c +++ b/drivers/usb/misc/usbtest.c @@ -423,7 +423,7 @@ alloc_sglist(int nents, int max, int vary) unsigned i; unsigned size = max; - sg = kmalloc(nents * sizeof *sg, GFP_KERNEL); + sg = kmalloc_array(nents, sizeof *sg, GFP_KERNEL); if (!sg) return NULL; sg_init_table(sg, nents); @@ -904,6 +904,9 @@ test_ctrl_queue(struct usbtest_dev *dev, struct usbtest_param *param) struct ctrl_ctx context; int i; + if (param->sglen == 0 || param->iterations > UINT_MAX / param->sglen) + return -EOPNOTSUPP; + spin_lock_init(&context.lock); context.dev = dev; init_completion(&context.complete); @@ -1981,8 +1984,6 @@ usbtest_ioctl(struct usb_interface *intf, unsigned int code, void *buf) /* queued control messaging */ case 10: - if (param->sglen == 0) - break; retval = 0; dev_info(&intf->dev, "TEST 10: queue %d control calls, %d times\n", @@ -2276,6 +2277,8 @@ usbtest_probe(struct usb_interface *intf, const struct usb_device_id *id) if (status < 0) { WARNING(dev, "couldn't get endpoints, %d\n", status); + kfree(dev->buf); + kfree(dev); return status; } /* may find bulk or ISO pipes */ diff --git a/drivers/usb/misc/yurex.c b/drivers/usb/misc/yurex.c index 897edda..7020146 100644 --- a/drivers/usb/misc/yurex.c +++ b/drivers/usb/misc/yurex.c @@ -99,9 +99,7 @@ static void yurex_delete(struct kref *kref) usb_put_dev(dev->udev); if (dev->cntl_urb) { usb_kill_urb(dev->cntl_urb); - if (dev->cntl_req) - usb_free_coherent(dev->udev, YUREX_BUF_SIZE, - dev->cntl_req, dev->cntl_urb->setup_dma); + kfree(dev->cntl_req); if (dev->cntl_buffer) usb_free_coherent(dev->udev, YUREX_BUF_SIZE, dev->cntl_buffer, dev->cntl_urb->transfer_dma); @@ -234,9 +232,7 @@ static int yurex_probe(struct usb_interface *interface, const struct usb_device_ } /* allocate buffer for control req */ - dev->cntl_req = usb_alloc_coherent(dev->udev, YUREX_BUF_SIZE, - GFP_KERNEL, - &dev->cntl_urb->setup_dma); + dev->cntl_req = kmalloc(YUREX_BUF_SIZE, GFP_KERNEL); if (!dev->cntl_req) { err("Could not allocate cntl_req"); goto error; @@ -286,7 +282,7 @@ static int yurex_probe(struct usb_interface *interface, const struct usb_device_ usb_rcvintpipe(dev->udev, dev->int_in_endpointAddr), dev->int_buffer, YUREX_BUF_SIZE, yurex_interrupt, dev, 1); - dev->cntl_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; + dev->urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; if (usb_submit_urb(dev->urb, GFP_KERNEL)) { retval = -EIO; err("Could not submitting URB"); diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index 0f8b829..66aaccf 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -137,6 +137,9 @@ static int musb_ulpi_read(struct usb_phy *phy, u32 offset) int i = 0; u8 r; u8 power; + int ret; + + pm_runtime_get_sync(phy->io_dev); /* Make sure the transceiver is not in low power mode */ power = musb_readb(addr, MUSB_POWER); @@ -154,15 +157,22 @@ static int musb_ulpi_read(struct usb_phy *phy, u32 offset) while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) & MUSB_ULPI_REG_CMPLT)) { i++; - if (i == 10000) - return -ETIMEDOUT; + if (i == 10000) { + ret = -ETIMEDOUT; + goto out; + } } r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); r &= ~MUSB_ULPI_REG_CMPLT; musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); - return musb_readb(addr, MUSB_ULPI_REG_DATA); + ret = musb_readb(addr, MUSB_ULPI_REG_DATA); + +out: + pm_runtime_put(phy->io_dev); + + return ret; } static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) @@ -171,6 +181,9 @@ static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) int i = 0; u8 r = 0; u8 power; + int ret = 0; + + pm_runtime_get_sync(phy->io_dev); /* Make sure the transceiver is not in low power mode */ power = musb_readb(addr, MUSB_POWER); @@ -184,15 +197,20 @@ static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) & MUSB_ULPI_REG_CMPLT)) { i++; - if (i == 10000) - return -ETIMEDOUT; + if (i == 10000) { + ret = -ETIMEDOUT; + goto out; + } } r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); r &= ~MUSB_ULPI_REG_CMPLT; musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); - return 0; +out: + pm_runtime_put(phy->io_dev); + + return ret; } #else #define musb_ulpi_read NULL @@ -1904,14 +1922,17 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) if (!musb->isr) { status = -ENODEV; - goto fail3; + goto fail2; } if (!musb->xceiv->io_ops) { + musb->xceiv->io_dev = musb->controller; musb->xceiv->io_priv = musb->mregs; musb->xceiv->io_ops = &musb_ulpi_access; } + pm_runtime_get_sync(musb->controller); + #ifndef CONFIG_MUSB_PIO_ONLY if (use_dma && dev->dma_mask) { struct dma_controller *c; @@ -2023,6 +2044,8 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) goto fail5; #endif + pm_runtime_put(musb->controller); + dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", ({char *s; switch (musb->board_mode) { @@ -2047,6 +2070,9 @@ fail4: musb_gadget_cleanup(musb); fail3: + pm_runtime_put_sync(musb->controller); + +fail2: if (musb->irq_wake) device_init_wakeup(dev, 0); musb_platform_exit(musb); diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c index 79cb0af..ef8d744 100644 --- a/drivers/usb/musb/musb_host.c +++ b/drivers/usb/musb/musb_host.c @@ -2098,7 +2098,7 @@ static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) } /* turn off DMA requests, discard state, stop polling ... */ - if (is_in) { + if (ep->epnum && is_in) { /* giveback saves bulk toggle */ csr = musb_h_flush_rxfifo(ep, 0); diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c index 2ae0bb3..c7785e8 100644 --- a/drivers/usb/musb/omap2430.c +++ b/drivers/usb/musb/omap2430.c @@ -282,7 +282,8 @@ static void musb_otg_notifier_work(struct work_struct *data_notifier_work) static int omap2430_musb_init(struct musb *musb) { - u32 l, status = 0; + u32 l; + int status = 0; struct device *dev = musb->controller; struct musb_hdrc_platform_data *plat = dev->platform_data; struct omap_musb_board_data *data = plat->board_data; @@ -301,7 +302,7 @@ static int omap2430_musb_init(struct musb *musb) status = pm_runtime_get_sync(dev); if (status < 0) { - dev_err(dev, "pm_runtime_get_sync FAILED"); + dev_err(dev, "pm_runtime_get_sync FAILED %d\n", status); goto err1; } @@ -333,6 +334,7 @@ static int omap2430_musb_init(struct musb *musb) setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); + pm_runtime_put_noidle(musb->controller); return 0; err1: @@ -452,14 +454,14 @@ static int __devinit omap2430_probe(struct platform_device *pdev) goto err2; } + pm_runtime_enable(&pdev->dev); + ret = platform_device_add(musb); if (ret) { dev_err(&pdev->dev, "failed to register musb device\n"); goto err2; } - pm_runtime_enable(&pdev->dev); - return 0; err2: @@ -478,7 +480,6 @@ static int __devexit omap2430_remove(struct platform_device *pdev) platform_device_del(glue->musb); platform_device_put(glue->musb); - pm_runtime_put(&pdev->dev); kfree(glue); return 0; @@ -491,11 +492,13 @@ static int omap2430_runtime_suspend(struct device *dev) struct omap2430_glue *glue = dev_get_drvdata(dev); struct musb *musb = glue_to_musb(glue); - musb->context.otg_interfsel = musb_readl(musb->mregs, - OTG_INTERFSEL); + if (musb) { + musb->context.otg_interfsel = musb_readl(musb->mregs, + OTG_INTERFSEL); - omap2430_low_level_exit(musb); - usb_phy_set_suspend(musb->xceiv, 1); + omap2430_low_level_exit(musb); + usb_phy_set_suspend(musb->xceiv, 1); + } return 0; } @@ -505,11 +508,13 @@ static int omap2430_runtime_resume(struct device *dev) struct omap2430_glue *glue = dev_get_drvdata(dev); struct musb *musb = glue_to_musb(glue); - omap2430_low_level_init(musb); - musb_writel(musb->mregs, OTG_INTERFSEL, - musb->context.otg_interfsel); + if (musb) { + omap2430_low_level_init(musb); + musb_writel(musb->mregs, OTG_INTERFSEL, + musb->context.otg_interfsel); - usb_phy_set_suspend(musb->xceiv, 0); + usb_phy_set_suspend(musb->xceiv, 0); + } return 0; } diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c index 0310e2d..ec30f95 100644 --- a/drivers/usb/serial/cp210x.c +++ b/drivers/usb/serial/cp210x.c @@ -287,7 +287,8 @@ static int cp210x_get_config(struct usb_serial_port *port, u8 request, /* Issue the request, attempting to read 'size' bytes */ result = usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0), request, REQTYPE_DEVICE_TO_HOST, 0x0000, - port_priv->bInterfaceNumber, buf, size, 300); + port_priv->bInterfaceNumber, buf, size, + USB_CTRL_GET_TIMEOUT); /* Convert data into an array of integers */ for (i = 0; i < length; i++) @@ -340,12 +341,14 @@ static int cp210x_set_config(struct usb_serial_port *port, u8 request, result = usb_control_msg(serial->dev, usb_sndctrlpipe(serial->dev, 0), request, REQTYPE_HOST_TO_DEVICE, 0x0000, - port_priv->bInterfaceNumber, buf, size, 300); + port_priv->bInterfaceNumber, buf, size, + USB_CTRL_SET_TIMEOUT); } else { result = usb_control_msg(serial->dev, usb_sndctrlpipe(serial->dev, 0), request, REQTYPE_HOST_TO_DEVICE, data[0], - port_priv->bInterfaceNumber, NULL, 0, 300); + port_priv->bInterfaceNumber, NULL, 0, + USB_CTRL_SET_TIMEOUT); } kfree(buf); diff --git a/drivers/usb/serial/sierra.c b/drivers/usb/serial/sierra.c index fdd5aa2..8c8bf80 100644 --- a/drivers/usb/serial/sierra.c +++ b/drivers/usb/serial/sierra.c @@ -221,7 +221,7 @@ static const struct sierra_iface_info typeB_interface_list = { }; /* 'blacklist' of interfaces not served by this driver */ -static const u8 direct_ip_non_serial_ifaces[] = { 7, 8, 9, 10, 11 }; +static const u8 direct_ip_non_serial_ifaces[] = { 7, 8, 9, 10, 11, 19, 20 }; static const struct sierra_iface_info direct_ip_interface_blacklist = { .infolen = ARRAY_SIZE(direct_ip_non_serial_ifaces), .ifaceinfo = direct_ip_non_serial_ifaces, @@ -289,7 +289,6 @@ static const struct usb_device_id id_table[] = { { USB_DEVICE(0x1199, 0x6856) }, /* Sierra Wireless AirCard 881 U */ { USB_DEVICE(0x1199, 0x6859) }, /* Sierra Wireless AirCard 885 E */ { USB_DEVICE(0x1199, 0x685A) }, /* Sierra Wireless AirCard 885 E */ - { USB_DEVICE(0x1199, 0x68A2) }, /* Sierra Wireless MC7710 */ /* Sierra Wireless C885 */ { USB_DEVICE_AND_INTERFACE_INFO(0x1199, 0x6880, 0xFF, 0xFF, 0xFF)}, /* Sierra Wireless C888, Air Card 501, USB 303, USB 304 */ @@ -299,6 +298,9 @@ static const struct usb_device_id id_table[] = { /* Sierra Wireless HSPA Non-Composite Device */ { USB_DEVICE_AND_INTERFACE_INFO(0x1199, 0x6892, 0xFF, 0xFF, 0xFF)}, { USB_DEVICE(0x1199, 0x6893) }, /* Sierra Wireless Device */ + { USB_DEVICE(0x1199, 0x68A2), /* Sierra Wireless MC77xx in QMI mode */ + .driver_info = (kernel_ulong_t)&direct_ip_interface_blacklist + }, { USB_DEVICE(0x1199, 0x68A3), /* Sierra Wireless Direct IP modems */ .driver_info = (kernel_ulong_t)&direct_ip_interface_blacklist }, diff --git a/drivers/uwb/hwa-rc.c b/drivers/uwb/hwa-rc.c index 66797e9..810c90a 100644 --- a/drivers/uwb/hwa-rc.c +++ b/drivers/uwb/hwa-rc.c @@ -645,7 +645,8 @@ void hwarc_neep_cb(struct urb *urb) dev_err(dev, "NEEP: URB error %d\n", urb->status); } result = usb_submit_urb(urb, GFP_ATOMIC); - if (result < 0) { + if (result < 0 && result != -ENODEV && result != -EPERM) { + /* ignoring unrecoverable errors */ dev_err(dev, "NEEP: Can't resubmit URB (%d) resetting device\n", result); goto error; diff --git a/drivers/uwb/neh.c b/drivers/uwb/neh.c index a269937..8cb71bb 100644 --- a/drivers/uwb/neh.c +++ b/drivers/uwb/neh.c @@ -107,6 +107,7 @@ struct uwb_rc_neh { u8 evt_type; __le16 evt; u8 context; + u8 completed; uwb_rc_cmd_cb_f cb; void *arg; @@ -409,6 +410,7 @@ static void uwb_rc_neh_grok_event(struct uwb_rc *rc, struct uwb_rceb *rceb, size struct device *dev = &rc->uwb_dev.dev; struct uwb_rc_neh *neh; struct uwb_rceb *notif; + unsigned long flags; if (rceb->bEventContext == 0) { notif = kmalloc(size, GFP_ATOMIC); @@ -422,7 +424,11 @@ static void uwb_rc_neh_grok_event(struct uwb_rc *rc, struct uwb_rceb *rceb, size } else { neh = uwb_rc_neh_lookup(rc, rceb); if (neh) { - del_timer_sync(&neh->timer); + spin_lock_irqsave(&rc->neh_lock, flags); + /* to guard against a timeout */ + neh->completed = 1; + del_timer(&neh->timer); + spin_unlock_irqrestore(&rc->neh_lock, flags); uwb_rc_neh_cb(neh, rceb, size); } else dev_warn(dev, "event 0x%02x/%04x/%02x (%zu bytes): nobody cared\n", @@ -568,6 +574,10 @@ static void uwb_rc_neh_timer(unsigned long arg) unsigned long flags; spin_lock_irqsave(&rc->neh_lock, flags); + if (neh->completed) { + spin_unlock_irqrestore(&rc->neh_lock, flags); + return; + } if (neh->context) __uwb_rc_neh_rm(rc, neh); else diff --git a/drivers/vhost/test.c b/drivers/vhost/test.c index fc9a1d7..3de00d9 100644 --- a/drivers/vhost/test.c +++ b/drivers/vhost/test.c @@ -155,7 +155,7 @@ static int vhost_test_release(struct inode *inode, struct file *f) vhost_test_stop(n, &private); vhost_test_flush(n); - vhost_dev_cleanup(&n->dev); + vhost_dev_cleanup(&n->dev, false); /* We do an extra flush before freeing memory, * since jobs can re-queue themselves. */ vhost_test_flush(n); diff --git a/drivers/virtio/virtio_balloon.c b/drivers/virtio/virtio_balloon.c index 05f0a80..c2d05a8 100644 --- a/drivers/virtio/virtio_balloon.c +++ b/drivers/virtio/virtio_balloon.c @@ -28,6 +28,13 @@ #include <linux/slab.h> #include <linux/module.h> +/* + * Balloon device works in 4K page units. So each page is pointed to by + * multiple balloon pages. All memory counters in this driver are in balloon + * page units. + */ +#define VIRTIO_BALLOON_PAGES_PER_PAGE (PAGE_SIZE >> VIRTIO_BALLOON_PFN_SHIFT) + struct virtio_balloon { struct virtio_device *vdev; @@ -42,8 +49,13 @@ struct virtio_balloon /* Waiting for host to ack the pages we released. */ struct completion acked; - /* The pages we've told the Host we're not using. */ + /* Number of balloon pages we've told the Host we're not using. */ unsigned int num_pages; + /* + * The pages we've told the Host we're not using. + * Each page on this list adds VIRTIO_BALLOON_PAGES_PER_PAGE + * to num_pages above. + */ struct list_head pages; /* The array of pfns we tell the Host about. */ @@ -66,7 +78,13 @@ static u32 page_to_balloon_pfn(struct page *page) BUILD_BUG_ON(PAGE_SHIFT < VIRTIO_BALLOON_PFN_SHIFT); /* Convert pfn from Linux page size to balloon page size. */ - return pfn >> (PAGE_SHIFT - VIRTIO_BALLOON_PFN_SHIFT); + return pfn * VIRTIO_BALLOON_PAGES_PER_PAGE; +} + +static struct page *balloon_pfn_to_page(u32 pfn) +{ + BUG_ON(pfn % VIRTIO_BALLOON_PAGES_PER_PAGE); + return pfn_to_page(pfn / VIRTIO_BALLOON_PAGES_PER_PAGE); } static void balloon_ack(struct virtqueue *vq) @@ -96,12 +114,23 @@ static void tell_host(struct virtio_balloon *vb, struct virtqueue *vq) wait_for_completion(&vb->acked); } +static void set_page_pfns(u32 pfns[], struct page *page) +{ + unsigned int i; + + /* Set balloon pfns pointing at this page. + * Note that the first pfn points at start of the page. */ + for (i = 0; i < VIRTIO_BALLOON_PAGES_PER_PAGE; i++) + pfns[i] = page_to_balloon_pfn(page) + i; +} + static void fill_balloon(struct virtio_balloon *vb, size_t num) { /* We can only do one array worth at a time. */ num = min(num, ARRAY_SIZE(vb->pfns)); - for (vb->num_pfns = 0; vb->num_pfns < num; vb->num_pfns++) { + for (vb->num_pfns = 0; vb->num_pfns < num; + vb->num_pfns += VIRTIO_BALLOON_PAGES_PER_PAGE) { struct page *page = alloc_page(GFP_HIGHUSER | __GFP_NORETRY | __GFP_NOMEMALLOC | __GFP_NOWARN); if (!page) { @@ -113,9 +142,9 @@ static void fill_balloon(struct virtio_balloon *vb, size_t num) msleep(200); break; } - vb->pfns[vb->num_pfns] = page_to_balloon_pfn(page); + set_page_pfns(vb->pfns + vb->num_pfns, page); + vb->num_pages += VIRTIO_BALLOON_PAGES_PER_PAGE; totalram_pages--; - vb->num_pages++; list_add(&page->lru, &vb->pages); } @@ -130,8 +159,9 @@ static void release_pages_by_pfn(const u32 pfns[], unsigned int num) { unsigned int i; - for (i = 0; i < num; i++) { - __free_page(pfn_to_page(pfns[i])); + /* Find pfns pointing at start of each page, get pages and free them. */ + for (i = 0; i < num; i += VIRTIO_BALLOON_PAGES_PER_PAGE) { + __free_page(balloon_pfn_to_page(pfns[i])); totalram_pages++; } } @@ -143,11 +173,12 @@ static void leak_balloon(struct virtio_balloon *vb, size_t num) /* We can only do one array worth at a time. */ num = min(num, ARRAY_SIZE(vb->pfns)); - for (vb->num_pfns = 0; vb->num_pfns < num; vb->num_pfns++) { + for (vb->num_pfns = 0; vb->num_pfns < num; + vb->num_pfns += VIRTIO_BALLOON_PAGES_PER_PAGE) { page = list_first_entry(&vb->pages, struct page, lru); list_del(&page->lru); - vb->pfns[vb->num_pfns] = page_to_balloon_pfn(page); - vb->num_pages--; + set_page_pfns(vb->pfns + vb->num_pfns, page); + vb->num_pages -= VIRTIO_BALLOON_PAGES_PER_PAGE; } /* @@ -234,11 +265,14 @@ static void virtballoon_changed(struct virtio_device *vdev) static inline s64 towards_target(struct virtio_balloon *vb) { - u32 v; + __le32 v; + s64 target; + vb->vdev->config->get(vb->vdev, offsetof(struct virtio_balloon_config, num_pages), &v, sizeof(v)); - return (s64)v - vb->num_pages; + target = le32_to_cpu(v); + return target - vb->num_pages; } static void update_balloon_size(struct virtio_balloon *vb) diff --git a/drivers/xen/gntdev.c b/drivers/xen/gntdev.c index 99d8151..1ffd03b 100644 --- a/drivers/xen/gntdev.c +++ b/drivers/xen/gntdev.c @@ -722,7 +722,7 @@ static int gntdev_mmap(struct file *flip, struct vm_area_struct *vma) vma->vm_flags |= VM_RESERVED|VM_DONTEXPAND; if (use_ptemod) - vma->vm_flags |= VM_DONTCOPY|VM_PFNMAP; + vma->vm_flags |= VM_DONTCOPY; vma->vm_private_data = map; diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c index b4d4eac..f100ce2 100644 --- a/drivers/xen/grant-table.c +++ b/drivers/xen/grant-table.c @@ -1029,6 +1029,7 @@ int gnttab_init(void) int i; unsigned int max_nr_glist_frames, nr_glist_frames; unsigned int nr_init_grefs; + int ret; nr_grant_frames = 1; boot_max_nr_grant_frames = __max_nr_grant_frames(); @@ -1047,12 +1048,16 @@ int gnttab_init(void) nr_glist_frames = (nr_grant_frames * GREFS_PER_GRANT_FRAME + RPP - 1) / RPP; for (i = 0; i < nr_glist_frames; i++) { gnttab_list[i] = (grant_ref_t *)__get_free_page(GFP_KERNEL); - if (gnttab_list[i] == NULL) + if (gnttab_list[i] == NULL) { + ret = -ENOMEM; goto ini_nomem; + } } - if (gnttab_resume() < 0) - return -ENODEV; + if (gnttab_resume() < 0) { + ret = -ENODEV; + goto ini_nomem; + } nr_init_grefs = nr_grant_frames * GREFS_PER_GRANT_FRAME; @@ -1070,7 +1075,7 @@ int gnttab_init(void) for (i--; i >= 0; i--) free_page((unsigned long)gnttab_list[i]); kfree(gnttab_list); - return -ENOMEM; + return ret; } EXPORT_SYMBOL_GPL(gnttab_init); diff --git a/drivers/xen/manage.c b/drivers/xen/manage.c index 9e14ae6..412b96c 100644 --- a/drivers/xen/manage.c +++ b/drivers/xen/manage.c @@ -132,6 +132,7 @@ static void do_suspend(void) err = dpm_suspend_end(PMSG_FREEZE); if (err) { printk(KERN_ERR "dpm_suspend_end failed: %d\n", err); + si.cancelled = 0; goto out_resume; } diff --git a/drivers/xen/xenbus/xenbus_probe_frontend.c b/drivers/xen/xenbus/xenbus_probe_frontend.c index f20c5f1..a31b54d 100644 --- a/drivers/xen/xenbus/xenbus_probe_frontend.c +++ b/drivers/xen/xenbus/xenbus_probe_frontend.c @@ -135,7 +135,7 @@ static int read_backend_details(struct xenbus_device *xendev) return xenbus_read_otherend_details(xendev, "backend-id", "backend"); } -static int is_device_connecting(struct device *dev, void *data) +static int is_device_connecting(struct device *dev, void *data, bool ignore_nonessential) { struct xenbus_device *xendev = to_xenbus_device(dev); struct device_driver *drv = data; @@ -152,16 +152,41 @@ static int is_device_connecting(struct device *dev, void *data) if (drv && (dev->driver != drv)) return 0; + if (ignore_nonessential) { + /* With older QEMU, for PVonHVM guests the guest config files + * could contain: vfb = [ 'vnc=1, vnclisten=0.0.0.0'] + * which is nonsensical as there is no PV FB (there can be + * a PVKB) running as HVM guest. */ + + if ((strncmp(xendev->nodename, "device/vkbd", 11) == 0)) + return 0; + + if ((strncmp(xendev->nodename, "device/vfb", 10) == 0)) + return 0; + } xendrv = to_xenbus_driver(dev->driver); return (xendev->state < XenbusStateConnected || (xendev->state == XenbusStateConnected && xendrv->is_ready && !xendrv->is_ready(xendev))); } +static int essential_device_connecting(struct device *dev, void *data) +{ + return is_device_connecting(dev, data, true /* ignore PV[KBB+FB] */); +} +static int non_essential_device_connecting(struct device *dev, void *data) +{ + return is_device_connecting(dev, data, false); +} -static int exists_connecting_device(struct device_driver *drv) +static int exists_essential_connecting_device(struct device_driver *drv) { return bus_for_each_dev(&xenbus_frontend.bus, NULL, drv, - is_device_connecting); + essential_device_connecting); +} +static int exists_non_essential_connecting_device(struct device_driver *drv) +{ + return bus_for_each_dev(&xenbus_frontend.bus, NULL, drv, + non_essential_device_connecting); } static int print_device_status(struct device *dev, void *data) @@ -192,6 +217,23 @@ static int print_device_status(struct device *dev, void *data) /* We only wait for device setup after most initcalls have run. */ static int ready_to_wait_for_devices; +static bool wait_loop(unsigned long start, unsigned int max_delay, + unsigned int *seconds_waited) +{ + if (time_after(jiffies, start + (*seconds_waited+5)*HZ)) { + if (!*seconds_waited) + printk(KERN_WARNING "XENBUS: Waiting for " + "devices to initialise: "); + *seconds_waited += 5; + printk("%us...", max_delay - *seconds_waited); + if (*seconds_waited == max_delay) + return true; + } + + schedule_timeout_interruptible(HZ/10); + + return false; +} /* * On a 5-minute timeout, wait for all devices currently configured. We need * to do this to guarantee that the filesystems and / or network devices @@ -215,19 +257,14 @@ static void wait_for_devices(struct xenbus_driver *xendrv) if (!ready_to_wait_for_devices || !xen_domain()) return; - while (exists_connecting_device(drv)) { - if (time_after(jiffies, start + (seconds_waited+5)*HZ)) { - if (!seconds_waited) - printk(KERN_WARNING "XENBUS: Waiting for " - "devices to initialise: "); - seconds_waited += 5; - printk("%us...", 300 - seconds_waited); - if (seconds_waited == 300) - break; - } - - schedule_timeout_interruptible(HZ/10); - } + while (exists_non_essential_connecting_device(drv)) + if (wait_loop(start, 30, &seconds_waited)) + break; + + /* Skips PVKB and PVFB check.*/ + while (exists_essential_connecting_device(drv)) + if (wait_loop(start, 270, &seconds_waited)) + break; if (seconds_waited) printk("\n"); |