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-rw-r--r--drivers/ata/Kconfig10
-rw-r--r--drivers/ata/Makefile1
-rw-r--r--drivers/ata/pata_macio.c1427
-rw-r--r--drivers/base/cpu.c34
-rw-r--r--drivers/block/swim3.c39
-rw-r--r--drivers/char/agp/uninorth-agp.c77
-rw-r--r--drivers/char/hvc_console.c1
-rw-r--r--drivers/ide/pmac.c92
-rw-r--r--drivers/macintosh/macio_asic.c52
-rw-r--r--drivers/macintosh/mediabay.c328
-rw-r--r--drivers/macintosh/nvram.c11
-rw-r--r--drivers/macintosh/therm_adt746x.c15
-rw-r--r--drivers/macintosh/via-pmu.c160
-rw-r--r--drivers/macintosh/windfarm_smu_controls.c2
-rw-r--r--drivers/mmc/host/of_mmc_spi.c2
-rw-r--r--drivers/net/ehea/ehea_hcall.h51
-rw-r--r--drivers/net/ehea/ehea_phyp.h1
-rw-r--r--drivers/of/platform.c305
-rw-r--r--drivers/spi/Kconfig11
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/mpc52xx_psc_spi.c25
-rw-r--r--drivers/spi/mpc52xx_spi.c520
-rw-r--r--drivers/spi/spi_mpc8xxx.c618
-rw-r--r--drivers/spi/xilinx_spi.c3
-rw-r--r--drivers/usb/gadget/fsl_qe_udc.h15
-rw-r--r--drivers/video/offb.c15
-rw-r--r--drivers/watchdog/Kconfig4
-rw-r--r--drivers/watchdog/Makefile1
-rw-r--r--drivers/watchdog/mpc5200_wdt.c293
29 files changed, 3247 insertions, 867 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 676f08b..85844d0 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -790,5 +790,15 @@ config PATA_BF54X
If unsure, say N.
+config PATA_MACIO
+ tristate "Apple PowerMac/PowerBook internal 'MacIO' IDE"
+ depends on PPC_PMAC
+ help
+ Most IDE capable PowerMacs have IDE busses driven by a variant
+ of this controller which is part of the Apple chipset used on
+ most PowerMac models. Some models have multiple busses using
+ different chipsets, though generally, MacIO is one of them.
+
+
endif # ATA_SFF
endif # ATA
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index d909435..fc936d4 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o
obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
obj-$(CONFIG_SATA_FSL) += sata_fsl.o
+obj-$(CONFIG_PATA_MACIO) += pata_macio.o
obj-$(CONFIG_PATA_ALI) += pata_ali.o
obj-$(CONFIG_PATA_AMD) += pata_amd.o
diff --git a/drivers/ata/pata_macio.c b/drivers/ata/pata_macio.c
new file mode 100644
index 0000000..4cc7bbd
--- /dev/null
+++ b/drivers/ata/pata_macio.c
@@ -0,0 +1,1427 @@
+/*
+ * Libata based driver for Apple "macio" family of PATA controllers
+ *
+ * Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp
+ * <benh@kernel.crashing.org>
+ *
+ * Some bits and pieces from drivers/ide/ppc/pmac.c
+ *
+ */
+
+#undef DEBUG
+#undef DEBUG_DMA
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/ata.h>
+#include <linux/libata.h>
+#include <linux/adb.h>
+#include <linux/pmu.h>
+#include <linux/scatterlist.h>
+#include <linux/of.h>
+
+#include <scsi/scsi.h>
+#include <scsi/scsi_host.h>
+#include <scsi/scsi_device.h>
+
+#include <asm/macio.h>
+#include <asm/io.h>
+#include <asm/dbdma.h>
+#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
+#include <asm/pmac_feature.h>
+#include <asm/mediabay.h>
+
+#ifdef DEBUG_DMA
+#define dev_dbgdma(dev, format, arg...) \
+ dev_printk(KERN_DEBUG , dev , format , ## arg)
+#else
+#define dev_dbgdma(dev, format, arg...) \
+ ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
+#endif
+
+#define DRV_NAME "pata_macio"
+#define DRV_VERSION "0.9"
+
+/* Models of macio ATA controller */
+enum {
+ controller_ohare, /* OHare based */
+ controller_heathrow, /* Heathrow/Paddington */
+ controller_kl_ata3, /* KeyLargo ATA-3 */
+ controller_kl_ata4, /* KeyLargo ATA-4 */
+ controller_un_ata6, /* UniNorth2 ATA-6 */
+ controller_k2_ata6, /* K2 ATA-6 */
+ controller_sh_ata6, /* Shasta ATA-6 */
+};
+
+static const char* macio_ata_names[] = {
+ "OHare ATA", /* OHare based */
+ "Heathrow ATA", /* Heathrow/Paddington */
+ "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
+ "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
+ "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
+ "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
+ "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
+};
+
+/*
+ * Extra registers, both 32-bit little-endian
+ */
+#define IDE_TIMING_CONFIG 0x200
+#define IDE_INTERRUPT 0x300
+
+/* Kauai (U2) ATA has different register setup */
+#define IDE_KAUAI_PIO_CONFIG 0x200
+#define IDE_KAUAI_ULTRA_CONFIG 0x210
+#define IDE_KAUAI_POLL_CONFIG 0x220
+
+/*
+ * Timing configuration register definitions
+ */
+
+/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
+#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
+#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
+#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
+#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
+
+/* 133Mhz cell, found in shasta.
+ * See comments about 100 Mhz Uninorth 2...
+ * Note that PIO_MASK and MDMA_MASK seem to overlap, that's just
+ * weird and I don't now why .. at this stage
+ */
+#define TR_133_PIOREG_PIO_MASK 0xff000fff
+#define TR_133_PIOREG_MDMA_MASK 0x00fff800
+#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
+#define TR_133_UDMAREG_UDMA_EN 0x00000001
+
+/* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device
+ * (106b/0033) on uninorth or K2 internal PCI bus and it's clock is
+ * controlled like gem or fw. It appears to be an evolution of keylargo
+ * ATA4 with a timing register extended to 2x32bits registers (one
+ * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.
+ * It has it's own local feature control register as well.
+ *
+ * After scratching my mind over the timing values, at least for PIO
+ * and MDMA, I think I've figured the format of the timing register,
+ * though I use pre-calculated tables for UDMA as usual...
+ */
+#define TR_100_PIO_ADDRSETUP_MASK 0xff000000 /* Size of field unknown */
+#define TR_100_PIO_ADDRSETUP_SHIFT 24
+#define TR_100_MDMA_MASK 0x00fff000
+#define TR_100_MDMA_RECOVERY_MASK 0x00fc0000
+#define TR_100_MDMA_RECOVERY_SHIFT 18
+#define TR_100_MDMA_ACCESS_MASK 0x0003f000
+#define TR_100_MDMA_ACCESS_SHIFT 12
+#define TR_100_PIO_MASK 0xff000fff
+#define TR_100_PIO_RECOVERY_MASK 0x00000fc0
+#define TR_100_PIO_RECOVERY_SHIFT 6
+#define TR_100_PIO_ACCESS_MASK 0x0000003f
+#define TR_100_PIO_ACCESS_SHIFT 0
+
+#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
+#define TR_100_UDMAREG_UDMA_EN 0x00000001
+
+
+/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
+ * 40 connector cable and to 4 on 80 connector one.
+ * Clock unit is 15ns (66Mhz)
+ *
+ * 3 Values can be programmed:
+ * - Write data setup, which appears to match the cycle time. They
+ * also call it DIOW setup.
+ * - Ready to pause time (from spec)
+ * - Address setup. That one is weird. I don't see where exactly
+ * it fits in UDMA cycles, I got it's name from an obscure piece
+ * of commented out code in Darwin. They leave it to 0, we do as
+ * well, despite a comment that would lead to think it has a
+ * min value of 45ns.
+ * Apple also add 60ns to the write data setup (or cycle time ?) on
+ * reads.
+ */
+#define TR_66_UDMA_MASK 0xfff00000
+#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
+#define TR_66_PIO_ADDRSETUP_MASK 0xe0000000 /* Address setup */
+#define TR_66_PIO_ADDRSETUP_SHIFT 29
+#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
+#define TR_66_UDMA_RDY2PAUS_SHIFT 25
+#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
+#define TR_66_UDMA_WRDATASETUP_SHIFT 21
+#define TR_66_MDMA_MASK 0x000ffc00
+#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
+#define TR_66_MDMA_RECOVERY_SHIFT 15
+#define TR_66_MDMA_ACCESS_MASK 0x00007c00
+#define TR_66_MDMA_ACCESS_SHIFT 10
+#define TR_66_PIO_MASK 0xe00003ff
+#define TR_66_PIO_RECOVERY_MASK 0x000003e0
+#define TR_66_PIO_RECOVERY_SHIFT 5
+#define TR_66_PIO_ACCESS_MASK 0x0000001f
+#define TR_66_PIO_ACCESS_SHIFT 0
+
+/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
+ * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
+ *
+ * The access time and recovery time can be programmed. Some older
+ * Darwin code base limit OHare to 150ns cycle time. I decided to do
+ * the same here fore safety against broken old hardware ;)
+ * The HalfTick bit, when set, adds half a clock (15ns) to the access
+ * time and removes one from recovery. It's not supported on KeyLargo
+ * implementation afaik. The E bit appears to be set for PIO mode 0 and
+ * is used to reach long timings used in this mode.
+ */
+#define TR_33_MDMA_MASK 0x003ff800
+#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
+#define TR_33_MDMA_RECOVERY_SHIFT 16
+#define TR_33_MDMA_ACCESS_MASK 0x0000f800
+#define TR_33_MDMA_ACCESS_SHIFT 11
+#define TR_33_MDMA_HALFTICK 0x00200000
+#define TR_33_PIO_MASK 0x000007ff
+#define TR_33_PIO_E 0x00000400
+#define TR_33_PIO_RECOVERY_MASK 0x000003e0
+#define TR_33_PIO_RECOVERY_SHIFT 5
+#define TR_33_PIO_ACCESS_MASK 0x0000001f
+#define TR_33_PIO_ACCESS_SHIFT 0
+
+/*
+ * Interrupt register definitions. Only present on newer cells
+ * (Keylargo and later afaik) so we don't use it.
+ */
+#define IDE_INTR_DMA 0x80000000
+#define IDE_INTR_DEVICE 0x40000000
+
+/*
+ * FCR Register on Kauai. Not sure what bit 0x4 is ...
+ */
+#define KAUAI_FCR_UATA_MAGIC 0x00000004
+#define KAUAI_FCR_UATA_RESET_N 0x00000002
+#define KAUAI_FCR_UATA_ENABLE 0x00000001
+
+
+/* Allow up to 256 DBDMA commands per xfer */
+#define MAX_DCMDS 256
+
+/* Don't let a DMA segment go all the way to 64K */
+#define MAX_DBDMA_SEG 0xff00
+
+
+/*
+ * Wait 1s for disk to answer on IDE bus after a hard reset
+ * of the device (via GPIO/FCR).
+ *
+ * Some devices seem to "pollute" the bus even after dropping
+ * the BSY bit (typically some combo drives slave on the UDMA
+ * bus) after a hard reset. Since we hard reset all drives on
+ * KeyLargo ATA66, we have to keep that delay around. I may end
+ * up not hard resetting anymore on these and keep the delay only
+ * for older interfaces instead (we have to reset when coming
+ * from MacOS...) --BenH.
+ */
+#define IDE_WAKEUP_DELAY_MS 1000
+
+struct pata_macio_timing;
+
+struct pata_macio_priv {
+ int kind;
+ int aapl_bus_id;
+ int mediabay : 1;
+ struct device_node *node;
+ struct macio_dev *mdev;
+ struct pci_dev *pdev;
+ struct device *dev;
+ int irq;
+ u32 treg[2][2];
+ void __iomem *tfregs;
+ void __iomem *kauai_fcr;
+ struct dbdma_cmd * dma_table_cpu;
+ dma_addr_t dma_table_dma;
+ struct ata_host *host;
+ const struct pata_macio_timing *timings;
+};
+
+/* Previous variants of this driver used to calculate timings
+ * for various variants of the chip and use tables for others.
+ *
+ * Not only was this confusing, but in addition, it isn't clear
+ * whether our calculation code was correct. It didn't entirely
+ * match the darwin code and whatever documentation I could find
+ * on these cells
+ *
+ * I decided to entirely rely on a table instead for this version
+ * of the driver. Also, because I don't really care about derated
+ * modes and really old HW other than making it work, I'm not going
+ * to calculate / snoop timing values for something else than the
+ * standard modes.
+ */
+struct pata_macio_timing {
+ int mode;
+ u32 reg1; /* Bits to set in first timing reg */
+ u32 reg2; /* Bits to set in second timing reg */
+};
+
+static const struct pata_macio_timing pata_macio_ohare_timings[] = {
+ { XFER_PIO_0, 0x00000526, 0, },
+ { XFER_PIO_1, 0x00000085, 0, },
+ { XFER_PIO_2, 0x00000025, 0, },
+ { XFER_PIO_3, 0x00000025, 0, },
+ { XFER_PIO_4, 0x00000025, 0, },
+ { XFER_MW_DMA_0, 0x00074000, 0, },
+ { XFER_MW_DMA_1, 0x00221000, 0, },
+ { XFER_MW_DMA_2, 0x00211000, 0, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_heathrow_timings[] = {
+ { XFER_PIO_0, 0x00000526, 0, },
+ { XFER_PIO_1, 0x00000085, 0, },
+ { XFER_PIO_2, 0x00000025, 0, },
+ { XFER_PIO_3, 0x00000025, 0, },
+ { XFER_PIO_4, 0x00000025, 0, },
+ { XFER_MW_DMA_0, 0x00074000, 0, },
+ { XFER_MW_DMA_1, 0x00221000, 0, },
+ { XFER_MW_DMA_2, 0x00211000, 0, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_kl33_timings[] = {
+ { XFER_PIO_0, 0x00000526, 0, },
+ { XFER_PIO_1, 0x00000085, 0, },
+ { XFER_PIO_2, 0x00000025, 0, },
+ { XFER_PIO_3, 0x00000025, 0, },
+ { XFER_PIO_4, 0x00000025, 0, },
+ { XFER_MW_DMA_0, 0x00084000, 0, },
+ { XFER_MW_DMA_1, 0x00021800, 0, },
+ { XFER_MW_DMA_2, 0x00011800, 0, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_kl66_timings[] = {
+ { XFER_PIO_0, 0x0000038c, 0, },
+ { XFER_PIO_1, 0x0000020a, 0, },
+ { XFER_PIO_2, 0x00000127, 0, },
+ { XFER_PIO_3, 0x000000c6, 0, },
+ { XFER_PIO_4, 0x00000065, 0, },
+ { XFER_MW_DMA_0, 0x00084000, 0, },
+ { XFER_MW_DMA_1, 0x00029800, 0, },
+ { XFER_MW_DMA_2, 0x00019400, 0, },
+ { XFER_UDMA_0, 0x19100000, 0, },
+ { XFER_UDMA_1, 0x14d00000, 0, },
+ { XFER_UDMA_2, 0x10900000, 0, },
+ { XFER_UDMA_3, 0x0c700000, 0, },
+ { XFER_UDMA_4, 0x0c500000, 0, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_kauai_timings[] = {
+ { XFER_PIO_0, 0x08000a92, 0, },
+ { XFER_PIO_1, 0x0800060f, 0, },
+ { XFER_PIO_2, 0x0800038b, 0, },
+ { XFER_PIO_3, 0x05000249, 0, },
+ { XFER_PIO_4, 0x04000148, 0, },
+ { XFER_MW_DMA_0, 0x00618000, 0, },
+ { XFER_MW_DMA_1, 0x00209000, 0, },
+ { XFER_MW_DMA_2, 0x00148000, 0, },
+ { XFER_UDMA_0, 0, 0x000070c1, },
+ { XFER_UDMA_1, 0, 0x00005d81, },
+ { XFER_UDMA_2, 0, 0x00004a61, },
+ { XFER_UDMA_3, 0, 0x00003a51, },
+ { XFER_UDMA_4, 0, 0x00002a31, },
+ { XFER_UDMA_5, 0, 0x00002921, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_shasta_timings[] = {
+ { XFER_PIO_0, 0x0a000c97, 0, },
+ { XFER_PIO_1, 0x07000712, 0, },
+ { XFER_PIO_2, 0x040003cd, 0, },
+ { XFER_PIO_3, 0x0500028b, 0, },
+ { XFER_PIO_4, 0x0400010a, 0, },
+ { XFER_MW_DMA_0, 0x00820800, 0, },
+ { XFER_MW_DMA_1, 0x0028b000, 0, },
+ { XFER_MW_DMA_2, 0x001ca000, 0, },
+ { XFER_UDMA_0, 0, 0x00035901, },
+ { XFER_UDMA_1, 0, 0x000348b1, },
+ { XFER_UDMA_2, 0, 0x00033881, },
+ { XFER_UDMA_3, 0, 0x00033861, },
+ { XFER_UDMA_4, 0, 0x00033841, },
+ { XFER_UDMA_5, 0, 0x00033031, },
+ { XFER_UDMA_6, 0, 0x00033021, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing *pata_macio_find_timing(
+ struct pata_macio_priv *priv,
+ int mode)
+{
+ int i;
+
+ for (i = 0; priv->timings[i].mode > 0; i++) {
+ if (priv->timings[i].mode == mode)
+ return &priv->timings[i];
+ }
+ return NULL;
+}
+
+
+static void pata_macio_apply_timings(struct ata_port *ap, unsigned int device)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+ void __iomem *rbase = ap->ioaddr.cmd_addr;
+
+ if (priv->kind == controller_sh_ata6 ||
+ priv->kind == controller_un_ata6 ||
+ priv->kind == controller_k2_ata6) {
+ writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG);
+ writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG);
+ } else
+ writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG);
+}
+
+static void pata_macio_dev_select(struct ata_port *ap, unsigned int device)
+{
+ ata_sff_dev_select(ap, device);
+
+ /* Apply timings */
+ pata_macio_apply_timings(ap, device);
+}
+
+static void pata_macio_set_timings(struct ata_port *ap,
+ struct ata_device *adev)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+ const struct pata_macio_timing *t;
+
+ dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n",
+ adev->devno,
+ adev->pio_mode,
+ ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)),
+ adev->dma_mode,
+ ata_mode_string(ata_xfer_mode2mask(adev->dma_mode)));
+
+ /* First clear timings */
+ priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0;
+
+ /* Now get the PIO timings */
+ t = pata_macio_find_timing(priv, adev->pio_mode);
+ if (t == NULL) {
+ dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n",
+ adev->pio_mode);
+ t = pata_macio_find_timing(priv, XFER_PIO_0);
+ }
+ BUG_ON(t == NULL);
+
+ /* PIO timings only ever use the first treg */
+ priv->treg[adev->devno][0] |= t->reg1;
+
+ /* Now get DMA timings */
+ t = pata_macio_find_timing(priv, adev->dma_mode);
+ if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) {
+ dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n");
+ t = pata_macio_find_timing(priv, XFER_MW_DMA_0);
+ }
+ BUG_ON(t == NULL);
+
+ /* DMA timings can use both tregs */
+ priv->treg[adev->devno][0] |= t->reg1;
+ priv->treg[adev->devno][1] |= t->reg2;
+
+ dev_dbg(priv->dev, " -> %08x %08x\n",
+ priv->treg[adev->devno][0],
+ priv->treg[adev->devno][1]);
+
+ /* Apply to hardware */
+ pata_macio_apply_timings(ap, adev->devno);
+}
+
+/*
+ * Blast some well known "safe" values to the timing registers at init or
+ * wakeup from sleep time, before we do real calculation
+ */
+static void pata_macio_default_timings(struct pata_macio_priv *priv)
+{
+ unsigned int value, value2 = 0;
+
+ switch(priv->kind) {
+ case controller_sh_ata6:
+ value = 0x0a820c97;
+ value2 = 0x00033031;
+ break;
+ case controller_un_ata6:
+ case controller_k2_ata6:
+ value = 0x08618a92;
+ value2 = 0x00002921;
+ break;
+ case controller_kl_ata4:
+ value = 0x0008438c;
+ break;
+ case controller_kl_ata3:
+ value = 0x00084526;
+ break;
+ case controller_heathrow:
+ case controller_ohare:
+ default:
+ value = 0x00074526;
+ break;
+ }
+ priv->treg[0][0] = priv->treg[1][0] = value;
+ priv->treg[0][1] = priv->treg[1][1] = value2;
+}
+
+static int pata_macio_cable_detect(struct ata_port *ap)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+
+ /* Get cable type from device-tree */
+ if (priv->kind == controller_kl_ata4 ||
+ priv->kind == controller_un_ata6 ||
+ priv->kind == controller_k2_ata6 ||
+ priv->kind == controller_sh_ata6) {
+ const char* cable = of_get_property(priv->node, "cable-type",
+ NULL);
+ struct device_node *root = of_find_node_by_path("/");
+ const char *model = of_get_property(root, "model", NULL);
+
+ if (cable && !strncmp(cable, "80-", 3)) {
+ /* Some drives fail to detect 80c cable in PowerBook
+ * These machine use proprietary short IDE cable
+ * anyway
+ */
+ if (!strncmp(model, "PowerBook", 9))
+ return ATA_CBL_PATA40_SHORT;
+ else
+ return ATA_CBL_PATA80;
+ }
+ }
+
+ /* G5's seem to have incorrect cable type in device-tree.
+ * Let's assume they always have a 80 conductor cable, this seem to
+ * be always the case unless the user mucked around
+ */
+ if (of_device_is_compatible(priv->node, "K2-UATA") ||
+ of_device_is_compatible(priv->node, "shasta-ata"))
+ return ATA_CBL_PATA80;
+
+ /* Anything else is 40 connectors */
+ return ATA_CBL_PATA40;
+}
+
+static void pata_macio_qc_prep(struct ata_queued_cmd *qc)
+{
+ unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE);
+ struct ata_port *ap = qc->ap;
+ struct pata_macio_priv *priv = ap->private_data;
+ struct scatterlist *sg;
+ struct dbdma_cmd *table;
+ unsigned int si, pi;
+
+ dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n",
+ __func__, qc, qc->flags, write, qc->dev->devno);
+
+ if (!(qc->flags & ATA_QCFLAG_DMAMAP))
+ return;
+
+ table = (struct dbdma_cmd *) priv->dma_table_cpu;
+
+ pi = 0;
+ for_each_sg(qc->sg, sg, qc->n_elem, si) {
+ u32 addr, sg_len, len;
+
+ /* determine if physical DMA addr spans 64K boundary.
+ * Note h/w doesn't support 64-bit, so we unconditionally
+ * truncate dma_addr_t to u32.
+ */
+ addr = (u32) sg_dma_address(sg);
+ sg_len = sg_dma_len(sg);
+
+ while (sg_len) {
+ /* table overflow should never happen */
+ BUG_ON (pi++ >= MAX_DCMDS);
+
+ len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG;
+ st_le16(&table->command, write ? OUTPUT_MORE: INPUT_MORE);
+ st_le16(&table->req_count, len);
+ st_le32(&table->phy_addr, addr);
+ table->cmd_dep = 0;
+ table->xfer_status = 0;
+ table->res_count = 0;
+ addr += len;
+ sg_len -= len;
+ ++table;
+ }
+ }
+
+ /* Should never happen according to Tejun */
+ BUG_ON(!pi);
+
+ /* Convert the last command to an input/output */
+ table--;
+ st_le16(&table->command, write ? OUTPUT_LAST: INPUT_LAST);
+ table++;
+
+ /* Add the stop command to the end of the list */
+ memset(table, 0, sizeof(struct dbdma_cmd));
+ st_le16(&table->command, DBDMA_STOP);
+
+ dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi);
+}
+
+
+static void pata_macio_freeze(struct ata_port *ap)
+{
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+
+ if (dma_regs) {
+ unsigned int timeout = 1000000;
+
+ /* Make sure DMA controller is stopped */
+ writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);
+ while (--timeout && (readl(&dma_regs->status) & RUN))
+ udelay(1);
+ }
+
+ ata_sff_freeze(ap);
+}
+
+
+static void pata_macio_bmdma_setup(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ struct pata_macio_priv *priv = ap->private_data;
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+ int dev = qc->dev->devno;
+
+ dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
+
+ /* Make sure DMA commands updates are visible */
+ writel(priv->dma_table_dma, &dma_regs->cmdptr);
+
+ /* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on
+ * UDMA reads
+ */
+ if (priv->kind == controller_kl_ata4 &&
+ (priv->treg[dev][0] & TR_66_UDMA_EN)) {
+ void __iomem *rbase = ap->ioaddr.cmd_addr;
+ u32 reg = priv->treg[dev][0];
+
+ if (!(qc->tf.flags & ATA_TFLAG_WRITE))
+ reg += 0x00800000;
+ writel(reg, rbase + IDE_TIMING_CONFIG);
+ }
+
+ /* issue r/w command */
+ ap->ops->sff_exec_command(ap, &qc->tf);
+}
+
+static void pata_macio_bmdma_start(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ struct pata_macio_priv *priv = ap->private_data;
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+
+ dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
+
+ writel((RUN << 16) | RUN, &dma_regs->control);
+ /* Make sure it gets to the controller right now */
+ (void)readl(&dma_regs->control);
+}
+
+static void pata_macio_bmdma_stop(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ struct pata_macio_priv *priv = ap->private_data;
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+ unsigned int timeout = 1000000;
+
+ dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
+
+ /* Stop the DMA engine and wait for it to full halt */
+ writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);
+ while (--timeout && (readl(&dma_regs->status) & RUN))
+ udelay(1);
+}
+
+static u8 pata_macio_bmdma_status(struct ata_port *ap)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+ u32 dstat, rstat = ATA_DMA_INTR;
+ unsigned long timeout = 0;
+
+ dstat = readl(&dma_regs->status);
+
+ dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat);
+
+ /* We have two things to deal with here:
+ *
+ * - The dbdma won't stop if the command was started
+ * but completed with an error without transferring all
+ * datas. This happens when bad blocks are met during
+ * a multi-block transfer.
+ *
+ * - The dbdma fifo hasn't yet finished flushing to
+ * to system memory when the disk interrupt occurs.
+ *
+ */
+
+ /* First check for errors */
+ if ((dstat & (RUN|DEAD)) != RUN)
+ rstat |= ATA_DMA_ERR;
+
+ /* If ACTIVE is cleared, the STOP command has been hit and
+ * the transfer is complete. If not, we have to flush the
+ * channel.
+ */
+ if ((dstat & ACTIVE) == 0)
+ return rstat;
+
+ dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__);
+
+ /* If dbdma didn't execute the STOP command yet, the
+ * active bit is still set. We consider that we aren't
+ * sharing interrupts (which is hopefully the case with
+ * those controllers) and so we just try to flush the
+ * channel for pending data in the fifo
+ */
+ udelay(1);
+ writel((FLUSH << 16) | FLUSH, &dma_regs->control);
+ for (;;) {
+ udelay(1);
+ dstat = readl(&dma_regs->status);
+ if ((dstat & FLUSH) == 0)
+ break;
+ if (++timeout > 1000) {
+ dev_warn(priv->dev, "timeout flushing DMA\n");
+ rstat |= ATA_DMA_ERR;
+ break;
+ }
+ }
+ return rstat;
+}
+
+/* port_start is when we allocate the DMA command list */
+static int pata_macio_port_start(struct ata_port *ap)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+
+ if (ap->ioaddr.bmdma_addr == NULL)
+ return 0;
+
+ /* Allocate space for the DBDMA commands.
+ *
+ * The +2 is +1 for the stop command and +1 to allow for
+ * aligning the start address to a multiple of 16 bytes.
+ */
+ priv->dma_table_cpu =
+ dmam_alloc_coherent(priv->dev,
+ (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
+ &priv->dma_table_dma, GFP_KERNEL);
+ if (priv->dma_table_cpu == NULL) {
+ dev_err(priv->dev, "Unable to allocate DMA command list\n");
+ ap->ioaddr.bmdma_addr = NULL;
+ }
+ return 0;
+}
+
+static void pata_macio_irq_clear(struct ata_port *ap)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+
+ /* Nothing to do here */
+
+ dev_dbgdma(priv->dev, "%s\n", __func__);
+}
+
+static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)
+{
+ dev_dbg(priv->dev, "Enabling & resetting... \n");
+
+ if (priv->mediabay)
+ return;
+
+ if (priv->kind == controller_ohare && !resume) {
+ /* The code below is having trouble on some ohare machines
+ * (timing related ?). Until I can put my hand on one of these
+ * units, I keep the old way
+ */
+ ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1);
+ } else {
+ int rc;
+
+ /* Reset and enable controller */
+ rc = ppc_md.feature_call(PMAC_FTR_IDE_RESET,
+ priv->node, priv->aapl_bus_id, 1);
+ ppc_md.feature_call(PMAC_FTR_IDE_ENABLE,
+ priv->node, priv->aapl_bus_id, 1);
+ msleep(10);
+ /* Only bother waiting if there's a reset control */
+ if (rc == 0) {
+ ppc_md.feature_call(PMAC_FTR_IDE_RESET,
+ priv->node, priv->aapl_bus_id, 0);
+ msleep(IDE_WAKEUP_DELAY_MS);
+ }
+ }
+
+ /* If resuming a PCI device, restore the config space here */
+ if (priv->pdev && resume) {
+ int rc;
+
+ pci_restore_state(priv->pdev);
+ rc = pcim_enable_device(priv->pdev);
+ if (rc)
+ dev_printk(KERN_ERR, &priv->pdev->dev,
+ "Failed to enable device after resume (%d)\n", rc);
+ else
+ pci_set_master(priv->pdev);
+ }
+
+ /* On Kauai, initialize the FCR. We don't perform a reset, doesn't really
+ * seem necessary and speeds up the boot process
+ */
+ if (priv->kauai_fcr)
+ writel(KAUAI_FCR_UATA_MAGIC |
+ KAUAI_FCR_UATA_RESET_N |
+ KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr);
+}
+
+/* Hook the standard slave config to fixup some HW related alignment
+ * restrictions
+ */
+static int pata_macio_slave_config(struct scsi_device *sdev)
+{
+ struct ata_port *ap = ata_shost_to_port(sdev->host);
+ struct pata_macio_priv *priv = ap->private_data;
+ struct ata_device *dev;
+ u16 cmd;
+ int rc;
+
+ /* First call original */
+ rc = ata_scsi_slave_config(sdev);
+ if (rc)
+ return rc;
+
+ /* This is lifted from sata_nv */
+ dev = &ap->link.device[sdev->id];
+
+ /* OHare has issues with non cache aligned DMA on some chipsets */
+ if (priv->kind == controller_ohare) {
+ blk_queue_update_dma_alignment(sdev->request_queue, 31);
+ blk_queue_update_dma_pad(sdev->request_queue, 31);
+
+ /* Tell the world about it */
+ ata_dev_printk(dev, KERN_INFO, "OHare alignment limits applied\n");
+ return 0;
+ }
+
+ /* We only have issues with ATAPI */
+ if (dev->class != ATA_DEV_ATAPI)
+ return 0;
+
+ /* Shasta and K2 seem to have "issues" with reads ... */
+ if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) {
+ /* Allright these are bad, apply restrictions */
+ blk_queue_update_dma_alignment(sdev->request_queue, 15);
+ blk_queue_update_dma_pad(sdev->request_queue, 15);
+
+ /* We enable MWI and hack cache line size directly here, this
+ * is specific to this chipset and not normal values, we happen
+ * to somewhat know what we are doing here (which is basically
+ * to do the same Apple does and pray they did not get it wrong :-)
+ */
+ BUG_ON(!priv->pdev);
+ pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd);
+ pci_write_config_word(priv->pdev, PCI_COMMAND,
+ cmd | PCI_COMMAND_INVALIDATE);
+
+ /* Tell the world about it */
+ ata_dev_printk(dev, KERN_INFO,
+ "K2/Shasta alignment limits applied\n");
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg)
+{
+ int rc;
+
+ /* First, core libata suspend to do most of the work */
+ rc = ata_host_suspend(priv->host, mesg);
+ if (rc)
+ return rc;
+
+ /* Restore to default timings */
+ pata_macio_default_timings(priv);
+
+ /* Mask interrupt. Not strictly necessary but old driver did
+ * it and I'd rather not change that here */
+ disable_irq(priv->irq);
+
+ /* The media bay will handle itself just fine */
+ if (priv->mediabay)
+ return 0;
+
+ /* Kauai has bus control FCRs directly here */
+ if (priv->kauai_fcr) {
+ u32 fcr = readl(priv->kauai_fcr);
+ fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
+ writel(fcr, priv->kauai_fcr);
+ }
+
+ /* For PCI, save state and disable DMA. No need to call
+ * pci_set_power_state(), the HW doesn't do D states that
+ * way, the platform code will take care of suspending the
+ * ASIC properly
+ */
+ if (priv->pdev) {
+ pci_save_state(priv->pdev);
+ pci_disable_device(priv->pdev);
+ }
+
+ /* Disable the bus on older machines and the cell on kauai */
+ ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node,
+ priv->aapl_bus_id, 0);
+
+ return 0;
+}
+
+static int pata_macio_do_resume(struct pata_macio_priv *priv)
+{
+ /* Reset and re-enable the HW */
+ pata_macio_reset_hw(priv, 1);
+
+ /* Sanitize drive timings */
+ pata_macio_apply_timings(priv->host->ports[0], 0);
+
+ /* We want our IRQ back ! */
+ enable_irq(priv->irq);
+
+ /* Let the libata core take it from there */
+ ata_host_resume(priv->host);
+
+ return 0;
+}
+
+#endif /* CONFIG_PM */
+
+static struct scsi_host_template pata_macio_sht = {
+ ATA_BASE_SHT(DRV_NAME),
+ .sg_tablesize = MAX_DCMDS,
+ /* We may not need that strict one */
+ .dma_boundary = ATA_DMA_BOUNDARY,
+ .slave_configure = pata_macio_slave_config,
+};
+
+static struct ata_port_operations pata_macio_ops = {
+ .inherits = &ata_sff_port_ops,
+
+ .freeze = pata_macio_freeze,
+ .set_piomode = pata_macio_set_timings,
+ .set_dmamode = pata_macio_set_timings,
+ .cable_detect = pata_macio_cable_detect,
+ .sff_dev_select = pata_macio_dev_select,
+ .qc_prep = pata_macio_qc_prep,
+ .mode_filter = ata_bmdma_mode_filter,
+ .bmdma_setup = pata_macio_bmdma_setup,
+ .bmdma_start = pata_macio_bmdma_start,
+ .bmdma_stop = pata_macio_bmdma_stop,
+ .bmdma_status = pata_macio_bmdma_status,
+ .port_start = pata_macio_port_start,
+ .sff_irq_clear = pata_macio_irq_clear,
+};
+
+static void __devinit pata_macio_invariants(struct pata_macio_priv *priv)
+{
+ const int *bidp;
+
+ /* Identify the type of controller */
+ if (of_device_is_compatible(priv->node, "shasta-ata")) {
+ priv->kind = controller_sh_ata6;
+ priv->timings = pata_macio_shasta_timings;
+ } else if (of_device_is_compatible(priv->node, "kauai-ata")) {
+ priv->kind = controller_un_ata6;
+ priv->timings = pata_macio_kauai_timings;
+ } else if (of_device_is_compatible(priv->node, "K2-UATA")) {
+ priv->kind = controller_k2_ata6;
+ priv->timings = pata_macio_kauai_timings;
+ } else if (of_device_is_compatible(priv->node, "keylargo-ata")) {
+ if (strcmp(priv->node->name, "ata-4") == 0) {
+ priv->kind = controller_kl_ata4;
+ priv->timings = pata_macio_kl66_timings;
+ } else {
+ priv->kind = controller_kl_ata3;
+ priv->timings = pata_macio_kl33_timings;
+ }
+ } else if (of_device_is_compatible(priv->node, "heathrow-ata")) {
+ priv->kind = controller_heathrow;
+ priv->timings = pata_macio_heathrow_timings;
+ } else {
+ priv->kind = controller_ohare;
+ priv->timings = pata_macio_ohare_timings;
+ }
+
+ /* XXX FIXME --- setup priv->mediabay here */
+
+ /* Get Apple bus ID (for clock and ASIC control) */
+ bidp = of_get_property(priv->node, "AAPL,bus-id", NULL);
+ priv->aapl_bus_id = bidp ? *bidp : 0;
+
+ /* Fixup missing Apple bus ID in case of media-bay */
+ if (priv->mediabay && bidp == 0)
+ priv->aapl_bus_id = 1;
+}
+
+static void __devinit pata_macio_setup_ios(struct ata_ioports *ioaddr,
+ void __iomem * base,
+ void __iomem * dma)
+{
+ /* cmd_addr is the base of regs for that port */
+ ioaddr->cmd_addr = base;
+
+ /* taskfile registers */
+ ioaddr->data_addr = base + (ATA_REG_DATA << 4);
+ ioaddr->error_addr = base + (ATA_REG_ERR << 4);
+ ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4);
+ ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4);
+ ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4);
+ ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4);
+ ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4);
+ ioaddr->device_addr = base + (ATA_REG_DEVICE << 4);
+ ioaddr->status_addr = base + (ATA_REG_STATUS << 4);
+ ioaddr->command_addr = base + (ATA_REG_CMD << 4);
+ ioaddr->altstatus_addr = base + 0x160;
+ ioaddr->ctl_addr = base + 0x160;
+ ioaddr->bmdma_addr = dma;
+}
+
+static void __devinit pmac_macio_calc_timing_masks(struct pata_macio_priv *priv,
+ struct ata_port_info *pinfo)
+{
+ int i = 0;
+
+ pinfo->pio_mask = 0;
+ pinfo->mwdma_mask = 0;
+ pinfo->udma_mask = 0;
+
+ while (priv->timings[i].mode > 0) {
+ unsigned int mask = 1U << (priv->timings[i].mode & 0x0f);
+ switch(priv->timings[i].mode & 0xf0) {
+ case 0x00: /* PIO */
+ pinfo->pio_mask |= (mask >> 8);
+ break;
+ case 0x20: /* MWDMA */
+ pinfo->mwdma_mask |= mask;
+ break;
+ case 0x40: /* UDMA */
+ pinfo->udma_mask |= mask;
+ break;
+ }
+ i++;
+ }
+ dev_dbg(priv->dev, "Supported masks: PIO=%lx, MWDMA=%lx, UDMA=%lx\n",
+ pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask);
+}
+
+static int __devinit pata_macio_common_init(struct pata_macio_priv *priv,
+ resource_size_t tfregs,
+ resource_size_t dmaregs,
+ resource_size_t fcregs,
+ unsigned long irq)
+{
+ struct ata_port_info pinfo;
+ const struct ata_port_info *ppi[] = { &pinfo, NULL };
+ void __iomem *dma_regs = NULL;
+
+ /* Fill up privates with various invariants collected from the
+ * device-tree
+ */
+ pata_macio_invariants(priv);
+
+ /* Make sure we have sane initial timings in the cache */
+ pata_macio_default_timings(priv);
+
+ /* Not sure what the real max is but we know it's less than 64K, let's
+ * use 64K minus 256
+ */
+ dma_set_max_seg_size(priv->dev, MAX_DBDMA_SEG);
+
+ /* Allocate libata host for 1 port */
+ memset(&pinfo, 0, sizeof(struct ata_port_info));
+ pmac_macio_calc_timing_masks(priv, &pinfo);
+ pinfo.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO |
+ ATA_FLAG_NO_LEGACY;
+ pinfo.port_ops = &pata_macio_ops;
+ pinfo.private_data = priv;
+
+ priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1);
+ if (priv->host == NULL) {
+ dev_err(priv->dev, "Failed to allocate ATA port structure\n");
+ return -ENOMEM;
+ }
+
+ /* Setup the private data in host too */
+ priv->host->private_data = priv;
+
+ /* Map base registers */
+ priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100);
+ if (priv->tfregs == NULL) {
+ dev_err(priv->dev, "Failed to map ATA ports\n");
+ return -ENOMEM;
+ }
+ priv->host->iomap = &priv->tfregs;
+
+ /* Map DMA regs */
+ if (dmaregs != 0) {
+ dma_regs = devm_ioremap(priv->dev, dmaregs,
+ sizeof(struct dbdma_regs));
+ if (dma_regs == NULL)
+ dev_warn(priv->dev, "Failed to map ATA DMA registers\n");
+ }
+
+ /* If chip has local feature control, map those regs too */
+ if (fcregs != 0) {
+ priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4);
+ if (priv->kauai_fcr == NULL) {
+ dev_err(priv->dev, "Failed to map ATA FCR register\n");
+ return -ENOMEM;
+ }
+ }
+
+ /* Setup port data structure */
+ pata_macio_setup_ios(&priv->host->ports[0]->ioaddr,
+ priv->tfregs, dma_regs);
+ priv->host->ports[0]->private_data = priv;
+
+ /* hard-reset the controller */
+ pata_macio_reset_hw(priv, 0);
+ pata_macio_apply_timings(priv->host->ports[0], 0);
+
+ /* Enable bus master if necessary */
+ if (priv->pdev && dma_regs)
+ pci_set_master(priv->pdev);
+
+ dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n",
+ macio_ata_names[priv->kind], priv->aapl_bus_id);
+
+ /* Start it up */
+ priv->irq = irq;
+ return ata_host_activate(priv->host, irq, ata_sff_interrupt, 0,
+ &pata_macio_sht);
+}
+
+static int __devinit pata_macio_attach(struct macio_dev *mdev,
+ const struct of_device_id *match)
+{
+ struct pata_macio_priv *priv;
+ resource_size_t tfregs, dmaregs = 0;
+ unsigned long irq;
+ int rc;
+
+ /* Check for broken device-trees */
+ if (macio_resource_count(mdev) == 0) {
+ dev_err(&mdev->ofdev.dev,
+ "No addresses for controller\n");
+ return -ENXIO;
+ }
+
+ /* Enable managed resources */
+ macio_enable_devres(mdev);
+
+ /* Allocate and init private data structure */
+ priv = devm_kzalloc(&mdev->ofdev.dev,
+ sizeof(struct pata_macio_priv), GFP_KERNEL);
+ if (priv == NULL) {
+ dev_err(&mdev->ofdev.dev,
+ "Failed to allocate private memory\n");
+ return -ENOMEM;
+ }
+ priv->node = of_node_get(mdev->ofdev.node);
+ priv->mdev = mdev;
+ priv->dev = &mdev->ofdev.dev;
+
+ /* Request memory resource for taskfile registers */
+ if (macio_request_resource(mdev, 0, "pata-macio")) {
+ dev_err(&mdev->ofdev.dev,
+ "Cannot obtain taskfile resource\n");
+ return -EBUSY;
+ }
+ tfregs = macio_resource_start(mdev, 0);
+
+ /* Request resources for DMA registers if any */
+ if (macio_resource_count(mdev) >= 2) {
+ if (macio_request_resource(mdev, 1, "pata-macio-dma"))
+ dev_err(&mdev->ofdev.dev,
+ "Cannot obtain DMA resource\n");
+ else
+ dmaregs = macio_resource_start(mdev, 1);
+ }
+
+ /*
+ * Fixup missing IRQ for some old implementations with broken
+ * device-trees.
+ *
+ * This is a bit bogus, it should be fixed in the device-tree itself,
+ * via the existing macio fixups, based on the type of interrupt
+ * controller in the machine. However, I have no test HW for this case,
+ * and this trick works well enough on those old machines...
+ */
+ if (macio_irq_count(mdev) == 0) {
+ dev_warn(&mdev->ofdev.dev,
+ "No interrupts for controller, using 13\n");
+ irq = irq_create_mapping(NULL, 13);
+ } else
+ irq = macio_irq(mdev, 0);
+
+ /* Prevvent media bay callbacks until fully registered */
+ lock_media_bay(priv->mdev->media_bay);
+
+ /* Get register addresses and call common initialization */
+ rc = pata_macio_common_init(priv,
+ tfregs, /* Taskfile regs */
+ dmaregs, /* DBDMA regs */
+ 0, /* Feature control */
+ irq);
+ unlock_media_bay(priv->mdev->media_bay);
+
+ return rc;
+}
+
+static int __devexit pata_macio_detach(struct macio_dev *mdev)
+{
+ struct ata_host *host = macio_get_drvdata(mdev);
+ struct pata_macio_priv *priv = host->private_data;
+
+ lock_media_bay(priv->mdev->media_bay);
+
+ /* Make sure the mediabay callback doesn't try to access
+ * dead stuff
+ */
+ priv->host->private_data = NULL;
+
+ ata_host_detach(host);
+
+ unlock_media_bay(priv->mdev->media_bay);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
+{
+ struct ata_host *host = macio_get_drvdata(mdev);
+
+ return pata_macio_do_suspend(host->private_data, mesg);
+}
+
+static int pata_macio_resume(struct macio_dev *mdev)
+{
+ struct ata_host *host = macio_get_drvdata(mdev);
+
+ return pata_macio_do_resume(host->private_data);
+}
+
+#endif /* CONFIG_PM */
+
+#ifdef CONFIG_PMAC_MEDIABAY
+static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state)
+{
+ struct ata_host *host = macio_get_drvdata(mdev);
+ struct ata_port *ap;
+ struct ata_eh_info *ehi;
+ struct ata_device *dev;
+ unsigned long flags;
+
+ if (!host || !host->private_data)
+ return;
+ ap = host->ports[0];
+ spin_lock_irqsave(ap->lock, flags);
+ ehi = &ap->link.eh_info;
+ if (mb_state == MB_CD) {
+ ata_ehi_push_desc(ehi, "mediabay plug");
+ ata_ehi_hotplugged(ehi);
+ ata_port_freeze(ap);
+ } else {
+ ata_ehi_push_desc(ehi, "mediabay unplug");
+ ata_for_each_dev(dev, &ap->link, ALL)
+ dev->flags |= ATA_DFLAG_DETACH;
+ ata_port_abort(ap);
+ }
+ spin_unlock_irqrestore(ap->lock, flags);
+
+}
+#endif /* CONFIG_PMAC_MEDIABAY */
+
+
+static int __devinit pata_macio_pci_attach(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ struct pata_macio_priv *priv;
+ struct device_node *np;
+ resource_size_t rbase;
+
+ /* We cannot use a MacIO controller without its OF device node */
+ np = pci_device_to_OF_node(pdev);
+ if (np == NULL) {
+ dev_err(&pdev->dev,
+ "Cannot find OF device node for controller\n");
+ return -ENODEV;
+ }
+
+ /* Check that it can be enabled */
+ if (pcim_enable_device(pdev)) {
+ dev_err(&pdev->dev,
+ "Cannot enable controller PCI device\n");
+ return -ENXIO;
+ }
+
+ /* Allocate and init private data structure */
+ priv = devm_kzalloc(&pdev->dev,
+ sizeof(struct pata_macio_priv), GFP_KERNEL);
+ if (priv == NULL) {
+ dev_err(&pdev->dev,
+ "Failed to allocate private memory\n");
+ return -ENOMEM;
+ }
+ priv->node = of_node_get(np);
+ priv->pdev = pdev;
+ priv->dev = &pdev->dev;
+
+ /* Get MMIO regions */
+ if (pci_request_regions(pdev, "pata-macio")) {
+ dev_err(&pdev->dev,
+ "Cannot obtain PCI resources\n");
+ return -EBUSY;
+ }
+
+ /* Get register addresses and call common initialization */
+ rbase = pci_resource_start(pdev, 0);
+ if (pata_macio_common_init(priv,
+ rbase + 0x2000, /* Taskfile regs */
+ rbase + 0x1000, /* DBDMA regs */
+ rbase, /* Feature control */
+ pdev->irq))
+ return -ENXIO;
+
+ return 0;
+}
+
+static void __devexit pata_macio_pci_detach(struct pci_dev *pdev)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+
+ ata_host_detach(host);
+}
+
+#ifdef CONFIG_PM
+
+static int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+
+ return pata_macio_do_suspend(host->private_data, mesg);
+}
+
+static int pata_macio_pci_resume(struct pci_dev *pdev)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+
+ return pata_macio_do_resume(host->private_data);
+}
+
+#endif /* CONFIG_PM */
+
+static struct of_device_id pata_macio_match[] =
+{
+ {
+ .name = "IDE",
+ },
+ {
+ .name = "ATA",
+ },
+ {
+ .type = "ide",
+ },
+ {
+ .type = "ata",
+ },
+ {},
+};
+
+static struct macio_driver pata_macio_driver =
+{
+ .name = "pata-macio",
+ .match_table = pata_macio_match,
+ .probe = pata_macio_attach,
+ .remove = pata_macio_detach,
+#ifdef CONFIG_PM
+ .suspend = pata_macio_suspend,
+ .resume = pata_macio_resume,
+#endif
+#ifdef CONFIG_PMAC_MEDIABAY
+ .mediabay_event = pata_macio_mb_event,
+#endif
+ .driver = {
+ .owner = THIS_MODULE,
+ },
+};
+
+static const struct pci_device_id pata_macio_pci_match[] = {
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
+ {},
+};
+
+static struct pci_driver pata_macio_pci_driver = {
+ .name = "pata-pci-macio",
+ .id_table = pata_macio_pci_match,
+ .probe = pata_macio_pci_attach,
+ .remove = pata_macio_pci_detach,
+#ifdef CONFIG_PM
+ .suspend = pata_macio_pci_suspend,
+ .resume = pata_macio_pci_resume,
+#endif
+ .driver = {
+ .owner = THIS_MODULE,
+ },
+};
+MODULE_DEVICE_TABLE(pci, pata_macio_pci_match);
+
+
+static int __init pata_macio_init(void)
+{
+ int rc;
+
+ if (!machine_is(powermac))
+ return -ENODEV;
+
+ rc = pci_register_driver(&pata_macio_pci_driver);
+ if (rc)
+ return rc;
+ rc = macio_register_driver(&pata_macio_driver);
+ if (rc) {
+ pci_unregister_driver(&pata_macio_pci_driver);
+ return rc;
+ }
+ return 0;
+}
+
+static void __exit pata_macio_exit(void)
+{
+ macio_unregister_driver(&pata_macio_driver);
+ pci_unregister_driver(&pata_macio_pci_driver);
+}
+
+module_init(pata_macio_init);
+module_exit(pata_macio_exit);
+
+MODULE_AUTHOR("Benjamin Herrenschmidt");
+MODULE_DESCRIPTION("Apple MacIO PATA driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
index e62a4cc..27fd775 100644
--- a/drivers/base/cpu.c
+++ b/drivers/base/cpu.c
@@ -35,6 +35,7 @@ static ssize_t __ref store_online(struct sys_device *dev, struct sysdev_attribut
struct cpu *cpu = container_of(dev, struct cpu, sysdev);
ssize_t ret;
+ cpu_hotplug_driver_lock();
switch (buf[0]) {
case '0':
ret = cpu_down(cpu->sysdev.id);
@@ -49,6 +50,7 @@ static ssize_t __ref store_online(struct sys_device *dev, struct sysdev_attribut
default:
ret = -EINVAL;
}
+ cpu_hotplug_driver_unlock();
if (ret >= 0)
ret = count;
@@ -72,6 +74,38 @@ void unregister_cpu(struct cpu *cpu)
per_cpu(cpu_sys_devices, logical_cpu) = NULL;
return;
}
+
+#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
+static ssize_t cpu_probe_store(struct class *class, const char *buf,
+ size_t count)
+{
+ return arch_cpu_probe(buf, count);
+}
+
+static ssize_t cpu_release_store(struct class *class, const char *buf,
+ size_t count)
+{
+ return arch_cpu_release(buf, count);
+}
+
+static CLASS_ATTR(probe, S_IWUSR, NULL, cpu_probe_store);
+static CLASS_ATTR(release, S_IWUSR, NULL, cpu_release_store);
+
+int __init cpu_probe_release_init(void)
+{
+ int rc;
+
+ rc = sysfs_create_file(&cpu_sysdev_class.kset.kobj,
+ &class_attr_probe.attr);
+ if (!rc)
+ rc = sysfs_create_file(&cpu_sysdev_class.kset.kobj,
+ &class_attr_release.attr);
+
+ return rc;
+}
+device_initcall(cpu_probe_release_init);
+#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
+
#else /* ... !CONFIG_HOTPLUG_CPU */
static inline void register_cpu_control(struct cpu *cpu)
{
diff --git a/drivers/block/swim3.c b/drivers/block/swim3.c
index 6380ad8..59ca2b7 100644
--- a/drivers/block/swim3.c
+++ b/drivers/block/swim3.c
@@ -200,7 +200,7 @@ struct floppy_state {
int ejected;
wait_queue_head_t wait;
int wanted;
- struct device_node* media_bay; /* NULL when not in bay */
+ struct macio_dev *mdev;
char dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)];
};
@@ -303,14 +303,13 @@ static int swim3_readbit(struct floppy_state *fs, int bit)
static void do_fd_request(struct request_queue * q)
{
int i;
- for(i=0;i<floppy_count;i++)
- {
-#ifdef CONFIG_PMAC_MEDIABAY
- if (floppy_states[i].media_bay &&
- check_media_bay(floppy_states[i].media_bay, MB_FD))
+
+ for(i=0; i<floppy_count; i++) {
+ struct floppy_state *fs = &floppy_states[i];
+ if (fs->mdev->media_bay &&
+ check_media_bay(fs->mdev->media_bay) != MB_FD)
continue;
-#endif /* CONFIG_PMAC_MEDIABAY */
- start_request(&floppy_states[i]);
+ start_request(fs);
}
}
@@ -849,10 +848,9 @@ static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
if ((cmd & 0x80) && !capable(CAP_SYS_ADMIN))
return -EPERM;
-#ifdef CONFIG_PMAC_MEDIABAY
- if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
+ if (fs->mdev->media_bay &&
+ check_media_bay(fs->mdev->media_bay) != MB_FD)
return -ENXIO;
-#endif
switch (cmd) {
case FDEJECT:
@@ -876,10 +874,9 @@ static int floppy_open(struct block_device *bdev, fmode_t mode)
int n, err = 0;
if (fs->ref_count == 0) {
-#ifdef CONFIG_PMAC_MEDIABAY
- if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
+ if (fs->mdev->media_bay &&
+ check_media_bay(fs->mdev->media_bay) != MB_FD)
return -ENXIO;
-#endif
out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2);
out_8(&sw->control_bic, 0xff);
out_8(&sw->mode, 0x95);
@@ -963,10 +960,9 @@ static int floppy_revalidate(struct gendisk *disk)
struct swim3 __iomem *sw;
int ret, n;
-#ifdef CONFIG_PMAC_MEDIABAY
- if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
+ if (fs->mdev->media_bay &&
+ check_media_bay(fs->mdev->media_bay) != MB_FD)
return -ENXIO;
-#endif
sw = fs->swim3;
grab_drive(fs, revalidating, 0);
@@ -1009,7 +1005,6 @@ static const struct block_device_operations floppy_fops = {
static int swim3_add_device(struct macio_dev *mdev, int index)
{
struct device_node *swim = mdev->ofdev.node;
- struct device_node *mediabay;
struct floppy_state *fs = &floppy_states[index];
int rc = -EBUSY;
@@ -1036,9 +1031,7 @@ static int swim3_add_device(struct macio_dev *mdev, int index)
}
dev_set_drvdata(&mdev->ofdev.dev, fs);
- mediabay = (strcasecmp(swim->parent->type, "media-bay") == 0) ?
- swim->parent : NULL;
- if (mediabay == NULL)
+ if (mdev->media_bay == NULL)
pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1);
memset(fs, 0, sizeof(*fs));
@@ -1068,7 +1061,7 @@ static int swim3_add_device(struct macio_dev *mdev, int index)
fs->secpercyl = 36;
fs->secpertrack = 18;
fs->total_secs = 2880;
- fs->media_bay = mediabay;
+ fs->mdev = mdev;
init_waitqueue_head(&fs->wait);
fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space);
@@ -1093,7 +1086,7 @@ static int swim3_add_device(struct macio_dev *mdev, int index)
init_timer(&fs->timeout);
printk(KERN_INFO "fd%d: SWIM3 floppy controller %s\n", floppy_count,
- mediabay ? "in media bay" : "");
+ mdev->media_bay ? "in media bay" : "");
return 0;
diff --git a/drivers/char/agp/uninorth-agp.c b/drivers/char/agp/uninorth-agp.c
index 703959e..d89da4a 100644
--- a/drivers/char/agp/uninorth-agp.c
+++ b/drivers/char/agp/uninorth-agp.c
@@ -144,16 +144,13 @@ static int uninorth_configure(void)
return 0;
}
-static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start,
- int type)
+static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
{
- int i, j, num_entries;
+ int i, num_entries;
void *temp;
+ u32 *gp;
int mask_type;
- temp = agp_bridge->current_size;
- num_entries = A_SIZE_32(temp)->num_entries;
-
if (type != mem->type)
return -EINVAL;
@@ -163,49 +160,12 @@ static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start,
return -EINVAL;
}
- if ((pg_start + mem->page_count) > num_entries)
- return -EINVAL;
-
- j = pg_start;
-
- while (j < (pg_start + mem->page_count)) {
- if (agp_bridge->gatt_table[j])
- return -EBUSY;
- j++;
- }
-
- for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
- agp_bridge->gatt_table[j] =
- cpu_to_le32((page_to_phys(mem->pages[i]) & 0xFFFFF000UL) | 0x1UL);
- flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])),
- (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000);
- }
- (void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]);
- mb();
-
- uninorth_tlbflush(mem);
- return 0;
-}
-
-static int u3_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
-{
- int i, num_entries;
- void *temp;
- u32 *gp;
- int mask_type;
+ if (mem->page_count == 0)
+ return 0;
temp = agp_bridge->current_size;
num_entries = A_SIZE_32(temp)->num_entries;
- if (type != mem->type)
- return -EINVAL;
-
- mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
- if (mask_type != 0) {
- /* We know nothing of memory types */
- return -EINVAL;
- }
-
if ((pg_start + mem->page_count) > num_entries)
return -EINVAL;
@@ -213,14 +173,18 @@ static int u3_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
for (i = 0; i < mem->page_count; ++i) {
if (gp[i]) {
dev_info(&agp_bridge->dev->dev,
- "u3_insert_memory: entry 0x%x occupied (%x)\n",
+ "uninorth_insert_memory: entry 0x%x occupied (%x)\n",
i, gp[i]);
return -EBUSY;
}
}
for (i = 0; i < mem->page_count; i++) {
- gp[i] = (page_to_phys(mem->pages[i]) >> PAGE_SHIFT) | 0x80000000UL;
+ if (is_u3)
+ gp[i] = (page_to_phys(mem->pages[i]) >> PAGE_SHIFT) | 0x80000000UL;
+ else
+ gp[i] = cpu_to_le32((page_to_phys(mem->pages[i]) & 0xFFFFF000UL) |
+ 0x1UL);
flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])),
(unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000);
}
@@ -230,14 +194,23 @@ static int u3_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
return 0;
}
-int u3_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
+int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
{
size_t i;
u32 *gp;
+ int mask_type;
+
+ if (type != mem->type)
+ return -EINVAL;
- if (type != 0 || mem->type != 0)
+ mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
+ if (mask_type != 0) {
/* We know nothing of memory types */
return -EINVAL;
+ }
+
+ if (mem->page_count == 0)
+ return 0;
gp = (u32 *) &agp_bridge->gatt_table[pg_start];
for (i = 0; i < mem->page_count; ++i)
@@ -536,7 +509,7 @@ const struct agp_bridge_driver uninorth_agp_driver = {
.create_gatt_table = uninorth_create_gatt_table,
.free_gatt_table = uninorth_free_gatt_table,
.insert_memory = uninorth_insert_memory,
- .remove_memory = agp_generic_remove_memory,
+ .remove_memory = uninorth_remove_memory,
.alloc_by_type = agp_generic_alloc_by_type,
.free_by_type = agp_generic_free_by_type,
.agp_alloc_page = agp_generic_alloc_page,
@@ -562,8 +535,8 @@ const struct agp_bridge_driver u3_agp_driver = {
.agp_enable = uninorth_agp_enable,
.create_gatt_table = uninorth_create_gatt_table,
.free_gatt_table = uninorth_free_gatt_table,
- .insert_memory = u3_insert_memory,
- .remove_memory = u3_remove_memory,
+ .insert_memory = uninorth_insert_memory,
+ .remove_memory = uninorth_remove_memory,
.alloc_by_type = agp_generic_alloc_by_type,
.free_by_type = agp_generic_free_by_type,
.agp_alloc_page = agp_generic_alloc_page,
diff --git a/drivers/char/hvc_console.c b/drivers/char/hvc_console.c
index a632f25..416d342 100644
--- a/drivers/char/hvc_console.c
+++ b/drivers/char/hvc_console.c
@@ -832,6 +832,7 @@ int hvc_remove(struct hvc_struct *hp)
tty_hangup(tty);
return 0;
}
+EXPORT_SYMBOL_GPL(hvc_remove);
/* Driver initialization: called as soon as someone uses hvc_alloc(). */
static int hvc_init(void)
diff --git a/drivers/ide/pmac.c b/drivers/ide/pmac.c
index 97642a7a..7a4e788 100644
--- a/drivers/ide/pmac.c
+++ b/drivers/ide/pmac.c
@@ -43,10 +43,7 @@
#include <asm/pmac_feature.h>
#include <asm/sections.h>
#include <asm/irq.h>
-
-#ifndef CONFIG_PPC64
#include <asm/mediabay.h>
-#endif
#define DRV_NAME "ide-pmac"
@@ -59,13 +56,14 @@ typedef struct pmac_ide_hwif {
int irq;
int kind;
int aapl_bus_id;
- unsigned mediabay : 1;
unsigned broken_dma : 1;
unsigned broken_dma_warn : 1;
struct device_node* node;
struct macio_dev *mdev;
u32 timings[4];
volatile u32 __iomem * *kauai_fcr;
+ ide_hwif_t *hwif;
+
/* Those fields are duplicating what is in hwif. We currently
* can't use the hwif ones because of some assumptions that are
* beeing done by the generic code about the kind of dma controller
@@ -854,6 +852,11 @@ sanitize_timings(pmac_ide_hwif_t *pmif)
pmif->timings[2] = pmif->timings[3] = value2;
}
+static int on_media_bay(pmac_ide_hwif_t *pmif)
+{
+ return pmif->mdev && pmif->mdev->media_bay != NULL;
+}
+
/* Suspend call back, should be called after the child devices
* have actually been suspended
*/
@@ -866,7 +869,7 @@ static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif)
disable_irq(pmif->irq);
/* The media bay will handle itself just fine */
- if (pmif->mediabay)
+ if (on_media_bay(pmif))
return 0;
/* Kauai has bus control FCRs directly here */
@@ -889,7 +892,7 @@ static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif)
static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif)
{
/* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
- if (!pmif->mediabay) {
+ if (!on_media_bay(pmif)) {
ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
msleep(10);
@@ -950,13 +953,11 @@ static void pmac_ide_init_dev(ide_drive_t *drive)
pmac_ide_hwif_t *pmif =
(pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
- if (pmif->mediabay) {
-#ifdef CONFIG_PMAC_MEDIABAY
- if (check_media_bay_by_base(pmif->regbase, MB_CD) == 0) {
+ if (on_media_bay(pmif)) {
+ if (check_media_bay(pmif->mdev->media_bay) == MB_CD) {
drive->dev_flags &= ~IDE_DFLAG_NOPROBE;
return;
}
-#endif
drive->dev_flags |= IDE_DFLAG_NOPROBE;
}
}
@@ -1072,26 +1073,23 @@ static int __devinit pmac_ide_setup_device(pmac_ide_hwif_t *pmif,
writel(KAUAI_FCR_UATA_MAGIC |
KAUAI_FCR_UATA_RESET_N |
KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
-
- pmif->mediabay = 0;
/* Make sure we have sane timings */
sanitize_timings(pmif);
+ /* If we are on a media bay, wait for it to settle and lock it */
+ if (pmif->mdev)
+ lock_media_bay(pmif->mdev->media_bay);
+
host = ide_host_alloc(&d, hws, 1);
- if (host == NULL)
- return -ENOMEM;
- hwif = host->ports[0];
+ if (host == NULL) {
+ rc = -ENOMEM;
+ goto bail;
+ }
+ hwif = pmif->hwif = host->ports[0];
-#ifndef CONFIG_PPC64
- /* XXX FIXME: Media bay stuff need re-organizing */
- if (np->parent && np->parent->name
- && strcasecmp(np->parent->name, "media-bay") == 0) {
-#ifdef CONFIG_PMAC_MEDIABAY
- media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq,
- hwif);
-#endif /* CONFIG_PMAC_MEDIABAY */
- pmif->mediabay = 1;
+ if (on_media_bay(pmif)) {
+ /* Fixup bus ID for media bay */
if (!bidp)
pmif->aapl_bus_id = 1;
} else if (pmif->kind == controller_ohare) {
@@ -1100,9 +1098,7 @@ static int __devinit pmac_ide_setup_device(pmac_ide_hwif_t *pmif,
* units, I keep the old way
*/
ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
- } else
-#endif
- {
+ } else {
/* This is necessary to enable IDE when net-booting */
ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
@@ -1112,17 +1108,21 @@ static int __devinit pmac_ide_setup_device(pmac_ide_hwif_t *pmif,
}
printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), "
- "bus ID %d%s, irq %d\n", model_name[pmif->kind],
- pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
- pmif->mediabay ? " (mediabay)" : "", hw->irq);
+ "bus ID %d%s, irq %d\n", model_name[pmif->kind],
+ pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
+ on_media_bay(pmif) ? " (mediabay)" : "", hw->irq);
rc = ide_host_register(host, &d, hws);
- if (rc) {
- ide_host_free(host);
- return rc;
- }
+ if (rc)
+ pmif->hwif = NULL;
- return 0;
+ if (pmif->mdev)
+ unlock_media_bay(pmif->mdev->media_bay);
+
+ bail:
+ if (rc && host)
+ ide_host_free(host);
+ return rc;
}
static void __devinit pmac_ide_init_ports(struct ide_hw *hw, unsigned long base)
@@ -1362,6 +1362,25 @@ pmac_ide_pci_resume(struct pci_dev *pdev)
return rc;
}
+#ifdef CONFIG_PMAC_MEDIABAY
+static void pmac_ide_macio_mb_event(struct macio_dev* mdev, int mb_state)
+{
+ pmac_ide_hwif_t *pmif =
+ (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
+
+ switch(mb_state) {
+ case MB_CD:
+ if (!pmif->hwif->present)
+ ide_port_scan(pmif->hwif);
+ break;
+ default:
+ if (pmif->hwif->present)
+ ide_port_unregister_devices(pmif->hwif);
+ }
+}
+#endif /* CONFIG_PMAC_MEDIABAY */
+
+
static struct of_device_id pmac_ide_macio_match[] =
{
{
@@ -1386,6 +1405,9 @@ static struct macio_driver pmac_ide_macio_driver =
.probe = pmac_ide_macio_attach,
.suspend = pmac_ide_macio_suspend,
.resume = pmac_ide_macio_resume,
+#ifdef CONFIG_PMAC_MEDIABAY
+ .mediabay_event = pmac_ide_macio_mb_event,
+#endif
};
static const struct pci_device_id pmac_ide_pci_match[] = {
diff --git a/drivers/macintosh/macio_asic.c b/drivers/macintosh/macio_asic.c
index 588a5b0..26a303a 100644
--- a/drivers/macintosh/macio_asic.c
+++ b/drivers/macintosh/macio_asic.c
@@ -379,6 +379,11 @@ static struct macio_dev * macio_add_one_device(struct macio_chip *chip,
dev->ofdev.dev.parent = parent;
dev->ofdev.dev.bus = &macio_bus_type;
dev->ofdev.dev.release = macio_release_dev;
+ dev->ofdev.dev.dma_parms = &dev->dma_parms;
+
+ /* Standard DMA paremeters */
+ dma_set_max_seg_size(&dev->ofdev.dev, 65536);
+ dma_set_seg_boundary(&dev->ofdev.dev, 0xffffffff);
#ifdef CONFIG_PCI
/* Set the DMA ops to the ones from the PCI device, this could be
@@ -538,6 +543,42 @@ void macio_unregister_driver(struct macio_driver *drv)
driver_unregister(&drv->driver);
}
+/* Managed MacIO resources */
+struct macio_devres {
+ u32 res_mask;
+};
+
+static void maciom_release(struct device *gendev, void *res)
+{
+ struct macio_dev *dev = to_macio_device(gendev);
+ struct macio_devres *dr = res;
+ int i, max;
+
+ max = min(dev->n_resources, 32);
+ for (i = 0; i < max; i++) {
+ if (dr->res_mask & (1 << i))
+ macio_release_resource(dev, i);
+ }
+}
+
+int macio_enable_devres(struct macio_dev *dev)
+{
+ struct macio_devres *dr;
+
+ dr = devres_find(&dev->ofdev.dev, maciom_release, NULL, NULL);
+ if (!dr) {
+ dr = devres_alloc(maciom_release, sizeof(*dr), GFP_KERNEL);
+ if (!dr)
+ return -ENOMEM;
+ }
+ return devres_get(&dev->ofdev.dev, dr, NULL, NULL) != NULL;
+}
+
+static struct macio_devres * find_macio_dr(struct macio_dev *dev)
+{
+ return devres_find(&dev->ofdev.dev, maciom_release, NULL, NULL);
+}
+
/**
* macio_request_resource - Request an MMIO resource
* @dev: pointer to the device holding the resource
@@ -555,6 +596,8 @@ void macio_unregister_driver(struct macio_driver *drv)
int macio_request_resource(struct macio_dev *dev, int resource_no,
const char *name)
{
+ struct macio_devres *dr = find_macio_dr(dev);
+
if (macio_resource_len(dev, resource_no) == 0)
return 0;
@@ -562,6 +605,9 @@ int macio_request_resource(struct macio_dev *dev, int resource_no,
macio_resource_len(dev, resource_no),
name))
goto err_out;
+
+ if (dr && resource_no < 32)
+ dr->res_mask |= 1 << resource_no;
return 0;
@@ -582,10 +628,14 @@ err_out:
*/
void macio_release_resource(struct macio_dev *dev, int resource_no)
{
+ struct macio_devres *dr = find_macio_dr(dev);
+
if (macio_resource_len(dev, resource_no) == 0)
return;
release_mem_region(macio_resource_start(dev, resource_no),
macio_resource_len(dev, resource_no));
+ if (dr && resource_no < 32)
+ dr->res_mask &= ~(1 << resource_no);
}
/**
@@ -744,3 +794,5 @@ EXPORT_SYMBOL(macio_request_resource);
EXPORT_SYMBOL(macio_release_resource);
EXPORT_SYMBOL(macio_request_resources);
EXPORT_SYMBOL(macio_release_resources);
+EXPORT_SYMBOL(macio_enable_devres);
+
diff --git a/drivers/macintosh/mediabay.c b/drivers/macintosh/mediabay.c
index 029ad8c..08002b8 100644
--- a/drivers/macintosh/mediabay.c
+++ b/drivers/macintosh/mediabay.c
@@ -33,15 +33,6 @@
#include <linux/adb.h>
#include <linux/pmu.h>
-
-#define MB_DEBUG
-
-#ifdef MB_DEBUG
-#define MBDBG(fmt, arg...) printk(KERN_INFO fmt , ## arg)
-#else
-#define MBDBG(fmt, arg...) do { } while (0)
-#endif
-
#define MB_FCR32(bay, r) ((bay)->base + ((r) >> 2))
#define MB_FCR8(bay, r) (((volatile u8 __iomem *)((bay)->base)) + (r))
@@ -76,28 +67,14 @@ struct media_bay_info {
int index;
int cached_gpio;
int sleeping;
+ int user_lock;
struct mutex lock;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- ide_hwif_t *cd_port;
- void __iomem *cd_base;
- int cd_irq;
- int cd_retry;
-#endif
-#if defined(CONFIG_BLK_DEV_IDE_PMAC)
- int cd_index;
-#endif
};
#define MAX_BAYS 2
static struct media_bay_info media_bays[MAX_BAYS];
-int media_bay_count = 0;
-
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
-/* check the busy bit in the media-bay ide interface
- (assumes the media-bay contains an ide device) */
-#define MB_IDE_READY(i) ((readb(media_bays[i].cd_base + 0x70) & 0x80) == 0)
-#endif
+static int media_bay_count = 0;
/*
* Wait that number of ms between each step in normal polling mode
@@ -130,21 +107,11 @@ int media_bay_count = 0;
/*
* Wait this many ticks after an IDE device (e.g. CD-ROM) is inserted
- * (or until the device is ready) before waiting for busy bit to disappear
+ * (or until the device is ready) before calling into the driver
*/
#define MB_IDE_WAIT 1000
/*
- * Timeout waiting for busy bit of an IDE device to go down
- */
-#define MB_IDE_TIMEOUT 5000
-
-/*
- * Max retries of the full power up/down sequence for an IDE device
- */
-#define MAX_CD_RETRIES 3
-
-/*
* States of a media bay
*/
enum {
@@ -153,7 +120,6 @@ enum {
mb_enabling_bay, /* enable bits set, waiting MB_RESET_DELAY */
mb_resetting, /* reset bit unset, waiting MB_SETUP_DELAY */
mb_ide_resetting, /* IDE reset bit unser, waiting MB_IDE_WAIT */
- mb_ide_waiting, /* Waiting for BUSY bit to go away until MB_IDE_TIMEOUT */
mb_up, /* Media bay full */
mb_powering_down /* Powering down (avoid too fast down/up) */
};
@@ -373,12 +339,12 @@ static inline void set_mb_power(struct media_bay_info* bay, int onoff)
if (onoff) {
bay->ops->power(bay, 1);
bay->state = mb_powering_up;
- MBDBG("mediabay%d: powering up\n", bay->index);
+ pr_debug("mediabay%d: powering up\n", bay->index);
} else {
/* Make sure everything is powered down & disabled */
bay->ops->power(bay, 0);
bay->state = mb_powering_down;
- MBDBG("mediabay%d: powering down\n", bay->index);
+ pr_debug("mediabay%d: powering down\n", bay->index);
}
bay->timer = msecs_to_jiffies(MB_POWER_DELAY);
}
@@ -387,107 +353,118 @@ static void poll_media_bay(struct media_bay_info* bay)
{
int id = bay->ops->content(bay);
- if (id == bay->last_value) {
- if (id != bay->content_id) {
- bay->value_count += msecs_to_jiffies(MB_POLL_DELAY);
- if (bay->value_count >= msecs_to_jiffies(MB_STABLE_DELAY)) {
- /* If the device type changes without going thru
- * "MB_NO", we force a pass by "MB_NO" to make sure
- * things are properly reset
- */
- if ((id != MB_NO) && (bay->content_id != MB_NO)) {
- id = MB_NO;
- MBDBG("mediabay%d: forcing MB_NO\n", bay->index);
- }
- MBDBG("mediabay%d: switching to %d\n", bay->index, id);
- set_mb_power(bay, id != MB_NO);
- bay->content_id = id;
- if (id == MB_NO) {
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- bay->cd_retry = 0;
-#endif
- printk(KERN_INFO "media bay %d is empty\n", bay->index);
- }
- }
- }
- } else {
+ static char *mb_content_types[] = {
+ "a floppy drive",
+ "a floppy drive",
+ "an unsuported audio device",
+ "an ATA device",
+ "an unsupported PCI device",
+ "an unknown device",
+ };
+
+ if (id != bay->last_value) {
bay->last_value = id;
bay->value_count = 0;
+ return;
+ }
+ if (id == bay->content_id)
+ return;
+
+ bay->value_count += msecs_to_jiffies(MB_POLL_DELAY);
+ if (bay->value_count >= msecs_to_jiffies(MB_STABLE_DELAY)) {
+ /* If the device type changes without going thru
+ * "MB_NO", we force a pass by "MB_NO" to make sure
+ * things are properly reset
+ */
+ if ((id != MB_NO) && (bay->content_id != MB_NO)) {
+ id = MB_NO;
+ pr_debug("mediabay%d: forcing MB_NO\n", bay->index);
+ }
+ pr_debug("mediabay%d: switching to %d\n", bay->index, id);
+ set_mb_power(bay, id != MB_NO);
+ bay->content_id = id;
+ if (id >= MB_NO || id < 0)
+ printk(KERN_INFO "mediabay%d: Bay is now empty\n", bay->index);
+ else
+ printk(KERN_INFO "mediabay%d: Bay contains %s\n",
+ bay->index, mb_content_types[id]);
}
}
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
-int check_media_bay(struct device_node *which_bay, int what)
+int check_media_bay(struct macio_dev *baydev)
{
- int i;
+ struct media_bay_info* bay;
+ int id;
- for (i=0; i<media_bay_count; i++)
- if (media_bays[i].mdev && which_bay == media_bays[i].mdev->ofdev.node) {
- if ((what == media_bays[i].content_id) && media_bays[i].state == mb_up)
- return 0;
- media_bays[i].cd_index = -1;
- return -EINVAL;
- }
- return -ENODEV;
+ if (baydev == NULL)
+ return MB_NO;
+
+ /* This returns an instant snapshot, not locking, sine
+ * we may be called with the bay lock held. The resulting
+ * fuzzyness of the result if called at the wrong time is
+ * not actually a huge deal
+ */
+ bay = macio_get_drvdata(baydev);
+ if (bay == NULL)
+ return MB_NO;
+ id = bay->content_id;
+ if (bay->state != mb_up)
+ return MB_NO;
+ if (id == MB_FD1)
+ return MB_FD;
+ return id;
}
-EXPORT_SYMBOL(check_media_bay);
+EXPORT_SYMBOL_GPL(check_media_bay);
-int check_media_bay_by_base(unsigned long base, int what)
+void lock_media_bay(struct macio_dev *baydev)
{
- int i;
-
- for (i=0; i<media_bay_count; i++)
- if (media_bays[i].mdev && base == (unsigned long) media_bays[i].cd_base) {
- if ((what == media_bays[i].content_id) && media_bays[i].state == mb_up)
- return 0;
- media_bays[i].cd_index = -1;
- return -EINVAL;
- }
+ struct media_bay_info* bay;
- return -ENODEV;
+ if (baydev == NULL)
+ return;
+ bay = macio_get_drvdata(baydev);
+ if (bay == NULL)
+ return;
+ mutex_lock(&bay->lock);
+ bay->user_lock = 1;
}
-EXPORT_SYMBOL_GPL(check_media_bay_by_base);
+EXPORT_SYMBOL_GPL(lock_media_bay);
-int media_bay_set_ide_infos(struct device_node* which_bay, unsigned long base,
- int irq, ide_hwif_t *hwif)
+void unlock_media_bay(struct macio_dev *baydev)
{
- int i;
+ struct media_bay_info* bay;
- for (i=0; i<media_bay_count; i++) {
- struct media_bay_info* bay = &media_bays[i];
-
- if (bay->mdev && which_bay == bay->mdev->ofdev.node) {
- int timeout = 5000, index = hwif->index;
-
- mutex_lock(&bay->lock);
-
- bay->cd_port = hwif;
- bay->cd_base = (void __iomem *) base;
- bay->cd_irq = irq;
-
- if ((MB_CD != bay->content_id) || bay->state != mb_up) {
- mutex_unlock(&bay->lock);
- return 0;
- }
- printk(KERN_DEBUG "Registered ide%d for media bay %d\n", index, i);
- do {
- if (MB_IDE_READY(i)) {
- bay->cd_index = index;
- mutex_unlock(&bay->lock);
- return 0;
- }
- mdelay(1);
- } while(--timeout);
- printk(KERN_DEBUG "Timeount waiting IDE in bay %d\n", i);
- mutex_unlock(&bay->lock);
- return -ENODEV;
- }
+ if (baydev == NULL)
+ return;
+ bay = macio_get_drvdata(baydev);
+ if (bay == NULL)
+ return;
+ if (bay->user_lock) {
+ bay->user_lock = 0;
+ mutex_unlock(&bay->lock);
}
+}
+EXPORT_SYMBOL_GPL(unlock_media_bay);
- return -ENODEV;
+static int mb_broadcast_hotplug(struct device *dev, void *data)
+{
+ struct media_bay_info* bay = data;
+ struct macio_dev *mdev;
+ struct macio_driver *drv;
+ int state;
+
+ if (dev->bus != &macio_bus_type)
+ return 0;
+
+ state = bay->state == mb_up ? bay->content_id : MB_NO;
+ if (state == MB_FD1)
+ state = MB_FD;
+ mdev = to_macio_device(dev);
+ drv = to_macio_driver(dev->driver);
+ if (dev->driver && drv->mediabay_event)
+ drv->mediabay_event(mdev, state);
+ return 0;
}
-EXPORT_SYMBOL_GPL(media_bay_set_ide_infos);
-#endif /* CONFIG_BLK_DEV_IDE_PMAC */
static void media_bay_step(int i)
{
@@ -497,8 +474,8 @@ static void media_bay_step(int i)
if (bay->state != mb_powering_down)
poll_media_bay(bay);
- /* If timer expired or polling IDE busy, run state machine */
- if ((bay->state != mb_ide_waiting) && (bay->timer != 0)) {
+ /* If timer expired run state machine */
+ if (bay->timer != 0) {
bay->timer -= msecs_to_jiffies(MB_POLL_DELAY);
if (bay->timer > 0)
return;
@@ -508,100 +485,50 @@ static void media_bay_step(int i)
switch(bay->state) {
case mb_powering_up:
if (bay->ops->setup_bus(bay, bay->last_value) < 0) {
- MBDBG("mediabay%d: device not supported (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: device not supported (kind:%d)\n",
+ i, bay->content_id);
set_mb_power(bay, 0);
break;
}
bay->timer = msecs_to_jiffies(MB_RESET_DELAY);
bay->state = mb_enabling_bay;
- MBDBG("mediabay%d: enabling (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: enabling (kind:%d)\n", i, bay->content_id);
break;
case mb_enabling_bay:
bay->ops->un_reset(bay);
bay->timer = msecs_to_jiffies(MB_SETUP_DELAY);
bay->state = mb_resetting;
- MBDBG("mediabay%d: waiting reset (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: releasing bay reset (kind:%d)\n",
+ i, bay->content_id);
break;
case mb_resetting:
if (bay->content_id != MB_CD) {
- MBDBG("mediabay%d: bay is up (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: bay is up (kind:%d)\n", i,
+ bay->content_id);
bay->state = mb_up;
+ device_for_each_child(&bay->mdev->ofdev.dev,
+ bay, mb_broadcast_hotplug);
break;
}
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- MBDBG("mediabay%d: waiting IDE reset (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: releasing ATA reset (kind:%d)\n",
+ i, bay->content_id);
bay->ops->un_reset_ide(bay);
bay->timer = msecs_to_jiffies(MB_IDE_WAIT);
bay->state = mb_ide_resetting;
-#else
- printk(KERN_DEBUG "media-bay %d is ide (not compiled in kernel)\n", i);
- set_mb_power(bay, 0);
-#endif /* CONFIG_BLK_DEV_IDE_PMAC */
break;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
+
case mb_ide_resetting:
- bay->timer = msecs_to_jiffies(MB_IDE_TIMEOUT);
- bay->state = mb_ide_waiting;
- MBDBG("mediabay%d: waiting IDE ready (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: bay is up (kind:%d)\n", i, bay->content_id);
+ bay->state = mb_up;
+ device_for_each_child(&bay->mdev->ofdev.dev,
+ bay, mb_broadcast_hotplug);
break;
- case mb_ide_waiting:
- if (bay->cd_base == NULL) {
- bay->timer = 0;
- bay->state = mb_up;
- MBDBG("mediabay%d: up before IDE init\n", i);
- break;
- } else if (MB_IDE_READY(i)) {
- bay->timer = 0;
- bay->state = mb_up;
- if (bay->cd_index < 0) {
- printk("mediabay %d, registering IDE...\n", i);
- pmu_suspend();
- ide_port_scan(bay->cd_port);
- if (bay->cd_port->present)
- bay->cd_index = bay->cd_port->index;
- pmu_resume();
- }
- if (bay->cd_index == -1) {
- /* We eventually do a retry */
- bay->cd_retry++;
- printk("IDE register error\n");
- set_mb_power(bay, 0);
- } else {
- printk(KERN_DEBUG "media-bay %d is ide%d\n", i, bay->cd_index);
- MBDBG("mediabay %d IDE ready\n", i);
- }
- break;
- } else if (bay->timer > 0)
- bay->timer -= msecs_to_jiffies(MB_POLL_DELAY);
- if (bay->timer <= 0) {
- printk("\nIDE Timeout in bay %d !, IDE state is: 0x%02x\n",
- i, readb(bay->cd_base + 0x70));
- MBDBG("mediabay%d: nIDE Timeout !\n", i);
- set_mb_power(bay, 0);
- bay->timer = 0;
- }
- break;
-#endif /* CONFIG_BLK_DEV_IDE_PMAC */
+
case mb_powering_down:
bay->state = mb_empty;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- if (bay->cd_index >= 0) {
- printk(KERN_DEBUG "Unregistering mb %d ide, index:%d\n", i,
- bay->cd_index);
- ide_port_unregister_devices(bay->cd_port);
- bay->cd_index = -1;
- }
- if (bay->cd_retry) {
- if (bay->cd_retry > MAX_CD_RETRIES) {
- /* Should add an error sound (sort of beep in dmasound) */
- printk("\nmedia-bay %d, IDE device badly inserted or unrecognised\n", i);
- } else {
- /* Force a new power down/up sequence */
- bay->content_id = MB_NO;
- }
- }
-#endif /* CONFIG_BLK_DEV_IDE_PMAC */
- MBDBG("mediabay%d: end of power down\n", i);
+ device_for_each_child(&bay->mdev->ofdev.dev,
+ bay, mb_broadcast_hotplug);
+ pr_debug("mediabay%d: end of power down\n", i);
break;
}
}
@@ -676,11 +603,6 @@ static int __devinit media_bay_attach(struct macio_dev *mdev, const struct of_de
bay->last_value = bay->ops->content(bay);
bay->value_count = msecs_to_jiffies(MB_STABLE_DELAY);
bay->state = mb_empty;
- do {
- msleep(MB_POLL_DELAY);
- media_bay_step(i);
- } while((bay->state != mb_empty) &&
- (bay->state != mb_up));
/* Mark us ready by filling our mdev data */
macio_set_drvdata(mdev, bay);
@@ -725,7 +647,7 @@ static int media_bay_resume(struct macio_dev *mdev)
set_mb_power(bay, 0);
msleep(MB_POWER_DELAY);
if (bay->ops->content(bay) != bay->content_id) {
- printk("mediabay%d: content changed during sleep...\n", bay->index);
+ printk("mediabay%d: Content changed during sleep...\n", bay->index);
mutex_unlock(&bay->lock);
return 0;
}
@@ -733,9 +655,6 @@ static int media_bay_resume(struct macio_dev *mdev)
bay->last_value = bay->content_id;
bay->value_count = msecs_to_jiffies(MB_STABLE_DELAY);
bay->timer = msecs_to_jiffies(MB_POWER_DELAY);
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- bay->cd_retry = 0;
-#endif
do {
msleep(MB_POLL_DELAY);
media_bay_step(bay->index);
@@ -823,9 +742,6 @@ static int __init media_bay_init(void)
for (i=0; i<MAX_BAYS; i++) {
memset((char *)&media_bays[i], 0, sizeof(struct media_bay_info));
media_bays[i].content_id = -1;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- media_bays[i].cd_index = -1;
-#endif
}
if (!machine_is(powermac))
return 0;
diff --git a/drivers/macintosh/nvram.c b/drivers/macintosh/nvram.c
index b195d75..c876349 100644
--- a/drivers/macintosh/nvram.c
+++ b/drivers/macintosh/nvram.c
@@ -13,7 +13,6 @@
#include <linux/fcntl.h>
#include <linux/nvram.h>
#include <linux/init.h>
-#include <linux/smp_lock.h>
#include <asm/uaccess.h>
#include <asm/nvram.h>
@@ -21,7 +20,6 @@
static loff_t nvram_llseek(struct file *file, loff_t offset, int origin)
{
- lock_kernel();
switch (origin) {
case 1:
offset += file->f_pos;
@@ -30,12 +28,10 @@ static loff_t nvram_llseek(struct file *file, loff_t offset, int origin)
offset += NVRAM_SIZE;
break;
}
- if (offset < 0) {
- unlock_kernel();
+ if (offset < 0)
return -EINVAL;
- }
+
file->f_pos = offset;
- unlock_kernel();
return file->f_pos;
}
@@ -76,8 +72,7 @@ static ssize_t write_nvram(struct file *file, const char __user *buf,
return p - buf;
}
-static int nvram_ioctl(struct inode *inode, struct file *file,
- unsigned int cmd, unsigned long arg)
+static long nvram_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
switch(cmd) {
case PMAC_NVRAM_GET_OFFSET:
diff --git a/drivers/macintosh/therm_adt746x.c b/drivers/macintosh/therm_adt746x.c
index 556f0fe..5ff47ba 100644
--- a/drivers/macintosh/therm_adt746x.c
+++ b/drivers/macintosh/therm_adt746x.c
@@ -79,6 +79,7 @@ struct thermostat {
u8 limits[3];
int last_speed[2];
int last_var[2];
+ int pwm_inv[2];
};
static enum {ADT7460, ADT7467} therm_type;
@@ -229,19 +230,23 @@ static void write_fan_speed(struct thermostat *th, int speed, int fan)
if (speed >= 0) {
manual = read_reg(th, MANUAL_MODE[fan]);
+ manual &= ~INVERT_MASK;
write_reg(th, MANUAL_MODE[fan],
- (manual|MANUAL_MASK) & (~INVERT_MASK));
+ manual | MANUAL_MASK | th->pwm_inv[fan]);
write_reg(th, FAN_SPD_SET[fan], speed);
} else {
/* back to automatic */
if(therm_type == ADT7460) {
manual = read_reg(th,
MANUAL_MODE[fan]) & (~MANUAL_MASK);
-
+ manual &= ~INVERT_MASK;
+ manual |= th->pwm_inv[fan];
write_reg(th,
MANUAL_MODE[fan], manual|REM_CONTROL[fan]);
} else {
manual = read_reg(th, MANUAL_MODE[fan]);
+ manual &= ~INVERT_MASK;
+ manual |= th->pwm_inv[fan];
write_reg(th, MANUAL_MODE[fan], manual&(~AUTO_MASK));
}
}
@@ -387,7 +392,7 @@ static int probe_thermostat(struct i2c_client *client,
i2c_set_clientdata(client, th);
th->clt = client;
- rc = read_reg(th, 0);
+ rc = read_reg(th, CONFIG_REG);
if (rc < 0) {
dev_err(&client->dev, "Thermostat failed to read config!\n");
kfree(th);
@@ -418,6 +423,10 @@ static int probe_thermostat(struct i2c_client *client,
thermostat = th;
+ /* record invert bit status because fw can corrupt it after suspend */
+ th->pwm_inv[0] = read_reg(th, MANUAL_MODE[0]) & INVERT_MASK;
+ th->pwm_inv[1] = read_reg(th, MANUAL_MODE[1]) & INVERT_MASK;
+
/* be sure to really write fan speed the first time */
th->last_speed[0] = -2;
th->last_speed[1] = -2;
diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c
index 6f308a4..db379c3 100644
--- a/drivers/macintosh/via-pmu.c
+++ b/drivers/macintosh/via-pmu.c
@@ -36,6 +36,7 @@
#include <linux/spinlock.h>
#include <linux/pm.h>
#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/device.h>
@@ -186,17 +187,11 @@ static int init_pmu(void);
static void pmu_start(void);
static irqreturn_t via_pmu_interrupt(int irq, void *arg);
static irqreturn_t gpio1_interrupt(int irq, void *arg);
-static int proc_get_info(char *page, char **start, off_t off,
- int count, int *eof, void *data);
-static int proc_get_irqstats(char *page, char **start, off_t off,
- int count, int *eof, void *data);
+static const struct file_operations pmu_info_proc_fops;
+static const struct file_operations pmu_irqstats_proc_fops;
static void pmu_pass_intr(unsigned char *data, int len);
-static int proc_get_batt(char *page, char **start, off_t off,
- int count, int *eof, void *data);
-static int proc_read_options(char *page, char **start, off_t off,
- int count, int *eof, void *data);
-static int proc_write_options(struct file *file, const char __user *buffer,
- unsigned long count, void *data);
+static const struct file_operations pmu_battery_proc_fops;
+static const struct file_operations pmu_options_proc_fops;
#ifdef CONFIG_ADB
struct adb_driver via_pmu_driver = {
@@ -507,19 +502,15 @@ static int __init via_pmu_dev_init(void)
for (i=0; i<pmu_battery_count; i++) {
char title[16];
sprintf(title, "battery_%ld", i);
- proc_pmu_batt[i] = create_proc_read_entry(title, 0, proc_pmu_root,
- proc_get_batt, (void *)i);
+ proc_pmu_batt[i] = proc_create_data(title, 0, proc_pmu_root,
+ &pmu_battery_proc_fops, (void *)i);
}
- proc_pmu_info = create_proc_read_entry("info", 0, proc_pmu_root,
- proc_get_info, NULL);
- proc_pmu_irqstats = create_proc_read_entry("interrupts", 0, proc_pmu_root,
- proc_get_irqstats, NULL);
- proc_pmu_options = create_proc_entry("options", 0600, proc_pmu_root);
- if (proc_pmu_options) {
- proc_pmu_options->read_proc = proc_read_options;
- proc_pmu_options->write_proc = proc_write_options;
- }
+ proc_pmu_info = proc_create("info", 0, proc_pmu_root, &pmu_info_proc_fops);
+ proc_pmu_irqstats = proc_create("interrupts", 0, proc_pmu_root,
+ &pmu_irqstats_proc_fops);
+ proc_pmu_options = proc_create("options", 0600, proc_pmu_root,
+ &pmu_options_proc_fops);
}
return 0;
}
@@ -799,27 +790,33 @@ query_battery_state(void)
2, PMU_SMART_BATTERY_STATE, pmu_cur_battery+1);
}
-static int
-proc_get_info(char *page, char **start, off_t off,
- int count, int *eof, void *data)
+static int pmu_info_proc_show(struct seq_file *m, void *v)
{
- char* p = page;
-
- p += sprintf(p, "PMU driver version : %d\n", PMU_DRIVER_VERSION);
- p += sprintf(p, "PMU firmware version : %02x\n", pmu_version);
- p += sprintf(p, "AC Power : %d\n",
+ seq_printf(m, "PMU driver version : %d\n", PMU_DRIVER_VERSION);
+ seq_printf(m, "PMU firmware version : %02x\n", pmu_version);
+ seq_printf(m, "AC Power : %d\n",
((pmu_power_flags & PMU_PWR_AC_PRESENT) != 0) || pmu_battery_count == 0);
- p += sprintf(p, "Battery count : %d\n", pmu_battery_count);
+ seq_printf(m, "Battery count : %d\n", pmu_battery_count);
+
+ return 0;
+}
- return p - page;
+static int pmu_info_proc_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, pmu_info_proc_show, NULL);
}
-static int
-proc_get_irqstats(char *page, char **start, off_t off,
- int count, int *eof, void *data)
+static const struct file_operations pmu_info_proc_fops = {
+ .owner = THIS_MODULE,
+ .open = pmu_info_proc_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static int pmu_irqstats_proc_show(struct seq_file *m, void *v)
{
int i;
- char* p = page;
static const char *irq_names[] = {
"Total CB1 triggered events",
"Total GPIO1 triggered events",
@@ -835,60 +832,76 @@ proc_get_irqstats(char *page, char **start, off_t off,
};
for (i=0; i<11; i++) {
- p += sprintf(p, " %2u: %10u (%s)\n",
+ seq_printf(m, " %2u: %10u (%s)\n",
i, pmu_irq_stats[i], irq_names[i]);
}
- return p - page;
+ return 0;
}
-static int
-proc_get_batt(char *page, char **start, off_t off,
- int count, int *eof, void *data)
+static int pmu_irqstats_proc_open(struct inode *inode, struct file *file)
{
- long batnum = (long)data;
- char *p = page;
+ return single_open(file, pmu_irqstats_proc_show, NULL);
+}
+
+static const struct file_operations pmu_irqstats_proc_fops = {
+ .owner = THIS_MODULE,
+ .open = pmu_irqstats_proc_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static int pmu_battery_proc_show(struct seq_file *m, void *v)
+{
+ long batnum = (long)m->private;
- p += sprintf(p, "\n");
- p += sprintf(p, "flags : %08x\n",
- pmu_batteries[batnum].flags);
- p += sprintf(p, "charge : %d\n",
- pmu_batteries[batnum].charge);
- p += sprintf(p, "max_charge : %d\n",
- pmu_batteries[batnum].max_charge);
- p += sprintf(p, "current : %d\n",
- pmu_batteries[batnum].amperage);
- p += sprintf(p, "voltage : %d\n",
- pmu_batteries[batnum].voltage);
- p += sprintf(p, "time rem. : %d\n",
- pmu_batteries[batnum].time_remaining);
-
- return p - page;
+ seq_putc(m, '\n');
+ seq_printf(m, "flags : %08x\n", pmu_batteries[batnum].flags);
+ seq_printf(m, "charge : %d\n", pmu_batteries[batnum].charge);
+ seq_printf(m, "max_charge : %d\n", pmu_batteries[batnum].max_charge);
+ seq_printf(m, "current : %d\n", pmu_batteries[batnum].amperage);
+ seq_printf(m, "voltage : %d\n", pmu_batteries[batnum].voltage);
+ seq_printf(m, "time rem. : %d\n", pmu_batteries[batnum].time_remaining);
+ return 0;
}
-static int
-proc_read_options(char *page, char **start, off_t off,
- int count, int *eof, void *data)
+static int pmu_battery_proc_open(struct inode *inode, struct file *file)
{
- char *p = page;
+ return single_open(file, pmu_battery_proc_show, PDE(inode)->data);
+}
+static const struct file_operations pmu_battery_proc_fops = {
+ .owner = THIS_MODULE,
+ .open = pmu_battery_proc_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static int pmu_options_proc_show(struct seq_file *m, void *v)
+{
#if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC32)
if (pmu_kind == PMU_KEYLARGO_BASED &&
pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,0,-1) >= 0)
- p += sprintf(p, "lid_wakeup=%d\n", option_lid_wakeup);
+ seq_printf(m, "lid_wakeup=%d\n", option_lid_wakeup);
#endif
if (pmu_kind == PMU_KEYLARGO_BASED)
- p += sprintf(p, "server_mode=%d\n", option_server_mode);
+ seq_printf(m, "server_mode=%d\n", option_server_mode);
- return p - page;
+ return 0;
}
-
-static int
-proc_write_options(struct file *file, const char __user *buffer,
- unsigned long count, void *data)
+
+static int pmu_options_proc_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, pmu_options_proc_show, NULL);
+}
+
+static ssize_t pmu_options_proc_write(struct file *file,
+ const char __user *buffer, size_t count, loff_t *pos)
{
char tmp[33];
char *label, *val;
- unsigned long fcount = count;
+ size_t fcount = count;
if (!count)
return -EINVAL;
@@ -927,6 +940,15 @@ proc_write_options(struct file *file, const char __user *buffer,
return fcount;
}
+static const struct file_operations pmu_options_proc_fops = {
+ .owner = THIS_MODULE,
+ .open = pmu_options_proc_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = pmu_options_proc_write,
+};
+
#ifdef CONFIG_ADB
/* Send an ADB command */
static int pmu_send_request(struct adb_request *req, int sync)
diff --git a/drivers/macintosh/windfarm_smu_controls.c b/drivers/macintosh/windfarm_smu_controls.c
index 961fa0e..6c68b9e 100644
--- a/drivers/macintosh/windfarm_smu_controls.c
+++ b/drivers/macintosh/windfarm_smu_controls.c
@@ -202,6 +202,8 @@ static struct smu_fan_control *smu_fan_create(struct device_node *node,
fct->ctrl.name = "cpu-front-fan-1";
else if (!strcmp(l, "CPU A PUMP"))
fct->ctrl.name = "cpu-pump-0";
+ else if (!strcmp(l, "CPU B PUMP"))
+ fct->ctrl.name = "cpu-pump-1";
else if (!strcmp(l, "Slots Fan") || !strcmp(l, "Slots fan") ||
!strcmp(l, "EXPANSION SLOTS INTAKE"))
fct->ctrl.name = "slots-fan";
diff --git a/drivers/mmc/host/of_mmc_spi.c b/drivers/mmc/host/of_mmc_spi.c
index 0c44d56..0c7a63c 100644
--- a/drivers/mmc/host/of_mmc_spi.c
+++ b/drivers/mmc/host/of_mmc_spi.c
@@ -22,6 +22,8 @@
#include <linux/mmc/core.h>
#include <linux/mmc/host.h>
+MODULE_LICENSE("GPL");
+
enum {
CD_GPIO = 0,
WP_GPIO,
diff --git a/drivers/net/ehea/ehea_hcall.h b/drivers/net/ehea/ehea_hcall.h
deleted file mode 100644
index 8e7d1c3..0000000
--- a/drivers/net/ehea/ehea_hcall.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * linux/drivers/net/ehea/ehea_hcall.h
- *
- * eHEA ethernet device driver for IBM eServer System p
- *
- * (C) Copyright IBM Corp. 2006
- *
- * Authors:
- * Christoph Raisch <raisch@de.ibm.com>
- * Jan-Bernd Themann <themann@de.ibm.com>
- * Thomas Klein <tklein@de.ibm.com>
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __EHEA_HCALL_H__
-#define __EHEA_HCALL_H__
-
-/**
- * This file contains HCALL defines that are to be included in the appropriate
- * kernel files later
- */
-
-#define H_ALLOC_HEA_RESOURCE 0x278
-#define H_MODIFY_HEA_QP 0x250
-#define H_QUERY_HEA_QP 0x254
-#define H_QUERY_HEA 0x258
-#define H_QUERY_HEA_PORT 0x25C
-#define H_MODIFY_HEA_PORT 0x260
-#define H_REG_BCMC 0x264
-#define H_DEREG_BCMC 0x268
-#define H_REGISTER_HEA_RPAGES 0x26C
-#define H_DISABLE_AND_GET_HEA 0x270
-#define H_GET_HEA_INFO 0x274
-#define H_ADD_CONN 0x284
-#define H_DEL_CONN 0x288
-
-#endif /* __EHEA_HCALL_H__ */
diff --git a/drivers/net/ehea/ehea_phyp.h b/drivers/net/ehea/ehea_phyp.h
index f3628c8..2f8174c 100644
--- a/drivers/net/ehea/ehea_phyp.h
+++ b/drivers/net/ehea/ehea_phyp.h
@@ -33,7 +33,6 @@
#include <asm/hvcall.h>
#include "ehea.h"
#include "ehea_hw.h"
-#include "ehea_hcall.h"
/* Some abbreviations used here:
*
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index 298de0f..d58ade1 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -65,47 +65,322 @@ static int of_platform_device_remove(struct device *dev)
return 0;
}
-static int of_platform_device_suspend(struct device *dev, pm_message_t state)
+static void of_platform_device_shutdown(struct device *dev)
{
struct of_device *of_dev = to_of_device(dev);
struct of_platform_driver *drv = to_of_platform_driver(dev->driver);
- int error = 0;
- if (dev->driver && drv->suspend)
- error = drv->suspend(of_dev, state);
- return error;
+ if (dev->driver && drv->shutdown)
+ drv->shutdown(of_dev);
}
-static int of_platform_device_resume(struct device * dev)
+#ifdef CONFIG_PM_SLEEP
+
+static int of_platform_legacy_suspend(struct device *dev, pm_message_t mesg)
{
struct of_device *of_dev = to_of_device(dev);
struct of_platform_driver *drv = to_of_platform_driver(dev->driver);
- int error = 0;
+ int ret = 0;
- if (dev->driver && drv->resume)
- error = drv->resume(of_dev);
- return error;
+ if (dev->driver && drv->suspend)
+ ret = drv->suspend(of_dev, mesg);
+ return ret;
}
-static void of_platform_device_shutdown(struct device *dev)
+static int of_platform_legacy_resume(struct device *dev)
{
struct of_device *of_dev = to_of_device(dev);
struct of_platform_driver *drv = to_of_platform_driver(dev->driver);
+ int ret = 0;
- if (dev->driver && drv->shutdown)
- drv->shutdown(of_dev);
+ if (dev->driver && drv->resume)
+ ret = drv->resume(of_dev);
+ return ret;
+}
+
+static int of_platform_pm_prepare(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+ int ret = 0;
+
+ if (drv && drv->pm && drv->pm->prepare)
+ ret = drv->pm->prepare(dev);
+
+ return ret;
+}
+
+static void of_platform_pm_complete(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+
+ if (drv && drv->pm && drv->pm->complete)
+ drv->pm->complete(dev);
+}
+
+#ifdef CONFIG_SUSPEND
+
+static int of_platform_pm_suspend(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+ int ret = 0;
+
+ if (!drv)
+ return 0;
+
+ if (drv->pm) {
+ if (drv->pm->suspend)
+ ret = drv->pm->suspend(dev);
+ } else {
+ ret = of_platform_legacy_suspend(dev, PMSG_SUSPEND);
+ }
+
+ return ret;
}
+static int of_platform_pm_suspend_noirq(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+ int ret = 0;
+
+ if (!drv)
+ return 0;
+
+ if (drv->pm) {
+ if (drv->pm->suspend_noirq)
+ ret = drv->pm->suspend_noirq(dev);
+ }
+
+ return ret;
+}
+
+static int of_platform_pm_resume(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+ int ret = 0;
+
+ if (!drv)
+ return 0;
+
+ if (drv->pm) {
+ if (drv->pm->resume)
+ ret = drv->pm->resume(dev);
+ } else {
+ ret = of_platform_legacy_resume(dev);
+ }
+
+ return ret;
+}
+
+static int of_platform_pm_resume_noirq(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+ int ret = 0;
+
+ if (!drv)
+ return 0;
+
+ if (drv->pm) {
+ if (drv->pm->resume_noirq)
+ ret = drv->pm->resume_noirq(dev);
+ }
+
+ return ret;
+}
+
+#else /* !CONFIG_SUSPEND */
+
+#define of_platform_pm_suspend NULL
+#define of_platform_pm_resume NULL
+#define of_platform_pm_suspend_noirq NULL
+#define of_platform_pm_resume_noirq NULL
+
+#endif /* !CONFIG_SUSPEND */
+
+#ifdef CONFIG_HIBERNATION
+
+static int of_platform_pm_freeze(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+ int ret = 0;
+
+ if (!drv)
+ return 0;
+
+ if (drv->pm) {
+ if (drv->pm->freeze)
+ ret = drv->pm->freeze(dev);
+ } else {
+ ret = of_platform_legacy_suspend(dev, PMSG_FREEZE);
+ }
+
+ return ret;
+}
+
+static int of_platform_pm_freeze_noirq(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+ int ret = 0;
+
+ if (!drv)
+ return 0;
+
+ if (drv->pm) {
+ if (drv->pm->freeze_noirq)
+ ret = drv->pm->freeze_noirq(dev);
+ }
+
+ return ret;
+}
+
+static int of_platform_pm_thaw(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+ int ret = 0;
+
+ if (!drv)
+ return 0;
+
+ if (drv->pm) {
+ if (drv->pm->thaw)
+ ret = drv->pm->thaw(dev);
+ } else {
+ ret = of_platform_legacy_resume(dev);
+ }
+
+ return ret;
+}
+
+static int of_platform_pm_thaw_noirq(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+ int ret = 0;
+
+ if (!drv)
+ return 0;
+
+ if (drv->pm) {
+ if (drv->pm->thaw_noirq)
+ ret = drv->pm->thaw_noirq(dev);
+ }
+
+ return ret;
+}
+
+static int of_platform_pm_poweroff(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+ int ret = 0;
+
+ if (!drv)
+ return 0;
+
+ if (drv->pm) {
+ if (drv->pm->poweroff)
+ ret = drv->pm->poweroff(dev);
+ } else {
+ ret = of_platform_legacy_suspend(dev, PMSG_HIBERNATE);
+ }
+
+ return ret;
+}
+
+static int of_platform_pm_poweroff_noirq(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+ int ret = 0;
+
+ if (!drv)
+ return 0;
+
+ if (drv->pm) {
+ if (drv->pm->poweroff_noirq)
+ ret = drv->pm->poweroff_noirq(dev);
+ }
+
+ return ret;
+}
+
+static int of_platform_pm_restore(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+ int ret = 0;
+
+ if (!drv)
+ return 0;
+
+ if (drv->pm) {
+ if (drv->pm->restore)
+ ret = drv->pm->restore(dev);
+ } else {
+ ret = of_platform_legacy_resume(dev);
+ }
+
+ return ret;
+}
+
+static int of_platform_pm_restore_noirq(struct device *dev)
+{
+ struct device_driver *drv = dev->driver;
+ int ret = 0;
+
+ if (!drv)
+ return 0;
+
+ if (drv->pm) {
+ if (drv->pm->restore_noirq)
+ ret = drv->pm->restore_noirq(dev);
+ }
+
+ return ret;
+}
+
+#else /* !CONFIG_HIBERNATION */
+
+#define of_platform_pm_freeze NULL
+#define of_platform_pm_thaw NULL
+#define of_platform_pm_poweroff NULL
+#define of_platform_pm_restore NULL
+#define of_platform_pm_freeze_noirq NULL
+#define of_platform_pm_thaw_noirq NULL
+#define of_platform_pm_poweroff_noirq NULL
+#define of_platform_pm_restore_noirq NULL
+
+#endif /* !CONFIG_HIBERNATION */
+
+static struct dev_pm_ops of_platform_dev_pm_ops = {
+ .prepare = of_platform_pm_prepare,
+ .complete = of_platform_pm_complete,
+ .suspend = of_platform_pm_suspend,
+ .resume = of_platform_pm_resume,
+ .freeze = of_platform_pm_freeze,
+ .thaw = of_platform_pm_thaw,
+ .poweroff = of_platform_pm_poweroff,
+ .restore = of_platform_pm_restore,
+ .suspend_noirq = of_platform_pm_suspend_noirq,
+ .resume_noirq = of_platform_pm_resume_noirq,
+ .freeze_noirq = of_platform_pm_freeze_noirq,
+ .thaw_noirq = of_platform_pm_thaw_noirq,
+ .poweroff_noirq = of_platform_pm_poweroff_noirq,
+ .restore_noirq = of_platform_pm_restore_noirq,
+};
+
+#define OF_PLATFORM_PM_OPS_PTR (&of_platform_dev_pm_ops)
+
+#else /* !CONFIG_PM_SLEEP */
+
+#define OF_PLATFORM_PM_OPS_PTR NULL
+
+#endif /* !CONFIG_PM_SLEEP */
+
int of_bus_type_init(struct bus_type *bus, const char *name)
{
bus->name = name;
bus->match = of_platform_bus_match;
bus->probe = of_platform_device_probe;
bus->remove = of_platform_device_remove;
- bus->suspend = of_platform_device_suspend;
- bus->resume = of_platform_device_resume;
bus->shutdown = of_platform_device_shutdown;
bus->dev_attrs = of_platform_device_attrs;
+ bus->pm = OF_PLATFORM_PM_OPS_PTR;
return bus_register(bus);
}
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4b6f7cb..28fce65 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -133,6 +133,14 @@ config SPI_LM70_LLP
which interfaces to an LM70 temperature sensor using
a parallel port.
+config SPI_MPC52xx
+ tristate "Freescale MPC52xx SPI (non-PSC) controller support"
+ depends on PPC_MPC52xx && SPI
+ select SPI_MASTER_OF
+ help
+ This drivers supports the MPC52xx SPI controller in master SPI
+ mode.
+
config SPI_MPC52xx_PSC
tristate "Freescale MPC52xx PSC SPI controller"
depends on PPC_MPC52xx && EXPERIMENTAL
@@ -147,9 +155,6 @@ config SPI_MPC8xxx
This enables using the Freescale MPC8xxx SPI controllers in master
mode.
- This driver uses a simple set of shift registers for data (opposed
- to the CPM based descriptor model).
-
config SPI_OMAP_UWIRE
tristate "OMAP1 MicroWire"
depends on ARCH_OMAP1
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 21a1182..e3f092a 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_OMAP24XX) += omap2_mcspi.o
obj-$(CONFIG_SPI_ORION) += orion_spi.o
obj-$(CONFIG_SPI_PL022) += amba-pl022.o
obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
+obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
obj-$(CONFIG_SPI_MPC8xxx) += spi_mpc8xxx.o
obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
diff --git a/drivers/spi/mpc52xx_psc_spi.c b/drivers/spi/mpc52xx_psc_spi.c
index 1b74d5c..f50c81d 100644
--- a/drivers/spi/mpc52xx_psc_spi.c
+++ b/drivers/spi/mpc52xx_psc_spi.c
@@ -17,6 +17,7 @@
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/of_platform.h>
+#include <linux/of_spi.h>
#include <linux/workqueue.h>
#include <linux/completion.h>
#include <linux/io.h>
@@ -313,11 +314,13 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
struct mpc52xx_psc __iomem *psc = mps->psc;
struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
u32 mclken_div;
- int ret = 0;
+ int ret;
/* default sysclk is 512MHz */
mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
- mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
+ ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
+ if (ret)
+ return ret;
/* Reset the PSC into a known state */
out_8(&psc->command, MPC52xx_PSC_RST_RX);
@@ -341,7 +344,7 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
mps->bits_per_word = 8;
- return ret;
+ return 0;
}
static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
@@ -410,8 +413,10 @@ static int __init mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
goto free_master;
ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
- if (ret < 0)
+ if (ret < 0) {
+ dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
goto free_irq;
+ }
spin_lock_init(&mps->lock);
init_completion(&mps->done);
@@ -464,10 +469,11 @@ static int __init mpc52xx_psc_spi_of_probe(struct of_device *op,
const u32 *regaddr_p;
u64 regaddr64, size64;
s16 id = -1;
+ int rc;
regaddr_p = of_get_address(op->node, 0, &size64, NULL);
if (!regaddr_p) {
- printk(KERN_ERR "Invalid PSC address\n");
+ dev_err(&op->dev, "Invalid PSC address\n");
return -EINVAL;
}
regaddr64 = of_translate_address(op->node, regaddr_p);
@@ -478,15 +484,18 @@ static int __init mpc52xx_psc_spi_of_probe(struct of_device *op,
psc_nump = of_get_property(op->node, "cell-index", NULL);
if (!psc_nump || *psc_nump > 5) {
- printk(KERN_ERR "mpc52xx_psc_spi: Device node %s has invalid "
- "cell-index property\n", op->node->full_name);
+ dev_err(&op->dev, "Invalid cell-index property\n");
return -EINVAL;
}
id = *psc_nump + 1;
}
- return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
+ rc = mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
irq_of_parse_and_map(op->node, 0), id);
+ if (rc == 0)
+ of_register_spi_devices(dev_get_drvdata(&op->dev), op->node);
+
+ return rc;
}
static int __exit mpc52xx_psc_spi_of_remove(struct of_device *op)
diff --git a/drivers/spi/mpc52xx_spi.c b/drivers/spi/mpc52xx_spi.c
new file mode 100644
index 0000000..ef8379b
--- /dev/null
+++ b/drivers/spi/mpc52xx_spi.c
@@ -0,0 +1,520 @@
+/*
+ * MPC52xx SPI bus driver.
+ *
+ * Copyright (C) 2008 Secret Lab Technologies Ltd.
+ *
+ * This file is released under the GPLv2
+ *
+ * This is the driver for the MPC5200's dedicated SPI controller.
+ *
+ * Note: this driver does not support the MPC5200 PSC in SPI mode. For
+ * that driver see drivers/spi/mpc52xx_psc_spi.c
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/of_platform.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/mpc52xx_spi.h>
+#include <linux/of_spi.h>
+#include <linux/io.h>
+#include <asm/time.h>
+#include <asm/mpc52xx.h>
+
+MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
+MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver");
+MODULE_LICENSE("GPL");
+
+/* Register offsets */
+#define SPI_CTRL1 0x00
+#define SPI_CTRL1_SPIE (1 << 7)
+#define SPI_CTRL1_SPE (1 << 6)
+#define SPI_CTRL1_MSTR (1 << 4)
+#define SPI_CTRL1_CPOL (1 << 3)
+#define SPI_CTRL1_CPHA (1 << 2)
+#define SPI_CTRL1_SSOE (1 << 1)
+#define SPI_CTRL1_LSBFE (1 << 0)
+
+#define SPI_CTRL2 0x01
+#define SPI_BRR 0x04
+
+#define SPI_STATUS 0x05
+#define SPI_STATUS_SPIF (1 << 7)
+#define SPI_STATUS_WCOL (1 << 6)
+#define SPI_STATUS_MODF (1 << 4)
+
+#define SPI_DATA 0x09
+#define SPI_PORTDATA 0x0d
+#define SPI_DATADIR 0x10
+
+/* FSM state return values */
+#define FSM_STOP 0 /* Nothing more for the state machine to */
+ /* do. If something interesting happens */
+ /* then and IRQ will be received */
+#define FSM_POLL 1 /* need to poll for completion, an IRQ is */
+ /* not expected */
+#define FSM_CONTINUE 2 /* Keep iterating the state machine */
+
+/* Driver internal data */
+struct mpc52xx_spi {
+ struct spi_master *master;
+ u32 sysclk;
+ void __iomem *regs;
+ int irq0; /* MODF irq */
+ int irq1; /* SPIF irq */
+ int ipb_freq;
+
+ /* Statistics */
+ int msg_count;
+ int wcol_count;
+ int wcol_ticks;
+ u32 wcol_tx_timestamp;
+ int modf_count;
+ int byte_count;
+
+ struct list_head queue; /* queue of pending messages */
+ spinlock_t lock;
+ struct work_struct work;
+
+
+ /* Details of current transfer (length, and buffer pointers) */
+ struct spi_message *message; /* current message */
+ struct spi_transfer *transfer; /* current transfer */
+ int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data);
+ int len;
+ int timestamp;
+ u8 *rx_buf;
+ const u8 *tx_buf;
+ int cs_change;
+};
+
+/*
+ * CS control function
+ */
+static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value)
+{
+ out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08);
+}
+
+/*
+ * Start a new transfer. This is called both by the idle state
+ * for the first transfer in a message, and by the wait state when the
+ * previous transfer in a message is complete.
+ */
+static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms)
+{
+ ms->rx_buf = ms->transfer->rx_buf;
+ ms->tx_buf = ms->transfer->tx_buf;
+ ms->len = ms->transfer->len;
+
+ /* Activate the chip select */
+ if (ms->cs_change)
+ mpc52xx_spi_chipsel(ms, 1);
+ ms->cs_change = ms->transfer->cs_change;
+
+ /* Write out the first byte */
+ ms->wcol_tx_timestamp = get_tbl();
+ if (ms->tx_buf)
+ out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
+ else
+ out_8(ms->regs + SPI_DATA, 0);
+}
+
+/* Forward declaration of state handlers */
+static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
+ u8 status, u8 data);
+static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms,
+ u8 status, u8 data);
+
+/*
+ * IDLE state
+ *
+ * No transfers are in progress; if another transfer is pending then retrieve
+ * it and kick it off. Otherwise, stop processing the state machine
+ */
+static int
+mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
+{
+ struct spi_device *spi;
+ int spr, sppr;
+ u8 ctrl1;
+
+ if (status && (irq != NO_IRQ))
+ dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
+ status);
+
+ /* Check if there is another transfer waiting. */
+ if (list_empty(&ms->queue))
+ return FSM_STOP;
+
+ /* get the head of the queue */
+ ms->message = list_first_entry(&ms->queue, struct spi_message, queue);
+ list_del_init(&ms->message->queue);
+
+ /* Setup the controller parameters */
+ ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
+ spi = ms->message->spi;
+ if (spi->mode & SPI_CPHA)
+ ctrl1 |= SPI_CTRL1_CPHA;
+ if (spi->mode & SPI_CPOL)
+ ctrl1 |= SPI_CTRL1_CPOL;
+ if (spi->mode & SPI_LSB_FIRST)
+ ctrl1 |= SPI_CTRL1_LSBFE;
+ out_8(ms->regs + SPI_CTRL1, ctrl1);
+
+ /* Setup the controller speed */
+ /* minimum divider is '2'. Also, add '1' to force rounding the
+ * divider up. */
+ sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1;
+ spr = 0;
+ if (sppr < 1)
+ sppr = 1;
+ while (((sppr - 1) & ~0x7) != 0) {
+ sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */
+ spr++;
+ }
+ sppr--; /* sppr quantity in register is offset by 1 */
+ if (spr > 7) {
+ /* Don't overrun limits of SPI baudrate register */
+ spr = 7;
+ sppr = 7;
+ }
+ out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */
+
+ ms->cs_change = 1;
+ ms->transfer = container_of(ms->message->transfers.next,
+ struct spi_transfer, transfer_list);
+
+ mpc52xx_spi_start_transfer(ms);
+ ms->state = mpc52xx_spi_fsmstate_transfer;
+
+ return FSM_CONTINUE;
+}
+
+/*
+ * TRANSFER state
+ *
+ * In the middle of a transfer. If the SPI core has completed processing
+ * a byte, then read out the received data and write out the next byte
+ * (unless this transfer is finished; in which case go on to the wait
+ * state)
+ */
+static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
+ u8 status, u8 data)
+{
+ if (!status)
+ return ms->irq0 ? FSM_STOP : FSM_POLL;
+
+ if (status & SPI_STATUS_WCOL) {
+ /* The SPI controller is stoopid. At slower speeds, it may
+ * raise the SPIF flag before the state machine is actually
+ * finished, which causes a collision (internal to the state
+ * machine only). The manual recommends inserting a delay
+ * between receiving the interrupt and sending the next byte,
+ * but it can also be worked around simply by retrying the
+ * transfer which is what we do here. */
+ ms->wcol_count++;
+ ms->wcol_ticks += get_tbl() - ms->wcol_tx_timestamp;
+ ms->wcol_tx_timestamp = get_tbl();
+ data = 0;
+ if (ms->tx_buf)
+ data = *(ms->tx_buf-1);
+ out_8(ms->regs + SPI_DATA, data); /* try again */
+ return FSM_CONTINUE;
+ } else if (status & SPI_STATUS_MODF) {
+ ms->modf_count++;
+ dev_err(&ms->master->dev, "mode fault\n");
+ mpc52xx_spi_chipsel(ms, 0);
+ ms->message->status = -EIO;
+ ms->message->complete(ms->message->context);
+ ms->state = mpc52xx_spi_fsmstate_idle;
+ return FSM_CONTINUE;
+ }
+
+ /* Read data out of the spi device */
+ ms->byte_count++;
+ if (ms->rx_buf)
+ *ms->rx_buf++ = data;
+
+ /* Is the transfer complete? */
+ ms->len--;
+ if (ms->len == 0) {
+ ms->timestamp = get_tbl();
+ ms->timestamp += ms->transfer->delay_usecs * tb_ticks_per_usec;
+ ms->state = mpc52xx_spi_fsmstate_wait;
+ return FSM_CONTINUE;
+ }
+
+ /* Write out the next byte */
+ ms->wcol_tx_timestamp = get_tbl();
+ if (ms->tx_buf)
+ out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
+ else
+ out_8(ms->regs + SPI_DATA, 0);
+
+ return FSM_CONTINUE;
+}
+
+/*
+ * WAIT state
+ *
+ * A transfer has completed; need to wait for the delay period to complete
+ * before starting the next transfer
+ */
+static int
+mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
+{
+ if (status && irq)
+ dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
+ status);
+
+ if (((int)get_tbl()) - ms->timestamp < 0)
+ return FSM_POLL;
+
+ ms->message->actual_length += ms->transfer->len;
+
+ /* Check if there is another transfer in this message. If there
+ * aren't then deactivate CS, notify sender, and drop back to idle
+ * to start the next message. */
+ if (ms->transfer->transfer_list.next == &ms->message->transfers) {
+ ms->msg_count++;
+ mpc52xx_spi_chipsel(ms, 0);
+ ms->message->status = 0;
+ ms->message->complete(ms->message->context);
+ ms->state = mpc52xx_spi_fsmstate_idle;
+ return FSM_CONTINUE;
+ }
+
+ /* There is another transfer; kick it off */
+
+ if (ms->cs_change)
+ mpc52xx_spi_chipsel(ms, 0);
+
+ ms->transfer = container_of(ms->transfer->transfer_list.next,
+ struct spi_transfer, transfer_list);
+ mpc52xx_spi_start_transfer(ms);
+ ms->state = mpc52xx_spi_fsmstate_transfer;
+ return FSM_CONTINUE;
+}
+
+/**
+ * mpc52xx_spi_fsm_process - Finite State Machine iteration function
+ * @irq: irq number that triggered the FSM or 0 for polling
+ * @ms: pointer to mpc52xx_spi driver data
+ */
+static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms)
+{
+ int rc = FSM_CONTINUE;
+ u8 status, data;
+
+ while (rc == FSM_CONTINUE) {
+ /* Interrupt cleared by read of STATUS followed by
+ * read of DATA registers */
+ status = in_8(ms->regs + SPI_STATUS);
+ data = in_8(ms->regs + SPI_DATA);
+ rc = ms->state(irq, ms, status, data);
+ }
+
+ if (rc == FSM_POLL)
+ schedule_work(&ms->work);
+}
+
+/**
+ * mpc52xx_spi_irq - IRQ handler
+ */
+static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms)
+{
+ struct mpc52xx_spi *ms = _ms;
+ spin_lock(&ms->lock);
+ mpc52xx_spi_fsm_process(irq, ms);
+ spin_unlock(&ms->lock);
+ return IRQ_HANDLED;
+}
+
+/**
+ * mpc52xx_spi_wq - Workqueue function for polling the state machine
+ */
+static void mpc52xx_spi_wq(struct work_struct *work)
+{
+ struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work);
+ unsigned long flags;
+
+ spin_lock_irqsave(&ms->lock, flags);
+ mpc52xx_spi_fsm_process(0, ms);
+ spin_unlock_irqrestore(&ms->lock, flags);
+}
+
+/*
+ * spi_master ops
+ */
+
+static int mpc52xx_spi_setup(struct spi_device *spi)
+{
+ if (spi->bits_per_word % 8)
+ return -EINVAL;
+
+ if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST))
+ return -EINVAL;
+
+ if (spi->chip_select >= spi->master->num_chipselect)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
+{
+ struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master);
+ unsigned long flags;
+
+ m->actual_length = 0;
+ m->status = -EINPROGRESS;
+
+ spin_lock_irqsave(&ms->lock, flags);
+ list_add_tail(&m->queue, &ms->queue);
+ spin_unlock_irqrestore(&ms->lock, flags);
+ schedule_work(&ms->work);
+
+ return 0;
+}
+
+/*
+ * OF Platform Bus Binding
+ */
+static int __devinit mpc52xx_spi_probe(struct of_device *op,
+ const struct of_device_id *match)
+{
+ struct spi_master *master;
+ struct mpc52xx_spi *ms;
+ void __iomem *regs;
+ int rc;
+
+ /* MMIO registers */
+ dev_dbg(&op->dev, "probing mpc5200 SPI device\n");
+ regs = of_iomap(op->node, 0);
+ if (!regs)
+ return -ENODEV;
+
+ /* initialize the device */
+ out_8(regs+SPI_CTRL1, SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR);
+ out_8(regs + SPI_CTRL2, 0x0);
+ out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */
+ out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */
+
+ /* Clear the status register and re-read it to check for a MODF
+ * failure. This driver cannot currently handle multiple masters
+ * on the SPI bus. This fault will also occur if the SPI signals
+ * are not connected to any pins (port_config setting) */
+ in_8(regs + SPI_STATUS);
+ in_8(regs + SPI_DATA);
+ if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) {
+ dev_err(&op->dev, "mode fault; is port_config correct?\n");
+ rc = -EIO;
+ goto err_init;
+ }
+
+ dev_dbg(&op->dev, "allocating spi_master struct\n");
+ master = spi_alloc_master(&op->dev, sizeof *ms);
+ if (!master) {
+ rc = -ENOMEM;
+ goto err_alloc;
+ }
+ master->bus_num = -1;
+ master->num_chipselect = 1;
+ master->setup = mpc52xx_spi_setup;
+ master->transfer = mpc52xx_spi_transfer;
+ dev_set_drvdata(&op->dev, master);
+
+ ms = spi_master_get_devdata(master);
+ ms->master = master;
+ ms->regs = regs;
+ ms->irq0 = irq_of_parse_and_map(op->node, 0);
+ ms->irq1 = irq_of_parse_and_map(op->node, 1);
+ ms->state = mpc52xx_spi_fsmstate_idle;
+ ms->ipb_freq = mpc5xxx_get_bus_frequency(op->node);
+ spin_lock_init(&ms->lock);
+ INIT_LIST_HEAD(&ms->queue);
+ INIT_WORK(&ms->work, mpc52xx_spi_wq);
+
+ /* Decide if interrupts can be used */
+ if (ms->irq0 && ms->irq1) {
+ rc = request_irq(ms->irq0, mpc52xx_spi_irq, IRQF_SAMPLE_RANDOM,
+ "mpc5200-spi-modf", ms);
+ rc |= request_irq(ms->irq1, mpc52xx_spi_irq, IRQF_SAMPLE_RANDOM,
+ "mpc5200-spi-spiF", ms);
+ if (rc) {
+ free_irq(ms->irq0, ms);
+ free_irq(ms->irq1, ms);
+ ms->irq0 = ms->irq1 = 0;
+ }
+ } else {
+ /* operate in polled mode */
+ ms->irq0 = ms->irq1 = 0;
+ }
+
+ if (!ms->irq0)
+ dev_info(&op->dev, "using polled mode\n");
+
+ dev_dbg(&op->dev, "registering spi_master struct\n");
+ rc = spi_register_master(master);
+ if (rc)
+ goto err_register;
+
+ of_register_spi_devices(master, op->node);
+ dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n");
+
+ return rc;
+
+ err_register:
+ dev_err(&ms->master->dev, "initialization failed\n");
+ spi_master_put(master);
+ err_alloc:
+ err_init:
+ iounmap(regs);
+ return rc;
+}
+
+static int __devexit mpc52xx_spi_remove(struct of_device *op)
+{
+ struct spi_master *master = dev_get_drvdata(&op->dev);
+ struct mpc52xx_spi *ms = spi_master_get_devdata(master);
+
+ free_irq(ms->irq0, ms);
+ free_irq(ms->irq1, ms);
+
+ spi_unregister_master(master);
+ spi_master_put(master);
+ iounmap(ms->regs);
+
+ return 0;
+}
+
+static struct of_device_id mpc52xx_spi_match[] __devinitdata = {
+ { .compatible = "fsl,mpc5200-spi", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, mpc52xx_spi_match);
+
+static struct of_platform_driver mpc52xx_spi_of_driver = {
+ .owner = THIS_MODULE,
+ .name = "mpc52xx-spi",
+ .match_table = mpc52xx_spi_match,
+ .probe = mpc52xx_spi_probe,
+ .remove = __exit_p(mpc52xx_spi_remove),
+};
+
+static int __init mpc52xx_spi_init(void)
+{
+ return of_register_platform_driver(&mpc52xx_spi_of_driver);
+}
+module_init(mpc52xx_spi_init);
+
+static void __exit mpc52xx_spi_exit(void)
+{
+ of_unregister_platform_driver(&mpc52xx_spi_of_driver);
+}
+module_exit(mpc52xx_spi_exit);
+
diff --git a/drivers/spi/spi_mpc8xxx.c b/drivers/spi/spi_mpc8xxx.c
index 0fd0ec4..930135d 100644
--- a/drivers/spi/spi_mpc8xxx.c
+++ b/drivers/spi/spi_mpc8xxx.c
@@ -5,6 +5,10 @@
*
* Copyright (C) 2006 Polycom, Inc.
*
+ * CPM SPI and QE buffer descriptors mode support:
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
@@ -27,6 +31,9 @@
#include <linux/spi/spi_bitbang.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
+#include <linux/dma-mapping.h>
+#include <linux/mm.h>
+#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/gpio.h>
@@ -34,8 +41,19 @@
#include <linux/of_spi.h>
#include <sysdev/fsl_soc.h>
+#include <asm/cpm.h>
+#include <asm/qe.h>
#include <asm/irq.h>
+/* CPM1 and CPM2 are mutually exclusive. */
+#ifdef CONFIG_CPM1
+#include <asm/cpm1.h>
+#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
+#else
+#include <asm/cpm2.h>
+#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
+#endif
+
/* SPI Controller registers */
struct mpc8xxx_spi_reg {
u8 res1[0x20];
@@ -47,6 +65,28 @@ struct mpc8xxx_spi_reg {
__be32 receive;
};
+/* SPI Parameter RAM */
+struct spi_pram {
+ __be16 rbase; /* Rx Buffer descriptor base address */
+ __be16 tbase; /* Tx Buffer descriptor base address */
+ u8 rfcr; /* Rx function code */
+ u8 tfcr; /* Tx function code */
+ __be16 mrblr; /* Max receive buffer length */
+ __be32 rstate; /* Internal */
+ __be32 rdp; /* Internal */
+ __be16 rbptr; /* Internal */
+ __be16 rbc; /* Internal */
+ __be32 rxtmp; /* Internal */
+ __be32 tstate; /* Internal */
+ __be32 tdp; /* Internal */
+ __be16 tbptr; /* Internal */
+ __be16 tbc; /* Internal */
+ __be32 txtmp; /* Internal */
+ __be32 res; /* Tx temp. */
+ __be16 rpbase; /* Relocation pointer (CPM1 only) */
+ __be16 res1; /* Reserved */
+};
+
/* SPI Controller mode register definitions */
#define SPMODE_LOOP (1 << 30)
#define SPMODE_CI_INACTIVEHIGH (1 << 29)
@@ -75,14 +115,40 @@ struct mpc8xxx_spi_reg {
#define SPIM_NE 0x00000200 /* Not empty */
#define SPIM_NF 0x00000100 /* Not full */
+#define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
+#define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
+
+/* SPCOM register values */
+#define SPCOM_STR (1 << 23) /* Start transmit */
+
+#define SPI_PRAM_SIZE 0x100
+#define SPI_MRBLR ((unsigned int)PAGE_SIZE)
+
/* SPI Controller driver's private data. */
struct mpc8xxx_spi {
+ struct device *dev;
struct mpc8xxx_spi_reg __iomem *base;
/* rx & tx bufs from the spi_transfer */
const void *tx;
void *rx;
+ int subblock;
+ struct spi_pram __iomem *pram;
+ struct cpm_buf_desc __iomem *tx_bd;
+ struct cpm_buf_desc __iomem *rx_bd;
+
+ struct spi_transfer *xfer_in_progress;
+
+ /* dma addresses for CPM transfers */
+ dma_addr_t tx_dma;
+ dma_addr_t rx_dma;
+ bool map_tx_dma;
+ bool map_rx_dma;
+
+ dma_addr_t dma_dummy_tx;
+ dma_addr_t dma_dummy_rx;
+
/* functions to deal with different sized buffers */
void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
u32(*get_tx) (struct mpc8xxx_spi *);
@@ -96,7 +162,7 @@ struct mpc8xxx_spi {
u32 rx_shift; /* RX data reg shift when in qe mode */
u32 tx_shift; /* TX data reg shift when in qe mode */
- bool qe_mode;
+ unsigned int flags;
struct workqueue_struct *workqueue;
struct work_struct work;
@@ -107,6 +173,10 @@ struct mpc8xxx_spi {
struct completion done;
};
+static void *mpc8xxx_dummy_rx;
+static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock);
+static int mpc8xxx_dummy_rx_refcnt;
+
struct spi_mpc8xxx_cs {
/* functions to deal with different sized buffers */
void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
@@ -155,6 +225,42 @@ MPC83XX_SPI_TX_BUF(u8)
MPC83XX_SPI_TX_BUF(u16)
MPC83XX_SPI_TX_BUF(u32)
+static void mpc8xxx_spi_change_mode(struct spi_device *spi)
+{
+ struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
+ struct spi_mpc8xxx_cs *cs = spi->controller_state;
+ __be32 __iomem *mode = &mspi->base->mode;
+ unsigned long flags;
+
+ if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
+ return;
+
+ /* Turn off IRQs locally to minimize time that SPI is disabled. */
+ local_irq_save(flags);
+
+ /* Turn off SPI unit prior changing mode */
+ mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
+ mpc8xxx_spi_write_reg(mode, cs->hw_mode);
+
+ /* When in CPM mode, we need to reinit tx and rx. */
+ if (mspi->flags & SPI_CPM_MODE) {
+ if (mspi->flags & SPI_QE) {
+ qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
+ QE_CR_PROTOCOL_UNSPECIFIED, 0);
+ } else {
+ cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
+ if (mspi->flags & SPI_CPM1) {
+ out_be16(&mspi->pram->rbptr,
+ in_be16(&mspi->pram->rbase));
+ out_be16(&mspi->pram->tbptr,
+ in_be16(&mspi->pram->tbase));
+ }
+ }
+ }
+
+ local_irq_restore(flags);
+}
+
static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
{
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
@@ -168,27 +274,13 @@ static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
}
if (value == BITBANG_CS_ACTIVE) {
- u32 regval = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
-
mpc8xxx_spi->rx_shift = cs->rx_shift;
mpc8xxx_spi->tx_shift = cs->tx_shift;
mpc8xxx_spi->get_rx = cs->get_rx;
mpc8xxx_spi->get_tx = cs->get_tx;
- if (cs->hw_mode != regval) {
- unsigned long flags;
- __be32 __iomem *mode = &mpc8xxx_spi->base->mode;
-
- regval = cs->hw_mode;
- /* Turn off IRQs locally to minimize time that
- * SPI is disabled
- */
- local_irq_save(flags);
- /* Turn off SPI unit prior changing mode */
- mpc8xxx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
- mpc8xxx_spi_write_reg(mode, regval);
- local_irq_restore(flags);
- }
+ mpc8xxx_spi_change_mode(spi);
+
if (pdata->cs_control)
pdata->cs_control(spi, pol);
}
@@ -198,7 +290,6 @@ static
int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
struct mpc8xxx_spi *mpc8xxx_spi;
- u32 regval;
u8 bits_per_word, pm;
u32 hz;
struct spi_mpc8xxx_cs *cs = spi->controller_state;
@@ -230,14 +321,14 @@ int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
if (bits_per_word <= 8) {
cs->get_rx = mpc8xxx_spi_rx_buf_u8;
cs->get_tx = mpc8xxx_spi_tx_buf_u8;
- if (mpc8xxx_spi->qe_mode) {
+ if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
cs->rx_shift = 16;
cs->tx_shift = 24;
}
} else if (bits_per_word <= 16) {
cs->get_rx = mpc8xxx_spi_rx_buf_u16;
cs->get_tx = mpc8xxx_spi_tx_buf_u16;
- if (mpc8xxx_spi->qe_mode) {
+ if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
cs->rx_shift = 16;
cs->tx_shift = 16;
}
@@ -247,7 +338,8 @@ int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
} else
return -EINVAL;
- if (mpc8xxx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
+ if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
+ spi->mode & SPI_LSB_FIRST) {
cs->tx_shift = 0;
if (bits_per_word <= 8)
cs->rx_shift = 8;
@@ -286,37 +378,138 @@ int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
pm--;
cs->hw_mode |= SPMODE_PM(pm);
- regval = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
- if (cs->hw_mode != regval) {
- unsigned long flags;
- __be32 __iomem *mode = &mpc8xxx_spi->base->mode;
-
- regval = cs->hw_mode;
- /* Turn off IRQs locally to minimize time
- * that SPI is disabled
- */
- local_irq_save(flags);
- /* Turn off SPI unit prior changing mode */
- mpc8xxx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
- mpc8xxx_spi_write_reg(mode, regval);
- local_irq_restore(flags);
+
+ mpc8xxx_spi_change_mode(spi);
+ return 0;
+}
+
+static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
+{
+ struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
+ struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
+ unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
+ unsigned int xfer_ofs;
+
+ xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
+
+ out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
+ out_be16(&rx_bd->cbd_datlen, 0);
+ out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
+
+ out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
+ out_be16(&tx_bd->cbd_datlen, xfer_len);
+ out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
+ BD_SC_LAST);
+
+ /* start transfer */
+ mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR);
+}
+
+static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
+ struct spi_transfer *t, bool is_dma_mapped)
+{
+ struct device *dev = mspi->dev;
+
+ if (is_dma_mapped) {
+ mspi->map_tx_dma = 0;
+ mspi->map_rx_dma = 0;
+ } else {
+ mspi->map_tx_dma = 1;
+ mspi->map_rx_dma = 1;
+ }
+
+ if (!t->tx_buf) {
+ mspi->tx_dma = mspi->dma_dummy_tx;
+ mspi->map_tx_dma = 0;
+ }
+
+ if (!t->rx_buf) {
+ mspi->rx_dma = mspi->dma_dummy_rx;
+ mspi->map_rx_dma = 0;
}
+
+ if (mspi->map_tx_dma) {
+ void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
+
+ mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
+ DMA_TO_DEVICE);
+ if (dma_mapping_error(dev, mspi->tx_dma)) {
+ dev_err(dev, "unable to map tx dma\n");
+ return -ENOMEM;
+ }
+ } else {
+ mspi->tx_dma = t->tx_dma;
+ }
+
+ if (mspi->map_rx_dma) {
+ mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(dev, mspi->rx_dma)) {
+ dev_err(dev, "unable to map rx dma\n");
+ goto err_rx_dma;
+ }
+ } else {
+ mspi->rx_dma = t->rx_dma;
+ }
+
+ /* enable rx ints */
+ mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB);
+
+ mspi->xfer_in_progress = t;
+ mspi->count = t->len;
+
+ /* start CPM transfers */
+ mpc8xxx_spi_cpm_bufs_start(mspi);
+
return 0;
+
+err_rx_dma:
+ if (mspi->map_tx_dma)
+ dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
+ return -ENOMEM;
}
-static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
+static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
{
- struct mpc8xxx_spi *mpc8xxx_spi;
- u32 word, len, bits_per_word;
+ struct device *dev = mspi->dev;
+ struct spi_transfer *t = mspi->xfer_in_progress;
+
+ if (mspi->map_tx_dma)
+ dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
+ if (mspi->map_tx_dma)
+ dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
+ mspi->xfer_in_progress = NULL;
+}
- mpc8xxx_spi = spi_master_get_devdata(spi->master);
+static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
+ struct spi_transfer *t, unsigned int len)
+{
+ u32 word;
+
+ mspi->count = len;
+
+ /* enable rx ints */
+ mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE);
+
+ /* transmit word */
+ word = mspi->get_tx(mspi);
+ mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
+
+ return 0;
+}
+
+static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
+ bool is_dma_mapped)
+{
+ struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
+ unsigned int len = t->len;
+ u8 bits_per_word;
+ int ret;
- mpc8xxx_spi->tx = t->tx_buf;
- mpc8xxx_spi->rx = t->rx_buf;
bits_per_word = spi->bits_per_word;
if (t->bits_per_word)
bits_per_word = t->bits_per_word;
- len = t->len;
+
if (bits_per_word > 8) {
/* invalid length? */
if (len & 1)
@@ -329,22 +522,27 @@ static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
return -EINVAL;
len /= 2;
}
- mpc8xxx_spi->count = len;
- INIT_COMPLETION(mpc8xxx_spi->done);
+ mpc8xxx_spi->tx = t->tx_buf;
+ mpc8xxx_spi->rx = t->rx_buf;
- /* enable rx ints */
- mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, SPIM_NE);
+ INIT_COMPLETION(mpc8xxx_spi->done);
- /* transmit word */
- word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
- mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word);
+ if (mpc8xxx_spi->flags & SPI_CPM_MODE)
+ ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
+ else
+ ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len);
+ if (ret)
+ return ret;
wait_for_completion(&mpc8xxx_spi->done);
/* disable rx ints */
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
+ if (mpc8xxx_spi->flags & SPI_CPM_MODE)
+ mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi);
+
return mpc8xxx_spi->count;
}
@@ -375,7 +573,7 @@ static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
}
cs_change = t->cs_change;
if (t->len)
- status = mpc8xxx_spi_bufs(spi, t);
+ status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped);
if (status) {
status = -EMSGSIZE;
break;
@@ -464,45 +662,80 @@ static int mpc8xxx_spi_setup(struct spi_device *spi)
return 0;
}
-static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
+static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
{
- struct mpc8xxx_spi *mpc8xxx_spi = context_data;
- u32 event;
- irqreturn_t ret = IRQ_NONE;
+ u16 len;
- /* Get interrupt events(tx/rx) */
- event = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event);
+ dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
+ in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
- /* We need handle RX first */
- if (event & SPIE_NE) {
- u32 rx_data = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->receive);
+ len = in_be16(&mspi->rx_bd->cbd_datlen);
+ if (len > mspi->count) {
+ WARN_ON(1);
+ len = mspi->count;
+ }
- if (mpc8xxx_spi->rx)
- mpc8xxx_spi->get_rx(rx_data, mpc8xxx_spi);
+ /* Clear the events */
+ mpc8xxx_spi_write_reg(&mspi->base->event, events);
- ret = IRQ_HANDLED;
+ mspi->count -= len;
+ if (mspi->count)
+ mpc8xxx_spi_cpm_bufs_start(mspi);
+ else
+ complete(&mspi->done);
+}
+
+static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
+{
+ /* We need handle RX first */
+ if (events & SPIE_NE) {
+ u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive);
+
+ if (mspi->rx)
+ mspi->get_rx(rx_data, mspi);
}
- if ((event & SPIE_NF) == 0)
+ if ((events & SPIE_NF) == 0)
/* spin until TX is done */
- while (((event =
- mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event)) &
+ while (((events =
+ mpc8xxx_spi_read_reg(&mspi->base->event)) &
SPIE_NF) == 0)
cpu_relax();
- mpc8xxx_spi->count -= 1;
- if (mpc8xxx_spi->count) {
- u32 word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
- mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word);
+ /* Clear the events */
+ mpc8xxx_spi_write_reg(&mspi->base->event, events);
+
+ mspi->count -= 1;
+ if (mspi->count) {
+ u32 word = mspi->get_tx(mspi);
+
+ mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
} else {
- complete(&mpc8xxx_spi->done);
+ complete(&mspi->done);
}
+}
- /* Clear the events */
- mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, event);
+static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
+{
+ struct mpc8xxx_spi *mspi = context_data;
+ irqreturn_t ret = IRQ_NONE;
+ u32 events;
+
+ /* Get interrupt events(tx/rx) */
+ events = mpc8xxx_spi_read_reg(&mspi->base->event);
+ if (events)
+ ret = IRQ_HANDLED;
+
+ dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
+
+ if (mspi->flags & SPI_CPM_MODE)
+ mpc8xxx_spi_cpm_irq(mspi, events);
+ else
+ mpc8xxx_spi_cpu_irq(mspi, events);
return ret;
}
+
static int mpc8xxx_spi_transfer(struct spi_device *spi,
struct spi_message *m)
{
@@ -526,6 +759,215 @@ static void mpc8xxx_spi_cleanup(struct spi_device *spi)
kfree(spi->controller_state);
}
+static void *mpc8xxx_spi_alloc_dummy_rx(void)
+{
+ mutex_lock(&mpc8xxx_dummy_rx_lock);
+
+ if (!mpc8xxx_dummy_rx)
+ mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
+ if (mpc8xxx_dummy_rx)
+ mpc8xxx_dummy_rx_refcnt++;
+
+ mutex_unlock(&mpc8xxx_dummy_rx_lock);
+
+ return mpc8xxx_dummy_rx;
+}
+
+static void mpc8xxx_spi_free_dummy_rx(void)
+{
+ mutex_lock(&mpc8xxx_dummy_rx_lock);
+
+ switch (mpc8xxx_dummy_rx_refcnt) {
+ case 0:
+ WARN_ON(1);
+ break;
+ case 1:
+ kfree(mpc8xxx_dummy_rx);
+ mpc8xxx_dummy_rx = NULL;
+ /* fall through */
+ default:
+ mpc8xxx_dummy_rx_refcnt--;
+ break;
+ }
+
+ mutex_unlock(&mpc8xxx_dummy_rx_lock);
+}
+
+static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
+{
+ struct device *dev = mspi->dev;
+ struct device_node *np = dev_archdata_get_node(&dev->archdata);
+ const u32 *iprop;
+ int size;
+ unsigned long spi_base_ofs;
+ unsigned long pram_ofs = -ENOMEM;
+
+ /* Can't use of_address_to_resource(), QE muram isn't at 0. */
+ iprop = of_get_property(np, "reg", &size);
+
+ /* QE with a fixed pram location? */
+ if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
+ return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
+
+ /* QE but with a dynamic pram location? */
+ if (mspi->flags & SPI_QE) {
+ pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
+ qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
+ QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
+ return pram_ofs;
+ }
+
+ /* CPM1 and CPM2 pram must be at a fixed addr. */
+ if (!iprop || size != sizeof(*iprop) * 4)
+ return -ENOMEM;
+
+ spi_base_ofs = cpm_muram_alloc_fixed(iprop[2], 2);
+ if (IS_ERR_VALUE(spi_base_ofs))
+ return -ENOMEM;
+
+ if (mspi->flags & SPI_CPM2) {
+ pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
+ if (!IS_ERR_VALUE(pram_ofs)) {
+ u16 __iomem *spi_base = cpm_muram_addr(spi_base_ofs);
+
+ out_be16(spi_base, pram_ofs);
+ }
+ } else {
+ struct spi_pram __iomem *pram = cpm_muram_addr(spi_base_ofs);
+ u16 rpbase = in_be16(&pram->rpbase);
+
+ /* Microcode relocation patch applied? */
+ if (rpbase)
+ pram_ofs = rpbase;
+ else
+ return spi_base_ofs;
+ }
+
+ cpm_muram_free(spi_base_ofs);
+ return pram_ofs;
+}
+
+static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
+{
+ struct device *dev = mspi->dev;
+ struct device_node *np = dev_archdata_get_node(&dev->archdata);
+ const u32 *iprop;
+ int size;
+ unsigned long pram_ofs;
+ unsigned long bds_ofs;
+
+ if (!(mspi->flags & SPI_CPM_MODE))
+ return 0;
+
+ if (!mpc8xxx_spi_alloc_dummy_rx())
+ return -ENOMEM;
+
+ if (mspi->flags & SPI_QE) {
+ iprop = of_get_property(np, "cell-index", &size);
+ if (iprop && size == sizeof(*iprop))
+ mspi->subblock = *iprop;
+
+ switch (mspi->subblock) {
+ default:
+ dev_warn(dev, "cell-index unspecified, assuming SPI1");
+ /* fall through */
+ case 0:
+ mspi->subblock = QE_CR_SUBBLOCK_SPI1;
+ break;
+ case 1:
+ mspi->subblock = QE_CR_SUBBLOCK_SPI2;
+ break;
+ }
+ }
+
+ pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi);
+ if (IS_ERR_VALUE(pram_ofs)) {
+ dev_err(dev, "can't allocate spi parameter ram\n");
+ goto err_pram;
+ }
+
+ bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
+ sizeof(*mspi->rx_bd), 8);
+ if (IS_ERR_VALUE(bds_ofs)) {
+ dev_err(dev, "can't allocate bds\n");
+ goto err_bds;
+ }
+
+ mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
+ DMA_TO_DEVICE);
+ if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
+ dev_err(dev, "unable to map dummy tx buffer\n");
+ goto err_dummy_tx;
+ }
+
+ mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR,
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
+ dev_err(dev, "unable to map dummy rx buffer\n");
+ goto err_dummy_rx;
+ }
+
+ mspi->pram = cpm_muram_addr(pram_ofs);
+
+ mspi->tx_bd = cpm_muram_addr(bds_ofs);
+ mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
+
+ /* Initialize parameter ram. */
+ out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
+ out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
+ out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
+ out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
+ out_be16(&mspi->pram->mrblr, SPI_MRBLR);
+ out_be32(&mspi->pram->rstate, 0);
+ out_be32(&mspi->pram->rdp, 0);
+ out_be16(&mspi->pram->rbptr, 0);
+ out_be16(&mspi->pram->rbc, 0);
+ out_be32(&mspi->pram->rxtmp, 0);
+ out_be32(&mspi->pram->tstate, 0);
+ out_be32(&mspi->pram->tdp, 0);
+ out_be16(&mspi->pram->tbptr, 0);
+ out_be16(&mspi->pram->tbc, 0);
+ out_be32(&mspi->pram->txtmp, 0);
+
+ return 0;
+
+err_dummy_rx:
+ dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
+err_dummy_tx:
+ cpm_muram_free(bds_ofs);
+err_bds:
+ cpm_muram_free(pram_ofs);
+err_pram:
+ mpc8xxx_spi_free_dummy_rx();
+ return -ENOMEM;
+}
+
+static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi)
+{
+ struct device *dev = mspi->dev;
+
+ dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
+ dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
+ cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
+ cpm_muram_free(cpm_muram_offset(mspi->pram));
+ mpc8xxx_spi_free_dummy_rx();
+}
+
+static const char *mpc8xxx_spi_strmode(unsigned int flags)
+{
+ if (flags & SPI_QE_CPU_MODE) {
+ return "QE CPU";
+ } else if (flags & SPI_CPM_MODE) {
+ if (flags & SPI_QE)
+ return "QE";
+ else if (flags & SPI_CPM2)
+ return "CPM2";
+ else
+ return "CPM1";
+ }
+ return "CPU";
+}
+
static struct spi_master * __devinit
mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
{
@@ -552,14 +994,19 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
master->cleanup = mpc8xxx_spi_cleanup;
mpc8xxx_spi = spi_master_get_devdata(master);
- mpc8xxx_spi->qe_mode = pdata->qe_mode;
+ mpc8xxx_spi->dev = dev;
mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
+ mpc8xxx_spi->flags = pdata->flags;
mpc8xxx_spi->spibrg = pdata->sysclk;
+ ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi);
+ if (ret)
+ goto err_cpm_init;
+
mpc8xxx_spi->rx_shift = 0;
mpc8xxx_spi->tx_shift = 0;
- if (mpc8xxx_spi->qe_mode) {
+ if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
mpc8xxx_spi->rx_shift = 16;
mpc8xxx_spi->tx_shift = 24;
}
@@ -569,7 +1016,7 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
mpc8xxx_spi->base = ioremap(mem->start, mem->end - mem->start + 1);
if (mpc8xxx_spi->base == NULL) {
ret = -ENOMEM;
- goto put_master;
+ goto err_ioremap;
}
mpc8xxx_spi->irq = irq;
@@ -592,7 +1039,7 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
/* Enable SPI interface */
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
- if (pdata->qe_mode)
+ if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
regval |= SPMODE_OP;
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
@@ -612,9 +1059,8 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
if (ret < 0)
goto unreg_master;
- printk(KERN_INFO
- "%s: MPC8xxx SPI Controller driver at 0x%p (irq = %d)\n",
- dev_name(dev), mpc8xxx_spi->base, mpc8xxx_spi->irq);
+ dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base,
+ mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
return master;
@@ -624,7 +1070,9 @@ free_irq:
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
unmap_io:
iounmap(mpc8xxx_spi->base);
-put_master:
+err_ioremap:
+ mpc8xxx_spi_cpm_free(mpc8xxx_spi);
+err_cpm_init:
spi_master_put(master);
err:
return ERR_PTR(ret);
@@ -644,6 +1092,7 @@ static int __devexit mpc8xxx_spi_remove(struct device *dev)
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
iounmap(mpc8xxx_spi->base);
+ mpc8xxx_spi_cpm_free(mpc8xxx_spi);
return 0;
}
@@ -709,6 +1158,7 @@ static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
gpio = of_get_gpio_flags(np, i, &flags);
if (!gpio_is_valid(gpio)) {
dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
+ ret = gpio;
goto err_loop;
}
@@ -804,7 +1254,13 @@ static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
prop = of_get_property(np, "mode", NULL);
if (prop && !strcmp(prop, "cpu-qe"))
- pdata->qe_mode = 1;
+ pdata->flags = SPI_QE_CPU_MODE;
+ else if (prop && !strcmp(prop, "qe"))
+ pdata->flags = SPI_CPM_MODE | SPI_QE;
+ else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
+ pdata->flags = SPI_CPM_MODE | SPI_CPM2;
+ else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
+ pdata->flags = SPI_CPM_MODE | SPI_CPM1;
ret = of_mpc8xxx_spi_get_chipselects(dev);
if (ret)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 46b8c5c..5a143b9 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -148,7 +148,8 @@ static int xilinx_spi_setup_transfer(struct spi_device *spi,
{
u8 bits_per_word;
- bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
+ bits_per_word = (t && t->bits_per_word)
+ ? t->bits_per_word : spi->bits_per_word;
if (bits_per_word != 8) {
dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
__func__, bits_per_word);
diff --git a/drivers/usb/gadget/fsl_qe_udc.h b/drivers/usb/gadget/fsl_qe_udc.h
index 31b2710..bea5b82 100644
--- a/drivers/usb/gadget/fsl_qe_udc.h
+++ b/drivers/usb/gadget/fsl_qe_udc.h
@@ -419,19 +419,4 @@ struct qe_udc {
#define CPM_USB_RESTART_TX_OPCODE 0x0b
#define CPM_USB_EP_SHIFT 5
-#ifndef CONFIG_CPM
-inline int cpm_command(u32 command, u8 opcode)
-{
- return -EOPNOTSUPP;
-}
-#endif
-
-#ifndef CONFIG_QUICC_ENGINE
-inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
- u32 cmd_input)
-{
- return -EOPNOTSUPP;
-}
-#endif
-
#endif /* __FSL_QE_UDC_H */
diff --git a/drivers/video/offb.c b/drivers/video/offb.c
index 4d8c54c..b043ac8 100644
--- a/drivers/video/offb.c
+++ b/drivers/video/offb.c
@@ -282,8 +282,17 @@ static int offb_set_par(struct fb_info *info)
return 0;
}
+static void offb_destroy(struct fb_info *info)
+{
+ if (info->screen_base)
+ iounmap(info->screen_base);
+ release_mem_region(info->aperture_base, info->aperture_size);
+ framebuffer_release(info);
+}
+
static struct fb_ops offb_ops = {
.owner = THIS_MODULE,
+ .fb_destroy = offb_destroy,
.fb_setcolreg = offb_setcolreg,
.fb_set_par = offb_set_par,
.fb_blank = offb_blank,
@@ -482,10 +491,14 @@ static void __init offb_init_fb(const char *name, const char *full_name,
var->sync = 0;
var->vmode = FB_VMODE_NONINTERLACED;
+ /* set offb aperture size for generic probing */
+ info->aperture_base = address;
+ info->aperture_size = fix->smem_len;
+
info->fbops = &offb_ops;
info->screen_base = ioremap(address, fix->smem_len);
info->pseudo_palette = (void *) (info + 1);
- info->flags = FBINFO_DEFAULT | foreign_endian;
+ info->flags = FBINFO_DEFAULT | FBINFO_MISC_FIRMWARE | foreign_endian;
fb_alloc_cmap(&info->cmap, 256, 0);
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 3711b88..d958b76 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -861,8 +861,10 @@ config GEF_WDT
Watchdog timer found in a number of GE Fanuc single board computers.
config MPC5200_WDT
- tristate "MPC5200 Watchdog Timer"
+ bool "MPC52xx Watchdog Timer"
depends on PPC_MPC52xx
+ help
+ Use General Purpose Timer (GPT) 0 on the MPC5200 as Watchdog.
config 8xxx_WDT
tristate "MPC8xxx Platform Watchdog Timer"
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 699199b..89c045d 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -118,7 +118,6 @@ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
# POWERPC Architecture
obj-$(CONFIG_GEF_WDT) += gef_wdt.o
-obj-$(CONFIG_MPC5200_WDT) += mpc5200_wdt.o
obj-$(CONFIG_8xxx_WDT) += mpc8xxx_wdt.o
obj-$(CONFIG_MV64X60_WDT) += mv64x60_wdt.o
obj-$(CONFIG_PIKA_WDT) += pika_wdt.o
diff --git a/drivers/watchdog/mpc5200_wdt.c b/drivers/watchdog/mpc5200_wdt.c
deleted file mode 100644
index fa9c47c..0000000
--- a/drivers/watchdog/mpc5200_wdt.c
+++ /dev/null
@@ -1,293 +0,0 @@
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/miscdevice.h>
-#include <linux/watchdog.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-#include <linux/of_platform.h>
-#include <linux/uaccess.h>
-#include <asm/mpc52xx.h>
-
-
-#define GPT_MODE_WDT (1 << 15)
-#define GPT_MODE_CE (1 << 12)
-#define GPT_MODE_MS_TIMER (0x4)
-
-
-struct mpc5200_wdt {
- unsigned count; /* timer ticks before watchdog kicks in */
- long ipb_freq;
- struct miscdevice miscdev;
- struct resource mem;
- struct mpc52xx_gpt __iomem *regs;
- spinlock_t io_lock;
-};
-
-/* is_active stores wether or not the /dev/watchdog device is opened */
-static unsigned long is_active;
-
-/* misc devices don't provide a way, to get back to 'dev' or 'miscdev' from
- * file operations, which sucks. But there can be max 1 watchdog anyway, so...
- */
-static struct mpc5200_wdt *wdt_global;
-
-
-/* helper to calculate timeout in timer counts */
-static void mpc5200_wdt_set_timeout(struct mpc5200_wdt *wdt, int timeout)
-{
- /* use biggest prescaler of 64k */
- wdt->count = (wdt->ipb_freq + 0xffff) / 0x10000 * timeout;
-
- if (wdt->count > 0xffff)
- wdt->count = 0xffff;
-}
-/* return timeout in seconds (calculated from timer count) */
-static int mpc5200_wdt_get_timeout(struct mpc5200_wdt *wdt)
-{
- return wdt->count * 0x10000 / wdt->ipb_freq;
-}
-
-
-/* watchdog operations */
-static int mpc5200_wdt_start(struct mpc5200_wdt *wdt)
-{
- spin_lock(&wdt->io_lock);
- /* disable */
- out_be32(&wdt->regs->mode, 0);
- /* set timeout, with maximum prescaler */
- out_be32(&wdt->regs->count, 0x0 | wdt->count);
- /* enable watchdog */
- out_be32(&wdt->regs->mode, GPT_MODE_CE | GPT_MODE_WDT |
- GPT_MODE_MS_TIMER);
- spin_unlock(&wdt->io_lock);
-
- return 0;
-}
-static int mpc5200_wdt_ping(struct mpc5200_wdt *wdt)
-{
- spin_lock(&wdt->io_lock);
- /* writing A5 to OCPW resets the watchdog */
- out_be32(&wdt->regs->mode, 0xA5000000 |
- (0xffffff & in_be32(&wdt->regs->mode)));
- spin_unlock(&wdt->io_lock);
- return 0;
-}
-static int mpc5200_wdt_stop(struct mpc5200_wdt *wdt)
-{
- spin_lock(&wdt->io_lock);
- /* disable */
- out_be32(&wdt->regs->mode, 0);
- spin_unlock(&wdt->io_lock);
- return 0;
-}
-
-
-/* file operations */
-static ssize_t mpc5200_wdt_write(struct file *file, const char __user *data,
- size_t len, loff_t *ppos)
-{
- struct mpc5200_wdt *wdt = file->private_data;
- mpc5200_wdt_ping(wdt);
- return 0;
-}
-static struct watchdog_info mpc5200_wdt_info = {
- .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
- .identity = "mpc5200 watchdog on GPT0",
-};
-static long mpc5200_wdt_ioctl(struct file *file, unsigned int cmd,
- unsigned long arg)
-{
- struct mpc5200_wdt *wdt = file->private_data;
- int __user *data = (int __user *)arg;
- int timeout;
- int ret = 0;
-
- switch (cmd) {
- case WDIOC_GETSUPPORT:
- ret = copy_to_user(data, &mpc5200_wdt_info,
- sizeof(mpc5200_wdt_info));
- if (ret)
- ret = -EFAULT;
- break;
-
- case WDIOC_GETSTATUS:
- case WDIOC_GETBOOTSTATUS:
- ret = put_user(0, data);
- break;
-
- case WDIOC_KEEPALIVE:
- mpc5200_wdt_ping(wdt);
- break;
-
- case WDIOC_SETTIMEOUT:
- ret = get_user(timeout, data);
- if (ret)
- break;
- mpc5200_wdt_set_timeout(wdt, timeout);
- mpc5200_wdt_start(wdt);
- /* fall through and return the timeout */
-
- case WDIOC_GETTIMEOUT:
- timeout = mpc5200_wdt_get_timeout(wdt);
- ret = put_user(timeout, data);
- break;
-
- default:
- ret = -ENOTTY;
- }
- return ret;
-}
-
-static int mpc5200_wdt_open(struct inode *inode, struct file *file)
-{
- /* /dev/watchdog can only be opened once */
- if (test_and_set_bit(0, &is_active))
- return -EBUSY;
-
- /* Set and activate the watchdog */
- mpc5200_wdt_set_timeout(wdt_global, 30);
- mpc5200_wdt_start(wdt_global);
- file->private_data = wdt_global;
- return nonseekable_open(inode, file);
-}
-static int mpc5200_wdt_release(struct inode *inode, struct file *file)
-{
-#if WATCHDOG_NOWAYOUT == 0
- struct mpc5200_wdt *wdt = file->private_data;
- mpc5200_wdt_stop(wdt);
- wdt->count = 0; /* == disabled */
-#endif
- clear_bit(0, &is_active);
- return 0;
-}
-
-static const struct file_operations mpc5200_wdt_fops = {
- .owner = THIS_MODULE,
- .write = mpc5200_wdt_write,
- .unlocked_ioctl = mpc5200_wdt_ioctl,
- .open = mpc5200_wdt_open,
- .release = mpc5200_wdt_release,
-};
-
-/* module operations */
-static int mpc5200_wdt_probe(struct of_device *op,
- const struct of_device_id *match)
-{
- struct mpc5200_wdt *wdt;
- int err;
- const void *has_wdt;
- int size;
-
- has_wdt = of_get_property(op->node, "has-wdt", NULL);
- if (!has_wdt)
- has_wdt = of_get_property(op->node, "fsl,has-wdt", NULL);
- if (!has_wdt)
- return -ENODEV;
-
- wdt = kzalloc(sizeof(*wdt), GFP_KERNEL);
- if (!wdt)
- return -ENOMEM;
-
- wdt->ipb_freq = mpc5xxx_get_bus_frequency(op->node);
-
- err = of_address_to_resource(op->node, 0, &wdt->mem);
- if (err)
- goto out_free;
- size = wdt->mem.end - wdt->mem.start + 1;
- if (!request_mem_region(wdt->mem.start, size, "mpc5200_wdt")) {
- err = -ENODEV;
- goto out_free;
- }
- wdt->regs = ioremap(wdt->mem.start, size);
- if (!wdt->regs) {
- err = -ENODEV;
- goto out_release;
- }
-
- dev_set_drvdata(&op->dev, wdt);
- spin_lock_init(&wdt->io_lock);
-
- wdt->miscdev = (struct miscdevice) {
- .minor = WATCHDOG_MINOR,
- .name = "watchdog",
- .fops = &mpc5200_wdt_fops,
- .parent = &op->dev,
- };
- wdt_global = wdt;
- err = misc_register(&wdt->miscdev);
- if (!err)
- return 0;
-
- iounmap(wdt->regs);
-out_release:
- release_mem_region(wdt->mem.start, size);
-out_free:
- kfree(wdt);
- return err;
-}
-
-static int mpc5200_wdt_remove(struct of_device *op)
-{
- struct mpc5200_wdt *wdt = dev_get_drvdata(&op->dev);
-
- mpc5200_wdt_stop(wdt);
- misc_deregister(&wdt->miscdev);
- iounmap(wdt->regs);
- release_mem_region(wdt->mem.start, wdt->mem.end - wdt->mem.start + 1);
- kfree(wdt);
-
- return 0;
-}
-static int mpc5200_wdt_suspend(struct of_device *op, pm_message_t state)
-{
- struct mpc5200_wdt *wdt = dev_get_drvdata(&op->dev);
- mpc5200_wdt_stop(wdt);
- return 0;
-}
-static int mpc5200_wdt_resume(struct of_device *op)
-{
- struct mpc5200_wdt *wdt = dev_get_drvdata(&op->dev);
- if (wdt->count)
- mpc5200_wdt_start(wdt);
- return 0;
-}
-static int mpc5200_wdt_shutdown(struct of_device *op)
-{
- struct mpc5200_wdt *wdt = dev_get_drvdata(&op->dev);
- mpc5200_wdt_stop(wdt);
- return 0;
-}
-
-static struct of_device_id mpc5200_wdt_match[] = {
- { .compatible = "mpc5200-gpt", },
- { .compatible = "fsl,mpc5200-gpt", },
- {},
-};
-static struct of_platform_driver mpc5200_wdt_driver = {
- .owner = THIS_MODULE,
- .name = "mpc5200-gpt-wdt",
- .match_table = mpc5200_wdt_match,
- .probe = mpc5200_wdt_probe,
- .remove = mpc5200_wdt_remove,
- .suspend = mpc5200_wdt_suspend,
- .resume = mpc5200_wdt_resume,
- .shutdown = mpc5200_wdt_shutdown,
-};
-
-
-static int __init mpc5200_wdt_init(void)
-{
- return of_register_platform_driver(&mpc5200_wdt_driver);
-}
-
-static void __exit mpc5200_wdt_exit(void)
-{
- of_unregister_platform_driver(&mpc5200_wdt_driver);
-}
-
-module_init(mpc5200_wdt_init);
-module_exit(mpc5200_wdt_exit);
-
-MODULE_AUTHOR("Domen Puncer <domen.puncer@telargo.com>");
-MODULE_LICENSE("Dual BSD/GPL");
-MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
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