diff options
Diffstat (limited to 'drivers/video')
66 files changed, 1647 insertions, 1521 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 8b31fdf..27c1fb4 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -17,6 +17,8 @@ source "drivers/gpu/vga/Kconfig" source "drivers/gpu/drm/Kconfig" +source "drivers/gpu/stub/Kconfig" + config VGASTATE tristate default n @@ -49,7 +51,7 @@ menuconfig FB You need an utility program called fbset to make full use of frame buffer devices. Please read <file:Documentation/fb/framebuffer.txt> and the Framebuffer-HOWTO at - <http://www.munted.org.uk/programming/Framebuffer-HOWTO-1.2.html> for more + <http://www.munted.org.uk/programming/Framebuffer-HOWTO-1.3.html> for more information. Say Y here and to the driver for your graphics board below if you @@ -955,7 +957,7 @@ config FB_EPSON1355 Build in support for the SED1355 Epson Research Embedded RAMDAC LCD/CRT Controller (since redesignated as the S1D13505) as a framebuffer. Product specs at - <http://www.erd.epson.com/vdc/html/products.htm>. + <http://vdc.epson.com/>. config FB_S1D13XXX tristate "Epson S1D13XXX framebuffer support" @@ -966,7 +968,7 @@ config FB_S1D13XXX help Support for S1D13XXX framebuffer device family (currently only working with S1D13806). Product specs at - <http://www.erd.epson.com/vdc/html/legacy_13xxx.htm> + <http://vdc.epson.com/> config FB_ATMEL tristate "AT91/AT32 LCD Controller support" @@ -1323,7 +1325,7 @@ config FB_RADEON don't need to choose this to run the Radeon in plain VGA mode. There is a product page at - http://apps.ati.com/ATIcompare/ + http://products.amd.com/en-us/GraphicCardResult.aspx config FB_RADEON_I2C bool "DDC/I2C for ATI Radeon support" @@ -1395,7 +1397,7 @@ config FB_ATY_CT Say Y here to support use of ATI's 64-bit Rage boards (or other boards based on the Mach64 CT, VT, GT, and LT chipsets) as a framebuffer device. The ATI product support page for these boards - is at <http://support.ati.com/products/pc/mach64/>. + is at <http://support.ati.com/products/pc/mach64/mach64.html>. config FB_ATY_GENERIC_LCD bool "Mach64 generic LCD support (EXPERIMENTAL)" @@ -1919,6 +1921,9 @@ config FB_SH_MOBILE_HDMI tristate "SuperH Mobile HDMI controller support" depends on FB_SH_MOBILE_LCDC select FB_MODE_HELPERS + select SOUND + select SND + select SND_SOC ---help--- Driver for the on-chip SH-Mobile HDMI controller. diff --git a/drivers/video/arcfb.c b/drivers/video/arcfb.c index f3d7440..3ec4923 100644 --- a/drivers/video/arcfb.c +++ b/drivers/video/arcfb.c @@ -2,7 +2,6 @@ * linux/drivers/video/arcfb.c -- FB driver for Arc monochrome LCD board * * Copyright (C) 2005, Jaya Kumar <jayalk@intworks.biz> - * http://www.intworks.biz/arclcd * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive for diff --git a/drivers/video/atafb.c b/drivers/video/atafb.c index f3aada2..5b2b5ef 100644 --- a/drivers/video/atafb.c +++ b/drivers/video/atafb.c @@ -1718,11 +1718,9 @@ static int falcon_setcolreg(unsigned int regno, unsigned int red, (((red & 0xe000) >> 13) | ((red & 0x1000) >> 12) << 8) | (((green & 0xe000) >> 13) | ((green & 0x1000) >> 12) << 4) | ((blue & 0xe000) >> 13) | ((blue & 0x1000) >> 12); -#ifdef ATAFB_FALCON ((u32 *)info->pseudo_palette)[regno] = ((red & 0xf800) | ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11)); -#endif } return 0; } diff --git a/drivers/video/aty/atyfb_base.c b/drivers/video/aty/atyfb_base.c index f8d69ad..5bf9123 100644 --- a/drivers/video/aty/atyfb_base.c +++ b/drivers/video/aty/atyfb_base.c @@ -2970,7 +2970,8 @@ static int __devinit atyfb_setup_sparc(struct pci_dev *pdev, struct atyfb_par *par = info->par; struct device_node *dp; char prop[128]; - int node, len, i, j, ret; + phandle node; + int len, i, j, ret; u32 mem, chip_id; /* diff --git a/drivers/video/aty/radeon_i2c.c b/drivers/video/aty/radeon_i2c.c index 359fc64..78d1f4c 100644 --- a/drivers/video/aty/radeon_i2c.c +++ b/drivers/video/aty/radeon_i2c.c @@ -7,7 +7,6 @@ #include <linux/i2c.h> -#include <linux/i2c-id.h> #include <linux/i2c-algo-bit.h> #include <asm/io.h> diff --git a/drivers/video/au1200fb.c b/drivers/video/au1200fb.c index e77e8e4..4ea187d 100644 --- a/drivers/video/au1200fb.c +++ b/drivers/video/au1200fb.c @@ -1079,7 +1079,7 @@ static int au1200fb_fb_check_var(struct fb_var_screeninfo *var, * clock can only be obtain by dividing this value by an even integer. * Fallback to a slower pixel clock if necessary. */ pixclock = max((u32)(PICOS2KHZ(var->pixclock) * 1000), fbi->monspecs.dclkmin); - pixclock = min(pixclock, min(fbi->monspecs.dclkmax, (u32)AU1200_LCD_MAX_CLK/2)); + pixclock = min3(pixclock, fbi->monspecs.dclkmax, (u32)AU1200_LCD_MAX_CLK/2); if (AU1200_LCD_MAX_CLK % pixclock) { int diff = AU1200_LCD_MAX_CLK % pixclock; diff --git a/drivers/video/bf54x-lq043fb.c b/drivers/video/bf54x-lq043fb.c index b020ba7..e7d0f52 100644 --- a/drivers/video/bf54x-lq043fb.c +++ b/drivers/video/bf54x-lq043fb.c @@ -241,12 +241,12 @@ static int request_ports(struct bfin_bf54xfb_info *fbi) u16 disp = fbi->mach_info->disp; if (gpio_request(disp, DRIVER_NAME)) { - printk(KERN_ERR "Requesting GPIO %d faild\n", disp); + printk(KERN_ERR "Requesting GPIO %d failed\n", disp); return -EFAULT; } if (peripheral_request_list(eppi_req_18, DRIVER_NAME)) { - printk(KERN_ERR "Requesting Peripherals faild\n"); + printk(KERN_ERR "Requesting Peripherals failed\n"); gpio_free(disp); return -EFAULT; } @@ -256,7 +256,7 @@ static int request_ports(struct bfin_bf54xfb_info *fbi) u16 eppi_req_24[] = EPPI0_24; if (peripheral_request_list(eppi_req_24, DRIVER_NAME)) { - printk(KERN_ERR "Requesting Peripherals faild\n"); + printk(KERN_ERR "Requesting Peripherals failed\n"); peripheral_free_list(eppi_req_18); gpio_free(disp); return -EFAULT; diff --git a/drivers/video/bfin-t350mcqb-fb.c b/drivers/video/bfin-t350mcqb-fb.c index 7a50272..3cf7767 100644 --- a/drivers/video/bfin-t350mcqb-fb.c +++ b/drivers/video/bfin-t350mcqb-fb.c @@ -192,7 +192,7 @@ static int bfin_t350mcqb_request_ports(int action) { if (action) { if (peripheral_request_list(ppi0_req_8, DRIVER_NAME)) { - printk(KERN_ERR "Requesting Peripherals faild\n"); + printk(KERN_ERR "Requesting Peripherals failed\n"); return -EFAULT; } } else diff --git a/drivers/video/epson1355fb.c b/drivers/video/epson1355fb.c index db9713b..a268cbf 100644 --- a/drivers/video/epson1355fb.c +++ b/drivers/video/epson1355fb.c @@ -4,7 +4,7 @@ * Epson Research S1D13505 Embedded RAMDAC LCD/CRT Controller * (previously known as SED1355) * - * Cf. http://www.erd.epson.com/vdc/html/S1D13505.html + * Cf. http://vdc.epson.com/ * * * Copyright (C) Hewlett-Packard Company. All rights reserved. diff --git a/drivers/video/fbcvt.c b/drivers/video/fbcvt.c index 7293eac..7cb715d 100644 --- a/drivers/video/fbcvt.c +++ b/drivers/video/fbcvt.c @@ -5,7 +5,7 @@ * * Based from the VESA(TM) Coordinated Video Timing Generator by * Graham Loveridge April 9, 2003 available at - * http://www.vesa.org/public/CVT/CVTd6r1.xls + * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c index b066475..0e6aa3d 100644 --- a/drivers/video/fbmem.c +++ b/drivers/video/fbmem.c @@ -697,9 +697,9 @@ fb_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) struct inode *inode = file->f_path.dentry->d_inode; int fbidx = iminor(inode); struct fb_info *info = registered_fb[fbidx]; - u32 *buffer, *dst; - u32 __iomem *src; - int c, i, cnt = 0, err = 0; + u8 *buffer, *dst; + u8 __iomem *src; + int c, cnt = 0, err = 0; unsigned long total_size; if (!info || ! info->screen_base) @@ -730,7 +730,7 @@ fb_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) if (!buffer) return -ENOMEM; - src = (u32 __iomem *) (info->screen_base + p); + src = (u8 __iomem *) (info->screen_base + p); if (info->fbops->fb_sync) info->fbops->fb_sync(info); @@ -738,17 +738,9 @@ fb_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) while (count) { c = (count > PAGE_SIZE) ? PAGE_SIZE : count; dst = buffer; - for (i = c >> 2; i--; ) - *dst++ = fb_readl(src++); - if (c & 3) { - u8 *dst8 = (u8 *) dst; - u8 __iomem *src8 = (u8 __iomem *) src; - - for (i = c & 3; i--;) - *dst8++ = fb_readb(src8++); - - src = (u32 __iomem *) src8; - } + fb_memcpy_fromfb(dst, src, c); + dst += c; + src += c; if (copy_to_user(buf, buffer, c)) { err = -EFAULT; @@ -772,9 +764,9 @@ fb_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) struct inode *inode = file->f_path.dentry->d_inode; int fbidx = iminor(inode); struct fb_info *info = registered_fb[fbidx]; - u32 *buffer, *src; - u32 __iomem *dst; - int c, i, cnt = 0, err = 0; + u8 *buffer, *src; + u8 __iomem *dst; + int c, cnt = 0, err = 0; unsigned long total_size; if (!info || !info->screen_base) @@ -811,7 +803,7 @@ fb_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) if (!buffer) return -ENOMEM; - dst = (u32 __iomem *) (info->screen_base + p); + dst = (u8 __iomem *) (info->screen_base + p); if (info->fbops->fb_sync) info->fbops->fb_sync(info); @@ -825,19 +817,9 @@ fb_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) break; } - for (i = c >> 2; i--; ) - fb_writel(*src++, dst++); - - if (c & 3) { - u8 *src8 = (u8 *) src; - u8 __iomem *dst8 = (u8 __iomem *) dst; - - for (i = c & 3; i--; ) - fb_writeb(*src8++, dst8++); - - dst = (u32 __iomem *) dst8; - } - + fb_memcpy_tofb(dst, src, c); + dst += c; + src += c; *ppos += c; buf += c; cnt += c; @@ -877,13 +859,13 @@ fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var) if ((err = info->fbops->fb_pan_display(var, info))) return err; - info->var.xoffset = var->xoffset; - info->var.yoffset = var->yoffset; - if (var->vmode & FB_VMODE_YWRAP) - info->var.vmode |= FB_VMODE_YWRAP; - else - info->var.vmode &= ~FB_VMODE_YWRAP; - return 0; + info->var.xoffset = var->xoffset; + info->var.yoffset = var->yoffset; + if (var->vmode & FB_VMODE_YWRAP) + info->var.vmode |= FB_VMODE_YWRAP; + else + info->var.vmode &= ~FB_VMODE_YWRAP; + return 0; } static int fb_check_caps(struct fb_info *info, struct fb_var_screeninfo *var, @@ -1439,6 +1421,7 @@ static const struct file_operations fb_fops = { #ifdef CONFIG_FB_DEFERRED_IO .fsync = fb_deferred_io_fsync, #endif + .llseek = default_llseek, }; struct class *fb_class; diff --git a/drivers/video/gbefb.c b/drivers/video/gbefb.c index ca3355e..933899d 100644 --- a/drivers/video/gbefb.c +++ b/drivers/video/gbefb.c @@ -1143,8 +1143,10 @@ static int __devinit gbefb_probe(struct platform_device *p_dev) return -ENOMEM; #ifndef MODULE - if (fb_get_options("gbefb", &options)) - return -ENODEV; + if (fb_get_options("gbefb", &options)) { + ret = -ENODEV; + goto out_release_framebuffer; + } gbefb_setup(options); #endif diff --git a/drivers/video/i810/i810.h b/drivers/video/i810/i810.h index 328ae6c..f37de60e 100644 --- a/drivers/video/i810/i810.h +++ b/drivers/video/i810/i810.h @@ -17,7 +17,6 @@ #include <linux/agp_backend.h> #include <linux/fb.h> #include <linux/i2c.h> -#include <linux/i2c-id.h> #include <linux/i2c-algo-bit.h> #include <video/vga.h> diff --git a/drivers/video/intelfb/intelfb_i2c.c b/drivers/video/intelfb/intelfb_i2c.c index 487f2be..3300bd3 100644 --- a/drivers/video/intelfb/intelfb_i2c.c +++ b/drivers/video/intelfb/intelfb_i2c.c @@ -32,7 +32,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include <linux/fb.h> #include <linux/i2c.h> -#include <linux/i2c-id.h> #include <linux/i2c-algo-bit.h> #include <asm/io.h> diff --git a/drivers/video/matrox/matroxfb_DAC1064.c b/drivers/video/matrox/matroxfb_DAC1064.c index f9fa0fd..1717623 100644 --- a/drivers/video/matrox/matroxfb_DAC1064.c +++ b/drivers/video/matrox/matroxfb_DAC1064.c @@ -869,12 +869,9 @@ static int MGAG100_preinit(struct matrox_fb_info *minfo) minfo->capable.plnwt = minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100 ? minfo->devflags.sgram : 1; -#ifdef CONFIG_FB_MATROX_G if (minfo->devflags.g450dac) { minfo->outputs[0].output = &g450out; - } else -#endif - { + } else { minfo->outputs[0].output = &m1064; } minfo->outputs[0].src = minfo->outputs[0].default_src; diff --git a/drivers/video/matrox/matroxfb_maven.c b/drivers/video/matrox/matroxfb_maven.c index 1e3e8f1..31b8f67 100644 --- a/drivers/video/matrox/matroxfb_maven.c +++ b/drivers/video/matrox/matroxfb_maven.c @@ -280,7 +280,7 @@ static int matroxfb_PLL_mavenclock(const struct matrox_pll_features2* pll, return fxtal * (*feed) / (*in) * ctl->den; } -static unsigned int matroxfb_mavenclock(const struct matrox_pll_ctl* ctl, +static int matroxfb_mavenclock(const struct matrox_pll_ctl *ctl, unsigned int htotal, unsigned int vtotal, unsigned int* in, unsigned int* feed, unsigned int* post, unsigned int* htotal2) { diff --git a/drivers/video/mbx/mbxdebugfs.c b/drivers/video/mbx/mbxdebugfs.c index ecad965..12dec76 100644 --- a/drivers/video/mbx/mbxdebugfs.c +++ b/drivers/video/mbx/mbxdebugfs.c @@ -175,36 +175,42 @@ static const struct file_operations sysconf_fops = { .read = sysconf_read_file, .write = write_file_dummy, .open = open_file_generic, + .llseek = default_llseek, }; static const struct file_operations clock_fops = { .read = clock_read_file, .write = write_file_dummy, .open = open_file_generic, + .llseek = default_llseek, }; static const struct file_operations display_fops = { .read = display_read_file, .write = write_file_dummy, .open = open_file_generic, + .llseek = default_llseek, }; static const struct file_operations gsctl_fops = { .read = gsctl_read_file, .write = write_file_dummy, .open = open_file_generic, + .llseek = default_llseek, }; static const struct file_operations sdram_fops = { .read = sdram_read_file, .write = write_file_dummy, .open = open_file_generic, + .llseek = default_llseek, }; static const struct file_operations misc_fops = { .read = misc_read_file, .write = write_file_dummy, .open = open_file_generic, + .llseek = default_llseek, }; static void __devinit mbxfb_debugfs_init(struct fb_info *fbi) diff --git a/drivers/video/metronomefb.c b/drivers/video/metronomefb.c index 9b3d6e4..63ed3b7 100644 --- a/drivers/video/metronomefb.c +++ b/drivers/video/metronomefb.c @@ -10,7 +10,7 @@ * Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven. * * This work was made possible by help and equipment support from E-Ink - * Corporation. http://support.eink.com/community + * Corporation. http://www.eink.com/ * * This driver is written to be used with the Metronome display controller. * It is intended to be architecture independent. A board specific driver diff --git a/drivers/video/omap/blizzard.c b/drivers/video/omap/blizzard.c index 2ffb34a..87785c2 100644 --- a/drivers/video/omap/blizzard.c +++ b/drivers/video/omap/blizzard.c @@ -1590,7 +1590,7 @@ static int blizzard_init(struct omapfb_device *fbdev, int ext_mode, blizzard.auto_update_window.width = fbdev->panel->x_res; blizzard.auto_update_window.height = fbdev->panel->y_res; blizzard.auto_update_window.out_x = 0; - blizzard.auto_update_window.out_x = 0; + blizzard.auto_update_window.out_y = 0; blizzard.auto_update_window.out_width = fbdev->panel->x_res; blizzard.auto_update_window.out_height = fbdev->panel->y_res; blizzard.auto_update_window.format = 0; diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c index ca75cc2..d7c6c3e 100644 --- a/drivers/video/omap/lcd_omap3beagle.c +++ b/drivers/video/omap/lcd_omap3beagle.c @@ -25,8 +25,6 @@ #include <linux/gpio.h> #include <linux/i2c/twl.h> -#include <plat/mux.h> -#include <plat/mux.h> #include <asm/mach-types.h> #include "omapfb.h" diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig index 881c9f7..12327bb 100644 --- a/drivers/video/omap2/displays/Kconfig +++ b/drivers/video/omap2/displays/Kconfig @@ -40,7 +40,7 @@ config PANEL_TPO_TD043MTEA1 config PANEL_ACX565AKM tristate "ACX565AKM Panel" - depends on OMAP2_DSS_SDI + depends on OMAP2_DSS_SDI && SPI select BACKLIGHT_CLASS_DEVICE help This is the LCD panel used on Nokia N900 diff --git a/drivers/video/omap2/displays/panel-acx565akm.c b/drivers/video/omap2/displays/panel-acx565akm.c index 07fbb8a..e773106 100644 --- a/drivers/video/omap2/displays/panel-acx565akm.c +++ b/drivers/video/omap2/displays/panel-acx565akm.c @@ -587,6 +587,9 @@ static int acx_panel_power_on(struct omap_dss_device *dssdev) dev_dbg(&dssdev->dev, "%s\n", __func__); + if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) + return 0; + mutex_lock(&md->mutex); r = omapdss_sdi_display_enable(dssdev); @@ -644,6 +647,9 @@ static void acx_panel_power_off(struct omap_dss_device *dssdev) dev_dbg(&dssdev->dev, "%s\n", __func__); + if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) + return; + mutex_lock(&md->mutex); if (!md->enabled) { diff --git a/drivers/video/omap2/displays/panel-generic.c b/drivers/video/omap2/displays/panel-generic.c index 300eff5..395a68d 100644 --- a/drivers/video/omap2/displays/panel-generic.c +++ b/drivers/video/omap2/displays/panel-generic.c @@ -39,6 +39,9 @@ static int generic_panel_power_on(struct omap_dss_device *dssdev) { int r; + if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) + return 0; + r = omapdss_dpi_display_enable(dssdev); if (r) goto err0; @@ -58,6 +61,9 @@ err0: static void generic_panel_power_off(struct omap_dss_device *dssdev) { + if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) + return; + if (dssdev->platform_disable) dssdev->platform_disable(dssdev); diff --git a/drivers/video/omap2/displays/panel-sharp-lq043t1dg01.c b/drivers/video/omap2/displays/panel-sharp-lq043t1dg01.c index 1026746..0c6896c 100644 --- a/drivers/video/omap2/displays/panel-sharp-lq043t1dg01.c +++ b/drivers/video/omap2/displays/panel-sharp-lq043t1dg01.c @@ -43,6 +43,9 @@ static int sharp_lq_panel_power_on(struct omap_dss_device *dssdev) { int r; + if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) + return 0; + r = omapdss_dpi_display_enable(dssdev); if (r) goto err0; @@ -65,6 +68,9 @@ err0: static void sharp_lq_panel_power_off(struct omap_dss_device *dssdev) { + if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) + return; + if (dssdev->platform_disable) dssdev->platform_disable(dssdev); diff --git a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c index 7d9eb2b..9a138f6 100644 --- a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c +++ b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c @@ -135,6 +135,9 @@ static int sharp_ls_power_on(struct omap_dss_device *dssdev) { int r = 0; + if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) + return 0; + r = omapdss_dpi_display_enable(dssdev); if (r) goto err0; @@ -157,6 +160,9 @@ err0: static void sharp_ls_power_off(struct omap_dss_device *dssdev) { + if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) + return; + if (dssdev->platform_disable) dssdev->platform_disable(dssdev); diff --git a/drivers/video/omap2/displays/panel-toppoly-tdo35s.c b/drivers/video/omap2/displays/panel-toppoly-tdo35s.c index e320e67..526e906 100644 --- a/drivers/video/omap2/displays/panel-toppoly-tdo35s.c +++ b/drivers/video/omap2/displays/panel-toppoly-tdo35s.c @@ -46,6 +46,9 @@ static int toppoly_tdo_panel_power_on(struct omap_dss_device *dssdev) { int r; + if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) + return 0; + r = omapdss_dpi_display_enable(dssdev); if (r) goto err0; @@ -65,6 +68,9 @@ err0: static void toppoly_tdo_panel_power_off(struct omap_dss_device *dssdev) { + if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) + return; + if (dssdev->platform_disable) dssdev->platform_disable(dssdev); diff --git a/drivers/video/omap2/displays/panel-tpo-td043mtea1.c b/drivers/video/omap2/displays/panel-tpo-td043mtea1.c index e866e76..dbe9d43 100644 --- a/drivers/video/omap2/displays/panel-tpo-td043mtea1.c +++ b/drivers/video/omap2/displays/panel-tpo-td043mtea1.c @@ -269,6 +269,9 @@ static int tpo_td043_power_on(struct omap_dss_device *dssdev) int nreset_gpio = dssdev->reset_gpio; int r; + if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) + return 0; + r = omapdss_dpi_display_enable(dssdev); if (r) goto err0; @@ -308,6 +311,9 @@ static void tpo_td043_power_off(struct omap_dss_device *dssdev) struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev); int nreset_gpio = dssdev->reset_gpio; + if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) + return; + tpo_td043_write(tpo_td043->spi, 3, TPO_R03_VAL_STANDBY | TPO_R03_EN_PWM); diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile index d71b5d9..7db17b5 100644 --- a/drivers/video/omap2/dss/Makefile +++ b/drivers/video/omap2/dss/Makefile @@ -1,5 +1,5 @@ obj-$(CONFIG_OMAP2_DSS) += omapdss.o -omapdss-y := core.o dss.o dispc.o display.o manager.o overlay.o +omapdss-y := core.o dss.o dss_features.o dispc.o display.o manager.o overlay.o omapdss-$(CONFIG_OMAP2_DSS_DPI) += dpi.o omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index b3a498f..8e89f60 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -37,6 +37,7 @@ #include <plat/clock.h> #include "dss.h" +#include "dss_features.h" static struct { struct platform_device *pdev; @@ -502,6 +503,8 @@ static int omap_dss_probe(struct platform_device *pdev) core.pdev = pdev; + dss_features_init(); + dss_init_overlay_managers(pdev); dss_init_overlays(pdev); diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 5ecdc00..fa40fa5 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -39,6 +39,7 @@ #include <plat/display.h> #include "dss.h" +#include "dss_features.h" /* DISPC */ #define DISPC_BASE 0x48050400 @@ -139,6 +140,22 @@ struct omap_dispc_isr_data { u32 mask; }; +struct dispc_h_coef { + s8 hc4; + s8 hc3; + u8 hc2; + s8 hc1; + s8 hc0; +}; + +struct dispc_v_coef { + s8 vc22; + s8 vc2; + u8 vc1; + s8 vc0; + s8 vc00; +}; + #define REG_GET(idx, start, end) \ FLD_GET(dispc_read_reg(idx), start, end) @@ -564,106 +581,77 @@ static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup, int vscaleup, int five_taps) { /* Coefficients for horizontal up-sampling */ - static const u32 coef_hup[8] = { - 0x00800000, - 0x0D7CF800, - 0x1E70F5FF, - 0x335FF5FE, - 0xF74949F7, - 0xF55F33FB, - 0xF5701EFE, - 0xF87C0DFF, + static const struct dispc_h_coef coef_hup[8] = { + { 0, 0, 128, 0, 0 }, + { -1, 13, 124, -8, 0 }, + { -2, 30, 112, -11, -1 }, + { -5, 51, 95, -11, -2 }, + { 0, -9, 73, 73, -9 }, + { -2, -11, 95, 51, -5 }, + { -1, -11, 112, 30, -2 }, + { 0, -8, 124, 13, -1 }, }; - /* Coefficients for horizontal down-sampling */ - static const u32 coef_hdown[8] = { - 0x24382400, - 0x28371FFE, - 0x2C361BFB, - 0x303516F9, - 0x11343311, - 0x1635300C, - 0x1B362C08, - 0x1F372804, + /* Coefficients for vertical up-sampling */ + static const struct dispc_v_coef coef_vup_3tap[8] = { + { 0, 0, 128, 0, 0 }, + { 0, 3, 123, 2, 0 }, + { 0, 12, 111, 5, 0 }, + { 0, 32, 89, 7, 0 }, + { 0, 0, 64, 64, 0 }, + { 0, 7, 89, 32, 0 }, + { 0, 5, 111, 12, 0 }, + { 0, 2, 123, 3, 0 }, }; - /* Coefficients for horizontal and vertical up-sampling */ - static const u32 coef_hvup[2][8] = { - { - 0x00800000, - 0x037B02FF, - 0x0C6F05FE, - 0x205907FB, - 0x00404000, - 0x075920FE, - 0x056F0CFF, - 0x027B0300, - }, - { - 0x00800000, - 0x0D7CF8FF, - 0x1E70F5FE, - 0x335FF5FB, - 0xF7404000, - 0xF55F33FE, - 0xF5701EFF, - 0xF87C0D00, - }, + static const struct dispc_v_coef coef_vup_5tap[8] = { + { 0, 0, 128, 0, 0 }, + { -1, 13, 124, -8, 0 }, + { -2, 30, 112, -11, -1 }, + { -5, 51, 95, -11, -2 }, + { 0, -9, 73, 73, -9 }, + { -2, -11, 95, 51, -5 }, + { -1, -11, 112, 30, -2 }, + { 0, -8, 124, 13, -1 }, }; - /* Coefficients for horizontal and vertical down-sampling */ - static const u32 coef_hvdown[2][8] = { - { - 0x24382400, - 0x28391F04, - 0x2D381B08, - 0x3237170C, - 0x123737F7, - 0x173732F9, - 0x1B382DFB, - 0x1F3928FE, - }, - { - 0x24382400, - 0x28371F04, - 0x2C361B08, - 0x3035160C, - 0x113433F7, - 0x163530F9, - 0x1B362CFB, - 0x1F3728FE, - }, + /* Coefficients for horizontal down-sampling */ + static const struct dispc_h_coef coef_hdown[8] = { + { 0, 36, 56, 36, 0 }, + { 4, 40, 55, 31, -2 }, + { 8, 44, 54, 27, -5 }, + { 12, 48, 53, 22, -7 }, + { -9, 17, 52, 51, 17 }, + { -7, 22, 53, 48, 12 }, + { -5, 27, 54, 44, 8 }, + { -2, 31, 55, 40, 4 }, }; - /* Coefficients for vertical up-sampling */ - static const u32 coef_vup[8] = { - 0x00000000, - 0x0000FF00, - 0x0000FEFF, - 0x0000FBFE, - 0x000000F7, - 0x0000FEFB, - 0x0000FFFE, - 0x000000FF, + /* Coefficients for vertical down-sampling */ + static const struct dispc_v_coef coef_vdown_3tap[8] = { + { 0, 36, 56, 36, 0 }, + { 0, 40, 57, 31, 0 }, + { 0, 45, 56, 27, 0 }, + { 0, 50, 55, 23, 0 }, + { 0, 18, 55, 55, 0 }, + { 0, 23, 55, 50, 0 }, + { 0, 27, 56, 45, 0 }, + { 0, 31, 57, 40, 0 }, }; - - /* Coefficients for vertical down-sampling */ - static const u32 coef_vdown[8] = { - 0x00000000, - 0x000004FE, - 0x000008FB, - 0x00000CF9, - 0x0000F711, - 0x0000F90C, - 0x0000FB08, - 0x0000FE04, + static const struct dispc_v_coef coef_vdown_5tap[8] = { + { 0, 36, 56, 36, 0 }, + { 4, 40, 55, 31, -2 }, + { 8, 44, 54, 27, -5 }, + { 12, 48, 53, 22, -7 }, + { -9, 17, 52, 51, 17 }, + { -7, 22, 53, 48, 12 }, + { -5, 27, 54, 44, 8 }, + { -2, 31, 55, 40, 4 }, }; - const u32 *h_coef; - const u32 *hv_coef; - const u32 *hv_coef_mod; - const u32 *v_coef; + const struct dispc_h_coef *h_coef; + const struct dispc_v_coef *v_coef; int i; if (hscaleup) @@ -671,47 +659,34 @@ static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup, else h_coef = coef_hdown; - if (vscaleup) { - hv_coef = coef_hvup[five_taps]; - v_coef = coef_vup; - - if (hscaleup) - hv_coef_mod = NULL; - else - hv_coef_mod = coef_hvdown[five_taps]; - } else { - hv_coef = coef_hvdown[five_taps]; - v_coef = coef_vdown; - - if (hscaleup) - hv_coef_mod = coef_hvup[five_taps]; - else - hv_coef_mod = NULL; - } + if (vscaleup) + v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap; + else + v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap; for (i = 0; i < 8; i++) { u32 h, hv; - h = h_coef[i]; - - hv = hv_coef[i]; - - if (hv_coef_mod) { - hv &= 0xffffff00; - hv |= (hv_coef_mod[i] & 0xff); - } + h = FLD_VAL(h_coef[i].hc0, 7, 0) + | FLD_VAL(h_coef[i].hc1, 15, 8) + | FLD_VAL(h_coef[i].hc2, 23, 16) + | FLD_VAL(h_coef[i].hc3, 31, 24); + hv = FLD_VAL(h_coef[i].hc4, 7, 0) + | FLD_VAL(v_coef[i].vc0, 15, 8) + | FLD_VAL(v_coef[i].vc1, 23, 16) + | FLD_VAL(v_coef[i].vc2, 31, 24); _dispc_write_firh_reg(plane, i, h); _dispc_write_firhv_reg(plane, i, hv); } - if (!five_taps) - return; - - for (i = 0; i < 8; i++) { - u32 v; - v = v_coef[i]; - _dispc_write_firv_reg(plane, i, v); + if (five_taps) { + for (i = 0; i < 8; i++) { + u32 v; + v = FLD_VAL(v_coef[i].vc00, 7, 0) + | FLD_VAL(v_coef[i].vc22, 15, 8); + _dispc_write_firv_reg(plane, i, v); + } } } @@ -800,12 +775,12 @@ static void _dispc_set_vid_size(enum omap_plane plane, int width, int height) static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha) { - - BUG_ON(plane == OMAP_DSS_VIDEO1); - - if (cpu_is_omap24xx()) + if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) return; + BUG_ON(!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) && + plane == OMAP_DSS_VIDEO1); + if (plane == OMAP_DSS_GFX) REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0); else if (plane == OMAP_DSS_VIDEO2) @@ -975,17 +950,14 @@ static void dispc_read_plane_fifo_sizes(void) DISPC_VID_FIFO_SIZE_STATUS(1) }; u32 size; int plane; + u8 start, end; enable_clocks(1); - for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) { - if (cpu_is_omap24xx()) - size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0); - else if (cpu_is_omap34xx()) - size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0); - else - BUG(); + dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); + for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) { + size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end); dispc.fifo_size[plane] = size; } @@ -1002,6 +974,8 @@ void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high) const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD, DISPC_VID_FIFO_THRESHOLD(0), DISPC_VID_FIFO_THRESHOLD(1) }; + u8 hi_start, hi_end, lo_start, lo_end; + enable_clocks(1); DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n", @@ -1010,12 +984,12 @@ void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high) REG_GET(ftrs_reg[plane], 27, 16), low, high); - if (cpu_is_omap24xx()) - dispc_write_reg(ftrs_reg[plane], - FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0)); - else - dispc_write_reg(ftrs_reg[plane], - FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0)); + dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); + dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); + + dispc_write_reg(ftrs_reg[plane], + FLD_VAL(high, hi_start, hi_end) | + FLD_VAL(low, lo_start, lo_end)); enable_clocks(0); } @@ -1035,13 +1009,16 @@ static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc) u32 val; const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0), DISPC_VID_FIR(1) }; + u8 hinc_start, hinc_end, vinc_start, vinc_end; BUG_ON(plane == OMAP_DSS_GFX); - if (cpu_is_omap24xx()) - val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0); - else - val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); + dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end); + dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end); + + val = FLD_VAL(vinc, vinc_start, vinc_end) | + FLD_VAL(hinc, hinc_start, hinc_end); + dispc_write_reg(fir_reg[plane-1], val); } @@ -1567,6 +1544,8 @@ static int _dispc_setup_plane(enum omap_plane plane, case OMAP_DSS_COLOR_ARGB16: case OMAP_DSS_COLOR_ARGB32: case OMAP_DSS_COLOR_RGBA32: + if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) + return -EINVAL; case OMAP_DSS_COLOR_RGBX32: if (cpu_is_omap24xx()) return -EINVAL; @@ -1607,9 +1586,10 @@ static int _dispc_setup_plane(enum omap_plane plane, case OMAP_DSS_COLOR_ARGB16: case OMAP_DSS_COLOR_ARGB32: case OMAP_DSS_COLOR_RGBA32: - if (cpu_is_omap24xx()) + if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) return -EINVAL; - if (plane == OMAP_DSS_VIDEO1) + if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) && + plane == OMAP_DSS_VIDEO1) return -EINVAL; break; @@ -2002,7 +1982,7 @@ void dispc_enable_trans_key(enum omap_channel ch, bool enable) } void dispc_enable_alpha_blending(enum omap_channel ch, bool enable) { - if (cpu_is_omap24xx()) + if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) return; enable_clocks(1); @@ -2016,7 +1996,7 @@ bool dispc_alpha_blending_enabled(enum omap_channel ch) { bool enabled; - if (cpu_is_omap24xx()) + if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) return false; enable_clocks(1); diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index b3fa3a7..aa4f7a5 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -3274,7 +3274,6 @@ int dsi_init(struct platform_device *pdev) dsi.vdds_dsi_reg = dss_get_vdds_dsi(); if (IS_ERR(dsi.vdds_dsi_reg)) { - iounmap(dsi.base); DSSERR("can't get VDDS_DSI regulator\n"); r = PTR_ERR(dsi.vdds_dsi_reg); goto err2; diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c new file mode 100644 index 0000000..867f68d --- /dev/null +++ b/drivers/video/omap2/dss/dss_features.c @@ -0,0 +1,191 @@ +/* + * linux/drivers/video/omap2/dss/dss_features.c + * + * Copyright (C) 2010 Texas Instruments + * Author: Archit Taneja <archit@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/err.h> +#include <linux/slab.h> + +#include <plat/display.h> +#include <plat/cpu.h> + +#include "dss_features.h" + +/* Defines a generic omap register field */ +struct dss_reg_field { + enum dss_feat_reg_field id; + u8 start, end; +}; + +struct omap_dss_features { + const struct dss_reg_field *reg_fields; + const int num_reg_fields; + + const u32 has_feature; + + const int num_mgrs; + const int num_ovls; + const enum omap_display_type *supported_displays; + const enum omap_color_mode *supported_color_modes; +}; + +/* This struct is assigned to one of the below during initialization */ +static struct omap_dss_features *omap_current_dss_features; + +static const struct dss_reg_field omap2_dss_reg_fields[] = { + { FEAT_REG_FIRHINC, 11, 0 }, + { FEAT_REG_FIRVINC, 27, 16 }, + { FEAT_REG_FIFOLOWTHRESHOLD, 8, 0 }, + { FEAT_REG_FIFOHIGHTHRESHOLD, 24, 16 }, + { FEAT_REG_FIFOSIZE, 8, 0 }, +}; + +static const struct dss_reg_field omap3_dss_reg_fields[] = { + { FEAT_REG_FIRHINC, 12, 0 }, + { FEAT_REG_FIRVINC, 28, 16 }, + { FEAT_REG_FIFOLOWTHRESHOLD, 11, 0 }, + { FEAT_REG_FIFOHIGHTHRESHOLD, 27, 16 }, + { FEAT_REG_FIFOSIZE, 10, 0 }, +}; + +static const enum omap_display_type omap2_dss_supported_displays[] = { + /* OMAP_DSS_CHANNEL_LCD */ + OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | + OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI, + + /* OMAP_DSS_CHANNEL_DIGIT */ + OMAP_DISPLAY_TYPE_VENC, +}; + +static const enum omap_display_type omap3_dss_supported_displays[] = { + /* OMAP_DSS_CHANNEL_LCD */ + OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | + OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI, + + /* OMAP_DSS_CHANNEL_DIGIT */ + OMAP_DISPLAY_TYPE_VENC, +}; + +static const enum omap_color_mode omap2_dss_supported_color_modes[] = { + /* OMAP_DSS_GFX */ + OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 | + OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 | + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 | + OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P, + + /* OMAP_DSS_VIDEO1 */ + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | + OMAP_DSS_COLOR_UYVY, + + /* OMAP_DSS_VIDEO2 */ + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | + OMAP_DSS_COLOR_UYVY, +}; + +static const enum omap_color_mode omap3_dss_supported_color_modes[] = { + /* OMAP_DSS_GFX */ + OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 | + OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 | + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 | + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 | + OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, + + /* OMAP_DSS_VIDEO1 */ + OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P | + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 | + OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY, + + /* OMAP_DSS_VIDEO2 */ + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 | + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | + OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 | + OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, +}; + +/* OMAP2 DSS Features */ +static struct omap_dss_features omap2_dss_features = { + .reg_fields = omap2_dss_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields), + + .num_mgrs = 2, + .num_ovls = 3, + .supported_displays = omap2_dss_supported_displays, + .supported_color_modes = omap2_dss_supported_color_modes, +}; + +/* OMAP3 DSS Features */ +static struct omap_dss_features omap3_dss_features = { + .reg_fields = omap3_dss_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), + + .has_feature = FEAT_GLOBAL_ALPHA, + + .num_mgrs = 2, + .num_ovls = 3, + .supported_displays = omap3_dss_supported_displays, + .supported_color_modes = omap3_dss_supported_color_modes, +}; + +/* Functions returning values related to a DSS feature */ +int dss_feat_get_num_mgrs(void) +{ + return omap_current_dss_features->num_mgrs; +} + +int dss_feat_get_num_ovls(void) +{ + return omap_current_dss_features->num_ovls; +} + +enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel) +{ + return omap_current_dss_features->supported_displays[channel]; +} + +enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane) +{ + return omap_current_dss_features->supported_color_modes[plane]; +} + +/* DSS has_feature check */ +bool dss_has_feature(enum dss_feat_id id) +{ + return omap_current_dss_features->has_feature & id; +} + +void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end) +{ + if (id >= omap_current_dss_features->num_reg_fields) + BUG(); + + *start = omap_current_dss_features->reg_fields[id].start; + *end = omap_current_dss_features->reg_fields[id].end; +} + +void dss_features_init(void) +{ + if (cpu_is_omap24xx()) + omap_current_dss_features = &omap2_dss_features; + else + omap_current_dss_features = &omap3_dss_features; +} diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h new file mode 100644 index 0000000..cb231ea --- /dev/null +++ b/drivers/video/omap2/dss/dss_features.h @@ -0,0 +1,50 @@ +/* + * linux/drivers/video/omap2/dss/dss_features.h + * + * Copyright (C) 2010 Texas Instruments + * Author: Archit Taneja <archit@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __OMAP2_DSS_FEATURES_H +#define __OMAP2_DSS_FEATURES_H + +#define MAX_DSS_MANAGERS 2 +#define MAX_DSS_OVERLAYS 3 + +/* DSS has feature id */ +enum dss_feat_id { + FEAT_GLOBAL_ALPHA = 1 << 0, + FEAT_GLOBAL_ALPHA_VID1 = 1 << 1, +}; + +/* DSS register field id */ +enum dss_feat_reg_field { + FEAT_REG_FIRHINC, + FEAT_REG_FIRVINC, + FEAT_REG_FIFOHIGHTHRESHOLD, + FEAT_REG_FIFOLOWTHRESHOLD, + FEAT_REG_FIFOSIZE, +}; + +/* DSS Feature Functions */ +int dss_feat_get_num_mgrs(void); +int dss_feat_get_num_ovls(void); +enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); +enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); + +bool dss_has_feature(enum dss_feat_id id); +void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); +void dss_features_init(void); +#endif diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c index 6a649ab..545e9b9 100644 --- a/drivers/video/omap2/dss/manager.c +++ b/drivers/video/omap2/dss/manager.c @@ -33,6 +33,7 @@ #include <plat/cpu.h> #include "dss.h" +#include "dss_features.h" static int num_managers; static struct list_head manager_list; @@ -448,8 +449,8 @@ struct manager_cache_data { static struct { spinlock_t lock; - struct overlay_cache_data overlay_cache[3]; - struct manager_cache_data manager_cache[2]; + struct overlay_cache_data overlay_cache[MAX_DSS_OVERLAYS]; + struct manager_cache_data manager_cache[MAX_DSS_MANAGERS]; bool irq_enabled; } dss_cache; @@ -882,12 +883,12 @@ static int configure_dispc(void) { struct overlay_cache_data *oc; struct manager_cache_data *mc; - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); - const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache); + const int num_ovls = dss_feat_get_num_ovls(); + const int num_mgrs = dss_feat_get_num_mgrs(); int i; int r; - bool mgr_busy[2]; - bool mgr_go[2]; + bool mgr_busy[MAX_DSS_MANAGERS]; + bool mgr_go[MAX_DSS_MANAGERS]; bool busy; r = 0; @@ -989,7 +990,7 @@ void dss_setup_partial_planes(struct omap_dss_device *dssdev, { struct overlay_cache_data *oc; struct manager_cache_data *mc; - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); + const int num_ovls = dss_feat_get_num_ovls(); struct omap_overlay_manager *mgr; int i; u16 x, y, w, h; @@ -1121,8 +1122,8 @@ void dss_start_update(struct omap_dss_device *dssdev) { struct manager_cache_data *mc; struct overlay_cache_data *oc; - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); - const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache); + const int num_ovls = dss_feat_get_num_ovls(); + const int num_mgrs = dss_feat_get_num_mgrs(); struct omap_overlay_manager *mgr; int i; @@ -1151,10 +1152,10 @@ static void dss_apply_irq_handler(void *data, u32 mask) { struct manager_cache_data *mc; struct overlay_cache_data *oc; - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); - const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache); + const int num_ovls = dss_feat_get_num_ovls(); + const int num_mgrs = dss_feat_get_num_mgrs(); int i, r; - bool mgr_busy[2]; + bool mgr_busy[MAX_DSS_MANAGERS]; mgr_busy[0] = dispc_go_busy(0); mgr_busy[1] = dispc_go_busy(1); @@ -1461,7 +1462,7 @@ int dss_init_overlay_managers(struct platform_device *pdev) num_managers = 0; - for (i = 0; i < 2; ++i) { + for (i = 0; i < dss_feat_get_num_mgrs(); ++i) { struct omap_overlay_manager *mgr; mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); @@ -1471,14 +1472,10 @@ int dss_init_overlay_managers(struct platform_device *pdev) case 0: mgr->name = "lcd"; mgr->id = OMAP_DSS_CHANNEL_LCD; - mgr->supported_displays = - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | - OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI; break; case 1: mgr->name = "tv"; mgr->id = OMAP_DSS_CHANNEL_DIGIT; - mgr->supported_displays = OMAP_DISPLAY_TYPE_VENC; break; } @@ -1494,6 +1491,8 @@ int dss_init_overlay_managers(struct platform_device *pdev) mgr->disable = &dss_mgr_disable; mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC; + mgr->supported_displays = + dss_feat_get_supported_displays(mgr->id); dss_overlay_setup_dispc_manager(mgr); diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c index 244dca8..75642c2 100644 --- a/drivers/video/omap2/dss/overlay.c +++ b/drivers/video/omap2/dss/overlay.c @@ -35,6 +35,7 @@ #include <plat/cpu.h> #include "dss.h" +#include "dss_features.h" static int num_overlays; static struct list_head overlay_list; @@ -237,7 +238,8 @@ static ssize_t overlay_global_alpha_store(struct omap_overlay *ovl, /* Video1 plane does not support global alpha * to always make it 255 completely opaque */ - if (ovl->id == OMAP_DSS_VIDEO1) + if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) && + ovl->id == OMAP_DSS_VIDEO1) info.global_alpha = 255; else info.global_alpha = simple_strtoul(buf, NULL, 10); @@ -510,11 +512,11 @@ static void omap_dss_add_overlay(struct omap_overlay *overlay) list_add_tail(&overlay->list, &overlay_list); } -static struct omap_overlay *dispc_overlays[3]; +static struct omap_overlay *dispc_overlays[MAX_DSS_OVERLAYS]; void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr) { - mgr->num_overlays = 3; + mgr->num_overlays = dss_feat_get_num_ovls(); mgr->overlays = dispc_overlays; } @@ -535,7 +537,7 @@ void dss_init_overlays(struct platform_device *pdev) num_overlays = 0; - for (i = 0; i < 3; ++i) { + for (i = 0; i < dss_feat_get_num_ovls(); ++i) { struct omap_overlay *ovl; ovl = kzalloc(sizeof(*ovl), GFP_KERNEL); @@ -545,18 +547,12 @@ void dss_init_overlays(struct platform_device *pdev) case 0: ovl->name = "gfx"; ovl->id = OMAP_DSS_GFX; - ovl->supported_modes = cpu_is_omap34xx() ? - OMAP_DSS_COLOR_GFX_OMAP3 : - OMAP_DSS_COLOR_GFX_OMAP2; ovl->caps = OMAP_DSS_OVL_CAP_DISPC; ovl->info.global_alpha = 255; break; case 1: ovl->name = "vid1"; ovl->id = OMAP_DSS_VIDEO1; - ovl->supported_modes = cpu_is_omap34xx() ? - OMAP_DSS_COLOR_VID1_OMAP3 : - OMAP_DSS_COLOR_VID_OMAP2; ovl->caps = OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_DISPC; ovl->info.global_alpha = 255; @@ -564,9 +560,6 @@ void dss_init_overlays(struct platform_device *pdev) case 2: ovl->name = "vid2"; ovl->id = OMAP_DSS_VIDEO2; - ovl->supported_modes = cpu_is_omap34xx() ? - OMAP_DSS_COLOR_VID2_OMAP3 : - OMAP_DSS_COLOR_VID_OMAP2; ovl->caps = OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_DISPC; ovl->info.global_alpha = 255; @@ -579,6 +572,9 @@ void dss_init_overlays(struct platform_device *pdev) ovl->get_overlay_info = &dss_ovl_get_overlay_info; ovl->wait_for_go = &dss_ovl_wait_for_go; + ovl->supported_modes = + dss_feat_get_supported_color_modes(ovl->id); + omap_dss_add_overlay(ovl); r = kobject_init_and_add(&ovl->kobj, &overlay_ktype, @@ -651,7 +647,7 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force) } if (mgr) { - for (i = 0; i < 3; i++) { + for (i = 0; i < dss_feat_get_num_ovls(); i++) { struct omap_overlay *ovl; ovl = omap_dss_get_overlay(i); if (!ovl->manager || force) { diff --git a/drivers/video/omap2/omapfb/Kconfig b/drivers/video/omap2/omapfb/Kconfig index 43496d6..65149b2 100644 --- a/drivers/video/omap2/omapfb/Kconfig +++ b/drivers/video/omap2/omapfb/Kconfig @@ -3,7 +3,7 @@ menuconfig FB_OMAP2 depends on FB && OMAP2_DSS select OMAP2_VRAM - select OMAP2_VRFB + select OMAP2_VRFB if ARCH_OMAP2 || ARCH_OMAP3 select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c index 04034d4..6a704f1 100644 --- a/drivers/video/omap2/omapfb/omapfb-main.c +++ b/drivers/video/omap2/omapfb/omapfb-main.c @@ -714,10 +714,10 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var) var->pixclock = timings.pixel_clock != 0 ? KHZ2PICOS(timings.pixel_clock) : 0; - var->left_margin = timings.hfp; - var->right_margin = timings.hbp; - var->upper_margin = timings.vfp; - var->lower_margin = timings.vbp; + var->left_margin = timings.hbp; + var->right_margin = timings.hfp; + var->upper_margin = timings.vbp; + var->lower_margin = timings.vfp; var->hsync_len = timings.hsw; var->vsync_len = timings.vsw; } else { @@ -2059,10 +2059,10 @@ static int omapfb_mode_to_timings(const char *mode_str, if (r != 0) { timings->pixel_clock = PICOS2KHZ(var.pixclock); - timings->hfp = var.left_margin; - timings->hbp = var.right_margin; - timings->vfp = var.upper_margin; - timings->vbp = var.lower_margin; + timings->hbp = var.left_margin; + timings->hfp = var.right_margin; + timings->vbp = var.upper_margin; + timings->vfp = var.lower_margin; timings->hsw = var.hsync_len; timings->vsw = var.vsync_len; timings->x_res = var.xres; @@ -2198,6 +2198,16 @@ static int omapfb_probe(struct platform_device *pdev) goto err0; } + /* TODO : Replace cpu check with omap_has_vrfb once HAS_FEATURE + * available for OMAP2 and OMAP3 + */ + if (def_vrfb && !cpu_is_omap24xx() && !cpu_is_omap34xx()) { + def_vrfb = 0; + dev_warn(&pdev->dev, "VRFB is not supported on this hardware, " + "ignoring the module parameter vrfb=y\n"); + } + + mutex_init(&fbdev->mtx); fbdev->dev = &pdev->dev; diff --git a/drivers/video/omap2/vram.c b/drivers/video/omap2/vram.c index f6fdc20..fed2a72 100644 --- a/drivers/video/omap2/vram.c +++ b/drivers/video/omap2/vram.c @@ -554,12 +554,8 @@ void __init omap_vram_reserve_sdram_memblock(void) size = PAGE_ALIGN(size); if (paddr) { - struct memblock_property res; - - res.base = paddr; - res.size = size; - if ((paddr & ~PAGE_MASK) || memblock_find(&res) || - res.base != paddr || res.size != size) { + if ((paddr & ~PAGE_MASK) || + !memblock_is_region_memory(paddr, size)) { pr_err("Illegal SDRAM region for VRAM\n"); return; } diff --git a/drivers/video/pxa168fb.c b/drivers/video/pxa168fb.c index a31a77f..cea6403 100644 --- a/drivers/video/pxa168fb.c +++ b/drivers/video/pxa168fb.c @@ -784,12 +784,53 @@ failed: return ret; } +static int __devexit pxa168fb_remove(struct platform_device *pdev) +{ + struct pxa168fb_info *fbi = platform_get_drvdata(pdev); + struct fb_info *info; + int irq; + unsigned int data; + + if (!fbi) + return 0; + + /* disable DMA transfer */ + data = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); + data &= ~CFG_GRA_ENA_MASK; + writel(data, fbi->reg_base + LCD_SPU_DMA_CTRL0); + + info = fbi->info; + + unregister_framebuffer(info); + + writel(GRA_FRAME_IRQ0_ENA(0x0), fbi->reg_base + SPU_IRQ_ENA); + + if (info->cmap.len) + fb_dealloc_cmap(&info->cmap); + + irq = platform_get_irq(pdev, 0); + free_irq(irq, fbi); + + dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len), + info->screen_base, info->fix.smem_start); + + iounmap(fbi->reg_base); + + clk_disable(fbi->clk); + clk_put(fbi->clk); + + framebuffer_release(info); + + return 0; +} + static struct platform_driver pxa168fb_driver = { .driver = { .name = "pxa168-fb", .owner = THIS_MODULE, }, .probe = pxa168fb_probe, + .remove = __devexit_p(pxa168fb_remove), }; static int __init pxa168fb_init(void) @@ -798,6 +839,12 @@ static int __init pxa168fb_init(void) } module_init(pxa168fb_init); +static void __exit pxa168fb_exit(void) +{ + platform_driver_unregister(&pxa168fb_driver); +} +module_exit(pxa168fb_exit); + MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com> " "Green Wan <gwan@marvell.com>"); MODULE_DESCRIPTION("Framebuffer driver for PXA168/910"); diff --git a/drivers/video/q40fb.c b/drivers/video/q40fb.c index fc32c32..f5a39f5 100644 --- a/drivers/video/q40fb.c +++ b/drivers/video/q40fb.c @@ -28,7 +28,7 @@ #define Q40_PHYS_SCREEN_ADDR 0xFE800000 -static struct fb_fix_screeninfo q40fb_fix __initdata = { +static struct fb_fix_screeninfo q40fb_fix __devinitdata = { .id = "Q40", .smem_len = 1024*1024, .type = FB_TYPE_PACKED_PIXELS, @@ -37,7 +37,7 @@ static struct fb_fix_screeninfo q40fb_fix __initdata = { .accel = FB_ACCEL_NONE, }; -static struct fb_var_screeninfo q40fb_var __initdata = { +static struct fb_var_screeninfo q40fb_var __devinitdata = { .xres = 1024, .yres = 512, .xres_virtual = 1024, diff --git a/drivers/video/savage/savagefb-i2c.c b/drivers/video/savage/savagefb-i2c.c index ed371c8..b16e613 100644 --- a/drivers/video/savage/savagefb-i2c.c +++ b/drivers/video/savage/savagefb-i2c.c @@ -181,6 +181,15 @@ void savagefb_create_i2c_busses(struct fb_info *info) par->chan.algo.getscl = prosavage_gpio_getscl; break; case FB_ACCEL_SAVAGE4: + par->chan.reg = CR_SERIAL1; + if (par->pcidev->revision > 1 && !(VGArCR(0xa6, par) & 0x40)) + par->chan.reg = CR_SERIAL2; + par->chan.ioaddr = par->mmio.vbase; + par->chan.algo.setsda = prosavage_gpio_setsda; + par->chan.algo.setscl = prosavage_gpio_setscl; + par->chan.algo.getsda = prosavage_gpio_getsda; + par->chan.algo.getscl = prosavage_gpio_getscl; + break; case FB_ACCEL_SAVAGE2000: par->chan.reg = 0xff20; par->chan.ioaddr = par->mmio.vbase; diff --git a/drivers/video/savage/savagefb.h b/drivers/video/savage/savagefb.h index 8bfdfc3..e4c3f21 100644 --- a/drivers/video/savage/savagefb.h +++ b/drivers/video/savage/savagefb.h @@ -13,7 +13,6 @@ #define __SAVAGEFB_H__ #include <linux/i2c.h> -#include <linux/i2c-id.h> #include <linux/i2c-algo-bit.h> #include <linux/mutex.h> #include <video/vga.h> diff --git a/drivers/video/sh_mobile_hdmi.c b/drivers/video/sh_mobile_hdmi.c index 2fde08c..ef989d9 100644 --- a/drivers/video/sh_mobile_hdmi.c +++ b/drivers/video/sh_mobile_hdmi.c @@ -22,6 +22,8 @@ #include <linux/slab.h> #include <linux/types.h> #include <linux/workqueue.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> #include <video/sh_mobile_hdmi.h> #include <video/sh_mobile_lcdc.h> @@ -222,6 +224,58 @@ static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg) return ioread8(hdmi->base + reg); } +/* + * HDMI sound + */ +static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec); + + return hdmi_read(hdmi, reg); +} + +static int sh_hdmi_snd_write(struct snd_soc_codec *codec, + unsigned int reg, + unsigned int value) +{ + struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec); + + hdmi_write(hdmi, value, reg); + return 0; +} + +static struct snd_soc_dai_driver sh_hdmi_dai = { + .name = "sh_mobile_hdmi-hifi", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 8, + .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, + }, +}; + +static int sh_hdmi_snd_probe(struct snd_soc_codec *codec) +{ + dev_info(codec->dev, "SH Mobile HDMI Audio Codec"); + + return 0; +} + +static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = { + .probe = sh_hdmi_snd_probe, + .read = sh_hdmi_snd_read, + .write = sh_hdmi_snd_write, +}; + +/* + * HDMI video + */ + /* External video parameter settings */ static void hdmi_external_video_param(struct sh_hdmi *hdmi) { @@ -318,6 +372,9 @@ static void sh_hdmi_video_config(struct sh_hdmi *hdmi) */ static void sh_hdmi_audio_config(struct sh_hdmi *hdmi) { + u8 data; + struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data; + /* * [7:4] L/R data swap control * [3:0] appropriate N[19:16] @@ -335,7 +392,23 @@ static void sh_hdmi_audio_config(struct sh_hdmi *hdmi) * [6:5] set required down sampling rate if required * [4:3] set required audio source */ - hdmi_write(hdmi, 0x00, HDMI_AUDIO_SETTING_1); + switch (pdata->flags & HDMI_SND_SRC_MASK) { + default: + /* fall through */ + case HDMI_SND_SRC_I2S: + data = 0x0 << 3; + break; + case HDMI_SND_SRC_SPDIF: + data = 0x1 << 3; + break; + case HDMI_SND_SRC_DSD: + data = 0x2 << 3; + break; + case HDMI_SND_SRC_HBR: + data = 0x3 << 3; + break; + } + hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1); /* [3:0] set sending channel number for channel status */ hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2); @@ -891,6 +964,11 @@ static int __init sh_hdmi_probe(struct platform_device *pdev) return -ENOMEM; } + ret = snd_soc_register_codec(&pdev->dev, + &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1); + if (ret < 0) + goto esndreg; + hdmi->dev = &pdev->dev; hdmi->hdmi_clk = clk_get(&pdev->dev, "ick"); @@ -976,6 +1054,8 @@ eclkenable: erate: clk_put(hdmi->hdmi_clk); egetclk: + snd_soc_unregister_codec(&pdev->dev); +esndreg: kfree(hdmi); return ret; @@ -988,6 +1068,8 @@ static int __exit sh_hdmi_remove(struct platform_device *pdev) struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); int irq = platform_get_irq(pdev, 0); + snd_soc_unregister_codec(&pdev->dev); + pdata->lcd_chan->board_cfg.display_on = NULL; pdata->lcd_chan->board_cfg.display_off = NULL; pdata->lcd_chan->board_cfg.board_data = NULL; diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c index d72075a..7a14192 100644 --- a/drivers/video/sh_mobile_lcdcfb.c +++ b/drivers/video/sh_mobile_lcdcfb.c @@ -1243,8 +1243,10 @@ static int sh_mobile_lcdc_remove(struct platform_device *pdev) if (priv->ch[i].sglist) vfree(priv->ch[i].sglist); - dma_free_coherent(&pdev->dev, info->fix.smem_len, - info->screen_base, priv->ch[i].dma_handle); + if (info->screen_base) + dma_free_coherent(&pdev->dev, info->fix.smem_len, + info->screen_base, + priv->ch[i].dma_handle); fb_dealloc_cmap(&info->cmap); framebuffer_release(info); } diff --git a/drivers/video/vesafb.c b/drivers/video/vesafb.c index 090aa1a..6a069d0 100644 --- a/drivers/video/vesafb.c +++ b/drivers/video/vesafb.c @@ -253,7 +253,7 @@ static int __init vesafb_probe(struct platform_device *dev) size_vmode = vesafb_defined.yres * vesafb_fix.line_length; /* size_total -- all video memory we have. Used for mtrr - * entries, ressource allocation and bounds + * entries, resource allocation and bounds * checking. */ size_total = screen_info.lfb_size * 65536; if (vram_total) diff --git a/drivers/video/via/Makefile b/drivers/video/via/Makefile index d496adb..96f01ee 100644 --- a/drivers/video/via/Makefile +++ b/drivers/video/via/Makefile @@ -5,5 +5,5 @@ obj-$(CONFIG_FB_VIA) += viafb.o viafb-y :=viafbdev.o hw.o via_i2c.o dvi.o lcd.o ioctl.o accel.o \ - via_utility.o vt1636.o global.o tblDPASetting.o viamode.o tbl1636.o \ + via_utility.o vt1636.o global.o tblDPASetting.o viamode.o \ via-core.o via-gpio.o via_modesetting.o diff --git a/drivers/video/via/accel.c b/drivers/video/via/accel.c index 04bec05..4b67b8e 100644 --- a/drivers/video/via/accel.c +++ b/drivers/video/via/accel.c @@ -283,11 +283,12 @@ static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height, writel(tmp, engine + 0x1C); } - if (op != VIA_BITBLT_COLOR) + if (op == VIA_BITBLT_FILL) { + writel(fg_color, engine + 0x58); + } else if (op == VIA_BITBLT_MONO) { writel(fg_color, engine + 0x4C); - - if (op == VIA_BITBLT_MONO) writel(bg_color, engine + 0x50); + } if (op == VIA_BITBLT_FILL) ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001; @@ -314,13 +315,11 @@ static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height, return 0; } -int viafb_init_engine(struct fb_info *info) +int viafb_setup_engine(struct fb_info *info) { struct viafb_par *viapar = info->par; void __iomem *engine; - int highest_reg, i; - u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high, - vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name; + u32 chip_name = viapar->shared->chip_info.gfx_chip_name; engine = viapar->shared->vdev->engine_mmio; if (!engine) { @@ -329,18 +328,6 @@ int viafb_init_engine(struct fb_info *info) return -ENOMEM; } - /* Initialize registers to reset the 2D engine */ - switch (viapar->shared->chip_info.twod_engine) { - case VIA_2D_ENG_M1: - highest_reg = 0x5c; - break; - default: - highest_reg = 0x40; - break; - } - for (i = 0; i <= highest_reg; i += 4) - writel(0x0, engine + i); - switch (chip_name) { case UNICHROME_CLE266: case UNICHROME_K400: @@ -356,6 +343,7 @@ int viafb_init_engine(struct fb_info *info) break; case UNICHROME_VX800: case UNICHROME_VX855: + case UNICHROME_VX900: viapar->shared->hw_bitblt = hw_bitblt_2; break; default: @@ -386,12 +374,36 @@ int viafb_init_engine(struct fb_info *info) viapar->shared->vdev->camera_fbmem_offset = viapar->fbmem_free; #endif + viafb_reset_engine(viapar); + return 0; +} + +void viafb_reset_engine(struct viafb_par *viapar) +{ + void __iomem *engine = viapar->shared->vdev->engine_mmio; + int highest_reg, i; + u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high, + vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name; + + /* Initialize registers to reset the 2D engine */ + switch (viapar->shared->chip_info.twod_engine) { + case VIA_2D_ENG_M1: + highest_reg = 0x5c; + break; + default: + highest_reg = 0x40; + break; + } + for (i = 0; i <= highest_reg; i += 4) + writel(0x0, engine + i); + /* Init AGP and VQ regs */ switch (chip_name) { case UNICHROME_K8M890: case UNICHROME_P4M900: case UNICHROME_VX800: case UNICHROME_VX855: + case UNICHROME_VX900: writel(0x00100000, engine + VIA_REG_CR_TRANSET); writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE); writel(0x02000000, engine + VIA_REG_CR_TRANSPACE); @@ -428,6 +440,7 @@ int viafb_init_engine(struct fb_info *info) case UNICHROME_P4M900: case UNICHROME_VX800: case UNICHROME_VX855: + case UNICHROME_VX900: vq_start_low |= 0x20000000; vq_end_low |= 0x20000000; vq_high |= 0x20000000; @@ -473,7 +486,7 @@ int viafb_init_engine(struct fb_info *info) writel(0x0, engine + VIA_REG_CURSOR_ORG); writel(0x0, engine + VIA_REG_CURSOR_BG); writel(0x0, engine + VIA_REG_CURSOR_FG); - return 0; + return; } void viafb_show_hw_cursor(struct fb_info *info, int Status) diff --git a/drivers/video/via/accel.h b/drivers/video/via/accel.h index 2c122d2..79d5e10 100644 --- a/drivers/video/via/accel.h +++ b/drivers/video/via/accel.h @@ -203,7 +203,8 @@ #define VIA_BITBLT_MONO 2 #define VIA_BITBLT_FILL 3 -int viafb_init_engine(struct fb_info *info); +int viafb_setup_engine(struct fb_info *info); +void viafb_reset_engine(struct viafb_par *viapar); void viafb_show_hw_cursor(struct fb_info *info, int Status); void viafb_wait_engine_idle(struct fb_info *info); diff --git a/drivers/video/via/chip.h b/drivers/video/via/chip.h index ef1f3de..48f1342 100644 --- a/drivers/video/via/chip.h +++ b/drivers/video/via/chip.h @@ -71,6 +71,9 @@ #define UNICHROME_VX855 12 #define UNICHROME_VX855_DID 0x5122 +#define UNICHROME_VX900 13 +#define UNICHROME_VX900_DID 0x7122 + /**************************************************/ /* Definition TMDS Trasmitter Information */ /**************************************************/ diff --git a/drivers/video/via/dvi.c b/drivers/video/via/dvi.c index 39b040b..84e21b3 100644 --- a/drivers/video/via/dvi.c +++ b/drivers/video/via/dvi.c @@ -25,10 +25,12 @@ static void tmds_register_write(int index, u8 data); static int tmds_register_read(int index); static int tmds_register_read_bytes(int index, u8 *buff, int buff_len); -static void dvi_get_panel_size_from_DDCv1(struct tmds_chip_information - *tmds_chip, struct tmds_setting_information *tmds_setting); -static void dvi_get_panel_size_from_DDCv2(struct tmds_chip_information - *tmds_chip, struct tmds_setting_information *tmds_setting); +static void __devinit dvi_get_panel_size_from_DDCv1( + struct tmds_chip_information *tmds_chip, + struct tmds_setting_information *tmds_setting); +static void __devinit dvi_get_panel_size_from_DDCv2( + struct tmds_chip_information *tmds_chip, + struct tmds_setting_information *tmds_setting); static int viafb_dvi_query_EDID(void); static int check_tmds_chip(int device_id_subaddr, int device_id) @@ -39,7 +41,7 @@ static int check_tmds_chip(int device_id_subaddr, int device_id) return FAIL; } -void viafb_init_dvi_size(struct tmds_chip_information *tmds_chip, +void __devinit viafb_init_dvi_size(struct tmds_chip_information *tmds_chip, struct tmds_setting_information *tmds_setting) { DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n"); @@ -60,7 +62,7 @@ void viafb_init_dvi_size(struct tmds_chip_information *tmds_chip, return; } -int viafb_tmds_trasmitter_identify(void) +int __devinit viafb_tmds_trasmitter_identify(void) { unsigned char sr2a = 0, sr1e = 0, sr3e = 0; @@ -208,8 +210,6 @@ void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp, } } viafb_fill_crtc_timing(pDviTiming, mode, mode_bpp / 8, set_iga); - viafb_set_output_path(DEVICE_DVI, set_iga, - viaparinfo->chip_info->tmds_chip_info.output_interface); } /* Sense DVI Connector */ @@ -313,8 +313,9 @@ static int viafb_dvi_query_EDID(void) } /* Get Panel Size Using EDID1 Table */ -static void dvi_get_panel_size_from_DDCv1(struct tmds_chip_information - *tmds_chip, struct tmds_setting_information *tmds_setting) +static void __devinit dvi_get_panel_size_from_DDCv1( + struct tmds_chip_information *tmds_chip, + struct tmds_setting_information *tmds_setting) { int i, max_h = 0, tmp, restore; unsigned char rData; @@ -418,8 +419,9 @@ static void dvi_get_panel_size_from_DDCv1(struct tmds_chip_information } /* Get Panel Size Using EDID2 Table */ -static void dvi_get_panel_size_from_DDCv2(struct tmds_chip_information - *tmds_chip, struct tmds_setting_information *tmds_setting) +static void __devinit dvi_get_panel_size_from_DDCv2( + struct tmds_chip_information *tmds_chip, + struct tmds_setting_information *tmds_setting) { int restore; unsigned char R_Buffer[2]; @@ -468,64 +470,107 @@ static void dvi_get_panel_size_from_DDCv2(struct tmds_chip_information void viafb_dvi_disable(void) { if (viaparinfo->chip_info-> - tmds_chip_info.output_interface == INTERFACE_DVP0) - viafb_write_reg(SR1E, VIASR, - viafb_read_reg(VIASR, SR1E) & (~0xC0)); - - if (viaparinfo->chip_info-> - tmds_chip_info.output_interface == INTERFACE_DVP1) - viafb_write_reg(SR1E, VIASR, - viafb_read_reg(VIASR, SR1E) & (~0x30)); - - if (viaparinfo->chip_info-> - tmds_chip_info.output_interface == INTERFACE_DFP_HIGH) - viafb_write_reg(SR2A, VIASR, - viafb_read_reg(VIASR, SR2A) & (~0x0C)); - - if (viaparinfo->chip_info-> - tmds_chip_info.output_interface == INTERFACE_DFP_LOW) - viafb_write_reg(SR2A, VIASR, - viafb_read_reg(VIASR, SR2A) & (~0x03)); - - if (viaparinfo->chip_info-> tmds_chip_info.output_interface == INTERFACE_TMDS) /* Turn off TMDS power. */ viafb_write_reg(CRD2, VIACR, viafb_read_reg(VIACR, CRD2) | 0x08); } +static void dvi_patch_skew_dvp0(void) +{ + /* Reset data driving first: */ + viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); + viafb_write_reg_mask(SR2A, VIASR, 0, BIT4); + + switch (viaparinfo->chip_info->gfx_chip_name) { + case UNICHROME_P4M890: + { + if ((viaparinfo->tmds_setting_info->h_active == 1600) && + (viaparinfo->tmds_setting_info->v_active == + 1200)) + viafb_write_reg_mask(CR96, VIACR, 0x03, + BIT0 + BIT1 + BIT2); + else + viafb_write_reg_mask(CR96, VIACR, 0x07, + BIT0 + BIT1 + BIT2); + break; + } + + case UNICHROME_P4M900: + { + viafb_write_reg_mask(CR96, VIACR, 0x07, + BIT0 + BIT1 + BIT2 + BIT3); + viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); + viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4); + break; + } + + default: + { + break; + } + } +} + +static void dvi_patch_skew_dvp_low(void) +{ + switch (viaparinfo->chip_info->gfx_chip_name) { + case UNICHROME_K8M890: + { + viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); + break; + } + + case UNICHROME_P4M900: + { + viafb_write_reg_mask(CR99, VIACR, 0x08, + BIT0 + BIT1 + BIT2 + BIT3); + break; + } + + case UNICHROME_P4M890: + { + viafb_write_reg_mask(CR99, VIACR, 0x0F, + BIT0 + BIT1 + BIT2 + BIT3); + break; + } + + default: + { + break; + } + } +} + /* If Enable DVI, turn off pad */ void viafb_dvi_enable(void) { u8 data; - if (viaparinfo->chip_info-> - tmds_chip_info.output_interface == INTERFACE_DVP0) { - viafb_write_reg(SR1E, VIASR, - viafb_read_reg(VIASR, SR1E) | 0xC0); + switch (viaparinfo->chip_info->tmds_chip_info.output_interface) { + case INTERFACE_DVP0: + viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); + viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); + dvi_patch_skew_dvp0(); if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) tmds_register_write(0x88, 0x3b); else /*clear CR91[5] to direct on display period in the secondary diplay path */ - viafb_write_reg(CR91, VIACR, - viafb_read_reg(VIACR, CR91) & 0xDF); - } + via_write_reg_mask(VIACR, 0x91, 0x00, 0x20); + break; - if (viaparinfo->chip_info-> - tmds_chip_info.output_interface == INTERFACE_DVP1) { - viafb_write_reg(SR1E, VIASR, - viafb_read_reg(VIASR, SR1E) | 0x30); + case INTERFACE_DVP1: + if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) + viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); /*fix dvi cann't be enabled with MB VT5718C4 - Al Zhang */ - if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { + if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) tmds_register_write(0x88, 0x3b); - } else { + else /*clear CR91[5] to direct on display period in the secondary diplay path */ - viafb_write_reg(CR91, VIACR, - viafb_read_reg(VIACR, CR91) & 0xDF); - } + via_write_reg_mask(VIACR, 0x91, 0x00, 0x20); /*fix DVI cannot enable on EPIA-M board */ if (viafb_platform_epia_dvi == 1) { @@ -537,36 +582,40 @@ void viafb_dvi_enable(void) else data = 0x37; viafb_i2c_writebyte(viaparinfo->chip_info-> - tmds_chip_info.i2c_port, - viaparinfo->chip_info-> - tmds_chip_info.tmds_chip_slave_addr, - 0x08, data); + tmds_chip_info.i2c_port, + viaparinfo->chip_info-> + tmds_chip_info.tmds_chip_slave_addr, + 0x08, data); } } - } + break; - if (viaparinfo->chip_info-> - tmds_chip_info.output_interface == INTERFACE_DFP_HIGH) { - viafb_write_reg(SR2A, VIASR, - viafb_read_reg(VIASR, SR2A) | 0x0C); - viafb_write_reg(CR91, VIACR, - viafb_read_reg(VIACR, CR91) & 0xDF); - } + case INTERFACE_DFP_HIGH: + if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) + via_write_reg_mask(VIACR, CR97, 0x03, 0x03); - if (viaparinfo->chip_info-> - tmds_chip_info.output_interface == INTERFACE_DFP_LOW) { - viafb_write_reg(SR2A, VIASR, - viafb_read_reg(VIASR, SR2A) | 0x03); - viafb_write_reg(CR91, VIACR, - viafb_read_reg(VIACR, CR91) & 0xDF); - } - if (viaparinfo->chip_info-> - tmds_chip_info.output_interface == INTERFACE_TMDS) { + via_write_reg_mask(VIACR, 0x91, 0x00, 0x20); + break; + + case INTERFACE_DFP_LOW: + if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) + break; + + dvi_patch_skew_dvp_low(); + via_write_reg_mask(VIACR, 0x91, 0x00, 0x20); + break; + + case INTERFACE_TMDS: /* Turn on Display period in the panel path. */ viafb_write_reg_mask(CR91, VIACR, 0, BIT7); /* Turn on TMDS power. */ viafb_write_reg_mask(CRD2, VIACR, 0, BIT3); + break; } -} + if (viaparinfo->tmds_setting_info->iga_path == IGA2) { + /* Disable LCD Scaling */ + viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0); + } +} diff --git a/drivers/video/via/dvi.h b/drivers/video/via/dvi.h index 0dffcfd..2c525c0 100644 --- a/drivers/video/via/dvi.h +++ b/drivers/video/via/dvi.h @@ -56,8 +56,8 @@ int viafb_dvi_sense(void); void viafb_dvi_disable(void); void viafb_dvi_enable(void); -int viafb_tmds_trasmitter_identify(void); -void viafb_init_dvi_size(struct tmds_chip_information *tmds_chip, +int __devinit viafb_tmds_trasmitter_identify(void); +void __devinit viafb_init_dvi_size(struct tmds_chip_information *tmds_chip, struct tmds_setting_information *tmds_setting); void viafb_dvi_set_mode(struct VideoModeTable *videoMode, int mode_bpp, int set_iga); diff --git a/drivers/video/via/global.h b/drivers/video/via/global.h index 28221a0..38ef5ac 100644 --- a/drivers/video/via/global.h +++ b/drivers/video/via/global.h @@ -48,7 +48,6 @@ #include "via_utility.h" #include "vt1636.h" #include "tblDPASetting.h" -#include "tbl1636.h" /* External struct*/ diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c index 7dcb4d5..36d73f9 100644 --- a/drivers/video/via/hw.c +++ b/drivers/video/via/hw.c @@ -718,16 +718,20 @@ static struct rgbLUT palLUT_table[] = { 0x00} }; -static void set_crt_output_path(int set_iga); -static void dvi_patch_skew_dvp0(void); -static void dvi_patch_skew_dvp1(void); -static void dvi_patch_skew_dvp_low(void); -static void set_dvi_output_path(int set_iga, int output_interface); -static void set_lcd_output_path(int set_iga, int output_interface); +static struct via_device_mapping device_mapping[] = { + {VIA_LDVP0, "LDVP0"}, + {VIA_LDVP1, "LDVP1"}, + {VIA_DVP0, "DVP0"}, + {VIA_CRT, "CRT"}, + {VIA_DVP1, "DVP1"}, + {VIA_LVDS1, "LVDS1"}, + {VIA_LVDS2, "LVDS2"} +}; + static void load_fix_bit_crtc_reg(void); -static void init_gfx_chip_info(int chip_type); -static void init_tmds_chip_info(void); -static void init_lvds_chip_info(void); +static void __devinit init_gfx_chip_info(int chip_type); +static void __devinit init_tmds_chip_info(void); +static void __devinit init_lvds_chip_info(void); static void device_screen_off(void); static void device_screen_on(void); static void set_display_channel(void); @@ -755,6 +759,66 @@ void write_dac_reg(u8 index, u8 r, u8 g, u8 b) outb(b, LUT_DATA); } +static u32 get_dvi_devices(int output_interface) +{ + switch (output_interface) { + case INTERFACE_DVP0: + return VIA_DVP0 | VIA_LDVP0; + + case INTERFACE_DVP1: + if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) + return VIA_LDVP1; + else + return VIA_DVP1; + + case INTERFACE_DFP_HIGH: + if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) + return 0; + else + return VIA_LVDS2 | VIA_DVP0; + + case INTERFACE_DFP_LOW: + if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) + return 0; + else + return VIA_DVP1 | VIA_LVDS1; + + case INTERFACE_TMDS: + return VIA_LVDS1; + } + + return 0; +} + +static u32 get_lcd_devices(int output_interface) +{ + switch (output_interface) { + case INTERFACE_DVP0: + return VIA_DVP0; + + case INTERFACE_DVP1: + return VIA_DVP1; + + case INTERFACE_DFP_HIGH: + return VIA_LVDS2 | VIA_DVP0; + + case INTERFACE_DFP_LOW: + return VIA_LVDS1 | VIA_DVP1; + + case INTERFACE_DFP: + return VIA_LVDS1 | VIA_LVDS2; + + case INTERFACE_LVDS0: + case INTERFACE_LVDS0LVDS1: + return VIA_LVDS1; + + case INTERFACE_LVDS1: + return VIA_LVDS2; + } + + return 0; +} + /*Set IGA path for each device*/ void viafb_set_iga_path(void) { @@ -821,6 +885,48 @@ void viafb_set_iga_path(void) viaparinfo->tmds_setting_info->iga_path = IGA1; } } + + viaparinfo->shared->iga1_devices = 0; + viaparinfo->shared->iga2_devices = 0; + if (viafb_CRT_ON) { + if (viaparinfo->crt_setting_info->iga_path == IGA1) + viaparinfo->shared->iga1_devices |= VIA_CRT; + else + viaparinfo->shared->iga2_devices |= VIA_CRT; + } + + if (viafb_DVI_ON) { + if (viaparinfo->tmds_setting_info->iga_path == IGA1) + viaparinfo->shared->iga1_devices |= get_dvi_devices( + viaparinfo->chip_info-> + tmds_chip_info.output_interface); + else + viaparinfo->shared->iga2_devices |= get_dvi_devices( + viaparinfo->chip_info-> + tmds_chip_info.output_interface); + } + + if (viafb_LCD_ON) { + if (viaparinfo->lvds_setting_info->iga_path == IGA1) + viaparinfo->shared->iga1_devices |= get_lcd_devices( + viaparinfo->chip_info-> + lvds_chip_info.output_interface); + else + viaparinfo->shared->iga2_devices |= get_lcd_devices( + viaparinfo->chip_info-> + lvds_chip_info.output_interface); + } + + if (viafb_LCD2_ON) { + if (viaparinfo->lvds_setting_info2->iga_path == IGA1) + viaparinfo->shared->iga1_devices |= get_lcd_devices( + viaparinfo->chip_info-> + lvds_chip_info2.output_interface); + else + viaparinfo->shared->iga2_devices |= get_lcd_devices( + viaparinfo->chip_info-> + lvds_chip_info2.output_interface); + } } static void set_color_register(u8 index, u8 red, u8 green, u8 blue) @@ -844,295 +950,266 @@ void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue) set_color_register(index, red, green, blue); } -void viafb_set_output_path(int device, int set_iga, int output_interface) +static void set_source_common(u8 index, u8 offset, u8 iga) { - switch (device) { - case DEVICE_CRT: - set_crt_output_path(set_iga); - break; - case DEVICE_DVI: - set_dvi_output_path(set_iga, output_interface); + u8 value, mask = 1 << offset; + + switch (iga) { + case IGA1: + value = 0x00; break; - case DEVICE_LCD: - set_lcd_output_path(set_iga, output_interface); + case IGA2: + value = mask; break; + default: + printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga); + return; } + + via_write_reg_mask(VIACR, index, value, mask); } -static void set_crt_output_path(int set_iga) +static void set_crt_source(u8 iga) { - viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5); + u8 value; - switch (set_iga) { + switch (iga) { case IGA1: - viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6); + value = 0x00; break; case IGA2: - viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7); - viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6); + value = 0x40; break; + default: + printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga); + return; } + + via_write_reg_mask(VIASR, 0x16, value, 0x40); } -static void dvi_patch_skew_dvp0(void) +static inline void set_ldvp0_source(u8 iga) { - /* Reset data driving first: */ - viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); - viafb_write_reg_mask(SR2A, VIASR, 0, BIT4); - - switch (viaparinfo->chip_info->gfx_chip_name) { - case UNICHROME_P4M890: - { - if ((viaparinfo->tmds_setting_info->h_active == 1600) && - (viaparinfo->tmds_setting_info->v_active == - 1200)) - viafb_write_reg_mask(CR96, VIACR, 0x03, - BIT0 + BIT1 + BIT2); - else - viafb_write_reg_mask(CR96, VIACR, 0x07, - BIT0 + BIT1 + BIT2); - break; - } + set_source_common(0x6C, 7, iga); +} - case UNICHROME_P4M900: - { - viafb_write_reg_mask(CR96, VIACR, 0x07, - BIT0 + BIT1 + BIT2 + BIT3); - viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); - viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4); - break; - } +static inline void set_ldvp1_source(u8 iga) +{ + set_source_common(0x93, 7, iga); +} - default: - { - break; - } - } +static inline void set_dvp0_source(u8 iga) +{ + set_source_common(0x96, 4, iga); } -static void dvi_patch_skew_dvp1(void) +static inline void set_dvp1_source(u8 iga) { - switch (viaparinfo->chip_info->gfx_chip_name) { - case UNICHROME_CX700: - { - break; - } + set_source_common(0x9B, 4, iga); +} - default: - { - break; - } - } +static inline void set_lvds1_source(u8 iga) +{ + set_source_common(0x99, 4, iga); } -static void dvi_patch_skew_dvp_low(void) +static inline void set_lvds2_source(u8 iga) { - switch (viaparinfo->chip_info->gfx_chip_name) { - case UNICHROME_K8M890: - { - viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); - break; - } + set_source_common(0x97, 4, iga); +} - case UNICHROME_P4M900: - { - viafb_write_reg_mask(CR99, VIACR, 0x08, - BIT0 + BIT1 + BIT2 + BIT3); - break; - } +void via_set_source(u32 devices, u8 iga) +{ + if (devices & VIA_LDVP0) + set_ldvp0_source(iga); + if (devices & VIA_LDVP1) + set_ldvp1_source(iga); + if (devices & VIA_DVP0) + set_dvp0_source(iga); + if (devices & VIA_CRT) + set_crt_source(iga); + if (devices & VIA_DVP1) + set_dvp1_source(iga); + if (devices & VIA_LVDS1) + set_lvds1_source(iga); + if (devices & VIA_LVDS2) + set_lvds2_source(iga); +} - case UNICHROME_P4M890: - { - viafb_write_reg_mask(CR99, VIACR, 0x0F, - BIT0 + BIT1 + BIT2 + BIT3); - break; - } +static void set_crt_state(u8 state) +{ + u8 value; + switch (state) { + case VIA_STATE_ON: + value = 0x00; + break; + case VIA_STATE_STANDBY: + value = 0x10; + break; + case VIA_STATE_SUSPEND: + value = 0x20; + break; + case VIA_STATE_OFF: + value = 0x30; + break; default: - { - break; - } + return; } + + via_write_reg_mask(VIACR, 0x36, value, 0x30); } -static void set_dvi_output_path(int set_iga, int output_interface) +static void set_dvp0_state(u8 state) { - switch (output_interface) { - case INTERFACE_DVP0: - viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); - - if (set_iga == IGA1) { - viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4); - viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + - BIT5 + BIT7); - } else { - viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4); - viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 + - BIT5 + BIT7); - } - - viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6); + u8 value; - dvi_patch_skew_dvp0(); + switch (state) { + case VIA_STATE_ON: + value = 0xC0; break; + case VIA_STATE_OFF: + value = 0x00; + break; + default: + return; + } - case INTERFACE_DVP1: - if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { - if (set_iga == IGA1) - viafb_write_reg_mask(CR93, VIACR, 0x21, - BIT0 + BIT5 + BIT7); - else - viafb_write_reg_mask(CR93, VIACR, 0xA1, - BIT0 + BIT5 + BIT7); - } else { - if (set_iga == IGA1) - viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4); - else - viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4); - } + via_write_reg_mask(VIASR, 0x1E, value, 0xC0); +} + +static void set_dvp1_state(u8 state) +{ + u8 value; - viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5); - dvi_patch_skew_dvp1(); + switch (state) { + case VIA_STATE_ON: + value = 0x30; break; - case INTERFACE_DFP_HIGH: - if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) { - if (set_iga == IGA1) { - viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4); - viafb_write_reg_mask(CR97, VIACR, 0x03, - BIT0 + BIT1 + BIT4); - } else { - viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4); - viafb_write_reg_mask(CR97, VIACR, 0x13, - BIT0 + BIT1 + BIT4); - } - } - viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3); + case VIA_STATE_OFF: + value = 0x00; break; + default: + return; + } - case INTERFACE_DFP_LOW: - if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) - break; + via_write_reg_mask(VIASR, 0x1E, value, 0x30); +} - if (set_iga == IGA1) { - viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4); - viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4); - } else { - viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4); - viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4); - } +static void set_lvds1_state(u8 state) +{ + u8 value; - viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); - dvi_patch_skew_dvp_low(); + switch (state) { + case VIA_STATE_ON: + value = 0x03; break; - - case INTERFACE_TMDS: - if (set_iga == IGA1) - viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4); - else - viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4); + case VIA_STATE_OFF: + value = 0x00; break; + default: + return; } - if (set_iga == IGA2) { - enable_second_display_channel(); - /* Disable LCD Scaling */ - viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0); - } + via_write_reg_mask(VIASR, 0x2A, value, 0x03); } -static void set_lcd_output_path(int set_iga, int output_interface) +static void set_lvds2_state(u8 state) { - DEBUG_MSG(KERN_INFO - "set_lcd_output_path, iga:%d,out_interface:%d\n", - set_iga, output_interface); - switch (set_iga) { - case IGA1: - viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3); - viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); + u8 value; - disable_second_display_channel(); + switch (state) { + case VIA_STATE_ON: + value = 0x0C; break; - - case IGA2: - viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3); - viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); - - enable_second_display_channel(); + case VIA_STATE_OFF: + value = 0x00; break; + default: + return; } - switch (output_interface) { - case INTERFACE_DVP0: - if (set_iga == IGA1) { - viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4); - } else { - viafb_write_reg(CR91, VIACR, 0x00); - viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4); - } - break; - - case INTERFACE_DVP1: - if (set_iga == IGA1) - viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4); - else { - viafb_write_reg(CR91, VIACR, 0x00); - viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4); - } - break; + via_write_reg_mask(VIASR, 0x2A, value, 0x0C); +} - case INTERFACE_DFP_HIGH: - if (set_iga == IGA1) - viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4); - else { - viafb_write_reg(CR91, VIACR, 0x00); - viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4); - viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4); - } - break; +void via_set_state(u32 devices, u8 state) +{ + /* + TODO: Can we enable/disable these devices? How? + if (devices & VIA_LDVP0) + if (devices & VIA_LDVP1) + */ + if (devices & VIA_DVP0) + set_dvp0_state(state); + if (devices & VIA_CRT) + set_crt_state(state); + if (devices & VIA_DVP1) + set_dvp1_state(state); + if (devices & VIA_LVDS1) + set_lvds1_state(state); + if (devices & VIA_LVDS2) + set_lvds2_state(state); +} - case INTERFACE_DFP_LOW: - if (set_iga == IGA1) - viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4); - else { - viafb_write_reg(CR91, VIACR, 0x00); - viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4); - viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4); - } +void via_set_sync_polarity(u32 devices, u8 polarity) +{ + if (polarity & ~(VIA_HSYNC_NEGATIVE | VIA_VSYNC_NEGATIVE)) { + printk(KERN_WARNING "viafb: Unsupported polarity: %d\n", + polarity); + return; + } - break; + if (devices & VIA_CRT) + via_write_misc_reg_mask(polarity << 6, 0xC0); + if (devices & VIA_DVP1) + via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60); + if (devices & VIA_LVDS1) + via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60); + if (devices & VIA_LVDS2) + via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60); +} - case INTERFACE_DFP: - if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name) - || (UNICHROME_P4M890 == - viaparinfo->chip_info->gfx_chip_name)) - viafb_write_reg_mask(CR97, VIACR, 0x84, - BIT7 + BIT2 + BIT1 + BIT0); - if (set_iga == IGA1) { - viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4); - viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4); - } else { - viafb_write_reg(CR91, VIACR, 0x00); - viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4); - viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4); +u32 via_parse_odev(char *input, char **end) +{ + char *ptr = input; + u32 odev = 0; + bool next = true; + int i, len; + + while (next) { + next = false; + for (i = 0; i < ARRAY_SIZE(device_mapping); i++) { + len = strlen(device_mapping[i].name); + if (!strncmp(ptr, device_mapping[i].name, len)) { + odev |= device_mapping[i].device; + ptr += len; + if (*ptr == ',') { + ptr++; + next = true; + } + } } - break; + } - case INTERFACE_LVDS0: - case INTERFACE_LVDS0LVDS1: - if (set_iga == IGA1) - viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4); - else - viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4); + *end = ptr; + return odev; +} - break; +void via_odev_to_seq(struct seq_file *m, u32 odev) +{ + int i, count = 0; - case INTERFACE_LVDS1: - if (set_iga == IGA1) - viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4); - else - viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4); - break; + for (i = 0; i < ARRAY_SIZE(device_mapping); i++) { + if (odev & device_mapping[i].device) { + if (count > 0) + seq_putc(m, ','); + + seq_puts(m, device_mapping[i].name); + count++; + } } + + seq_putc(m, '\n'); } static void load_fix_bit_crtc_reg(void) @@ -1352,6 +1429,15 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active) VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; } + if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) { + iga1_fifo_max_depth = VX900_IGA1_FIFO_MAX_DEPTH; + iga1_fifo_threshold = VX900_IGA1_FIFO_THRESHOLD; + iga1_fifo_high_threshold = + VX900_IGA1_FIFO_HIGH_THRESHOLD; + iga1_display_queue_expire_num = + VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; + } + /* Set Display FIFO Depath Select */ reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth); viafb_load_reg_num = @@ -1492,6 +1578,15 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active) VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; } + if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) { + iga2_fifo_max_depth = VX900_IGA2_FIFO_MAX_DEPTH; + iga2_fifo_threshold = VX900_IGA2_FIFO_THRESHOLD; + iga2_fifo_high_threshold = + VX900_IGA2_FIFO_HIGH_THRESHOLD; + iga2_display_queue_expire_num = + VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; + } + if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { /* Set Display FIFO Depath Select */ reg_value = @@ -1612,6 +1707,7 @@ u32 viafb_get_clk_value(int clk) break; case UNICHROME_VX855: + case UNICHROME_VX900: value = vx855_encode_pll(pll_value[i].vx855_pll); break; } @@ -1645,6 +1741,7 @@ void viafb_set_vclock(u32 clk, int set_iga) case UNICHROME_P4M900: case UNICHROME_VX800: case UNICHROME_VX855: + case UNICHROME_VX900: via_write_reg(VIASR, SR44, (clk & 0x0000FF)); via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8); via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16); @@ -1671,6 +1768,7 @@ void viafb_set_vclock(u32 clk, int set_iga) case UNICHROME_P4M900: case UNICHROME_VX800: case UNICHROME_VX855: + case UNICHROME_VX900: via_write_reg(VIASR, SR4A, (clk & 0x0000FF)); via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8); via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16); @@ -1688,8 +1786,8 @@ void viafb_set_vclock(u32 clk, int set_iga) } if (set_iga == IGA2) { - viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0); - viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0); + viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2); + viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2); } /* Fire! */ @@ -1937,7 +2035,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, int index = 0; int h_addr, v_addr; u32 pll_D_N; - u8 polarity = 0; for (i = 0; i < video_mode->mode_array; i++) { index = i; @@ -1964,14 +2061,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, h_addr = crt_reg.hor_addr; v_addr = crt_reg.ver_addr; - - /* update polarity for CRT timing */ - if (crt_table[index].h_sync_polarity == NEGATIVE) - polarity |= BIT6; - if (crt_table[index].v_sync_polarity == NEGATIVE) - polarity |= BIT7; - via_write_misc_reg_mask(polarity, BIT6 | BIT7); - if (set_iga == IGA1) { viafb_unlock_crt(); viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */ @@ -2004,7 +2093,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, } -void viafb_init_chip_info(int chip_type) +void __devinit viafb_init_chip_info(int chip_type) { init_gfx_chip_info(chip_type); init_tmds_chip_info(); @@ -2071,7 +2160,7 @@ void viafb_update_device_setting(int hres, int vres, } } -static void init_gfx_chip_info(int chip_type) +static void __devinit init_gfx_chip_info(int chip_type) { u8 tmp; @@ -2111,6 +2200,7 @@ static void init_gfx_chip_info(int chip_type) switch (viaparinfo->chip_info->gfx_chip_name) { case UNICHROME_VX800: case UNICHROME_VX855: + case UNICHROME_VX900: viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1; break; case UNICHROME_K8M890: @@ -2123,7 +2213,7 @@ static void init_gfx_chip_info(int chip_type) } } -static void init_tmds_chip_info(void) +static void __devinit init_tmds_chip_info(void) { viafb_tmds_trasmitter_identify(); @@ -2168,7 +2258,7 @@ static void init_tmds_chip_info(void) &viaparinfo->shared->tmds_setting_info); } -static void init_lvds_chip_info(void) +static void __devinit init_lvds_chip_info(void) { viafb_lvds_trasmitter_identify(); viafb_init_lcd_size(); @@ -2202,7 +2292,7 @@ static void init_lvds_chip_info(void) viaparinfo->chip_info->lvds_chip_info.output_interface); } -void viafb_init_dac(int set_iga) +void __devinit viafb_init_dac(int set_iga) { int i; u8 tmp; @@ -2275,11 +2365,24 @@ static void set_display_channel(void) } } +static u8 get_sync(struct fb_info *info) +{ + u8 polarity = 0; + + if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) + polarity |= VIA_HSYNC_NEGATIVE; + if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) + polarity |= VIA_VSYNC_NEGATIVE; + return polarity; +} + int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, struct VideoModeTable *vmode_tbl1, int video_bpp1) { int i, j; int port; + u32 devices = viaparinfo->shared->iga1_devices + | viaparinfo->shared->iga2_devices; u8 value, index, mask; struct crt_mode_table *crt_timing; struct crt_mode_table *crt_timing1 = NULL; @@ -2322,11 +2425,13 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, break; case UNICHROME_VX855: + case UNICHROME_VX900: viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs); break; } device_off(); + via_set_state(devices, VIA_STATE_OFF); /* Fill VPIT Parameters */ /* Write Misc Register */ @@ -2337,7 +2442,6 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, via_write_reg(VIASR, i, VPIT.SR[i - 1]); viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2); - viafb_set_iga_path(); /* Write CRTC */ viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1); @@ -2377,6 +2481,13 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, via_set_primary_color_depth(viaparinfo->depth); via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth : viaparinfo->depth); + via_set_source(viaparinfo->shared->iga1_devices, IGA1); + via_set_source(viaparinfo->shared->iga2_devices, IGA2); + if (viaparinfo->shared->iga2_devices) + enable_second_display_channel(); + else + disable_second_display_channel(); + /* Update Refresh Rate Setting */ /* Clear On Screen */ @@ -2394,8 +2505,6 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, viaparinfo->crt_setting_info->iga_path); } - set_crt_output_path(viaparinfo->crt_setting_info->iga_path); - /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode to 8 alignment (1368),there is several pixels (2 pixels) on right side of screen. */ @@ -2482,10 +2591,16 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, viafb_DeviceStatus = CRT_Device; } device_on(); + if (!viafb_dual_fb) + via_set_sync_polarity(devices, get_sync(viafbinfo)); + else { + via_set_sync_polarity(viaparinfo->shared->iga1_devices, + get_sync(viafbinfo)); + via_set_sync_polarity(viaparinfo->shared->iga2_devices, + get_sync(viafbinfo1)); + } - if (viafb_SAMM_ON == 1) - viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7); - + via_set_state(devices, VIA_STATE_ON); device_screen_on(); return 1; } @@ -2526,31 +2641,18 @@ int viafb_get_refresh(int hres, int vres, u32 long_refresh) static void device_off(void) { - viafb_crt_disable(); viafb_dvi_disable(); viafb_lcd_disable(); } static void device_on(void) { - if (viafb_CRT_ON == 1) - viafb_crt_enable(); if (viafb_DVI_ON == 1) viafb_dvi_enable(); if (viafb_LCD_ON == 1) viafb_lcd_enable(); } -void viafb_crt_disable(void) -{ - viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4); -} - -void viafb_crt_enable(void) -{ - viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4); -} - static void enable_second_display_channel(void) { /* to enable second display channel. */ @@ -2567,7 +2669,6 @@ static void disable_second_display_channel(void) viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); } - void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ *p_gfx_dpa_setting) { @@ -2652,4 +2753,9 @@ void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh, crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end); var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr; var->vsync_len = crt_reg.ver_sync_end; + var->sync = 0; + if (crt_timing[index].h_sync_polarity == POSITIVE) + var->sync |= FB_SYNC_HOR_HIGH_ACT; + if (crt_timing[index].v_sync_polarity == POSITIVE) + var->sync |= FB_SYNC_VERT_HIGH_ACT; } diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h index c443998..668d534 100644 --- a/drivers/video/via/hw.h +++ b/drivers/video/via/hw.h @@ -22,6 +22,8 @@ #ifndef __HW_H__ #define __HW_H__ +#include <linux/seq_file.h> + #include "viamode.h" #include "global.h" #include "via_modesetting.h" @@ -30,6 +32,25 @@ #define viafb_write_reg(i, p, d) via_write_reg(p, i, d) #define viafb_write_reg_mask(i, p, d, m) via_write_reg_mask(p, i, d, m) +/* VIA output devices */ +#define VIA_LDVP0 0x00000001 +#define VIA_LDVP1 0x00000002 +#define VIA_DVP0 0x00000004 +#define VIA_CRT 0x00000010 +#define VIA_DVP1 0x00000020 +#define VIA_LVDS1 0x00000040 +#define VIA_LVDS2 0x00000080 + +/* VIA output device power states */ +#define VIA_STATE_ON 0 +#define VIA_STATE_STANDBY 1 +#define VIA_STATE_SUSPEND 2 +#define VIA_STATE_OFF 3 + +/* VIA output device sync polarity */ +#define VIA_HSYNC_NEGATIVE 0x01 +#define VIA_VSYNC_NEGATIVE 0x02 + /*************************************************** * Definition IGA1 Design Method of CRTC Registers * ****************************************************/ @@ -341,6 +362,17 @@ is reserved, so it may have problem to set 1600x1200 on IGA2. */ #define VX855_IGA2_FIFO_HIGH_THRESHOLD 160 #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320 +/* For VT3410 */ +#define VX900_IGA1_FIFO_MAX_DEPTH 400 +#define VX900_IGA1_FIFO_THRESHOLD 320 +#define VX900_IGA1_FIFO_HIGH_THRESHOLD 320 +#define VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160 + +#define VX900_IGA2_FIFO_MAX_DEPTH 192 +#define VX900_IGA2_FIFO_THRESHOLD 160 +#define VX900_IGA2_FIFO_HIGH_THRESHOLD 160 +#define VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320 + #define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1 #define IGA1_FIFO_THRESHOLD_REG_NUM 2 #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2 @@ -858,6 +890,8 @@ struct iga2_crtc_timing { #define VX800_FUNCTION3 0x3353 /* VT3409 chipset*/ #define VX855_FUNCTION3 0x3409 +/* VT3410 chipset*/ +#define VX900_FUNCTION3 0x3410 #define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value) @@ -873,6 +907,11 @@ struct pci_device_id_info { u32 chip_index; }; +struct via_device_mapping { + u32 device; + const char *name; +}; + extern unsigned int viafb_second_virtual_xres; extern int viafb_SAMM_ON; extern int viafb_dual_fb; @@ -881,9 +920,6 @@ extern int viafb_LCD_ON; extern int viafb_DVI_ON; extern int viafb_hotplug; -void viafb_set_output_path(int device, int set_iga, - int output_interface); - void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, struct VideoModeTable *video_mode, int bpp_byte, int set_iga); @@ -891,8 +927,11 @@ void viafb_set_vclock(u32 CLK, int set_iga); void viafb_load_reg(int timing_value, int viafb_load_reg_num, struct io_register *reg, int io_type); -void viafb_crt_disable(void); -void viafb_crt_enable(void); +void via_set_source(u32 devices, u8 iga); +void via_set_state(u32 devices, u8 state); +void via_set_sync_polarity(u32 devices, u8 polarity); +u32 via_parse_odev(char *input, char **end); +void via_odev_to_seq(struct seq_file *m, u32 odev); void init_ad9389(void); /* Access I/O Function */ void viafb_lock_crt(void); @@ -908,8 +947,8 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, struct VideoModeTable *vmode_tbl1, int video_bpp1); void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh, struct VideoModeTable *vmode_tbl); -void viafb_init_chip_info(int chip_type); -void viafb_init_dac(int set_iga); +void __devinit viafb_init_chip_info(int chip_type); +void __devinit viafb_init_dac(int set_iga); int viafb_get_pixclock(int hres, int vres, int vmode_refresh); int viafb_get_refresh(int hres, int vres, u32 float_refresh); void viafb_update_device_setting(int hres, int vres, int bpp, diff --git a/drivers/video/via/ioctl.c b/drivers/video/via/ioctl.c index 4d553d0..ea1c514 100644 --- a/drivers/video/via/ioctl.c +++ b/drivers/video/via/ioctl.c @@ -94,6 +94,7 @@ int viafb_ioctl_hotplug(int hres, int vres, int bpp) viafb_CRT_ON = 0; viafb_LCD_ON = 0; viafb_DeviceStatus = DVI_Device; + viafb_set_iga_path(); return viafb_DeviceStatus; } status = 1; @@ -107,6 +108,7 @@ int viafb_ioctl_hotplug(int hres, int vres, int bpp) viafb_LCD_ON = 0; viafb_DeviceStatus = CRT_Device; + viafb_set_iga_path(); return viafb_DeviceStatus; } diff --git a/drivers/video/via/lcd.c b/drivers/video/via/lcd.c index fc25ae3..3425c39 100644 --- a/drivers/video/via/lcd.c +++ b/drivers/video/via/lcd.c @@ -21,10 +21,16 @@ #include <linux/via-core.h> #include <linux/via_i2c.h> #include "global.h" -#include "lcdtbl.h" #define viafb_compact_res(x, y) (((x)<<16)|(y)) +/* CLE266 Software Power Sequence */ +/* {Mask}, {Data}, {Delay} */ +int PowerSequenceOn[3][3] = { {0x10, 0x08, 0x06}, {0x10, 0x08, 0x06}, + {0x19, 0x1FE, 0x01} }; +int PowerSequenceOff[3][3] = { {0x06, 0x08, 0x10}, {0x00, 0x00, 0x00}, + {0xD2, 0x19, 0x01} }; + static struct _lcd_scaling_factor lcd_scaling_factor = { /* LCD Horizontal Scaling Factor Register */ {LCD_HOR_SCALING_FACTOR_REG_NUM, @@ -42,7 +48,7 @@ static struct _lcd_scaling_factor lcd_scaling_factor_CLE = { static int check_lvds_chip(int device_id_subaddr, int device_id); static bool lvds_identify_integratedlvds(void); -static void fp_id_to_vindex(int panel_id); +static void __devinit fp_id_to_vindex(int panel_id); static int lvds_register_read(int index); static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres, int panel_vres); @@ -84,7 +90,7 @@ static int check_lvds_chip(int device_id_subaddr, int device_id) return FAIL; } -void viafb_init_lcd_size(void) +void __devinit viafb_init_lcd_size(void) { DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n"); @@ -144,7 +150,7 @@ static bool lvds_identify_integratedlvds(void) return true; } -int viafb_lvds_trasmitter_identify(void) +int __devinit viafb_lvds_trasmitter_identify(void) { if (viafb_lvds_identify_vt1636(VIA_PORT_31)) { viaparinfo->chip_info->lvds_chip_info.i2c_port = VIA_PORT_31; @@ -185,7 +191,7 @@ int viafb_lvds_trasmitter_identify(void) return FAIL; } -static void fp_id_to_vindex(int panel_id) +static void __devinit fp_id_to_vindex(int panel_id) { DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n"); @@ -436,6 +442,7 @@ static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres, case UNICHROME_CN750: case UNICHROME_VX800: case UNICHROME_VX855: + case UNICHROME_VX900: reg_value = K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres); /* Horizontal scaling enabled */ @@ -479,6 +486,7 @@ static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres, case UNICHROME_CN750: case UNICHROME_VX800: case UNICHROME_VX855: + case UNICHROME_VX900: reg_value = K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres); /* Vertical scaling enabled */ @@ -655,9 +663,6 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk); DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N); viafb_set_vclock(pll_D_N, set_iga); - - viafb_set_output_path(DEVICE_LCD, set_iga, - plvds_chip_info->output_interface); lcd_patch_skew(plvds_setting_info, plvds_chip_info); /* If K8M800, enable LCD Prefetch Mode. */ @@ -700,9 +705,6 @@ static void integrated_lvds_disable(struct lvds_setting_information viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); } - /* Turn DFP High/Low Pad off. */ - viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3); - /* Power off LVDS channel. */ switch (plvds_chip_info->output_interface) { case INTERFACE_LVDS0: @@ -758,9 +760,6 @@ static void integrated_lvds_enable(struct lvds_setting_information break; } - /* Turn DFP High/Low pad on. */ - viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3); - /* Power on LVDS channel. */ switch (plvds_chip_info->output_interface) { case INTERFACE_LVDS0: @@ -809,29 +808,48 @@ void viafb_lcd_disable(void) viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info, &viaparinfo->chip_info->lvds_chip_info); } else { - /* DFP-HL pad off */ - viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F); /* Backlight off */ viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20); /* 24 bit DI data paht off */ viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80); - /* Simultaneout disabled */ - viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08); } /* Disable expansion bit */ viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01); - /* CRT path set to IGA1 */ - viafb_write_reg_mask(SR16, VIASR, 0x00, 0x40); /* Simultaneout disabled */ viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08); - /* IGA2 path disabled */ - viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80); +} +static void set_lcd_output_path(int set_iga, int output_interface) +{ + switch (output_interface) { + case INTERFACE_DFP: + if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name) + || (UNICHROME_P4M890 == + viaparinfo->chip_info->gfx_chip_name)) + viafb_write_reg_mask(CR97, VIACR, 0x84, + BIT7 + BIT2 + BIT1 + BIT0); + case INTERFACE_DVP0: + case INTERFACE_DVP1: + case INTERFACE_DFP_HIGH: + case INTERFACE_DFP_LOW: + if (set_iga == IGA2) + viafb_write_reg(CR91, VIACR, 0x00); + break; + } } void viafb_lcd_enable(void) { + viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3); + viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); + set_lcd_output_path(viaparinfo->lvds_setting_info->iga_path, + viaparinfo->chip_info->lvds_chip_info.output_interface); + if (viafb_LCD2_ON) + set_lcd_output_path(viaparinfo->lvds_setting_info2->iga_path, + viaparinfo->chip_info-> + lvds_chip_info2.output_interface); + if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { /* DI1 pad on */ viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30); @@ -855,39 +873,13 @@ void viafb_lcd_enable(void) viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info, &viaparinfo->chip_info->lvds_chip_info); } else { - /* DFP-HL pad on */ - viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F); /* Backlight on */ viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20); /* 24 bit DI data paht on */ viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80); - - /* Set data source selection bit by iga path */ - if (viaparinfo->lvds_setting_info->iga_path == IGA1) { - /* DFP-H set to IGA1 */ - viafb_write_reg_mask(CR97, VIACR, 0x00, 0x10); - /* DFP-L set to IGA1 */ - viafb_write_reg_mask(CR99, VIACR, 0x00, 0x10); - } else { - /* DFP-H set to IGA2 */ - viafb_write_reg_mask(CR97, VIACR, 0x10, 0x10); - /* DFP-L set to IGA2 */ - viafb_write_reg_mask(CR99, VIACR, 0x10, 0x10); - } /* LCD enabled */ viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48); } - - if (viaparinfo->lvds_setting_info->iga_path == IGA1) { - /* CRT path set to IGA2 */ - viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40); - /* IGA2 path disabled */ - viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80); - /* IGA2 path enabled */ - } else { /* IGA2 */ - viafb_write_reg_mask(CR6A, VIACR, 0x80, 0x80); - } - } static void lcd_powersequence_off(void) @@ -993,7 +985,7 @@ static void check_diport_of_integrated_lvds( plvds_chip_info->output_interface); } -void viafb_init_lvds_output_interface(struct lvds_chip_information +void __devinit viafb_init_lvds_output_interface(struct lvds_chip_information *plvds_chip_info, struct lvds_setting_information *plvds_setting_info) diff --git a/drivers/video/via/lcd.h b/drivers/video/via/lcd.h index b348efc..c7909fe 100644 --- a/drivers/video/via/lcd.h +++ b/drivers/video/via/lcd.h @@ -71,15 +71,15 @@ void viafb_enable_lvds_vt1636(struct lvds_setting_information struct lvds_chip_information *plvds_chip_info); void viafb_lcd_disable(void); void viafb_lcd_enable(void); -void viafb_init_lcd_size(void); -void viafb_init_lvds_output_interface(struct lvds_chip_information +void __devinit viafb_init_lcd_size(void); +void __devinit viafb_init_lvds_output_interface(struct lvds_chip_information *plvds_chip_info, struct lvds_setting_information *plvds_setting_info); void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, struct lvds_setting_information *plvds_setting_info, struct lvds_chip_information *plvds_chip_info); -int viafb_lvds_trasmitter_identify(void); +int __devinit viafb_lvds_trasmitter_identify(void); void viafb_init_lvds_output_interface(struct lvds_chip_information *plvds_chip_info, struct lvds_setting_information diff --git a/drivers/video/via/lcdtbl.h b/drivers/video/via/lcdtbl.h deleted file mode 100644 index 6f3dd80..0000000 --- a/drivers/video/via/lcdtbl.h +++ /dev/null @@ -1,591 +0,0 @@ -/* - * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. - * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. - - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public - * License as published by the Free Software Foundation; - * either version 2, or (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even - * the implied warranty of MERCHANTABILITY or FITNESS FOR - * A PARTICULAR PURPOSE.See the GNU General Public License - * for more details. - - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#ifndef __LCDTBL_H__ -#define __LCDTBL_H__ - -#include "share.h" - -/* CLE266 Software Power Sequence */ -/* {Mask}, {Data}, {Delay} */ -int PowerSequenceOn[3][3] = - { {0x10, 0x08, 0x06}, {0x10, 0x08, 0x06}, {0x19, 0x1FE, 0x01} }; -int PowerSequenceOff[3][3] = - { {0x06, 0x08, 0x10}, {0x00, 0x00, 0x00}, {0xD2, 0x19, 0x01} }; - -/* ++++++ P880 ++++++ */ -/* Panel 1600x1200 */ -struct io_reg P880_LCD_RES_6X4_16X12[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x73}, {VIACR, CR55, 0x0F, 0x08}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x73}, {VIACR, CR54, 0x38, 0x00}, - {VIACR, CR5D, 0x40, 0x40}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x5A}, {VIACR, CR71, 0x08, 0x00}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x5E}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xD6}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR44, 0xFF, 0x7D}, {VIASR, SR45, 0xFF, 0x8C}, - {VIASR, SR46, 0xFF, 0x02} - -}; - -#define NUM_TOTAL_P880_LCD_RES_6X4_16X12 ARRAY_SIZE(P880_LCD_RES_6X4_16X12) - -struct io_reg P880_LCD_RES_7X4_16X12[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x67}, {VIACR, CR55, 0x0F, 0x08}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x67}, {VIACR, CR54, 0x38, 0x00}, - {VIACR, CR5D, 0x40, 0x40}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x74}, {VIACR, CR71, 0x08, 0x00}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x78}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xF5}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR44, 0xFF, 0x78}, {VIASR, SR45, 0xFF, 0x8C}, - {VIASR, SR46, 0xFF, 0x01} - -}; - -#define NUM_TOTAL_P880_LCD_RES_7X4_16X12 ARRAY_SIZE(P880_LCD_RES_7X4_16X12) - -struct io_reg P880_LCD_RES_8X6_16X12[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x65}, {VIACR, CR55, 0x0F, 0x08}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x65}, {VIACR, CR54, 0x38, 0x00}, - {VIACR, CR5D, 0x40, 0x40}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x00}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x83}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xE1}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR44, 0xFF, 0x6D}, {VIASR, SR45, 0xFF, 0x88}, - {VIASR, SR46, 0xFF, 0x03} - -}; - -#define NUM_TOTAL_P880_LCD_RES_8X6_16X12 ARRAY_SIZE(P880_LCD_RES_8X6_16X12) - -struct io_reg P880_LCD_RES_10X7_16X12[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x65}, {VIACR, CR55, 0x0F, 0x08}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x65}, {VIACR, CR54, 0x38, 0x00}, - {VIACR, CR5D, 0x40, 0x40}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0xAB}, {VIACR, CR71, 0x08, 0x00}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0xAF}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xF0}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR44, 0xFF, 0x92}, {VIASR, SR45, 0xFF, 0x88}, - {VIASR, SR46, 0xFF, 0x03} - -}; - -#define NUM_TOTAL_P880_LCD_RES_10X7_16X12 ARRAY_SIZE(P880_LCD_RES_10X7_16X12) - -struct io_reg P880_LCD_RES_12X10_16X12[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x7D}, {VIACR, CR55, 0x0F, 0x08}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x7D}, {VIACR, CR54, 0x38, 0x00}, - {VIACR, CR5D, 0x40, 0x40}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0xD0}, {VIACR, CR71, 0x08, 0x00}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0xD4}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xFA}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR44, 0xFF, 0xF6}, {VIASR, SR45, 0xFF, 0x88}, - {VIASR, SR46, 0xFF, 0x05} - -}; - -#define NUM_TOTAL_P880_LCD_RES_12X10_16X12 ARRAY_SIZE(P880_LCD_RES_12X10_16X12) - -/* Panel 1400x1050 */ -struct io_reg P880_LCD_RES_6X4_14X10[] = { - /* 640x480 */ - /* IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56}, - /* IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75}, - {VIACR, CR5D, 0x40, 0x24}, - /* IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x5F}, {VIACR, CR71, 0x08, 0x44}, - /* IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x63}, - /* IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xB4}, {VIACR, CR67, 0x03, 0x00}, - /* VCLK */ - {VIASR, SR44, 0xFF, 0xC6}, {VIASR, SR45, 0xFF, 0x8C}, - {VIASR, SR46, 0xFF, 0x05} -}; - -#define NUM_TOTAL_P880_LCD_RES_6X4_14X10 ARRAY_SIZE(P880_LCD_RES_6X4_14X10) - -struct io_reg P880_LCD_RES_8X6_14X10[] = { - /* 800x600 */ - /* IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56}, - /* IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75}, - {VIACR, CR5D, 0x40, 0x24}, - /* IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x44}, - /* IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x83}, - /* IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xBE}, {VIACR, CR67, 0x03, 0x00}, - /* VCLK */ - {VIASR, SR44, 0xFF, 0x06}, {VIASR, SR45, 0xFF, 0x8D}, - {VIASR, SR46, 0xFF, 0x05} -}; - -#define NUM_TOTAL_P880_LCD_RES_8X6_14X10 ARRAY_SIZE(P880_LCD_RES_8X6_14X10) - -/* ++++++ K400 ++++++ */ -/* Panel 1600x1200 */ -struct io_reg K400_LCD_RES_6X4_16X12[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x73}, {VIACR, CR55, 0x0F, 0x08}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x73}, {VIACR, CR54, 0x38, 0x00}, - {VIACR, CR5D, 0x40, 0x40}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x5A}, {VIACR, CR71, 0x08, 0x00}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x5E}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xDA}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0xC4}, {VIASR, SR47, 0xFF, 0x7F} -}; - -#define NUM_TOTAL_K400_LCD_RES_6X4_16X12 ARRAY_SIZE(K400_LCD_RES_6X4_16X12) - -struct io_reg K400_LCD_RES_7X4_16X12[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x67}, {VIACR, CR55, 0x0F, 0x08}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x67}, {VIACR, CR54, 0x38, 0x00}, - {VIACR, CR5D, 0x40, 0x40}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x74}, {VIACR, CR71, 0x08, 0x00}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x78}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xF5}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0x46}, {VIASR, SR47, 0xFF, 0x3D} -}; - -#define NUM_TOTAL_K400_LCD_RES_7X4_16X12 ARRAY_SIZE(K400_LCD_RES_7X4_16X12) - -struct io_reg K400_LCD_RES_8X6_16X12[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x65}, {VIACR, CR55, 0x0F, 0x08}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x65}, {VIACR, CR54, 0x38, 0x00}, - {VIACR, CR5D, 0x40, 0x40}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x00}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x83}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xE1}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0x85}, {VIASR, SR47, 0xFF, 0x6F} -}; - -#define NUM_TOTAL_K400_LCD_RES_8X6_16X12 ARRAY_SIZE(K400_LCD_RES_8X6_16X12) - -struct io_reg K400_LCD_RES_10X7_16X12[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x65}, {VIACR, CR55, 0x0F, 0x08}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x65}, {VIACR, CR54, 0x38, 0x00}, - {VIACR, CR5D, 0x40, 0x40}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0xAB}, {VIACR, CR71, 0x08, 0x00}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0xAF}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xF0}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0x45}, {VIASR, SR47, 0xFF, 0x4A} -}; - -#define NUM_TOTAL_K400_LCD_RES_10X7_16X12 ARRAY_SIZE(K400_LCD_RES_10X7_16X12) - -struct io_reg K400_LCD_RES_12X10_16X12[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x7D}, {VIACR, CR55, 0x0F, 0x08}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x7D}, {VIACR, CR54, 0x38, 0x00}, - {VIACR, CR5D, 0x40, 0x40}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0xD0}, {VIACR, CR71, 0x08, 0x00}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0xD4}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xFA}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0x47}, {VIASR, SR47, 0xFF, 0x7C} -}; - -#define NUM_TOTAL_K400_LCD_RES_12X10_16X12 ARRAY_SIZE(K400_LCD_RES_12X10_16X12) - -/* Panel 1400x1050 */ -struct io_reg K400_LCD_RES_6X4_14X10[] = { - /* 640x400 */ - /* IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56}, - /* IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75}, - {VIACR, CR5D, 0x40, 0x24}, - /* IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x5F}, {VIACR, CR71, 0x08, 0x44}, - /* IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x63}, - /* IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xB4}, {VIACR, CR67, 0x03, 0x00}, - /* VCLK */ - {VIASR, SR46, 0xFF, 0x07}, {VIASR, SR47, 0xFF, 0x19} -}; - -#define NUM_TOTAL_K400_LCD_RES_6X4_14X10 ARRAY_SIZE(K400_LCD_RES_6X4_14X10) - -struct io_reg K400_LCD_RES_8X6_14X10[] = { - /* 800x600 */ - /* IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56}, - /* IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75}, - {VIACR, CR5D, 0x40, 0x24}, - /* IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x44}, - /* IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x83}, - /* IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xBE}, {VIACR, CR67, 0x03, 0x00}, - /* VCLK */ - {VIASR, SR46, 0xFF, 0x07}, {VIASR, SR47, 0xFF, 0x21} -}; - -#define NUM_TOTAL_K400_LCD_RES_8X6_14X10 ARRAY_SIZE(K400_LCD_RES_8X6_14X10) - -struct io_reg K400_LCD_RES_10X7_14X10[] = { - /* 1024x768 */ - /* IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56}, - /* IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75}, - {VIACR, CR5D, 0x40, 0x24}, - /* IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0xA3}, {VIACR, CR71, 0x08, 0x44}, - /* IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0xA7}, - /* IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xC3}, {VIACR, CR67, 0x03, 0x04}, - /* VCLK */ - {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x1E} -}; - -#define NUM_TOTAL_K400_LCD_RES_10X7_14X10 ARRAY_SIZE(K400_LCD_RES_10X7_14X10) - -struct io_reg K400_LCD_RES_12X10_14X10[] = { - /* 1280x768, 1280x960, 1280x1024 */ - /* IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x97}, {VIACR, CR55, 0x0F, 0x56}, - /* IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x97}, {VIACR, CR54, 0x38, 0x75}, - {VIACR, CR5D, 0x40, 0x24}, - /* IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0xCE}, {VIACR, CR71, 0x08, 0x44}, - /* IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0xD2}, - /* IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xC9}, {VIACR, CR67, 0x03, 0x04}, - /* VCLK */ - {VIASR, SR46, 0xFF, 0x84}, {VIASR, SR47, 0xFF, 0x79} -}; - -#define NUM_TOTAL_K400_LCD_RES_12X10_14X10 ARRAY_SIZE(K400_LCD_RES_12X10_14X10) - -/* ++++++ K400 ++++++ */ -/* Panel 1366x768 */ -struct io_reg K400_LCD_RES_6X4_1366X7[] = { - /* 640x400 */ - /* IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x47}, {VIACR, CR55, 0x0F, 0x35}, - /* IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x47}, {VIACR, CR54, 0x38, 0x2B}, - {VIACR, CR5D, 0x40, 0x13}, - /* IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x60}, {VIACR, CR71, 0x08, 0x23}, - /* IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x64}, - /* IGA2 Offset */ - {VIACR, CR66, 0xFF, 0x8C}, {VIACR, CR67, 0x03, 0x00}, - /* VCLK */ - {VIASR, SR46, 0xFF, 0x87}, {VIASR, SR47, 0xFF, 0x4C} -}; - -#define NUM_TOTAL_K400_LCD_RES_6X4_1366X7 ARRAY_SIZE(K400_LCD_RES_6X4_1366X7) - -struct io_reg K400_LCD_RES_7X4_1366X7[] = { - /* IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x3B}, {VIACR, CR55, 0x0F, 0x35}, - /* IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x3B}, {VIACR, CR54, 0x38, 0x2B}, - {VIACR, CR5D, 0x40, 0x13}, - /* IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x71}, {VIACR, CR71, 0x08, 0x23}, - /* IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x75}, - /* IGA2 Offset */ - {VIACR, CR66, 0xFF, 0x96}, {VIACR, CR67, 0x03, 0x00}, - /* VCLK */ - {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x10} -}; - -#define NUM_TOTAL_K400_LCD_RES_7X4_1366X7 ARRAY_SIZE(K400_LCD_RES_7X4_1366X7) - -struct io_reg K400_LCD_RES_8X6_1366X7[] = { - /* 800x600 */ - /* IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x37}, {VIACR, CR55, 0x0F, 0x35}, - /* IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x37}, {VIACR, CR54, 0x38, 0x2B}, - {VIACR, CR5D, 0x40, 0x13}, - /* IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x7E}, {VIACR, CR71, 0x08, 0x23}, - /* IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x82}, - /* IGA2 Offset */ - {VIACR, CR66, 0xFF, 0x8C}, {VIACR, CR67, 0x03, 0x00}, - /* VCLK */ - {VIASR, SR46, 0xFF, 0x84}, {VIASR, SR47, 0xFF, 0xB9} -}; - -#define NUM_TOTAL_K400_LCD_RES_8X6_1366X7 ARRAY_SIZE(K400_LCD_RES_8X6_1366X7) - -struct io_reg K400_LCD_RES_10X7_1366X7[] = { - /* 1024x768 */ - /* IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56}, - /* IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75}, - {VIACR, CR5D, 0x40, 0x24}, - /* IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0xA3}, {VIACR, CR71, 0x08, 0x44}, - /* IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0xA7}, - /* IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xC3}, {VIACR, CR67, 0x03, 0x04}, - /* VCLK */ - {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x1E} -}; - -#define NUM_TOTAL_K400_LCD_RES_10X7_1366X7 ARRAY_SIZE(K400_LCD_RES_10X7_1366X7) - -struct io_reg K400_LCD_RES_12X10_1366X7[] = { - /* 1280x768, 1280x960, 1280x1024 */ - /* IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x97}, {VIACR, CR55, 0x0F, 0x56}, - /* IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x97}, {VIACR, CR54, 0x38, 0x75}, - {VIACR, CR5D, 0x40, 0x24}, - /* IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0xCE}, {VIACR, CR71, 0x08, 0x44}, - /* IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0xD2}, - /* IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xC9}, {VIACR, CR67, 0x03, 0x04}, - /* VCLK */ - {VIASR, SR46, 0xFF, 0x84}, {VIASR, SR47, 0xFF, 0x79} -}; - -#define NUM_TOTAL_K400_LCD_RES_12X10_1366X7\ - ARRAY_SIZE(K400_LCD_RES_12X10_1366X7) - -/* ++++++ K400 ++++++ */ -/* Panel 1280x1024 */ -struct io_reg K400_LCD_RES_6X4_12X10[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x46}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x74}, - {VIACR, CR5D, 0x40, 0x1C}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x5F}, {VIACR, CR71, 0x08, 0x34}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x63}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xAA}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0x07}, {VIASR, SR47, 0xFF, 0x19} -}; - -#define NUM_TOTAL_K400_LCD_RES_6X4_12X10 ARRAY_SIZE(K400_LCD_RES_6X4_12X10) - -struct io_reg K400_LCD_RES_7X4_12X10[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x46}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x74}, - {VIACR, CR5D, 0x40, 0x1C}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x68}, {VIACR, CR71, 0x08, 0x34}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x6C}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xA8}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0x87}, {VIASR, SR47, 0xFF, 0xED} -}; - -#define NUM_TOTAL_K400_LCD_RES_7X4_12X10 ARRAY_SIZE(K400_LCD_RES_7X4_12X10) - -struct io_reg K400_LCD_RES_8X6_12X10[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x46}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x74}, - {VIACR, CR5D, 0x40, 0x1C}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x34}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x83}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xBE}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0x07}, {VIASR, SR47, 0xFF, 0x21} -}; - -#define NUM_TOTAL_K400_LCD_RES_8X6_12X10 ARRAY_SIZE(K400_LCD_RES_8X6_12X10) - -struct io_reg K400_LCD_RES_10X7_12X10[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x46}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x74}, - {VIACR, CR5D, 0x40, 0x1C}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0xA3}, {VIACR, CR71, 0x08, 0x34}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0xA7}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0xBE}, {VIACR, CR67, 0x03, 0x04}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x1E} -}; - -#define NUM_TOTAL_K400_LCD_RES_10X7_12X10 ARRAY_SIZE(K400_LCD_RES_10X7_12X10) - -/* ++++++ K400 ++++++ */ -/* Panel 1024x768 */ -struct io_reg K400_LCD_RES_6X4_10X7[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x47}, {VIACR, CR55, 0x0F, 0x35}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x47}, {VIACR, CR54, 0x38, 0x2B}, - {VIACR, CR5D, 0x40, 0x13}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x60}, {VIACR, CR71, 0x08, 0x23}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x64}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0x8C}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0x87}, {VIASR, SR47, 0xFF, 0x4C} -}; - -#define NUM_TOTAL_K400_LCD_RES_6X4_10X7 ARRAY_SIZE(K400_LCD_RES_6X4_10X7) - -struct io_reg K400_LCD_RES_7X4_10X7[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x3B}, {VIACR, CR55, 0x0F, 0x35}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x3B}, {VIACR, CR54, 0x38, 0x2B}, - {VIACR, CR5D, 0x40, 0x13}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x71}, {VIACR, CR71, 0x08, 0x23}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x75}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0x96}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x10} -}; - -#define NUM_TOTAL_K400_LCD_RES_7X4_10X7 ARRAY_SIZE(K400_LCD_RES_7X4_10X7) - -struct io_reg K400_LCD_RES_8X6_10X7[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x37}, {VIACR, CR55, 0x0F, 0x35}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x37}, {VIACR, CR54, 0x38, 0x2B}, - {VIACR, CR5D, 0x40, 0x13}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x7E}, {VIACR, CR71, 0x08, 0x23}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x82}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0x8C}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0x84}, {VIASR, SR47, 0xFF, 0xB9} -}; - -#define NUM_TOTAL_K400_LCD_RES_8X6_10X7 ARRAY_SIZE(K400_LCD_RES_8X6_10X7) - -/* ++++++ K400 ++++++ */ -/* Panel 800x600 */ -struct io_reg K400_LCD_RES_6X4_8X6[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x1A}, {VIACR, CR55, 0x0F, 0x34}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x1A}, {VIACR, CR54, 0x38, 0xE3}, - {VIACR, CR5D, 0x40, 0x12}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x5F}, {VIACR, CR71, 0x08, 0x22}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x63}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0x6E}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0x86}, {VIASR, SR47, 0xFF, 0xB3} -}; - -#define NUM_TOTAL_K400_LCD_RES_6X4_8X6 ARRAY_SIZE(K400_LCD_RES_6X4_8X6) - -struct io_reg K400_LCD_RES_7X4_8X6[] = { - /*IGA2 Horizontal Total */ - {VIACR, CR50, 0xFF, 0x1F}, {VIACR, CR55, 0x0F, 0x34}, - /*IGA2 Horizontal Blank End */ - {VIACR, CR53, 0xFF, 0x1F}, {VIACR, CR54, 0x38, 0xE3}, - {VIACR, CR5D, 0x40, 0x12}, - /*IGA2 Horizontal Total Shadow */ - {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x22}, - /*IGA2 Horizontal Blank End Shadow */ - {VIACR, CR6E, 0xFF, 0x83}, - /*IGA2 Offset */ - {VIACR, CR66, 0xFF, 0x78}, {VIACR, CR67, 0x03, 0x00}, - /*VCLK*/ {VIASR, SR46, 0xFF, 0xC4}, {VIASR, SR47, 0xFF, 0x59} -}; - -#define NUM_TOTAL_K400_LCD_RES_7X4_8X6 ARRAY_SIZE(K400_LCD_RES_7X4_8X6) - -#endif /* __LCDTBL_H__ */ diff --git a/drivers/video/via/tbl1636.c b/drivers/video/via/tbl1636.c deleted file mode 100644 index 2d84534..0000000 --- a/drivers/video/via/tbl1636.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. - * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. - - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public - * License as published by the Free Software Foundation; - * either version 2, or (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even - * the implied warranty of MERCHANTABILITY or FITNESS FOR - * A PARTICULAR PURPOSE.See the GNU General Public License - * for more details. - - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#include "global.h" -struct IODATA COMMON_INIT_TBL_VT1636[] = { -/* Index, Mask, Value */ - /* Set panel power sequence timing */ - {0x10, 0xC0, 0x00}, - /* T1: VDD on - Data on. Each increment is 1 ms. (50ms = 031h) */ - {0x0B, 0xFF, 0x40}, - /* T2: Data on - Backlight on. Each increment is 2 ms. (210ms = 068h) */ - {0x0C, 0xFF, 0x31}, - /* T3: Backlight off -Data off. Each increment is 2 ms. (210ms = 068h)*/ - {0x0D, 0xFF, 0x31}, - /* T4: Data off - VDD off. Each increment is 1 ms. (50ms = 031h) */ - {0x0E, 0xFF, 0x68}, - /* T5: VDD off - VDD on. Each increment is 100 ms. (500ms = 04h) */ - {0x0F, 0xFF, 0x68}, - /* LVDS output power up */ - {0x09, 0xA0, 0xA0}, - /* turn on back light */ - {0x10, 0x33, 0x13} -}; - -struct IODATA DUAL_CHANNEL_ENABLE_TBL_VT1636[] = { -/* Index, Mask, Value */ - {0x08, 0xF0, 0xE0} /* Input Data Mode Select */ -}; - -struct IODATA SINGLE_CHANNEL_ENABLE_TBL_VT1636[] = { -/* Index, Mask, Value */ - {0x08, 0xF0, 0x00} /* Input Data Mode Select */ -}; - -struct IODATA DITHERING_ENABLE_TBL_VT1636[] = { -/* Index, Mask, Value */ - {0x0A, 0x70, 0x50} -}; - -struct IODATA DITHERING_DISABLE_TBL_VT1636[] = { -/* Index, Mask, Value */ - {0x0A, 0x70, 0x00} -}; - -struct IODATA VDD_ON_TBL_VT1636[] = { -/* Index, Mask, Value */ - {0x10, 0x20, 0x20} -}; - -struct IODATA VDD_OFF_TBL_VT1636[] = { -/* Index, Mask, Value */ - {0x10, 0x20, 0x00} -}; diff --git a/drivers/video/via/tbl1636.h b/drivers/video/via/tbl1636.h deleted file mode 100644 index d906055..0000000 --- a/drivers/video/via/tbl1636.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. - * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. - - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public - * License as published by the Free Software Foundation; - * either version 2, or (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even - * the implied warranty of MERCHANTABILITY or FITNESS FOR - * A PARTICULAR PURPOSE.See the GNU General Public License - * for more details. - - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef _TBL1636_H_ -#define _TBL1636_H_ -#include "hw.h" - -extern struct IODATA COMMON_INIT_TBL_VT1636[8]; -extern struct IODATA DUAL_CHANNEL_ENABLE_TBL_VT1636[1]; -extern struct IODATA SINGLE_CHANNEL_ENABLE_TBL_VT1636[1]; -extern struct IODATA DITHERING_ENABLE_TBL_VT1636[1]; -extern struct IODATA DITHERING_DISABLE_TBL_VT1636[1]; -extern struct IODATA VDD_ON_TBL_VT1636[1]; -extern struct IODATA VDD_OFF_TBL_VT1636[1]; - -#endif /* _VIA_TBL1636_H_ */ diff --git a/drivers/video/via/via-core.c b/drivers/video/via/via-core.c index 27d7260..a3aa917 100644 --- a/drivers/video/via/via-core.c +++ b/drivers/video/via/via-core.c @@ -20,7 +20,7 @@ * The default port config. */ static struct via_port_cfg adap_configs[] = { - [VIA_PORT_26] = { VIA_PORT_I2C, VIA_MODE_OFF, VIASR, 0x26 }, + [VIA_PORT_26] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x26 }, [VIA_PORT_31] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x31 }, [VIA_PORT_25] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x25 }, [VIA_PORT_2C] = { VIA_PORT_GPIO, VIA_MODE_I2C, VIASR, 0x2c }, @@ -340,7 +340,7 @@ EXPORT_SYMBOL_GPL(viafb_dma_copy_out_sg); static u16 via_function3[] = { CLE266_FUNCTION3, KM400_FUNCTION3, CN400_FUNCTION3, CN700_FUNCTION3, CX700_FUNCTION3, KM800_FUNCTION3, KM890_FUNCTION3, P4M890_FUNCTION3, - P4M900_FUNCTION3, VX800_FUNCTION3, VX855_FUNCTION3, + P4M900_FUNCTION3, VX800_FUNCTION3, VX855_FUNCTION3, VX900_FUNCTION3, }; /* Get the BIOS-configured framebuffer size from PCI configuration space @@ -377,6 +377,7 @@ static int viafb_get_fb_size_from_pci(int chip_type) case P4M900_FUNCTION3: case VX800_FUNCTION3: case VX855_FUNCTION3: + case VX900_FUNCTION3: /*case CN750_FUNCTION3: */ offset = 0xA0; break; @@ -481,7 +482,10 @@ static int __devinit via_pci_setup_mmio(struct viafb_dev *vdev) * Eventually we want to move away from mapping this * entire region. */ - vdev->fbmem_start = pci_resource_start(vdev->pdev, 0); + if (vdev->chip_type == UNICHROME_VX900) + vdev->fbmem_start = pci_resource_start(vdev->pdev, 2); + else + vdev->fbmem_start = pci_resource_start(vdev->pdev, 0); ret = vdev->fbmem_len = viafb_get_fb_size_from_pci(vdev->chip_type); if (ret < 0) goto out_unmap; @@ -647,6 +651,8 @@ static struct pci_device_id via_pci_table[] __devinitdata = { .driver_data = UNICHROME_VX800 }, { PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_VX855_DID), .driver_data = UNICHROME_VX855 }, + { PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_VX900_DID), + .driver_data = UNICHROME_VX900 }, { } }; MODULE_DEVICE_TABLE(pci, via_pci_table); @@ -656,6 +662,10 @@ static struct pci_driver via_driver = { .id_table = via_pci_table, .probe = via_pci_probe, .remove = __devexit_p(via_pci_remove), +#ifdef CONFIG_PM + .suspend = viafb_suspend, + .resume = viafb_resume, +#endif }; static int __init via_core_init(void) diff --git a/drivers/video/via/via_i2c.c b/drivers/video/via/via_i2c.c index da9e4ca..3844b55 100644 --- a/drivers/video/via/via_i2c.c +++ b/drivers/video/via/via_i2c.c @@ -114,6 +114,7 @@ static void via_i2c_setsda(void *data, int state) int viafb_i2c_readbyte(u8 adap, u8 slave_addr, u8 index, u8 *pdata) { + int ret; u8 mm1[] = {0x00}; struct i2c_msg msgs[2]; @@ -126,11 +127,18 @@ int viafb_i2c_readbyte(u8 adap, u8 slave_addr, u8 index, u8 *pdata) mm1[0] = index; msgs[0].len = 1; msgs[1].len = 1; msgs[0].buf = mm1; msgs[1].buf = pdata; - return i2c_transfer(&via_i2c_par[adap].adapter, msgs, 2); + ret = i2c_transfer(&via_i2c_par[adap].adapter, msgs, 2); + if (ret == 2) + ret = 0; + else if (ret >= 0) + ret = -EIO; + + return ret; } int viafb_i2c_writebyte(u8 adap, u8 slave_addr, u8 index, u8 data) { + int ret; u8 msg[2] = { index, data }; struct i2c_msg msgs; @@ -140,11 +148,18 @@ int viafb_i2c_writebyte(u8 adap, u8 slave_addr, u8 index, u8 data) msgs.addr = slave_addr / 2; msgs.len = 2; msgs.buf = msg; - return i2c_transfer(&via_i2c_par[adap].adapter, &msgs, 1); + ret = i2c_transfer(&via_i2c_par[adap].adapter, &msgs, 1); + if (ret == 1) + ret = 0; + else if (ret >= 0) + ret = -EIO; + + return ret; } int viafb_i2c_readbytes(u8 adap, u8 slave_addr, u8 index, u8 *buff, int buff_len) { + int ret; u8 mm1[] = {0x00}; struct i2c_msg msgs[2]; @@ -156,7 +171,13 @@ int viafb_i2c_readbytes(u8 adap, u8 slave_addr, u8 index, u8 *buff, int buff_len mm1[0] = index; msgs[0].len = 1; msgs[1].len = buff_len; msgs[0].buf = mm1; msgs[1].buf = buff; - return i2c_transfer(&via_i2c_par[adap].adapter, msgs, 2); + ret = i2c_transfer(&via_i2c_par[adap].adapter, msgs, 2); + if (ret == 2) + ret = 0; + else if (ret >= 0) + ret = -EIO; + + return ret; } /* @@ -181,8 +202,8 @@ static int create_i2c_bus(struct i2c_adapter *adapter, algo->setscl = via_i2c_setscl; algo->getsda = via_i2c_getsda; algo->getscl = via_i2c_getscl; - algo->udelay = 40; - algo->timeout = 20; + algo->udelay = 10; + algo->timeout = 2; algo->data = adap_cfg; sprintf(adapter->name, "viafb i2c io_port idx 0x%02x", diff --git a/drivers/video/via/viafbdev.c b/drivers/video/via/viafbdev.c index bdd0e41..d298cfc 100644 --- a/drivers/video/via/viafbdev.c +++ b/drivers/video/via/viafbdev.c @@ -56,6 +56,32 @@ static int viafb_pan_display(struct fb_var_screeninfo *var, static struct fb_ops viafb_ops; +/* supported output devices on each IGP + * only CX700, VX800, VX855, VX900 were documented + * VIA_CRT should be everywhere + * VIA_6C can be onle pre-CX700 (probably only on CLE266) as 6C is used for PLL + * source selection on CX700 and later + * K400 seems to support VIA_96, VIA_DVP1, VIA_LVDS{1,2} as in viamode.c + */ +static const u32 supported_odev_map[] = { + [UNICHROME_CLE266] = VIA_CRT | VIA_LDVP0 | VIA_LDVP1, + [UNICHROME_K400] = VIA_CRT | VIA_DVP0 | VIA_DVP1 | VIA_LVDS1 + | VIA_LVDS2, + [UNICHROME_K800] = VIA_CRT | VIA_DVP0 | VIA_DVP1 | VIA_LVDS1 + | VIA_LVDS2, + [UNICHROME_PM800] = VIA_CRT | VIA_DVP0 | VIA_DVP1 | VIA_LVDS1 + | VIA_LVDS2, + [UNICHROME_CN700] = VIA_CRT | VIA_DVP0 | VIA_DVP1 | VIA_LVDS1 + | VIA_LVDS2, + [UNICHROME_CX700] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2, + [UNICHROME_CN750] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2, + [UNICHROME_K8M890] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2, + [UNICHROME_P4M890] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2, + [UNICHROME_P4M900] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2, + [UNICHROME_VX800] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2, + [UNICHROME_VX855] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2, + [UNICHROME_VX900] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2, +}; static void viafb_fill_var_color_info(struct fb_var_screeninfo *var, u8 depth) { @@ -332,22 +358,22 @@ static int viafb_blank(int blank_mode, struct fb_info *info) case FB_BLANK_UNBLANK: /* Screen: On, HSync: On, VSync: On */ /* control CRT monitor power management */ - viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5); + via_set_state(VIA_CRT, VIA_STATE_ON); break; case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off, HSync: Off, VSync: On */ /* control CRT monitor power management */ - viafb_write_reg_mask(CR36, VIACR, 0x10, BIT4 + BIT5); + via_set_state(VIA_CRT, VIA_STATE_STANDBY); break; case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off, HSync: On, VSync: Off */ /* control CRT monitor power management */ - viafb_write_reg_mask(CR36, VIACR, 0x20, BIT4 + BIT5); + via_set_state(VIA_CRT, VIA_STATE_SUSPEND); break; case FB_BLANK_POWERDOWN: /* Screen: Off, HSync: Off, VSync: Off */ /* control CRT monitor power management */ - viafb_write_reg_mask(CR36, VIACR, 0x30, BIT4 + BIT5); + via_set_state(VIA_CRT, VIA_STATE_OFF); break; } @@ -457,7 +483,7 @@ static int viafb_ioctl(struct fb_info *info, u_int cmd, u_long arg) if (copy_from_user(&gpu32, argp, sizeof(gpu32))) return -EFAULT; if (gpu32 & CRT_Device) - viafb_crt_enable(); + via_set_state(VIA_CRT, VIA_STATE_ON); if (gpu32 & DVI_Device) viafb_dvi_enable(); if (gpu32 & LCD_Device) @@ -467,7 +493,7 @@ static int viafb_ioctl(struct fb_info *info, u_int cmd, u_long arg) if (copy_from_user(&gpu32, argp, sizeof(gpu32))) return -EFAULT; if (gpu32 & CRT_Device) - viafb_crt_disable(); + via_set_state(VIA_CRT, VIA_STATE_OFF); if (gpu32 & DVI_Device) viafb_dvi_disable(); if (gpu32 & LCD_Device) @@ -787,7 +813,8 @@ static int viafb_cursor(struct fb_info *info, struct fb_cursor *cursor) bg_color = cursor->image.bg_color; if (chip_name == UNICHROME_CX700 || chip_name == UNICHROME_VX800 || - chip_name == UNICHROME_VX855) { + chip_name == UNICHROME_VX855 || + chip_name == UNICHROME_VX900) { fg_color = ((info->cmap.red[fg_color] & 0xFFC0) << 14) | ((info->cmap.green[fg_color] & 0xFFC0) << 4) | @@ -961,7 +988,7 @@ static void retrieve_device_setting(struct viafb_ioctl_setting setting_info->lcd_attributes.lcd_mode = viafb_lcd_mode; } -static int parse_active_dev(void) +static int __init parse_active_dev(void) { viafb_CRT_ON = STATE_OFF; viafb_DVI_ON = STATE_OFF; @@ -1031,7 +1058,7 @@ static int parse_active_dev(void) return 0; } -static int parse_port(char *opt_str, int *output_interface) +static int __devinit parse_port(char *opt_str, int *output_interface) { if (!strncmp(opt_str, "DVP0", 4)) *output_interface = INTERFACE_DVP0; @@ -1048,7 +1075,7 @@ static int parse_port(char *opt_str, int *output_interface) return 0; } -static void parse_lcd_port(void) +static void __devinit parse_lcd_port(void) { parse_port(viafb_lcd_port, &viaparinfo->chip_info->lvds_chip_info. output_interface); @@ -1061,7 +1088,7 @@ static void parse_lcd_port(void) output_interface); } -static void parse_dvi_port(void) +static void __devinit parse_dvi_port(void) { parse_port(viafb_dvi_port, &viaparinfo->chip_info->tmds_chip_info. output_interface); @@ -1431,38 +1458,196 @@ static const struct file_operations viafb_vt1636_proc_fops = { .write = viafb_vt1636_proc_write, }; -static void viafb_init_proc(struct proc_dir_entry **viafb_entry) +#endif /* CONFIG_FB_VIA_DIRECT_PROCFS */ + +static int viafb_sup_odev_proc_show(struct seq_file *m, void *v) { - *viafb_entry = proc_mkdir("viafb", NULL); - if (*viafb_entry) { - proc_create("dvp0", 0, *viafb_entry, &viafb_dvp0_proc_fops); - proc_create("dvp1", 0, *viafb_entry, &viafb_dvp1_proc_fops); - proc_create("dfph", 0, *viafb_entry, &viafb_dfph_proc_fops); - proc_create("dfpl", 0, *viafb_entry, &viafb_dfpl_proc_fops); - if (VT1636_LVDS == viaparinfo->chip_info->lvds_chip_info. - lvds_chip_name || VT1636_LVDS == - viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) { - proc_create("vt1636", 0, *viafb_entry, &viafb_vt1636_proc_fops); - } + via_odev_to_seq(m, supported_odev_map[ + viaparinfo->shared->chip_info.gfx_chip_name]); + return 0; +} + +static int viafb_sup_odev_proc_open(struct inode *inode, struct file *file) +{ + return single_open(file, viafb_sup_odev_proc_show, NULL); +} + +static const struct file_operations viafb_sup_odev_proc_fops = { + .owner = THIS_MODULE, + .open = viafb_sup_odev_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static ssize_t odev_update(const char __user *buffer, size_t count, u32 *odev) +{ + char buf[64], *ptr = buf; + u32 devices; + bool add, sub; + + if (count < 1 || count > 63) + return -EINVAL; + if (copy_from_user(&buf[0], buffer, count)) + return -EFAULT; + buf[count] = '\0'; + add = buf[0] == '+'; + sub = buf[0] == '-'; + if (add || sub) + ptr++; + devices = via_parse_odev(ptr, &ptr); + if (*ptr == '\n') + ptr++; + if (*ptr != 0) + return -EINVAL; + if (add) + *odev |= devices; + else if (sub) + *odev &= ~devices; + else + *odev = devices; + return count; +} + +static int viafb_iga1_odev_proc_show(struct seq_file *m, void *v) +{ + via_odev_to_seq(m, viaparinfo->shared->iga1_devices); + return 0; +} + +static int viafb_iga1_odev_proc_open(struct inode *inode, struct file *file) +{ + return single_open(file, viafb_iga1_odev_proc_show, NULL); +} + +static ssize_t viafb_iga1_odev_proc_write(struct file *file, + const char __user *buffer, size_t count, loff_t *pos) +{ + u32 dev_on, dev_off, dev_old, dev_new; + ssize_t res; + + dev_old = dev_new = viaparinfo->shared->iga1_devices; + res = odev_update(buffer, count, &dev_new); + if (res != count) + return res; + dev_off = dev_old & ~dev_new; + dev_on = dev_new & ~dev_old; + viaparinfo->shared->iga1_devices = dev_new; + viaparinfo->shared->iga2_devices &= ~dev_new; + via_set_state(dev_off, VIA_STATE_OFF); + via_set_source(dev_new, IGA1); + via_set_state(dev_on, VIA_STATE_ON); + return res; +} + +static const struct file_operations viafb_iga1_odev_proc_fops = { + .owner = THIS_MODULE, + .open = viafb_iga1_odev_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = viafb_iga1_odev_proc_write, +}; + +static int viafb_iga2_odev_proc_show(struct seq_file *m, void *v) +{ + via_odev_to_seq(m, viaparinfo->shared->iga2_devices); + return 0; +} +static int viafb_iga2_odev_proc_open(struct inode *inode, struct file *file) +{ + return single_open(file, viafb_iga2_odev_proc_show, NULL); +} + +static ssize_t viafb_iga2_odev_proc_write(struct file *file, + const char __user *buffer, size_t count, loff_t *pos) +{ + u32 dev_on, dev_off, dev_old, dev_new; + ssize_t res; + + dev_old = dev_new = viaparinfo->shared->iga2_devices; + res = odev_update(buffer, count, &dev_new); + if (res != count) + return res; + dev_off = dev_old & ~dev_new; + dev_on = dev_new & ~dev_old; + viaparinfo->shared->iga2_devices = dev_new; + viaparinfo->shared->iga1_devices &= ~dev_new; + via_set_state(dev_off, VIA_STATE_OFF); + via_set_source(dev_new, IGA2); + via_set_state(dev_on, VIA_STATE_ON); + return res; +} + +static const struct file_operations viafb_iga2_odev_proc_fops = { + .owner = THIS_MODULE, + .open = viafb_iga2_odev_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = viafb_iga2_odev_proc_write, +}; + +#define IS_VT1636(lvds_chip) ((lvds_chip).lvds_chip_name == VT1636_LVDS) +static void viafb_init_proc(struct viafb_shared *shared) +{ + struct proc_dir_entry *iga1_entry, *iga2_entry, + *viafb_entry = proc_mkdir("viafb", NULL); + + shared->proc_entry = viafb_entry; + if (viafb_entry) { +#ifdef CONFIG_FB_VIA_DIRECT_PROCFS + proc_create("dvp0", 0, viafb_entry, &viafb_dvp0_proc_fops); + proc_create("dvp1", 0, viafb_entry, &viafb_dvp1_proc_fops); + proc_create("dfph", 0, viafb_entry, &viafb_dfph_proc_fops); + proc_create("dfpl", 0, viafb_entry, &viafb_dfpl_proc_fops); + if (IS_VT1636(shared->chip_info.lvds_chip_info) + || IS_VT1636(shared->chip_info.lvds_chip_info2)) + proc_create("vt1636", 0, viafb_entry, + &viafb_vt1636_proc_fops); +#endif /* CONFIG_FB_VIA_DIRECT_PROCFS */ + + proc_create("supported_output_devices", 0, viafb_entry, + &viafb_sup_odev_proc_fops); + iga1_entry = proc_mkdir("iga1", viafb_entry); + shared->iga1_proc_entry = iga1_entry; + proc_create("output_devices", 0, iga1_entry, + &viafb_iga1_odev_proc_fops); + iga2_entry = proc_mkdir("iga2", viafb_entry); + shared->iga2_proc_entry = iga2_entry; + proc_create("output_devices", 0, iga2_entry, + &viafb_iga2_odev_proc_fops); } } -static void viafb_remove_proc(struct proc_dir_entry *viafb_entry) +static void viafb_remove_proc(struct viafb_shared *shared) { - struct chip_information *chip_info = &viaparinfo->shared->chip_info; + struct proc_dir_entry *viafb_entry = shared->proc_entry, + *iga1_entry = shared->iga1_proc_entry, + *iga2_entry = shared->iga2_proc_entry; + if (!viafb_entry) + return; + + remove_proc_entry("output_devices", iga2_entry); + remove_proc_entry("iga2", viafb_entry); + remove_proc_entry("output_devices", iga1_entry); + remove_proc_entry("iga1", viafb_entry); + remove_proc_entry("supported_output_devices", viafb_entry); + +#ifdef CONFIG_FB_VIA_DIRECT_PROCFS remove_proc_entry("dvp0", viafb_entry);/* parent dir */ remove_proc_entry("dvp1", viafb_entry); remove_proc_entry("dfph", viafb_entry); remove_proc_entry("dfpl", viafb_entry); - if (chip_info->lvds_chip_info.lvds_chip_name == VT1636_LVDS - || chip_info->lvds_chip_info2.lvds_chip_name == VT1636_LVDS) + if (IS_VT1636(shared->chip_info.lvds_chip_info) + || IS_VT1636(shared->chip_info.lvds_chip_info2)) remove_proc_entry("vt1636", viafb_entry); +#endif /* CONFIG_FB_VIA_DIRECT_PROCFS */ remove_proc_entry("viafb", NULL); } - -#endif /* CONFIG_FB_VIA_DIRECT_PROCFS */ +#undef IS_VT1636 static int parse_mode(const char *str, u32 *xres, u32 *yres) { @@ -1486,6 +1671,47 @@ static int parse_mode(const char *str, u32 *xres, u32 *yres) } +#ifdef CONFIG_PM +int viafb_suspend(struct pci_dev *pdev, pm_message_t state) +{ + if (state.event == PM_EVENT_SUSPEND) { + acquire_console_sem(); + fb_set_suspend(viafbinfo, 1); + + viafb_sync(viafbinfo); + + pci_save_state(pdev); + pci_disable_device(pdev); + pci_set_power_state(pdev, pci_choose_state(pdev, state)); + release_console_sem(); + } + + return 0; +} + +int viafb_resume(struct pci_dev *pdev) +{ + acquire_console_sem(); + pci_set_power_state(pdev, PCI_D0); + pci_restore_state(pdev); + if (pci_enable_device(pdev)) + goto fail; + pci_set_master(pdev); + if (viaparinfo->shared->vdev->engine_mmio) + viafb_reset_engine(viaparinfo); + viafb_set_par(viafbinfo); + if (viafb_dual_fb) + viafb_set_par(viafbinfo1); + fb_set_suspend(viafbinfo, 0); + +fail: + release_console_sem(); + return 0; +} + +#endif + + int __devinit via_fb_pci_probe(struct viafb_dev *vdev) { u32 default_xres, default_yres; @@ -1544,7 +1770,7 @@ int __devinit via_fb_pci_probe(struct viafb_dev *vdev) viafbinfo->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; viafbinfo->pseudo_palette = pseudo_pal; - if (viafb_accel && !viafb_init_engine(viafbinfo)) { + if (viafb_accel && !viafb_setup_engine(viafbinfo)) { viafbinfo->flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_IMAGEBLIT; default_var.accel_flags = FB_ACCELF_TEXT; @@ -1671,9 +1897,7 @@ int __devinit via_fb_pci_probe(struct viafb_dev *vdev) viafbinfo->node, viafbinfo->fix.id, default_var.xres, default_var.yres, default_var.bits_per_pixel); -#ifdef CONFIG_FB_VIA_DIRECT_PROCFS - viafb_init_proc(&viaparinfo->shared->proc_entry); -#endif + viafb_init_proc(viaparinfo->shared); viafb_init_dac(IGA2); return 0; @@ -1700,9 +1924,7 @@ void __devexit via_fb_pci_remove(struct pci_dev *pdev) unregister_framebuffer(viafbinfo); if (viafb_dual_fb) unregister_framebuffer(viafbinfo1); -#ifdef CONFIG_FB_VIA_DIRECT_PROCFS - viafb_remove_proc(viaparinfo->shared->proc_entry); -#endif + viafb_remove_proc(viaparinfo->shared); framebuffer_release(viafbinfo); if (viafb_dual_fb) framebuffer_release(viafbinfo1); diff --git a/drivers/video/via/viafbdev.h b/drivers/video/via/viafbdev.h index 52a35fa..4960e3d 100644 --- a/drivers/video/via/viafbdev.h +++ b/drivers/video/via/viafbdev.h @@ -40,7 +40,12 @@ #define VIAFB_NUM_I2C 5 struct viafb_shared { + u32 iga1_devices; + u32 iga2_devices; + struct proc_dir_entry *proc_entry; /*viafb proc entry */ + struct proc_dir_entry *iga1_proc_entry; + struct proc_dir_entry *iga2_proc_entry; struct viafb_dev *vdev; /* Global dev info */ /* All the information will be needed to set engine */ @@ -103,4 +108,6 @@ void via_fb_pci_remove(struct pci_dev *pdev); /* Temporary */ int viafb_init(void); void viafb_exit(void); +int viafb_suspend(struct pci_dev *pdev, pm_message_t state); +int viafb_resume(struct pci_dev *pdev); #endif /* __VIAFBDEV_H__ */ diff --git a/drivers/video/via/vt1636.c b/drivers/video/via/vt1636.c index d65bf1a..60e4192 100644 --- a/drivers/video/via/vt1636.c +++ b/drivers/video/via/vt1636.c @@ -23,6 +23,34 @@ #include <linux/via_i2c.h> #include "global.h" +static const struct IODATA common_init_data[] = { +/* Index, Mask, Value */ + /* Set panel power sequence timing */ + {0x10, 0xC0, 0x00}, + /* T1: VDD on - Data on. Each increment is 1 ms. (50ms = 031h) */ + {0x0B, 0xFF, 0x40}, + /* T2: Data on - Backlight on. Each increment is 2 ms. (210ms = 068h) */ + {0x0C, 0xFF, 0x31}, + /* T3: Backlight off -Data off. Each increment is 2 ms. (210ms = 068h)*/ + {0x0D, 0xFF, 0x31}, + /* T4: Data off - VDD off. Each increment is 1 ms. (50ms = 031h) */ + {0x0E, 0xFF, 0x68}, + /* T5: VDD off - VDD on. Each increment is 100 ms. (500ms = 04h) */ + {0x0F, 0xFF, 0x68}, + /* LVDS output power up */ + {0x09, 0xA0, 0xA0}, + /* turn on back light */ + {0x10, 0x33, 0x13} +}; + +/* Index, Mask, Value */ +static const struct IODATA dual_channel_enable_data = {0x08, 0xF0, 0xE0}; +static const struct IODATA single_channel_enable_data = {0x08, 0xF0, 0x00}; +static const struct IODATA dithering_enable_data = {0x0A, 0x70, 0x50}; +static const struct IODATA dithering_disable_data = {0x0A, 0x70, 0x00}; +static const struct IODATA vdd_on_data = {0x10, 0x20, 0x20}; +static const struct IODATA vdd_off_data = {0x10, 0x20, 0x00}; + u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information *plvds_setting_info, struct lvds_chip_information *plvds_chip_info, u8 index) @@ -55,108 +83,41 @@ void viafb_init_lvds_vt1636(struct lvds_setting_information int reg_num, i; /* Common settings: */ - reg_num = ARRAY_SIZE(COMMON_INIT_TBL_VT1636); - - for (i = 0; i < reg_num; i++) { + reg_num = ARRAY_SIZE(common_init_data); + for (i = 0; i < reg_num; i++) viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, - plvds_chip_info, - COMMON_INIT_TBL_VT1636[i]); - } + plvds_chip_info, common_init_data[i]); /* Input Data Mode Select */ - if (plvds_setting_info->device_lcd_dualedge) { + if (plvds_setting_info->device_lcd_dualedge) viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, - plvds_chip_info, - DUAL_CHANNEL_ENABLE_TBL_VT1636[0]); - } else { + plvds_chip_info, dual_channel_enable_data); + else viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, - plvds_chip_info, - SINGLE_CHANNEL_ENABLE_TBL_VT1636[0]); - } + plvds_chip_info, single_channel_enable_data); - if (plvds_setting_info->LCDDithering) { + if (plvds_setting_info->LCDDithering) viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, - plvds_chip_info, - DITHERING_ENABLE_TBL_VT1636[0]); - } else { + plvds_chip_info, dithering_enable_data); + else viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, - plvds_chip_info, - DITHERING_DISABLE_TBL_VT1636[0]); - } + plvds_chip_info, dithering_disable_data); } void viafb_enable_lvds_vt1636(struct lvds_setting_information *plvds_setting_info, struct lvds_chip_information *plvds_chip_info) { - viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info, - VDD_ON_TBL_VT1636[0]); - - /* Pad on: */ - switch (plvds_chip_info->output_interface) { - case INTERFACE_DVP0: - { - viafb_write_reg_mask(SR1E, VIASR, 0xC0, 0xC0); - break; - } - - case INTERFACE_DVP1: - { - viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30); - break; - } - - case INTERFACE_DFP_LOW: - { - viafb_write_reg_mask(SR2A, VIASR, 0x03, 0x03); - break; - } - - case INTERFACE_DFP_HIGH: - { - viafb_write_reg_mask(SR2A, VIASR, 0x03, 0x0C); - break; - } - - } + vdd_on_data); } void viafb_disable_lvds_vt1636(struct lvds_setting_information *plvds_setting_info, struct lvds_chip_information *plvds_chip_info) { - viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info, - VDD_OFF_TBL_VT1636[0]); - - /* Pad off: */ - switch (plvds_chip_info->output_interface) { - case INTERFACE_DVP0: - { - viafb_write_reg_mask(SR1E, VIASR, 0x00, 0xC0); - break; - } - - case INTERFACE_DVP1: - { - viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30); - break; - } - - case INTERFACE_DFP_LOW: - { - viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x03); - break; - } - - case INTERFACE_DFP_HIGH: - { - viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0C); - break; - } - - } + vdd_off_data); } bool viafb_lvds_identify_vt1636(u8 i2c_adapter) diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c index 0c9ce88..68bd234 100644 --- a/drivers/video/xilinxfb.c +++ b/drivers/video/xilinxfb.c @@ -32,10 +32,14 @@ #include <linux/dma-mapping.h> #include <linux/of_device.h> #include <linux/of_platform.h> +#include <linux/of_address.h> #include <linux/io.h> #include <linux/xilinxfb.h> #include <linux/slab.h> + +#ifdef CONFIG_PPC_DCR #include <asm/dcr.h> +#endif #define DRIVER_NAME "xilinxfb" @@ -123,10 +127,10 @@ struct xilinxfb_drvdata { registers */ void __iomem *regs; /* virt. address of the control registers */ - +#ifdef CONFIG_PPC_DCR dcr_host_t dcr_host; unsigned int dcr_len; - +#endif void *fb_virt; /* virt. address of the frame buffer */ dma_addr_t fb_phys; /* phys. address of the frame buffer */ int fb_alloced; /* Flag, was the fb memory alloced? */ @@ -152,9 +156,10 @@ static void xilinx_fb_out_be32(struct xilinxfb_drvdata *drvdata, u32 offset, { if (drvdata->flags & PLB_ACCESS_FLAG) out_be32(drvdata->regs + (offset << 2), val); +#ifdef CONFIG_PPC_DCR else dcr_write(drvdata->dcr_host, offset, val); - +#endif } static int @@ -383,8 +388,11 @@ static int xilinxfb_release(struct device *dev) if (drvdata->flags & PLB_ACCESS_FLAG) { iounmap(drvdata->regs); release_mem_region(drvdata->regs_phys, 8); - } else + } +#ifdef CONFIG_PPC_DCR + else dcr_unmap(drvdata->dcr_host, drvdata->dcr_len); +#endif kfree(drvdata); dev_set_drvdata(dev, NULL); @@ -404,7 +412,7 @@ xilinxfb_of_probe(struct platform_device *op, const struct of_device_id *match) u32 tft_access; struct xilinxfb_platform_data pdata; struct resource res; - int size, rc, start; + int size, rc; struct xilinxfb_drvdata *drvdata; /* Copy with the default pdata (not a ptr reference!) */ @@ -437,7 +445,10 @@ xilinxfb_of_probe(struct platform_device *op, const struct of_device_id *match) dev_err(&op->dev, "invalid address\n"); goto err; } - } else { + } +#ifdef CONFIG_PPC_DCR + else { + int start; res.start = 0; start = dcr_resource_start(op->dev.of_node, 0); drvdata->dcr_len = dcr_resource_len(op->dev.of_node, 0); @@ -447,6 +458,7 @@ xilinxfb_of_probe(struct platform_device *op, const struct of_device_id *match) goto err; } } +#endif prop = of_get_property(op->dev.of_node, "phys-size", &size); if ((prop) && (size >= sizeof(u32)*2)) { |
