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path: root/drivers/video/aty/aty128fb.c
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Diffstat (limited to 'drivers/video/aty/aty128fb.c')
-rw-r--r--drivers/video/aty/aty128fb.c36
1 files changed, 24 insertions, 12 deletions
diff --git a/drivers/video/aty/aty128fb.c b/drivers/video/aty/aty128fb.c
index fb2b0f5..35e8eb0 100644
--- a/drivers/video/aty/aty128fb.c
+++ b/drivers/video/aty/aty128fb.c
@@ -1853,13 +1853,14 @@ static void aty128_bl_exit(struct backlight_device *bd)
* Initialisation
*/
-#ifdef CONFIG_PPC_PMAC
+#ifdef CONFIG_PPC_PMAC__disabled
static void aty128_early_resume(void *data)
{
struct aty128fb_par *par = data;
if (try_acquire_console_sem())
return;
+ pci_restore_state(par->pdev);
aty128_do_resume(par->pdev);
release_console_sem();
}
@@ -1907,7 +1908,14 @@ static int __devinit aty128_init(struct pci_dev *pdev, const struct pci_device_i
/* Indicate sleep capability */
if (par->chip_gen == rage_M3) {
pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
+#if 0 /* Disable the early video resume hack for now as it's causing problems, among
+ * others we now rely on the PCI core restoring the config space for us, which
+ * isn't the case with that hack, and that code path causes various things to
+ * be called with interrupts off while they shouldn't. I'm leaving the code in
+ * as it can be useful for debugging purposes
+ */
pmac_set_early_video_resume(aty128_early_resume, par);
+#endif
}
/* Find default mode */
@@ -2365,7 +2373,6 @@ static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx
static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
{
u32 pmgt;
- u16 pwr_command;
struct pci_dev *pdev = par->pdev;
if (!par->pm_reg)
@@ -2374,6 +2381,8 @@ static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
/* Set the chip into the appropriate suspend mode (we use D2,
* D3 would require a complete re-initialisation of the chip,
* including PCI config registers, clocks, AGP configuration, ...)
+ *
+ * For resume, the core will have already brought us back to D0
*/
if (suspend) {
/* Make sure CRTC2 is reset. Remove that the day we decide to
@@ -2391,17 +2400,9 @@ static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
aty_st_le32(BUS_CNTL1, 0x00000010);
aty_st_le32(MEM_POWER_MISC, 0x0c830000);
mdelay(100);
- pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
+
/* Switch PCI power management to D2 */
- pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL,
- (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2);
- pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
- } else {
- /* Switch back PCI power management to D0 */
- mdelay(100);
- pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 0);
- pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
- mdelay(100);
+ pci_set_power_state(pdev, PCI_D2);
}
}
@@ -2410,6 +2411,12 @@ static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
struct fb_info *info = pci_get_drvdata(pdev);
struct aty128fb_par *par = info->par;
+ /* Because we may change PCI D state ourselves, we need to
+ * first save the config space content so the core can
+ * restore it properly on resume.
+ */
+ pci_save_state(pdev);
+
/* We don't do anything but D2, for now we return 0, but
* we may want to change that. How do we know if the BIOS
* can properly take care of D3 ? Also, with swsusp, we
@@ -2476,6 +2483,11 @@ static int aty128_do_resume(struct pci_dev *pdev)
if (pdev->dev.power.power_state.event == PM_EVENT_ON)
return 0;
+ /* PCI state will have been restored by the core, so
+ * we should be in D0 now with our config space fully
+ * restored
+ */
+
/* Wakeup chip */
aty128_set_suspend(par, 0);
par->asleep = 0;
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