diff options
Diffstat (limited to 'drivers/staging')
27 files changed, 957 insertions, 1616 deletions
diff --git a/drivers/staging/iio/accel/Makefile b/drivers/staging/iio/accel/Makefile index febb137..5d8ad21 100644 --- a/drivers/staging/iio/accel/Makefile +++ b/drivers/staging/iio/accel/Makefile @@ -2,14 +2,7 @@ # Makefile for industrial I/O accelerometer drivers # -adis16201-y := adis16201_core.o obj-$(CONFIG_ADIS16201) += adis16201.o - -adis16203-y := adis16203_core.o obj-$(CONFIG_ADIS16203) += adis16203.o - -adis16209-y := adis16209_core.o obj-$(CONFIG_ADIS16209) += adis16209.o - -adis16240-y := adis16240_core.o obj-$(CONFIG_ADIS16240) += adis16240.o diff --git a/drivers/staging/iio/accel/adis16201_core.c b/drivers/staging/iio/accel/adis16201.c index 7963d4a..d6c8658 100644 --- a/drivers/staging/iio/accel/adis16201_core.c +++ b/drivers/staging/iio/accel/adis16201.c @@ -20,7 +20,145 @@ #include <linux/iio/buffer.h> #include <linux/iio/imu/adis.h> -#include "adis16201.h" +#define ADIS16201_STARTUP_DELAY 220 /* ms */ + +/* Flash memory write count */ +#define ADIS16201_FLASH_CNT 0x00 + +/* Output, power supply */ +#define ADIS16201_SUPPLY_OUT 0x02 + +/* Output, x-axis accelerometer */ +#define ADIS16201_XACCL_OUT 0x04 + +/* Output, y-axis accelerometer */ +#define ADIS16201_YACCL_OUT 0x06 + +/* Output, auxiliary ADC input */ +#define ADIS16201_AUX_ADC 0x08 + +/* Output, temperature */ +#define ADIS16201_TEMP_OUT 0x0A + +/* Output, x-axis inclination */ +#define ADIS16201_XINCL_OUT 0x0C + +/* Output, y-axis inclination */ +#define ADIS16201_YINCL_OUT 0x0E + +/* Calibration, x-axis acceleration offset */ +#define ADIS16201_XACCL_OFFS 0x10 + +/* Calibration, y-axis acceleration offset */ +#define ADIS16201_YACCL_OFFS 0x12 + +/* x-axis acceleration scale factor */ +#define ADIS16201_XACCL_SCALE 0x14 + +/* y-axis acceleration scale factor */ +#define ADIS16201_YACCL_SCALE 0x16 + +/* Calibration, x-axis inclination offset */ +#define ADIS16201_XINCL_OFFS 0x18 + +/* Calibration, y-axis inclination offset */ +#define ADIS16201_YINCL_OFFS 0x1A + +/* x-axis inclination scale factor */ +#define ADIS16201_XINCL_SCALE 0x1C + +/* y-axis inclination scale factor */ +#define ADIS16201_YINCL_SCALE 0x1E + +/* Alarm 1 amplitude threshold */ +#define ADIS16201_ALM_MAG1 0x20 + +/* Alarm 2 amplitude threshold */ +#define ADIS16201_ALM_MAG2 0x22 + +/* Alarm 1, sample period */ +#define ADIS16201_ALM_SMPL1 0x24 + +/* Alarm 2, sample period */ +#define ADIS16201_ALM_SMPL2 0x26 + +/* Alarm control */ +#define ADIS16201_ALM_CTRL 0x28 + +/* Auxiliary DAC data */ +#define ADIS16201_AUX_DAC 0x30 + +/* General-purpose digital input/output control */ +#define ADIS16201_GPIO_CTRL 0x32 + +/* Miscellaneous control */ +#define ADIS16201_MSC_CTRL 0x34 + +/* Internal sample period (rate) control */ +#define ADIS16201_SMPL_PRD 0x36 + +/* Operation, filter configuration */ +#define ADIS16201_AVG_CNT 0x38 + +/* Operation, sleep mode control */ +#define ADIS16201_SLP_CNT 0x3A + +/* Diagnostics, system status register */ +#define ADIS16201_DIAG_STAT 0x3C + +/* Operation, system command register */ +#define ADIS16201_GLOB_CMD 0x3E + +/* MSC_CTRL */ + +/* Self-test enable */ +#define ADIS16201_MSC_CTRL_SELF_TEST_EN BIT(8) + +/* Data-ready enable: 1 = enabled, 0 = disabled */ +#define ADIS16201_MSC_CTRL_DATA_RDY_EN BIT(2) + +/* Data-ready polarity: 1 = active high, 0 = active low */ +#define ADIS16201_MSC_CTRL_ACTIVE_HIGH BIT(1) + +/* Data-ready line selection: 1 = DIO1, 0 = DIO0 */ +#define ADIS16201_MSC_CTRL_DATA_RDY_DIO1 BIT(0) + +/* DIAG_STAT */ + +/* Alarm 2 status: 1 = alarm active, 0 = alarm inactive */ +#define ADIS16201_DIAG_STAT_ALARM2 BIT(9) + +/* Alarm 1 status: 1 = alarm active, 0 = alarm inactive */ +#define ADIS16201_DIAG_STAT_ALARM1 BIT(8) + +/* SPI communications failure */ +#define ADIS16201_DIAG_STAT_SPI_FAIL_BIT 3 + +/* Flash update failure */ +#define ADIS16201_DIAG_STAT_FLASH_UPT_BIT 2 + +/* Power supply above 3.625 V */ +#define ADIS16201_DIAG_STAT_POWER_HIGH_BIT 1 + +/* Power supply below 3.15 V */ +#define ADIS16201_DIAG_STAT_POWER_LOW_BIT 0 + +/* GLOB_CMD */ + +#define ADIS16201_GLOB_CMD_SW_RESET BIT(7) +#define ADIS16201_GLOB_CMD_FACTORY_CAL BIT(1) + +#define ADIS16201_ERROR_ACTIVE BIT(14) + +enum adis16201_scan { + ADIS16201_SCAN_ACC_X, + ADIS16201_SCAN_ACC_Y, + ADIS16201_SCAN_INCLI_X, + ADIS16201_SCAN_INCLI_Y, + ADIS16201_SCAN_SUPPLY, + ADIS16201_SCAN_AUX_ADC, + ADIS16201_SCAN_TEMP, +}; static const u8 adis16201_addresses[] = { [ADIS16201_SCAN_ACC_X] = ADIS16201_XACCL_OFFS, diff --git a/drivers/staging/iio/accel/adis16201.h b/drivers/staging/iio/accel/adis16201.h deleted file mode 100644 index 64844ad..0000000 --- a/drivers/staging/iio/accel/adis16201.h +++ /dev/null @@ -1,144 +0,0 @@ -#ifndef SPI_ADIS16201_H_ -#define SPI_ADIS16201_H_ - -#define ADIS16201_STARTUP_DELAY 220 /* ms */ - -/* Flash memory write count */ -#define ADIS16201_FLASH_CNT 0x00 - -/* Output, power supply */ -#define ADIS16201_SUPPLY_OUT 0x02 - -/* Output, x-axis accelerometer */ -#define ADIS16201_XACCL_OUT 0x04 - -/* Output, y-axis accelerometer */ -#define ADIS16201_YACCL_OUT 0x06 - -/* Output, auxiliary ADC input */ -#define ADIS16201_AUX_ADC 0x08 - -/* Output, temperature */ -#define ADIS16201_TEMP_OUT 0x0A - -/* Output, x-axis inclination */ -#define ADIS16201_XINCL_OUT 0x0C - -/* Output, y-axis inclination */ -#define ADIS16201_YINCL_OUT 0x0E - -/* Calibration, x-axis acceleration offset */ -#define ADIS16201_XACCL_OFFS 0x10 - -/* Calibration, y-axis acceleration offset */ -#define ADIS16201_YACCL_OFFS 0x12 - -/* x-axis acceleration scale factor */ -#define ADIS16201_XACCL_SCALE 0x14 - -/* y-axis acceleration scale factor */ -#define ADIS16201_YACCL_SCALE 0x16 - -/* Calibration, x-axis inclination offset */ -#define ADIS16201_XINCL_OFFS 0x18 - -/* Calibration, y-axis inclination offset */ -#define ADIS16201_YINCL_OFFS 0x1A - -/* x-axis inclination scale factor */ -#define ADIS16201_XINCL_SCALE 0x1C - -/* y-axis inclination scale factor */ -#define ADIS16201_YINCL_SCALE 0x1E - -/* Alarm 1 amplitude threshold */ -#define ADIS16201_ALM_MAG1 0x20 - -/* Alarm 2 amplitude threshold */ -#define ADIS16201_ALM_MAG2 0x22 - -/* Alarm 1, sample period */ -#define ADIS16201_ALM_SMPL1 0x24 - -/* Alarm 2, sample period */ -#define ADIS16201_ALM_SMPL2 0x26 - -/* Alarm control */ -#define ADIS16201_ALM_CTRL 0x28 - -/* Auxiliary DAC data */ -#define ADIS16201_AUX_DAC 0x30 - -/* General-purpose digital input/output control */ -#define ADIS16201_GPIO_CTRL 0x32 - -/* Miscellaneous control */ -#define ADIS16201_MSC_CTRL 0x34 - -/* Internal sample period (rate) control */ -#define ADIS16201_SMPL_PRD 0x36 - -/* Operation, filter configuration */ -#define ADIS16201_AVG_CNT 0x38 - -/* Operation, sleep mode control */ -#define ADIS16201_SLP_CNT 0x3A - -/* Diagnostics, system status register */ -#define ADIS16201_DIAG_STAT 0x3C - -/* Operation, system command register */ -#define ADIS16201_GLOB_CMD 0x3E - -/* MSC_CTRL */ - -/* Self-test enable */ -#define ADIS16201_MSC_CTRL_SELF_TEST_EN BIT(8) - -/* Data-ready enable: 1 = enabled, 0 = disabled */ -#define ADIS16201_MSC_CTRL_DATA_RDY_EN BIT(2) - -/* Data-ready polarity: 1 = active high, 0 = active low */ -#define ADIS16201_MSC_CTRL_ACTIVE_HIGH BIT(1) - -/* Data-ready line selection: 1 = DIO1, 0 = DIO0 */ -#define ADIS16201_MSC_CTRL_DATA_RDY_DIO1 BIT(0) - -/* DIAG_STAT */ - -/* Alarm 2 status: 1 = alarm active, 0 = alarm inactive */ -#define ADIS16201_DIAG_STAT_ALARM2 BIT(9) - -/* Alarm 1 status: 1 = alarm active, 0 = alarm inactive */ -#define ADIS16201_DIAG_STAT_ALARM1 BIT(8) - -/* SPI communications failure */ -#define ADIS16201_DIAG_STAT_SPI_FAIL_BIT 3 - -/* Flash update failure */ -#define ADIS16201_DIAG_STAT_FLASH_UPT_BIT 2 - -/* Power supply above 3.625 V */ -#define ADIS16201_DIAG_STAT_POWER_HIGH_BIT 1 - -/* Power supply below 3.15 V */ -#define ADIS16201_DIAG_STAT_POWER_LOW_BIT 0 - -/* GLOB_CMD */ - -#define ADIS16201_GLOB_CMD_SW_RESET BIT(7) -#define ADIS16201_GLOB_CMD_FACTORY_CAL BIT(1) - -#define ADIS16201_ERROR_ACTIVE BIT(14) - -enum adis16201_scan { - ADIS16201_SCAN_ACC_X, - ADIS16201_SCAN_ACC_Y, - ADIS16201_SCAN_INCLI_X, - ADIS16201_SCAN_INCLI_Y, - ADIS16201_SCAN_SUPPLY, - ADIS16201_SCAN_AUX_ADC, - ADIS16201_SCAN_TEMP, -}; - -#endif /* SPI_ADIS16201_H_ */ diff --git a/drivers/staging/iio/accel/adis16203_core.c b/drivers/staging/iio/accel/adis16203.c index bd8119a..68189ad 100644 --- a/drivers/staging/iio/accel/adis16203_core.c +++ b/drivers/staging/iio/accel/adis16203.c @@ -7,20 +7,140 @@ */ #include <linux/delay.h> -#include <linux/mutex.h> #include <linux/device.h> + +#include <linux/iio/buffer.h> +#include <linux/iio/iio.h> +#include <linux/iio/imu/adis.h> +#include <linux/iio/sysfs.h> + #include <linux/kernel.h> -#include <linux/spi/spi.h> +#include <linux/module.h> +#include <linux/mutex.h> #include <linux/slab.h> +#include <linux/spi/spi.h> #include <linux/sysfs.h> -#include <linux/module.h> -#include <linux/iio/iio.h> -#include <linux/iio/sysfs.h> -#include <linux/iio/buffer.h> -#include <linux/iio/imu/adis.h> +#define ADIS16203_STARTUP_DELAY 220 /* ms */ + +/* Flash memory write count */ +#define ADIS16203_FLASH_CNT 0x00 + +/* Output, power supply */ +#define ADIS16203_SUPPLY_OUT 0x02 + +/* Output, auxiliary ADC input */ +#define ADIS16203_AUX_ADC 0x08 + +/* Output, temperature */ +#define ADIS16203_TEMP_OUT 0x0A + +/* Output, x-axis inclination */ +#define ADIS16203_XINCL_OUT 0x0C + +/* Output, y-axis inclination */ +#define ADIS16203_YINCL_OUT 0x0E + +/* Incline null calibration */ +#define ADIS16203_INCL_NULL 0x18 + +/* Alarm 1 amplitude threshold */ +#define ADIS16203_ALM_MAG1 0x20 + +/* Alarm 2 amplitude threshold */ +#define ADIS16203_ALM_MAG2 0x22 + +/* Alarm 1, sample period */ +#define ADIS16203_ALM_SMPL1 0x24 + +/* Alarm 2, sample period */ +#define ADIS16203_ALM_SMPL2 0x26 + +/* Alarm control */ +#define ADIS16203_ALM_CTRL 0x28 -#include "adis16203.h" +/* Auxiliary DAC data */ +#define ADIS16203_AUX_DAC 0x30 + +/* General-purpose digital input/output control */ +#define ADIS16203_GPIO_CTRL 0x32 + +/* Miscellaneous control */ +#define ADIS16203_MSC_CTRL 0x34 + +/* Internal sample period (rate) control */ +#define ADIS16203_SMPL_PRD 0x36 + +/* Operation, filter configuration */ +#define ADIS16203_AVG_CNT 0x38 + +/* Operation, sleep mode control */ +#define ADIS16203_SLP_CNT 0x3A + +/* Diagnostics, system status register */ +#define ADIS16203_DIAG_STAT 0x3C + +/* Operation, system command register */ +#define ADIS16203_GLOB_CMD 0x3E + +/* MSC_CTRL */ + +/* Self-test at power-on: 1 = disabled, 0 = enabled */ +#define ADIS16203_MSC_CTRL_PWRUP_SELF_TEST BIT(10) + +/* Reverses rotation of both inclination outputs */ +#define ADIS16203_MSC_CTRL_REVERSE_ROT_EN BIT(9) + +/* Self-test enable */ +#define ADIS16203_MSC_CTRL_SELF_TEST_EN BIT(8) + +/* Data-ready enable: 1 = enabled, 0 = disabled */ +#define ADIS16203_MSC_CTRL_DATA_RDY_EN BIT(2) + +/* Data-ready polarity: 1 = active high, 0 = active low */ +#define ADIS16203_MSC_CTRL_ACTIVE_HIGH BIT(1) + +/* Data-ready line selection: 1 = DIO1, 0 = DIO0 */ +#define ADIS16203_MSC_CTRL_DATA_RDY_DIO1 BIT(0) + +/* DIAG_STAT */ + +/* Alarm 2 status: 1 = alarm active, 0 = alarm inactive */ +#define ADIS16203_DIAG_STAT_ALARM2 BIT(9) + +/* Alarm 1 status: 1 = alarm active, 0 = alarm inactive */ +#define ADIS16203_DIAG_STAT_ALARM1 BIT(8) + +/* Self-test diagnostic error flag */ +#define ADIS16203_DIAG_STAT_SELFTEST_FAIL_BIT 5 + +/* SPI communications failure */ +#define ADIS16203_DIAG_STAT_SPI_FAIL_BIT 3 + +/* Flash update failure */ +#define ADIS16203_DIAG_STAT_FLASH_UPT_BIT 2 + +/* Power supply above 3.625 V */ +#define ADIS16203_DIAG_STAT_POWER_HIGH_BIT 1 + +/* Power supply below 3.15 V */ +#define ADIS16203_DIAG_STAT_POWER_LOW_BIT 0 + +/* GLOB_CMD */ + +#define ADIS16203_GLOB_CMD_SW_RESET BIT(7) +#define ADIS16203_GLOB_CMD_CLEAR_STAT BIT(4) +#define ADIS16203_GLOB_CMD_FACTORY_CAL BIT(1) + +#define ADIS16203_ERROR_ACTIVE BIT(14) + +enum adis16203_scan { + ADIS16203_SCAN_INCLI_X, + ADIS16203_SCAN_INCLI_Y, + ADIS16203_SCAN_SUPPLY, + ADIS16203_SCAN_AUX_ADC, + ADIS16203_SCAN_TEMP, +}; #define DRIVER_NAME "adis16203" diff --git a/drivers/staging/iio/accel/adis16203.h b/drivers/staging/iio/accel/adis16203.h deleted file mode 100644 index b483e4e..0000000 --- a/drivers/staging/iio/accel/adis16203.h +++ /dev/null @@ -1,125 +0,0 @@ -#ifndef SPI_ADIS16203_H_ -#define SPI_ADIS16203_H_ - -#define ADIS16203_STARTUP_DELAY 220 /* ms */ - -/* Flash memory write count */ -#define ADIS16203_FLASH_CNT 0x00 - -/* Output, power supply */ -#define ADIS16203_SUPPLY_OUT 0x02 - -/* Output, auxiliary ADC input */ -#define ADIS16203_AUX_ADC 0x08 - -/* Output, temperature */ -#define ADIS16203_TEMP_OUT 0x0A - -/* Output, x-axis inclination */ -#define ADIS16203_XINCL_OUT 0x0C - -/* Output, y-axis inclination */ -#define ADIS16203_YINCL_OUT 0x0E - -/* Incline null calibration */ -#define ADIS16203_INCL_NULL 0x18 - -/* Alarm 1 amplitude threshold */ -#define ADIS16203_ALM_MAG1 0x20 - -/* Alarm 2 amplitude threshold */ -#define ADIS16203_ALM_MAG2 0x22 - -/* Alarm 1, sample period */ -#define ADIS16203_ALM_SMPL1 0x24 - -/* Alarm 2, sample period */ -#define ADIS16203_ALM_SMPL2 0x26 - -/* Alarm control */ -#define ADIS16203_ALM_CTRL 0x28 - -/* Auxiliary DAC data */ -#define ADIS16203_AUX_DAC 0x30 - -/* General-purpose digital input/output control */ -#define ADIS16203_GPIO_CTRL 0x32 - -/* Miscellaneous control */ -#define ADIS16203_MSC_CTRL 0x34 - -/* Internal sample period (rate) control */ -#define ADIS16203_SMPL_PRD 0x36 - -/* Operation, filter configuration */ -#define ADIS16203_AVG_CNT 0x38 - -/* Operation, sleep mode control */ -#define ADIS16203_SLP_CNT 0x3A - -/* Diagnostics, system status register */ -#define ADIS16203_DIAG_STAT 0x3C - -/* Operation, system command register */ -#define ADIS16203_GLOB_CMD 0x3E - -/* MSC_CTRL */ - -/* Self-test at power-on: 1 = disabled, 0 = enabled */ -#define ADIS16203_MSC_CTRL_PWRUP_SELF_TEST BIT(10) - -/* Reverses rotation of both inclination outputs */ -#define ADIS16203_MSC_CTRL_REVERSE_ROT_EN BIT(9) - -/* Self-test enable */ -#define ADIS16203_MSC_CTRL_SELF_TEST_EN BIT(8) - -/* Data-ready enable: 1 = enabled, 0 = disabled */ -#define ADIS16203_MSC_CTRL_DATA_RDY_EN BIT(2) - -/* Data-ready polarity: 1 = active high, 0 = active low */ -#define ADIS16203_MSC_CTRL_ACTIVE_HIGH BIT(1) - -/* Data-ready line selection: 1 = DIO1, 0 = DIO0 */ -#define ADIS16203_MSC_CTRL_DATA_RDY_DIO1 BIT(0) - -/* DIAG_STAT */ - -/* Alarm 2 status: 1 = alarm active, 0 = alarm inactive */ -#define ADIS16203_DIAG_STAT_ALARM2 BIT(9) - -/* Alarm 1 status: 1 = alarm active, 0 = alarm inactive */ -#define ADIS16203_DIAG_STAT_ALARM1 BIT(8) - -/* Self-test diagnostic error flag */ -#define ADIS16203_DIAG_STAT_SELFTEST_FAIL_BIT 5 - -/* SPI communications failure */ -#define ADIS16203_DIAG_STAT_SPI_FAIL_BIT 3 - -/* Flash update failure */ -#define ADIS16203_DIAG_STAT_FLASH_UPT_BIT 2 - -/* Power supply above 3.625 V */ -#define ADIS16203_DIAG_STAT_POWER_HIGH_BIT 1 - -/* Power supply below 3.15 V */ -#define ADIS16203_DIAG_STAT_POWER_LOW_BIT 0 - -/* GLOB_CMD */ - -#define ADIS16203_GLOB_CMD_SW_RESET BIT(7) -#define ADIS16203_GLOB_CMD_CLEAR_STAT BIT(4) -#define ADIS16203_GLOB_CMD_FACTORY_CAL BIT(1) - -#define ADIS16203_ERROR_ACTIVE BIT(14) - -enum adis16203_scan { - ADIS16203_SCAN_INCLI_X, - ADIS16203_SCAN_INCLI_Y, - ADIS16203_SCAN_SUPPLY, - ADIS16203_SCAN_AUX_ADC, - ADIS16203_SCAN_TEMP, -}; - -#endif /* SPI_ADIS16203_H_ */ diff --git a/drivers/staging/iio/accel/adis16209_core.c b/drivers/staging/iio/accel/adis16209.c index a599e19..8ff537f 100644 --- a/drivers/staging/iio/accel/adis16209_core.c +++ b/drivers/staging/iio/accel/adis16209.c @@ -21,7 +21,145 @@ #include <linux/iio/buffer.h> #include <linux/iio/imu/adis.h> -#include "adis16209.h" +#define ADIS16209_STARTUP_DELAY 220 /* ms */ + +/* Flash memory write count */ +#define ADIS16209_FLASH_CNT 0x00 + +/* Output, power supply */ +#define ADIS16209_SUPPLY_OUT 0x02 + +/* Output, x-axis accelerometer */ +#define ADIS16209_XACCL_OUT 0x04 + +/* Output, y-axis accelerometer */ +#define ADIS16209_YACCL_OUT 0x06 + +/* Output, auxiliary ADC input */ +#define ADIS16209_AUX_ADC 0x08 + +/* Output, temperature */ +#define ADIS16209_TEMP_OUT 0x0A + +/* Output, x-axis inclination */ +#define ADIS16209_XINCL_OUT 0x0C + +/* Output, y-axis inclination */ +#define ADIS16209_YINCL_OUT 0x0E + +/* Output, +/-180 vertical rotational position */ +#define ADIS16209_ROT_OUT 0x10 + +/* Calibration, x-axis acceleration offset null */ +#define ADIS16209_XACCL_NULL 0x12 + +/* Calibration, y-axis acceleration offset null */ +#define ADIS16209_YACCL_NULL 0x14 + +/* Calibration, x-axis inclination offset null */ +#define ADIS16209_XINCL_NULL 0x16 + +/* Calibration, y-axis inclination offset null */ +#define ADIS16209_YINCL_NULL 0x18 + +/* Calibration, vertical rotation offset null */ +#define ADIS16209_ROT_NULL 0x1A + +/* Alarm 1 amplitude threshold */ +#define ADIS16209_ALM_MAG1 0x20 + +/* Alarm 2 amplitude threshold */ +#define ADIS16209_ALM_MAG2 0x22 + +/* Alarm 1, sample period */ +#define ADIS16209_ALM_SMPL1 0x24 + +/* Alarm 2, sample period */ +#define ADIS16209_ALM_SMPL2 0x26 + +/* Alarm control */ +#define ADIS16209_ALM_CTRL 0x28 + +/* Auxiliary DAC data */ +#define ADIS16209_AUX_DAC 0x30 + +/* General-purpose digital input/output control */ +#define ADIS16209_GPIO_CTRL 0x32 + +/* Miscellaneous control */ +#define ADIS16209_MSC_CTRL 0x34 + +/* Internal sample period (rate) control */ +#define ADIS16209_SMPL_PRD 0x36 + +/* Operation, filter configuration */ +#define ADIS16209_AVG_CNT 0x38 + +/* Operation, sleep mode control */ +#define ADIS16209_SLP_CNT 0x3A + +/* Diagnostics, system status register */ +#define ADIS16209_DIAG_STAT 0x3C + +/* Operation, system command register */ +#define ADIS16209_GLOB_CMD 0x3E + +/* MSC_CTRL */ + +/* Self-test at power-on: 1 = disabled, 0 = enabled */ +#define ADIS16209_MSC_CTRL_PWRUP_SELF_TEST BIT(10) + +/* Self-test enable */ +#define ADIS16209_MSC_CTRL_SELF_TEST_EN BIT(8) + +/* Data-ready enable: 1 = enabled, 0 = disabled */ +#define ADIS16209_MSC_CTRL_DATA_RDY_EN BIT(2) + +/* Data-ready polarity: 1 = active high, 0 = active low */ +#define ADIS16209_MSC_CTRL_ACTIVE_HIGH BIT(1) + +/* Data-ready line selection: 1 = DIO2, 0 = DIO1 */ +#define ADIS16209_MSC_CTRL_DATA_RDY_DIO2 BIT(0) + +/* DIAG_STAT */ + +/* Alarm 2 status: 1 = alarm active, 0 = alarm inactive */ +#define ADIS16209_DIAG_STAT_ALARM2 BIT(9) + +/* Alarm 1 status: 1 = alarm active, 0 = alarm inactive */ +#define ADIS16209_DIAG_STAT_ALARM1 BIT(8) + +/* Self-test diagnostic error flag: 1 = error condition, 0 = normal operation */ +#define ADIS16209_DIAG_STAT_SELFTEST_FAIL_BIT 5 + +/* SPI communications failure */ +#define ADIS16209_DIAG_STAT_SPI_FAIL_BIT 3 + +/* Flash update failure */ +#define ADIS16209_DIAG_STAT_FLASH_UPT_BIT 2 + +/* Power supply above 3.625 V */ +#define ADIS16209_DIAG_STAT_POWER_HIGH_BIT 1 + +/* Power supply below 3.15 V */ +#define ADIS16209_DIAG_STAT_POWER_LOW_BIT 0 + +/* GLOB_CMD */ + +#define ADIS16209_GLOB_CMD_SW_RESET BIT(7) +#define ADIS16209_GLOB_CMD_CLEAR_STAT BIT(4) +#define ADIS16209_GLOB_CMD_FACTORY_CAL BIT(1) + +#define ADIS16209_ERROR_ACTIVE BIT(14) + +#define ADIS16209_SCAN_SUPPLY 0 +#define ADIS16209_SCAN_ACC_X 1 +#define ADIS16209_SCAN_ACC_Y 2 +#define ADIS16209_SCAN_AUX_ADC 3 +#define ADIS16209_SCAN_TEMP 4 +#define ADIS16209_SCAN_INCLI_X 5 +#define ADIS16209_SCAN_INCLI_Y 6 +#define ADIS16209_SCAN_ROT 7 static const u8 adis16209_addresses[8][1] = { [ADIS16209_SCAN_SUPPLY] = { }, diff --git a/drivers/staging/iio/accel/adis16209.h b/drivers/staging/iio/accel/adis16209.h deleted file mode 100644 index 315f1c0..0000000 --- a/drivers/staging/iio/accel/adis16209.h +++ /dev/null @@ -1,144 +0,0 @@ -#ifndef SPI_ADIS16209_H_ -#define SPI_ADIS16209_H_ - -#define ADIS16209_STARTUP_DELAY 220 /* ms */ - -/* Flash memory write count */ -#define ADIS16209_FLASH_CNT 0x00 - -/* Output, power supply */ -#define ADIS16209_SUPPLY_OUT 0x02 - -/* Output, x-axis accelerometer */ -#define ADIS16209_XACCL_OUT 0x04 - -/* Output, y-axis accelerometer */ -#define ADIS16209_YACCL_OUT 0x06 - -/* Output, auxiliary ADC input */ -#define ADIS16209_AUX_ADC 0x08 - -/* Output, temperature */ -#define ADIS16209_TEMP_OUT 0x0A - -/* Output, x-axis inclination */ -#define ADIS16209_XINCL_OUT 0x0C - -/* Output, y-axis inclination */ -#define ADIS16209_YINCL_OUT 0x0E - -/* Output, +/-180 vertical rotational position */ -#define ADIS16209_ROT_OUT 0x10 - -/* Calibration, x-axis acceleration offset null */ -#define ADIS16209_XACCL_NULL 0x12 - -/* Calibration, y-axis acceleration offset null */ -#define ADIS16209_YACCL_NULL 0x14 - -/* Calibration, x-axis inclination offset null */ -#define ADIS16209_XINCL_NULL 0x16 - -/* Calibration, y-axis inclination offset null */ -#define ADIS16209_YINCL_NULL 0x18 - -/* Calibration, vertical rotation offset null */ -#define ADIS16209_ROT_NULL 0x1A - -/* Alarm 1 amplitude threshold */ -#define ADIS16209_ALM_MAG1 0x20 - -/* Alarm 2 amplitude threshold */ -#define ADIS16209_ALM_MAG2 0x22 - -/* Alarm 1, sample period */ -#define ADIS16209_ALM_SMPL1 0x24 - -/* Alarm 2, sample period */ -#define ADIS16209_ALM_SMPL2 0x26 - -/* Alarm control */ -#define ADIS16209_ALM_CTRL 0x28 - -/* Auxiliary DAC data */ -#define ADIS16209_AUX_DAC 0x30 - -/* General-purpose digital input/output control */ -#define ADIS16209_GPIO_CTRL 0x32 - -/* Miscellaneous control */ -#define ADIS16209_MSC_CTRL 0x34 - -/* Internal sample period (rate) control */ -#define ADIS16209_SMPL_PRD 0x36 - -/* Operation, filter configuration */ -#define ADIS16209_AVG_CNT 0x38 - -/* Operation, sleep mode control */ -#define ADIS16209_SLP_CNT 0x3A - -/* Diagnostics, system status register */ -#define ADIS16209_DIAG_STAT 0x3C - -/* Operation, system command register */ -#define ADIS16209_GLOB_CMD 0x3E - -/* MSC_CTRL */ - -/* Self-test at power-on: 1 = disabled, 0 = enabled */ -#define ADIS16209_MSC_CTRL_PWRUP_SELF_TEST BIT(10) - -/* Self-test enable */ -#define ADIS16209_MSC_CTRL_SELF_TEST_EN BIT(8) - -/* Data-ready enable: 1 = enabled, 0 = disabled */ -#define ADIS16209_MSC_CTRL_DATA_RDY_EN BIT(2) - -/* Data-ready polarity: 1 = active high, 0 = active low */ -#define ADIS16209_MSC_CTRL_ACTIVE_HIGH BIT(1) - -/* Data-ready line selection: 1 = DIO2, 0 = DIO1 */ -#define ADIS16209_MSC_CTRL_DATA_RDY_DIO2 BIT(0) - -/* DIAG_STAT */ - -/* Alarm 2 status: 1 = alarm active, 0 = alarm inactive */ -#define ADIS16209_DIAG_STAT_ALARM2 BIT(9) - -/* Alarm 1 status: 1 = alarm active, 0 = alarm inactive */ -#define ADIS16209_DIAG_STAT_ALARM1 BIT(8) - -/* Self-test diagnostic error flag: 1 = error condition, 0 = normal operation */ -#define ADIS16209_DIAG_STAT_SELFTEST_FAIL_BIT 5 - -/* SPI communications failure */ -#define ADIS16209_DIAG_STAT_SPI_FAIL_BIT 3 - -/* Flash update failure */ -#define ADIS16209_DIAG_STAT_FLASH_UPT_BIT 2 - -/* Power supply above 3.625 V */ -#define ADIS16209_DIAG_STAT_POWER_HIGH_BIT 1 - -/* Power supply below 3.15 V */ -#define ADIS16209_DIAG_STAT_POWER_LOW_BIT 0 - -/* GLOB_CMD */ - -#define ADIS16209_GLOB_CMD_SW_RESET BIT(7) -#define ADIS16209_GLOB_CMD_CLEAR_STAT BIT(4) -#define ADIS16209_GLOB_CMD_FACTORY_CAL BIT(1) - -#define ADIS16209_ERROR_ACTIVE BIT(14) - -#define ADIS16209_SCAN_SUPPLY 0 -#define ADIS16209_SCAN_ACC_X 1 -#define ADIS16209_SCAN_ACC_Y 2 -#define ADIS16209_SCAN_AUX_ADC 3 -#define ADIS16209_SCAN_TEMP 4 -#define ADIS16209_SCAN_INCLI_X 5 -#define ADIS16209_SCAN_INCLI_Y 6 -#define ADIS16209_SCAN_ROT 7 - -#endif /* SPI_ADIS16209_H_ */ diff --git a/drivers/staging/iio/accel/adis16240_core.c b/drivers/staging/iio/accel/adis16240.c index d5b99e6..27d7f6a 100644 --- a/drivers/staging/iio/accel/adis16240_core.c +++ b/drivers/staging/iio/accel/adis16240.c @@ -24,7 +24,180 @@ #include <linux/iio/buffer.h> #include <linux/iio/imu/adis.h> -#include "adis16240.h" +#define ADIS16240_STARTUP_DELAY 220 /* ms */ + +/* Flash memory write count */ +#define ADIS16240_FLASH_CNT 0x00 + +/* Output, power supply */ +#define ADIS16240_SUPPLY_OUT 0x02 + +/* Output, x-axis accelerometer */ +#define ADIS16240_XACCL_OUT 0x04 + +/* Output, y-axis accelerometer */ +#define ADIS16240_YACCL_OUT 0x06 + +/* Output, z-axis accelerometer */ +#define ADIS16240_ZACCL_OUT 0x08 + +/* Output, auxiliary ADC input */ +#define ADIS16240_AUX_ADC 0x0A + +/* Output, temperature */ +#define ADIS16240_TEMP_OUT 0x0C + +/* Output, x-axis acceleration peak */ +#define ADIS16240_XPEAK_OUT 0x0E + +/* Output, y-axis acceleration peak */ +#define ADIS16240_YPEAK_OUT 0x10 + +/* Output, z-axis acceleration peak */ +#define ADIS16240_ZPEAK_OUT 0x12 + +/* Output, sum-of-squares acceleration peak */ +#define ADIS16240_XYZPEAK_OUT 0x14 + +/* Output, Capture Buffer 1, X and Y acceleration */ +#define ADIS16240_CAPT_BUF1 0x16 + +/* Output, Capture Buffer 2, Z acceleration */ +#define ADIS16240_CAPT_BUF2 0x18 + +/* Diagnostic, error flags */ +#define ADIS16240_DIAG_STAT 0x1A + +/* Diagnostic, event counter */ +#define ADIS16240_EVNT_CNTR 0x1C + +/* Diagnostic, check sum value from firmware test */ +#define ADIS16240_CHK_SUM 0x1E + +/* Calibration, x-axis acceleration offset adjustment */ +#define ADIS16240_XACCL_OFF 0x20 + +/* Calibration, y-axis acceleration offset adjustment */ +#define ADIS16240_YACCL_OFF 0x22 + +/* Calibration, z-axis acceleration offset adjustment */ +#define ADIS16240_ZACCL_OFF 0x24 + +/* Clock, hour and minute */ +#define ADIS16240_CLK_TIME 0x2E + +/* Clock, month and day */ +#define ADIS16240_CLK_DATE 0x30 + +/* Clock, year */ +#define ADIS16240_CLK_YEAR 0x32 + +/* Wake-up setting, hour and minute */ +#define ADIS16240_WAKE_TIME 0x34 + +/* Wake-up setting, month and day */ +#define ADIS16240_WAKE_DATE 0x36 + +/* Alarm 1 amplitude threshold */ +#define ADIS16240_ALM_MAG1 0x38 + +/* Alarm 2 amplitude threshold */ +#define ADIS16240_ALM_MAG2 0x3A + +/* Alarm control */ +#define ADIS16240_ALM_CTRL 0x3C + +/* Capture, external trigger control */ +#define ADIS16240_XTRIG_CTRL 0x3E + +/* Capture, address pointer */ +#define ADIS16240_CAPT_PNTR 0x40 + +/* Capture, configuration and control */ +#define ADIS16240_CAPT_CTRL 0x42 + +/* General-purpose digital input/output control */ +#define ADIS16240_GPIO_CTRL 0x44 + +/* Miscellaneous control */ +#define ADIS16240_MSC_CTRL 0x46 + +/* Internal sample period (rate) control */ +#define ADIS16240_SMPL_PRD 0x48 + +/* System command */ +#define ADIS16240_GLOB_CMD 0x4A + +/* MSC_CTRL */ + +/* Enables sum-of-squares output (XYZPEAK_OUT) */ +#define ADIS16240_MSC_CTRL_XYZPEAK_OUT_EN BIT(15) + +/* Enables peak tracking output (XPEAK_OUT, YPEAK_OUT, and ZPEAK_OUT) */ +#define ADIS16240_MSC_CTRL_X_Y_ZPEAK_OUT_EN BIT(14) + +/* Self-test enable: 1 = apply electrostatic force, 0 = disabled */ +#define ADIS16240_MSC_CTRL_SELF_TEST_EN BIT(8) + +/* Data-ready enable: 1 = enabled, 0 = disabled */ +#define ADIS16240_MSC_CTRL_DATA_RDY_EN BIT(2) + +/* Data-ready polarity: 1 = active high, 0 = active low */ +#define ADIS16240_MSC_CTRL_ACTIVE_HIGH BIT(1) + +/* Data-ready line selection: 1 = DIO2, 0 = DIO1 */ +#define ADIS16240_MSC_CTRL_DATA_RDY_DIO2 BIT(0) + +/* DIAG_STAT */ + +/* Alarm 2 status: 1 = alarm active, 0 = alarm inactive */ +#define ADIS16240_DIAG_STAT_ALARM2 BIT(9) + +/* Alarm 1 status: 1 = alarm active, 0 = alarm inactive */ +#define ADIS16240_DIAG_STAT_ALARM1 BIT(8) + +/* Capture buffer full: 1 = capture buffer is full */ +#define ADIS16240_DIAG_STAT_CPT_BUF_FUL BIT(7) + +/* Flash test, checksum flag: 1 = mismatch, 0 = match */ +#define ADIS16240_DIAG_STAT_CHKSUM BIT(6) + +/* Power-on, self-test flag: 1 = failure, 0 = pass */ +#define ADIS16240_DIAG_STAT_PWRON_FAIL_BIT 5 + +/* Power-on self-test: 1 = in-progress, 0 = complete */ +#define ADIS16240_DIAG_STAT_PWRON_BUSY BIT(4) + +/* SPI communications failure */ +#define ADIS16240_DIAG_STAT_SPI_FAIL_BIT 3 + +/* Flash update failure */ +#define ADIS16240_DIAG_STAT_FLASH_UPT_BIT 2 + +/* Power supply above 3.625 V */ +#define ADIS16240_DIAG_STAT_POWER_HIGH_BIT 1 + + /* Power supply below 3.15 V */ +#define ADIS16240_DIAG_STAT_POWER_LOW_BIT 0 + +/* GLOB_CMD */ + +#define ADIS16240_GLOB_CMD_RESUME BIT(8) +#define ADIS16240_GLOB_CMD_SW_RESET BIT(7) +#define ADIS16240_GLOB_CMD_STANDBY BIT(2) + +#define ADIS16240_ERROR_ACTIVE BIT(14) + +/* At the moment triggers are only used for ring buffer + * filling. This may change! + */ + +#define ADIS16240_SCAN_ACC_X 0 +#define ADIS16240_SCAN_ACC_Y 1 +#define ADIS16240_SCAN_ACC_Z 2 +#define ADIS16240_SCAN_SUPPLY 3 +#define ADIS16240_SCAN_AUX_ADC 4 +#define ADIS16240_SCAN_TEMP 5 static ssize_t adis16240_spi_read_signed(struct device *dev, struct device_attribute *attr, @@ -65,7 +238,7 @@ static ssize_t adis16240_read_12bit_signed(struct device *dev, return ret; } -static IIO_DEVICE_ATTR(in_accel_xyz_squared_peak_raw, S_IRUGO, +static IIO_DEVICE_ATTR(in_accel_xyz_squared_peak_raw, 0444, adis16240_read_12bit_signed, NULL, ADIS16240_XYZPEAK_OUT); diff --git a/drivers/staging/iio/accel/adis16240.h b/drivers/staging/iio/accel/adis16240.h deleted file mode 100644 index b2cb37b..0000000 --- a/drivers/staging/iio/accel/adis16240.h +++ /dev/null @@ -1,179 +0,0 @@ -#ifndef SPI_ADIS16240_H_ -#define SPI_ADIS16240_H_ - -#define ADIS16240_STARTUP_DELAY 220 /* ms */ - -/* Flash memory write count */ -#define ADIS16240_FLASH_CNT 0x00 - -/* Output, power supply */ -#define ADIS16240_SUPPLY_OUT 0x02 - -/* Output, x-axis accelerometer */ -#define ADIS16240_XACCL_OUT 0x04 - -/* Output, y-axis accelerometer */ -#define ADIS16240_YACCL_OUT 0x06 - -/* Output, z-axis accelerometer */ -#define ADIS16240_ZACCL_OUT 0x08 - -/* Output, auxiliary ADC input */ -#define ADIS16240_AUX_ADC 0x0A - -/* Output, temperature */ -#define ADIS16240_TEMP_OUT 0x0C - -/* Output, x-axis acceleration peak */ -#define ADIS16240_XPEAK_OUT 0x0E - -/* Output, y-axis acceleration peak */ -#define ADIS16240_YPEAK_OUT 0x10 - -/* Output, z-axis acceleration peak */ -#define ADIS16240_ZPEAK_OUT 0x12 - -/* Output, sum-of-squares acceleration peak */ -#define ADIS16240_XYZPEAK_OUT 0x14 - -/* Output, Capture Buffer 1, X and Y acceleration */ -#define ADIS16240_CAPT_BUF1 0x16 - -/* Output, Capture Buffer 2, Z acceleration */ -#define ADIS16240_CAPT_BUF2 0x18 - -/* Diagnostic, error flags */ -#define ADIS16240_DIAG_STAT 0x1A - -/* Diagnostic, event counter */ -#define ADIS16240_EVNT_CNTR 0x1C - -/* Diagnostic, check sum value from firmware test */ -#define ADIS16240_CHK_SUM 0x1E - -/* Calibration, x-axis acceleration offset adjustment */ -#define ADIS16240_XACCL_OFF 0x20 - -/* Calibration, y-axis acceleration offset adjustment */ -#define ADIS16240_YACCL_OFF 0x22 - -/* Calibration, z-axis acceleration offset adjustment */ -#define ADIS16240_ZACCL_OFF 0x24 - -/* Clock, hour and minute */ -#define ADIS16240_CLK_TIME 0x2E - -/* Clock, month and day */ -#define ADIS16240_CLK_DATE 0x30 - -/* Clock, year */ -#define ADIS16240_CLK_YEAR 0x32 - -/* Wake-up setting, hour and minute */ -#define ADIS16240_WAKE_TIME 0x34 - -/* Wake-up setting, month and day */ -#define ADIS16240_WAKE_DATE 0x36 - -/* Alarm 1 amplitude threshold */ -#define ADIS16240_ALM_MAG1 0x38 - -/* Alarm 2 amplitude threshold */ -#define ADIS16240_ALM_MAG2 0x3A - -/* Alarm control */ -#define ADIS16240_ALM_CTRL 0x3C - -/* Capture, external trigger control */ -#define ADIS16240_XTRIG_CTRL 0x3E - -/* Capture, address pointer */ -#define ADIS16240_CAPT_PNTR 0x40 - -/* Capture, configuration and control */ -#define ADIS16240_CAPT_CTRL 0x42 - -/* General-purpose digital input/output control */ -#define ADIS16240_GPIO_CTRL 0x44 - -/* Miscellaneous control */ -#define ADIS16240_MSC_CTRL 0x46 - -/* Internal sample period (rate) control */ -#define ADIS16240_SMPL_PRD 0x48 - -/* System command */ -#define ADIS16240_GLOB_CMD 0x4A - -/* MSC_CTRL */ - -/* Enables sum-of-squares output (XYZPEAK_OUT) */ -#define ADIS16240_MSC_CTRL_XYZPEAK_OUT_EN BIT(15) - -/* Enables peak tracking output (XPEAK_OUT, YPEAK_OUT, and ZPEAK_OUT) */ -#define ADIS16240_MSC_CTRL_X_Y_ZPEAK_OUT_EN BIT(14) - -/* Self-test enable: 1 = apply electrostatic force, 0 = disabled */ -#define ADIS16240_MSC_CTRL_SELF_TEST_EN BIT(8) - -/* Data-ready enable: 1 = enabled, 0 = disabled */ -#define ADIS16240_MSC_CTRL_DATA_RDY_EN BIT(2) - -/* Data-ready polarity: 1 = active high, 0 = active low */ -#define ADIS16240_MSC_CTRL_ACTIVE_HIGH BIT(1) - -/* Data-ready line selection: 1 = DIO2, 0 = DIO1 */ -#define ADIS16240_MSC_CTRL_DATA_RDY_DIO2 BIT(0) - -/* DIAG_STAT */ - -/* Alarm 2 status: 1 = alarm active, 0 = alarm inactive */ -#define ADIS16240_DIAG_STAT_ALARM2 BIT(9) - -/* Alarm 1 status: 1 = alarm active, 0 = alarm inactive */ -#define ADIS16240_DIAG_STAT_ALARM1 BIT(8) - -/* Capture buffer full: 1 = capture buffer is full */ -#define ADIS16240_DIAG_STAT_CPT_BUF_FUL BIT(7) - -/* Flash test, checksum flag: 1 = mismatch, 0 = match */ -#define ADIS16240_DIAG_STAT_CHKSUM BIT(6) - -/* Power-on, self-test flag: 1 = failure, 0 = pass */ -#define ADIS16240_DIAG_STAT_PWRON_FAIL_BIT 5 - -/* Power-on self-test: 1 = in-progress, 0 = complete */ -#define ADIS16240_DIAG_STAT_PWRON_BUSY BIT(4) - -/* SPI communications failure */ -#define ADIS16240_DIAG_STAT_SPI_FAIL_BIT 3 - -/* Flash update failure */ -#define ADIS16240_DIAG_STAT_FLASH_UPT_BIT 2 - -/* Power supply above 3.625 V */ -#define ADIS16240_DIAG_STAT_POWER_HIGH_BIT 1 - - /* Power supply below 3.15 V */ -#define ADIS16240_DIAG_STAT_POWER_LOW_BIT 0 - -/* GLOB_CMD */ - -#define ADIS16240_GLOB_CMD_RESUME BIT(8) -#define ADIS16240_GLOB_CMD_SW_RESET BIT(7) -#define ADIS16240_GLOB_CMD_STANDBY BIT(2) - -#define ADIS16240_ERROR_ACTIVE BIT(14) - -/* At the moment triggers are only used for ring buffer - * filling. This may change! - */ - -#define ADIS16240_SCAN_ACC_X 0 -#define ADIS16240_SCAN_ACC_Y 1 -#define ADIS16240_SCAN_ACC_Z 2 -#define ADIS16240_SCAN_SUPPLY 3 -#define ADIS16240_SCAN_AUX_ADC 4 -#define ADIS16240_SCAN_TEMP 5 - -#endif /* SPI_ADIS16240_H_ */ diff --git a/drivers/staging/iio/adc/Kconfig b/drivers/staging/iio/adc/Kconfig index deff899..e17efb0 100644 --- a/drivers/staging/iio/adc/Kconfig +++ b/drivers/staging/iio/adc/Kconfig @@ -80,26 +80,4 @@ config AD7280 To compile this driver as a module, choose M here: the module will be called ad7280a -config LPC32XX_ADC - tristate "NXP LPC32XX ADC" - depends on ARCH_LPC32XX || COMPILE_TEST - depends on HAS_IOMEM - help - Say yes here to build support for the integrated ADC inside the - LPC32XX SoC. Note that this feature uses the same hardware as the - touchscreen driver, so you should either select only one of the two - drivers (lpc32xx_adc or lpc32xx_ts) or, in the OpenFirmware case, - activate only one via device tree selection. Provides direct access - via sysfs. - -config SPEAR_ADC - tristate "ST SPEAr ADC" - depends on PLAT_SPEAR || COMPILE_TEST - depends on HAS_IOMEM - help - Say yes here to build support for the integrated ADC inside the - ST SPEAr SoC. Provides direct access via sysfs. - - To compile this driver as a module, choose M here: the - module will be called spear_adc. endmenu diff --git a/drivers/staging/iio/adc/Makefile b/drivers/staging/iio/adc/Makefile index ac09485..bf18bdd 100644 --- a/drivers/staging/iio/adc/Makefile +++ b/drivers/staging/iio/adc/Makefile @@ -10,5 +10,3 @@ obj-$(CONFIG_AD7780) += ad7780.o obj-$(CONFIG_AD7816) += ad7816.o obj-$(CONFIG_AD7192) += ad7192.o obj-$(CONFIG_AD7280) += ad7280a.o -obj-$(CONFIG_LPC32XX_ADC) += lpc32xx_adc.o -obj-$(CONFIG_SPEAR_ADC) += spear_adc.o diff --git a/drivers/staging/iio/adc/ad7192.c b/drivers/staging/iio/adc/ad7192.c index 1fb68c0..4fc8588 100644 --- a/drivers/staging/iio/adc/ad7192.c +++ b/drivers/staging/iio/adc/ad7192.c @@ -342,9 +342,9 @@ ad7192_show_scale_available(struct device *dev, static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available, in_voltage-voltage_scale_available, - S_IRUGO, ad7192_show_scale_available, NULL, 0); + 0444, ad7192_show_scale_available, NULL, 0); -static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, +static IIO_DEVICE_ATTR(in_voltage_scale_available, 0444, ad7192_show_scale_available, NULL, 0); static ssize_t ad7192_show_ac_excitation(struct device *dev, @@ -412,11 +412,11 @@ static ssize_t ad7192_set(struct device *dev, return ret ? ret : len; } -static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(bridge_switch_en, 0644, ad7192_show_bridge_switch, ad7192_set, AD7192_REG_GPOCON); -static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(ac_excitation_en, 0644, ad7192_show_ac_excitation, ad7192_set, AD7192_REG_MODE); diff --git a/drivers/staging/iio/adc/lpc32xx_adc.c b/drivers/staging/iio/adc/lpc32xx_adc.c deleted file mode 100644 index b51f237..0000000 --- a/drivers/staging/iio/adc/lpc32xx_adc.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * lpc32xx_adc.c - Support for ADC in LPC32XX - * - * 3-channel, 10-bit ADC - * - * Copyright (C) 2011, 2012 Roland Stigge <stigge@antcom.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/device.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/completion.h> -#include <linux/of.h> - -#include <linux/iio/iio.h> -#include <linux/iio/sysfs.h> - -/* - * LPC32XX registers definitions - */ -#define LPC32XX_ADC_SELECT(x) ((x) + 0x04) -#define LPC32XX_ADC_CTRL(x) ((x) + 0x08) -#define LPC32XX_ADC_VALUE(x) ((x) + 0x48) - -/* Bit definitions for LPC32XX_ADC_SELECT: */ -#define AD_REFm 0x00000200 /* constant, always write this value! */ -#define AD_REFp 0x00000080 /* constant, always write this value! */ -#define AD_IN 0x00000010 /* multiple of this is the */ - /* channel number: 0, 1, 2 */ -#define AD_INTERNAL 0x00000004 /* constant, always write this value! */ - -/* Bit definitions for LPC32XX_ADC_CTRL: */ -#define AD_STROBE 0x00000002 -#define AD_PDN_CTRL 0x00000004 - -/* Bit definitions for LPC32XX_ADC_VALUE: */ -#define ADC_VALUE_MASK 0x000003FF - -#define MOD_NAME "lpc32xx-adc" - -struct lpc32xx_adc_info { - void __iomem *adc_base; - struct clk *clk; - struct completion completion; - - u32 value; -}; - -static int lpc32xx_read_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int *val, - int *val2, - long mask) -{ - struct lpc32xx_adc_info *info = iio_priv(indio_dev); - - if (mask == IIO_CHAN_INFO_RAW) { - mutex_lock(&indio_dev->mlock); - clk_prepare_enable(info->clk); - /* Measurement setup */ - __raw_writel(AD_INTERNAL | (chan->address) | AD_REFp | AD_REFm, - LPC32XX_ADC_SELECT(info->adc_base)); - /* Trigger conversion */ - __raw_writel(AD_PDN_CTRL | AD_STROBE, - LPC32XX_ADC_CTRL(info->adc_base)); - wait_for_completion(&info->completion); /* set by ISR */ - clk_disable_unprepare(info->clk); - *val = info->value; - mutex_unlock(&indio_dev->mlock); - - return IIO_VAL_INT; - } - - return -EINVAL; -} - -static const struct iio_info lpc32xx_adc_iio_info = { - .read_raw = &lpc32xx_read_raw, - .driver_module = THIS_MODULE, -}; - -#define LPC32XX_ADC_CHANNEL(_index) { \ - .type = IIO_VOLTAGE, \ - .indexed = 1, \ - .channel = _index, \ - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ - .address = AD_IN * _index, \ - .scan_index = _index, \ -} - -static const struct iio_chan_spec lpc32xx_adc_iio_channels[] = { - LPC32XX_ADC_CHANNEL(0), - LPC32XX_ADC_CHANNEL(1), - LPC32XX_ADC_CHANNEL(2), -}; - -static irqreturn_t lpc32xx_adc_isr(int irq, void *dev_id) -{ - struct lpc32xx_adc_info *info = dev_id; - - /* Read value and clear irq */ - info->value = __raw_readl(LPC32XX_ADC_VALUE(info->adc_base)) & - ADC_VALUE_MASK; - complete(&info->completion); - - return IRQ_HANDLED; -} - -static int lpc32xx_adc_probe(struct platform_device *pdev) -{ - struct lpc32xx_adc_info *info = NULL; - struct resource *res; - int retval = -ENODEV; - struct iio_dev *iodev = NULL; - int irq; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "failed to get platform I/O memory\n"); - return -ENXIO; - } - - iodev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); - if (!iodev) - return -ENOMEM; - - info = iio_priv(iodev); - - info->adc_base = devm_ioremap(&pdev->dev, res->start, - resource_size(res)); - if (!info->adc_base) { - dev_err(&pdev->dev, "failed mapping memory\n"); - return -EBUSY; - } - - info->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(info->clk)) { - dev_err(&pdev->dev, "failed getting clock\n"); - return PTR_ERR(info->clk); - } - - irq = platform_get_irq(pdev, 0); - if (irq <= 0) { - dev_err(&pdev->dev, "failed getting interrupt resource\n"); - return -ENXIO; - } - - retval = devm_request_irq(&pdev->dev, irq, lpc32xx_adc_isr, 0, - MOD_NAME, info); - if (retval < 0) { - dev_err(&pdev->dev, "failed requesting interrupt\n"); - return retval; - } - - platform_set_drvdata(pdev, iodev); - - init_completion(&info->completion); - - iodev->name = MOD_NAME; - iodev->dev.parent = &pdev->dev; - iodev->info = &lpc32xx_adc_iio_info; - iodev->modes = INDIO_DIRECT_MODE; - iodev->channels = lpc32xx_adc_iio_channels; - iodev->num_channels = ARRAY_SIZE(lpc32xx_adc_iio_channels); - - retval = devm_iio_device_register(&pdev->dev, iodev); - if (retval) - return retval; - - dev_info(&pdev->dev, "LPC32XX ADC driver loaded, IRQ %d\n", irq); - - return 0; -} - -#ifdef CONFIG_OF -static const struct of_device_id lpc32xx_adc_match[] = { - { .compatible = "nxp,lpc3220-adc" }, - {}, -}; -MODULE_DEVICE_TABLE(of, lpc32xx_adc_match); -#endif - -static struct platform_driver lpc32xx_adc_driver = { - .probe = lpc32xx_adc_probe, - .driver = { - .name = MOD_NAME, - .of_match_table = of_match_ptr(lpc32xx_adc_match), - }, -}; - -module_platform_driver(lpc32xx_adc_driver); - -MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); -MODULE_DESCRIPTION("LPC32XX ADC driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/staging/iio/adc/spear_adc.c b/drivers/staging/iio/adc/spear_adc.c deleted file mode 100644 index 5dd61f6..0000000 --- a/drivers/staging/iio/adc/spear_adc.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * ST SPEAr ADC driver - * - * Copyright 2012 Stefan Roese <sr@denx.de> - * - * Licensed under the GPL-2. - */ - -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/device.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/completion.h> -#include <linux/of.h> -#include <linux/of_address.h> - -#include <linux/iio/iio.h> -#include <linux/iio/sysfs.h> - -/* SPEAR registers definitions */ -#define SPEAR600_ADC_SCAN_RATE_LO(x) ((x) & 0xFFFF) -#define SPEAR600_ADC_SCAN_RATE_HI(x) (((x) >> 0x10) & 0xFFFF) -#define SPEAR_ADC_CLK_LOW(x) (((x) & 0xf) << 0) -#define SPEAR_ADC_CLK_HIGH(x) (((x) & 0xf) << 4) - -/* Bit definitions for SPEAR_ADC_STATUS */ -#define SPEAR_ADC_STATUS_START_CONVERSION BIT(0) -#define SPEAR_ADC_STATUS_CHANNEL_NUM(x) ((x) << 1) -#define SPEAR_ADC_STATUS_ADC_ENABLE BIT(4) -#define SPEAR_ADC_STATUS_AVG_SAMPLE(x) ((x) << 5) -#define SPEAR_ADC_STATUS_VREF_INTERNAL BIT(9) - -#define SPEAR_ADC_DATA_MASK 0x03ff -#define SPEAR_ADC_DATA_BITS 10 - -#define SPEAR_ADC_MOD_NAME "spear-adc" - -#define SPEAR_ADC_CHANNEL_NUM 8 - -#define SPEAR_ADC_CLK_MIN 2500000 -#define SPEAR_ADC_CLK_MAX 20000000 - -struct adc_regs_spear3xx { - u32 status; - u32 average; - u32 scan_rate; - u32 clk; /* Not avail for 1340 & 1310 */ - u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM]; - u32 ch_data[SPEAR_ADC_CHANNEL_NUM]; -}; - -struct chan_data { - u32 lsb; - u32 msb; -}; - -struct adc_regs_spear6xx { - u32 status; - u32 pad[2]; - u32 clk; - u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM]; - struct chan_data ch_data[SPEAR_ADC_CHANNEL_NUM]; - u32 scan_rate_lo; - u32 scan_rate_hi; - struct chan_data average; -}; - -struct spear_adc_state { - struct device_node *np; - struct adc_regs_spear3xx __iomem *adc_base_spear3xx; - struct adc_regs_spear6xx __iomem *adc_base_spear6xx; - struct clk *clk; - struct completion completion; - u32 current_clk; - u32 sampling_freq; - u32 avg_samples; - u32 vref_external; - u32 value; -}; - -/* - * Functions to access some SPEAr ADC register. Abstracted into - * static inline functions, because of different register offsets - * on different SoC variants (SPEAr300 vs SPEAr600 etc). - */ -static void spear_adc_set_status(struct spear_adc_state *st, u32 val) -{ - __raw_writel(val, &st->adc_base_spear6xx->status); -} - -static void spear_adc_set_clk(struct spear_adc_state *st, u32 val) -{ - u32 clk_high, clk_low, count; - u32 apb_clk = clk_get_rate(st->clk); - - count = DIV_ROUND_UP(apb_clk, val); - clk_low = count / 2; - clk_high = count - clk_low; - st->current_clk = apb_clk / count; - - __raw_writel(SPEAR_ADC_CLK_LOW(clk_low) | SPEAR_ADC_CLK_HIGH(clk_high), - &st->adc_base_spear6xx->clk); -} - -static void spear_adc_set_ctrl(struct spear_adc_state *st, int n, - u32 val) -{ - __raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]); -} - -static u32 spear_adc_get_average(struct spear_adc_state *st) -{ - if (of_device_is_compatible(st->np, "st,spear600-adc")) { - return __raw_readl(&st->adc_base_spear6xx->average.msb) & - SPEAR_ADC_DATA_MASK; - } else { - return __raw_readl(&st->adc_base_spear3xx->average) & - SPEAR_ADC_DATA_MASK; - } -} - -static void spear_adc_set_scanrate(struct spear_adc_state *st, u32 rate) -{ - if (of_device_is_compatible(st->np, "st,spear600-adc")) { - __raw_writel(SPEAR600_ADC_SCAN_RATE_LO(rate), - &st->adc_base_spear6xx->scan_rate_lo); - __raw_writel(SPEAR600_ADC_SCAN_RATE_HI(rate), - &st->adc_base_spear6xx->scan_rate_hi); - } else { - __raw_writel(rate, &st->adc_base_spear3xx->scan_rate); - } -} - -static int spear_adc_read_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int *val, - int *val2, - long mask) -{ - struct spear_adc_state *st = iio_priv(indio_dev); - u32 status; - - switch (mask) { - case IIO_CHAN_INFO_RAW: - mutex_lock(&indio_dev->mlock); - - status = SPEAR_ADC_STATUS_CHANNEL_NUM(chan->channel) | - SPEAR_ADC_STATUS_AVG_SAMPLE(st->avg_samples) | - SPEAR_ADC_STATUS_START_CONVERSION | - SPEAR_ADC_STATUS_ADC_ENABLE; - if (st->vref_external == 0) - status |= SPEAR_ADC_STATUS_VREF_INTERNAL; - - spear_adc_set_status(st, status); - wait_for_completion(&st->completion); /* set by ISR */ - *val = st->value; - - mutex_unlock(&indio_dev->mlock); - - return IIO_VAL_INT; - - case IIO_CHAN_INFO_SCALE: - *val = st->vref_external; - *val2 = SPEAR_ADC_DATA_BITS; - return IIO_VAL_FRACTIONAL_LOG2; - case IIO_CHAN_INFO_SAMP_FREQ: - *val = st->current_clk; - return IIO_VAL_INT; - } - - return -EINVAL; -} - -static int spear_adc_write_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int val, - int val2, - long mask) -{ - struct spear_adc_state *st = iio_priv(indio_dev); - int ret = 0; - - if (mask != IIO_CHAN_INFO_SAMP_FREQ) - return -EINVAL; - - mutex_lock(&indio_dev->mlock); - - if ((val < SPEAR_ADC_CLK_MIN) || - (val > SPEAR_ADC_CLK_MAX) || - (val2 != 0)) { - ret = -EINVAL; - goto out; - } - - spear_adc_set_clk(st, val); - -out: - mutex_unlock(&indio_dev->mlock); - return ret; -} - -#define SPEAR_ADC_CHAN(idx) { \ - .type = IIO_VOLTAGE, \ - .indexed = 1, \ - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ - .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ - .channel = idx, \ -} - -static const struct iio_chan_spec spear_adc_iio_channels[] = { - SPEAR_ADC_CHAN(0), - SPEAR_ADC_CHAN(1), - SPEAR_ADC_CHAN(2), - SPEAR_ADC_CHAN(3), - SPEAR_ADC_CHAN(4), - SPEAR_ADC_CHAN(5), - SPEAR_ADC_CHAN(6), - SPEAR_ADC_CHAN(7), -}; - -static irqreturn_t spear_adc_isr(int irq, void *dev_id) -{ - struct spear_adc_state *st = dev_id; - - /* Read value to clear IRQ */ - st->value = spear_adc_get_average(st); - complete(&st->completion); - - return IRQ_HANDLED; -} - -static int spear_adc_configure(struct spear_adc_state *st) -{ - int i; - - /* Reset ADC core */ - spear_adc_set_status(st, 0); - __raw_writel(0, &st->adc_base_spear6xx->clk); - for (i = 0; i < 8; i++) - spear_adc_set_ctrl(st, i, 0); - spear_adc_set_scanrate(st, 0); - - spear_adc_set_clk(st, st->sampling_freq); - - return 0; -} - -static const struct iio_info spear_adc_info = { - .read_raw = &spear_adc_read_raw, - .write_raw = &spear_adc_write_raw, - .driver_module = THIS_MODULE, -}; - -static int spear_adc_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct device *dev = &pdev->dev; - struct spear_adc_state *st; - struct resource *res; - struct iio_dev *indio_dev = NULL; - int ret = -ENODEV; - int irq; - - indio_dev = devm_iio_device_alloc(dev, sizeof(struct spear_adc_state)); - if (!indio_dev) { - dev_err(dev, "failed allocating iio device\n"); - return -ENOMEM; - } - - st = iio_priv(indio_dev); - st->np = np; - - /* - * SPEAr600 has a different register layout than other SPEAr SoC's - * (e.g. SPEAr3xx). Let's provide two register base addresses - * to support multi-arch kernels. - */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - st->adc_base_spear6xx = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(st->adc_base_spear6xx)) - return PTR_ERR(st->adc_base_spear6xx); - - st->adc_base_spear3xx = - (struct adc_regs_spear3xx __iomem *)st->adc_base_spear6xx; - - st->clk = devm_clk_get(dev, NULL); - if (IS_ERR(st->clk)) { - dev_err(dev, "failed getting clock\n"); - return PTR_ERR(st->clk); - } - - ret = clk_prepare_enable(st->clk); - if (ret) { - dev_err(dev, "failed enabling clock\n"); - return ret; - } - - irq = platform_get_irq(pdev, 0); - if (irq <= 0) { - dev_err(dev, "failed getting interrupt resource\n"); - ret = -EINVAL; - goto errout2; - } - - ret = devm_request_irq(dev, irq, spear_adc_isr, 0, SPEAR_ADC_MOD_NAME, - st); - if (ret < 0) { - dev_err(dev, "failed requesting interrupt\n"); - goto errout2; - } - - if (of_property_read_u32(np, "sampling-frequency", - &st->sampling_freq)) { - dev_err(dev, "sampling-frequency missing in DT\n"); - ret = -EINVAL; - goto errout2; - } - - /* - * Optional avg_samples defaults to 0, resulting in single data - * conversion - */ - of_property_read_u32(np, "average-samples", &st->avg_samples); - - /* - * Optional vref_external defaults to 0, resulting in internal vref - * selection - */ - of_property_read_u32(np, "vref-external", &st->vref_external); - - spear_adc_configure(st); - - platform_set_drvdata(pdev, indio_dev); - - init_completion(&st->completion); - - indio_dev->name = SPEAR_ADC_MOD_NAME; - indio_dev->dev.parent = dev; - indio_dev->info = &spear_adc_info; - indio_dev->modes = INDIO_DIRECT_MODE; - indio_dev->channels = spear_adc_iio_channels; - indio_dev->num_channels = ARRAY_SIZE(spear_adc_iio_channels); - - ret = iio_device_register(indio_dev); - if (ret) - goto errout2; - - dev_info(dev, "SPEAR ADC driver loaded, IRQ %d\n", irq); - - return 0; - -errout2: - clk_disable_unprepare(st->clk); - return ret; -} - -static int spear_adc_remove(struct platform_device *pdev) -{ - struct iio_dev *indio_dev = platform_get_drvdata(pdev); - struct spear_adc_state *st = iio_priv(indio_dev); - - iio_device_unregister(indio_dev); - clk_disable_unprepare(st->clk); - - return 0; -} - -#ifdef CONFIG_OF -static const struct of_device_id spear_adc_dt_ids[] = { - { .compatible = "st,spear600-adc", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, spear_adc_dt_ids); -#endif - -static struct platform_driver spear_adc_driver = { - .probe = spear_adc_probe, - .remove = spear_adc_remove, - .driver = { - .name = SPEAR_ADC_MOD_NAME, - .of_match_table = of_match_ptr(spear_adc_dt_ids), - }, -}; - -module_platform_driver(spear_adc_driver); - -MODULE_AUTHOR("Stefan Roese <sr@denx.de>"); -MODULE_DESCRIPTION("SPEAr ADC driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/staging/iio/addac/adt7316.c b/drivers/staging/iio/addac/adt7316.c index 6054c72..aa251c2 100644 --- a/drivers/staging/iio/addac/adt7316.c +++ b/drivers/staging/iio/addac/adt7316.c @@ -267,7 +267,7 @@ static ssize_t adt7316_store_enabled(struct device *dev, return len; } -static IIO_DEVICE_ATTR(enabled, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(enabled, 0644, adt7316_show_enabled, adt7316_store_enabled, 0); @@ -311,7 +311,7 @@ static ssize_t adt7316_store_select_ex_temp(struct device *dev, return len; } -static IIO_DEVICE_ATTR(select_ex_temp, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(select_ex_temp, 0644, adt7316_show_select_ex_temp, adt7316_store_select_ex_temp, 0); @@ -352,7 +352,7 @@ static ssize_t adt7316_store_mode(struct device *dev, return len; } -static IIO_DEVICE_ATTR(mode, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(mode, 0644, adt7316_show_mode, adt7316_store_mode, 0); @@ -364,7 +364,7 @@ static ssize_t adt7316_show_all_modes(struct device *dev, return sprintf(buf, "single_channel\nround_robin\n"); } -static IIO_DEVICE_ATTR(all_modes, S_IRUGO, adt7316_show_all_modes, NULL, 0); +static IIO_DEVICE_ATTR(all_modes, 0444, adt7316_show_all_modes, NULL, 0); static ssize_t adt7316_show_ad_channel(struct device *dev, struct device_attribute *attr, @@ -446,7 +446,7 @@ static ssize_t adt7316_store_ad_channel(struct device *dev, return len; } -static IIO_DEVICE_ATTR(ad_channel, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(ad_channel, 0644, adt7316_show_ad_channel, adt7316_store_ad_channel, 0); @@ -469,7 +469,7 @@ static ssize_t adt7316_show_all_ad_channels(struct device *dev, "2 - External Temperature\n"); } -static IIO_DEVICE_ATTR(all_ad_channels, S_IRUGO, +static IIO_DEVICE_ATTR(all_ad_channels, 0444, adt7316_show_all_ad_channels, NULL, 0); static ssize_t adt7316_show_disable_averaging(struct device *dev, @@ -506,7 +506,7 @@ static ssize_t adt7316_store_disable_averaging(struct device *dev, return len; } -static IIO_DEVICE_ATTR(disable_averaging, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(disable_averaging, 0644, adt7316_show_disable_averaging, adt7316_store_disable_averaging, 0); @@ -545,7 +545,7 @@ static ssize_t adt7316_store_enable_smbus_timeout(struct device *dev, return len; } -static IIO_DEVICE_ATTR(enable_smbus_timeout, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(enable_smbus_timeout, 0644, adt7316_show_enable_smbus_timeout, adt7316_store_enable_smbus_timeout, 0); @@ -583,7 +583,7 @@ static ssize_t adt7316_store_powerdown(struct device *dev, return len; } -static IIO_DEVICE_ATTR(powerdown, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(powerdown, 0644, adt7316_show_powerdown, adt7316_store_powerdown, 0); @@ -621,7 +621,7 @@ static ssize_t adt7316_store_fast_ad_clock(struct device *dev, return len; } -static IIO_DEVICE_ATTR(fast_ad_clock, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(fast_ad_clock, 0644, adt7316_show_fast_ad_clock, adt7316_store_fast_ad_clock, 0); @@ -674,7 +674,7 @@ static ssize_t adt7316_store_da_high_resolution(struct device *dev, return len; } -static IIO_DEVICE_ATTR(da_high_resolution, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(da_high_resolution, 0644, adt7316_show_da_high_resolution, adt7316_store_da_high_resolution, 0); @@ -720,7 +720,7 @@ static ssize_t adt7316_store_AIN_internal_Vref(struct device *dev, return len; } -static IIO_DEVICE_ATTR(AIN_internal_Vref, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(AIN_internal_Vref, 0644, adt7316_show_AIN_internal_Vref, adt7316_store_AIN_internal_Vref, 0); @@ -760,7 +760,7 @@ static ssize_t adt7316_store_enable_prop_DACA(struct device *dev, return len; } -static IIO_DEVICE_ATTR(enable_proportion_DACA, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(enable_proportion_DACA, 0644, adt7316_show_enable_prop_DACA, adt7316_store_enable_prop_DACA, 0); @@ -799,7 +799,7 @@ static ssize_t adt7316_store_enable_prop_DACB(struct device *dev, return len; } -static IIO_DEVICE_ATTR(enable_proportion_DACB, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(enable_proportion_DACB, 0644, adt7316_show_enable_prop_DACB, adt7316_store_enable_prop_DACB, 0); @@ -842,7 +842,7 @@ static ssize_t adt7316_store_DAC_2Vref_ch_mask(struct device *dev, return len; } -static IIO_DEVICE_ATTR(DAC_2Vref_channels_mask, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(DAC_2Vref_channels_mask, 0644, adt7316_show_DAC_2Vref_ch_mask, adt7316_store_DAC_2Vref_ch_mask, 0); @@ -902,7 +902,7 @@ static ssize_t adt7316_store_DAC_update_mode(struct device *dev, return len; } -static IIO_DEVICE_ATTR(DAC_update_mode, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(DAC_update_mode, 0644, adt7316_show_DAC_update_mode, adt7316_store_DAC_update_mode, 0); @@ -922,7 +922,7 @@ static ssize_t adt7316_show_all_DAC_update_modes(struct device *dev, return sprintf(buf, "manual\n"); } -static IIO_DEVICE_ATTR(all_DAC_update_modes, S_IRUGO, +static IIO_DEVICE_ATTR(all_DAC_update_modes, 0444, adt7316_show_all_DAC_update_modes, NULL, 0); @@ -961,7 +961,7 @@ static ssize_t adt7316_store_update_DAC(struct device *dev, return len; } -static IIO_DEVICE_ATTR(update_DAC, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(update_DAC, 0644, NULL, adt7316_store_update_DAC, 0); @@ -1006,7 +1006,7 @@ static ssize_t adt7316_store_DA_AB_Vref_bypass(struct device *dev, return len; } -static IIO_DEVICE_ATTR(DA_AB_Vref_bypass, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(DA_AB_Vref_bypass, 0644, adt7316_show_DA_AB_Vref_bypass, adt7316_store_DA_AB_Vref_bypass, 0); @@ -1051,7 +1051,7 @@ static ssize_t adt7316_store_DA_CD_Vref_bypass(struct device *dev, return len; } -static IIO_DEVICE_ATTR(DA_CD_Vref_bypass, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(DA_CD_Vref_bypass, 0644, adt7316_show_DA_CD_Vref_bypass, adt7316_store_DA_CD_Vref_bypass, 0); @@ -1112,7 +1112,7 @@ static ssize_t adt7316_store_DAC_internal_Vref(struct device *dev, return len; } -static IIO_DEVICE_ATTR(DAC_internal_Vref, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(DAC_internal_Vref, 0644, adt7316_show_DAC_internal_Vref, adt7316_store_DAC_internal_Vref, 0); @@ -1201,7 +1201,7 @@ static ssize_t adt7316_show_VDD(struct device *dev, return adt7316_show_ad(chip, ADT7316_AD_SINGLE_CH_VDD, buf); } -static IIO_DEVICE_ATTR(VDD, S_IRUGO, adt7316_show_VDD, NULL, 0); +static IIO_DEVICE_ATTR(VDD, 0444, adt7316_show_VDD, NULL, 0); static ssize_t adt7316_show_in_temp(struct device *dev, struct device_attribute *attr, @@ -1213,7 +1213,7 @@ static ssize_t adt7316_show_in_temp(struct device *dev, return adt7316_show_ad(chip, ADT7316_AD_SINGLE_CH_IN, buf); } -static IIO_DEVICE_ATTR(in_temp, S_IRUGO, adt7316_show_in_temp, NULL, 0); +static IIO_DEVICE_ATTR(in_temp, 0444, adt7316_show_in_temp, NULL, 0); static ssize_t adt7316_show_ex_temp_AIN1(struct device *dev, struct device_attribute *attr, @@ -1225,9 +1225,9 @@ static ssize_t adt7316_show_ex_temp_AIN1(struct device *dev, return adt7316_show_ad(chip, ADT7316_AD_SINGLE_CH_EX, buf); } -static IIO_DEVICE_ATTR(ex_temp_AIN1, S_IRUGO, adt7316_show_ex_temp_AIN1, +static IIO_DEVICE_ATTR(ex_temp_AIN1, 0444, adt7316_show_ex_temp_AIN1, NULL, 0); -static IIO_DEVICE_ATTR(ex_temp, S_IRUGO, adt7316_show_ex_temp_AIN1, NULL, 0); +static IIO_DEVICE_ATTR(ex_temp, 0444, adt7316_show_ex_temp_AIN1, NULL, 0); static ssize_t adt7316_show_AIN2(struct device *dev, struct device_attribute *attr, @@ -1238,7 +1238,7 @@ static ssize_t adt7316_show_AIN2(struct device *dev, return adt7316_show_ad(chip, ADT7516_AD_SINGLE_CH_AIN2, buf); } -static IIO_DEVICE_ATTR(AIN2, S_IRUGO, adt7316_show_AIN2, NULL, 0); +static IIO_DEVICE_ATTR(AIN2, 0444, adt7316_show_AIN2, NULL, 0); static ssize_t adt7316_show_AIN3(struct device *dev, struct device_attribute *attr, @@ -1249,7 +1249,7 @@ static ssize_t adt7316_show_AIN3(struct device *dev, return adt7316_show_ad(chip, ADT7516_AD_SINGLE_CH_AIN3, buf); } -static IIO_DEVICE_ATTR(AIN3, S_IRUGO, adt7316_show_AIN3, NULL, 0); +static IIO_DEVICE_ATTR(AIN3, 0444, adt7316_show_AIN3, NULL, 0); static ssize_t adt7316_show_AIN4(struct device *dev, struct device_attribute *attr, @@ -1260,7 +1260,7 @@ static ssize_t adt7316_show_AIN4(struct device *dev, return adt7316_show_ad(chip, ADT7516_AD_SINGLE_CH_AIN4, buf); } -static IIO_DEVICE_ATTR(AIN4, S_IRUGO, adt7316_show_AIN4, NULL, 0); +static IIO_DEVICE_ATTR(AIN4, 0444, adt7316_show_AIN4, NULL, 0); static ssize_t adt7316_show_temp_offset(struct adt7316_chip_info *chip, int offset_addr, char *buf) @@ -1325,7 +1325,7 @@ static ssize_t adt7316_store_in_temp_offset(struct device *dev, len); } -static IIO_DEVICE_ATTR(in_temp_offset, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(in_temp_offset, 0644, adt7316_show_in_temp_offset, adt7316_store_in_temp_offset, 0); @@ -1351,7 +1351,7 @@ static ssize_t adt7316_store_ex_temp_offset(struct device *dev, len); } -static IIO_DEVICE_ATTR(ex_temp_offset, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(ex_temp_offset, 0644, adt7316_show_ex_temp_offset, adt7316_store_ex_temp_offset, 0); @@ -1378,7 +1378,7 @@ static ssize_t adt7316_store_in_analog_temp_offset(struct device *dev, ADT7316_IN_ANALOG_TEMP_OFFSET, buf, len); } -static IIO_DEVICE_ATTR(in_analog_temp_offset, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(in_analog_temp_offset, 0644, adt7316_show_in_analog_temp_offset, adt7316_store_in_analog_temp_offset, 0); @@ -1405,7 +1405,7 @@ static ssize_t adt7316_store_ex_analog_temp_offset(struct device *dev, ADT7316_EX_ANALOG_TEMP_OFFSET, buf, len); } -static IIO_DEVICE_ATTR(ex_analog_temp_offset, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(ex_analog_temp_offset, 0644, adt7316_show_ex_analog_temp_offset, adt7316_store_ex_analog_temp_offset, 0); @@ -1500,7 +1500,7 @@ static ssize_t adt7316_store_DAC_A(struct device *dev, return adt7316_store_DAC(chip, 0, buf, len); } -static IIO_DEVICE_ATTR(DAC_A, S_IRUGO | S_IWUSR, adt7316_show_DAC_A, +static IIO_DEVICE_ATTR(DAC_A, 0644, adt7316_show_DAC_A, adt7316_store_DAC_A, 0); static ssize_t adt7316_show_DAC_B(struct device *dev, @@ -1524,7 +1524,7 @@ static ssize_t adt7316_store_DAC_B(struct device *dev, return adt7316_store_DAC(chip, 1, buf, len); } -static IIO_DEVICE_ATTR(DAC_B, S_IRUGO | S_IWUSR, adt7316_show_DAC_B, +static IIO_DEVICE_ATTR(DAC_B, 0644, adt7316_show_DAC_B, adt7316_store_DAC_B, 0); static ssize_t adt7316_show_DAC_C(struct device *dev, @@ -1548,7 +1548,7 @@ static ssize_t adt7316_store_DAC_C(struct device *dev, return adt7316_store_DAC(chip, 2, buf, len); } -static IIO_DEVICE_ATTR(DAC_C, S_IRUGO | S_IWUSR, adt7316_show_DAC_C, +static IIO_DEVICE_ATTR(DAC_C, 0644, adt7316_show_DAC_C, adt7316_store_DAC_C, 0); static ssize_t adt7316_show_DAC_D(struct device *dev, @@ -1572,7 +1572,7 @@ static ssize_t adt7316_store_DAC_D(struct device *dev, return adt7316_store_DAC(chip, 3, buf, len); } -static IIO_DEVICE_ATTR(DAC_D, S_IRUGO | S_IWUSR, adt7316_show_DAC_D, +static IIO_DEVICE_ATTR(DAC_D, 0644, adt7316_show_DAC_D, adt7316_store_DAC_D, 0); static ssize_t adt7316_show_device_id(struct device *dev, @@ -1591,7 +1591,7 @@ static ssize_t adt7316_show_device_id(struct device *dev, return sprintf(buf, "%d\n", id); } -static IIO_DEVICE_ATTR(device_id, S_IRUGO, adt7316_show_device_id, NULL, 0); +static IIO_DEVICE_ATTR(device_id, 0444, adt7316_show_device_id, NULL, 0); static ssize_t adt7316_show_manufactorer_id(struct device *dev, struct device_attribute *attr, @@ -1609,7 +1609,7 @@ static ssize_t adt7316_show_manufactorer_id(struct device *dev, return sprintf(buf, "%d\n", id); } -static IIO_DEVICE_ATTR(manufactorer_id, S_IRUGO, +static IIO_DEVICE_ATTR(manufactorer_id, 0444, adt7316_show_manufactorer_id, NULL, 0); static ssize_t adt7316_show_device_rev(struct device *dev, @@ -1628,7 +1628,7 @@ static ssize_t adt7316_show_device_rev(struct device *dev, return sprintf(buf, "%d\n", rev); } -static IIO_DEVICE_ATTR(device_rev, S_IRUGO, adt7316_show_device_rev, NULL, 0); +static IIO_DEVICE_ATTR(device_rev, 0444, adt7316_show_device_rev, NULL, 0); static ssize_t adt7316_show_bus_type(struct device *dev, struct device_attribute *attr, @@ -1649,7 +1649,7 @@ static ssize_t adt7316_show_bus_type(struct device *dev, return sprintf(buf, "i2c\n"); } -static IIO_DEVICE_ATTR(bus_type, S_IRUGO, adt7316_show_bus_type, NULL, 0); +static IIO_DEVICE_ATTR(bus_type, 0444, adt7316_show_bus_type, NULL, 0); static struct attribute *adt7316_attributes[] = { &iio_dev_attr_all_modes.dev_attr.attr, @@ -1972,61 +1972,61 @@ static ssize_t adt7316_set_int_enabled(struct device *dev, } static IIO_DEVICE_ATTR(int_mask, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_int_mask, adt7316_set_int_mask, 0); static IIO_DEVICE_ATTR(in_temp_high_value, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_ad_bound, adt7316_set_ad_bound, ADT7316_IN_TEMP_HIGH); static IIO_DEVICE_ATTR(in_temp_low_value, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_ad_bound, adt7316_set_ad_bound, ADT7316_IN_TEMP_LOW); static IIO_DEVICE_ATTR(ex_temp_high_value, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_ad_bound, adt7316_set_ad_bound, ADT7316_EX_TEMP_HIGH); static IIO_DEVICE_ATTR(ex_temp_low_value, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_ad_bound, adt7316_set_ad_bound, ADT7316_EX_TEMP_LOW); /* NASTY duplication to be fixed */ static IIO_DEVICE_ATTR(ex_temp_ain1_high_value, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_ad_bound, adt7316_set_ad_bound, ADT7316_EX_TEMP_HIGH); static IIO_DEVICE_ATTR(ex_temp_ain1_low_value, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_ad_bound, adt7316_set_ad_bound, ADT7316_EX_TEMP_LOW); static IIO_DEVICE_ATTR(ain2_high_value, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_ad_bound, adt7316_set_ad_bound, ADT7516_AIN2_HIGH); static IIO_DEVICE_ATTR(ain2_low_value, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_ad_bound, adt7316_set_ad_bound, ADT7516_AIN2_LOW); static IIO_DEVICE_ATTR(ain3_high_value, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_ad_bound, adt7316_set_ad_bound, ADT7516_AIN3_HIGH); static IIO_DEVICE_ATTR(ain3_low_value, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_ad_bound, adt7316_set_ad_bound, ADT7516_AIN3_LOW); static IIO_DEVICE_ATTR(ain4_high_value, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_ad_bound, adt7316_set_ad_bound, ADT7516_AIN4_HIGH); static IIO_DEVICE_ATTR(ain4_low_value, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_ad_bound, adt7316_set_ad_bound, ADT7516_AIN4_LOW); static IIO_DEVICE_ATTR(int_enabled, - S_IRUGO | S_IWUSR, + 0644, adt7316_show_int_enabled, adt7316_set_int_enabled, 0); diff --git a/drivers/staging/iio/cdc/ad7152.c b/drivers/staging/iio/cdc/ad7152.c index b91b50f..e8609b8 100644 --- a/drivers/staging/iio/cdc/ad7152.c +++ b/drivers/staging/iio/cdc/ad7152.c @@ -41,10 +41,10 @@ #define AD7152_REG_CFG2 26 /* Status Register Bit Designations (AD7152_REG_STATUS) */ -#define AD7152_STATUS_RDY1 (1 << 0) -#define AD7152_STATUS_RDY2 (1 << 1) -#define AD7152_STATUS_C1C2 (1 << 2) -#define AD7152_STATUS_PWDN (1 << 7) +#define AD7152_STATUS_RDY1 BIT(0) +#define AD7152_STATUS_RDY2 BIT(1) +#define AD7152_STATUS_C1C2 BIT(2) +#define AD7152_STATUS_PWDN BIT(7) /* Setup Register Bit Designations (AD7152_REG_CHx_SETUP) */ #define AD7152_SETUP_CAPDIFF (1 << 5) diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/frequency/ad9832.c index a5b2f06..8d40c8e 100644 --- a/drivers/staging/iio/frequency/ad9832.c +++ b/drivers/staging/iio/frequency/ad9832.c @@ -22,6 +22,98 @@ #include "ad9832.h" +/* Registers */ + +#define AD9832_FREQ0LL 0x0 +#define AD9832_FREQ0HL 0x1 +#define AD9832_FREQ0LM 0x2 +#define AD9832_FREQ0HM 0x3 +#define AD9832_FREQ1LL 0x4 +#define AD9832_FREQ1HL 0x5 +#define AD9832_FREQ1LM 0x6 +#define AD9832_FREQ1HM 0x7 +#define AD9832_PHASE0L 0x8 +#define AD9832_PHASE0H 0x9 +#define AD9832_PHASE1L 0xA +#define AD9832_PHASE1H 0xB +#define AD9832_PHASE2L 0xC +#define AD9832_PHASE2H 0xD +#define AD9832_PHASE3L 0xE +#define AD9832_PHASE3H 0xF + +#define AD9832_PHASE_SYM 0x10 +#define AD9832_FREQ_SYM 0x11 +#define AD9832_PINCTRL_EN 0x12 +#define AD9832_OUTPUT_EN 0x13 + +/* Command Control Bits */ + +#define AD9832_CMD_PHA8BITSW 0x1 +#define AD9832_CMD_PHA16BITSW 0x0 +#define AD9832_CMD_FRE8BITSW 0x3 +#define AD9832_CMD_FRE16BITSW 0x2 +#define AD9832_CMD_FPSELECT 0x6 +#define AD9832_CMD_SYNCSELSRC 0x8 +#define AD9832_CMD_SLEEPRESCLR 0xC + +#define AD9832_FREQ BIT(11) +#define AD9832_PHASE(x) (((x) & 3) << 9) +#define AD9832_SYNC BIT(13) +#define AD9832_SELSRC BIT(12) +#define AD9832_SLEEP BIT(13) +#define AD9832_RESET BIT(12) +#define AD9832_CLR BIT(11) +#define CMD_SHIFT 12 +#define ADD_SHIFT 8 +#define AD9832_FREQ_BITS 32 +#define AD9832_PHASE_BITS 12 +#define RES_MASK(bits) ((1 << (bits)) - 1) + +/** + * struct ad9832_state - driver instance specific data + * @spi: spi_device + * @avdd: supply regulator for the analog section + * @dvdd: supply regulator for the digital section + * @mclk: external master clock + * @ctrl_fp: cached frequency/phase control word + * @ctrl_ss: cached sync/selsrc control word + * @ctrl_src: cached sleep/reset/clr word + * @xfer: default spi transfer + * @msg: default spi message + * @freq_xfer: tuning word spi transfer + * @freq_msg: tuning word spi message + * @phase_xfer: tuning word spi transfer + * @phase_msg: tuning word spi message + * @data: spi transmit buffer + * @phase_data: tuning word spi transmit buffer + * @freq_data: tuning word spi transmit buffer + */ + +struct ad9832_state { + struct spi_device *spi; + struct regulator *avdd; + struct regulator *dvdd; + unsigned long mclk; + unsigned short ctrl_fp; + unsigned short ctrl_ss; + unsigned short ctrl_src; + struct spi_transfer xfer; + struct spi_message msg; + struct spi_transfer freq_xfer[4]; + struct spi_message freq_msg; + struct spi_transfer phase_xfer[2]; + struct spi_message phase_msg; + /* + * DMA (thus cache coherency maintenance) requires the + * transfer buffers to live in their own cache lines. + */ + union { + __be16 freq_data[4]____cacheline_aligned; + __be16 phase_data[2]; + __be16 data; + }; +}; + static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout) { unsigned long long freqreg = (u64)fout * diff --git a/drivers/staging/iio/frequency/ad9832.h b/drivers/staging/iio/frequency/ad9832.h index 1b08b0448..39d326c 100644 --- a/drivers/staging/iio/frequency/ad9832.h +++ b/drivers/staging/iio/frequency/ad9832.h @@ -8,98 +8,6 @@ #ifndef IIO_DDS_AD9832_H_ #define IIO_DDS_AD9832_H_ -/* Registers */ - -#define AD9832_FREQ0LL 0x0 -#define AD9832_FREQ0HL 0x1 -#define AD9832_FREQ0LM 0x2 -#define AD9832_FREQ0HM 0x3 -#define AD9832_FREQ1LL 0x4 -#define AD9832_FREQ1HL 0x5 -#define AD9832_FREQ1LM 0x6 -#define AD9832_FREQ1HM 0x7 -#define AD9832_PHASE0L 0x8 -#define AD9832_PHASE0H 0x9 -#define AD9832_PHASE1L 0xA -#define AD9832_PHASE1H 0xB -#define AD9832_PHASE2L 0xC -#define AD9832_PHASE2H 0xD -#define AD9832_PHASE3L 0xE -#define AD9832_PHASE3H 0xF - -#define AD9832_PHASE_SYM 0x10 -#define AD9832_FREQ_SYM 0x11 -#define AD9832_PINCTRL_EN 0x12 -#define AD9832_OUTPUT_EN 0x13 - -/* Command Control Bits */ - -#define AD9832_CMD_PHA8BITSW 0x1 -#define AD9832_CMD_PHA16BITSW 0x0 -#define AD9832_CMD_FRE8BITSW 0x3 -#define AD9832_CMD_FRE16BITSW 0x2 -#define AD9832_CMD_FPSELECT 0x6 -#define AD9832_CMD_SYNCSELSRC 0x8 -#define AD9832_CMD_SLEEPRESCLR 0xC - -#define AD9832_FREQ BIT(11) -#define AD9832_PHASE(x) (((x) & 3) << 9) -#define AD9832_SYNC BIT(13) -#define AD9832_SELSRC BIT(12) -#define AD9832_SLEEP BIT(13) -#define AD9832_RESET BIT(12) -#define AD9832_CLR BIT(11) -#define CMD_SHIFT 12 -#define ADD_SHIFT 8 -#define AD9832_FREQ_BITS 32 -#define AD9832_PHASE_BITS 12 -#define RES_MASK(bits) ((1 << (bits)) - 1) - -/** - * struct ad9832_state - driver instance specific data - * @spi: spi_device - * @avdd: supply regulator for the analog section - * @dvdd: supply regulator for the digital section - * @mclk: external master clock - * @ctrl_fp: cached frequency/phase control word - * @ctrl_ss: cached sync/selsrc control word - * @ctrl_src: cached sleep/reset/clr word - * @xfer: default spi transfer - * @msg: default spi message - * @freq_xfer: tuning word spi transfer - * @freq_msg: tuning word spi message - * @phase_xfer: tuning word spi transfer - * @phase_msg: tuning word spi message - * @data: spi transmit buffer - * @phase_data: tuning word spi transmit buffer - * @freq_data: tuning word spi transmit buffer - */ - -struct ad9832_state { - struct spi_device *spi; - struct regulator *avdd; - struct regulator *dvdd; - unsigned long mclk; - unsigned short ctrl_fp; - unsigned short ctrl_ss; - unsigned short ctrl_src; - struct spi_transfer xfer; - struct spi_message msg; - struct spi_transfer freq_xfer[4]; - struct spi_message freq_msg; - struct spi_transfer phase_xfer[2]; - struct spi_message phase_msg; - /* - * DMA (thus cache coherency maintenance) requires the - * transfer buffers to live in their own cache lines. - */ - union { - __be16 freq_data[4]____cacheline_aligned; - __be16 phase_data[2]; - __be16 data; - }; -}; - /* * TODO: struct ad9832_platform_data needs to go into include/linux/iio */ diff --git a/drivers/staging/iio/frequency/ad9834.c b/drivers/staging/iio/frequency/ad9834.c index 19216af..f92ff7f 100644 --- a/drivers/staging/iio/frequency/ad9834.c +++ b/drivers/staging/iio/frequency/ad9834.c @@ -25,6 +25,78 @@ #include "ad9834.h" +/* Registers */ + +#define AD9834_REG_CMD 0 +#define AD9834_REG_FREQ0 BIT(14) +#define AD9834_REG_FREQ1 BIT(15) +#define AD9834_REG_PHASE0 (BIT(15) | BIT(14)) +#define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13)) + +/* Command Control Bits */ + +#define AD9834_B28 BIT(13) +#define AD9834_HLB BIT(12) +#define AD9834_FSEL BIT(11) +#define AD9834_PSEL BIT(10) +#define AD9834_PIN_SW BIT(9) +#define AD9834_RESET BIT(8) +#define AD9834_SLEEP1 BIT(7) +#define AD9834_SLEEP12 BIT(6) +#define AD9834_OPBITEN BIT(5) +#define AD9834_SIGN_PIB BIT(4) +#define AD9834_DIV2 BIT(3) +#define AD9834_MODE BIT(1) + +#define AD9834_FREQ_BITS 28 +#define AD9834_PHASE_BITS 12 + +#define RES_MASK(bits) (BIT(bits) - 1) + +/** + * struct ad9834_state - driver instance specific data + * @spi: spi_device + * @reg: supply regulator + * @mclk: external master clock + * @control: cached control word + * @xfer: default spi transfer + * @msg: default spi message + * @freq_xfer: tuning word spi transfer + * @freq_msg: tuning word spi message + * @data: spi transmit buffer + * @freq_data: tuning word spi transmit buffer + */ + +struct ad9834_state { + struct spi_device *spi; + struct regulator *reg; + unsigned int mclk; + unsigned short control; + unsigned short devid; + struct spi_transfer xfer; + struct spi_message msg; + struct spi_transfer freq_xfer[2]; + struct spi_message freq_msg; + + /* + * DMA (thus cache coherency maintenance) requires the + * transfer buffers to live in their own cache lines. + */ + __be16 data ____cacheline_aligned; + __be16 freq_data[2]; +}; + +/** + * ad9834_supported_device_ids: + */ + +enum ad9834_supported_device_ids { + ID_AD9833, + ID_AD9834, + ID_AD9837, + ID_AD9838, +}; + static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout) { unsigned long long freqreg = (u64)fout * (u64)BIT(AD9834_FREQ_BITS); diff --git a/drivers/staging/iio/frequency/ad9834.h b/drivers/staging/iio/frequency/ad9834.h index 40fdd5d..ae620f3 100644 --- a/drivers/staging/iio/frequency/ad9834.h +++ b/drivers/staging/iio/frequency/ad9834.h @@ -8,67 +8,6 @@ #ifndef IIO_DDS_AD9834_H_ #define IIO_DDS_AD9834_H_ -/* Registers */ - -#define AD9834_REG_CMD 0 -#define AD9834_REG_FREQ0 BIT(14) -#define AD9834_REG_FREQ1 BIT(15) -#define AD9834_REG_PHASE0 (BIT(15) | BIT(14)) -#define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13)) - -/* Command Control Bits */ - -#define AD9834_B28 BIT(13) -#define AD9834_HLB BIT(12) -#define AD9834_FSEL BIT(11) -#define AD9834_PSEL BIT(10) -#define AD9834_PIN_SW BIT(9) -#define AD9834_RESET BIT(8) -#define AD9834_SLEEP1 BIT(7) -#define AD9834_SLEEP12 BIT(6) -#define AD9834_OPBITEN BIT(5) -#define AD9834_SIGN_PIB BIT(4) -#define AD9834_DIV2 BIT(3) -#define AD9834_MODE BIT(1) - -#define AD9834_FREQ_BITS 28 -#define AD9834_PHASE_BITS 12 - -#define RES_MASK(bits) (BIT(bits) - 1) - -/** - * struct ad9834_state - driver instance specific data - * @spi: spi_device - * @reg: supply regulator - * @mclk: external master clock - * @control: cached control word - * @xfer: default spi transfer - * @msg: default spi message - * @freq_xfer: tuning word spi transfer - * @freq_msg: tuning word spi message - * @data: spi transmit buffer - * @freq_data: tuning word spi transmit buffer - */ - -struct ad9834_state { - struct spi_device *spi; - struct regulator *reg; - unsigned int mclk; - unsigned short control; - unsigned short devid; - struct spi_transfer xfer; - struct spi_message msg; - struct spi_transfer freq_xfer[2]; - struct spi_message freq_msg; - - /* - * DMA (thus cache coherency maintenance) requires the - * transfer buffers to live in their own cache lines. - */ - __be16 data ____cacheline_aligned; - __be16 freq_data[2]; -}; - /* * TODO: struct ad7887_platform_data needs to go into include/linux/iio */ @@ -97,15 +36,4 @@ struct ad9834_platform_data { bool en_signbit_msb_out; }; -/** - * ad9834_supported_device_ids: - */ - -enum ad9834_supported_device_ids { - ID_AD9833, - ID_AD9834, - ID_AD9837, - ID_AD9838, -}; - #endif /* IIO_DDS_AD9834_H_ */ diff --git a/drivers/staging/iio/impedance-analyzer/ad5933.c b/drivers/staging/iio/impedance-analyzer/ad5933.c index 5e96352..297665d 100644 --- a/drivers/staging/iio/impedance-analyzer/ad5933.c +++ b/drivers/staging/iio/impedance-analyzer/ad5933.c @@ -345,12 +345,12 @@ static ssize_t ad5933_store_frequency(struct device *dev, return ret ? ret : len; } -static IIO_DEVICE_ATTR(out_voltage0_freq_start, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(out_voltage0_freq_start, 0644, ad5933_show_frequency, ad5933_store_frequency, AD5933_REG_FREQ_START); -static IIO_DEVICE_ATTR(out_voltage0_freq_increment, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(out_voltage0_freq_increment, 0644, ad5933_show_frequency, ad5933_store_frequency, AD5933_REG_FREQ_INC); @@ -469,32 +469,32 @@ static ssize_t ad5933_store(struct device *dev, return ret ? ret : len; } -static IIO_DEVICE_ATTR(out_voltage0_scale, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(out_voltage0_scale, 0644, ad5933_show, ad5933_store, AD5933_OUT_RANGE); -static IIO_DEVICE_ATTR(out_voltage0_scale_available, S_IRUGO, +static IIO_DEVICE_ATTR(out_voltage0_scale_available, 0444, ad5933_show, NULL, AD5933_OUT_RANGE_AVAIL); -static IIO_DEVICE_ATTR(in_voltage0_scale, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(in_voltage0_scale, 0644, ad5933_show, ad5933_store, AD5933_IN_PGA_GAIN); -static IIO_DEVICE_ATTR(in_voltage0_scale_available, S_IRUGO, +static IIO_DEVICE_ATTR(in_voltage0_scale_available, 0444, ad5933_show, NULL, AD5933_IN_PGA_GAIN_AVAIL); -static IIO_DEVICE_ATTR(out_voltage0_freq_points, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(out_voltage0_freq_points, 0644, ad5933_show, ad5933_store, AD5933_FREQ_POINTS); -static IIO_DEVICE_ATTR(out_voltage0_settling_cycles, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(out_voltage0_settling_cycles, 0644, ad5933_show, ad5933_store, AD5933_OUT_SETTLING_CYCLES); diff --git a/drivers/staging/iio/light/isl29028.c b/drivers/staging/iio/light/isl29028.c index 6bb6d37..5375e7a 100644 --- a/drivers/staging/iio/light/isl29028.c +++ b/drivers/staging/iio/light/isl29028.c @@ -3,6 +3,7 @@ * ISL29028 is Concurrent Ambient Light and Proximity Sensor * * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017 Brian Masney <masneyb@onstation.org> * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -63,6 +64,9 @@ #define ISL29028_POWER_OFF_DELAY_MS 2000 +static const unsigned int isl29028_prox_sleep_time[] = {800, 400, 200, 100, 75, + 50, 12, 0}; + enum isl29028_als_ir_mode { ISL29028_MODE_NONE = 0, ISL29028_MODE_ALS, @@ -78,22 +82,29 @@ struct isl29028_chip { enum isl29028_als_ir_mode als_ir_mode; }; -static int isl29028_set_proxim_sampling(struct isl29028_chip *chip, - unsigned int sampling) +static int isl29028_find_prox_sleep_time_index(int sampling) { - struct device *dev = regmap_get_device(chip->regmap); - static unsigned int prox_period[] = {800, 400, 200, 100, 75, 50, 12, 0}; unsigned int period = DIV_ROUND_UP(1000, sampling); - int sel, ret; + int i; - for (sel = 0; sel < ARRAY_SIZE(prox_period); ++sel) { - if (period >= prox_period[sel]) + for (i = 0; i < ARRAY_SIZE(isl29028_prox_sleep_time); ++i) { + if (period >= isl29028_prox_sleep_time[i]) break; } + return i; +} + +static int isl29028_set_proxim_sampling(struct isl29028_chip *chip, + unsigned int sampling) +{ + struct device *dev = regmap_get_device(chip->regmap); + int sleep_index, ret; + + sleep_index = isl29028_find_prox_sleep_time_index(sampling); ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE, ISL29028_CONF_PROX_SLP_MASK, - sel << ISL29028_CONF_PROX_SLP_SH); + sleep_index << ISL29028_CONF_PROX_SLP_SH); if (ret < 0) { dev_err(dev, "%s(): Error %d setting the proximity sampling\n", @@ -108,7 +119,7 @@ static int isl29028_set_proxim_sampling(struct isl29028_chip *chip, static int isl29028_enable_proximity(struct isl29028_chip *chip) { - int ret; + int sleep_index, ret; ret = isl29028_set_proxim_sampling(chip, chip->prox_sampling); if (ret < 0) @@ -121,7 +132,8 @@ static int isl29028_enable_proximity(struct isl29028_chip *chip) return ret; /* Wait for conversion to be complete for first sample */ - mdelay(DIV_ROUND_UP(1000, chip->prox_sampling)); + sleep_index = isl29028_find_prox_sleep_time_index(chip->prox_sampling); + msleep(isl29028_prox_sleep_time[sleep_index]); return 0; } @@ -192,7 +204,7 @@ static int isl29028_set_als_ir_mode(struct isl29028_chip *chip, return ret; /* Need to wait for conversion time if ALS/IR mode enabled */ - mdelay(ISL29028_CONV_TIME_MS); + msleep(ISL29028_CONV_TIME_MS); chip->als_ir_mode = mode; @@ -645,7 +657,8 @@ static int __maybe_unused isl29028_resume(struct device *dev) } static const struct dev_pm_ops isl29028_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(isl29028_suspend, isl29028_resume) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) SET_RUNTIME_PM_OPS(isl29028_suspend, isl29028_resume, NULL) }; diff --git a/drivers/staging/iio/meter/ade7753.c b/drivers/staging/iio/meter/ade7753.c index 671dc99..dfd8b71 100644 --- a/drivers/staging/iio/meter/ade7753.c +++ b/drivers/staging/iio/meter/ade7753.c @@ -6,22 +6,88 @@ * Licensed under the GPL-2 or later. */ -#include <linux/interrupt.h> -#include <linux/irq.h> #include <linux/delay.h> -#include <linux/mutex.h> #include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/irq.h> #include <linux/kernel.h> -#include <linux/spi/spi.h> -#include <linux/slab.h> -#include <linux/sysfs.h> #include <linux/list.h> #include <linux/module.h> - +#include <linux/mutex.h> +#include <linux/slab.h> +#include <linux/sysfs.h> #include <linux/iio/iio.h> #include <linux/iio/sysfs.h> +#include <linux/spi/spi.h> #include "meter.h" -#include "ade7753.h" + +#define ADE7753_WAVEFORM 0x01 +#define ADE7753_AENERGY 0x02 +#define ADE7753_RAENERGY 0x03 +#define ADE7753_LAENERGY 0x04 +#define ADE7753_VAENERGY 0x05 +#define ADE7753_RVAENERGY 0x06 +#define ADE7753_LVAENERGY 0x07 +#define ADE7753_LVARENERGY 0x08 +#define ADE7753_MODE 0x09 +#define ADE7753_IRQEN 0x0A +#define ADE7753_STATUS 0x0B +#define ADE7753_RSTSTATUS 0x0C +#define ADE7753_CH1OS 0x0D +#define ADE7753_CH2OS 0x0E +#define ADE7753_GAIN 0x0F +#define ADE7753_PHCAL 0x10 +#define ADE7753_APOS 0x11 +#define ADE7753_WGAIN 0x12 +#define ADE7753_WDIV 0x13 +#define ADE7753_CFNUM 0x14 +#define ADE7753_CFDEN 0x15 +#define ADE7753_IRMS 0x16 +#define ADE7753_VRMS 0x17 +#define ADE7753_IRMSOS 0x18 +#define ADE7753_VRMSOS 0x19 +#define ADE7753_VAGAIN 0x1A +#define ADE7753_VADIV 0x1B +#define ADE7753_LINECYC 0x1C +#define ADE7753_ZXTOUT 0x1D +#define ADE7753_SAGCYC 0x1E +#define ADE7753_SAGLVL 0x1F +#define ADE7753_IPKLVL 0x20 +#define ADE7753_VPKLVL 0x21 +#define ADE7753_IPEAK 0x22 +#define ADE7753_RSTIPEAK 0x23 +#define ADE7753_VPEAK 0x24 +#define ADE7753_RSTVPEAK 0x25 +#define ADE7753_TEMP 0x26 +#define ADE7753_PERIOD 0x27 +#define ADE7753_TMODE 0x3D +#define ADE7753_CHKSUM 0x3E +#define ADE7753_DIEREV 0x3F + +#define ADE7753_READ_REG(a) a +#define ADE7753_WRITE_REG(a) ((a) | 0x80) + +#define ADE7753_MAX_TX 4 +#define ADE7753_MAX_RX 4 +#define ADE7753_STARTUP_DELAY 1000 + +#define ADE7753_SPI_SLOW (u32)(300 * 1000) +#define ADE7753_SPI_BURST (u32)(1000 * 1000) +#define ADE7753_SPI_FAST (u32)(2000 * 1000) + +/** + * struct ade7753_state - device instance specific data + * @us: actual spi_device + * @tx: transmit buffer + * @rx: receive buffer + * @buf_lock: mutex to protect tx and rx + **/ +struct ade7753_state { + struct spi_device *us; + struct mutex buf_lock; + u8 tx[ADE7753_MAX_TX] ____cacheline_aligned; + u8 rx[ADE7753_MAX_RX]; +}; static int ade7753_spi_write_reg_8(struct device *dev, u8 reg_address, diff --git a/drivers/staging/iio/meter/ade7753.h b/drivers/staging/iio/meter/ade7753.h deleted file mode 100644 index bfe7491..0000000 --- a/drivers/staging/iio/meter/ade7753.h +++ /dev/null @@ -1,72 +0,0 @@ -#ifndef _ADE7753_H -#define _ADE7753_H - -#define ADE7753_WAVEFORM 0x01 -#define ADE7753_AENERGY 0x02 -#define ADE7753_RAENERGY 0x03 -#define ADE7753_LAENERGY 0x04 -#define ADE7753_VAENERGY 0x05 -#define ADE7753_RVAENERGY 0x06 -#define ADE7753_LVAENERGY 0x07 -#define ADE7753_LVARENERGY 0x08 -#define ADE7753_MODE 0x09 -#define ADE7753_IRQEN 0x0A -#define ADE7753_STATUS 0x0B -#define ADE7753_RSTSTATUS 0x0C -#define ADE7753_CH1OS 0x0D -#define ADE7753_CH2OS 0x0E -#define ADE7753_GAIN 0x0F -#define ADE7753_PHCAL 0x10 -#define ADE7753_APOS 0x11 -#define ADE7753_WGAIN 0x12 -#define ADE7753_WDIV 0x13 -#define ADE7753_CFNUM 0x14 -#define ADE7753_CFDEN 0x15 -#define ADE7753_IRMS 0x16 -#define ADE7753_VRMS 0x17 -#define ADE7753_IRMSOS 0x18 -#define ADE7753_VRMSOS 0x19 -#define ADE7753_VAGAIN 0x1A -#define ADE7753_VADIV 0x1B -#define ADE7753_LINECYC 0x1C -#define ADE7753_ZXTOUT 0x1D -#define ADE7753_SAGCYC 0x1E -#define ADE7753_SAGLVL 0x1F -#define ADE7753_IPKLVL 0x20 -#define ADE7753_VPKLVL 0x21 -#define ADE7753_IPEAK 0x22 -#define ADE7753_RSTIPEAK 0x23 -#define ADE7753_VPEAK 0x24 -#define ADE7753_RSTVPEAK 0x25 -#define ADE7753_TEMP 0x26 -#define ADE7753_PERIOD 0x27 -#define ADE7753_TMODE 0x3D -#define ADE7753_CHKSUM 0x3E -#define ADE7753_DIEREV 0x3F - -#define ADE7753_READ_REG(a) a -#define ADE7753_WRITE_REG(a) ((a) | 0x80) - -#define ADE7753_MAX_TX 4 -#define ADE7753_MAX_RX 4 -#define ADE7753_STARTUP_DELAY 1000 - -#define ADE7753_SPI_SLOW (u32)(300 * 1000) -#define ADE7753_SPI_BURST (u32)(1000 * 1000) -#define ADE7753_SPI_FAST (u32)(2000 * 1000) - -/** - * struct ade7753_state - device instance specific data - * @us: actual spi_device - * @tx: transmit buffer - * @rx: receive buffer - * @buf_lock: mutex to protect tx and rx - **/ -struct ade7753_state { - struct spi_device *us; - struct mutex buf_lock; - u8 tx[ADE7753_MAX_TX] ____cacheline_aligned; - u8 rx[ADE7753_MAX_RX]; -}; - -#endif diff --git a/drivers/staging/iio/meter/ade7854.c b/drivers/staging/iio/meter/ade7854.c index e8007f0..c6cffc1 100644 --- a/drivers/staging/iio/meter/ade7854.c +++ b/drivers/staging/iio/meter/ade7854.c @@ -426,9 +426,7 @@ static int ade7854_set_irq(struct device *dev, bool enable) else irqen &= ~BIT(17); - ret = st->write_reg_32(dev, ADE7854_MASK0, irqen); - - return ret; + return st->write_reg_32(dev, ADE7854_MASK0, irqen); } static int ade7854_initial_setup(struct iio_dev *indio_dev) diff --git a/drivers/staging/iio/meter/meter.h b/drivers/staging/iio/meter/meter.h index dfba510..0e37f23 100644 --- a/drivers/staging/iio/meter/meter.h +++ b/drivers/staging/iio/meter/meter.h @@ -81,94 +81,94 @@ IIO_DEVICE_ATTR(reactive_power_c_gain, _mode, _show, _store, _addr) #define IIO_DEV_ATTR_CURRENT_A(_show, _addr) \ - IIO_DEVICE_ATTR(current_a, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(current_a, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_CURRENT_B(_show, _addr) \ - IIO_DEVICE_ATTR(current_b, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(current_b, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_CURRENT_C(_show, _addr) \ - IIO_DEVICE_ATTR(current_c, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(current_c, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_VOLT_A(_show, _addr) \ - IIO_DEVICE_ATTR(volt_a, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(volt_a, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_VOLT_B(_show, _addr) \ - IIO_DEVICE_ATTR(volt_b, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(volt_b, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_VOLT_C(_show, _addr) \ - IIO_DEVICE_ATTR(volt_c, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(volt_c, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_AENERGY(_show, _addr) \ - IIO_DEVICE_ATTR(aenergy, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(aenergy, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_LENERGY(_show, _addr) \ - IIO_DEVICE_ATTR(lenergy, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(lenergy, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_RAENERGY(_show, _addr) \ - IIO_DEVICE_ATTR(raenergy, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(raenergy, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_LAENERGY(_show, _addr) \ - IIO_DEVICE_ATTR(laenergy, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(laenergy, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_VAENERGY(_show, _addr) \ - IIO_DEVICE_ATTR(vaenergy, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(vaenergy, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_LVAENERGY(_show, _addr) \ - IIO_DEVICE_ATTR(lvaenergy, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(lvaenergy, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_RVAENERGY(_show, _addr) \ - IIO_DEVICE_ATTR(rvaenergy, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(rvaenergy, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_LVARENERGY(_show, _addr) \ - IIO_DEVICE_ATTR(lvarenergy, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(lvarenergy, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_CHKSUM(_show, _addr) \ - IIO_DEVICE_ATTR(chksum, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(chksum, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_ANGLE0(_show, _addr) \ - IIO_DEVICE_ATTR(angle0, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(angle0, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_ANGLE1(_show, _addr) \ - IIO_DEVICE_ATTR(angle1, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(angle1, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_ANGLE2(_show, _addr) \ - IIO_DEVICE_ATTR(angle2, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(angle2, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_AWATTHR(_show, _addr) \ - IIO_DEVICE_ATTR(awatthr, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(awatthr, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_BWATTHR(_show, _addr) \ - IIO_DEVICE_ATTR(bwatthr, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(bwatthr, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_CWATTHR(_show, _addr) \ - IIO_DEVICE_ATTR(cwatthr, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(cwatthr, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_AFWATTHR(_show, _addr) \ - IIO_DEVICE_ATTR(afwatthr, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(afwatthr, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_BFWATTHR(_show, _addr) \ - IIO_DEVICE_ATTR(bfwatthr, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(bfwatthr, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_CFWATTHR(_show, _addr) \ - IIO_DEVICE_ATTR(cfwatthr, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(cfwatthr, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_AVARHR(_show, _addr) \ - IIO_DEVICE_ATTR(avarhr, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(avarhr, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_BVARHR(_show, _addr) \ - IIO_DEVICE_ATTR(bvarhr, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(bvarhr, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_CVARHR(_show, _addr) \ - IIO_DEVICE_ATTR(cvarhr, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(cvarhr, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_AVAHR(_show, _addr) \ - IIO_DEVICE_ATTR(avahr, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(avahr, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_BVAHR(_show, _addr) \ - IIO_DEVICE_ATTR(bvahr, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(bvahr, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_CVAHR(_show, _addr) \ - IIO_DEVICE_ATTR(cvahr, S_IRUGO, _show, NULL, _addr) + IIO_DEVICE_ATTR(cvahr, 0444, _show, NULL, _addr) #define IIO_DEV_ATTR_IOS(_mode, _show, _store, _addr) \ IIO_DEVICE_ATTR(ios, _mode, _show, _store, _addr) diff --git a/drivers/staging/iio/resolver/ad2s1210.c b/drivers/staging/iio/resolver/ad2s1210.c index 6b99263..90b57c0 100644 --- a/drivers/staging/iio/resolver/ad2s1210.c +++ b/drivers/staging/iio/resolver/ad2s1210.c @@ -531,36 +531,36 @@ error_ret: return ret; } -static IIO_DEVICE_ATTR(fclkin, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(fclkin, 0644, ad2s1210_show_fclkin, ad2s1210_store_fclkin, 0); -static IIO_DEVICE_ATTR(fexcit, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(fexcit, 0644, ad2s1210_show_fexcit, ad2s1210_store_fexcit, 0); -static IIO_DEVICE_ATTR(control, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(control, 0644, ad2s1210_show_control, ad2s1210_store_control, 0); -static IIO_DEVICE_ATTR(bits, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(bits, 0644, ad2s1210_show_resolution, ad2s1210_store_resolution, 0); -static IIO_DEVICE_ATTR(fault, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(fault, 0644, ad2s1210_show_fault, ad2s1210_clear_fault, 0); -static IIO_DEVICE_ATTR(los_thrd, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(los_thrd, 0644, ad2s1210_show_reg, ad2s1210_store_reg, AD2S1210_REG_LOS_THRD); -static IIO_DEVICE_ATTR(dos_ovr_thrd, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(dos_ovr_thrd, 0644, ad2s1210_show_reg, ad2s1210_store_reg, AD2S1210_REG_DOS_OVR_THRD); -static IIO_DEVICE_ATTR(dos_mis_thrd, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(dos_mis_thrd, 0644, ad2s1210_show_reg, ad2s1210_store_reg, AD2S1210_REG_DOS_MIS_THRD); -static IIO_DEVICE_ATTR(dos_rst_max_thrd, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(dos_rst_max_thrd, 0644, ad2s1210_show_reg, ad2s1210_store_reg, AD2S1210_REG_DOS_RST_MAX_THRD); -static IIO_DEVICE_ATTR(dos_rst_min_thrd, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(dos_rst_min_thrd, 0644, ad2s1210_show_reg, ad2s1210_store_reg, AD2S1210_REG_DOS_RST_MIN_THRD); -static IIO_DEVICE_ATTR(lot_high_thrd, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(lot_high_thrd, 0644, ad2s1210_show_reg, ad2s1210_store_reg, AD2S1210_REG_LOT_HIGH_THRD); -static IIO_DEVICE_ATTR(lot_low_thrd, S_IRUGO | S_IWUSR, +static IIO_DEVICE_ATTR(lot_low_thrd, 0644, ad2s1210_show_reg, ad2s1210_store_reg, AD2S1210_REG_LOT_LOW_THRD); |
