diff options
Diffstat (limited to 'drivers/staging/tidspbridge')
| -rw-r--r-- | drivers/staging/tidspbridge/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/staging/tidspbridge/core/io_sm.c | 2 | ||||
| -rw-r--r-- | drivers/staging/tidspbridge/core/tiomap3430.c | 23 | ||||
| -rw-r--r-- | drivers/staging/tidspbridge/core/tiomap3430_pwr.c | 15 | ||||
| -rw-r--r-- | drivers/staging/tidspbridge/dynload/tramp.c | 2 | ||||
| -rw-r--r-- | drivers/staging/tidspbridge/rmgr/dbdcd.c | 4 | ||||
| -rw-r--r-- | drivers/staging/tidspbridge/rmgr/drv.c | 2 | ||||
| -rw-r--r-- | drivers/staging/tidspbridge/rmgr/mgr.c | 8 | ||||
| -rw-r--r-- | drivers/staging/tidspbridge/rmgr/nldr.c | 5 | ||||
| -rw-r--r-- | drivers/staging/tidspbridge/rmgr/node.c | 20 |
10 files changed, 44 insertions, 39 deletions
diff --git a/drivers/staging/tidspbridge/Kconfig b/drivers/staging/tidspbridge/Kconfig index 1b6d581..b5e74e9 100644 --- a/drivers/staging/tidspbridge/Kconfig +++ b/drivers/staging/tidspbridge/Kconfig @@ -17,7 +17,7 @@ menuconfig TIDSPBRIDGE config TIDSPBRIDGE_DVFS bool "Enable Bridge Dynamic Voltage and Frequency Scaling (DVFS)" - depends on TIDSPBRIDGE && OMAP_PM_SRF && CPU_FREQ + depends on TIDSPBRIDGE && CPU_FREQ help DVFS allows DSP Bridge to initiate the operating point change to scale the chip voltage and frequency in order to match the diff --git a/drivers/staging/tidspbridge/core/io_sm.c b/drivers/staging/tidspbridge/core/io_sm.c index e322fb7..c2829aa 100644 --- a/drivers/staging/tidspbridge/core/io_sm.c +++ b/drivers/staging/tidspbridge/core/io_sm.c @@ -2127,7 +2127,7 @@ void dump_dl_modules(struct bridge_dev_context *bridge_context) u32 module_size; u32 module_struct_size = 0; u32 sect_ndx; - char *sect_str ; + char *sect_str; int status = 0; status = dev_get_intf_fxns(dev_object, &intf_fxns); diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index b770b22..8945b4e 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -280,9 +280,8 @@ static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt) OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); /* Wait until the state has moved to ON */ - while ((*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) & - OMAP_INTRANSITION_MASK) - ; + while (*pdata->dsp_prm_read(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST)& + OMAP_INTRANSITION_MASK); /* Disable Automatic transition */ (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); @@ -419,7 +418,8 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt, /* Assert RST1 i.e only the RST only for DSP megacell */ if (!status) { (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, - OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD, + OMAP3430_RST1_IVA2_MASK, + OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); /* Mask address with 1K for compatibility */ @@ -432,7 +432,8 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt, /* Reset and Unreset the RST2, so that BOOTADDR is copied to * IVA2 SYSC register */ (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, - OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); + OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD, + OMAP2_RM_RSTCTRL); udelay(100); (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); @@ -446,7 +447,8 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt, /* Only make TLB entry if both addresses are non-zero */ for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; entry_ndx++) { - struct bridge_ioctl_extproc *e = &dev_context->atlb_entry[entry_ndx]; + struct bridge_ioctl_extproc *e = + &dev_context->atlb_entry[entry_ndx]; struct hw_mmu_map_attrs_t map_attrs = { .endianism = e->endianism, .element_size = e->elem_size, @@ -641,8 +643,8 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt) /* as per TRM, it is advised to first drive the IVA2 to 'Standby' mode, * before turning off the clocks.. This is to ensure that there are no * pending L3 or other transactons from IVA2 */ - dsp_pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) & - OMAP_POWERSTATEST_MASK; + dsp_pwr_state = (*pdata->dsp_prm_read) + (OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) & OMAP_POWERSTATEST_MASK; if (dsp_pwr_state != PWRDM_POWER_OFF) { (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); @@ -682,8 +684,9 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt) dev_context->mbox = NULL; } /* Reset IVA2 clocks*/ - (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK | - OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); + (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | + OMAP3430_RST2_IVA2_MASK | OMAP3430_RST3_IVA2_MASK, + OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); dsp_clock_disable_all(dev_context->dsp_per_clks); dsp_clk_disable(DSP_CLK_IVA2); diff --git a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c index 1862afd..657104f 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c +++ b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c @@ -99,7 +99,8 @@ int handle_hibernation_from_dsp(struct bridge_dev_context *dev_context) return -EPERM; } pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, - OMAP2_PM_PWSTST) & OMAP_POWERSTATEST_MASK; + OMAP2_PM_PWSTST) & + OMAP_POWERSTATEST_MASK; } if (timeout == 0) { pr_err("%s: Timed out waiting for DSP off mode\n", __func__); @@ -209,7 +210,8 @@ int sleep_dsp(struct bridge_dev_context *dev_context, u32 dw_cmd, return -EPERM; } pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, - OMAP2_PM_PWSTST) & OMAP_POWERSTATEST_MASK; + OMAP2_PM_PWSTST) & + OMAP_POWERSTATEST_MASK; } if (!timeout) { @@ -355,7 +357,7 @@ int pre_scale_dsp(struct bridge_dev_context *dev_context, void *pargs) (dev_context->brd_state == BRD_DSP_HIBERNATION)) { dev_dbg(bridge, "OPP: %s IVA in sleep. No message to DSP\n"); return 0; - } else if ((dev_context->brd_state == BRD_RUNNING)) { + } else if (dev_context->brd_state == BRD_RUNNING) { /* Send a prenotification to DSP */ dev_dbg(bridge, "OPP: %s sent notification to DSP\n", __func__); sm_interrupt_dsp(dev_context, MBX_PM_SETPOINT_PRENOTIFY); @@ -396,13 +398,14 @@ int post_scale_dsp(struct bridge_dev_context *dev_context, io_sh_msetting(hio_mgr, SHM_CURROPP, &level); dev_dbg(bridge, "OPP: %s IVA in sleep. Wrote to shm\n", __func__); - } else if ((dev_context->brd_state == BRD_RUNNING)) { + } else if (dev_context->brd_state == BRD_RUNNING) { /* Update the OPP value in shared memory */ io_sh_msetting(hio_mgr, SHM_CURROPP, &level); /* Send a post notification to DSP */ sm_interrupt_dsp(dev_context, MBX_PM_SETPOINT_POSTNOTIFY); - dev_dbg(bridge, "OPP: %s wrote to shm. Sent post notification " - "to DSP\n", __func__); + dev_dbg(bridge, + "OPP: %s wrote to shm. Sent post notification to DSP\n", + __func__); } else { status = -EPERM; } diff --git a/drivers/staging/tidspbridge/dynload/tramp.c b/drivers/staging/tidspbridge/dynload/tramp.c index 404af18..5f04313 100644 --- a/drivers/staging/tidspbridge/dynload/tramp.c +++ b/drivers/staging/tidspbridge/dynload/tramp.c @@ -503,7 +503,7 @@ static int priv_tgt_img_gen(struct dload_state *dlthis, u32 base, * TRAMPOLINES ARE TREATED AS 2ND PASS even though this is really * the first (and only) relocation that will be performed on them. */ -static int priv_pkt_relo(struct dload_state *dlthis, tgt_au_t * data, +static int priv_pkt_relo(struct dload_state *dlthis, tgt_au_t *data, struct reloc_record_t *rp[], u32 relo_count) { int ret_val = 1; diff --git a/drivers/staging/tidspbridge/rmgr/dbdcd.c b/drivers/staging/tidspbridge/rmgr/dbdcd.c index 190ca3f..2ae48c9 100644 --- a/drivers/staging/tidspbridge/rmgr/dbdcd.c +++ b/drivers/staging/tidspbridge/rmgr/dbdcd.c @@ -101,14 +101,14 @@ static int dcd_uuid_from_string(char *sz_uuid, struct dsp_uuid *uuid_obj) * if the converted value doesn't fit in u32. So, convert the * last six bytes to u64 and memcpy what is needed */ - if(sscanf(sz_uuid, "%8x%c%4hx%c%4hx%c%2hhx%2hhx%c%llx", + if (sscanf(sz_uuid, "%8x%c%4hx%c%4hx%c%2hhx%2hhx%c%llx", &uuid_tmp.data1, &c, &uuid_tmp.data2, &c, &uuid_tmp.data3, &c, &uuid_tmp.data4, &uuid_tmp.data5, &c, &t) != 10) return -EINVAL; t = cpu_to_be64(t); - memcpy(&uuid_tmp.data6[0], ((char*)&t) + 2, 6); + memcpy(&uuid_tmp.data6[0], ((char *)&t) + 2, 6); *uuid_obj = uuid_tmp; return 0; diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c index be26917..757ae20 100644 --- a/drivers/staging/tidspbridge/rmgr/drv.c +++ b/drivers/staging/tidspbridge/rmgr/drv.c @@ -738,7 +738,7 @@ void mem_ext_phys_pool_release(void) * Allocate physically contiguous, uncached memory from external memory pool */ -static void *mem_ext_phys_mem_alloc(u32 bytes, u32 align, u32 * phys_addr) +static void *mem_ext_phys_mem_alloc(u32 bytes, u32 align, u32 *phys_addr) { u32 new_alloc_ptr; u32 offset; diff --git a/drivers/staging/tidspbridge/rmgr/mgr.c b/drivers/staging/tidspbridge/rmgr/mgr.c index b32ba0a..93e6282 100644 --- a/drivers/staging/tidspbridge/rmgr/mgr.c +++ b/drivers/staging/tidspbridge/rmgr/mgr.c @@ -266,15 +266,15 @@ int mgr_enum_processor_info(u32 processor_id, * this is a clumsy overwrite */ processor_info->processor_type = DSPTYPE64; } else { - dev_dbg(bridge, "%s: Failed to get DCD processor info " - "%x\n", __func__, status2); + dev_dbg(bridge, "%s: Failed to get DCD processor info %x\n", + __func__, status2); status = -EPERM; } } *pu_num_procs = proc_index; if (proc_detect == false) { - dev_dbg(bridge, "%s: Failed to get proc info from DCD, so use " - "CFG registry\n", __func__); + dev_dbg(bridge, "%s: Failed to get proc info from DCD, so use CFG registry\n", + __func__); processor_info->processor_type = DSPTYPE64; } func_end: diff --git a/drivers/staging/tidspbridge/rmgr/nldr.c b/drivers/staging/tidspbridge/rmgr/nldr.c index ca38050..5ac507c 100644 --- a/drivers/staging/tidspbridge/rmgr/nldr.c +++ b/drivers/staging/tidspbridge/rmgr/nldr.c @@ -623,7 +623,7 @@ void nldr_delete(struct nldr_object *nldr_obj) * ======== nldr_get_fxn_addr ======== */ int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj, - char *str_fxn, u32 * addr) + char *str_fxn, u32 *addr) { struct dbll_sym_val *dbll_sym; struct nldr_object *nldr_obj; @@ -1751,9 +1751,8 @@ static void unload_ovly(struct nldr_nodeobject *nldr_node_obj, } if (ref_count && (*ref_count > 0)) { *ref_count -= 1; - if (other_ref) { + if (other_ref) *other_ref -= 1; - } } if (ref_count && *ref_count == 0) { diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index 87dfa92..9d3044a 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -246,7 +246,7 @@ static void fill_stream_def(struct node_object *hnode, struct node_strmdef *pstrm_def, struct dsp_strmattr *pattrs); static void free_stream(struct node_mgr *hnode_mgr, struct stream_chnl stream); -static int get_fxn_address(struct node_object *hnode, u32 * fxn_addr, +static int get_fxn_address(struct node_object *hnode, u32 *fxn_addr, u32 phase); static int get_node_props(struct dcd_manager *hdcd_mgr, struct node_object *hnode, @@ -406,7 +406,7 @@ int node_allocate(struct proc_object *hprocessor, /* check for page aligned Heap size */ if (((attr_in->heap_size) & (PG_SIZE4K - 1))) { - pr_err("%s: node heap size not aligned to 4K, size = 0x%x \n", + pr_err("%s: node heap size not aligned to 4K, size = 0x%x\n", __func__, attr_in->heap_size); status = -EINVAL; } else { @@ -703,9 +703,9 @@ DBAPI node_alloc_msg_buf(struct node_object *hnode, u32 usize, pattr = &node_dfltbufattrs; /* set defaults */ status = proc_get_processor_id(pnode->processor, &proc_id); - if (proc_id != DSP_UNIT) { + if (proc_id != DSP_UNIT) goto func_end; - } + /* If segment ID includes MEM_SETVIRTUALSEGID then pbuffer is a * virt address, so set this info in this node's translator * object for future ref. If MEM_GETVIRTUALSEGID then retrieve @@ -886,11 +886,10 @@ int node_connect(struct node_object *node1, u32 stream1, if (pattrs && pattrs->strm_mode != STRMMODE_PROCCOPY) return -EPERM; /* illegal stream mode */ - if (node1_type != NODE_GPP) { + if (node1_type != NODE_GPP) hnode_mgr = node1->node_mgr; - } else { + else hnode_mgr = node2->node_mgr; - } /* Enter critical section */ mutex_lock(&hnode_mgr->node_mgr_lock); @@ -1576,7 +1575,7 @@ func_end: * Purpose: * Frees the message buffer. */ -int node_free_msg_buf(struct node_object *hnode, u8 * pbuffer, +int node_free_msg_buf(struct node_object *hnode, u8 *pbuffer, struct dsp_bufferattr *pattr) { struct node_object *pnode = (struct node_object *)hnode; @@ -2322,7 +2321,8 @@ int node_terminate(struct node_object *hnode, int *pstatus) if (!hdeh_mgr) goto func_cont; - bridge_deh_notify(hdeh_mgr, DSP_SYSERROR, DSP_EXCEPTIONABORT); + bridge_deh_notify(hdeh_mgr, DSP_SYSERROR, + DSP_EXCEPTIONABORT); } } func_cont: @@ -2640,7 +2640,7 @@ static void free_stream(struct node_mgr *hnode_mgr, struct stream_chnl stream) * Purpose: * Retrieves the address for create, execute or delete phase for a node. */ -static int get_fxn_address(struct node_object *hnode, u32 * fxn_addr, +static int get_fxn_address(struct node_object *hnode, u32 *fxn_addr, u32 phase) { char *pstr_fxn_name = NULL; |
