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path: root/drivers/staging/sm750fb/ddk750_mode.c
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Diffstat (limited to 'drivers/staging/sm750fb/ddk750_mode.c')
-rw-r--r--drivers/staging/sm750fb/ddk750_mode.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/staging/sm750fb/ddk750_mode.c b/drivers/staging/sm750fb/ddk750_mode.c
index 37b5d48..bb673e1 100644
--- a/drivers/staging/sm750fb/ddk750_mode.c
+++ b/drivers/staging/sm750fb/ddk750_mode.c
@@ -12,7 +12,8 @@
* HW only supports 7 predefined pixel clocks, and clock select is
* in bit 29:27 of Display Control register.
*/
-static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, unsigned long dispControl)
+static unsigned long displayControlAdjust_SM750LE(struct mode_parameter *pModeParam,
+ unsigned long dispControl)
{
unsigned long x, y;
@@ -72,7 +73,8 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam,
}
/* only timing related registers will be programed */
-static int programModeRegisters(mode_parameter_t *pModeParam, struct pll_value *pll)
+static int programModeRegisters(struct mode_parameter *pModeParam,
+ struct pll_value *pll)
{
int ret = 0;
int cnt = 0;
@@ -203,7 +205,7 @@ static int programModeRegisters(mode_parameter_t *pModeParam, struct pll_value *
return ret;
}
-int ddk750_setModeTiming(mode_parameter_t *parm, clock_type_t clock)
+int ddk750_setModeTiming(struct mode_parameter *parm, clock_type_t clock)
{
struct pll_value pll;
unsigned int uiActualPixelClk;
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