diff options
Diffstat (limited to 'drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a')
4 files changed, 783 insertions, 0 deletions
diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c new file mode 100644 index 0000000..8ef6c54 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c @@ -0,0 +1,386 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif +#include "sh_css_frac.h" +#include "assert_support.h" + +#include "bh/bh_2/ia_css_bh.host.h" +#include "ia_css_s3a.host.h" + +const struct ia_css_3a_config default_3a_config = { + 25559, + 32768, + 7209, + 65535, + 0, + 65535, + {-3344, -6104, -19143, 19143, 6104, 3344, 0}, + {1027, 0, -9219, 16384, -9219, 1027, 0} +}; + +static unsigned int s3a_raw_bit_depth; + +void +ia_css_s3a_configure(unsigned int raw_bit_depth) +{ + s3a_raw_bit_depth = raw_bit_depth; +} + +static void +ia_css_ae_encode( + struct sh_css_isp_ae_params *to, + const struct ia_css_3a_config *from, + unsigned size) +{ + (void)size; + /* coefficients to calculate Y */ + to->y_coef_r = + uDIGIT_FITTING(from->ae_y_coef_r, 16, SH_CSS_AE_YCOEF_SHIFT); + to->y_coef_g = + uDIGIT_FITTING(from->ae_y_coef_g, 16, SH_CSS_AE_YCOEF_SHIFT); + to->y_coef_b = + uDIGIT_FITTING(from->ae_y_coef_b, 16, SH_CSS_AE_YCOEF_SHIFT); +} + +static void +ia_css_awb_encode( + struct sh_css_isp_awb_params *to, + const struct ia_css_3a_config *from, + unsigned size) +{ + (void)size; + /* AWB level gate */ + to->lg_high_raw = + uDIGIT_FITTING(from->awb_lg_high_raw, 16, s3a_raw_bit_depth); + to->lg_low = + uDIGIT_FITTING(from->awb_lg_low, 16, SH_CSS_BAYER_BITS); + to->lg_high = + uDIGIT_FITTING(from->awb_lg_high, 16, SH_CSS_BAYER_BITS); +} + +static void +ia_css_af_encode( + struct sh_css_isp_af_params *to, + const struct ia_css_3a_config *from, + unsigned size) +{ + unsigned int i; + (void)size; + + /* af fir coefficients */ + for (i = 0; i < 7; ++i) { + to->fir1[i] = + sDIGIT_FITTING(from->af_fir1_coef[i], 15, + SH_CSS_AF_FIR_SHIFT); + to->fir2[i] = + sDIGIT_FITTING(from->af_fir2_coef[i], 15, + SH_CSS_AF_FIR_SHIFT); + } +} + +void +ia_css_s3a_encode( + struct sh_css_isp_s3a_params *to, + const struct ia_css_3a_config *from, + unsigned size) +{ + (void)size; + + ia_css_ae_encode(&to->ae, from, sizeof(to->ae)); + ia_css_awb_encode(&to->awb, from, sizeof(to->awb)); + ia_css_af_encode(&to->af, from, sizeof(to->af)); +} + +#if 0 +void +ia_css_process_s3a( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + short dmem_offset = stage->binary->info->mem_offsets->dmem.s3a; + + assert(params != NULL); + + if (dmem_offset >= 0) { + ia_css_s3a_encode((struct sh_css_isp_s3a_params *) + &stage->isp_mem_params[IA_CSS_ISP_DMEM0].address[dmem_offset], + ¶ms->s3a_config); + ia_css_bh_encode((struct sh_css_isp_bh_params *) + &stage->isp_mem_params[IA_CSS_ISP_DMEM0].address[dmem_offset], + ¶ms->s3a_config); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM0] = true; + } + + params->isp_params_changed = true; +} +#endif + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_ae_dump( + const struct sh_css_isp_ae_params *ae, + unsigned level) +{ + if (!ae) return; + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ae_y_coef_r", ae->y_coef_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ae_y_coef_g", ae->y_coef_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ae_y_coef_b", ae->y_coef_b); +} + +void +ia_css_awb_dump( + const struct sh_css_isp_awb_params *awb, + unsigned level) +{ + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "awb_lg_high_raw", awb->lg_high_raw); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "awb_lg_low", awb->lg_low); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "awb_lg_high", awb->lg_high); +} + +void +ia_css_af_dump( + const struct sh_css_isp_af_params *af, + unsigned level) +{ + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[0]", af->fir1[0]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[1]", af->fir1[1]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[2]", af->fir1[2]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[3]", af->fir1[3]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[4]", af->fir1[4]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[5]", af->fir1[5]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[6]", af->fir1[6]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[0]", af->fir2[0]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[1]", af->fir2[1]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[2]", af->fir2[2]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[3]", af->fir2[3]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[4]", af->fir2[4]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[5]", af->fir2[5]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[6]", af->fir2[6]); +} + +void +ia_css_s3a_dump( + const struct sh_css_isp_s3a_params *s3a, + unsigned level) +{ + ia_css_debug_dtrace(level, "S3A Support:\n"); + ia_css_ae_dump (&s3a->ae, level); + ia_css_awb_dump (&s3a->awb, level); + ia_css_af_dump (&s3a->af, level); +} + +void +ia_css_s3a_debug_dtrace( + const struct ia_css_3a_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.ae_y_coef_r=%d, config.ae_y_coef_g=%d, " + "config.ae_y_coef_b=%d, config.awb_lg_high_raw=%d, " + "config.awb_lg_low=%d, config.awb_lg_high=%d\n", + config->ae_y_coef_r, config->ae_y_coef_g, + config->ae_y_coef_b, config->awb_lg_high_raw, + config->awb_lg_low, config->awb_lg_high); +} +#endif + +void +ia_css_s3a_hmem_decode( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_bh_table *hmem_buf) +{ +#if defined(HAS_NO_HMEM) + (void)host_stats; + (void)hmem_buf; +#else + struct ia_css_3a_rgby_output *out_ptr; + int i; + + /* pixel counts(BQ) for 3A area */ + int count_for_3a; + int sum_r, diff; + + assert(host_stats != NULL); + assert(host_stats->rgby_data != NULL); + assert(hmem_buf != NULL); + + count_for_3a = host_stats->grid.width * host_stats->grid.height + * host_stats->grid.bqs_per_grid_cell + * host_stats->grid.bqs_per_grid_cell; + + out_ptr = host_stats->rgby_data; + + ia_css_bh_hmem_decode(out_ptr, hmem_buf); + + /* Calculate sum of histogram of R, + which should not be less than count_for_3a */ + sum_r = 0; + for (i = 0; i < HMEM_UNIT_SIZE; i++) { + sum_r += out_ptr[i].r; + } + if (sum_r < count_for_3a) { + /* histogram is invalid */ + return; + } + + /* Verify for sum of histogram of R/G/B/Y */ +#if 0 + { + int sum_g = 0; + int sum_b = 0; + int sum_y = 0; + for (i = 0; i < HMEM_UNIT_SIZE; i++) { + sum_g += out_ptr[i].g; + sum_b += out_ptr[i].b; + sum_y += out_ptr[i].y; + } + if (sum_g != sum_r || sum_b != sum_r || sum_y != sum_r) { + /* histogram is invalid */ + return; + } + } +#endif + + /* + * Limit the histogram area only to 3A area. + * In DSP, the histogram of 0 is incremented for pixels + * which are outside of 3A area. That amount should be subtracted here. + * hist[0] = hist[0] - ((sum of all hist[]) - (pixel count for 3A area)) + */ + diff = sum_r - count_for_3a; + out_ptr[0].r -= diff; + out_ptr[0].g -= diff; + out_ptr[0].b -= diff; + out_ptr[0].y -= diff; +#endif +} + +void +ia_css_s3a_dmem_decode( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_3a_output *isp_stats) +{ + int isp_width, host_width, height, i; + struct ia_css_3a_output *host_ptr; + + assert(host_stats != NULL); + assert(host_stats->data != NULL); + assert(isp_stats != NULL); + + isp_width = host_stats->grid.aligned_width; + host_width = host_stats->grid.width; + height = host_stats->grid.height; + host_ptr = host_stats->data; + + /* Getting 3A statistics from DMEM does not involve any + * transformation (like the VMEM version), we just copy the data + * using a different output width. */ + for (i = 0; i < height; i++) { + memcpy(host_ptr, isp_stats, host_width * sizeof(*host_ptr)); + isp_stats += isp_width; + host_ptr += host_width; + } +} + +/* MW: this is an ISP function */ +STORAGE_CLASS_INLINE int +merge_hi_lo_14(unsigned short hi, unsigned short lo) +{ + int val = (int) ((((unsigned int) hi << 14) & 0xfffc000) | + ((unsigned int) lo & 0x3fff)); + return val; +} + +void +ia_css_s3a_vmem_decode( + struct ia_css_3a_statistics *host_stats, + const uint16_t *isp_stats_hi, + const uint16_t *isp_stats_lo) +{ + int out_width, out_height, chunk, rest, kmax, y, x, k, elm_start, elm, ofs; + const uint16_t *hi, *lo; + struct ia_css_3a_output *output; + + assert(host_stats!= NULL); + assert(host_stats->data != NULL); + assert(isp_stats_hi != NULL); + assert(isp_stats_lo != NULL); + + output = host_stats->data; + out_width = host_stats->grid.width; + out_height = host_stats->grid.height; + hi = isp_stats_hi; + lo = isp_stats_lo; + + chunk = ISP_VEC_NELEMS >> host_stats->grid.deci_factor_log2; + chunk = max(chunk, 1); + + for (y = 0; y < out_height; y++) { + elm_start = y * ISP_S3ATBL_HI_LO_STRIDE; + rest = out_width; + x = 0; + while (x < out_width) { + kmax = (rest > chunk) ? chunk : rest; + ofs = y * out_width + x; + elm = elm_start + x * sizeof(*output) / sizeof(int32_t); + for (k = 0; k < kmax; k++, elm++) { + output[ofs + k].ae_y = merge_hi_lo_14( + hi[elm + chunk * 0], lo[elm + chunk * 0]); + output[ofs + k].awb_cnt = merge_hi_lo_14( + hi[elm + chunk * 1], lo[elm + chunk * 1]); + output[ofs + k].awb_gr = merge_hi_lo_14( + hi[elm + chunk * 2], lo[elm + chunk * 2]); + output[ofs + k].awb_r = merge_hi_lo_14( + hi[elm + chunk * 3], lo[elm + chunk * 3]); + output[ofs + k].awb_b = merge_hi_lo_14( + hi[elm + chunk * 4], lo[elm + chunk * 4]); + output[ofs + k].awb_gb = merge_hi_lo_14( + hi[elm + chunk * 5], lo[elm + chunk * 5]); + output[ofs + k].af_hpf1 = merge_hi_lo_14( + hi[elm + chunk * 6], lo[elm + chunk * 6]); + output[ofs + k].af_hpf2 = merge_hi_lo_14( + hi[elm + chunk * 7], lo[elm + chunk * 7]); + } + x += chunk; + rest -= chunk; + } + } +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h new file mode 100644 index 0000000..4bc6c0b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h @@ -0,0 +1,77 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_S3A_HOST_H +#define __IA_CSS_S3A_HOST_H + +#include "ia_css_s3a_types.h" +#include "ia_css_s3a_param.h" +#include "bh/bh_2/ia_css_bh.host.h" + +extern const struct ia_css_3a_config default_3a_config; + +void +ia_css_s3a_configure( + unsigned int raw_bit_depth); + +void +ia_css_s3a_encode( + struct sh_css_isp_s3a_params *to, + const struct ia_css_3a_config *from, + unsigned size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_ae_dump( + const struct sh_css_isp_ae_params *ae, + unsigned level); + +void +ia_css_awb_dump( + const struct sh_css_isp_awb_params *awb, + unsigned level); + +void +ia_css_af_dump( + const struct sh_css_isp_af_params *af, + unsigned level); + +void +ia_css_s3a_dump( + const struct sh_css_isp_s3a_params *s3a, + unsigned level); + +void +ia_css_s3a_debug_dtrace( + const struct ia_css_3a_config *config, + unsigned level); +#endif + +void +ia_css_s3a_hmem_decode( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_bh_table *hmem_buf); + +void +ia_css_s3a_dmem_decode( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_3a_output *isp_stats); + +void +ia_css_s3a_vmem_decode( + struct ia_css_3a_statistics *host_stats, + const uint16_t *isp_stats_hi, + const uint16_t *isp_stats_lo); + +#endif /* __IA_CSS_S3A_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_param.h new file mode 100644 index 0000000..35fb0a2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_param.h @@ -0,0 +1,54 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_S3A_PARAM_H +#define __IA_CSS_S3A_PARAM_H + +#include "type_support.h" + +/* AE (3A Support) */ +struct sh_css_isp_ae_params { + /* coefficients to calculate Y */ + int32_t y_coef_r; + int32_t y_coef_g; + int32_t y_coef_b; +}; + +/* AWB (3A Support) */ +struct sh_css_isp_awb_params { + int32_t lg_high_raw; + int32_t lg_low; + int32_t lg_high; +}; + +/* AF (3A Support) */ +struct sh_css_isp_af_params { + int32_t fir1[7]; + int32_t fir2[7]; +}; + +/* S3A (3A Support) */ +struct sh_css_isp_s3a_params { + /* coefficients to calculate Y */ + struct sh_css_isp_ae_params ae; + + /* AWB level gate */ + struct sh_css_isp_awb_params awb; + + /* af fir coefficients */ + struct sh_css_isp_af_params af; +}; + + +#endif /* __IA_CSS_S3A_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h new file mode 100644 index 0000000..f57ed1e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h @@ -0,0 +1,266 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_S3A_TYPES_H +#define __IA_CSS_S3A_TYPES_H + +/** @file +* CSS-API header file for 3A statistics parameters. +*/ + +#include <ia_css_frac.h> + +#if (defined(SYSTEM_css_skycam_c0_system)) && (! defined(PIPE_GENERATION) ) +#include "../../../../components/stats_3a/src/stats_3a_public.h" +#endif + +/** 3A configuration. This configures the 3A statistics collection + * module. + */ + +/** 3A statistics grid + * + * ISP block: S3A1 (3A Support for 3A ver.1 (Histogram is not used for AE)) + * S3A2 (3A Support for 3A ver.2 (Histogram is used for AE)) + * ISP1: S3A1 is used. + * ISP2: S3A2 is used. + */ +struct ia_css_3a_grid_info { + +#if defined(SYSTEM_css_skycam_c0_system) + uint32_t ae_enable; /**< ae enabled in binary, + 0:disabled, 1:enabled */ + struct ae_public_config_grid_config ae_grd_info; /**< see description in ae_public.h*/ + + uint32_t awb_enable; /**< awb enabled in binary, + 0:disabled, 1:enabled */ + struct awb_public_config_grid_config awb_grd_info; /**< see description in awb_public.h*/ + + uint32_t af_enable; /**< af enabled in binary, + 0:disabled, 1:enabled */ + struct af_public_grid_config af_grd_info; /**< see description in af_public.h*/ + + uint32_t awb_fr_enable; /**< awb_fr enabled in binary, + 0:disabled, 1:enabled */ + struct awb_fr_public_grid_config awb_fr_grd_info;/**< see description in awb_fr_public.h*/ + + uint32_t elem_bit_depth; /**< TODO:Taken from BYT - need input from AIQ + if needed for SKC + Bit depth of element used + to calculate 3A statistics. + This is 13, which is the normalized + bayer bit depth in DSP. */ + +#else + uint32_t enable; /**< 3A statistics enabled. + 0:disabled, 1:enabled */ + uint32_t use_dmem; /**< DMEM or VMEM determines layout. + 0:3A statistics are stored to VMEM, + 1:3A statistics are stored to DMEM */ + uint32_t has_histogram; /**< Statistics include histogram. + 0:no histogram, 1:has histogram */ + uint32_t width; /**< Width of 3A grid table. + (= Horizontal number of grid cells + in table, which cells have effective + statistics.) */ + uint32_t height; /**< Height of 3A grid table. + (= Vertical number of grid cells + in table, which cells have effective + statistics.) */ + uint32_t aligned_width; /**< Horizontal stride (for alloc). + (= Horizontal number of grid cells + in table, which means + the allocated width.) */ + uint32_t aligned_height; /**< Vertical stride (for alloc). + (= Vertical number of grid cells + in table, which means + the allocated height.) */ + uint32_t bqs_per_grid_cell; /**< Grid cell size in BQ(Bayer Quad) unit. + (1BQ means {Gr,R,B,Gb}(2x2 pixels).) + Valid values are 8,16,32,64. */ + uint32_t deci_factor_log2; /**< log2 of bqs_per_grid_cell. */ + uint32_t elem_bit_depth; /**< Bit depth of element used + to calculate 3A statistics. + This is 13, which is the normalized + bayer bit depth in DSP. */ +#endif +}; + + +#if defined(SYSTEM_css_skycam_c0_system) +#if defined USE_NEW_AE_STRUCT || defined USE_NEW_AWB_STRUCT +#define DEFAULT_3A_GRID_INFO \ +{ \ + 0, /* ae_enable */ \ + {0,0,0,0,0,0,0}, /* AE: width,height,b_width,b_height,x_start,y_start*/ \ + 0, /* awb_enable */ \ + {0,0,0,0,0,0}, /* AWB: width,height,b_width,b_height,x_start,y_start*/ \ + 0, /* af_enable */ \ + {0,0,0,0,0,0,0}, /* AF: width,height,b_width,b_height,x_start,y_start,ff_en*/ \ + 0, /* awb_fr_enable */ \ + {0,0,0,0,0,0,0}, /* AWB_FR: width,height,b_width,b_height,x_start,y_start,ff_en*/ \ + 0, /* elem_bit_depth */ \ +} +#else +#define DEFAULT_3A_GRID_INFO \ +{ \ + 0, /* ae_enable */ \ + {0,0,0,0,0,0,0,0,0}, /* AE: width,height,b_width,b_height,x_start,y_start,x_end,y_end*/ \ + 0, /* awb_enable */ \ + {0,0,0,0,0,0,0,0}, /* AWB: width,height,b_width,b_height,x_start,y_start,x_end,y_end*/ \ + 0, /* af_enable */ \ + {0,0,0,0,0,0,0}, /* AF: width,height,b_width,b_height,x_start,y_start,ff_en*/ \ + 0, /* awb_fr_enable */ \ + {0,0,0,0,0,0,0}, /* AWB_FR: width,height,b_width,b_height,x_start,y_start,ff_en*/ \ + 0, /* elem_bit_depth */ \ +} +#endif /* USE_NEW_AE_STRUCT || defined USE_NEW_AWB_STRUCT */ + +#else +#define DEFAULT_3A_GRID_INFO \ +{ \ + 0, /* enable */ \ + 0, /* use_dmem */ \ + 0, /* has_histogram */ \ + 0, /* width */ \ + 0, /* height */ \ + 0, /* aligned_width */ \ + 0, /* aligned_height */ \ + 0, /* bqs_per_grid_cell */ \ + 0, /* deci_factor_log2 */ \ + 0, /* elem_bit_depth */ \ +} + +#endif + +/* This struct should be split into 3, for AE, AWB and AF. + * However, that will require driver/ 3A lib modifications. + */ + +/** 3A configuration. This configures the 3A statistics collection + * module. + * + * ae_y_*: Coefficients to calculate luminance from bayer. + * awb_lg_*: Thresholds to check the saturated bayer pixels for AWB. + * Condition of effective pixel for AWB level gate check: + * bayer(sensor) <= awb_lg_high_raw && + * bayer(when AWB statisitcs is calculated) >= awb_lg_low && + * bayer(when AWB statisitcs is calculated) <= awb_lg_high + * af_fir*: Coefficients of high pass filter to calculate AF statistics. + * + * ISP block: S3A1(ae_y_* for AE/AF, awb_lg_* for AWB) + * S3A2(ae_y_* for AF, awb_lg_* for AWB) + * SDVS1(ae_y_*) + * SDVS2(ae_y_*) + * ISP1: S3A1 and SDVS1 are used. + * ISP2: S3A2 and SDVS2 are used. + */ +struct ia_css_3a_config { + ia_css_u0_16 ae_y_coef_r; /**< Weight of R for Y. + u0.16, [0,65535], + default/ineffective 25559 */ + ia_css_u0_16 ae_y_coef_g; /**< Weight of G for Y. + u0.16, [0,65535], + default/ineffective 32768 */ + ia_css_u0_16 ae_y_coef_b; /**< Weight of B for Y. + u0.16, [0,65535], + default/ineffective 7209 */ + ia_css_u0_16 awb_lg_high_raw; /**< AWB level gate high for raw. + u0.16, [0,65535], + default 65472(=1023*64), + ineffective 65535 */ + ia_css_u0_16 awb_lg_low; /**< AWB level gate low. + u0.16, [0,65535], + default 64(=1*64), + ineffective 0 */ + ia_css_u0_16 awb_lg_high; /**< AWB level gate high. + u0.16, [0,65535], + default 65535, + ineffective 65535 */ + ia_css_s0_15 af_fir1_coef[7]; /**< AF FIR coefficients of fir1. + s0.15, [-32768,32767], + default/ineffective + -6689,-12207,-32768,32767,12207,6689,0 */ + ia_css_s0_15 af_fir2_coef[7]; /**< AF FIR coefficients of fir2. + s0.15, [-32768,32767], + default/ineffective + 2053,0,-18437,32767,-18437,2053,0 */ +}; + +/** 3A statistics. This structure describes the data stored + * in each 3A grid point. + * + * ISP block: S3A1 (3A Support for 3A ver.1) (Histogram is not used for AE) + * S3A2 (3A Support for 3A ver.2) (Histogram is used for AE) + * - ae_y is used only for S3A1. + * - awb_* and af_* are used both for S3A1 and S3A2. + * ISP1: S3A1 is used. + * ISP2: S3A2 is used. + */ +struct ia_css_3a_output { + int32_t ae_y; /**< Sum of Y in a statistics window, for AE. + (u19.13) */ + int32_t awb_cnt; /**< Number of effective pixels + in a statistics window. + Pixels passed by the AWB level gate check are + judged as "effective". (u32) */ + int32_t awb_gr; /**< Sum of Gr in a statistics window, for AWB. + All Gr pixels (not only for effective pixels) + are summed. (u19.13) */ + int32_t awb_r; /**< Sum of R in a statistics window, for AWB. + All R pixels (not only for effective pixels) + are summed. (u19.13) */ + int32_t awb_b; /**< Sum of B in a statistics window, for AWB. + All B pixels (not only for effective pixels) + are summed. (u19.13) */ + int32_t awb_gb; /**< Sum of Gb in a statistics window, for AWB. + All Gb pixels (not only for effective pixels) + are summed. (u19.13) */ + int32_t af_hpf1; /**< Sum of |Y| following high pass filter af_fir1 + within a statistics window, for AF. (u19.13) */ + int32_t af_hpf2; /**< Sum of |Y| following high pass filter af_fir2 + within a statistics window, for AF. (u19.13) */ +}; + + +/** 3A Statistics. This structure describes the statistics that are generated + * using the provided configuration (ia_css_3a_config). + */ +struct ia_css_3a_statistics { + struct ia_css_3a_grid_info grid; /**< grid info contains the dimensions of the 3A grid */ + struct ia_css_3a_output *data; /**< the pointer to 3a_output[grid.width * grid.height] + containing the 3A statistics */ + struct ia_css_3a_rgby_output *rgby_data;/**< the pointer to 3a_rgby_output[256] + containing the histogram */ +}; + +/** Histogram (Statistics for AE). + * + * 4 histograms(r,g,b,y), + * 256 bins for each histogram, unsigned 24bit value for each bin. + * struct ia_css_3a_rgby_output data[256]; + + * ISP block: HIST2 + * (ISP1: HIST2 is not used.) + * ISP2: HIST2 is used. + */ +struct ia_css_3a_rgby_output { + uint32_t r; /**< Number of R of one bin of the histogram R. (u24) */ + uint32_t g; /**< Number of G of one bin of the histogram G. (u24) */ + uint32_t b; /**< Number of B of one bin of the histogram B. (u24) */ + uint32_t y; /**< Number of Y of one bin of the histogram Y. (u24) */ +}; + +#endif /* __IA_CSS_S3A_TYPES_H */ + |
