diff options
Diffstat (limited to 'drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system')
75 files changed, 15789 insertions, 0 deletions
diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/csi_rx_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/csi_rx_global.h new file mode 100644 index 0000000..146a578 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/csi_rx_global.h @@ -0,0 +1,63 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_GLOBAL_H_INCLUDED__ +#define __CSI_RX_GLOBAL_H_INCLUDED__ + +#include <type_support.h> + +typedef enum { + CSI_MIPI_PACKET_TYPE_UNDEFINED = 0, + CSI_MIPI_PACKET_TYPE_LONG, + CSI_MIPI_PACKET_TYPE_SHORT, + CSI_MIPI_PACKET_TYPE_RESERVED, + N_CSI_MIPI_PACKET_TYPE +} csi_mipi_packet_type_t; + +typedef struct csi_rx_backend_lut_entry_s csi_rx_backend_lut_entry_t; +struct csi_rx_backend_lut_entry_s { + uint32_t long_packet_entry; + uint32_t short_packet_entry; +}; + +typedef struct csi_rx_backend_cfg_s csi_rx_backend_cfg_t; +struct csi_rx_backend_cfg_s { + /* LUT entry for the packet */ + csi_rx_backend_lut_entry_t lut_entry; + + /* can be derived from the Data Type */ + csi_mipi_packet_type_t csi_mipi_packet_type; + + struct { + bool comp_enable; + uint32_t virtual_channel; + uint32_t data_type; + uint32_t comp_scheme; + uint32_t comp_predictor; + uint32_t comp_bit_idx; + } csi_mipi_cfg; +}; + +typedef struct csi_rx_frontend_cfg_s csi_rx_frontend_cfg_t; +struct csi_rx_frontend_cfg_s { + uint32_t active_lanes; +}; + +extern const uint32_t N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID]; +extern const uint32_t N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID]; +extern const uint32_t N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID]; +/* sid_width for CSI_RX_BACKEND<N>_ID */ +extern const uint32_t N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID]; + +#endif /* __CSI_RX_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.c new file mode 100644 index 0000000..325b821 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.c @@ -0,0 +1,360 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Generated code: do not edit or commmit. */ + +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_pipeline.h" +#include "ia_css_isp_configs.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_iterator( + const struct ia_css_binary *binary, + const struct ia_css_iterator_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.iterator.size; + offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset; + } + if (size) { + ia_css_iterator_config((struct sh_css_isp_iterator_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_copy_output( + const struct ia_css_binary *binary, + const struct ia_css_copy_output_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.copy_output.size; + offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset; + } + if (size) { + ia_css_copy_output_config((struct sh_css_isp_copy_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_crop( + const struct ia_css_binary *binary, + const struct ia_css_crop_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.crop.size; + offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset; + } + if (size) { + ia_css_crop_config((struct sh_css_isp_crop_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_fpn( + const struct ia_css_binary *binary, + const struct ia_css_fpn_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.fpn.size; + offset = binary->info->mem_offsets.offsets.config->dmem.fpn.offset; + } + if (size) { + ia_css_fpn_config((struct sh_css_isp_fpn_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_dvs( + const struct ia_css_binary *binary, + const struct ia_css_dvs_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.dvs.size; + offset = binary->info->mem_offsets.offsets.config->dmem.dvs.offset; + } + if (size) { + ia_css_dvs_config((struct sh_css_isp_dvs_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_qplane( + const struct ia_css_binary *binary, + const struct ia_css_qplane_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.qplane.size; + offset = binary->info->mem_offsets.offsets.config->dmem.qplane.offset; + } + if (size) { + ia_css_qplane_config((struct sh_css_isp_qplane_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output0( + const struct ia_css_binary *binary, + const struct ia_css_output0_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.output0.size; + offset = binary->info->mem_offsets.offsets.config->dmem.output0.offset; + } + if (size) { + ia_css_output0_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output1( + const struct ia_css_binary *binary, + const struct ia_css_output1_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.output1.size; + offset = binary->info->mem_offsets.offsets.config->dmem.output1.offset; + } + if (size) { + ia_css_output1_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output( + const struct ia_css_binary *binary, + const struct ia_css_output_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.output.size; + offset = binary->info->mem_offsets.offsets.config->dmem.output.offset; + } + if (size) { + ia_css_output_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ +#ifdef ISP2401 + +void +ia_css_configure_sc( + const struct ia_css_binary *binary, + const struct ia_css_sc_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.sc.size; + offset = binary->info->mem_offsets.offsets.config->dmem.sc.offset; + } + if (size) { + ia_css_sc_config((struct sh_css_isp_sc_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ +#endif + +void +ia_css_configure_raw( + const struct ia_css_binary *binary, + const struct ia_css_raw_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.raw.size; + offset = binary->info->mem_offsets.offsets.config->dmem.raw.offset; + } + if (size) { + ia_css_raw_config((struct sh_css_isp_raw_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_tnr( + const struct ia_css_binary *binary, + const struct ia_css_tnr_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.tnr.size; + offset = binary->info->mem_offsets.offsets.config->dmem.tnr.offset; + } + if (size) { + ia_css_tnr_config((struct sh_css_isp_tnr_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_ref( + const struct ia_css_binary *binary, + const struct ia_css_ref_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.ref.size; + offset = binary->info->mem_offsets.offsets.config->dmem.ref.offset; + } + if (size) { + ia_css_ref_config((struct sh_css_isp_ref_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_vf( + const struct ia_css_binary *binary, + const struct ia_css_vf_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.vf.size; + offset = binary->info->mem_offsets.offsets.config->dmem.vf.offset; + } + if (size) { + ia_css_vf_config((struct sh_css_isp_vf_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() leave:\n"); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.h new file mode 100644 index 0000000..8aacd3d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.h @@ -0,0 +1,189 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifdef IA_CSS_INCLUDE_CONFIGURATIONS +#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h" +#include "isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h" +#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h" +#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h" +#include "isp/kernels/output/output_1.0/ia_css_output.host.h" +#include "isp/kernels/qplane/qplane_2/ia_css_qplane.host.h" +#include "isp/kernels/raw/raw_1.0/ia_css_raw.host.h" +#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h" +#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h" +#ifdef ISP2401 +#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h" +#endif +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/vf/vf_1.0/ia_css_vf.host.h" +#include "isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h" +#include "isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h" +#endif /* IA_CSS_INCLUDE_CONFIGURATIONS */ +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_CONFIG_H +#define _IA_CSS_ISP_CONFIG_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_configuration_ids { + IA_CSS_ITERATOR_CONFIG_ID, + IA_CSS_COPY_OUTPUT_CONFIG_ID, + IA_CSS_CROP_CONFIG_ID, + IA_CSS_FPN_CONFIG_ID, + IA_CSS_DVS_CONFIG_ID, + IA_CSS_QPLANE_CONFIG_ID, + IA_CSS_OUTPUT0_CONFIG_ID, + IA_CSS_OUTPUT1_CONFIG_ID, + IA_CSS_OUTPUT_CONFIG_ID, +#ifdef ISP2401 + IA_CSS_SC_CONFIG_ID, +#endif + IA_CSS_RAW_CONFIG_ID, + IA_CSS_TNR_CONFIG_ID, + IA_CSS_REF_CONFIG_ID, + IA_CSS_VF_CONFIG_ID, + IA_CSS_NUM_CONFIGURATION_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_config_memory_offsets { + struct { + struct ia_css_isp_parameter iterator; + struct ia_css_isp_parameter copy_output; + struct ia_css_isp_parameter crop; + struct ia_css_isp_parameter fpn; + struct ia_css_isp_parameter dvs; + struct ia_css_isp_parameter qplane; + struct ia_css_isp_parameter output0; + struct ia_css_isp_parameter output1; + struct ia_css_isp_parameter output; +#ifdef ISP2401 + struct ia_css_isp_parameter sc; +#endif + struct ia_css_isp_parameter raw; + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter ref; + struct ia_css_isp_parameter vf; + } dmem; +}; + +#if defined(IA_CSS_INCLUDE_CONFIGURATIONS) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_iterator( + const struct ia_css_binary *binary, + const struct ia_css_iterator_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_copy_output( + const struct ia_css_binary *binary, + const struct ia_css_copy_output_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_crop( + const struct ia_css_binary *binary, + const struct ia_css_crop_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_fpn( + const struct ia_css_binary *binary, + const struct ia_css_fpn_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_dvs( + const struct ia_css_binary *binary, + const struct ia_css_dvs_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_qplane( + const struct ia_css_binary *binary, + const struct ia_css_qplane_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output0( + const struct ia_css_binary *binary, + const struct ia_css_output0_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output1( + const struct ia_css_binary *binary, + const struct ia_css_output1_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output( + const struct ia_css_binary *binary, + const struct ia_css_output_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +#ifdef ISP2401 +void +ia_css_configure_sc( + const struct ia_css_binary *binary, + const struct ia_css_sc_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +#endif +void +ia_css_configure_raw( + const struct ia_css_binary *binary, + const struct ia_css_raw_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_tnr( + const struct ia_css_binary *binary, + const struct ia_css_tnr_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_ref( + const struct ia_css_binary *binary, + const struct ia_css_ref_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_vf( + const struct ia_css_binary *binary, + const struct ia_css_vf_configuration *config_dmem); + +#endif /* IA_CSS_INCLUDE_CONFIGURATION */ + +#endif /* _IA_CSS_ISP_CONFIG_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.c new file mode 100644 index 0000000..11e4463 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.c @@ -0,0 +1,3220 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#define IA_CSS_INCLUDE_PARAMETERS +#include "sh_css_params.h" +#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h" +#include "isp/kernels/anr/anr_1.0/ia_css_anr.host.h" +#include "isp/kernels/anr/anr_2/ia_css_anr2.host.h" +#include "isp/kernels/bh/bh_2/ia_css_bh.host.h" +#include "isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.h" +#include "isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.h" +#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h" +#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h" +#include "isp/kernels/csc/csc_1.0/ia_css_csc.host.h" +#include "isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.h" +#include "isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.h" +#include "isp/kernels/ctc/ctc2/ia_css_ctc2.host.h" +#include "isp/kernels/de/de_1.0/ia_css_de.host.h" +#include "isp/kernels/de/de_2/ia_css_de2.host.h" +#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h" +#include "isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds_param.h" +#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h" +#include "isp/kernels/gc/gc_1.0/ia_css_gc.host.h" +#include "isp/kernels/gc/gc_2/ia_css_gc2.host.h" +#include "isp/kernels/macc/macc_1.0/ia_css_macc.host.h" +#include "isp/kernels/macc/macc1_5/ia_css_macc1_5.host.h" +#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h" +#include "isp/kernels/ob/ob2/ia_css_ob2.host.h" +#include "isp/kernels/output/output_1.0/ia_css_output.host.h" +#include "isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.h" +#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h" +#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h" +#include "isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.h" +#include "isp/kernels/sdis/sdis_2/ia_css_sdis2.host.h" +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/uds/uds_1.0/ia_css_uds_param.h" +#include "isp/kernels/wb/wb_1.0/ia_css_wb.host.h" +#include "isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.h" +#include "isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.h" +#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h" +#include "isp/kernels/ynr/ynr_2/ia_css_ynr2.host.h" +#include "isp/kernels/fc/fc_1.0/ia_css_formats.host.h" +#include "isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.h" +#include "isp/kernels/dpc2/ia_css_dpc2.host.h" +#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h" +#include "isp/kernels/bnlm/ia_css_bnlm.host.h" +#include "isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.h" +/* Generated code: do not edit or commmit. */ + +#include "ia_css_pipeline.h" +#include "ia_css_isp_params.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_aa( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.aa.size; + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset; + + if (size) { + struct sh_css_isp_aa_params *t = (struct sh_css_isp_aa_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + t->strength = params->aa_config.strength; + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_anr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.anr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() enter:\n"); + + ia_css_anr_encode((struct sh_css_isp_anr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->anr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_anr2( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() enter:\n"); + + ia_css_anr2_vmem_encode((struct ia_css_isp_anr2_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->anr_thres, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bh( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bh.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n"); + + ia_css_bh_encode((struct sh_css_isp_bh_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->s3a_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n"); + + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_HMEM0] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_cnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() enter:\n"); + + ia_css_cnr_encode((struct sh_css_isp_cnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->cnr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_crop( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.crop.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.crop.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() enter:\n"); + + ia_css_crop_encode((struct sh_css_isp_crop_isp_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->crop_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_csc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.csc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.csc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() enter:\n"); + + ia_css_csc_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->cc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_dp( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() enter:\n"); + + ia_css_dp_encode((struct sh_css_isp_dp_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dp_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() enter:\n"); + + ia_css_bnr_encode((struct sh_css_isp_bnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->nr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_de( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.de.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.de.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() enter:\n"); + + ia_css_de_encode((struct sh_css_isp_de_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->de_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ecd( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() enter:\n"); + + ia_css_ecd_encode((struct sh_css_isp_ecd_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ecd_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_formats( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.formats.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.formats.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() enter:\n"); + + ia_css_formats_encode((struct sh_css_isp_formats_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->formats_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_fpn( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() enter:\n"); + + ia_css_fpn_encode((struct sh_css_isp_fpn_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->fpn_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_gc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.gc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.gc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n"); + + ia_css_gc_encode((struct sh_css_isp_gc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->gc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n"); + + ia_css_gc_vamem_encode((struct sh_css_isp_gc_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->gc_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ce( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ce.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ce.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() enter:\n"); + + ia_css_ce_encode((struct sh_css_isp_ce_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ce_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_yuv2rgb( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() enter:\n"); + + ia_css_yuv2rgb_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->yuv2rgb_cc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_rgb2yuv( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() enter:\n"); + + ia_css_rgb2yuv_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->rgb2yuv_cc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_r_gamma( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() enter:\n"); + + ia_css_r_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM0].address[offset], + ¶ms->r_gamma_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM0] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_g_gamma( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() enter:\n"); + + ia_css_g_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->g_gamma_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_b_gamma( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() enter:\n"); + + ia_css_b_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM2].address[offset], + ¶ms->b_gamma_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM2] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_uds( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.uds.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.uds.offset; + + if (size) { + struct sh_css_sp_uds_params *p; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() enter:\n"); + + p = (struct sh_css_sp_uds_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + p->crop_pos = params->uds_config.crop_pos; + p->uds = params->uds_config.uds; + + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_raa( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.raa.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.raa.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() enter:\n"); + + ia_css_raa_encode((struct sh_css_isp_aa_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->raa_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_s3a( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() enter:\n"); + + ia_css_s3a_encode((struct sh_css_isp_s3a_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->s3a_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ob( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ob.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ob.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n"); + + ia_css_ob_encode((struct sh_css_isp_ob_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ob_config, +¶ms->stream_configs.ob, size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.ob.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.ob.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n"); + + ia_css_ob_vmem_encode((struct sh_css_isp_ob_vmem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->ob_config, +¶ms->stream_configs.ob, size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_output( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.output.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.output.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() enter:\n"); + + ia_css_output_encode((struct sh_css_isp_output_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->output_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() enter:\n"); + + ia_css_sc_encode((struct sh_css_isp_sc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->sc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bds( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bds.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bds.offset; + + if (size) { + struct sh_css_isp_bds_params *p; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() enter:\n"); + + p = (struct sh_css_isp_bds_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + p->baf_strength = params->bds_config.strength; + + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_tnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() enter:\n"); + + ia_css_tnr_encode((struct sh_css_isp_tnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->tnr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_macc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.macc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.macc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() enter:\n"); + + ia_css_macc_encode((struct sh_css_isp_macc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->macc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_horicoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() enter:\n"); + + ia_css_sdis_horicoef_vmem_encode((struct sh_css_isp_sdis_hori_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_vertcoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() enter:\n"); + + ia_css_sdis_vertcoef_vmem_encode((struct sh_css_isp_sdis_vert_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_horiproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() enter:\n"); + + ia_css_sdis_horiproj_encode((struct sh_css_isp_sdis_hori_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_vertproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() enter:\n"); + + ia_css_sdis_vertproj_encode((struct sh_css_isp_sdis_vert_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_horicoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() enter:\n"); + + ia_css_sdis2_horicoef_vmem_encode((struct sh_css_isp_sdis_hori_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_vertcoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() enter:\n"); + + ia_css_sdis2_vertcoef_vmem_encode((struct sh_css_isp_sdis_vert_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_horiproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() enter:\n"); + + ia_css_sdis2_horiproj_encode((struct sh_css_isp_sdis_hori_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_vertproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() enter:\n"); + + ia_css_sdis2_vertproj_encode((struct sh_css_isp_sdis_vert_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_wb( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.wb.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.wb.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() enter:\n"); + + ia_css_wb_encode((struct sh_css_isp_wb_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->wb_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_nr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.nr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.nr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() enter:\n"); + + ia_css_nr_encode((struct sh_css_isp_ynr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->nr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_yee( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yee.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yee.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() enter:\n"); + + ia_css_yee_encode((struct sh_css_isp_yee_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->yee_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ynr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() enter:\n"); + + ia_css_ynr_encode((struct sh_css_isp_yee2_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ynr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_fc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() enter:\n"); + + ia_css_fc_encode((struct sh_css_isp_fc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->fc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ctc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n"); + + ia_css_ctc_encode((struct sh_css_isp_ctc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ctc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n"); + + ia_css_ctc_vamem_encode((struct sh_css_isp_ctc_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM0].address[offset], + ¶ms->ctc_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM0] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr_table( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() enter:\n"); + + ia_css_xnr_table_vamem_encode((struct sh_css_isp_xnr_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->xnr_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() enter:\n"); + + ia_css_xnr_encode((struct sh_css_isp_xnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->xnr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr3( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n"); + + ia_css_xnr3_encode((struct sh_css_isp_xnr3_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->xnr3_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n"); + } + + } +#ifdef ISP2401 + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n"); + + ia_css_xnr3_vmem_encode((struct sh_css_isp_xnr3_vmem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->xnr3_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n"); + } + + } +#endif +} + +/* Code generated by genparam/gencode.c:gen_param_process_table() */ + +void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) = { + ia_css_process_aa, + ia_css_process_anr, + ia_css_process_anr2, + ia_css_process_bh, + ia_css_process_cnr, + ia_css_process_crop, + ia_css_process_csc, + ia_css_process_dp, + ia_css_process_bnr, + ia_css_process_de, + ia_css_process_ecd, + ia_css_process_formats, + ia_css_process_fpn, + ia_css_process_gc, + ia_css_process_ce, + ia_css_process_yuv2rgb, + ia_css_process_rgb2yuv, + ia_css_process_r_gamma, + ia_css_process_g_gamma, + ia_css_process_b_gamma, + ia_css_process_uds, + ia_css_process_raa, + ia_css_process_s3a, + ia_css_process_ob, + ia_css_process_output, + ia_css_process_sc, + ia_css_process_bds, + ia_css_process_tnr, + ia_css_process_macc, + ia_css_process_sdis_horicoef, + ia_css_process_sdis_vertcoef, + ia_css_process_sdis_horiproj, + ia_css_process_sdis_vertproj, + ia_css_process_sdis2_horicoef, + ia_css_process_sdis2_vertcoef, + ia_css_process_sdis2_horiproj, + ia_css_process_sdis2_vertproj, + ia_css_process_wb, + ia_css_process_nr, + ia_css_process_yee, + ia_css_process_ynr, + ia_css_process_fc, + ia_css_process_ctc, + ia_css_process_xnr_table, + ia_css_process_xnr, + ia_css_process_xnr3, +}; + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_dp_config(const struct ia_css_isp_parameters *params, + struct ia_css_dp_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() enter: " + "config=%p\n",config); + + *config = params->dp_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() leave\n"); + ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_dp_config(struct ia_css_isp_parameters *params, + const struct ia_css_dp_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_dp_config() enter:\n"); + ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dp_config = *config; + params->config_changed[IA_CSS_DP_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_DP_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_dp_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_wb_config(const struct ia_css_isp_parameters *params, + struct ia_css_wb_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() enter: " + "config=%p\n",config); + + *config = params->wb_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() leave\n"); + ia_css_wb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_wb_config(struct ia_css_isp_parameters *params, + const struct ia_css_wb_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_wb_config() enter:\n"); + ia_css_wb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->wb_config = *config; + params->config_changed[IA_CSS_WB_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_WB_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_wb_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_tnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_tnr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() enter: " + "config=%p\n",config); + + *config = params->tnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() leave\n"); + ia_css_tnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_tnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_tnr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_tnr_config() enter:\n"); + ia_css_tnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->tnr_config = *config; + params->config_changed[IA_CSS_TNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_TNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_tnr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ob_config(const struct ia_css_isp_parameters *params, + struct ia_css_ob_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() enter: " + "config=%p\n",config); + + *config = params->ob_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() leave\n"); + ia_css_ob_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ob_config(struct ia_css_isp_parameters *params, + const struct ia_css_ob_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ob_config() enter:\n"); + ia_css_ob_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ob_config = *config; + params->config_changed[IA_CSS_OB_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_OB_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ob_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_de_config(const struct ia_css_isp_parameters *params, + struct ia_css_de_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() enter: " + "config=%p\n",config); + + *config = params->de_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() leave\n"); + ia_css_de_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_de_config(struct ia_css_isp_parameters *params, + const struct ia_css_de_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_de_config() enter:\n"); + ia_css_de_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->de_config = *config; + params->config_changed[IA_CSS_DE_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_DE_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_de_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_anr_config(const struct ia_css_isp_parameters *params, + struct ia_css_anr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() enter: " + "config=%p\n",config); + + *config = params->anr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() leave\n"); + ia_css_anr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr_config() enter:\n"); + ia_css_anr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->anr_config = *config; + params->config_changed[IA_CSS_ANR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_ANR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_anr2_config(const struct ia_css_isp_parameters *params, + struct ia_css_anr_thres *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() enter: " + "config=%p\n",config); + + *config = params->anr_thres; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() leave\n"); + ia_css_anr2_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr2_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_thres *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr2_config() enter:\n"); + ia_css_anr2_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->anr_thres = *config; + params->config_changed[IA_CSS_ANR2_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_ANR2_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr2_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ce_config(const struct ia_css_isp_parameters *params, + struct ia_css_ce_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() enter: " + "config=%p\n",config); + + *config = params->ce_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() leave\n"); + ia_css_ce_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ce_config(struct ia_css_isp_parameters *params, + const struct ia_css_ce_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ce_config() enter:\n"); + ia_css_ce_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ce_config = *config; + params->config_changed[IA_CSS_CE_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CE_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ce_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ecd_config(const struct ia_css_isp_parameters *params, + struct ia_css_ecd_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() enter: " + "config=%p\n",config); + + *config = params->ecd_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() leave\n"); + ia_css_ecd_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ecd_config(struct ia_css_isp_parameters *params, + const struct ia_css_ecd_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ecd_config() enter:\n"); + ia_css_ecd_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ecd_config = *config; + params->config_changed[IA_CSS_ECD_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_ECD_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ecd_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ynr_config(const struct ia_css_isp_parameters *params, + struct ia_css_ynr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() enter: " + "config=%p\n",config); + + *config = params->ynr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() leave\n"); + ia_css_ynr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ynr_config(struct ia_css_isp_parameters *params, + const struct ia_css_ynr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ynr_config() enter:\n"); + ia_css_ynr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ynr_config = *config; + params->config_changed[IA_CSS_YNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_YNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ynr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_fc_config(const struct ia_css_isp_parameters *params, + struct ia_css_fc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() enter: " + "config=%p\n",config); + + *config = params->fc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() leave\n"); + ia_css_fc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_fc_config(struct ia_css_isp_parameters *params, + const struct ia_css_fc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_fc_config() enter:\n"); + ia_css_fc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->fc_config = *config; + params->config_changed[IA_CSS_FC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_FC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_fc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_cnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_cnr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() enter: " + "config=%p\n",config); + + *config = params->cnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() leave\n"); + ia_css_cnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_cnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_cnr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_cnr_config() enter:\n"); + ia_css_cnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->cnr_config = *config; + params->config_changed[IA_CSS_CNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_cnr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_macc_config(const struct ia_css_isp_parameters *params, + struct ia_css_macc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() enter: " + "config=%p\n",config); + + *config = params->macc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() leave\n"); + ia_css_macc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_macc_config(struct ia_css_isp_parameters *params, + const struct ia_css_macc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_macc_config() enter:\n"); + ia_css_macc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->macc_config = *config; + params->config_changed[IA_CSS_MACC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_MACC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_macc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ctc_config(const struct ia_css_isp_parameters *params, + struct ia_css_ctc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() enter: " + "config=%p\n",config); + + *config = params->ctc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() leave\n"); + ia_css_ctc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ctc_config(struct ia_css_isp_parameters *params, + const struct ia_css_ctc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ctc_config() enter:\n"); + ia_css_ctc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ctc_config = *config; + params->config_changed[IA_CSS_CTC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CTC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ctc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_aa_config(const struct ia_css_isp_parameters *params, + struct ia_css_aa_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() enter: " + "config=%p\n",config); + + *config = params->aa_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() leave\n"); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_aa_config(struct ia_css_isp_parameters *params, + const struct ia_css_aa_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_aa_config() enter:\n"); + params->aa_config = *config; + params->config_changed[IA_CSS_AA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_AA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_aa_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_yuv2rgb_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() enter: " + "config=%p\n",config); + + *config = params->yuv2rgb_cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() leave\n"); + ia_css_yuv2rgb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_yuv2rgb_config() enter:\n"); + ia_css_yuv2rgb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->yuv2rgb_cc_config = *config; + params->config_changed[IA_CSS_YUV2RGB_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_YUV2RGB_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_yuv2rgb_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_rgb2yuv_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() enter: " + "config=%p\n",config); + + *config = params->rgb2yuv_cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() leave\n"); + ia_css_rgb2yuv_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_rgb2yuv_config() enter:\n"); + ia_css_rgb2yuv_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->rgb2yuv_cc_config = *config; + params->config_changed[IA_CSS_RGB2YUV_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_RGB2YUV_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_rgb2yuv_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_csc_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() enter: " + "config=%p\n",config); + + *config = params->cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() leave\n"); + ia_css_csc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_csc_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_csc_config() enter:\n"); + ia_css_csc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->cc_config = *config; + params->config_changed[IA_CSS_CSC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CSC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_csc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_nr_config(const struct ia_css_isp_parameters *params, + struct ia_css_nr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() enter: " + "config=%p\n",config); + + *config = params->nr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() leave\n"); + ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_nr_config(struct ia_css_isp_parameters *params, + const struct ia_css_nr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_nr_config() enter:\n"); + ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->nr_config = *config; + params->config_changed[IA_CSS_BNR_ID] = true; + params->config_changed[IA_CSS_NR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_NR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_nr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_gc_config(const struct ia_css_isp_parameters *params, + struct ia_css_gc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() enter: " + "config=%p\n",config); + + *config = params->gc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() leave\n"); + ia_css_gc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_gc_config(struct ia_css_isp_parameters *params, + const struct ia_css_gc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_gc_config() enter:\n"); + ia_css_gc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->gc_config = *config; + params->config_changed[IA_CSS_GC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_GC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_gc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_horicoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() leave\n"); + ia_css_sdis_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horicoef_config() enter:\n"); + ia_css_sdis_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horicoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_vertcoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() leave\n"); + ia_css_sdis_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertcoef_config() enter:\n"); + ia_css_sdis_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertcoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_horiproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() leave\n"); + ia_css_sdis_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horiproj_config() enter:\n"); + ia_css_sdis_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horiproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_vertproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() leave\n"); + ia_css_sdis_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertproj_config() enter:\n"); + ia_css_sdis_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_horicoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() leave\n"); + ia_css_sdis2_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horicoef_config() enter:\n"); + ia_css_sdis2_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horicoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_vertcoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() leave\n"); + ia_css_sdis2_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertcoef_config() enter:\n"); + ia_css_sdis2_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertcoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_horiproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() leave\n"); + ia_css_sdis2_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horiproj_config() enter:\n"); + ia_css_sdis2_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horiproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_vertproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() leave\n"); + ia_css_sdis2_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertproj_config() enter:\n"); + ia_css_sdis2_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_r_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() enter: " + "config=%p\n",config); + + *config = params->r_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() leave\n"); + ia_css_r_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_r_gamma_config() enter:\n"); + ia_css_r_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->r_gamma_table = *config; + params->config_changed[IA_CSS_R_GAMMA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_R_GAMMA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_r_gamma_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_g_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() enter: " + "config=%p\n",config); + + *config = params->g_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() leave\n"); + ia_css_g_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_g_gamma_config() enter:\n"); + ia_css_g_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->g_gamma_table = *config; + params->config_changed[IA_CSS_G_GAMMA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_G_GAMMA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_g_gamma_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_b_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() enter: " + "config=%p\n",config); + + *config = params->b_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() leave\n"); + ia_css_b_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_b_gamma_config() enter:\n"); + ia_css_b_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->b_gamma_table = *config; + params->config_changed[IA_CSS_B_GAMMA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_B_GAMMA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_b_gamma_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr_table_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() enter: " + "config=%p\n",config); + + *config = params->xnr_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() leave\n"); + ia_css_xnr_table_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_table_config() enter:\n"); + ia_css_xnr_table_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr_table = *config; + params->config_changed[IA_CSS_XNR_TABLE_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_XNR_TABLE_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_table_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_formats_config(const struct ia_css_isp_parameters *params, + struct ia_css_formats_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() enter: " + "config=%p\n",config); + + *config = params->formats_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() leave\n"); + ia_css_formats_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_formats_config(struct ia_css_isp_parameters *params, + const struct ia_css_formats_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_formats_config() enter:\n"); + ia_css_formats_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->formats_config = *config; + params->config_changed[IA_CSS_FORMATS_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_FORMATS_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_formats_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() enter: " + "config=%p\n",config); + + *config = params->xnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() leave\n"); + ia_css_xnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_config() enter:\n"); + ia_css_xnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr_config = *config; + params->config_changed[IA_CSS_XNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_XNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr3_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr3_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() enter: " + "config=%p\n",config); + + *config = params->xnr3_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() leave\n"); + ia_css_xnr3_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr3_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr3_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr3_config() enter:\n"); + ia_css_xnr3_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr3_config = *config; + params->config_changed[IA_CSS_XNR3_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_XNR3_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr3_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_s3a_config(const struct ia_css_isp_parameters *params, + struct ia_css_3a_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() enter: " + "config=%p\n",config); + + *config = params->s3a_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() leave\n"); + ia_css_s3a_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_s3a_config(struct ia_css_isp_parameters *params, + const struct ia_css_3a_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_s3a_config() enter:\n"); + ia_css_s3a_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->s3a_config = *config; + params->config_changed[IA_CSS_BH_ID] = true; + params->config_changed[IA_CSS_S3A_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_S3A_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_s3a_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_output_config(const struct ia_css_isp_parameters *params, + struct ia_css_output_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() enter: " + "config=%p\n",config); + + *config = params->output_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() leave\n"); + ia_css_output_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_output_config(struct ia_css_isp_parameters *params, + const struct ia_css_output_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_output_config() enter:\n"); + ia_css_output_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->output_config = *config; + params->config_changed[IA_CSS_OUTPUT_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_OUTPUT_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_output_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_get_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +{ + ia_css_get_dp_config(params, config->dp_config); + ia_css_get_wb_config(params, config->wb_config); + ia_css_get_tnr_config(params, config->tnr_config); + ia_css_get_ob_config(params, config->ob_config); + ia_css_get_de_config(params, config->de_config); + ia_css_get_anr_config(params, config->anr_config); + ia_css_get_anr2_config(params, config->anr_thres); + ia_css_get_ce_config(params, config->ce_config); + ia_css_get_ecd_config(params, config->ecd_config); + ia_css_get_ynr_config(params, config->ynr_config); + ia_css_get_fc_config(params, config->fc_config); + ia_css_get_cnr_config(params, config->cnr_config); + ia_css_get_macc_config(params, config->macc_config); + ia_css_get_ctc_config(params, config->ctc_config); + ia_css_get_aa_config(params, config->aa_config); + ia_css_get_yuv2rgb_config(params, config->yuv2rgb_cc_config); + ia_css_get_rgb2yuv_config(params, config->rgb2yuv_cc_config); + ia_css_get_csc_config(params, config->cc_config); + ia_css_get_nr_config(params, config->nr_config); + ia_css_get_gc_config(params, config->gc_config); + ia_css_get_sdis_horicoef_config(params, config->dvs_coefs); + ia_css_get_sdis_vertcoef_config(params, config->dvs_coefs); + ia_css_get_sdis_horiproj_config(params, config->dvs_coefs); + ia_css_get_sdis_vertproj_config(params, config->dvs_coefs); + ia_css_get_sdis2_horicoef_config(params, config->dvs2_coefs); + ia_css_get_sdis2_vertcoef_config(params, config->dvs2_coefs); + ia_css_get_sdis2_horiproj_config(params, config->dvs2_coefs); + ia_css_get_sdis2_vertproj_config(params, config->dvs2_coefs); + ia_css_get_r_gamma_config(params, config->r_gamma_table); + ia_css_get_g_gamma_config(params, config->g_gamma_table); + ia_css_get_b_gamma_config(params, config->b_gamma_table); + ia_css_get_xnr_table_config(params, config->xnr_table); + ia_css_get_formats_config(params, config->formats_config); + ia_css_get_xnr_config(params, config->xnr_config); + ia_css_get_xnr3_config(params, config->xnr3_config); + ia_css_get_s3a_config(params, config->s3a_config); + ia_css_get_output_config(params, config->output_config); +} + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_set_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +{ + ia_css_set_dp_config(params, config->dp_config); + ia_css_set_wb_config(params, config->wb_config); + ia_css_set_tnr_config(params, config->tnr_config); + ia_css_set_ob_config(params, config->ob_config); + ia_css_set_de_config(params, config->de_config); + ia_css_set_anr_config(params, config->anr_config); + ia_css_set_anr2_config(params, config->anr_thres); + ia_css_set_ce_config(params, config->ce_config); + ia_css_set_ecd_config(params, config->ecd_config); + ia_css_set_ynr_config(params, config->ynr_config); + ia_css_set_fc_config(params, config->fc_config); + ia_css_set_cnr_config(params, config->cnr_config); + ia_css_set_macc_config(params, config->macc_config); + ia_css_set_ctc_config(params, config->ctc_config); + ia_css_set_aa_config(params, config->aa_config); + ia_css_set_yuv2rgb_config(params, config->yuv2rgb_cc_config); + ia_css_set_rgb2yuv_config(params, config->rgb2yuv_cc_config); + ia_css_set_csc_config(params, config->cc_config); + ia_css_set_nr_config(params, config->nr_config); + ia_css_set_gc_config(params, config->gc_config); + ia_css_set_sdis_horicoef_config(params, config->dvs_coefs); + ia_css_set_sdis_vertcoef_config(params, config->dvs_coefs); + ia_css_set_sdis_horiproj_config(params, config->dvs_coefs); + ia_css_set_sdis_vertproj_config(params, config->dvs_coefs); + ia_css_set_sdis2_horicoef_config(params, config->dvs2_coefs); + ia_css_set_sdis2_vertcoef_config(params, config->dvs2_coefs); + ia_css_set_sdis2_horiproj_config(params, config->dvs2_coefs); + ia_css_set_sdis2_vertproj_config(params, config->dvs2_coefs); + ia_css_set_r_gamma_config(params, config->r_gamma_table); + ia_css_set_g_gamma_config(params, config->g_gamma_table); + ia_css_set_b_gamma_config(params, config->b_gamma_table); + ia_css_set_xnr_table_config(params, config->xnr_table); + ia_css_set_formats_config(params, config->formats_config); + ia_css_set_xnr_config(params, config->xnr_config); + ia_css_set_xnr3_config(params, config->xnr3_config); + ia_css_set_s3a_config(params, config->s3a_config); + ia_css_set_output_config(params, config->output_config); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.h new file mode 100644 index 0000000..5b3deb7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.h @@ -0,0 +1,399 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_PARAM_H +#define _IA_CSS_ISP_PARAM_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_parameter_ids { + IA_CSS_AA_ID, + IA_CSS_ANR_ID, + IA_CSS_ANR2_ID, + IA_CSS_BH_ID, + IA_CSS_CNR_ID, + IA_CSS_CROP_ID, + IA_CSS_CSC_ID, + IA_CSS_DP_ID, + IA_CSS_BNR_ID, + IA_CSS_DE_ID, + IA_CSS_ECD_ID, + IA_CSS_FORMATS_ID, + IA_CSS_FPN_ID, + IA_CSS_GC_ID, + IA_CSS_CE_ID, + IA_CSS_YUV2RGB_ID, + IA_CSS_RGB2YUV_ID, + IA_CSS_R_GAMMA_ID, + IA_CSS_G_GAMMA_ID, + IA_CSS_B_GAMMA_ID, + IA_CSS_UDS_ID, + IA_CSS_RAA_ID, + IA_CSS_S3A_ID, + IA_CSS_OB_ID, + IA_CSS_OUTPUT_ID, + IA_CSS_SC_ID, + IA_CSS_BDS_ID, + IA_CSS_TNR_ID, + IA_CSS_MACC_ID, + IA_CSS_SDIS_HORICOEF_ID, + IA_CSS_SDIS_VERTCOEF_ID, + IA_CSS_SDIS_HORIPROJ_ID, + IA_CSS_SDIS_VERTPROJ_ID, + IA_CSS_SDIS2_HORICOEF_ID, + IA_CSS_SDIS2_VERTCOEF_ID, + IA_CSS_SDIS2_HORIPROJ_ID, + IA_CSS_SDIS2_VERTPROJ_ID, + IA_CSS_WB_ID, + IA_CSS_NR_ID, + IA_CSS_YEE_ID, + IA_CSS_YNR_ID, + IA_CSS_FC_ID, + IA_CSS_CTC_ID, + IA_CSS_XNR_TABLE_ID, + IA_CSS_XNR_ID, + IA_CSS_XNR3_ID, + IA_CSS_NUM_PARAMETER_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_memory_offsets { + struct { + struct ia_css_isp_parameter aa; + struct ia_css_isp_parameter anr; + struct ia_css_isp_parameter bh; + struct ia_css_isp_parameter cnr; + struct ia_css_isp_parameter crop; + struct ia_css_isp_parameter csc; + struct ia_css_isp_parameter dp; + struct ia_css_isp_parameter bnr; + struct ia_css_isp_parameter de; + struct ia_css_isp_parameter ecd; + struct ia_css_isp_parameter formats; + struct ia_css_isp_parameter fpn; + struct ia_css_isp_parameter gc; + struct ia_css_isp_parameter ce; + struct ia_css_isp_parameter yuv2rgb; + struct ia_css_isp_parameter rgb2yuv; + struct ia_css_isp_parameter uds; + struct ia_css_isp_parameter raa; + struct ia_css_isp_parameter s3a; + struct ia_css_isp_parameter ob; + struct ia_css_isp_parameter output; + struct ia_css_isp_parameter sc; + struct ia_css_isp_parameter bds; + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter macc; + struct ia_css_isp_parameter sdis_horiproj; + struct ia_css_isp_parameter sdis_vertproj; + struct ia_css_isp_parameter sdis2_horiproj; + struct ia_css_isp_parameter sdis2_vertproj; + struct ia_css_isp_parameter wb; + struct ia_css_isp_parameter nr; + struct ia_css_isp_parameter yee; + struct ia_css_isp_parameter ynr; + struct ia_css_isp_parameter fc; + struct ia_css_isp_parameter ctc; + struct ia_css_isp_parameter xnr; + struct ia_css_isp_parameter xnr3; + struct ia_css_isp_parameter get; + struct ia_css_isp_parameter put; + } dmem; + struct { + struct ia_css_isp_parameter anr2; + struct ia_css_isp_parameter ob; + struct ia_css_isp_parameter sdis_horicoef; + struct ia_css_isp_parameter sdis_vertcoef; + struct ia_css_isp_parameter sdis2_horicoef; + struct ia_css_isp_parameter sdis2_vertcoef; +#ifdef ISP2401 + struct ia_css_isp_parameter xnr3; +#endif + } vmem; + struct { + struct ia_css_isp_parameter bh; + } hmem0; + struct { + struct ia_css_isp_parameter gc; + struct ia_css_isp_parameter g_gamma; + struct ia_css_isp_parameter xnr_table; + } vamem1; + struct { + struct ia_css_isp_parameter r_gamma; + struct ia_css_isp_parameter ctc; + } vamem0; + struct { + struct ia_css_isp_parameter b_gamma; + } vamem2; +}; + +#if defined(IA_CSS_INCLUDE_PARAMETERS) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/gencode.c:gen_param_process_table() */ + +struct ia_css_pipeline_stage; /* forward declaration */ + +extern void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_dp_config(struct ia_css_isp_parameters *params, + const struct ia_css_dp_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_wb_config(struct ia_css_isp_parameters *params, + const struct ia_css_wb_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_tnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_tnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ob_config(struct ia_css_isp_parameters *params, + const struct ia_css_ob_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_de_config(struct ia_css_isp_parameters *params, + const struct ia_css_de_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr2_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_thres *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ce_config(struct ia_css_isp_parameters *params, + const struct ia_css_ce_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ecd_config(struct ia_css_isp_parameters *params, + const struct ia_css_ecd_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ynr_config(struct ia_css_isp_parameters *params, + const struct ia_css_ynr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_fc_config(struct ia_css_isp_parameters *params, + const struct ia_css_fc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_cnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_cnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_macc_config(struct ia_css_isp_parameters *params, + const struct ia_css_macc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ctc_config(struct ia_css_isp_parameters *params, + const struct ia_css_ctc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_aa_config(struct ia_css_isp_parameters *params, + const struct ia_css_aa_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_csc_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_nr_config(struct ia_css_isp_parameters *params, + const struct ia_css_nr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_gc_config(struct ia_css_isp_parameters *params, + const struct ia_css_gc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_formats_config(struct ia_css_isp_parameters *params, + const struct ia_css_formats_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr3_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr3_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_s3a_config(struct ia_css_isp_parameters *params, + const struct ia_css_3a_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_output_config(struct ia_css_isp_parameters *params, + const struct ia_css_output_config *config); + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_get_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +; +#ifdef ISP2401 + +#endif +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_set_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +; +#ifdef ISP2401 + +#endif +#endif /* IA_CSS_INCLUDE_PARAMETER */ + +#endif /* _IA_CSS_ISP_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.c new file mode 100644 index 0000000..e87d05b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.c @@ -0,0 +1,214 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Generated code: do not edit or commmit. */ + +#include "ia_css_pipeline.h" +#include "ia_css_isp_states.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_aa_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.aa.size; + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset; + + if (size) + memset(&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], 0, size); + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_cnr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset; + + if (size) { + ia_css_init_cnr_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_cnr2_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset; + + if (size) { + ia_css_init_cnr2_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_dp_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.dp.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset; + + if (size) { + ia_css_init_dp_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_de_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.de.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.de.offset; + + if (size) { + ia_css_init_de_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_tnr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->dmem.tnr.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset; + + if (size) { + ia_css_init_tnr_state((struct sh_css_isp_tnr_dmem_state *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_ref_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->dmem.ref.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset; + + if (size) { + ia_css_init_ref_state((struct sh_css_isp_ref_dmem_state *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_ynr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.ynr.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset; + + if (size) { + ia_css_init_ynr_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_state_init_table() */ + +void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(const struct ia_css_binary *binary) = { + ia_css_initialize_aa_state, + ia_css_initialize_cnr_state, + ia_css_initialize_cnr2_state, + ia_css_initialize_dp_state, + ia_css_initialize_de_state, + ia_css_initialize_tnr_state, + ia_css_initialize_ref_state, + ia_css_initialize_ynr_state, +}; + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.h new file mode 100644 index 0000000..732adaf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.h @@ -0,0 +1,72 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#define IA_CSS_INCLUDE_STATES +#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h" +#include "isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h" +#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h" +#include "isp/kernels/de/de_1.0/ia_css_de.host.h" +#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h" +#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h" +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h" +#include "isp/kernels/dpc2/ia_css_dpc2.host.h" +#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h" +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_STATE_H +#define _IA_CSS_ISP_STATE_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_state_ids { + IA_CSS_AA_STATE_ID, + IA_CSS_CNR_STATE_ID, + IA_CSS_CNR2_STATE_ID, + IA_CSS_DP_STATE_ID, + IA_CSS_DE_STATE_ID, + IA_CSS_TNR_STATE_ID, + IA_CSS_REF_STATE_ID, + IA_CSS_YNR_STATE_ID, + IA_CSS_NUM_STATE_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_state_memory_offsets { + struct { + struct ia_css_isp_parameter aa; + struct ia_css_isp_parameter cnr; + struct ia_css_isp_parameter cnr2; + struct ia_css_isp_parameter dp; + struct ia_css_isp_parameter de; + struct ia_css_isp_parameter ynr; + } vmem; + struct { + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter ref; + } dmem; +}; + +#if defined(IA_CSS_INCLUDE_STATES) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/genstate.c:gen_state_init_table() */ + +extern void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(const struct ia_css_binary *binary); + +#endif /* IA_CSS_INCLUDE_STATE */ + +#endif /* _IA_CSS_ISP_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx.c new file mode 100644 index 0000000..505e2b6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx.c @@ -0,0 +1,41 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + + +#include "system_global.h" + +const uint32_t N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = { + 4, /* 4 entries at CSI_RX_BACKEND0_ID*/ + 4, /* 4 entries at CSI_RX_BACKEND1_ID*/ + 4 /* 4 entries at CSI_RX_BACKEND2_ID*/ +}; + +const uint32_t N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = { + 8, /* 8 entries at CSI_RX_BACKEND0_ID*/ + 4, /* 4 entries at CSI_RX_BACKEND1_ID*/ + 4 /* 4 entries at CSI_RX_BACKEND2_ID*/ +}; + +const uint32_t N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID] = { + N_CSI_RX_DLANE_ID, /* 4 dlanes for CSI_RX_FR0NTEND0_ID */ + N_CSI_RX_DLANE_ID, /* 4 dlanes for CSI_RX_FR0NTEND1_ID */ + N_CSI_RX_DLANE_ID /* 4 dlanes for CSI_RX_FR0NTEND2_ID */ +}; + +/* sid_width for CSI_RX_BACKEND<N>_ID */ +const uint32_t N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID] = { + 3, + 2, + 2 +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_local.h new file mode 100644 index 0000000..a2e9d54 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_local.h @@ -0,0 +1,61 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_LOCAL_H_INCLUDED__ +#define __CSI_RX_LOCAL_H_INCLUDED__ + +#include "csi_rx_global.h" +#define N_CSI_RX_BE_MIPI_COMP_FMT_REG 4 +#define N_CSI_RX_BE_MIPI_CUSTOM_PEC 12 +#define N_CSI_RX_BE_SHORT_PKT_LUT 4 +#define N_CSI_RX_BE_LONG_PKT_LUT 8 +typedef struct csi_rx_fe_ctrl_state_s csi_rx_fe_ctrl_state_t; +typedef struct csi_rx_fe_ctrl_lane_s csi_rx_fe_ctrl_lane_t; +typedef struct csi_rx_be_ctrl_state_s csi_rx_be_ctrl_state_t; +/*mipi_backend_custom_mode_pixel_extraction_config*/ +typedef struct csi_rx_be_ctrl_pec_s csi_rx_be_ctrl_pec_t; + + +struct csi_rx_fe_ctrl_lane_s { + hrt_data termen; + hrt_data settle; +}; +struct csi_rx_fe_ctrl_state_s { + hrt_data enable; + hrt_data nof_enable_lanes; + hrt_data error_handling; + hrt_data status; + hrt_data status_dlane_hs; + hrt_data status_dlane_lp; + csi_rx_fe_ctrl_lane_t clane; + csi_rx_fe_ctrl_lane_t dlane[N_CSI_RX_DLANE_ID]; +}; +struct csi_rx_be_ctrl_state_s { + hrt_data enable; + hrt_data status; + hrt_data comp_format_reg[N_CSI_RX_BE_MIPI_COMP_FMT_REG]; + hrt_data raw16; + hrt_data raw18; + hrt_data force_raw8; + hrt_data irq_status; + hrt_data custom_mode_enable; + hrt_data custom_mode_data_state; + hrt_data pec[N_CSI_RX_BE_MIPI_CUSTOM_PEC]; + hrt_data custom_mode_valid_eop_config; + hrt_data global_lut_disregard_reg; + hrt_data packet_status_stall; + hrt_data short_packet_lut_entry[N_CSI_RX_BE_SHORT_PKT_LUT]; + hrt_data long_packet_lut_entry[N_CSI_RX_BE_LONG_PKT_LUT]; +}; +#endif /* __CSI_RX_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_private.h new file mode 100644 index 0000000..5819bcf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_private.h @@ -0,0 +1,282 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_PRIVATE_H_INCLUDED__ +#define __CSI_RX_PRIVATE_H_INCLUDED__ + +#include "rx_csi_defs.h" +#include "mipi_backend_defs.h" +#include "csi_rx_public.h" + +#include "device_access.h" /* ia_css_device_load_uint32 */ + +#include "assert_support.h" /* assert */ +#include "print_support.h" /* print */ + + +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the csi rx fe state. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_fe_ctrl_get_state( + const csi_rx_frontend_ID_t ID, + csi_rx_fe_ctrl_state_t *state) +{ + uint32_t i; + + state->enable = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ENABLE_REG_IDX); + state->nof_enable_lanes = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX); + state->error_handling = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ERROR_HANDLING_REG_IDX); + state->status = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_REG_IDX); + state->status_dlane_hs = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX); + state->status_dlane_lp = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX); + state->clane.termen = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX); + state->clane.settle = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX); + + /* + * Get the values of the register-set per + * dlane. + */ + for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) { + csi_rx_fe_ctrl_get_dlane_state( + ID, + i, + &(state->dlane[i])); + } +} + +/** + * @brief Get the state of the csi rx fe dlane process. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_fe_ctrl_get_dlane_state( + const csi_rx_frontend_ID_t ID, + const uint32_t lane, + csi_rx_fe_ctrl_lane_t *dlane_state) +{ + + dlane_state->termen = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane)); + dlane_state->settle = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane)); + +} +/** + * @brief dump the csi rx fe state. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_fe_ctrl_dump_state( + const csi_rx_frontend_ID_t ID, + csi_rx_fe_ctrl_state_t *state) +{ + uint32_t i; + + ia_css_print("CSI RX FE STATE Controller %d Enable state 0x%x \n", ID, state->enable); + ia_css_print("CSI RX FE STATE Controller %d No Of enable lanes 0x%x \n", ID, state->nof_enable_lanes); + ia_css_print("CSI RX FE STATE Controller %d Error handling 0x%x \n", ID, state->error_handling); + ia_css_print("CSI RX FE STATE Controller %d Status 0x%x \n", ID, state->status); + ia_css_print("CSI RX FE STATE Controller %d Status Dlane HS 0x%x \n", ID, state->status_dlane_hs); + ia_css_print("CSI RX FE STATE Controller %d Status Dlane LP 0x%x \n", ID, state->status_dlane_lp); + ia_css_print("CSI RX FE STATE Controller %d Status term enable LP 0x%x \n", ID, state->clane.termen); + ia_css_print("CSI RX FE STATE Controller %d Status term settle LP 0x%x \n", ID, state->clane.settle); + + /* + * Get the values of the register-set per + * dlane. + */ + for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) { + ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d termen 0x%x \n", ID, i, state->dlane[i].termen); + ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d settle 0x%x \n", ID, i, state->dlane[i].settle); + } +} + +/** + * @brief Get the csi rx be state. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_be_ctrl_get_state( + const csi_rx_backend_ID_t ID, + csi_rx_be_ctrl_state_t *state) +{ + uint32_t i; + + state->enable = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_ENABLE_REG_IDX); + + state->status = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_STATUS_REG_IDX); + + for(i = 0; i <N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) { + state->comp_format_reg[i] = + csi_rx_be_ctrl_reg_load(ID, + _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX+i); + } + + state->raw16 = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX); + + state->raw18 = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX); + state->force_raw8 = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX); + state->irq_status = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX); +#if 0 /* device access error for these registers */ + /* ToDo: rootcause this failure */ + state->custom_mode_enable = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_EN_REG_IDX); + + state->custom_mode_data_state = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX); + for(i = 0; i <N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) { + state->pec[i] = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX + i); + } + state->custom_mode_valid_eop_config = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX); +#endif + state->global_lut_disregard_reg = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX); + state->packet_status_stall = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX); + /* + * Get the values of the register-set per + * lut. + */ + for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) { + state->short_packet_lut_entry[i] = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX + i); + } + for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) { + state->long_packet_lut_entry[i] = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX + i); + } +} + +/** + * @brief Dump the csi rx be state. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_be_ctrl_dump_state( + const csi_rx_backend_ID_t ID, + csi_rx_be_ctrl_state_t *state) +{ + uint32_t i; + + ia_css_print("CSI RX BE STATE Controller %d Enable 0x%x \n", ID, state->enable); + ia_css_print("CSI RX BE STATE Controller %d Status 0x%x \n", ID, state->status); + + for(i = 0; i <N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) { + ia_css_print("CSI RX BE STATE Controller %d comp format reg vc%d value 0x%x \n", ID, i, state->status); + } + ia_css_print("CSI RX BE STATE Controller %d RAW16 0x%x \n", ID, state->raw16); + ia_css_print("CSI RX BE STATE Controller %d RAW18 0x%x \n", ID, state->raw18); + ia_css_print("CSI RX BE STATE Controller %d Force RAW8 0x%x \n", ID, state->force_raw8); + ia_css_print("CSI RX BE STATE Controller %d IRQ state 0x%x \n", ID, state->irq_status); +#if 0 /* ToDo:Getting device access error for this register */ + for(i = 0; i <N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) { + ia_css_print("CSI RX BE STATE Controller %d PEC ID %d custom pec 0x%x \n", ID, i, state->pec[i]); + } +#endif + ia_css_print("CSI RX BE STATE Controller %d Global LUT diregard reg 0x%x \n", ID, state->global_lut_disregard_reg); + ia_css_print("CSI RX BE STATE Controller %d packet stall reg 0x%x \n", ID, state->packet_status_stall); + /* + * Get the values of the register-set per + * lut. + */ + for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) { + ia_css_print("CSI RX BE STATE Controller ID %d Short packat entry %d shart packet lut id 0x%x \n", ID, i, state->short_packet_lut_entry[i]); + } + for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) { + ia_css_print("CSI RX BE STATE Controller ID %d Long packat entry %d Long packet lut id 0x%x \n", ID, i, state->long_packet_lut_entry[i]); + } +} +/* end of NCI */ +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C hrt_data csi_rx_fe_ctrl_reg_load( + const csi_rx_frontend_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_CSI_RX_FRONTEND_ID); + assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg*sizeof(hrt_data)); +} + + +/** + * @brief Store a value to the register. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_fe_ctrl_reg_store( + const csi_rx_frontend_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_CSI_RX_FRONTEND_ID); + assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); +} +/** + * @brief Load the register value. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C hrt_data csi_rx_be_ctrl_reg_load( + const csi_rx_backend_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_CSI_RX_BACKEND_ID); + assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg*sizeof(hrt_data)); +} + + +/** + * @brief Store a value to the register. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_be_ctrl_reg_store( + const csi_rx_backend_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_CSI_RX_BACKEND_ID); + assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); +} +/** end of DLI */ + +#endif /* __CSI_RX_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl.c new file mode 100644 index 0000000..14973d1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl.c @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <type_support.h> +#include "system_global.h" + +const uint32_t N_IBUF_CTRL_PROCS[N_IBUF_CTRL_ID] = { + 8, /* IBUF_CTRL0_ID supports at most 8 processes */ + 4, /* IBUF_CTRL1_ID supports at most 4 processes */ + 4 /* IBUF_CTRL2_ID supports at most 4 processes */ +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_local.h new file mode 100644 index 0000000..ea40284 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_local.h @@ -0,0 +1,58 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IBUF_CTRL_LOCAL_H_INCLUDED__ +#define __IBUF_CTRL_LOCAL_H_INCLUDED__ + +#include "ibuf_ctrl_global.h" + +typedef struct ibuf_ctrl_proc_state_s ibuf_ctrl_proc_state_t; +typedef struct ibuf_ctrl_state_s ibuf_ctrl_state_t; + +struct ibuf_ctrl_proc_state_s { + hrt_data num_items; + hrt_data num_stores; + hrt_data dma_channel; + hrt_data dma_command; + hrt_data ibuf_st_addr; + hrt_data ibuf_stride; + hrt_data ibuf_end_addr; + hrt_data dest_st_addr; + hrt_data dest_stride; + hrt_data dest_end_addr; + hrt_data sync_frame; + hrt_data sync_command; + hrt_data store_command; + hrt_data shift_returned_items; + hrt_data elems_ibuf; + hrt_data elems_dest; + hrt_data cur_stores; + hrt_data cur_acks; + hrt_data cur_s2m_ibuf_addr; + hrt_data cur_dma_ibuf_addr; + hrt_data cur_dma_dest_addr; + hrt_data cur_isp_dest_addr; + hrt_data dma_cmds_send; + hrt_data main_cntrl_state; + hrt_data dma_sync_state; + hrt_data isp_sync_state; +}; + +struct ibuf_ctrl_state_s { + hrt_data recalc_words; + hrt_data arbiters; + ibuf_ctrl_proc_state_t proc_state[N_STREAM2MMIO_SID_ID]; +}; + +#endif /* __IBUF_CTRL_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_private.h new file mode 100644 index 0000000..470c92d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_private.h @@ -0,0 +1,233 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IBUF_CTRL_PRIVATE_H_INCLUDED__ +#define __IBUF_CTRL_PRIVATE_H_INCLUDED__ + +#include "ibuf_ctrl_public.h" + +#include "device_access.h" /* ia_css_device_load_uint32 */ + +#include "assert_support.h" /* assert */ +#include "print_support.h" /* print */ + + +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the ibuf-controller state. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_get_state( + const ibuf_ctrl_ID_t ID, + ibuf_ctrl_state_t *state) +{ + uint32_t i; + + state->recalc_words = + ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_RECALC_WORDS_STATUS); + state->arbiters = + ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_ARBITERS_STATUS); + + /* + * Get the values of the register-set per + * ibuf-controller process. + */ + for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) { + ibuf_ctrl_get_proc_state( + ID, + i, + &(state->proc_state[i])); + } +} + +/** + * @brief Get the state of the ibuf-controller process. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_get_proc_state( + const ibuf_ctrl_ID_t ID, + const uint32_t proc_id, + ibuf_ctrl_proc_state_t *state) +{ + hrt_address reg_bank_offset; + + reg_bank_offset = + _IBUF_CNTRL_PROC_REG_ALIGN * (1 + proc_id); + + state->num_items = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_ITEMS_PER_STORE); + + state->num_stores = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_STORES_PER_FRAME); + + state->dma_channel = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CHANNEL); + + state->dma_command = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CMD); + + state->ibuf_st_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_START_ADDRESS); + + state->ibuf_stride = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_STRIDE); + + state->ibuf_end_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_END_ADDRESS); + + state->dest_st_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_START_ADDRESS); + + state->dest_stride = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_STRIDE); + + state->dest_end_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_END_ADDRESS); + + state->sync_frame = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SYNC_FRAME); + + state->sync_command = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_SYNC_CMD); + + state->store_command = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_STORE_CMD); + + state->shift_returned_items = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SHIFT_ITEMS); + + state->elems_ibuf = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_IBUF); + + state->elems_dest = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_DEST); + + state->cur_stores = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_STORES); + + state->cur_acks = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ACKS); + + state->cur_s2m_ibuf_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_S2M_IBUF_ADDR); + + state->cur_dma_ibuf_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_IBUF_ADDR); + + state->cur_dma_dest_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_DEST_ADDR); + + state->cur_isp_dest_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ISP_DEST_ADDR); + + state->dma_cmds_send = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_NR_DMA_CMDS_SEND); + + state->main_cntrl_state = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_MAIN_CNTRL_STATE); + + state->dma_sync_state = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_SYNC_STATE); + + state->isp_sync_state = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ISP_SYNC_STATE); +} +/** + * @brief Dump the ibuf-controller state. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_dump_state( + const ibuf_ctrl_ID_t ID, + ibuf_ctrl_state_t *state) +{ + uint32_t i; + ia_css_print("IBUF controller ID %d recalculate words 0x%x\n", ID, state->recalc_words); + ia_css_print("IBUF controller ID %d arbiters 0x%x\n", ID, state->arbiters); + + /* + * Dump the values of the register-set per + * ibuf-controller process. + */ + for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) { + ia_css_print("IBUF controller ID %d Process ID %d num_items 0x%x\n", ID, i, state->proc_state[i].num_items); + ia_css_print("IBUF controller ID %d Process ID %d num_stores 0x%x\n", ID, i, state->proc_state[i].num_stores); + ia_css_print("IBUF controller ID %d Process ID %d dma_channel 0x%x\n", ID, i, state->proc_state[i].dma_channel); + ia_css_print("IBUF controller ID %d Process ID %d dma_command 0x%x\n", ID, i, state->proc_state[i].dma_command); + ia_css_print("IBUF controller ID %d Process ID %d ibuf_st_addr 0x%x\n", ID, i, state->proc_state[i].ibuf_st_addr); + ia_css_print("IBUF controller ID %d Process ID %d ibuf_stride 0x%x\n", ID, i, state->proc_state[i].ibuf_stride); + ia_css_print("IBUF controller ID %d Process ID %d ibuf_end_addr 0x%x\n", ID, i, state->proc_state[i].ibuf_end_addr); + ia_css_print("IBUF controller ID %d Process ID %d dest_st_addr 0x%x\n", ID, i, state->proc_state[i].dest_st_addr); + ia_css_print("IBUF controller ID %d Process ID %d dest_stride 0x%x\n", ID, i, state->proc_state[i].dest_stride); + ia_css_print("IBUF controller ID %d Process ID %d dest_end_addr 0x%x\n", ID, i, state->proc_state[i].dest_end_addr); + ia_css_print("IBUF controller ID %d Process ID %d sync_frame 0x%x\n", ID, i, state->proc_state[i].sync_frame); + ia_css_print("IBUF controller ID %d Process ID %d sync_command 0x%x\n", ID, i, state->proc_state[i].sync_command); + ia_css_print("IBUF controller ID %d Process ID %d store_command 0x%x\n", ID, i, state->proc_state[i].store_command); + ia_css_print("IBUF controller ID %d Process ID %d shift_returned_items 0x%x\n", ID, i, state->proc_state[i].shift_returned_items); + ia_css_print("IBUF controller ID %d Process ID %d elems_ibuf 0x%x\n", ID, i, state->proc_state[i].elems_ibuf); + ia_css_print("IBUF controller ID %d Process ID %d elems_dest 0x%x\n", ID, i, state->proc_state[i].elems_dest); + ia_css_print("IBUF controller ID %d Process ID %d cur_stores 0x%x\n", ID, i, state->proc_state[i].cur_stores); + ia_css_print("IBUF controller ID %d Process ID %d cur_acks 0x%x\n", ID, i, state->proc_state[i].cur_acks); + ia_css_print("IBUF controller ID %d Process ID %d cur_s2m_ibuf_addr 0x%x\n", ID, i, state->proc_state[i].cur_s2m_ibuf_addr); + ia_css_print("IBUF controller ID %d Process ID %d cur_dma_ibuf_addr 0x%x\n", ID, i, state->proc_state[i].cur_dma_ibuf_addr); + ia_css_print("IBUF controller ID %d Process ID %d cur_dma_dest_addr 0x%x\n", ID, i, state->proc_state[i].cur_dma_dest_addr); + ia_css_print("IBUF controller ID %d Process ID %d cur_isp_dest_addr 0x%x\n", ID, i, state->proc_state[i].cur_isp_dest_addr); + ia_css_print("IBUF controller ID %d Process ID %d dma_cmds_send 0x%x\n", ID, i, state->proc_state[i].dma_cmds_send); + ia_css_print("IBUF controller ID %d Process ID %d main_cntrl_state 0x%x\n", ID, i, state->proc_state[i].main_cntrl_state); + ia_css_print("IBUF controller ID %d Process ID %d dma_sync_state 0x%x\n", ID, i, state->proc_state[i].dma_sync_state); + ia_css_print("IBUF controller ID %d Process ID %d isp_sync_state 0x%x\n", ID, i, state->proc_state[i].isp_sync_state); + } +} +/** end of NCI */ + +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_IBUF_CTRL_C hrt_data ibuf_ctrl_reg_load( + const ibuf_ctrl_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_IBUF_CTRL_ID); + assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg*sizeof(hrt_data)); +} + + +/** + * @brief Store a value to the register. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_reg_store( + const ibuf_ctrl_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_IBUF_CTRL_ID); + assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); +} +/** end of DLI */ + + +#endif /* __IBUF_CTRL_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/input_system_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/input_system_local.h new file mode 100644 index 0000000..f199423 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/input_system_local.h @@ -0,0 +1,106 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_LOCAL_H_INCLUDED__ +#define __INPUT_SYSTEM_LOCAL_H_INCLUDED__ + +#include "type_support.h" +#include "input_system_global.h" + +#include "ibuf_ctrl.h" +#include "csi_rx.h" +#include "pixelgen.h" +#include "isys_stream2mmio.h" +#include "isys_irq.h" + +typedef input_system_err_t input_system_error_t; + +typedef enum { + MIPI_FORMAT_SHORT1 = 0x08, + MIPI_FORMAT_SHORT2, + MIPI_FORMAT_SHORT3, + MIPI_FORMAT_SHORT4, + MIPI_FORMAT_SHORT5, + MIPI_FORMAT_SHORT6, + MIPI_FORMAT_SHORT7, + MIPI_FORMAT_SHORT8, + MIPI_FORMAT_EMBEDDED = 0x12, + MIPI_FORMAT_YUV420_8 = 0x18, + MIPI_FORMAT_YUV420_10, + MIPI_FORMAT_YUV420_8_LEGACY, + MIPI_FORMAT_YUV420_8_SHIFT = 0x1C, + MIPI_FORMAT_YUV420_10_SHIFT, + MIPI_FORMAT_YUV422_8 = 0x1E, + MIPI_FORMAT_YUV422_10, + MIPI_FORMAT_RGB444 = 0x20, + MIPI_FORMAT_RGB555, + MIPI_FORMAT_RGB565, + MIPI_FORMAT_RGB666, + MIPI_FORMAT_RGB888, + MIPI_FORMAT_RAW6 = 0x28, + MIPI_FORMAT_RAW7, + MIPI_FORMAT_RAW8, + MIPI_FORMAT_RAW10, + MIPI_FORMAT_RAW12, + MIPI_FORMAT_RAW14, + MIPI_FORMAT_CUSTOM0 = 0x30, + MIPI_FORMAT_CUSTOM1, + MIPI_FORMAT_CUSTOM2, + MIPI_FORMAT_CUSTOM3, + MIPI_FORMAT_CUSTOM4, + MIPI_FORMAT_CUSTOM5, + MIPI_FORMAT_CUSTOM6, + MIPI_FORMAT_CUSTOM7, + //MIPI_FORMAT_RAW16, /*not supported by 2401*/ + //MIPI_FORMAT_RAW18, + N_MIPI_FORMAT +} mipi_format_t; + +#define N_MIPI_FORMAT_CUSTOM 8 + +/* The number of stores for compressed format types */ +#define N_MIPI_COMPRESSOR_CONTEXT (N_RX_CHANNEL_ID * N_MIPI_FORMAT_CUSTOM) +#define UNCOMPRESSED_BITS_PER_PIXEL_10 10 +#define UNCOMPRESSED_BITS_PER_PIXEL_12 12 +#define COMPRESSED_BITS_PER_PIXEL_6 6 +#define COMPRESSED_BITS_PER_PIXEL_7 7 +#define COMPRESSED_BITS_PER_PIXEL_8 8 +enum mipi_compressor { + MIPI_COMPRESSOR_NONE = 0, + MIPI_COMPRESSOR_10_6_10, + MIPI_COMPRESSOR_10_7_10, + MIPI_COMPRESSOR_10_8_10, + MIPI_COMPRESSOR_12_6_12, + MIPI_COMPRESSOR_12_7_12, + MIPI_COMPRESSOR_12_8_12, + N_MIPI_COMPRESSOR_METHODS +}; + +typedef enum { + MIPI_PREDICTOR_NONE = 0, + MIPI_PREDICTOR_TYPE1, + MIPI_PREDICTOR_TYPE2, + N_MIPI_PREDICTOR_TYPES +} mipi_predictor_t; + +typedef struct input_system_state_s input_system_state_t; +struct input_system_state_s { + ibuf_ctrl_state_t ibuf_ctrl_state[N_IBUF_CTRL_ID]; + csi_rx_fe_ctrl_state_t csi_rx_fe_ctrl_state[N_CSI_RX_FRONTEND_ID]; + csi_rx_be_ctrl_state_t csi_rx_be_ctrl_state[N_CSI_RX_BACKEND_ID]; + pixelgen_ctrl_state_t pixelgen_ctrl_state[N_PIXELGEN_ID]; + stream2mmio_state_t stream2mmio_state[N_STREAM2MMIO_ID]; + isys_irqc_state_t isys_irqc_state[N_ISYS_IRQ_ID]; +}; +#endif /* __INPUT_SYSTEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/input_system_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/input_system_private.h new file mode 100644 index 0000000..97505e4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/input_system_private.h @@ -0,0 +1,128 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ +#define __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ + +#include "input_system_public.h" + +STORAGE_CLASS_INPUT_SYSTEM_C input_system_err_t input_system_get_state( + const input_system_ID_t ID, + input_system_state_t *state) +{ + uint32_t i; + + (void)(ID); + + /* get the states of all CSI RX frontend devices */ + for (i = 0; i < N_CSI_RX_FRONTEND_ID; i++) { + csi_rx_fe_ctrl_get_state( + (csi_rx_frontend_ID_t)i, + &(state->csi_rx_fe_ctrl_state[i])); + } + + /* get the states of all CIS RX backend devices */ + for (i = 0; i < N_CSI_RX_BACKEND_ID; i++) { + csi_rx_be_ctrl_get_state( + (csi_rx_backend_ID_t)i, + &(state->csi_rx_be_ctrl_state[i])); + } + + /* get the states of all pixelgen devices */ + for (i = 0; i < N_PIXELGEN_ID; i++) { + pixelgen_ctrl_get_state( + (pixelgen_ID_t)i, + &(state->pixelgen_ctrl_state[i])); + } + + /* get the states of all stream2mmio devices */ + for (i = 0; i < N_STREAM2MMIO_ID; i++) { + stream2mmio_get_state( + (stream2mmio_ID_t)i, + &(state->stream2mmio_state[i])); + } + + /* get the states of all ibuf-controller devices */ + for (i = 0; i < N_IBUF_CTRL_ID; i++) { + ibuf_ctrl_get_state( + (ibuf_ctrl_ID_t)i, + &(state->ibuf_ctrl_state[i])); + } + + /* get the states of all isys irq controllers */ + for (i = 0; i < N_ISYS_IRQ_ID; i++) { + isys_irqc_state_get((isys_irq_ID_t)i, &(state->isys_irqc_state[i])); + } + + /* TODO: get the states of all ISYS2401 DMA devices */ + for (i = 0; i < N_ISYS2401_DMA_ID; i++) { + } + + return INPUT_SYSTEM_ERR_NO_ERROR; +} +STORAGE_CLASS_INPUT_SYSTEM_C void input_system_dump_state( + const input_system_ID_t ID, + input_system_state_t *state) +{ + uint32_t i; + + (void)(ID); + + /* dump the states of all CSI RX frontend devices */ + for (i = 0; i < N_CSI_RX_FRONTEND_ID; i++) { + csi_rx_fe_ctrl_dump_state( + (csi_rx_frontend_ID_t)i, + &(state->csi_rx_fe_ctrl_state[i])); + } + + /* dump the states of all CIS RX backend devices */ + for (i = 0; i < N_CSI_RX_BACKEND_ID; i++) { + csi_rx_be_ctrl_dump_state( + (csi_rx_backend_ID_t)i, + &(state->csi_rx_be_ctrl_state[i])); + } + + /* dump the states of all pixelgen devices */ + for (i = 0; i < N_PIXELGEN_ID; i++) { + pixelgen_ctrl_dump_state( + (pixelgen_ID_t)i, + &(state->pixelgen_ctrl_state[i])); + } + + /* dump the states of all st2mmio devices */ + for (i = 0; i < N_STREAM2MMIO_ID; i++) { + stream2mmio_dump_state( + (stream2mmio_ID_t)i, + &(state->stream2mmio_state[i])); + } + + /* dump the states of all ibuf-controller devices */ + for (i = 0; i < N_IBUF_CTRL_ID; i++) { + ibuf_ctrl_dump_state( + (ibuf_ctrl_ID_t)i, + &(state->ibuf_ctrl_state[i])); + } + + /* dump the states of all isys irq controllers */ + for (i = 0; i < N_ISYS_IRQ_ID; i++) { + isys_irqc_state_dump((isys_irq_ID_t)i, &(state->isys_irqc_state[i])); + } + + /* TODO: dump the states of all ISYS2401 DMA devices */ + for (i = 0; i < N_ISYS2401_DMA_ID; i++) { + } + + return; +} +#endif /* __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma.c new file mode 100644 index 0000000..7776722 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma.c @@ -0,0 +1,40 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "isys_dma.h" +#include "assert_support.h" + +#ifndef __INLINE_ISYS2401_DMA__ +/* + * Include definitions for isys dma register access functions. isys_dma.h + * includes declarations of these functions by including isys_dma_public.h. + */ +#include "isys_dma_private.h" +#endif + +const isys2401_dma_channel N_ISYS2401_DMA_CHANNEL_PROCS[N_ISYS2401_DMA_ID] = { + N_ISYS2401_DMA_CHANNEL +}; + +void isys2401_dma_set_max_burst_size( + const isys2401_dma_ID_t dma_id, + uint32_t max_burst_size) +{ + assert(dma_id < N_ISYS2401_DMA_ID); + assert((max_burst_size > 0x00) && (max_burst_size <= 0xFF)); + + isys2401_dma_reg_store(dma_id, + DMA_DEV_INFO_REG_IDX(_DMA_V2_DEV_INTERF_MAX_BURST_IDX, HIVE_DMA_BUS_DDR_CONN), + (max_burst_size - 1)); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma_local.h new file mode 100644 index 0000000..5c694a2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma_local.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_DMA_LOCAL_H_INCLUDED__ +#define __ISYS_DMA_LOCAL_H_INCLUDED__ + +#include "isys_dma_global.h" + +#endif /* __ISYS_DMA_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma_private.h new file mode 100644 index 0000000..2cd1aee --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma_private.h @@ -0,0 +1,60 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_DMA_PRIVATE_H_INCLUDED__ +#define __ISYS_DMA_PRIVATE_H_INCLUDED__ + +#include "isys_dma_public.h" +#include "device_access.h" +#include "assert_support.h" +#include "dma.h" +#include "dma_v2_defs.h" +#include "print_support.h" + + +STORAGE_CLASS_ISYS2401_DMA_C void isys2401_dma_reg_store( + const isys2401_dma_ID_t dma_id, + const unsigned int reg, + const hrt_data value) +{ + unsigned int reg_loc; + + assert(dma_id < N_ISYS2401_DMA_ID); + assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address)-1); + + reg_loc = ISYS2401_DMA_BASE[dma_id] + (reg * sizeof(hrt_data)); + + ia_css_print("isys dma store at addr(0x%x) val(%u)\n", reg_loc, (unsigned int)value); + ia_css_device_store_uint32(reg_loc, value); +} + +STORAGE_CLASS_ISYS2401_DMA_C hrt_data isys2401_dma_reg_load( + const isys2401_dma_ID_t dma_id, + const unsigned int reg) +{ + unsigned int reg_loc; + hrt_data value; + + assert(dma_id < N_ISYS2401_DMA_ID); + assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address)-1); + + reg_loc = ISYS2401_DMA_BASE[dma_id] + (reg * sizeof(hrt_data)); + + value = ia_css_device_load_uint32(reg_loc); + ia_css_print("isys dma load from addr(0x%x) val(%u)\n", reg_loc, (unsigned int)value); + + return value; +} + +#endif /* __ISYS_DMA_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq.c new file mode 100644 index 0000000..14d1d3b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq.c @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <system_local.h> +#include "device_access.h" +#include "assert_support.h" +#include "ia_css_debug.h" +#include "isys_irq.h" + +#ifndef __INLINE_ISYS2401_IRQ__ +/* + * Include definitions for isys irq private functions. isys_irq.h includes + * declarations of these functions by including isys_irq_public.h. + */ +#include "isys_irq_private.h" +#endif + +/** Public interface */ +STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_status_enable( + const isys_irq_ID_t isys_irqc_id) +{ + assert(isys_irqc_id < N_ISYS_IRQ_ID); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Setting irq mask for port %u\n", isys_irqc_id); + isys_irqc_reg_store(isys_irqc_id, ISYS_IRQ_MASK_REG_IDX, ISYS_IRQ_MASK_REG_VALUE); + isys_irqc_reg_store(isys_irqc_id, ISYS_IRQ_CLEAR_REG_IDX, ISYS_IRQ_CLEAR_REG_VALUE); + isys_irqc_reg_store(isys_irqc_id, ISYS_IRQ_ENABLE_REG_IDX, ISYS_IRQ_ENABLE_REG_VALUE); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_local.h new file mode 100644 index 0000000..0bffb56 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_local.h @@ -0,0 +1,35 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_IRQ_LOCAL_H__ +#define __ISYS_IRQ_LOCAL_H__ + +#include <type_support.h> + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + +typedef struct isys_irqc_state_s isys_irqc_state_t; + +struct isys_irqc_state_s { + hrt_data edge; + hrt_data mask; + hrt_data status; + hrt_data enable; + hrt_data level_no; +/*hrt_data clear; */ /* write-only register */ +}; + +#endif /* defined(USE_INPUT_SYSTEM_VERSION_2401) */ + +#endif /* __ISYS_IRQ_LOCAL_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_private.h new file mode 100644 index 0000000..c17ce13 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_private.h @@ -0,0 +1,108 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_IRQ_PRIVATE_H__ +#define __ISYS_IRQ_PRIVATE_H__ + +#include "isys_irq_global.h" +#include "isys_irq_local.h" + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + +/* -------------------------------------------------------+ + | Native command interface (NCI) | + + -------------------------------------------------------*/ + +/** +* @brief Get the isys irq status. +* Refer to "isys_irq.h" for details. +*/ +STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_state_get( + const isys_irq_ID_t isys_irqc_id, + isys_irqc_state_t *state) +{ + state->edge = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_EDGE_REG_IDX); + state->mask = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_MASK_REG_IDX); + state->status = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_STATUS_REG_IDX); + state->enable = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_ENABLE_REG_IDX); + state->level_no = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_LEVEL_NO_REG_IDX); + /* + ** Invalid to read/load from write-only register 'clear' + ** state->clear = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_CLEAR_REG_IDX); + */ +} + +/** +* @brief Dump the isys irq status. +* Refer to "isys_irq.h" for details. +*/ +STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_state_dump( + const isys_irq_ID_t isys_irqc_id, + const isys_irqc_state_t *state) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "isys irq controller id %d" + "\n\tstatus:0x%x\n\tedge:0x%x\n\tmask:0x%x" + "\n\tenable:0x%x\n\tlevel_not_pulse:0x%x\n", + isys_irqc_id, + state->status, state->edge, state->mask, state->enable, state->level_no); +} + +/** end of NCI */ + +/* -------------------------------------------------------+ + | Device level interface (DLI) | + + -------------------------------------------------------*/ + +/* Support functions */ +STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_reg_store( + const isys_irq_ID_t isys_irqc_id, + const unsigned int reg_idx, + const hrt_data value) +{ + unsigned int reg_addr; + + assert(isys_irqc_id < N_ISYS_IRQ_ID); + assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX); + + reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "isys irq store at addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value); + + ia_css_device_store_uint32(reg_addr, value); +} + +STORAGE_CLASS_ISYS2401_IRQ_C hrt_data isys_irqc_reg_load( + const isys_irq_ID_t isys_irqc_id, + const unsigned int reg_idx) +{ + unsigned int reg_addr; + hrt_data value; + + assert(isys_irqc_id < N_ISYS_IRQ_ID); + assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX); + + reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); + value = ia_css_device_load_uint32(reg_addr); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "isys irq load from addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value); + + return value; +} + +/** end of DLI */ + +#endif /* defined(USE_INPUT_SYSTEM_VERSION_2401) */ + +#endif /* __ISYS_IRQ_PRIVATE_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio.c new file mode 100644 index 0000000..6757013 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio.c @@ -0,0 +1,21 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "isys_stream2mmio.h" + +const stream2mmio_sid_ID_t N_STREAM2MMIO_SID_PROCS[N_STREAM2MMIO_ID] = { + N_STREAM2MMIO_SID_ID, + STREAM2MMIO_SID4_ID, + STREAM2MMIO_SID4_ID +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_local.h new file mode 100644 index 0000000..8015239 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_local.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_STREAM2MMIO_LOCAL_H_INCLUDED__ +#define __ISYS_STREAM2MMIO_LOCAL_H_INCLUDED__ + +#include "isys_stream2mmio_global.h" + +typedef struct stream2mmio_state_s stream2mmio_state_t; +typedef struct stream2mmio_sid_state_s stream2mmio_sid_state_t; + +struct stream2mmio_sid_state_s { + hrt_data rcv_ack; + hrt_data pix_width_id; + hrt_data start_addr; + hrt_data end_addr; + hrt_data strides; + hrt_data num_items; + hrt_data block_when_no_cmd; +}; + +struct stream2mmio_state_s { + stream2mmio_sid_state_t sid_state[N_STREAM2MMIO_SID_ID]; +}; +#endif /* __ISYS_STREAM2MMIO_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_private.h new file mode 100644 index 0000000..1603a09 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_private.h @@ -0,0 +1,168 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ +#define __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ + +#include "isys_stream2mmio_public.h" +#include "device_access.h" /* ia_css_device_load_uint32 */ +#include "assert_support.h" /* assert */ +#include "print_support.h" /* print */ + +#define STREAM2MMIO_COMMAND_REG_ID 0 +#define STREAM2MMIO_ACKNOWLEDGE_REG_ID 1 +#define STREAM2MMIO_PIX_WIDTH_ID_REG_ID 2 +#define STREAM2MMIO_START_ADDR_REG_ID 3 /* master port address,NOT Byte */ +#define STREAM2MMIO_END_ADDR_REG_ID 4 /* master port address,NOT Byte */ +#define STREAM2MMIO_STRIDE_REG_ID 5 /* stride in master port words, increment is per packet for long sids, stride is not used for short sid's*/ +#define STREAM2MMIO_NUM_ITEMS_REG_ID 6 /* number of packets for store packets cmd, number of words for store_words cmd */ +#define STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID 7 /* if this register is 1, input will be stalled if there is no pending command for this sid */ +#define STREAM2MMIO_REGS_PER_SID 8 + +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the stream2mmio-controller state. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_state( + const stream2mmio_ID_t ID, + stream2mmio_state_t *state) +{ + stream2mmio_sid_ID_t i; + + /* + * Get the values of the register-set per + * stream2mmio-controller sids. + */ + for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) { + stream2mmio_get_sid_state(ID, i, &(state->sid_state[i])); + } +} + +/** + * @brief Get the state of the stream2mmio-controller sidess. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_sid_state( + const stream2mmio_ID_t ID, + const stream2mmio_sid_ID_t sid_id, + stream2mmio_sid_state_t *state) +{ + + state->rcv_ack = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_ACKNOWLEDGE_REG_ID); + + state->pix_width_id = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_PIX_WIDTH_ID_REG_ID); + + state->start_addr = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_START_ADDR_REG_ID); + + state->end_addr = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_END_ADDR_REG_ID); + + state->strides = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_STRIDE_REG_ID); + + state->num_items = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_NUM_ITEMS_REG_ID); + + state->block_when_no_cmd = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID); + +} + +/** + * @brief Dump the state of the stream2mmio-controller sidess. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_print_sid_state( + stream2mmio_sid_state_t *state) +{ + ia_css_print("\t \t Receive acks 0x%x\n", state->rcv_ack); + ia_css_print("\t \t Pixel width 0x%x\n", state->pix_width_id); + ia_css_print("\t \t Startaddr 0x%x\n", state->start_addr); + ia_css_print("\t \t Endaddr 0x%x\n", state->end_addr); + ia_css_print("\t \t Strides 0x%x\n", state->strides); + ia_css_print("\t \t Num Items 0x%x\n", state->num_items); + ia_css_print("\t \t block when no cmd 0x%x\n", state->block_when_no_cmd); + +} +/** + * @brief Dump the ibuf-controller state. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_dump_state( + const stream2mmio_ID_t ID, + stream2mmio_state_t *state) +{ + stream2mmio_sid_ID_t i; + + /* + * Get the values of the register-set per + * stream2mmio-controller sids. + */ + for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) { + ia_css_print("StREAM2MMIO ID %d SID %d\n", ID, i); + stream2mmio_print_sid_state(&(state->sid_state[i])); + } +} +/** end of NCI */ + +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C hrt_data stream2mmio_reg_load( + const stream2mmio_ID_t ID, + const stream2mmio_sid_ID_t sid_id, + const uint32_t reg_idx) +{ + uint32_t reg_bank_offset; + + assert(ID < N_STREAM2MMIO_ID); + + reg_bank_offset = STREAM2MMIO_REGS_PER_SID * sid_id; + return ia_css_device_load_uint32(STREAM2MMIO_CTRL_BASE[ID] + + (reg_bank_offset + reg_idx) * sizeof(hrt_data)); +} + + +/** + * @brief Store a value to the register. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_reg_store( + const stream2mmio_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_STREAM2MMIO_ID); + assert(STREAM2MMIO_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(STREAM2MMIO_CTRL_BASE[ID] + + reg * sizeof(hrt_data), value); +} +/** end of DLI */ + +#endif /* __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_local.h new file mode 100644 index 0000000..24f4da9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_local.h @@ -0,0 +1,50 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PIXELGEN_LOCAL_H_INCLUDED__ +#define __PIXELGEN_LOCAL_H_INCLUDED__ + +#include "pixelgen_global.h" + +typedef struct pixelgen_ctrl_state_s pixelgen_ctrl_state_t; +struct pixelgen_ctrl_state_s { + hrt_data com_enable; + hrt_data prbs_rstval0; + hrt_data prbs_rstval1; + hrt_data syng_sid; + hrt_data syng_free_run; + hrt_data syng_pause; + hrt_data syng_nof_frames; + hrt_data syng_nof_pixels; + hrt_data syng_nof_line; + hrt_data syng_hblank_cyc; + hrt_data syng_vblank_cyc; + hrt_data syng_stat_hcnt; + hrt_data syng_stat_vcnt; + hrt_data syng_stat_fcnt; + hrt_data syng_stat_done; + hrt_data tpg_mode; + hrt_data tpg_hcnt_mask; + hrt_data tpg_vcnt_mask; + hrt_data tpg_xycnt_mask; + hrt_data tpg_hcnt_delta; + hrt_data tpg_vcnt_delta; + hrt_data tpg_r1; + hrt_data tpg_g1; + hrt_data tpg_b1; + hrt_data tpg_r2; + hrt_data tpg_g2; + hrt_data tpg_b2; +}; +#endif /* __PIXELGEN_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_private.h new file mode 100644 index 0000000..3f34b50 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_private.h @@ -0,0 +1,164 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PIXELGEN_PRIVATE_H_INCLUDED__ +#define __PIXELGEN_PRIVATE_H_INCLUDED__ +#include "pixelgen_public.h" +#include "hive_isp_css_host_ids_hrt.h" +#include "PixelGen_SysBlock_defs.h" +#include "device_access.h" /* ia_css_device_load_uint32 */ +#include "assert_support.h" /* assert */ + + +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the pixelgen state. + * Refer to "pixelgen_public.h" for details. + */ +STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_get_state( + const pixelgen_ID_t ID, + pixelgen_ctrl_state_t *state) +{ + + state->com_enable = + pixelgen_ctrl_reg_load(ID, _PXG_COM_ENABLE_REG_IDX); + state->prbs_rstval0 = + pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG0_IDX); + state->prbs_rstval1 = + pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG1_IDX); + state->syng_sid = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_SID_REG_IDX); + state->syng_free_run = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_FREE_RUN_REG_IDX); + state->syng_pause = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_PAUSE_REG_IDX); + state->syng_nof_frames = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_FRAME_REG_IDX); + state->syng_nof_pixels = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_PIXEL_REG_IDX); + state->syng_nof_line = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_LINE_REG_IDX); + state->syng_hblank_cyc = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_HBLANK_CYC_REG_IDX); + state->syng_vblank_cyc = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_VBLANK_CYC_REG_IDX); + state->syng_stat_hcnt = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_HCNT_REG_IDX); + state->syng_stat_vcnt = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_VCNT_REG_IDX); + state->syng_stat_fcnt = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_FCNT_REG_IDX); + state->syng_stat_done = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_DONE_REG_IDX); + state->tpg_mode = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_MODE_REG_IDX); + state->tpg_hcnt_mask = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_MASK_REG_IDX); + state->tpg_vcnt_mask = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_MASK_REG_IDX); + state->tpg_xycnt_mask = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_XYCNT_MASK_REG_IDX); + state->tpg_hcnt_delta = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_DELTA_REG_IDX); + state->tpg_vcnt_delta = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_DELTA_REG_IDX); + state->tpg_r1 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_R1_REG_IDX); + state->tpg_g1 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_G1_REG_IDX); + state->tpg_b1 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_B1_REG_IDX); + state->tpg_r2 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_R2_REG_IDX); + state->tpg_g2 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_G2_REG_IDX); + state->tpg_b2 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_B2_REG_IDX); +} +/** + * @brief Dump the pixelgen state. + * Refer to "pixelgen_public.h" for details. + */ +STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_dump_state( + const pixelgen_ID_t ID, + pixelgen_ctrl_state_t *state) +{ + ia_css_print("Pixel Generator ID %d Enable 0x%x \n", ID, state->com_enable); + ia_css_print("Pixel Generator ID %d PRBS reset vlue 0 0x%x \n", ID, state->prbs_rstval0); + ia_css_print("Pixel Generator ID %d PRBS reset vlue 1 0x%x \n", ID, state->prbs_rstval1); + ia_css_print("Pixel Generator ID %d SYNC SID 0x%x \n", ID, state->syng_sid); + ia_css_print("Pixel Generator ID %d syng free run 0x%x \n", ID, state->syng_free_run); + ia_css_print("Pixel Generator ID %d syng pause 0x%x \n", ID, state->syng_pause); + ia_css_print("Pixel Generator ID %d syng no of frames 0x%x \n", ID, state->syng_nof_frames); + ia_css_print("Pixel Generator ID %d syng no of pixels 0x%x \n", ID, state->syng_nof_pixels); + ia_css_print("Pixel Generator ID %d syng no of line 0x%x \n", ID, state->syng_nof_line); + ia_css_print("Pixel Generator ID %d syng hblank cyc 0x%x \n", ID, state->syng_hblank_cyc); + ia_css_print("Pixel Generator ID %d syng vblank cyc 0x%x \n", ID, state->syng_vblank_cyc); + ia_css_print("Pixel Generator ID %d syng stat hcnt 0x%x \n", ID, state->syng_stat_hcnt); + ia_css_print("Pixel Generator ID %d syng stat vcnt 0x%x \n", ID, state->syng_stat_vcnt); + ia_css_print("Pixel Generator ID %d syng stat fcnt 0x%x \n", ID, state->syng_stat_fcnt); + ia_css_print("Pixel Generator ID %d syng stat done 0x%x \n", ID, state->syng_stat_done); + ia_css_print("Pixel Generator ID %d tpg modee 0x%x \n", ID, state->tpg_mode); + ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x \n", ID, state->tpg_hcnt_mask); + ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x \n", ID, state->tpg_hcnt_mask); + ia_css_print("Pixel Generator ID %d tpg xycnt mask 0x%x \n", ID, state->tpg_xycnt_mask); + ia_css_print("Pixel Generator ID %d tpg hcnt delta 0x%x \n", ID, state->tpg_hcnt_delta); + ia_css_print("Pixel Generator ID %d tpg vcnt delta 0x%x \n", ID, state->tpg_vcnt_delta); + ia_css_print("Pixel Generator ID %d tpg r1 0x%x \n", ID, state->tpg_r1); + ia_css_print("Pixel Generator ID %d tpg g1 0x%x \n", ID, state->tpg_g1); + ia_css_print("Pixel Generator ID %d tpg b1 0x%x \n", ID, state->tpg_b1); + ia_css_print("Pixel Generator ID %d tpg r2 0x%x \n", ID, state->tpg_r2); + ia_css_print("Pixel Generator ID %d tpg g2 0x%x \n", ID, state->tpg_g2); + ia_css_print("Pixel Generator ID %d tpg b2 0x%x \n", ID, state->tpg_b2); +} +/* end of NCI */ +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Refer to "pixelgen_public.h" for details. + */ +STORAGE_CLASS_PIXELGEN_C hrt_data pixelgen_ctrl_reg_load( + const pixelgen_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_PIXELGEN_ID); + assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg*sizeof(hrt_data)); +} + + +/** + * @brief Store a value to the register. + * Refer to "pixelgen_ctrl_public.h" for details. + */ +STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_reg_store( + const pixelgen_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_PIXELGEN_ID); + assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); +} +/** end of DLI */ +#endif /* __PIXELGEN_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/system_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/system_local.h new file mode 100644 index 0000000..c166709 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/system_local.h @@ -0,0 +1,381 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SYSTEM_LOCAL_H_INCLUDED__ +#define __SYSTEM_LOCAL_H_INCLUDED__ + +#ifdef HRT_ISP_CSS_CUSTOM_HOST +#ifndef HRT_USE_VIR_ADDRS +#define HRT_USE_VIR_ADDRS +#endif +/* This interface is deprecated */ +/*#include "hive_isp_css_custom_host_hrt.h"*/ +#endif + +#include "system_global.h" + +#ifdef __FIST__ +#define HRT_ADDRESS_WIDTH 32 /* Surprise, this is a local property and even differs per platform */ +#else +#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */ +#endif + +#if !defined(__KERNEL__) || (1 == 1) +/* This interface is deprecated */ +#include "hrt/hive_types.h" +#else /* __KERNEL__ */ +#include <type_support.h> + +#if HRT_ADDRESS_WIDTH == 64 +typedef uint64_t hrt_address; +#elif HRT_ADDRESS_WIDTH == 32 +typedef uint32_t hrt_address; +#else +#error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}" +#endif + +typedef uint32_t hrt_vaddress; +typedef uint32_t hrt_data; +#endif /* __KERNEL__ */ + +/* + * Cell specific address maps + */ +#if HRT_ADDRESS_WIDTH == 64 + +#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */ + +/* DDR */ +static const hrt_address DDR_BASE[N_DDR_ID] = { + 0x0000000120000000ULL}; + +/* ISP */ +static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = { + 0x0000000000020000ULL}; + +static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = { + 0x0000000000200000ULL}; + +static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = { + 0x0000000000100000ULL}; + +static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = { + 0x00000000001C0000ULL, + 0x00000000001D0000ULL, + 0x00000000001E0000ULL}; + +static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = { + 0x00000000001F0000ULL}; + +/* SP */ +static const hrt_address SP_CTRL_BASE[N_SP_ID] = { + 0x0000000000010000ULL}; + +static const hrt_address SP_DMEM_BASE[N_SP_ID] = { + 0x0000000000300000ULL}; + +/* MMU */ +#if defined(IS_ISP_2400_MAMOIADA_SYSTEM) || defined(IS_ISP_2401_MAMOIADA_SYSTEM) +/* + * MMU0_ID: The data MMU + * MMU1_ID: The icache MMU + */ +static const hrt_address MMU_BASE[N_MMU_ID] = { + 0x0000000000070000ULL, + 0x00000000000A0000ULL}; +#else +#error "system_local.h: SYSTEM must be one of {2400, 2401 }" +#endif + +/* DMA */ +static const hrt_address DMA_BASE[N_DMA_ID] = { + 0x0000000000040000ULL}; + +static const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = { + 0x00000000000CA000ULL}; + +/* IRQ */ +static const hrt_address IRQ_BASE[N_IRQ_ID] = { + 0x0000000000000500ULL, + 0x0000000000030A00ULL, + 0x000000000008C000ULL, + 0x0000000000090200ULL}; +/* + 0x0000000000000500ULL}; + */ + +/* GDC */ +static const hrt_address GDC_BASE[N_GDC_ID] = { + 0x0000000000050000ULL, + 0x0000000000060000ULL}; + +/* FIFO_MONITOR (not a subset of GP_DEVICE) */ +static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = { + 0x0000000000000000ULL}; + +/* +static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = { + 0x0000000000000000ULL}; + +static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + 0x0000000000090000ULL}; +*/ + +/* GP_DEVICE (single base for all separate GP_REG instances) */ +static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + 0x0000000000000000ULL}; + +/*GP TIMER , all timer registers are inter-twined, + * so, having multiple base addresses for + * different timers does not help*/ +static const hrt_address GP_TIMER_BASE = + (hrt_address)0x0000000000000600ULL; + +/* GPIO */ +static const hrt_address GPIO_BASE[N_GPIO_ID] = { + 0x0000000000000400ULL}; + +/* TIMED_CTRL */ +static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = { + 0x0000000000000100ULL}; + + +/* INPUT_FORMATTER */ +static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = { + 0x0000000000030000ULL, + 0x0000000000030200ULL, + 0x0000000000030400ULL, + 0x0000000000030600ULL}; /* memcpy() */ + +/* INPUT_SYSTEM */ +static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = { + 0x0000000000080000ULL}; +/* 0x0000000000081000ULL, */ /* capture A */ +/* 0x0000000000082000ULL, */ /* capture B */ +/* 0x0000000000083000ULL, */ /* capture C */ +/* 0x0000000000084000ULL, */ /* Acquisition */ +/* 0x0000000000085000ULL, */ /* DMA */ +/* 0x0000000000089000ULL, */ /* ctrl */ +/* 0x000000000008A000ULL, */ /* GP regs */ +/* 0x000000000008B000ULL, */ /* FIFO */ +/* 0x000000000008C000ULL, */ /* IRQ */ + +/* RX, the MIPI lane control regs start at offset 0 */ +static const hrt_address RX_BASE[N_RX_ID] = { + 0x0000000000080100ULL}; + +/* IBUF_CTRL, part of the Input System 2401 */ +static const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = { + 0x00000000000C1800ULL, /* ibuf controller A */ + 0x00000000000C3800ULL, /* ibuf controller B */ + 0x00000000000C5800ULL /* ibuf controller C */ +}; + +/* ISYS IRQ Controllers, part of the Input System 2401 */ +static const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = { + 0x00000000000C1400ULL, /* port a */ + 0x00000000000C3400ULL, /* port b */ + 0x00000000000C5400ULL /* port c */ +}; + +/* CSI FE, part of the Input System 2401 */ +static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = { + 0x00000000000C0400ULL, /* csi fe controller A */ + 0x00000000000C2400ULL, /* csi fe controller B */ + 0x00000000000C4400ULL /* csi fe controller C */ +}; +/* CSI BE, part of the Input System 2401 */ +static const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = { + 0x00000000000C0800ULL, /* csi be controller A */ + 0x00000000000C2800ULL, /* csi be controller B */ + 0x00000000000C4800ULL /* csi be controller C */ +}; +/* PIXEL Generator, part of the Input System 2401 */ +static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = { + 0x00000000000C1000ULL, /* pixel gen controller A */ + 0x00000000000C3000ULL, /* pixel gen controller B */ + 0x00000000000C5000ULL /* pixel gen controller C */ +}; +/* Stream2MMIO, part of the Input System 2401 */ +static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = { + 0x00000000000C0C00ULL, /* stream2mmio controller A */ + 0x00000000000C2C00ULL, /* stream2mmio controller B */ + 0x00000000000C4C00ULL /* stream2mmio controller C */ +}; +#elif HRT_ADDRESS_WIDTH == 32 + +#define GP_FIFO_BASE ((hrt_address)0x00090104) /* This is NOT a base address */ + +/* DDR : Attention, this value not defined in 32-bit */ +static const hrt_address DDR_BASE[N_DDR_ID] = { + 0x00000000UL}; + +/* ISP */ +static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = { + 0x00020000UL}; + +static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = { + 0xffffffffUL}; + +static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = { + 0xffffffffUL}; + +static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = { + 0xffffffffUL, + 0xffffffffUL, + 0xffffffffUL}; + +static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = { + 0xffffffffUL}; + +/* SP */ +static const hrt_address SP_CTRL_BASE[N_SP_ID] = { + 0x00010000UL}; + +static const hrt_address SP_DMEM_BASE[N_SP_ID] = { + 0x00300000UL}; + +/* MMU */ +#if defined(IS_ISP_2400_MAMOIADA_SYSTEM) || defined(IS_ISP_2401_MAMOIADA_SYSTEM) +/* + * MMU0_ID: The data MMU + * MMU1_ID: The icache MMU + */ +static const hrt_address MMU_BASE[N_MMU_ID] = { + 0x00070000UL, + 0x000A0000UL}; +#else +#error "system_local.h: SYSTEM must be one of {2400, 2401 }" +#endif + +/* DMA */ +static const hrt_address DMA_BASE[N_DMA_ID] = { + 0x00040000UL}; + +static const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = { + 0x000CA000UL}; + +/* IRQ */ +static const hrt_address IRQ_BASE[N_IRQ_ID] = { + 0x00000500UL, + 0x00030A00UL, + 0x0008C000UL, + 0x00090200UL}; +/* + 0x00000500UL}; + */ + +/* GDC */ +static const hrt_address GDC_BASE[N_GDC_ID] = { + 0x00050000UL, + 0x00060000UL}; + +/* FIFO_MONITOR (not a subset of GP_DEVICE) */ +static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = { + 0x00000000UL}; + +/* +static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = { + 0x00000000UL}; + +static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + 0x00090000UL}; +*/ + +/* GP_DEVICE (single base for all separate GP_REG instances) */ +static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + 0x00000000UL}; + +/*GP TIMER , all timer registers are inter-twined, + * so, having multiple base addresses for + * different timers does not help*/ +static const hrt_address GP_TIMER_BASE = + (hrt_address)0x00000600UL; +/* GPIO */ +static const hrt_address GPIO_BASE[N_GPIO_ID] = { + 0x00000400UL}; + +/* TIMED_CTRL */ +static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = { + 0x00000100UL}; + + +/* INPUT_FORMATTER */ +static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = { + 0x00030000UL, + 0x00030200UL, + 0x00030400UL}; +/* 0x00030600UL, */ /* memcpy() */ + +/* INPUT_SYSTEM */ +static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = { + 0x00080000UL}; +/* 0x00081000UL, */ /* capture A */ +/* 0x00082000UL, */ /* capture B */ +/* 0x00083000UL, */ /* capture C */ +/* 0x00084000UL, */ /* Acquisition */ +/* 0x00085000UL, */ /* DMA */ +/* 0x00089000UL, */ /* ctrl */ +/* 0x0008A000UL, */ /* GP regs */ +/* 0x0008B000UL, */ /* FIFO */ +/* 0x0008C000UL, */ /* IRQ */ + +/* RX, the MIPI lane control regs start at offset 0 */ +static const hrt_address RX_BASE[N_RX_ID] = { + 0x00080100UL}; + +/* IBUF_CTRL, part of the Input System 2401 */ +static const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = { + 0x000C1800UL, /* ibuf controller A */ + 0x000C3800UL, /* ibuf controller B */ + 0x000C5800UL /* ibuf controller C */ +}; + +/* ISYS IRQ Controllers, part of the Input System 2401 */ +static const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = { + 0x000C1400ULL, /* port a */ + 0x000C3400ULL, /* port b */ + 0x000C5400ULL /* port c */ +}; + +/* CSI FE, part of the Input System 2401 */ +static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = { + 0x000C0400UL, /* csi fe controller A */ + 0x000C2400UL, /* csi fe controller B */ + 0x000C4400UL /* csi fe controller C */ +}; +/* CSI BE, part of the Input System 2401 */ +static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = { + 0x000C0800UL, /* csi be controller A */ + 0x000C2800UL, /* csi be controller B */ + 0x000C4800UL /* csi be controller C */ +}; +/* PIXEL Generator, part of the Input System 2401 */ +static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = { + 0x000C1000UL, /* pixel gen controller A */ + 0x000C3000UL, /* pixel gen controller B */ + 0x000C5000UL /* pixel gen controller C */ +}; +/* Stream2MMIO, part of the Input System 2401 */ +static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = { + 0x000C0C00UL, /* stream2mmio controller A */ + 0x000C2C00UL, /* stream2mmio controller B */ + 0x000C4C00UL /* stream2mmio controller C */ +}; + +#else +#error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}" +#endif + +#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/PixelGen_SysBlock_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/PixelGen_SysBlock_defs.h new file mode 100644 index 0000000..1b3391c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/PixelGen_SysBlock_defs.h @@ -0,0 +1,126 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _PixelGen_SysBlock_defs_h +#define _PixelGen_SysBlock_defs_h + +#ifdef ISYS2401_PXG_A +#else +#ifdef ISYS2401_PXG_B +#else +#ifdef ISYS2401_PXG_C +#else +#include <mipi_backend/hrt/include/mipi_backend_defs.h> +#endif +#endif +#endif + +/* Parematers and User_Parameters for HSS */ +#define _PXG_PPC Ppc +#define _PXG_PIXEL_BITS PixelWidth +#define _PXG_MAX_NOF_SID MaxNofSids +#define _PXG_DATA_BITS DataWidth +#define _PXG_CNT_BITS CntWidth +#define _PXG_FIFODEPTH FifoDepth +#define _PXG_DBG Dbg_device_not_included + +/* ID's and Address */ +#define _PXG_ADRRESS_ALIGN_REG 4 + +#define _PXG_COM_ENABLE_REG_IDX 0 +#define _PXG_PRBS_RSTVAL_REG0_IDX 1 +#define _PXG_PRBS_RSTVAL_REG1_IDX 2 +#define _PXG_SYNG_SID_REG_IDX 3 +#define _PXG_SYNG_FREE_RUN_REG_IDX 4 +#define _PXG_SYNG_PAUSE_REG_IDX 5 +#define _PXG_SYNG_NOF_FRAME_REG_IDX 6 +#define _PXG_SYNG_NOF_PIXEL_REG_IDX 7 +#define _PXG_SYNG_NOF_LINE_REG_IDX 8 +#define _PXG_SYNG_HBLANK_CYC_REG_IDX 9 +#define _PXG_SYNG_VBLANK_CYC_REG_IDX 10 +#define _PXG_SYNG_STAT_HCNT_REG_IDX 11 +#define _PXG_SYNG_STAT_VCNT_REG_IDX 12 +#define _PXG_SYNG_STAT_FCNT_REG_IDX 13 +#define _PXG_SYNG_STAT_DONE_REG_IDX 14 +#define _PXG_TPG_MODE_REG_IDX 15 +#define _PXG_TPG_HCNT_MASK_REG_IDX 16 +#define _PXG_TPG_VCNT_MASK_REG_IDX 17 +#define _PXG_TPG_XYCNT_MASK_REG_IDX 18 +#define _PXG_TPG_HCNT_DELTA_REG_IDX 19 +#define _PXG_TPG_VCNT_DELTA_REG_IDX 20 +#define _PXG_TPG_R1_REG_IDX 21 +#define _PXG_TPG_G1_REG_IDX 22 +#define _PXG_TPG_B1_REG_IDX 23 +#define _PXG_TPG_R2_REG_IDX 24 +#define _PXG_TPG_G2_REG_IDX 25 +#define _PXG_TPG_B2_REG_IDX 26 +/* */ +#define _PXG_SYNG_PAUSE_CYCLES 0 +/* Subblock ID's */ +#define _PXG_DISBALE_IDX 0 +#define _PXG_PRBS_IDX 0 +#define _PXG_TPG_IDX 1 +#define _PXG_SYNG_IDX 2 +#define _PXG_SMUX_IDX 3 +/* Register Widths */ +#define _PXG_COM_ENABLE_REG_WIDTH 2 +#define _PXG_COM_SRST_REG_WIDTH 4 +#define _PXG_PRBS_RSTVAL_REG0_WIDTH 31 +#define _PXG_PRBS_RSTVAL_REG1_WIDTH 31 + +#define _PXG_SYNG_SID_REG_WIDTH 3 + +#define _PXG_SYNG_FREE_RUN_REG_WIDTH 1 +#define _PXG_SYNG_PAUSE_REG_WIDTH 1 +/* +#define _PXG_SYNG_NOF_FRAME_REG_WIDTH <sync_gen_cnt_width> +#define _PXG_SYNG_NOF_PIXEL_REG_WIDTH <sync_gen_cnt_width> +#define _PXG_SYNG_NOF_LINE_REG_WIDTH <sync_gen_cnt_width> +#define _PXG_SYNG_HBLANK_CYC_REG_WIDTH <sync_gen_cnt_width> +#define _PXG_SYNG_VBLANK_CYC_REG_WIDTH <sync_gen_cnt_width> +#define _PXG_SYNG_STAT_HCNT_REG_WIDTH <sync_gen_cnt_width> +#define _PXG_SYNG_STAT_VCNT_REG_WIDTH <sync_gen_cnt_width> +#define _PXG_SYNG_STAT_FCNT_REG_WIDTH <sync_gen_cnt_width> +*/ +#define _PXG_SYNG_STAT_DONE_REG_WIDTH 1 +#define _PXG_TPG_MODE_REG_WIDTH 2 +/* +#define _PXG_TPG_HCNT_MASK_REG_WIDTH <sync_gen_cnt_width> +#define _PXG_TPG_VCNT_MASK_REG_WIDTH <sync_gen_cnt_width> +#define _PXG_TPG_XYCNT_MASK_REG_WIDTH <pixle_width> +*/ +#define _PXG_TPG_HCNT_DELTA_REG_WIDTH 4 +#define _PXG_TPG_VCNT_DELTA_REG_WIDTH 4 +/* +#define _PXG_TPG_R1_REG_WIDTH <pixle_width> +#define _PXG_TPG_G1_REG_WIDTH <pixle_width> +#define _PXG_TPG_B1_REG_WIDTH <pixle_width> +#define _PXG_TPG_R2_REG_WIDTH <pixle_width> +#define _PXG_TPG_G2_REG_WIDTH <pixle_width> +#define _PXG_TPG_B2_REG_WIDTH <pixle_width> +*/ +#define _PXG_FIFO_DEPTH 2 +/* MISC */ +#define _PXG_ENABLE_REG_VAL 1 +#define _PXG_PRBS_ENABLE_REG_VAL 1 +#define _PXG_TPG_ENABLE_REG_VAL 2 +#define _PXG_SYNG_ENABLE_REG_VAL 4 +#define _PXG_FIFO_ENABLE_REG_VAL 8 +#define _PXG_PXL_BITS 14 +#define _PXG_INVALID_FLAG 0xDEADBEEF +#define _PXG_CAFE_FLAG 0xCAFEBABE + + +#endif /* _PixelGen_SysBlock_defs_h */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/bits.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/bits.h new file mode 100644 index 0000000..e71e33d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/bits.h @@ -0,0 +1,104 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_BITS_H +#define _HRT_BITS_H + +#include "defs.h" + +#define _hrt_ones(n) HRTCAT(_hrt_ones_, n) +#define _hrt_ones_0x0 0x00000000U +#define _hrt_ones_0x1 0x00000001U +#define _hrt_ones_0x2 0x00000003U +#define _hrt_ones_0x3 0x00000007U +#define _hrt_ones_0x4 0x0000000FU +#define _hrt_ones_0x5 0x0000001FU +#define _hrt_ones_0x6 0x0000003FU +#define _hrt_ones_0x7 0x0000007FU +#define _hrt_ones_0x8 0x000000FFU +#define _hrt_ones_0x9 0x000001FFU +#define _hrt_ones_0xA 0x000003FFU +#define _hrt_ones_0xB 0x000007FFU +#define _hrt_ones_0xC 0x00000FFFU +#define _hrt_ones_0xD 0x00001FFFU +#define _hrt_ones_0xE 0x00003FFFU +#define _hrt_ones_0xF 0x00007FFFU +#define _hrt_ones_0x10 0x0000FFFFU +#define _hrt_ones_0x11 0x0001FFFFU +#define _hrt_ones_0x12 0x0003FFFFU +#define _hrt_ones_0x13 0x0007FFFFU +#define _hrt_ones_0x14 0x000FFFFFU +#define _hrt_ones_0x15 0x001FFFFFU +#define _hrt_ones_0x16 0x003FFFFFU +#define _hrt_ones_0x17 0x007FFFFFU +#define _hrt_ones_0x18 0x00FFFFFFU +#define _hrt_ones_0x19 0x01FFFFFFU +#define _hrt_ones_0x1A 0x03FFFFFFU +#define _hrt_ones_0x1B 0x07FFFFFFU +#define _hrt_ones_0x1C 0x0FFFFFFFU +#define _hrt_ones_0x1D 0x1FFFFFFFU +#define _hrt_ones_0x1E 0x3FFFFFFFU +#define _hrt_ones_0x1F 0x7FFFFFFFU +#define _hrt_ones_0x20 0xFFFFFFFFU + +#define _hrt_ones_0 _hrt_ones_0x0 +#define _hrt_ones_1 _hrt_ones_0x1 +#define _hrt_ones_2 _hrt_ones_0x2 +#define _hrt_ones_3 _hrt_ones_0x3 +#define _hrt_ones_4 _hrt_ones_0x4 +#define _hrt_ones_5 _hrt_ones_0x5 +#define _hrt_ones_6 _hrt_ones_0x6 +#define _hrt_ones_7 _hrt_ones_0x7 +#define _hrt_ones_8 _hrt_ones_0x8 +#define _hrt_ones_9 _hrt_ones_0x9 +#define _hrt_ones_10 _hrt_ones_0xA +#define _hrt_ones_11 _hrt_ones_0xB +#define _hrt_ones_12 _hrt_ones_0xC +#define _hrt_ones_13 _hrt_ones_0xD +#define _hrt_ones_14 _hrt_ones_0xE +#define _hrt_ones_15 _hrt_ones_0xF +#define _hrt_ones_16 _hrt_ones_0x10 +#define _hrt_ones_17 _hrt_ones_0x11 +#define _hrt_ones_18 _hrt_ones_0x12 +#define _hrt_ones_19 _hrt_ones_0x13 +#define _hrt_ones_20 _hrt_ones_0x14 +#define _hrt_ones_21 _hrt_ones_0x15 +#define _hrt_ones_22 _hrt_ones_0x16 +#define _hrt_ones_23 _hrt_ones_0x17 +#define _hrt_ones_24 _hrt_ones_0x18 +#define _hrt_ones_25 _hrt_ones_0x19 +#define _hrt_ones_26 _hrt_ones_0x1A +#define _hrt_ones_27 _hrt_ones_0x1B +#define _hrt_ones_28 _hrt_ones_0x1C +#define _hrt_ones_29 _hrt_ones_0x1D +#define _hrt_ones_30 _hrt_ones_0x1E +#define _hrt_ones_31 _hrt_ones_0x1F +#define _hrt_ones_32 _hrt_ones_0x20 + +#define _hrt_mask(b, n) \ + (_hrt_ones(n) << (b)) +#define _hrt_get_bits(w, b, n) \ + (((w) >> (b)) & _hrt_ones(n)) +#define _hrt_set_bits(w, b, n, v) \ + (((w) & ~_hrt_mask(b, n)) | (((v) & _hrt_ones(n)) << (b))) +#define _hrt_get_bit(w, b) \ + (((w) >> (b)) & 1) +#define _hrt_set_bit(w, b, v) \ + (((w) & (~(1 << (b)))) | (((v)&1) << (b))) +#define _hrt_set_lower_half(w, v) \ + _hrt_set_bits(w, 0, 16, v) +#define _hrt_set_upper_half(w, v) \ + _hrt_set_bits(w, 16, 16, v) + +#endif /* _HRT_BITS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/cell_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/cell_params.h new file mode 100644 index 0000000..b5756bf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/cell_params.h @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _cell_params_h +#define _cell_params_h + +#define SP_PMEM_LOG_WIDTH_BITS 6 /*Width of PC, 64 bits, 8 bytes*/ +#define SP_ICACHE_TAG_BITS 4 /*size of tag*/ +#define SP_ICACHE_SET_BITS 8 /* 256 sets*/ +#define SP_ICACHE_BLOCKS_PER_SET_BITS 1 /* 2 way associative*/ +#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/ + +#define SP_ICACHE_ADDRESS_BITS \ + (SP_ICACHE_TAG_BITS+SP_ICACHE_BLOCK_ADDRESS_BITS) + +#define SP_PMEM_DEPTH (1<<SP_ICACHE_ADDRESS_BITS) + +#define SP_FIFO_0_DEPTH 0 +#define SP_FIFO_1_DEPTH 0 +#define SP_FIFO_2_DEPTH 0 +#define SP_FIFO_3_DEPTH 0 +#define SP_FIFO_4_DEPTH 0 +#define SP_FIFO_5_DEPTH 0 +#define SP_FIFO_6_DEPTH 0 +#define SP_FIFO_7_DEPTH 0 + + +#define SP_SLV_BUS_MAXBURSTSIZE 1 + +#endif /* _cell_params_h */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/css_receiver_2400_common_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/css_receiver_2400_common_defs.h new file mode 100644 index 0000000..f3054fe --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/css_receiver_2400_common_defs.h @@ -0,0 +1,200 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _css_receiver_2400_common_defs_h_ +#define _css_receiver_2400_common_defs_h_ +#ifndef _mipi_backend_common_defs_h_ +#define _mipi_backend_common_defs_h_ + +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH 16 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH 2 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH 3 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH (_HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */ + +/* Definition of data format ID at the interface CSS_receiver capture/acquisition units */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit legacy */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB888 36 /* 10 0100 RGB888 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW6 40 /* 10 1000 RAW6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW7 41 /* 10 1001 RAW7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW8 42 /* 10 1010 RAW8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW10 43 /* 10 1011 RAW10 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW12 44 /* 10 1100 RAW12 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW14 45 /* 10 1101 RAW14 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_1 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_2 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_3 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_4 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_5 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_6 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_7 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_8 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_Emb 18 /* 01 0010 embedded eight bit non image data */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH1 8 /* 00 1000 Generic Short Packet Code 1 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH2 9 /* 00 1001 Generic Short Packet Code 2 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH3 10 /* 00 1010 Generic Short Packet Code 3 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH4 11 /* 00 1011 Generic Short Packet Code 4 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH5 12 /* 00 1100 Generic Short Packet Code 5 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH6 13 /* 00 1101 Generic Short Packet Code 6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH7 14 /* 00 1110 Generic Short Packet Code 7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH8 15 /* 00 1111 Generic Short Packet Code 8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +/* used reseved mipi positions for these */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38 + +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_WIDTH 6 + +/* Definition of format_types at the interface CSS --> input_selector*/ +/* !! Changes here should be copied to systems/isp/isp_css/bin/conv_transmitter_cmd.tcl !! */ +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB888 0 // 36 'h24 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB555 1 // 33 'h +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW12 9 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW14 10 // 45 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8 11 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10 12 // 25 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_8 13 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_10 14 // 31 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_1 15 // 48 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8L 16 // 26 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_Emb 17 // 18 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_2 18 // 49 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_3 19 // 50 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_4 20 // 51 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_5 21 // 52 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_6 22 // 53 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_7 23 // 54 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_8 24 // 55 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8_CSPS 25 // 28 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10_CSPS 26 // 29 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW16 27 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding + +/* definition for state machine of data FIFO for decode different type of data */ +#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9 +#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7 +#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7 + +#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_WIDTH 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_IDX 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_WIDTH 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_USD_BITS 4 /* bits per USD type */ + +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_EN_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_EN_IDX 8 + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_NO_COMP 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_6_10 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_7_10 2 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_8_10 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_6_12 4 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6 + + +/* packet bit definition */ +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32 +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_IDX 22 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_BITS 2 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_IDX 16 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_BITS 16 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32 + + +/*************************************************************************************************/ +/* Custom Decoding */ +/* These Custom Defs are defined based on design-time config in "csi_be_pixel_formatter.chdl" !! */ +/*************************************************************************************************/ +#define BE_CUST_EN_IDX 0 /* 2bits */ +#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */ +#define BE_CUST_EN_WIDTH 8 +#define BE_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */ +#define BE_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */ + +/* Data State config = {get_bits(6bits), valid(1bit)} */ +#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */ +#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */ +#define BE_CUST_DATA_STATE_S2_IDX 14 /* 7bits */ +#define BE_CUST_DATA_STATE_WIDTH 21 +#define BE_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */ +#define BE_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */ + +/* Pixel Extractor config */ +#define BE_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 5bits */ +#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 5 /* 5bits */ +#define BE_CUST_PIX_EXT_PIX_MASK_IDX 10 /* 18bits */ +#define BE_CUST_PIX_EXT_PIX_EN_IDX 28 /* 1bits */ +#define BE_CUST_PIX_EXT_WIDTH 29 + +/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */ +#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_WIDTH 16 +#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */ +#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */ +#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */ +#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */ + +#endif /* _mipi_backend_common_defs_h_ */ +#endif /* _css_receiver_2400_common_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/css_receiver_2400_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/css_receiver_2400_defs.h new file mode 100644 index 0000000..6f5b7d3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/css_receiver_2400_defs.h @@ -0,0 +1,258 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _css_receiver_2400_defs_h_ +#define _css_receiver_2400_defs_h_ + +#include "css_receiver_2400_common_defs.h" + +#define CSS_RECEIVER_DATA_WIDTH 8 +#define CSS_RECEIVER_RX_TRIG 4 +#define CSS_RECEIVER_RF_WORD 32 +#define CSS_RECEIVER_IMG_PROC_RF_ADDR 10 +#define CSS_RECEIVER_CSI_RF_ADDR 4 +#define CSS_RECEIVER_DATA_OUT 12 +#define CSS_RECEIVER_CHN_NO 2 +#define CSS_RECEIVER_DWORD_CNT 11 +#define CSS_RECEIVER_FORMAT_TYP 5 +#define CSS_RECEIVER_HRESPONSE 2 +#define CSS_RECEIVER_STATE_WIDTH 3 +#define CSS_RECEIVER_FIFO_DAT 32 +#define CSS_RECEIVER_CNT_VAL 2 +#define CSS_RECEIVER_PRED10_VAL 10 +#define CSS_RECEIVER_PRED12_VAL 12 +#define CSS_RECEIVER_CNT_WIDTH 8 +#define CSS_RECEIVER_WORD_CNT 16 +#define CSS_RECEIVER_PIXEL_LEN 6 +#define CSS_RECEIVER_PIXEL_CNT 5 +#define CSS_RECEIVER_COMP_8_BIT 8 +#define CSS_RECEIVER_COMP_7_BIT 7 +#define CSS_RECEIVER_COMP_6_BIT 6 + +#define CSI_CONFIG_WIDTH 4 + +/* division of gen_short data, ch_id and fmt_type over streaming data interface */ +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB 0 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB - 1) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH - 1) + +#define _HRT_CSS_RECEIVER_2400_REG_ALIGN 4 +#define _HRT_CSS_RECEIVER_2400_BYTES_PER_PKT 4 + +#define hrt_css_receiver_2400_4_lane_port_offset 0x100 +#define hrt_css_receiver_2400_1_lane_port_offset 0x200 +#define hrt_css_receiver_2400_2_lane_port_offset 0x300 +#define hrt_css_receiver_2400_backend_port_offset 0x100 + +#define _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX 0 +#define _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX 1 +#define _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX 2 +#define _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 3 +#define _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX 4 +#define _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX 7 +#define _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX 8 +#define _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX 9 +#define _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 10 +#define _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX 11 +#define _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX 12 +#define _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX 13 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX 14 +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX 15 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX 16 +#define _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX 17 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX 18 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX 19 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX 20 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX 21 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX 22 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX 23 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX 24 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX 25 +#define _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX 26 +#define _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX 27 +#define _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX 28 + +/* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */ +#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT 0 +#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT 1 +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT 2 +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT 3 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT 4 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT 5 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT 6 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT 7 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT 8 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT 9 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 10 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT 11 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT 12 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT 13 +#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT 14 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT 15 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT 16 + +#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_CAUSE_ "Fifo Overrun" +#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_CAUSE_ "Reserved" +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_CAUSE_ "Sleep mode entry" +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_CAUSE_ "Sleep mode exit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_CAUSE_ "Error high speed SOT" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_CAUSE_ "Error high speed sync SOT" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_CAUSE_ "Error control" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_CAUSE_ "Error correction double bit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_CAUSE_ "Error correction single bit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_CAUSE_ "No error" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_CAUSE_ "Error cyclic redundancy check" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_CAUSE_ "Error id" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_CAUSE_ "Error frame sync" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_CAUSE_ "Error frame data" +#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_CAUSE_ "Data time-out" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_CAUSE_ "Error escape" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_CAUSE_ "Error line sync" + +/* Bits for CSI2_DEVICE_READY register */ +#define _HRT_CSS_RECEIVER_2400_CSI2_DEVICE_READY_IDX 0 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_INIT_TIME_OUT_ERR_IDX 2 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_OVER_RUN_ERR_IDX 3 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_SOT_SYNC_ERR_IDX 4 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_RECEIVE_DATA_TIME_OUT_ERR_IDX 5 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7 + + +/* Bits for CSI2_FUNC_PROG register */ +#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19 + +/* Bits for INIT_COUNT register */ +#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_IDX 0 +#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_BITS 16 + +/* Bits for COUNT registers */ +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_BITS 8 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_BITS 8 + +/* Bits for RAW116_18_DATAID register */ +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_BITS 6 + +/* Bits for COMP_FORMAT register, this selects the compression data format */ +#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS 8 +#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_IDX (_HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX + _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS) +#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_BITS 8 + +/* Bits for COMP_PREDICT register, this selects the predictor algorithm */ +#define _HRT_CSS_RECEIVER_2400_PREDICT_NO_COMP 0 +#define _HRT_CSS_RECEIVER_2400_PREDICT_1 1 +#define _HRT_CSS_RECEIVER_2400_PREDICT_2 2 + +/* Number of bits used for the delay registers */ +#define _HRT_CSS_RECEIVER_2400_DELAY_BITS 8 + +/* Bits for COMP_SCHEME register, this selects the compression scheme for a VC */ +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD1_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD2_BITS_IDX 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD3_BITS_IDX 10 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD4_BITS_IDX 15 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD5_BITS_IDX 20 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD6_BITS_IDX 25 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD7_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD8_BITS_IDX 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_BITS_BITS 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_BITS 3 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2 + + +/* BITS for backend RAW16 and RAW 18 registers */ + +#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_BITS 2 +#define _HRT_CSS_RECEIVER_2400_RAW18_EN_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW18_EN_BITS 1 + +#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_BITS 2 +#define _HRT_CSS_RECEIVER_2400_RAW16_EN_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1 + +/* These hsync and vsync values are for HSS simulation only */ +#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL (1<<16) +#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL (1<<17) + +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28 +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0 +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB + CSS_RECEIVER_DATA_OUT - 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB + CSS_RECEIVER_DATA_OUT - 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_EOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT + 1) + +// SH Backend Register IDs +#define _HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX 1 +#define _HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX 2 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX 4 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX 5 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX 7 +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX 8 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX 9 +#define _HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX 10 +#define _HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX 11 +#define _HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX 12 +#define _HRT_CSS_RECEIVER_2400_BE_CUST_EN_REG_IDX 13 +#define _HRT_CSS_RECEIVER_2400_BE_CUST_DATA_STATE_REG_IDX 14 /* Data State 0,1,2 config */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P0_REG_IDX 15 /* Pixel Extractor config for Data State 0 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P1_REG_IDX 16 /* Pixel Extractor config for Data State 0 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P2_REG_IDX 17 /* Pixel Extractor config for Data State 0 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P3_REG_IDX 18 /* Pixel Extractor config for Data State 0 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P0_REG_IDX 19 /* Pixel Extractor config for Data State 1 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P1_REG_IDX 20 /* Pixel Extractor config for Data State 1 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P2_REG_IDX 21 /* Pixel Extractor config for Data State 1 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P3_REG_IDX 22 /* Pixel Extractor config for Data State 1 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P0_REG_IDX 23 /* Pixel Extractor config for Data State 2 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P1_REG_IDX 24 /* Pixel Extractor config for Data State 2 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P2_REG_IDX 25 /* Pixel Extractor config for Data State 2 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P3_REG_IDX 26 /* Pixel Extractor config for Data State 2 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_VALID_EOP_REG_IDX 27 /* Pixel Valid & EoP config for Pix 0,1,2,3 */ + +#define _HRT_CSS_RECEIVER_2400_BE_NOF_REGISTERS 28 + +#define _HRT_CSS_RECEIVER_2400_BE_SRST_HE 0 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_RCF 1 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_PF 2 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_SM 3 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_PD 4 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_SD 5 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_OT 6 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_BC 7 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_WIDTH 8 + +#endif /* _css_receiver_2400_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/defs.h new file mode 100644 index 0000000..47505f4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/defs.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_DEFS_H_ +#define _HRT_DEFS_H_ + +#ifndef HRTCAT +#define _HRTCAT(m, n) m##n +#define HRTCAT(m, n) _HRTCAT(m, n) +#endif + +#ifndef HRTSTR +#define _HRTSTR(x) #x +#define HRTSTR(x) _HRTSTR(x) +#endif + +#ifndef HRTMIN +#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef HRTMAX +#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#endif /* _HRT_DEFS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/dma_v2_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/dma_v2_defs.h new file mode 100644 index 0000000..d184a8b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/dma_v2_defs.h @@ -0,0 +1,199 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _dma_v2_defs_h +#define _dma_v2_defs_h + +#define _DMA_V2_NUM_CHANNELS_ID MaxNumChannels +#define _DMA_V2_CONNECTIONS_ID Connections +#define _DMA_V2_DEV_ELEM_WIDTHS_ID DevElemWidths +#define _DMA_V2_DEV_FIFO_DEPTH_ID DevFifoDepth +#define _DMA_V2_DEV_FIFO_RD_LAT_ID DevFifoRdLat +#define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID DevFifoRdLatBypass +#define _DMA_V2_DEV_NO_BURST_ID DevNoBurst +#define _DMA_V2_DEV_RD_ACCEPT_ID DevRdAccept +#define _DMA_V2_DEV_SRMD_ID DevSRMD +#define _DMA_V2_DEV_HAS_CRUN_ID CRunMasters +#define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID CtrlAckFifoDepth +#define _DMA_V2_CMD_FIFO_DEPTH_ID CommandFifoDepth +#define _DMA_V2_CMD_FIFO_RD_LAT_ID CommandFifoRdLat +#define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID CommandFifoRdLatBypass +#define _DMA_V2_NO_PACK_ID has_no_pack + +#define _DMA_V2_REG_ALIGN 4 +#define _DMA_V2_REG_ADDR_BITS 2 + +/* Command word */ +#define _DMA_V2_CMD_IDX 0 +#define _DMA_V2_CMD_BITS 6 +#define _DMA_V2_CHANNEL_IDX (_DMA_V2_CMD_IDX + _DMA_V2_CMD_BITS) +#define _DMA_V2_CHANNEL_BITS 5 + +/* The command to set a parameter contains the PARAM field next */ +#define _DMA_V2_PARAM_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) +#define _DMA_V2_PARAM_BITS 4 + +/* Commands to read, write or init specific blocks contain these + three values */ +#define _DMA_V2_SPEC_DEV_A_XB_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) +#define _DMA_V2_SPEC_DEV_A_XB_BITS 8 +#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS) +#define _DMA_V2_SPEC_DEV_B_XB_BITS 8 +#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS) +#define _DMA_V2_SPEC_YB_BITS (32-_DMA_V2_SPEC_DEV_B_XB_BITS-_DMA_V2_SPEC_DEV_A_XB_BITS-_DMA_V2_CMD_BITS-_DMA_V2_CHANNEL_BITS) + +/* */ +#define _DMA_V2_CMD_CTRL_IDX 4 +#define _DMA_V2_CMD_CTRL_BITS 4 + +/* Packing setup word */ +#define _DMA_V2_CONNECTION_IDX 0 +#define _DMA_V2_CONNECTION_BITS 4 +#define _DMA_V2_EXTENSION_IDX (_DMA_V2_CONNECTION_IDX + _DMA_V2_CONNECTION_BITS) +#define _DMA_V2_EXTENSION_BITS 1 + +/* Elements packing word */ +#define _DMA_V2_ELEMENTS_IDX 0 +#define _DMA_V2_ELEMENTS_BITS 8 +#define _DMA_V2_LEFT_CROPPING_IDX (_DMA_V2_ELEMENTS_IDX + _DMA_V2_ELEMENTS_BITS) +#define _DMA_V2_LEFT_CROPPING_BITS 8 + +#define _DMA_V2_WIDTH_IDX 0 +#define _DMA_V2_WIDTH_BITS 16 + +#define _DMA_V2_HEIGHT_IDX 0 +#define _DMA_V2_HEIGHT_BITS 16 + +#define _DMA_V2_STRIDE_IDX 0 +#define _DMA_V2_STRIDE_BITS 32 + +/* Command IDs */ +#define _DMA_V2_MOVE_B2A_COMMAND 0 +#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1 +#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2 +#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3 +#define _DMA_V2_MOVE_A2B_COMMAND 4 +#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5 +#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6 +#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7 +#define _DMA_V2_INIT_A_COMMAND 8 +#define _DMA_V2_INIT_A_BLOCK_COMMAND 9 +#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10 +#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11 +#define _DMA_V2_INIT_B_COMMAND 12 +#define _DMA_V2_INIT_B_BLOCK_COMMAND 13 +#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14 +#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15 +#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32 +#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33 +#define _DMA_V2_SET_CRUN_COMMAND 62 + +/* Channel Parameter IDs */ +#define _DMA_V2_PACKING_SETUP_PARAM 0 +#define _DMA_V2_STRIDE_A_PARAM 1 +#define _DMA_V2_ELEM_CROPPING_A_PARAM 2 +#define _DMA_V2_WIDTH_A_PARAM 3 +#define _DMA_V2_STRIDE_B_PARAM 4 +#define _DMA_V2_ELEM_CROPPING_B_PARAM 5 +#define _DMA_V2_WIDTH_B_PARAM 6 +#define _DMA_V2_HEIGHT_PARAM 7 +#define _DMA_V2_QUEUED_CMDS 8 + +/* Parameter Constants */ +#define _DMA_V2_ZERO_EXTEND 0 +#define _DMA_V2_SIGN_EXTEND 1 + + /* SLAVE address map */ +#define _DMA_V2_SEL_FSM_CMD 0 +#define _DMA_V2_SEL_CH_REG 1 +#define _DMA_V2_SEL_CONN_GROUP 2 +#define _DMA_V2_SEL_DEV_INTERF 3 + +#define _DMA_V2_ADDR_SEL_COMP_IDX 12 +#define _DMA_V2_ADDR_SEL_COMP_BITS 4 +#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2 +#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6 +#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS+_DMA_V2_ADDR_SEL_CH_REG_IDX) +#define _DMA_V2_ADDR_SEL_PARAM_BITS 4 + +#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2 +#define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS 6 +#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX (_DMA_V2_ADDR_SEL_GROUP_COMP_BITS + _DMA_V2_ADDR_SEL_GROUP_COMP_IDX) +#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS 4 + +#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2 +#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6 +#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX+_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS) +#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4 + +#define _DMA_V2_FSM_GROUP_CMD_IDX 0 +#define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX 1 +#define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX 2 +#define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX 4 +#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5 +#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6 +#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7 + +#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX 4 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX 5 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX 6 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX 7 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX 8 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX 9 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX 10 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX 11 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX 12 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX 13 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX 14 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX 15 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX 15 + +#define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX 3 + +#define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX 4 + +#define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX 4 + +#define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX 0 +#define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX 1 +#define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX 2 +#define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX 3 +#define _DMA_V2_DEV_INTERF_MAX_BURST_IDX 4 +#define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN 5 + +#endif /* _dma_v2_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gdc_v2_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gdc_v2_defs.h new file mode 100644 index 0000000..77722d2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gdc_v2_defs.h @@ -0,0 +1,170 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef HRT_GDC_v2_defs_h_ +#define HRT_GDC_v2_defs_h_ + +#define HRT_GDC_IS_V2 + +#define HRT_GDC_N 1024 /* Top-level design constant, equal to the number of entries in the LUT */ +#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */ + +#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */ +#define HRT_GDC_BLI_COEF_ONE (1 << HRT_GDC_BLI_FRAC_BITS) + +#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */ +#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS-2)) /* We represent signed 10 bit coefficients. */ + /* The supported range is [-256, .., +256] */ + /* in 14-bit signed notation, */ + /* We need all ten bits (MSB must be zero). */ + /* -s is inserted to solve this issue, and */ + /* therefore "1" is equal to +256. */ +#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1) + +#define HRT_GDC_LUT_BYTES (HRT_GDC_N*4*2) /* 1024 addresses, 4 coefficients per address, */ + /* 2 bytes per coefficient */ + +#define _HRT_GDC_REG_ALIGN 4 + + // 31 30 29 25 24 0 + // |-----|---|--------|------------------------| + // | CMD | C | Reg_ID | Value | + + + // There are just two commands possible for the GDC block: + // 1 - Configure reg + // 0 - Data token + + // C - Reserved bit + // Used in protocol to indicate whether it is C-run or other type of runs + // In case of C-run, this bit has a value of 1, for all the other runs, it is 0. + + // Reg_ID - Address of the register to be configured + + // Value - Value to store to the addressed register, maximum of 24 bits + + // Configure reg command is not followed by any other token. + // The address of the register and the data to be filled in is contained in the same token + + // When the first data token is received, it must be: + // 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or, + // 2. P0'X (device configured in one of the tetragon modes) + // After the first data token is received, pre-defined number of tokens with the following meaning follow: + // 1. two tokens: SRC address ; DST address + // 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address + +#define HRT_GDC_CONFIG_CMD 1 +#define HRT_GDC_DATA_CMD 0 + + +#define HRT_GDC_CMD_POS 31 +#define HRT_GDC_CMD_BITS 1 +#define HRT_GDC_CRUN_POS 30 +#define HRT_GDC_REG_ID_POS 25 +#define HRT_GDC_REG_ID_BITS 5 +#define HRT_GDC_DATA_POS 0 +#define HRT_GDC_DATA_BITS 25 + +#define HRT_GDC_FRYIPXFRX_BITS 26 +#define HRT_GDC_P0X_BITS 23 + + +#define HRT_GDC_MAX_OXDIM (8192-64) +#define HRT_GDC_MAX_OYDIM 4095 +#define HRT_GDC_MAX_IXDIM (8192-64) +#define HRT_GDC_MAX_IYDIM 4095 +#define HRT_GDC_MAX_DS_FAC 16 +#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC*HRT_GDC_N - 1) +#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX + + +/* GDC lookup tables entries are 10 bits values, but they're + stored 2 by 2 as 32 bit values, yielding 16 bits per entry. + A GDC lookup table contains 64 * 4 elements */ + +#define HRT_GDC_PERF_1_1_pix 0 +#define HRT_GDC_PERF_2_1_pix 1 +#define HRT_GDC_PERF_1_2_pix 2 +#define HRT_GDC_PERF_2_2_pix 3 + +#define HRT_GDC_NND_MODE 0 +#define HRT_GDC_BLI_MODE 1 +#define HRT_GDC_BCI_MODE 2 +#define HRT_GDC_LUT_MODE 3 + +#define HRT_GDC_SCAN_STB 0 +#define HRT_GDC_SCAN_STR 1 + +#define HRT_GDC_MODE_SCALING 0 +#define HRT_GDC_MODE_TETRAGON 1 + +#define HRT_GDC_LUT_COEFF_OFFSET 16 +#define HRT_GDC_FRY_BIT_OFFSET 16 +// FRYIPXFRX is the only register where we store two values in one field, +// to save one token in the scaling protocol. +// Like this, we have three tokens in the scaling protocol, +// Otherwise, we would have had four. +// The register bit-map is: +// 31 26 25 16 15 10 9 0 +// |------|----------|------|----------| +// | XXXX | FRY | IPX | FRX | + + +#define HRT_GDC_CE_FSM0_POS 0 +#define HRT_GDC_CE_FSM0_LEN 2 +#define HRT_GDC_CE_OPY_POS 2 +#define HRT_GDC_CE_OPY_LEN 14 +#define HRT_GDC_CE_OPX_POS 16 +#define HRT_GDC_CE_OPX_LEN 16 +// CHK_ENGINE register bit-map: +// 31 16 15 2 1 0 +// |----------------|-----------|----| +// | OPX | OPY |FSM0| +// However, for the time being at least, +// this implementation is meaningless in hss model, +// So, we just return 0 + + +#define HRT_GDC_CHK_ENGINE_IDX 0 +#define HRT_GDC_WOIX_IDX 1 +#define HRT_GDC_WOIY_IDX 2 +#define HRT_GDC_BPP_IDX 3 +#define HRT_GDC_FRYIPXFRX_IDX 4 +#define HRT_GDC_OXDIM_IDX 5 +#define HRT_GDC_OYDIM_IDX 6 +#define HRT_GDC_SRC_ADDR_IDX 7 +#define HRT_GDC_SRC_END_ADDR_IDX 8 +#define HRT_GDC_SRC_WRAP_ADDR_IDX 9 +#define HRT_GDC_SRC_STRIDE_IDX 10 +#define HRT_GDC_DST_ADDR_IDX 11 +#define HRT_GDC_DST_STRIDE_IDX 12 +#define HRT_GDC_DX_IDX 13 +#define HRT_GDC_DY_IDX 14 +#define HRT_GDC_P0X_IDX 15 +#define HRT_GDC_P0Y_IDX 16 +#define HRT_GDC_P1X_IDX 17 +#define HRT_GDC_P1Y_IDX 18 +#define HRT_GDC_P2X_IDX 19 +#define HRT_GDC_P2Y_IDX 20 +#define HRT_GDC_P3X_IDX 21 +#define HRT_GDC_P3Y_IDX 22 +#define HRT_GDC_PERF_POINT_IDX 23 // 1x1 ; 1x2 ; 2x1 ; 2x2 pixels per cc +#define HRT_GDC_INTERP_TYPE_IDX 24 // NND ; BLI ; BCI ; LUT +#define HRT_GDC_SCAN_IDX 25 // 0 = STB (Slide To Bottom) ; 1 = STR (Slide To Right) +#define HRT_GDC_PROC_MODE_IDX 26 // 0 = Scaling ; 1 = Tetragon + +#define HRT_GDC_LUT_IDX 32 + + +#endif /* HRT_GDC_v2_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_regs_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_regs_defs.h new file mode 100644 index 0000000..34e734f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_regs_defs.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gp_regs_defs_h +#define _gp_regs_defs_h + +#define _HRT_GP_REGS_IS_FWD_REG_IDX 0 + +#define _HRT_GP_REGS_REG_ALIGN 4 + +#endif /* _gp_regs_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_timer_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_timer_defs.h new file mode 100644 index 0000000..3082e2f5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_timer_defs.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gp_timer_defs_h +#define _gp_timer_defs_h + +#define _HRT_GP_TIMER_REG_ALIGN 4 + +#define HIVE_GP_TIMER_RESET_REG_IDX 0 +#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1 +#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer) +#define HIVE_GP_TIMER_VALUE_REG_IDX(timer,timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer) +#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer,timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer) +#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer,timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer) +#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq,timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq) +#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq) +#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq) + +#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0 +#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1 +#define HIVE_GP_TIMER_COUNT_TYPE_POSEDGE 2 +#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3 +#define HIVE_GP_TIMER_COUNT_TYPES 4 + +#endif /* _gp_timer_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gpio_block_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gpio_block_defs.h new file mode 100644 index 0000000..a807d4c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gpio_block_defs.h @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gpio_block_defs_h_ +#define _gpio_block_defs_h_ + +#define _HRT_GPIO_BLOCK_REG_ALIGN 4 + +/* R/W registers */ +#define _gpio_block_reg_do_e 0 +#define _gpio_block_reg_do_select 1 +#define _gpio_block_reg_do_0 2 +#define _gpio_block_reg_do_1 3 +#define _gpio_block_reg_do_pwm_cnt_0 4 +#define _gpio_block_reg_do_pwm_cnt_1 5 +#define _gpio_block_reg_do_pwm_cnt_2 6 +#define _gpio_block_reg_do_pwm_cnt_3 7 +#define _gpio_block_reg_do_pwm_main_cnt 8 +#define _gpio_block_reg_do_pwm_enable 9 +#define _gpio_block_reg_di_debounce_sel 10 +#define _gpio_block_reg_di_debounce_cnt_0 11 +#define _gpio_block_reg_di_debounce_cnt_1 12 +#define _gpio_block_reg_di_debounce_cnt_2 13 +#define _gpio_block_reg_di_debounce_cnt_3 14 +#define _gpio_block_reg_di_active_level 15 + + +/* read-only registers */ +#define _gpio_block_reg_di 16 + +#endif /* _gpio_block_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_2401_irq_types_hrt.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_2401_irq_types_hrt.h new file mode 100644 index 0000000..2f7cb2d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_2401_irq_types_hrt.h @@ -0,0 +1,68 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HIVE_ISP_CSS_2401_IRQ_TYPES_HRT_H_ +#define _HIVE_ISP_CSS_2401_IRQ_TYPES_HRT_H_ + +/* + * These are the indices of each interrupt in the interrupt + * controller's registers. these can be used as the irq_id + * argument to the hrt functions irq_controller.h. + * + * The definitions are taken from <system>_defs.h + */ +typedef enum hrt_isp_css_irq { + hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID , + hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID , + hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID , + hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID , + hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID , + hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID , + hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID , + hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID , + hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID , + hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID , + hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID , + hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID , + hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID , + hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID , + hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID , + hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID , + hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID , + hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID , + hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID , + hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID , + hrt_isp_css_irq_is2401 = HIVE_GP_DEV_IRQ_IS2401_BIT_ID , + hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID , + hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID , + hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID , + hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID , + hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID , + hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID , + hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID , + hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID , + hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID , + hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID , + hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID , + /* this must (obviously) be the last on in the enum */ + hrt_isp_css_irq_num_irqs +} hrt_isp_css_irq_t; + +typedef enum hrt_isp_css_irq_status { + hrt_isp_css_irq_status_error, + hrt_isp_css_irq_status_more_irqs, + hrt_isp_css_irq_status_success +} hrt_isp_css_irq_status_t; + +#endif /* _HIVE_ISP_CSS_2401_IRQ_TYPES_HRT_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_defs.h new file mode 100644 index 0000000..5a2ce91 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_defs.h @@ -0,0 +1,435 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _hive_isp_css_defs_h__ +#define _hive_isp_css_defs_h__ + +#define _HIVE_ISP_CSS_2401_SYSTEM 1 +#define HIVE_ISP_CTRL_DATA_WIDTH 32 +#define HIVE_ISP_CTRL_ADDRESS_WIDTH 32 +#define HIVE_ISP_CTRL_MAX_BURST_SIZE 1 +#define HIVE_ISP_DDR_ADDRESS_WIDTH 36 + +#define HIVE_ISP_HOST_MAX_BURST_SIZE 8 /* host supports bursts in order to prevent repeating DDRAM accesses */ +#define HIVE_ISP_NUM_GPIO_PINS 12 + +/* This list of vector num_elems/elem_bits pairs is valid both in C as initializer + and in the DMA parameter list */ +#define HIVE_ISP_DDR_DMA_SPECS {{32, 8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}} +#define HIVE_ISP_DDR_WORD_BITS 256 +#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS/8) +#define HIVE_ISP_DDR_BYTES (512 * 1024 * 1024) +#define HIVE_ISP_DDR_BYTES_RTL (127 * 1024 * 1024) +#define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8) +#define HIVE_ISP_PAGE_SHIFT 12 +#define HIVE_ISP_PAGE_SIZE (1<<HIVE_ISP_PAGE_SHIFT) + +#define CSS_DDR_WORD_BITS HIVE_ISP_DDR_WORD_BITS +#define CSS_DDR_WORD_BYTES HIVE_ISP_DDR_WORD_BYTES + +/* settings used in applications */ +#define HIVE_XMEM_WIDTH HIVE_ISP_DDR_WORD_BITS +#define HIVE_VMEM_VECTOR_ELEMENTS 64 +#define HIVE_VMEM_ELEMENT_BITS 14 +#define HIVE_XMEM_ELEMENT_BITS 16 +#define HIVE_VMEM_VECTOR_BYTES (HIVE_VMEM_VECTOR_ELEMENTS*HIVE_XMEM_ELEMENT_BITS/8) /* used for # addr bytes for one vector */ +#define HIVE_XMEM_PACKED_WORD_VMEM_ELEMENTS (HIVE_XMEM_WIDTH/HIVE_VMEM_ELEMENT_BITS) +#define HIVE_XMEM_WORD_VMEM_ELEMENTS (HIVE_XMEM_WIDTH/HIVE_XMEM_ELEMENT_BITS) +#define XMEM_INT_SIZE 4 + + + +#define HIVE_ISYS_INP_BUFFER_BYTES (64*1024) /* 64 kByte = 2k words (of 256 bits) */ + +/* If HIVE_ISP_DDR_BASE_OFFSET is set to a non-zero value, the wide bus just before the DDRAM gets an extra dummy port where */ +/* address range 0 .. HIVE_ISP_DDR_BASE_OFFSET-1 maps onto. This effectively creates an offset for the DDRAM from system perspective */ +#define HIVE_ISP_DDR_BASE_OFFSET 0x120000000 /* 0x200000 */ + +#define HIVE_DMA_ISP_BUS_CONN 0 +#define HIVE_DMA_ISP_DDR_CONN 1 +#define HIVE_DMA_BUS_DDR_CONN 2 +#define HIVE_DMA_ISP_MASTER master_port0 +#define HIVE_DMA_BUS_MASTER master_port1 +#define HIVE_DMA_DDR_MASTER master_port2 + +#define HIVE_DMA_NUM_CHANNELS 32 /* old value was 8 */ +#define HIVE_DMA_CMD_FIFO_DEPTH 24 /* old value was 12 */ + +#define HIVE_IF_PIXEL_WIDTH 12 + +#define HIVE_MMU_TLB_SETS 8 +#define HIVE_MMU_TLB_SET_BLOCKS 8 +#define HIVE_MMU_TLB_BLOCK_ELEMENTS 8 +#define HIVE_MMU_PAGE_TABLE_LEVELS 2 +#define HIVE_MMU_PAGE_BYTES HIVE_ISP_PAGE_SIZE + +#define HIVE_ISP_CH_ID_BITS 2 +#define HIVE_ISP_FMT_TYPE_BITS 5 +#define HIVE_ISP_ISEL_SEL_BITS 2 + +#define HIVE_GP_REGS_SDRAM_WAKEUP_IDX 0 +#define HIVE_GP_REGS_IDLE_IDX 1 +#define HIVE_GP_REGS_IRQ_0_IDX 2 +#define HIVE_GP_REGS_IRQ_1_IDX 3 +#define HIVE_GP_REGS_SP_STREAM_STAT_IDX 4 +#define HIVE_GP_REGS_SP_STREAM_STAT_B_IDX 5 +#define HIVE_GP_REGS_ISP_STREAM_STAT_IDX 6 +#define HIVE_GP_REGS_MOD_STREAM_STAT_IDX 7 +#define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_COND_IDX 8 +#define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_COND_IDX 9 +#define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_COND_IDX 10 +#define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_COND_IDX 11 +#define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_ENABLE_IDX 12 +#define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_ENABLE_IDX 13 +#define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_ENABLE_IDX 14 +#define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_ENABLE_IDX 15 +#define HIVE_GP_REGS_SWITCH_PRIM_IF_IDX 16 +#define HIVE_GP_REGS_SWITCH_GDC1_IDX 17 +#define HIVE_GP_REGS_SWITCH_GDC2_IDX 18 +#define HIVE_GP_REGS_SRST_IDX 19 +#define HIVE_GP_REGS_SLV_REG_SRST_IDX 20 +#define HIVE_GP_REGS_SWITCH_ISYS_IDX 21 + +/* Bit numbers of the soft reset register */ +#define HIVE_GP_REGS_SRST_ISYS_CBUS 0 +#define HIVE_GP_REGS_SRST_ISEL_CBUS 1 +#define HIVE_GP_REGS_SRST_IFMT_CBUS 2 +#define HIVE_GP_REGS_SRST_GPDEV_CBUS 3 +#define HIVE_GP_REGS_SRST_GPIO 4 +#define HIVE_GP_REGS_SRST_TC 5 +#define HIVE_GP_REGS_SRST_GPTIMER 6 +#define HIVE_GP_REGS_SRST_FACELLFIFOS 7 +#define HIVE_GP_REGS_SRST_D_OSYS 8 +#define HIVE_GP_REGS_SRST_IFT_SEC_PIPE 9 +#define HIVE_GP_REGS_SRST_GDC1 10 +#define HIVE_GP_REGS_SRST_GDC2 11 +#define HIVE_GP_REGS_SRST_VEC_BUS 12 +#define HIVE_GP_REGS_SRST_ISP 13 +#define HIVE_GP_REGS_SRST_SLV_GRP_BUS 14 +#define HIVE_GP_REGS_SRST_DMA 15 +#define HIVE_GP_REGS_SRST_SF_ISP_SP 16 +#define HIVE_GP_REGS_SRST_SF_PIF_CELLS 17 +#define HIVE_GP_REGS_SRST_SF_SIF_SP 18 +#define HIVE_GP_REGS_SRST_SF_MC_SP 19 +#define HIVE_GP_REGS_SRST_SF_ISYS_SP 20 +#define HIVE_GP_REGS_SRST_SF_DMA_CELLS 21 +#define HIVE_GP_REGS_SRST_SF_GDC1_CELLS 22 +#define HIVE_GP_REGS_SRST_SF_GDC2_CELLS 23 +#define HIVE_GP_REGS_SRST_SP 24 +#define HIVE_GP_REGS_SRST_OCP2CIO 25 +#define HIVE_GP_REGS_SRST_NBUS 26 +#define HIVE_GP_REGS_SRST_HOST12BUS 27 +#define HIVE_GP_REGS_SRST_WBUS 28 +#define HIVE_GP_REGS_SRST_IC_OSYS 29 +#define HIVE_GP_REGS_SRST_WBUS_IC 30 +#define HIVE_GP_REGS_SRST_ISYS_INP_BUF_BUS 31 + +/* Bit numbers of the slave register soft reset register */ +#define HIVE_GP_REGS_SLV_REG_SRST_DMA 0 +#define HIVE_GP_REGS_SLV_REG_SRST_GDC1 1 +#define HIVE_GP_REGS_SLV_REG_SRST_GDC2 2 + +/* order of the input bits for the irq controller */ +#define HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID 0 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID 1 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID 2 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID 3 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID 4 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID 5 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID 6 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID 7 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID 8 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID 9 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID 10 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID 11 +#define HIVE_GP_DEV_IRQ_SP_BIT_ID 12 +#define HIVE_GP_DEV_IRQ_ISP_BIT_ID 13 +#define HIVE_GP_DEV_IRQ_ISYS_BIT_ID 14 +#define HIVE_GP_DEV_IRQ_ISEL_BIT_ID 15 +#define HIVE_GP_DEV_IRQ_IFMT_BIT_ID 16 +#define HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID 17 +#define HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID 18 +#define HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID 19 +#define HIVE_GP_DEV_IRQ_IS2401_BIT_ID 20 +#define HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID 21 +#define HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID 22 +#define HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID 23 +#define HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID 24 +#define HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID 25 +#define HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID 26 +#define HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID 27 +#define HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID 28 +#define HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID 29 +#define HIVE_GP_DEV_IRQ_DMA_BIT_ID 30 +#define HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID 31 + +#define HIVE_GP_REGS_NUM_SW_IRQ_REGS 2 + +/* order of the input bits for the timed controller */ +#define HIVE_GP_DEV_TC_GPIO_PIN_0_BIT_ID 0 +#define HIVE_GP_DEV_TC_GPIO_PIN_1_BIT_ID 1 +#define HIVE_GP_DEV_TC_GPIO_PIN_2_BIT_ID 2 +#define HIVE_GP_DEV_TC_GPIO_PIN_3_BIT_ID 3 +#define HIVE_GP_DEV_TC_GPIO_PIN_4_BIT_ID 4 +#define HIVE_GP_DEV_TC_GPIO_PIN_5_BIT_ID 5 +#define HIVE_GP_DEV_TC_GPIO_PIN_6_BIT_ID 6 +#define HIVE_GP_DEV_TC_GPIO_PIN_7_BIT_ID 7 +#define HIVE_GP_DEV_TC_GPIO_PIN_8_BIT_ID 8 +#define HIVE_GP_DEV_TC_GPIO_PIN_9_BIT_ID 9 +#define HIVE_GP_DEV_TC_GPIO_PIN_10_BIT_ID 10 +#define HIVE_GP_DEV_TC_GPIO_PIN_11_BIT_ID 11 +#define HIVE_GP_DEV_TC_SP_BIT_ID 12 +#define HIVE_GP_DEV_TC_ISP_BIT_ID 13 +#define HIVE_GP_DEV_TC_ISYS_BIT_ID 14 +#define HIVE_GP_DEV_TC_ISEL_BIT_ID 15 +#define HIVE_GP_DEV_TC_IFMT_BIT_ID 16 +#define HIVE_GP_DEV_TC_GP_TIMER_0_BIT_ID 17 +#define HIVE_GP_DEV_TC_GP_TIMER_1_BIT_ID 18 +#define HIVE_GP_DEV_TC_MIPI_SOL_BIT_ID 19 +#define HIVE_GP_DEV_TC_MIPI_EOL_BIT_ID 20 +#define HIVE_GP_DEV_TC_MIPI_SOF_BIT_ID 21 +#define HIVE_GP_DEV_TC_MIPI_EOF_BIT_ID 22 +#define HIVE_GP_DEV_TC_INPSYS_SM 23 + +/* definitions for the gp_timer block */ +#define HIVE_GP_TIMER_0 0 +#define HIVE_GP_TIMER_1 1 +#define HIVE_GP_TIMER_2 2 +#define HIVE_GP_TIMER_3 3 +#define HIVE_GP_TIMER_4 4 +#define HIVE_GP_TIMER_5 5 +#define HIVE_GP_TIMER_6 6 +#define HIVE_GP_TIMER_7 7 +#define HIVE_GP_TIMER_NUM_COUNTERS 8 + +#define HIVE_GP_TIMER_IRQ_0 0 +#define HIVE_GP_TIMER_IRQ_1 1 +#define HIVE_GP_TIMER_NUM_IRQS 2 + +#define HIVE_GP_TIMER_GPIO_0_BIT_ID 0 +#define HIVE_GP_TIMER_GPIO_1_BIT_ID 1 +#define HIVE_GP_TIMER_GPIO_2_BIT_ID 2 +#define HIVE_GP_TIMER_GPIO_3_BIT_ID 3 +#define HIVE_GP_TIMER_GPIO_4_BIT_ID 4 +#define HIVE_GP_TIMER_GPIO_5_BIT_ID 5 +#define HIVE_GP_TIMER_GPIO_6_BIT_ID 6 +#define HIVE_GP_TIMER_GPIO_7_BIT_ID 7 +#define HIVE_GP_TIMER_GPIO_8_BIT_ID 8 +#define HIVE_GP_TIMER_GPIO_9_BIT_ID 9 +#define HIVE_GP_TIMER_GPIO_10_BIT_ID 10 +#define HIVE_GP_TIMER_GPIO_11_BIT_ID 11 +#define HIVE_GP_TIMER_INP_SYS_IRQ 12 +#define HIVE_GP_TIMER_ISEL_IRQ 13 +#define HIVE_GP_TIMER_IFMT_IRQ 14 +#define HIVE_GP_TIMER_SP_STRMON_IRQ 15 +#define HIVE_GP_TIMER_SP_B_STRMON_IRQ 16 +#define HIVE_GP_TIMER_ISP_STRMON_IRQ 17 +#define HIVE_GP_TIMER_MOD_STRMON_IRQ 18 +#define HIVE_GP_TIMER_IS2401_IRQ 19 +#define HIVE_GP_TIMER_ISP_BAMEM_ERROR_IRQ 20 +#define HIVE_GP_TIMER_ISP_DMEM_ERROR_IRQ 21 +#define HIVE_GP_TIMER_SP_ICACHE_MEM_ERROR_IRQ 22 +#define HIVE_GP_TIMER_SP_DMEM_ERROR_IRQ 23 +#define HIVE_GP_TIMER_SP_OUT_RUN_DP 24 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I0 25 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I1 26 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I2 27 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I3 28 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I4 29 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I5 30 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I6 31 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I7 32 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I8 33 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I9 34 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I10 35 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I1_I0 36 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I2_I0 37 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I3_I0 38 +#define HIVE_GP_TIMER_ISP_OUT_RUN_DP 39 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I0_I0 40 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I0_I1 41 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I1_I0 42 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I0 43 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I1 44 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I2 45 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I3 46 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I4 47 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I5 48 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I6 49 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I3_I0 50 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I4_I0 51 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I5_I0 52 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I6_I0 53 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54 +#define HIVE_GP_TIMER_MIPI_SOL_BIT_ID 55 +#define HIVE_GP_TIMER_MIPI_EOL_BIT_ID 56 +#define HIVE_GP_TIMER_MIPI_SOF_BIT_ID 57 +#define HIVE_GP_TIMER_MIPI_EOF_BIT_ID 58 +#define HIVE_GP_TIMER_INPSYS_SM 59 +#define HIVE_GP_TIMER_ISP_PMEM_ERROR_IRQ 60 + +/* port definitions for the streaming monitors */ +/* port definititions SP streaming monitor, monitors the status of streaming ports at the SP side of the streaming FIFO's */ +#define SP_STR_MON_PORT_SP2SIF 0 +#define SP_STR_MON_PORT_SIF2SP 1 +#define SP_STR_MON_PORT_SP2MC 2 +#define SP_STR_MON_PORT_MC2SP 3 +#define SP_STR_MON_PORT_SP2DMA 4 +#define SP_STR_MON_PORT_DMA2SP 5 +#define SP_STR_MON_PORT_SP2ISP 6 +#define SP_STR_MON_PORT_ISP2SP 7 +#define SP_STR_MON_PORT_SP2GPD 8 +#define SP_STR_MON_PORT_FA2SP 9 +#define SP_STR_MON_PORT_SP2ISYS 10 +#define SP_STR_MON_PORT_ISYS2SP 11 +#define SP_STR_MON_PORT_SP2PIFA 12 +#define SP_STR_MON_PORT_PIFA2SP 13 +#define SP_STR_MON_PORT_SP2PIFB 14 +#define SP_STR_MON_PORT_PIFB2SP 15 + +#define SP_STR_MON_PORT_B_SP2GDC1 0 +#define SP_STR_MON_PORT_B_GDC12SP 1 +#define SP_STR_MON_PORT_B_SP2GDC2 2 +#define SP_STR_MON_PORT_B_GDC22SP 3 + +/* previously used SP streaming monitor port identifiers, kept for backward compatibility */ +#define SP_STR_MON_PORT_SND_SIF SP_STR_MON_PORT_SP2SIF +#define SP_STR_MON_PORT_RCV_SIF SP_STR_MON_PORT_SIF2SP +#define SP_STR_MON_PORT_SND_MC SP_STR_MON_PORT_SP2MC +#define SP_STR_MON_PORT_RCV_MC SP_STR_MON_PORT_MC2SP +#define SP_STR_MON_PORT_SND_DMA SP_STR_MON_PORT_SP2DMA +#define SP_STR_MON_PORT_RCV_DMA SP_STR_MON_PORT_DMA2SP +#define SP_STR_MON_PORT_SND_ISP SP_STR_MON_PORT_SP2ISP +#define SP_STR_MON_PORT_RCV_ISP SP_STR_MON_PORT_ISP2SP +#define SP_STR_MON_PORT_SND_GPD SP_STR_MON_PORT_SP2GPD +#define SP_STR_MON_PORT_RCV_GPD SP_STR_MON_PORT_FA2SP +/* Deprecated */ +#define SP_STR_MON_PORT_SND_PIF SP_STR_MON_PORT_SP2PIFA +#define SP_STR_MON_PORT_RCV_PIF SP_STR_MON_PORT_PIFA2SP +#define SP_STR_MON_PORT_SND_PIFB SP_STR_MON_PORT_SP2PIFB +#define SP_STR_MON_PORT_RCV_PIFB SP_STR_MON_PORT_PIFB2SP + +#define SP_STR_MON_PORT_SND_PIF_A SP_STR_MON_PORT_SP2PIFA +#define SP_STR_MON_PORT_RCV_PIF_A SP_STR_MON_PORT_PIFA2SP +#define SP_STR_MON_PORT_SND_PIF_B SP_STR_MON_PORT_SP2PIFB +#define SP_STR_MON_PORT_RCV_PIF_B SP_STR_MON_PORT_PIFB2SP + +/* port definititions ISP streaming monitor, monitors the status of streaming ports at the ISP side of the streaming FIFO's */ +#define ISP_STR_MON_PORT_ISP2PIFA 0 +#define ISP_STR_MON_PORT_PIFA2ISP 1 +#define ISP_STR_MON_PORT_ISP2PIFB 2 +#define ISP_STR_MON_PORT_PIFB2ISP 3 +#define ISP_STR_MON_PORT_ISP2DMA 4 +#define ISP_STR_MON_PORT_DMA2ISP 5 +#define ISP_STR_MON_PORT_ISP2GDC1 6 +#define ISP_STR_MON_PORT_GDC12ISP 7 +#define ISP_STR_MON_PORT_ISP2GDC2 8 +#define ISP_STR_MON_PORT_GDC22ISP 9 +#define ISP_STR_MON_PORT_ISP2GPD 10 +#define ISP_STR_MON_PORT_FA2ISP 11 +#define ISP_STR_MON_PORT_ISP2SP 12 +#define ISP_STR_MON_PORT_SP2ISP 13 + +/* previously used ISP streaming monitor port identifiers, kept for backward compatibility */ +#define ISP_STR_MON_PORT_SND_PIF_A ISP_STR_MON_PORT_ISP2PIFA +#define ISP_STR_MON_PORT_RCV_PIF_A ISP_STR_MON_PORT_PIFA2ISP +#define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB +#define ISP_STR_MON_PORT_RCV_PIF_B ISP_STR_MON_PORT_PIFB2ISP +#define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA +#define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP +#define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1 +#define ISP_STR_MON_PORT_RCV_GDC ISP_STR_MON_PORT_GDC12ISP +#define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD +#define ISP_STR_MON_PORT_RCV_GPD ISP_STR_MON_PORT_FA2ISP +#define ISP_STR_MON_PORT_SND_SP ISP_STR_MON_PORT_ISP2SP +#define ISP_STR_MON_PORT_RCV_SP ISP_STR_MON_PORT_SP2ISP + +/* port definititions MOD streaming monitor, monitors the status of streaming ports at the module side of the streaming FIFO's */ + +#define MOD_STR_MON_PORT_PIFA2CELLS 0 +#define MOD_STR_MON_PORT_CELLS2PIFA 1 +#define MOD_STR_MON_PORT_PIFB2CELLS 2 +#define MOD_STR_MON_PORT_CELLS2PIFB 3 +#define MOD_STR_MON_PORT_SIF2SP 4 +#define MOD_STR_MON_PORT_SP2SIF 5 +#define MOD_STR_MON_PORT_MC2SP 6 +#define MOD_STR_MON_PORT_SP2MC 7 +#define MOD_STR_MON_PORT_DMA2ISP 8 +#define MOD_STR_MON_PORT_ISP2DMA 9 +#define MOD_STR_MON_PORT_DMA2SP 10 +#define MOD_STR_MON_PORT_SP2DMA 11 +#define MOD_STR_MON_PORT_GDC12CELLS 12 +#define MOD_STR_MON_PORT_CELLS2GDC1 13 +#define MOD_STR_MON_PORT_GDC22CELLS 14 +#define MOD_STR_MON_PORT_CELLS2GDC2 15 + +#define MOD_STR_MON_PORT_SND_PIF_A 0 +#define MOD_STR_MON_PORT_RCV_PIF_A 1 +#define MOD_STR_MON_PORT_SND_PIF_B 2 +#define MOD_STR_MON_PORT_RCV_PIF_B 3 +#define MOD_STR_MON_PORT_SND_SIF 4 +#define MOD_STR_MON_PORT_RCV_SIF 5 +#define MOD_STR_MON_PORT_SND_MC 6 +#define MOD_STR_MON_PORT_RCV_MC 7 +#define MOD_STR_MON_PORT_SND_DMA2ISP 8 +#define MOD_STR_MON_PORT_RCV_DMA_FR_ISP 9 +#define MOD_STR_MON_PORT_SND_DMA2SP 10 +#define MOD_STR_MON_PORT_RCV_DMA_FR_SP 11 +#define MOD_STR_MON_PORT_SND_GDC 12 +#define MOD_STR_MON_PORT_RCV_GDC 13 + + +/* testbench signals: */ + +/* testbench GP adapter register ids */ +#define HIVE_TESTBENCH_GPIO_DATA_OUT_REG_IDX 0 +#define HIVE_TESTBENCH_GPIO_DIR_OUT_REG_IDX 1 +#define HIVE_TESTBENCH_IRQ_REG_IDX 2 +#define HIVE_TESTBENCH_SDRAM_WAKEUP_REG_IDX 3 +#define HIVE_TESTBENCH_IDLE_REG_IDX 4 +#define HIVE_TESTBENCH_GPIO_DATA_IN_REG_IDX 5 +#define HIVE_TESTBENCH_MIPI_BFM_EN_REG_IDX 6 +#define HIVE_TESTBENCH_CSI_CONFIG_REG_IDX 7 +#define HIVE_TESTBENCH_DDR_STALL_EN_REG_IDX 8 + +#define HIVE_TESTBENCH_ISP_PMEM_ERROR_IRQ_REG_IDX 9 +#define HIVE_TESTBENCH_ISP_BAMEM_ERROR_IRQ_REG_IDX 10 +#define HIVE_TESTBENCH_ISP_DMEM_ERROR_IRQ_REG_IDX 11 +#define HIVE_TESTBENCH_SP_ICACHE_MEM_ERROR_IRQ_REG_IDX 12 +#define HIVE_TESTBENCH_SP_DMEM_ERROR_IRQ_REG_IDX 13 + +#define HIVE_TESTBENCH_MIPI_PARPATHEN_REG_IDX 14 +#define HIVE_TESTBENCH_FB_HPLL_FREQ_REG_IDX 15 +#define HIVE_TESTBENCH_ISCLK_RATIO_REG_IDX 16 + +/* Signal monitor input bit ids */ +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_O_BIT_ID 0 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_1_BIT_ID 1 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_2_BIT_ID 2 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_3_BIT_ID 3 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_4_BIT_ID 4 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_5_BIT_ID 5 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_6_BIT_ID 6 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_7_BIT_ID 7 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_8_BIT_ID 8 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_9_BIT_ID 9 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_10_BIT_ID 10 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_11_BIT_ID 11 +#define HIVE_TESTBENCH_SIG_MON_IRQ_PIN_BIT_ID 12 +#define HIVE_TESTBENCH_SIG_MON_SDRAM_WAKEUP_PIN_BIT_ID 13 +#define HIVE_TESTBENCH_SIG_MON_IDLE_PIN_BIT_ID 14 + +#define ISP2400_DEBUG_NETWORK 1 + +#endif /* _hive_isp_css_defs_h__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_host_ids_hrt.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_host_ids_hrt.h new file mode 100644 index 0000000..8d4c9d6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_host_ids_hrt.h @@ -0,0 +1,119 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _hive_isp_css_host_ids_hrt_h_ +#define _hive_isp_css_host_ids_hrt_h_ + +/* ISP_CSS identifiers */ +#define INP_SYS testbench_isp_isp_css_part_is_2400_inp_sys +#define ISYS_GP_REGS testbench_isp_isp_css_part_is_2400_inp_sys_gpreg +#define ISYS_IRQ_CTRL testbench_isp_isp_css_part_is_2400_inp_sys_irq_ctrl +#define ISYS_CAP_A testbench_isp_isp_css_part_is_2400_inp_sys_capt_unit_a +#define ISYS_CAP_B testbench_isp_isp_css_part_is_2400_inp_sys_capt_unit_b +#define ISYS_CAP_C testbench_isp_isp_css_part_is_2400_inp_sys_capt_unit_c +#define ISYS_INP_BUF testbench_isp_isp_css_part_input_buffer +#define ISYS_INP_CTRL testbench_isp_isp_css_part_is_2400_inp_sys_inp_ctrl +#define ISYS_ACQ testbench_isp_isp_css_part_is_2400_inp_sys_acq_unit + +#define ISP testbench_isp_isp_css_sec_part_isp +#define SP testbench_isp_isp_css_sec_part_scp + +#define IF_PRIM testbench_isp_isp_css_part_is_2400_ifmt_ift_prim +#define IF_PRIM_B testbench_isp_isp_css_part_is_2400_ifmt_ift_prim_b +#define IF_SEC testbench_isp_isp_css_part_is_2400_ifmt_ift_sec +#define IF_SEC_MASTER testbench_isp_isp_css_part_is_2400_ifmt_ift_sec_mt_out +#define STR_TO_MEM testbench_isp_isp_css_part_is_2400_ifmt_mem_cpy +#define IFMT_GP_REGS testbench_isp_isp_css_part_is_2400_ifmt_gp_reg +#define IFMT_IRQ_CTRL testbench_isp_isp_css_part_is_2400_ifmt_irq_ctrl + +#define CSS_RECEIVER testbench_isp_isp_css_part_is_2400_inp_sys_csi_receiver + +#define TC testbench_isp_isp_css_sec_part_gpd_tc +#define GPTIMER testbench_isp_isp_css_sec_part_gpd_gptimer +#define DMA testbench_isp_isp_css_sec_part_isp_dma +#define GDC testbench_isp_isp_css_sec_part_gdc1 +#define GDC2 testbench_isp_isp_css_sec_part_gdc2 +#define IRQ_CTRL testbench_isp_isp_css_sec_part_gpd_irq_ctrl +#define GPIO testbench_isp_isp_css_sec_part_gpd_c_gpio +#define GP_REGS testbench_isp_isp_css_sec_part_gpd_gp_reg +#define ISEL_GP_REGS testbench_isp_isp_css_part_is_2400_isel_gpr +#define ISEL_IRQ_CTRL testbench_isp_isp_css_part_is_2400_isel_irq_ctrl +#define DATA_MMU testbench_isp_isp_css_sec_part_data_out_sys_c_mmu +#define ICACHE_MMU testbench_isp_isp_css_sec_part_icache_out_sys_c_mmu + +/* next is actually not FIFO but FIFO adapter, or slave to streaming adapter */ +#define ISP_SP_FIFO testbench_isp_isp_css_sec_part_fa_sp_isp +#define ISEL_FIFO testbench_isp_isp_css_part_is_2400_isel_sf_fa_in + +#define FIFO_GPF_SP testbench_isp_isp_css_sec_part_sf_fa2sp_in +#define FIFO_GPF_ISP testbench_isp_isp_css_sec_part_sf_fa2isp_in +#define FIFO_SP_GPF testbench_isp_isp_css_sec_part_sf_sp2fa_in +#define FIFO_ISP_GPF testbench_isp_isp_css_sec_part_sf_isp2fa_in + +#define DATA_OCP_MASTER testbench_isp_isp_css_sec_part_data_out_sys_cio2ocp_wide_data_out_mt +#define ICACHE_OCP_MASTER testbench_isp_isp_css_sec_part_icache_out_sys_cio2ocp_wide_data_out_mt + +#define SP_IN_FIFO testbench_isp_isp_css_sec_part_sf_fa2sp_in +#define SP_OUT_FIFO testbench_isp_isp_css_sec_part_sf_sp2fa_out +#define ISP_IN_FIFO testbench_isp_isp_css_sec_part_sf_fa2isp_in +#define ISP_OUT_FIFO testbench_isp_isp_css_sec_part_sf_isp2fa_out +#define GEN_SHORT_PACK_PORT testbench_isp_isp_css_part_is_2400_inp_sys_csi_str_mon_fa_gensh_out + +/* input_system_2401 identifiers */ +#define ISYS2401_GP_REGS testbench_isp_isp_css_part_is_2401_gpreg +#define ISYS2401_DMA testbench_isp_isp_css_part_is_2401_dma +#define ISYS2401_IRQ_CTRL testbench_isp_isp_css_part_is_2401_isys_irq_ctrl + +#define ISYS2401_CSI_RX_A testbench_isp_isp_css_part_is_2401_is_pipe_a_csi_rx +#define ISYS2401_MIPI_BE_A testbench_isp_isp_css_part_is_2401_is_pipe_a_mipi_be +#define ISYS2401_S2M_A testbench_isp_isp_css_part_is_2401_is_pipe_a_s2m +#define ISYS2401_PXG_A testbench_isp_isp_css_part_is_2401_is_pipe_a_pxlgen +#define ISYS2401_IBUF_CNTRL_A testbench_isp_isp_css_part_is_2401_is_pipe_a_ibuf_ctrl +#define ISYS2401_IRQ_CTRL_A testbench_isp_isp_css_part_is_2401_is_pipe_a_irq_ctrl_pipe + +#define ISYS2401_CSI_RX_B testbench_isp_isp_css_part_is_2401_is_pipe_b_csi_rx +#define ISYS2401_MIPI_BE_B testbench_isp_isp_css_part_is_2401_is_pipe_b_mipi_be +#define ISYS2401_S2M_B testbench_isp_isp_css_part_is_2401_is_pipe_b_s2m +#define ISYS2401_PXG_B testbench_isp_isp_css_part_is_2401_is_pipe_b_pxlgen +#define ISYS2401_IBUF_CNTRL_B testbench_isp_isp_css_part_is_2401_is_pipe_b_ibuf_ctrl +#define ISYS2401_IRQ_CTRL_B testbench_isp_isp_css_part_is_2401_is_pipe_b_irq_ctrl_pipe + +#define ISYS2401_CSI_RX_C testbench_isp_isp_css_part_is_2401_is_pipe_c_csi_rx +#define ISYS2401_MIPI_BE_C testbench_isp_isp_css_part_is_2401_is_pipe_c_mipi_be +#define ISYS2401_S2M_C testbench_isp_isp_css_part_is_2401_is_pipe_c_s2m +#define ISYS2401_PXG_C testbench_isp_isp_css_part_is_2401_is_pipe_c_pxlgen +#define ISYS2401_IBUF_CNTRL_C testbench_isp_isp_css_part_is_2401_is_pipe_c_ibuf_ctrl +#define ISYS2401_IRQ_CTRL_C testbench_isp_isp_css_part_is_2401_is_pipe_c_irq_ctrl_pipe + + +/* Testbench identifiers */ +#define DDR testbench_ddram +#define DDR_SMALL testbench_ddram_small +#define XMEM DDR +#define GPIO_ADAPTER testbench_gp_adapter +#define SIG_MONITOR testbench_sig_mon +#define DDR_SLAVE testbench_ddram_ip0 +#define DDR_SMALL_SLAVE testbench_ddram_small_ip0 +#define HOST_MASTER host_op0 + +#define CSI_SENSOR testbench_vied_sensor +#define CSI_SENSOR_GP_REGS testbench_vied_sensor_gpreg +#define CSI_STR_IN_A testbench_vied_sensor_tx_a_csi_tx_data_in +#define CSI_STR_IN_B testbench_vied_sensor_tx_b_csi_tx_data_in +#define CSI_STR_IN_C testbench_vied_sensor_tx_c_csi_tx_data_in +#define CSI_SENSOR_TX_A testbench_vied_sensor_tx_a +#define CSI_SENSOR_TX_B testbench_vied_sensor_tx_b +#define CSI_SENSOR_TX_C testbench_vied_sensor_tx_c + +#endif /* _hive_isp_css_host_ids_hrt_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_streaming_to_mipi_types_hrt.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_streaming_to_mipi_types_hrt.h new file mode 100644 index 0000000..b4211a0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_streaming_to_mipi_types_hrt.h @@ -0,0 +1,26 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _hive_isp_css_streaming_to_mipi_types_hrt_h_ +#define _hive_isp_css_streaming_to_mipi_types_hrt_h_ + +#include <streaming_to_mipi_defs.h> + +#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS)-1) +#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS)-1) + +#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS) +#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH) + +#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_types.h new file mode 100644 index 0000000..58b0e6e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_types.h @@ -0,0 +1,128 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_HIVE_TYPES_H +#define _HRT_HIVE_TYPES_H + +#include "version.h" +#include "defs.h" + +#ifndef HRTCAT3 +#define _HRTCAT3(m,n,o) m##n##o +#define HRTCAT3(m,n,o) _HRTCAT3(m,n,o) +#endif + +#ifndef HRTCAT4 +#define _HRTCAT4(m,n,o,p) m##n##o##p +#define HRTCAT4(m,n,o,p) _HRTCAT4(m,n,o,p) +#endif + +#ifndef HRTMIN +#define HRTMIN(a,b) (((a)<(b))?(a):(b)) +#endif + +#ifndef HRTMAX +#define HRTMAX(a,b) (((a)>(b))?(a):(b)) +#endif + +/* boolean data type */ +typedef unsigned int hive_bool; +#define hive_false 0 +#define hive_true 1 + +typedef char hive_int8; +typedef short hive_int16; +typedef int hive_int32; +typedef long long hive_int64; + +typedef unsigned char hive_uint8; +typedef unsigned short hive_uint16; +typedef unsigned int hive_uint32; +typedef unsigned long long hive_uint64; + +/* by default assume 32 bit master port (both data and address) */ +#ifndef HRT_DATA_WIDTH +#define HRT_DATA_WIDTH 32 +#endif +#ifndef HRT_ADDRESS_WIDTH +#define HRT_ADDRESS_WIDTH 32 +#endif + +#define HRT_DATA_BYTES (HRT_DATA_WIDTH/8) +#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH/8) + +#if HRT_DATA_WIDTH == 64 +typedef hive_uint64 hrt_data; +#elif HRT_DATA_WIDTH == 32 +typedef hive_uint32 hrt_data; +#else +#error data width not supported +#endif + +#if HRT_ADDRESS_WIDTH == 64 +typedef hive_uint64 hrt_address; +#elif HRT_ADDRESS_WIDTH == 32 +typedef hive_uint32 hrt_address; +#else +#error adddres width not supported +#endif + +/* The SP side representation of an HMM virtual address */ +typedef hive_uint32 hrt_vaddress; + +/* use 64 bit addresses in simulation, where possible */ +typedef hive_uint64 hive_sim_address; + +/* below is for csim, not for hrt, rename and move this elsewhere */ + +typedef unsigned int hive_uint; +typedef hive_uint32 hive_address; +typedef hive_address hive_slave_address; +typedef hive_address hive_mem_address; + +/* MMIO devices */ +typedef hive_uint hive_mmio_id; +typedef hive_mmio_id hive_slave_id; +typedef hive_mmio_id hive_port_id; +typedef hive_mmio_id hive_master_id; +typedef hive_mmio_id hive_mem_id; +typedef hive_mmio_id hive_dev_id; +typedef hive_mmio_id hive_fifo_id; + +typedef hive_uint hive_hier_id; +typedef hive_hier_id hive_device_id; +typedef hive_device_id hive_proc_id; +typedef hive_device_id hive_cell_id; +typedef hive_device_id hive_host_id; +typedef hive_device_id hive_bus_id; +typedef hive_device_id hive_bridge_id; +typedef hive_device_id hive_fifo_adapter_id; +typedef hive_device_id hive_custom_device_id; + +typedef hive_uint hive_slot_id; +typedef hive_uint hive_fu_id; +typedef hive_uint hive_reg_file_id; +typedef hive_uint hive_reg_id; + +/* Streaming devices */ +typedef hive_uint hive_outport_id; +typedef hive_uint hive_inport_id; + +typedef hive_uint hive_msink_id; + +/* HRT specific */ +typedef char* hive_program; +typedef char* hive_function; + +#endif /* _HRT_HIVE_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/ibuf_cntrl_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/ibuf_cntrl_defs.h new file mode 100644 index 0000000..f82bb79 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/ibuf_cntrl_defs.h @@ -0,0 +1,138 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _ibuf_cntrl_defs_h_ +#define _ibuf_cntrl_defs_h_ + +#include <stream2mmio_defs.h> +#include <dma_v2_defs.h> + +#define _IBUF_CNTRL_REG_ALIGN 4 + /* alignment of register banks, first bank are shared configuration and status registers: */ +#define _IBUF_CNTRL_PROC_REG_ALIGN 32 + + /* the actual amount of configuration registers per proc: */ +#define _IBUF_CNTRL_CONFIG_REGS_PER_PROC 18 + /* the actual amount of shared configuration registers: */ +#define _IBUF_CNTRL_CONFIG_REGS_NO_PROC 0 + + /* the actual amount of status registers per proc */ +#define _IBUF_CNTRL_STATUS_REGS_PER_PROC (_IBUF_CNTRL_CONFIG_REGS_PER_PROC + 10) + /* the actual amount shared status registers */ +#define _IBUF_CNTRL_STATUS_REGS_NO_PROC (_IBUF_CNTRL_CONFIG_REGS_NO_PROC + 2) + + /* time out bits, maximum time out value is 2^_IBUF_CNTRL_TIME_OUT_BITS - 1 */ +#define _IBUF_CNTRL_TIME_OUT_BITS 5 + +/* command token definition */ +#define _IBUF_CNTRL_CMD_TOKEN_LSB 0 +#define _IBUF_CNTRL_CMD_TOKEN_MSB 1 + +/* Str2MMIO defines */ +#define _IBUF_CNTRL_STREAM2MMIO_CMD_TOKEN_MSB _STREAM2MMIO_CMD_TOKEN_CMD_MSB +#define _IBUF_CNTRL_STREAM2MMIO_CMD_TOKEN_LSB _STREAM2MMIO_CMD_TOKEN_CMD_LSB +#define _IBUF_CNTRL_STREAM2MMIO_NUM_ITEMS_BITS _STREAM2MMIO_PACK_NUM_ITEMS_BITS +#define _IBUF_CNTRL_STREAM2MMIO_ACK_EOF_BIT _STREAM2MMIO_PACK_ACK_EOF_BIT +#define _IBUF_CNTRL_STREAM2MMIO_ACK_TOKEN_VALID_BIT _STREAM2MMIO_ACK_TOKEN_VALID_BIT + +/* acknowledge token definition */ +#define _IBUF_CNTRL_ACK_TOKEN_STORES_IDX 0 +#define _IBUF_CNTRL_ACK_TOKEN_STORES_BITS 15 +#define _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX (_IBUF_CNTRL_ACK_TOKEN_STORES_BITS + _IBUF_CNTRL_ACK_TOKEN_STORES_IDX) +#define _IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS _STREAM2MMIO_PACK_NUM_ITEMS_BITS +#define _IBUF_CNTRL_ACK_TOKEN_LSB _IBUF_CNTRL_ACK_TOKEN_STORES_IDX +#define _IBUF_CNTRL_ACK_TOKEN_MSB (_IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS + _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX - 1) + /* bit 31 indicates a valid ack: */ +#define _IBUF_CNTRL_ACK_TOKEN_VALID_BIT (_IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS + _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX) + + +/*shared registers:*/ +#define _IBUF_CNTRL_RECALC_WORDS_STATUS 0 +#define _IBUF_CNTRL_ARBITERS_STATUS 1 + +#define _IBUF_CNTRL_SET_CRUN 2 /* NO PHYSICAL REGISTER!! Only used in HSS model */ + + +/*register addresses for each proc: */ +#define _IBUF_CNTRL_CMD 0 +#define _IBUF_CNTRL_ACK 1 + + /* number of items (packets or words) per frame: */ +#define _IBUF_CNTRL_NUM_ITEMS_PER_STORE 2 + + /* number of stores (packets or words) per store/buffer: */ +#define _IBUF_CNTRL_NUM_STORES_PER_FRAME 3 + + /* the channel and command in the DMA */ +#define _IBUF_CNTRL_DMA_CHANNEL 4 +#define _IBUF_CNTRL_DMA_CMD 5 + + /* the start address and stride of the buffers */ +#define _IBUF_CNTRL_BUFFER_START_ADDRESS 6 +#define _IBUF_CNTRL_BUFFER_STRIDE 7 +#define _IBUF_CNTRL_BUFFER_END_ADDRESS 8 + + /* destination start address, stride and end address; should be the same as in the DMA */ +#define _IBUF_CNTRL_DEST_START_ADDRESS 9 +#define _IBUF_CNTRL_DEST_STRIDE 10 +#define _IBUF_CNTRL_DEST_END_ADDRESS 11 + + /* send a frame sync or not, default 1 */ +#define _IBUF_CNTRL_SYNC_FRAME 12 + + /* str2mmio cmds */ +#define _IBUF_CNTRL_STR2MMIO_SYNC_CMD 13 +#define _IBUF_CNTRL_STR2MMIO_STORE_CMD 14 + + /* num elems p word*/ +#define _IBUF_CNTRL_SHIFT_ITEMS 15 +#define _IBUF_CNTRL_ELEMS_P_WORD_IBUF 16 +#define _IBUF_CNTRL_ELEMS_P_WORD_DEST 17 + + + /* STATUS */ + /* current frame and stores in buffer */ +#define _IBUF_CNTRL_CUR_STORES 18 +#define _IBUF_CNTRL_CUR_ACKS 19 + + /* current buffer and destination address for DMA cmd's */ +#define _IBUF_CNTRL_CUR_S2M_IBUF_ADDR 20 +#define _IBUF_CNTRL_CUR_DMA_IBUF_ADDR 21 +#define _IBUF_CNTRL_CUR_DMA_DEST_ADDR 22 +#define _IBUF_CNTRL_CUR_ISP_DEST_ADDR 23 + +#define _IBUF_CNTRL_CUR_NR_DMA_CMDS_SEND 24 + +#define _IBUF_CNTRL_MAIN_CNTRL_STATE 25 +#define _IBUF_CNTRL_DMA_SYNC_STATE 26 +#define _IBUF_CNTRL_ISP_SYNC_STATE 27 + + +/*Commands: */ +#define _IBUF_CNTRL_CMD_STORE_FRAME_IDX 0 +#define _IBUF_CNTRL_CMD_ONLINE_IDX 1 + + /* initialize, copy st_addr to cur_addr etc */ +#define _IBUF_CNTRL_CMD_INITIALIZE 0 + + /* store an online frame (sync with ISP, use end cfg start, stride and end address: */ +#define _IBUF_CNTRL_CMD_STORE_ONLINE_FRAME ((1<<_IBUF_CNTRL_CMD_STORE_FRAME_IDX) | (1<<_IBUF_CNTRL_CMD_ONLINE_IDX)) + + /* store an offline frame (don't sync with ISP, requires start address as 2nd token, no end address: */ +#define _IBUF_CNTRL_CMD_STORE_OFFLINE_FRAME (1<<_IBUF_CNTRL_CMD_STORE_FRAME_IDX) + + /* false command token, should be different then commands. Use online bit, not store frame: */ +#define _IBUF_CNTRL_FALSE_ACK 2 + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/if_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/if_defs.h new file mode 100644 index 0000000..7d39e45 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/if_defs.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IF_DEFS_H +#define _IF_DEFS_H + +#define HIVE_IF_FRAME_REQUEST 0xA000 +#define HIVE_IF_LINES_REQUEST 0xB000 +#define HIVE_IF_VECTORS_REQUEST 0xC000 + +#endif /* _IF_DEFS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_formatter_subsystem_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_formatter_subsystem_defs.h new file mode 100644 index 0000000..16bfe1d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_formatter_subsystem_defs.h @@ -0,0 +1,53 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _if_subsystem_defs_h +#define _if_subsystem_defs_h__ + +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 0 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_1 1 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_2 2 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_3 3 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8 +#define HIVE_IFMT_GP_REGS_SRST_IDX 9 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10 + +#define HIVE_IFMT_GP_REGS_CH_ID_FMT_TYPE_IDX 11 + +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_BASE HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 + +/* order of the input bits for the ifmt irq controller */ +#define HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID 0 +#define HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID 1 +#define HIVE_IFMT_IRQ_IFT_SEC_BIT_ID 2 +#define HIVE_IFMT_IRQ_MEM_CPY_BIT_ID 3 +#define HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID 4 + +/* order of the input bits for the ifmt Soft reset register */ +#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_BIT_IDX 0 +#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_B_BIT_IDX 1 +#define HIVE_IFMT_GP_REGS_SRST_IFT_SEC_BIT_IDX 2 +#define HIVE_IFMT_GP_REGS_SRST_MEM_CPY_BIT_IDX 3 + +/* order of the input bits for the ifmt Soft reset register */ +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_BIT_IDX 0 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_B_BIT_IDX 1 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_SEC_BIT_IDX 2 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_MEM_CPY_BIT_IDX 3 + +#endif /* _if_subsystem_defs_h__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_selector_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_selector_defs.h new file mode 100644 index 0000000..87fbf82 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_selector_defs.h @@ -0,0 +1,89 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_selector_defs_h +#define _input_selector_defs_h + +#ifndef HIVE_ISP_ISEL_SEL_BITS +#define HIVE_ISP_ISEL_SEL_BITS 2 +#endif + +#ifndef HIVE_ISP_CH_ID_BITS +#define HIVE_ISP_CH_ID_BITS 2 +#endif + +#ifndef HIVE_ISP_FMT_TYPE_BITS +#define HIVE_ISP_FMT_TYPE_BITS 5 +#endif + +/* gp_register register id's -- Outputs */ +#define HIVE_ISEL_GP_REGS_SYNCGEN_ENABLE_IDX 0 +#define HIVE_ISEL_GP_REGS_SYNCGEN_FREE_RUNNING_IDX 1 +#define HIVE_ISEL_GP_REGS_SYNCGEN_PAUSE_IDX 2 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5 +#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6 +#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7 + +#define HIVE_ISEL_GP_REGS_SOF_IDX 8 +#define HIVE_ISEL_GP_REGS_EOF_IDX 9 +#define HIVE_ISEL_GP_REGS_SOL_IDX 10 +#define HIVE_ISEL_GP_REGS_EOL_IDX 11 + +#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12 +#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13 +#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14 + +#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15 +#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16 +#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17 +#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18 +#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19 +#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20 +#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21 +#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22 +#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23 +#define HIVE_ISEL_GP_REGS_TPG_G1_IDX 24 +#define HIVE_ISEL_GP_REGS_TPG_B1_IDX 25 +#define HIVE_ISEL_GP_REGS_TPG_R2_IDX 26 +#define HIVE_ISEL_GP_REGS_TPG_G2_IDX 27 +#define HIVE_ISEL_GP_REGS_TPG_B2_IDX 28 + + +#define HIVE_ISEL_GP_REGS_CH_ID_IDX 29 +#define HIVE_ISEL_GP_REGS_FMT_TYPE_IDX 30 +#define HIVE_ISEL_GP_REGS_DATA_SEL_IDX 31 +#define HIVE_ISEL_GP_REGS_SBAND_SEL_IDX 32 +#define HIVE_ISEL_GP_REGS_SYNC_SEL_IDX 33 +#define HIVE_ISEL_GP_REGS_SRST_IDX 37 + +#define HIVE_ISEL_GP_REGS_SRST_SYNCGEN_BIT 0 +#define HIVE_ISEL_GP_REGS_SRST_PRBS_BIT 1 +#define HIVE_ISEL_GP_REGS_SRST_TPG_BIT 2 +#define HIVE_ISEL_GP_REGS_SRST_FIFO_BIT 3 + +/* gp_register register id's -- Inputs */ +#define HIVE_ISEL_GP_REGS_SYNCGEN_HOR_CNT_IDX 34 +#define HIVE_ISEL_GP_REGS_SYNCGEN_VER_CNT_IDX 35 +#define HIVE_ISEL_GP_REGS_SYNCGEN_FRAMES_CNT_IDX 36 + +/* irq sources isel irq controller */ +#define HIVE_ISEL_IRQ_SYNC_GEN_SOF_BIT_ID 0 +#define HIVE_ISEL_IRQ_SYNC_GEN_EOF_BIT_ID 1 +#define HIVE_ISEL_IRQ_SYNC_GEN_SOL_BIT_ID 2 +#define HIVE_ISEL_IRQ_SYNC_GEN_EOL_BIT_ID 3 +#define HIVE_ISEL_IRQ_NUM_IRQS 4 + +#endif /* _input_selector_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_switch_2400_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_switch_2400_defs.h new file mode 100644 index 0000000..20a13c4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_switch_2400_defs.h @@ -0,0 +1,30 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_switch_2400_defs_h +#define _input_switch_2400_defs_h + +#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id)*2) + ((fmt_type)>=16)) +#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type)%16) * 2) + +#define HIVE_INPUT_SWITCH_SELECT_NO_OUTPUT 0 +#define HIVE_INPUT_SWITCH_SELECT_IF_PRIM 1 +#define HIVE_INPUT_SWITCH_SELECT_IF_SEC 2 +#define HIVE_INPUT_SWITCH_SELECT_STR_TO_MEM 3 +#define HIVE_INPUT_SWITCH_VSELECT_NO_OUTPUT 0 +#define HIVE_INPUT_SWITCH_VSELECT_IF_PRIM 1 +#define HIVE_INPUT_SWITCH_VSELECT_IF_SEC 2 +#define HIVE_INPUT_SWITCH_VSELECT_STR_TO_MEM 4 + +#endif /* _input_switch_2400_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_ctrl_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_ctrl_defs.h new file mode 100644 index 0000000..a7f0ca8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_ctrl_defs.h @@ -0,0 +1,254 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_system_ctrl_defs_h +#define _input_system_ctrl_defs_h + +#define _INPUT_SYSTEM_CTRL_REG_ALIGN 4 /* assuming 32 bit control bus width */ + +/* --------------------------------------------------*/ + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +// Number of registers +#define ISYS_CTRL_NOF_REGS 23 + +// Register id's of MMIO slave accesible registers +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID 0 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID 1 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID 2 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID 3 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID 4 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID 5 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID 6 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID 7 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID 8 +#define ISYS_CTRL_ACQ_START_ADDR_REG_ID 9 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID 10 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID 11 +#define ISYS_CTRL_INIT_REG_ID 12 +#define ISYS_CTRL_LAST_COMMAND_REG_ID 13 +#define ISYS_CTRL_NEXT_COMMAND_REG_ID 14 +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID 15 +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID 16 +#define ISYS_CTRL_FSM_STATE_INFO_REG_ID 17 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID 18 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID 19 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID 20 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID 21 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID 22 + + +/* register reset value */ +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3 +#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL 0 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define ISYS_CTRL_INIT_REG_RSTVAL 0 +#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0 + +/* register width value */ +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9 +#define ISYS_CTRL_INIT_REG_WIDTH 3 +#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH 32 /* slave data width */ +#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH 32 +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH 1 + +/* bit definitions */ + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ + +/* +InpSysCaptFramesAcq 1/0 [3:0] - 'b0000 +[7:4] - CaptPortId, + CaptA-'b0000 + CaptB-'b0001 + CaptC-'b0010 +[31:16] - NOF_frames +InpSysCaptFrameExt 2/0 [3:0] - 'b0001' +[7:4] - CaptPortId, + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + + 2/1 [31:0] - external capture address +InpSysAcqFrame 2/0 [3:0] - 'b0010, +[31:4] - NOF_ext_mem_words + 2/1 [31:0] - external memory read start address +InpSysOverruleON 1/0 [3:0] - 'b0011, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysOverruleOFF 1/0 [3:0] - 'b0100, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysOverruleCmd 2/0 [3:0] - 'b0101, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + + 2/1 [31:0] - command token value for port opid + + +acknowledge tokens: + +InpSysAckCFA 1/0 [3:0] - 'b0000 + [7:4] - CaptPortId, + CaptA-'b0000 + CaptB- 'b0001 + CaptC-'b0010 + [31:16] - NOF_frames +InpSysAckCFE 1/0 [3:0] - 'b0001' +[7:4] - CaptPortId, + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + +InpSysAckAF 1/0 [3:0] - 'b0010 +InpSysAckOverruleON 1/0 [3:0] - 'b0011, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysAckOverruleOFF 1/0 [3:0] - 'b0100, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysAckOverrule 2/0 [3:0] - 'b0101, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + + 2/1 [31:0] - acknowledge token value from port opid + + + +*/ + + +/* Command and acknowledge tokens IDs */ +#define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID 0 /* 0000b */ +#define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID 1 /* 0001b */ +#define ISYS_CTRL_ACQ_FRAME_TOKEN_ID 2 /* 0010b */ +#define ISYS_CTRL_OVERRULE_ON_TOKEN_ID 3 /* 0011b */ +#define ISYS_CTRL_OVERRULE_OFF_TOKEN_ID 4 /* 0100b */ +#define ISYS_CTRL_OVERRULE_TOKEN_ID 5 /* 0101b */ + +#define ISYS_CTRL_ACK_CFA_TOKEN_ID 0 +#define ISYS_CTRL_ACK_CFE_TOKEN_ID 1 +#define ISYS_CTRL_ACK_AF_TOKEN_ID 2 +#define ISYS_CTRL_ACK_OVERRULE_ON_TOKEN_ID 3 +#define ISYS_CTRL_ACK_OVERRULE_OFF_TOKEN_ID 4 +#define ISYS_CTRL_ACK_OVERRULE_TOKEN_ID 5 +#define ISYS_CTRL_ACK_DEVICE_ERROR_TOKEN_ID 6 + +#define ISYS_CTRL_TOKEN_ID_MSB 3 +#define ISYS_CTRL_TOKEN_ID_LSB 0 +#define ISYS_CTRL_PORT_ID_TOKEN_MSB 7 +#define ISYS_CTRL_PORT_ID_TOKEN_LSB 4 +#define ISYS_CTRL_NOF_CAPT_TOKEN_MSB 31 +#define ISYS_CTRL_NOF_CAPT_TOKEN_LSB 16 +#define ISYS_CTRL_NOF_EXT_TOKEN_MSB 31 +#define ISYS_CTRL_NOF_EXT_TOKEN_LSB 8 + +#define ISYS_CTRL_TOKEN_ID_IDX 0 +#define ISYS_CTRL_TOKEN_ID_BITS (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1) +#define ISYS_CTRL_PORT_ID_IDX (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS) +#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB +1) +#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB +#define ISYS_CTRL_NOF_CAPT_BITS (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1) +#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB +#define ISYS_CTRL_NOF_EXT_BITS (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1) + +#define ISYS_CTRL_PORT_ID_CAPT_A 0 /* device ID for capture unit A */ +#define ISYS_CTRL_PORT_ID_CAPT_B 1 /* device ID for capture unit B */ +#define ISYS_CTRL_PORT_ID_CAPT_C 2 /* device ID for capture unit C */ +#define ISYS_CTRL_PORT_ID_ACQUISITION 3 /* device ID for acquistion unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_A 4 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_B 5 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_C 6 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_ACQ 7 /* device ID for dma unit */ + +#define ISYS_CTRL_NO_ACQ_ACK 16 /* no ack from acquisition unit */ +#define ISYS_CTRL_NO_DMA_ACK 0 +#define ISYS_CTRL_NO_CAPT_ACK 16 + +#endif /* _input_system_ctrl_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_defs.h new file mode 100644 index 0000000..ae62163 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_defs.h @@ -0,0 +1,126 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_system_defs_h +#define _input_system_defs_h + +/* csi controller modes */ +#define HIVE_CSI_CONFIG_MAIN 0 +#define HIVE_CSI_CONFIG_STEREO1 4 +#define HIVE_CSI_CONFIG_STEREO2 8 + +/* general purpose register IDs */ + +/* Stream Multicast select modes */ +#define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0 +#define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1 +#define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2 + +/* Stream Mux select modes */ +#define HIVE_ISYS_GPREG_MUX_IDX 3 + +/* streaming monitor status and control */ +#define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4 +#define HIVE_ISYS_GPREG_STRMON_COND_IDX 5 +#define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6 +#define HIVE_ISYS_GPREG_SRST_IDX 7 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8 +#define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9 +#define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10 + +/* Bit numbers of the soft reset register */ +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0 +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1 +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5 +#define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6 +#define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7 +#define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8 +#define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9 +/* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */ +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */ +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14 +/* -- */ +#define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15 +#define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16 +#define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17 +#define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv +#define HIVE_ISYS_GPREG_SRST_DMA_BIT 19 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23 +#define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24 + +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5 + +/* streaming monitor port id's */ +#define HIVE_ISYS_STR_MON_PORT_CAPA 0 +#define HIVE_ISYS_STR_MON_PORT_CAPB 1 +#define HIVE_ISYS_STR_MON_PORT_CAPC 2 +#define HIVE_ISYS_STR_MON_PORT_ACQ 3 +#define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4 +#define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5 +#define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6 +#define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7 +#define HIVE_ISYS_STR_MON_PORT_PIXA 8 +#define HIVE_ISYS_STR_MON_PORT_PIXB 9 + +/* interrupt bit ID's */ +#define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0 +#define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1 +#define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2 +#define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3 +#define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4 +#define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5 +#define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6 +#define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/ +#define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8 +#define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/ +#define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10 +#define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/ +#define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12 +/*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/ +#define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13 +#define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14 +#define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15 +#define HIVE_ISYS_IRQ_CIO2AHB 16 +#define HIVE_ISYS_IRQ_DMA_BIT_ID 17 +#define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18 +#define HIVE_ISYS_IRQ_NUM_BITS 19 + +/* DMA */ +#define HIVE_ISYS_DMA_CHANNEL 0 +#define HIVE_ISYS_DMA_IBUF_DDR_CONN 0 +#define HIVE_ISYS_DMA_HEIGHT 1 +#define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */ +#define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */ +#define HIVE_ISYS_DMA_CROP 0 /* no cropping */ +#define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */ + +#endif /* _input_system_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/irq_controller_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/irq_controller_defs.h new file mode 100644 index 0000000..ec6dd44 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/irq_controller_defs.h @@ -0,0 +1,28 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _irq_controller_defs_h +#define _irq_controller_defs_h + +#define _HRT_IRQ_CONTROLLER_EDGE_REG_IDX 0 +#define _HRT_IRQ_CONTROLLER_MASK_REG_IDX 1 +#define _HRT_IRQ_CONTROLLER_STATUS_REG_IDX 2 +#define _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX 3 +#define _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX 4 +#define _HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX 5 +#define _HRT_IRQ_CONTROLLER_STR_OUT_ENABLE_REG_IDX 6 + +#define _HRT_IRQ_CONTROLLER_REG_ALIGN 4 + +#endif /* _irq_controller_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2400_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2400_support.h new file mode 100644 index 0000000..e00bc84 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2400_support.h @@ -0,0 +1,38 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp2400_support_h +#define _isp2400_support_h + +#ifndef ISP2400_VECTOR_TYPES +/* This typedef is to be able to include hive header files + in the host code which is useful in crun */ +typedef char *tmemvectors, *tmemvectoru, *tvector; +#endif + +#define hrt_isp_vamem1_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem1), addr, val) +#define hrt_isp_vamem2_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem2), addr, val) + +#define hrt_isp_dmem(cell) HRT_PROC_TYPE_PROP(cell, _base_dmem) +#define hrt_isp_vmem(cell) HRT_PROC_TYPE_PROP(cell, _simd_vmem) + +#define hrt_isp_dmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_dmem(cell)) +#define hrt_isp_vmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_vmem(cell)) + +#if ISP_HAS_HIST + #define hrt_isp_hist(cell) HRT_PROC_TYPE_PROP(cell, _simd_histogram) + #define hrt_isp_hist_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_hist(cell)) +#endif + +#endif /* _isp2400_support_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2401_mamoiada_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2401_mamoiada_params.h new file mode 100644 index 0000000..033e23b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2401_mamoiada_params.h @@ -0,0 +1,258 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Version */ +#define RTL_VERSION + +/* Cell name */ +#define ISP_CELL_TYPE isp2401_mamoiada +#define ISP_VMEM simd_vmem +#define _HRT_ISP_VMEM isp2401_mamoiada_simd_vmem + +/* instruction pipeline depth */ +#define ISP_BRANCHDELAY 5 + +/* bus */ +#define ISP_BUS_WIDTH 32 +#define ISP_BUS_ADDR_WIDTH 32 +#define ISP_BUS_BURST_SIZE 1 + +/* data-path */ +#define ISP_SCALAR_WIDTH 32 +#define ISP_SLICE_NELEMS 4 +#define ISP_VEC_NELEMS 64 +#define ISP_VEC_ELEMBITS 14 +#define ISP_VEC_ELEM8BITS 16 +#define ISP_CLONE_DATAPATH_IS_16 1 + +/* memories */ +#define ISP_DMEM_DEPTH 4096 +#define ISP_DMEM_BSEL_DOWNSAMPLE 8 +#define ISP_VMEM_DEPTH 3072 +#define ISP_VMEM_BSEL_DOWNSAMPLE 8 +#define ISP_VMEM_ELEMBITS 14 +#define ISP_VMEM_ELEM_PRECISION 14 +#define ISP_VMEM_IS_BAMEM 1 +#if ISP_VMEM_IS_BAMEM + #define ISP_VMEM_BAMEM_MAX_BOI_HEIGHT 8 + #define ISP_VMEM_BAMEM_LATENCY 5 + #define ISP_VMEM_BAMEM_BANK_NARROWING_FACTOR 2 + #define ISP_VMEM_BAMEM_NR_DATA_PLANES 8 + #define ISP_VMEM_BAMEM_NR_CFG_REGISTERS 16 + #define ISP_VMEM_BAMEM_LININT 0 + #define ISP_VMEM_BAMEM_DAP_BITS 3 + #define ISP_VMEM_BAMEM_LININT_FRAC_BITS 0 + #define ISP_VMEM_BAMEM_PID_BITS 3 + #define ISP_VMEM_BAMEM_OFFSET_BITS 19 + #define ISP_VMEM_BAMEM_ADDRESS_BITS 25 + #define ISP_VMEM_BAMEM_RID_BITS 4 + #define ISP_VMEM_BAMEM_TRANSPOSITION 1 + #define ISP_VMEM_BAMEM_VEC_PLUS_SLICE 1 + #define ISP_VMEM_BAMEM_ARB_SERVICE_CYCLE_BITS 1 + #define ISP_VMEM_BAMEM_LUT_ELEMS 16 + #define ISP_VMEM_BAMEM_LUT_ADDR_WIDTH 14 + #define ISP_VMEM_BAMEM_HALF_BLOCK_WRITE 1 + #define ISP_VMEM_BAMEM_SMART_FETCH 1 + #define ISP_VMEM_BAMEM_BIG_ENDIANNESS 0 +#endif /* ISP_VMEM_IS_BAMEM */ +#define ISP_PMEM_DEPTH 2048 +#define ISP_PMEM_WIDTH 640 +#define ISP_VAMEM_ADDRESS_BITS 12 +#define ISP_VAMEM_ELEMBITS 12 +#define ISP_VAMEM_DEPTH 2048 +#define ISP_VAMEM_ALIGNMENT 2 +#define ISP_VA_ADDRESS_WIDTH 896 +#define ISP_VEC_VALSU_LATENCY ISP_VEC_NELEMS +#define ISP_HIST_ADDRESS_BITS 12 +#define ISP_HIST_ALIGNMENT 4 +#define ISP_HIST_COMP_IN_PREC 12 +#define ISP_HIST_DEPTH 1024 +#define ISP_HIST_WIDTH 24 +#define ISP_HIST_COMPONENTS 4 + +/* program counter */ +#define ISP_PC_WIDTH 13 + +/* Template switches */ +#define ISP_SHIELD_INPUT_DMEM 0 +#define ISP_SHIELD_OUTPUT_DMEM 1 +#define ISP_SHIELD_INPUT_VMEM 0 +#define ISP_SHIELD_OUTPUT_VMEM 0 +#define ISP_SHIELD_INPUT_PMEM 1 +#define ISP_SHIELD_OUTPUT_PMEM 1 +#define ISP_SHIELD_INPUT_HIST 1 +#define ISP_SHIELD_OUTPUT_HIST 1 +/* When LUT is select the shielding is always on */ +#define ISP_SHIELD_INPUT_VAMEM 1 +#define ISP_SHIELD_OUTPUT_VAMEM 1 + +#define ISP_HAS_IRQ 1 +#define ISP_HAS_SOFT_RESET 1 +#define ISP_HAS_VEC_DIV 0 +#define ISP_HAS_VFU_W_2O 1 +#define ISP_HAS_DEINT3 1 +#define ISP_HAS_LUT 1 +#define ISP_HAS_HIST 1 +#define ISP_HAS_VALSU 1 +#define ISP_HAS_3rdVALSU 1 +#define ISP_VRF1_HAS_2P 1 + +#define ISP_SRU_GUARDING 1 +#define ISP_VLSU_GUARDING 1 + +#define ISP_VRF_RAM 1 +#define ISP_SRF_RAM 1 + +#define ISP_SPLIT_VMUL_VADD_IS 0 +#define ISP_RFSPLIT_FPGA 0 + +/* RSN or Bus pipelining */ +#define ISP_RSN_PIPE 1 +#define ISP_VSF_BUS_PIPE 0 + +/* extra slave port to vmem */ +#define ISP_IF_VMEM 0 +#define ISP_GDC_VMEM 0 + +/* Streaming ports */ +#define ISP_IF 1 +#define ISP_IF_B 1 +#define ISP_GDC 1 +#define ISP_SCL 1 +#define ISP_GPFIFO 1 +#define ISP_SP 1 + +/* Removing Issue Slot(s) */ +#define ISP_HAS_NOT_SIMD_IS2 0 +#define ISP_HAS_NOT_SIMD_IS3 0 +#define ISP_HAS_NOT_SIMD_IS4 0 +#define ISP_HAS_NOT_SIMD_IS4_VADD 0 +#define ISP_HAS_NOT_SIMD_IS5 0 +#define ISP_HAS_NOT_SIMD_IS6 0 +#define ISP_HAS_NOT_SIMD_IS7 0 +#define ISP_HAS_NOT_SIMD_IS8 0 + +/* ICache */ +#define ISP_ICACHE 1 +#define ISP_ICACHE_ONLY 0 +#define ISP_ICACHE_PREFETCH 1 +#define ISP_ICACHE_INDEX_BITS 8 +#define ISP_ICACHE_SET_BITS 5 +#define ISP_ICACHE_BLOCKS_PER_SET_BITS 1 + +/* Experimental Flags */ +#define ISP_EXP_1 0 +#define ISP_EXP_2 0 +#define ISP_EXP_3 0 +#define ISP_EXP_4 0 +#define ISP_EXP_5 0 +#define ISP_EXP_6 0 + +/* Derived values */ +#define ISP_LOG2_PMEM_WIDTH 10 +#define ISP_VEC_WIDTH 896 +#define ISP_SLICE_WIDTH 56 +#define ISP_VMEM_WIDTH 896 +#define ISP_VMEM_ALIGN 128 +#if ISP_VMEM_IS_BAMEM + #define ISP_VMEM_ALIGN_ELEM 2 +#endif /* ISP_VMEM_IS_BAMEM */ +#define ISP_SIMDLSU 1 +#define ISP_LSU_IMM_BITS 12 + +/* convenient shortcuts for software*/ +#define ISP_NWAY ISP_VEC_NELEMS +#define NBITS ISP_VEC_ELEMBITS + +#define _isp_ceil_div(a,b) (((a)+(b)-1)/(b)) + +#ifdef C_RUN +#define ISP_VEC_ALIGN (_isp_ceil_div(ISP_VEC_WIDTH, 64)*8) +#else +#define ISP_VEC_ALIGN ISP_VMEM_ALIGN +#endif + +/* HRT specific vector support */ +#define isp2401_mamoiada_vector_alignment ISP_VEC_ALIGN +#define isp2401_mamoiada_vector_elem_bits ISP_VMEM_ELEMBITS +#define isp2401_mamoiada_vector_elem_precision ISP_VMEM_ELEM_PRECISION +#define isp2401_mamoiada_vector_num_elems ISP_VEC_NELEMS + +/* register file sizes */ +#define ISP_RF0_SIZE 64 +#define ISP_RF1_SIZE 16 +#define ISP_RF2_SIZE 64 +#define ISP_RF3_SIZE 4 +#define ISP_RF4_SIZE 64 +#define ISP_RF5_SIZE 16 +#define ISP_RF6_SIZE 16 +#define ISP_RF7_SIZE 16 +#define ISP_RF8_SIZE 16 +#define ISP_RF9_SIZE 16 +#define ISP_RF10_SIZE 16 +#define ISP_RF11_SIZE 16 +#define ISP_VRF1_SIZE 32 +#define ISP_VRF2_SIZE 32 +#define ISP_VRF3_SIZE 32 +#define ISP_VRF4_SIZE 32 +#define ISP_VRF5_SIZE 32 +#define ISP_VRF6_SIZE 32 +#define ISP_VRF7_SIZE 32 +#define ISP_VRF8_SIZE 32 +#define ISP_SRF1_SIZE 4 +#define ISP_SRF2_SIZE 64 +#define ISP_SRF3_SIZE 64 +#define ISP_SRF4_SIZE 32 +#define ISP_SRF5_SIZE 64 +#define ISP_FRF0_SIZE 16 +#define ISP_FRF1_SIZE 4 +#define ISP_FRF2_SIZE 16 +#define ISP_FRF3_SIZE 4 +#define ISP_FRF4_SIZE 4 +#define ISP_FRF5_SIZE 8 +#define ISP_FRF6_SIZE 4 +/* register file read latency */ +#define ISP_VRF1_READ_LAT 1 +#define ISP_VRF2_READ_LAT 1 +#define ISP_VRF3_READ_LAT 1 +#define ISP_VRF4_READ_LAT 1 +#define ISP_VRF5_READ_LAT 1 +#define ISP_VRF6_READ_LAT 1 +#define ISP_VRF7_READ_LAT 1 +#define ISP_VRF8_READ_LAT 1 +#define ISP_SRF1_READ_LAT 1 +#define ISP_SRF2_READ_LAT 1 +#define ISP_SRF3_READ_LAT 1 +#define ISP_SRF4_READ_LAT 1 +#define ISP_SRF5_READ_LAT 1 +#define ISP_SRF5_READ_LAT 1 +/* immediate sizes */ +#define ISP_IS1_IMM_BITS 14 +#define ISP_IS2_IMM_BITS 13 +#define ISP_IS3_IMM_BITS 14 +#define ISP_IS4_IMM_BITS 14 +#define ISP_IS5_IMM_BITS 9 +#define ISP_IS6_IMM_BITS 16 +#define ISP_IS7_IMM_BITS 9 +#define ISP_IS8_IMM_BITS 16 +#define ISP_IS9_IMM_BITS 11 +/* fifo depths */ +#define ISP_IF_FIFO_DEPTH 0 +#define ISP_IF_B_FIFO_DEPTH 0 +#define ISP_DMA_FIFO_DEPTH 0 +#define ISP_OF_FIFO_DEPTH 0 +#define ISP_GDC_FIFO_DEPTH 0 +#define ISP_SCL_FIFO_DEPTH 0 +#define ISP_GPFIFO_FIFO_DEPTH 0 +#define ISP_SP_FIFO_DEPTH 0 diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_acquisition_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_acquisition_defs.h new file mode 100644 index 0000000..5936207 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_acquisition_defs.h @@ -0,0 +1,234 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp_acquisition_defs_h +#define _isp_acquisition_defs_h + +#define _ISP_ACQUISITION_REG_ALIGN 4 /* assuming 32 bit control bus width */ +#define _ISP_ACQUISITION_BYTES_PER_ELEM 4 + +/* --------------------------------------------------*/ + +#define NOF_ACQ_IRQS 1 + +/* --------------------------------------------------*/ +/* FSM */ +/* --------------------------------------------------*/ +#define MEM2STREAM_FSM_STATE_BITS 2 +#define ACQ_SYNCHRONIZER_FSM_STATE_BITS 2 + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +#define NOF_ACQ_REGS 12 + +// Register id's of MMIO slave accesible registers +#define ACQ_START_ADDR_REG_ID 0 +#define ACQ_MEM_REGION_SIZE_REG_ID 1 +#define ACQ_NUM_MEM_REGIONS_REG_ID 2 +#define ACQ_INIT_REG_ID 3 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_ID 4 +#define ACQ_RECEIVED_LONG_PACKETS_REG_ID 5 +#define ACQ_LAST_COMMAND_REG_ID 6 +#define ACQ_NEXT_COMMAND_REG_ID 7 +#define ACQ_LAST_ACKNOWLEDGE_REG_ID 8 +#define ACQ_NEXT_ACKNOWLEDGE_REG_ID 9 +#define ACQ_FSM_STATE_INFO_REG_ID 10 +#define ACQ_INT_CNTR_INFO_REG_ID 11 + +// Register width +#define ACQ_START_ADDR_REG_WIDTH 9 +#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9 +#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9 +#define ACQ_INIT_REG_WIDTH 3 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32 +#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32 +#define ACQ_LAST_COMMAND_REG_WIDTH 32 +#define ACQ_NEXT_COMMAND_REG_WIDTH 32 +#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS *3)) +#define ACQ_INT_CNTR_INFO_REG_WIDTH 32 + +/* register reset value */ +#define ACQ_START_ADDR_REG_RSTVAL 0 +#define ACQ_MEM_REGION_SIZE_REG_RSTVAL 128 +#define ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define ACQ_INIT_REG_RSTVAL 0 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0 +#define ACQ_RECEIVED_LONG_PACKETS_REG_RSTVAL 0 +#define ACQ_LAST_COMMAND_REG_RSTVAL 0 +#define ACQ_NEXT_COMMAND_REG_RSTVAL 0 +#define ACQ_LAST_ACKNOWLEDGE_REG_RSTVAL 0 +#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0 +#define ACQ_FSM_STATE_INFO_REG_RSTVAL 0 +#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0 + +/* bit definitions */ +#define ACQ_INIT_RST_REG_BIT 0 +#define ACQ_INIT_RESYNC_BIT 2 +#define ACQ_INIT_RST_IDX ACQ_INIT_RST_REG_BIT +#define ACQ_INIT_RST_BITS 1 +#define ACQ_INIT_RESYNC_IDX ACQ_INIT_RESYNC_BIT +#define ACQ_INIT_RESYNC_BITS 1 + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ +#define ACQ_TOKEN_ID_LSB 0 +#define ACQ_TOKEN_ID_MSB 3 +#define ACQ_TOKEN_WIDTH (ACQ_TOKEN_ID_MSB - ACQ_TOKEN_ID_LSB + 1) // 4 +#define ACQ_TOKEN_ID_IDX 0 +#define ACQ_TOKEN_ID_BITS ACQ_TOKEN_WIDTH +#define ACQ_INIT_CMD_INIT_IDX 4 +#define ACQ_INIT_CMD_INIT_BITS 3 +#define ACQ_CMD_START_ADDR_IDX 4 +#define ACQ_CMD_START_ADDR_BITS 9 +#define ACQ_CMD_NOFWORDS_IDX 13 +#define ACQ_CMD_NOFWORDS_BITS 9 +#define ACQ_MEM_REGION_ID_IDX 22 +#define ACQ_MEM_REGION_ID_BITS 9 +#define ACQ_PACKET_LENGTH_TOKEN_MSB 21 +#define ACQ_PACKET_LENGTH_TOKEN_LSB 13 +#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_MSB 9 +#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_LSB 4 +#define ACQ_PACKET_CH_ID_TOKEN_MSB 11 +#define ACQ_PACKET_CH_ID_TOKEN_LSB 10 +#define ACQ_PACKET_MEM_REGION_ID_TOKEN_MSB 12 /* only for capt_end_of_packet_written */ +#define ACQ_PACKET_MEM_REGION_ID_TOKEN_LSB 4 /* only for capt_end_of_packet_written */ + + +/* Command tokens IDs */ +#define ACQ_READ_REGION_AUTO_INCR_TOKEN_ID 0 //0000b +#define ACQ_READ_REGION_TOKEN_ID 1 //0001b +#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b +#define ACQ_INIT_TOKEN_ID 8 //1000b + +/* Acknowledge token IDs */ +#define ACQ_READ_REGION_ACK_TOKEN_ID 0 //0000b +#define ACQ_END_OF_PACKET_TOKEN_ID 4 //0100b +#define ACQ_END_OF_REGION_TOKEN_ID 5 //0101b +#define ACQ_SOP_MISMATCH_TOKEN_ID 6 //0110b +#define ACQ_UNDEF_PH_TOKEN_ID 7 //0111b + +#define ACQ_TOKEN_MEMREGIONID_MSB 30 +#define ACQ_TOKEN_MEMREGIONID_LSB 22 +#define ACQ_TOKEN_NOFWORDS_MSB 21 +#define ACQ_TOKEN_NOFWORDS_LSB 13 +#define ACQ_TOKEN_STARTADDR_MSB 12 +#define ACQ_TOKEN_STARTADDR_LSB 4 + + +/* --------------------------------------------------*/ +/* MIPI */ +/* --------------------------------------------------*/ + +#define WORD_COUNT_WIDTH 16 +#define PKT_CODE_WIDTH 6 +#define CHN_NO_WIDTH 2 +#define ERROR_INFO_WIDTH 8 + +#define LONG_PKTCODE_MAX 63 +#define LONG_PKTCODE_MIN 16 +#define SHORT_PKTCODE_MAX 15 + +#define EOF_CODE 1 + +/* --------------------------------------------------*/ +/* Packet Info */ +/* --------------------------------------------------*/ +#define ACQ_START_OF_FRAME 0 +#define ACQ_END_OF_FRAME 1 +#define ACQ_START_OF_LINE 2 +#define ACQ_END_OF_LINE 3 +#define ACQ_LINE_PAYLOAD 4 +#define ACQ_GEN_SH_PKT 5 + + +/* bit definition */ +#define ACQ_PKT_TYPE_IDX 16 +#define ACQ_PKT_TYPE_BITS 6 +#define ACQ_PKT_SOP_IDX 32 +#define ACQ_WORD_CNT_IDX 0 +#define ACQ_WORD_CNT_BITS 16 +#define ACQ_PKT_INFO_IDX 16 +#define ACQ_PKT_INFO_BITS 8 +#define ACQ_HEADER_DATA_IDX 0 +#define ACQ_HEADER_DATA_BITS 16 +#define ACQ_ACK_TOKEN_ID_IDX ACQ_TOKEN_ID_IDX +#define ACQ_ACK_TOKEN_ID_BITS ACQ_TOKEN_ID_BITS +#define ACQ_ACK_NOFWORDS_IDX 13 +#define ACQ_ACK_NOFWORDS_BITS 9 +#define ACQ_ACK_PKT_LEN_IDX 4 +#define ACQ_ACK_PKT_LEN_BITS 16 + + +/* --------------------------------------------------*/ +/* Packet Data Type */ +/* --------------------------------------------------*/ + + +#define ACQ_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */ +#define ACQ_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */ +#define ACQ_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */ +#define ACQ_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */ +#define ACQ_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */ +#define ACQ_RGB444_DATA 32 /* 10 0000 RGB444 */ +#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */ +#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */ +#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */ +#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */ +#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */ +#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */ +#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */ +#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */ +#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */ +#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */ +#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */ +#define ACQ_SOF_DATA 0 /* 00 0000 frame start */ +#define ACQ_EOF_DATA 1 /* 00 0001 frame end */ +#define ACQ_SOL_DATA 2 /* 00 0010 line start */ +#define ACQ_EOL_DATA 3 /* 00 0011 line end */ +#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */ +#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */ +#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */ +#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */ +#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */ +#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */ +#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */ +#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */ +#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +#define ACQ_RESERVED_DATA_TYPE_MIN 56 +#define ACQ_RESERVED_DATA_TYPE_MAX 63 +#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MIN 19 +#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MAX 23 +#define ACQ_YUV_RESERVED_DATA_TYPE 27 +#define ACQ_RGB_RESERVED_DATA_TYPE_MIN 37 +#define ACQ_RGB_RESERVED_DATA_TYPE_MAX 39 +#define ACQ_RAW_RESERVED_DATA_TYPE_MIN 46 +#define ACQ_RAW_RESERVED_DATA_TYPE_MAX 47 + +/* --------------------------------------------------*/ + +#endif /* _isp_acquisition_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_capture_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_capture_defs.h new file mode 100644 index 0000000..aa413df --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_capture_defs.h @@ -0,0 +1,310 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp_capture_defs_h +#define _isp_capture_defs_h + +#define _ISP_CAPTURE_REG_ALIGN 4 /* assuming 32 bit control bus width */ +#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */ +#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM/8 ) +#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */ +#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM + +//#define CAPT_RCV_ACK 1 +//#define CAPT_WRT_ACK 2 +//#define CAPT_IRQ_ACK 3 + +/* --------------------------------------------------*/ + +#define NOF_IRQS 2 + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +// Number of registers +#define CAPT_NOF_REGS 16 + +// Register id's of MMIO slave accesible registers +#define CAPT_START_MODE_REG_ID 0 +#define CAPT_START_ADDR_REG_ID 1 +#define CAPT_MEM_REGION_SIZE_REG_ID 2 +#define CAPT_NUM_MEM_REGIONS_REG_ID 3 +#define CAPT_INIT_REG_ID 4 +#define CAPT_START_REG_ID 5 +#define CAPT_STOP_REG_ID 6 + +#define CAPT_PACKET_LENGTH_REG_ID 7 +#define CAPT_RECEIVED_LENGTH_REG_ID 8 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9 +#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10 +#define CAPT_LAST_COMMAND_REG_ID 11 +#define CAPT_NEXT_COMMAND_REG_ID 12 +#define CAPT_LAST_ACKNOWLEDGE_REG_ID 13 +#define CAPT_NEXT_ACKNOWLEDGE_REG_ID 14 +#define CAPT_FSM_STATE_INFO_REG_ID 15 + +// Register width +#define CAPT_START_MODE_REG_WIDTH 1 +//#define CAPT_START_ADDR_REG_WIDTH 9 +//#define CAPT_MEM_REGION_SIZE_REG_WIDTH 9 +//#define CAPT_NUM_MEM_REGIONS_REG_WIDTH 9 +#define CAPT_INIT_REG_WIDTH (22 + 4) + +#define CAPT_START_REG_WIDTH 1 +#define CAPT_STOP_REG_WIDTH 1 + +/* --------------------------------------------------*/ +/* FSM */ +/* --------------------------------------------------*/ +#define CAPT_WRITE2MEM_FSM_STATE_BITS 2 +#define CAPT_SYNCHRONIZER_FSM_STATE_BITS 3 + + +#define CAPT_PACKET_LENGTH_REG_WIDTH 17 +#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_WIDTH 32 +#define CAPT_RECEIVED_LONG_PACKETS_REG_WIDTH 32 +#define CAPT_LAST_COMMAND_REG_WIDTH 32 +/* #define CAPT_NEXT_COMMAND_REG_WIDTH 32 */ +#define CAPT_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define CAPT_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define CAPT_FSM_STATE_INFO_REG_WIDTH ((CAPT_WRITE2MEM_FSM_STATE_BITS * 3) + (CAPT_SYNCHRONIZER_FSM_STATE_BITS * 3)) + +//#define CAPT_INIT_RESTART_MEM_ADDR_WIDTH 9 +//#define CAPT_INIT_RESTART_MEM_REGION_WIDTH 9 + +/* register reset value */ +#define CAPT_START_MODE_REG_RSTVAL 0 +#define CAPT_START_ADDR_REG_RSTVAL 0 +#define CAPT_MEM_REGION_SIZE_REG_RSTVAL 128 +#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define CAPT_INIT_REG_RSTVAL 0 + +#define CAPT_START_REG_RSTVAL 0 +#define CAPT_STOP_REG_RSTVAL 0 + +#define CAPT_PACKET_LENGTH_REG_RSTVAL 0 +#define CAPT_RECEIVED_LENGTH_REG_RSTVAL 0 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0 +#define CAPT_RECEIVED_LONG_PACKETS_REG_RSTVAL 0 +#define CAPT_LAST_COMMAND_REG_RSTVAL 0 +#define CAPT_NEXT_COMMAND_REG_RSTVAL 0 +#define CAPT_LAST_ACKNOWLEDGE_REG_RSTVAL 0 +#define CAPT_NEXT_ACKNOWLEDGE_REG_RSTVAL 0 +#define CAPT_FSM_STATE_INFO_REG_RSTVAL 0 + +/* bit definitions */ +#define CAPT_INIT_RST_REG_BIT 0 +#define CAPT_INIT_FLUSH_BIT 1 +#define CAPT_INIT_RESYNC_BIT 2 +#define CAPT_INIT_RESTART_BIT 3 +#define CAPT_INIT_RESTART_MEM_ADDR_LSB 4 +#define CAPT_INIT_RESTART_MEM_ADDR_MSB 14 +#define CAPT_INIT_RESTART_MEM_REGION_LSB 15 +#define CAPT_INIT_RESTART_MEM_REGION_MSB 25 + + +#define CAPT_INIT_RST_REG_IDX CAPT_INIT_RST_REG_BIT +#define CAPT_INIT_RST_REG_BITS 1 +#define CAPT_INIT_FLUSH_IDX CAPT_INIT_FLUSH_BIT +#define CAPT_INIT_FLUSH_BITS 1 +#define CAPT_INIT_RESYNC_IDX CAPT_INIT_RESYNC_BIT +#define CAPT_INIT_RESYNC_BITS 1 +#define CAPT_INIT_RESTART_IDX CAPT_INIT_RESTART_BIT +#define CAPT_INIT_RESTART_BITS 1 +#define CAPT_INIT_RESTART_MEM_ADDR_IDX CAPT_INIT_RESTART_MEM_ADDR_LSB +#define CAPT_INIT_RESTART_MEM_ADDR_BITS (CAPT_INIT_RESTART_MEM_ADDR_MSB - CAPT_INIT_RESTART_MEM_ADDR_LSB + 1) +#define CAPT_INIT_RESTART_MEM_REGION_IDX CAPT_INIT_RESTART_MEM_REGION_LSB +#define CAPT_INIT_RESTART_MEM_REGION_BITS (CAPT_INIT_RESTART_MEM_REGION_MSB - CAPT_INIT_RESTART_MEM_REGION_LSB + 1) + + + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ +#define CAPT_TOKEN_ID_LSB 0 +#define CAPT_TOKEN_ID_MSB 3 +#define CAPT_TOKEN_WIDTH (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) /* 4 */ + +/* Command tokens IDs */ +#define CAPT_START_TOKEN_ID 0 /* 0000b */ +#define CAPT_STOP_TOKEN_ID 1 /* 0001b */ +#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */ +#define CAPT_RESUME_TOKEN_ID 3 /* 0011b */ +#define CAPT_INIT_TOKEN_ID 8 /* 1000b */ + +#define CAPT_START_TOKEN_BIT 0 +#define CAPT_STOP_TOKEN_BIT 0 +#define CAPT_FREEZE_TOKEN_BIT 0 +#define CAPT_RESUME_TOKEN_BIT 0 +#define CAPT_INIT_TOKEN_BIT 0 + +/* Acknowledge token IDs */ +#define CAPT_END_OF_PACKET_RECEIVED_TOKEN_ID 0 /* 0000b */ +#define CAPT_END_OF_PACKET_WRITTEN_TOKEN_ID 1 /* 0001b */ +#define CAPT_END_OF_REGION_WRITTEN_TOKEN_ID 2 /* 0010b */ +#define CAPT_FLUSH_DONE_TOKEN_ID 3 /* 0011b */ +#define CAPT_PREMATURE_SOP_TOKEN_ID 4 /* 0100b */ +#define CAPT_MISSING_SOP_TOKEN_ID 5 /* 0101b */ +#define CAPT_UNDEF_PH_TOKEN_ID 6 /* 0110b */ +#define CAPT_STOP_ACK_TOKEN_ID 7 /* 0111b */ + +#define CAPT_PACKET_LENGTH_TOKEN_MSB 19 +#define CAPT_PACKET_LENGTH_TOKEN_LSB 4 +#define CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB 20 +#define CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB 4 +#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB 25 +#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB 20 +#define CAPT_PACKET_CH_ID_TOKEN_MSB 27 +#define CAPT_PACKET_CH_ID_TOKEN_LSB 26 +#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29 +#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21 + +/* bit definition */ +#define CAPT_CMD_IDX CAPT_TOKEN_ID_LSB +#define CAPT_CMD_BITS (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) +#define CAPT_SOP_IDX 32 +#define CAPT_SOP_BITS 1 +#define CAPT_PKT_INFO_IDX 16 +#define CAPT_PKT_INFO_BITS 8 +#define CAPT_PKT_TYPE_IDX 0 +#define CAPT_PKT_TYPE_BITS 6 +#define CAPT_HEADER_DATA_IDX 0 +#define CAPT_HEADER_DATA_BITS 16 +#define CAPT_PKT_DATA_IDX 0 +#define CAPT_PKT_DATA_BITS 32 +#define CAPT_WORD_CNT_IDX 0 +#define CAPT_WORD_CNT_BITS 16 +#define CAPT_ACK_TOKEN_ID_IDX 0 +#define CAPT_ACK_TOKEN_ID_BITS 4 +//#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB +//#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1) +//#define CAPT_ACK_PKT_INFO_IDX 20 +//#define CAPT_ACK_PKT_INFO_BITS 8 +//#define CAPT_ACK_MEM_REG_ID1_IDX 20 /* for capt_end_of_packet_written */ +//#define CAPT_ACK_MEM_REG_ID2_IDX 4 /* for capt_end_of_region_written */ +#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB +#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1) +#define CAPT_ACK_SUPER_PKT_LEN_IDX CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB +#define CAPT_ACK_SUPER_PKT_LEN_BITS (CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB - CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB + 1) +#define CAPT_ACK_PKT_INFO_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB +#define CAPT_ACK_PKT_INFO_BITS (CAPT_PACKET_CH_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1) +#define CAPT_ACK_MEM_REGION_ID_IDX CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB +#define CAPT_ACK_MEM_REGION_ID_BITS (CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB - CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB + 1) +#define CAPT_ACK_PKT_TYPE_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB +#define CAPT_ACK_PKT_TYPE_BITS (CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1) +#define CAPT_INIT_TOKEN_INIT_IDX 4 +#define CAPT_INIT_TOKEN_INIT_BITS 22 + + +/* --------------------------------------------------*/ +/* MIPI */ +/* --------------------------------------------------*/ + +#define CAPT_WORD_COUNT_WIDTH 16 +#define CAPT_PKT_CODE_WIDTH 6 +#define CAPT_CHN_NO_WIDTH 2 +#define CAPT_ERROR_INFO_WIDTH 8 + +#define LONG_PKTCODE_MAX 63 +#define LONG_PKTCODE_MIN 16 +#define SHORT_PKTCODE_MAX 15 + + +/* --------------------------------------------------*/ +/* Packet Info */ +/* --------------------------------------------------*/ +#define CAPT_START_OF_FRAME 0 +#define CAPT_END_OF_FRAME 1 +#define CAPT_START_OF_LINE 2 +#define CAPT_END_OF_LINE 3 +#define CAPT_LINE_PAYLOAD 4 +#define CAPT_GEN_SH_PKT 5 + + +/* --------------------------------------------------*/ +/* Packet Data Type */ +/* --------------------------------------------------*/ + +#define CAPT_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */ +#define CAPT_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */ +#define CAPT_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */ +#define CAPT_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */ +#define CAPT_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */ +#define CAPT_RGB444_DATA 32 /* 10 0000 RGB444 */ +#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */ +#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */ +#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */ +#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */ +#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */ +#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */ +#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */ +#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */ +#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */ +#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */ +#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */ +#define CAPT_SOF_DATA 0 /* 00 0000 frame start */ +#define CAPT_EOF_DATA 1 /* 00 0001 frame end */ +#define CAPT_SOL_DATA 2 /* 00 0010 line start */ +#define CAPT_EOL_DATA 3 /* 00 0011 line end */ +#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */ +#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */ +#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */ +#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */ +#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */ +#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */ +#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */ +#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */ +#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +#define CAPT_RESERVED_DATA_TYPE_MIN 56 +#define CAPT_RESERVED_DATA_TYPE_MAX 63 +#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MIN 19 +#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MAX 23 +#define CAPT_YUV_RESERVED_DATA_TYPE 27 +#define CAPT_RGB_RESERVED_DATA_TYPE_MIN 37 +#define CAPT_RGB_RESERVED_DATA_TYPE_MAX 39 +#define CAPT_RAW_RESERVED_DATA_TYPE_MIN 46 +#define CAPT_RAW_RESERVED_DATA_TYPE_MAX 47 + + +/* --------------------------------------------------*/ +/* Capture Unit State */ +/* --------------------------------------------------*/ +#define CAPT_FREE_RUN 0 +#define CAPT_NO_SYNC 1 +#define CAPT_SYNC_SWP 2 +#define CAPT_SYNC_MWP 3 +#define CAPT_SYNC_WAIT 4 +#define CAPT_FREEZE 5 +#define CAPT_RUN 6 + + +/* --------------------------------------------------*/ + +#endif /* _isp_capture_defs_h */ + + + + + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mipi_backend_common_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mipi_backend_common_defs.h new file mode 100644 index 0000000..76705d7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mipi_backend_common_defs.h @@ -0,0 +1,210 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _css_receiver_2400_common_defs_h_ +#define _css_receiver_2400_common_defs_h_ +#ifndef _mipi_backend_common_defs_h_ +#define _mipi_backend_common_defs_h_ + +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH 16 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH 2 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH 3 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH (_HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */ + +/* Definition of data format ID at the interface CSS_receiver capture/acquisition units */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit legacy */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB888 36 /* 10 0100 RGB888 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW6 40 /* 10 1000 RAW6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW7 41 /* 10 1001 RAW7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW8 42 /* 10 1010 RAW8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW10 43 /* 10 1011 RAW10 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW12 44 /* 10 1100 RAW12 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW14 45 /* 10 1101 RAW14 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_1 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_2 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_3 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_4 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_5 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_6 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_7 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_8 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_Emb 18 /* 01 0010 embedded eight bit non image data */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH1 8 /* 00 1000 Generic Short Packet Code 1 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH2 9 /* 00 1001 Generic Short Packet Code 2 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH3 10 /* 00 1010 Generic Short Packet Code 3 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH4 11 /* 00 1011 Generic Short Packet Code 4 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH5 12 /* 00 1100 Generic Short Packet Code 5 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH6 13 /* 00 1101 Generic Short Packet Code 6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH7 14 /* 00 1110 Generic Short Packet Code 7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH8 15 /* 00 1111 Generic Short Packet Code 8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +/* used reseved mipi positions for these */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38 + +//_HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 63 +#define _HRT_MIPI_BACKEND_FMT_TYPE_CUSTOM 63 + +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_WIDTH 6 + +/* Definition of format_types at the interface CSS --> input_selector*/ +/* !! Changes here should be copied to systems/isp/isp_css/bin/conv_transmitter_cmd.tcl !! */ +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB888 0 // 36 'h24 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB555 1 // 33 'h +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW12 9 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW14 10 // 45 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8 11 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10 12 // 25 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_8 13 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_10 14 // 31 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_1 15 // 48 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8L 16 // 26 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_Emb 17 // 18 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_2 18 // 49 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_3 19 // 50 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_4 20 // 51 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_5 21 // 52 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_6 22 // 53 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_7 23 // 54 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_8 24 // 55 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8_CSPS 25 // 28 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10_CSPS 26 // 29 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW16 27 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding + +/* definition for state machine of data FIFO for decode different type of data */ +#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9 +#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7 +#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7 + +#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_WIDTH 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_IDX 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_WIDTH 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_USD_BITS 4 /* bits per USD type */ + +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_EN_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_EN_IDX 8 + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_NO_COMP 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_6_10 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_7_10 2 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_8_10 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_6_12 4 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6 + + +/* packet bit definition */ +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32 +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_IDX 22 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_BITS 2 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_IDX 16 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_BITS 16 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32 + + +/*************************************************************************************************/ +/* Custom Decoding */ +/* These Custom Defs are defined based on design-time config in "mipi_backend_pixel_formatter.chdl" !! */ +/*************************************************************************************************/ +/* +#define BE_CUST_EN_IDX 0 // 2bits +#define BE_CUST_EN_DATAID_IDX 2 // 6bits MIPI DATA ID +#define BE_CUST_EN_WIDTH 8 +#define BE_CUST_MODE_ALL 1 // Enable Custom Decoding for all DATA IDs +#define BE_CUST_MODE_ONE 3 // Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID + +// Data State config = {get_bits(6bits), valid(1bit)} // +#define BE_CUST_DATA_STATE_S0_IDX 0 // 7bits +#define BE_CUST_DATA_STATE_S1_IDX 8 //7 // 7bits +#define BE_CUST_DATA_STATE_S2_IDX 16//14 // 7bits / +#define BE_CUST_DATA_STATE_WIDTH 24//21 +#define BE_CUST_DATA_STATE_VALID_IDX 0 // 1bits +#define BE_CUST_DATA_STATE_GETBITS_IDX 1 // 6bits + + + + +// Pixel Extractor config +#define BE_CUST_PIX_EXT_DATA_ALIGN_IDX 0 // 6bits +#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 6//5 // 5bits +#define BE_CUST_PIX_EXT_PIX_MASK_IDX 11//10 // 18bits +#define BE_CUST_PIX_EXT_PIX_EN_IDX 29 //28 // 1bits + +#define BE_CUST_PIX_EXT_WIDTH 30//29 + +// Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} +#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 // 4bits +#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 // 4bits +#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 // 4bits +#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 // 4bits +#define BE_CUST_PIX_VALID_EOP_WIDTH 16 +#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 // Normal (NO less get_bits case) Valid - 1bits +#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 // Normal (NO less get_bits case) EoP - 1bits +#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 // Especial (less get_bits case) Valid - 1bits +#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 // Especial (less get_bits case) EoP - 1bits + +*/ + +#endif /* _mipi_backend_common_defs_h_ */ +#endif /* _css_receiver_2400_common_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mipi_backend_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mipi_backend_defs.h new file mode 100644 index 0000000..db5a1d2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mipi_backend_defs.h @@ -0,0 +1,215 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _mipi_backend_defs_h +#define _mipi_backend_defs_h + +#include "mipi_backend_common_defs.h" + +#define MIPI_BACKEND_REG_ALIGN 4 // assuming 32 bit control bus width + +#define _HRT_MIPI_BACKEND_NOF_IRQS 3 // sid_lut + +// SH Backend Register IDs +#define _HRT_MIPI_BACKEND_ENABLE_REG_IDX 0 +#define _HRT_MIPI_BACKEND_STATUS_REG_IDX 1 +//#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_IDX 2 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX 2 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG1_IDX 3 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG2_IDX 4 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG3_IDX 5 +#define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX 6 +#define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX 7 +#define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX 8 +#define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX 9 +#define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_IDX 10 +//// +#define _HRT_MIPI_BACKEND_CUST_EN_REG_IDX 11 +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX 12 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX 13 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P1_REG_IDX 14 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P2_REG_IDX 15 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P3_REG_IDX 16 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P0_REG_IDX 17 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P1_REG_IDX 18 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P2_REG_IDX 19 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P3_REG_IDX 20 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P0_REG_IDX 21 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P1_REG_IDX 22 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P2_REG_IDX 23 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P3_REG_IDX 24 +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX 25 +//// +#define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX 26 +#define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX 27 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_IDX 28 +#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX 28 +#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_IDX 29 +#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_IDX 30 +#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_IDX 31 + +#define _HRT_MIPI_BACKEND_NOF_REGISTERS 32 // excluding the LP LUT entries + +#define _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX 32 + + +///////////////////////////////////////////////////////////////////////////////////////////////////// +#define _HRT_MIPI_BACKEND_ENABLE_REG_WIDTH 1 +#define _HRT_MIPI_BACKEND_STATUS_REG_WIDTH 1 +//#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_WIDTH 1 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG_WIDTH 32 +#define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_WIDTH 7 +#define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_WIDTH 9 +#define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_WIDTH 8 +#define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_WIDTH _HRT_MIPI_BACKEND_NOF_IRQS +#define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_WIDTH 0 +#define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_WIDTH 1 +#define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_WIDTH 1+2+6 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_WIDTH 1 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_WIDTH 7 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_WIDTH 7 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_WIDTH 7 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_WIDTH 7 + +///////////////////////////////////////////////////////////////////////////////////////////////////// + +#define _HRT_MIPI_BACKEND_NOF_SP_LUT_ENTRIES 4 + +//#define _HRT_MIPI_BACKEND_MAX_NOF_LP_LUT_ENTRIES 16 // to satisfy hss model static array declaration + + +#define _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH 2 +#define _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH 6 +#define _HRT_MIPI_BACKEND_PACKET_ID_WIDTH _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH + +#define _HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB 0 +#define _HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB + (pix_width) - 1) +#define _HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) + (pix_width) - 1) +#define _HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_WIDTH(pix_width) (_HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) + 1) + +/*************************************************************************************************/ +/* Custom Decoding */ +/* These Custom Defs are defined based on design-time config in "mipi_backend_pixel_formatter.chdl" !! */ +/*************************************************************************************************/ +#define _HRT_MIPI_BACKEND_CUST_EN_IDX 0 /* 2bits */ +#define _HRT_MIPI_BACKEND_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */ +#define _HRT_MIPI_BACKEND_CUST_EN_HIGH_PREC_IDX 8 // 1 bit +#define _HRT_MIPI_BACKEND_CUST_EN_WIDTH 9 +#define _HRT_MIPI_BACKEND_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */ +#define _HRT_MIPI_BACKEND_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */ + +#define _HRT_MIPI_BACKEND_CUST_EN_OPTION_IDX 1 + +/* Data State config = {get_bits(6bits), valid(1bit)} */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S0_IDX 0 /* 7bits */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S1_IDX 8 /* 7bits */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S2_IDX 16 /* was 14 7bits */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_WIDTH 24 /* was 21*/ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */ + +/* Pixel Extractor config */ +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 6bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_ALIGN_IDX 6 /* 5bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_MASK_IDX 11 /* was 10 18bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_EN_IDX 29 /* was 28 1bits */ + +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_WIDTH 30 /* was 29 */ + +/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_WIDTH 16 +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */ + +/*************************************************************************************************/ +/* MIPI backend output streaming interface definition */ +/* These parameters define the fields within the streaming bus. These should also be used by the */ +/* subsequent block, ie stream2mmio. */ +/*************************************************************************************************/ +/* The pipe backend - stream2mmio should be design time configurable in */ +/* PixWidth - Number of bits per pixel */ +/* PPC - Pixel per Clocks */ +/* NumSids - Max number of source Ids (ifc's) and derived from that: */ +/* SidWidth - Number of bits required for the sid parameter */ +/* In order to keep this configurability, below Macro's have these as a parameter */ +/*************************************************************************************************/ + +#define HRT_MIPI_BACKEND_STREAM_EOP_BIT 0 +#define HRT_MIPI_BACKEND_STREAM_SOP_BIT 1 +#define HRT_MIPI_BACKEND_STREAM_EOF_BIT 2 +#define HRT_MIPI_BACKEND_STREAM_SOF_BIT 3 +#define HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT 4 +#define HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT+(sid_width)-1) +#define HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width,p) (HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width)+1+p) + +#define HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width,ppc,pix_width,p) (HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width,ppc)+ ((pix_width)*p)) +#define HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width,ppc,pix_width,p) (HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width,ppc,pix_width,p) + (pix_width) - 1) + +#if 0 +//#define HRT_MIPI_BACKEND_STREAM_PIX_BITS 14 +//#define HRT_MIPI_BACKEND_STREAM_CHID_BITS 4 +//#define HRT_MIPI_BACKEND_STREAM_PPC 4 +#endif + +#define HRT_MIPI_BACKEND_STREAM_BITS(sid_width,ppc,pix_width) (HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width,ppc,pix_width,(ppc-1))+1) + + +/* SP and LP LUT BIT POSITIONS */ +#define HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT 0 // 0 +#define HRT_MIPI_BACKEND_LUT_SID_LS_BIT HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT + 1 // 1 +#define HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_LUT_SID_LS_BIT+(sid_width)-1) // 1 + (4) - 1 = 4 +#define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 // 5 +#define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH - 1 // 6 +#define HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 +#define HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH - 1 // 12 + +/* #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 */ + +#define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 +#define HRT_MIPI_BACKEND_LP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) + 1 // 13 + + +// temp solution +//#define HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT + 1 // 8 +//#define HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT + 1 // 9 +//#define HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT + 1 // 10 +//#define HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT + 1 // 11 +//#define HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT + 1 // 12 +//#define HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 25 +//#define HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT + 1 // 26 +//#define HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 39 +//#define HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT + 1 // 40 +//#define HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 53 +//#define HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT + 1 // 54 +//#define HRT_MIPI_BACKEND_STREAM_PIXD_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 67 + +// vc hidden in pixb data (passed as raw12 the pipe) +#define HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width,ppc,pix_width) HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width,ppc,pix_width,1) + 10 //HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + 10 // 36 +#define HRT_MIPI_BACKEND_STREAM_VC_MS_BIT(sid_width,ppc,pix_width) HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width,ppc,pix_width) + 1 // 37 + + + + +#endif /* _mipi_backend_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mmu_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mmu_defs.h new file mode 100644 index 0000000..c038f39 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mmu_defs.h @@ -0,0 +1,23 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _mmu_defs_h +#define _mmu_defs_h + +#define _HRT_MMU_INVALIDATE_TLB_REG_IDX 0 +#define _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX 1 + +#define _HRT_MMU_REG_ALIGN 4 + +#endif /* _mmu_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/rx_csi_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/rx_csi_defs.h new file mode 100644 index 0000000..0aad86e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/rx_csi_defs.h @@ -0,0 +1,175 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _csi_rx_defs_h +#define _csi_rx_defs_h + +//#include "rx_csi_common_defs.h" + + + +#define MIPI_PKT_DATA_WIDTH 32 +//#define CLK_CROSSING_FIFO_DEPTH 16 +#define _CSI_RX_REG_ALIGN 4 + +//define number of IRQ (see below for definition of each IRQ bits) +#define CSI_RX_NOF_IRQS_BYTE_DOMAIN 11 +#define CSI_RX_NOF_IRQS_ISP_DOMAIN 15 // CSI_RX_NOF_IRQS_BYTE_DOMAIN + remaining from Dphy_rx already on ISP clock domain + +// REGISTER DESCRIPTION +//#define _HRT_CSI_RX_SOFTRESET_REG_IDX 0 +#define _HRT_CSI_RX_ENABLE_REG_IDX 0 +#define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX 1 +#define _HRT_CSI_RX_ERROR_HANDLING_REG_IDX 2 +#define _HRT_CSI_RX_STATUS_REG_IDX 3 +#define _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX 4 +#define _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX 5 +//#define _HRT_CSI_RX_IRQ_CONFIG_REG_IDX 6 +#define _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX 6 +#define _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX 7 +#define _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane_idx) (8+(2*lane_idx)) +#define _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane_idx) (8+(2*lane_idx)+1) + +#define _HRT_CSI_RX_NOF_REGISTERS(nof_dlanes) (8+2*(nof_dlanes)) + + +//#define _HRT_CSI_RX_SOFTRESET_REG_WIDTH 1 +#define _HRT_CSI_RX_ENABLE_REG_WIDTH 1 +#define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_WIDTH 3 +#define _HRT_CSI_RX_ERROR_HANDLING_REG_WIDTH 4 +#define _HRT_CSI_RX_STATUS_REG_WIDTH 1 +#define _HRT_CSI_RX_STATUS_DLANE_HS_REG_WIDTH 8 +#define _HRT_CSI_RX_STATUS_DLANE_LP_REG_WIDTH 24 +#define _HRT_CSI_RX_IRQ_CONFIG_REG_WIDTH (CSI_RX_NOF_IRQS_ISP_DOMAIN) +#define _HRT_CSI_RX_DLY_CNT_REG_WIDTH 24 +//#define _HRT_CSI_RX_IRQ_STATUS_REG_WIDTH NOF_IRQS +//#define _HRT_CSI_RX_IRQ_CLEAR_REG_WIDTH 0 + + +#define ONE_LANE_ENABLED 0 +#define TWO_LANES_ENABLED 1 +#define THREE_LANES_ENABLED 2 +#define FOUR_LANES_ENABLED 3 + +// Error handling reg bit positions +#define ERR_DECISION_BIT 0 +#define DISC_RESERVED_SP_BIT 1 +#define DISC_RESERVED_LP_BIT 2 +#define DIS_INCOMP_PKT_CHK_BIT 3 + +#define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_POSEDGE 0 +#define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_ORIGINAL 1 + +// Interrupt bits +#define _HRT_RX_CSI_IRQ_SINGLE_PH_ERROR_CORRECTED 0 +#define _HRT_RX_CSI_IRQ_MULTIPLE_PH_ERROR_DETECTED 1 +#define _HRT_RX_CSI_IRQ_PAYLOAD_CHECKSUM_ERROR 2 +#define _HRT_RX_CSI_IRQ_FIFO_FULL_ERROR 3 +#define _HRT_RX_CSI_IRQ_RESERVED_SP_DETECTED 4 +#define _HRT_RX_CSI_IRQ_RESERVED_LP_DETECTED 5 +//#define _HRT_RX_CSI_IRQ_PREMATURE_SOP 6 +#define _HRT_RX_CSI_IRQ_INCOMPLETE_PACKET 6 +#define _HRT_RX_CSI_IRQ_FRAME_SYNC_ERROR 7 +#define _HRT_RX_CSI_IRQ_LINE_SYNC_ERROR 8 +#define _HRT_RX_CSI_IRQ_DLANE_HS_SOT_ERROR 9 +#define _HRT_RX_CSI_IRQ_DLANE_HS_SOT_SYNC_ERROR 10 + +#define _HRT_RX_CSI_IRQ_DLANE_ESC_ERROR 11 +#define _HRT_RX_CSI_IRQ_DLANE_TRIGGERESC 12 +#define _HRT_RX_CSI_IRQ_DLANE_ULPSESC 13 +#define _HRT_RX_CSI_IRQ_CLANE_ULPSCLKNOT 14 + +/* OLD ARASAN FRONTEND IRQs +#define _HRT_RX_CSI_IRQ_OVERRUN_BIT 0 +#define _HRT_RX_CSI_IRQ_RESERVED_BIT 1 +#define _HRT_RX_CSI_IRQ_SLEEP_MODE_ENTRY_BIT 2 +#define _HRT_RX_CSI_IRQ_SLEEP_MODE_EXIT_BIT 3 +#define _HRT_RX_CSI_IRQ_ERR_SOT_HS_BIT 4 +#define _HRT_RX_CSI_IRQ_ERR_SOT_SYNC_HS_BIT 5 +#define _HRT_RX_CSI_IRQ_ERR_CONTROL_BIT 6 +#define _HRT_RX_CSI_IRQ_ERR_ECC_DOUBLE_BIT 7 +#define _HRT_RX_CSI_IRQ_ERR_ECC_CORRECTED_BIT 8 +#define _HRT_RX_CSI_IRQ_ERR_ECC_NO_CORRECTION_BIT 9 +#define _HRT_RX_CSI_IRQ_ERR_CRC_BIT 10 +#define _HRT_RX_CSI_IRQ_ERR_ID_BIT 11 +#define _HRT_RX_CSI_IRQ_ERR_FRAME_SYNC_BIT 12 +#define _HRT_RX_CSI_IRQ_ERR_FRAME_DATA_BIT 13 +#define _HRT_RX_CSI_IRQ_DATA_TIMEOUT_BIT 14 +#define _HRT_RX_CSI_IRQ_ERR_ESCAPE_BIT 15 +#define _HRT_RX_CSI_IRQ_ERR_LINE_SYNC_BIT 16 +*/ + + +////Bit Description for reg _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE0 0 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE1 1 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE2 2 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE3 3 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE0 4 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE1 5 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE2 6 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE3 7 + +////Bit Description for reg _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX +#define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE0 0 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE1 1 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE2 2 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE3 3 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE0 4 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE0 5 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE0 6 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE0 7 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE1 8 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE1 9 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE1 10 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE1 11 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE2 12 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE2 13 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE2 14 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE2 15 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE3 16 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE3 17 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE3 18 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE3 19 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE0 20 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE1 21 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE2 22 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE3 23 + +/*********************************************************/ +/*** Relevant declarations from rx_csi_common_defs.h *****/ +/*********************************************************/ +/* packet bit definition */ +#define _HRT_RX_CSI_PKT_SOP_BITPOS 32 +#define _HRT_RX_CSI_PKT_EOP_BITPOS 33 +#define _HRT_RX_CSI_PKT_PAYLOAD_BITPOS 0 +#define _HRT_RX_CSI_PH_CH_ID_BITPOS 22 +#define _HRT_RX_CSI_PH_FMT_ID_BITPOS 16 +#define _HRT_RX_CSI_PH_DATA_FIELD_BITPOS 0 + +#define _HRT_RX_CSI_PKT_SOP_BITS 1 +#define _HRT_RX_CSI_PKT_EOP_BITS 1 +#define _HRT_RX_CSI_PKT_PAYLOAD_BITS 32 +#define _HRT_RX_CSI_PH_CH_ID_BITS 2 +#define _HRT_RX_CSI_PH_FMT_ID_BITS 6 +#define _HRT_RX_CSI_PH_DATA_FIELD_BITS 16 + +/* Definition of data format ID at the interface CSS_receiver units */ +#define _HRT_RX_CSI_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */ +#define _HRT_RX_CSI_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */ +#define _HRT_RX_CSI_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */ +#define _HRT_RX_CSI_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */ + + +#endif /* _csi_rx_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/scalar_processor_2400_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/scalar_processor_2400_params.h new file mode 100644 index 0000000..9b6c2893 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/scalar_processor_2400_params.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _scalar_processor_2400_params_h +#define _scalar_processor_2400_params_h + +#include "cell_params.h" + +#endif /* _scalar_processor_2400_params_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/sp_hrt.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/sp_hrt.h new file mode 100644 index 0000000..7ee4deb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/sp_hrt.h @@ -0,0 +1,24 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _sp_hrt_h_ +#define _sp_hrt_h_ + +#define hrt_sp_dmem(cell) HRT_PROC_TYPE_PROP(cell, _dmem) + +#define hrt_sp_dmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_sp_dmem(cell)) + +#endif /* _sp_hrt_h_ */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/str2mem_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/str2mem_defs.h new file mode 100644 index 0000000..1cb6244 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/str2mem_defs.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _ST2MEM_DEFS_H +#define _ST2MEM_DEFS_H + +#define _STR2MEM_CRUN_BIT 0x100000 +#define _STR2MEM_CMD_BITS 0x0F0000 +#define _STR2MEM_COUNT_BITS 0x00FFFF + +#define _STR2MEM_BLOCKS_CMD 0xA0000 +#define _STR2MEM_PACKETS_CMD 0xB0000 +#define _STR2MEM_BYTES_CMD 0xC0000 +#define _STR2MEM_BYTES_FROM_PACKET_CMD 0xD0000 + +#define _STR2MEM_SOFT_RESET_REG_ID 0 +#define _STR2MEM_INPUT_ENDIANNESS_REG_ID 1 +#define _STR2MEM_OUTPUT_ENDIANNESS_REG_ID 2 +#define _STR2MEM_BIT_SWAPPING_REG_ID 3 +#define _STR2MEM_BLOCK_SYNC_LEVEL_REG_ID 4 +#define _STR2MEM_PACKET_SYNC_LEVEL_REG_ID 5 +#define _STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ID 6 +#define _STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ID 7 +#define _STR2MEM_EN_STAT_UPDATE_ID 8 + +#define _STR2MEM_REG_ALIGN 4 + +#endif /* _ST2MEM_DEFS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/stream2mmio_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/stream2mmio_defs.h new file mode 100644 index 0000000..46b52fe --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/stream2mmio_defs.h @@ -0,0 +1,71 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _STREAM2MMMIO_DEFS_H +#define _STREAM2MMMIO_DEFS_H + +#include <mipi_backend_defs.h> + +#define _STREAM2MMIO_REG_ALIGN 4 + +#define _STREAM2MMIO_COMMAND_REG_ID 0 +#define _STREAM2MMIO_ACKNOWLEDGE_REG_ID 1 +#define _STREAM2MMIO_PIX_WIDTH_ID_REG_ID 2 +#define _STREAM2MMIO_START_ADDR_REG_ID 3 /* master port address,NOT Byte */ +#define _STREAM2MMIO_END_ADDR_REG_ID 4 /* master port address,NOT Byte */ +#define _STREAM2MMIO_STRIDE_REG_ID 5 /* stride in master port words, increment is per packet for long sids, stride is not used for short sid's*/ +#define _STREAM2MMIO_NUM_ITEMS_REG_ID 6 /* number of packets for store packets cmd, number of words for store_words cmd */ +#define _STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID 7 /* if this register is 1, input will be stalled if there is no pending command for this sid */ +#define _STREAM2MMIO_REGS_PER_SID 8 + +#define _STREAM2MMIO_SID_REG_OFFSET 8 +#define _STREAM2MMIO_MAX_NOF_SIDS 64 /* value used in hss model */ + +/* command token definition */ +#define _STREAM2MMIO_CMD_TOKEN_CMD_LSB 0 /* bits 1-0 is for the command field */ +#define _STREAM2MMIO_CMD_TOKEN_CMD_MSB 1 + +#define _STREAM2MMIO_CMD_TOKEN_WIDTH (_STREAM2MMIO_CMD_TOKEN_CMD_MSB+1-_STREAM2MMIO_CMD_TOKEN_CMD_LSB) + +#define _STREAM2MMIO_CMD_TOKEN_STORE_WORDS 0 /* command for storing a number of output words indicated by reg _STREAM2MMIO_NUM_ITEMS */ +#define _STREAM2MMIO_CMD_TOKEN_STORE_PACKETS 1 /* command for storing a number of packets indicated by reg _STREAM2MMIO_NUM_ITEMS */ +#define _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME 2 /* command for waiting for a frame start */ + +/* acknowledges from packer module */ +/* fields: eof - indicates whether last (short) packet received was an eof packet */ +/* eop - indicates whether command has ended due to packet end or due to no of words requested has been received */ +/* count - indicates number of words stored */ +#define _STREAM2MMIO_PACK_NUM_ITEMS_BITS 16 +#define _STREAM2MMIO_PACK_ACK_EOP_BIT _STREAM2MMIO_PACK_NUM_ITEMS_BITS +#define _STREAM2MMIO_PACK_ACK_EOF_BIT (_STREAM2MMIO_PACK_ACK_EOP_BIT+1) + +/* acknowledge token definition */ +#define _STREAM2MMIO_ACK_TOKEN_NUM_ITEMS_LSB 0 /* bits 3-0 is for the command field */ +#define _STREAM2MMIO_ACK_TOKEN_NUM_ITEMS_MSB (_STREAM2MMIO_PACK_NUM_ITEMS_BITS-1) +#define _STREAM2MMIO_ACK_TOKEN_EOP_BIT _STREAM2MMIO_PACK_ACK_EOP_BIT +#define _STREAM2MMIO_ACK_TOKEN_EOF_BIT _STREAM2MMIO_PACK_ACK_EOF_BIT +#define _STREAM2MMIO_ACK_TOKEN_VALID_BIT (_STREAM2MMIO_ACK_TOKEN_EOF_BIT+1) /* this bit indicates a valid ack */ + /* if there is no valid ack, a read */ + /* on the ack register returns 0 */ +#define _STREAM2MMIO_ACK_TOKEN_WIDTH (_STREAM2MMIO_ACK_TOKEN_VALID_BIT+1) + +/* commands for packer module */ +#define _STREAM2MMIO_PACK_CMD_STORE_WORDS 0 +#define _STREAM2MMIO_PACK_CMD_STORE_LONG_PACKET 1 +#define _STREAM2MMIO_PACK_CMD_STORE_SHORT_PACKET 2 + + + + +#endif /* _STREAM2MMIO_DEFS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/streaming_to_mipi_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/streaming_to_mipi_defs.h new file mode 100644 index 0000000..60143b8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/streaming_to_mipi_defs.h @@ -0,0 +1,28 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _streaming_to_mipi_defs_h +#define _streaming_to_mipi_defs_h + +#define HIVE_STR_TO_MIPI_VALID_A_BIT 0 +#define HIVE_STR_TO_MIPI_VALID_B_BIT 1 +#define HIVE_STR_TO_MIPI_SOL_BIT 2 +#define HIVE_STR_TO_MIPI_EOL_BIT 3 +#define HIVE_STR_TO_MIPI_SOF_BIT 4 +#define HIVE_STR_TO_MIPI_EOF_BIT 5 +#define HIVE_STR_TO_MIPI_CH_ID_LSB 6 + +#define HIVE_STR_TO_MIPI_DATA_A_LSB (HIVE_STR_TO_MIPI_VALID_B_BIT + 1) + +#endif /* _streaming_to_mipi_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/timed_controller_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/timed_controller_defs.h new file mode 100644 index 0000000..d2b8972 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/timed_controller_defs.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _timed_controller_defs_h +#define _timed_controller_defs_h + +#define _HRT_TIMED_CONTROLLER_CMD_REG_IDX 0 + +#define _HRT_TIMED_CONTROLLER_REG_ALIGN 4 + +#endif /* _timed_controller_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/var.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/var.h new file mode 100644 index 0000000..19b19ef --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/var.h @@ -0,0 +1,99 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_VAR_H +#define _HRT_VAR_H + +#include "version.h" +#include "system_api.h" +#include "hive_types.h" + +#define hrt_int_type_of_char char +#define hrt_int_type_of_uchar unsigned char +#define hrt_int_type_of_short short +#define hrt_int_type_of_ushort unsigned short +#define hrt_int_type_of_int int +#define hrt_int_type_of_uint unsigned int +#define hrt_int_type_of_long long +#define hrt_int_type_of_ulong unsigned long +#define hrt_int_type_of_ptr unsigned int + +#define hrt_host_type_of_char char +#define hrt_host_type_of_uchar unsigned char +#define hrt_host_type_of_short short +#define hrt_host_type_of_ushort unsigned short +#define hrt_host_type_of_int int +#define hrt_host_type_of_uint unsigned int +#define hrt_host_type_of_long long +#define hrt_host_type_of_ulong unsigned long +#define hrt_host_type_of_ptr void* + +#define HRT_TYPE_BYTES(cell, type) (HRT_TYPE_BITS(cell, type)/8) +#define HRT_HOST_TYPE(cell_type) HRTCAT(hrt_host_type_of_, cell_type) +#define HRT_INT_TYPE(type) HRTCAT(hrt_int_type_of_, type) + +#ifdef C_RUN + +#ifdef C_RUN_DYNAMIC_LINK_PROGRAMS +extern void *csim_processor_get_crun_symbol(hive_proc_id p, const char *sym); +#define _hrt_cell_get_crun_symbol(cell,sym) csim_processor_get_crun_symbol(cell,HRTSTR(sym)) +#define _hrt_cell_get_crun_indexed_symbol(cell,sym) csim_processor_get_crun_symbol(cell,HRTSTR(sym)) +#else +#define _hrt_cell_get_crun_symbol(cell,sym) (&sym) +#define _hrt_cell_get_crun_indexed_symbol(cell,sym) (sym) +#endif // C_RUN_DYNAMIC_LINK_PROGRAMS + +#define hrt_scalar_store(cell, type, var, data) \ + ((*(HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_symbol(cell,var)) = (data)) +#define hrt_scalar_load(cell, type, var) \ + ((*(HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_symbol(cell,var))) + +#define hrt_indexed_store(cell, type, array, index, data) \ + ((((HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_indexed_symbol(cell,array))[index]) = (data)) +#define hrt_indexed_load(cell, type, array, index) \ + (((HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_indexed_symbol(cell,array))[index]) + +#else /* C_RUN */ + +#define hrt_scalar_store(cell, type, var, data) \ + HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\ + cell, \ + HRTCAT(HIVE_MEM_,var), \ + HRTCAT(HIVE_ADDR_,var), \ + (HRT_INT_TYPE(type))(data)) + +#define hrt_scalar_load(cell, type, var) \ + (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \ + cell, \ + HRTCAT(HIVE_MEM_,var), \ + HRTCAT(HIVE_ADDR_,var))) + +#define hrt_indexed_store(cell, type, array, index, data) \ + HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\ + cell, \ + HRTCAT(HIVE_MEM_,array), \ + (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type)), \ + (HRT_INT_TYPE(type))(data)) + +#define hrt_indexed_load(cell, type, array, index) \ + (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \ + cell, \ + HRTCAT(HIVE_MEM_,array), \ + (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type)))) + +#endif /* C_RUN */ + +#endif /* _HRT_VAR_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/version.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/version.h new file mode 100644 index 0000000..bbc4948 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/version.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef HRT_VERSION_H +#define HRT_VERSION_H +#define HRT_VERSION_MAJOR 1 +#define HRT_VERSION_MINOR 4 +#define HRT_VERSION 1_4 +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/ibuf_ctrl_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/ibuf_ctrl_global.h new file mode 100644 index 0000000..edb2325 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/ibuf_ctrl_global.h @@ -0,0 +1,80 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IBUF_CTRL_GLOBAL_H_INCLUDED__ +#define __IBUF_CTRL_GLOBAL_H_INCLUDED__ + +#include <type_support.h> + +#include <ibuf_cntrl_defs.h> /* _IBUF_CNTRL_RECALC_WORDS_STATUS, + * _IBUF_CNTRL_ARBITERS_STATUS, + * _IBUF_CNTRL_PROC_REG_ALIGN, + * etc. + */ + +/* Definition of contents of main controller state register is lacking + * in ibuf_cntrl_defs.h, so define these here: + */ +#define _IBUF_CNTRL_MAIN_CNTRL_FSM_MASK 0xf +#define _IBUF_CNTRL_MAIN_CNTRL_FSM_NEXT_COMMAND_CHECK 0x9 +#define _IBUF_CNTRL_MAIN_CNTRL_MEM_INP_BUF_ALLOC (1 << 8) +#define _IBUF_CNTRL_DMA_SYNC_WAIT_FOR_SYNC 1 +#define _IBUF_CNTRL_DMA_SYNC_FSM_WAIT_FOR_ACK (0x3 << 1) + +typedef struct ib_buffer_s ib_buffer_t; +struct ib_buffer_s { + uint32_t start_addr; /* start address of the buffer in the + * "input-buffer hardware block" + */ + + uint32_t stride; /* stride per buffer line (in bytes) */ + uint32_t lines; /* lines in the buffer */ +}; + +typedef struct ibuf_ctrl_cfg_s ibuf_ctrl_cfg_t; +struct ibuf_ctrl_cfg_s { + + bool online; + + struct { + /* DMA configuration */ + uint32_t channel; + uint32_t cmd; /* must be _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND */ + + /* DMA reconfiguration */ + uint32_t shift_returned_items; + uint32_t elems_per_word_in_ibuf; + uint32_t elems_per_word_in_dest; + } dma_cfg; + + ib_buffer_t ib_buffer; + + struct { + uint32_t stride; + uint32_t start_addr; + uint32_t lines; + } dest_buf_cfg; + + uint32_t items_per_store; + uint32_t stores_per_frame; + + struct { + uint32_t sync_cmd; /* must be _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME */ + uint32_t store_cmd; /* must be _STREAM2MMIO_CMD_TOKEN_STORE_PACKETS */ + } stream2mmio_cfg; +}; + +extern const uint32_t N_IBUF_CTRL_PROCS[N_IBUF_CTRL_ID]; + +#endif /* __IBUF_CTRL_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/input_system_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/input_system_global.h new file mode 100644 index 0000000..25e3f04 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/input_system_global.h @@ -0,0 +1,206 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ +#define __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ + +#define IS_INPUT_SYSTEM_VERSION_VERSION_2401 + +/* CSI reveiver has 3 ports. */ +#define N_CSI_PORTS (3) + +#include "isys_dma.h" /* isys2401_dma_channel, + * isys2401_dma_cfg_t + */ + +#include "ibuf_ctrl.h" /* ibuf_cfg_t, + * ibuf_ctrl_cfg_t + */ + +#include "isys_stream2mmio.h" /* stream2mmio_cfg_t */ + +#include "csi_rx.h" /* csi_rx_frontend_cfg_t, + * csi_rx_backend_cfg_t, + * csi_rx_backend_lut_entry_t + */ +#include "pixelgen.h" + + +#define INPUT_SYSTEM_N_STREAM_ID 6 /* maximum number of simultaneous + virtual channels supported*/ + +typedef enum { + INPUT_SYSTEM_ERR_NO_ERROR = 0, + INPUT_SYSTEM_ERR_CREATE_CHANNEL_FAIL, + INPUT_SYSTEM_ERR_CONFIGURE_CHANNEL_FAIL, + INPUT_SYSTEM_ERR_OPEN_CHANNEL_FAIL, + INPUT_SYSTEM_ERR_TRANSFER_FAIL, + INPUT_SYSTEM_ERR_CREATE_INPUT_PORT_FAIL, + INPUT_SYSTEM_ERR_CONFIGURE_INPUT_PORT_FAIL, + INPUT_SYSTEM_ERR_OPEN_INPUT_PORT_FAIL, + N_INPUT_SYSTEM_ERR +} input_system_err_t; + +typedef enum { + INPUT_SYSTEM_SOURCE_TYPE_UNDEFINED = 0, + INPUT_SYSTEM_SOURCE_TYPE_SENSOR, + INPUT_SYSTEM_SOURCE_TYPE_TPG, + INPUT_SYSTEM_SOURCE_TYPE_PRBS, + N_INPUT_SYSTEM_SOURCE_TYPE +} input_system_source_type_t; + +typedef enum { + INPUT_SYSTEM_POLL_ON_WAIT_FOR_FRAME, + INPUT_SYSTEM_POLL_ON_CAPTURE_REQUEST, +} input_system_polling_mode_t; + +typedef struct input_system_channel_s input_system_channel_t; +struct input_system_channel_s { + stream2mmio_ID_t stream2mmio_id; + stream2mmio_sid_ID_t stream2mmio_sid_id; + + ibuf_ctrl_ID_t ibuf_ctrl_id; + ib_buffer_t ib_buffer; + + isys2401_dma_ID_t dma_id; + isys2401_dma_channel dma_channel; +}; + +typedef struct input_system_channel_cfg_s input_system_channel_cfg_t; +struct input_system_channel_cfg_s { + stream2mmio_cfg_t stream2mmio_cfg; + ibuf_ctrl_cfg_t ibuf_ctrl_cfg; + isys2401_dma_cfg_t dma_cfg; + isys2401_dma_port_cfg_t dma_src_port_cfg; + isys2401_dma_port_cfg_t dma_dest_port_cfg; +}; + +typedef struct input_system_input_port_s input_system_input_port_t; +struct input_system_input_port_s { + input_system_source_type_t source_type; + + struct { + csi_rx_frontend_ID_t frontend_id; + csi_rx_backend_ID_t backend_id; + csi_mipi_packet_type_t packet_type; + csi_rx_backend_lut_entry_t backend_lut_entry; + } csi_rx; + + struct { + csi_mipi_packet_type_t packet_type; + csi_rx_backend_lut_entry_t backend_lut_entry; + } metadata; + + struct { + pixelgen_ID_t pixelgen_id; + } pixelgen; +}; + +typedef struct input_system_input_port_cfg_s input_system_input_port_cfg_t; +struct input_system_input_port_cfg_s { + struct { + csi_rx_frontend_cfg_t frontend_cfg; + csi_rx_backend_cfg_t backend_cfg; + csi_rx_backend_cfg_t md_backend_cfg; + } csi_rx_cfg; + + struct { + pixelgen_tpg_cfg_t tpg_cfg; + pixelgen_prbs_cfg_t prbs_cfg; + } pixelgen_cfg; +}; + +typedef struct input_system_cfg_s input_system_cfg_t; +struct input_system_cfg_s { + input_system_input_port_ID_t input_port_id; + + input_system_source_type_t mode; +#ifdef ISP2401 + input_system_polling_mode_t polling_mode; +#endif + + bool online; + bool raw_packed; + int8_t linked_isys_stream_id; + + struct { + bool comp_enable; + int32_t active_lanes; + int32_t fmt_type; + int32_t ch_id; + int32_t comp_predictor; + int32_t comp_scheme; + } csi_port_attr; + + pixelgen_tpg_cfg_t tpg_port_attr; + + pixelgen_prbs_cfg_t prbs_port_attr; + + struct { + int32_t align_req_in_bytes; + int32_t bits_per_pixel; + int32_t pixels_per_line; + int32_t lines_per_frame; + } input_port_resolution; + + struct { + int32_t left_padding; + int32_t max_isp_input_width; + } output_port_attr; + + struct { + bool enable; + int32_t fmt_type; + int32_t align_req_in_bytes; + int32_t bits_per_pixel; + int32_t pixels_per_line; + int32_t lines_per_frame; + } metadata; +}; + +typedef struct virtual_input_system_stream_s virtual_input_system_stream_t; +struct virtual_input_system_stream_s { + uint32_t id; /*Used when multiple MIPI data types and/or virtual channels are used. + Must be unique within one CSI RX + and lower than SH_CSS_MAX_ISYS_CHANNEL_NODES */ + uint8_t enable_metadata; + input_system_input_port_t input_port; + input_system_channel_t channel; + input_system_channel_t md_channel; /* metadata channel */ + uint8_t online; + int8_t linked_isys_stream_id; + uint8_t valid; +#ifdef ISP2401 + input_system_polling_mode_t polling_mode; + int32_t subscr_index; +#endif +}; + +typedef struct virtual_input_system_stream_cfg_s virtual_input_system_stream_cfg_t; +struct virtual_input_system_stream_cfg_s { + uint8_t enable_metadata; + input_system_input_port_cfg_t input_port_cfg; + input_system_channel_cfg_t channel_cfg; + input_system_channel_cfg_t md_channel_cfg; + uint8_t valid; +}; + +#define ISP_INPUT_BUF_START_ADDR 0 +#define NUM_OF_INPUT_BUF 2 +#define NUM_OF_LINES_PER_BUF 2 +#define LINES_OF_ISP_INPUT_BUF (NUM_OF_INPUT_BUF * NUM_OF_LINES_PER_BUF) +#define ISP_INPUT_BUF_STRIDE SH_CSS_MAX_SENSOR_WIDTH + + +#endif /* __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_dma_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_dma_global.h new file mode 100644 index 0000000..e7a734a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_dma_global.h @@ -0,0 +1,87 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_DMA_GLOBAL_H_INCLUDED__ +#define __ISYS_DMA_GLOBAL_H_INCLUDED__ + +#include <type_support.h> + +#define HIVE_ISYS2401_DMA_IBUF_DDR_CONN 0 +#define HIVE_ISYS2401_DMA_IBUF_VMEM_CONN 1 +#define _DMA_V2_ZERO_EXTEND 0 +#define _DMA_V2_SIGN_EXTEND 1 + +#define _DMA_ZERO_EXTEND _DMA_V2_ZERO_EXTEND +#define _DMA_SIGN_EXTEND _DMA_V2_SIGN_EXTEND + +/******************************************************** + * + * DMA Port. + * + * The DMA port definition for the input system + * 2401 DMA is the duplication of the DMA port + * definition for the CSS system DMA. It is duplicated + * here just as the temporal step before the device libary + * is available. The device libary is suppose to provide + * the capability of reusing the control interface of the + * same device prototypes. The refactor team will work on + * this, right? + * + ********************************************************/ +typedef struct isys2401_dma_port_cfg_s isys2401_dma_port_cfg_t; +struct isys2401_dma_port_cfg_s { + uint32_t stride; + uint32_t elements; + uint32_t cropping; + uint32_t width; + }; +/** end of DMA Port */ + +/************************************************ + * + * DMA Device. + * + * The DMA device definition for the input system + * 2401 DMA is the duplicattion of the DMA device + * definition for the CSS system DMA. It is duplicated + * here just as the temporal step before the device libary + * is available. The device libary is suppose to provide + * the capability of reusing the control interface of the + * same device prototypes. The refactor team will work on + * this, right? + * + ************************************************/ +typedef enum { + isys2401_dma_ibuf_to_ddr_connection = HIVE_ISYS2401_DMA_IBUF_DDR_CONN, + isys2401_dma_ibuf_to_vmem_connection = HIVE_ISYS2401_DMA_IBUF_VMEM_CONN +} isys2401_dma_connection; + +typedef enum { + isys2401_dma_zero_extension = _DMA_ZERO_EXTEND, + isys2401_dma_sign_extension = _DMA_SIGN_EXTEND +} isys2401_dma_extension; + +typedef struct isys2401_dma_cfg_s isys2401_dma_cfg_t; +struct isys2401_dma_cfg_s { + isys2401_dma_channel channel; + isys2401_dma_connection connection; + isys2401_dma_extension extension; + uint32_t height; +}; +/** end of DMA Device */ + +/* isys2401_dma_channel limits per DMA ID */ +extern const isys2401_dma_channel N_ISYS2401_DMA_CHANNEL_PROCS[N_ISYS2401_DMA_ID]; + +#endif /* __ISYS_DMA_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_irq_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_irq_global.h new file mode 100644 index 0000000..41d051d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_irq_global.h @@ -0,0 +1,35 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_IRQ_GLOBAL_H__ +#define __ISYS_IRQ_GLOBAL_H__ + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + +/* Register offset/index from base location */ +#define ISYS_IRQ_EDGE_REG_IDX (0) +#define ISYS_IRQ_MASK_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 1) +#define ISYS_IRQ_STATUS_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 2) +#define ISYS_IRQ_CLEAR_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 3) +#define ISYS_IRQ_ENABLE_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 4) +#define ISYS_IRQ_LEVEL_NO_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 5) + +/* Register values */ +#define ISYS_IRQ_MASK_REG_VALUE (0xFFFF) +#define ISYS_IRQ_CLEAR_REG_VALUE (0xFFFF) +#define ISYS_IRQ_ENABLE_REG_VALUE (0xFFFF) + +#endif /* defined(USE_INPUT_SYSTEM_VERSION_2401) */ + +#endif /* __ISYS_IRQ_GLOBAL_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_stream2mmio_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_stream2mmio_global.h new file mode 100644 index 0000000..649f44f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_stream2mmio_global.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_STREAM2MMIO_GLOBAL_H_INCLUDED__ +#define __ISYS_STREAM2MMIO_GLOBAL_H_INCLUDED__ + +#include <type_support.h> + +typedef struct stream2mmio_cfg_s stream2mmio_cfg_t; +struct stream2mmio_cfg_s { + uint32_t bits_per_pixel; + uint32_t enable_blocking; +}; + +/* Stream2MMIO limits per ID*/ +/* + * Stream2MMIO 0 has 8 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID]. + * + * Stream2MMIO 1 has 4 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID]. + * + * Stream2MMIO 2 has 4 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID]. + */ +extern const stream2mmio_sid_ID_t N_STREAM2MMIO_SID_PROCS[N_STREAM2MMIO_ID]; + +#endif /* __ISYS_STREAM2MMIO_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/pixelgen_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/pixelgen_global.h new file mode 100644 index 0000000..216813e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/pixelgen_global.h @@ -0,0 +1,91 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PIXELGEN_GLOBAL_H_INCLUDED__ +#define __PIXELGEN_GLOBAL_H_INCLUDED__ + +#include <type_support.h> + +/** + * Pixel-generator. ("pixelgen_global.h") + */ +/* + * Duplicates "sync_generator_cfg_t" in "input_system_global.h". + */ +typedef struct sync_generator_cfg_s sync_generator_cfg_t; +struct sync_generator_cfg_s { + uint32_t hblank_cycles; + uint32_t vblank_cycles; + uint32_t pixels_per_clock; + uint32_t nr_of_frames; + uint32_t pixels_per_line; + uint32_t lines_per_frame; +}; + +typedef enum { + PIXELGEN_TPG_MODE_RAMP = 0, + PIXELGEN_TPG_MODE_CHBO, + PIXELGEN_TPG_MODE_MONO, + N_PIXELGEN_TPG_MODE +} pixelgen_tpg_mode_t; + +/* + * "pixelgen_tpg_cfg_t" duplicates parts of + * "tpg_cfg_t" in "input_system_global.h". + */ +typedef struct pixelgen_tpg_cfg_s pixelgen_tpg_cfg_t; +struct pixelgen_tpg_cfg_s { + pixelgen_tpg_mode_t mode; /* CHBO, MONO */ + + struct { + /* be used by CHBO and MON */ + uint32_t R1; + uint32_t G1; + uint32_t B1; + + /* be used by CHBO only */ + uint32_t R2; + uint32_t G2; + uint32_t B2; + } color_cfg; + + struct { + uint32_t h_mask; /* horizontal mask */ + uint32_t v_mask; /* vertical mask */ + uint32_t hv_mask; /* horizontal+vertical mask? */ + } mask_cfg; + + struct { + int32_t h_delta; /* horizontal delta? */ + int32_t v_delta; /* vertical delta? */ + } delta_cfg; + + sync_generator_cfg_t sync_gen_cfg; +}; + +/* + * "pixelgen_prbs_cfg_t" duplicates parts of + * prbs_cfg_t" in "input_system_global.h". + */ +typedef struct pixelgen_prbs_cfg_s pixelgen_prbs_cfg_t; +struct pixelgen_prbs_cfg_s { + int32_t seed0; + int32_t seed1; + + sync_generator_cfg_t sync_gen_cfg; +}; + +/** end of Pixel-generator: TPG. ("pixelgen_global.h") */ +#endif /* __PIXELGEN_GLOBAL_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/spmem_dump.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/spmem_dump.c new file mode 100644 index 0000000..d733a35 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/spmem_dump.c @@ -0,0 +1,3686 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _sp_map_h_ +#define _sp_map_h_ + + +#ifndef _hrt_dummy_use_blob_sp +#define _hrt_dummy_use_blob_sp() +#endif + +#define _hrt_cell_load_program_sp(proc) _hrt_cell_load_program_embedded(proc, sp) + +#ifndef ISP2401 +/* function longjmp: 680D */ +#else +/* function longjmp: 6A0B */ +#endif + +#ifndef ISP2401 +/* function tmpmem_init_dmem: 6558 */ +#else +/* function tmpmem_init_dmem: 671E */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_addr_B: 3C50 */ +#else +/* function ia_css_dmaproxy_sp_set_addr_B: 3DC5 */ + +/* function ia_css_pipe_data_init_tagger_resources: AC7 */ +#endif + +/* function debug_buffer_set_ddr_addr: DD */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_mipi +#define HIVE_MEM_vbuf_mipi scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_mipi 0x7398 +#else +#define HIVE_ADDR_vbuf_mipi 0x7444 +#endif +#define HIVE_SIZE_vbuf_mipi 12 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_mipi scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_mipi 0x7398 +#else +#define HIVE_ADDR_sp_vbuf_mipi 0x7444 +#endif +#define HIVE_SIZE_sp_vbuf_mipi 12 + +#ifndef ISP2401 +/* function ia_css_event_sp_decode: 3E41 */ +#else +/* function ia_css_event_sp_decode: 3FB6 */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_get_size: 51BF */ +#else +/* function ia_css_queue_get_size: 53C8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_load: 5800 */ +#else +/* function ia_css_queue_load: 59DF */ +#endif + +#ifndef ISP2401 +/* function setjmp: 6816 */ +#else +/* function setjmp: 6A14 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_sfi_get_current_frame: 27BF */ +#else +/* function ia_css_pipeline_sp_sfi_get_current_frame: 2790 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_sp2host_isys_event_queue +#define HIVE_MEM_sem_for_sp2host_isys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_sp2host_isys_event_queue 0x5760 +#else +#define HIVE_ADDR_sem_for_sp2host_isys_event_queue 0x57FC +#endif +#define HIVE_SIZE_sem_for_sp2host_isys_event_queue 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_sp2host_isys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_sp2host_isys_event_queue 0x5760 +#else +#define HIVE_ADDR_sp_sem_for_sp2host_isys_event_queue 0x57FC +#endif +#define HIVE_SIZE_sp_sem_for_sp2host_isys_event_queue 20 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_wait_for_ack: 6DA9 */ +#else +/* function ia_css_dmaproxy_sp_wait_for_ack: 6FF7 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_func: 596B */ +#else +/* function ia_css_sp_rawcopy_func: 5B4A */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_pop_marked: 3339 */ +#else +/* function ia_css_tagger_buf_sp_pop_marked: 345C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_CSI_RX_BE_SID_WIDTH +#define HIVE_MEM_N_CSI_RX_BE_SID_WIDTH scalar_processor_2400_dmem +#define HIVE_ADDR_N_CSI_RX_BE_SID_WIDTH 0x1D0 +#define HIVE_SIZE_N_CSI_RX_BE_SID_WIDTH 12 +#else +#endif +#endif +#define HIVE_MEM_sp_N_CSI_RX_BE_SID_WIDTH scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_CSI_RX_BE_SID_WIDTH 0x1D0 +#define HIVE_SIZE_sp_N_CSI_RX_BE_SID_WIDTH 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_stage +#define HIVE_MEM_isp_stage scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_stage 0x6C98 +#else +#define HIVE_ADDR_isp_stage 0x6D48 +#endif +#define HIVE_SIZE_isp_stage 832 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_stage scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_stage 0x6C98 +#else +#define HIVE_ADDR_sp_isp_stage 0x6D48 +#endif +#define HIVE_SIZE_sp_isp_stage 832 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_raw +#define HIVE_MEM_vbuf_raw scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_raw 0x37C +#else +#define HIVE_ADDR_vbuf_raw 0x394 +#endif +#define HIVE_SIZE_vbuf_raw 4 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_raw scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_raw 0x37C +#else +#define HIVE_ADDR_sp_vbuf_raw 0x394 +#endif +#define HIVE_SIZE_sp_vbuf_raw 4 + +#ifndef ISP2401 +/* function ia_css_sp_bin_copy_func: 594C */ +#else +/* function ia_css_sp_bin_copy_func: 5B2B */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_item_store: 554E */ +#else +/* function ia_css_queue_item_store: 572D */ +#endif + +#ifndef ISP2401 +/* function input_system_reset: 1286 */ +#else +/* function input_system_reset: 1201 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_metadata_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_metadata_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_metadata_bufs 0x5B38 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_metadata_bufs 0x5BE4 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_metadata_bufs 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_metadata_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 0x5B38 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 0x5BE4 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_buffer_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_buffer_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_buffer_bufs 0x5B4C +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_buffer_bufs 0x5BF8 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_buffer_bufs 160 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_buffer_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 0x5B4C +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 0x5BF8 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 160 + +/* function sp_start_isp: 39C */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_binary_group +#define HIVE_MEM_sp_binary_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_binary_group 0x7088 +#else +#define HIVE_ADDR_sp_binary_group 0x7138 +#endif +#define HIVE_SIZE_sp_binary_group 32 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_binary_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_binary_group 0x7088 +#else +#define HIVE_ADDR_sp_sp_binary_group 0x7138 +#endif +#define HIVE_SIZE_sp_sp_binary_group 32 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_sw_state +#define HIVE_MEM_sp_sw_state scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sw_state 0x7344 +#else +#define HIVE_ADDR_sp_sw_state 0x73F0 +#endif +#define HIVE_SIZE_sp_sw_state 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_sw_state scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_sw_state 0x7344 +#else +#define HIVE_ADDR_sp_sp_sw_state 0x73F0 +#endif +#define HIVE_SIZE_sp_sp_sw_state 4 + +#ifndef ISP2401 +/* function ia_css_thread_sp_main: 13F7 */ +#else +/* function ia_css_thread_sp_main: 136D */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_internal_buffers: 4047 */ +#else +/* function ia_css_ispctrl_sp_init_internal_buffers: 41F7 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp2host_psys_event_queue_handle +#define HIVE_MEM_sp2host_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp2host_psys_event_queue_handle 0x5BEC +#else +#define HIVE_ADDR_sp2host_psys_event_queue_handle 0x5C98 +#endif +#define HIVE_SIZE_sp2host_psys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_sp2host_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp2host_psys_event_queue_handle 0x5BEC +#else +#define HIVE_ADDR_sp_sp2host_psys_event_queue_handle 0x5C98 +#endif +#define HIVE_SIZE_sp_sp2host_psys_event_queue_handle 12 + +#ifndef ISP2401 +/* function pixelgen_unit_test: E68 */ +#else +/* function pixelgen_unit_test: E62 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_sp2host_psys_event_queue +#define HIVE_MEM_sem_for_sp2host_psys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_sp2host_psys_event_queue 0x5774 +#else +#define HIVE_ADDR_sem_for_sp2host_psys_event_queue 0x5810 +#endif +#define HIVE_SIZE_sem_for_sp2host_psys_event_queue 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_sp2host_psys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_sp2host_psys_event_queue 0x5774 +#else +#define HIVE_ADDR_sp_sem_for_sp2host_psys_event_queue 0x5810 +#endif +#define HIVE_SIZE_sp_sem_for_sp2host_psys_event_queue 20 + +#ifndef ISP2401 +/* function ia_css_tagger_sp_propagate_frame: 2D52 */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_stop_copy_preview +#define HIVE_MEM_sp_stop_copy_preview scalar_processor_2400_dmem +#define HIVE_ADDR_sp_stop_copy_preview 0x7328 +#define HIVE_SIZE_sp_stop_copy_preview 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_stop_copy_preview scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_stop_copy_preview 0x7328 +#define HIVE_SIZE_sp_sp_stop_copy_preview 4 +#else +/* function ia_css_tagger_sp_propagate_frame: 2D23 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_handles +#define HIVE_MEM_vbuf_handles scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_handles 0x73A4 +#else +#define HIVE_ADDR_vbuf_handles 0x7450 +#endif +#define HIVE_SIZE_vbuf_handles 960 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_handles scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_handles 0x73A4 +#else +#define HIVE_ADDR_sp_vbuf_handles 0x7450 +#endif +#define HIVE_SIZE_sp_vbuf_handles 960 + +#ifndef ISP2401 +/* function ia_css_queue_store: 56B4 */ + +/* function ia_css_sp_flash_register: 356E */ +#else +/* function ia_css_queue_store: 5893 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_dummy_function: 5CF7 */ +#else +/* function ia_css_sp_flash_register: 3691 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_init: 201C */ +#else +/* function ia_css_pipeline_sp_init: 1FD7 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_configure: 2C42 */ +#else +/* function ia_css_tagger_sp_configure: 2C13 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_end_binary: 3E8A */ +#else +/* function ia_css_ispctrl_sp_end_binary: 3FFF */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs +#define HIVE_MEM_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x5BF8 +#else +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x5CA4 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x5BF8 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x5CA4 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 20 + +#ifndef ISP2401 +/* function pixelgen_tpg_run: F1E */ +#else +/* function pixelgen_tpg_run: F18 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_event_is_pending_mask +#define HIVE_MEM_event_is_pending_mask scalar_processor_2400_dmem +#define HIVE_ADDR_event_is_pending_mask 0x5C +#define HIVE_SIZE_event_is_pending_mask 44 +#else +#endif +#endif +#define HIVE_MEM_sp_event_is_pending_mask scalar_processor_2400_dmem +#define HIVE_ADDR_sp_event_is_pending_mask 0x5C +#define HIVE_SIZE_sp_event_is_pending_mask 44 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cb_elems_frame +#define HIVE_MEM_sp_all_cb_elems_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cb_elems_frame 0x5788 +#else +#define HIVE_ADDR_sp_all_cb_elems_frame 0x5824 +#endif +#define HIVE_SIZE_sp_all_cb_elems_frame 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cb_elems_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cb_elems_frame 0x5788 +#else +#define HIVE_ADDR_sp_sp_all_cb_elems_frame 0x5824 +#endif +#define HIVE_SIZE_sp_sp_all_cb_elems_frame 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp2host_isys_event_queue_handle +#define HIVE_MEM_sp2host_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp2host_isys_event_queue_handle 0x5C0C +#else +#define HIVE_ADDR_sp2host_isys_event_queue_handle 0x5CB8 +#endif +#define HIVE_SIZE_sp2host_isys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_sp2host_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp2host_isys_event_queue_handle 0x5C0C +#else +#define HIVE_ADDR_sp_sp2host_isys_event_queue_handle 0x5CB8 +#endif +#define HIVE_SIZE_sp_sp2host_isys_event_queue_handle 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host_sp_com +#define HIVE_MEM_host_sp_com scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host_sp_com 0x3E48 +#else +#define HIVE_ADDR_host_sp_com 0x3E6C +#endif +#define HIVE_SIZE_host_sp_com 220 +#else +#endif +#endif +#define HIVE_MEM_sp_host_sp_com scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host_sp_com 0x3E48 +#else +#define HIVE_ADDR_sp_host_sp_com 0x3E6C +#endif +#define HIVE_SIZE_sp_host_sp_com 220 + +#ifndef ISP2401 +/* function ia_css_queue_get_free_space: 5313 */ +#else +/* function ia_css_queue_get_free_space: 54F2 */ +#endif + +#ifndef ISP2401 +/* function exec_image_pipe: 5E6 */ +#else +/* function exec_image_pipe: 57A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_init_dmem_data +#define HIVE_MEM_sp_init_dmem_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_init_dmem_data 0x7348 +#else +#define HIVE_ADDR_sp_init_dmem_data 0x73F4 +#endif +#define HIVE_SIZE_sp_init_dmem_data 24 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_init_dmem_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_init_dmem_data 0x7348 +#else +#define HIVE_ADDR_sp_sp_init_dmem_data 0x73F4 +#endif +#define HIVE_SIZE_sp_sp_init_dmem_data 24 + +#ifndef ISP2401 +/* function ia_css_sp_metadata_start: 5DD1 */ +#else +/* function ia_css_sp_metadata_start: 5EB3 */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_init_buffer_queues: 35BF */ +#else +/* function ia_css_bufq_sp_init_buffer_queues: 36E2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_stop: 1FFF */ +#else +/* function ia_css_pipeline_sp_stop: 1FBA */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_connect_pipes: 312C */ +#else +/* function ia_css_tagger_sp_connect_pipes: 30FD */ +#endif + +#ifndef ISP2401 +/* function sp_isys_copy_wait: 644 */ +#else +/* function sp_isys_copy_wait: 5D8 */ +#endif + +/* function is_isp_debug_buffer_full: 337 */ + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_configure_channel_from_info: 3BD3 */ +#else +/* function ia_css_dmaproxy_sp_configure_channel_from_info: 3D35 */ +#endif + +#ifndef ISP2401 +/* function encode_and_post_timer_event: AA8 */ +#else +/* function encode_and_post_timer_event: A3C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_input_system_bz2788_active +#define HIVE_MEM_input_system_bz2788_active scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_input_system_bz2788_active 0x250C +#else +#define HIVE_ADDR_input_system_bz2788_active 0x2524 +#endif +#define HIVE_SIZE_input_system_bz2788_active 4 +#else +#endif +#endif +#define HIVE_MEM_sp_input_system_bz2788_active scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_input_system_bz2788_active 0x250C +#else +#define HIVE_ADDR_sp_input_system_bz2788_active 0x2524 +#endif +#define HIVE_SIZE_sp_input_system_bz2788_active 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_IBUF_CTRL_PROCS +#define HIVE_MEM_N_IBUF_CTRL_PROCS scalar_processor_2400_dmem +#define HIVE_ADDR_N_IBUF_CTRL_PROCS 0x1FC +#define HIVE_SIZE_N_IBUF_CTRL_PROCS 12 +#else +#endif +#endif +#define HIVE_MEM_sp_N_IBUF_CTRL_PROCS scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_IBUF_CTRL_PROCS 0x1FC +#define HIVE_SIZE_sp_N_IBUF_CTRL_PROCS 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_per_frame_data +#define HIVE_MEM_sp_per_frame_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_per_frame_data 0x3F24 +#else +#define HIVE_ADDR_sp_per_frame_data 0x3F48 +#endif +#define HIVE_SIZE_sp_per_frame_data 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_per_frame_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_per_frame_data 0x3F24 +#else +#define HIVE_ADDR_sp_sp_per_frame_data 0x3F48 +#endif +#define HIVE_SIZE_sp_sp_per_frame_data 4 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_vbuf_dequeue: 62AC */ +#else +/* function ia_css_rmgr_sp_vbuf_dequeue: 6472 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_psys_event_queue_handle +#define HIVE_MEM_host2sp_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_psys_event_queue_handle 0x5C18 +#else +#define HIVE_ADDR_host2sp_psys_event_queue_handle 0x5CC4 +#endif +#define HIVE_SIZE_host2sp_psys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_psys_event_queue_handle 0x5C18 +#else +#define HIVE_ADDR_sp_host2sp_psys_event_queue_handle 0x5CC4 +#endif +#define HIVE_SIZE_sp_host2sp_psys_event_queue_handle 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_xmem_bin_addr +#define HIVE_MEM_xmem_bin_addr scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_xmem_bin_addr 0x3F28 +#else +#define HIVE_ADDR_xmem_bin_addr 0x3F4C +#endif +#define HIVE_SIZE_xmem_bin_addr 4 +#else +#endif +#endif +#define HIVE_MEM_sp_xmem_bin_addr scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_xmem_bin_addr 0x3F28 +#else +#define HIVE_ADDR_sp_xmem_bin_addr 0x3F4C +#endif +#define HIVE_SIZE_sp_xmem_bin_addr 4 + +#ifndef ISP2401 +/* function tmr_clock_init: 16F9 */ +#else +/* function tmr_clock_init: 166F */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_run: 1ABF */ +#else +/* function ia_css_pipeline_sp_run: 1A61 */ +#endif + +#ifndef ISP2401 +/* function memcpy: 68B6 */ +#else +/* function memcpy: 6AB4 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_ISYS2401_DMA_CHANNEL_PROCS +#define HIVE_MEM_N_ISYS2401_DMA_CHANNEL_PROCS scalar_processor_2400_dmem +#define HIVE_ADDR_N_ISYS2401_DMA_CHANNEL_PROCS 0x214 +#define HIVE_SIZE_N_ISYS2401_DMA_CHANNEL_PROCS 4 +#else +#endif +#endif +#define HIVE_MEM_sp_N_ISYS2401_DMA_CHANNEL_PROCS scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_ISYS2401_DMA_CHANNEL_PROCS 0x214 +#define HIVE_SIZE_sp_N_ISYS2401_DMA_CHANNEL_PROCS 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_GP_DEVICE_BASE +#define HIVE_MEM_GP_DEVICE_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_GP_DEVICE_BASE 0x384 +#else +#define HIVE_ADDR_GP_DEVICE_BASE 0x39C +#endif +#define HIVE_SIZE_GP_DEVICE_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_GP_DEVICE_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_GP_DEVICE_BASE 0x384 +#else +#define HIVE_ADDR_sp_GP_DEVICE_BASE 0x39C +#endif +#define HIVE_SIZE_sp_GP_DEVICE_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_thread_sp_ready_queue +#define HIVE_MEM_ia_css_thread_sp_ready_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_thread_sp_ready_queue 0x278 +#else +#define HIVE_ADDR_ia_css_thread_sp_ready_queue 0x27C +#endif +#define HIVE_SIZE_ia_css_thread_sp_ready_queue 12 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_thread_sp_ready_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_thread_sp_ready_queue 0x278 +#else +#define HIVE_ADDR_sp_ia_css_thread_sp_ready_queue 0x27C +#endif +#define HIVE_SIZE_sp_ia_css_thread_sp_ready_queue 12 + +#ifndef ISP2401 +/* function stream2mmio_send_command: E0A */ +#else +/* function stream2mmio_send_command: E04 */ +#endif + +#ifndef ISP2401 +/* function ia_css_uds_sp_scale_params: 65BF */ +#else +/* function ia_css_uds_sp_scale_params: 67BD */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_increase_size: 14DC */ +#else +/* function ia_css_circbuf_increase_size: 1452 */ +#endif + +#ifndef ISP2401 +/* function __divu: 6834 */ +#else +/* function __divu: 6A32 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_get_state: 131F */ +#else +/* function ia_css_thread_sp_get_state: 1295 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_cont_capt_stop +#define HIVE_MEM_sem_for_cont_capt_stop scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_cont_capt_stop 0x5798 +#else +#define HIVE_ADDR_sem_for_cont_capt_stop 0x5834 +#endif +#define HIVE_SIZE_sem_for_cont_capt_stop 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_cont_capt_stop scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_cont_capt_stop 0x5798 +#else +#define HIVE_ADDR_sp_sem_for_cont_capt_stop 0x5834 +#endif +#define HIVE_SIZE_sp_sem_for_cont_capt_stop 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_SHORT_PACKET_LUT_ENTRIES +#define HIVE_MEM_N_SHORT_PACKET_LUT_ENTRIES scalar_processor_2400_dmem +#define HIVE_ADDR_N_SHORT_PACKET_LUT_ENTRIES 0x1AC +#define HIVE_SIZE_N_SHORT_PACKET_LUT_ENTRIES 12 +#else +#endif +#endif +#define HIVE_MEM_sp_N_SHORT_PACKET_LUT_ENTRIES scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_SHORT_PACKET_LUT_ENTRIES 0x1AC +#define HIVE_SIZE_sp_N_SHORT_PACKET_LUT_ENTRIES 12 + +#ifndef ISP2401 +/* function thread_fiber_sp_main: 14D5 */ +#else +/* function thread_fiber_sp_main: 144B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_isp_pipe_thread +#define HIVE_MEM_sp_isp_pipe_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_pipe_thread 0x58DC +#define HIVE_SIZE_sp_isp_pipe_thread 340 +#else +#define HIVE_ADDR_sp_isp_pipe_thread 0x5978 +#define HIVE_SIZE_sp_isp_pipe_thread 360 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_isp_pipe_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_isp_pipe_thread 0x58DC +#define HIVE_SIZE_sp_sp_isp_pipe_thread 340 +#else +#define HIVE_ADDR_sp_sp_isp_pipe_thread 0x5978 +#define HIVE_SIZE_sp_sp_isp_pipe_thread 360 +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_handle_parameter_sets: 193F */ +#else +/* function ia_css_parambuf_sp_handle_parameter_sets: 18B5 */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_set_state: 5DED */ +#else +/* function ia_css_spctrl_sp_set_state: 5ECF */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sem_sp_signal: 6A99 */ +#else +/* function ia_css_thread_sem_sp_signal: 6D18 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_IRQ_BASE +#define HIVE_MEM_IRQ_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_IRQ_BASE 0x2C +#define HIVE_SIZE_IRQ_BASE 16 +#else +#endif +#endif +#define HIVE_MEM_sp_IRQ_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_IRQ_BASE 0x2C +#define HIVE_SIZE_sp_IRQ_BASE 16 + +#ifndef ISP2401 +/* function ia_css_virtual_isys_sp_isr_init: 5E8C */ +#else +/* function ia_css_virtual_isys_sp_isr_init: 5F70 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_TIMED_CTRL_BASE +#define HIVE_MEM_TIMED_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_TIMED_CTRL_BASE 0x40 +#define HIVE_SIZE_TIMED_CTRL_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_TIMED_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_TIMED_CTRL_BASE 0x40 +#define HIVE_SIZE_sp_TIMED_CTRL_BASE 4 + +#ifndef ISP2401 +/* function ia_css_isys_sp_generate_exp_id: 613C */ + +/* function ia_css_rmgr_sp_init: 61A7 */ +#else +/* function ia_css_isys_sp_generate_exp_id: 6302 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sem_sp_init: 6B6A */ +#else +/* function ia_css_rmgr_sp_init: 636D */ +#endif + +#ifndef ISP2401 +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_is_isp_requested +#define HIVE_MEM_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_is_isp_requested 0x390 +#define HIVE_SIZE_is_isp_requested 4 +#else +#endif +#endif +#define HIVE_MEM_sp_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_sp_is_isp_requested 0x390 +#define HIVE_SIZE_sp_is_isp_requested 4 +#else +/* function ia_css_thread_sem_sp_init: 6DE7 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_reading_cb_frame +#define HIVE_MEM_sem_for_reading_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_reading_cb_frame 0x57AC +#else +#define HIVE_ADDR_sem_for_reading_cb_frame 0x5848 +#endif +#define HIVE_SIZE_sem_for_reading_cb_frame 40 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_reading_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_reading_cb_frame 0x57AC +#else +#define HIVE_ADDR_sp_sem_for_reading_cb_frame 0x5848 +#endif +#define HIVE_SIZE_sp_sem_for_reading_cb_frame 40 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_execute: 3B3B */ +#else +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_is_isp_requested +#define HIVE_MEM_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_is_isp_requested 0x3A8 +#define HIVE_SIZE_is_isp_requested 4 +#else +#endif +#endif +#define HIVE_MEM_sp_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_sp_is_isp_requested 0x3A8 +#define HIVE_SIZE_sp_is_isp_requested 4 + +/* function ia_css_dmaproxy_sp_execute: 3C9B */ +#endif + +#ifndef ISP2401 +/* function csi_rx_backend_rst: CE6 */ +#else +/* function csi_rx_backend_rst: CE0 */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_is_empty: 51FA */ +#else +/* function ia_css_queue_is_empty: 7144 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_has_stopped: 1FF5 */ +#else +/* function ia_css_pipeline_sp_has_stopped: 1FB0 */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_extract: 15E0 */ +#else +/* function ia_css_circbuf_extract: 1556 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_is_locked_from_start: 344F */ +#else +/* function ia_css_tagger_buf_sp_is_locked_from_start: 3572 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_current_sp_thread +#define HIVE_MEM_current_sp_thread scalar_processor_2400_dmem +#define HIVE_ADDR_current_sp_thread 0x274 +#define HIVE_SIZE_current_sp_thread 4 +#else +#endif +#endif +#define HIVE_MEM_sp_current_sp_thread scalar_processor_2400_dmem +#define HIVE_ADDR_sp_current_sp_thread 0x274 +#define HIVE_SIZE_sp_current_sp_thread 4 + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_get_spid: 5DF4 */ +#else +/* function ia_css_spctrl_sp_get_spid: 5ED6 */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_reset_buffers: 3646 */ +#else +/* function ia_css_bufq_sp_reset_buffers: 3769 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_read_byte_addr: 6DD7 */ +#else +/* function ia_css_dmaproxy_sp_read_byte_addr: 7025 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_uninit: 61A0 */ +#else +/* function ia_css_rmgr_sp_uninit: 6366 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_threads_stack +#define HIVE_MEM_sp_threads_stack scalar_processor_2400_dmem +#define HIVE_ADDR_sp_threads_stack 0x164 +#define HIVE_SIZE_sp_threads_stack 24 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_threads_stack scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_threads_stack 0x164 +#define HIVE_SIZE_sp_sp_threads_stack 24 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_STREAM2MMIO_SID_PROCS +#define HIVE_MEM_N_STREAM2MMIO_SID_PROCS scalar_processor_2400_dmem +#define HIVE_ADDR_N_STREAM2MMIO_SID_PROCS 0x218 +#define HIVE_SIZE_N_STREAM2MMIO_SID_PROCS 12 +#else +#endif +#endif +#define HIVE_MEM_sp_N_STREAM2MMIO_SID_PROCS scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_STREAM2MMIO_SID_PROCS 0x218 +#define HIVE_SIZE_sp_N_STREAM2MMIO_SID_PROCS 12 + +#ifndef ISP2401 +/* function ia_css_circbuf_peek: 15C2 */ +#else +/* function ia_css_circbuf_peek: 1538 */ +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_wait_for_in_param: 1708 */ +#else +/* function ia_css_parambuf_sp_wait_for_in_param: 167E */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cb_elems_param +#define HIVE_MEM_sp_all_cb_elems_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cb_elems_param 0x57D4 +#else +#define HIVE_ADDR_sp_all_cb_elems_param 0x5870 +#endif +#define HIVE_SIZE_sp_all_cb_elems_param 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cb_elems_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cb_elems_param 0x57D4 +#else +#define HIVE_ADDR_sp_sp_all_cb_elems_param 0x5870 +#endif +#define HIVE_SIZE_sp_sp_all_cb_elems_param 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_pipeline_sp_curr_binary_id +#define HIVE_MEM_pipeline_sp_curr_binary_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_pipeline_sp_curr_binary_id 0x284 +#else +#define HIVE_ADDR_pipeline_sp_curr_binary_id 0x288 +#endif +#define HIVE_SIZE_pipeline_sp_curr_binary_id 4 +#else +#endif +#endif +#define HIVE_MEM_sp_pipeline_sp_curr_binary_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_pipeline_sp_curr_binary_id 0x284 +#else +#define HIVE_ADDR_sp_pipeline_sp_curr_binary_id 0x288 +#endif +#define HIVE_SIZE_sp_pipeline_sp_curr_binary_id 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_frame_desc +#define HIVE_MEM_sp_all_cbs_frame_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_frame_desc 0x57E4 +#else +#define HIVE_ADDR_sp_all_cbs_frame_desc 0x5880 +#endif +#define HIVE_SIZE_sp_all_cbs_frame_desc 8 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_frame_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_frame_desc 0x57E4 +#else +#define HIVE_ADDR_sp_sp_all_cbs_frame_desc 0x5880 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_frame_desc 8 + +#ifndef ISP2401 +/* function sp_isys_copy_func_v2: 629 */ +#else +/* function sp_isys_copy_func_v2: 5BD */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_reading_cb_param +#define HIVE_MEM_sem_for_reading_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_reading_cb_param 0x57EC +#else +#define HIVE_ADDR_sem_for_reading_cb_param 0x5888 +#endif +#define HIVE_SIZE_sem_for_reading_cb_param 40 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_reading_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_reading_cb_param 0x57EC +#else +#define HIVE_ADDR_sp_sem_for_reading_cb_param 0x5888 +#endif +#define HIVE_SIZE_sp_sem_for_reading_cb_param 40 + +#ifndef ISP2401 +/* function ia_css_queue_get_used_space: 52C7 */ +#else +/* function ia_css_queue_get_used_space: 54A6 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_cont_capt_start +#define HIVE_MEM_sem_for_cont_capt_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_cont_capt_start 0x5814 +#else +#define HIVE_ADDR_sem_for_cont_capt_start 0x58B0 +#endif +#define HIVE_SIZE_sem_for_cont_capt_start 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_cont_capt_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_cont_capt_start 0x5814 +#else +#define HIVE_ADDR_sp_sem_for_cont_capt_start 0x58B0 +#endif +#define HIVE_SIZE_sp_sem_for_cont_capt_start 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_tmp_heap +#define HIVE_MEM_tmp_heap scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_tmp_heap 0x70A8 +#else +#define HIVE_ADDR_tmp_heap 0x7158 +#endif +#define HIVE_SIZE_tmp_heap 640 +#else +#endif +#endif +#define HIVE_MEM_sp_tmp_heap scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_tmp_heap 0x70A8 +#else +#define HIVE_ADDR_sp_tmp_heap 0x7158 +#endif +#define HIVE_SIZE_sp_tmp_heap 640 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_get_num_vbuf: 64B0 */ +#else +/* function ia_css_rmgr_sp_get_num_vbuf: 6676 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_output_compute_dma_info: 4863 */ +#else +/* function ia_css_ispctrl_sp_output_compute_dma_info: 4A27 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_lock_exp_id: 2A0F */ +#else +/* function ia_css_tagger_sp_lock_exp_id: 29E0 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_s3a_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_s3a_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_s3a_bufs 0x5C24 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_s3a_bufs 0x5CD0 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_s3a_bufs 60 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_s3a_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 0x5C24 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 0x5CD0 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 60 + +#ifndef ISP2401 +/* function ia_css_queue_is_full: 535E */ +#else +/* function ia_css_queue_is_full: 553D */ +#endif + +/* function debug_buffer_init_isp: E4 */ + +#ifndef ISP2401 +/* function ia_css_tagger_sp_exp_id_is_locked: 2945 */ +#else +/* function ia_css_tagger_sp_exp_id_is_locked: 2916 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_rmgr_sp_mipi_frame_sem +#define HIVE_MEM_ia_css_rmgr_sp_mipi_frame_sem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_rmgr_sp_mipi_frame_sem 0x7764 +#else +#define HIVE_ADDR_ia_css_rmgr_sp_mipi_frame_sem 0x7810 +#endif +#define HIVE_SIZE_ia_css_rmgr_sp_mipi_frame_sem 60 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_rmgr_sp_mipi_frame_sem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_rmgr_sp_mipi_frame_sem 0x7764 +#else +#define HIVE_ADDR_sp_ia_css_rmgr_sp_mipi_frame_sem 0x7810 +#endif +#define HIVE_SIZE_sp_ia_css_rmgr_sp_mipi_frame_sem 60 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_dump: 6287 */ +#else +/* function ia_css_rmgr_sp_refcount_dump: 644D */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_isp_parameters_id +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_isp_parameters_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x5C60 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x5D0C +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_isp_parameters_id 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x5C60 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x5D0C +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_pipe_threads +#define HIVE_MEM_sp_pipe_threads scalar_processor_2400_dmem +#define HIVE_ADDR_sp_pipe_threads 0x150 +#define HIVE_SIZE_sp_pipe_threads 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_pipe_threads scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_pipe_threads 0x150 +#define HIVE_SIZE_sp_sp_pipe_threads 20 + +#ifndef ISP2401 +/* function sp_event_proxy_func: 78D */ +#else +/* function sp_event_proxy_func: 721 */ +#endif + +#ifndef ISP2401 +/* function ibuf_ctrl_run: D7F */ +#else +/* function ibuf_ctrl_run: D79 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_isys_event_queue_handle +#define HIVE_MEM_host2sp_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_isys_event_queue_handle 0x5C74 +#else +#define HIVE_ADDR_host2sp_isys_event_queue_handle 0x5D20 +#endif +#define HIVE_SIZE_host2sp_isys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_isys_event_queue_handle 0x5C74 +#else +#define HIVE_ADDR_sp_host2sp_isys_event_queue_handle 0x5D20 +#endif +#define HIVE_SIZE_sp_host2sp_isys_event_queue_handle 12 + +#ifndef ISP2401 +/* function ia_css_thread_sp_yield: 6A12 */ +#else +/* function ia_css_thread_sp_yield: 6C96 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_param_desc +#define HIVE_MEM_sp_all_cbs_param_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_param_desc 0x5828 +#else +#define HIVE_ADDR_sp_all_cbs_param_desc 0x58C4 +#endif +#define HIVE_SIZE_sp_all_cbs_param_desc 8 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_param_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_param_desc 0x5828 +#else +#define HIVE_ADDR_sp_sp_all_cbs_param_desc 0x58C4 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_param_desc 8 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_dmaproxy_sp_invalidate_tlb +#define HIVE_MEM_ia_css_dmaproxy_sp_invalidate_tlb scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb 0x6C8C +#else +#define HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb 0x6D38 +#endif +#define HIVE_SIZE_ia_css_dmaproxy_sp_invalidate_tlb 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_dmaproxy_sp_invalidate_tlb scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_dmaproxy_sp_invalidate_tlb 0x6C8C +#else +#define HIVE_ADDR_sp_ia_css_dmaproxy_sp_invalidate_tlb 0x6D38 +#endif +#define HIVE_SIZE_sp_ia_css_dmaproxy_sp_invalidate_tlb 4 + +#ifndef ISP2401 +/* function ia_css_thread_sp_fork: 13AC */ +#else +/* function ia_css_thread_sp_fork: 1322 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_destroy: 3136 */ +#else +/* function ia_css_tagger_sp_destroy: 3107 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_vmem_read: 3ADB */ +#else +/* function ia_css_dmaproxy_sp_vmem_read: 3C3B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_LONG_PACKET_LUT_ENTRIES +#define HIVE_MEM_N_LONG_PACKET_LUT_ENTRIES scalar_processor_2400_dmem +#define HIVE_ADDR_N_LONG_PACKET_LUT_ENTRIES 0x1B8 +#define HIVE_SIZE_N_LONG_PACKET_LUT_ENTRIES 12 +#else +#endif +#endif +#define HIVE_MEM_sp_N_LONG_PACKET_LUT_ENTRIES scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_LONG_PACKET_LUT_ENTRIES 0x1B8 +#define HIVE_SIZE_sp_N_LONG_PACKET_LUT_ENTRIES 12 + +#ifndef ISP2401 +/* function initialize_sp_group: 5F6 */ +#else +/* function initialize_sp_group: 58A */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_peek: 325B */ +#else +/* function ia_css_tagger_buf_sp_peek: 337E */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_init: 13D8 */ +#else +/* function ia_css_thread_sp_init: 134E */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_reset_exp_id: 6133 */ +#else +/* function qos_scheduler_update_fps: 67AD */ +#endif + +#ifndef ISP2401 +/* function qos_scheduler_update_fps: 65AF */ +#else +/* function ia_css_isys_sp_reset_exp_id: 62F9 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_set_stream_base_addr: 4F38 */ +#else +/* function ia_css_ispctrl_sp_set_stream_base_addr: 5114 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_DMEM_BASE +#define HIVE_MEM_ISP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_DMEM_BASE 0x10 +#define HIVE_SIZE_ISP_DMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_DMEM_BASE 0x10 +#define HIVE_SIZE_sp_ISP_DMEM_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_SP_DMEM_BASE +#define HIVE_MEM_SP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_SP_DMEM_BASE 0x4 +#define HIVE_SIZE_SP_DMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_SP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_SP_DMEM_BASE 0x4 +#define HIVE_SIZE_sp_SP_DMEM_BASE 4 + +#ifndef ISP2401 +/* function ibuf_ctrl_transfer: D67 */ +#else +/* function ibuf_ctrl_transfer: D61 */ + +/* function __ia_css_queue_is_empty_text: 5403 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_read: 3B51 */ +#else +/* function ia_css_dmaproxy_sp_read: 3CB1 */ +#endif + +#ifndef ISP2401 +/* function virtual_isys_stream_is_capture_done: 5EB0 */ +#else +/* function virtual_isys_stream_is_capture_done: 5F94 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_raw_copy_line_count +#define HIVE_MEM_raw_copy_line_count scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_raw_copy_line_count 0x360 +#else +#define HIVE_ADDR_raw_copy_line_count 0x378 +#endif +#define HIVE_SIZE_raw_copy_line_count 4 +#else +#endif +#endif +#define HIVE_MEM_sp_raw_copy_line_count scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_raw_copy_line_count 0x360 +#else +#define HIVE_ADDR_sp_raw_copy_line_count 0x378 +#endif +#define HIVE_SIZE_sp_raw_copy_line_count 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_tag_cmd_queue_handle +#define HIVE_MEM_host2sp_tag_cmd_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_tag_cmd_queue_handle 0x5C80 +#else +#define HIVE_ADDR_host2sp_tag_cmd_queue_handle 0x5D2C +#endif +#define HIVE_SIZE_host2sp_tag_cmd_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_tag_cmd_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_tag_cmd_queue_handle 0x5C80 +#else +#define HIVE_ADDR_sp_host2sp_tag_cmd_queue_handle 0x5D2C +#endif +#define HIVE_SIZE_sp_host2sp_tag_cmd_queue_handle 12 + +#ifndef ISP2401 +/* function ia_css_queue_peek: 523D */ +#else +/* function ia_css_queue_peek: 541C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_frame_cnt +#define HIVE_MEM_ia_css_flash_sp_frame_cnt scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_frame_cnt 0x5B2C +#else +#define HIVE_ADDR_ia_css_flash_sp_frame_cnt 0x5BD8 +#endif +#define HIVE_SIZE_ia_css_flash_sp_frame_cnt 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_frame_cnt scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_frame_cnt 0x5B2C +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_frame_cnt 0x5BD8 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_frame_cnt 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_event_can_send_token_mask +#define HIVE_MEM_event_can_send_token_mask scalar_processor_2400_dmem +#define HIVE_ADDR_event_can_send_token_mask 0x88 +#define HIVE_SIZE_event_can_send_token_mask 44 +#else +#endif +#endif +#define HIVE_MEM_sp_event_can_send_token_mask scalar_processor_2400_dmem +#define HIVE_ADDR_sp_event_can_send_token_mask 0x88 +#define HIVE_SIZE_sp_event_can_send_token_mask 44 + +#ifndef ISP2401 +/* function csi_rx_frontend_stop: C11 */ +#else +/* function csi_rx_frontend_stop: C0B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_thread +#define HIVE_MEM_isp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_thread 0x6FD8 +#else +#define HIVE_ADDR_isp_thread 0x7088 +#endif +#define HIVE_SIZE_isp_thread 4 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_thread 0x6FD8 +#else +#define HIVE_ADDR_sp_isp_thread 0x7088 +#endif +#define HIVE_SIZE_sp_isp_thread 4 + +#ifndef ISP2401 +/* function encode_and_post_sp_event_non_blocking: AF0 */ +#else +/* function encode_and_post_sp_event_non_blocking: A84 */ +#endif + +/* function is_ddr_debug_buffer_full: 2CC */ + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_get_oldest_marked_offset: 32AB */ +#else +/* function ia_css_tagger_buf_sp_get_oldest_marked_offset: 33CE */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_threads_fiber +#define HIVE_MEM_sp_threads_fiber scalar_processor_2400_dmem +#define HIVE_ADDR_sp_threads_fiber 0x194 +#define HIVE_SIZE_sp_threads_fiber 24 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_threads_fiber scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_threads_fiber 0x194 +#define HIVE_SIZE_sp_sp_threads_fiber 24 + +#ifndef ISP2401 +/* function encode_and_post_sp_event: A79 */ +#else +/* function encode_and_post_sp_event: A0D */ +#endif + +/* function debug_enqueue_ddr: EE */ + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_init_vbuf: 6242 */ +#else +/* function ia_css_rmgr_sp_refcount_init_vbuf: 6408 */ +#endif + +#ifndef ISP2401 +/* function dmaproxy_sp_read_write: 6E86 */ +#else +/* function dmaproxy_sp_read_write: 70C3 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_dmaproxy_isp_dma_cmd_buffer +#define HIVE_MEM_ia_css_dmaproxy_isp_dma_cmd_buffer scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_dmaproxy_isp_dma_cmd_buffer 0x6C90 +#else +#define HIVE_ADDR_ia_css_dmaproxy_isp_dma_cmd_buffer 0x6D3C +#endif +#define HIVE_SIZE_ia_css_dmaproxy_isp_dma_cmd_buffer 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_dmaproxy_isp_dma_cmd_buffer scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 0x6C90 +#else +#define HIVE_ADDR_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 0x6D3C +#endif +#define HIVE_SIZE_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_buffer_queue_handle +#define HIVE_MEM_host2sp_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_buffer_queue_handle 0x5C8C +#else +#define HIVE_ADDR_host2sp_buffer_queue_handle 0x5D38 +#endif +#define HIVE_SIZE_host2sp_buffer_queue_handle 480 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_buffer_queue_handle 0x5C8C +#else +#define HIVE_ADDR_sp_host2sp_buffer_queue_handle 0x5D38 +#endif +#define HIVE_SIZE_sp_host2sp_buffer_queue_handle 480 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_in_service +#define HIVE_MEM_ia_css_flash_sp_in_service scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_in_service 0x3054 +#else +#define HIVE_ADDR_ia_css_flash_sp_in_service 0x3074 +#endif +#define HIVE_SIZE_ia_css_flash_sp_in_service 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_in_service scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_in_service 0x3054 +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_in_service 0x3074 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_in_service 4 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_process: 6B92 */ +#else +/* function ia_css_dmaproxy_sp_process: 6E0F */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_mark_from_end: 3533 */ +#else +/* function ia_css_tagger_buf_sp_mark_from_end: 3656 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_cs: 3F77 */ +#else +/* function ia_css_ispctrl_sp_init_cs: 40FA */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_init: 5E02 */ +#else +/* function ia_css_spctrl_sp_init: 5EE4 */ +#endif + +#ifndef ISP2401 +/* function sp_event_proxy_init: 7A2 */ +#else +/* function sp_event_proxy_init: 736 */ +#endif + +#ifndef ISP2401 +/* function input_system_input_port_close: 109B */ +#else +/* function input_system_input_port_close: 1095 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_previous_clock_tick +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_previous_clock_tick scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x5E6C +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x5F18 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_previous_clock_tick 40 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x5E6C +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x5F18 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 40 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_output +#define HIVE_MEM_sp_output scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_output 0x3F2C +#else +#define HIVE_ADDR_sp_output 0x3F50 +#endif +#define HIVE_SIZE_sp_output 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_output scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_output 0x3F2C +#else +#define HIVE_ADDR_sp_sp_output 0x3F50 +#endif +#define HIVE_SIZE_sp_sp_output 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_sems_for_host2sp_buf_queues +#define HIVE_MEM_ia_css_bufq_sp_sems_for_host2sp_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x5E94 +#else +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x5F40 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_sems_for_host2sp_buf_queues 800 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x5E94 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x5F40 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 800 + +#ifndef ISP2401 +/* function pixelgen_prbs_config: E93 */ +#else +/* function pixelgen_prbs_config: E8D */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_CTRL_BASE +#define HIVE_MEM_ISP_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_CTRL_BASE 0x8 +#define HIVE_SIZE_ISP_CTRL_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_CTRL_BASE 0x8 +#define HIVE_SIZE_sp_ISP_CTRL_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_INPUT_FORMATTER_BASE +#define HIVE_MEM_INPUT_FORMATTER_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_INPUT_FORMATTER_BASE 0x4C +#define HIVE_SIZE_INPUT_FORMATTER_BASE 16 +#else +#endif +#endif +#define HIVE_MEM_sp_INPUT_FORMATTER_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_INPUT_FORMATTER_BASE 0x4C +#define HIVE_SIZE_sp_INPUT_FORMATTER_BASE 16 + +#ifndef ISP2401 +/* function sp_dma_proxy_reset_channels: 3DAB */ +#else +/* function sp_dma_proxy_reset_channels: 3F20 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_update_size: 322A */ +#else +/* function ia_css_tagger_sp_update_size: 334D */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_host_sp_queue +#define HIVE_MEM_ia_css_bufq_host_sp_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_host_sp_queue 0x61B4 +#else +#define HIVE_ADDR_ia_css_bufq_host_sp_queue 0x6260 +#endif +#define HIVE_SIZE_ia_css_bufq_host_sp_queue 2008 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_host_sp_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_host_sp_queue 0x61B4 +#else +#define HIVE_ADDR_sp_ia_css_bufq_host_sp_queue 0x6260 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_host_sp_queue 2008 + +#ifndef ISP2401 +/* function thread_fiber_sp_create: 1444 */ +#else +/* function thread_fiber_sp_create: 13BA */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_increments: 3C3D */ +#else +/* function ia_css_dmaproxy_sp_set_increments: 3DB2 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_writing_cb_frame +#define HIVE_MEM_sem_for_writing_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_writing_cb_frame 0x5830 +#else +#define HIVE_ADDR_sem_for_writing_cb_frame 0x58CC +#endif +#define HIVE_SIZE_sem_for_writing_cb_frame 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_writing_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_writing_cb_frame 0x5830 +#else +#define HIVE_ADDR_sp_sem_for_writing_cb_frame 0x58CC +#endif +#define HIVE_SIZE_sp_sem_for_writing_cb_frame 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_writing_cb_param +#define HIVE_MEM_sem_for_writing_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_writing_cb_param 0x5844 +#else +#define HIVE_ADDR_sem_for_writing_cb_param 0x58E0 +#endif +#define HIVE_SIZE_sem_for_writing_cb_param 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_writing_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_writing_cb_param 0x5844 +#else +#define HIVE_ADDR_sp_sem_for_writing_cb_param 0x58E0 +#endif +#define HIVE_SIZE_sp_sem_for_writing_cb_param 20 + +#ifndef ISP2401 +/* function pixelgen_tpg_is_done: F0D */ +#else +/* function pixelgen_tpg_is_done: F07 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_stream_capture_indication: 5FB6 */ +#else +/* function ia_css_isys_stream_capture_indication: 60D7 */ +#endif + +/* function sp_start_isp_entry: 392 */ +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifdef HIVE_ADDR_sp_start_isp_entry +#endif +#define HIVE_ADDR_sp_start_isp_entry 0x392 +#endif +#define HIVE_ADDR_sp_sp_start_isp_entry 0x392 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_unmark_all: 34B7 */ +#else +/* function ia_css_tagger_buf_sp_unmark_all: 35DA */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_unmark_from_start: 34F8 */ +#else +/* function ia_css_tagger_buf_sp_unmark_from_start: 361B */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_channel_acquire: 3DD7 */ +#else +/* function ia_css_dmaproxy_sp_channel_acquire: 3F4C */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_add_num_vbuf: 648C */ +#else +/* function ia_css_rmgr_sp_add_num_vbuf: 6652 */ +#endif + +#ifndef ISP2401 +/* function ibuf_ctrl_config: D8B */ +#else +/* function ibuf_ctrl_config: D85 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_stream_stop: 602E */ +#else +/* function ia_css_isys_stream_stop: 61F4 */ +#endif + +#ifndef ISP2401 +/* function __ia_css_dmaproxy_sp_wait_for_ack_text: 3AA7 */ +#else +/* function __ia_css_dmaproxy_sp_wait_for_ack_text: 3C07 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_acquire_buf_elem: 291D */ +#else +/* function ia_css_tagger_sp_acquire_buf_elem: 28EE */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_is_dynamic_buffer: 3990 */ +#else +/* function ia_css_bufq_sp_is_dynamic_buffer: 3AB3 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_group +#define HIVE_MEM_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_group 0x3F3C +#define HIVE_SIZE_sp_group 6176 +#else +#define HIVE_ADDR_sp_group 0x3F60 +#define HIVE_SIZE_sp_group 6296 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_group 0x3F3C +#define HIVE_SIZE_sp_sp_group 6176 +#else +#define HIVE_ADDR_sp_sp_group 0x3F60 +#define HIVE_SIZE_sp_sp_group 6296 +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_event_proxy_thread +#define HIVE_MEM_sp_event_proxy_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_event_proxy_thread 0x5A30 +#define HIVE_SIZE_sp_event_proxy_thread 68 +#else +#define HIVE_ADDR_sp_event_proxy_thread 0x5AE0 +#define HIVE_SIZE_sp_event_proxy_thread 72 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_event_proxy_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_event_proxy_thread 0x5A30 +#define HIVE_SIZE_sp_sp_event_proxy_thread 68 +#else +#define HIVE_ADDR_sp_sp_event_proxy_thread 0x5AE0 +#define HIVE_SIZE_sp_sp_event_proxy_thread 72 +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_kill: 1372 */ +#else +/* function ia_css_thread_sp_kill: 12E8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_create: 31E4 */ +#else +/* function ia_css_tagger_sp_create: 32FB */ +#endif + +#ifndef ISP2401 +/* function tmpmem_acquire_dmem: 6539 */ +#else +/* function tmpmem_acquire_dmem: 66FF */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_MMU_BASE +#define HIVE_MEM_MMU_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_MMU_BASE 0x24 +#define HIVE_SIZE_MMU_BASE 8 +#else +#endif +#endif +#define HIVE_MEM_sp_MMU_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_MMU_BASE 0x24 +#define HIVE_SIZE_sp_MMU_BASE 8 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_channel_release: 3DC3 */ +#else +/* function ia_css_dmaproxy_sp_channel_release: 3F38 */ +#endif + +#ifndef ISP2401 +/* function pixelgen_prbs_run: E81 */ +#else +/* function pixelgen_prbs_run: E7B */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_is_idle: 3DA3 */ +#else +/* function ia_css_dmaproxy_sp_is_idle: 3F18 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_qos_start +#define HIVE_MEM_sem_for_qos_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_qos_start 0x5858 +#else +#define HIVE_ADDR_sem_for_qos_start 0x58F4 +#endif +#define HIVE_SIZE_sem_for_qos_start 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_qos_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_qos_start 0x5858 +#else +#define HIVE_ADDR_sp_sem_for_qos_start 0x58F4 +#endif +#define HIVE_SIZE_sp_sem_for_qos_start 20 + +#ifndef ISP2401 +/* function isp_hmem_load: B63 */ +#else +/* function isp_hmem_load: B5D */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_release_buf_elem: 28F9 */ +#else +/* function ia_css_tagger_sp_release_buf_elem: 28CA */ +#endif + +#ifndef ISP2401 +/* function ia_css_eventq_sp_send: 3E19 */ +#else +/* function ia_css_eventq_sp_send: 3F8E */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_unlock_from_start: 33E7 */ +#else +/* function ia_css_tagger_buf_sp_unlock_from_start: 350A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_debug_buffer_ddr_address +#define HIVE_MEM_debug_buffer_ddr_address scalar_processor_2400_dmem +#define HIVE_ADDR_debug_buffer_ddr_address 0xBC +#define HIVE_SIZE_debug_buffer_ddr_address 4 +#else +#endif +#endif +#define HIVE_MEM_sp_debug_buffer_ddr_address scalar_processor_2400_dmem +#define HIVE_ADDR_sp_debug_buffer_ddr_address 0xBC +#define HIVE_SIZE_sp_debug_buffer_ddr_address 4 + +#ifndef ISP2401 +/* function sp_isys_copy_request: 6ED */ +#else +/* function sp_isys_copy_request: 681 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_retain_vbuf: 631C */ +#else +/* function ia_css_rmgr_sp_refcount_retain_vbuf: 64E2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_set_priority: 136A */ +#else +/* function ia_css_thread_sp_set_priority: 12E0 */ +#endif + +#ifndef ISP2401 +/* function sizeof_hmem: C0A */ +#else +/* function sizeof_hmem: C04 */ +#endif + +#ifndef ISP2401 +/* function input_system_channel_open: 1241 */ +#else +/* function input_system_channel_open: 11BC */ +#endif + +#ifndef ISP2401 +/* function pixelgen_tpg_stop: EFB */ +#else +/* function pixelgen_tpg_stop: EF5 */ +#endif + +#ifndef ISP2401 +/* function tmpmem_release_dmem: 6528 */ +#else +/* function tmpmem_release_dmem: 66EE */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_width_exception: 3C28 */ +#else +/* function __ia_css_dmaproxy_sp_process_text: 3BAB */ +#endif + +#ifndef ISP2401 +/* function sp_event_assert: 929 */ +#else +/* function ia_css_dmaproxy_sp_set_width_exception: 3D9D */ +#endif + +#ifndef ISP2401 +/* function ia_css_flash_sp_init_internal_params: 35B4 */ +#else +/* function sp_event_assert: 8BD */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_pop_unmarked_and_unlocked: 32ED */ +#else +/* function ia_css_flash_sp_init_internal_params: 36D7 */ +#endif + +#ifndef ISP2401 +/* function __modu: 687A */ +#else +/* function ia_css_tagger_buf_sp_pop_unmarked_and_unlocked: 3410 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init_isp_vector: 3AAD */ +#else +/* function __modu: 6A78 */ +#endif + +#ifndef ISP2401 +/* function input_system_channel_transfer: 122A */ +#else +/* function ia_css_dmaproxy_sp_init_isp_vector: 3C0D */ + +/* function input_system_channel_transfer: 11A5 */ +#endif + +/* function isp_vamem_store: 0 */ + +#ifdef ISP2401 +/* function ia_css_tagger_sp_set_copy_pipe: 32F2 */ + +#endif +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_GDC_BASE +#define HIVE_MEM_GDC_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_GDC_BASE 0x44 +#define HIVE_SIZE_GDC_BASE 8 +#else +#endif +#endif +#define HIVE_MEM_sp_GDC_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_GDC_BASE 0x44 +#define HIVE_SIZE_sp_GDC_BASE 8 + +#ifndef ISP2401 +/* function ia_css_queue_local_init: 5528 */ +#else +/* function ia_css_queue_local_init: 5707 */ +#endif + +#ifndef ISP2401 +/* function sp_event_proxy_callout_func: 6947 */ +#else +/* function sp_event_proxy_callout_func: 6B45 */ +#endif + +#ifndef ISP2401 +/* function qos_scheduler_schedule_stage: 6580 */ +#else +/* function qos_scheduler_schedule_stage: 6759 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_thread_sp_num_ready_threads +#define HIVE_MEM_ia_css_thread_sp_num_ready_threads scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_thread_sp_num_ready_threads 0x5A78 +#else +#define HIVE_ADDR_ia_css_thread_sp_num_ready_threads 0x5B28 +#endif +#define HIVE_SIZE_ia_css_thread_sp_num_ready_threads 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_thread_sp_num_ready_threads scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_thread_sp_num_ready_threads 0x5A78 +#else +#define HIVE_ADDR_sp_ia_css_thread_sp_num_ready_threads 0x5B28 +#endif +#define HIVE_SIZE_sp_ia_css_thread_sp_num_ready_threads 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_threads_stack_size +#define HIVE_MEM_sp_threads_stack_size scalar_processor_2400_dmem +#define HIVE_ADDR_sp_threads_stack_size 0x17C +#define HIVE_SIZE_sp_threads_stack_size 24 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_threads_stack_size scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_threads_stack_size 0x17C +#define HIVE_SIZE_sp_sp_threads_stack_size 24 + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_isp_done_row_striping: 4849 */ +#else +/* function ia_css_ispctrl_sp_isp_done_row_striping: 4A0D */ +#endif + +#ifndef ISP2401 +/* function __ia_css_virtual_isys_sp_isr_text: 5E45 */ +#else +/* function __ia_css_virtual_isys_sp_isr_text: 5F4E */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_dequeue: 53A6 */ +#else +/* function ia_css_queue_dequeue: 5585 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_configure_channel: 6DEE */ +#else +/* function is_qos_standalone_mode: 6734 */ + +/* function ia_css_dmaproxy_sp_configure_channel: 703C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_current_thread_fiber_sp +#define HIVE_MEM_current_thread_fiber_sp scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_current_thread_fiber_sp 0x5A80 +#else +#define HIVE_ADDR_current_thread_fiber_sp 0x5B2C +#endif +#define HIVE_SIZE_current_thread_fiber_sp 4 +#else +#endif +#endif +#define HIVE_MEM_sp_current_thread_fiber_sp scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_current_thread_fiber_sp 0x5A80 +#else +#define HIVE_ADDR_sp_current_thread_fiber_sp 0x5B2C +#endif +#define HIVE_SIZE_sp_current_thread_fiber_sp 4 + +#ifndef ISP2401 +/* function ia_css_circbuf_pop: 1674 */ +#else +/* function ia_css_circbuf_pop: 15EA */ +#endif + +#ifndef ISP2401 +/* function memset: 68F9 */ +#else +/* function memset: 6AF7 */ +#endif + +/* function irq_raise_set_token: B6 */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_GPIO_BASE +#define HIVE_MEM_GPIO_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_GPIO_BASE 0x3C +#define HIVE_SIZE_GPIO_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_GPIO_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_GPIO_BASE 0x3C +#define HIVE_SIZE_sp_GPIO_BASE 4 + +#ifndef ISP2401 +/* function pixelgen_prbs_stop: E6F */ +#else +/* function pixelgen_prbs_stop: E69 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_acc_stage_enable: 1FC0 */ +#else +/* function ia_css_pipeline_acc_stage_enable: 1F69 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_unlock_exp_id: 296A */ +#else +/* function ia_css_tagger_sp_unlock_exp_id: 293B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_ph +#define HIVE_MEM_isp_ph scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_ph 0x7360 +#else +#define HIVE_ADDR_isp_ph 0x740C +#endif +#define HIVE_SIZE_isp_ph 28 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_ph scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_ph 0x7360 +#else +#define HIVE_ADDR_sp_isp_ph 0x740C +#endif +#define HIVE_SIZE_sp_isp_ph 28 + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_ds: 40D6 */ +#else +/* function ia_css_ispctrl_sp_init_ds: 4286 */ +#endif + +#ifndef ISP2401 +/* function get_xmem_base_addr_raw: 4479 */ +#else +/* function get_xmem_base_addr_raw: 4635 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_param +#define HIVE_MEM_sp_all_cbs_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_param 0x586C +#else +#define HIVE_ADDR_sp_all_cbs_param 0x5908 +#endif +#define HIVE_SIZE_sp_all_cbs_param 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_param 0x586C +#else +#define HIVE_ADDR_sp_sp_all_cbs_param 0x5908 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_param 16 + +#ifndef ISP2401 +/* function pixelgen_tpg_config: F30 */ +#else +/* function pixelgen_tpg_config: F2A */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_create: 16C2 */ +#else +/* function ia_css_circbuf_create: 1638 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_sp_group +#define HIVE_MEM_sem_for_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_sp_group 0x587C +#else +#define HIVE_ADDR_sem_for_sp_group 0x5918 +#endif +#define HIVE_SIZE_sem_for_sp_group 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_sp_group 0x587C +#else +#define HIVE_ADDR_sp_sem_for_sp_group 0x5918 +#endif +#define HIVE_SIZE_sp_sem_for_sp_group 20 + +#ifndef ISP2401 +/* function csi_rx_frontend_run: C22 */ +#else +/* function csi_rx_frontend_run: C1C */ + +/* function __ia_css_dmaproxy_sp_configure_channel_text: 3D7C */ +#endif + +#ifndef ISP2401 +/* function ia_css_framebuf_sp_wait_for_in_frame: 64B7 */ +#else +/* function ia_css_framebuf_sp_wait_for_in_frame: 667D */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_stream_open: 60E3 */ +#else +/* function ia_css_isys_stream_open: 62A9 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_tag_frame: 5C71 */ +#else +/* function ia_css_sp_rawcopy_tag_frame: 5E35 */ +#endif + +#ifndef ISP2401 +/* function input_system_channel_configure: 125D */ +#else +/* function input_system_channel_configure: 11D8 */ +#endif + +#ifndef ISP2401 +/* function isp_hmem_clear: B33 */ +#else +/* function isp_hmem_clear: B2D */ +#endif + +#ifndef ISP2401 +/* function ia_css_framebuf_sp_release_in_frame: 64FA */ +#else +/* function ia_css_framebuf_sp_release_in_frame: 66C0 */ +#endif + +#ifndef ISP2401 +/* function stream2mmio_config: E1B */ +#else +/* function stream2mmio_config: E15 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_start_binary: 3F55 */ +#else +/* function ia_css_ispctrl_sp_start_binary: 40D8 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_h_pipe_private_ddr_ptrs +#define HIVE_MEM_ia_css_bufq_sp_h_pipe_private_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x698C +#else +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x6A38 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x698C +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x6A38 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 20 + +#ifndef ISP2401 +/* function ia_css_eventq_sp_recv: 3DEB */ +#else +/* function ia_css_eventq_sp_recv: 3F60 */ +#endif + +#ifndef ISP2401 +/* function csi_rx_frontend_config: C7A */ +#else +/* function csi_rx_frontend_config: C74 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_pool +#define HIVE_MEM_isp_pool scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_pool 0x370 +#else +#define HIVE_ADDR_isp_pool 0x388 +#endif +#define HIVE_SIZE_isp_pool 4 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_pool scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_pool 0x370 +#else +#define HIVE_ADDR_sp_isp_pool 0x388 +#endif +#define HIVE_SIZE_sp_isp_pool 4 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_rel_gen: 61E9 */ +#else +/* function ia_css_rmgr_sp_rel_gen: 63AF */ + +/* function ia_css_tagger_sp_unblock_clients: 31C3 */ +#endif + +#ifndef ISP2401 +/* function css_get_frame_processing_time_end: 28E9 */ +#else +/* function css_get_frame_processing_time_end: 28BA */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_event_any_pending_mask +#define HIVE_MEM_event_any_pending_mask scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_event_any_pending_mask 0x388 +#else +#define HIVE_ADDR_event_any_pending_mask 0x3A0 +#endif +#define HIVE_SIZE_event_any_pending_mask 8 +#else +#endif +#endif +#define HIVE_MEM_sp_event_any_pending_mask scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_event_any_pending_mask 0x388 +#else +#define HIVE_ADDR_sp_event_any_pending_mask 0x3A0 +#endif +#define HIVE_SIZE_sp_event_any_pending_mask 8 + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_get_pipe_io_status: 1AB8 */ +#else +/* function ia_css_pipeline_sp_get_pipe_io_status: 1A5A */ +#endif + +/* function sh_css_decode_tag_descr: 352 */ + +/* function debug_enqueue_isp: 27B */ + +#ifndef ISP2401 +/* function qos_scheduler_update_stage_budget: 656E */ +#else +/* function qos_scheduler_update_stage_budget: 673C */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_uninit: 5DFB */ +#else +/* function ia_css_spctrl_sp_uninit: 5EDD */ +#endif + +#ifndef ISP2401 +/* function csi_rx_backend_run: C68 */ +#else +/* function csi_rx_backend_run: C62 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_dis_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_dis_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_dis_bufs 0x69A0 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_dis_bufs 0x6A4C +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_dis_bufs 140 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_dis_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_dis_bufs 0x69A0 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_dis_bufs 0x6A4C +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_dis_bufs 140 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_lock_from_start: 341B */ +#else +/* function ia_css_tagger_buf_sp_lock_from_start: 353E */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_isp_idle +#define HIVE_MEM_sem_for_isp_idle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_isp_idle 0x5890 +#else +#define HIVE_ADDR_sem_for_isp_idle 0x592C +#endif +#define HIVE_SIZE_sem_for_isp_idle 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_isp_idle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_isp_idle 0x5890 +#else +#define HIVE_ADDR_sp_sem_for_isp_idle 0x592C +#endif +#define HIVE_SIZE_sp_sem_for_isp_idle 20 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_write_byte_addr: 3B0A */ +#else +/* function ia_css_dmaproxy_sp_write_byte_addr: 3C6A */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init: 3A81 */ +#else +/* function ia_css_dmaproxy_sp_init: 3BE1 */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_release_dynamic_buf_clock_tick: 3686 */ +#else +/* function ia_css_bufq_sp_release_dynamic_buf_clock_tick: 37A9 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_VAMEM_BASE +#define HIVE_MEM_ISP_VAMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_VAMEM_BASE 0x14 +#define HIVE_SIZE_ISP_VAMEM_BASE 12 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_VAMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_VAMEM_BASE 0x14 +#define HIVE_SIZE_sp_ISP_VAMEM_BASE 12 + +#ifndef ISP2401 +/* function input_system_channel_sync: 11A4 */ +#else +/* function input_system_channel_sync: 6C10 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_rawcopy_sp_tagger +#define HIVE_MEM_ia_css_rawcopy_sp_tagger scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_rawcopy_sp_tagger 0x732C +#else +#define HIVE_ADDR_ia_css_rawcopy_sp_tagger 0x73D8 +#endif +#define HIVE_SIZE_ia_css_rawcopy_sp_tagger 24 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_rawcopy_sp_tagger scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_rawcopy_sp_tagger 0x732C +#else +#define HIVE_ADDR_sp_ia_css_rawcopy_sp_tagger 0x73D8 +#endif +#define HIVE_SIZE_sp_ia_css_rawcopy_sp_tagger 24 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_exp_ids +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_exp_ids scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_exp_ids 0x6A2C +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_exp_ids 0x6AD8 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_exp_ids 70 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_exp_ids scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_exp_ids 0x6A2C +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_exp_ids 0x6AD8 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_exp_ids 70 + +#ifndef ISP2401 +/* function ia_css_queue_item_load: 561A */ +#else +/* function ia_css_queue_item_load: 57F9 */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_get_state: 5DE6 */ +#else +/* function ia_css_spctrl_sp_get_state: 5EC8 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_callout_sp_thread +#define HIVE_MEM_callout_sp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_callout_sp_thread 0x5A74 +#else +#define HIVE_ADDR_callout_sp_thread 0x278 +#endif +#define HIVE_SIZE_callout_sp_thread 4 +#else +#endif +#endif +#define HIVE_MEM_sp_callout_sp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_callout_sp_thread 0x5A74 +#else +#define HIVE_ADDR_sp_callout_sp_thread 0x278 +#endif +#define HIVE_SIZE_sp_callout_sp_thread 4 + +#ifndef ISP2401 +/* function thread_fiber_sp_init: 14CB */ +#else +/* function thread_fiber_sp_init: 1441 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_SP_PMEM_BASE +#define HIVE_MEM_SP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_SP_PMEM_BASE 0x0 +#define HIVE_SIZE_SP_PMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_SP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_SP_PMEM_BASE 0x0 +#define HIVE_SIZE_sp_SP_PMEM_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_isp_input_stream_format +#define HIVE_MEM_sp_isp_input_stream_format scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_input_stream_format 0x3E2C +#else +#define HIVE_ADDR_sp_isp_input_stream_format 0x3E50 +#endif +#define HIVE_SIZE_sp_isp_input_stream_format 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_isp_input_stream_format scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_isp_input_stream_format 0x3E2C +#else +#define HIVE_ADDR_sp_sp_isp_input_stream_format 0x3E50 +#endif +#define HIVE_SIZE_sp_sp_isp_input_stream_format 20 + +#ifndef ISP2401 +/* function __mod: 6866 */ +#else +/* function __mod: 6A64 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init_dmem_channel: 3B6B */ +#else +/* function ia_css_dmaproxy_sp_init_dmem_channel: 3CCB */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_join: 139B */ +#else +/* function ia_css_thread_sp_join: 1311 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_add_command: 6EF1 */ +#else +/* function ia_css_dmaproxy_sp_add_command: 712E */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_metadata_thread_func: 5DDF */ +#else +/* function ia_css_sp_metadata_thread_func: 5EC1 */ +#endif + +#ifndef ISP2401 +/* function __sp_event_proxy_func_critical: 6934 */ +#else +/* function __sp_event_proxy_func_critical: 6B32 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_wait_for_isys_stream_N: 5F53 */ +#else +/* function ia_css_pipeline_sp_wait_for_isys_stream_N: 6074 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_metadata_wait: 5DD8 */ +#else +/* function ia_css_sp_metadata_wait: 5EBA */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_peek_from_start: 15A4 */ +#else +/* function ia_css_circbuf_peek_from_start: 151A */ +#endif + +#ifndef ISP2401 +/* function ia_css_event_sp_encode: 3E76 */ +#else +/* function ia_css_event_sp_encode: 3FEB */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_run: 140E */ +#else +/* function ia_css_thread_sp_run: 1384 */ +#endif + +#ifndef ISP2401 +/* function sp_isys_copy_func: 618 */ +#else +/* function sp_isys_copy_func: 5AC */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_isp_param_init_isp_memories: 50A3 */ +#else +/* function ia_css_sp_isp_param_init_isp_memories: 52AC */ +#endif + +#ifndef ISP2401 +/* function register_isr: 921 */ +#else +/* function register_isr: 8B5 */ +#endif + +/* function irq_raise: C8 */ + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_mmu_invalidate: 3A48 */ +#else +/* function ia_css_dmaproxy_sp_mmu_invalidate: 3B71 */ +#endif + +#ifndef ISP2401 +/* function csi_rx_backend_disable: C34 */ +#else +/* function csi_rx_backend_disable: C2E */ +#endif + +#ifndef ISP2401 +/* function pipeline_sp_initialize_stage: 2104 */ +#else +/* function pipeline_sp_initialize_stage: 20BF */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_CSI_RX_FE_CTRL_DLANES +#define HIVE_MEM_N_CSI_RX_FE_CTRL_DLANES scalar_processor_2400_dmem +#define HIVE_ADDR_N_CSI_RX_FE_CTRL_DLANES 0x1C4 +#define HIVE_SIZE_N_CSI_RX_FE_CTRL_DLANES 12 +#else +#endif +#endif +#define HIVE_MEM_sp_N_CSI_RX_FE_CTRL_DLANES scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_CSI_RX_FE_CTRL_DLANES 0x1C4 +#define HIVE_SIZE_sp_N_CSI_RX_FE_CTRL_DLANES 12 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_read_byte_addr_mmio: 6DC0 */ +#else +/* function ia_css_dmaproxy_sp_read_byte_addr_mmio: 700E */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_done_ds: 40BD */ +#else +/* function ia_css_ispctrl_sp_done_ds: 426D */ +#endif + +#ifndef ISP2401 +/* function csi_rx_backend_config: C8B */ +#else +/* function csi_rx_backend_config: C85 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_isp_param_get_mem_inits: 507E */ +#else +/* function ia_css_sp_isp_param_get_mem_inits: 5287 */ +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_init_buffer_queues: 1A85 */ +#else +/* function ia_css_parambuf_sp_init_buffer_queues: 1A27 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_pfp_spref +#define HIVE_MEM_vbuf_pfp_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_pfp_spref 0x378 +#else +#define HIVE_ADDR_vbuf_pfp_spref 0x390 +#endif +#define HIVE_SIZE_vbuf_pfp_spref 4 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_pfp_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_pfp_spref 0x378 +#else +#define HIVE_ADDR_sp_vbuf_pfp_spref 0x390 +#endif +#define HIVE_SIZE_sp_vbuf_pfp_spref 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_HMEM_BASE +#define HIVE_MEM_ISP_HMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_HMEM_BASE 0x20 +#define HIVE_SIZE_ISP_HMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_HMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_HMEM_BASE 0x20 +#define HIVE_SIZE_sp_ISP_HMEM_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_frames +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_frames 0x6A74 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_frames 0x6B20 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_frames 280 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_frames 0x6A74 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_frames 0x6B20 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_frames 280 + +#ifndef ISP2401 +/* function qos_scheduler_init_stage_budget: 65A7 */ +#else +/* function qos_scheduler_init_stage_budget: 679A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp2host_buffer_queue_handle +#define HIVE_MEM_sp2host_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp2host_buffer_queue_handle 0x6B8C +#else +#define HIVE_ADDR_sp2host_buffer_queue_handle 0x6C38 +#endif +#define HIVE_SIZE_sp2host_buffer_queue_handle 96 +#else +#endif +#endif +#define HIVE_MEM_sp_sp2host_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp2host_buffer_queue_handle 0x6B8C +#else +#define HIVE_ADDR_sp_sp2host_buffer_queue_handle 0x6C38 +#endif +#define HIVE_SIZE_sp_sp2host_buffer_queue_handle 96 + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_isp_vars: 4D9D */ +#else +/* function ia_css_ispctrl_sp_init_isp_vars: 4F79 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_stream_start: 6010 */ +#else +/* function ia_css_isys_stream_start: 6187 */ +#endif + +#ifndef ISP2401 +/* function sp_warning: 954 */ +#else +/* function sp_warning: 8E8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_vbuf_enqueue: 62DC */ +#else +/* function ia_css_rmgr_sp_vbuf_enqueue: 64A2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_tag_exp_id: 2A84 */ +#else +/* function ia_css_tagger_sp_tag_exp_id: 2A55 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_sfi_release_current_frame: 276B */ +#else +/* function ia_css_pipeline_sp_sfi_release_current_frame: 273C */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_write: 3B21 */ +#else +/* function ia_css_dmaproxy_sp_write: 3C81 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_stream_start_async: 608A */ +#else +/* function ia_css_isys_stream_start_async: 6250 */ +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_release_in_param: 1905 */ +#else +/* function ia_css_parambuf_sp_release_in_param: 187B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_irq_sw_interrupt_token +#define HIVE_MEM_irq_sw_interrupt_token scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_irq_sw_interrupt_token 0x3E28 +#else +#define HIVE_ADDR_irq_sw_interrupt_token 0x3E4C +#endif +#define HIVE_SIZE_irq_sw_interrupt_token 4 +#else +#endif +#endif +#define HIVE_MEM_sp_irq_sw_interrupt_token scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_irq_sw_interrupt_token 0x3E28 +#else +#define HIVE_ADDR_sp_irq_sw_interrupt_token 0x3E4C +#endif +#define HIVE_SIZE_sp_irq_sw_interrupt_token 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_isp_addresses +#define HIVE_MEM_sp_isp_addresses scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_addresses 0x6FDC +#else +#define HIVE_ADDR_sp_isp_addresses 0x708C +#endif +#define HIVE_SIZE_sp_isp_addresses 172 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_isp_addresses scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_isp_addresses 0x6FDC +#else +#define HIVE_ADDR_sp_sp_isp_addresses 0x708C +#endif +#define HIVE_SIZE_sp_sp_isp_addresses 172 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_acq_gen: 6201 */ +#else +/* function ia_css_rmgr_sp_acq_gen: 63C7 */ +#endif + +#ifndef ISP2401 +/* function input_system_input_port_open: 10ED */ +#else +/* function input_system_input_port_open: 10E7 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isps +#define HIVE_MEM_isps scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isps 0x737C +#else +#define HIVE_ADDR_isps 0x7428 +#endif +#define HIVE_SIZE_isps 28 +#else +#endif +#endif +#define HIVE_MEM_sp_isps scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isps 0x737C +#else +#define HIVE_ADDR_sp_isps 0x7428 +#endif +#define HIVE_SIZE_sp_isps 28 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host_sp_queues_initialized +#define HIVE_MEM_host_sp_queues_initialized scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host_sp_queues_initialized 0x3E40 +#else +#define HIVE_ADDR_host_sp_queues_initialized 0x3E64 +#endif +#define HIVE_SIZE_host_sp_queues_initialized 4 +#else +#endif +#endif +#define HIVE_MEM_sp_host_sp_queues_initialized scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host_sp_queues_initialized 0x3E40 +#else +#define HIVE_ADDR_sp_host_sp_queues_initialized 0x3E64 +#endif +#define HIVE_SIZE_sp_host_sp_queues_initialized 4 + +#ifndef ISP2401 +/* function ia_css_queue_uninit: 54E6 */ +#else +/* function ia_css_queue_uninit: 56C5 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_ispctrl_sp_isp_started +#define HIVE_MEM_ia_css_ispctrl_sp_isp_started scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_ispctrl_sp_isp_started 0x6C94 +#else +#define HIVE_ADDR_ia_css_ispctrl_sp_isp_started 0x6D40 +#endif +#define HIVE_SIZE_ia_css_ispctrl_sp_isp_started 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_ispctrl_sp_isp_started scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_ispctrl_sp_isp_started 0x6C94 +#else +#define HIVE_ADDR_sp_ia_css_ispctrl_sp_isp_started 0x6D40 +#endif +#define HIVE_SIZE_sp_ia_css_ispctrl_sp_isp_started 4 + +#ifndef ISP2401 +/* function ia_css_bufq_sp_release_dynamic_buf: 36F2 */ +#else +/* function ia_css_bufq_sp_release_dynamic_buf: 3815 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_height_exception: 3C19 */ +#else +/* function ia_css_dmaproxy_sp_set_height_exception: 3D8E */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init_vmem_channel: 3B9E */ +#else +/* function ia_css_dmaproxy_sp_init_vmem_channel: 3CFF */ +#endif + +#ifndef ISP2401 +/* function csi_rx_backend_stop: C57 */ +#else +/* function csi_rx_backend_stop: C51 */ +#endif + +#ifndef ISP2401 +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_num_ready_threads +#define HIVE_MEM_num_ready_threads scalar_processor_2400_dmem +#define HIVE_ADDR_num_ready_threads 0x5A7C +#define HIVE_SIZE_num_ready_threads 4 +#else +#endif +#endif +#define HIVE_MEM_sp_num_ready_threads scalar_processor_2400_dmem +#define HIVE_ADDR_sp_num_ready_threads 0x5A7C +#define HIVE_SIZE_sp_num_ready_threads 4 + +/* function ia_css_dmaproxy_sp_write_byte_addr_mmio: 3AF3 */ +#else +/* function ia_css_dmaproxy_sp_write_byte_addr_mmio: 3C53 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_spref +#define HIVE_MEM_vbuf_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_spref 0x374 +#else +#define HIVE_ADDR_vbuf_spref 0x38C +#endif +#define HIVE_SIZE_vbuf_spref 4 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_spref 0x374 +#else +#define HIVE_ADDR_sp_vbuf_spref 0x38C +#endif +#define HIVE_SIZE_sp_vbuf_spref 4 + +#ifndef ISP2401 +/* function ia_css_queue_enqueue: 5430 */ +#else +/* function ia_css_queue_enqueue: 560F */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_request +#define HIVE_MEM_ia_css_flash_sp_request scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_request 0x5B30 +#else +#define HIVE_ADDR_ia_css_flash_sp_request 0x5BDC +#endif +#define HIVE_SIZE_ia_css_flash_sp_request 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_request scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_request 0x5B30 +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_request 0x5BDC +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_request 4 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_vmem_write: 3AC4 */ +#else +/* function ia_css_dmaproxy_sp_vmem_write: 3C24 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_tagger_frames +#define HIVE_MEM_tagger_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_tagger_frames 0x5A84 +#else +#define HIVE_ADDR_tagger_frames 0x5B30 +#endif +#define HIVE_SIZE_tagger_frames 168 +#else +#endif +#endif +#define HIVE_MEM_sp_tagger_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_tagger_frames 0x5A84 +#else +#define HIVE_ADDR_sp_tagger_frames 0x5B30 +#endif +#define HIVE_SIZE_sp_tagger_frames 168 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_reading_if +#define HIVE_MEM_sem_for_reading_if scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_reading_if 0x58A4 +#else +#define HIVE_ADDR_sem_for_reading_if 0x5940 +#endif +#define HIVE_SIZE_sem_for_reading_if 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_reading_if scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_reading_if 0x58A4 +#else +#define HIVE_ADDR_sp_sem_for_reading_if 0x5940 +#endif +#define HIVE_SIZE_sp_sem_for_reading_if 20 + +#ifndef ISP2401 +/* function sp_generate_interrupts: 9D3 */ +#else +/* function sp_generate_interrupts: 967 */ + +/* function ia_css_pipeline_sp_start: 1FC2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_start: 2007 */ +#else +/* function ia_css_thread_default_callout: 6C8F */ +#endif + +#ifndef ISP2401 +/* function csi_rx_backend_enable: C45 */ +#else +/* function csi_rx_backend_enable: C3F */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_init: 5953 */ +#else +/* function ia_css_sp_rawcopy_init: 5B32 */ +#endif + +#ifndef ISP2401 +/* function input_system_input_port_configure: 113F */ +#else +/* function input_system_input_port_configure: 1139 */ +#endif + +#ifndef ISP2401 +/* function tmr_clock_read: 16EF */ +#else +/* function tmr_clock_read: 1665 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_BAMEM_BASE +#define HIVE_MEM_ISP_BAMEM_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ISP_BAMEM_BASE 0x380 +#else +#define HIVE_ADDR_ISP_BAMEM_BASE 0x398 +#endif +#define HIVE_SIZE_ISP_BAMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_BAMEM_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ISP_BAMEM_BASE 0x380 +#else +#define HIVE_ADDR_sp_ISP_BAMEM_BASE 0x398 +#endif +#define HIVE_SIZE_sp_ISP_BAMEM_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_sems_for_sp2host_buf_queues +#define HIVE_MEM_ia_css_bufq_sp_sems_for_sp2host_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x6BEC +#else +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x6C98 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_sems_for_sp2host_buf_queues 160 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x6BEC +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x6C98 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 160 + +#ifndef ISP2401 +/* function isys2401_dma_config_legacy: DE0 */ +#else +/* function isys2401_dma_config_legacy: DDA */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ibuf_ctrl_master_ports +#define HIVE_MEM_ibuf_ctrl_master_ports scalar_processor_2400_dmem +#define HIVE_ADDR_ibuf_ctrl_master_ports 0x208 +#define HIVE_SIZE_ibuf_ctrl_master_ports 12 +#else +#endif +#endif +#define HIVE_MEM_sp_ibuf_ctrl_master_ports scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ibuf_ctrl_master_ports 0x208 +#define HIVE_SIZE_sp_ibuf_ctrl_master_ports 12 + +#ifndef ISP2401 +/* function css_get_frame_processing_time_start: 28F1 */ +#else +/* function css_get_frame_processing_time_start: 28C2 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_frame +#define HIVE_MEM_sp_all_cbs_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_frame 0x58B8 +#else +#define HIVE_ADDR_sp_all_cbs_frame 0x5954 +#endif +#define HIVE_SIZE_sp_all_cbs_frame 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_frame 0x58B8 +#else +#define HIVE_ADDR_sp_sp_all_cbs_frame 0x5954 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_frame 16 + +#ifndef ISP2401 +/* function ia_css_virtual_isys_sp_isr: 6F07 */ +#else +/* function ia_css_virtual_isys_sp_isr: 716E */ +#endif + +#ifndef ISP2401 +/* function thread_sp_queue_print: 142B */ +#else +/* function thread_sp_queue_print: 13A1 */ +#endif + +#ifndef ISP2401 +/* function sp_notify_eof: 97F */ +#else +/* function sp_notify_eof: 913 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_str2mem +#define HIVE_MEM_sem_for_str2mem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_str2mem 0x58C8 +#else +#define HIVE_ADDR_sem_for_str2mem 0x5964 +#endif +#define HIVE_SIZE_sem_for_str2mem 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_str2mem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_str2mem 0x58C8 +#else +#define HIVE_ADDR_sp_sem_for_str2mem 0x5964 +#endif +#define HIVE_SIZE_sp_sem_for_str2mem 20 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_is_marked_from_start: 3483 */ +#else +/* function ia_css_tagger_buf_sp_is_marked_from_start: 35A6 */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_acquire_dynamic_buf: 38AA */ +#else +/* function ia_css_bufq_sp_acquire_dynamic_buf: 39CD */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_sfi_mode_is_enabled: 28BF */ +#else +/* function ia_css_pipeline_sp_sfi_mode_is_enabled: 2890 */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_destroy: 16B9 */ +#else +/* function ia_css_circbuf_destroy: 162F */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_PMEM_BASE +#define HIVE_MEM_ISP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_PMEM_BASE 0xC +#define HIVE_SIZE_ISP_PMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_PMEM_BASE 0xC +#define HIVE_SIZE_sp_ISP_PMEM_BASE 4 + +#ifndef ISP2401 +/* function ia_css_sp_isp_param_mem_load: 5011 */ +#else +/* function ia_css_sp_isp_param_mem_load: 521A */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_pop_from_start: 326F */ +#else +/* function ia_css_tagger_buf_sp_pop_from_start: 3392 */ +#endif + +#ifndef ISP2401 +/* function __div: 681E */ +#else +/* function __div: 6A1C */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_release_vbuf: 62FB */ +#else +/* function ia_css_rmgr_sp_refcount_release_vbuf: 64C1 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_in_use +#define HIVE_MEM_ia_css_flash_sp_in_use scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_in_use 0x5B34 +#else +#define HIVE_ADDR_ia_css_flash_sp_in_use 0x5BE0 +#endif +#define HIVE_SIZE_ia_css_flash_sp_in_use 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_in_use scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_in_use 0x5B34 +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_in_use 0x5BE0 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_in_use 4 + +#ifndef ISP2401 +/* function ia_css_thread_sem_sp_wait: 6AE4 */ +#else +/* function ia_css_thread_sem_sp_wait: 6D63 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_sleep_mode +#define HIVE_MEM_sp_sleep_mode scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sleep_mode 0x3E44 +#else +#define HIVE_ADDR_sp_sleep_mode 0x3E68 +#endif +#define HIVE_SIZE_sp_sleep_mode 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_sleep_mode scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_sleep_mode 0x3E44 +#else +#define HIVE_ADDR_sp_sp_sleep_mode 0x3E68 +#endif +#define HIVE_SIZE_sp_sp_sleep_mode 4 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_push: 337E */ +#else +/* function ia_css_tagger_buf_sp_push: 34A1 */ +#endif + +/* function mmu_invalidate_cache: D3 */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_max_cb_elems +#define HIVE_MEM_sp_max_cb_elems scalar_processor_2400_dmem +#define HIVE_ADDR_sp_max_cb_elems 0x148 +#define HIVE_SIZE_sp_max_cb_elems 8 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_max_cb_elems scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_max_cb_elems 0x148 +#define HIVE_SIZE_sp_sp_max_cb_elems 8 + +#ifndef ISP2401 +/* function ia_css_queue_remote_init: 5508 */ +#else +/* function ia_css_queue_remote_init: 56E7 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_stop_req +#define HIVE_MEM_isp_stop_req scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_stop_req 0x575C +#else +#define HIVE_ADDR_isp_stop_req 0x57F8 +#endif +#define HIVE_SIZE_isp_stop_req 4 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_stop_req scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_stop_req 0x575C +#else +#define HIVE_ADDR_sp_isp_stop_req 0x57F8 +#endif +#define HIVE_SIZE_sp_isp_stop_req 4 + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_sfi_request_next_frame: 2781 */ +#else +/* function ia_css_pipeline_sp_sfi_request_next_frame: 2752 */ +#endif + +#ifndef ISP2401 +#define HIVE_ICACHE_sp_critical_SEGMENT_START 0 +#define HIVE_ICACHE_sp_critical_NUM_SEGMENTS 1 +#endif + +#endif /* _sp_map_h_ */ +#ifndef ISP2401 +extern void sh_css_dump_sp_dmem(void); +void sh_css_dump_sp_dmem(void) +{ +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/system_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/system_global.h new file mode 100644 index 0000000..9f7ecac4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/system_global.h @@ -0,0 +1,458 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SYSTEM_GLOBAL_H_INCLUDED__ +#define __SYSTEM_GLOBAL_H_INCLUDED__ + +#include <hive_isp_css_defs.h> +#include <type_support.h> + +/* + * The longest allowed (uninteruptible) bus transfer, does not + * take stalling into account + */ +#define HIVE_ISP_MAX_BURST_LENGTH 1024 + +/* + * Maximum allowed burst length in words for the ISP DMA + * This value is set to 2 to prevent the ISP DMA from blocking + * the bus for too long; as the input system can only buffer + * 2 lines on Moorefield and Cherrytrail, the input system buffers + * may overflow if blocked for too long (BZ 2726). + */ +#define ISP_DMA_MAX_BURST_LENGTH 2 + +/* + * Create a list of HAS and IS properties that defines the system + * + * The configuration assumes the following + * - The system is hetereogeneous; Multiple cells and devices classes + * - The cell and device instances are homogeneous, each device type + * belongs to the same class + * - Device instances supporting a subset of the class capabilities are + * allowed + * + * We could manage different device classes through the enumerated + * lists (C) or the use of classes (C++), but that is presently not + * fully supported + * + * N.B. the 3 input formatters are of 2 different classess + */ + +#define USE_INPUT_SYSTEM_VERSION_2401 + +#define IS_ISP_2400_SYSTEM +/* + * Since this file is visible everywhere and the system definition + * macros are not, detect the separate definitions for {host, SP, ISP} + * + * The 2401 system has the nice property that it uses a vanilla 2400 SP + * so the SP will believe it is a 2400 system rather than 2401... + */ +/* #if defined(SYSTEM_hive_isp_css_2401_system) || defined(__isp2401_mamoiada) || defined(__scalar_processor_2401) */ +#if defined(SYSTEM_hive_isp_css_2401_system) || defined(__isp2401_mamoiada) +#define IS_ISP_2401_MAMOIADA_SYSTEM +#define HAS_ISP_2401_MAMOIADA +#define HAS_SP_2400 +/* #elif defined(SYSTEM_hive_isp_css_2400_system) || defined(__isp2400_mamoiada) || defined(__scalar_processor_2400)*/ +#elif defined(SYSTEM_hive_isp_css_2400_system) || defined(__isp2400_mamoiada) +#define IS_ISP_2400_MAMOIADA_SYSTEM +#define HAS_ISP_2400_MAMOIADA +#define HAS_SP_2400 +#else +#error "system_global.h: 2400_SYSTEM must be one of {2400, 2401 }" +#endif + +#define HAS_MMU_VERSION_2 +#define HAS_DMA_VERSION_2 +#define HAS_GDC_VERSION_2 +#define HAS_VAMEM_VERSION_2 +#define HAS_HMEM_VERSION_1 +#define HAS_BAMEM_VERSION_2 +#define HAS_IRQ_VERSION_2 +#define HAS_IRQ_MAP_VERSION_2 +#define HAS_INPUT_FORMATTER_VERSION_2 +/* 2401: HAS_INPUT_SYSTEM_VERSION_3 */ +/* 2400: HAS_INPUT_SYSTEM_VERSION_2 */ +#define HAS_INPUT_SYSTEM_VERSION_2 +#define HAS_INPUT_SYSTEM_VERSION_2401 +#define HAS_BUFFERED_SENSOR +#define HAS_FIFO_MONITORS_VERSION_2 +/* #define HAS_GP_REGS_VERSION_2 */ +#define HAS_GP_DEVICE_VERSION_2 +#define HAS_GPIO_VERSION_1 +#define HAS_TIMED_CTRL_VERSION_1 +#define HAS_RX_VERSION_2 +#define HAS_NO_INPUT_FORMATTER +/*#define HAS_NO_PACKED_RAW_PIXELS*/ +/*#define HAS_NO_DVS_6AXIS_CONFIG_UPDATE*/ + +#define DMA_DDR_TO_VAMEM_WORKAROUND +#define DMA_DDR_TO_HMEM_WORKAROUND + + +/* + * Semi global. "HRT" is accessible from SP, but + * the HRT types do not fully apply + */ +#define HRT_VADDRESS_WIDTH 32 +/* Surprise, this is a local property*/ +/*#define HRT_ADDRESS_WIDTH 64 */ +#define HRT_DATA_WIDTH 32 + +#define SIZEOF_HRT_REG (HRT_DATA_WIDTH>>3) +#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH/8) + +/* The main bus connecting all devices */ +#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH +#define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES + +#define CSI2P_DISABLE_ISYS2401_ONLINE_MODE + +/* per-frame parameter handling support */ +#define SH_CSS_ENABLE_PER_FRAME_PARAMS + +typedef uint32_t hrt_bus_align_t; + +/* + * Enumerate the devices, device access through the API is by ID, + * through the DLI by address. The enumerator terminators are used + * to size the wiring arrays and as an exception value. + */ +typedef enum { + DDR0_ID = 0, + N_DDR_ID +} ddr_ID_t; + +typedef enum { + ISP0_ID = 0, + N_ISP_ID +} isp_ID_t; + +typedef enum { + SP0_ID = 0, + N_SP_ID +} sp_ID_t; + +#if defined(IS_ISP_2401_MAMOIADA_SYSTEM) +typedef enum { + MMU0_ID = 0, + MMU1_ID, + N_MMU_ID +} mmu_ID_t; +#elif defined(IS_ISP_2400_MAMOIADA_SYSTEM) +typedef enum { + MMU0_ID = 0, + MMU1_ID, + N_MMU_ID +} mmu_ID_t; +#else +#error "system_global.h: SYSTEM must be one of {2400, 2401}" +#endif + +typedef enum { + DMA0_ID = 0, + N_DMA_ID +} dma_ID_t; + +typedef enum { + GDC0_ID = 0, + GDC1_ID, + N_GDC_ID +} gdc_ID_t; + +/* this extra define is needed because we want to use it also + in the preprocessor, and that doesn't work with enums. + */ +#define N_GDC_ID_CPP 2 + +typedef enum { + VAMEM0_ID = 0, + VAMEM1_ID, + VAMEM2_ID, + N_VAMEM_ID +} vamem_ID_t; + +typedef enum { + BAMEM0_ID = 0, + N_BAMEM_ID +} bamem_ID_t; + +typedef enum { + HMEM0_ID = 0, + N_HMEM_ID +} hmem_ID_t; + +typedef enum { + ISYS_IRQ0_ID = 0, /* port a */ + ISYS_IRQ1_ID, /* port b */ + ISYS_IRQ2_ID, /* port c */ + N_ISYS_IRQ_ID +} isys_irq_ID_t; + +typedef enum { + IRQ0_ID = 0, /* GP IRQ block */ + IRQ1_ID, /* Input formatter */ + IRQ2_ID, /* input system */ + IRQ3_ID, /* input selector */ + N_IRQ_ID +} irq_ID_t; + +typedef enum { + FIFO_MONITOR0_ID = 0, + N_FIFO_MONITOR_ID +} fifo_monitor_ID_t; + +/* + * Deprecated: Since all gp_reg instances are different + * and put in the address maps of other devices we cannot + * enumerate them as that assumes the instrances are the + * same. + * + * We define a single GP_DEVICE containing all gp_regs + * w.r.t. a single base address + * +typedef enum { + GP_REGS0_ID = 0, + N_GP_REGS_ID +} gp_regs_ID_t; + */ +typedef enum { + GP_DEVICE0_ID = 0, + N_GP_DEVICE_ID +} gp_device_ID_t; + +typedef enum { + GP_TIMER0_ID = 0, + GP_TIMER1_ID, + GP_TIMER2_ID, + GP_TIMER3_ID, + GP_TIMER4_ID, + GP_TIMER5_ID, + GP_TIMER6_ID, + GP_TIMER7_ID, + N_GP_TIMER_ID +} gp_timer_ID_t; + +typedef enum { + GPIO0_ID = 0, + N_GPIO_ID +} gpio_ID_t; + +typedef enum { + TIMED_CTRL0_ID = 0, + N_TIMED_CTRL_ID +} timed_ctrl_ID_t; + +typedef enum { + INPUT_FORMATTER0_ID = 0, + INPUT_FORMATTER1_ID, + INPUT_FORMATTER2_ID, + INPUT_FORMATTER3_ID, + N_INPUT_FORMATTER_ID +} input_formatter_ID_t; + +/* The IF RST is outside the IF */ +#define INPUT_FORMATTER0_SRST_OFFSET 0x0824 +#define INPUT_FORMATTER1_SRST_OFFSET 0x0624 +#define INPUT_FORMATTER2_SRST_OFFSET 0x0424 +#define INPUT_FORMATTER3_SRST_OFFSET 0x0224 + +#define INPUT_FORMATTER0_SRST_MASK 0x0001 +#define INPUT_FORMATTER1_SRST_MASK 0x0002 +#define INPUT_FORMATTER2_SRST_MASK 0x0004 +#define INPUT_FORMATTER3_SRST_MASK 0x0008 + +typedef enum { + INPUT_SYSTEM0_ID = 0, + N_INPUT_SYSTEM_ID +} input_system_ID_t; + +typedef enum { + RX0_ID = 0, + N_RX_ID +} rx_ID_t; + +typedef enum { + MIPI_PORT0_ID = 0, + MIPI_PORT1_ID, + MIPI_PORT2_ID, + N_MIPI_PORT_ID +} mipi_port_ID_t; + +#define N_RX_CHANNEL_ID 4 + +/* Generic port enumeration with an internal port type ID */ +typedef enum { + CSI_PORT0_ID = 0, + CSI_PORT1_ID, + CSI_PORT2_ID, + TPG_PORT0_ID, + PRBS_PORT0_ID, + FIFO_PORT0_ID, + MEMORY_PORT0_ID, + N_INPUT_PORT_ID +} input_port_ID_t; + +typedef enum { + CAPTURE_UNIT0_ID = 0, + CAPTURE_UNIT1_ID, + CAPTURE_UNIT2_ID, + ACQUISITION_UNIT0_ID, + DMA_UNIT0_ID, + CTRL_UNIT0_ID, + GPREGS_UNIT0_ID, + FIFO_UNIT0_ID, + IRQ_UNIT0_ID, + N_SUB_SYSTEM_ID +} sub_system_ID_t; + +#define N_CAPTURE_UNIT_ID 3 +#define N_ACQUISITION_UNIT_ID 1 +#define N_CTRL_UNIT_ID 1 + +/* + * Input-buffer Controller. + */ +typedef enum { + IBUF_CTRL0_ID = 0, /* map to ISYS2401_IBUF_CNTRL_A */ + IBUF_CTRL1_ID, /* map to ISYS2401_IBUF_CNTRL_B */ + IBUF_CTRL2_ID, /* map ISYS2401_IBUF_CNTRL_C */ + N_IBUF_CTRL_ID +} ibuf_ctrl_ID_t; +/** end of Input-buffer Controller */ + +/* + * Stream2MMIO. + */ +typedef enum { + STREAM2MMIO0_ID = 0, /* map to ISYS2401_S2M_A */ + STREAM2MMIO1_ID, /* map to ISYS2401_S2M_B */ + STREAM2MMIO2_ID, /* map to ISYS2401_S2M_C */ + N_STREAM2MMIO_ID +} stream2mmio_ID_t; + +typedef enum { + /* + * Stream2MMIO 0 has 8 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID]. + * + * Stream2MMIO 1 has 4 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID]. + * + * Stream2MMIO 2 has 4 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID]. + */ + STREAM2MMIO_SID0_ID = 0, + STREAM2MMIO_SID1_ID, + STREAM2MMIO_SID2_ID, + STREAM2MMIO_SID3_ID, + STREAM2MMIO_SID4_ID, + STREAM2MMIO_SID5_ID, + STREAM2MMIO_SID6_ID, + STREAM2MMIO_SID7_ID, + N_STREAM2MMIO_SID_ID +} stream2mmio_sid_ID_t; +/** end of Stream2MMIO */ + +/** + * Input System 2401: CSI-MIPI recevier. + */ +typedef enum { + CSI_RX_BACKEND0_ID = 0, /* map to ISYS2401_MIPI_BE_A */ + CSI_RX_BACKEND1_ID, /* map to ISYS2401_MIPI_BE_B */ + CSI_RX_BACKEND2_ID, /* map to ISYS2401_MIPI_BE_C */ + N_CSI_RX_BACKEND_ID +} csi_rx_backend_ID_t; + +typedef enum { + CSI_RX_FRONTEND0_ID = 0, /* map to ISYS2401_CSI_RX_A */ + CSI_RX_FRONTEND1_ID, /* map to ISYS2401_CSI_RX_B */ + CSI_RX_FRONTEND2_ID, /* map to ISYS2401_CSI_RX_C */ +#define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID+1) +} csi_rx_frontend_ID_t; + +typedef enum { + CSI_RX_DLANE0_ID = 0, /* map to DLANE0 in CSI RX */ + CSI_RX_DLANE1_ID, /* map to DLANE1 in CSI RX */ + CSI_RX_DLANE2_ID, /* map to DLANE2 in CSI RX */ + CSI_RX_DLANE3_ID, /* map to DLANE3 in CSI RX */ + N_CSI_RX_DLANE_ID +} csi_rx_fe_dlane_ID_t; +/** end of CSI-MIPI receiver */ + +typedef enum { + ISYS2401_DMA0_ID = 0, + N_ISYS2401_DMA_ID +} isys2401_dma_ID_t; + +/** + * Pixel-generator. ("system_global.h") + */ +typedef enum { + PIXELGEN0_ID = 0, + PIXELGEN1_ID, + PIXELGEN2_ID, + N_PIXELGEN_ID +} pixelgen_ID_t; +/** end of pixel-generator. ("system_global.h") */ + +typedef enum { + INPUT_SYSTEM_CSI_PORT0_ID = 0, + INPUT_SYSTEM_CSI_PORT1_ID, + INPUT_SYSTEM_CSI_PORT2_ID, + + INPUT_SYSTEM_PIXELGEN_PORT0_ID, + INPUT_SYSTEM_PIXELGEN_PORT1_ID, + INPUT_SYSTEM_PIXELGEN_PORT2_ID, + + N_INPUT_SYSTEM_INPUT_PORT_ID +} input_system_input_port_ID_t; + +#define N_INPUT_SYSTEM_CSI_PORT 3 + +typedef enum { + ISYS2401_DMA_CHANNEL_0 = 0, + ISYS2401_DMA_CHANNEL_1, + ISYS2401_DMA_CHANNEL_2, + ISYS2401_DMA_CHANNEL_3, + ISYS2401_DMA_CHANNEL_4, + ISYS2401_DMA_CHANNEL_5, + ISYS2401_DMA_CHANNEL_6, + ISYS2401_DMA_CHANNEL_7, + ISYS2401_DMA_CHANNEL_8, + ISYS2401_DMA_CHANNEL_9, + ISYS2401_DMA_CHANNEL_10, + ISYS2401_DMA_CHANNEL_11, + N_ISYS2401_DMA_CHANNEL +} isys2401_dma_channel; + +enum ia_css_isp_memories { + IA_CSS_ISP_PMEM0 = 0, + IA_CSS_ISP_DMEM0, + IA_CSS_ISP_VMEM0, + IA_CSS_ISP_VAMEM0, + IA_CSS_ISP_VAMEM1, + IA_CSS_ISP_VAMEM2, + IA_CSS_ISP_HMEM0, + IA_CSS_SP_DMEM0, + IA_CSS_DDR, + N_IA_CSS_MEMORIES +}; +#define IA_CSS_NUM_MEMORIES 9 +/* For driver compatability */ +#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES +#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES + +#endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */ |
