diff options
Diffstat (limited to 'drivers/staging/media/atomisp/i2c')
51 files changed, 39115 insertions, 0 deletions
diff --git a/drivers/staging/media/atomisp/i2c/Kconfig b/drivers/staging/media/atomisp/i2c/Kconfig new file mode 100644 index 0000000..b80d29d --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/Kconfig @@ -0,0 +1,106 @@ +# +# Kconfig for sensor drivers +# + +source "drivers/staging/media/atomisp/i2c/ov5693/Kconfig" +source "drivers/staging/media/atomisp/i2c/imx/Kconfig" + +config VIDEO_OV2722 + tristate "OVT ov2722 sensor support" + depends on I2C && VIDEO_V4L2 + ---help--- + This is a Video4Linux2 sensor-level driver for the OVT + OV2722 raw camera. + + OVT is a 2M raw sensor. + + It currently only works with the atomisp driver. + +config VIDEO_GC2235 + tristate "Galaxy gc2235 sensor support" + depends on I2C && VIDEO_V4L2 + ---help--- + This is a Video4Linux2 sensor-level driver for the OVT + GC2235 raw camera. + + GC2235 is a 2M raw sensor. + + It currently only works with the atomisp driver. + +config VIDEO_OV8858 + tristate "Omnivision ov8858 sensor support" + depends on I2C && VIDEO_V4L2 && VIDEO_ATOMISP + ---help--- + This is a Video4Linux2 sensor-level driver for the Omnivision + ov8858 RAW sensor. + + OV8858 is a 8M raw sensor. + + It currently only works with the atomisp driver. + +config VIDEO_MSRLIST_HELPER + tristate "Helper library to load, parse and apply large register lists." + depends on I2C + ---help--- + This is a helper library to be used from a sensor driver to load, parse + and apply large register lists. + + To compile this driver as a module, choose M here: the + module will be called libmsrlisthelper. + +config VIDEO_MT9M114 + tristate "Aptina mt9m114 sensor support" + depends on I2C && VIDEO_V4L2 + ---help--- + This is a Video4Linux2 sensor-level driver for the Micron + mt9m114 1.3 Mpixel camera. + + mt9m114 is video camera sensor. + + It currently only works with the atomisp driver. + +config VIDEO_AP1302 + tristate "AP1302 external ISP support" + depends on I2C && VIDEO_V4L2 + select REGMAP_I2C + ---help--- + This is a Video4Linux2 sensor-level driver for the external + ISP AP1302. + + AP1302 is an exteral ISP. + + It currently only works with the atomisp driver. + +config VIDEO_GC0310 + tristate "GC0310 sensor support" + depends on I2C && VIDEO_V4L2 + ---help--- + This is a Video4Linux2 sensor-level driver for the Galaxycore + GC0310 0.3MP sensor. + +config VIDEO_OV2680 + tristate "Omnivision OV2680 sensor support" + depends on I2C && VIDEO_V4L2 + ---help--- + This is a Video4Linux2 sensor-level driver for the Omnivision + OV2680 raw camera. + + ov2680 is a 2M raw sensor. + + It currently only works with the atomisp driver. + +# +# Kconfig for flash drivers +# + +config VIDEO_LM3554 + tristate "LM3554 flash light driver" + depends on VIDEO_V4L2 && I2C + ---help--- + This is a Video4Linux2 sub-dev driver for the LM3554 + flash light driver. + + To compile this driver as a module, choose M here: the + module will be called lm3554 + + diff --git a/drivers/staging/media/atomisp/i2c/Makefile b/drivers/staging/media/atomisp/i2c/Makefile new file mode 100644 index 0000000..8ea0190 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/Makefile @@ -0,0 +1,23 @@ +# +# Makefile for sensor drivers +# + +obj-$(CONFIG_VIDEO_IMX) += imx/ +obj-$(CONFIG_VIDEO_OV5693) += ov5693/ +obj-$(CONFIG_VIDEO_MT9M114) += mt9m114.o +obj-$(CONFIG_VIDEO_GC2235) += gc2235.o +obj-$(CONFIG_VIDEO_OV2722) += ov2722.o +obj-$(CONFIG_VIDEO_OV2680) += ov2680.o +obj-$(CONFIG_VIDEO_GC0310) += gc0310.o + +obj-$(CONFIG_VIDEO_MSRLIST_HELPER) += libmsrlisthelper.o + +obj-$(CONFIG_VIDEO_AP1302) += ap1302.o + +# Makefile for flash drivers +# + +obj-$(CONFIG_VIDEO_LM3554) += lm3554.o + +ccflags-y += -Werror + diff --git a/drivers/staging/media/atomisp/i2c/ap1302.c b/drivers/staging/media/atomisp/i2c/ap1302.c new file mode 100644 index 0000000..bacffbe --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ap1302.c @@ -0,0 +1,1260 @@ +/* + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "../include/linux/atomisp.h" +#include <linux/delay.h> +#include <linux/firmware.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/string.h> +#include <linux/types.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include "ap1302.h" + +#define to_ap1302_device(sub_dev) \ + container_of(sub_dev, struct ap1302_device, sd) + +/* Static definitions */ +static struct regmap_config ap1302_reg16_config = { + .reg_bits = 16, + .val_bits = 16, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_BIG, +}; + +static struct regmap_config ap1302_reg32_config = { + .reg_bits = 16, + .val_bits = 32, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_BIG, +}; + +static enum ap1302_contexts ap1302_cntx_mapping[] = { + CONTEXT_PREVIEW, /* Invalid atomisp run mode */ + CONTEXT_VIDEO, /* ATOMISP_RUN_MODE_VIDEO */ + CONTEXT_SNAPSHOT, /* ATOMISP_RUN_MODE_STILL_CAPTURE */ + CONTEXT_SNAPSHOT, /* ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE */ + CONTEXT_PREVIEW, /* ATOMISP_RUN_MODE_PREVIEW */ +}; + +static struct ap1302_res_struct ap1302_preview_res[] = { + { + .width = 640, + .height = 480, + .fps = 30, + }, + { + .width = 720, + .height = 480, + .fps = 30, + }, + { + .width = 1280, + .height = 720, + .fps = 30, + }, + { + .width = 1920, + .height = 1080, + .fps = 30, + } +}; + +static struct ap1302_res_struct ap1302_snapshot_res[] = { + { + .width = 640, + .height = 480, + .fps = 30, + }, + { + .width = 720, + .height = 480, + .fps = 30, + }, + { + .width = 1280, + .height = 720, + .fps = 30, + }, + { + .width = 1920, + .height = 1080, + .fps = 30, + } +}; + +static struct ap1302_res_struct ap1302_video_res[] = { + { + .width = 640, + .height = 480, + .fps = 30, + }, + { + .width = 720, + .height = 480, + .fps = 30, + }, + { + .width = 1280, + .height = 720, + .fps = 30, + }, + { + .width = 1920, + .height = 1080, + .fps = 30, + } +}; + +static enum ap1302_contexts stream_to_context[] = { + CONTEXT_SNAPSHOT, + CONTEXT_PREVIEW, + CONTEXT_PREVIEW, + CONTEXT_VIDEO +}; + +static u16 aux_stream_config[CONTEXT_NUM][CONTEXT_NUM] = { + {0, 0, 0}, /* Preview: No aux streams. */ + {1, 0, 2}, /* Snapshot: 1 for postview. 2 for video */ + {1, 0, 0}, /* Video: 1 for preview. */ +}; + +static struct ap1302_context_info context_info[] = { + {CNTX_WIDTH, AP1302_REG16, "width"}, + {CNTX_HEIGHT, AP1302_REG16, "height"}, + {CNTX_ROI_X0, AP1302_REG16, "roi_x0"}, + {CNTX_ROI_X1, AP1302_REG16, "roi_x1"}, + {CNTX_ROI_Y0, AP1302_REG16, "roi_y0"}, + {CNTX_ROI_Y1, AP1302_REG16, "roi_y1"}, + {CNTX_ASPECT, AP1302_REG16, "aspect"}, + {CNTX_LOCK, AP1302_REG16, "lock"}, + {CNTX_ENABLE, AP1302_REG16, "enable"}, + {CNTX_OUT_FMT, AP1302_REG16, "out_fmt"}, + {CNTX_SENSOR_MODE, AP1302_REG16, "sensor_mode"}, + {CNTX_MIPI_CTRL, AP1302_REG16, "mipi_ctrl"}, + {CNTX_MIPI_II_CTRL, AP1302_REG16, "mipi_ii_ctrl"}, + {CNTX_LINE_TIME, AP1302_REG32, "line_time"}, + {CNTX_MAX_FPS, AP1302_REG16, "max_fps"}, + {CNTX_AE_USG, AP1302_REG16, "ae_usg"}, + {CNTX_AE_UPPER_ET, AP1302_REG32, "ae_upper_et"}, + {CNTX_AE_MAX_ET, AP1302_REG32, "ae_max_et"}, + {CNTX_SS, AP1302_REG16, "ss"}, + {CNTX_S1_SENSOR_MODE, AP1302_REG16, "s1_sensor_mode"}, + {CNTX_HINF_CTRL, AP1302_REG16, "hinf_ctrl"}, +}; + +/* This array stores the description list for metadata. + The metadata contains exposure settings and face + detection results. */ +static u16 ap1302_ss_list[] = { + 0xb01c, /* From 0x0186 with size 0x1C are exposure settings. */ + 0x0186, + 0xb002, /* 0x71c0 is for F-number */ + 0x71c0, + 0xb010, /* From 0x03dc with size 0x10 are face general infos. */ + 0x03dc, + 0xb0a0, /* From 0x03e4 with size 0xa0 are face detail infos. */ + 0x03e4, + 0xb020, /* From 0x0604 with size 0x20 are smile rate infos. */ + 0x0604, + 0x0000 +}; + +/* End of static definitions */ + +static int ap1302_i2c_read_reg(struct v4l2_subdev *sd, + u16 reg, u16 len, void *val) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (len == AP1302_REG16) + ret = regmap_read(dev->regmap16, reg, val); + else if (len == AP1302_REG32) + ret = regmap_read(dev->regmap32, reg, val); + else + ret = -EINVAL; + if (ret) { + dev_dbg(&client->dev, "Read reg failed. reg=0x%04X\n", reg); + return ret; + } + if (len == AP1302_REG16) + dev_dbg(&client->dev, "read_reg[0x%04X] = 0x%04X\n", + reg, *(u16 *)val); + else + dev_dbg(&client->dev, "read_reg[0x%04X] = 0x%08X\n", + reg, *(u32 *)val); + return ret; +} + +static int ap1302_i2c_write_reg(struct v4l2_subdev *sd, + u16 reg, u16 len, u32 val) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + if (len == AP1302_REG16) + ret = regmap_write(dev->regmap16, reg, val); + else if (len == AP1302_REG32) + ret = regmap_write(dev->regmap32, reg, val); + else + ret = -EINVAL; + if (ret) { + dev_dbg(&client->dev, "Write reg failed. reg=0x%04X\n", reg); + return ret; + } + if (len == AP1302_REG16) + dev_dbg(&client->dev, "write_reg[0x%04X] = 0x%04X\n", + reg, (u16)val); + else + dev_dbg(&client->dev, "write_reg[0x%04X] = 0x%08X\n", + reg, (u32)val); + return ret; +} + +static u16 +ap1302_calculate_context_reg_addr(enum ap1302_contexts context, u16 offset) +{ + u16 reg_addr; + /* The register offset is defined according to preview/video registers. + Preview and video context have the same register definition. + But snapshot context does not have register S1_SENSOR_MODE. + When setting snapshot registers, if the offset exceeds + S1_SENSOR_MODE, the actual offset needs to minus 2. */ + if (context == CONTEXT_SNAPSHOT) { + if (offset == CNTX_S1_SENSOR_MODE) + return 0; + if (offset > CNTX_S1_SENSOR_MODE) + offset -= 2; + } + if (context == CONTEXT_PREVIEW) + reg_addr = REG_PREVIEW_BASE + offset; + else if (context == CONTEXT_VIDEO) + reg_addr = REG_VIDEO_BASE + offset; + else + reg_addr = REG_SNAPSHOT_BASE + offset; + return reg_addr; +} + +static int ap1302_read_context_reg(struct v4l2_subdev *sd, + enum ap1302_contexts context, u16 offset, u16 len) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + u16 reg_addr = ap1302_calculate_context_reg_addr(context, offset); + if (reg_addr == 0) + return -EINVAL; + return ap1302_i2c_read_reg(sd, reg_addr, len, + ((u8 *)&dev->cntx_config[context]) + offset); +} + +static int ap1302_write_context_reg(struct v4l2_subdev *sd, + enum ap1302_contexts context, u16 offset, u16 len) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + u16 reg_addr = ap1302_calculate_context_reg_addr(context, offset); + if (reg_addr == 0) + return -EINVAL; + return ap1302_i2c_write_reg(sd, reg_addr, len, + *(u32 *)(((u8 *)&dev->cntx_config[context]) + offset)); +} + +static int ap1302_dump_context_reg(struct v4l2_subdev *sd, + enum ap1302_contexts context) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ap1302_device *dev = to_ap1302_device(sd); + int i; + dev_dbg(&client->dev, "Dump registers for context[%d]:\n", context); + for (i = 0; i < ARRAY_SIZE(context_info); i++) { + struct ap1302_context_info *info = &context_info[i]; + u8 *var = (u8 *)&dev->cntx_config[context] + info->offset; + /* Snapshot context does not have s1_sensor_mode register. */ + if (context == CONTEXT_SNAPSHOT && + info->offset == CNTX_S1_SENSOR_MODE) + continue; + ap1302_read_context_reg(sd, context, info->offset, info->len); + if (info->len == AP1302_REG16) + dev_dbg(&client->dev, "context.%s = 0x%04X (%d)\n", + info->name, *(u16 *)var, *(u16 *)var); + else + dev_dbg(&client->dev, "context.%s = 0x%08X (%d)\n", + info->name, *(u32 *)var, *(u32 *)var); + } + return 0; +} + +static int ap1302_request_firmware(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ap1302_device *dev = to_ap1302_device(sd); + int ret; + ret = request_firmware(&dev->fw, "ap1302_fw.bin", &client->dev); + if (ret) + dev_err(&client->dev, + "ap1302_request_firmware failed. ret=%d\n", ret); + return ret; +} + +/* When loading firmware, host writes firmware data from address 0x8000. + When the address reaches 0x9FFF, the next address should return to 0x8000. + This function handles this address window and load firmware data to AP1302. + win_pos indicates the offset within this window. Firmware loading procedure + may call this function several times. win_pos records the current position + that has been written to.*/ +static int ap1302_write_fw_window(struct v4l2_subdev *sd, + u16 *win_pos, const u8 *buf, u32 len) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + int ret; + u32 pos; + u32 sub_len; + for (pos = 0; pos < len; pos += sub_len) { + if (len - pos < AP1302_FW_WINDOW_SIZE - *win_pos) + sub_len = len - pos; + else + sub_len = AP1302_FW_WINDOW_SIZE - *win_pos; + ret = regmap_raw_write(dev->regmap16, + *win_pos + AP1302_FW_WINDOW_OFFSET, + buf + pos, sub_len); + if (ret) + return ret; + *win_pos += sub_len; + if (*win_pos >= AP1302_FW_WINDOW_SIZE) + *win_pos = 0; + } + return 0; +} + +static int ap1302_load_firmware(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ap1302_device *dev = to_ap1302_device(sd); + const struct ap1302_firmware *fw; + const u8 *fw_data; + u16 reg_val = 0; + u16 win_pos = 0; + int ret; + + dev_info(&client->dev, "Start to load firmware.\n"); + if (!dev->fw) { + dev_err(&client->dev, "firmware not requested.\n"); + return -EINVAL; + } + fw = (const struct ap1302_firmware *) dev->fw->data; + if (dev->fw->size != (sizeof(*fw) + fw->total_size)) { + dev_err(&client->dev, "firmware size does not match.\n"); + return -EINVAL; + } + /* The fw binary contains a header of struct ap1302_firmware. + Following the header is the bootdata of AP1302. + The bootdata pointer can be referenced as &fw[1]. */ + fw_data = (u8 *)&fw[1]; + + /* Clear crc register. */ + ret = ap1302_i2c_write_reg(sd, REG_SIP_CRC, AP1302_REG16, 0xFFFF); + if (ret) + return ret; + + /* Load FW data for PLL init stage. */ + ret = ap1302_write_fw_window(sd, &win_pos, fw_data, fw->pll_init_size); + if (ret) + return ret; + + /* Write 2 to bootdata_stage register to apply basic_init_hp + settings and enable PLL. */ + ret = ap1302_i2c_write_reg(sd, REG_BOOTDATA_STAGE, + AP1302_REG16, 0x0002); + if (ret) + return ret; + + /* Wait 1ms for PLL to lock. */ + msleep(20); + + /* Load the rest of bootdata content. */ + ret = ap1302_write_fw_window(sd, &win_pos, fw_data + fw->pll_init_size, + fw->total_size - fw->pll_init_size); + if (ret) + return ret; + + /* Check crc. */ + ret = ap1302_i2c_read_reg(sd, REG_SIP_CRC, AP1302_REG16, ®_val); + if (ret) + return ret; + if (reg_val != fw->crc) { + dev_err(&client->dev, + "crc does not match. T:0x%04X F:0x%04X\n", + fw->crc, reg_val); + return -EAGAIN; + } + + /* Write 0xFFFF to bootdata_stage register to indicate AP1302 that + the whole bootdata content has been loaded. */ + ret = ap1302_i2c_write_reg(sd, REG_BOOTDATA_STAGE, + AP1302_REG16, 0xFFFF); + if (ret) + return ret; + dev_info(&client->dev, "Load firmware successfully.\n"); + + return 0; +} + +static int __ap1302_s_power(struct v4l2_subdev *sd, int on, int load_fw) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret, i; + u16 ss_ptr; + + dev_info(&client->dev, "ap1302_s_power is called.\n"); + ret = dev->platform_data->power_ctrl(sd, on); + if (ret) { + dev_err(&client->dev, + "ap1302_s_power error. on=%d ret=%d\n", on, ret); + return ret; + } + dev->power_on = on; + if (!on || !load_fw) + return 0; + /* Load firmware after power on. */ + ret = ap1302_load_firmware(sd); + if (ret) { + dev_err(&client->dev, + "ap1302_load_firmware failed. ret=%d\n", ret); + return ret; + } + ret = ap1302_i2c_read_reg(sd, REG_SS_HEAD_PT0, AP1302_REG16, &ss_ptr); + if (ret) + return ret; + for (i = 0; i < ARRAY_SIZE(ap1302_ss_list); i++) { + ret = ap1302_i2c_write_reg(sd, ss_ptr + i * 2, + AP1302_REG16, ap1302_ss_list[i]); + if (ret) + return ret; + } + return ret; +} + +static int ap1302_s_power(struct v4l2_subdev *sd, int on) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ap1302_s_power(sd, on, 1); + dev->sys_activated = 0; + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int ap1302_s_config(struct v4l2_subdev *sd, void *pdata) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *mipi_info; + u16 reg_val = 0; + int ret; + + dev_info(&client->dev, "ap1302_s_config is called.\n"); + if (pdata == NULL) + return -ENODEV; + + dev->platform_data = pdata; + + mutex_lock(&dev->input_lock); + + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) + goto fail_power; + } + + ret = __ap1302_s_power(sd, 1, 0); + if (ret) + goto fail_power; + + /* Detect for AP1302 */ + ret = ap1302_i2c_read_reg(sd, REG_CHIP_VERSION, AP1302_REG16, ®_val); + if (ret || (reg_val != AP1302_CHIP_ID)) { + dev_err(&client->dev, + "Chip version does no match. ret=%d ver=0x%04x\n", + ret, reg_val); + goto fail_config; + } + dev_info(&client->dev, "AP1302 Chip ID is 0x%X\n", reg_val); + + /* Detect revision for AP1302 */ + ret = ap1302_i2c_read_reg(sd, REG_CHIP_REV, AP1302_REG16, ®_val); + if (ret) + goto fail_config; + dev_info(&client->dev, "AP1302 Chip Rev is 0x%X\n", reg_val); + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_config; + + mipi_info = v4l2_get_subdev_hostdata(sd); + if (!mipi_info) + goto fail_config; + dev->num_lanes = mipi_info->num_lanes; + + ret = __ap1302_s_power(sd, 0, 0); + if (ret) + goto fail_power; + + mutex_unlock(&dev->input_lock); + + return ret; + +fail_config: + __ap1302_s_power(sd, 0, 0); +fail_power: + mutex_unlock(&dev->input_lock); + dev_err(&client->dev, "ap1302_s_config failed\n"); + return ret; +} + +static enum ap1302_contexts ap1302_get_context(struct v4l2_subdev *sd) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + return dev->cur_context; +} + +static int ap1302_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_UYVY8_1X16; + + return 0; +} + +static int ap1302_match_resolution(struct ap1302_context_res *res, + struct v4l2_mbus_framefmt *fmt) +{ + s32 w0, h0, mismatch, distance; + s32 w1 = fmt->width; + s32 h1 = fmt->height; + s32 min_distance = INT_MAX; + s32 i, idx = -1; + + if (w1 == 0 || h1 == 0) + return -1; + + for (i = 0; i < res->res_num; i++) { + w0 = res->res_table[i].width; + h0 = res->res_table[i].height; + if (w0 < w1 || h0 < h1) + continue; + mismatch = abs(w0 * h1 - w1 * h0) * 8192 / w1 / h0; + if (mismatch > 8192 * AP1302_MAX_RATIO_MISMATCH / 100) + continue; + distance = (w0 * h1 + w1 * h0) * 8192 / w1 / h1; + if (distance < min_distance) { + min_distance = distance; + idx = i; + } + } + + return idx; +} + +static s32 ap1302_try_mbus_fmt_locked(struct v4l2_subdev *sd, + enum ap1302_contexts context, + struct v4l2_mbus_framefmt *fmt) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + struct ap1302_res_struct *res_table; + s32 res_num, idx = -1; + + res_table = dev->cntx_res[context].res_table; + res_num = dev->cntx_res[context].res_num; + + if ((fmt->width <= res_table[res_num - 1].width) && + (fmt->height <= res_table[res_num - 1].height)) + idx = ap1302_match_resolution(&dev->cntx_res[context], fmt); + if (idx == -1) + idx = res_num - 1; + + fmt->width = res_table[idx].width; + fmt->height = res_table[idx].height; + fmt->code = MEDIA_BUS_FMT_UYVY8_1X16; + return idx; +} + + +static int ap1302_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) + +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ap1302_device *dev = to_ap1302_device(sd); + enum ap1302_contexts context; + struct ap1302_res_struct *res_table; + s32 cur_res; + if (format->pad) + return -EINVAL; + mutex_lock(&dev->input_lock); + context = ap1302_get_context(sd); + res_table = dev->cntx_res[context].res_table; + cur_res = dev->cntx_res[context].cur_res; + fmt->code = MEDIA_BUS_FMT_UYVY8_1X16; + fmt->width = res_table[cur_res].width; + fmt->height = res_table[cur_res].height; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int ap1302_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ap1302_device *dev = to_ap1302_device(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct atomisp_input_stream_info *stream_info = + (struct atomisp_input_stream_info *)fmt->reserved; + enum ap1302_contexts context, main_context; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + mutex_lock(&dev->input_lock); + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + context = ap1302_get_context(sd); + ap1302_try_mbus_fmt_locked(sd, context, fmt); + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + context = stream_to_context[stream_info->stream]; + dev_dbg(&client->dev, "ap1302_set_mbus_fmt. stream=%d context=%d\n", + stream_info->stream, context); + dev->cntx_res[context].cur_res = + ap1302_try_mbus_fmt_locked(sd, context, fmt); + dev->cntx_config[context].width = fmt->width; + dev->cntx_config[context].height = fmt->height; + ap1302_write_context_reg(sd, context, CNTX_WIDTH, AP1302_REG16); + ap1302_write_context_reg(sd, context, CNTX_HEIGHT, AP1302_REG16); + ap1302_read_context_reg(sd, context, CNTX_OUT_FMT, AP1302_REG16); + dev->cntx_config[context].out_fmt &= ~OUT_FMT_TYPE_MASK; + dev->cntx_config[context].out_fmt |= AP1302_FMT_UYVY422; + ap1302_write_context_reg(sd, context, CNTX_OUT_FMT, AP1302_REG16); + + main_context = ap1302_get_context(sd); + if (context == main_context) { + ap1302_read_context_reg(sd, context, + CNTX_MIPI_CTRL, AP1302_REG16); + dev->cntx_config[context].mipi_ctrl &= ~MIPI_CTRL_IMGVC_MASK; + dev->cntx_config[context].mipi_ctrl |= + (context << MIPI_CTRL_IMGVC_OFFSET); + dev->cntx_config[context].mipi_ctrl &= ~MIPI_CTRL_SSVC_MASK; + dev->cntx_config[context].mipi_ctrl |= + (context << MIPI_CTRL_SSVC_OFFSET); + dev->cntx_config[context].mipi_ctrl &= ~MIPI_CTRL_SSTYPE_MASK; + dev->cntx_config[context].mipi_ctrl |= + (0x12 << MIPI_CTRL_SSTYPE_OFFSET); + ap1302_write_context_reg(sd, context, + CNTX_MIPI_CTRL, AP1302_REG16); + ap1302_read_context_reg(sd, context, + CNTX_SS, AP1302_REG16); + dev->cntx_config[context].ss = AP1302_SS_CTRL; + ap1302_write_context_reg(sd, context, + CNTX_SS, AP1302_REG16); + } else { + /* Configure aux stream */ + ap1302_read_context_reg(sd, context, + CNTX_MIPI_II_CTRL, AP1302_REG16); + dev->cntx_config[context].mipi_ii_ctrl &= ~MIPI_CTRL_IMGVC_MASK; + dev->cntx_config[context].mipi_ii_ctrl |= + (context << MIPI_CTRL_IMGVC_OFFSET); + ap1302_write_context_reg(sd, context, + CNTX_MIPI_II_CTRL, AP1302_REG16); + if (stream_info->enable) { + ap1302_read_context_reg(sd, main_context, + CNTX_OUT_FMT, AP1302_REG16); + dev->cntx_config[context].out_fmt |= + (aux_stream_config[main_context][context] + << OUT_FMT_IIS_OFFSET); + ap1302_write_context_reg(sd, main_context, + CNTX_OUT_FMT, AP1302_REG16); + } + } + stream_info->ch_id = context; + mutex_unlock(&dev->input_lock); + + return 0; +} + + +static int ap1302_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + enum ap1302_contexts context; + struct ap1302_res_struct *res_table; + u32 cur_res; + + mutex_lock(&dev->input_lock); + context = ap1302_get_context(sd); + res_table = dev->cntx_res[context].res_table; + cur_res = dev->cntx_res[context].cur_res; + interval->interval.denominator = res_table[cur_res].fps; + interval->interval.numerator = 1; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int ap1302_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + enum ap1302_contexts context; + struct ap1302_res_struct *res_table; + int index = fse->index; + + mutex_lock(&dev->input_lock); + context = ap1302_get_context(sd); + if (index >= dev->cntx_res[context].res_num) { + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + res_table = dev->cntx_res[context].res_table; + fse->min_width = res_table[index].width; + fse->min_height = res_table[index].height; + fse->max_width = res_table[index].width; + fse->max_height = res_table[index].height; + mutex_unlock(&dev->input_lock); + + return 0; +} + + +static int ap1302_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + *frames = 0; + return 0; +} + +static int ap1302_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + enum ap1302_contexts context; + u32 reg_val; + int ret; + + mutex_lock(&dev->input_lock); + context = ap1302_get_context(sd); + dev_dbg(&client->dev, "ap1302_s_stream. context=%d enable=%d\n", + context, enable); + /* Switch context */ + ap1302_i2c_read_reg(sd, REG_CTRL, + AP1302_REG16, ®_val); + reg_val &= ~CTRL_CNTX_MASK; + reg_val |= (context<<CTRL_CNTX_OFFSET); + ap1302_i2c_write_reg(sd, REG_CTRL, + AP1302_REG16, reg_val); + /* Select sensor */ + ap1302_i2c_read_reg(sd, REG_SENSOR_SELECT, + AP1302_REG16, ®_val); + reg_val &= ~SENSOR_SELECT_MASK; + reg_val |= (AP1302_SENSOR_PRI<<SENSOR_SELECT_OFFSET); + ap1302_i2c_write_reg(sd, REG_SENSOR_SELECT, + AP1302_REG16, reg_val); + if (enable) { + dev_info(&client->dev, "Start stream. context=%d\n", context); + ap1302_dump_context_reg(sd, context); + if (!dev->sys_activated) { + reg_val = AP1302_SYS_ACTIVATE; + dev->sys_activated = 1; + } else { + reg_val = AP1302_SYS_SWITCH; + } + } else { + dev_info(&client->dev, "Stop stream. context=%d\n", context); + reg_val = AP1302_SYS_SWITCH; + } + ret = ap1302_i2c_write_reg(sd, REG_SYS_START, AP1302_REG16, reg_val); + if (ret) + dev_err(&client->dev, + "AP1302 set stream failed. enable=%d\n", enable); + mutex_unlock(&dev->input_lock); + return ret; +} + +static u16 ap1302_ev_values[] = {0xfd00, 0xfe80, 0x0, 0x180, 0x300}; + +static int ap1302_set_exposure_off(struct v4l2_subdev *sd, s32 val) +{ + val -= AP1302_MIN_EV; + return ap1302_i2c_write_reg(sd, REG_AE_BV_OFF, AP1302_REG16, + ap1302_ev_values[val]); +} + +static u16 ap1302_wb_values[] = { + 0, /* V4L2_WHITE_BALANCE_MANUAL */ + 0xf, /* V4L2_WHITE_BALANCE_AUTO */ + 0x2, /* V4L2_WHITE_BALANCE_INCANDESCENT */ + 0x4, /* V4L2_WHITE_BALANCE_FLUORESCENT */ + 0x5, /* V4L2_WHITE_BALANCE_FLUORESCENT_H */ + 0x1, /* V4L2_WHITE_BALANCE_HORIZON */ + 0x5, /* V4L2_WHITE_BALANCE_DAYLIGHT */ + 0xf, /* V4L2_WHITE_BALANCE_FLASH */ + 0x6, /* V4L2_WHITE_BALANCE_CLOUDY */ + 0x6, /* V4L2_WHITE_BALANCE_SHADE */ +}; + +static int ap1302_set_wb_mode(struct v4l2_subdev *sd, s32 val) +{ + int ret = 0; + u16 reg_val; + + ret = ap1302_i2c_read_reg(sd, REG_AWB_CTRL, AP1302_REG16, ®_val); + if (ret) + return ret; + reg_val &= ~AWB_CTRL_MODE_MASK; + reg_val |= ap1302_wb_values[val] << AWB_CTRL_MODE_OFFSET; + if (val == V4L2_WHITE_BALANCE_FLASH) + reg_val |= AWB_CTRL_FLASH_MASK; + else + reg_val &= ~AWB_CTRL_FLASH_MASK; + ret = ap1302_i2c_write_reg(sd, REG_AWB_CTRL, AP1302_REG16, reg_val); + return ret; +} + +static int ap1302_set_zoom(struct v4l2_subdev *sd, s32 val) +{ + ap1302_i2c_write_reg(sd, REG_DZ_TGT_FCT, AP1302_REG16, + val * 4 + 0x100); + return 0; +} + +static u16 ap1302_sfx_values[] = { + 0x00, /* V4L2_COLORFX_NONE */ + 0x03, /* V4L2_COLORFX_BW */ + 0x0d, /* V4L2_COLORFX_SEPIA */ + 0x07, /* V4L2_COLORFX_NEGATIVE */ + 0x04, /* V4L2_COLORFX_EMBOSS */ + 0x0f, /* V4L2_COLORFX_SKETCH */ + 0x08, /* V4L2_COLORFX_SKY_BLUE */ + 0x09, /* V4L2_COLORFX_GRASS_GREEN */ + 0x0a, /* V4L2_COLORFX_SKIN_WHITEN */ + 0x00, /* V4L2_COLORFX_VIVID */ + 0x00, /* V4L2_COLORFX_AQUA */ + 0x00, /* V4L2_COLORFX_ART_FREEZE */ + 0x00, /* V4L2_COLORFX_SILHOUETTE */ + 0x10, /* V4L2_COLORFX_SOLARIZATION */ + 0x02, /* V4L2_COLORFX_ANTIQUE */ + 0x00, /* V4L2_COLORFX_SET_CBCR */ +}; + +static int ap1302_set_special_effect(struct v4l2_subdev *sd, s32 val) +{ + ap1302_i2c_write_reg(sd, REG_SFX_MODE, AP1302_REG16, + ap1302_sfx_values[val]); + return 0; +} + +static u16 ap1302_scene_mode_values[] = { + 0x00, /* V4L2_SCENE_MODE_NONE */ + 0x07, /* V4L2_SCENE_MODE_BACKLIGHT */ + 0x0a, /* V4L2_SCENE_MODE_BEACH_SNOW */ + 0x06, /* V4L2_SCENE_MODE_CANDLE_LIGHT */ + 0x00, /* V4L2_SCENE_MODE_DAWN_DUSK */ + 0x00, /* V4L2_SCENE_MODE_FALL_COLORS */ + 0x0d, /* V4L2_SCENE_MODE_FIREWORKS */ + 0x02, /* V4L2_SCENE_MODE_LANDSCAPE */ + 0x05, /* V4L2_SCENE_MODE_NIGHT */ + 0x0c, /* V4L2_SCENE_MODE_PARTY_INDOOR */ + 0x01, /* V4L2_SCENE_MODE_PORTRAIT */ + 0x03, /* V4L2_SCENE_MODE_SPORTS */ + 0x0e, /* V4L2_SCENE_MODE_SUNSET */ + 0x0b, /* V4L2_SCENE_MODE_TEXT */ +}; + +static int ap1302_set_scene_mode(struct v4l2_subdev *sd, s32 val) +{ + ap1302_i2c_write_reg(sd, REG_SCENE_CTRL, AP1302_REG16, + ap1302_scene_mode_values[val]); + return 0; +} + +static u16 ap1302_flicker_values[] = { + 0x0, /* OFF */ + 0x3201, /* 50HZ */ + 0x3c01, /* 60HZ */ + 0x2 /* AUTO */ +}; + +static int ap1302_set_flicker_freq(struct v4l2_subdev *sd, s32 val) +{ + ap1302_i2c_write_reg(sd, REG_FLICK_CTRL, AP1302_REG16, + ap1302_flicker_values[val]); + return 0; +} + +static int ap1302_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ap1302_device *dev = container_of( + ctrl->handler, struct ap1302_device, ctrl_handler); + + switch (ctrl->id) { + case V4L2_CID_RUN_MODE: + dev->cur_context = ap1302_cntx_mapping[ctrl->val]; + break; + case V4L2_CID_EXPOSURE: + ap1302_set_exposure_off(&dev->sd, ctrl->val); + break; + case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE: + ap1302_set_wb_mode(&dev->sd, ctrl->val); + break; + case V4L2_CID_ZOOM_ABSOLUTE: + ap1302_set_zoom(&dev->sd, ctrl->val); + break; + case V4L2_CID_COLORFX: + ap1302_set_special_effect(&dev->sd, ctrl->val); + break; + case V4L2_CID_SCENE_MODE: + ap1302_set_scene_mode(&dev->sd, ctrl->val); + break; + case V4L2_CID_POWER_LINE_FREQUENCY: + ap1302_set_flicker_freq(&dev->sd, ctrl->val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int ap1302_g_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + int ret; + u32 reg_val; + + if (reg->size != AP1302_REG16 && + reg->size != AP1302_REG32) + return -EINVAL; + + mutex_lock(&dev->input_lock); + if (dev->power_on) + ret = ap1302_i2c_read_reg(sd, reg->reg, reg->size, ®_val); + else + ret = -EIO; + mutex_unlock(&dev->input_lock); + if (ret) + return ret; + + reg->val = reg_val; + + return 0; +} + +static int ap1302_s_register(struct v4l2_subdev *sd, + const struct v4l2_dbg_register *reg) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + int ret; + + if (reg->size != AP1302_REG16 && + reg->size != AP1302_REG32) + return -EINVAL; + + mutex_lock(&dev->input_lock); + if (dev->power_on) + ret = ap1302_i2c_write_reg(sd, reg->reg, reg->size, reg->val); + else + ret = -EIO; + mutex_unlock(&dev->input_lock); + return ret; +} + +static long ap1302_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + long ret = 0; + switch (cmd) { + case VIDIOC_DBG_G_REGISTER: + ret = ap1302_g_register(sd, arg); + break; + case VIDIOC_DBG_S_REGISTER: + ret = ap1302_s_register(sd, arg); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = ap1302_s_ctrl, +}; + +static const char * const ctrl_run_mode_menu[] = { + NULL, + "Video", + "Still capture", + "Continuous capture", + "Preview", +}; + +static const struct v4l2_ctrl_config ctrls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_RUN_MODE, + .name = "Run Mode", + .type = V4L2_CTRL_TYPE_MENU, + .min = 1, + .def = 4, + .max = 4, + .qmenu = ctrl_run_mode_menu, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE, + .name = "Exposure", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = AP1302_MIN_EV, + .def = 0, + .max = AP1302_MAX_EV, + .step = 1, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE, + .name = "White Balance", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .def = 0, + .max = 9, + .step = 1, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_ZOOM_ABSOLUTE, + .name = "Zoom Absolute", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .def = 0, + .max = 1024, + .step = 1, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_COLORFX, + .name = "Color Special Effect", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .def = 0, + .max = 15, + .step = 1, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_SCENE_MODE, + .name = "Scene Mode", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .def = 0, + .max = 13, + .step = 1, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_POWER_LINE_FREQUENCY, + .name = "Light frequency filter", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .def = 3, + .max = 3, + .step = 1, + }, +}; + +static struct v4l2_subdev_sensor_ops ap1302_sensor_ops = { + .g_skip_frames = ap1302_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops ap1302_video_ops = { + .s_stream = ap1302_s_stream, + .g_frame_interval = ap1302_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops ap1302_core_ops = { + .s_power = ap1302_s_power, + .ioctl = ap1302_ioctl, +#ifdef CONFIG_VIDEO_ADV_DEBUG + .g_register = ap1302_g_register, + .s_register = ap1302_s_register, +#endif +}; + +static const struct v4l2_subdev_pad_ops ap1302_pad_ops = { + .enum_mbus_code = ap1302_enum_mbus_code, + .enum_frame_size = ap1302_enum_frame_size, + .get_fmt = ap1302_get_fmt, + .set_fmt = ap1302_set_fmt, +}; + +static const struct v4l2_subdev_ops ap1302_ops = { + .core = &ap1302_core_ops, + .pad = &ap1302_pad_ops, + .video = &ap1302_video_ops, + .sensor = &ap1302_sensor_ops +}; + +static int ap1302_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ap1302_device *dev = to_ap1302_device(sd); + + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + + release_firmware(dev->fw); + + media_entity_cleanup(&dev->sd.entity); + dev->platform_data->csi_cfg(sd, 0); + v4l2_device_unregister_subdev(sd); + + return 0; +} + +static int ap1302_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ap1302_device *dev; + int ret; + unsigned int i; + + dev_info(&client->dev, "ap1302 probe called.\n"); + + /* allocate device & init sub device */ + dev = devm_kzalloc(&client->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "%s: out of memory\n", __func__); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + v4l2_i2c_subdev_init(&(dev->sd), client, &ap1302_ops); + + ret = ap1302_request_firmware(&(dev->sd)); + if (ret) { + dev_err(&client->dev, "Cannot request ap1302 firmware.\n"); + goto out_free; + } + + dev->regmap16 = devm_regmap_init_i2c(client, &ap1302_reg16_config); + if (IS_ERR(dev->regmap16)) { + ret = PTR_ERR(dev->regmap16); + dev_err(&client->dev, + "Failed to allocate 16bit register map: %d\n", ret); + return ret; + } + + dev->regmap32 = devm_regmap_init_i2c(client, &ap1302_reg32_config); + if (IS_ERR(dev->regmap32)) { + ret = PTR_ERR(dev->regmap32); + dev_err(&client->dev, + "Failed to allocate 32bit register map: %d\n", ret); + return ret; + } + + if (client->dev.platform_data) { + ret = ap1302_s_config(&dev->sd, client->dev.platform_data); + if (ret) + goto out_free; + } + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + dev->cntx_res[CONTEXT_PREVIEW].res_num = ARRAY_SIZE(ap1302_preview_res); + dev->cntx_res[CONTEXT_PREVIEW].res_table = ap1302_preview_res; + dev->cntx_res[CONTEXT_SNAPSHOT].res_num = + ARRAY_SIZE(ap1302_snapshot_res); + dev->cntx_res[CONTEXT_SNAPSHOT].res_table = ap1302_snapshot_res; + dev->cntx_res[CONTEXT_VIDEO].res_num = ARRAY_SIZE(ap1302_video_res); + dev->cntx_res[CONTEXT_VIDEO].res_table = ap1302_video_res; + + ret = v4l2_ctrl_handler_init(&dev->ctrl_handler, ARRAY_SIZE(ctrls)); + if (ret) { + ap1302_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(ctrls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &ctrls[i], NULL); + + if (dev->ctrl_handler.error) { + ap1302_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + v4l2_ctrl_handler_setup(&dev->ctrl_handler); + + dev->run_mode = v4l2_ctrl_find(&dev->ctrl_handler, V4L2_CID_RUN_MODE); + v4l2_ctrl_s_ctrl(dev->run_mode, ATOMISP_RUN_MODE_PREVIEW); + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + ap1302_remove(client); + return ret; +out_free: + v4l2_device_unregister_subdev(&dev->sd); + return ret; +} + +static const struct i2c_device_id ap1302_id[] = { + {AP1302_NAME, 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, ap1302_id); + +static struct i2c_driver ap1302_driver = { + .driver = { + .name = AP1302_NAME, + }, + .probe = ap1302_probe, + .remove = ap1302_remove, + .id_table = ap1302_id, +}; + +module_i2c_driver(ap1302_driver); + +MODULE_AUTHOR("Tianshu Qiu <tian.shu.qiu@intel.com>"); +MODULE_DESCRIPTION("AP1302 Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/ap1302.h b/drivers/staging/media/atomisp/i2c/ap1302.h new file mode 100644 index 0000000..9341232 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ap1302.h @@ -0,0 +1,198 @@ +/* + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __AP1302_H__ +#define __AP1302_H__ + +#include "../include/linux/atomisp_platform.h" +#include <linux/regmap.h> +#include <linux/types.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-subdev.h> + +#define AP1302_NAME "ap1302" +#define AP1302_CHIP_ID 0x265 +#define AP1302_I2C_MAX_LEN 65534 +#define AP1302_FW_WINDOW_OFFSET 0x8000 +#define AP1302_FW_WINDOW_SIZE 0x2000 + +#define AP1302_REG16 2 +#define AP1302_REG32 4 + +#define REG_CHIP_VERSION 0x0000 +#define REG_CHIP_REV 0x0050 +#define REG_MF_ID 0x0004 +#define REG_ERROR 0x0006 +#define REG_CTRL 0x1000 +#define REG_DZ_TGT_FCT 0x1010 +#define REG_SFX_MODE 0x1016 +#define REG_SS_HEAD_PT0 0x1174 +#define REG_AE_BV_OFF 0x5014 +#define REG_AE_BV_BIAS 0x5016 +#define REG_AWB_CTRL 0x5100 +#define REG_FLICK_CTRL 0x5440 +#define REG_SCENE_CTRL 0x5454 +#define REG_BOOTDATA_STAGE 0x6002 +#define REG_SENSOR_SELECT 0x600C +#define REG_SYS_START 0x601A +#define REG_SIP_CRC 0xF052 + +#define REG_PREVIEW_BASE 0x2000 +#define REG_SNAPSHOT_BASE 0x3000 +#define REG_VIDEO_BASE 0x4000 +#define CNTX_WIDTH 0x00 +#define CNTX_HEIGHT 0x02 +#define CNTX_ROI_X0 0x04 +#define CNTX_ROI_Y0 0x06 +#define CNTX_ROI_X1 0x08 +#define CNTX_ROI_Y1 0x0A +#define CNTX_ASPECT 0x0C +#define CNTX_LOCK 0x0E +#define CNTX_ENABLE 0x10 +#define CNTX_OUT_FMT 0x12 +#define CNTX_SENSOR_MODE 0x14 +#define CNTX_MIPI_CTRL 0x16 +#define CNTX_MIPI_II_CTRL 0x18 +#define CNTX_LINE_TIME 0x1C +#define CNTX_MAX_FPS 0x20 +#define CNTX_AE_USG 0x22 +#define CNTX_AE_UPPER_ET 0x24 +#define CNTX_AE_MAX_ET 0x28 +#define CNTX_SS 0x2C +#define CNTX_S1_SENSOR_MODE 0x2E +#define CNTX_HINF_CTRL 0x30 + +#define CTRL_CNTX_MASK 0x03 +#define CTRL_CNTX_OFFSET 0x00 +#define HINF_CTRL_LANE_MASK 0x07 +#define HINF_CTRL_LANE_OFFSET 0x00 +#define MIPI_CTRL_IMGVC_MASK 0xC0 +#define MIPI_CTRL_IMGVC_OFFSET 0x06 +#define MIPI_CTRL_IMGTYPE_AUTO 0x3F +#define MIPI_CTRL_SSVC_MASK 0xC000 +#define MIPI_CTRL_SSVC_OFFSET 0x0E +#define MIPI_CTRL_SSTYPE_MASK 0x3F00 +#define MIPI_CTRL_SSTYPE_OFFSET 0x08 +#define OUT_FMT_IIS_MASK 0x30 +#define OUT_FMT_IIS_OFFSET 0x08 +#define OUT_FMT_SS_MASK 0x1000 +#define OUT_FMT_SS_OFFSET 0x12 +#define OUT_FMT_TYPE_MASK 0xFF +#define SENSOR_SELECT_MASK 0x03 +#define SENSOR_SELECT_OFFSET 0x00 +#define AWB_CTRL_MODE_MASK 0x0F +#define AWB_CTRL_MODE_OFFSET 0x00 +#define AWB_CTRL_FLASH_MASK 0x100 + +#define AP1302_FMT_UYVY422 0x50 + +#define AP1302_SYS_ACTIVATE 0x8010 +#define AP1302_SYS_SWITCH 0x8140 +#define AP1302_SENSOR_PRI 0x01 +#define AP1302_SENSOR_SEC 0x02 +#define AP1302_SS_CTRL 0x31 + +#define AP1302_MAX_RATIO_MISMATCH 10 /* Unit in percentage */ +#define AP1302_MAX_EV 2 +#define AP1302_MIN_EV -2 + +enum ap1302_contexts { + CONTEXT_PREVIEW = 0, + CONTEXT_SNAPSHOT, + CONTEXT_VIDEO, + CONTEXT_NUM +}; + +/* The context registers are defined according to preview/video registers. + Preview and video context have the same register definition. + But snapshot context does not have register S1_SENSOR_MODE. + When setting snapshot registers, if the offset exceeds + S1_SENSOR_MODE, the actual offset needs to minus 2. */ +struct ap1302_context_config { + u16 width; + u16 height; + u16 roi_x0; + u16 roi_y0; + u16 roi_x1; + u16 roi_y1; + u16 aspect_factor; + u16 lock; + u16 enable; + u16 out_fmt; + u16 sensor_mode; + u16 mipi_ctrl; + u16 mipi_ii_ctrl; + u16 padding; + u32 line_time; + u16 max_fps; + u16 ae_usg; + u32 ae_upper_et; + u32 ae_max_et; + u16 ss; + u16 s1_sensor_mode; + u16 hinf_ctrl; + u32 reserved; +}; + +struct ap1302_res_struct { + u16 width; + u16 height; + u16 fps; +}; + +struct ap1302_context_res { + s32 res_num; + s32 cur_res; + struct ap1302_res_struct *res_table; +}; + +struct ap1302_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct camera_sensor_platform_data *platform_data; + const struct firmware *fw; + struct mutex input_lock; /* serialize sensor's ioctl */ + struct v4l2_mbus_framefmt format; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *run_mode; + struct ap1302_context_config cntx_config[CONTEXT_NUM]; + struct ap1302_context_res cntx_res[CONTEXT_NUM]; + enum ap1302_contexts cur_context; + unsigned int num_lanes; + struct regmap *regmap16; + struct regmap *regmap32; + bool sys_activated; + bool power_on; +}; + +struct ap1302_firmware { + u32 crc; + u32 pll_init_size; + u32 total_size; + u32 reserved; +}; + +struct ap1302_context_info { + u16 offset; + u16 len; + char *name; +}; + +#endif diff --git a/drivers/staging/media/atomisp/i2c/gc0310.c b/drivers/staging/media/atomisp/i2c/gc0310.c new file mode 100644 index 0000000..1ec616a --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/gc0310.c @@ -0,0 +1,1490 @@ +/* + * Support for GalaxyCore GC0310 VGA camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/string.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kmod.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/moduleparam.h> +#include <media/v4l2-device.h> +#include <linux/io.h> +#include "../include/linux/atomisp_gmin_platform.h" + +#include "gc0310.h" + +/* i2c read/write stuff */ +static int gc0310_read_reg(struct i2c_client *client, + u16 data_length, u8 reg, u8 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[1]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != GC0310_8BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0, sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == GC0310_8BIT) + *val = (u8)data[0]; + + return 0; +} + +static int gc0310_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int gc0310_write_reg(struct i2c_client *client, u16 data_length, + u8 reg, u8 val) +{ + int ret; + unsigned char data[2] = {0}; + u8 *wreg = (u8 *)data; + const u16 len = data_length + sizeof(u8); /* 8-bit address + data */ + + if (data_length != GC0310_8BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = (u8)(reg & 0xff); + + if (data_length == GC0310_8BIT) { + data[1] = (u8)(val); + } + + ret = gc0310_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * gc0310_write_reg_array - Initializes a list of GC0310 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __gc0310_flush_reg_array, __gc0310_buf_reg_array() and + * __gc0310_write_reg_is_consecutive() are internal functions to + * gc0310_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __gc0310_flush_reg_array(struct i2c_client *client, + struct gc0310_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u8) + ctrl->index; /* 8-bit address + data */ + ctrl->buffer.addr = (u8)(ctrl->buffer.addr); + ctrl->index = 0; + + return gc0310_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __gc0310_buf_reg_array(struct i2c_client *client, + struct gc0310_write_ctrl *ctrl, + const struct gc0310_reg *next) +{ + int size; + + switch (next->type) { + case GC0310_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u8) >= GC0310_MAX_WRITE_BUF_SIZE) + return __gc0310_flush_reg_array(client, ctrl); + + return 0; +} + +static int __gc0310_write_reg_is_consecutive(struct i2c_client *client, + struct gc0310_write_ctrl *ctrl, + const struct gc0310_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +static int gc0310_write_reg_array(struct i2c_client *client, + const struct gc0310_reg *reglist) +{ + const struct gc0310_reg *next = reglist; + struct gc0310_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != GC0310_TOK_TERM; next++) { + switch (next->type & GC0310_TOK_MASK) { + case GC0310_TOK_DELAY: + err = __gc0310_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__gc0310_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __gc0310_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __gc0310_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __gc0310_flush_reg_array(client, &ctrl); +} +static int gc0310_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (GC0310_FOCAL_LENGTH_NUM << 16) | GC0310_FOCAL_LENGTH_DEM; + return 0; +} + +static int gc0310_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (GC0310_F_NUMBER_DEFAULT_NUM << 16) | GC0310_F_NUMBER_DEM; + return 0; +} + +static int gc0310_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (GC0310_F_NUMBER_DEFAULT_NUM << 24) | + (GC0310_F_NUMBER_DEM << 16) | + (GC0310_F_NUMBER_DEFAULT_NUM << 8) | GC0310_F_NUMBER_DEM; + return 0; +} + +static int gc0310_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + + *val = gc0310_res[dev->fmt_idx].bin_factor_x; + + return 0; +} + +static int gc0310_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + + *val = gc0310_res[dev->fmt_idx].bin_factor_y; + + return 0; +} + +static int gc0310_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct gc0310_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct atomisp_sensor_mode_data *buf = &info->data; + u16 val; + u8 reg_val; + int ret; + unsigned int hori_blanking; + unsigned int vert_blanking; + unsigned int sh_delay; + + if (!info) + return -EINVAL; + + /* pixel clock calculattion */ + dev->vt_pix_clk_freq_mhz = 14400000; // 16.8MHz + buf->vt_pix_clk_freq_mhz = dev->vt_pix_clk_freq_mhz; + pr_info("vt_pix_clk_freq_mhz=%d\n", buf->vt_pix_clk_freq_mhz); + + /* get integration time */ + buf->coarse_integration_time_min = GC0310_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + GC0310_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = GC0310_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + GC0310_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = GC0310_FINE_INTG_TIME_MIN; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + /* Getting crop_horizontal_start */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_CROP_START_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_CROP_START_L, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = val | (reg_val & 0xFF); + pr_info("crop_horizontal_start=%d\n", buf->crop_horizontal_start); + + /* Getting crop_vertical_start */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_CROP_START_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_CROP_START_L, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = val | (reg_val & 0xFF); + pr_info("crop_vertical_start=%d\n", buf->crop_vertical_start); + + /* Getting output_width */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_OUTSIZE_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_OUTSIZE_L, ®_val); + if (ret) + return ret; + buf->output_width = val | (reg_val & 0xFF); + pr_info("output_width=%d\n", buf->output_width); + + /* Getting output_height */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_OUTSIZE_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_OUTSIZE_L, ®_val); + if (ret) + return ret; + buf->output_height = val | (reg_val & 0xFF); + pr_info("output_height=%d\n", buf->output_height); + + buf->crop_horizontal_end = buf->crop_horizontal_start + buf->output_width - 1; + buf->crop_vertical_end = buf->crop_vertical_start + buf->output_height - 1; + pr_info("crop_horizontal_end=%d\n", buf->crop_horizontal_end); + pr_info("crop_vertical_end=%d\n", buf->crop_vertical_end); + + /* Getting line_length_pck */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_BLANKING_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_BLANKING_L, ®_val); + if (ret) + return ret; + hori_blanking = val | (reg_val & 0xFF); + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_SH_DELAY, ®_val); + if (ret) + return ret; + sh_delay = reg_val; + buf->line_length_pck = buf->output_width + hori_blanking + sh_delay + 4; + pr_info("hori_blanking=%d sh_delay=%d line_length_pck=%d\n", hori_blanking, sh_delay, buf->line_length_pck); + + /* Getting frame_length_lines */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_BLANKING_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_BLANKING_L, ®_val); + if (ret) + return ret; + vert_blanking = val | (reg_val & 0xFF); + buf->frame_length_lines = buf->output_height + vert_blanking; + pr_info("vert_blanking=%d frame_length_lines=%d\n", vert_blanking, buf->frame_length_lines); + + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static int gc0310_set_gain(struct v4l2_subdev *sd, int gain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 again, dgain; + + if (gain < 0x20) + gain = 0x20; + if (gain > 0x80) + gain = 0x80; + + if (gain >= 0x20 && gain < 0x40) { + again = 0x0; /* sqrt(2) */ + dgain = gain; + } else { + again = 0x2; /* 2 * sqrt(2) */ + dgain = gain / 2; + } + + pr_info("gain=0x%x again=0x%x dgain=0x%x\n", gain, again, dgain); + + /* set analog gain */ + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_AGC_ADJ, again); + if (ret) + return ret; + + /* set digital gain */ + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_DGC_ADJ, dgain); + if (ret) + return ret; + + return 0; +} + +static int __gc0310_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + pr_info("coarse_itg=%d gain=%d digitgain=%d\n", coarse_itg, gain, digitgain); + + /* set exposure */ + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_AEC_PK_EXPO_L, + coarse_itg & 0xff); + if (ret) + return ret; + + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_AEC_PK_EXPO_H, + (coarse_itg >> 8) & 0x0f); + if (ret) + return ret; + + ret = gc0310_set_gain(sd, gain); + if (ret) + return ret; + + return ret; +} + +static int gc0310_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __gc0310_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long gc0310_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + int exp = exposure->integration_time[0]; + int gain = exposure->gain[0]; + int digitgain = exposure->gain[1]; + + /* we should not accept the invalid value below. */ + if (gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + + return gc0310_set_exposure(sd, exp, gain, digitgain); +} + +/* TO DO */ +static int gc0310_v_flip(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +/* TO DO */ +static int gc0310_h_flip(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +static long gc0310_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return gc0310_s_exposure(sd, arg); + default: + return -EINVAL; + } + return 0; +} + +/* This returns the exposure time being used. This should only be used + * for filling in EXIF data, not for actual image processing. + */ +static int gc0310_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 reg_v; + int ret; + + /* get exposure */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_AEC_PK_EXPO_L, + ®_v); + if (ret) + goto err; + + *value = reg_v; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_AEC_PK_EXPO_H, + ®_v); + if (ret) + goto err; + + *value = *value + (reg_v << 8); +err: + return ret; +} + +static int gc0310_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct gc0310_device *dev = + container_of(ctrl->handler, struct gc0310_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + dev_dbg(&client->dev, "%s: CID_VFLIP:%d.\n", + __func__, ctrl->val); + ret = gc0310_v_flip(&dev->sd, ctrl->val); + break; + case V4L2_CID_HFLIP: + dev_dbg(&client->dev, "%s: CID_HFLIP:%d.\n", + __func__, ctrl->val); + ret = gc0310_h_flip(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int gc0310_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct gc0310_device *dev = + container_of(ctrl->handler, struct gc0310_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = gc0310_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = gc0310_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = gc0310_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = gc0310_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_HORZ: + ret = gc0310_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = gc0310_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = gc0310_s_ctrl, + .g_volatile_ctrl = gc0310_g_volatile_ctrl +}; + +struct v4l2_ctrl_config gc0310_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flip", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Mirror", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = GC0310_FOCAL_LENGTH_DEFAULT, + .max = GC0310_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = GC0310_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = GC0310_F_NUMBER_DEFAULT, + .max = GC0310_F_NUMBER_DEFAULT, + .step = 0x01, + .def = GC0310_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = GC0310_F_NUMBER_RANGE, + .max = GC0310_F_NUMBER_RANGE, + .step = 0x01, + .def = GC0310_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "horizontal binning factor", + .min = 0, + .max = GC0310_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vertical binning factor", + .min = 0, + .max = GC0310_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, +}; + +static int gc0310_init(struct v4l2_subdev *sd) +{ + int ret; + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct gc0310_device *dev = to_gc0310_sensor(sd); + + pr_info("%s S\n", __func__); + mutex_lock(&dev->input_lock); + + /* set inital registers */ + ret = gc0310_write_reg_array(client, gc0310_reset_register); + + /* restore settings */ + gc0310_res = gc0310_res_preview; + N_RES = N_RES_PREVIEW; + + mutex_unlock(&dev->input_lock); + + pr_info("%s E\n", __func__); + return 0; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = 0; + struct gc0310_device *dev = to_gc0310_sensor(sd); + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + if (flag) { + /* The upstream module driver (written to Crystal + * Cove) had this logic to pulse the rails low first. + * This appears to break things on the MRD7 with the + * X-Powers PMIC... + * + * ret = dev->platform_data->v1p8_ctrl(sd, 0); + * ret |= dev->platform_data->v2p8_ctrl(sd, 0); + * mdelay(50); + */ + ret |= dev->platform_data->v1p8_ctrl(sd, 1); + ret |= dev->platform_data->v2p8_ctrl(sd, 1); + usleep_range(10000, 15000); + } + + if (!flag || ret) { + ret |= dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct gc0310_device *dev = to_gc0310_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + /* GPIO0 == "reset" (active low), GPIO1 == "power down" */ + if (flag) { + /* Pulse reset, then release power down */ + ret = dev->platform_data->gpio0_ctrl(sd, 0); + usleep_range(5000, 10000); + ret |= dev->platform_data->gpio0_ctrl(sd, 1); + usleep_range(10000, 15000); + ret |= dev->platform_data->gpio1_ctrl(sd, 0); + usleep_range(10000, 15000); + } else { + ret = dev->platform_data->gpio1_ctrl(sd, 1); + ret |= dev->platform_data->gpio0_ctrl(sd, 0); + } + return ret; +} + + +static int power_down(struct v4l2_subdev *sd); + +static int power_up(struct v4l2_subdev *sd) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + pr_info("%s S\n", __func__); + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 1); + if (ret) + goto fail_gpio; + } + + msleep(100); + + pr_info("%s E\n", __func__); + return 0; + +fail_gpio: + dev->platform_data->flisclk_ctrl(sd, 0); +fail_clk: + power_ctrl(sd, 0); +fail_power: + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int gc0310_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + if (on == 0) + return power_down(sd); + else { + ret = power_up(sd); + if (!ret) + return gc0310_init(sd); + } + return ret; +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between resolution and w/h. + * res->width/height smaller than w/h wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 800 +static int distance(struct gc0310_resolution *res, u32 w, u32 h) +{ + unsigned int w_ratio = (res->width << 13) / w; + unsigned int h_ratio; + int match; + + if (h == 0) + return -1; + h_ratio = (res->height << 13) / h; + if (h_ratio == 0) + return -1; + match = abs(((w_ratio << 13) / h_ratio) - ((int)8192)); + + if ((w_ratio < (int)8192) || (h_ratio < (int)8192) || + (match > LARGEST_ALLOWED_RATIO_MISMATCH)) + return -1; + + return w_ratio + h_ratio; +} + +/* Return the nearest higher resolution index */ +static int nearest_resolution_index(int w, int h) +{ + int i; + int idx = -1; + int dist; + int min_dist = INT_MAX; + struct gc0310_resolution *tmp_res = NULL; + + for (i = 0; i < N_RES; i++) { + tmp_res = &gc0310_res[i]; + dist = distance(tmp_res, w, h); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + } + } + + return idx; +} + +static int get_resolution_index(int w, int h) +{ + int i; + + for (i = 0; i < N_RES; i++) { + if (w != gc0310_res[i].width) + continue; + if (h != gc0310_res[i].height) + continue; + + return i; + } + + return -1; +} + + +/* TODO: remove it. */ +static int startup(struct v4l2_subdev *sd) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + pr_info("%s S\n", __func__); + + ret = gc0310_write_reg_array(client, gc0310_res[dev->fmt_idx].regs); + if (ret) { + dev_err(&client->dev, "gc0310 write register err.\n"); + return ret; + } + + pr_info("%s E\n", __func__); + return ret; +} + +static int gc0310_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *gc0310_info = NULL; + int ret = 0; + int idx = 0; + pr_info("%s S\n", __func__); + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + gc0310_info = v4l2_get_subdev_hostdata(sd); + if (!gc0310_info) + return -EINVAL; + + mutex_lock(&dev->input_lock); + + idx = nearest_resolution_index(fmt->width, fmt->height); + if (idx == -1) { + /* return the largest resolution */ + fmt->width = gc0310_res[N_RES - 1].width; + fmt->height = gc0310_res[N_RES - 1].height; + } else { + fmt->width = gc0310_res[idx].width; + fmt->height = gc0310_res[idx].height; + } + fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8; + + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + dev->fmt_idx = get_resolution_index(fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + dev_err(&client->dev, "get resolution fail\n"); + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + printk("%s: before gc0310_write_reg_array %s\n", __FUNCTION__, + gc0310_res[dev->fmt_idx].desc); + ret = startup(sd); + if (ret) { + dev_err(&client->dev, "gc0310 startup err\n"); + goto err; + } + + ret = gc0310_get_intg_factor(client, gc0310_info, + &gc0310_res[dev->fmt_idx]); + if (ret) { + dev_err(&client->dev, "failed to get integration_factor\n"); + goto err; + } + + pr_info("%s E\n", __func__); +err: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc0310_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct gc0310_device *dev = to_gc0310_sensor(sd); + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + fmt->width = gc0310_res[dev->fmt_idx].width; + fmt->height = gc0310_res[dev->fmt_idx].height; + fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8; + + return 0; +} + +static int gc0310_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u8 high, low; + int ret; + u16 id; + + pr_info("%s S\n", __func__); + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_SC_CMMN_CHIP_ID_H, &high); + if (ret) { + dev_err(&client->dev, "read sensor_id_high failed\n"); + return -ENODEV; + } + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_SC_CMMN_CHIP_ID_L, &low); + if (ret) { + dev_err(&client->dev, "read sensor_id_low failed\n"); + return -ENODEV; + } + id = ((((u16) high) << 8) | (u16) low); + pr_info("sensor ID = 0x%x\n", id); + + if (id != GC0310_ID) { + dev_err(&client->dev, "sensor ID error, read id = 0x%x, target id = 0x%x\n", id, GC0310_ID); + return -ENODEV; + } + + dev_dbg(&client->dev, "detect gc0310 success\n"); + + pr_info("%s E\n", __func__); + + return 0; +} + +static int gc0310_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + pr_info("%s S enable=%d\n", __func__, enable); + mutex_lock(&dev->input_lock); + + if (enable) { + /* enable per frame MIPI and sensor ctrl reset */ + ret = gc0310_write_reg(client, GC0310_8BIT, + 0xFE, 0x30); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + } + + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_RESET_RELATED, GC0310_REGISTER_PAGE_3); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = gc0310_write_reg(client, GC0310_8BIT, GC0310_SW_STREAM, + enable ? GC0310_START_STREAMING : + GC0310_STOP_STREAMING); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_RESET_RELATED, GC0310_REGISTER_PAGE_0); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + + mutex_unlock(&dev->input_lock); + pr_info("%s E\n", __func__); + return ret; +} + + +static int gc0310_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + pr_info("%s S\n", __func__); + if (!platform_data) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) { + dev_err(&client->dev, "platform init err\n"); + goto platform_init_failed; + } + } + /* power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "gc0310 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "gc0310 power-up err.\n"); + goto fail_power_on; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = gc0310_detect(client); + if (ret) { + dev_err(&client->dev, "gc0310_detect err s_config.\n"); + goto fail_csi_cfg; + } + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "gc0310 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + pr_info("%s E\n", __func__); + return 0; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); +platform_init_failed: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc0310_g_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (!param) + return -EINVAL; + + if (param->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(&client->dev, "unsupported buffer type.\n"); + return -EINVAL; + } + + memset(param, 0, sizeof(*param)); + param->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + if (dev->fmt_idx >= 0 && dev->fmt_idx < N_RES) { + param->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + param->parm.capture.timeperframe.numerator = 1; + param->parm.capture.capturemode = dev->run_mode; + param->parm.capture.timeperframe.denominator = + gc0310_res[dev->fmt_idx].fps; + } + return 0; +} + +static int gc0310_s_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + dev->run_mode = param->parm.capture.capturemode; + + mutex_lock(&dev->input_lock); + switch (dev->run_mode) { + case CI_MODE_VIDEO: + gc0310_res = gc0310_res_video; + N_RES = N_RES_VIDEO; + break; + case CI_MODE_STILL_CAPTURE: + gc0310_res = gc0310_res_still; + N_RES = N_RES_STILL; + break; + default: + gc0310_res = gc0310_res_preview; + N_RES = N_RES_PREVIEW; + } + mutex_unlock(&dev->input_lock); + return 0; +} + +static int gc0310_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = gc0310_res[dev->fmt_idx].fps; + + return 0; +} + +static int gc0310_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SGRBG8_1X8; + return 0; +} + +static int gc0310_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = gc0310_res[index].width; + fse->min_height = gc0310_res[index].height; + fse->max_width = gc0310_res[index].width; + fse->max_height = gc0310_res[index].height; + + return 0; + +} + + +static int gc0310_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = gc0310_res[dev->fmt_idx].skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops gc0310_sensor_ops = { + .g_skip_frames = gc0310_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops gc0310_video_ops = { + .s_stream = gc0310_s_stream, + .g_parm = gc0310_g_parm, + .s_parm = gc0310_s_parm, + .g_frame_interval = gc0310_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops gc0310_core_ops = { + .s_power = gc0310_s_power, + .ioctl = gc0310_ioctl, +}; + +static const struct v4l2_subdev_pad_ops gc0310_pad_ops = { + .enum_mbus_code = gc0310_enum_mbus_code, + .enum_frame_size = gc0310_enum_frame_size, + .get_fmt = gc0310_get_fmt, + .set_fmt = gc0310_set_fmt, +}; + +static const struct v4l2_subdev_ops gc0310_ops = { + .core = &gc0310_core_ops, + .video = &gc0310_video_ops, + .pad = &gc0310_pad_ops, + .sensor = &gc0310_sensor_ops, +}; + +static int gc0310_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct gc0310_device *dev = to_gc0310_sensor(sd); + dev_dbg(&client->dev, "gc0310_remove...\n"); + + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + + dev->platform_data->csi_cfg(sd, 0); + + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); + + return 0; +} + +static int gc0310_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct gc0310_device *dev; + int ret; + void *pdata; + unsigned int i; + + pr_info("%s S\n", __func__); + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + dev->fmt_idx = 0; + v4l2_i2c_subdev_init(&(dev->sd), client, &gc0310_ops); + + if (ACPI_COMPANION(&client->dev)) + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_8, + atomisp_bayer_order_grbg); + else + pdata = client->dev.platform_data; + + if (!pdata) { + ret = -EINVAL; + goto out_free; + } + + ret = gc0310_s_config(&dev->sd, client->irq, pdata); + if (ret) + goto out_free; + + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) + goto out_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SGRBG8_1X8; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(gc0310_controls)); + if (ret) { + gc0310_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(gc0310_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &gc0310_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + gc0310_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + gc0310_remove(client); + + pr_info("%s E\n", __func__); + return ret; +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +static struct acpi_device_id gc0310_acpi_match[] = { + {"XXGC0310"}, + {}, +}; + +MODULE_DEVICE_TABLE(acpi, gc0310_acpi_match); + +MODULE_DEVICE_TABLE(i2c, gc0310_id); +static struct i2c_driver gc0310_driver = { + .driver = { + .name = GC0310_NAME, + .acpi_match_table = ACPI_PTR(gc0310_acpi_match), + }, + .probe = gc0310_probe, + .remove = gc0310_remove, + .id_table = gc0310_id, +}; + +static int init_gc0310(void) +{ + return i2c_add_driver(&gc0310_driver); +} + +static void exit_gc0310(void) +{ + + i2c_del_driver(&gc0310_driver); +} + +module_init(init_gc0310); +module_exit(exit_gc0310); + +MODULE_AUTHOR("Lai, Angie <angie.lai@intel.com>"); +MODULE_DESCRIPTION("A low-level driver for GalaxyCore GC0310 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/gc0310.h b/drivers/staging/media/atomisp/i2c/gc0310.h new file mode 100644 index 0000000..f31eb27 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/gc0310.h @@ -0,0 +1,459 @@ +/* + * Support for GalaxyCore GC0310 VGA camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __GC0310_H__ +#define __GC0310_H__ +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/i2c.h> +#include <linux/acpi.h> +#include <linux/delay.h> +#include <linux/videodev2.h> +#include <linux/spinlock.h> +#include <media/v4l2-subdev.h> +#include <media/v4l2-device.h> +#include <media/v4l2-ctrls.h> +#include <linux/v4l2-mediabus.h> +#include <media/media-entity.h> + +#include "../include/linux/atomisp_platform.h" + +#define GC0310_NAME "gc0310" + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 1 +#define I2C_RETRY_COUNT 5 + +#define GC0310_FOCAL_LENGTH_NUM 278 /*2.78mm*/ +#define GC0310_FOCAL_LENGTH_DEM 100 +#define GC0310_F_NUMBER_DEFAULT_NUM 26 +#define GC0310_F_NUMBER_DEM 10 + +#define MAX_FMTS 1 + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define GC0310_FOCAL_LENGTH_DEFAULT 0x1160064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define GC0310_F_NUMBER_DEFAULT 0x1a000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define GC0310_F_NUMBER_RANGE 0x1a0a1a0a +#define GC0310_ID 0xa310 + +#define GC0310_RESET_RELATED 0xFE +#define GC0310_REGISTER_PAGE_0 0x0 +#define GC0310_REGISTER_PAGE_3 0x3 + +#define GC0310_FINE_INTG_TIME_MIN 0 +#define GC0310_FINE_INTG_TIME_MAX_MARGIN 0 +#define GC0310_COARSE_INTG_TIME_MIN 1 +#define GC0310_COARSE_INTG_TIME_MAX_MARGIN 6 + +/* + * GC0310 System control registers + */ +#define GC0310_SW_STREAM 0x10 + +#define GC0310_SC_CMMN_CHIP_ID_H 0xf0 +#define GC0310_SC_CMMN_CHIP_ID_L 0xf1 + +#define GC0310_AEC_PK_EXPO_H 0x03 +#define GC0310_AEC_PK_EXPO_L 0x04 +#define GC0310_AGC_ADJ 0x48 +#define GC0310_DGC_ADJ 0x71 +#if 0 +#define GC0310_GROUP_ACCESS 0x3208 +#endif + +#define GC0310_H_CROP_START_H 0x09 +#define GC0310_H_CROP_START_L 0x0A +#define GC0310_V_CROP_START_H 0x0B +#define GC0310_V_CROP_START_L 0x0C +#define GC0310_H_OUTSIZE_H 0x0F +#define GC0310_H_OUTSIZE_L 0x10 +#define GC0310_V_OUTSIZE_H 0x0D +#define GC0310_V_OUTSIZE_L 0x0E +#define GC0310_H_BLANKING_H 0x05 +#define GC0310_H_BLANKING_L 0x06 +#define GC0310_V_BLANKING_H 0x07 +#define GC0310_V_BLANKING_L 0x08 +#define GC0310_SH_DELAY 0x11 + +#define GC0310_START_STREAMING 0x94 /* 8-bit enable */ +#define GC0310_STOP_STREAMING 0x0 /* 8-bit disable */ + +#define GC0310_BIN_FACTOR_MAX 3 + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct gc0310_resolution { + u8 *desc; + const struct gc0310_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u32 skip_frames; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; +}; + +struct gc0310_format { + u8 *desc; + u32 pixelformat; + struct gc0310_reg *regs; +}; + +/* + * gc0310 device structure. + */ +struct gc0310_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + struct v4l2_ctrl_handler ctrl_handler; + + struct camera_sensor_platform_data *platform_data; + int vt_pix_clk_freq_mhz; + int fmt_idx; + int run_mode; + u8 res; + u8 type; +}; + +enum gc0310_tok_type { + GC0310_8BIT = 0x0001, + GC0310_TOK_TERM = 0xf000, /* terminating token for reg list */ + GC0310_TOK_DELAY = 0xfe00, /* delay token for reg list */ + GC0310_TOK_MASK = 0xfff0 +}; + +/** + * struct gc0310_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct gc0310_reg { + enum gc0310_tok_type type; + u8 reg; + u8 val; /* @set value for read/mod/write, @mask */ +}; + +#define to_gc0310_sensor(x) container_of(x, struct gc0310_device, sd) + +#define GC0310_MAX_WRITE_BUF_SIZE 30 + +struct gc0310_write_buffer { + u8 addr; + u8 data[GC0310_MAX_WRITE_BUF_SIZE]; +}; + +struct gc0310_write_ctrl { + int index; + struct gc0310_write_buffer buffer; +}; + +static const struct i2c_device_id gc0310_id[] = { + {GC0310_NAME, 0}, + {} +}; + +/* + * Register settings for various resolution + */ +static const struct gc0310_reg gc0310_reset_register[] = { +///////////////////////////////////////////////// +///////////////// system reg ///////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0xfe, 0xf0}, + {GC0310_8BIT, 0xfe, 0xf0}, + {GC0310_8BIT, 0xfe, 0x00}, + + {GC0310_8BIT, 0xfc, 0x0e}, //4e + {GC0310_8BIT, 0xfc, 0x0e}, //16//4e // [0]apwd [6]regf_clk_gate + {GC0310_8BIT, 0xf2, 0x80}, //sync output + {GC0310_8BIT, 0xf3, 0x00}, //1f//01 data output + {GC0310_8BIT, 0xf7, 0x33}, //f9 + {GC0310_8BIT, 0xf8, 0x05}, //00 + {GC0310_8BIT, 0xf9, 0x0e}, // 0x8e //0f + {GC0310_8BIT, 0xfa, 0x11}, + +///////////////////////////////////////////////// +/////////////////// MIPI //////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0xfe, 0x03}, + {GC0310_8BIT, 0x01, 0x03}, ///mipi 1lane + {GC0310_8BIT, 0x02, 0x22}, // 0x33 + {GC0310_8BIT, 0x03, 0x94}, + {GC0310_8BIT, 0x04, 0x01}, // fifo_prog + {GC0310_8BIT, 0x05, 0x00}, //fifo_prog + {GC0310_8BIT, 0x06, 0x80}, //b0 //YUV ISP data + {GC0310_8BIT, 0x11, 0x2a},//1e //LDI set YUV422 + {GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0] // + {GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8] + {GC0310_8BIT, 0x15, 0x12}, // 0x10 //DPHYY_MODE read_ready + {GC0310_8BIT, 0x17, 0x01}, + {GC0310_8BIT, 0x40, 0x08}, + {GC0310_8BIT, 0x41, 0x00}, + {GC0310_8BIT, 0x42, 0x00}, + {GC0310_8BIT, 0x43, 0x00}, + {GC0310_8BIT, 0x21, 0x02}, // 0x01 + {GC0310_8BIT, 0x22, 0x02}, // 0x01 + {GC0310_8BIT, 0x23, 0x01}, // 0x05 //Nor:0x05 DOU:0x06 + {GC0310_8BIT, 0x29, 0x00}, + {GC0310_8BIT, 0x2A, 0x25}, // 0x05 //data zero 0x7a de + {GC0310_8BIT, 0x2B, 0x02}, + + {GC0310_8BIT, 0xfe, 0x00}, + +///////////////////////////////////////////////// +///////////////// CISCTL reg ///////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0x00, 0x2f}, //2f//0f//02//01 + {GC0310_8BIT, 0x01, 0x0f}, //06 + {GC0310_8BIT, 0x02, 0x04}, + {GC0310_8BIT, 0x4f, 0x00}, //AEC 0FF + {GC0310_8BIT, 0x03, 0x01}, // 0x03 //04 + {GC0310_8BIT, 0x04, 0xc0}, // 0xe8 //58 + {GC0310_8BIT, 0x05, 0x00}, + {GC0310_8BIT, 0x06, 0xb2}, // 0x0a //HB + {GC0310_8BIT, 0x07, 0x00}, + {GC0310_8BIT, 0x08, 0x0c}, // 0x89 //VB + {GC0310_8BIT, 0x09, 0x00}, //row start + {GC0310_8BIT, 0x0a, 0x00}, // + {GC0310_8BIT, 0x0b, 0x00}, //col start + {GC0310_8BIT, 0x0c, 0x00}, + {GC0310_8BIT, 0x0d, 0x01}, //height + {GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height + {GC0310_8BIT, 0x0f, 0x02}, //width + {GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height + {GC0310_8BIT, 0x17, 0x14}, + {GC0310_8BIT, 0x18, 0x1a}, //0a//[4]double reset + {GC0310_8BIT, 0x19, 0x14}, //AD pipeline + {GC0310_8BIT, 0x1b, 0x48}, + {GC0310_8BIT, 0x1e, 0x6b}, //3b//col bias + {GC0310_8BIT, 0x1f, 0x28}, //20//00//08//txlow + {GC0310_8BIT, 0x20, 0x89}, //88//0c//[3:2]DA15 + {GC0310_8BIT, 0x21, 0x49}, //48//[3] txhigh + {GC0310_8BIT, 0x22, 0xb0}, + {GC0310_8BIT, 0x23, 0x04}, //[1:0]vcm_r + {GC0310_8BIT, 0x24, 0x16}, //15 + {GC0310_8BIT, 0x34, 0x20}, //[6:4] rsg high//range + +///////////////////////////////////////////////// +//////////////////// BLK //////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0x26, 0x23}, //[1]dark_current_en [0]offset_en + {GC0310_8BIT, 0x28, 0xff}, //BLK_limie_value + {GC0310_8BIT, 0x29, 0x00}, //global offset + {GC0310_8BIT, 0x33, 0x18}, //offset_ratio + {GC0310_8BIT, 0x37, 0x20}, //dark_current_ratio + {GC0310_8BIT, 0x2a, 0x00}, + {GC0310_8BIT, 0x2b, 0x00}, + {GC0310_8BIT, 0x2c, 0x00}, + {GC0310_8BIT, 0x2d, 0x00}, + {GC0310_8BIT, 0x2e, 0x00}, + {GC0310_8BIT, 0x2f, 0x00}, + {GC0310_8BIT, 0x30, 0x00}, + {GC0310_8BIT, 0x31, 0x00}, + {GC0310_8BIT, 0x47, 0x80}, //a7 + {GC0310_8BIT, 0x4e, 0x66}, //select_row + {GC0310_8BIT, 0xa8, 0x02}, //win_width_dark, same with crop_win_width + {GC0310_8BIT, 0xa9, 0x80}, + +///////////////////////////////////////////////// +////////////////// ISP reg /////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0x40, 0x06}, // 0xff //ff //48 + {GC0310_8BIT, 0x41, 0x00}, // 0x21 //00//[0]curve_en + {GC0310_8BIT, 0x42, 0x04}, // 0xcf //0a//[1]awn_en + {GC0310_8BIT, 0x44, 0x18}, // 0x18 //02 + {GC0310_8BIT, 0x46, 0x02}, // 0x03 //sync + {GC0310_8BIT, 0x49, 0x03}, + {GC0310_8BIT, 0x4c, 0x20}, //00[5]pretect exp + {GC0310_8BIT, 0x50, 0x01}, //crop enable + {GC0310_8BIT, 0x51, 0x00}, + {GC0310_8BIT, 0x52, 0x00}, + {GC0310_8BIT, 0x53, 0x00}, + {GC0310_8BIT, 0x54, 0x01}, + {GC0310_8BIT, 0x55, 0x01}, //crop window height + {GC0310_8BIT, 0x56, 0xf0}, + {GC0310_8BIT, 0x57, 0x02}, //crop window width + {GC0310_8BIT, 0x58, 0x90}, + +///////////////////////////////////////////////// +/////////////////// GAIN //////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0x70, 0x70}, //70 //80//global gain + {GC0310_8BIT, 0x71, 0x20}, // pregain gain + {GC0310_8BIT, 0x72, 0x40}, // post gain + {GC0310_8BIT, 0x5a, 0x84}, //84//analog gain 0 + {GC0310_8BIT, 0x5b, 0xc9}, //c9 + {GC0310_8BIT, 0x5c, 0xed}, //ed//not use pga gain highest level + {GC0310_8BIT, 0x77, 0x40}, // R gain 0x74 //awb gain + {GC0310_8BIT, 0x78, 0x40}, // G gain + {GC0310_8BIT, 0x79, 0x40}, // B gain 0x5f + + {GC0310_8BIT, 0x48, 0x00}, + {GC0310_8BIT, 0xfe, 0x01}, + {GC0310_8BIT, 0x0a, 0x45}, //[7]col gain mode + + {GC0310_8BIT, 0x3e, 0x40}, + {GC0310_8BIT, 0x3f, 0x5c}, + {GC0310_8BIT, 0x40, 0x7b}, + {GC0310_8BIT, 0x41, 0xbd}, + {GC0310_8BIT, 0x42, 0xf6}, + {GC0310_8BIT, 0x43, 0x63}, + {GC0310_8BIT, 0x03, 0x60}, + {GC0310_8BIT, 0x44, 0x03}, + +///////////////////////////////////////////////// +///////////////// dark sun ////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0xfe, 0x01}, + {GC0310_8BIT, 0x45, 0xa4}, // 0xf7 + {GC0310_8BIT, 0x46, 0xf0}, // 0xff //f0//sun vaule th + {GC0310_8BIT, 0x48, 0x03}, //sun mode + {GC0310_8BIT, 0x4f, 0x60}, //sun_clamp + {GC0310_8BIT, 0xfe, 0x00}, + + {GC0310_TOK_TERM, 0, 0}, +}; + +static struct gc0310_reg const gc0310_VGA_30fps[] = { + {GC0310_8BIT, 0xfe, 0x00}, + {GC0310_8BIT, 0x0d, 0x01}, //height + {GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height + {GC0310_8BIT, 0x0f, 0x02}, //width + {GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height + + {GC0310_8BIT, 0x50, 0x01}, //crop enable + {GC0310_8BIT, 0x51, 0x00}, + {GC0310_8BIT, 0x52, 0x00}, + {GC0310_8BIT, 0x53, 0x00}, + {GC0310_8BIT, 0x54, 0x01}, + {GC0310_8BIT, 0x55, 0x01}, //crop window height + {GC0310_8BIT, 0x56, 0xf0}, + {GC0310_8BIT, 0x57, 0x02}, //crop window width + {GC0310_8BIT, 0x58, 0x90}, + + {GC0310_8BIT, 0xfe, 0x03}, + {GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0] // + {GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8] + + {GC0310_8BIT, 0xfe, 0x00}, + + {GC0310_TOK_TERM, 0, 0}, +}; + + +struct gc0310_resolution gc0310_res_preview[] = { + { + .desc = "gc0310_VGA_30fps", + .width = 656, // 648, + .height = 496, // 488, + .fps = 30, + //.pix_clk_freq = 73, + .used = 0, +#if 0 + .pixels_per_line = 0x0314, + .lines_per_frame = 0x0213, +#endif + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 2, + .regs = gc0310_VGA_30fps, + }, +}; +#define N_RES_PREVIEW (ARRAY_SIZE(gc0310_res_preview)) + +struct gc0310_resolution gc0310_res_still[] = { + { + .desc = "gc0310_VGA_30fps", + .width = 656, // 648, + .height = 496, // 488, + .fps = 30, + //.pix_clk_freq = 73, + .used = 0, +#if 0 + .pixels_per_line = 0x0314, + .lines_per_frame = 0x0213, +#endif + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 2, + .regs = gc0310_VGA_30fps, + }, +}; +#define N_RES_STILL (ARRAY_SIZE(gc0310_res_still)) + +struct gc0310_resolution gc0310_res_video[] = { + { + .desc = "gc0310_VGA_30fps", + .width = 656, // 648, + .height = 496, // 488, + .fps = 30, + //.pix_clk_freq = 73, + .used = 0, +#if 0 + .pixels_per_line = 0x0314, + .lines_per_frame = 0x0213, +#endif + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 2, + .regs = gc0310_VGA_30fps, + }, +}; +#define N_RES_VIDEO (ARRAY_SIZE(gc0310_res_video)) + +static struct gc0310_resolution *gc0310_res = gc0310_res_preview; +static int N_RES = N_RES_PREVIEW; +#endif + diff --git a/drivers/staging/media/atomisp/i2c/gc2235.c b/drivers/staging/media/atomisp/i2c/gc2235.c new file mode 100644 index 0000000..50f4317 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/gc2235.c @@ -0,0 +1,1219 @@ +/* + * Support for GalaxyCore GC2235 2M camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/string.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kmod.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/moduleparam.h> +#include <media/v4l2-device.h> +#include "../include/linux/atomisp_gmin_platform.h" +#include <linux/acpi.h> +#include <linux/io.h> + +#include "gc2235.h" + +/* i2c read/write stuff */ +static int gc2235_read_reg(struct i2c_client *client, + u16 data_length, u16 reg, u16 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[6]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != GC2235_8BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0, sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == GC2235_8BIT) + *val = (u8)data[0]; + + return 0; +} + +static int gc2235_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int gc2235_write_reg(struct i2c_client *client, u16 data_length, + u8 reg, u8 val) +{ + int ret; + unsigned char data[4] = {0}; + const u16 len = data_length + sizeof(u8); /* 16-bit address + data */ + + if (data_length != GC2235_8BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + data[0] = reg; + data[1] = val; + + ret = gc2235_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +static int __gc2235_flush_reg_array(struct i2c_client *client, + struct gc2235_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u8) + ctrl->index; /* 8-bit address + data */ + ctrl->index = 0; + + return gc2235_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __gc2235_buf_reg_array(struct i2c_client *client, + struct gc2235_write_ctrl *ctrl, + const struct gc2235_reg *next) +{ + int size; + + if (next->type != GC2235_8BIT) + return -EINVAL; + + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u8) >= GC2235_MAX_WRITE_BUF_SIZE) + return __gc2235_flush_reg_array(client, ctrl); + + return 0; +} +static int __gc2235_write_reg_is_consecutive(struct i2c_client *client, + struct gc2235_write_ctrl *ctrl, + const struct gc2235_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} +static int gc2235_write_reg_array(struct i2c_client *client, + const struct gc2235_reg *reglist) +{ + const struct gc2235_reg *next = reglist; + struct gc2235_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != GC2235_TOK_TERM; next++) { + switch (next->type & GC2235_TOK_MASK) { + case GC2235_TOK_DELAY: + err = __gc2235_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__gc2235_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __gc2235_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __gc2235_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __gc2235_flush_reg_array(client, &ctrl); +} + +static int gc2235_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (GC2235_FOCAL_LENGTH_NUM << 16) | GC2235_FOCAL_LENGTH_DEM; + return 0; +} + +static int gc2235_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (GC2235_F_NUMBER_DEFAULT_NUM << 16) | GC2235_F_NUMBER_DEM; + return 0; +} + +static int gc2235_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (GC2235_F_NUMBER_DEFAULT_NUM << 24) | + (GC2235_F_NUMBER_DEM << 16) | + (GC2235_F_NUMBER_DEFAULT_NUM << 8) | GC2235_F_NUMBER_DEM; + return 0; +} + + +static int gc2235_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct gc2235_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct atomisp_sensor_mode_data *buf = &info->data; + u16 reg_val, reg_val_h, dummy; + int ret; + + if (!info) + return -EINVAL; + + /* pixel clock calculattion */ + buf->vt_pix_clk_freq_mhz = dev->vt_pix_clk_freq_mhz = 30000000; + + /* get integration time */ + buf->coarse_integration_time_min = GC2235_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + GC2235_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = GC2235_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + GC2235_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = GC2235_FINE_INTG_TIME_MIN; + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_H_CROP_START_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_H_CROP_START_L, ®_val); + if (ret) + return ret; + + buf->crop_horizontal_start = (reg_val_h << 8) | reg_val; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_V_CROP_START_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_V_CROP_START_L, ®_val); + if (ret) + return ret; + + buf->crop_vertical_start = (reg_val_h << 8) | reg_val; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_H_OUTSIZE_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_H_OUTSIZE_L, ®_val); + if (ret) + return ret; + buf->output_width = (reg_val_h << 8) | reg_val; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_V_OUTSIZE_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_V_OUTSIZE_L, ®_val); + if (ret) + return ret; + buf->output_height = (reg_val_h << 8) | reg_val; + + buf->crop_horizontal_end = buf->crop_horizontal_start + + buf->output_width - 1; + buf->crop_vertical_end = buf->crop_vertical_start + + buf->output_height - 1; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_HB_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_HB_L, ®_val); + if (ret) + return ret; + + dummy = (reg_val_h << 8) | reg_val; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_SH_DELAY_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_SH_DELAY_L, ®_val); + +#if 0 + buf->line_length_pck = buf->output_width + 16 + dummy + + (((u16)reg_val_h << 8) | (u16)reg_val) + 4; +#endif + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_VB_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_VB_L, ®_val); + if (ret) + return ret; + +#if 0 + buf->frame_length_lines = buf->output_height + 32 + + (((u16)reg_val_h << 8) | (u16)reg_val); +#endif + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static long __gc2235_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 coarse_integration = (u16)coarse_itg; + int ret = 0; + u16 expo_coarse_h, expo_coarse_l, gain_val = 0xF0, gain_val2 = 0xF0; + expo_coarse_h = coarse_integration >> 8; + expo_coarse_l = coarse_integration & 0xff; + + ret = gc2235_write_reg(client, GC2235_8BIT, + GC2235_EXPOSURE_H, expo_coarse_h); + ret = gc2235_write_reg(client, GC2235_8BIT, + GC2235_EXPOSURE_L, expo_coarse_l); + + if (gain <= 0x58) { + gain_val = 0x40; + gain_val2 = 0x58; + } else if (gain < 256) { + gain_val = 0x40; + gain_val2 = gain; + } else { + gain_val2 = 64 * gain / 256; + gain_val = 0xff; + } + + ret = gc2235_write_reg(client, GC2235_8BIT, + GC2235_GLOBAL_GAIN, (u8)gain_val); + ret = gc2235_write_reg(client, GC2235_8BIT, + GC2235_PRE_GAIN, (u8)gain_val2); + + return ret; +} + + +static int gc2235_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __gc2235_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long gc2235_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + int exp = exposure->integration_time[0]; + int gain = exposure->gain[0]; + int digitgain = exposure->gain[1]; + + /* we should not accept the invalid value below. */ + if (gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + + return gc2235_set_exposure(sd, exp, gain, digitgain); +} +static long gc2235_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return gc2235_s_exposure(sd, arg); + default: + return -EINVAL; + } + return 0; +} +/* This returns the exposure time being used. This should only be used + * for filling in EXIF data, not for actual image processing. + */ +static int gc2235_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 reg_v, reg_v2; + int ret; + + /* get exposure */ + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_EXPOSURE_L, + ®_v); + if (ret) + goto err; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_EXPOSURE_H, + ®_v2); + if (ret) + goto err; + + reg_v += reg_v2 << 8; + + *value = reg_v; +err: + return ret; +} + +static int gc2235_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct gc2235_device *dev = + container_of(ctrl->handler, struct gc2235_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = gc2235_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = gc2235_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = gc2235_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = gc2235_g_fnumber_range(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .g_volatile_ctrl = gc2235_g_volatile_ctrl +}; + +struct v4l2_ctrl_config gc2235_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = GC2235_FOCAL_LENGTH_DEFAULT, + .max = GC2235_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = GC2235_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = GC2235_F_NUMBER_DEFAULT, + .max = GC2235_F_NUMBER_DEFAULT, + .step = 0x01, + .def = GC2235_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = GC2235_F_NUMBER_RANGE, + .max = GC2235_F_NUMBER_RANGE, + .step = 0x01, + .def = GC2235_F_NUMBER_RANGE, + .flags = 0, + }, +}; + +static int __gc2235_init(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + /* restore settings */ + gc2235_res = gc2235_res_preview; + N_RES = N_RES_PREVIEW; + + return gc2235_write_reg_array(client, gc2235_init_settings); +} + +static int is_init; + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = -1; + struct gc2235_device *dev = to_gc2235_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + if (flag) { + ret = dev->platform_data->v1p8_ctrl(sd, 1); + usleep_range(60, 90); + if (ret == 0) + ret |= dev->platform_data->v2p8_ctrl(sd, 1); + } else { + ret = dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + int ret = -1; + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + ret |= dev->platform_data->gpio1_ctrl(sd, !flag); + usleep_range(60, 90); + return dev->platform_data->gpio0_ctrl(sd, flag); +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* according to DS, at least 5ms is needed between DOVDD and PWDN */ + usleep_range(5000, 6000); + + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + usleep_range(5000, 6000); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 1); + if (ret) + goto fail_power; + } + + msleep(5); + return 0; + +fail_clk: + gpio_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int gc2235_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + + if (on == 0) + ret = power_down(sd); + else { + ret = power_up(sd); + if (!ret) + ret = __gc2235_init(sd); + is_init = 1; + } + return ret; +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between resolution and w/h. + * res->width/height smaller than w/h wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 800 +static int distance(struct gc2235_resolution *res, u32 w, u32 h) +{ + unsigned int w_ratio = (res->width << 13) / w; + unsigned int h_ratio; + int match; + + if (h == 0) + return -1; + h_ratio = (res->height << 13) / h; + if (h_ratio == 0) + return -1; + match = abs(((w_ratio << 13) / h_ratio) - 8192); + + if ((w_ratio < 8192) || (h_ratio < 8192) || + (match > LARGEST_ALLOWED_RATIO_MISMATCH)) + return -1; + + return w_ratio + h_ratio; +} + +/* Return the nearest higher resolution index */ +static int nearest_resolution_index(int w, int h) +{ + int i; + int idx = -1; + int dist; + int min_dist = INT_MAX; + struct gc2235_resolution *tmp_res = NULL; + + for (i = 0; i < N_RES; i++) { + tmp_res = &gc2235_res[i]; + dist = distance(tmp_res, w, h); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + } + } + + return idx; +} + +static int get_resolution_index(int w, int h) +{ + int i; + + for (i = 0; i < N_RES; i++) { + if (w != gc2235_res[i].width) + continue; + if (h != gc2235_res[i].height) + continue; + + return i; + } + + return -1; +} + +static int startup(struct v4l2_subdev *sd) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + if (is_init == 0) { + /* force gc2235 to do a reset in res change, otherwise it + * can not output normal after switching res. and it is not + * necessary for first time run up after power on, for the sack + * of performance + */ + power_down(sd); + power_up(sd); + gc2235_write_reg_array(client, gc2235_init_settings); + } + + ret = gc2235_write_reg_array(client, gc2235_res[dev->fmt_idx].regs); + if (ret) { + dev_err(&client->dev, "gc2235 write register err.\n"); + return ret; + } + is_init = 0; + + return ret; +} + +static int gc2235_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + + struct v4l2_mbus_framefmt *fmt = &format->format; + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *gc2235_info = NULL; + int ret = 0; + int idx; + + gc2235_info = v4l2_get_subdev_hostdata(sd); + if (!gc2235_info) + return -EINVAL; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + mutex_lock(&dev->input_lock); + idx = nearest_resolution_index(fmt->width, fmt->height); + if (idx == -1) { + /* return the largest resolution */ + fmt->width = gc2235_res[N_RES - 1].width; + fmt->height = gc2235_res[N_RES - 1].height; + } else { + fmt->width = gc2235_res[idx].width; + fmt->height = gc2235_res[idx].height; + } + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + dev->fmt_idx = get_resolution_index(fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + dev_err(&client->dev, "get resolution fail\n"); + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + ret = startup(sd); + if (ret) { + dev_err(&client->dev, "gc2235 startup err\n"); + goto err; + } + + ret = gc2235_get_intg_factor(client, gc2235_info, + &gc2235_res[dev->fmt_idx]); + if (ret) + dev_err(&client->dev, "failed to get integration_factor\n"); + +err: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc2235_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct gc2235_device *dev = to_gc2235_sensor(sd); + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + fmt->width = gc2235_res[dev->fmt_idx].width; + fmt->height = gc2235_res[dev->fmt_idx].height; + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + + return 0; +} + +static int gc2235_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u16 high, low; + int ret; + u16 id; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_SENSOR_ID_H, &high); + if (ret) { + dev_err(&client->dev, "sensor_id_high = 0x%x\n", high); + return -ENODEV; + } + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_SENSOR_ID_L, &low); + id = ((high << 8) | low); + + if (id != GC2235_ID) { + dev_err(&client->dev, "sensor ID error, 0x%x\n", id); + return -ENODEV; + } + + dev_info(&client->dev, "detect gc2235 success\n"); + return 0; +} + +static int gc2235_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + mutex_lock(&dev->input_lock); + + if (enable) + ret = gc2235_write_reg_array(client, gc2235_stream_on); + else + ret = gc2235_write_reg_array(client, gc2235_stream_off); + + mutex_unlock(&dev->input_lock); + return ret; +} + + +static int gc2235_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!platform_data) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) { + dev_err(&client->dev, "platform init err\n"); + goto platform_init_failed; + } + } + /* power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "gc2235 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "gc2235 power-up err.\n"); + goto fail_power_on; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = gc2235_detect(client); + if (ret) { + dev_err(&client->dev, "gc2235_detect err s_config.\n"); + goto fail_csi_cfg; + } + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "gc2235 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + return 0; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); +platform_init_failed: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc2235_g_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (!param) + return -EINVAL; + + if (param->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(&client->dev, "unsupported buffer type.\n"); + return -EINVAL; + } + + memset(param, 0, sizeof(*param)); + param->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + if (dev->fmt_idx >= 0 && dev->fmt_idx < N_RES) { + param->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + param->parm.capture.timeperframe.numerator = 1; + param->parm.capture.capturemode = dev->run_mode; + param->parm.capture.timeperframe.denominator = + gc2235_res[dev->fmt_idx].fps; + } + return 0; +} + +static int gc2235_s_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + dev->run_mode = param->parm.capture.capturemode; + + mutex_lock(&dev->input_lock); + switch (dev->run_mode) { + case CI_MODE_VIDEO: + gc2235_res = gc2235_res_video; + N_RES = N_RES_VIDEO; + break; + case CI_MODE_STILL_CAPTURE: + gc2235_res = gc2235_res_still; + N_RES = N_RES_STILL; + break; + default: + gc2235_res = gc2235_res_preview; + N_RES = N_RES_PREVIEW; + } + mutex_unlock(&dev->input_lock); + return 0; +} + +static int gc2235_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = gc2235_res[dev->fmt_idx].fps; + + return 0; +} + +static int gc2235_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + return 0; +} + +static int gc2235_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = gc2235_res[index].width; + fse->min_height = gc2235_res[index].height; + fse->max_width = gc2235_res[index].width; + fse->max_height = gc2235_res[index].height; + + return 0; + +} + +static int gc2235_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = gc2235_res[dev->fmt_idx].skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops gc2235_sensor_ops = { + .g_skip_frames = gc2235_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops gc2235_video_ops = { + .s_stream = gc2235_s_stream, + .g_parm = gc2235_g_parm, + .s_parm = gc2235_s_parm, + .g_frame_interval = gc2235_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops gc2235_core_ops = { + .s_power = gc2235_s_power, + .ioctl = gc2235_ioctl, +}; + +static const struct v4l2_subdev_pad_ops gc2235_pad_ops = { + .enum_mbus_code = gc2235_enum_mbus_code, + .enum_frame_size = gc2235_enum_frame_size, + .get_fmt = gc2235_get_fmt, + .set_fmt = gc2235_set_fmt, +}; + +static const struct v4l2_subdev_ops gc2235_ops = { + .core = &gc2235_core_ops, + .video = &gc2235_video_ops, + .pad = &gc2235_pad_ops, + .sensor = &gc2235_sensor_ops, +}; + +static int gc2235_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct gc2235_device *dev = to_gc2235_sensor(sd); + dev_dbg(&client->dev, "gc2235_remove...\n"); + + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + + dev->platform_data->csi_cfg(sd, 0); + + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); + + return 0; +} + +static int gc2235_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct gc2235_device *dev; + void *gcpdev; + int ret; + unsigned int i; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + dev->fmt_idx = 0; + v4l2_i2c_subdev_init(&(dev->sd), client, &gc2235_ops); + + gcpdev = client->dev.platform_data; + if (ACPI_COMPANION(&client->dev)) + gcpdev = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_grbg); + + ret = gc2235_s_config(&dev->sd, client->irq, gcpdev); + if (ret) + goto out_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(gc2235_controls)); + if (ret) { + gc2235_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(gc2235_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &gc2235_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + gc2235_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + gc2235_remove(client); + + if (ACPI_HANDLE(&client->dev)) + ret = atomisp_register_i2c_module(&dev->sd, gcpdev, RAW_CAMERA); + + return ret; +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + + return ret; +} + +static struct acpi_device_id gc2235_acpi_match[] = { + { "INT33F8" }, + {}, +}; + +MODULE_DEVICE_TABLE(acpi, gc2235_acpi_match); +MODULE_DEVICE_TABLE(i2c, gc2235_id); +static struct i2c_driver gc2235_driver = { + .driver = { + .name = GC2235_NAME, + .acpi_match_table = ACPI_PTR(gc2235_acpi_match), + }, + .probe = gc2235_probe, + .remove = gc2235_remove, + .id_table = gc2235_id, +}; + +static int init_gc2235(void) +{ + return i2c_add_driver(&gc2235_driver); +} + +static void exit_gc2235(void) +{ + + i2c_del_driver(&gc2235_driver); +} + +module_init(init_gc2235); +module_exit(exit_gc2235); + +MODULE_AUTHOR("Shuguang Gong <Shuguang.Gong@intel.com>"); +MODULE_DESCRIPTION("A low-level driver for GC2235 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/gc2235.h b/drivers/staging/media/atomisp/i2c/gc2235.h new file mode 100644 index 0000000..ccbc757 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/gc2235.h @@ -0,0 +1,672 @@ +/* + * Support for GalaxyCore GC2235 2M camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. + * + */ + +#ifndef __GC2235_H__ +#define __GC2235_H__ +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/i2c.h> +#include <linux/delay.h> +#include <linux/videodev2.h> +#include <linux/spinlock.h> +#include <media/v4l2-subdev.h> +#include <media/v4l2-device.h> +#include <media/v4l2-ctrls.h> +#include <linux/v4l2-mediabus.h> +#include <media/media-entity.h> + +#include "../include/linux/atomisp_platform.h" + +#define GC2235_NAME "gc2235" + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 0x2 +#define I2C_RETRY_COUNT 5 + +#define GC2235_FOCAL_LENGTH_NUM 278 /*2.78mm*/ +#define GC2235_FOCAL_LENGTH_DEM 100 +#define GC2235_F_NUMBER_DEFAULT_NUM 26 +#define GC2235_F_NUMBER_DEM 10 + +#define MAX_FMTS 1 + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define GC2235_FOCAL_LENGTH_DEFAULT 0x1160064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define GC2235_F_NUMBER_DEFAULT 0x1a000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define GC2235_F_NUMBER_RANGE 0x1a0a1a0a +#define GC2235_ID 0x2235 + +#define GC2235_FINE_INTG_TIME_MIN 0 +#define GC2235_FINE_INTG_TIME_MAX_MARGIN 0 +#define GC2235_COARSE_INTG_TIME_MIN 1 +#define GC2235_COARSE_INTG_TIME_MAX_MARGIN 6 + +/* + * GC2235 System control registers + */ +/* + * GC2235 System control registers + */ +#define GC2235_SENSOR_ID_H 0xF0 +#define GC2235_SENSOR_ID_L 0xF1 +#define GC2235_RESET_RELATED 0xFE +#define GC2235_SW_RESET 0x8 +#define GC2235_MIPI_RESET 0x3 +#define GC2235_RESET_BIT 0x4 +#define GC2235_REGISTER_PAGE_0 0x0 +#define GC2235_REGISTER_PAGE_3 0x3 + +#define GC2235_V_CROP_START_H 0x91 +#define GC2235_V_CROP_START_L 0x92 +#define GC2235_H_CROP_START_H 0x93 +#define GC2235_H_CROP_START_L 0x94 +#define GC2235_V_OUTSIZE_H 0x95 +#define GC2235_V_OUTSIZE_L 0x96 +#define GC2235_H_OUTSIZE_H 0x97 +#define GC2235_H_OUTSIZE_L 0x98 + +#define GC2235_HB_H 0x5 +#define GC2235_HB_L 0x6 +#define GC2235_VB_H 0x7 +#define GC2235_VB_L 0x8 +#define GC2235_SH_DELAY_H 0x11 +#define GC2235_SH_DELAY_L 0x12 + +#define GC2235_CSI2_MODE 0x10 + +#define GC2235_EXPOSURE_H 0x3 +#define GC2235_EXPOSURE_L 0x4 +#define GC2235_GLOBAL_GAIN 0xB0 +#define GC2235_PRE_GAIN 0xB1 +#define GC2235_AWB_R_GAIN 0xB3 +#define GC2235_AWB_G_GAIN 0xB4 +#define GC2235_AWB_B_GAIN 0xB5 + +#define GC2235_START_STREAMING 0x91 +#define GC2235_STOP_STREAMING 0x0 + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct gc2235_resolution { + u8 *desc; + const struct gc2235_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u32 skip_frames; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; +}; + +struct gc2235_format { + u8 *desc; + u32 pixelformat; + struct gc2235_reg *regs; +}; + +/* + * gc2235 device structure. + */ +struct gc2235_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + struct v4l2_ctrl_handler ctrl_handler; + + struct camera_sensor_platform_data *platform_data; + int vt_pix_clk_freq_mhz; + int fmt_idx; + int run_mode; + u8 res; + u8 type; +}; + +enum gc2235_tok_type { + GC2235_8BIT = 0x0001, + GC2235_16BIT = 0x0002, + GC2235_32BIT = 0x0004, + GC2235_TOK_TERM = 0xf000, /* terminating token for reg list */ + GC2235_TOK_DELAY = 0xfe00, /* delay token for reg list */ + GC2235_TOK_MASK = 0xfff0 +}; + +/** + * struct gc2235_reg - MI sensor register format + * @type: type of the register + * @reg: 8-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct gc2235_reg { + enum gc2235_tok_type type; + u8 reg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +#define to_gc2235_sensor(x) container_of(x, struct gc2235_device, sd) + +#define GC2235_MAX_WRITE_BUF_SIZE 30 + +struct gc2235_write_buffer { + u8 addr; + u8 data[GC2235_MAX_WRITE_BUF_SIZE]; +}; + +struct gc2235_write_ctrl { + int index; + struct gc2235_write_buffer buffer; +}; + +static const struct i2c_device_id gc2235_id[] = { + {GC2235_NAME, 0}, + {} +}; + +static struct gc2235_reg const gc2235_stream_on[] = { + { GC2235_8BIT, 0xfe, 0x03}, /* switch to P3 */ + { GC2235_8BIT, 0x10, 0x91}, /* start mipi */ + { GC2235_8BIT, 0xfe, 0x00}, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_stream_off[] = { + { GC2235_8BIT, 0xfe, 0x03}, /* switch to P3 */ + { GC2235_8BIT, 0x10, 0x01}, /* stop mipi */ + { GC2235_8BIT, 0xfe, 0x00}, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_init_settings[] = { + /* Sysytem */ + { GC2235_8BIT, 0xfe, 0x80 }, + { GC2235_8BIT, 0xfe, 0x80 }, + { GC2235_8BIT, 0xfe, 0x80 }, + { GC2235_8BIT, 0xf2, 0x00 }, + { GC2235_8BIT, 0xf6, 0x00 }, + { GC2235_8BIT, 0xfc, 0x06 }, + { GC2235_8BIT, 0xf7, 0x15 }, + { GC2235_8BIT, 0xf8, 0x84 }, + { GC2235_8BIT, 0xf9, 0xfe }, + { GC2235_8BIT, 0xfa, 0x00 }, + { GC2235_8BIT, 0xfe, 0x00 }, + /* Analog & cisctl */ + { GC2235_8BIT, 0x03, 0x04 }, + { GC2235_8BIT, 0x04, 0x9E }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x06, 0xfd }, + { GC2235_8BIT, 0x07, 0x00 }, + { GC2235_8BIT, 0x08, 0x14 }, + { GC2235_8BIT, 0x0a, 0x02 }, /* row start */ + { GC2235_8BIT, 0x0c, 0x00 }, /* col start */ + { GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */ + { GC2235_8BIT, 0x0e, 0xd0 }, + { GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */ + { GC2235_8BIT, 0x10, 0x60 }, + { GC2235_8BIT, 0x17, 0x15 }, /* mirror flip */ + { GC2235_8BIT, 0x18, 0x1a }, + { GC2235_8BIT, 0x19, 0x06 }, + { GC2235_8BIT, 0x1a, 0x01 }, + { GC2235_8BIT, 0x1b, 0x4d }, + { GC2235_8BIT, 0x1e, 0x88 }, + { GC2235_8BIT, 0x1f, 0x48 }, + { GC2235_8BIT, 0x20, 0x03 }, + { GC2235_8BIT, 0x21, 0x7f }, + { GC2235_8BIT, 0x22, 0x83 }, + { GC2235_8BIT, 0x23, 0x42 }, + { GC2235_8BIT, 0x24, 0x16 }, + { GC2235_8BIT, 0x26, 0x01 }, /*analog gain*/ + { GC2235_8BIT, 0x27, 0x30 }, + { GC2235_8BIT, 0x3f, 0x00 }, /* PRC */ + /* blk */ + { GC2235_8BIT, 0x40, 0xa3 }, + { GC2235_8BIT, 0x41, 0x82 }, + { GC2235_8BIT, 0x43, 0x20 }, + { GC2235_8BIT, 0x5e, 0x18 }, + { GC2235_8BIT, 0x5f, 0x18 }, + { GC2235_8BIT, 0x60, 0x18 }, + { GC2235_8BIT, 0x61, 0x18 }, + { GC2235_8BIT, 0x62, 0x18 }, + { GC2235_8BIT, 0x63, 0x18 }, + { GC2235_8BIT, 0x64, 0x18 }, + { GC2235_8BIT, 0x65, 0x18 }, + { GC2235_8BIT, 0x66, 0x20 }, + { GC2235_8BIT, 0x67, 0x20 }, + { GC2235_8BIT, 0x68, 0x20 }, + { GC2235_8BIT, 0x69, 0x20 }, + /* Gain */ + { GC2235_8BIT, 0xb2, 0x00 }, + { GC2235_8BIT, 0xb3, 0x40 }, + { GC2235_8BIT, 0xb4, 0x40 }, + { GC2235_8BIT, 0xb5, 0x40 }, + /* Dark sun */ + { GC2235_8BIT, 0xbc, 0x00 }, + + { GC2235_8BIT, 0xfe, 0x03 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; +/* + * Register settings for various resolution + */ +static struct gc2235_reg const gc2235_1296_736_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x07, 0x01 }, /* VBI */ + { GC2235_8BIT, 0x08, 0x44 }, + { GC2235_8BIT, 0x09, 0x00 }, /* row start */ + { GC2235_8BIT, 0x0a, 0xf0 }, + { GC2235_8BIT, 0x0b, 0x00 }, /* col start */ + { GC2235_8BIT, 0x0c, 0xa0 }, + { GC2235_8BIT, 0x0d, 0x02 }, /* win height 736 */ + { GC2235_8BIT, 0x0e, 0xf0 }, + { GC2235_8BIT, 0x0f, 0x05 }, /* win width: 1296 */ + { GC2235_8BIT, 0x10, 0x20 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x08 }, + { GC2235_8BIT, 0x94, 0x08 }, + { GC2235_8BIT, 0x95, 0x02 }, /* crop win height 736 */ + { GC2235_8BIT, 0x96, 0xe0 }, + { GC2235_8BIT, 0x97, 0x05 }, /* crop win width 1296 */ + { GC2235_8BIT, 0x98, 0x10 }, + /* mimi init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0x54 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x06 }, /* val_high = (width * 10 / 8) >> 8 */ + + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_960_640_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x07, 0x02 }, /* VBI */ + { GC2235_8BIT, 0x08, 0xA4 }, + { GC2235_8BIT, 0x09, 0x01 }, /* row start */ + { GC2235_8BIT, 0x0a, 0x18 }, + { GC2235_8BIT, 0x0b, 0x01 }, /* col start */ + { GC2235_8BIT, 0x0c, 0x40 }, + { GC2235_8BIT, 0x0d, 0x02 }, /* win height 656 */ + { GC2235_8BIT, 0x0e, 0x90 }, + { GC2235_8BIT, 0x0f, 0x03 }, /* win width: 976 */ + { GC2235_8BIT, 0x10, 0xd0 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x02 }, + { GC2235_8BIT, 0x94, 0x06 }, + { GC2235_8BIT, 0x95, 0x02 }, /* crop win height 640 */ + { GC2235_8BIT, 0x96, 0x80 }, + { GC2235_8BIT, 0x97, 0x03 }, /* crop win width 960 */ + { GC2235_8BIT, 0x98, 0xc0 }, + /* mimp init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0xb0 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x04 }, /* val_high = (width * 10 / 8) >> 8 */ + + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_1600_900_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x0d, 0x03 }, /* win height 932 */ + { GC2235_8BIT, 0x0e, 0xa4 }, + { GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1632 */ + { GC2235_8BIT, 0x10, 0x50 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x02 }, + { GC2235_8BIT, 0x94, 0x06 }, + { GC2235_8BIT, 0x95, 0x03 }, /* crop win height 900 */ + { GC2235_8BIT, 0x96, 0x84 }, + { GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1600 */ + { GC2235_8BIT, 0x98, 0x40 }, + /* mimi init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0xd0 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */ + + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_1616_1082_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */ + { GC2235_8BIT, 0x0e, 0xd0 }, + { GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */ + { GC2235_8BIT, 0x10, 0x50 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x4a }, + { GC2235_8BIT, 0x94, 0x00 }, + { GC2235_8BIT, 0x95, 0x04 }, /* crop win height 1082 */ + { GC2235_8BIT, 0x96, 0x3a }, + { GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1616 */ + { GC2235_8BIT, 0x98, 0x50 }, + /* mimp init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0xe4 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */ + + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_1616_1216_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */ + { GC2235_8BIT, 0x0e, 0xd0 }, + { GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */ + { GC2235_8BIT, 0x10, 0x50 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x02 }, + { GC2235_8BIT, 0x94, 0x00 }, + { GC2235_8BIT, 0x95, 0x04 }, /* crop win height 1216 */ + { GC2235_8BIT, 0x96, 0xc0 }, + { GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1616 */ + { GC2235_8BIT, 0x98, 0x50 }, + /* mimi init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0xe4 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */ + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +struct gc2235_resolution gc2235_res_preview[] = { + + { + .desc = "gc2235_1600_900_30fps", + .width = 1600, + .height = 900, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1068, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1600_900_30fps, + }, + + { + .desc = "gc2235_1600_1066_30fps", + .width = 1616, + .height = 1082, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1368, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1616_1082_30fps, + }, + { + .desc = "gc2235_1600_1200_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1368, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1616_1216_30fps, + }, + +}; +#define N_RES_PREVIEW (ARRAY_SIZE(gc2235_res_preview)) + +struct gc2235_resolution gc2235_res_still[] = { + { + .desc = "gc2235_1600_900_30fps", + .width = 1600, + .height = 900, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1068, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1600_900_30fps, + }, + { + .desc = "gc2235_1600_1066_30fps", + .width = 1616, + .height = 1082, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1368, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1616_1082_30fps, + }, + { + .desc = "gc2235_1600_1200_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1368, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1616_1216_30fps, + }, + +}; +#define N_RES_STILL (ARRAY_SIZE(gc2235_res_still)) + +struct gc2235_resolution gc2235_res_video[] = { + { + .desc = "gc2235_1296_736_30fps", + .width = 1296, + .height = 736, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 1828, + .lines_per_frame = 888, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1296_736_30fps, + }, + { + .desc = "gc2235_960_640_30fps", + .width = 960, + .height = 640, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 1492, + .lines_per_frame = 792, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_960_640_30fps, + }, + +}; +#define N_RES_VIDEO (ARRAY_SIZE(gc2235_res_video)) + +static struct gc2235_resolution *gc2235_res = gc2235_res_preview; +static int N_RES = N_RES_PREVIEW; +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/Kconfig b/drivers/staging/media/atomisp/i2c/imx/Kconfig new file mode 100644 index 0000000..a39eeb3 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/Kconfig @@ -0,0 +1,9 @@ +config VIDEO_IMX + tristate "sony imx sensor support" + depends on I2C && VIDEO_V4L2 && VIDEO_MSRLIST_HELPER && m + ---help--- + This is a Video4Linux2 sensor-level driver for the Sony + IMX RAW sensor. + + It currently depends on internal V4L2 extensions defined in + atomisp driver. diff --git a/drivers/staging/media/atomisp/i2c/imx/Makefile b/drivers/staging/media/atomisp/i2c/imx/Makefile new file mode 100644 index 0000000..1d7f7ab --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/Makefile @@ -0,0 +1,8 @@ +obj-$(CONFIG_VIDEO_IMX) += imx1x5.o + +imx1x5-objs := imx.o drv201.o ad5816g.o dw9714.o dw9719.o dw9718.o vcm.o otp.o otp_imx.o otp_brcc064_e2prom.o otp_e2prom.o + +ov8858_driver-objs := ../ov8858.o dw9718.o vcm.o +obj-$(CONFIG_VIDEO_OV8858) += ov8858_driver.o + +ccflags-y += -Werror diff --git a/drivers/staging/media/atomisp/i2c/imx/ad5816g.c b/drivers/staging/media/atomisp/i2c/imx/ad5816g.c new file mode 100644 index 0000000..d68ebb4 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/ad5816g.c @@ -0,0 +1,225 @@ +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/kmod.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/types.h> +#include <media/v4l2-device.h> + +#include "ad5816g.h" + +struct ad5816g_device ad5816g_dev; + +static int ad5816g_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2]; + buf[0] = reg; + buf[1] = 0; + + msg[0].addr = AD5816G_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &buf[0]; + + msg[1].addr = AD5816G_VCM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf[1]; + *val = 0; + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + return 0; +} + +static int ad5816g_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2]; + buf[0] = reg; + buf[1] = val; + msg.addr = AD5816G_VCM_ADDR; + msg.flags = 0; + msg.len = 2; + msg.buf = &buf[0]; + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +static int ad5816g_i2c_wr16(struct i2c_client *client, u8 reg, u16 val) +{ + struct i2c_msg msg; + u8 buf[3]; + buf[0] = reg; + buf[1] = (u8)(val >> 8); + buf[2] = (u8)(val & 0xff); + msg.addr = AD5816G_VCM_ADDR; + msg.flags = 0; + msg.len = 3; + msg.buf = &buf[0]; + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +static int ad5816g_set_arc_mode(struct i2c_client *client) +{ + int ret; + + ret = ad5816g_i2c_wr8(client, AD5816G_CONTROL, AD5816G_ARC_EN); + if (ret) + return ret; + + ret = ad5816g_i2c_wr8(client, AD5816G_MODE, + AD5816G_MODE_2_5M_SWITCH_CLOCK); + if (ret) + return ret; + + ret = ad5816g_i2c_wr8(client, AD5816G_VCM_FREQ, AD5816G_DEF_FREQ); + return ret; +} + +int ad5816g_vcm_power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 ad5816g_id; + + /* Enable power */ + ret = ad5816g_dev.platform_data->power_ctrl(sd, 1); + if (ret) + return ret; + /* waiting time AD5816G(vcm) - t1 + t2 + * t1(1ms) -Time from VDD high to first i2c cmd + * t2(100us) - exit power-down mode time + */ + usleep_range(1100, 2200); + /* Detect device */ + ret = ad5816g_i2c_rd8(client, AD5816G_IC_INFO, &ad5816g_id); + if (ret < 0) + goto fail_powerdown; + if (ad5816g_id != AD5816G_ID) { + ret = -ENXIO; + goto fail_powerdown; + } + ret = ad5816g_set_arc_mode(client); + if (ret) + return ret; + + /* set the VCM_THRESHOLD */ + ret = ad5816g_i2c_wr8(client, AD5816G_VCM_THRESHOLD, + AD5816G_DEF_THRESHOLD); + + return ret; + +fail_powerdown: + ad5816g_dev.platform_data->power_ctrl(sd, 0); + return ret; +} + +int ad5816g_vcm_power_down(struct v4l2_subdev *sd) +{ + return ad5816g_dev.platform_data->power_ctrl(sd, 0); +} + + +int ad5816g_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 data = val & VCM_CODE_MASK; + + return ad5816g_i2c_wr16(client, AD5816G_VCM_CODE_MSB, data); +} + +int ad5816g_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + int ret; + + value = clamp(value, 0, AD5816G_MAX_FOCUS_POS); + ret = ad5816g_t_focus_vcm(sd, value); + if (ret == 0) { + ad5816g_dev.number_of_steps = value - ad5816g_dev.focus; + ad5816g_dev.focus = value; + getnstimeofday(&(ad5816g_dev.timestamp_t_focus_abs)); + } + + return ret; +} + +int ad5816g_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + + return ad5816g_t_focus_abs(sd, ad5816g_dev.focus + value); +} + +int ad5816g_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + u32 status = 0; + struct timespec temptime; + const struct timespec timedelay = { + 0, + min_t(u32, abs(ad5816g_dev.number_of_steps) * DELAY_PER_STEP_NS, + DELAY_MAX_PER_STEP_NS), + }; + + ktime_get_ts(&temptime); + + temptime = timespec_sub(temptime, (ad5816g_dev.timestamp_t_focus_abs)); + + if (timespec_compare(&temptime, &timedelay) <= 0) { + status |= ATOMISP_FOCUS_STATUS_MOVING; + status |= ATOMISP_FOCUS_HP_IN_PROGRESS; + } else { + status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + status |= ATOMISP_FOCUS_HP_COMPLETE; + } + *value = status; + + return 0; +} + +int ad5816g_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + s32 val; + + ad5816g_q_focus_status(sd, &val); + + if (val & ATOMISP_FOCUS_STATUS_MOVING) + *value = ad5816g_dev.focus - ad5816g_dev.number_of_steps; + else + *value = ad5816g_dev.focus; + + return 0; +} + +int ad5816g_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int ad5816g_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int ad5816g_vcm_init(struct v4l2_subdev *sd) +{ + ad5816g_dev.platform_data = camera_get_af_platform_data(); + return (NULL == ad5816g_dev.platform_data) ? -ENODEV : 0; + +} + + diff --git a/drivers/staging/media/atomisp/i2c/imx/ad5816g.h b/drivers/staging/media/atomisp/i2c/imx/ad5816g.h new file mode 100644 index 0000000..f995c2e --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/ad5816g.h @@ -0,0 +1,49 @@ +#ifndef __AD5816G_H__ +#define __AD5816G_H__ + +#include "../../include/linux/atomisp_platform.h" +#include <linux/types.h> +#include <linux/time.h> + +#define AD5816G_VCM_ADDR 0x0e + +/* ad5816g device structure */ +struct ad5816g_device { + const struct camera_af_platform_data *platform_data; + struct timespec timestamp_t_focus_abs; + struct timespec focus_time; /* Time when focus was last time set */ + s32 focus; /* Current focus value */ + s16 number_of_steps; +}; + +#define AD5816G_INVALID_CONFIG 0xffffffff +#define AD5816G_MAX_FOCUS_POS 1023 +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) + +/* Register Definitions */ +#define AD5816G_IC_INFO 0x00 +#define AD5816G_IC_VERSION 0x01 +#define AD5816G_CONTROL 0x02 +#define AD5816G_VCM_CODE_MSB 0x03 +#define AD5816G_VCM_CODE_LSB 0x04 +#define AD5816G_STATUS 0x05 +#define AD5816G_MODE 0x06 +#define AD5816G_VCM_FREQ 0x07 +#define AD5816G_VCM_THRESHOLD 0x08 + +/* ARC MODE ENABLE */ +#define AD5816G_ARC_EN 0x02 +/* ARC RES2 MODE */ +#define AD5816G_ARC_RES2 0x01 +/* ARC VCM FREQ - 78.1Hz */ +#define AD5816G_DEF_FREQ 0x7a +/* ARC VCM THRESHOLD - 0x08 << 1 */ +#define AD5816G_DEF_THRESHOLD 0x64 +#define AD5816G_ID 0x24 +#define VCM_CODE_MASK 0x03ff + +#define AD5816G_MODE_2_5M_SWITCH_CLOCK 0x14 + +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/common.h b/drivers/staging/media/atomisp/i2c/imx/common.h new file mode 100644 index 0000000..7e525ce --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/common.h @@ -0,0 +1,65 @@ +#ifndef __COMMON_H__ +#define __COMMON_H__ + +#define MAX_FPS_OPTIONS_SUPPORTED 3 +#define I2C_MSG_LENGTH 0x2 +#define E2PROM_2ADDR 0x80000000 +#define E2PROM_ADDR_MASK 0x7fffffff + +/* Defines for register writes and register array processing */ +#define IMX_BYTE_MAX 32 +#define IMX_SHORT_MAX 16 +#define I2C_RETRY_COUNT 5 +#define IMX_TOK_MASK 0xfff0 + +enum imx_tok_type { + IMX_8BIT = 0x0001, + IMX_16BIT = 0x0002, + IMX_TOK_TERM = 0xf000, /* terminating token for reg list */ + IMX_TOK_DELAY = 0xfe00 /* delay token for reg list */ +}; + +/** + * struct imx_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct imx_reg { + enum imx_tok_type type; + u16 sreg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +struct imx_fps_setting { + int fps; + unsigned short pixels_per_line; + unsigned short lines_per_frame; + int mipi_freq; /* MIPI lane frequency in kHz */ + const struct imx_reg *regs; /* regs that the fps setting needs */ +}; + +struct imx_resolution { + const struct imx_fps_setting fps_options[MAX_FPS_OPTIONS_SUPPORTED]; + u8 *desc; + const struct imx_reg *regs; + int res; + int width; + int height; + int fps; + unsigned short pixels_per_line; + unsigned short lines_per_frame; + int mipi_freq; /* MIPI lane frequency in kHz */ + unsigned short skip_frames; + u8 bin_factor_x; + u8 bin_factor_y; + bool used; +}; + +#define GROUPED_PARAMETER_HOLD_ENABLE {IMX_8BIT, 0x0104, 0x1} +#define GROUPED_PARAMETER_HOLD_DISABLE {IMX_8BIT, 0x0104, 0x0} + +int imx_write_reg(struct i2c_client *client, u16 data_length, u16 reg, u16 val); +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/drv201.c b/drivers/staging/media/atomisp/i2c/imx/drv201.c new file mode 100644 index 0000000..915e401 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/drv201.c @@ -0,0 +1,218 @@ +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/kmod.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/types.h> +#include <media/v4l2-device.h> +#include <asm/intel-mid.h> + +#include "drv201.h" + +static struct drv201_device drv201_dev; + +static int drv201_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2]; + buf[0] = reg; + buf[1] = 0; + + msg[0].addr = DRV201_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &buf[0]; + + msg[1].addr = DRV201_VCM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf[1]; + *val = 0; + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + return 0; +} + +static int drv201_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2]; + buf[0] = reg; + buf[1] = val; + msg.addr = DRV201_VCM_ADDR; + msg.flags = 0; + msg.len = 2; + msg.buf = &buf[0]; + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +static int drv201_i2c_wr16(struct i2c_client *client, u8 reg, u16 val) +{ + struct i2c_msg msg; + u8 buf[3]; + buf[0] = reg; + buf[1] = (u8)(val >> 8); + buf[2] = (u8)(val & 0xff); + msg.addr = DRV201_VCM_ADDR; + msg.flags = 0; + msg.len = 3; + msg.buf = &buf[0]; + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +int drv201_vcm_power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 value; + + /* Enable power */ + ret = drv201_dev.platform_data->power_ctrl(sd, 1); + if (ret) + return ret; + /* Wait for VBAT to stabilize */ + udelay(1); + /* + * Jiggle SCL pin to wake up device. + * Drv201 expect SCL from low to high to wake device up. + * So the 1st access to i2c would fail. + * Using following function to wake device up. + */ + drv201_i2c_wr8(client, DRV201_CONTROL, DRV201_RESET); + + /* Need 100us to transit from SHUTDOWN to STANDBY*/ + usleep_range(WAKEUP_DELAY_US, WAKEUP_DELAY_US * 10); + + /* Reset device */ + ret = drv201_i2c_wr8(client, DRV201_CONTROL, DRV201_RESET); + if (ret < 0) + goto fail_powerdown; + + /* Detect device */ + ret = drv201_i2c_rd8(client, DRV201_CONTROL, &value); + if (ret < 0) + goto fail_powerdown; + if (value != DEFAULT_CONTROL_VAL) { + ret = -ENXIO; + goto fail_powerdown; + } + + drv201_dev.focus = DRV201_MAX_FOCUS_POS; + drv201_dev.initialized = true; + + return 0; +fail_powerdown: + drv201_dev.platform_data->power_ctrl(sd, 0); + return ret; +} + +int drv201_vcm_power_down(struct v4l2_subdev *sd) +{ + return drv201_dev.platform_data->power_ctrl(sd, 0); +} + + +int drv201_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 data = val & VCM_CODE_MASK; + + if (!drv201_dev.initialized) + return -ENODEV; + return drv201_i2c_wr16(client, DRV201_VCM_CURRENT, data); +} + +int drv201_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + int ret; + + value = clamp(value, 0, DRV201_MAX_FOCUS_POS); + ret = drv201_t_focus_vcm(sd, value); + if (ret == 0) { + drv201_dev.number_of_steps = value - drv201_dev.focus; + drv201_dev.focus = value; + getnstimeofday(&(drv201_dev.timestamp_t_focus_abs)); + } + + return ret; +} + +int drv201_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + return drv201_t_focus_abs(sd, drv201_dev.focus + value); +} + +int drv201_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + u32 status = 0; + struct timespec temptime; + const struct timespec timedelay = { + 0, + min_t(u32, abs(drv201_dev.number_of_steps)*DELAY_PER_STEP_NS, + DELAY_MAX_PER_STEP_NS), + }; + + ktime_get_ts(&temptime); + + temptime = timespec_sub(temptime, (drv201_dev.timestamp_t_focus_abs)); + + if (timespec_compare(&temptime, &timedelay) <= 0) { + status |= ATOMISP_FOCUS_STATUS_MOVING; + status |= ATOMISP_FOCUS_HP_IN_PROGRESS; + } else { + status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + status |= ATOMISP_FOCUS_HP_COMPLETE; + } + *value = status; + + return 0; +} + +int drv201_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + s32 val; + + drv201_q_focus_status(sd, &val); + + if (val & ATOMISP_FOCUS_STATUS_MOVING) + *value = drv201_dev.focus - drv201_dev.number_of_steps; + else + *value = drv201_dev.focus; + + return 0; +} + +int drv201_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int drv201_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int drv201_vcm_init(struct v4l2_subdev *sd) +{ + drv201_dev.platform_data = camera_get_af_platform_data(); + return (NULL == drv201_dev.platform_data) ? -ENODEV : 0; +} + + + diff --git a/drivers/staging/media/atomisp/i2c/imx/drv201.h b/drivers/staging/media/atomisp/i2c/imx/drv201.h new file mode 100644 index 0000000..8fc0ad1 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/drv201.h @@ -0,0 +1,38 @@ +#ifndef __DRV201_H__ +#define __DRV201_H__ + +#include "../../include/linux/atomisp_platform.h" +#include <linux/types.h> +#include <linux/time.h> + +#define DRV201_VCM_ADDR 0x0e + +/* drv201 device structure */ +struct drv201_device { + const struct camera_af_platform_data *platform_data; + struct timespec timestamp_t_focus_abs; + struct timespec focus_time; /* Time when focus was last time set */ + s32 focus; /* Current focus value */ + s16 number_of_steps; + bool initialized; /* true if drv201 is detected */ +}; + +#define DRV201_INVALID_CONFIG 0xffffffff +#define DRV201_MAX_FOCUS_POS 1023 +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) + +#define DRV201_CONTROL 2 +#define DRV201_VCM_CURRENT 3 +#define DRV201_STATUS 5 +#define DRV201_MODE 6 +#define DRV201_VCM_FREQ 7 + +#define DEFAULT_CONTROL_VAL 2 +#define DRV201_RESET 1 +#define WAKEUP_DELAY_US 100 +#define VCM_CODE_MASK 0x03ff + +#endif + + diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9714.c b/drivers/staging/media/atomisp/i2c/imx/dw9714.c new file mode 100644 index 0000000..b7dee1b --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9714.c @@ -0,0 +1,235 @@ +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/kmod.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/types.h> +#include <media/v4l2-device.h> +#include <asm/intel-mid.h> + +#include "dw9714.h" + +static struct dw9714_device dw9714_dev; +static int dw9714_i2c_write(struct i2c_client *client, u16 data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + u16 val; + + val = cpu_to_be16(data); + msg.addr = DW9714_VCM_ADDR; + msg.flags = 0; + msg.len = DW9714_16BIT; + msg.buf = (u8 *)&val; + + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +int dw9714_vcm_power_up(struct v4l2_subdev *sd) +{ + int ret; + + /* Enable power */ + ret = dw9714_dev.platform_data->power_ctrl(sd, 1); + /* waiting time requested by DW9714A(vcm) */ + usleep_range(12000, 12500); + return ret; +} + +int dw9714_vcm_power_down(struct v4l2_subdev *sd) +{ + return dw9714_dev.platform_data->power_ctrl(sd, 0); +} + + +int dw9714_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = -EINVAL; + u8 mclk = vcm_step_mclk(dw9714_dev.vcm_settings.step_setting); + u8 s = vcm_step_s(dw9714_dev.vcm_settings.step_setting); + + /* + * For different mode, VCM_PROTECTION_OFF/ON required by the + * control procedure. For DW9714_DIRECT/DLC mode, slew value is + * VCM_DEFAULT_S(0). + */ + switch (dw9714_dev.vcm_mode) { + case DW9714_DIRECT: + if (dw9714_dev.vcm_settings.update) { + ret = dw9714_i2c_write(client, VCM_PROTECTION_OFF); + if (ret) + return ret; + ret = dw9714_i2c_write(client, DIRECT_VCM); + if (ret) + return ret; + ret = dw9714_i2c_write(client, VCM_PROTECTION_ON); + if (ret) + return ret; + dw9714_dev.vcm_settings.update = false; + } + ret = dw9714_i2c_write(client, + vcm_val(val, VCM_DEFAULT_S)); + break; + case DW9714_LSC: + if (dw9714_dev.vcm_settings.update) { + ret = dw9714_i2c_write(client, VCM_PROTECTION_OFF); + if (ret) + return ret; + ret = dw9714_i2c_write(client, + vcm_dlc_mclk(DLC_DISABLE, mclk)); + if (ret) + return ret; + ret = dw9714_i2c_write(client, + vcm_tsrc(dw9714_dev.vcm_settings.t_src)); + if (ret) + return ret; + ret = dw9714_i2c_write(client, VCM_PROTECTION_ON); + if (ret) + return ret; + dw9714_dev.vcm_settings.update = false; + } + ret = dw9714_i2c_write(client, vcm_val(val, s)); + break; + case DW9714_DLC: + if (dw9714_dev.vcm_settings.update) { + ret = dw9714_i2c_write(client, VCM_PROTECTION_OFF); + if (ret) + return ret; + ret = dw9714_i2c_write(client, + vcm_dlc_mclk(DLC_ENABLE, mclk)); + if (ret) + return ret; + ret = dw9714_i2c_write(client, + vcm_tsrc(dw9714_dev.vcm_settings.t_src)); + if (ret) + return ret; + ret = dw9714_i2c_write(client, VCM_PROTECTION_ON); + if (ret) + return ret; + dw9714_dev.vcm_settings.update = false; + } + ret = dw9714_i2c_write(client, + vcm_val(val, VCM_DEFAULT_S)); + break; + } + return ret; +} + +int dw9714_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + int ret; + + value = clamp(value, 0, DW9714_MAX_FOCUS_POS); + ret = dw9714_t_focus_vcm(sd, value); + if (ret == 0) { + dw9714_dev.number_of_steps = value - dw9714_dev.focus; + dw9714_dev.focus = value; + getnstimeofday(&(dw9714_dev.timestamp_t_focus_abs)); + } + + return ret; +} + +int dw9714_t_focus_abs_init(struct v4l2_subdev *sd) +{ + int ret; + + ret = dw9714_t_focus_vcm(sd, DW9714_DEFAULT_FOCUS_POS); + if (ret == 0) { + dw9714_dev.number_of_steps = + DW9714_DEFAULT_FOCUS_POS - dw9714_dev.focus; + dw9714_dev.focus = DW9714_DEFAULT_FOCUS_POS; + getnstimeofday(&(dw9714_dev.timestamp_t_focus_abs)); + } + + return ret; +} + +int dw9714_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + + return dw9714_t_focus_abs(sd, dw9714_dev.focus + value); +} + +int dw9714_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + u32 status = 0; + struct timespec temptime; + const struct timespec timedelay = { + 0, + min_t(u32, abs(dw9714_dev.number_of_steps)*DELAY_PER_STEP_NS, + DELAY_MAX_PER_STEP_NS), + }; + + ktime_get_ts(&temptime); + + temptime = timespec_sub(temptime, (dw9714_dev.timestamp_t_focus_abs)); + + if (timespec_compare(&temptime, &timedelay) <= 0) { + status |= ATOMISP_FOCUS_STATUS_MOVING; + status |= ATOMISP_FOCUS_HP_IN_PROGRESS; + } else { + status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + status |= ATOMISP_FOCUS_HP_COMPLETE; + } + *value = status; + + return 0; +} + +int dw9714_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + s32 val; + + dw9714_q_focus_status(sd, &val); + + if (val & ATOMISP_FOCUS_STATUS_MOVING) + *value = dw9714_dev.focus - dw9714_dev.number_of_steps; + else + *value = dw9714_dev.focus; + + return 0; +} + +int dw9714_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + dw9714_dev.vcm_settings.step_setting = value; + dw9714_dev.vcm_settings.update = true; + + return 0; +} + +int dw9714_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + dw9714_dev.vcm_settings.t_src = value; + dw9714_dev.vcm_settings.update = true; + + return 0; +} + +int dw9714_vcm_init(struct v4l2_subdev *sd) +{ + + /* set VCM to home position and vcm mode to direct*/ + dw9714_dev.vcm_mode = DW9714_DIRECT; + dw9714_dev.vcm_settings.update = false; + dw9714_dev.platform_data = camera_get_af_platform_data(); + return (NULL == dw9714_dev.platform_data) ? -ENODEV : 0; + +} + diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9714.h b/drivers/staging/media/atomisp/i2c/imx/dw9714.h new file mode 100644 index 0000000..5a98a9c --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9714.h @@ -0,0 +1,63 @@ +#ifndef __DW9714_H__ +#define __DW9714_H__ + +#include "../../include/linux/atomisp_platform.h" +#include <linux/types.h> + + +#define DW9714_VCM_ADDR 0x0c + +enum dw9714_tok_type { + DW9714_8BIT = 0x0001, + DW9714_16BIT = 0x0002, +}; + +struct dw9714_vcm_settings { + u16 code; /* bit[9:0]: Data[9:0] */ + u8 t_src; /* bit[4:0]: T_SRC[4:0] */ + u8 step_setting; /* bit[3:0]: S[3:0]/bit[5:4]: MCLK[1:0] */ + bool update; +}; + +enum dw9714_vcm_mode { + DW9714_DIRECT = 0x1, /* direct control */ + DW9714_LSC = 0x2, /* linear slope control */ + DW9714_DLC = 0x3, /* dual level control */ +}; + +/* dw9714 device structure */ +struct dw9714_device { + struct dw9714_vcm_settings vcm_settings; + struct timespec timestamp_t_focus_abs; + enum dw9714_vcm_mode vcm_mode; + s16 number_of_steps; + bool initialized; /* true if dw9714 is detected */ + s32 focus; /* Current focus value */ + struct timespec focus_time; /* Time when focus was last time set */ + __u8 buffer[4]; /* Used for i2c transactions */ + const struct camera_af_platform_data *platform_data; +}; + +#define DW9714_INVALID_CONFIG 0xffffffff +#define DW9714_MAX_FOCUS_POS 1023 +#define DW9714_DEFAULT_FOCUS_POS 290 + + +/* MCLK[1:0] = 01 T_SRC[4:0] = 00001 S[3:0] = 0111 */ +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) + +#define DLC_ENABLE 1 +#define DLC_DISABLE 0 +#define VCM_PROTECTION_OFF 0xeca3 +#define VCM_PROTECTION_ON 0xdc51 +#define VCM_DEFAULT_S 0x0 + +#define vcm_step_s(a) (u8)(a & 0xf) +#define vcm_step_mclk(a) (u8)((a >> 4) & 0x3) +#define vcm_dlc_mclk(dlc, mclk) (u16)((dlc << 3) | mclk | 0xa104) +#define vcm_tsrc(tsrc) (u16)(tsrc << 3 | 0xf200) +#define vcm_val(data, s) (u16)(data << 4 | s) +#define DIRECT_VCM vcm_dlc_mclk(0, 0) + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9718.c b/drivers/staging/media/atomisp/i2c/imx/dw9718.c new file mode 100644 index 0000000..65a1fcf --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9718.c @@ -0,0 +1,238 @@ +/* + * Support for dw9718 vcm driver. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include <linux/delay.h> +#include "dw9718.h" + +static struct dw9718_device dw9718_dev; + +static int dw9718_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2] = { reg }; + + msg[0].addr = DW9718_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = buf; + + msg[1].addr = DW9718_VCM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf[1]; + *val = 0; + + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + + return 0; +} + +static int dw9718_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2] = { reg, val}; + + msg.addr = DW9718_VCM_ADDR; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + + return 0; +} + +static int dw9718_i2c_wr16(struct i2c_client *client, u8 reg, u16 val) +{ + struct i2c_msg msg; + u8 buf[3] = { reg, (u8)(val >> 8), (u8)(val & 0xff)}; + + msg.addr = DW9718_VCM_ADDR; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + + return 0; +} + +int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + value = clamp(value, 0, DW9718_MAX_FOCUS_POS); + ret = dw9718_i2c_wr16(client, DW9718_DATA_M, value); + /*pr_info("%s: value = %d\n", __func__, value);*/ + if (ret < 0) + return ret; + + getnstimeofday(&dw9718_dev.focus_time); + dw9718_dev.focus = value; + + return 0; +} + +int dw9718_vcm_power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 value; + + if (dw9718_dev.power_on) + return 0; + + /* Enable power */ + ret = dw9718_dev.platform_data->power_ctrl(sd, 1); + if (ret) { + dev_err(&client->dev, "DW9718_PD power_ctrl failed %d\n", ret); + return ret; + } + /* Wait for VBAT to stabilize */ + udelay(100); + + /* Detect device */ + ret = dw9718_i2c_rd8(client, DW9718_SACT, &value); + if (ret < 0) { + dev_err(&client->dev, "read DW9718_SACT failed %d\n", ret); + goto fail_powerdown; + } + /* + * WORKAROUND: for module P8V12F-203 which are used on + * Cherrytrail Refresh Davis Reef AoB, register SACT is not + * returning default value as spec. But VCM works as expected and + * root cause is still under discussion with vendor. + * workaround here to avoid aborting the power up sequence and just + * give a warning about this error. + */ + if (value != DW9718_SACT_DEFAULT_VAL) + dev_warn(&client->dev, "%s error, incorrect ID\n", __func__); + + /* Initialize according to recommended settings */ + ret = dw9718_i2c_wr8(client, DW9718_CONTROL, + DW9718_CONTROL_SW_LINEAR | + DW9718_CONTROL_S_SAC4 | + DW9718_CONTROL_OCP_DISABLE | + DW9718_CONTROL_UVLO_DISABLE); + if (ret < 0) { + dev_err(&client->dev, "write DW9718_CONTROL failed %d\n", ret); + goto fail_powerdown; + } + ret = dw9718_i2c_wr8(client, DW9718_SACT, + DW9718_SACT_MULT_TWO | + DW9718_SACT_PERIOD_8_8MS); + if (ret < 0) { + dev_err(&client->dev, "write DW9718_SACT failed %d\n", ret); + goto fail_powerdown; + } + + ret = dw9718_t_focus_abs(sd, dw9718_dev.focus); + if (ret) + return ret; + dw9718_dev.initialized = true; + dw9718_dev.power_on = 1; + + return 0; + +fail_powerdown: + dev_err(&client->dev, "%s error, powerup failed\n", __func__); + dw9718_dev.platform_data->power_ctrl(sd, 0); + return ret; +} + +int dw9718_vcm_power_down(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!dw9718_dev.power_on) + return 0; + + ret = dw9718_dev.platform_data->power_ctrl(sd, 0); + if (ret) { + dev_err(&client->dev, "%s power_ctrl failed\n", + __func__); + return ret; + } + dw9718_dev.power_on = 0; + + return 0; +} + +int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + static const struct timespec move_time = { + .tv_sec = 0, + .tv_nsec = 60000000 + }; + struct timespec current_time, finish_time, delta_time; + + getnstimeofday(¤t_time); + finish_time = timespec_add(dw9718_dev.focus_time, move_time); + delta_time = timespec_sub(current_time, finish_time); + if (delta_time.tv_sec >= 0 && delta_time.tv_nsec >= 0) { + *value = ATOMISP_FOCUS_HP_COMPLETE | + ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + } else { + *value = ATOMISP_FOCUS_STATUS_MOVING | + ATOMISP_FOCUS_HP_IN_PROGRESS; + } + + return 0; +} + +int dw9718_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + return -EINVAL; +} + +int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + return dw9718_t_focus_abs(sd, dw9718_dev.focus + value); +} + +int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + *value = dw9718_dev.focus; + return 0; +} +int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int dw9718_vcm_init(struct v4l2_subdev *sd) +{ + dw9718_dev.platform_data = camera_get_af_platform_data(); + dw9718_dev.focus = DW9718_DEFAULT_FOCUS_POSITION; + dw9718_dev.power_on = 0; + return (NULL == dw9718_dev.platform_data) ? -ENODEV : 0; +} diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9718.h b/drivers/staging/media/atomisp/i2c/imx/dw9718.h new file mode 100644 index 0000000..4a1040c --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9718.h @@ -0,0 +1,64 @@ +/* + * Support for dw9719 vcm driver. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __DW9718_H__ +#define __DW9718_H__ + +#include "../../include/linux/atomisp_platform.h" +#include <linux/types.h> + +#define DW9718_VCM_ADDR (0x18 >> 1) + +/* dw9718 device structure */ +struct dw9718_device { + struct timespec timestamp_t_focus_abs; + s16 number_of_steps; + bool initialized; /* true if dw9718 is detected */ + s32 focus; /* Current focus value */ + struct timespec focus_time; /* Time when focus was last time set */ + __u8 buffer[4]; /* Used for i2c transactions */ + const struct camera_af_platform_data *platform_data; + __u8 power_on; +}; + +#define DW9718_MAX_FOCUS_POS 1023 + +/* Register addresses */ +#define DW9718_PD 0x00 +#define DW9718_CONTROL 0x01 +#define DW9718_DATA_M 0x02 +#define DW9718_DATA_L 0x03 +#define DW9718_SW 0x04 +#define DW9718_SACT 0x05 +#define DW9718_FLAG 0x10 + +#define DW9718_CONTROL_SW_LINEAR BIT(0) +#define DW9718_CONTROL_S_SAC4 (BIT(1) | BIT(3)) +#define DW9718_CONTROL_OCP_DISABLE BIT(4) +#define DW9718_CONTROL_UVLO_DISABLE BIT(5) + +#define DW9718_SACT_MULT_TWO 0x00 +#define DW9718_SACT_PERIOD_8_8MS 0x19 +#define DW9718_SACT_DEFAULT_VAL 0x60 + +#define DW9718_DEFAULT_FOCUS_POSITION 300 + +#endif /* __DW9718_H__ */ diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9719.c b/drivers/staging/media/atomisp/i2c/imx/dw9719.c new file mode 100644 index 0000000..eca2d76 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9719.c @@ -0,0 +1,209 @@ +/* + * Support for dw9719 vcm driver. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include <linux/delay.h> +#include "dw9719.h" + +static struct dw9719_device dw9719_dev; + +static int dw9719_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2] = { reg }; + + msg[0].addr = DW9719_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = buf; + + msg[1].addr = DW9719_VCM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf[1]; + *val = 0; + + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + + return 0; +} + +static int dw9719_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2] = { reg, val }; + + msg.addr = DW9719_VCM_ADDR; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + + return 0; +} + +static int dw9719_i2c_wr16(struct i2c_client *client, u8 reg, u16 val) +{ + struct i2c_msg msg; + u8 buf[3] = { reg, (u8)(val >> 8), (u8)(val & 0xff)}; + + msg.addr = DW9719_VCM_ADDR; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + + return 0; +} + +int dw9719_vcm_power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 value; + + /* Enable power */ + ret = dw9719_dev.platform_data->power_ctrl(sd, 1); + /* waiting time requested by DW9714A(vcm) */ + if (ret) + return ret; + /* Wait for VBAT to stabilize */ + udelay(1); + + /* + * Jiggle SCL pin to wake up device. + */ + ret = dw9719_i2c_wr8(client, DW9719_CONTROL, 1); + /* Need 100us to transit from SHUTDOWN to STANDBY*/ + usleep_range(100, 1000); + + /* Enable the ringing compensation */ + ret = dw9719_i2c_wr8(client, DW9719_CONTROL, DW9719_ENABLE_RINGING); + if (ret < 0) + goto fail_powerdown; + + /* Use SAC3 mode */ + ret = dw9719_i2c_wr8(client, DW9719_MODE, DW9719_MODE_SAC3); + if (ret < 0) + goto fail_powerdown; + + /* Set the resonance frequency */ + ret = dw9719_i2c_wr8(client, DW9719_VCM_FREQ, DW9719_DEFAULT_VCM_FREQ); + if (ret < 0) + goto fail_powerdown; + + /* Detect device */ + ret = dw9719_i2c_rd8(client, DW9719_INFO, &value); + if (ret < 0) + goto fail_powerdown; + if (value != DW9719_ID) { + ret = -ENXIO; + goto fail_powerdown; + } + dw9719_dev.focus = 0; + dw9719_dev.initialized = true; + + return 0; + +fail_powerdown: + dw9719_dev.platform_data->power_ctrl(sd, 0); + return ret; +} + +int dw9719_vcm_power_down(struct v4l2_subdev *sd) +{ + return dw9719_dev.platform_data->power_ctrl(sd, 0); +} + +int dw9719_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + static const struct timespec move_time = { + + .tv_sec = 0, + .tv_nsec = 60000000 + }; + struct timespec current_time, finish_time, delta_time; + + getnstimeofday(¤t_time); + finish_time = timespec_add(dw9719_dev.focus_time, move_time); + delta_time = timespec_sub(current_time, finish_time); + if (delta_time.tv_sec >= 0 && delta_time.tv_nsec >= 0) { + *value = ATOMISP_FOCUS_HP_COMPLETE | + ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + } else { + *value = ATOMISP_FOCUS_STATUS_MOVING | + ATOMISP_FOCUS_HP_IN_PROGRESS; + } + + return 0; +} + +int dw9719_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + return -EINVAL; +} + +int dw9719_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + value = clamp(value, 0, DW9719_MAX_FOCUS_POS); + ret = dw9719_i2c_wr16(client, DW9719_VCM_CURRENT, value); + if (ret < 0) + return ret; + + getnstimeofday(&dw9719_dev.focus_time); + dw9719_dev.focus = value; + + return 0; +} + +int dw9719_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + return dw9719_t_focus_abs(sd, dw9719_dev.focus + value); +} + +int dw9719_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + *value = dw9719_dev.focus; + return 0; +} +int dw9719_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int dw9719_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int dw9719_vcm_init(struct v4l2_subdev *sd) +{ + dw9719_dev.platform_data = camera_get_af_platform_data(); + return (NULL == dw9719_dev.platform_data) ? -ENODEV : 0; +} diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9719.h b/drivers/staging/media/atomisp/i2c/imx/dw9719.h new file mode 100644 index 0000000..711f412 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9719.h @@ -0,0 +1,58 @@ +/* + * Support for dw9719 vcm driver. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __DW9719_H__ +#define __DW9719_H__ + +#include "../../include/linux/atomisp_platform.h" +#include <linux/types.h> + +#define DW9719_VCM_ADDR (0x18 >> 1) + +/* dw9719 device structure */ +struct dw9719_device { + struct timespec timestamp_t_focus_abs; + s16 number_of_steps; + bool initialized; /* true if dw9719 is detected */ + s32 focus; /* Current focus value */ + struct timespec focus_time; /* Time when focus was last time set */ + __u8 buffer[4]; /* Used for i2c transactions */ + const struct camera_af_platform_data *platform_data; +}; + +#define DW9719_INVALID_CONFIG 0xffffffff +#define DW9719_MAX_FOCUS_POS 1023 +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) + +#define DW9719_INFO 0 +#define DW9719_ID 0xF1 +#define DW9719_CONTROL 2 +#define DW9719_VCM_CURRENT 3 + +#define DW9719_MODE 6 +#define DW9719_VCM_FREQ 7 + +#define DW9719_MODE_SAC3 0x40 +#define DW9719_DEFAULT_VCM_FREQ 0x04 +#define DW9719_ENABLE_RINGING 0x02 + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/imx.c b/drivers/staging/media/atomisp/i2c/imx/imx.c new file mode 100644 index 0000000..408a7b9 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx.c @@ -0,0 +1,2512 @@ +/* + * Support for Sony imx 8MP camera sensor. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <asm/intel-mid.h> +#include "../../include/linux/atomisp_platform.h" +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include "../../include/linux/libmsrlisthelper.h" +#include <linux/mm.h> +#include <linux/kmod.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/types.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include "imx.h" + +/* + * The imx135 embedded data info: + * embedded data line num: 2 + * line 0 effective data size(byte): 76 + * line 1 effective data size(byte): 113 + */ +static const uint32_t + imx135_embedded_effective_size[IMX135_EMBEDDED_DATA_LINE_NUM] + = {76, 113}; + +static enum atomisp_bayer_order imx_bayer_order_mapping[] = { + atomisp_bayer_order_rggb, + atomisp_bayer_order_grbg, + atomisp_bayer_order_gbrg, + atomisp_bayer_order_bggr +}; + +static const unsigned int +IMX227_BRACKETING_LUT_FRAME_ENTRY[IMX_MAX_AE_LUT_LENGTH] = { + 0x0E10, 0x0E1E, 0x0E2C, 0x0E3A, 0x0E48}; + +static int +imx_read_reg(struct i2c_client *client, u16 len, u16 reg, u16 *val) +{ + struct i2c_msg msg[2]; + u16 data[IMX_SHORT_MAX]; + int ret, i; + int retry = 0; + + if (len > IMX_BYTE_MAX) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + do { + memset(msg, 0 , sizeof(msg)); + memset(data, 0 , sizeof(data)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = (u8 *)data; + /* high byte goes first */ + data[0] = cpu_to_be16(reg); + + msg[1].addr = client->addr; + msg[1].len = len; + msg[1].flags = I2C_M_RD; + msg[1].buf = (u8 *)data; + + ret = i2c_transfer(client->adapter, msg, 2); + if (ret != 2) { + dev_err(&client->dev, + "retrying i2c read from offset 0x%x error %d... %d\n", + reg, ret, retry); + msleep(20); + } + } while (ret != 2 && retry++ < I2C_RETRY_COUNT); + + if (ret != 2) + return -EIO; + + /* high byte comes first */ + if (len == IMX_8BIT) { + *val = (u8)data[0]; + } else { + /* 16-bit access is default when len > 1 */ + for (i = 0; i < (len >> 1); i++) + val[i] = be16_to_cpu(data[i]); + } + + return 0; +} + +static int imx_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + int ret; + int retry = 0; + + do { + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret != 1) { + dev_err(&client->dev, + "retrying i2c write transfer... %d\n", retry); + msleep(20); + } + } while (ret != 1 && retry++ < I2C_RETRY_COUNT); + + return ret == 1 ? 0 : -EIO; +} + +int +imx_write_reg(struct i2c_client *client, u16 data_length, u16 reg, u16 val) +{ + int ret; + unsigned char data[4] = {0}; + u16 *wreg = (u16 *)data; + const u16 len = data_length + sizeof(u16); /* 16-bit address + data */ + + if (data_length != IMX_8BIT && data_length != IMX_16BIT) { + v4l2_err(client, "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = cpu_to_be16(reg); + + if (data_length == IMX_8BIT) + data[2] = (u8)(val); + else { + /* IMX_16BIT */ + u16 *wdata = (u16 *)&data[2]; + *wdata = cpu_to_be16(val); + } + + ret = imx_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * imx_write_reg_array - Initializes a list of imx registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __imx_flush_reg_array, __imx_buf_reg_array() and + * __imx_write_reg_is_consecutive() are internal functions to + * imx_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __imx_flush_reg_array(struct i2c_client *client, + struct imx_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u16) + ctrl->index; /* 16-bit address + data */ + ctrl->buffer.addr = cpu_to_be16(ctrl->buffer.addr); + ctrl->index = 0; + + return imx_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __imx_buf_reg_array(struct i2c_client *client, + struct imx_write_ctrl *ctrl, + const struct imx_reg *next) +{ + int size; + u16 *data16; + + switch (next->type) { + case IMX_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case IMX_16BIT: + size = 2; + data16 = (u16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->sreg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u16) >= IMX_MAX_WRITE_BUF_SIZE) + return __imx_flush_reg_array(client, ctrl); + + return 0; +} + +static int +__imx_write_reg_is_consecutive(struct i2c_client *client, + struct imx_write_ctrl *ctrl, + const struct imx_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->sreg; +} + +static int imx_write_reg_array(struct i2c_client *client, + const struct imx_reg *reglist) +{ + const struct imx_reg *next = reglist; + struct imx_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != IMX_TOK_TERM; next++) { + switch (next->type & IMX_TOK_MASK) { + case IMX_TOK_DELAY: + err = __imx_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__imx_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __imx_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __imx_buf_reg_array(client, &ctrl, next); + if (err) { + v4l2_err(client, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __imx_flush_reg_array(client, &ctrl); +} + +static int __imx_min_fps_diff(int fps, const struct imx_fps_setting *fps_list) +{ + int diff = INT_MAX; + int i; + + if (fps == 0) + return 0; + + for (i = 0; i < MAX_FPS_OPTIONS_SUPPORTED; i++) { + if (!fps_list[i].fps) + break; + if (abs(fps_list[i].fps - fps) < diff) + diff = abs(fps_list[i].fps - fps); + } + + return diff; +} + +static int __imx_nearest_fps_index(int fps, + const struct imx_fps_setting *fps_list) +{ + int fps_index = 0; + int i; + + for (i = 0; i < MAX_FPS_OPTIONS_SUPPORTED; i++) { + if (!fps_list[i].fps) + break; + if (abs(fps_list[i].fps - fps) + < abs(fps_list[fps_index].fps - fps)) + fps_index = i; + } + return fps_index; +} + +/* + * This is to choose the nearest fps setting above the requested fps + * fps_list should be in ascendant order. + */ +static int __imx_above_nearest_fps_index(int fps, + const struct imx_fps_setting *fps_list) +{ + int fps_index = 0; + int i; + + for (i = 0; i < MAX_FPS_OPTIONS_SUPPORTED; i++) { + if (!fps_list[i].fps) + break; + if (fps <= fps_list[i].fps) { + fps_index = i; + break; + } + } + + return fps_index; +} + +static int imx_get_lanes(struct v4l2_subdev *sd) +{ + struct camera_mipi_info *imx_info = v4l2_get_subdev_hostdata(sd); + + if (!imx_info) + return -ENOSYS; + if (imx_info->num_lanes < 1 || imx_info->num_lanes > 4 || + imx_info->num_lanes == 3) + return -EINVAL; + + return imx_info->num_lanes; +} + +static int __imx_update_exposure_timing(struct i2c_client *client, u16 exposure, + u16 llp, u16 fll) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx_device *dev = to_imx_sensor(sd); + int ret = 0; + + if (dev->sensor_id != IMX227_ID) { + /* Increase the VTS to match exposure + margin */ + if (exposure > fll - IMX_INTEGRATION_TIME_MARGIN) + fll = exposure + IMX_INTEGRATION_TIME_MARGIN; + } + + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->line_length_pixels, llp); + if (ret) + return ret; + + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->frame_length_lines, fll); + if (ret) + return ret; + + if (exposure) + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->coarse_integration_time, exposure); + + return ret; +} + +static int __imx_update_gain(struct v4l2_subdev *sd, u16 gain) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + /* set global gain */ + ret = imx_write_reg(client, IMX_8BIT, dev->reg_addr->global_gain, gain); + if (ret) + return ret; + + /* set short analog gain */ + if (dev->sensor_id == IMX135_ID) + ret = imx_write_reg(client, IMX_8BIT, IMX_SHORT_AGC_GAIN, gain); + + return ret; +} + +static int __imx_update_digital_gain(struct i2c_client *client, u16 digitgain) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx_device *dev = to_imx_sensor(sd); + struct imx_write_buffer digit_gain; + + digit_gain.addr = cpu_to_be16(dev->reg_addr->dgc_adj); + digit_gain.data[0] = (digitgain >> 8) & 0xFF; + digit_gain.data[1] = digitgain & 0xFF; + + if (dev->sensor_id == IMX219_ID) { + return imx_i2c_write(client, IMX219_DGC_LEN, (u8 *)&digit_gain); + } else if (dev->sensor_id == IMX227_ID) { + return imx_i2c_write(client, IMX227_DGC_LEN, (u8 *)&digit_gain); + } else { + digit_gain.data[2] = (digitgain >> 8) & 0xFF; + digit_gain.data[3] = digitgain & 0xFF; + digit_gain.data[4] = (digitgain >> 8) & 0xFF; + digit_gain.data[5] = digitgain & 0xFF; + digit_gain.data[6] = (digitgain >> 8) & 0xFF; + digit_gain.data[7] = digitgain & 0xFF; + return imx_i2c_write(client, IMX_DGC_LEN, (u8 *)&digit_gain); + } + return 0; +} + +static int imx_set_exposure_gain(struct v4l2_subdev *sd, u16 coarse_itg, + u16 gain, u16 digitgain) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int lanes = imx_get_lanes(sd); + unsigned int digitgain_scaled; + int ret = 0; + + /* Validate exposure: cannot exceed VTS-4 where VTS is 16bit */ + coarse_itg = clamp_t(u16, coarse_itg, 0, IMX_MAX_EXPOSURE_SUPPORTED); + + /* Validate gain: must not exceed maximum 8bit value */ + gain = clamp_t(u16, gain, 0, IMX_MAX_GLOBAL_GAIN_SUPPORTED); + + mutex_lock(&dev->input_lock); + + if (dev->sensor_id == IMX227_ID) { + ret = imx_write_reg_array(client, imx_param_hold); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + } + + /* For imx175, setting gain must be delayed by one */ + if ((dev->sensor_id == IMX175_ID) && dev->digital_gain) + digitgain_scaled = dev->digital_gain; + else + digitgain_scaled = digitgain; + /* imx132 with two lanes needs more gain to saturate at max */ + if (dev->sensor_id == IMX132_ID && lanes > 1) { + digitgain_scaled *= IMX132_2LANES_GAINFACT; + digitgain_scaled >>= IMX132_2LANES_GAINFACT_SHIFT; + } + /* Validate digital gain: must not exceed 12 bit value*/ + digitgain_scaled = clamp_t(unsigned int, digitgain_scaled, + 0, IMX_MAX_DIGITAL_GAIN_SUPPORTED); + + ret = __imx_update_exposure_timing(client, coarse_itg, + dev->pixels_per_line, dev->lines_per_frame); + if (ret) + goto out; + dev->coarse_itg = coarse_itg; + + if (dev->sensor_id == IMX175_ID) + ret = __imx_update_gain(sd, dev->gain); + else + ret = __imx_update_gain(sd, gain); + if (ret) + goto out; + dev->gain = gain; + + ret = __imx_update_digital_gain(client, digitgain_scaled); + if (ret) + goto out; + dev->digital_gain = digitgain; + +out: + if (dev->sensor_id == IMX227_ID) + ret = imx_write_reg_array(client, imx_param_update); + mutex_unlock(&dev->input_lock); + return ret; +} + +static long imx_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + return imx_set_exposure_gain(sd, exposure->integration_time[0], + exposure->gain[0], exposure->gain[1]); +} + +/* FIXME -To be updated with real OTP reading */ +static int imx_g_priv_int_data(struct v4l2_subdev *sd, + struct v4l2_private_int_data *priv) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + u8 __user *to = priv->data; + u32 read_size = priv->size; + int ret; + + /* No need to copy data if size is 0 */ + if (!read_size) + goto out; + + if (IS_ERR(dev->otp_data)) { + dev_err(&client->dev, "OTP data not available"); + return PTR_ERR(dev->otp_data); + } + /* Correct read_size value only if bigger than maximum */ + if (read_size > dev->otp_driver->size) + read_size = dev->otp_driver->size; + + ret = copy_to_user(to, dev->otp_data, read_size); + if (ret) { + dev_err(&client->dev, "%s: failed to copy OTP data to user\n", + __func__); + return -EFAULT; + } +out: + /* Return correct size */ + priv->size = dev->otp_driver->size; + + return 0; +} + +static int __imx_init(struct v4l2_subdev *sd, u32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + int lanes = imx_get_lanes(sd); + int ret; + + if (dev->sensor_id == IMX_ID_DEFAULT) + return 0; + + /* The default is no flip at sensor initialization */ + dev->h_flip->cur.val = 0; + dev->v_flip->cur.val = 0; + /* Sets the default FPS */ + dev->fps_index = 0; + dev->curr_res_table = dev->mode_tables->res_preview; + dev->entries_curr_table = dev->mode_tables->n_res_preview; + + ret = imx_write_reg_array(client, dev->mode_tables->init_settings); + if (ret) + return ret; + + if (dev->sensor_id == IMX132_ID && lanes > 0) { + static const u8 imx132_rglanesel[] = { + IMX132_RGLANESEL_1LANE, /* 1 lane */ + IMX132_RGLANESEL_2LANES, /* 2 lanes */ + IMX132_RGLANESEL_1LANE, /* undefined */ + IMX132_RGLANESEL_4LANES, /* 4 lanes */ + }; + ret = imx_write_reg(client, IMX_8BIT, + IMX132_RGLANESEL, imx132_rglanesel[lanes - 1]); + } + + return ret; +} + +static int imx_init(struct v4l2_subdev *sd, u32 val) +{ + struct imx_device *dev = to_imx_sensor(sd); + int ret = 0; + + mutex_lock(&dev->input_lock); + ret = __imx_init(sd, val); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long imx_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return imx_s_exposure(sd, arg); + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + return imx_g_priv_int_data(sd, arg); + default: + return -EINVAL; + } + return 0; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + int ret; + + /* power control */ + ret = dev->platform_data->power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* gpio ctrl */ + ret = dev->platform_data->gpio_ctrl(sd, 1); + if (ret) { + dev_err(&client->dev, "gpio failed\n"); + goto fail_gpio; + } + + return 0; +fail_gpio: + dev->platform_data->gpio_ctrl(sd, 0); +fail_clk: + dev->platform_data->flisclk_ctrl(sd, 0); +fail_power: + dev->platform_data->power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = dev->platform_data->gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed\n"); + + /* power control */ + ret = dev->platform_data->power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int __imx_s_power(struct v4l2_subdev *sd, int on) +{ + struct imx_device *dev = to_imx_sensor(sd); + int ret = 0; + int r = 0; + + if (on == 0) { + ret = power_down(sd); + if (dev->vcm_driver && dev->vcm_driver->power_down) + r = dev->vcm_driver->power_down(sd); + if (ret == 0) + ret = r; + dev->power = 0; + } else { + if (dev->vcm_driver && dev->vcm_driver->power_up) + ret = dev->vcm_driver->power_up(sd); + if (ret) + return ret; + ret = power_up(sd); + if (!ret) { + dev->power = 1; + return __imx_init(sd, 0); + } + } + + return ret; +} + +static int imx_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + ret = __imx_s_power(sd, on); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int imx_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct imx_reg *reglist) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx_device *dev = to_imx_sensor(sd); + int lanes = imx_get_lanes(sd); + u32 vt_pix_clk_div; + u32 vt_sys_clk_div; + u32 pre_pll_clk_div; + u32 pll_multiplier; + + const int ext_clk_freq_hz = 19200000; + struct atomisp_sensor_mode_data *buf = &info->data; + int ret; + u16 data[IMX_INTG_BUF_COUNT]; + + u32 vt_pix_clk_freq_mhz; + u32 coarse_integration_time_min; + u32 coarse_integration_time_max_margin; + u32 read_mode; + u32 div; + + if (info == NULL) + return -EINVAL; + + memset(data, 0, IMX_INTG_BUF_COUNT * sizeof(u16)); + ret = imx_read_reg(client, 1, IMX_VT_PIX_CLK_DIV, data); + if (ret) + return ret; + vt_pix_clk_div = data[0] & IMX_MASK_5BIT; + + if (dev->sensor_id == IMX132_ID || dev->sensor_id == IMX208_ID) { + static const int rgpltd[] = { 2, 4, 1, 1 }; + ret = imx_read_reg(client, 1, IMX132_208_VT_RGPLTD, data); + if (ret) + return ret; + vt_sys_clk_div = rgpltd[data[0] & IMX_MASK_2BIT]; + } else { + ret = imx_read_reg(client, 1, IMX_VT_SYS_CLK_DIV, data); + if (ret) + return ret; + vt_sys_clk_div = data[0] & IMX_MASK_2BIT; + } + ret = imx_read_reg(client, 1, IMX_PRE_PLL_CLK_DIV, data); + if (ret) + return ret; + pre_pll_clk_div = data[0] & IMX_MASK_4BIT; + + ret = imx_read_reg(client, 2, + (dev->sensor_id == IMX132_ID || + dev->sensor_id == IMX219_ID || + dev->sensor_id == IMX208_ID) ? + IMX132_208_219_PLL_MULTIPLIER : IMX_PLL_MULTIPLIER, data); + if (ret) + return ret; + pll_multiplier = data[0] & IMX_MASK_11BIT; + + memset(data, 0, IMX_INTG_BUF_COUNT * sizeof(u16)); + ret = imx_read_reg(client, 4, IMX_COARSE_INTG_TIME_MIN, data); + if (ret) + return ret; + coarse_integration_time_min = data[0]; + coarse_integration_time_max_margin = data[1]; + + /* Get the cropping and output resolution to ISP for this mode. */ + ret = imx_read_reg(client, 2, dev->reg_addr->horizontal_start_h, data); + if (ret) + return ret; + buf->crop_horizontal_start = data[0]; + + ret = imx_read_reg(client, 2, dev->reg_addr->vertical_start_h, data); + if (ret) + return ret; + buf->crop_vertical_start = data[0]; + + ret = imx_read_reg(client, 2, dev->reg_addr->horizontal_end_h, data); + if (ret) + return ret; + buf->crop_horizontal_end = data[0]; + + ret = imx_read_reg(client, 2, dev->reg_addr->vertical_end_h, data); + if (ret) + return ret; + buf->crop_vertical_end = data[0]; + + ret = imx_read_reg(client, 2, + dev->reg_addr->horizontal_output_size_h, data); + if (ret) + return ret; + buf->output_width = data[0]; + + ret = imx_read_reg(client, 2, + dev->reg_addr->vertical_output_size_h, data); + if (ret) + return ret; + buf->output_height = data[0]; + + memset(data, 0, IMX_INTG_BUF_COUNT * sizeof(u16)); + if (dev->sensor_id == IMX132_ID || dev->sensor_id == IMX208_ID || + dev->sensor_id == IMX219_ID) + read_mode = 0; + else { + if (dev->sensor_id == IMX227_ID) + ret = imx_read_reg(client, 1, IMX227_READ_MODE, data); + else + ret = imx_read_reg(client, 1, IMX_READ_MODE, data); + + if (ret) + return ret; + read_mode = data[0] & IMX_MASK_2BIT; + } + + div = pre_pll_clk_div*vt_sys_clk_div*vt_pix_clk_div; + if (div == 0) + return -EINVAL; + + if (dev->sensor_id == IMX132_ID || dev->sensor_id == IMX208_ID) + vt_pix_clk_freq_mhz = ext_clk_freq_hz / div; + else if (dev->sensor_id == IMX227_ID) { + /* according to IMX227 datasheet: + * vt_pix_freq_mhz = * num_of_vt_lanes(4) * ivt_pix_clk_freq_mhz + */ + vt_pix_clk_freq_mhz = + (u64)4 * ext_clk_freq_hz * pll_multiplier; + do_div(vt_pix_clk_freq_mhz, div); + } else + vt_pix_clk_freq_mhz = 2 * ext_clk_freq_hz / div; + + vt_pix_clk_freq_mhz *= pll_multiplier; + if (dev->sensor_id == IMX132_ID && lanes > 0) + vt_pix_clk_freq_mhz *= lanes; + + dev->vt_pix_clk_freq_mhz = vt_pix_clk_freq_mhz; + + buf->vt_pix_clk_freq_mhz = vt_pix_clk_freq_mhz; + buf->coarse_integration_time_min = coarse_integration_time_min; + buf->coarse_integration_time_max_margin = + coarse_integration_time_max_margin; + + buf->fine_integration_time_min = IMX_FINE_INTG_TIME; + buf->fine_integration_time_max_margin = IMX_FINE_INTG_TIME; + buf->fine_integration_time_def = IMX_FINE_INTG_TIME; + buf->frame_length_lines = dev->lines_per_frame; + buf->line_length_pck = dev->pixels_per_line; + buf->read_mode = read_mode; + + if (dev->sensor_id == IMX132_ID || dev->sensor_id == IMX208_ID || + dev->sensor_id == IMX219_ID) { + buf->binning_factor_x = 1; + buf->binning_factor_y = 1; + } else { + if (dev->sensor_id == IMX227_ID) + ret = imx_read_reg(client, 1, IMX227_BINNING_ENABLE, + data); + else + ret = imx_read_reg(client, 1, IMX_BINNING_ENABLE, data); + + if (ret) + return ret; + /* 1:binning enabled, 0:disabled */ + if (data[0] == 1) { + if (dev->sensor_id == IMX227_ID) + ret = imx_read_reg(client, 1, + IMX227_BINNING_TYPE, data); + else + ret = imx_read_reg(client, 1, + IMX_BINNING_TYPE, data); + + if (ret) + return ret; + buf->binning_factor_x = data[0] >> 4 & 0x0f; + if (!buf->binning_factor_x) + buf->binning_factor_x = 1; + buf->binning_factor_y = data[0] & 0xf; + if (!buf->binning_factor_y) + buf->binning_factor_y = 1; + /* WOWRKAROUND, NHD setting for IMX227 should have 4x4 + * binning but the register setting does not reflect + * this, I am asking vendor why this happens. this is + * workaround for INTEL BZ 216560. + */ + if (dev->sensor_id == IMX227_ID) { + if (dev->curr_res_table[dev->fmt_idx].width == + 376 && + dev->curr_res_table[dev->fmt_idx].height == + 656) { + buf->binning_factor_x = 4; + buf->binning_factor_y = 4; + } + } + } else { + buf->binning_factor_x = 1; + buf->binning_factor_y = 1; + } + } + + return 0; +} + +/* This returns the exposure time being used. This should only be used + for filling in EXIF data, not for actual image processing. */ +static int imx_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + u16 coarse; + int ret; + + /* the fine integration time is currently not calculated */ + ret = imx_read_reg(client, IMX_16BIT, + dev->reg_addr->coarse_integration_time, &coarse); + *value = coarse; + + return ret; +} + +static int imx_test_pattern(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + int ret; + + if (dev->power == 0) + return 0; + + ret = imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_COLOR_R, + (u16)(dev->tp_r->val >> 22)); + if (ret) + return ret; + + ret = imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_COLOR_GR, + (u16)(dev->tp_gr->val >> 22)); + if (ret) + return ret; + + ret = imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_COLOR_GB, + (u16)(dev->tp_gb->val >> 22)); + if (ret) + return ret; + + ret = imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_COLOR_B, + (u16)(dev->tp_b->val >> 22)); + if (ret) + return ret; + + return imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_MODE, + (u16)(dev->tp_mode->val)); +} + +static u32 imx_translate_bayer_order(enum atomisp_bayer_order code) +{ + switch (code) { + case atomisp_bayer_order_rggb: + return MEDIA_BUS_FMT_SRGGB10_1X10; + case atomisp_bayer_order_grbg: + return MEDIA_BUS_FMT_SGRBG10_1X10; + case atomisp_bayer_order_bggr: + return MEDIA_BUS_FMT_SBGGR10_1X10; + case atomisp_bayer_order_gbrg: + return MEDIA_BUS_FMT_SGBRG10_1X10; + } + return 0; +} + +static int imx_v_flip(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct camera_mipi_info *imx_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u16 val; + + if (dev->power == 0) + return -EIO; + + ret = imx_write_reg_array(client, dev->param_hold); + if (ret) + return ret; + + ret = imx_read_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, &val); + if (ret) + return ret; + if (value) + val |= IMX_VFLIP_BIT; + else + val &= ~IMX_VFLIP_BIT; + + ret = imx_write_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, val); + if (ret) + return ret; + + imx_info = v4l2_get_subdev_hostdata(sd); + if (imx_info) { + val &= (IMX_VFLIP_BIT|IMX_HFLIP_BIT); + imx_info->raw_bayer_order = imx_bayer_order_mapping[val]; + dev->format.code = imx_translate_bayer_order( + imx_info->raw_bayer_order); + } + + return imx_write_reg_array(client, dev->param_update); +} + +static int imx_h_flip(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct camera_mipi_info *imx_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u16 val; + + if (dev->power == 0) + return -EIO; + + ret = imx_write_reg_array(client, dev->param_hold); + if (ret) + return ret; + ret = imx_read_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, &val); + if (ret) + return ret; + if (value) + val |= IMX_HFLIP_BIT; + else + val &= ~IMX_HFLIP_BIT; + ret = imx_write_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, val); + if (ret) + return ret; + + imx_info = v4l2_get_subdev_hostdata(sd); + if (imx_info) { + val &= (IMX_VFLIP_BIT|IMX_HFLIP_BIT); + imx_info->raw_bayer_order = imx_bayer_order_mapping[val]; + dev->format.code = imx_translate_bayer_order( + imx_info->raw_bayer_order); + } + + return imx_write_reg_array(client, dev->param_update); +} + +static int imx_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (IMX_FOCAL_LENGTH_NUM << 16) | IMX_FOCAL_LENGTH_DEM; + return 0; +} + +static int imx_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (IMX_F_NUMBER_DEFAULT_NUM << 16) | IMX_F_NUMBER_DEM; + return 0; +} + +static int imx_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (IMX_F_NUMBER_DEFAULT_NUM << 24) | + (IMX_F_NUMBER_DEM << 16) | + (IMX_F_NUMBER_DEFAULT_NUM << 8) | IMX_F_NUMBER_DEM; + return 0; +} + +static int imx_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct imx_device *dev = to_imx_sensor(sd); + + *val = dev->curr_res_table[dev->fmt_idx].bin_factor_x; + + return 0; +} + +static int imx_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct imx_device *dev = to_imx_sensor(sd); + + *val = dev->curr_res_table[dev->fmt_idx].bin_factor_y; + + return 0; +} + +int imx_vcm_power_up(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->power_up) + return dev->vcm_driver->power_up(sd); + return 0; +} + +int imx_vcm_power_down(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->power_down) + return dev->vcm_driver->power_down(sd); + return 0; +} + +int imx_vcm_init(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->init) + return dev->vcm_driver->init(sd); + return 0; +} + +int imx_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_focus_vcm) + return dev->vcm_driver->t_focus_vcm(sd, val); + return 0; +} + +int imx_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_focus_abs) + return dev->vcm_driver->t_focus_abs(sd, value); + return 0; +} +int imx_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_focus_rel) + return dev->vcm_driver->t_focus_rel(sd, value); + return 0; +} + +int imx_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->q_focus_status) + return dev->vcm_driver->q_focus_status(sd, value); + return 0; +} + +int imx_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->q_focus_abs) + return dev->vcm_driver->q_focus_abs(sd, value); + return 0; +} + +int imx_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_vcm_slew) + return dev->vcm_driver->t_vcm_slew(sd, value); + return 0; +} + +int imx_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_vcm_timing) + return dev->vcm_driver->t_vcm_timing(sd, value); + return 0; +} + +static int imx_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct imx_device *dev = container_of( + ctrl->handler, struct imx_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_TEST_PATTERN: + ret = imx_test_pattern(&dev->sd); + break; + case V4L2_CID_VFLIP: + dev_dbg(&client->dev, "%s: CID_VFLIP:%d.\n", + __func__, ctrl->val); + ret = imx_v_flip(&dev->sd, ctrl->val); + break; + case V4L2_CID_HFLIP: + dev_dbg(&client->dev, "%s: CID_HFLIP:%d.\n", + __func__, ctrl->val); + ret = imx_h_flip(&dev->sd, ctrl->val); + break; + case V4L2_CID_FOCUS_ABSOLUTE: + ret = imx_t_focus_abs(&dev->sd, ctrl->val); + break; + case V4L2_CID_FOCUS_RELATIVE: + ret = imx_t_focus_rel(&dev->sd, ctrl->val); + break; + case V4L2_CID_VCM_SLEW: + ret = imx_t_vcm_slew(&dev->sd, ctrl->val); + break; + case V4L2_CID_VCM_TIMEING: + ret = imx_t_vcm_timing(&dev->sd, ctrl->val); + break; + } + + return ret; +} + +static int imx_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct imx_device *dev = container_of( + ctrl->handler, struct imx_device, ctrl_handler); + int ret = 0; + unsigned int val; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = imx_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCUS_ABSOLUTE: + ret = imx_q_focus_abs(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCUS_STATUS: + ret = imx_q_focus_status(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = imx_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = imx_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = imx_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_HORZ: + ret = imx_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = imx_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + case V4L2_CID_VBLANK: + ctrl->val = dev->lines_per_frame - + dev->curr_res_table[dev->fmt_idx].height; + break; + case V4L2_CID_HBLANK: + ctrl->val = dev->pixels_per_line - + dev->curr_res_table[dev->fmt_idx].width; + break; + case V4L2_CID_PIXEL_RATE: + ctrl->val = dev->vt_pix_clk_freq_mhz; + break; + case V4L2_CID_LINK_FREQ: + val = dev->curr_res_table[dev->fmt_idx]. + fps_options[dev->fps_index].mipi_freq; + if (val == 0) + val = dev->curr_res_table[dev->fmt_idx].mipi_freq; + if (val == 0) + return -EINVAL; + ctrl->val = val * 1000; /* To Hz */ + break; + default: + return -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = imx_s_ctrl, + .g_volatile_ctrl = imx_g_volatile_ctrl +}; + +static const struct v4l2_ctrl_config imx_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern", + .min = 0, + .max = 0xffff, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_COLOR_R, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern solid color R", + .min = INT_MIN, + .max = INT_MAX, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_COLOR_GR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern solid color GR", + .min = INT_MIN, + .max = INT_MAX, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_COLOR_GB, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern solid color GB", + .min = INT_MIN, + .max = INT_MAX, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_COLOR_B, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern solid color B", + .min = INT_MIN, + .max = INT_MAX, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flip", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Mirror", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus move absolute", + .min = 0, + .max = IMX_MAX_FOCUS_POS, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_RELATIVE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus move relative", + .min = IMX_MAX_FOCUS_NEG, + .max = IMX_MAX_FOCUS_POS, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_STATUS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus status", + .min = 0, + .max = 100, /* allow enum to grow in the future */ + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VCM_SLEW, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vcm slew", + .min = 0, + .max = IMX_VCM_SLEW_STEP_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VCM_TIMEING, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vcm step time", + .min = 0, + .max = IMX_VCM_SLEW_TIME_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = IMX_FOCAL_LENGTH_DEFAULT, + .max = IMX_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = IMX_FOCAL_LENGTH_DEFAULT, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = IMX_F_NUMBER_DEFAULT, + .max = IMX_F_NUMBER_DEFAULT, + .step = 0x01, + .def = IMX_F_NUMBER_DEFAULT, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = IMX_F_NUMBER_RANGE, + .max = IMX_F_NUMBER_RANGE, + .step = 0x01, + .def = IMX_F_NUMBER_RANGE, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "horizontal binning factor", + .min = 0, + .max = IMX_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vertical binning factor", + .min = 0, + .max = IMX_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_LINK_FREQ, + .name = "Link Frequency", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 1, + .max = 1500000 * 1000, + .step = 1, + .def = 1, + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_PIXEL_RATE, + .name = "Pixel Rate", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = INT_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HBLANK, + .name = "Horizontal Blanking", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = SHRT_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VBLANK, + .name = "Vertical Blanking", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = SHRT_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .name = "Horizontal Flip", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 1, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .name = "Vertical Flip", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 1, + .step = 1, + .def = 0, + .flags = 0, + }, +}; + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between resolution and w/h. + * res->width/height smaller than w/h wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 600 +static int distance(struct imx_resolution const *res, u32 w, u32 h, + bool keep_ratio) +{ + unsigned int w_ratio; + unsigned int h_ratio; + int match; + unsigned int allowed_ratio_mismatch = LARGEST_ALLOWED_RATIO_MISMATCH; + + if (!keep_ratio) + allowed_ratio_mismatch = ~0; + + if (w == 0) + return -1; + w_ratio = (res->width << 13) / w; + if (h == 0) + return -1; + h_ratio = (res->height << 13) / h; + if (h_ratio == 0) + return -1; + match = abs(((w_ratio << 13) / h_ratio) - ((int)8192)); + + if ((w_ratio < (int)8192) || (h_ratio < (int)8192) || + (match > allowed_ratio_mismatch)) + return -1; + + return w_ratio + h_ratio; +} + +/* Return the nearest higher resolution index */ +static int nearest_resolution_index(struct v4l2_subdev *sd, int w, int h) +{ + int i; + int idx = -1; + int dist; + int fps_diff; + int min_fps_diff = INT_MAX; + int min_dist = INT_MAX; + const struct imx_resolution *tmp_res = NULL; + struct imx_device *dev = to_imx_sensor(sd); + bool again = 1; +retry: + for (i = 0; i < dev->entries_curr_table; i++) { + tmp_res = &dev->curr_res_table[i]; + dist = distance(tmp_res, w, h, again); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + } + if (dist == min_dist) { + fps_diff = __imx_min_fps_diff(dev->targetfps, + tmp_res->fps_options); + if (fps_diff < min_fps_diff) { + min_fps_diff = fps_diff; + idx = i; + } + } + } + + /* + * FIXME! + * only IMX135 for Saltbay and IMX227 use this algorithm + */ + if (idx == -1 && again == true && dev->new_res_sel_method) { + again = false; + goto retry; + } + return idx; +} + +/* Call with ctrl_handler.lock hold */ +static int __adjust_hvblank(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + u16 new_frame_length_lines, new_line_length_pck; + int ret; + + /* + * No need to adjust h/v blank if not set dbg value + * Note that there is no other checking on the h/v blank value, + * as h/v blank can be set to any value above zero for debug purpose + */ + if (!dev->v_blank->val || !dev->h_blank->val) + return 0; + + new_frame_length_lines = dev->curr_res_table[dev->fmt_idx].height + + dev->v_blank->val; + new_line_length_pck = dev->curr_res_table[dev->fmt_idx].width + + dev->h_blank->val; + + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->line_length_pixels, new_line_length_pck); + if (ret) + return ret; + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->frame_length_lines, new_frame_length_lines); + if (ret) + return ret; + + dev->lines_per_frame = new_frame_length_lines; + dev->pixels_per_line = new_line_length_pck; + + return 0; +} + +static int imx_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct imx_device *dev = to_imx_sensor(sd); + struct camera_mipi_info *imx_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + const struct imx_resolution *res; + int lanes = imx_get_lanes(sd); + int ret; + u16 data, val; + int idx; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + imx_info = v4l2_get_subdev_hostdata(sd); + if (imx_info == NULL) + return -EINVAL; + if ((fmt->width > imx_max_res[dev->sensor_id].res_max_width) + || (fmt->height > imx_max_res[dev->sensor_id].res_max_height)) { + fmt->width = imx_max_res[dev->sensor_id].res_max_width; + fmt->height = imx_max_res[dev->sensor_id].res_max_height; + } else { + idx = nearest_resolution_index(sd, fmt->width, fmt->height); + + /* + * nearest_resolution_index() doesn't return smaller + * resolutions. If it fails, it means the requested + * resolution is higher than wecan support. Fallback + * to highest possible resolution in this case. + */ + if (idx == -1) + idx = dev->entries_curr_table - 1; + + fmt->width = dev->curr_res_table[idx].width; + fmt->height = dev->curr_res_table[idx].height; + } + + fmt->code = dev->format.code; + if(format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + return 0; + } + mutex_lock(&dev->input_lock); + + dev->fmt_idx = nearest_resolution_index(sd, fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + ret = -EINVAL; + goto out; + } + res = &dev->curr_res_table[dev->fmt_idx]; + + /* Adjust the FPS selection based on the resolution selected */ + dev->fps_index = __imx_nearest_fps_index(dev->targetfps, + res->fps_options); + dev->fps = res->fps_options[dev->fps_index].fps; + dev->regs = res->fps_options[dev->fps_index].regs; + if (!dev->regs) + dev->regs = res->regs; + + ret = imx_write_reg_array(client, dev->regs); + if (ret) + goto out; + + if (dev->sensor_id == IMX132_ID && lanes > 0) { + static const u8 imx132_rgpltd[] = { + 2, /* 1 lane: /1 */ + 0, /* 2 lanes: /2 */ + 0, /* undefined */ + 1, /* 4 lanes: /4 */ + }; + ret = imx_write_reg(client, IMX_8BIT, IMX132_208_VT_RGPLTD, + imx132_rgpltd[lanes - 1]); + if (ret) + goto out; + } + + dev->pixels_per_line = res->fps_options[dev->fps_index].pixels_per_line; + dev->lines_per_frame = res->fps_options[dev->fps_index].lines_per_frame; + + /* dbg h/v blank time */ + __adjust_hvblank(sd); + + ret = __imx_update_exposure_timing(client, dev->coarse_itg, + dev->pixels_per_line, dev->lines_per_frame); + if (ret) + goto out; + + ret = __imx_update_gain(sd, dev->gain); + if (ret) + goto out; + + ret = __imx_update_digital_gain(client, dev->digital_gain); + if (ret) + goto out; + + ret = imx_write_reg_array(client, dev->param_update); + if (ret) + goto out; + + ret = imx_get_intg_factor(client, imx_info, dev->regs); + if (ret) + goto out; + + ret = imx_read_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, &val); + if (ret) + goto out; + val &= (IMX_VFLIP_BIT|IMX_HFLIP_BIT); + imx_info->raw_bayer_order = imx_bayer_order_mapping[val]; + dev->format.code = imx_translate_bayer_order( + imx_info->raw_bayer_order); + + /* + * Fill meta data info. add imx135 metadata setting for RAW10 format + */ + switch (dev->sensor_id) { + case IMX135_ID: + ret = imx_read_reg(client, 2, + IMX135_OUTPUT_DATA_FORMAT_REG, &data); + if (ret) + goto out; + /* + * The IMX135 can support various resolutions like + * RAW6/8/10/12/14. + * 1.The data format is RAW10: + * matadata width = current resolution width(pixel) * 10 / 8 + * 2.The data format is RAW6 or RAW8: + * matadata width = current resolution width(pixel); + * 3.other data format(RAW12/14 etc): + * TBD. + */ + if (data == IMX135_OUTPUT_FORMAT_RAW10) + /* the data format is RAW10. */ + imx_info->metadata_width = res->width * 10 / 8; + else + /* The data format is RAW6/8/12/14/ etc. */ + imx_info->metadata_width = res->width; + + imx_info->metadata_height = IMX135_EMBEDDED_DATA_LINE_NUM; + + if (imx_info->metadata_effective_width == NULL) + imx_info->metadata_effective_width = + imx135_embedded_effective_size; + + break; + case IMX227_ID: + ret = imx_read_reg(client, 2, IMX227_OUTPUT_DATA_FORMAT_REG, + &data); + if (ret) + goto out; + if (data == IMX227_OUTPUT_FORMAT_RAW10) + /* the data format is RAW10. */ + imx_info->metadata_width = res->width * 10 / 8; + else + /* The data format is RAW6/8/12/14/ etc. */ + imx_info->metadata_width = res->width; + + imx_info->metadata_height = IMX227_EMBEDDED_DATA_LINE_NUM; + + if (imx_info->metadata_effective_width == NULL) + imx_info->metadata_effective_width = + imx227_embedded_effective_size; + + break; + default: + imx_info->metadata_width = 0; + imx_info->metadata_height = 0; + imx_info->metadata_effective_width = NULL; + break; + } + +out: + mutex_unlock(&dev->input_lock); + return ret; +} + + +static int imx_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct imx_device *dev = to_imx_sensor(sd); + + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + mutex_lock(&dev->input_lock); + fmt->width = dev->curr_res_table[dev->fmt_idx].width; + fmt->height = dev->curr_res_table[dev->fmt_idx].height; + fmt->code = dev->format.code; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int imx_detect(struct i2c_client *client, u16 *id, u8 *revision) +{ + struct i2c_adapter *adapter = client->adapter; + + /* i2c check */ + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + /* check sensor chip ID */ + if (imx_read_reg(client, IMX_16BIT, IMX132_175_208_219_CHIP_ID, id)) { + v4l2_err(client, "sensor_id = 0x%x\n", *id); + return -ENODEV; + } + + if (*id == IMX132_ID || *id == IMX175_ID || + *id == IMX208_ID || *id == IMX219_ID) + goto found; + + if (imx_read_reg(client, IMX_16BIT, IMX134_135_227_CHIP_ID, id)) { + v4l2_err(client, "sensor_id = 0x%x\n", *id); + return -ENODEV; + } + if (*id != IMX134_ID && *id != IMX135_ID && *id != IMX227_ID) { + v4l2_err(client, "no imx sensor found\n"); + return -ENODEV; + } +found: + v4l2_info(client, "sensor_id = 0x%x\n", *id); + + /* TODO - need to be updated */ + *revision = 0; + + return 0; +} + +static void __imx_print_timing(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 width = dev->curr_res_table[dev->fmt_idx].width; + u16 height = dev->curr_res_table[dev->fmt_idx].height; + + dev_dbg(&client->dev, "Dump imx timing in stream on:\n"); + dev_dbg(&client->dev, "width: %d:\n", width); + dev_dbg(&client->dev, "height: %d:\n", height); + dev_dbg(&client->dev, "pixels_per_line: %d:\n", dev->pixels_per_line); + dev_dbg(&client->dev, "line per frame: %d:\n", dev->lines_per_frame); + dev_dbg(&client->dev, "pix freq: %d:\n", dev->vt_pix_clk_freq_mhz); + dev_dbg(&client->dev, "init fps: %d:\n", dev->vt_pix_clk_freq_mhz / + dev->pixels_per_line / dev->lines_per_frame); + dev_dbg(&client->dev, "HBlank: %d nS:\n", + 1000 * (dev->pixels_per_line - width) / + (dev->vt_pix_clk_freq_mhz / 1000000)); + dev_dbg(&client->dev, "VBlank: %d uS:\n", + (dev->lines_per_frame - height) * dev->pixels_per_line / + (dev->vt_pix_clk_freq_mhz / 1000000)); +} + +/* + * imx stream on/off + */ +static int imx_s_stream(struct v4l2_subdev *sd, int enable) +{ + int ret; + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + if (enable) { + /* Noise reduction & dead pixel applied before streaming */ + if (dev->fw == NULL) { + dev_warn(&client->dev, "No MSR loaded from library"); + } else { + ret = apply_msr_data(client, dev->fw); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + } + ret = imx_test_pattern(sd); + if (ret) { + v4l2_err(client, "Configure test pattern failed.\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + __imx_print_timing(sd); + ret = imx_write_reg_array(client, imx_streaming); + if (ret != 0) { + v4l2_err(client, "write_reg_array err\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + dev->streaming = 1; + if (dev->vcm_driver && dev->vcm_driver->t_focus_abs_init) + dev->vcm_driver->t_focus_abs_init(sd); + } else { + ret = imx_write_reg_array(client, imx_soft_standby); + if (ret != 0) { + v4l2_err(client, "write_reg_array err\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + dev->streaming = 0; + dev->targetfps = 0; + } + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int __update_imx_device_settings(struct imx_device *dev, u16 sensor_id) +{ + /* IMX on other platform is not supported yet */ + return -EINVAL; +} + +static int imx_s_config(struct v4l2_subdev *sd, + int irq, void *pdata) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 sensor_revision; + u16 sensor_id; + int ret; + if (pdata == NULL) + return -ENODEV; + + dev->platform_data = pdata; + + mutex_lock(&dev->input_lock); + + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) { + mutex_unlock(&dev->input_lock); + dev_err(&client->dev, "imx platform init err\n"); + return ret; + } + } + /* + * power off the module first. + * + * As first power on by board have undecided state of power/gpio pins. + */ + ret = __imx_s_power(sd, 0); + if (ret) { + v4l2_err(client, "imx power-down err.\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = __imx_s_power(sd, 1); + if (ret) { + v4l2_err(client, "imx power-up err.\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = imx_detect(client, &sensor_id, &sensor_revision); + if (ret) { + v4l2_err(client, "imx_detect err s_config.\n"); + goto fail_detect; + } + + dev->sensor_id = sensor_id; + dev->sensor_revision = sensor_revision; + + /* Resolution settings depend on sensor type and platform */ + ret = __update_imx_device_settings(dev, dev->sensor_id); + if (ret) + goto fail_detect; + /* Read sensor's OTP data */ + dev->otp_data = dev->otp_driver->otp_read(sd, + dev->otp_driver->dev_addr, dev->otp_driver->start_addr, + dev->otp_driver->size); + + /* power off sensor */ + ret = __imx_s_power(sd, 0); + + mutex_unlock(&dev->input_lock); + if (ret) + v4l2_err(client, "imx power-down err.\n"); + + return ret; + +fail_detect: + dev->platform_data->csi_cfg(sd, 0); +fail_csi_cfg: + __imx_s_power(sd, 0); + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + mutex_unlock(&dev->input_lock); + dev_err(&client->dev, "sensor power-gating failed\n"); + return ret; +} + +static int +imx_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (code->index >= MAX_FMTS) + return -EINVAL; + + mutex_lock(&dev->input_lock); + code->code = dev->format.code; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int +imx_enum_frame_size(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + if (index >= dev->entries_curr_table) { + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + fse->min_width = dev->curr_res_table[index].width; + fse->min_height = dev->curr_res_table[index].height; + fse->max_width = dev->curr_res_table[index].width; + fse->max_height = dev->curr_res_table[index].height; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int +imx_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param) +{ + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + dev->run_mode = param->parm.capture.capturemode; + + switch (dev->run_mode) { + case CI_MODE_VIDEO: + dev->curr_res_table = dev->mode_tables->res_video; + dev->entries_curr_table = dev->mode_tables->n_res_video; + break; + case CI_MODE_STILL_CAPTURE: + dev->curr_res_table = dev->mode_tables->res_still; + dev->entries_curr_table = dev->mode_tables->n_res_still; + break; + default: + dev->curr_res_table = dev->mode_tables->res_preview; + dev->entries_curr_table = dev->mode_tables->n_res_preview; + } + mutex_unlock(&dev->input_lock); + return 0; +} + +int +imx_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + interval->interval.denominator = dev->fps; + interval->interval.numerator = 1; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int __imx_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + const struct imx_resolution *res = + &dev->curr_res_table[dev->fmt_idx]; + struct camera_mipi_info *imx_info = NULL; + unsigned short pixels_per_line; + unsigned short lines_per_frame; + unsigned int fps_index; + int fps; + int ret = 0; + + + imx_info = v4l2_get_subdev_hostdata(sd); + if (imx_info == NULL) + return -EINVAL; + + if (!interval->interval.numerator) + interval->interval.numerator = 1; + + fps = interval->interval.denominator / interval->interval.numerator; + + if (!fps) + return -EINVAL; + + dev->targetfps = fps; + /* No need to proceed further if we are not streaming */ + if (!dev->streaming) + return 0; + + /* Ignore if we are already using the required FPS. */ + if (fps == dev->fps) + return 0; + + /* + * Start here, sensor is already streaming, so adjust fps dynamically + */ + fps_index = __imx_above_nearest_fps_index(fps, res->fps_options); + if (fps > res->fps_options[fps_index].fps) { + /* + * if does not have high fps setting, not support increase fps + * by adjust lines per frame. + */ + dev_err(&client->dev, "Could not support fps: %d.\n", fps); + return -EINVAL; + } + + if (res->fps_options[fps_index].regs && + res->fps_options[fps_index].regs != dev->regs) { + /* + * if need a new setting, but the new setting has difference + * with current setting, not use this one, as may have + * unexpected result, e.g. PLL, IQ. + */ + dev_dbg(&client->dev, + "Sensor is streaming, not apply new sensor setting\n"); + if (fps > res->fps_options[dev->fps_index].fps) { + /* + * Does not support increase fps based on low fps + * setting, as the high fps setting could not be used, + * and fps requested is above current setting fps. + */ + dev_warn(&client->dev, + "Could not support fps: %d, keep current: %d.\n", + fps, dev->fps); + return 0; + } + } else { + dev->fps_index = fps_index; + dev->fps = res->fps_options[dev->fps_index].fps; + } + + /* Update the new frametimings based on FPS */ + pixels_per_line = res->fps_options[dev->fps_index].pixels_per_line; + lines_per_frame = res->fps_options[dev->fps_index].lines_per_frame; + + if (fps > res->fps_options[fps_index].fps) { + /* + * if does not have high fps setting, not support increase fps + * by adjust lines per frame. + */ + dev_warn(&client->dev, "Could not support fps: %d. Use:%d.\n", + fps, res->fps_options[fps_index].fps); + goto done; + } + + /* if the new setting does not match exactly */ + if (dev->fps != fps) { +#define MAX_LINES_PER_FRAME 0xffff + dev_dbg(&client->dev, "adjusting fps using lines_per_frame\n"); + /* + * FIXME! + * 1: check DS on max value of lines_per_frame + * 2: consider use pixel per line for more range? + */ + if (dev->lines_per_frame * dev->fps / fps > + MAX_LINES_PER_FRAME) { + dev_warn(&client->dev, + "adjust lines_per_frame out of range, try to use max value.\n"); + lines_per_frame = MAX_LINES_PER_FRAME; + } else { + lines_per_frame = lines_per_frame * dev->fps / fps; + } + } +done: + /* Update the new frametimings based on FPS */ + dev->pixels_per_line = pixels_per_line; + dev->lines_per_frame = lines_per_frame; + + /* Update the new values so that user side knows the current settings */ + ret = __imx_update_exposure_timing(client, + dev->coarse_itg, dev->pixels_per_line, dev->lines_per_frame); + if (ret) + return ret; + + dev->fps = fps; + + ret = imx_get_intg_factor(client, imx_info, dev->regs); + if (ret) + return ret; + + interval->interval.denominator = res->fps_options[dev->fps_index].fps; + interval->interval.numerator = 1; + __imx_print_timing(sd); + + return ret; +} + +static int imx_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct imx_device *dev = to_imx_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __imx_s_frame_interval(sd, interval); + mutex_unlock(&dev->input_lock); + + return ret; +} +static int imx_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = dev->curr_res_table[dev->fmt_idx].skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops imx_sensor_ops = { + .g_skip_frames = imx_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops imx_video_ops = { + .s_stream = imx_s_stream, + .s_parm = imx_s_parm, + .g_frame_interval = imx_g_frame_interval, + .s_frame_interval = imx_s_frame_interval, +}; + +static const struct v4l2_subdev_core_ops imx_core_ops = { + .s_power = imx_s_power, + .ioctl = imx_ioctl, + .init = imx_init, +}; + +static const struct v4l2_subdev_pad_ops imx_pad_ops = { + .enum_mbus_code = imx_enum_mbus_code, + .enum_frame_size = imx_enum_frame_size, + .get_fmt = imx_get_fmt, + .set_fmt = imx_set_fmt, +}; + +static const struct v4l2_subdev_ops imx_ops = { + .core = &imx_core_ops, + .video = &imx_video_ops, + .pad = &imx_pad_ops, + .sensor = &imx_sensor_ops, +}; + +static const struct media_entity_operations imx_entity_ops = { + .link_setup = NULL, +}; + +static int imx_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx_device *dev = to_imx_sensor(sd); + + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + dev->platform_data->csi_cfg(sd, 0); + v4l2_device_unregister_subdev(sd); + release_msr_list(client, dev->fw); + kfree(dev); + + return 0; +} + +static int __imx_init_ctrl_handler(struct imx_device *dev) +{ + struct v4l2_ctrl_handler *hdl; + int i; + + hdl = &dev->ctrl_handler; + + v4l2_ctrl_handler_init(&dev->ctrl_handler, ARRAY_SIZE(imx_controls)); + + for (i = 0; i < ARRAY_SIZE(imx_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, + &imx_controls[i], NULL); + + dev->pixel_rate = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_PIXEL_RATE); + dev->h_blank = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_HBLANK); + dev->v_blank = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_VBLANK); + dev->link_freq = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_LINK_FREQ); + dev->h_flip = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_HFLIP); + dev->v_flip = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_VFLIP); + dev->tp_mode = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN); + dev->tp_r = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN_COLOR_R); + dev->tp_gr = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN_COLOR_GR); + dev->tp_gb = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN_COLOR_GB); + dev->tp_b = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN_COLOR_B); + + if (dev->ctrl_handler.error || dev->pixel_rate == NULL + || dev->h_blank == NULL || dev->v_blank == NULL + || dev->h_flip == NULL || dev->v_flip == NULL + || dev->link_freq == NULL) { + return dev->ctrl_handler.error; + } + + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = hdl; + v4l2_ctrl_handler_setup(&dev->ctrl_handler); + + return 0; +} + +static void imx_update_reg_info(struct imx_device *dev) +{ + if (dev->sensor_id == IMX219_ID) { + dev->reg_addr = &imx219_addr; + dev->param_hold = imx219_param_hold; + dev->param_update = imx219_param_update; + } else { + dev->reg_addr = &imx_addr; + dev->param_hold = imx_param_hold; + dev->param_update = imx_param_update; + } +} + +static int imx_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct imx_device *dev; + struct camera_mipi_info *imx_info = NULL; + int ret; + char *msr_file_name = NULL; + + /* allocate sensor device & init sub device */ + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + v4l2_err(client, "%s: out of memory\n", __func__); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + dev->i2c_id = id->driver_data; + dev->fmt_idx = 0; + dev->sensor_id = IMX_ID_DEFAULT; + dev->vcm_driver = &imx_vcms[IMX_ID_DEFAULT]; + dev->digital_gain = 256; + + v4l2_i2c_subdev_init(&(dev->sd), client, &imx_ops); + + if (client->dev.platform_data) { + ret = imx_s_config(&dev->sd, client->irq, + client->dev.platform_data); + if (ret) + goto out_free; + } + imx_info = v4l2_get_subdev_hostdata(&dev->sd); + + /* + * sd->name is updated with sensor driver name by the v4l2. + * change it to sensor name in this case. + */ + imx_update_reg_info(dev); + snprintf(dev->sd.name, sizeof(dev->sd.name), "%s%x %d-%04x", + IMX_SUBDEV_PREFIX, dev->sensor_id, + i2c_adapter_id(client->adapter), client->addr); + + ret = __imx_init_ctrl_handler(dev); + if (ret) + goto out_ctrl_handler_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = imx_translate_bayer_order( + imx_info->raw_bayer_order); + dev->sd.entity.ops = &imx_entity_ops; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) { + imx_remove(client); + return ret; + } + + /* Load the Noise reduction, Dead pixel registers from cpf file*/ + if (dev->platform_data->msr_file_name != NULL) + msr_file_name = dev->platform_data->msr_file_name(); + if (msr_file_name) { + ret = load_msr_list(client, msr_file_name, &dev->fw); + if (ret) { + imx_remove(client); + return ret; + } + } else { + dev_warn(&client->dev, "Drvb file not present"); + } + + return ret; + +out_ctrl_handler_free: + v4l2_ctrl_handler_free(&dev->ctrl_handler); + +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +static const struct i2c_device_id imx_ids[] = { + {IMX_NAME_175, IMX175_ID}, + {IMX_NAME_135, IMX135_ID}, + {IMX_NAME_135_FUJI, IMX135_FUJI_ID}, + {IMX_NAME_134, IMX134_ID}, + {IMX_NAME_132, IMX132_ID}, + {IMX_NAME_208, IMX208_ID}, + {IMX_NAME_219, IMX219_ID}, + {IMX_NAME_227, IMX227_ID}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, imx_ids); + +static struct i2c_driver imx_driver = { + .driver = { + .name = IMX_DRIVER, + }, + .probe = imx_probe, + .remove = imx_remove, + .id_table = imx_ids, +}; + +static __init int init_imx(void) +{ + return i2c_add_driver(&imx_driver); +} + +static __exit void exit_imx(void) +{ + i2c_del_driver(&imx_driver); +} + +module_init(init_imx); +module_exit(exit_imx); + +MODULE_DESCRIPTION("A low-level driver for Sony IMX sensors"); +MODULE_AUTHOR("Shenbo Huang <shenbo.huang@intel.com>"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx.h b/drivers/staging/media/atomisp/i2c/imx/imx.h new file mode 100644 index 0000000..36b3f3a --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx.h @@ -0,0 +1,766 @@ +/* + * Support for Sony IMX camera sensor. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __IMX_H__ +#define __IMX_H__ +#include "../../include/linux/atomisp_platform.h" +#include "../../include/linux/atomisp.h" +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/kernel.h> +#include <linux/spinlock.h> +#include <linux/types.h> +#include <linux/videodev2.h> +#include <linux/v4l2-mediabus.h> +#include <media/media-entity.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include <media/v4l2-subdev.h> +#include "imx175.h" +#include "imx135.h" +#include "imx134.h" +#include "imx132.h" +#include "imx208.h" +#include "imx219.h" +#include "imx227.h" + +#define IMX_MCLK 192 + +/* TODO - This should be added into include/linux/videodev2.h */ +#ifndef V4L2_IDENT_IMX +#define V4L2_IDENT_IMX 8245 +#endif + +#define IMX_MAX_AE_LUT_LENGTH 5 +/* + * imx System control registers + */ +#define IMX_MASK_5BIT 0x1F +#define IMX_MASK_4BIT 0xF +#define IMX_MASK_3BIT 0x7 +#define IMX_MASK_2BIT 0x3 +#define IMX_MASK_8BIT 0xFF +#define IMX_MASK_11BIT 0x7FF +#define IMX_INTG_BUF_COUNT 2 + +#define IMX_FINE_INTG_TIME 0x1E8 + +#define IMX_VT_PIX_CLK_DIV 0x0301 +#define IMX_VT_SYS_CLK_DIV 0x0303 +#define IMX_PRE_PLL_CLK_DIV 0x0305 +#define IMX227_IOP_PRE_PLL_CLK_DIV 0x030D +#define IMX227_PLL_MULTIPLIER 0x0306 +#define IMX227_IOP_PLL_MULTIPLIER 0x030E +#define IMX227_PLL_MULTI_DRIVE 0x0310 +#define IMX227_OP_PIX_CLK_DIV 0x0309 +#define IMX227_OP_SYS_CLK_DIV 0x030B +#define IMX_PLL_MULTIPLIER 0x030C +#define IMX_OP_PIX_DIV 0x0309 +#define IMX_OP_SYS_DIV 0x030B +#define IMX_FRAME_LENGTH_LINES 0x0340 +#define IMX_LINE_LENGTH_PIXELS 0x0342 +#define IMX_COARSE_INTG_TIME_MIN 0x1004 +#define IMX_COARSE_INTG_TIME_MAX 0x1006 +#define IMX_BINNING_ENABLE 0x0390 +#define IMX227_BINNING_ENABLE 0x0900 +#define IMX_BINNING_TYPE 0x0391 +#define IMX227_BINNING_TYPE 0x0901 +#define IMX_READ_MODE 0x0390 +#define IMX227_READ_MODE 0x0900 + +#define IMX_HORIZONTAL_START_H 0x0344 +#define IMX_VERTICAL_START_H 0x0346 +#define IMX_HORIZONTAL_END_H 0x0348 +#define IMX_VERTICAL_END_H 0x034a +#define IMX_HORIZONTAL_OUTPUT_SIZE_H 0x034c +#define IMX_VERTICAL_OUTPUT_SIZE_H 0x034e + +/* Post Divider setting register for imx132 and imx208 */ +#define IMX132_208_VT_RGPLTD 0x30A4 + +/* Multiplier setting register for imx132, imx208, and imx219 */ +#define IMX132_208_219_PLL_MULTIPLIER 0x0306 + +#define IMX_COARSE_INTEGRATION_TIME 0x0202 +#define IMX_TEST_PATTERN_MODE 0x0600 +#define IMX_TEST_PATTERN_COLOR_R 0x0602 +#define IMX_TEST_PATTERN_COLOR_GR 0x0604 +#define IMX_TEST_PATTERN_COLOR_B 0x0606 +#define IMX_TEST_PATTERN_COLOR_GB 0x0608 +#define IMX_IMG_ORIENTATION 0x0101 +#define IMX_VFLIP_BIT 2 +#define IMX_HFLIP_BIT 1 +#define IMX_GLOBAL_GAIN 0x0205 +#define IMX_SHORT_AGC_GAIN 0x0233 +#define IMX_DGC_ADJ 0x020E +#define IMX_DGC_LEN 10 +#define IMX227_DGC_LEN 4 +#define IMX_MAX_EXPOSURE_SUPPORTED 0xfffb +#define IMX_MAX_GLOBAL_GAIN_SUPPORTED 0x00ff +#define IMX_MAX_DIGITAL_GAIN_SUPPORTED 0x0fff + +#define MAX_FMTS 1 +#define IMX_OTP_DATA_SIZE 1280 + +#define IMX_SUBDEV_PREFIX "imx" +#define IMX_DRIVER "imx1x5" + +/* Sensor ids from identification register */ +#define IMX_NAME_134 "imx134" +#define IMX_NAME_135 "imx135" +#define IMX_NAME_175 "imx175" +#define IMX_NAME_132 "imx132" +#define IMX_NAME_208 "imx208" +#define IMX_NAME_219 "imx219" +#define IMX_NAME_227 "imx227" +#define IMX175_ID 0x0175 +#define IMX135_ID 0x0135 +#define IMX134_ID 0x0134 +#define IMX132_ID 0x0132 +#define IMX208_ID 0x0208 +#define IMX219_ID 0x0219 +#define IMX227_ID 0x0227 + +/* Sensor id based on i2c_device_id table + * (Fuji module can not be detected based on sensor registers) */ +#define IMX135_FUJI_ID 0x0136 +#define IMX_NAME_135_FUJI "imx135fuji" + +/* imx175 - use dw9714 vcm */ +#define IMX175_MERRFLD 0x175 +#define IMX175_VALLEYVIEW 0x176 +#define IMX135_SALTBAY 0x135 +#define IMX135_VICTORIABAY 0x136 +#define IMX132_SALTBAY 0x132 +#define IMX134_VALLEYVIEW 0x134 +#define IMX208_MOFD_PD2 0x208 +#define IMX219_MFV0_PRH 0x219 +#define IMX227_SAND 0x227 + +/* otp - specific settings */ +#define E2PROM_ADDR 0xa0 +#define E2PROM_LITEON_12P1BA869D_ADDR 0xa0 +#define E2PROM_ABICO_SS89A839_ADDR 0xa8 +#define DEFAULT_OTP_SIZE 1280 +#define IMX135_OTP_SIZE 1280 +#define IMX219_OTP_SIZE 2048 +#define IMX227_OTP_SIZE 2560 +#define E2PROM_LITEON_12P1BA869D_SIZE 544 + +#define IMX_ID_DEFAULT 0x0000 +#define IMX132_175_208_219_CHIP_ID 0x0000 +#define IMX134_135_CHIP_ID 0x0016 +#define IMX134_135_227_CHIP_ID 0x0016 + +#define IMX175_RES_WIDTH_MAX 3280 +#define IMX175_RES_HEIGHT_MAX 2464 +#define IMX135_RES_WIDTH_MAX 4208 +#define IMX135_RES_HEIGHT_MAX 3120 +#define IMX132_RES_WIDTH_MAX 1936 +#define IMX132_RES_HEIGHT_MAX 1096 +#define IMX134_RES_WIDTH_MAX 3280 +#define IMX134_RES_HEIGHT_MAX 2464 +#define IMX208_RES_WIDTH_MAX 1936 +#define IMX208_RES_HEIGHT_MAX 1096 +#define IMX219_RES_WIDTH_MAX 3280 +#define IMX219_RES_HEIGHT_MAX 2464 +#define IMX227_RES_WIDTH_MAX 2400 +#define IMX227_RES_HEIGHT_MAX 2720 + +/* Defines for lens/VCM */ +#define IMX_FOCAL_LENGTH_NUM 369 /*3.69mm*/ +#define IMX_FOCAL_LENGTH_DEM 100 +#define IMX_F_NUMBER_DEFAULT_NUM 22 +#define IMX_F_NUMBER_DEM 10 +#define IMX_INVALID_CONFIG 0xffffffff +#define IMX_MAX_FOCUS_POS 1023 +#define IMX_MAX_FOCUS_NEG (-1023) +#define IMX_VCM_SLEW_STEP_MAX 0x3f +#define IMX_VCM_SLEW_TIME_MAX 0x1f + +#define IMX_BIN_FACTOR_MAX 4 +#define IMX_INTEGRATION_TIME_MARGIN 4 +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define IMX_FOCAL_LENGTH_DEFAULT 0x1710064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define IMX_F_NUMBER_DEFAULT 0x16000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define IMX_F_NUMBER_RANGE 0x160a160a + +struct imx_vcm { + int (*power_up)(struct v4l2_subdev *sd); + int (*power_down)(struct v4l2_subdev *sd); + int (*init)(struct v4l2_subdev *sd); + int (*t_focus_vcm)(struct v4l2_subdev *sd, u16 val); + int (*t_focus_abs)(struct v4l2_subdev *sd, s32 value); + int (*t_focus_abs_init)(struct v4l2_subdev *sd); + int (*t_focus_rel)(struct v4l2_subdev *sd, s32 value); + int (*q_focus_status)(struct v4l2_subdev *sd, s32 *value); + int (*q_focus_abs)(struct v4l2_subdev *sd, s32 *value); + int (*t_vcm_slew)(struct v4l2_subdev *sd, s32 value); + int (*t_vcm_timing)(struct v4l2_subdev *sd, s32 value); +}; + +struct imx_otp { + void * (*otp_read)(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); + u32 start_addr; + u32 size; + u8 dev_addr; +}; + +struct max_res { + int res_max_width; + int res_max_height; +}; + +struct max_res imx_max_res[] = { + [IMX175_ID] = { + .res_max_width = IMX175_RES_WIDTH_MAX, + .res_max_height = IMX175_RES_HEIGHT_MAX, + }, + [IMX135_ID] = { + .res_max_width = IMX135_RES_WIDTH_MAX, + .res_max_height = IMX135_RES_HEIGHT_MAX, + }, + [IMX132_ID] = { + .res_max_width = IMX132_RES_WIDTH_MAX, + .res_max_height = IMX132_RES_HEIGHT_MAX, + }, + [IMX134_ID] = { + .res_max_width = IMX134_RES_WIDTH_MAX, + .res_max_height = IMX134_RES_HEIGHT_MAX, + }, + [IMX208_ID] = { + .res_max_width = IMX208_RES_WIDTH_MAX, + .res_max_height = IMX208_RES_HEIGHT_MAX, + }, + [IMX219_ID] = { + .res_max_width = IMX219_RES_WIDTH_MAX, + .res_max_height = IMX219_RES_HEIGHT_MAX, + }, + [IMX227_ID] = { + .res_max_width = IMX227_RES_WIDTH_MAX, + .res_max_height = IMX227_RES_HEIGHT_MAX, + }, +}; + +struct imx_settings { + struct imx_reg const *init_settings; + struct imx_resolution *res_preview; + struct imx_resolution *res_still; + struct imx_resolution *res_video; + int n_res_preview; + int n_res_still; + int n_res_video; +}; + +struct imx_settings imx_sets[] = { + [IMX175_MERRFLD] = { + .init_settings = imx175_init_settings, + .res_preview = imx175_res_preview, + .res_still = imx175_res_still, + .res_video = imx175_res_video, + .n_res_preview = ARRAY_SIZE(imx175_res_preview), + .n_res_still = ARRAY_SIZE(imx175_res_still), + .n_res_video = ARRAY_SIZE(imx175_res_video), + }, + [IMX175_VALLEYVIEW] = { + .init_settings = imx175_init_settings, + .res_preview = imx175_res_preview, + .res_still = imx175_res_still, + .res_video = imx175_res_video, + .n_res_preview = ARRAY_SIZE(imx175_res_preview), + .n_res_still = ARRAY_SIZE(imx175_res_still), + .n_res_video = ARRAY_SIZE(imx175_res_video), + }, + [IMX135_SALTBAY] = { + .init_settings = imx135_init_settings, + .res_preview = imx135_res_preview, + .res_still = imx135_res_still, + .res_video = imx135_res_video, + .n_res_preview = ARRAY_SIZE(imx135_res_preview), + .n_res_still = ARRAY_SIZE(imx135_res_still), + .n_res_video = ARRAY_SIZE(imx135_res_video), + }, + [IMX135_VICTORIABAY] = { + .init_settings = imx135_init_settings, + .res_preview = imx135_res_preview_mofd, + .res_still = imx135_res_still_mofd, + .res_video = imx135_res_video, + .n_res_preview = ARRAY_SIZE(imx135_res_preview_mofd), + .n_res_still = ARRAY_SIZE(imx135_res_still_mofd), + .n_res_video = ARRAY_SIZE(imx135_res_video), + }, + [IMX132_SALTBAY] = { + .init_settings = imx132_init_settings, + .res_preview = imx132_res_preview, + .res_still = imx132_res_still, + .res_video = imx132_res_video, + .n_res_preview = ARRAY_SIZE(imx132_res_preview), + .n_res_still = ARRAY_SIZE(imx132_res_still), + .n_res_video = ARRAY_SIZE(imx132_res_video), + }, + [IMX134_VALLEYVIEW] = { + .init_settings = imx134_init_settings, + .res_preview = imx134_res_preview, + .res_still = imx134_res_still, + .res_video = imx134_res_video, + .n_res_preview = ARRAY_SIZE(imx134_res_preview), + .n_res_still = ARRAY_SIZE(imx134_res_still), + .n_res_video = ARRAY_SIZE(imx134_res_video), + }, + [IMX208_MOFD_PD2] = { + .init_settings = imx208_init_settings, + .res_preview = imx208_res_preview, + .res_still = imx208_res_still, + .res_video = imx208_res_video, + .n_res_preview = ARRAY_SIZE(imx208_res_preview), + .n_res_still = ARRAY_SIZE(imx208_res_still), + .n_res_video = ARRAY_SIZE(imx208_res_video), + }, + [IMX219_MFV0_PRH] = { + .init_settings = imx219_init_settings, + .res_preview = imx219_res_preview, + .res_still = imx219_res_still, + .res_video = imx219_res_video, + .n_res_preview = ARRAY_SIZE(imx219_res_preview), + .n_res_still = ARRAY_SIZE(imx219_res_still), + .n_res_video = ARRAY_SIZE(imx219_res_video), + }, + [IMX227_SAND] = { + .init_settings = imx227_init_settings, + .res_preview = imx227_res_preview, + .res_still = imx227_res_still, + .res_video = imx227_res_video, + .n_res_preview = ARRAY_SIZE(imx227_res_preview), + .n_res_still = ARRAY_SIZE(imx227_res_still), + .n_res_video = ARRAY_SIZE(imx227_res_video), + }, +}; + +struct imx_reg_addr { + u16 frame_length_lines; + u16 line_length_pixels; + u16 horizontal_start_h; + u16 vertical_start_h; + u16 horizontal_end_h; + u16 vertical_end_h; + u16 horizontal_output_size_h; + u16 vertical_output_size_h; + u16 coarse_integration_time; + u16 img_orientation; + u16 global_gain; + u16 dgc_adj; +}; + +struct imx_reg_addr imx_addr = { + IMX_FRAME_LENGTH_LINES, + IMX_LINE_LENGTH_PIXELS, + IMX_HORIZONTAL_START_H, + IMX_VERTICAL_START_H, + IMX_HORIZONTAL_END_H, + IMX_VERTICAL_END_H, + IMX_HORIZONTAL_OUTPUT_SIZE_H, + IMX_VERTICAL_OUTPUT_SIZE_H, + IMX_COARSE_INTEGRATION_TIME, + IMX_IMG_ORIENTATION, + IMX_GLOBAL_GAIN, + IMX_DGC_ADJ, +}; + +struct imx_reg_addr imx219_addr = { + IMX219_FRAME_LENGTH_LINES, + IMX219_LINE_LENGTH_PIXELS, + IMX219_HORIZONTAL_START_H, + IMX219_VERTICAL_START_H, + IMX219_HORIZONTAL_END_H, + IMX219_VERTICAL_END_H, + IMX219_HORIZONTAL_OUTPUT_SIZE_H, + IMX219_VERTICAL_OUTPUT_SIZE_H, + IMX219_COARSE_INTEGRATION_TIME, + IMX219_IMG_ORIENTATION, + IMX219_GLOBAL_GAIN, + IMX219_DGC_ADJ, +}; + +#define v4l2_format_capture_type_entry(_width, _height, \ + _pixelformat, _bytesperline, _colorspace) \ + {\ + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,\ + .fmt.pix.width = (_width),\ + .fmt.pix.height = (_height),\ + .fmt.pix.pixelformat = (_pixelformat),\ + .fmt.pix.bytesperline = (_bytesperline),\ + .fmt.pix.colorspace = (_colorspace),\ + .fmt.pix.sizeimage = (_height)*(_bytesperline),\ + } + +#define s_output_format_entry(_width, _height, _pixelformat, \ + _bytesperline, _colorspace, _fps) \ + {\ + .v4l2_fmt = v4l2_format_capture_type_entry(_width, \ + _height, _pixelformat, _bytesperline, \ + _colorspace),\ + .fps = (_fps),\ + } + +#define s_output_format_reg_entry(_width, _height, _pixelformat, \ + _bytesperline, _colorspace, _fps, _reg_setting) \ + {\ + .s_fmt = s_output_format_entry(_width, _height,\ + _pixelformat, _bytesperline, \ + _colorspace, _fps),\ + .reg_setting = (_reg_setting),\ + } + +/* imx device structure */ +struct imx_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct camera_sensor_platform_data *platform_data; + struct mutex input_lock; /* serialize sensor's ioctl */ + int fmt_idx; + int status; + int streaming; + int power; + int run_mode; + int vt_pix_clk_freq_mhz; + int fps_index; + u32 focus; + u16 sensor_id; /* Sensor id from registers */ + u16 i2c_id; /* Sensor id from i2c_device_id */ + u16 coarse_itg; + u16 fine_itg; + u16 digital_gain; + u16 gain; + u16 pixels_per_line; + u16 lines_per_frame; + u8 targetfps; + u8 fps; + const struct imx_reg *regs; + u8 res; + u8 type; + u8 sensor_revision; + u8 *otp_data; + struct imx_settings *mode_tables; + struct imx_vcm *vcm_driver; + struct imx_otp *otp_driver; + const struct imx_resolution *curr_res_table; + int entries_curr_table; + const struct firmware *fw; + struct imx_reg_addr *reg_addr; + const struct imx_reg *param_hold; + const struct imx_reg *param_update; + + /* used for h/b blank tuning */ + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *h_blank; + struct v4l2_ctrl *v_blank; + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *h_flip; + struct v4l2_ctrl *v_flip; + + /* Test pattern control */ + struct v4l2_ctrl *tp_mode; + struct v4l2_ctrl *tp_r; + struct v4l2_ctrl *tp_gr; + struct v4l2_ctrl *tp_gb; + struct v4l2_ctrl *tp_b; + + /* FIXME! */ + bool new_res_sel_method; +}; + +#define to_imx_sensor(x) container_of(x, struct imx_device, sd) + +#define IMX_MAX_WRITE_BUF_SIZE 32 +struct imx_write_buffer { + u16 addr; + u8 data[IMX_MAX_WRITE_BUF_SIZE]; +}; + +struct imx_write_ctrl { + int index; + struct imx_write_buffer buffer; +}; + +static const struct imx_reg imx_soft_standby[] = { + {IMX_8BIT, 0x0100, 0x00}, + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx_streaming[] = { + {IMX_8BIT, 0x0100, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx_param_hold[] = { + {IMX_8BIT, 0x0104, 0x01}, /* GROUPED_PARAMETER_HOLD */ + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx_param_update[] = { + {IMX_8BIT, 0x0104, 0x00}, /* GROUPED_PARAMETER_HOLD */ + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx219_param_hold[] = { + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx219_param_update[] = { + {IMX_TOK_TERM, 0, 0} +}; + +extern int ad5816g_vcm_power_up(struct v4l2_subdev *sd); +extern int ad5816g_vcm_power_down(struct v4l2_subdev *sd); +extern int ad5816g_vcm_init(struct v4l2_subdev *sd); + +extern int ad5816g_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int ad5816g_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int ad5816g_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int ad5816g_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int ad5816g_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int ad5816g_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int ad5816g_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int drv201_vcm_power_up(struct v4l2_subdev *sd); +extern int drv201_vcm_power_down(struct v4l2_subdev *sd); +extern int drv201_vcm_init(struct v4l2_subdev *sd); + +extern int drv201_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int drv201_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int drv201_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int drv201_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int drv201_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int drv201_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int drv201_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int dw9714_vcm_power_up(struct v4l2_subdev *sd); +extern int dw9714_vcm_power_down(struct v4l2_subdev *sd); +extern int dw9714_vcm_init(struct v4l2_subdev *sd); + +extern int dw9714_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int dw9714_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int dw9714_t_focus_abs_init(struct v4l2_subdev *sd); +extern int dw9714_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int dw9714_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int dw9714_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int dw9714_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int dw9714_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int dw9719_vcm_power_up(struct v4l2_subdev *sd); +extern int dw9719_vcm_power_down(struct v4l2_subdev *sd); +extern int dw9719_vcm_init(struct v4l2_subdev *sd); + +extern int dw9719_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int dw9719_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int dw9719_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int dw9719_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int dw9719_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int dw9719_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int dw9719_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int dw9718_vcm_power_up(struct v4l2_subdev *sd); +extern int dw9718_vcm_power_down(struct v4l2_subdev *sd); +extern int dw9718_vcm_init(struct v4l2_subdev *sd); + +extern int dw9718_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int vcm_power_up(struct v4l2_subdev *sd); +extern int vcm_power_down(struct v4l2_subdev *sd); + +struct imx_vcm imx_vcms[] = { + [IMX175_MERRFLD] = { + .power_up = drv201_vcm_power_up, + .power_down = drv201_vcm_power_down, + .init = drv201_vcm_init, + .t_focus_vcm = drv201_t_focus_vcm, + .t_focus_abs = drv201_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = drv201_t_focus_rel, + .q_focus_status = drv201_q_focus_status, + .q_focus_abs = drv201_q_focus_abs, + .t_vcm_slew = drv201_t_vcm_slew, + .t_vcm_timing = drv201_t_vcm_timing, + }, + [IMX175_VALLEYVIEW] = { + .power_up = dw9714_vcm_power_up, + .power_down = dw9714_vcm_power_down, + .init = dw9714_vcm_init, + .t_focus_vcm = dw9714_t_focus_vcm, + .t_focus_abs = dw9714_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = dw9714_t_focus_rel, + .q_focus_status = dw9714_q_focus_status, + .q_focus_abs = dw9714_q_focus_abs, + .t_vcm_slew = dw9714_t_vcm_slew, + .t_vcm_timing = dw9714_t_vcm_timing, + }, + [IMX135_SALTBAY] = { + .power_up = ad5816g_vcm_power_up, + .power_down = ad5816g_vcm_power_down, + .init = ad5816g_vcm_init, + .t_focus_vcm = ad5816g_t_focus_vcm, + .t_focus_abs = ad5816g_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = ad5816g_t_focus_rel, + .q_focus_status = ad5816g_q_focus_status, + .q_focus_abs = ad5816g_q_focus_abs, + .t_vcm_slew = ad5816g_t_vcm_slew, + .t_vcm_timing = ad5816g_t_vcm_timing, + }, + [IMX135_VICTORIABAY] = { + .power_up = dw9719_vcm_power_up, + .power_down = dw9719_vcm_power_down, + .init = dw9719_vcm_init, + .t_focus_vcm = dw9719_t_focus_vcm, + .t_focus_abs = dw9719_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = dw9719_t_focus_rel, + .q_focus_status = dw9719_q_focus_status, + .q_focus_abs = dw9719_q_focus_abs, + .t_vcm_slew = dw9719_t_vcm_slew, + .t_vcm_timing = dw9719_t_vcm_timing, + }, + [IMX134_VALLEYVIEW] = { + .power_up = dw9714_vcm_power_up, + .power_down = dw9714_vcm_power_down, + .init = dw9714_vcm_init, + .t_focus_vcm = dw9714_t_focus_vcm, + .t_focus_abs = dw9714_t_focus_abs, + .t_focus_abs_init = dw9714_t_focus_abs_init, + .t_focus_rel = dw9714_t_focus_rel, + .q_focus_status = dw9714_q_focus_status, + .q_focus_abs = dw9714_q_focus_abs, + .t_vcm_slew = dw9714_t_vcm_slew, + .t_vcm_timing = dw9714_t_vcm_timing, + }, + [IMX219_MFV0_PRH] = { + .power_up = dw9718_vcm_power_up, + .power_down = dw9718_vcm_power_down, + .init = dw9718_vcm_init, + .t_focus_vcm = dw9718_t_focus_vcm, + .t_focus_abs = dw9718_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = dw9718_t_focus_rel, + .q_focus_status = dw9718_q_focus_status, + .q_focus_abs = dw9718_q_focus_abs, + .t_vcm_slew = dw9718_t_vcm_slew, + .t_vcm_timing = dw9718_t_vcm_timing, + }, + [IMX_ID_DEFAULT] = { + .power_up = NULL, + .power_down = NULL, + .t_focus_abs_init = NULL, + }, +}; + +extern void *dummy_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *imx_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *e2prom_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *brcc064_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *imx227_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *e2prom_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +struct imx_otp imx_otps[] = { + [IMX175_MERRFLD] = { + .otp_read = imx_otp_read, + .dev_addr = E2PROM_ADDR, + .start_addr = 0, + .size = DEFAULT_OTP_SIZE, + }, + [IMX175_VALLEYVIEW] = { + .otp_read = e2prom_otp_read, + .dev_addr = E2PROM_ABICO_SS89A839_ADDR, + .start_addr = E2PROM_2ADDR, + .size = DEFAULT_OTP_SIZE, + }, + [IMX135_SALTBAY] = { + .otp_read = e2prom_otp_read, + .dev_addr = E2PROM_ADDR, + .start_addr = 0, + .size = DEFAULT_OTP_SIZE, + }, + [IMX135_VICTORIABAY] = { + .otp_read = imx_otp_read, + .size = DEFAULT_OTP_SIZE, + }, + [IMX134_VALLEYVIEW] = { + .otp_read = e2prom_otp_read, + .dev_addr = E2PROM_LITEON_12P1BA869D_ADDR, + .start_addr = 0, + .size = E2PROM_LITEON_12P1BA869D_SIZE, + }, + [IMX132_SALTBAY] = { + .otp_read = dummy_otp_read, + .size = DEFAULT_OTP_SIZE, + }, + [IMX208_MOFD_PD2] = { + .otp_read = dummy_otp_read, + .size = DEFAULT_OTP_SIZE, + }, + [IMX219_MFV0_PRH] = { + .otp_read = brcc064_otp_read, + .dev_addr = E2PROM_ADDR, + .start_addr = 0, + .size = IMX219_OTP_SIZE, + }, + [IMX227_SAND] = { + .otp_read = imx227_otp_read, + .size = IMX227_OTP_SIZE, + }, + [IMX_ID_DEFAULT] = { + .otp_read = dummy_otp_read, + .size = DEFAULT_OTP_SIZE, + }, +}; + +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx132.h b/drivers/staging/media/atomisp/i2c/imx/imx132.h new file mode 100644 index 0000000..98f047b --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx132.h @@ -0,0 +1,566 @@ +/* + * Support for Sony IMX camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __IMX132_H__ +#define __IMX132_H__ +#include "common.h" + +/********************** registers define ********************************/ +#define IMX132_RGLANESEL 0x3301 /* Number of lanes */ +#define IMX132_RGLANESEL_1LANE 0x01 +#define IMX132_RGLANESEL_2LANES 0x00 +#define IMX132_RGLANESEL_4LANES 0x03 + +#define IMX132_2LANES_GAINFACT 2096 /* 524/256 * 2^10 */ +#define IMX132_2LANES_GAINFACT_SHIFT 10 + +/********************** settings for imx from vendor*********************/ +static struct imx_reg imx132_1080p_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + /* PLL setting */ + {IMX_8BIT, 0x0305, 0x02}, + {IMX_8BIT, 0x0307, 0x50}, + {IMX_8BIT, 0x30A4, 0x02}, + {IMX_8BIT, 0x303C, 0x3C}, + /* Mode setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x14}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x32}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0xA3}, + {IMX_8BIT, 0x034A, 0x04}, + {IMX_8BIT, 0x034B, 0x79}, + {IMX_8BIT, 0x034C, 0x07}, + {IMX_8BIT, 0x034D, 0x90}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x48}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x303D, 0x10}, + {IMX_8BIT, 0x303E, 0x5A}, + {IMX_8BIT, 0x3040, 0x00}, + {IMX_8BIT, 0x3041, 0x00}, + {IMX_8BIT, 0x3048, 0x00}, + {IMX_8BIT, 0x304C, 0x2F}, + {IMX_8BIT, 0x304D, 0x02}, + {IMX_8BIT, 0x3064, 0x92}, + {IMX_8BIT, 0x306A, 0x10}, + {IMX_8BIT, 0x309B, 0x00}, + {IMX_8BIT, 0x309E, 0x41}, + {IMX_8BIT, 0x30A0, 0x10}, + {IMX_8BIT, 0x30A1, 0x0B}, + {IMX_8BIT, 0x30B2, 0x00}, + {IMX_8BIT, 0x30D5, 0x00}, + {IMX_8BIT, 0x30D6, 0x00}, + {IMX_8BIT, 0x30D7, 0x00}, + {IMX_8BIT, 0x30D8, 0x00}, + {IMX_8BIT, 0x30D9, 0x00}, + {IMX_8BIT, 0x30DA, 0x00}, + {IMX_8BIT, 0x30DB, 0x00}, + {IMX_8BIT, 0x30DC, 0x00}, + {IMX_8BIT, 0x30DD, 0x00}, + {IMX_8BIT, 0x30DE, 0x00}, + {IMX_8BIT, 0x3102, 0x0C}, + {IMX_8BIT, 0x3103, 0x33}, + {IMX_8BIT, 0x3104, 0x18}, + {IMX_8BIT, 0x3105, 0x00}, + {IMX_8BIT, 0x3106, 0x65}, + {IMX_8BIT, 0x3107, 0x00}, + {IMX_8BIT, 0x3108, 0x06}, + {IMX_8BIT, 0x3109, 0x04}, + {IMX_8BIT, 0x310A, 0x04}, + {IMX_8BIT, 0x315C, 0x3D}, + {IMX_8BIT, 0x315D, 0x3C}, + {IMX_8BIT, 0x316E, 0x3E}, + {IMX_8BIT, 0x316F, 0x3D}, + /* Global timing */ + {IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */ + {IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */ + {IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */ + {IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */ + {IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */ + {IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */ + {IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */ + {IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */ + {IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */ + {IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */ + {IMX_8BIT, 0x330E, 0x03}, + {IMX_8BIT, 0x3318, 0x62}, + {IMX_8BIT, 0x3322, 0x09}, + {IMX_8BIT, 0x3342, 0x00}, + {IMX_8BIT, 0x3348, 0xE0}, + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx132_1456x1096_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + /* PLL setting */ + {IMX_8BIT, 0x0305, 0x02}, + {IMX_8BIT, 0x0307, 0x50}, + {IMX_8BIT, 0x30A4, 0x02}, + {IMX_8BIT, 0x303C, 0x3C}, + /* Mode setting */ + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0x04}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x32}, + {IMX_8BIT, 0x0348, 0x06}, + {IMX_8BIT, 0x0349, 0xB3}, + {IMX_8BIT, 0x034A, 0x04}, + {IMX_8BIT, 0x034B, 0x79}, + {IMX_8BIT, 0x034C, 0x05}, + {IMX_8BIT, 0x034D, 0xB0}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x48}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x303D, 0x10}, + {IMX_8BIT, 0x303E, 0x5A}, + {IMX_8BIT, 0x3040, 0x00}, + {IMX_8BIT, 0x3041, 0x00}, + {IMX_8BIT, 0x3048, 0x00}, + {IMX_8BIT, 0x304C, 0x2F}, + {IMX_8BIT, 0x304D, 0x02}, + {IMX_8BIT, 0x3064, 0x92}, + {IMX_8BIT, 0x306A, 0x10}, + {IMX_8BIT, 0x309B, 0x00}, + {IMX_8BIT, 0x309E, 0x41}, + {IMX_8BIT, 0x30A0, 0x10}, + {IMX_8BIT, 0x30A1, 0x0B}, + {IMX_8BIT, 0x30B2, 0x00}, + {IMX_8BIT, 0x30D5, 0x00}, + {IMX_8BIT, 0x30D6, 0x00}, + {IMX_8BIT, 0x30D7, 0x00}, + {IMX_8BIT, 0x30D8, 0x00}, + {IMX_8BIT, 0x30D9, 0x00}, + {IMX_8BIT, 0x30DA, 0x00}, + {IMX_8BIT, 0x30DB, 0x00}, + {IMX_8BIT, 0x30DC, 0x00}, + {IMX_8BIT, 0x30DD, 0x00}, + {IMX_8BIT, 0x30DE, 0x00}, + {IMX_8BIT, 0x3102, 0x0C}, + {IMX_8BIT, 0x3103, 0x33}, + {IMX_8BIT, 0x3104, 0x18}, + {IMX_8BIT, 0x3105, 0x00}, + {IMX_8BIT, 0x3106, 0x65}, + {IMX_8BIT, 0x3107, 0x00}, + {IMX_8BIT, 0x3108, 0x06}, + {IMX_8BIT, 0x3109, 0x04}, + {IMX_8BIT, 0x310A, 0x04}, + {IMX_8BIT, 0x315C, 0x3D}, + {IMX_8BIT, 0x315D, 0x3C}, + {IMX_8BIT, 0x316E, 0x3E}, + {IMX_8BIT, 0x316F, 0x3D}, + /* Global timing */ + {IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */ + {IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */ + {IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */ + {IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */ + {IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */ + {IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */ + {IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */ + {IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */ + {IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */ + {IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */ + {IMX_8BIT, 0x330E, 0x03}, + {IMX_8BIT, 0x3318, 0x62}, + {IMX_8BIT, 0x3322, 0x09}, + {IMX_8BIT, 0x3342, 0x00}, + {IMX_8BIT, 0x3348, 0xE0}, + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx132_1636x1096_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + /* PLL setting */ + {IMX_8BIT, 0x0305, 0x02}, + {IMX_8BIT, 0x0307, 0x50}, + {IMX_8BIT, 0x30A4, 0x02}, + {IMX_8BIT, 0x303C, 0x3C}, + /* Mode setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0xAA}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x32}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0x0D}, + {IMX_8BIT, 0x034A, 0x04}, + {IMX_8BIT, 0x034B, 0x79}, + {IMX_8BIT, 0x034C, 0x06}, + {IMX_8BIT, 0x034D, 0x64}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x48}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x303D, 0x10}, + {IMX_8BIT, 0x303E, 0x5A}, + {IMX_8BIT, 0x3040, 0x00}, + {IMX_8BIT, 0x3041, 0x00}, + {IMX_8BIT, 0x3048, 0x00}, + {IMX_8BIT, 0x304C, 0x2F}, + {IMX_8BIT, 0x304D, 0x02}, + {IMX_8BIT, 0x3064, 0x92}, + {IMX_8BIT, 0x306A, 0x10}, + {IMX_8BIT, 0x309B, 0x00}, + {IMX_8BIT, 0x309E, 0x41}, + {IMX_8BIT, 0x30A0, 0x10}, + {IMX_8BIT, 0x30A1, 0x0B}, + {IMX_8BIT, 0x30B2, 0x00}, + {IMX_8BIT, 0x30D5, 0x00}, + {IMX_8BIT, 0x30D6, 0x00}, + {IMX_8BIT, 0x30D7, 0x00}, + {IMX_8BIT, 0x30D8, 0x00}, + {IMX_8BIT, 0x30D9, 0x00}, + {IMX_8BIT, 0x30DA, 0x00}, + {IMX_8BIT, 0x30DB, 0x00}, + {IMX_8BIT, 0x30DC, 0x00}, + {IMX_8BIT, 0x30DD, 0x00}, + {IMX_8BIT, 0x30DE, 0x00}, + {IMX_8BIT, 0x3102, 0x0C}, + {IMX_8BIT, 0x3103, 0x33}, + {IMX_8BIT, 0x3104, 0x18}, + {IMX_8BIT, 0x3105, 0x00}, + {IMX_8BIT, 0x3106, 0x65}, + {IMX_8BIT, 0x3107, 0x00}, + {IMX_8BIT, 0x3108, 0x06}, + {IMX_8BIT, 0x3109, 0x04}, + {IMX_8BIT, 0x310A, 0x04}, + {IMX_8BIT, 0x315C, 0x3D}, + {IMX_8BIT, 0x315D, 0x3C}, + {IMX_8BIT, 0x316E, 0x3E}, + {IMX_8BIT, 0x316F, 0x3D}, + /* Global timing */ + {IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */ + {IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */ + {IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */ + {IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */ + {IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */ + {IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */ + {IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */ + {IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */ + {IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */ + {IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */ + {IMX_8BIT, 0x330E, 0x03}, + {IMX_8BIT, 0x3318, 0x62}, + {IMX_8BIT, 0x3322, 0x09}, + {IMX_8BIT, 0x3342, 0x00}, + {IMX_8BIT, 0x3348, 0xE0}, + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx132_1336x1096_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + /* PLL setting */ + {IMX_8BIT, 0x0305, 0x02}, + {IMX_8BIT, 0x0307, 0x50}, + {IMX_8BIT, 0x30A4, 0x02}, + {IMX_8BIT, 0x303C, 0x3C}, + /* Mode setting */ + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0x2C}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x32}, + {IMX_8BIT, 0x0348, 0x06}, + {IMX_8BIT, 0x0349, 0x77}, + {IMX_8BIT, 0x034A, 0x04}, + {IMX_8BIT, 0x034B, 0x79}, + {IMX_8BIT, 0x034C, 0x05}, + {IMX_8BIT, 0x034D, 0x38}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x48}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x303D, 0x10}, + {IMX_8BIT, 0x303E, 0x5A}, + {IMX_8BIT, 0x3040, 0x00}, + {IMX_8BIT, 0x3041, 0x00}, + {IMX_8BIT, 0x3048, 0x00}, + {IMX_8BIT, 0x304C, 0x2F}, + {IMX_8BIT, 0x304D, 0x02}, + {IMX_8BIT, 0x3064, 0x92}, + {IMX_8BIT, 0x306A, 0x10}, + {IMX_8BIT, 0x309B, 0x00}, + {IMX_8BIT, 0x309E, 0x41}, + {IMX_8BIT, 0x30A0, 0x10}, + {IMX_8BIT, 0x30A1, 0x0B}, + {IMX_8BIT, 0x30B2, 0x00}, + {IMX_8BIT, 0x30D5, 0x00}, + {IMX_8BIT, 0x30D6, 0x00}, + {IMX_8BIT, 0x30D7, 0x00}, + {IMX_8BIT, 0x30D8, 0x00}, + {IMX_8BIT, 0x30D9, 0x00}, + {IMX_8BIT, 0x30DA, 0x00}, + {IMX_8BIT, 0x30DB, 0x00}, + {IMX_8BIT, 0x30DC, 0x00}, + {IMX_8BIT, 0x30DD, 0x00}, + {IMX_8BIT, 0x30DE, 0x00}, + {IMX_8BIT, 0x3102, 0x0C}, + {IMX_8BIT, 0x3103, 0x33}, + {IMX_8BIT, 0x3104, 0x18}, + {IMX_8BIT, 0x3105, 0x00}, + {IMX_8BIT, 0x3106, 0x65}, + {IMX_8BIT, 0x3107, 0x00}, + {IMX_8BIT, 0x3108, 0x06}, + {IMX_8BIT, 0x3109, 0x04}, + {IMX_8BIT, 0x310A, 0x04}, + {IMX_8BIT, 0x315C, 0x3D}, + {IMX_8BIT, 0x315D, 0x3C}, + {IMX_8BIT, 0x316E, 0x3E}, + {IMX_8BIT, 0x316F, 0x3D}, + /* Global timing */ + {IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */ + {IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */ + {IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */ + {IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */ + {IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */ + {IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */ + {IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */ + {IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */ + {IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */ + {IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */ + {IMX_8BIT, 0x330E, 0x03}, + {IMX_8BIT, 0x3318, 0x62}, + {IMX_8BIT, 0x3322, 0x09}, + {IMX_8BIT, 0x3342, 0x00}, + {IMX_8BIT, 0x3348, 0xE0}, + + {IMX_TOK_TERM, 0, 0}, +}; + +/********************** settings for imx - reference *********************/ +static struct imx_reg const imx132_init_settings[] = { + /* sw reset */ + { IMX_8BIT, 0x0100, 0x00 }, + { IMX_8BIT, 0x0103, 0x01 }, + { IMX_TOK_DELAY, 0, 5}, + { IMX_8BIT, 0x0103, 0x00 }, + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + GROUPED_PARAMETER_HOLD_DISABLE, + { IMX_TOK_TERM, 0, 0} +}; + +struct imx_resolution imx132_res_preview[] = { + { + .desc = "imx132_1080p_30fps", + .regs = imx132_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, +}; + +struct imx_resolution imx132_res_still[] = { + { + .desc = "imx132_1080p_30fps", + .regs = imx132_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, +}; + +struct imx_resolution imx132_res_video[] = { + { + .desc = "imx132_1336x1096_30fps", + .regs = imx132_1336x1096_30fps, + .width = 1336, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, + { + .desc = "imx132_1456x1096_30fps", + .regs = imx132_1456x1096_30fps, + .width = 1456, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, + { + .desc = "imx132_1636x1096_30fps", + .regs = imx132_1636x1096_30fps, + .width = 1636, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, + { + .desc = "imx132_1080p_30fps", + .regs = imx132_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, +}; +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx134.h b/drivers/staging/media/atomisp/i2c/imx/imx134.h new file mode 100644 index 0000000..cf35197 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx134.h @@ -0,0 +1,2464 @@ +#ifndef __IMX134_H__ +#define __IMX134_H__ + +/********************** imx134 setting - version 1 *********************/ +static struct imx_reg const imx134_init_settings[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Basic settings */ + { IMX_8BIT, 0x0105, 0x01 }, + { IMX_8BIT, 0x0220, 0x01 }, + { IMX_8BIT, 0x3302, 0x11 }, + { IMX_8BIT, 0x3833, 0x20 }, + { IMX_8BIT, 0x3893, 0x00 }, + { IMX_8BIT, 0x3906, 0x08 }, + { IMX_8BIT, 0x3907, 0x01 }, + { IMX_8BIT, 0x391B, 0x01 }, + { IMX_8BIT, 0x3C09, 0x01 }, + { IMX_8BIT, 0x600A, 0x00 }, + + /* Analog settings */ + { IMX_8BIT, 0x3008, 0xB0 }, + { IMX_8BIT, 0x320A, 0x01 }, + { IMX_8BIT, 0x320D, 0x10 }, + { IMX_8BIT, 0x3216, 0x2E }, + { IMX_8BIT, 0x322C, 0x02 }, + { IMX_8BIT, 0x3409, 0x0C }, + { IMX_8BIT, 0x340C, 0x2D }, + { IMX_8BIT, 0x3411, 0x39 }, + { IMX_8BIT, 0x3414, 0x1E }, + { IMX_8BIT, 0x3427, 0x04 }, + { IMX_8BIT, 0x3480, 0x1E }, + { IMX_8BIT, 0x3484, 0x1E }, + { IMX_8BIT, 0x3488, 0x1E }, + { IMX_8BIT, 0x348C, 0x1E }, + { IMX_8BIT, 0x3490, 0x1E }, + { IMX_8BIT, 0x3494, 0x1E }, + { IMX_8BIT, 0x3511, 0x8F }, + { IMX_8BIT, 0x3617, 0x2D }, + + GROUPED_PARAMETER_HOLD_DISABLE, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 3280x2464 8M 30fps, vendor provide */ +static struct imx_reg const imx134_8M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* clock setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0345, 0x00 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3279 */ + { IMX_8BIT, 0x0349, 0xCF }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0x9F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x0C }, /* x_output_size[15:8]: 3280*/ + { IMX_8BIT, 0x034D, 0xD0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x09 }, /* y_output_size[15:8]:2464 */ + { IMX_8BIT, 0x034F, 0xA0 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0C }, + { IMX_8BIT, 0x0355, 0xD0 }, + { IMX_8BIT, 0x0356, 0x09 }, + { IMX_8BIT, 0x0357, 0xA0 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x0C }, + { IMX_8BIT, 0x3311, 0xD0 }, + { IMX_8BIT, 0x3312, 0x09 }, + { IMX_8BIT, 0x3313, 0xA0 }, + { IMX_8BIT, 0x331C, 0x01 }, + { IMX_8BIT, 0x331D, 0xAE }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global timing setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration time setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/2 binning 30fps 1640x1232, vendor provide */ +static struct imx_reg const imx134_1640_1232_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0345, 0x00 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3279 */ + { IMX_8BIT, 0x0349, 0xCF }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0x9F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x06 }, /* x_output_size[15:8]:1640 */ + { IMX_8BIT, 0x034D, 0x68 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x04 }, /* y_output_size[15:8]:1232 */ + { IMX_8BIT, 0x034F, 0xD0 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x68 }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0xD0 }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x68 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0xD0 }, + + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x06 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/4 binning 30fps 820x616, vendor provide */ +static struct imx_reg const imx134_820_616_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x44 }, /* 4x4 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0345, 0x00 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3279 */ + { IMX_8BIT, 0x0349, 0xCF }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0x9F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x03 }, /* x_output_size[15:8]:820 */ + { IMX_8BIT, 0x034D, 0x34 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:616 */ + { IMX_8BIT, 0x034F, 0x68 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x03 }, + { IMX_8BIT, 0x0355, 0x34 }, + { IMX_8BIT, 0x0356, 0x02 }, + { IMX_8BIT, 0x0357, 0x68 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x03 }, + { IMX_8BIT, 0x3311, 0x34 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x68 }, + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/4 binning 30fps 820x552 */ +static struct imx_reg const imx134_820_552_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x44 }, /* 4x4 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0345, 0x00 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:128 */ + { IMX_8BIT, 0x0347, 0x80 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3280-1 */ + { IMX_8BIT, 0x0349, 0xCF }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2208+128-1 */ + { IMX_8BIT, 0x034B, 0x1F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x03 }, /* x_output_size[15:8]: */ + { IMX_8BIT, 0x034D, 0x34 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:616 */ + { IMX_8BIT, 0x034F, 0x28 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x03 }, + { IMX_8BIT, 0x0355, 0x34 }, + { IMX_8BIT, 0x0356, 0x02 }, + { IMX_8BIT, 0x0357, 0x28 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x03 }, + { IMX_8BIT, 0x3311, 0x34 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x28 }, + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/4 binning 30fps 720x592 */ +static struct imx_reg const imx134_720_592_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x44 }, /* 4x4 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:200 */ + { IMX_8BIT, 0x0345, 0xC8 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:40 */ + { IMX_8BIT, 0x0347, 0x28 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:2880+200-1 */ + { IMX_8BIT, 0x0349, 0x07 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2368+40-1 */ + { IMX_8BIT, 0x034B, 0x67 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x02 }, /* x_output_size[15:8]: */ + { IMX_8BIT, 0x034D, 0xD0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:616 */ + { IMX_8BIT, 0x034F, 0x50 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x02 }, + { IMX_8BIT, 0x0355, 0xD0 }, + { IMX_8BIT, 0x0356, 0x02 }, + { IMX_8BIT, 0x0357, 0x50 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x02 }, + { IMX_8BIT, 0x3311, 0xD0 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x50 }, + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +static struct imx_reg const imx134_752_616_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x44 }, /* 4x4 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:136 */ + { IMX_8BIT, 0x0345, 0x88 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3145+134-1 */ + { IMX_8BIT, 0x0349, 0x47 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0x9F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x02 }, /* x_output_size[15:8]: 752*/ + { IMX_8BIT, 0x034D, 0xF0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:616 */ + { IMX_8BIT, 0x034F, 0x68 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + + { IMX_8BIT, 0x0354, 0x02 }, + { IMX_8BIT, 0x0355, 0xF0 }, + { IMX_8BIT, 0x0356, 0x02 }, + { IMX_8BIT, 0x0357, 0x68 }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x02 }, + { IMX_8BIT, 0x3311, 0xF0 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x68 }, + + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 1424x1168 */ +static struct imx_reg const imx134_1424_1168_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* binning */ + { IMX_8BIT, 0x0391, 0x11 }, /* no binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x22 }, /* 34/16=2.125 */ + { IMX_8BIT, 0x4082, 0x00 }, /* ?? */ + { IMX_8BIT, 0x4083, 0x00 }, /* ?? */ + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:136 */ + { IMX_8BIT, 0x0345, 0x80 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3145+134-1 */ + { IMX_8BIT, 0x0349, 0x51 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0xB1 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x05 }, /* x_output_size[15:8]: 1424*/ + { IMX_8BIT, 0x034D, 0x90 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x04 }, /* y_output_size[15:8]:1168 */ + { IMX_8BIT, 0x034F, 0x90 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + + { IMX_8BIT, 0x0354, 0x0B }, + { IMX_8BIT, 0x0355, 0xD2 }, + { IMX_8BIT, 0x0356, 0x09 }, + { IMX_8BIT, 0x0357, 0xB2 }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x05 }, + { IMX_8BIT, 0x3311, 0x90 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x90 }, + + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x05 }, + { IMX_8BIT, 0x4085, 0x90 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x90 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/4 binning, 16/35 down scaling, 30fps, dvs */ +static struct imx_reg const imx134_240_196_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /*4x4 binning */ + { IMX_8BIT, 0x0391, 0x44 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x23 }, /* down scaling = 16/35 */ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x02 }, /* x_addr_start[15:8]:590 */ + { IMX_8BIT, 0x0345, 0x4E }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:366 */ + { IMX_8BIT, 0x0347, 0x6E }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0A }, /* x_addr_end[15:8]:2104+590-1 */ + { IMX_8BIT, 0x0349, 0x85 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:1720+366-1 */ + { IMX_8BIT, 0x034B, 0x25 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x00 }, /* x_output_size[15:8]: 240*/ + { IMX_8BIT, 0x034D, 0xF0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x00 }, /* y_output_size[15:8]:196 */ + { IMX_8BIT, 0x034F, 0xC4 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x02 }, /* crop_x: 526 */ + { IMX_8BIT, 0x0355, 0x0E }, + { IMX_8BIT, 0x0356, 0x01 }, /* crop_y: 430 */ + { IMX_8BIT, 0x0357, 0xAE }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x00 }, + { IMX_8BIT, 0x3311, 0xF0 }, + { IMX_8BIT, 0x3312, 0x00 }, + { IMX_8BIT, 0x3313, 0xC4 }, + + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x4C }, + + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0xF0 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0xC4 }, + + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x0A }, + { IMX_8BIT, 0x0203, 0x88 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/2 binning, 16/38 downscaling, 30fps, dvs */ +static struct imx_reg const imx134_448_366_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* 2x2 binning */ + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x26 }, /* down scaling = 16/38 */ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x02 }, /* x_addr_start[15:8]:590 */ + { IMX_8BIT, 0x0345, 0x4E }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:366 */ + { IMX_8BIT, 0x0347, 0x6E }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0A }, /* x_addr_end[15:8]:2128+590-1 */ + { IMX_8BIT, 0x0349, 0x9D }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:1740+366-1 */ + { IMX_8BIT, 0x034B, 0x39 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x01 }, /* x_output_size[15:8]: 448*/ + { IMX_8BIT, 0x034D, 0xC0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x01 }, /* y_output_size[15:8]:366 */ + { IMX_8BIT, 0x034F, 0x6E }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x04 }, /* crop_x: 1064 */ + { IMX_8BIT, 0x0355, 0x28 }, + { IMX_8BIT, 0x0356, 0x03 }, /* crop_y: 870 */ + { IMX_8BIT, 0x0357, 0x66 }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x01 }, + { IMX_8BIT, 0x3311, 0xC0 }, + { IMX_8BIT, 0x3312, 0x01 }, + { IMX_8BIT, 0x3313, 0x6E }, + + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + + { IMX_8BIT, 0x4084, 0x01 }, + { IMX_8BIT, 0x4085, 0xC0 }, + { IMX_8BIT, 0x4086, 0x01 }, + { IMX_8BIT, 0x4087, 0x6E }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 2336x1312, 30fps, for 1080p dvs, vendor provide */ +static struct imx_reg const imx134_2336_1312_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* disable binning */ + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x16 }, /* down scaling = 16/22 = 8/11 */ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:34 */ + { IMX_8BIT, 0x0345, 0x22 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:332 */ + { IMX_8BIT, 0x0347, 0x4C }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3245 */ + { IMX_8BIT, 0x0349, 0xAD }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2135 */ + { IMX_8BIT, 0x034B, 0x57 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x09 }, /* x_output_size[15:8]:2336 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x05 }, /* y_output_size[15:8]:1312 */ + { IMX_8BIT, 0x034F, 0x20 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0C }, + { IMX_8BIT, 0x0355, 0x8C }, + { IMX_8BIT, 0x0356, 0x07 }, + { IMX_8BIT, 0x0357, 0x0C }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x09 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x05 }, + { IMX_8BIT, 0x3313, 0x20 }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xEB }, + { IMX_8BIT, 0x4084, 0x09 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x05 }, + { IMX_8BIT, 0x4087, 0x20 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 1920x1080, 30fps, for 720p still capture */ +static struct imx_reg const imx134_1936_1096_30fps_v1[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* disable binning */ + { IMX_8BIT, 0x0391, 0x11 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1A }, /* downscaling 16/26*/ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:64 */ + { IMX_8BIT, 0x0345, 0x40 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:340 */ + { IMX_8BIT, 0x0347, 0x54 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3209 */ + { IMX_8BIT, 0x0349, 0x89 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2121 */ + { IMX_8BIT, 0x034B, 0x49 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x07 }, /* x_output_size[15:8]:1936 */ + { IMX_8BIT, 0x034D, 0x90 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x04 }, /* y_output_size[15:8]:1096 */ + { IMX_8BIT, 0x034F, 0x48 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0C }, /* crop x:3146 */ + { IMX_8BIT, 0x0355, 0x4A }, + { IMX_8BIT, 0x0356, 0x06 }, /* xrop y:1782 */ + { IMX_8BIT, 0x0357, 0xF6 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x07 }, + { IMX_8BIT, 0x3311, 0x80 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x38 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x1E }, + { IMX_8BIT, 0x4084, 0x07 }, + { IMX_8BIT, 0x4085, 0x80 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x38 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 1920x1080, 30fps, for 720p still capture, vendor provide */ +static struct imx_reg const imx134_1936_1096_30fps_v2[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* disable binning */ + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1B }, /* downscaling 16/27*/ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:64 */ + { IMX_8BIT, 0x0345, 0x06 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:340 */ + { IMX_8BIT, 0x0347, 0x34 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3209 */ + { IMX_8BIT, 0x0349, 0xC9 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2121 */ + { IMX_8BIT, 0x034B, 0x6F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x07 }, /* x_output_size[15:8]:1936 */ + { IMX_8BIT, 0x034D, 0x90 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x04 }, /* y_output_size[15:8]:1096 */ + { IMX_8BIT, 0x034F, 0x48 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0C }, /* crop x:3146 */ + { IMX_8BIT, 0x0355, 0xC4 }, + { IMX_8BIT, 0x0356, 0x07 }, /* xrop y:1782 */ + { IMX_8BIT, 0x0357, 0x3A }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x07 }, /* decide by mode and output size */ + { IMX_8BIT, 0x3311, 0x90 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x48 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x1E }, + { IMX_8BIT, 0x4084, 0x07 }, + { IMX_8BIT, 0x4085, 0x90 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x48 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 1296x736, 30fps, for 720p still capture, vendor provide */ +static struct imx_reg const imx134_1296_736_30fps_v2[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x14 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:40 */ + { IMX_8BIT, 0x0345, 0x14 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:332 */ + { IMX_8BIT, 0x0347, 0x38 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3239 */ + { IMX_8BIT, 0x0349, 0xBB }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2131 */ + { IMX_8BIT, 0x034B, 0x67 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x05 }, /* x_output_size[15:8]:1280 */ + { IMX_8BIT, 0x034D, 0x10 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:720 */ + { IMX_8BIT, 0x034F, 0xE0 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x54 }, + { IMX_8BIT, 0x0356, 0x03 }, + { IMX_8BIT, 0x0357, 0x98 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x05 }, + { IMX_8BIT, 0x3311, 0x10 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0xE0 }, + { IMX_8BIT, 0x331C, 0x01 }, + { IMX_8BIT, 0x331D, 0x10 }, + { IMX_8BIT, 0x4084, 0x05 }, + { IMX_8BIT, 0x4085, 0x10 }, + { IMX_8BIT, 0x4086, 0x02 }, + { IMX_8BIT, 0x4087, 0xE0 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 1280x720, 30fps, for 720p dvs, vendor provide */ +static struct imx_reg const imx134_1568_880_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:72 */ + { IMX_8BIT, 0x0345, 0x48 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:356 */ + { IMX_8BIT, 0x0347, 0x64 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3207 */ + { IMX_8BIT, 0x0349, 0x87 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2115 */ + { IMX_8BIT, 0x034B, 0x43 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x06 }, /* x_output_size[15:8]:1568 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x03 }, /* y_output_size[15:8]:880 */ + { IMX_8BIT, 0x034F, 0x70 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x03 }, + { IMX_8BIT, 0x0357, 0x70 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x70 }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xF2 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +static struct imx_reg const imx134_1568_876_60fps_0625[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0x8F }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:72 */ + { IMX_8BIT, 0x0345, 0x48 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:356 */ + { IMX_8BIT, 0x0347, 0x64 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3207 */ + { IMX_8BIT, 0x0349, 0x87 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2115 */ + { IMX_8BIT, 0x034B, 0x3B }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x06 }, /* x_output_size[15:8]:1568 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x03 }, /* y_output_size[15:8]:880 */ + { IMX_8BIT, 0x034F, 0x6C }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x03 }, + { IMX_8BIT, 0x0357, 0x6C }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x6C }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xF2 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x6F }, + { IMX_8BIT, 0x0831, 0x27 }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x2F }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x2F }, + { IMX_8BIT, 0x0836, 0x9F }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + + +/* 4 lane for 720p dvs, vendor provide */ +static struct imx_reg const imx134_1568_880[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xC8 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:72 */ + { IMX_8BIT, 0x0345, 0x48 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:356 */ + { IMX_8BIT, 0x0347, 0x64 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3207 */ + { IMX_8BIT, 0x0349, 0x87 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2115 */ + { IMX_8BIT, 0x034B, 0x43 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x06 }, /* x_output_size[15:8]:1568 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x03 }, /* y_output_size[15:8]:880 */ + { IMX_8BIT, 0x034F, 0x70 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x03 }, + { IMX_8BIT, 0x0357, 0x70 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x70 }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xF2 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x5F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x37 }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xBF }, + { IMX_8BIT, 0x0837, 0x3F }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; +/* 4 lane for 480p dvs, default 60fps, vendor provide */ +static struct imx_reg const imx134_880_592[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xC8 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1D }, /* downscaling ratio = 16/29 */ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:44 */ + { IMX_8BIT, 0x0345, 0x2C }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:160 */ + { IMX_8BIT, 0x0347, 0xA0 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3235 */ + { IMX_8BIT, 0x0349, 0xA3 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2307 */ + { IMX_8BIT, 0x034B, 0x03 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x03 }, /* x_output_size[15:8]:880 */ + { IMX_8BIT, 0x034D, 0x70 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:592 */ + { IMX_8BIT, 0x034F, 0x50 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x3C }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x32 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x03 }, + { IMX_8BIT, 0x3311, 0x70 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x50 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x4C }, + { IMX_8BIT, 0x4084, 0x03 }, + { IMX_8BIT, 0x4085, 0x70 }, + { IMX_8BIT, 0x4086, 0x02 }, + { IMX_8BIT, 0x4087, 0x50 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x5F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x37 }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xBF }, + { IMX_8BIT, 0x0837, 0x3F }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x05 }, + { IMX_8BIT, 0x0203, 0x42 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; +static struct imx_reg const imx134_2336_1308_60fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xC8 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x11 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x01 }, /* x_addr_start[15:8]:72 */ + { IMX_8BIT, 0x0345, 0xD8 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x02 }, /* y_addr_start[15:8]:356 */ + { IMX_8BIT, 0x0347, 0x44 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0A }, /* x_addr_end[15:8]:3207 */ + { IMX_8BIT, 0x0349, 0xF7 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x07 }, /* y_addr_end[15:8]:2107 */ + { IMX_8BIT, 0x034B, 0x5F+4 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x09 }, /* x_output_size[15:8]:1568 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x05 }, /* y_output_size[15:8]:876 */ + { IMX_8BIT, 0x034F, 0x1C+4 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x09 }, + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x05 }, + { IMX_8BIT, 0x0357, 0x1C+4 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x09 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x05 }, + { IMX_8BIT, 0x3313, 0x1C+4 }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xE8 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x5F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x37 }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xBF }, + { IMX_8BIT, 0x0837, 0x3F }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x05 }, + { IMX_8BIT, 0x0203, 0x42 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +struct imx_resolution imx134_res_preview[] = { + { + .desc = "imx134_CIF_30fps", + .regs = imx134_720_592_30fps, + .width = 720, + .height = 592, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_820_552_30fps_preview", + .regs = imx134_820_552_30fps, + .width = 820, + .height = 552, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_820_616_preview_30fps", + .regs = imx134_820_616_30fps, + .width = 820, + .height = 616, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_1080p_preview_30fps", + .regs = imx134_1936_1096_30fps_v2, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, + { + .desc = "imx134_1640_1232_preview_30fps", + .regs = imx134_1640_1232_30fps, + .width = 1640, + .height = 1232, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_8M_preview_30fps", + .regs = imx134_8M_30fps, + .width = 3280, + .height = 2464, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, +}; + +struct imx_resolution imx134_res_still[] = { + { + .desc = "imx134_CIF_30fps", + .regs = imx134_1424_1168_30fps, + .width = 1424, + .height = 1168, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_VGA_still_30fps", + .regs = imx134_1640_1232_30fps, + .width = 1640, + .height = 1232, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_1080p_still_30fps", + .regs = imx134_1936_1096_30fps_v2, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, + { + .desc = "imx134_1640_1232_still_30fps", + .regs = imx134_1640_1232_30fps, + .width = 1640, + .height = 1232, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_8M_still_30fps", + .regs = imx134_8M_30fps, + .width = 3280, + .height = 2464, + .fps_options = { + { + /* WORKAROUND for FW performance limitation */ + .fps = 8, + .pixels_per_line = 6400, + .lines_per_frame = 5312, + }, + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, +}; + +struct imx_resolution imx134_res_video[] = { + { + .desc = "imx134_QCIF_DVS_30fps", + .regs = imx134_240_196_30fps, + .width = 240, + .height = 196, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_CIF_DVS_30fps", + .regs = imx134_448_366_30fps, + .width = 448, + .height = 366, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_VGA_30fps", + .regs = imx134_820_616_30fps, + .width = 820, + .height = 616, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_480p", + .regs = imx134_880_592, + .width = 880, + .height = 592, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2700, + }, + { + .fps = 60, + .pixels_per_line = 3600, + .lines_per_frame = 1350, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_1568_880", + .regs = imx134_1568_880, + .width = 1568, + .height = 880, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2700, + }, + { + .fps = 60, + .pixels_per_line = 3600, + .lines_per_frame = 1350, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_1080p_dvs_30fps", + .regs = imx134_2336_1312_30fps, + .width = 2336, + .height = 1312, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, + { + .desc = "imx134_1080p_dvs_60fps", + .regs = imx134_2336_1308_60fps, + .width = 2336, + .height = 1312, + .fps_options = { + { + .fps = 60, + .pixels_per_line = 3600, + .lines_per_frame = 1350, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, + { + /*This setting only be used for SDV mode*/ + .desc = "imx134_8M_sdv_30fps", + .regs = imx134_8M_30fps, + .width = 3280, + .height = 2464, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, +}; + +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx135.h b/drivers/staging/media/atomisp/i2c/imx/imx135.h new file mode 100644 index 0000000..58b43af --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx135.h @@ -0,0 +1,3374 @@ +/* + * Support for Sony IMX camera sensor. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __IMX135_H__ +#define __IMX135_H__ + +#include "common.h" + +#define IMX_SC_CMMN_CHIP_ID_H 0x0016 +#define IMX_SC_CMMN_CHIP_ID_L 0x0017 + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define IMX_FOCAL_LENGTH_DEFAULT 0x1710064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define IMX_F_NUMBER_DEFAULT 0x16000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define IMX_F_NUMBER_RANGE 0x160a160a + +#define GROUPED_PARAMETER_HOLD_ENABLE {IMX_8BIT, 0x0104, 0x1} +#define GROUPED_PARAMETER_HOLD_DISABLE {IMX_8BIT, 0x0104, 0x0} + +#define IMX135_EMBEDDED_DATA_LINE_NUM 2 +#define IMX135_OUTPUT_DATA_FORMAT_REG 0x0112 +#define IMX135_OUTPUT_FORMAT_RAW10 0x0a0a +/* + * We use three different MIPI rates for our modes based on the resolution and + * FPS requirements. So we have three PLL configurationa and these are based + * on the EMC friendly MIPI values. + * + * Maximum clock: Pix clock @ 360.96MHz MIPI @ 451.2MHz 902.4mbps + * Reduced clock: Pix clock @ 273.00MHz MIPI @ 342.0MHz 684.0mbps + * Binning modes: Pix clock @ 335.36MHz MIPI @ 209.6MHz 419.2mbps + * Global Timing registers are based on the data rates and these are part of + * the below clock definitions. + */ +/* MIPI 499.2MHz 998.4mbps PIXCLK: 399.36MHz */ +#define PLL_SETTINGS_FOR_MIPI_499_2MHZ_SALTBAY \ + {IMX_8BIT, 0x011e, 0x13}, \ + {IMX_8BIT, 0x011f, 0x33}, \ + {IMX_8BIT, 0x0301, 0x05}, \ + {IMX_8BIT, 0x0303, 0x01}, \ + {IMX_8BIT, 0x0305, 0x0c}, \ + {IMX_8BIT, 0x0309, 0x05}, \ + {IMX_8BIT, 0x030b, 0x01}, \ + {IMX_8BIT, 0x030c, 0x02}, \ + {IMX_8BIT, 0x030d, 0x70}, \ + {IMX_8BIT, 0x030e, 0x01}, \ + {IMX_8BIT, 0x3a06, 0x11}, \ + {IMX_8BIT, 0x0830, 0x7f}, \ + {IMX_8BIT, 0x0831, 0x37}, \ + {IMX_8BIT, 0x0832, 0x67}, \ + {IMX_8BIT, 0x0833, 0x3f}, \ + {IMX_8BIT, 0x0834, 0x3f}, \ + {IMX_8BIT, 0x0835, 0x47}, \ + {IMX_8BIT, 0x0836, 0xdf}, \ + {IMX_8BIT, 0x0837, 0x47}, \ + {IMX_8BIT, 0x0839, 0x1f}, \ + {IMX_8BIT, 0x083a, 0x17}, \ + {IMX_8BIT, 0x083b, 0x02} + +/* MIPI 451.2MHz 902.4mbps PIXCLK: 360.96MHz */ +#define PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY \ + {IMX_8BIT, 0x011e, 0x13}, \ + {IMX_8BIT, 0x011f, 0x33}, \ + {IMX_8BIT, 0x0301, 0x05}, \ + {IMX_8BIT, 0x0303, 0x01}, \ + {IMX_8BIT, 0x0305, 0x0c}, \ + {IMX_8BIT, 0x0309, 0x05}, \ + {IMX_8BIT, 0x030b, 0x01}, \ + {IMX_8BIT, 0x030c, 0x02}, \ + {IMX_8BIT, 0x030d, 0x34}, \ + {IMX_8BIT, 0x030e, 0x01}, \ + {IMX_8BIT, 0x3a06, 0x11}, \ + {IMX_8BIT, 0x0830, 0x7f}, \ + {IMX_8BIT, 0x0831, 0x37}, \ + {IMX_8BIT, 0x0832, 0x67}, \ + {IMX_8BIT, 0x0833, 0x3f}, \ + {IMX_8BIT, 0x0834, 0x3f}, \ + {IMX_8BIT, 0x0835, 0x47}, \ + {IMX_8BIT, 0x0836, 0xdf}, \ + {IMX_8BIT, 0x0837, 0x47}, \ + {IMX_8BIT, 0x0839, 0x1f}, \ + {IMX_8BIT, 0x083a, 0x17}, \ + {IMX_8BIT, 0x083b, 0x02} + +/* MIPI 209.6MHz, 419.2mbps PIXCLK: 335.36 MHz */ +#define PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY \ + {IMX_8BIT, 0x011e, 0x13}, \ + {IMX_8BIT, 0x011f, 0x33}, \ + {IMX_8BIT, 0x0301, 0x05}, \ + {IMX_8BIT, 0x0303, 0x01}, \ + {IMX_8BIT, 0x0305, 0x06}, \ + {IMX_8BIT, 0x0309, 0x05}, \ + {IMX_8BIT, 0x030b, 0x02}, \ + {IMX_8BIT, 0x030c, 0x01}, \ + {IMX_8BIT, 0x030d, 0x06}, \ + {IMX_8BIT, 0x030e, 0x01}, \ + {IMX_8BIT, 0x3a06, 0x12}, \ + {IMX_8BIT, 0x0830, 0x5f}, \ + {IMX_8BIT, 0x0831, 0x1f}, \ + {IMX_8BIT, 0x0832, 0x3f}, \ + {IMX_8BIT, 0x0833, 0x1f}, \ + {IMX_8BIT, 0x0834, 0x1f}, \ + {IMX_8BIT, 0x0835, 0x17}, \ + {IMX_8BIT, 0x0836, 0x67}, \ + {IMX_8BIT, 0x0837, 0x27}, \ + {IMX_8BIT, 0x0839, 0x1f}, \ + {IMX_8BIT, 0x083a, 0x17}, \ + {IMX_8BIT, 0x083b, 0x02} + +/* MIPI 342MHz 684mbps PIXCLK: 273.6MHz */ +#define PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY \ + {IMX_8BIT, 0x011e, 0x13}, \ + {IMX_8BIT, 0x011f, 0x33}, \ + {IMX_8BIT, 0x0301, 0x05}, \ + {IMX_8BIT, 0x0303, 0x01}, \ + {IMX_8BIT, 0x0305, 0x08}, \ + {IMX_8BIT, 0x0309, 0x05}, \ + {IMX_8BIT, 0x030b, 0x01}, \ + {IMX_8BIT, 0x030c, 0x01}, \ + {IMX_8BIT, 0x030d, 0x1d}, \ + {IMX_8BIT, 0x030e, 0x01}, \ + {IMX_8BIT, 0x3a06, 0x11}, \ + {IMX_8BIT, 0x0830, 0x77}, \ + {IMX_8BIT, 0x0831, 0x2f}, \ + {IMX_8BIT, 0x0832, 0x4f}, \ + {IMX_8BIT, 0x0833, 0x37}, \ + {IMX_8BIT, 0x0834, 0x2f}, \ + {IMX_8BIT, 0x0835, 0x37}, \ + {IMX_8BIT, 0x0836, 0xa7}, \ + {IMX_8BIT, 0x0837, 0x37}, \ + {IMX_8BIT, 0x0839, 0x1f}, \ + {IMX_8BIT, 0x083a, 0x17}, \ + {IMX_8BIT, 0x083b, 0x02} + +/* Basic settings: Applied only once after the sensor power up */ +static struct imx_reg const imx135_init_settings[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + { IMX_8BIT, 0x0220, 0x01}, + { IMX_8BIT, 0x3008, 0xB0}, + { IMX_8BIT, 0x320A, 0x01}, + { IMX_8BIT, 0x320D, 0x10}, + { IMX_8BIT, 0x3216, 0x2E}, + { IMX_8BIT, 0x3230, 0x0A}, + { IMX_8BIT, 0x3228, 0x05}, + { IMX_8BIT, 0x3229, 0x02}, + { IMX_8BIT, 0x322C, 0x02}, + { IMX_8BIT, 0x3302, 0x10}, + { IMX_8BIT, 0x3390, 0x45}, + { IMX_8BIT, 0x3409, 0x0C}, + { IMX_8BIT, 0x340B, 0xF5}, + { IMX_8BIT, 0x340C, 0x2D}, + { IMX_8BIT, 0x3412, 0x41}, + { IMX_8BIT, 0x3413, 0xAD}, + { IMX_8BIT, 0x3414, 0x1E}, + { IMX_8BIT, 0x3427, 0x04}, + { IMX_8BIT, 0x3480, 0x1E}, + { IMX_8BIT, 0x3484, 0x1E}, + { IMX_8BIT, 0x3488, 0x1E}, + { IMX_8BIT, 0x348C, 0x1E}, + { IMX_8BIT, 0x3490, 0x1E}, + { IMX_8BIT, 0x3494, 0x1E}, + { IMX_8BIT, 0x349C, 0x38}, + { IMX_8BIT, 0x34A3, 0x38}, + { IMX_8BIT, 0x3511, 0x8F}, + { IMX_8BIT, 0x3518, 0x00}, + { IMX_8BIT, 0x3519, 0x94}, + { IMX_8BIT, 0x3833, 0x20}, + { IMX_8BIT, 0x3893, 0x01}, + { IMX_8BIT, 0x38C2, 0x08}, + { IMX_8BIT, 0x38C3, 0x08}, + { IMX_8BIT, 0x3C09, 0x01}, + { IMX_8BIT, 0x4000, 0x0E}, + { IMX_8BIT, 0x4300, 0x00}, + { IMX_8BIT, 0x4316, 0x12}, + { IMX_8BIT, 0x4317, 0x22}, + { IMX_8BIT, 0x4318, 0x00}, + { IMX_8BIT, 0x4319, 0x00}, + { IMX_8BIT, 0x431A, 0x00}, + { IMX_8BIT, 0x4324, 0x03}, + { IMX_8BIT, 0x4325, 0x20}, + { IMX_8BIT, 0x4326, 0x03}, + { IMX_8BIT, 0x4327, 0x84}, + { IMX_8BIT, 0x4328, 0x03}, + { IMX_8BIT, 0x4329, 0x20}, + { IMX_8BIT, 0x432A, 0x03}, + { IMX_8BIT, 0x432B, 0x84}, + { IMX_8BIT, 0x432C, 0x01}, + { IMX_8BIT, 0x4401, 0x3F}, + { IMX_8BIT, 0x4402, 0xFF}, + { IMX_8BIT, 0x4412, 0x3F}, + { IMX_8BIT, 0x4413, 0xFF}, + { IMX_8BIT, 0x441D, 0x28}, + { IMX_8BIT, 0x4444, 0x00}, + { IMX_8BIT, 0x4445, 0x00}, + { IMX_8BIT, 0x4446, 0x3F}, + { IMX_8BIT, 0x4447, 0xFF}, + { IMX_8BIT, 0x4452, 0x00}, + { IMX_8BIT, 0x4453, 0xA0}, + { IMX_8BIT, 0x4454, 0x08}, + { IMX_8BIT, 0x4455, 0x00}, + { IMX_8BIT, 0x4458, 0x18}, + { IMX_8BIT, 0x4459, 0x18}, + { IMX_8BIT, 0x445A, 0x3F}, + { IMX_8BIT, 0x445B, 0x3A}, + { IMX_8BIT, 0x4462, 0x00}, + { IMX_8BIT, 0x4463, 0x00}, + { IMX_8BIT, 0x4464, 0x00}, + { IMX_8BIT, 0x4465, 0x00}, + { IMX_8BIT, 0x446E, 0x01}, + { IMX_8BIT, 0x4500, 0x1F}, + { IMX_8BIT, 0x600a, 0x00}, + { IMX_8BIT, 0x380a, 0x00}, + { IMX_8BIT, 0x380b, 0x00}, + { IMX_8BIT, 0x4103, 0x00}, + { IMX_8BIT, 0x4243, 0x9a}, + { IMX_8BIT, 0x4330, 0x01}, + { IMX_8BIT, 0x4331, 0x90}, + { IMX_8BIT, 0x4332, 0x02}, + { IMX_8BIT, 0x4333, 0x58}, + { IMX_8BIT, 0x4334, 0x03}, + { IMX_8BIT, 0x4335, 0x20}, + { IMX_8BIT, 0x4336, 0x03}, + { IMX_8BIT, 0x4337, 0x84}, + { IMX_8BIT, 0x433C, 0x01}, + { IMX_8BIT, 0x4340, 0x02}, + { IMX_8BIT, 0x4341, 0x58}, + { IMX_8BIT, 0x4342, 0x03}, + { IMX_8BIT, 0x4343, 0x52}, + { IMX_8BIT, 0x4364, 0x0b}, + { IMX_8BIT, 0x4368, 0x00}, + { IMX_8BIT, 0x4369, 0x0f}, + { IMX_8BIT, 0x436a, 0x03}, + { IMX_8BIT, 0x436b, 0xa8}, + { IMX_8BIT, 0x436c, 0x00}, + { IMX_8BIT, 0x436d, 0x00}, + { IMX_8BIT, 0x436e, 0x00}, + { IMX_8BIT, 0x436f, 0x06}, + { IMX_8BIT, 0x4281, 0x21}, + { IMX_8BIT, 0x4282, 0x18}, + { IMX_8BIT, 0x4283, 0x04}, + { IMX_8BIT, 0x4284, 0x08}, + { IMX_8BIT, 0x4287, 0x7f}, + { IMX_8BIT, 0x4288, 0x08}, + { IMX_8BIT, 0x428c, 0x08}, + { IMX_8BIT, 0x4297, 0x00}, + { IMX_8BIT, 0x4299, 0x7E}, + { IMX_8BIT, 0x42A4, 0xFB}, + { IMX_8BIT, 0x42A5, 0x7E}, + { IMX_8BIT, 0x42A6, 0xDF}, + { IMX_8BIT, 0x42A7, 0xB7}, + { IMX_8BIT, 0x42AF, 0x03}, + { IMX_8BIT, 0x4207, 0x03}, + { IMX_8BIT, 0x4218, 0x00}, + { IMX_8BIT, 0x421B, 0x20}, + { IMX_8BIT, 0x421F, 0x04}, + { IMX_8BIT, 0x4222, 0x02}, + { IMX_8BIT, 0x4223, 0x22}, + { IMX_8BIT, 0x422E, 0x54}, + { IMX_8BIT, 0x422F, 0xFB}, + { IMX_8BIT, 0x4230, 0xFF}, + { IMX_8BIT, 0x4231, 0xFE}, + { IMX_8BIT, 0x4232, 0xFF}, + { IMX_8BIT, 0x4235, 0x58}, + { IMX_8BIT, 0x4236, 0xF7}, + { IMX_8BIT, 0x4237, 0xFD}, + { IMX_8BIT, 0x4239, 0x4E}, + { IMX_8BIT, 0x423A, 0xFC}, + { IMX_8BIT, 0x423B, 0xFD}, + { IMX_8BIT, 0x4300, 0x00}, + { IMX_8BIT, 0x4316, 0x12}, + { IMX_8BIT, 0x4317, 0x22}, + { IMX_8BIT, 0x4318, 0x00}, + { IMX_8BIT, 0x4319, 0x00}, + { IMX_8BIT, 0x431A, 0x00}, + { IMX_8BIT, 0x4324, 0x03}, + { IMX_8BIT, 0x4325, 0x20}, + { IMX_8BIT, 0x4326, 0x03}, + { IMX_8BIT, 0x4327, 0x84}, + { IMX_8BIT, 0x4328, 0x03}, + { IMX_8BIT, 0x4329, 0x20}, + { IMX_8BIT, 0x432A, 0x03}, + { IMX_8BIT, 0x432B, 0x20}, + { IMX_8BIT, 0x432C, 0x01}, + { IMX_8BIT, 0x432D, 0x01}, + { IMX_8BIT, 0x4338, 0x02}, + { IMX_8BIT, 0x4339, 0x00}, + { IMX_8BIT, 0x433A, 0x00}, + { IMX_8BIT, 0x433B, 0x02}, + { IMX_8BIT, 0x435A, 0x03}, + { IMX_8BIT, 0x435B, 0x84}, + { IMX_8BIT, 0x435E, 0x01}, + { IMX_8BIT, 0x435F, 0xFF}, + { IMX_8BIT, 0x4360, 0x01}, + { IMX_8BIT, 0x4361, 0xF4}, + { IMX_8BIT, 0x4362, 0x03}, + { IMX_8BIT, 0x4363, 0x84}, + { IMX_8BIT, 0x437B, 0x01}, + { IMX_8BIT, 0x4400, 0x00}, /* STATS off ISP do not support STATS*/ + { IMX_8BIT, 0x4401, 0x3F}, + { IMX_8BIT, 0x4402, 0xFF}, + { IMX_8BIT, 0x4404, 0x13}, + { IMX_8BIT, 0x4405, 0x26}, + { IMX_8BIT, 0x4406, 0x07}, + { IMX_8BIT, 0x4408, 0x20}, + { IMX_8BIT, 0x4409, 0xE5}, + { IMX_8BIT, 0x440A, 0xFB}, + { IMX_8BIT, 0x440C, 0xF6}, + { IMX_8BIT, 0x440D, 0xEA}, + { IMX_8BIT, 0x440E, 0x20}, + { IMX_8BIT, 0x4410, 0x00}, + { IMX_8BIT, 0x4411, 0x00}, + { IMX_8BIT, 0x4412, 0x3F}, + { IMX_8BIT, 0x4413, 0xFF}, + { IMX_8BIT, 0x4414, 0x1F}, + { IMX_8BIT, 0x4415, 0xFF}, + { IMX_8BIT, 0x4416, 0x20}, + { IMX_8BIT, 0x4417, 0x00}, + { IMX_8BIT, 0x4418, 0x1F}, + { IMX_8BIT, 0x4419, 0xFF}, + { IMX_8BIT, 0x441A, 0x20}, + { IMX_8BIT, 0x441B, 0x00}, + { IMX_8BIT, 0x441D, 0x40}, + { IMX_8BIT, 0x441E, 0x1E}, + { IMX_8BIT, 0x441F, 0x38}, + { IMX_8BIT, 0x4420, 0x01}, + { IMX_8BIT, 0x4444, 0x00}, + { IMX_8BIT, 0x4445, 0x00}, + { IMX_8BIT, 0x4446, 0x1D}, + { IMX_8BIT, 0x4447, 0xF9}, + { IMX_8BIT, 0x4452, 0x00}, + { IMX_8BIT, 0x4453, 0xA0}, + { IMX_8BIT, 0x4454, 0x08}, + { IMX_8BIT, 0x4455, 0x00}, + { IMX_8BIT, 0x4456, 0x0F}, + { IMX_8BIT, 0x4457, 0xFF}, + { IMX_8BIT, 0x4458, 0x18}, + { IMX_8BIT, 0x4459, 0x18}, + { IMX_8BIT, 0x445A, 0x3F}, + { IMX_8BIT, 0x445B, 0x3A}, + { IMX_8BIT, 0x445C, 0x00}, + { IMX_8BIT, 0x445D, 0x28}, + { IMX_8BIT, 0x445E, 0x01}, + { IMX_8BIT, 0x445F, 0x90}, + { IMX_8BIT, 0x4460, 0x00}, + { IMX_8BIT, 0x4461, 0x60}, + { IMX_8BIT, 0x4462, 0x00}, + { IMX_8BIT, 0x4463, 0x00}, + { IMX_8BIT, 0x4464, 0x00}, + { IMX_8BIT, 0x4465, 0x00}, + { IMX_8BIT, 0x446C, 0x00}, + { IMX_8BIT, 0x446D, 0x00}, + { IMX_8BIT, 0x446E, 0x00}, + { IMX_8BIT, 0x452A, 0x02}, + { IMX_8BIT, 0x0712, 0x01}, + { IMX_8BIT, 0x0713, 0x00}, + { IMX_8BIT, 0x0714, 0x01}, + { IMX_8BIT, 0x0715, 0x00}, + { IMX_8BIT, 0x0716, 0x01}, + { IMX_8BIT, 0x0717, 0x00}, + { IMX_8BIT, 0x0718, 0x01}, + { IMX_8BIT, 0x0719, 0x00}, + { IMX_8BIT, 0x4500, 0x1F }, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + { IMX_8BIT, 0x0205, 0x00}, + { IMX_8BIT, 0x020E, 0x01}, + { IMX_8BIT, 0x020F, 0x00}, + { IMX_8BIT, 0x0210, 0x02}, + { IMX_8BIT, 0x0211, 0x00}, + { IMX_8BIT, 0x0212, 0x02}, + { IMX_8BIT, 0x0213, 0x00}, + { IMX_8BIT, 0x0214, 0x01}, + { IMX_8BIT, 0x0215, 0x00}, + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00}, + { IMX_8BIT, 0x0231, 0x00}, + { IMX_8BIT, 0x0233, 0x00}, + { IMX_8BIT, 0x0234, 0x00}, + { IMX_8BIT, 0x0235, 0x40}, + { IMX_8BIT, 0x0238, 0x00}, + { IMX_8BIT, 0x0239, 0x04}, + { IMX_8BIT, 0x023B, 0x00}, + { IMX_8BIT, 0x023C, 0x01}, + { IMX_8BIT, 0x33B0, 0x04}, + { IMX_8BIT, 0x33B1, 0x00}, + { IMX_8BIT, 0x33B3, 0x00}, + { IMX_8BIT, 0x33B4, 0x01}, + { IMX_8BIT, 0x3800, 0x00}, + GROUPED_PARAMETER_HOLD_DISABLE, + { IMX_TOK_TERM, 0, 0} +}; + +/********* Preview, continuous capture and still modes *****************/ + +static struct imx_reg const imx135_13m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size Setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 0, 0, 4207,3119 4208x3120 */ + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x00}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x6F}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x2F}, + {IMX_8BIT, 0x034C, 0x10}, + {IMX_8BIT, 0x034D, 0x70}, + {IMX_8BIT, 0x034E, 0x0C}, + {IMX_8BIT, 0x034F, 0x30}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* 4208x3120 */ + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x0C}, + {IMX_8BIT, 0x0357, 0x30}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x10}, + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x0C}, + {IMX_8BIT, 0x3313, 0x30}, + {IMX_8BIT, 0x331C, 0x00}, + {IMX_8BIT, 0x331D, 0x10}, + {IMX_8BIT, 0x4084, 0x00}, /* If scaling, Fill this */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +/* 13MP reduced pixel clock MIPI 342MHz is EMC friendly*/ +static struct imx_reg const imx135_13m_for_mipi_342[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size Setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x00}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x6F}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x2F}, + {IMX_8BIT, 0x034C, 0x10}, + {IMX_8BIT, 0x034D, 0x70}, + {IMX_8BIT, 0x034E, 0x0C}, + {IMX_8BIT, 0x034F, 0x30}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x0C}, + {IMX_8BIT, 0x0357, 0x30}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x10}, + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x0C}, + {IMX_8BIT, 0x3313, 0x30}, + {IMX_8BIT, 0x331C, 0x00}, + {IMX_8BIT, 0x331D, 0x10}, + {IMX_8BIT, 0x4084, 0x00}, /* If scaling, Fill this */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_10m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 0, 376, 4207, 2743 */ + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x78}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x6f}, + {IMX_8BIT, 0x034A, 0x0a}, + {IMX_8BIT, 0x034B, 0xb7}, + {IMX_8BIT, 0x034C, 0x10}, /* 4208x2368 */ + {IMX_8BIT, 0x034D, 0x70}, + {IMX_8BIT, 0x034E, 0x09}, + {IMX_8BIT, 0x034F, 0x40}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0x40}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x10}, + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0x40}, + {IMX_8BIT, 0x331C, 0x01}, + {IMX_8BIT, 0x331D, 0x68}, + {IMX_8BIT, 0x4084, 0x00}, + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_10m_for_mipi_342[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 0, 376, 4207, 2743 */ + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x78}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x6f}, + {IMX_8BIT, 0x034A, 0x0a}, + {IMX_8BIT, 0x034B, 0xb7}, + {IMX_8BIT, 0x034C, 0x10}, /* 4208x2368 */ + {IMX_8BIT, 0x034D, 0x70}, + {IMX_8BIT, 0x034E, 0x09}, + {IMX_8BIT, 0x034F, 0x40}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0x40}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x10}, + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0x40}, + {IMX_8BIT, 0x331C, 0x01}, + {IMX_8BIT, 0x331D, 0x68}, + {IMX_8BIT, 0x4084, 0x00}, + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 8.5 DS from (3:2)8m cropped setting. + * + * The 8m(3:2) cropped setting is 2992x2448 effective res. + * The ISP effect cropped setting should be 1408x1152 effect res. + * + * Consider ISP 16x16 padding: + * sensor outputs 368x304 + * cropped region is 3128x2584 + */ +static struct imx_reg const imx135_368x304_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, /* no binning */ + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* resize */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x88}, /* 136/16=8.5 */ + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x02}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0x1C}, /* 540 */ + {IMX_8BIT, 0x0346, 0x01}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x0C}, /* 268 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0x53}, /* 3667 */ + {IMX_8BIT, 0x034A, 0x0B}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0x23}, /* 2851 */ + {IMX_8BIT, 0x034C, 0x01}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x70}, /* 368 */ + {IMX_8BIT, 0x034E, 0x01}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0x30}, /* 304 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0C}, /* Cut out siz same as the size after crop */ + {IMX_8BIT, 0x0355, 0x38}, + {IMX_8BIT, 0x0356, 0x0A}, + {IMX_8BIT, 0x0357, 0x18}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x01}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x01}, + {IMX_8BIT, 0x3313, 0x30}, + {IMX_8BIT, 0x331C, 0x02}, /* ?? */ + {IMX_8BIT, 0x331D, 0xD0}, + {IMX_8BIT, 0x4084, 0x01}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x70}, + {IMX_8BIT, 0x4086, 0x01}, + {IMX_8BIT, 0x4087, 0x30}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 1/4 binning from 8m cropped setting. + * + * The 8m cropped setting is 3264x2448 effective res. + * The xga cropped setting should be 816x612 effect res. + * + * Consider ISP 16x16 padding: + * sensor outputs 832x628 + * cropped region is 3328x2512 + */ +static struct imx_reg const imx135_xga_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x44}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, +/* {IMX_8BIT, 0x4203, 0xFF}, */ + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0xB8}, /* 440 */ + {IMX_8BIT, 0x0346, 0x01}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x30}, /* 304 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0xB7}, /* 4207-440=3767 */ + {IMX_8BIT, 0x034A, 0x0A}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0xFF}, /* 3119-304=2815 */ + {IMX_8BIT, 0x034C, 0x03}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x40}, /* 832 */ + {IMX_8BIT, 0x034E, 0x02}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0x74}, /* 628 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x03}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0x40}, + {IMX_8BIT, 0x0356, 0x02}, + {IMX_8BIT, 0x0357, 0x74}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x03}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x40}, + {IMX_8BIT, 0x3312, 0x02}, + {IMX_8BIT, 0x3313, 0x74}, + {IMX_8BIT, 0x331C, 0x02}, /* ?? */ + {IMX_8BIT, 0x331D, 0x21}, + {IMX_8BIT, 0x4084, 0x03}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x40}, + {IMX_8BIT, 0x4086, 0x02}, + {IMX_8BIT, 0x4087, 0x74}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 28/16 DS from (16:9)8m cropped setting. + * + * The 8m(16:9) cropped setting is 3360x1890 effective res. + * - this is larger then the expected 3264x1836 FOV + * + * Consider ISP 16x16 padding: + * sensor outputs 1936x1096 + * cropped region is 3388x1918 + */ +static struct imx_reg const imx135_1936x1096_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, /* no binning */ + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* resize */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x1C}, /* 28/16 */ + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0x9A}, /* 410 */ + {IMX_8BIT, 0x0346, 0x02}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x58}, /* 600 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0xD5}, /* 3797 */ + {IMX_8BIT, 0x034A, 0x09}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0xD5}, /* 2517 */ + {IMX_8BIT, 0x034C, 0x07}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x90}, /* 1936 */ + {IMX_8BIT, 0x034E, 0x04}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0x48}, /* 1096 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0D}, /* Cut out siz same as the size after crop */ + {IMX_8BIT, 0x0355, 0x3C}, + {IMX_8BIT, 0x0356, 0x07}, + {IMX_8BIT, 0x0357, 0x7E}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x07}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x90}, + {IMX_8BIT, 0x3312, 0x04}, + {IMX_8BIT, 0x3313, 0x48}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0xAA}, + {IMX_8BIT, 0x4084, 0x07}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x90}, + {IMX_8BIT, 0x4086, 0x04}, + {IMX_8BIT, 0x4087, 0x48}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 2.125 DS from (3:2)8m cropped setting. + * + * The 8m(3:2) cropped setting is 2992x2448 effective res. + * The ISP effect cropped setting should be 1408x1152 effect res. + * + * Consider ISP 16x16 padding: + * sensor outputs 1424x1168 + * cropped region is 3026x2482 + */ +static struct imx_reg const imx135_1424x1168_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, /* no binning */ + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* resize */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x22}, /* 34/16=2.125 */ + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x02}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0x4E}, /* 590 */ + {IMX_8BIT, 0x0346, 0x01}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x3E}, /* 318 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0x1F}, /* 3615 */ + {IMX_8BIT, 0x034A, 0x0A}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0xEF}, /* 2799 */ + {IMX_8BIT, 0x034C, 0x05}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x90}, /* 1424 */ + {IMX_8BIT, 0x034E, 0x04}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0x90}, /* 1168 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0B}, /* Cut out siz same as the size after crop */ + {IMX_8BIT, 0x0355, 0xD2}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0xB2}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x05}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x90}, + {IMX_8BIT, 0x3312, 0x04}, + {IMX_8BIT, 0x3313, 0x90}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0xAA}, + {IMX_8BIT, 0x4084, 0x05}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x90}, + {IMX_8BIT, 0x4086, 0x04}, + {IMX_8BIT, 0x4087, 0x90}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 1/2 binning from 8m cropped setting. + * + * The 8m cropped setting is 3264x2448 effective res. + * The 2m cropped setting should be 1632x1224 effect res. + * + * Consider ISP 16x16 padding: + * sensor outputs 1648x1240 + * cropped region is 3296x2480 + */ +static struct imx_reg const imx135_2m_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x22}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0xC8}, /* 464(1D0) -> 456(1C8)*/ + {IMX_8BIT, 0x0346, 0x01}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x40}, /* 320 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0xA7}, /* 4207-456=3751 */ + {IMX_8BIT, 0x034A, 0x0A}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0xEF}, /* 3119-320=2799 */ + {IMX_8BIT, 0x034C, 0x06}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x70}, /* 1648 */ + {IMX_8BIT, 0x034E, 0x04}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0xD8}, /* 1240 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x06}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x04}, + {IMX_8BIT, 0x0357, 0xD8}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x06}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x04}, + {IMX_8BIT, 0x3313, 0xD8}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0xAA}, + {IMX_8BIT, 0x4084, 0x00}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * 8M Cropped 16:9 setting + * + * Effect res: 3264x1836 + * Sensor out: 3280x1852 + */ +static struct imx_reg const imx135_6m_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xD0}, + {IMX_8BIT, 0x0346, 0x02}, /* 634 */ + {IMX_8BIT, 0x0347, 0x7A}, + {IMX_8BIT, 0x0348, 0x0E}, + {IMX_8BIT, 0x0349, 0x9F}, + {IMX_8BIT, 0x034A, 0x09}, /* 2485 */ + {IMX_8BIT, 0x034B, 0xB5}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x07}, /* 1852 */ + {IMX_8BIT, 0x034F, 0x3C}, + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0C}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0xD0}, + {IMX_8BIT, 0x0356, 0x07}, + {IMX_8BIT, 0x0357, 0x3C}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x0C}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x07}, + {IMX_8BIT, 0x3313, 0x3C}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0x10}, + {IMX_8BIT, 0x4084, 0x00}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_8m_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xD0}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x48}, + {IMX_8BIT, 0x0348, 0x0E}, + {IMX_8BIT, 0x0349, 0x9F}, + {IMX_8BIT, 0x034A, 0x0A}, + {IMX_8BIT, 0x034B, 0xE7}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x09}, /* 2464 */ + {IMX_8BIT, 0x034F, 0xA0}, + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0C}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0xD0}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0xA0}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x0C}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0xA0}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0x10}, + {IMX_8BIT, 0x4084, 0x00}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_8m_scaled_from_12m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* Scaling */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x14}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x36}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x14}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x39}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x1B}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280x2464 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x09}, + {IMX_8BIT, 0x034F, 0xA0}, + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0x04}, + {IMX_8BIT, 0x0356, 0x0C}, + {IMX_8BIT, 0x0357, 0x08}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x0C}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0xA0}, + {IMX_8BIT, 0x331C, 0x02}, /* ?? */ + {IMX_8BIT, 0x331D, 0xA0}, + {IMX_8BIT, 0x4084, 0x0C}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0xD0}, + {IMX_8BIT, 0x4086, 0x09}, + {IMX_8BIT, 0x4087, 0xA0}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_8m_scaled_from_12m_for_mipi342[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* Scaling */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x14}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x36}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x14}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x39}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x1B}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280x2464 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x09}, + {IMX_8BIT, 0x034F, 0xA0}, + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0x04}, + {IMX_8BIT, 0x0356, 0x0C}, + {IMX_8BIT, 0x0357, 0x08}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x0C}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0xA0}, + {IMX_8BIT, 0x331C, 0x02}, /* ?? */ + {IMX_8BIT, 0x331D, 0xA0}, + {IMX_8BIT, 0x4084, 0x0C}, /* Resize IMG Hand V size-> Scaling related?*/ + {IMX_8BIT, 0x4085, 0xD0}, + {IMX_8BIT, 0x4086, 0x09}, + {IMX_8BIT, 0x4087, 0xA0}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_6m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x14}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 36, 194, 1039, a9f 4100x2316 */ + {IMX_8BIT, 0x0345, 0x36}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x94}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x39}, + {IMX_8BIT, 0x034A, 0x0A}, + {IMX_8BIT, 0x034B, 0x9F}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280x1852 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x07}, + {IMX_8BIT, 0x034F, 0x3C}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* 4100x2316 */ + {IMX_8BIT, 0x0355, 0x04}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0x0C}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x0C}, + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x07}, + {IMX_8BIT, 0x3313, 0x3C}, + {IMX_8BIT, 0x331C, 0x02}, + {IMX_8BIT, 0x331D, 0xA0}, + {IMX_8BIT, 0x4084, 0x0C}, + {IMX_8BIT, 0x4085, 0xD0}, + {IMX_8BIT, 0x4086, 0x07}, + {IMX_8BIT, 0x4087, 0x3C}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_6m_for_mipi_342[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x14}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 36, 194, 1039, a9f 4100x2316 */ + {IMX_8BIT, 0x0345, 0x36}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x94}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x39}, + {IMX_8BIT, 0x034A, 0x0A}, + {IMX_8BIT, 0x034B, 0x9F}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280x1852 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x07}, + {IMX_8BIT, 0x034F, 0x3C}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* 4100x2316 */ + {IMX_8BIT, 0x0355, 0x04}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0x0C}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x0C}, + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x07}, + {IMX_8BIT, 0x3313, 0x3C}, + {IMX_8BIT, 0x331C, 0x02}, + {IMX_8BIT, 0x331D, 0xA0}, + {IMX_8BIT, 0x4084, 0x0C}, + {IMX_8BIT, 0x4085, 0xD0}, + {IMX_8BIT, 0x4086, 0x07}, + {IMX_8BIT, 0x4087, 0x3C}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * FOV is: 3280x2464, larger then 3264x2448. + * Sensor output: 336x256 + * Cropping region: 3444x2624 + */ +static struct imx_reg const imx135_336x256[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x22}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* 2x binning */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x52}, /* scaling: 82/16 */ + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, /* x_start: 374 */ + {IMX_8BIT, 0x0345, 0x76}, + {IMX_8BIT, 0x0346, 0x00}, /* y_start: 248 */ + {IMX_8BIT, 0x0347, 0xF8}, + {IMX_8BIT, 0x0348, 0x0E}, /* x_end: 3817 */ + {IMX_8BIT, 0x0349, 0xE9}, + {IMX_8BIT, 0x034A, 0x0B}, /* y_end: 2871 */ + {IMX_8BIT, 0x034B, 0x37}, + {IMX_8BIT, 0x034C, 0x01}, /* x_out: 336 */ + {IMX_8BIT, 0x034D, 0x50}, + {IMX_8BIT, 0x034E, 0x01}, /* y_out: 256 */ + {IMX_8BIT, 0x034F, 0x00}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x06}, /* dig x_out: 1722 */ + {IMX_8BIT, 0x0355, 0xBA}, + {IMX_8BIT, 0x0356, 0x05}, /* dig y_out: 1312 */ + {IMX_8BIT, 0x0357, 0x20}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x01}, /* ?: x_out */ + {IMX_8BIT, 0x3311, 0x50}, + {IMX_8BIT, 0x3312, 0x01}, /* ?: y_out */ + {IMX_8BIT, 0x3313, 0x00}, + {IMX_8BIT, 0x331C, 0x02}, + {IMX_8BIT, 0x331D, 0x4E}, + {IMX_8BIT, 0x4084, 0x01}, /* ?: x_out */ + {IMX_8BIT, 0x4085, 0x50}, + {IMX_8BIT, 0x4086, 0x01}, /* ?: y_out */ + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_1m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x22}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x1F}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x58}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x28}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x17}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x07}, + {IMX_8BIT, 0x034C, 0x04}, + {IMX_8BIT, 0x034D, 0x10}, + {IMX_8BIT, 0x034E, 0x03}, + {IMX_8BIT, 0x034F, 0x10}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x07}, + {IMX_8BIT, 0x0355, 0xE0}, + {IMX_8BIT, 0x0356, 0x05}, + {IMX_8BIT, 0x0357, 0xF0}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x04}, + {IMX_8BIT, 0x3311, 0x10}, + {IMX_8BIT, 0x3312, 0x03}, + {IMX_8BIT, 0x3313, 0x10}, + {IMX_8BIT, 0x331C, 0x02}, + {IMX_8BIT, 0x331D, 0x4E}, + {IMX_8BIT, 0x4084, 0x04}, + {IMX_8BIT, 0x4085, 0x10}, + {IMX_8BIT, 0x4086, 0x03}, + {IMX_8BIT, 0x4087, 0x10}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_3m_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, /* Binning */ + {IMX_8BIT, 0x0391, 0x22}, /* 2x2 binning */ + {IMX_8BIT, 0x0392, 0x00}, /* average */ + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x28}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x08}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x47}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x27}, + {IMX_8BIT, 0x034C, 0x08}, + {IMX_8BIT, 0x034D, 0x10}, + {IMX_8BIT, 0x034E, 0x06}, + {IMX_8BIT, 0x034F, 0x10}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x08}, + {IMX_8BIT, 0x0355, 0x10}, + {IMX_8BIT, 0x0356, 0x06}, + {IMX_8BIT, 0x0357, 0x10}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x08}, + {IMX_8BIT, 0x3311, 0x10}, + {IMX_8BIT, 0x3312, 0x06}, + {IMX_8BIT, 0x3313, 0x10}, + {IMX_8BIT, 0x331C, 0x00}, + {IMX_8BIT, 0x331D, 0xAA}, + {IMX_8BIT, 0x4084, 0x00}, + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +/* 1080P 1936x1104 */ +static struct imx_reg const imx135_1080p_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x22}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x11}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x2E}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x84}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x41}, + {IMX_8BIT, 0x034A, 0x0A}, + {IMX_8BIT, 0x034B, 0xAF}, + {IMX_8BIT, 0x034C, 0x07}, + {IMX_8BIT, 0x034D, 0x90}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x50}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x08}, + {IMX_8BIT, 0x0355, 0x0A}, + {IMX_8BIT, 0x0356, 0x04}, + {IMX_8BIT, 0x0357, 0x96}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x07}, + {IMX_8BIT, 0x3311, 0x90}, + {IMX_8BIT, 0x3312, 0x04}, + {IMX_8BIT, 0x3313, 0x50}, + {IMX_8BIT, 0x331C, 0x01}, + {IMX_8BIT, 0x331D, 0x00}, + {IMX_8BIT, 0x4084, 0x07}, + {IMX_8BIT, 0x4085, 0x90}, + {IMX_8BIT, 0x4086, 0x04}, + {IMX_8BIT, 0x4087, 0x50}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static const struct imx_reg imx135_1080p_nodvs_fullfov_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 168,464,4039,2655: 3872x2192 */ + { IMX_8BIT, 0x0345, 0xA8 }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0xD0 }, + { IMX_8BIT, 0x0348, 0x0F }, + { IMX_8BIT, 0x0349, 0xC7 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0x5F }, + { IMX_8BIT, 0x034C, 0x07 }, /*1936 x 1096 */ + { IMX_8BIT, 0x034D, 0x90 }, + { IMX_8BIT, 0x034E, 0x04 }, + { IMX_8BIT, 0x034F, 0x48 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x07 }, /*1936 x 1096 */ + { IMX_8BIT, 0x0355, 0x90 }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x48 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x07 }, + { IMX_8BIT, 0x3311, 0x90 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x48 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0xB0 }, + { IMX_8BIT, 0x4084, 0x07 }, + { IMX_8BIT, 0x4085, 0x90 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x48 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* 1080P NODVS 1936x1096 */ +static const struct imx_reg imx135_1080p_nodvs_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x11 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 46,396,4161,2727: 4116x2332 */ + { IMX_8BIT, 0x0345, 0x2E }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x8C }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x41 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0xA7 }, + { IMX_8BIT, 0x034C, 0x07 }, /*1936 x 1096 */ + { IMX_8BIT, 0x034D, 0x90 }, + { IMX_8BIT, 0x034E, 0x04 }, + { IMX_8BIT, 0x034F, 0x48 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /* 2058x1166 */ + { IMX_8BIT, 0x0355, 0x0A }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x8E }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x07 }, + { IMX_8BIT, 0x3311, 0x90 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x48 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0xB0 }, + { IMX_8BIT, 0x4084, 0x07 }, + { IMX_8BIT, 0x4085, 0x90 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x48 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* 1080P 10%DVS 2104x1184 */ +static const struct imx_reg imx135_1080p_10_dvs_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 0,376,4207,2743: 4208x2368 */ + { IMX_8BIT, 0x0345, 0x00 }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x78 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x6F }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0xB7 }, + { IMX_8BIT, 0x034C, 0x08 }, /* 2104 x 1184 */ + { IMX_8BIT, 0x034D, 0x38 }, + { IMX_8BIT, 0x034E, 0x04 }, + { IMX_8BIT, 0x034F, 0xA0 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /* 2104 x 1184 */ + { IMX_8BIT, 0x0355, 0x38 }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0xA0 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x08 }, + { IMX_8BIT, 0x3311, 0x38 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0xA0 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0xB0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx135_720pdvs_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x15 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 46,404,4161,2715: 4116x2312 */ + { IMX_8BIT, 0x0345, 0x2E }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x94 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x41 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0x9B }, + { IMX_8BIT, 0x034C, 0x06 }, /*1568 x 880 */ + { IMX_8BIT, 0x034D, 0x20 }, + { IMX_8BIT, 0x034E, 0x03 }, + { IMX_8BIT, 0x034F, 0x70 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /*2058 x 1156 */ + { IMX_8BIT, 0x0355, 0x0A }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x84 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x70 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x4C }, + { IMX_8BIT, 0x4084, 0x06 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x03 }, + { IMX_8BIT, 0x4087, 0x70 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/******************* Video Modes ******************/ + +/* 1080P DVS 2336x1320 */ +static const struct imx_reg imx135_2336x1320_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1C }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 60,404,4147,2715: 4088x2312 */ + { IMX_8BIT, 0x0345, 0x3C }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x94 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x33 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0x9B }, + { IMX_8BIT, 0x034C, 0x09 }, /*2336 x 1320 */ + { IMX_8BIT, 0x034D, 0x20 }, + { IMX_8BIT, 0x034E, 0x05 }, + { IMX_8BIT, 0x034F, 0x28 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0F }, /* 4088x2312 */ + { IMX_8BIT, 0x0355, 0xF8 }, + { IMX_8BIT, 0x0356, 0x09 }, + { IMX_8BIT, 0x0357, 0x08 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x09 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x05 }, + { IMX_8BIT, 0x3313, 0x28 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0xE2 }, + { IMX_8BIT, 0x4084, 0x09 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x05 }, + { IMX_8BIT, 0x4087, 0x28 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* 1080P DVS 2336x1320 Cropped */ +static const struct imx_reg imx135_2336x1320_cropped_mipi499[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_499_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1C }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x03 }, /* 936,900,3271,2219: 2336x1320 */ + { IMX_8BIT, 0x0345, 0xA8 }, + { IMX_8BIT, 0x0346, 0x03 }, + { IMX_8BIT, 0x0347, 0x84 }, + { IMX_8BIT, 0x0348, 0x0C }, + { IMX_8BIT, 0x0349, 0xC7 }, + { IMX_8BIT, 0x034A, 0x08 }, + { IMX_8BIT, 0x034B, 0xAB }, + { IMX_8BIT, 0x034C, 0x09 }, /* 2336 x 1320 */ + { IMX_8BIT, 0x034D, 0x20 }, + { IMX_8BIT, 0x034E, 0x05 }, + { IMX_8BIT, 0x034F, 0x28 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x09 }, /* 2336 x 1320 */ + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x05 }, + { IMX_8BIT, 0x0357, 0x28 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x09 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x05 }, + { IMX_8BIT, 0x3313, 0x28 }, + { IMX_8BIT, 0x331C, 0x00 }, + { IMX_8BIT, 0x331D, 0xB4 }, + { IMX_8BIT, 0x4084, 0x09 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x05 }, + { IMX_8BIT, 0x4087, 0x28 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* 720P DVS 1568 x 880 */ +static const struct imx_reg imx135_720p_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x15 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 46,404,4161,2715: 4116x2312 */ + { IMX_8BIT, 0x0345, 0x2e }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x94 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x41 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0x9B }, + { IMX_8BIT, 0x034C, 0x06 }, /*1568 x 880 */ + { IMX_8BIT, 0x034D, 0x20 }, + { IMX_8BIT, 0x034E, 0x03 }, + { IMX_8BIT, 0x034F, 0x70 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /* 2058x1156 */ + { IMX_8BIT, 0x0355, 0x0a }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x84 }, + { IMX_8BIT, 0x301D, 0x30 }, /* TODO! */ + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x70 }, + { IMX_8BIT, 0x331C, 0x01 }, /* TODO! */ + { IMX_8BIT, 0x331D, 0xd6 }, /* TODO! */ + { IMX_8BIT, 0x4084, 0x06 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x03 }, + { IMX_8BIT, 0x4087, 0x70 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* wvga: H : 1640 V : 1024 */ +static const struct imx_reg imx135_wvga_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x22 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x14 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, + {IMX_8BIT, 0x0345, 0x36 }, + {IMX_8BIT, 0x0346, 0x01 }, + {IMX_8BIT, 0x0347, 0x18 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x39 }, + {IMX_8BIT, 0x034A, 0x0B }, + {IMX_8BIT, 0x034B, 0x17 }, + {IMX_8BIT, 0x034C, 0x06 }, + {IMX_8BIT, 0x034D, 0x68 }, + {IMX_8BIT, 0x034E, 0x04 }, + {IMX_8BIT, 0x034F, 0x00 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x08 }, + {IMX_8BIT, 0x0355, 0x02 }, + {IMX_8BIT, 0x0356, 0x05 }, + {IMX_8BIT, 0x0357, 0x00 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x06 }, + {IMX_8BIT, 0x3311, 0x68 }, + {IMX_8BIT, 0x3312, 0x04 }, + {IMX_8BIT, 0x3313, 0x00 }, + {IMX_8BIT, 0x331C, 0x01 }, + {IMX_8BIT, 0x331D, 0xBD }, + {IMX_8BIT, 0x4084, 0x06 }, + {IMX_8BIT, 0x4085, 0x68 }, + {IMX_8BIT, 0x4086, 0x04 }, + {IMX_8BIT, 0x4087, 0x00 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* 480P 1036 x 696 */ +static const struct imx_reg imx135_480p_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x00 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x10 },/* No scal */ + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 52,20,4155, 3099 4144x2784*/ + {IMX_8BIT, 0x0345, 0x20 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0xA8 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x4F }, + {IMX_8BIT, 0x034A, 0x0B }, + {IMX_8BIT, 0x034B, 0x88 }, + {IMX_8BIT, 0x034C, 0x04 }, /* 1036 * 696 */ + {IMX_8BIT, 0x034D, 0x0C }, + {IMX_8BIT, 0x034E, 0x02 }, + {IMX_8BIT, 0x034F, 0xB8 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x04 }, /* 1036x696 */ + {IMX_8BIT, 0x0355, 0x0C }, + {IMX_8BIT, 0x0356, 0x02 }, + {IMX_8BIT, 0x0357, 0xB8 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x04 }, + {IMX_8BIT, 0x3311, 0x0C }, + {IMX_8BIT, 0x3312, 0x02 }, + {IMX_8BIT, 0x3313, 0xB8 }, + {IMX_8BIT, 0x331C, 0x02 }, + {IMX_8BIT, 0x331D, 0x21 }, + {IMX_8BIT, 0x4084, 0x04 }, + {IMX_8BIT, 0x4085, 0x0C }, + {IMX_8BIT, 0x4086, 0x02 }, + {IMX_8BIT, 0x4087, 0xB8 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* 480P DVS 936 x 602 */ +static const struct imx_reg imx135_480p_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x23 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 56,244,4151,2877: 4096x2634 */ + { IMX_8BIT, 0x0345, 0x38 }, + { IMX_8BIT, 0x0346, 0x00 }, + { IMX_8BIT, 0x0347, 0xf4 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x37 }, + { IMX_8BIT, 0x034A, 0x0b }, + { IMX_8BIT, 0x034B, 0x3d }, + { IMX_8BIT, 0x034C, 0x03 }, /* 936 x 602 */ + { IMX_8BIT, 0x034D, 0xa8 }, + { IMX_8BIT, 0x034E, 0x02 }, + { IMX_8BIT, 0x034F, 0x5a }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /* 2058x1156 */ + { IMX_8BIT, 0x0355, 0x00 }, + { IMX_8BIT, 0x0356, 0x05 }, + { IMX_8BIT, 0x0357, 0x25 }, + { IMX_8BIT, 0x301D, 0x30 }, /* TODO! */ + { IMX_8BIT, 0x3310, 0x03 }, + { IMX_8BIT, 0x3311, 0xa8 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x5a }, + { IMX_8BIT, 0x331C, 0x01 }, /* TODO! */ + { IMX_8BIT, 0x331D, 0xd6 }, + { IMX_8BIT, 0x4084, 0x03 }, + { IMX_8BIT, 0x4085, 0xa8 }, + { IMX_8BIT, 0x4086, 0x02 }, + { IMX_8BIT, 0x4087, 0x5a }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* VGA: H : 1036 V : 780 */ +static const struct imx_reg imx135_vga_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x00 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x10 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 52,20,4155, 3099 4144x3120*/ + {IMX_8BIT, 0x0345, 0x20 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x00 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x4F }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x2F }, + {IMX_8BIT, 0x034C, 0x04 }, /* 1036x780 */ + {IMX_8BIT, 0x034D, 0x0C }, + {IMX_8BIT, 0x034E, 0x03 }, + {IMX_8BIT, 0x034F, 0x0C }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x04 }, /* 1036x780 */ + {IMX_8BIT, 0x0355, 0x0C }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x0C }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x04 }, + {IMX_8BIT, 0x3311, 0x0C }, + {IMX_8BIT, 0x3312, 0x03 }, + {IMX_8BIT, 0x3313, 0x0C }, + {IMX_8BIT, 0x331C, 0x02 }, + {IMX_8BIT, 0x331D, 0x21 }, + {IMX_8BIT, 0x4084, 0x04 }, + {IMX_8BIT, 0x4085, 0x0C }, + {IMX_8BIT, 0x4086, 0x03 }, + {IMX_8BIT, 0x4087, 0x0C }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* VGA: H : 820 V : 616 */ +static const struct imx_reg imx135_vga_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x14 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 52,20,4155, 3099 4104x3080*/ + {IMX_8BIT, 0x0345, 0x34 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x14 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x3B }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x1B }, + {IMX_8BIT, 0x034C, 0x03 }, /* 820x616 */ + {IMX_8BIT, 0x034D, 0x34 }, + {IMX_8BIT, 0x034E, 0x02 }, + {IMX_8BIT, 0x034F, 0x68 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x04 }, /* 1026x770 */ + {IMX_8BIT, 0x0355, 0x02 }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x02 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x03 }, + {IMX_8BIT, 0x3311, 0x34 }, + {IMX_8BIT, 0x3312, 0x02 }, + {IMX_8BIT, 0x3313, 0x68 }, + {IMX_8BIT, 0x331C, 0x02 }, + {IMX_8BIT, 0x331D, 0x21 }, + {IMX_8BIT, 0x4084, 0x03 }, + {IMX_8BIT, 0x4085, 0x34 }, + {IMX_8BIT, 0x4086, 0x02 }, + {IMX_8BIT, 0x4087, 0x68 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* VGA: H : 436 V : 360 */ +static const struct imx_reg imx135_436x360_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x22 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 212,0,3995,3119 3784x3120 */ + {IMX_8BIT, 0x0345, 0xD4 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x00 }, + {IMX_8BIT, 0x0348, 0x0F }, + {IMX_8BIT, 0x0349, 0x9B }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x2F }, + + {IMX_8BIT, 0x034C, 0x01 }, /* 436x360 */ + {IMX_8BIT, 0x034D, 0xB4 }, + {IMX_8BIT, 0x034E, 0x01 }, + {IMX_8BIT, 0x034F, 0x68 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x12 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x0C }, + + {IMX_8BIT, 0x0354, 0x03 }, /* 928x768 crop from 946x780*/ + {IMX_8BIT, 0x0355, 0xA0 }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x00 }, + + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x01 }, + {IMX_8BIT, 0x3311, 0xB4 }, + {IMX_8BIT, 0x3312, 0x01 }, + {IMX_8BIT, 0x3313, 0x68 }, + {IMX_8BIT, 0x331C, 0x02 }, + {IMX_8BIT, 0x331D, 0x21 }, + {IMX_8BIT, 0x4084, 0x01 }, + {IMX_8BIT, 0x4085, 0xB4 }, + {IMX_8BIT, 0x4086, 0x01 }, + {IMX_8BIT, 0x4087, 0x68 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* QVGA: H : 408 V : 308 */ +static const struct imx_reg imx135_qvga__dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x28 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 64,20,4143,3099 4080x3080 */ + {IMX_8BIT, 0x0345, 0x40 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x14 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x2F }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x1B }, + {IMX_8BIT, 0x034C, 0x01 }, /* 408x308 */ + {IMX_8BIT, 0x034D, 0x98 }, + {IMX_8BIT, 0x034E, 0x01 }, + {IMX_8BIT, 0x034F, 0x34 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x03 }, /* 1020x770 */ + {IMX_8BIT, 0x0355, 0xFC }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x02 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x01 }, + {IMX_8BIT, 0x3311, 0x98 }, + {IMX_8BIT, 0x3312, 0x01 }, + {IMX_8BIT, 0x3313, 0x34 }, + {IMX_8BIT, 0x331C, 0x01 }, + {IMX_8BIT, 0x331D, 0x68 }, + {IMX_8BIT, 0x4084, 0x01 }, + {IMX_8BIT, 0x4085, 0x98 }, + {IMX_8BIT, 0x4086, 0x01 }, + {IMX_8BIT, 0x4087, 0x34 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* CIF H : 368 V : 304 */ +static const struct imx_reg imx135_cif_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x28 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01 }, /* 264,42,3943,3081 3680x3040 */ + {IMX_8BIT, 0x0345, 0x08 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x2a }, + {IMX_8BIT, 0x0348, 0x0F }, + {IMX_8BIT, 0x0349, 0x67 }, + {IMX_8BIT, 0x034A, 0x0c }, + {IMX_8BIT, 0x034B, 0x09 }, + {IMX_8BIT, 0x034C, 0x01 }, /* 368x304 */ + {IMX_8BIT, 0x034D, 0x70 }, + {IMX_8BIT, 0x034E, 0x01 }, + {IMX_8BIT, 0x034F, 0x30 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x03 }, /* 920x760 */ + {IMX_8BIT, 0x0355, 0x98 }, + {IMX_8BIT, 0x0356, 0x02 }, + {IMX_8BIT, 0x0357, 0xf8 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x01 }, + {IMX_8BIT, 0x3311, 0x70 }, + {IMX_8BIT, 0x3312, 0x01 }, + {IMX_8BIT, 0x3313, 0x30 }, + {IMX_8BIT, 0x331C, 0x02 }, /* TODO! binning 4x4 must be 021c? */ + {IMX_8BIT, 0x331D, 0x1C }, + {IMX_8BIT, 0x4084, 0x01 }, + {IMX_8BIT, 0x4085, 0x70 }, + {IMX_8BIT, 0x4086, 0x01 }, + {IMX_8BIT, 0x4087, 0x30 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* CIF H : 1888 V : 1548 */ +static const struct imx_reg imx135_cif_binning_1888x1548[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x22 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x00 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x10 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 264,42, 3776x3096 */ + {IMX_8BIT, 0x0345, 0xD8 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x0C }, + {IMX_8BIT, 0x0348, 0x0F }, + {IMX_8BIT, 0x0349, 0x97 }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x23 }, + {IMX_8BIT, 0x034C, 0x07 }, /* 1888x1548 */ + {IMX_8BIT, 0x034D, 0x60 }, + {IMX_8BIT, 0x034E, 0x06 }, + {IMX_8BIT, 0x034F, 0x0C }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x07 }, /* 1888x1548 */ + {IMX_8BIT, 0x0355, 0x60 }, + {IMX_8BIT, 0x0356, 0x06 }, + {IMX_8BIT, 0x0357, 0x0C }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x07 }, + {IMX_8BIT, 0x3311, 0x60 }, + {IMX_8BIT, 0x3312, 0x06 }, + {IMX_8BIT, 0x3313, 0x0C }, + {IMX_8BIT, 0x331C, 0x02 }, /* TODO! binning 4x4 must be 021c? */ + {IMX_8BIT, 0x331D, 0x1C }, + {IMX_8BIT, 0x4084, 0x07 }, + {IMX_8BIT, 0x4085, 0x60 }, + {IMX_8BIT, 0x4086, 0x06 }, + {IMX_8BIT, 0x4087, 0x0C }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* QCIF H : 216 V : 176 */ +static const struct imx_reg imx135_qcif_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x46 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 212,20,3995,3099 3784x3080 */ + {IMX_8BIT, 0x0345, 0xD4 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x14 }, + {IMX_8BIT, 0x0348, 0x0F }, + {IMX_8BIT, 0x0349, 0x9B }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x1B }, + {IMX_8BIT, 0x034C, 0x00 }, /* 216x176 */ + {IMX_8BIT, 0x034D, 0xD8 }, + {IMX_8BIT, 0x034E, 0x00 }, + {IMX_8BIT, 0x034F, 0xB0 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x03 }, /* 946x770 */ + {IMX_8BIT, 0x0355, 0xB2 }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x02 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x00 }, + {IMX_8BIT, 0x3311, 0xD8 }, + {IMX_8BIT, 0x3312, 0x00 }, + {IMX_8BIT, 0x3313, 0xB0 }, + {IMX_8BIT, 0x331C, 0x02 }, /* TODO! binning 4x4 must be 021c */ + {IMX_8BIT, 0x331D, 0x1C }, + {IMX_8BIT, 0x4084, 0x00 }, + {IMX_8BIT, 0x4085, 0xD8 }, + {IMX_8BIT, 0x4086, 0x00 }, + {IMX_8BIT, 0x4087, 0xB0 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* + * ISP Scaling is now supported in offine capture use cases. Because of that + * we need only few modes to cover the different aspect ratios from the + * sensor and the ISP will scale it based on the requested resolution from HAL. + * + * There is a performance impact when continuous view finder option is chose + * for resolutions above 8MP. So 8MP and 6MP resolution are kept, so that lower + * than these take 8MP or 6MP espectively for down scaling based on the + * aspect ratio. + */ +struct imx_resolution imx135_res_preview_mofd[] = { + { + .desc = "imx135_cif_binning_preview", + .regs = imx135_cif_binning, + .width = 368, + .height = 304, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 9114, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_vga_binning_preview", + .regs = imx135_vga_binning, + .width = 1036, + .height = 780, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_480p_preview", + .regs = imx135_480p_binning, + .width = 1036, + .height = 696, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_1080p_binning_preview", + .regs = imx135_1080p_binning, + .width = 1936, + .height = 1104, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_3m__cont_cap", + .regs = imx135_3m_binning, + .width = 2064, + .height = 1552, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_6m_cont_cap", + .regs = imx135_6m, + .width = 3280, + .height = 1852, + .fps_options = { + { /* Binning Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_8m_scaled_from_12m__cont_cap", + .regs = imx135_8m_scaled_from_12m, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 24, + .pixels_per_line = 4572, + .lines_per_frame = 3280, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_10m__cont_cap", + .regs = imx135_10m, + .width = 4208, + .height = 2368, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2632, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_13m__cont_cap", + .regs = imx135_13m, + .width = 4208, + .height = 3120, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 24, + .pixels_per_line = 4572, + .lines_per_frame = 3290, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, +}; + +struct imx_resolution imx135_res_preview[] = { + { + .desc = "imx135_xga_cropped_video", + .regs = imx135_xga_cropped, + .width = 832, + .height = 628, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_2m_cropped_video", + .regs = imx135_2m_cropped, + .width = 1648, + .height = 1240, + .fps_options = { + { /* Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_1936x1096_cropped", + .regs = imx135_1936x1096_cropped, + .width = 1936, + .height = 1096, + .fps_options = { + { /* Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_8m_cropped_video", + .regs = imx135_8m_cropped, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, +}; + +/* + * ISP Scaling is now supported in online capture use cases. Because of that + * we need only few modes to cover the different aspect ratios from the + * sensor and the ISP will scale it based on the requested resolution from HAL. + * + * There is a performance impact when continuous view finder option is chose + * for resolutions above 8MP. So 8MP and 6MP resolution are kept, so that lower + * than these take 8MP or 6MP espectively for down scaling based on the + * aspect ratio. + */ +struct imx_resolution imx135_res_still_mofd[] = { + { + .desc = "imx135_cif_binning_still", + .regs = imx135_cif_binning_1888x1548, + .width = 1888, + .height = 1548, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 209600, + }, + { + .desc = "imx135_vga_binning_preview", + .regs = imx135_vga_binning, + .width = 1036, + .height = 780, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_480p_preview", + .regs = imx135_480p_binning, + .width = 1036, + .height = 696, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_1080p_binning_still", + .regs = imx135_1080p_binning, + .width = 1936, + .height = 1104, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 15, + .pixels_per_line = 9114, + .lines_per_frame = 2453, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_3m__still", + .regs = imx135_3m_binning, + .width = 2064, + .height = 1552, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 15, + .pixels_per_line = 9114, + .lines_per_frame = 2453, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_6m_for_mipi_342_still", + .regs = imx135_6m_for_mipi_342, + .width = 3280, + .height = 1852, + .fps_options = { + { /* Pixel clock: 273.6MHz */ + .fps = 11, + .pixels_per_line = 9114, + .lines_per_frame = 2664, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 342000, + }, + { + .desc = "imx135_8m_scaled_from_12m_for_mipi342_still", + .regs = imx135_8m_scaled_from_12m_for_mipi342, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 273.6MHz */ + .fps = 8, + .pixels_per_line = 7672, + .lines_per_frame = 4458, + }, + { /* Pixel clock: 273.6MHz */ + .fps = 15, + .pixels_per_line = 5500, + .lines_per_frame = 3314, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 342000, + }, + { + .desc = "imx135_10m_for_mipi_342_still", + .regs = imx135_10m_for_mipi_342, + .width = 4208, + .height = 2368, + .fps_options = { + { /* Pixel clock: 273.6MHz */ + .fps = 11, + .pixels_per_line = 9144, + .lines_per_frame = 2664, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 342000, + }, + { + .desc = "imx135_13m_still", + .regs = imx135_13m_for_mipi_342, + .width = 4208, + .height = 3120, + .fps_options = { + { /* Pixel clock: 273.6MHz */ + .fps = 5, + .pixels_per_line = 9144, + .lines_per_frame = 5990, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 342000, + }, +}; + +struct imx_resolution imx135_res_still[] = { + { + .desc = "imx135_qvga", + .regs = imx135_336x256, + .width = 336, + .height = 256, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_cif", + .regs = imx135_368x304_cropped, + .width = 368, + .height = 304, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_xga_cropped_video", + .regs = imx135_xga_cropped, + .width = 832, + .height = 628, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_2M_for_11:9", + .regs = imx135_1424x1168_cropped, + .width = 1424, + .height = 1168, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_2m_cropped_video", + .regs = imx135_2m_cropped, + .width = 1648, + .height = 1240, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 15, + .pixels_per_line = 6466, + .lines_per_frame = 3710, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_6m_cropped_video", + .regs = imx135_6m_cropped, + .width = 3280, + .height = 1852, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 8, + .pixels_per_line = 8850, + .lines_per_frame = 5080, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_8m_cropped_video", + .regs = imx135_8m_cropped, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 8, + .pixels_per_line = 8850, + .lines_per_frame = 5080, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, +}; + +/* + * ISP scaling is not supported in case of video modes. So we need to have + * separate sensor mode for video use cases + */ +struct imx_resolution imx135_res_video[] = { + /* For binning modes pix clock is 335.36 MHz. */ + { + .desc = "imx135_qcif_dvs_binning_video", + .regs = imx135_qcif_dvs_binning, + .width = 216, + .height = 176, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_cif_binning_video", + .regs = imx135_cif_binning, + .width = 368, + .height = 304, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_qvga__dvs_binning_video", + .regs = imx135_qvga__dvs_binning, + .width = 408, + .height = 308, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_436x360_binning_video", + .regs = imx135_436x360_binning, + .width = 436, + .height = 360, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_vga_dvs_binning_video", + .regs = imx135_vga_dvs_binning, + .width = 820, + .height = 616, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_480p_dvs_binning_video", + .regs = imx135_480p_dvs_binning, + .width = 936, + .height = 602, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 209600, + }, + { + .desc = "imx135_720P_dvs_video", + .regs = imx135_720pdvs_max_clock, + .width = 1568, + .height = 880, + .fps_options = { + {/* Pixel Clock : 360.96 MHz */ + .fps = 30, + .pixels_per_line = 5850, + .lines_per_frame = 2000, + }, + {/* Pixel Clock : 360.96 MHz */ + .fps = 60, + .pixels_per_line = 4572, + .lines_per_frame = 1310, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 451200, + }, + { + .desc = "imx135_wvga_dvs_binning_video", + .regs = imx135_wvga_dvs_binning, + .width = 1640, + .height = 1024, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 209600, + }, + { + .desc = "imx135_1936_1096_fullfov_max_clock", + .regs = imx135_1080p_nodvs_max_clock, + .width = 1936, + .height = 1096, + .fps_options = { + {/* Pixel Clock : 360.96 MHz */ + .fps = 30, + .pixels_per_line = 5850, + .lines_per_frame = 2000, + }, + {/* Pixel Clock : 360.96 MHz */ + .fps = 60, + .pixels_per_line = 4572, + .lines_per_frame = 1310, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 451200, + }, + { + .desc = "imx135_1080P_dvs_video", + .regs = imx135_2336x1320_max_clock, + .width = 2336, + .height = 1320, + .fps_options = { + {/* Pixel Clock : 360.96 MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2632, + .regs = imx135_2336x1320_max_clock, + .mipi_freq = 451200, + }, + {/* Pixel Clock : 399.36MHz */ + .fps = 60, + .pixels_per_line = 4754, + .lines_per_frame = 1400, + .regs = imx135_2336x1320_cropped_mipi499, + .mipi_freq = 499200, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_6m_cont_cap", + .regs = imx135_6m, + .width = 3280, + .height = 1852, + .fps_options = { + { /* Binning Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_8m_cropped_video", + .regs = imx135_8m_cropped, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, +}; + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/imx175.h b/drivers/staging/media/atomisp/i2c/imx/imx175.h new file mode 100644 index 0000000..5f409cc --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx175.h @@ -0,0 +1,1959 @@ +#ifndef __IMX175_H__ +#define __IMX175_H__ +#include "common.h" + +/************************** settings for imx *************************/ +static struct imx_reg const imx_STILL_8M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0C}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD0}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x09}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xA0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_8M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0C}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD0}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x09}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xA0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_3M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x08}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x06}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x10}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x19}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_3M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x08}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x06}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x10}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x19}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + + +static struct imx_reg const imx_STILL_5M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0A}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x07}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x90}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x14}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_5M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0A}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x07}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x90}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x14}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_6M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x32}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x6D}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0C}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD0}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x07}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x3C}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_6M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x32}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x6D}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0C}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD0}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x07}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x3C}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_2M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x8C}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x68}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xD0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_2M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x8C}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x68}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xD0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_PREVIEW_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x06}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x05}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x48}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x70}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x03}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x34}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x68}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x03}, + {IMX_8BIT, 0x33D5, 0x34}, + {IMX_8BIT, 0x33D6, 0x02}, + {IMX_8BIT, 0x33D7, 0x68}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_WIDE_PREVIEW_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x06}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0D}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x70}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x10}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x00}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x14}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x8C}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x68}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xBC}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x68}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0xBC}, + {IMX_TOK_TERM, 0, 0} +}; + +/*****************************video************************/ +static struct imx_reg const imx_1080p_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x06}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x4C}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xA4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x11}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0xC6}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0xDB}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x02}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x42}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0A}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xEA}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x07}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x61}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x09}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x05}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x20}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_1080p_no_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x08}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xD5}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x07}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xD0}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0F}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x3C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x34}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x6B}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x07}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x94}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x44}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x1B}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_1080p_no_dvs_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x08}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xD5}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xA6}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x18}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x9C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x34}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x6B}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x07}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x94}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x44}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x1B}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; +/*****************************video************************/ +static struct imx_reg const imx_720p_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x13}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x9C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0xD7}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x02}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x3E}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0A}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xEE}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x07}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x65}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x70}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x18}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_480p_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x13}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x9C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0xD4}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0xC8}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0A}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xF1}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x07}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0xDB}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x03}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x70}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x50}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x15}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_720p_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x05}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x48}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x14}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x28}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x48}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x64}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0x87}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x3B}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x20}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x6C}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_720p_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x08}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xCA}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x18}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x38}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x48}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x64}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0x87}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x3B}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x20}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x6C}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_WVGA_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x13}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x9C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0xD0}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0xCF}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x68}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x00}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; +static struct imx_reg const imx_CIF_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x11}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0xDB}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x01}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x70}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x01}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x30}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_VGA_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x11}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x94}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x03}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x34}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x68}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_VGA_strong_dvs_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x07}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x9E}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x1C}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0xB6}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x03}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x34}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x68}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_QVGA_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x06}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x05}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x48}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x70}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x03}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x38}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x02}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x68}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x09}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0x97}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x07}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x37}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x01}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x98}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x01}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x34}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x01}, + {IMX_8BIT, 0x33D5, 0x98}, + {IMX_8BIT, 0x33D6, 0x01}, + {IMX_8BIT, 0x33D7, 0x34}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_QCIF_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x06}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x05}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x48}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x70}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x04}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0xB8}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x03}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x70}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x08}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0x17}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x06}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x2F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x00}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD8}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x00}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xB0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x00}, + {IMX_8BIT, 0x33D5, 0xD8}, + {IMX_8BIT, 0x33D6, 0x00}, + {IMX_8BIT, 0x33D7, 0xB0}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx175_init_settings[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0103, 0x01}, + /* misc control */ + {IMX_8BIT, 0x3020, 0x10}, + {IMX_8BIT, 0x302D, 0x02}, + {IMX_8BIT, 0x302F, 0x80}, + {IMX_8BIT, 0x3032, 0xA3}, + {IMX_8BIT, 0x3033, 0x20}, + {IMX_8BIT, 0x3034, 0x24}, + {IMX_8BIT, 0x3041, 0x15}, + {IMX_8BIT, 0x3042, 0x87}, + {IMX_8BIT, 0x3050, 0x35}, + {IMX_8BIT, 0x3056, 0x57}, + {IMX_8BIT, 0x305D, 0x41}, + {IMX_8BIT, 0x3097, 0x69}, + {IMX_8BIT, 0x3109, 0x41}, + {IMX_8BIT, 0x3148, 0x3F}, + {IMX_8BIT, 0x330F, 0x07}, + /* csi & inck */ + {IMX_8BIT, 0x3364, 0x00}, + {IMX_8BIT, 0x3368, 0x13}, + {IMX_8BIT, 0x3369, 0x33}, + /* znr */ + {IMX_8BIT, 0x4100, 0x0E}, + {IMX_8BIT, 0x4104, 0x32}, + {IMX_8BIT, 0x4105, 0x32}, + {IMX_8BIT, 0x4108, 0x01}, + {IMX_8BIT, 0x4109, 0x7C}, + {IMX_8BIT, 0x410A, 0x00}, + {IMX_8BIT, 0x410B, 0x00}, + GROUPED_PARAMETER_HOLD_DISABLE, + {IMX_TOK_TERM, 0, 0} +}; +/* TODO settings of preview/still/video will be updated with new use case */ +struct imx_resolution imx175_res_preview[] = { + { + .desc = "CIF_strong_dvs_30fps", + .regs = imx_CIF_strong_dvs_30fps, + .width = 368, + .height = 304, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x11DB, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 261500, + + }, + { + .desc = "VGA_strong_dvs_30fps", + .regs = imx_VGA_strong_dvs_30fps, + .width = 820, + .height = 616, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x11DB, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "WIDE_PREVIEW_30fps", + .regs = imx_WIDE_PREVIEW_30fps, + .width = 1640, + .height = 956, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x1000, + .lines_per_frame = 0x0D70, + }, + { + } + }, + .mipi_freq = 174500, + }, + { + .desc = "STILL_720p_30fps", + .regs = imx_STILL_720p_30fps, + .width = 1568, + .height = 876, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x1428, + .lines_per_frame = 0x0548, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "STILL_2M_30fps", + .regs = imx_STILL_2M_30fps, + .width = 1640, + .height = 1232, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "1080p_strong_dvs_30fps", + .regs = imx_1080p_no_dvs_30fps, + .width = 1940, + .height = 1092, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0F3C, + .lines_per_frame = 0x07D0, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "STILL_3M_30fps", + .regs = imx_STILL_3M_30fps, + .width = 2064, + .height = 1552, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_5M_30fps", + .regs = imx_STILL_5M_30fps, + .width = 2576, + .height = 1936, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_6M_30fps", + .regs = imx_STILL_6M_30fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_8M_30fps", + .regs = imx_STILL_8M_30fps, + .width = 3280, + .height = 2464, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, +}; + +struct imx_resolution imx175_res_still[] = { + { + .desc = "CIF_strong_dvs_30fps", + .regs = imx_CIF_strong_dvs_30fps, + .width = 368, + .height = 304, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x11DB, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 261000, + }, + { + .desc = "VGA_strong_dvs_15fps", + .regs = imx_VGA_strong_dvs_15fps, + .width = 820, + .height = 616, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1C86, + .lines_per_frame = 0x079E, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "imx_STILL_720p_15fps", + .regs = imx_STILL_720p_15fps, + .width = 1568, + .height = 876, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1838, + .lines_per_frame = 0x08CA, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "STILL_2M_15fps", + .regs = imx_STILL_2M_15fps, + .width = 1640, + .height = 1232, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "1080p_strong_dvs_15fps", + .regs = imx_1080p_no_dvs_15fps, + .width = 1940, + .height = 1092, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x189C, + .lines_per_frame = 0x09A6, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "STILL_3M_15fps", + .regs = imx_STILL_3M_15fps, + .width = 2064, + .height = 1552, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_5M_15fps", + .regs = imx_STILL_5M_15fps, + .width = 2576, + .height = 1936, + .fps = 15, + .pixels_per_line = 0x1646, /* consistent with regs arrays */ + .lines_per_frame = 0x0BB8, /* consistent with regs arrays */ + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_6M_15fps", + .regs = imx_STILL_6M_15fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_8M_15fps", + .regs = imx_STILL_8M_15fps, + .width = 3280, + .height = 2464, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, +}; + +struct imx_resolution imx175_res_video[] = { + { + .desc = "QCIF_strong_dvs_30fps", + .regs = imx_QCIF_strong_dvs_30fps, + .width = 216, + .height = 176, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D70, + .lines_per_frame = 0x0548, + }, + { + } + }, + .mipi_freq = 174500, + }, + { + .desc = "QVGA_strong_dvs_30fps", + .regs = imx_QVGA_strong_dvs_30fps, + .width = 408, + .height = 308, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D70, + .lines_per_frame = 0x0548, + }, + { + } + }, + .mipi_freq = 174500, + }, + { + .desc = "VGA_strong_dvs_30fps", + .regs = imx_VGA_strong_dvs_30fps, + .width = 820, + .height = 616, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x1194, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "720p_strong_dvs_30fps", + .regs = imx_720p_strong_dvs_30fps, + .width = 1552, + .height = 880, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x139C, + .lines_per_frame = 0x0600, + }, + { + .fps = 60, + .pixels_per_line = 0xD70, + .lines_per_frame = 0x444, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "480p_strong_dvs_30fps", + .regs = imx_480p_strong_dvs_30fps, + .width = 880, + .height = 592, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x139C, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "WVGA_strong_dvs_30fps", + .regs = imx_WVGA_strong_dvs_30fps, + .width = 1640, + .height = 1024, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x139C, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "1080p_strong_dvs_30fps", + .regs = imx_1080p_strong_dvs_30fps, + .width = 2320, + .height = 1312, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x11C6, + .lines_per_frame = 0x06A4, + }, + { + } + }, + .mipi_freq = 292500, + }, +}; + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/imx208.h b/drivers/staging/media/atomisp/i2c/imx/imx208.h new file mode 100644 index 0000000..fed387f --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx208.h @@ -0,0 +1,550 @@ +/* + * Support for Sony IMX camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __IMX208_H__ +#define __IMX208_H__ +#include "common.h" + +/********************** settings for imx from vendor*********************/ +static struct imx_reg imx208_1080p_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x07}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x8F}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x04}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x47}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x07}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0x90}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0x48}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x01}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x01}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x00}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x00}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x61}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx208_1296x736_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x40}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0xB4}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x06}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x4F}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x03}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x93}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x05}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0xE0}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x01}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x01}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x00}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x00}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x61}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx208_1296x976_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x40}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0x3C}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x06}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x4F}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x04}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x0B}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x05}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0xD0}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x01}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x01}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x00}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x00}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x61}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx208_336x256_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x02}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x78}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0x24}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x05}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x17}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x03}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x23}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x01}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0x50}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x01}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0x00}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x03}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x03}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x01}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x03}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x66}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx208_192x160_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x02}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x48}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0xE4}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x05}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x47}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x03}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x63}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x00}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0xC0}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x00}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0xA0}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x03}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x05}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x03}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x05}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x01}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x03}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x11}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x74}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; +/********************** settings for imx - reference *********************/ +static struct imx_reg const imx208_init_settings[] = { + { IMX_TOK_TERM, 0, 0} +}; + +struct imx_resolution imx208_res_preview[] = { + { + .desc = "imx208_1080p_30fps", + .regs = imx208_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x976_30fps", + .regs = imx208_1296x976_30fps, + .width = 1296, + .height = 976, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x736_30fps", + .regs = imx208_1296x736_30fps, + .width = 1296, + .height = 736, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_336x256_30fps", + .regs = imx208_336x256_30fps, + .width = 336, + .height = 256, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .skip_frames = 2, + .mipi_freq = 201600, + }, + { + .desc = "imx208_192x160_30fps", + .regs = imx208_192x160_30fps, + .width = 192, + .height = 160, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .skip_frames = 2, + .mipi_freq = 100800, + }, +}; + +struct imx_resolution imx208_res_still[] = { + { + .desc = "imx208_1080p_30fps", + .regs = imx208_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x976_30fps", + .regs = imx208_1296x976_30fps, + .width = 1296, + .height = 976, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x736_30fps", + .regs = imx208_1296x736_30fps, + .width = 1296, + .height = 736, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_336x256_30fps", + .regs = imx208_336x256_30fps, + .width = 336, + .height = 256, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .skip_frames = 2, + .mipi_freq = 201600, + }, + { + .desc = "imx208_192x160_30fps", + .regs = imx208_192x160_30fps, + .width = 192, + .height = 160, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .skip_frames = 2, + .mipi_freq = 100800, + }, +}; + +struct imx_resolution imx208_res_video[] = { + { + .desc = "imx208_1080p_30fps", + .regs = imx208_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x976_30fps", + .regs = imx208_1296x976_30fps, + .width = 1296, + .height = 976, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x736_30fps", + .regs = imx208_1296x736_30fps, + .width = 1296, + .height = 736, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_336x256_30fps", + .regs = imx208_336x256_30fps, + .width = 336, + .height = 256, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .skip_frames = 2, + .mipi_freq = 201600, + }, + { + .desc = "imx208_192x160_30fps", + .regs = imx208_192x160_30fps, + .width = 192, + .height = 160, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .skip_frames = 2, + .mipi_freq = 100800, + }, +}; +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx219.h b/drivers/staging/media/atomisp/i2c/imx/imx219.h new file mode 100644 index 0000000..52df582 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx219.h @@ -0,0 +1,227 @@ +#ifndef __IMX219_H__ +#define __IMX219_H__ +#include "common.h" + +#define IMX219_FRAME_LENGTH_LINES 0x0160 +#define IMX219_LINE_LENGTH_PIXELS 0x0162 +#define IMX219_HORIZONTAL_START_H 0x0164 +#define IMX219_VERTICAL_START_H 0x0168 +#define IMX219_HORIZONTAL_END_H 0x0166 +#define IMX219_VERTICAL_END_H 0x016A +#define IMX219_HORIZONTAL_OUTPUT_SIZE_H 0x016c +#define IMX219_VERTICAL_OUTPUT_SIZE_H 0x016E +#define IMX219_COARSE_INTEGRATION_TIME 0x015A +#define IMX219_IMG_ORIENTATION 0x0172 +#define IMX219_GLOBAL_GAIN 0x0157 +#define IMX219_DGC_ADJ 0x0158 + +#define IMX219_DGC_LEN 4 + +/************************** settings for imx *************************/ +static struct imx_reg const imx219_STILL_8M_30fps[] = { + {IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x0C}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x300A, 0xFF}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x300B, 0xFF}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x09}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x0114, 0x03}, /*CSI_LANE_MODE[1:0}*/ + {IMX_8BIT, 0x0128, 0x00}, /*DPHY_CNTRL*/ + {IMX_8BIT, 0x012A, 0x13}, /*EXCK_FREQ[15:8]*/ + {IMX_8BIT, 0x012B, 0x34}, /*EXCK_FREQ[7:0]*/ + {IMX_8BIT, 0x0160, 0x0A}, /*FRM_LENGTH_A[15:8]*/ + {IMX_8BIT, 0x0161, 0x94}, /*FRM_LENGTH_A[7:0]*/ + {IMX_8BIT, 0x0162, 0x0D}, /*LINE_LENGTH_A[15:8]*/ + {IMX_8BIT, 0x0163, 0x78}, /*LINE_LENGTH_A[7:0]*/ + {IMX_8BIT, 0x0164, 0x00}, /*X_ADD_STA_A[11:8]*/ + {IMX_8BIT, 0x0165, 0x00}, /*X_ADD_STA_A[7:0]*/ + {IMX_8BIT, 0x0166, 0x0C}, /*X_ADD_END_A[11:8]*/ + {IMX_8BIT, 0x0167, 0xCF}, /*X_ADD_END_A[7:0]*/ + {IMX_8BIT, 0x0168, 0x00}, /*Y_ADD_STA_A[11:8]*/ + {IMX_8BIT, 0x0169, 0x00}, /*Y_ADD_STA_A[7:0]*/ + {IMX_8BIT, 0x016A, 0x09}, /*Y_ADD_END_A[11:8]*/ + {IMX_8BIT, 0x016B, 0x9F}, /*Y_ADD_END_A[7:0]*/ + {IMX_8BIT, 0x016C, 0x0C}, /*X_OUTPUT_SIZE_A[11:8]*/ + {IMX_8BIT, 0x016D, 0xD0}, /*X_OUTPUT_SIZE_A[7:0]*/ + {IMX_8BIT, 0x016E, 0x09}, /*Y_OUTPUT_SIZE_A[11:8]*/ + {IMX_8BIT, 0x016F, 0xA0}, /*Y_OUTPUT_SIZE_A[7:0]*/ + {IMX_8BIT, 0x0170, 0x01}, /*X_ODD_INC_A[2:0]*/ + {IMX_8BIT, 0x0171, 0x01}, /*Y_ODD_INC_A[2:0]*/ + {IMX_8BIT, 0x0174, 0x00}, /*BINNING_MODE_H_A*/ + {IMX_8BIT, 0x0175, 0x00}, /*BINNING_MODE_V_A*/ + {IMX_8BIT, 0x018C, 0x0A}, /*CSI_DATA_FORMAT_A[15:8]*/ + {IMX_8BIT, 0x018D, 0x0A}, /*CSI_DATA_FORMAT_A[7:0]*/ + {IMX_8BIT, 0x0301, 0x05}, /*VTPXCK_DIV*/ + {IMX_8BIT, 0x0303, 0x01}, /*VTSYCK_DIV*/ + {IMX_8BIT, 0x0304, 0x02}, /*PREPLLCK_VT_DIV[3:0]*/ + {IMX_8BIT, 0x0305, 0x02}, /*PREPLLCK_OP_DIV[3:0]*/ + {IMX_8BIT, 0x0306, 0x00}, /*PLL_VT_MPY[10:8]*/ + {IMX_8BIT, 0x0307, 0x49}, /*PLL_VT_MPY[7:0]*/ + {IMX_8BIT, 0x0309, 0x0A}, /*OPPXCK_DIV[4:0]*/ + {IMX_8BIT, 0x030B, 0x01}, /*OPSYCK_DIV*/ + {IMX_8BIT, 0x030C, 0x00}, /*PLL_OP_MPY[10:8]*/ + {IMX_8BIT, 0x030D, 0x4C}, /*PLL_OP_MPY[7:0]*/ + {IMX_8BIT, 0x4767, 0x0F}, /*CIS Tuning*/ + {IMX_8BIT, 0x4750, 0x14}, /*CIS Tuning*/ + {IMX_8BIT, 0x47B4, 0x14}, /*CIS Tuning*/ + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx219_STILL_6M_30fps[] = { + {IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x0C}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x300A, 0xFF}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x300B, 0xFF}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x09}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x0114, 0x03}, /*CSI_LANE_MODE[1:0}*/ + {IMX_8BIT, 0x0128, 0x00}, /*DPHY_CNTRL*/ + {IMX_8BIT, 0x012A, 0x13}, /*EXCK_FREQ[15:8]*/ + {IMX_8BIT, 0x012B, 0x34}, /*EXCK_FREQ[7:0]*/ + {IMX_8BIT, 0x0160, 0x07}, /*FRM_LENGTH_A[15:8]*/ + {IMX_8BIT, 0x0161, 0x64}, /*FRM_LENGTH_A[7:0]*/ + {IMX_8BIT, 0x0162, 0x0D}, /*LINE_LENGTH_A[15:8]*/ + {IMX_8BIT, 0x0163, 0x78}, /*LINE_LENGTH_A[7:0]*/ + {IMX_8BIT, 0x0164, 0x00}, /*X_ADD_STA_A[11:8]*/ + {IMX_8BIT, 0x0165, 0x00}, /*X_ADD_STA_A[7:0]*/ + {IMX_8BIT, 0x0166, 0x0C}, /*X_ADD_END_A[11:8]*/ + {IMX_8BIT, 0x0167, 0xCF}, /*X_ADD_END_A[7:0]*/ + {IMX_8BIT, 0x0168, 0x01}, /*Y_ADD_STA_A[11:8]*/ + {IMX_8BIT, 0x0169, 0x32}, /*Y_ADD_STA_A[7:0]*/ + {IMX_8BIT, 0x016A, 0x08}, /*Y_ADD_END_A[11:8]*/ + {IMX_8BIT, 0x016B, 0x6D}, /*Y_ADD_END_A[7:0]*/ + {IMX_8BIT, 0x016C, 0x0C}, /*X_OUTPUT_SIZE_A[11:8]*/ + {IMX_8BIT, 0x016D, 0xD0}, /*X_OUTPUT_SIZE_A[7:0]*/ + {IMX_8BIT, 0x016E, 0x07}, /*Y_OUTPUT_SIZE_A[11:8]*/ + {IMX_8BIT, 0x016F, 0x3C}, /*Y_OUTPUT_SIZE_A[7:0]*/ + {IMX_8BIT, 0x0170, 0x01}, /*X_ODD_INC_A[2:0]*/ + {IMX_8BIT, 0x0171, 0x01}, /*Y_ODD_INC_A[2:0]*/ + {IMX_8BIT, 0x0174, 0x00}, /*BINNING_MODE_H_A*/ + {IMX_8BIT, 0x0175, 0x00}, /*BINNING_MODE_V_A*/ + {IMX_8BIT, 0x018C, 0x0A}, /*CSI_DATA_FORMAT_A[15:8]*/ + {IMX_8BIT, 0x018D, 0x0A}, /*CSI_DATA_FORMAT_A[7:0]*/ + {IMX_8BIT, 0x0301, 0x05}, /*VTPXCK_DIV*/ + {IMX_8BIT, 0x0303, 0x01}, /*VTSYCK_DIV*/ + {IMX_8BIT, 0x0304, 0x02}, /*PREPLLCK_VT_DIV[3:0]*/ + {IMX_8BIT, 0x0305, 0x02}, /*PREPLLCK_OP_DIV[3:0]*/ + {IMX_8BIT, 0x0306, 0x00}, /*PLL_VT_MPY[10:8]*/ + {IMX_8BIT, 0x0307, 0x33}, /*PLL_VT_MPY[7:0]*/ + {IMX_8BIT, 0x0309, 0x0A}, /*OPPXCK_DIV[4:0]*/ + {IMX_8BIT, 0x030B, 0x01}, /*OPSYCK_DIV*/ + {IMX_8BIT, 0x030C, 0x00}, /*PLL_OP_MPY[10:8]*/ + {IMX_8BIT, 0x030D, 0x36}, /*PLL_OP_MPY[7:0]*/ + {IMX_8BIT, 0x4767, 0x0F}, /*CIS Tuning*/ + {IMX_8BIT, 0x4750, 0x14}, /*CIS Tuning*/ + {IMX_8BIT, 0x47B4, 0x14}, /*CIS Tuning*/ + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx219_init_settings[] = { + {IMX_TOK_TERM, 0, 0} +}; + +struct imx_resolution imx219_res_preview[] = { + { + .desc = "STILL_6M_30fps", + .regs = imx219_STILL_6M_30fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0764, + }, + { + } + }, + .mipi_freq = 259000, + }, + { + .desc = "STILL_8M_30fps", + .regs = imx219_STILL_8M_30fps, + .width = 3280, + .height = 2464, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0A94, + }, + { + } + }, + .mipi_freq = 365000, + }, +}; + +struct imx_resolution imx219_res_still[] = { + { + .desc = "STILL_6M_30fps", + .regs = imx219_STILL_6M_30fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0764, + }, + { + } + }, + .mipi_freq = 259000, + }, + { + .desc = "STILL_8M_30fps", + .regs = imx219_STILL_8M_30fps, + .width = 3280, + .height = 2464, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0A94, + }, + { + } + }, + .mipi_freq = 365000, + }, +}; + +struct imx_resolution imx219_res_video[] = { + { + .desc = "STILL_6M_30fps", + .regs = imx219_STILL_6M_30fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0764, + }, + { + } + }, + .mipi_freq = 259000, + }, +}; + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/imx227.h b/drivers/staging/media/atomisp/i2c/imx/imx227.h new file mode 100644 index 0000000..10e5b86 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx227.h @@ -0,0 +1,726 @@ +#ifndef __IMX227_H__ +#define __IMX227_H__ + +#include "common.h" + +#define IMX227_EMBEDDED_DATA_LINE_NUM 2 +#define IMX227_OUTPUT_DATA_FORMAT_REG 0x0112 +#define IMX227_OUTPUT_FORMAT_RAW10 0x0a0a + +/* AE Bracketing Registers */ +#define IMX227_BRACKETING_LUT_MODE_BIT_CONTINUE_STREAMING 0x1 +#define IMX227_BRACKETING_LUT_MODE_BIT_LOOP_MODE 0x2 + +#define IMX227_BRACKETING_LUT_CONTROL 0x0E00 +#define IMX227_BRACKETING_LUT_MODE 0x0E01 +#define IMX227_BRACKETING_LUT_ENTRY_CONTROL 0x0E02 + +/* + * The imx135 embedded data info: + * embedded data line num: 2 + * line 0 effective data size(byte): 76 + * line 1 effective data size(byte): 113 + */ +static const uint32_t +imx227_embedded_effective_size[IMX227_EMBEDDED_DATA_LINE_NUM] = {160, 62}; + +/************************** settings for imx *************************/ +/* Full Output Mode */ +static struct imx_reg const imx_STILL_6_5M_25fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x6259, 0x06}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xd0}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* 4:3 Output Mode */ +static struct imx_reg const imx_STILL_5_5M_3X4_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0xb0}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x00}, + {IMX_8BIT, 0x0348, 0x08}, + {IMX_8BIT, 0x0349, 0xaf}, + {IMX_8BIT, 0x034a, 0x0a}, + {IMX_8BIT, 0x034b, 0x9f}, + {IMX_8BIT, 0x034c, 0x08}, + {IMX_8BIT, 0x034d, 0x00}, + {IMX_8BIT, 0x034e, 0x0a}, + {IMX_8BIT, 0x034f, 0xa0}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xd8}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Square Output Mode */ +static struct imx_reg const imx_STILL_5_7M_1X1_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0xa0}, + {IMX_8BIT, 0x0348, 0x09}, + {IMX_8BIT, 0x0349, 0x5f}, + {IMX_8BIT, 0x034a, 0x09}, + {IMX_8BIT, 0x034b, 0xff}, + {IMX_8BIT, 0x034c, 0x09}, + {IMX_8BIT, 0x034d, 0x60}, + {IMX_8BIT, 0x034e, 0x09}, + {IMX_8BIT, 0x034f, 0x60}, + + {IMX_8BIT, 0x6259, 0x06}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xd4}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Full Frame 1080P Mode (use ISP scaler)*/ +static struct imx_reg const imx_VIDEO_4M_9X16_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xdc}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Cropped 1080P Mode */ +static struct imx_reg const imx_VIDEO_2M_9X16_45fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x02}, + {IMX_8BIT, 0x0345, 0x8a}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x88}, + {IMX_8BIT, 0x0348, 0x06}, + {IMX_8BIT, 0x0349, 0xd1}, + {IMX_8BIT, 0x034a, 0x09}, + {IMX_8BIT, 0x034b, 0x17}, + {IMX_8BIT, 0x034c, 0x04}, + {IMX_8BIT, 0x034d, 0x48}, + {IMX_8BIT, 0x034e, 0x07}, + {IMX_8BIT, 0x034f, 0x90}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x01}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x00}, + {IMX_8BIT, 0x040c, 0x04}, + {IMX_8BIT, 0x040d, 0x48}, + {IMX_8BIT, 0x040e, 0x07}, + {IMX_8BIT, 0x040f, 0x90}, + + {IMX_8BIT, 0x0900, 0x00}, + {IMX_8BIT, 0x0901, 0x00}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xdc}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Moment mode */ +static struct imx_reg const imx_VIDEO_1_3M_3X4_60fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xd9}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* High Speed 3:4 mode */ +static struct imx_reg const imx_VIDEO_VGA_3X4_120fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x9004, 0xca}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + + +/* Binned 720P mode */ +static struct imx_reg const imx_VIDEO_1M_9X16_60fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xd0}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x40}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0x8f}, + {IMX_8BIT, 0x034a, 0x0a}, + {IMX_8BIT, 0x034b, 0x5f}, + {IMX_8BIT, 0x034c, 0x02}, + {IMX_8BIT, 0x034d, 0xe0}, + {IMX_8BIT, 0x034e, 0x05}, + {IMX_8BIT, 0x034f, 0x10}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x01}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x00}, + {IMX_8BIT, 0x040c, 0x02}, + {IMX_8BIT, 0x040d, 0xe0}, + {IMX_8BIT, 0x040e, 0x05}, + {IMX_8BIT, 0x040f, 0x10}, + + {IMX_8BIT, 0x0900, 0x01}, + {IMX_8BIT, 0x0901, 0x22}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xdd}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Binned 496x868 mode */ +static struct imx_reg const imx_VIDEO_496x868_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x02}, + {IMX_8BIT, 0x0345, 0xc0}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0xec}, + {IMX_8BIT, 0x0348, 0x06}, + {IMX_8BIT, 0x0349, 0x9f}, + {IMX_8BIT, 0x034a, 0x08}, + {IMX_8BIT, 0x034b, 0xb3}, + {IMX_8BIT, 0x034c, 0x01}, + {IMX_8BIT, 0x034d, 0xf0}, + {IMX_8BIT, 0x034e, 0x03}, + {IMX_8BIT, 0x034f, 0x64}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x01}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x00}, + {IMX_8BIT, 0x040c, 0x01}, + {IMX_8BIT, 0x040d, 0xf0}, + {IMX_8BIT, 0x040e, 0x03}, + {IMX_8BIT, 0x040f, 0x64}, + + {IMX_8BIT, 0x0900, 0x01}, + {IMX_8BIT, 0x0901, 0x22}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xdd}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + + +/* Hangout mode */ +static struct imx_reg const imx_PREVIEW_374X652_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xc0}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x30}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0x9f}, + {IMX_8BIT, 0x034a, 0x0a}, + {IMX_8BIT, 0x034b, 0x6f}, + {IMX_8BIT, 0x034c, 0x01}, + {IMX_8BIT, 0x034d, 0x78}, + {IMX_8BIT, 0x034e, 0x02}, + {IMX_8BIT, 0x034f, 0x90}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x03}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x03}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x02}, + {IMX_8BIT, 0x040c, 0x01}, + {IMX_8BIT, 0x040d, 0x76}, + {IMX_8BIT, 0x040e, 0x02}, + {IMX_8BIT, 0x040f, 0x8c}, + + {IMX_8BIT, 0x0900, 0x01}, + {IMX_8BIT, 0x0901, 0x22}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xde}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_VIDEO_NHD_9X16_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xc0}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x30}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0x9f}, + {IMX_8BIT, 0x034a, 0x0a}, + {IMX_8BIT, 0x034b, 0x6f}, + {IMX_8BIT, 0x034c, 0x01}, + {IMX_8BIT, 0x034d, 0x78}, + {IMX_8BIT, 0x034e, 0x02}, + {IMX_8BIT, 0x034f, 0x90}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x03}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x03}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x00}, + {IMX_8BIT, 0x040c, 0x01}, + {IMX_8BIT, 0x040d, 0x78}, + {IMX_8BIT, 0x040e, 0x02}, + {IMX_8BIT, 0x040f, 0x90}, + + {IMX_8BIT, 0x0900, 0x01}, + {IMX_8BIT, 0x0901, 0x22}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xde}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + + +static struct imx_reg const imx227_init_settings[] = { + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0306, 0x00}, + {IMX_8BIT, 0x0307, 0xBB}, + {IMX_8BIT, 0x030E, 0x03}, + {IMX_8BIT, 0x030F, 0x0D}, + {IMX_8BIT, 0x463b, 0x30}, + {IMX_8BIT, 0x463e, 0x05}, + {IMX_8BIT, 0x4612, 0x66}, + {IMX_8BIT, 0x4815, 0x65}, + {IMX_8BIT, 0x4991, 0x00}, + {IMX_8BIT, 0x4992, 0x01}, + {IMX_8BIT, 0x4993, 0xff}, + {IMX_8BIT, 0x458b, 0x00}, + {IMX_8BIT, 0x452a, 0x02}, + {IMX_8BIT, 0x4a7c, 0x00}, + {IMX_8BIT, 0x4a7d, 0x1c}, + {IMX_8BIT, 0x4a7e, 0x00}, + {IMX_8BIT, 0x4a7f, 0x17}, + {IMX_8BIT, 0x462C, 0x2E}, + {IMX_8BIT, 0x461B, 0x28}, + {IMX_8BIT, 0x4663, 0x29}, + {IMX_8BIT, 0x461A, 0x7C}, + {IMX_8BIT, 0x4619, 0x28}, + {IMX_8BIT, 0x4667, 0x22}, + {IMX_8BIT, 0x466B, 0x23}, + {IMX_8BIT, 0x40AD, 0xFF}, + {IMX_8BIT, 0x40BE, 0x00}, + {IMX_8BIT, 0x40BF, 0x6E}, + {IMX_8BIT, 0x40CE, 0x00}, + {IMX_8BIT, 0x40CF, 0x0A}, + {IMX_8BIT, 0x40CA, 0x00}, + {IMX_8BIT, 0x40CB, 0x1F}, + {IMX_8BIT, 0x4D16, 0x00}, + {IMX_8BIT, 0x6204, 0x01}, + {IMX_8BIT, 0x6209, 0x00}, + {IMX_8BIT, 0x621F, 0x01}, + {IMX_8BIT, 0x621E, 0x10}, + GROUPED_PARAMETER_HOLD_DISABLE, + {IMX_TOK_TERM, 0, 0} +}; + +/* TODO settings of preview/still/video will be updated with new use case */ +struct imx_resolution imx227_res_preview[] = { + { + .desc = "imx_PREVIEW_374X652_30fps", + .regs = imx_PREVIEW_374X652_30fps, + .width = 374, + .height = 652, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C0A, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_496x868_30fps", + .regs = imx_VIDEO_496x868_30fps, + .width = 496, + .height = 868, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + } + }, + }, + { + .desc = "imx_STILL_5_5M_3X4_30fps", + .regs = imx_STILL_5_5M_3X4_30fps, + .width = 2048, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0ED8, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + + }, + { + .desc = "imx_STILL_5_7M_1X1_30fps", + .regs = imx_STILL_5_7M_1X1_30fps, + .width = 2400, + .height = 2400, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x1130, + .lines_per_frame = 0x0A1E, + }, + { + } + }, + + }, + { + .desc = "imx_STILL_6_5M_25fps", + .regs = imx_STILL_6_5M_25fps, + .width = 2400, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 25, + .pixels_per_line = 0x1130, + .lines_per_frame = 0x0C24, + }, + { + } + }, + } +}; + +struct imx_resolution imx227_res_still[] = { + { + .desc = "imx_STILL_5_5M_3X4_30fps", + .regs = imx_STILL_5_5M_3X4_30fps, + .width = 2048, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 6, + .pixels_per_line = 0x2130, + .lines_per_frame = 0x1A22, + }, + { + .fps = 30, + .pixels_per_line = 0x0ED8, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + + }, + { + .desc = "imx_STILL_5_7M_1X1_30fps", + .regs = imx_STILL_5_7M_1X1_30fps, + .width = 2400, + .height = 2400, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 6, + .pixels_per_line = 0x266E, + .lines_per_frame = 0x1704, + }, + { + .fps = 30, + .pixels_per_line = 0x1130, + .lines_per_frame = 0x0A1E, + }, + { + } + }, + + }, + { + .desc = "imx_STILL_6_5M_25fps", + .regs = imx_STILL_6_5M_25fps, + .width = 2400, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 25, + .pixels_per_line = 0x1130, + .lines_per_frame = 0x0C24, + }, + { + } + }, + }, +}; + +struct imx_resolution imx227_res_video[] = { + { + .desc = "imx_VIDEO_4M_9X16_30fps", + .regs = imx_VIDEO_4M_9X16_30fps, + .width = 1536, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + } + }, + + }, + { + .desc = "imx_VIDEO_2M_9X16_45fps", + .regs = imx_VIDEO_2M_9X16_45fps, + .width = 1096, + .height = 1936, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + .fps = 45, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0800, + }, + { + } + }, + + }, + { + .desc = "imx_VIDEO_1_3M_3X4_60fps", + .regs = imx_VIDEO_1_3M_3X4_60fps, + .width = 1024, + .height = 1360, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 60, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0604, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_496x868_30fps", + .regs = imx_VIDEO_496x868_30fps, + .width = 496, + .height = 868, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_1M_9X16_60fps", + .regs = imx_VIDEO_1M_9X16_60fps, + .width = 736, + .height = 1296, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 60, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0604, + }, + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C10, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_VGA_3X4_120fps", + .regs = imx_VIDEO_VGA_3X4_120fps, + .width = 512, + .height = 680, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 120, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0302, + }, + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_NHD_9X16_30fps", + .regs = imx_VIDEO_NHD_9X16_30fps, + .width = 376, + .height = 656, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C0A, + }, + { + } + }, + }, +}; + +#endif /* __IMX227_H__ */ diff --git a/drivers/staging/media/atomisp/i2c/imx/otp.c b/drivers/staging/media/atomisp/i2c/imx/otp.c new file mode 100644 index 0000000..4622750 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/otp.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/i2c.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/string.h> +#include <linux/types.h> +#include <media/v4l2-device.h> + +void *dummy_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 *buf; + + buf = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + return buf; +} diff --git a/drivers/staging/media/atomisp/i2c/imx/otp_brcc064_e2prom.c b/drivers/staging/media/atomisp/i2c/imx/otp_brcc064_e2prom.c new file mode 100644 index 0000000..b11f90c --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/otp_brcc064_e2prom.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/types.h> +#include <media/v4l2-device.h> +#include "common.h" + +/* + * Read EEPROM data from brcc064 and store + * it into a kmalloced buffer. On error return NULL. + * @size: set to the size of the returned EEPROM data. + */ +void *brcc064_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int e2prom_i2c_addr = dev_addr >> 1; + static const unsigned int max_read_size = 30; + int addr; + u32 s_addr = start_addr & E2PROM_ADDR_MASK; + unsigned char *buffer; + + buffer = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buffer) + return NULL; + + for (addr = s_addr; addr < size; addr += max_read_size) { + struct i2c_msg msg[2]; + unsigned int i2c_addr = e2prom_i2c_addr; + u16 addr_buf; + int r; + + msg[0].flags = 0; + msg[0].addr = i2c_addr; + addr_buf = cpu_to_be16(addr & 0xFFFF); + msg[0].len = 2; + msg[0].buf = (u8 *)&addr_buf; + + msg[1].addr = i2c_addr; + msg[1].flags = I2C_M_RD; + msg[1].len = min(max_read_size, size - addr); + msg[1].buf = &buffer[addr]; + + r = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); + if (r != ARRAY_SIZE(msg)) { + dev_err(&client->dev, "read failed at 0x%03x\n", addr); + return NULL; + } + } + return buffer; + +} + + diff --git a/drivers/staging/media/atomisp/i2c/imx/otp_e2prom.c b/drivers/staging/media/atomisp/i2c/imx/otp_e2prom.c new file mode 100644 index 0000000..73d041f --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/otp_e2prom.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/types.h> +#include <media/v4l2-device.h> +#include "common.h" + +/* + * Read EEPROM data from the gerneral e2prom chip(eg. + * CAT24C08, CAT24C128, le24l042cs, and store + * it into a kmalloced buffer. On error return NULL. + * @size: set to the size of the returned EEPROM data. + */ +void *e2prom_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int e2prom_i2c_addr = dev_addr >> 1; + static const unsigned int max_read_size = 30; + int addr; + u32 s_addr = start_addr & E2PROM_ADDR_MASK; + bool two_addr = (start_addr & E2PROM_2ADDR) >> 31; + char *buffer; + + buffer = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buffer) + return NULL; + + for (addr = s_addr; addr < size; addr += max_read_size) { + struct i2c_msg msg[2]; + unsigned int i2c_addr = e2prom_i2c_addr; + u16 addr_buf; + int r; + + msg[0].flags = 0; + if (two_addr) { + msg[0].addr = i2c_addr; + addr_buf = cpu_to_be16(addr & 0xFFFF); + msg[0].len = 2; + msg[0].buf = (u8 *)&addr_buf; + } else { + i2c_addr |= (addr >> 8) & 0x7; + msg[0].addr = i2c_addr; + addr_buf = addr & 0xFF; + msg[0].len = 1; + msg[0].buf = (u8 *)&addr_buf; + } + + msg[1].addr = i2c_addr; + msg[1].flags = I2C_M_RD; + msg[1].len = min(max_read_size, size - addr); + msg[1].buf = &buffer[addr]; + + r = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); + if (r != ARRAY_SIZE(msg)) { + dev_err(&client->dev, "read failed at 0x%03x\n", addr); + return NULL; + } + } + return buffer; +} + + diff --git a/drivers/staging/media/atomisp/i2c/imx/otp_imx.c b/drivers/staging/media/atomisp/i2c/imx/otp_imx.c new file mode 100644 index 0000000..1ca27c2 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/otp_imx.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/types.h> +#include <media/v4l2-device.h> +#include <asm/intel-mid.h> +#include "common.h" + +/* Defines for OTP Data Registers */ +#define IMX_OTP_START_ADDR 0x3B04 +#define IMX_OTP_PAGE_SIZE 64 +#define IMX_OTP_READY_REG 0x3B01 +#define IMX_OTP_PAGE_REG 0x3B02 +#define IMX_OTP_MODE_REG 0x3B00 +#define IMX_OTP_PAGE_MAX 20 +#define IMX_OTP_READY_REG_DONE 1 +#define IMX_OTP_READ_ONETIME 32 +#define IMX_OTP_MODE_READ 1 +#define IMX227_OTP_START_ADDR 0x0A04 +#define IMX227_OTP_ENABLE_REG 0x0A00 +#define IMX227_OTP_READY_REG 0x0A01 +#define IMX227_OTP_PAGE_REG 0x0A02 +#define IMX227_OTP_READY_REG_DONE 1 +#define IMX227_OTP_MODE_READ 1 + +static int +imx_read_otp_data(struct i2c_client *client, u16 len, u16 reg, void *val) +{ + struct i2c_msg msg[2]; + u16 data[IMX_SHORT_MAX] = { 0 }; + int err; + + if (len > IMX_BYTE_MAX) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0 , sizeof(msg)); + memset(data, 0 , sizeof(data)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = (u8 *)data; + /* high byte goes first */ + data[0] = cpu_to_be16(reg); + + msg[1].addr = client->addr; + msg[1].len = len; + msg[1].flags = I2C_M_RD; + msg[1].buf = (u8 *)data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + goto error; + } + + memcpy(val, data, len); + return 0; + +error: + dev_err(&client->dev, "read from offset 0x%x error %d", reg, err); + return err; +} + +static int imx_read_otp_reg_array(struct i2c_client *client, u16 size, u16 addr, + u8 *buf) +{ + u16 index; + int ret; + + for (index = 0; index + IMX_OTP_READ_ONETIME <= size; + index += IMX_OTP_READ_ONETIME) { + ret = imx_read_otp_data(client, IMX_OTP_READ_ONETIME, + addr + index, &buf[index]); + if (ret) + return ret; + } + return 0; +} + +void *imx_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 *buf; + int ret; + int i; + + buf = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < IMX_OTP_PAGE_MAX; i++) { + + /*set page NO.*/ + ret = imx_write_reg(client, IMX_8BIT, + IMX_OTP_PAGE_REG, i & 0xff); + if (ret) + goto fail; + + /*set read mode*/ + ret = imx_write_reg(client, IMX_8BIT, + IMX_OTP_MODE_REG, IMX_OTP_MODE_READ); + if (ret) + goto fail; + + /* Reading the OTP data array */ + ret = imx_read_otp_reg_array(client, IMX_OTP_PAGE_SIZE, + IMX_OTP_START_ADDR, buf + i * IMX_OTP_PAGE_SIZE); + if (ret) + goto fail; + } + + return buf; +fail: + /* Driver has failed to find valid data */ + dev_err(&client->dev, "sensor found no valid OTP data\n"); + return ERR_PTR(ret); +} + +void *imx227_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 *buf; + int ret; + int i; + + buf = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < IMX_OTP_PAGE_MAX; i++) { + + /*set page NO.*/ + ret = imx_write_reg(client, IMX_8BIT, + IMX227_OTP_PAGE_REG, i & 0xff); + if (ret) + goto fail; + + /*set read mode*/ + ret = imx_write_reg(client, IMX_8BIT, + IMX227_OTP_ENABLE_REG, IMX227_OTP_MODE_READ); + if (ret) + goto fail; + + /* Reading the OTP data array */ + ret = imx_read_otp_reg_array(client, IMX_OTP_PAGE_SIZE, + IMX227_OTP_START_ADDR, buf + i * IMX_OTP_PAGE_SIZE); + if (ret) + goto fail; + } + + return buf; +fail: + /* Driver has failed to find valid data */ + dev_err(&client->dev, "sensor found no valid OTP data\n"); + return ERR_PTR(ret); +} + diff --git a/drivers/staging/media/atomisp/i2c/imx/vcm.c b/drivers/staging/media/atomisp/i2c/imx/vcm.c new file mode 100644 index 0000000..2d2df04 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/vcm.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <linux/errno.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <media/v4l2-device.h> +#include "../../include/linux/atomisp_platform.h" + +int vcm_power_up(struct v4l2_subdev *sd) +{ + const struct camera_af_platform_data *vcm_platform_data; + + vcm_platform_data = camera_get_af_platform_data(); + if (NULL == vcm_platform_data) + return -ENODEV; + /* Enable power */ + return vcm_platform_data->power_ctrl(sd, 1); +} + +int vcm_power_down(struct v4l2_subdev *sd) +{ + const struct camera_af_platform_data *vcm_platform_data; + + vcm_platform_data = camera_get_af_platform_data(); + if (NULL == vcm_platform_data) + return -ENODEV; + return vcm_platform_data->power_ctrl(sd, 0); +} + diff --git a/drivers/staging/media/atomisp/i2c/libmsrlisthelper.c b/drivers/staging/media/atomisp/i2c/libmsrlisthelper.c new file mode 100644 index 0000000..decb65c --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/libmsrlisthelper.c @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <linux/i2c.h> +#include <linux/firmware.h> +#include <linux/device.h> +#include <linux/export.h> +#include "../include/linux/libmsrlisthelper.h" +#include <linux/module.h> +#include <linux/slab.h> + +/* Tagged binary data container structure definitions. */ +struct tbd_header { + uint32_t tag; /*!< Tag identifier, also checks endianness */ + uint32_t size; /*!< Container size including this header */ + uint32_t version; /*!< Version, format 0xYYMMDDVV */ + uint32_t revision; /*!< Revision, format 0xYYMMDDVV */ + uint32_t config_bits; /*!< Configuration flag bits set */ + uint32_t checksum; /*!< Global checksum, header included */ +} __packed; + +struct tbd_record_header { + uint32_t size; /*!< Size of record including header */ + uint8_t format_id; /*!< tbd_format_t enumeration values used */ + uint8_t packing_key; /*!< Packing method; 0 = no packing */ + uint16_t class_id; /*!< tbd_class_t enumeration values used */ +} __packed; + +struct tbd_data_record_header { + uint16_t next_offset; + uint16_t flags; + uint16_t data_offset; + uint16_t data_size; +} __packed; + +#define TBD_CLASS_DRV_ID 2 + +static int set_msr_configuration(struct i2c_client *client, uint8_t *bufptr, + unsigned int size) +{ + /* The configuration data contains any number of sequences where + * the first byte (that is, uint8_t) that marks the number of bytes + * in the sequence to follow, is indeed followed by the indicated + * number of bytes of actual data to be written to sensor. + * By convention, the first two bytes of actual data should be + * understood as an address in the sensor address space (hibyte + * followed by lobyte) where the remaining data in the sequence + * will be written. */ + + uint8_t *ptr = bufptr; + while (ptr < bufptr + size) { + struct i2c_msg msg = { + .addr = client->addr, + .flags = 0, + }; + int ret; + + /* How many bytes */ + msg.len = *ptr++; + /* Where the bytes are located */ + msg.buf = ptr; + ptr += msg.len; + + if (ptr > bufptr + size) + /* Accessing data beyond bounds is not tolerated */ + return -EINVAL; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret < 0) { + dev_err(&client->dev, "i2c write error: %d", ret); + return ret; + } + } + return 0; +} + +static int parse_and_apply(struct i2c_client *client, uint8_t *buffer, + unsigned int size) +{ + uint8_t *endptr8 = buffer + size; + struct tbd_data_record_header *header = + (struct tbd_data_record_header *)buffer; + + /* There may be any number of datasets present */ + unsigned int dataset = 0; + + do { + /* In below, four variables are read from buffer */ + if ((uint8_t *)header + sizeof(*header) > endptr8) + return -EINVAL; + + /* All data should be located within given buffer */ + if ((uint8_t *)header + header->data_offset + + header->data_size > endptr8) + return -EINVAL; + + /* We have a new valid dataset */ + dataset++; + /* See whether there is MSR data */ + /* If yes, update the reg info */ + if (header->data_size && (header->flags & 1)) { + int ret; + + dev_info(&client->dev, + "New MSR data for sensor driver (dataset %02d) size:%d\n", + dataset, header->data_size); + ret = set_msr_configuration(client, + buffer + header->data_offset, + header->data_size); + if (ret) + return ret; + } + header = (struct tbd_data_record_header *)(buffer + + header->next_offset); + } while (header->next_offset); + + return 0; +} + +int apply_msr_data(struct i2c_client *client, const struct firmware *fw) +{ + struct tbd_header *header; + struct tbd_record_header *record; + + if (!fw) { + dev_warn(&client->dev, "Drv data is not loaded.\n"); + return -EINVAL; + } + + if (sizeof(*header) > fw->size) + return -EINVAL; + + header = (struct tbd_header *)fw->data; + /* Check that we have drvb block. */ + if (memcmp(&header->tag, "DRVB", 4)) + return -EINVAL; + + /* Check the size */ + if (header->size != fw->size) + return -EINVAL; + + if (sizeof(*header) + sizeof(*record) > fw->size) + return -EINVAL; + + record = (struct tbd_record_header *)(header + 1); + /* Check that class id mathes tbd's drv id. */ + if (record->class_id != TBD_CLASS_DRV_ID) + return -EINVAL; + + /* Size 0 shall not be treated as an error */ + if (!record->size) + return 0; + + return parse_and_apply(client, (uint8_t *)(record + 1), record->size); +} +EXPORT_SYMBOL_GPL(apply_msr_data); + +int load_msr_list(struct i2c_client *client, char *name, + const struct firmware **fw) +{ + int ret = request_firmware(fw, name, &client->dev); + if (ret) { + dev_err(&client->dev, + "Error %d while requesting firmware %s\n", + ret, name); + return ret; + } + dev_info(&client->dev, "Received %lu bytes drv data\n", + (unsigned long)(*fw)->size); + + return 0; +} +EXPORT_SYMBOL_GPL(load_msr_list); + +void release_msr_list(struct i2c_client *client, const struct firmware *fw) +{ + release_firmware(fw); +} +EXPORT_SYMBOL_GPL(release_msr_list); + +static int init_msrlisthelper(void) +{ + return 0; +} + +static void exit_msrlisthelper(void) +{ +} + +module_init(init_msrlisthelper); +module_exit(exit_msrlisthelper); + +MODULE_AUTHOR("Jukka Kaartinen <jukka.o.kaartinen@intel.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/lm3554.c b/drivers/staging/media/atomisp/i2c/lm3554.c new file mode 100644 index 0000000..dd9c9c3 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/lm3554.c @@ -0,0 +1,1009 @@ +/* + * LED flash driver for LM3554 + * + * Copyright (c) 2010-2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <linux/module.h> +#include <linux/i2c.h> +#include <linux/mutex.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/slab.h> + +#include "../include/media/lm3554.h" +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include <linux/acpi.h> +#include <linux/gpio/consumer.h> +#include "../include/linux/atomisp_gmin_platform.h" +#include "../include/linux/atomisp.h" + +/* Registers */ + +#define LM3554_TORCH_BRIGHTNESS_REG 0xA0 +#define LM3554_TORCH_MODE_SHIFT 0 +#define LM3554_TORCH_CURRENT_SHIFT 3 +#define LM3554_INDICATOR_CURRENT_SHIFT 6 + +#define LM3554_FLASH_BRIGHTNESS_REG 0xB0 +#define LM3554_FLASH_MODE_SHIFT 0 +#define LM3554_FLASH_CURRENT_SHIFT 3 +#define LM3554_STROBE_SENSITIVITY_SHIFT 7 + +#define LM3554_FLASH_DURATION_REG 0xC0 +#define LM3554_FLASH_TIMEOUT_SHIFT 0 +#define LM3554_CURRENT_LIMIT_SHIFT 5 + +#define LM3554_FLAGS_REG 0xD0 +#define LM3554_FLAG_TIMEOUT (1 << 0) +#define LM3554_FLAG_THERMAL_SHUTDOWN (1 << 1) +#define LM3554_FLAG_LED_FAULT (1 << 2) +#define LM3554_FLAG_TX1_INTERRUPT (1 << 3) +#define LM3554_FLAG_TX2_INTERRUPT (1 << 4) +#define LM3554_FLAG_LED_THERMAL_FAULT (1 << 5) +#define LM3554_FLAG_UNUSED (1 << 6) +#define LM3554_FLAG_INPUT_VOLTAGE_LOW (1 << 7) + +#define LM3554_CONFIG_REG_1 0xE0 +#define LM3554_ENVM_TX2_SHIFT 5 +#define LM3554_TX2_POLARITY_SHIFT 6 + +struct lm3554 { + struct v4l2_subdev sd; + + struct mutex power_lock; + struct v4l2_ctrl_handler ctrl_handler; + int power_count; + + unsigned int mode; + int timeout; + u8 torch_current; + u8 indicator_current; + u8 flash_current; + + struct timer_list flash_off_delay; + struct lm3554_platform_data *pdata; +}; + +#define to_lm3554(p_sd) container_of(p_sd, struct lm3554, sd) + +/* Return negative errno else zero on success */ +static int lm3554_write(struct lm3554 *flash, u8 addr, u8 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); + int ret; + + ret = i2c_smbus_write_byte_data(client, addr, val); + + dev_dbg(&client->dev, "Write Addr:%02X Val:%02X %s\n", addr, val, + ret < 0 ? "fail" : "ok"); + + return ret; +} + +/* Return negative errno else a data byte received from the device. */ +static int lm3554_read(struct lm3554 *flash, u8 addr) +{ + struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); + int ret; + + ret = i2c_smbus_read_byte_data(client, addr); + + dev_dbg(&client->dev, "Read Addr:%02X Val:%02X %s\n", addr, ret, + ret < 0 ? "fail" : "ok"); + + return ret; +} + +/* ----------------------------------------------------------------------------- + * Hardware configuration + */ + +static int lm3554_set_mode(struct lm3554 *flash, unsigned int mode) +{ + u8 val; + int ret; + + val = (mode << LM3554_FLASH_MODE_SHIFT) | + (flash->flash_current << LM3554_FLASH_CURRENT_SHIFT); + + ret = lm3554_write(flash, LM3554_FLASH_BRIGHTNESS_REG, val); + if (ret == 0) + flash->mode = mode; + return ret; +} + +static int lm3554_set_torch(struct lm3554 *flash) +{ + u8 val; + + val = (flash->mode << LM3554_TORCH_MODE_SHIFT) | + (flash->torch_current << LM3554_TORCH_CURRENT_SHIFT) | + (flash->indicator_current << LM3554_INDICATOR_CURRENT_SHIFT); + + return lm3554_write(flash, LM3554_TORCH_BRIGHTNESS_REG, val); +} + +static int lm3554_set_flash(struct lm3554 *flash) +{ + u8 val; + + val = (flash->mode << LM3554_FLASH_MODE_SHIFT) | + (flash->flash_current << LM3554_FLASH_CURRENT_SHIFT); + + return lm3554_write(flash, LM3554_FLASH_BRIGHTNESS_REG, val); +} + +static int lm3554_set_duration(struct lm3554 *flash) +{ + u8 val; + + val = (flash->timeout << LM3554_FLASH_TIMEOUT_SHIFT) | + (flash->pdata->current_limit << LM3554_CURRENT_LIMIT_SHIFT); + + return lm3554_write(flash, LM3554_FLASH_DURATION_REG, val); +} + +static int lm3554_set_config1(struct lm3554 *flash) +{ + u8 val; + + val = (flash->pdata->envm_tx2 << LM3554_ENVM_TX2_SHIFT) | + (flash->pdata->tx2_polarity << LM3554_TX2_POLARITY_SHIFT); + return lm3554_write(flash, LM3554_CONFIG_REG_1, val); +} + +/* ----------------------------------------------------------------------------- + * Hardware trigger + */ +static void lm3554_flash_off_delay(long unsigned int arg) +{ + struct v4l2_subdev *sd = i2c_get_clientdata((struct i2c_client *)arg); + struct lm3554 *flash = to_lm3554(sd); + struct lm3554_platform_data *pdata = flash->pdata; + + gpio_set_value(pdata->gpio_strobe, 0); +} + +static int lm3554_hw_strobe(struct i2c_client *client, bool strobe) +{ + int ret, timer_pending; + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(sd); + struct lm3554_platform_data *pdata = flash->pdata; + + /* + * An abnormal high flash current is observed when strobe off the + * flash. Workaround here is firstly set flash current to lower level, + * wait a short moment, and then strobe off the flash. + */ + + timer_pending = del_timer_sync(&flash->flash_off_delay); + + /* Flash off */ + if (!strobe) { + /* set current to 70mA and wait a while */ + ret = lm3554_write(flash, LM3554_FLASH_BRIGHTNESS_REG, 0); + if (ret < 0) + goto err; + mod_timer(&flash->flash_off_delay, + jiffies + msecs_to_jiffies(LM3554_TIMER_DELAY)); + return 0; + } + + /* Flash on */ + + /* + * If timer is killed before run, flash is not strobe off, + * so must strobe off here + */ + if (timer_pending) + gpio_set_value(pdata->gpio_strobe, 0); + + /* Restore flash current settings */ + ret = lm3554_set_flash(flash); + if (ret < 0) + goto err; + + /* Strobe on Flash */ + gpio_set_value(pdata->gpio_strobe, 1); + + return 0; +err: + dev_err(&client->dev, "failed to %s flash strobe (%d)\n", + strobe ? "on" : "off", ret); + return ret; +} + +/* ----------------------------------------------------------------------------- + * V4L2 controls + */ + +static int lm3554_read_status(struct lm3554 *flash) +{ + int ret; + struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); + + /* NOTE: reading register clear fault status */ + ret = lm3554_read(flash, LM3554_FLAGS_REG); + if (ret < 0) + return ret; + + /* + * Accordingly to datasheet we read back '1' in bit 6. + * Clear it first. + */ + ret &= ~LM3554_FLAG_UNUSED; + + /* + * Do not take TX1/TX2 signal as an error + * because MSIC will not turn off flash, but turn to + * torch mode according to gsm modem signal by hardware. + */ + ret &= ~(LM3554_FLAG_TX1_INTERRUPT | LM3554_FLAG_TX2_INTERRUPT); + + if (ret > 0) + dev_dbg(&client->dev, "LM3554 flag status: %02x\n", ret); + + return ret; +} + +static int lm3554_s_flash_timeout(struct v4l2_subdev *sd, u32 val) +{ + struct lm3554 *flash = to_lm3554(sd); + + val = clamp(val, LM3554_MIN_TIMEOUT, LM3554_MAX_TIMEOUT); + val = val / LM3554_TIMEOUT_STEPSIZE - 1; + + flash->timeout = val; + + return lm3554_set_duration(flash); +} + +static int lm3554_g_flash_timeout(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + + *val = (u32)(flash->timeout + 1) * LM3554_TIMEOUT_STEPSIZE; + + return 0; +} + +static int lm3554_s_flash_intensity(struct v4l2_subdev *sd, u32 intensity) +{ + struct lm3554 *flash = to_lm3554(sd); + + intensity = LM3554_CLAMP_PERCENTAGE(intensity); + intensity = LM3554_PERCENT_TO_VALUE(intensity, LM3554_FLASH_STEP); + + flash->flash_current = intensity; + + return lm3554_set_flash(flash); +} + +static int lm3554_g_flash_intensity(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + + *val = LM3554_VALUE_TO_PERCENT((u32)flash->flash_current, + LM3554_FLASH_STEP); + + return 0; +} + +static int lm3554_s_torch_intensity(struct v4l2_subdev *sd, u32 intensity) +{ + struct lm3554 *flash = to_lm3554(sd); + + intensity = LM3554_CLAMP_PERCENTAGE(intensity); + intensity = LM3554_PERCENT_TO_VALUE(intensity, LM3554_TORCH_STEP); + + flash->torch_current = intensity; + + return lm3554_set_torch(flash); +} + +static int lm3554_g_torch_intensity(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + + *val = LM3554_VALUE_TO_PERCENT((u32)flash->torch_current, + LM3554_TORCH_STEP); + + return 0; +} + +static int lm3554_s_indicator_intensity(struct v4l2_subdev *sd, u32 intensity) +{ + struct lm3554 *flash = to_lm3554(sd); + + intensity = LM3554_CLAMP_PERCENTAGE(intensity); + intensity = LM3554_PERCENT_TO_VALUE(intensity, LM3554_INDICATOR_STEP); + + flash->indicator_current = intensity; + + return lm3554_set_torch(flash); +} + +static int lm3554_g_indicator_intensity(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + + *val = LM3554_VALUE_TO_PERCENT((u32)flash->indicator_current, + LM3554_INDICATOR_STEP); + + return 0; +} + +static int lm3554_s_flash_strobe(struct v4l2_subdev *sd, u32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + return lm3554_hw_strobe(client, val); +} + +static int lm3554_s_flash_mode(struct v4l2_subdev *sd, u32 new_mode) +{ + struct lm3554 *flash = to_lm3554(sd); + unsigned int mode; + + switch (new_mode) { + case ATOMISP_FLASH_MODE_OFF: + mode = LM3554_MODE_SHUTDOWN; + break; + case ATOMISP_FLASH_MODE_FLASH: + mode = LM3554_MODE_FLASH; + break; + case ATOMISP_FLASH_MODE_INDICATOR: + mode = LM3554_MODE_INDICATOR; + break; + case ATOMISP_FLASH_MODE_TORCH: + mode = LM3554_MODE_TORCH; + break; + default: + return -EINVAL; + } + + return lm3554_set_mode(flash, mode); +} + +static int lm3554_g_flash_mode(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + *val = flash->mode; + return 0; +} + +static int lm3554_g_flash_status(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + int value; + + value = lm3554_read_status(flash); + if (value < 0) + return value; + + if (value & LM3554_FLAG_TIMEOUT) + *val = ATOMISP_FLASH_STATUS_TIMEOUT; + else if (value > 0) + *val = ATOMISP_FLASH_STATUS_HW_ERROR; + else + *val = ATOMISP_FLASH_STATUS_OK; + + return 0; +} + +#ifndef CSS15 +static int lm3554_g_flash_status_register(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + int ret; + + ret = lm3554_read(flash, LM3554_FLAGS_REG); + + if (ret < 0) + return ret; + + *val = ret; + return 0; +} +#endif + +static int lm3554_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct lm3554 *dev = + container_of(ctrl->handler, struct lm3554, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_FLASH_TIMEOUT: + ret = lm3554_s_flash_timeout(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_INTENSITY: + ret = lm3554_s_flash_intensity(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_TORCH_INTENSITY: + ret = lm3554_s_torch_intensity(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_INDICATOR_INTENSITY: + ret = lm3554_s_indicator_intensity(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_STROBE: + ret = lm3554_s_flash_strobe(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_MODE: + ret = lm3554_s_flash_mode(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int lm3554_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct lm3554 *dev = + container_of(ctrl->handler, struct lm3554, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_FLASH_TIMEOUT: + ret = lm3554_g_flash_timeout(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_INTENSITY: + ret = lm3554_g_flash_intensity(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_TORCH_INTENSITY: + ret = lm3554_g_torch_intensity(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_INDICATOR_INTENSITY: + ret = lm3554_g_indicator_intensity(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_MODE: + ret = lm3554_g_flash_mode(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_STATUS: + ret = lm3554_g_flash_status(&dev->sd, &ctrl->val); + break; +#ifndef CSS15 + case V4L2_CID_FLASH_STATUS_REGISTER: + ret = lm3554_g_flash_status_register(&dev->sd, &ctrl->val); + break; +#endif + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = lm3554_s_ctrl, + .g_volatile_ctrl = lm3554_g_volatile_ctrl +}; + +struct v4l2_ctrl_config lm3554_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_TIMEOUT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Flash Timeout", + .min = 0x0, + .max = LM3554_MAX_TIMEOUT, + .step = 0x01, + .def = LM3554_DEFAULT_TIMEOUT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_INTENSITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Flash Intensity", + .min = LM3554_MIN_PERCENT, + .max = LM3554_MAX_PERCENT, + .step = 0x01, + .def = LM3554_FLASH_DEFAULT_BRIGHTNESS, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_TORCH_INTENSITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Torch Intensity", + .min = LM3554_MIN_PERCENT, + .max = LM3554_MAX_PERCENT, + .step = 0x01, + .def = LM3554_TORCH_DEFAULT_BRIGHTNESS, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_INDICATOR_INTENSITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Indicator Intensity", + .min = LM3554_MIN_PERCENT, + .max = LM3554_MAX_PERCENT, + .step = 0x01, + .def = LM3554_INDICATOR_DEFAULT_BRIGHTNESS, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_STROBE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flash Strobe", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_MODE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Flash Mode", + .min = 0, + .max = 100, + .step = 1, + .def = ATOMISP_FLASH_MODE_OFF, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_STATUS, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flash Status", + .min = 0, + .max = 100, + .step = 1, + .def = ATOMISP_FLASH_STATUS_OK, + .flags = 0, + }, +#ifndef CSS15 + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_STATUS_REGISTER, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flash Status Register", + .min = 0, + .max = 100, + .step = 1, + .def = 0, + .flags = 0, + }, +#endif +}; + +/* ----------------------------------------------------------------------------- + * V4L2 subdev core operations + */ + +/* Put device into known state. */ +static int lm3554_setup(struct lm3554 *flash) +{ + struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); + int ret; + + /* clear the flags register */ + ret = lm3554_read(flash, LM3554_FLAGS_REG); + if (ret < 0) + return ret; + + dev_dbg(&client->dev, "Fault info: %02x\n", ret); + + ret = lm3554_set_config1(flash); + if (ret < 0) + return ret; + + ret = lm3554_set_duration(flash); + if (ret < 0) + return ret; + + ret = lm3554_set_torch(flash); + if (ret < 0) + return ret; + + ret = lm3554_set_flash(flash); + if (ret < 0) + return ret; + + /* read status */ + ret = lm3554_read_status(flash); + if (ret < 0) + return ret; + + return ret ? -EIO : 0; +} + +static int __lm3554_s_power(struct lm3554 *flash, int power) +{ + struct lm3554_platform_data *pdata = flash->pdata; + int ret; + + /*initialize flash driver*/ + gpio_set_value(pdata->gpio_reset, power); + usleep_range(100, 100 + 1); + + if (power) { + /* Setup default values. This makes sure that the chip + * is in a known state. + */ + ret = lm3554_setup(flash); + if (ret < 0) { + __lm3554_s_power(flash, 0); + return ret; + } + } + + return 0; +} + +static int lm3554_s_power(struct v4l2_subdev *sd, int power) +{ + struct lm3554 *flash = to_lm3554(sd); + int ret = 0; + + mutex_lock(&flash->power_lock); + + if (flash->power_count == !power) { + ret = __lm3554_s_power(flash, !!power); + if (ret < 0) + goto done; + } + + flash->power_count += power ? 1 : -1; + WARN_ON(flash->power_count < 0); + +done: + mutex_unlock(&flash->power_lock); + return ret; +} + +static const struct v4l2_subdev_core_ops lm3554_core_ops = { + .s_power = lm3554_s_power, +}; + +static const struct v4l2_subdev_ops lm3554_ops = { + .core = &lm3554_core_ops, +}; + +static int lm3554_detect(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct i2c_adapter *adapter = client->adapter; + struct lm3554 *flash = to_lm3554(sd); + int ret; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { + dev_err(&client->dev, "lm3554_detect i2c error\n"); + return -ENODEV; + } + + /* Power up the flash driver and reset it */ + ret = lm3554_s_power(&flash->sd, 1); + if (ret < 0) { + dev_err(&client->dev, "Failed to power on lm3554 LED flash\n"); + } else { + dev_dbg(&client->dev, "Successfully detected lm3554 LED flash\n"); + lm3554_s_power(&flash->sd, 0); + } + + return ret; +} + +static int lm3554_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + return lm3554_s_power(sd, 1); +} + +static int lm3554_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + return lm3554_s_power(sd, 0); +} + +static const struct v4l2_subdev_internal_ops lm3554_internal_ops = { + .registered = lm3554_detect, + .open = lm3554_open, + .close = lm3554_close, +}; + +/* ----------------------------------------------------------------------------- + * I2C driver + */ +#ifdef CONFIG_PM + +static int lm3554_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(subdev); + int rval; + + if (flash->power_count == 0) + return 0; + + rval = __lm3554_s_power(flash, 0); + + dev_dbg(&client->dev, "Suspend %s\n", rval < 0 ? "failed" : "ok"); + + return rval; +} + +static int lm3554_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(subdev); + int rval; + + if (flash->power_count == 0) + return 0; + + rval = __lm3554_s_power(flash, 1); + + dev_dbg(&client->dev, "Resume %s\n", rval < 0 ? "fail" : "ok"); + + return rval; +} + +#else + +#define lm3554_suspend NULL +#define lm3554_resume NULL + +#endif /* CONFIG_PM */ + +static int lm3554_gpio_init(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(sd); + struct lm3554_platform_data *pdata = flash->pdata; + int ret; + + if (!gpio_is_valid(pdata->gpio_reset)) + return -EINVAL; + + ret = gpio_direction_output(pdata->gpio_reset, 0); + if (ret < 0) + goto err_gpio_reset; + dev_info(&client->dev, "flash led reset successfully\n"); + + if (!gpio_is_valid(pdata->gpio_strobe)) { + ret = -EINVAL; + goto err_gpio_dir_reset; + } + + ret = gpio_direction_output(pdata->gpio_strobe, 0); + if (ret < 0) + goto err_gpio_strobe; + + return 0; + +err_gpio_strobe: + gpio_free(pdata->gpio_strobe); +err_gpio_dir_reset: + gpio_direction_output(pdata->gpio_reset, 0); +err_gpio_reset: + gpio_free(pdata->gpio_reset); + + return ret; +} + +static int lm3554_gpio_uninit(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(sd); + struct lm3554_platform_data *pdata = flash->pdata; + int ret; + + ret = gpio_direction_output(pdata->gpio_strobe, 0); + if (ret < 0) + return ret; + + ret = gpio_direction_output(pdata->gpio_reset, 0); + if (ret < 0) + return ret; + + gpio_free(pdata->gpio_strobe); + gpio_free(pdata->gpio_reset); + return 0; +} + +void *lm3554_platform_data_func(struct i2c_client *client) +{ + static struct lm3554_platform_data platform_data; + + if (ACPI_COMPANION(&client->dev)) { + platform_data.gpio_reset = + desc_to_gpio(gpiod_get_index(&(client->dev), + NULL, 2, GPIOD_OUT_LOW)); + platform_data.gpio_strobe = + desc_to_gpio(gpiod_get_index(&(client->dev), + NULL, 0, GPIOD_OUT_LOW)); + platform_data.gpio_torch = + desc_to_gpio(gpiod_get_index(&(client->dev), + NULL, 1, GPIOD_OUT_LOW)); + } else { + platform_data.gpio_reset = -1; + platform_data.gpio_strobe = -1; + platform_data.gpio_torch = -1; + } + + dev_info(&client->dev, "camera pdata: lm3554: reset: %d strobe %d torch %d\n", + platform_data.gpio_reset, platform_data.gpio_strobe, + platform_data.gpio_torch); + + /* Set to TX2 mode, then ENVM/TX2 pin is a power amplifier sync input: + * ENVM/TX pin asserted, flash forced into torch; + * ENVM/TX pin desserted, flash set back; + */ + platform_data.envm_tx2 = 1; + platform_data.tx2_polarity = 0; + + /* set peak current limit to be 1000mA */ + platform_data.current_limit = 0; + + return &platform_data; +} + +static int lm3554_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int err = 0; + struct lm3554 *flash; + unsigned int i; + int ret; + + flash = kzalloc(sizeof(*flash), GFP_KERNEL); + if (!flash) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + flash->pdata = client->dev.platform_data; + + if (!flash->pdata || ACPI_COMPANION(&client->dev)) + flash->pdata = lm3554_platform_data_func(client); + + v4l2_i2c_subdev_init(&flash->sd, client, &lm3554_ops); + flash->sd.internal_ops = &lm3554_internal_ops; + flash->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + flash->mode = ATOMISP_FLASH_MODE_OFF; + flash->timeout = LM3554_MAX_TIMEOUT / LM3554_TIMEOUT_STEPSIZE - 1; + ret = + v4l2_ctrl_handler_init(&flash->ctrl_handler, + ARRAY_SIZE(lm3554_controls)); + if (ret) { + dev_err(&client->dev, "error initialize a ctrl_handler.\n"); + goto fail2; + } + + for (i = 0; i < ARRAY_SIZE(lm3554_controls); i++) + v4l2_ctrl_new_custom(&flash->ctrl_handler, &lm3554_controls[i], + NULL); + + if (flash->ctrl_handler.error) { + + dev_err(&client->dev, "ctrl_handler error.\n"); + goto fail2; + } + + flash->sd.ctrl_handler = &flash->ctrl_handler; + err = media_entity_pads_init(&flash->sd.entity, 0, NULL); + if (err) { + dev_err(&client->dev, "error initialize a media entity.\n"); + goto fail1; + } + + flash->sd.entity.function = MEDIA_ENT_F_FLASH; + + mutex_init(&flash->power_lock); + + setup_timer(&flash->flash_off_delay, lm3554_flash_off_delay, + (unsigned long)client); + + err = lm3554_gpio_init(client); + if (err) { + dev_err(&client->dev, "gpio request/direction_output fail"); + goto fail2; + } + if (ACPI_HANDLE(&client->dev)) + err = atomisp_register_i2c_module(&flash->sd, NULL, LED_FLASH); + return 0; +fail2: + media_entity_cleanup(&flash->sd.entity); + v4l2_ctrl_handler_free(&flash->ctrl_handler); +fail1: + v4l2_device_unregister_subdev(&flash->sd); + kfree(flash); + + return err; +} + +static int lm3554_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(sd); + int ret; + + media_entity_cleanup(&flash->sd.entity); + v4l2_ctrl_handler_free(&flash->ctrl_handler); + v4l2_device_unregister_subdev(sd); + + atomisp_gmin_remove_subdev(sd); + + del_timer_sync(&flash->flash_off_delay); + + ret = lm3554_gpio_uninit(client); + if (ret < 0) + goto fail; + + kfree(flash); + + return 0; +fail: + dev_err(&client->dev, "gpio request/direction_output fail"); + return ret; +} + +static const struct i2c_device_id lm3554_id[] = { + {LM3554_NAME, 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, lm3554_id); + +static const struct dev_pm_ops lm3554_pm_ops = { + .suspend = lm3554_suspend, + .resume = lm3554_resume, +}; + +static struct acpi_device_id lm3554_acpi_match[] = { + { "INTCF1C" }, + {}, +}; + +MODULE_DEVICE_TABLE(acpi, lm3554_acpi_match); + +static struct i2c_driver lm3554_driver = { + .driver = { + .name = LM3554_NAME, + .pm = &lm3554_pm_ops, + .acpi_match_table = ACPI_PTR(lm3554_acpi_match), + }, + .probe = lm3554_probe, + .remove = lm3554_remove, + .id_table = lm3554_id, +}; + +static __init int init_lm3554(void) +{ + return i2c_add_driver(&lm3554_driver); +} + +static __exit void exit_lm3554(void) +{ + i2c_del_driver(&lm3554_driver); +} + +module_init(init_lm3554); +module_exit(exit_lm3554); +MODULE_AUTHOR("Jing Tao <jing.tao@intel.com>"); +MODULE_DESCRIPTION("LED flash driver for LM3554"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/mt9m114.c b/drivers/staging/media/atomisp/i2c/mt9m114.c new file mode 100644 index 0000000..ced175c --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/mt9m114.c @@ -0,0 +1,1963 @@ +/* + * Support for mt9m114 Camera Sensor. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/string.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kmod.h> +#include <linux/device.h> +#include <linux/fs.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/acpi.h> +#include "../include/linux/atomisp_gmin_platform.h" +#include <media/v4l2-device.h> + +#include "mt9m114.h" + +#define to_mt9m114_sensor(sd) container_of(sd, struct mt9m114_device, sd) + +/* + * TODO: use debug parameter to actually define when debug messages should + * be printed. + */ +static int debug; +static int aaalock; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Debug level (0-1)"); + +static int mt9m114_t_vflip(struct v4l2_subdev *sd, int value); +static int mt9m114_t_hflip(struct v4l2_subdev *sd, int value); +static int mt9m114_wait_state(struct i2c_client *client, int timeout); + +static int +mt9m114_read_reg(struct i2c_client *client, u16 data_length, u32 reg, u32 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[4]; + + if (!client->adapter) { + v4l2_err(client, "%s error, no client->adapter\n", __func__); + return -ENODEV; + } + + if (data_length != MISENSOR_8BIT && data_length != MISENSOR_16BIT + && data_length != MISENSOR_32BIT) { + v4l2_err(client, "%s error, invalid data length\n", __func__); + return -EINVAL; + } + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = MSG_LEN_OFFSET; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u16) (reg >> 8); + data[1] = (u16) (reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + + if (err >= 0) { + *val = 0; + /* high byte comes first */ + if (data_length == MISENSOR_8BIT) + *val = data[0]; + else if (data_length == MISENSOR_16BIT) + *val = data[1] + (data[0] << 8); + else + *val = data[3] + (data[2] << 8) + + (data[1] << 16) + (data[0] << 24); + + return 0; + } + + dev_err(&client->dev, "read from offset 0x%x error %d", reg, err); + return err; +} + +static int +mt9m114_write_reg(struct i2c_client *client, u16 data_length, u16 reg, u32 val) +{ + int num_msg; + struct i2c_msg msg; + unsigned char data[6] = {0}; + u16 *wreg; + int retry = 0; + + if (!client->adapter) { + v4l2_err(client, "%s error, no client->adapter\n", __func__); + return -ENODEV; + } + + if (data_length != MISENSOR_8BIT && data_length != MISENSOR_16BIT + && data_length != MISENSOR_32BIT) { + v4l2_err(client, "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + memset(&msg, 0, sizeof(msg)); + +again: + msg.addr = client->addr; + msg.flags = 0; + msg.len = 2 + data_length; + msg.buf = data; + + /* high byte goes out first */ + wreg = (u16 *)data; + *wreg = cpu_to_be16(reg); + + if (data_length == MISENSOR_8BIT) { + data[2] = (u8)(val); + } else if (data_length == MISENSOR_16BIT) { + u16 *wdata = (u16 *)&data[2]; + *wdata = be16_to_cpu((u16)val); + } else { + /* MISENSOR_32BIT */ + u32 *wdata = (u32 *)&data[2]; + *wdata = be32_to_cpu(val); + } + + num_msg = i2c_transfer(client->adapter, &msg, 1); + + /* + * HACK: Need some delay here for Rev 2 sensors otherwise some + * registers do not seem to load correctly. + */ + mdelay(1); + + if (num_msg >= 0) + return 0; + + dev_err(&client->dev, "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, num_msg); + if (retry <= I2C_RETRY_COUNT) { + dev_dbg(&client->dev, "retrying... %d", retry); + retry++; + msleep(20); + goto again; + } + + return num_msg; +} + +/** + * misensor_rmw_reg - Read/Modify/Write a value to a register in the sensor + * device + * @client: i2c driver client structure + * @data_length: 8/16/32-bits length + * @reg: register address + * @mask: masked out bits + * @set: bits set + * + * Read/modify/write a value to a register in the sensor device. + * Returns zero if successful, or non-zero otherwise. + */ +static int +misensor_rmw_reg(struct i2c_client *client, u16 data_length, u16 reg, + u32 mask, u32 set) +{ + int err; + u32 val; + + /* Exit when no mask */ + if (mask == 0) + return 0; + + /* @mask must not exceed data length */ + switch (data_length) { + case MISENSOR_8BIT: + if (mask & ~0xff) + return -EINVAL; + break; + case MISENSOR_16BIT: + if (mask & ~0xffff) + return -EINVAL; + break; + case MISENSOR_32BIT: + break; + default: + /* Wrong @data_length */ + return -EINVAL; + } + + err = mt9m114_read_reg(client, data_length, reg, &val); + if (err) { + v4l2_err(client, "misensor_rmw_reg error exit, read failed\n"); + return -EINVAL; + } + + val &= ~mask; + + /* + * Perform the OR function if the @set exists. + * Shift @set value to target bit location. @set should set only + * bits included in @mask. + * + * REVISIT: This function expects @set to be non-shifted. Its shift + * value is then defined to be equal to mask's LSB position. + * How about to inform values in their right offset position and avoid + * this unneeded shift operation? + */ + set <<= ffs(mask) - 1; + val |= set & mask; + + err = mt9m114_write_reg(client, data_length, reg, val); + if (err) { + v4l2_err(client, "misensor_rmw_reg error exit, write failed\n"); + return -EINVAL; + } + + return 0; +} + + +static int __mt9m114_flush_reg_array(struct i2c_client *client, + struct mt9m114_write_ctrl *ctrl) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + int retry = 0; + + if (ctrl->index == 0) + return 0; + +again: + msg.addr = client->addr; + msg.flags = 0; + msg.len = 2 + ctrl->index; + ctrl->buffer.addr = cpu_to_be16(ctrl->buffer.addr); + msg.buf = (u8 *)&ctrl->buffer; + + ret = i2c_transfer(client->adapter, &msg, num_msg); + if (ret != num_msg) { + if (++retry <= I2C_RETRY_COUNT) { + dev_dbg(&client->dev, "retrying... %d\n", retry); + msleep(20); + goto again; + } + dev_err(&client->dev, "%s: i2c transfer error\n", __func__); + return -EIO; + } + + ctrl->index = 0; + + /* + * REVISIT: Previously we had a delay after writing data to sensor. + * But it was removed as our tests have shown it is not necessary + * anymore. + */ + + return 0; +} + +static int __mt9m114_buf_reg_array(struct i2c_client *client, + struct mt9m114_write_ctrl *ctrl, + const struct misensor_reg *next) +{ + u16 *data16; + u32 *data32; + int err; + + /* Insufficient buffer? Let's flush and get more free space. */ + if (ctrl->index + next->length >= MT9M114_MAX_WRITE_BUF_SIZE) { + err = __mt9m114_flush_reg_array(client, ctrl); + if (err) + return err; + } + + switch (next->length) { + case MISENSOR_8BIT: + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case MISENSOR_16BIT: + data16 = (u16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + case MISENSOR_32BIT: + data32 = (u32 *)&ctrl->buffer.data[ctrl->index]; + *data32 = cpu_to_be32(next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += next->length; + + return 0; +} + +static int +__mt9m114_write_reg_is_consecutive(struct i2c_client *client, + struct mt9m114_write_ctrl *ctrl, + const struct misensor_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +/* + * mt9m114_write_reg_array - Initializes a list of mt9m114 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * @poll: completion polling requirement + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __mt9m114_flush_reg_array, __mt9m114_buf_reg_array() and + * __mt9m114_write_reg_is_consecutive() are internal functions to + * mt9m114_write_reg_array() and should be not used anywhere else. + * + */ +static int mt9m114_write_reg_array(struct i2c_client *client, + const struct misensor_reg *reglist, + int poll) +{ + const struct misensor_reg *next = reglist; + struct mt9m114_write_ctrl ctrl; + int err; + + if (poll == PRE_POLLING) { + err = mt9m114_wait_state(client, MT9M114_WAIT_STAT_TIMEOUT); + if (err) + return err; + } + + ctrl.index = 0; + for (; next->length != MISENSOR_TOK_TERM; next++) { + switch (next->length & MISENSOR_TOK_MASK) { + case MISENSOR_TOK_DELAY: + err = __mt9m114_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + case MISENSOR_TOK_RMW: + err = __mt9m114_flush_reg_array(client, &ctrl); + err |= misensor_rmw_reg(client, + next->length & + ~MISENSOR_TOK_RMW, + next->reg, next->val, + next->val2); + if (err) { + dev_err(&client->dev, "%s read err. aborted\n", + __func__); + return -EINVAL; + } + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__mt9m114_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __mt9m114_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __mt9m114_buf_reg_array(client, &ctrl, next); + if (err) { + v4l2_err(client, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + err = __mt9m114_flush_reg_array(client, &ctrl); + if (err) + return err; + + if (poll == POST_POLLING) + return mt9m114_wait_state(client, MT9M114_WAIT_STAT_TIMEOUT); + + return 0; +} + +static int mt9m114_wait_state(struct i2c_client *client, int timeout) +{ + int ret; + unsigned int val; + + while (timeout-- > 0) { + ret = mt9m114_read_reg(client, MISENSOR_16BIT, 0x0080, &val); + if (ret) + return ret; + if ((val & 0x2) == 0) + return 0; + msleep(20); + } + + return -EINVAL; + +} + +static int mt9m114_set_suspend(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + return mt9m114_write_reg_array(client, + mt9m114_standby_reg, POST_POLLING); +} + +static int mt9m114_init_common(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + return mt9m114_write_reg_array(client, mt9m114_common, PRE_POLLING); +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + if (flag) { + ret = dev->platform_data->v2p8_ctrl(sd, 1); + if (ret == 0) { + ret = dev->platform_data->v1p8_ctrl(sd, 1); + if (ret) + ret = dev->platform_data->v2p8_ctrl(sd, 0); + } + } else { + ret = dev->platform_data->v2p8_ctrl(sd, 0); + ret = dev->platform_data->v1p8_ctrl(sd, 0); + } + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + /* Note: current modules wire only one GPIO signal (RESET#), + * but the schematic wires up two to the connector. BIOS + * versions have been unfortunately inconsistent with which + * ACPI index RESET# is on, so hit both */ + + if (flag) { + ret = dev->platform_data->gpio0_ctrl(sd, 0); + ret = dev->platform_data->gpio1_ctrl(sd, 0); + msleep(60); + ret |= dev->platform_data->gpio0_ctrl(sd, 1); + ret |= dev->platform_data->gpio1_ctrl(sd, 1); + } else { + ret = dev->platform_data->gpio0_ctrl(sd, 0); + ret = dev->platform_data->gpio1_ctrl(sd, 0); + } + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (NULL == dev->platform_data) { + dev_err(&client->dev, "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) + dev_err(&client->dev, "gpio failed 1\n"); + /* + * according to DS, 44ms is needed between power up and first i2c + * commend + */ + msleep(50); + + return 0; + +fail_clk: + dev->platform_data->flisclk_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (NULL == dev->platform_data) { + dev_err(&client->dev, "no camera_sensor_platform_data"); + return -ENODEV; + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 1\n"); + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + /*according to DS, 20ms is needed after power down*/ + msleep(20); + + return ret; +} + +static int mt9m114_s_power(struct v4l2_subdev *sd, int power) +{ + if (power == 0) + return power_down(sd); + else { + if (power_up(sd)) + return -EINVAL; + + return mt9m114_init_common(sd); + } +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between resolution and w/h. + * res->width/height smaller than w/h wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 600 +static int distance(struct mt9m114_res_struct const *res, u32 w, u32 h) +{ + unsigned int w_ratio; + unsigned int h_ratio; + int match; + + if (w == 0) + return -1; + w_ratio = (res->width << 13) / w; + if (h == 0) + return -1; + h_ratio = (res->height << 13) / h; + if (h_ratio == 0) + return -1; + match = abs(((w_ratio << 13) / h_ratio) - 8192); + + if ((w_ratio < 8192) || (h_ratio < 8192) || + (match > LARGEST_ALLOWED_RATIO_MISMATCH)) + return -1; + + return w_ratio + h_ratio; +} + +/* Return the nearest higher resolution index */ +static int nearest_resolution_index(int w, int h) +{ + int i; + int idx = -1; + int dist; + int min_dist = INT_MAX; + const struct mt9m114_res_struct *tmp_res = NULL; + + for (i = 0; i < ARRAY_SIZE(mt9m114_res); i++) { + tmp_res = &mt9m114_res[i]; + dist = distance(tmp_res, w, h); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + } + } + + return idx; +} + +static int mt9m114_try_res(u32 *w, u32 *h) +{ + int idx = 0; + + if ((*w > MT9M114_RES_960P_SIZE_H) + || (*h > MT9M114_RES_960P_SIZE_V)) { + *w = MT9M114_RES_960P_SIZE_H; + *h = MT9M114_RES_960P_SIZE_V; + } else { + idx = nearest_resolution_index(*w, *h); + + /* + * nearest_resolution_index() doesn't return smaller + * resolutions. If it fails, it means the requested + * resolution is higher than wecan support. Fallback + * to highest possible resolution in this case. + */ + if (idx == -1) + idx = ARRAY_SIZE(mt9m114_res) - 1; + + *w = mt9m114_res[idx].width; + *h = mt9m114_res[idx].height; + } + + return 0; +} + +static struct mt9m114_res_struct *mt9m114_to_res(u32 w, u32 h) +{ + int index; + + for (index = 0; index < N_RES; index++) { + if ((mt9m114_res[index].width == w) && + (mt9m114_res[index].height == h)) + break; + } + + /* No mode found */ + if (index >= N_RES) + return NULL; + + return &mt9m114_res[index]; +} + +static int mt9m114_res2size(struct v4l2_subdev *sd, int *h_size, int *v_size) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + unsigned short hsize; + unsigned short vsize; + + switch (dev->res) { + case MT9M114_RES_736P: + hsize = MT9M114_RES_736P_SIZE_H; + vsize = MT9M114_RES_736P_SIZE_V; + break; + case MT9M114_RES_864P: + hsize = MT9M114_RES_864P_SIZE_H; + vsize = MT9M114_RES_864P_SIZE_V; + break; + case MT9M114_RES_960P: + hsize = MT9M114_RES_960P_SIZE_H; + vsize = MT9M114_RES_960P_SIZE_V; + break; + default: + v4l2_err(sd, "%s: Resolution 0x%08x unknown\n", __func__, + dev->res); + return -EINVAL; + } + + if (h_size != NULL) + *h_size = hsize; + if (v_size != NULL) + *v_size = vsize; + + return 0; +} + +static int mt9m114_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct mt9m114_res_struct *res) +{ + struct atomisp_sensor_mode_data *buf = &info->data; + u32 reg_val; + int ret; + + if (info == NULL) + return -EINVAL; + + ret = mt9m114_read_reg(client, MISENSOR_32BIT, + REG_PIXEL_CLK, ®_val); + if (ret) + return ret; + buf->vt_pix_clk_freq_mhz = reg_val; + + /* get integration time */ + buf->coarse_integration_time_min = MT9M114_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + MT9M114_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = MT9M114_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + MT9M114_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = MT9M114_FINE_INTG_TIME_MIN; + + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_H_START, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_V_START, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_H_END, ®_val); + if (ret) + return ret; + buf->crop_horizontal_end = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_V_END, ®_val); + if (ret) + return ret; + buf->crop_vertical_end = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_WIDTH, ®_val); + if (ret) + return ret; + buf->output_width = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_HEIGHT, ®_val); + if (ret) + return ret; + buf->output_height = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_TIMING_HTS, ®_val); + if (ret) + return ret; + buf->line_length_pck = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_TIMING_VTS, ®_val); + if (ret) + return ret; + buf->frame_length_lines = reg_val; + + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static int mt9m114_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + int width, height; + int ret; + if (format->pad) + return -EINVAL; + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + + ret = mt9m114_res2size(sd, &width, &height); + if (ret) + return ret; + fmt->width = width; + fmt->height = height; + + return 0; +} + +static int mt9m114_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct i2c_client *c = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct mt9m114_res_struct *res_index; + u32 width = fmt->width; + u32 height = fmt->height; + struct camera_mipi_info *mt9m114_info = NULL; + + int ret; + if (format->pad) + return -EINVAL; + dev->streamon = 0; + dev->first_exp = MT9M114_DEFAULT_FIRST_EXP; + + mt9m114_info = v4l2_get_subdev_hostdata(sd); + if (mt9m114_info == NULL) + return -EINVAL; + + mt9m114_try_res(&width, &height); + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + return 0; + } + res_index = mt9m114_to_res(width, height); + + /* Sanity check */ + if (unlikely(!res_index)) { + WARN_ON(1); + return -EINVAL; + } + + switch (res_index->res) { + case MT9M114_RES_736P: + ret = mt9m114_write_reg_array(c, mt9m114_736P_init, NO_POLLING); + ret += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_R_MODE_MASK, MISENSOR_NORMAL_SET); + break; + case MT9M114_RES_864P: + ret = mt9m114_write_reg_array(c, mt9m114_864P_init, NO_POLLING); + ret += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_R_MODE_MASK, MISENSOR_NORMAL_SET); + break; + case MT9M114_RES_960P: + ret = mt9m114_write_reg_array(c, mt9m114_976P_init, NO_POLLING); + /* set sensor read_mode to Normal */ + ret += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_R_MODE_MASK, MISENSOR_NORMAL_SET); + break; + default: + v4l2_err(sd, "set resolution: %d failed!\n", res_index->res); + return -EINVAL; + } + + if (ret) + return -EINVAL; + + ret = mt9m114_write_reg_array(c, mt9m114_chgstat_reg, POST_POLLING); + if (ret < 0) + return ret; + + if (mt9m114_set_suspend(sd)) + return -EINVAL; + + if (dev->res != res_index->res) { + int index; + + /* Switch to different size */ + if (width <= 640) { + dev->nctx = 0x00; /* Set for context A */ + } else { + /* + * Context B is used for resolutions larger than 640x480 + * Using YUV for Context B. + */ + dev->nctx = 0x01; /* set for context B */ + } + + /* + * Marked current sensor res as being "used" + * + * REVISIT: We don't need to use an "used" field on each mode + * list entry to know which mode is selected. If this + * information is really necessary, how about to use a single + * variable on sensor dev struct? + */ + for (index = 0; index < N_RES; index++) { + if ((width == mt9m114_res[index].width) && + (height == mt9m114_res[index].height)) { + mt9m114_res[index].used = true; + continue; + } + mt9m114_res[index].used = false; + } + } + ret = mt9m114_get_intg_factor(c, mt9m114_info, + &mt9m114_res[res_index->res]); + if (ret) { + dev_err(&c->dev, "failed to get integration_factor\n"); + return -EINVAL; + } + /* + * mt9m114 - we don't poll for context switch + * because it does not happen with streaming disabled. + */ + dev->res = res_index->res; + + fmt->width = width; + fmt->height = height; + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + return 0; +} + +/* TODO: Update to SOC functions, remove exposure and gain */ +static int mt9m114_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (MT9M114_FOCAL_LENGTH_NUM << 16) | MT9M114_FOCAL_LENGTH_DEM; + return 0; +} + +static int mt9m114_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for mt9m114*/ + *val = (MT9M114_F_NUMBER_DEFAULT_NUM << 16) | MT9M114_F_NUMBER_DEM; + return 0; +} + +static int mt9m114_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (MT9M114_F_NUMBER_DEFAULT_NUM << 24) | + (MT9M114_F_NUMBER_DEM << 16) | + (MT9M114_F_NUMBER_DEFAULT_NUM << 8) | MT9M114_F_NUMBER_DEM; + return 0; +} + +/* Horizontal flip the image. */ +static int mt9m114_g_hflip(struct v4l2_subdev *sd, s32 *val) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + int ret; + u32 data; + ret = mt9m114_read_reg(c, MISENSOR_16BIT, + (u32)MISENSOR_READ_MODE, &data); + if (ret) + return ret; + *val = !!(data & MISENSOR_HFLIP_MASK); + + return 0; +} + +static int mt9m114_g_vflip(struct v4l2_subdev *sd, s32 *val) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + int ret; + u32 data; + + ret = mt9m114_read_reg(c, MISENSOR_16BIT, + (u32)MISENSOR_READ_MODE, &data); + if (ret) + return ret; + *val = !!(data & MISENSOR_VFLIP_MASK); + + return 0; +} + +static long mt9m114_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + int ret = 0; + unsigned int coarse_integration = 0; + unsigned int fine_integration = 0; + unsigned int FLines = 0; + unsigned int FrameLengthLines = 0; /* ExposureTime.FrameLengthLines; */ + unsigned int AnalogGain, DigitalGain; + u32 AnalogGainToWrite = 0; + u16 exposure_local[3]; + + dev_dbg(&client->dev, "%s(0x%X 0x%X 0x%X)\n", __func__, + exposure->integration_time[0], exposure->gain[0], + exposure->gain[1]); + + coarse_integration = exposure->integration_time[0]; + /* fine_integration = ExposureTime.FineIntegrationTime; */ + /* FrameLengthLines = ExposureTime.FrameLengthLines; */ + FLines = mt9m114_res[dev->res].lines_per_frame; + AnalogGain = exposure->gain[0]; + DigitalGain = exposure->gain[1]; + if (!dev->streamon) { + /*Save the first exposure values while stream is off*/ + dev->first_exp = coarse_integration; + dev->first_gain = AnalogGain; + dev->first_diggain = DigitalGain; + } + /* DigitalGain = 0x400 * (((u16) DigitalGain) >> 8) + + ((unsigned int)(0x400 * (((u16) DigitalGain) & 0xFF)) >>8); */ + + /* set frame length */ + if (FLines < coarse_integration + 6) + FLines = coarse_integration + 6; + if (FLines < FrameLengthLines) + FLines = FrameLengthLines; + ret = mt9m114_write_reg(client, MISENSOR_16BIT, 0x300A, FLines); + if (ret) { + v4l2_err(client, "%s: fail to set FLines\n", __func__); + return -EINVAL; + } + + /* set coarse/fine integration */ + exposure_local[0] = REG_EXPO_COARSE; + exposure_local[1] = (u16)coarse_integration; + exposure_local[2] = (u16)fine_integration; + /* 3A provide real exposure time. + should not translate to any value here. */ + ret = mt9m114_write_reg(client, MISENSOR_16BIT, + REG_EXPO_COARSE, (u16)(coarse_integration)); + if (ret) { + v4l2_err(client, "%s: fail to set exposure time\n", __func__); + return -EINVAL; + } + + /* + // set analog/digital gain + switch(AnalogGain) + { + case 0: + AnalogGainToWrite = 0x0; + break; + case 1: + AnalogGainToWrite = 0x20; + break; + case 2: + AnalogGainToWrite = 0x60; + break; + case 4: + AnalogGainToWrite = 0xA0; + break; + case 8: + AnalogGainToWrite = 0xE0; + break; + default: + AnalogGainToWrite = 0x20; + break; + } + */ + if (DigitalGain >= 16 || DigitalGain <= 1) + DigitalGain = 1; + /* AnalogGainToWrite = + (u16)((DigitalGain << 12) | AnalogGainToWrite); */ + AnalogGainToWrite = (u16)((DigitalGain << 12) | (u16)AnalogGain); + ret = mt9m114_write_reg(client, MISENSOR_16BIT, + REG_GAIN, AnalogGainToWrite); + if (ret) { + v4l2_err(client, "%s: fail to set AnalogGainToWrite\n", + __func__); + return -EINVAL; + } + + return ret; +} + +static long mt9m114_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return mt9m114_s_exposure(sd, arg); + default: + return -EINVAL; + } + + return 0; +} + +/* This returns the exposure time being used. This should only be used + for filling in EXIF data, not for actual image processing. */ +static int mt9m114_g_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u32 coarse; + int ret; + + /* the fine integration time is currently not calculated */ + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_EXPO_COARSE, &coarse); + if (ret) + return ret; + + *value = coarse; + return 0; +} +#ifndef CSS15 +/* + * This function will return the sensor supported max exposure zone number. + * the sensor which supports max exposure zone number is 1. + */ +static int mt9m114_g_exposure_zone_num(struct v4l2_subdev *sd, s32 *val) +{ + *val = 1; + + return 0; +} + +/* + * set exposure metering, average/center_weighted/spot/matrix. + */ +static int mt9m114_s_exposure_metering(struct v4l2_subdev *sd, s32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + switch (val) { + case V4L2_EXPOSURE_METERING_SPOT: + ret = mt9m114_write_reg_array(client, mt9m114_exp_average, + NO_POLLING); + if (ret) { + dev_err(&client->dev, "write exp_average reg err.\n"); + return ret; + } + break; + case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED: + default: + ret = mt9m114_write_reg_array(client, mt9m114_exp_center, + NO_POLLING); + if (ret) { + dev_err(&client->dev, "write exp_default reg err"); + return ret; + } + } + + return 0; +} + +/* + * This function is for touch exposure feature. + */ +static int mt9m114_s_exposure_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct misensor_reg exp_reg; + int width, height; + int grid_width, grid_height; + int grid_left, grid_top, grid_right, grid_bottom; + int win_left, win_top, win_right, win_bottom; + int i, j; + int ret; + + if (sel->which != V4L2_SUBDEV_FORMAT_TRY && + sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) + return -EINVAL; + + grid_left = sel->r.left; + grid_top = sel->r.top; + grid_right = sel->r.left + sel->r.width - 1; + grid_bottom = sel->r.top + sel->r.height - 1; + + ret = mt9m114_res2size(sd, &width, &height); + if (ret) + return ret; + + grid_width = width / 5; + grid_height = height / 5; + + if (grid_width && grid_height) { + win_left = grid_left / grid_width; + win_top = grid_top / grid_height; + win_right = grid_right / grid_width; + win_bottom = grid_bottom / grid_height; + } else { + dev_err(&client->dev, "Incorrect exp grid.\n"); + return -EINVAL; + } + + clamp_t(int, win_left, 0, 4); + clamp_t(int, win_top, 0, 4); + clamp_t(int, win_right, 0, 4); + clamp_t(int, win_bottom, 0, 4); + + ret = mt9m114_write_reg_array(client, mt9m114_exp_average, NO_POLLING); + if (ret) { + dev_err(&client->dev, "write exp_average reg err.\n"); + return ret; + } + + for (i = win_top; i <= win_bottom; i++) { + for (j = win_left; j <= win_right; j++) { + exp_reg = mt9m114_exp_win[i][j]; + + ret = mt9m114_write_reg(client, exp_reg.length, + exp_reg.reg, exp_reg.val); + if (ret) { + dev_err(&client->dev, "write exp_reg err.\n"); + return ret; + } + } + } + + return 0; +} +#endif + +static int mt9m114_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + *val = mt9m114_res[dev->res].bin_factor_x; + + return 0; +} + +static int mt9m114_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + *val = mt9m114_res[dev->res].bin_factor_y; + + return 0; +} + +static int mt9m114_s_ev(struct v4l2_subdev *sd, s32 val) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + s32 luma = 0x37; + int err; + + /* EV value only support -2 to 2 + * 0: 0x37, 1:0x47, 2:0x57, -1:0x27, -2:0x17 + */ + if (val < -2 || val > 2) + return -EINVAL; + luma += 0x10 * val; + dev_dbg(&c->dev, "%s val:%d luma:0x%x\n", __func__, val, luma); + err = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC87A); + if (err) { + dev_err(&c->dev, "%s logic addr access error\n", __func__); + return err; + } + err = mt9m114_write_reg(c, MISENSOR_8BIT, 0xC87A, (u32)luma); + if (err) { + dev_err(&c->dev, "%s write target_average_luma failed\n", + __func__); + return err; + } + udelay(10); + + return 0; +} + +static int mt9m114_g_ev(struct v4l2_subdev *sd, s32 *val) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + int err; + u32 luma; + + err = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC87A); + if (err) { + dev_err(&c->dev, "%s logic addr access error\n", __func__); + return err; + } + err = mt9m114_read_reg(c, MISENSOR_8BIT, 0xC87A, &luma); + if (err) { + dev_err(&c->dev, "%s read target_average_luma failed\n", + __func__); + return err; + } + luma -= 0x17; + luma /= 0x10; + *val = (s32)luma - 2; + dev_dbg(&c->dev, "%s val:%d\n", __func__, *val); + + return 0; +} + +/* Fake interface + * mt9m114 now can not support 3a_lock +*/ +static int mt9m114_s_3a_lock(struct v4l2_subdev *sd, s32 val) +{ + aaalock = val; + return 0; +} + +static int mt9m114_g_3a_lock(struct v4l2_subdev *sd, s32 *val) +{ + if (aaalock) + return V4L2_LOCK_EXPOSURE | V4L2_LOCK_WHITE_BALANCE + | V4L2_LOCK_FOCUS; + return 0; +} + +static int mt9m114_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct mt9m114_device *dev = + container_of(ctrl->handler, struct mt9m114_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + dev_dbg(&client->dev, "%s: CID_VFLIP:%d.\n", + __func__, ctrl->val); + ret = mt9m114_t_vflip(&dev->sd, ctrl->val); + break; + case V4L2_CID_HFLIP: + dev_dbg(&client->dev, "%s: CID_HFLIP:%d.\n", + __func__, ctrl->val); + ret = mt9m114_t_hflip(&dev->sd, ctrl->val); + break; +#ifndef CSS15 + case V4L2_CID_EXPOSURE_METERING: + ret = mt9m114_s_exposure_metering(&dev->sd, ctrl->val); + break; +#endif + case V4L2_CID_EXPOSURE: + ret = mt9m114_s_ev(&dev->sd, ctrl->val); + break; + case V4L2_CID_3A_LOCK: + ret = mt9m114_s_3a_lock(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int mt9m114_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct mt9m114_device *dev = + container_of(ctrl->handler, struct mt9m114_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + ret = mt9m114_g_vflip(&dev->sd, &ctrl->val); + break; + case V4L2_CID_HFLIP: + ret = mt9m114_g_hflip(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = mt9m114_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = mt9m114_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = mt9m114_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = mt9m114_g_exposure(&dev->sd, &ctrl->val); + break; +#ifndef CSS15 + case V4L2_CID_EXPOSURE_ZONE_NUM: + ret = mt9m114_g_exposure_zone_num(&dev->sd, &ctrl->val); + break; +#endif + case V4L2_CID_BIN_FACTOR_HORZ: + ret = mt9m114_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = mt9m114_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + case V4L2_CID_EXPOSURE: + ret = mt9m114_g_ev(&dev->sd, &ctrl->val); + break; + case V4L2_CID_3A_LOCK: + ret = mt9m114_g_3a_lock(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = mt9m114_s_ctrl, + .g_volatile_ctrl = mt9m114_g_volatile_ctrl +}; + +static struct v4l2_ctrl_config mt9m114_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .name = "Image v-Flip", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .name = "Image h-Flip", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .name = "focal length", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = MT9M114_FOCAL_LENGTH_DEFAULT, + .max = MT9M114_FOCAL_LENGTH_DEFAULT, + .step = 1, + .def = MT9M114_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .name = "f-number", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = MT9M114_F_NUMBER_DEFAULT, + .max = MT9M114_F_NUMBER_DEFAULT, + .step = 1, + .def = MT9M114_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .name = "f-number range", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = MT9M114_F_NUMBER_RANGE, + .max = MT9M114_F_NUMBER_RANGE, + .step = 1, + .def = MT9M114_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .name = "exposure", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 0xffff, + .step = 1, + .def = 0, + .flags = 0, + }, +#ifndef CSS15 + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ZONE_NUM, + .name = "one-time exposure zone number", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 0xffff, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_METERING, + .name = "metering", + .type = V4L2_CTRL_TYPE_MENU, + .min = 0, + .max = 3, + .step = 1, + .def = 1, + .flags = 0, + }, +#endif + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .name = "horizontal binning factor", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = MT9M114_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .name = "vertical binning factor", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = MT9M114_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE, + .name = "exposure biasx", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = -2, + .max = 2, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_3A_LOCK, + .name = "3a lock", + .type = V4L2_CTRL_TYPE_BITMASK, + .min = 0, + .max = V4L2_LOCK_EXPOSURE | V4L2_LOCK_WHITE_BALANCE | V4L2_LOCK_FOCUS, + .step = 1, + .def = 0, + .flags = 0, + }, +}; + +static int mt9m114_detect(struct mt9m114_device *dev, struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u32 retvalue; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) { + dev_err(&client->dev, "%s: i2c error", __func__); + return -ENODEV; + } + mt9m114_read_reg(client, MISENSOR_16BIT, (u32)MT9M114_PID, &retvalue); + dev->real_model_id = retvalue; + + if (retvalue != MT9M114_MOD_ID) { + dev_err(&client->dev, "%s: failed: client->addr = %x\n", + __func__, client->addr); + return -ENODEV; + } + + return 0; +} + +static int +mt9m114_s_config(struct v4l2_subdev *sd, int irq, void *platform_data) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (NULL == platform_data) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) { + v4l2_err(client, "mt9m114 platform init err\n"); + return ret; + } + } + ret = power_up(sd); + if (ret) { + v4l2_err(client, "mt9m114 power-up err"); + return ret; + } + + /* config & detect sensor */ + ret = mt9m114_detect(dev, client); + if (ret) { + v4l2_err(client, "mt9m114_detect err s_config.\n"); + goto fail_detect; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + ret = mt9m114_set_suspend(sd); + if (ret) { + v4l2_err(client, "mt9m114 suspend err"); + return ret; + } + + ret = power_down(sd); + if (ret) { + v4l2_err(client, "mt9m114 power down err"); + return ret; + } + + return ret; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_detect: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); + return ret; +} + +/* Horizontal flip the image. */ +static int mt9m114_t_hflip(struct v4l2_subdev *sd, int value) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + int err; + /* set for direct mode */ + err = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC850); + if (value) { + /* enable H flip ctx A */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x01, 0x01); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x01, 0x01); + /* ctx B */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x01, 0x01); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x01, 0x01); + + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_HFLIP_MASK, MISENSOR_FLIP_EN); + + dev->bpat = MT9M114_BPAT_GRGRBGBG; + } else { + /* disable H flip ctx A */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x01, 0x00); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x01, 0x00); + /* ctx B */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x01, 0x00); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x01, 0x00); + + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_HFLIP_MASK, MISENSOR_FLIP_DIS); + + dev->bpat = MT9M114_BPAT_BGBGGRGR; + } + + err += mt9m114_write_reg(c, MISENSOR_8BIT, 0x8404, 0x06); + udelay(10); + + return !!err; +} + +/* Vertically flip the image */ +static int mt9m114_t_vflip(struct v4l2_subdev *sd, int value) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + int err; + /* set for direct mode */ + err = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC850); + if (value >= 1) { + /* enable H flip - ctx A */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x02, 0x01); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x02, 0x01); + /* ctx B */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x02, 0x01); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x02, 0x01); + + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_VFLIP_MASK, MISENSOR_FLIP_EN); + } else { + /* disable H flip - ctx A */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x02, 0x00); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x02, 0x00); + /* ctx B */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x02, 0x00); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x02, 0x00); + + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_VFLIP_MASK, MISENSOR_FLIP_DIS); + } + + err += mt9m114_write_reg(c, MISENSOR_8BIT, 0x8404, 0x06); + udelay(10); + + return !!err; +} +static int mt9m114_s_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + return 0; +} + +static int mt9m114_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = mt9m114_res[dev->res].fps; + + return 0; +} + +static int mt9m114_s_stream(struct v4l2_subdev *sd, int enable) +{ + int ret; + struct i2c_client *c = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct atomisp_exposure exposure; + + if (enable) { + ret = mt9m114_write_reg_array(c, mt9m114_chgstat_reg, + POST_POLLING); + if (ret < 0) + return ret; + + if (dev->first_exp > MT9M114_MAX_FIRST_EXP) { + exposure.integration_time[0] = dev->first_exp; + exposure.gain[0] = dev->first_gain; + exposure.gain[1] = dev->first_diggain; + mt9m114_s_exposure(sd, &exposure); + } + dev->streamon = 1; + + } else { + dev->streamon = 0; + ret = mt9m114_set_suspend(sd); + } + + return ret; +} + +static int mt9m114_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index) + return -EINVAL; + code->code = MEDIA_BUS_FMT_SGRBG10_1X10; + + return 0; +} + +static int mt9m114_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + + unsigned int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = mt9m114_res[index].width; + fse->min_height = mt9m114_res[index].height; + fse->max_width = mt9m114_res[index].width; + fse->max_height = mt9m114_res[index].height; + + return 0; +} + +static int mt9m114_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + int index; + struct mt9m114_device *snr = to_mt9m114_sensor(sd); + + if (frames == NULL) + return -EINVAL; + + for (index = 0; index < N_RES; index++) { + if (mt9m114_res[index].res == snr->res) + break; + } + + if (index >= N_RES) + return -EINVAL; + + *frames = mt9m114_res[index].skip_frames; + + return 0; +} + +static const struct v4l2_subdev_video_ops mt9m114_video_ops = { + .s_parm = mt9m114_s_parm, + .s_stream = mt9m114_s_stream, + .g_frame_interval = mt9m114_g_frame_interval, +}; + +static struct v4l2_subdev_sensor_ops mt9m114_sensor_ops = { + .g_skip_frames = mt9m114_g_skip_frames, +}; + +static const struct v4l2_subdev_core_ops mt9m114_core_ops = { + .s_power = mt9m114_s_power, + .ioctl = mt9m114_ioctl, +}; + +/* REVISIT: Do we need pad operations? */ +static const struct v4l2_subdev_pad_ops mt9m114_pad_ops = { + .enum_mbus_code = mt9m114_enum_mbus_code, + .enum_frame_size = mt9m114_enum_frame_size, + .get_fmt = mt9m114_get_fmt, + .set_fmt = mt9m114_set_fmt, +#ifndef CSS15 + .set_selection = mt9m114_s_exposure_selection, +#endif +}; + +static const struct v4l2_subdev_ops mt9m114_ops = { + .core = &mt9m114_core_ops, + .video = &mt9m114_video_ops, + .pad = &mt9m114_pad_ops, + .sensor = &mt9m114_sensor_ops, +}; + +static const struct media_entity_operations mt9m114_entity_ops = { + .link_setup = NULL, +}; + +static int mt9m114_remove(struct i2c_client *client) +{ + struct mt9m114_device *dev; + struct v4l2_subdev *sd = i2c_get_clientdata(client); + + dev = container_of(sd, struct mt9m114_device, sd); + dev->platform_data->csi_cfg(sd, 0); + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); + return 0; +} + +static int mt9m114_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct mt9m114_device *dev; + int ret = 0; + unsigned int i; + void *pdata; + + /* Setup sensor configuration structure */ + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + v4l2_i2c_subdev_init(&dev->sd, client, &mt9m114_ops); + pdata = client->dev.platform_data; + if (ACPI_COMPANION(&client->dev)) + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_grbg); + if (pdata) + ret = mt9m114_s_config(&dev->sd, client->irq, pdata); + if (!pdata || ret) { + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; + } + + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) { + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + /* Coverity CID 298095 - return on error */ + return ret; + } + + /*TODO add format code here*/ + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(mt9m114_controls)); + if (ret) { + mt9m114_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(mt9m114_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &mt9m114_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + mt9m114_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + /* REVISIT: Do we need media controller? */ + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) { + mt9m114_remove(client); + return ret; + } + return 0; +} + +MODULE_DEVICE_TABLE(i2c, mt9m114_id); + +static struct acpi_device_id mt9m114_acpi_match[] = { + { "INT33F0" }, + { "CRMT1040" }, + {}, +}; + +MODULE_DEVICE_TABLE(acpi, mt9m114_acpi_match); + +static struct i2c_driver mt9m114_driver = { + .driver = { + .name = "mt9m114", + .acpi_match_table = ACPI_PTR(mt9m114_acpi_match), + }, + .probe = mt9m114_probe, + .remove = mt9m114_remove, + .id_table = mt9m114_id, +}; + +static __init int init_mt9m114(void) +{ + return i2c_add_driver(&mt9m114_driver); +} + +static __exit void exit_mt9m114(void) +{ + i2c_del_driver(&mt9m114_driver); +} + +module_init(init_mt9m114); +module_exit(exit_mt9m114); + +MODULE_AUTHOR("Shuguang Gong <Shuguang.gong@intel.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/mt9m114.h b/drivers/staging/media/atomisp/i2c/mt9m114.h new file mode 100644 index 0000000..5e7d79d --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/mt9m114.h @@ -0,0 +1,1786 @@ +/* + * Support for mt9m114 Camera Sensor. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __A1040_H__ +#define __A1040_H__ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/i2c.h> +#include <linux/delay.h> +#include <linux/videodev2.h> +#include <linux/spinlock.h> +#include <media/v4l2-subdev.h> +#include <media/v4l2-device.h> +#include <media/v4l2-ctrls.h> +#include <linux/v4l2-mediabus.h> +#include <media/media-entity.h> +#include "../include/linux/atomisp_platform.h" +#include "../include/linux/atomisp.h" + +#define V4L2_IDENT_MT9M114 8245 + +#define MT9P111_REV3 +#define FULLINISUPPORT + +/* #defines for register writes and register array processing */ +#define MISENSOR_8BIT 1 +#define MISENSOR_16BIT 2 +#define MISENSOR_32BIT 4 + +#define MISENSOR_FWBURST0 0x80 +#define MISENSOR_FWBURST1 0x81 +#define MISENSOR_FWBURST4 0x84 +#define MISENSOR_FWBURST 0x88 + +#define MISENSOR_TOK_TERM 0xf000 /* terminating token for reg list */ +#define MISENSOR_TOK_DELAY 0xfe00 /* delay token for reg list */ +#define MISENSOR_TOK_FWLOAD 0xfd00 /* token indicating load FW */ +#define MISENSOR_TOK_POLL 0xfc00 /* token indicating poll instruction */ +#define MISENSOR_TOK_RMW 0x0010 /* RMW operation */ +#define MISENSOR_TOK_MASK 0xfff0 +#define MISENSOR_AWB_STEADY (1<<0) /* awb steady */ +#define MISENSOR_AE_READY (1<<3) /* ae status ready */ + +/* mask to set sensor read_mode via misensor_rmw_reg */ +#define MISENSOR_R_MODE_MASK 0x0330 +/* mask to set sensor vert_flip and horz_mirror */ +#define MISENSOR_VFLIP_MASK 0x0002 +#define MISENSOR_HFLIP_MASK 0x0001 +#define MISENSOR_FLIP_EN 1 +#define MISENSOR_FLIP_DIS 0 + +/* bits set to set sensor read_mode via misensor_rmw_reg */ +#define MISENSOR_SKIPPING_SET 0x0011 +#define MISENSOR_SUMMING_SET 0x0033 +#define MISENSOR_NORMAL_SET 0x0000 + +/* sensor register that control sensor read-mode and mirror */ +#define MISENSOR_READ_MODE 0xC834 +/* sensor ae-track status register */ +#define MISENSOR_AE_TRACK_STATUS 0xA800 +/* sensor awb status register */ +#define MISENSOR_AWB_STATUS 0xAC00 +/* sensor coarse integration time register */ +#define MISENSOR_COARSE_INTEGRATION_TIME 0xC83C + +/* registers */ +#define REG_SW_RESET 0x301A +#define REG_SW_STREAM 0xDC00 +#define REG_SCCB_CTRL 0x3100 +#define REG_SC_CMMN_CHIP_ID 0x0000 +#define REG_V_START 0xc800 /* 16bits */ +#define REG_H_START 0xc802 /* 16bits */ +#define REG_V_END 0xc804 /* 16bits */ +#define REG_H_END 0xc806 /* 16bits */ +#define REG_PIXEL_CLK 0xc808 /* 32bits */ +#define REG_TIMING_VTS 0xc812 /* 16bits */ +#define REG_TIMING_HTS 0xc814 /* 16bits */ +#define REG_WIDTH 0xC868 /* 16bits */ +#define REG_HEIGHT 0xC86A /* 16bits */ +#define REG_EXPO_COARSE 0x3012 /* 16bits */ +#define REG_EXPO_FINE 0x3014 /* 16bits */ +#define REG_GAIN 0x305E +#define REG_ANALOGGAIN 0x305F +#define REG_ADDR_ACESSS 0x098E /* logical_address_access */ +#define REG_COMM_Register 0x0080 /* command_register */ + +#define SENSOR_DETECTED 1 +#define SENSOR_NOT_DETECTED 0 + +#define I2C_RETRY_COUNT 5 +#define MSG_LEN_OFFSET 2 + +#ifndef MIPI_CONTROL +#define MIPI_CONTROL 0x3400 /* MIPI_Control */ +#endif + +/* GPIO pin on Moorestown */ +#define GPIO_SCLK_25 44 +#define GPIO_STB_PIN 47 + +#define GPIO_STDBY_PIN 49 /* ab:new */ +#define GPIO_RESET_PIN 50 + +/* System control register for Aptina A-1040SOC*/ +#define MT9M114_PID 0x0 + +/* MT9P111_DEVICE_ID */ +#define MT9M114_MOD_ID 0x2481 + +#define MT9M114_FINE_INTG_TIME_MIN 0 +#define MT9M114_FINE_INTG_TIME_MAX_MARGIN 0 +#define MT9M114_COARSE_INTG_TIME_MIN 1 +#define MT9M114_COARSE_INTG_TIME_MAX_MARGIN 6 + + +/* ulBPat; */ + +#define MT9M114_BPAT_RGRGGBGB (1 << 0) +#define MT9M114_BPAT_GRGRBGBG (1 << 1) +#define MT9M114_BPAT_GBGBRGRG (1 << 2) +#define MT9M114_BPAT_BGBGGRGR (1 << 3) + +#define MT9M114_FOCAL_LENGTH_NUM 208 /*2.08mm*/ +#define MT9M114_FOCAL_LENGTH_DEM 100 +#define MT9M114_F_NUMBER_DEFAULT_NUM 24 +#define MT9M114_F_NUMBER_DEM 10 +#define MT9M114_WAIT_STAT_TIMEOUT 100 +#define MT9M114_FLICKER_MODE_50HZ 1 +#define MT9M114_FLICKER_MODE_60HZ 2 +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define MT9M114_FOCAL_LENGTH_DEFAULT 0xD00064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define MT9M114_F_NUMBER_DEFAULT 0x18000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define MT9M114_F_NUMBER_RANGE 0x180a180a + +/* Supported resolutions */ +enum { + MT9M114_RES_736P, + MT9M114_RES_864P, + MT9M114_RES_960P, +}; +#define MT9M114_RES_960P_SIZE_H 1296 +#define MT9M114_RES_960P_SIZE_V 976 +#define MT9M114_RES_720P_SIZE_H 1280 +#define MT9M114_RES_720P_SIZE_V 720 +#define MT9M114_RES_576P_SIZE_H 1024 +#define MT9M114_RES_576P_SIZE_V 576 +#define MT9M114_RES_480P_SIZE_H 768 +#define MT9M114_RES_480P_SIZE_V 480 +#define MT9M114_RES_VGA_SIZE_H 640 +#define MT9M114_RES_VGA_SIZE_V 480 +#define MT9M114_RES_QVGA_SIZE_H 320 +#define MT9M114_RES_QVGA_SIZE_V 240 +#define MT9M114_RES_QCIF_SIZE_H 176 +#define MT9M114_RES_QCIF_SIZE_V 144 + +#define MT9M114_RES_720_480p_768_SIZE_H 736 +#define MT9M114_RES_720_480p_768_SIZE_V 496 +#define MT9M114_RES_736P_SIZE_H 1296 +#define MT9M114_RES_736P_SIZE_V 736 +#define MT9M114_RES_864P_SIZE_H 1296 +#define MT9M114_RES_864P_SIZE_V 864 +#define MT9M114_RES_976P_SIZE_H 1296 +#define MT9M114_RES_976P_SIZE_V 976 + +#define MT9M114_BIN_FACTOR_MAX 3 + +#define MT9M114_DEFAULT_FIRST_EXP 0x10 +#define MT9M114_MAX_FIRST_EXP 0x302 + +/* completion status polling requirements, usage based on Aptina .INI Rev2 */ +enum poll_reg { + NO_POLLING, + PRE_POLLING, + POST_POLLING, +}; +/* + * struct misensor_reg - MI sensor register format + * @length: length of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * Define a structure for sensor register initialization values + */ +struct misensor_reg { + u32 length; + u32 reg; + u32 val; /* value or for read/mod/write, AND mask */ + u32 val2; /* optional; for rmw, OR mask */ +}; + +/* + * struct misensor_fwreg - Firmware burst command + * @type: FW burst or 8/16 bit register + * @addr: 16-bit offset to register or other values depending on type + * @valx: data value for burst (or other commands) + * + * Define a structure for sensor register initialization values + */ +struct misensor_fwreg { + u32 type; /* type of value, register or FW burst string */ + u32 addr; /* target address */ + u32 val0; + u32 val1; + u32 val2; + u32 val3; + u32 val4; + u32 val5; + u32 val6; + u32 val7; +}; + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct mt9m114_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + + struct camera_sensor_platform_data *platform_data; + struct mutex input_lock; /* serialize sensor's ioctl */ + struct v4l2_ctrl_handler ctrl_handler; + int real_model_id; + int nctx; + int power; + + unsigned int bus_width; + unsigned int mode; + unsigned int field_inv; + unsigned int field_sel; + unsigned int ycseq; + unsigned int conv422; + unsigned int bpat; + unsigned int hpol; + unsigned int vpol; + unsigned int edge; + unsigned int bls; + unsigned int gamma; + unsigned int cconv; + unsigned int res; + unsigned int dwn_sz; + unsigned int blc; + unsigned int agc; + unsigned int awb; + unsigned int aec; + /* extention SENSOR version 2 */ + unsigned int cie_profile; + + /* extention SENSOR version 3 */ + unsigned int flicker_freq; + + /* extension SENSOR version 4 */ + unsigned int smia_mode; + unsigned int mipi_mode; + + /* Add name here to load shared library */ + unsigned int type; + + /*Number of MIPI lanes*/ + unsigned int mipi_lanes; + /*WA for low light AE*/ + unsigned int first_exp; + unsigned int first_gain; + unsigned int first_diggain; + char name[32]; + + u8 lightfreq; + u8 streamon; +}; + +struct mt9m114_format_struct { + u8 *desc; + u32 pixelformat; + struct regval_list *regs; +}; + +struct mt9m114_res_struct { + u8 *desc; + int res; + int width; + int height; + int fps; + int skip_frames; + bool used; + struct regval_list *regs; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; +}; + +/* 2 bytes used for address: 256 bytes total */ +#define MT9M114_MAX_WRITE_BUF_SIZE 254 +struct mt9m114_write_buffer { + u16 addr; + u8 data[MT9M114_MAX_WRITE_BUF_SIZE]; +}; + +struct mt9m114_write_ctrl { + int index; + struct mt9m114_write_buffer buffer; +}; + +/* + * Modes supported by the mt9m114 driver. + * Please, keep them in ascending order. + */ +static struct mt9m114_res_struct mt9m114_res[] = { + { + .desc = "720P", + .res = MT9M114_RES_736P, + .width = 1296, + .height = 736, + .fps = 30, + .used = false, + .regs = NULL, + .skip_frames = 1, + + .pixels_per_line = 0x0640, + .lines_per_frame = 0x0307, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + }, + { + .desc = "848P", + .res = MT9M114_RES_864P, + .width = 1296, + .height = 864, + .fps = 30, + .used = false, + .regs = NULL, + .skip_frames = 1, + + .pixels_per_line = 0x0640, + .lines_per_frame = 0x03E8, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + }, + { + .desc = "960P", + .res = MT9M114_RES_960P, + .width = 1296, + .height = 976, + .fps = 30, + .used = false, + .regs = NULL, + .skip_frames = 1, + + .pixels_per_line = 0x0644, /* consistent with regs arrays */ + .lines_per_frame = 0x03E5, /* consistent with regs arrays */ + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + }, +}; +#define N_RES (ARRAY_SIZE(mt9m114_res)) + +static const struct i2c_device_id mt9m114_id[] = { + {"mt9m114", 0}, + {} +}; + +static struct misensor_reg const mt9m114_exitstandby[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + /* exit-standby */ + {MISENSOR_8BIT, 0xDC00, 0x54}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_exp_win[5][5] = { + { + {MISENSOR_8BIT, 0xA407, 0x64}, + {MISENSOR_8BIT, 0xA408, 0x64}, + {MISENSOR_8BIT, 0xA409, 0x64}, + {MISENSOR_8BIT, 0xA40A, 0x64}, + {MISENSOR_8BIT, 0xA40B, 0x64}, + }, + { + {MISENSOR_8BIT, 0xA40C, 0x64}, + {MISENSOR_8BIT, 0xA40D, 0x64}, + {MISENSOR_8BIT, 0xA40E, 0x64}, + {MISENSOR_8BIT, 0xA40F, 0x64}, + {MISENSOR_8BIT, 0xA410, 0x64}, + }, + { + {MISENSOR_8BIT, 0xA411, 0x64}, + {MISENSOR_8BIT, 0xA412, 0x64}, + {MISENSOR_8BIT, 0xA413, 0x64}, + {MISENSOR_8BIT, 0xA414, 0x64}, + {MISENSOR_8BIT, 0xA415, 0x64}, + }, + { + {MISENSOR_8BIT, 0xA416, 0x64}, + {MISENSOR_8BIT, 0xA417, 0x64}, + {MISENSOR_8BIT, 0xA418, 0x64}, + {MISENSOR_8BIT, 0xA419, 0x64}, + {MISENSOR_8BIT, 0xA41A, 0x64}, + }, + { + {MISENSOR_8BIT, 0xA41B, 0x64}, + {MISENSOR_8BIT, 0xA41C, 0x64}, + {MISENSOR_8BIT, 0xA41D, 0x64}, + {MISENSOR_8BIT, 0xA41E, 0x64}, + {MISENSOR_8BIT, 0xA41F, 0x64}, + }, +}; + +static struct misensor_reg const mt9m114_exp_average[] = { + {MISENSOR_8BIT, 0xA407, 0x00}, + {MISENSOR_8BIT, 0xA408, 0x00}, + {MISENSOR_8BIT, 0xA409, 0x00}, + {MISENSOR_8BIT, 0xA40A, 0x00}, + {MISENSOR_8BIT, 0xA40B, 0x00}, + {MISENSOR_8BIT, 0xA40C, 0x00}, + {MISENSOR_8BIT, 0xA40D, 0x00}, + {MISENSOR_8BIT, 0xA40E, 0x00}, + {MISENSOR_8BIT, 0xA40F, 0x00}, + {MISENSOR_8BIT, 0xA410, 0x00}, + {MISENSOR_8BIT, 0xA411, 0x00}, + {MISENSOR_8BIT, 0xA412, 0x00}, + {MISENSOR_8BIT, 0xA413, 0x00}, + {MISENSOR_8BIT, 0xA414, 0x00}, + {MISENSOR_8BIT, 0xA415, 0x00}, + {MISENSOR_8BIT, 0xA416, 0x00}, + {MISENSOR_8BIT, 0xA417, 0x00}, + {MISENSOR_8BIT, 0xA418, 0x00}, + {MISENSOR_8BIT, 0xA419, 0x00}, + {MISENSOR_8BIT, 0xA41A, 0x00}, + {MISENSOR_8BIT, 0xA41B, 0x00}, + {MISENSOR_8BIT, 0xA41C, 0x00}, + {MISENSOR_8BIT, 0xA41D, 0x00}, + {MISENSOR_8BIT, 0xA41E, 0x00}, + {MISENSOR_8BIT, 0xA41F, 0x00}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_exp_center[] = { + {MISENSOR_8BIT, 0xA407, 0x19}, + {MISENSOR_8BIT, 0xA408, 0x19}, + {MISENSOR_8BIT, 0xA409, 0x19}, + {MISENSOR_8BIT, 0xA40A, 0x19}, + {MISENSOR_8BIT, 0xA40B, 0x19}, + {MISENSOR_8BIT, 0xA40C, 0x19}, + {MISENSOR_8BIT, 0xA40D, 0x4B}, + {MISENSOR_8BIT, 0xA40E, 0x4B}, + {MISENSOR_8BIT, 0xA40F, 0x4B}, + {MISENSOR_8BIT, 0xA410, 0x19}, + {MISENSOR_8BIT, 0xA411, 0x19}, + {MISENSOR_8BIT, 0xA412, 0x4B}, + {MISENSOR_8BIT, 0xA413, 0x64}, + {MISENSOR_8BIT, 0xA414, 0x4B}, + {MISENSOR_8BIT, 0xA415, 0x19}, + {MISENSOR_8BIT, 0xA416, 0x19}, + {MISENSOR_8BIT, 0xA417, 0x4B}, + {MISENSOR_8BIT, 0xA418, 0x4B}, + {MISENSOR_8BIT, 0xA419, 0x4B}, + {MISENSOR_8BIT, 0xA41A, 0x19}, + {MISENSOR_8BIT, 0xA41B, 0x19}, + {MISENSOR_8BIT, 0xA41C, 0x19}, + {MISENSOR_8BIT, 0xA41D, 0x19}, + {MISENSOR_8BIT, 0xA41E, 0x19}, + {MISENSOR_8BIT, 0xA41F, 0x19}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_suspend[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x40}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_streaming[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x34}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_standby_reg[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x50}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_wakeup_reg[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x54}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_chgstat_reg[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x28}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +/* [1296x976_30fps] - Intel */ +static struct misensor_reg const mt9m114_960P_init[] = { + {MISENSOR_16BIT, 0x098E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0000}, /* cam_sensor_cfg_y_addr_start = 0 */ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MISENSOR_16BIT, 0xC804, 0x03CF}, /* cam_sensor_cfg_y_addr_end = 971 */ + {MISENSOR_16BIT, 0xC806, 0x050F}, /* cam_sensor_cfg_x_addr_end = 1291 */ + {MISENSOR_16BIT, 0xC808, 0x02DC}, /* cam_sensor_cfg_pixclk = 48000000 */ + {MISENSOR_16BIT, 0xC80A, 0x6C00}, + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* cam_sensor_cfg_fine_integ_time_max = 1459 */ + {MISENSOR_16BIT, 0xC810, 0x05B3}, + /* cam_sensor_cfg_frame_length_lines = 1006 */ + {MISENSOR_16BIT, 0xC812, 0x03F6}, + /* cam_sensor_cfg_line_length_pck = 1590 */ + {MISENSOR_16BIT, 0xC814, 0x063E}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + /* cam_sensor_cfg_cpipe_last_row = 963 */ + {MISENSOR_16BIT, 0xC818, 0x03C3}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0508}, /* cam_crop_window_width = 1280 */ + {MISENSOR_16BIT, 0xC85A, 0x03C8}, /* cam_crop_window_height = 960 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0508}, /* cam_output_width = 1280 */ + {MISENSOR_16BIT, 0xC86A, 0x03C8}, /* cam_output_height = 960 */ + {MISENSOR_TOK_TERM, 0, 0}, +}; + +/* [1296x976_30fps_768Mbps] */ +static struct misensor_reg const mt9m114_976P_init[] = { + {MISENSOR_16BIT, 0x98E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0000}, /* cam_sensor_cfg_y_addr_start = 0 */ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MISENSOR_16BIT, 0xC804, 0x03CF}, /* cam_sensor_cfg_y_addr_end = 975 */ + {MISENSOR_16BIT, 0xC806, 0x050F}, /* cam_sensor_cfg_x_addr_end = 1295 */ + {MISENSOR_32BIT, 0xC808, 0x2DC6C00},/* cam_sensor_cfg_pixclk = 480000*/ + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* 0x062E //cam_sensor_cfg_fine_integ_time_max = 1459 */ + {MISENSOR_16BIT, 0xC810, 0x05B3}, + /* 0x074C //cam_sensor_cfg_frame_length_lines = 1006 */ + {MISENSOR_16BIT, 0xC812, 0x03E5}, + /* 0x06B1 /cam_sensor_cfg_line_length_pck = 1590 */ + {MISENSOR_16BIT, 0xC814, 0x0644}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + /* cam_sensor_cfg_cpipe_last_row = 963 */ + {MISENSOR_16BIT, 0xC818, 0x03C3}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0508}, /* cam_crop_window_width = 1288 */ + {MISENSOR_16BIT, 0xC85A, 0x03C8}, /* cam_crop_window_height = 968 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0508}, /* cam_output_width = 1288 */ + {MISENSOR_16BIT, 0xC86A, 0x03C8}, /* cam_output_height = 968 */ + {MISENSOR_8BIT, 0xC878, 0x00}, /* 0x0E //cam_aet_aemode = 0 */ + {MISENSOR_TOK_TERM, 0, 0} +}; + +/* [1296x864_30fps] */ +static struct misensor_reg const mt9m114_864P_init[] = { + {MISENSOR_16BIT, 0x98E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0038}, /* cam_sensor_cfg_y_addr_start = 56 */ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MISENSOR_16BIT, 0xC804, 0x0397}, /* cam_sensor_cfg_y_addr_end = 919 */ + {MISENSOR_16BIT, 0xC806, 0x050F}, /* cam_sensor_cfg_x_addr_end = 1295 */ + /* cam_sensor_cfg_pixclk = 48000000 */ + {MISENSOR_32BIT, 0xC808, 0x2DC6C00}, + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* cam_sensor_cfg_fine_integ_time_max = 1469 */ + {MISENSOR_16BIT, 0xC810, 0x05BD}, + /* cam_sensor_cfg_frame_length_lines = 1000 */ + {MISENSOR_16BIT, 0xC812, 0x03E8}, + /* cam_sensor_cfg_line_length_pck = 1600 */ + {MISENSOR_16BIT, 0xC814, 0x0640}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + /* cam_sensor_cfg_cpipe_last_row = 859 */ + {MISENSOR_16BIT, 0xC818, 0x035B}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0508}, /* cam_crop_window_width = 1288 */ + {MISENSOR_16BIT, 0xC85A, 0x0358}, /* cam_crop_window_height = 856 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0508}, /* cam_output_width = 1288 */ + {MISENSOR_16BIT, 0xC86A, 0x0358}, /* cam_output_height = 856 */ + {MISENSOR_8BIT, 0xC878, 0x00}, /* 0x0E //cam_aet_aemode = 0 */ + {MISENSOR_TOK_TERM, 0, 0} +}; + +/* [1296x736_30fps] */ +static struct misensor_reg const mt9m114_736P_init[] = { + {MISENSOR_16BIT, 0x98E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x011F}, /* cam_sysctl_pll_divider_m_n = 287 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0078}, /* cam_sensor_cfg_y_addr_start = 120*/ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MISENSOR_16BIT, 0xC804, 0x0357}, /* cam_sensor_cfg_y_addr_end = 855 */ + {MISENSOR_16BIT, 0xC806, 0x050F}, /* cam_sensor_cfg_x_addr_end = 1295 */ + {MISENSOR_32BIT, 0xC808, 0x237A07F}, /* cam_sensor_cfg_pixclk=37199999*/ + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* 0x062E //cam_sensor_cfg_fine_integ_time_max = 1469 */ + {MISENSOR_16BIT, 0xC810, 0x05BD}, + /* 0x074C //cam_sensor_cfg_frame_length_lines = 775 */ + {MISENSOR_16BIT, 0xC812, 0x0307}, + /* 0x06B1 /cam_sensor_cfg_line_length_pck = 1600 */ + {MISENSOR_16BIT, 0xC814, 0x0640}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + /* cam_sensor_cfg_cpipe_last_row = 731 */ + {MISENSOR_16BIT, 0xC818, 0x02DB}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0508}, /* cam_crop_window_width = 1288 */ + {MISENSOR_16BIT, 0xC85A, 0x02D8}, /* cam_crop_window_height = 728 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0508}, /* cam_output_width = 1288 */ + {MISENSOR_16BIT, 0xC86A, 0x02D8}, /* cam_output_height = 728 */ + {MISENSOR_8BIT, 0xC878, 0x00}, /* 0x0E //cam_aet_aemode = 0 */ + {MISENSOR_TOK_TERM, 0, 0} +}; + +/* [736x496_30fps_768Mbps] */ +static struct misensor_reg const mt9m114_720_480P_init[] = { + {MISENSOR_16BIT, 0x98E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x00F0}, /* cam_sensor_cfg_y_addr_start = 240*/ + {MISENSOR_16BIT, 0xC802, 0x0118}, /* cam_sensor_cfg_x_addr_start = 280*/ + {MISENSOR_16BIT, 0xC804, 0x02DF}, /* cam_sensor_cfg_y_addr_end = 735 */ + {MISENSOR_16BIT, 0xC806, 0x03F7}, /* cam_sensor_cfg_x_addr_end = 1015 */ + /* cam_sensor_cfg_pixclk = 48000000 */ + {MISENSOR_32BIT, 0xC808, 0x2DC6C00}, + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* 0x062E //cam_sensor_cfg_fine_integ_time_max = 1459 */ + {MISENSOR_16BIT, 0xC810, 0x05B3}, + /* 0x074C //cam_sensor_cfg_frame_length_lines = 997 */ + {MISENSOR_16BIT, 0xC812, 0x03E5}, + /* 0x06B1 /cam_sensor_cfg_line_length_pck = 1604 */ + {MISENSOR_16BIT, 0xC814, 0x0644}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + {MISENSOR_16BIT, 0xC818, 0x03C3}, /* cam_sensor_cfg_cpipe_last_row=963*/ + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0*/ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x02D8}, /* cam_crop_window_width = 728 */ + {MISENSOR_16BIT, 0xC85A, 0x01E8}, /* cam_crop_window_height = 488 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x02D8}, /* cam_output_width = 728 */ + {MISENSOR_16BIT, 0xC86A, 0x01E8}, /* cam_output_height = 488 */ + {MISENSOR_8BIT, 0xC878, 0x00}, /* 0x0E //cam_aet_aemode = 0 */ + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_common[] = { + /* reset */ + {MISENSOR_16BIT, 0x301A, 0x0234}, + /* LOAD = Step2-PLL_Timing //PLL and Timing */ + {MISENSOR_16BIT, 0x098E, 0x1000}, /* LOGICAL_ADDRESS_ACCESS */ + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0000}, /* cam_sensor_cfg_y_addr_start = 216*/ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 168*/ + {MISENSOR_16BIT, 0xC804, 0x03CD}, /* cam_sensor_cfg_y_addr_end = 761 */ + {MISENSOR_16BIT, 0xC806, 0x050D}, /* cam_sensor_cfg_x_addr_end = 1127 */ + {MISENSOR_16BIT, 0xC808, 0x02DC}, /* cam_sensor_cfg_pixclk = 24000000 */ + {MISENSOR_16BIT, 0xC80A, 0x6C00}, + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x01C3}, + /* cam_sensor_cfg_fine_integ_time_max = 1149 */ + {MISENSOR_16BIT, 0xC810, 0x03F7}, + /* cam_sensor_cfg_frame_length_lines = 625 */ + {MISENSOR_16BIT, 0xC812, 0x0500}, + /* cam_sensor_cfg_line_length_pck = 1280 */ + {MISENSOR_16BIT, 0xC814, 0x04E2}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x00E0}, + /* cam_sensor_cfg_cpipe_last_row = 541 */ + {MISENSOR_16BIT, 0xC818, 0x01E3}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0330}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0280}, /* cam_crop_window_width = 952 */ + {MISENSOR_16BIT, 0xC85A, 0x01E0}, /* cam_crop_window_height = 538 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0280}, /* cam_output_width = 952 */ + {MISENSOR_16BIT, 0xC86A, 0x01E0}, /* cam_output_height = 538 */ + /* LOAD = Step3-Recommended + * Patch,Errata and Sensor optimization Setting */ + {MISENSOR_16BIT, 0x316A, 0x8270}, /* DAC_TXLO_ROW */ + {MISENSOR_16BIT, 0x316C, 0x8270}, /* DAC_TXLO */ + {MISENSOR_16BIT, 0x3ED0, 0x2305}, /* DAC_LD_4_5 */ + {MISENSOR_16BIT, 0x3ED2, 0x77CF}, /* DAC_LD_6_7 */ + {MISENSOR_16BIT, 0x316E, 0x8202}, /* DAC_ECL */ + {MISENSOR_16BIT, 0x3180, 0x87FF}, /* DELTA_DK_CONTROL */ + {MISENSOR_16BIT, 0x30D4, 0x6080}, /* COLUMN_CORRECTION */ + {MISENSOR_16BIT, 0xA802, 0x0008}, /* AE_TRACK_MODE */ + {MISENSOR_16BIT, 0x3E14, 0xFF39}, /* SAMP_COL_PUP2 */ + {MISENSOR_16BIT, 0x31E0, 0x0003}, /* PIX_DEF_ID */ + /* LOAD = Step8-Features //Ports, special features, etc. */ + {MISENSOR_16BIT, 0x098E, 0x0000}, /* LOGICAL_ADDRESS_ACCESS */ + {MISENSOR_16BIT, 0x001E, 0x0777}, /* PAD_SLEW */ + {MISENSOR_16BIT, 0x098E, 0x0000}, /* LOGICAL_ADDRESS_ACCESS */ + {MISENSOR_16BIT, 0xC984, 0x8001}, /* CAM_PORT_OUTPUT_CONTROL */ + {MISENSOR_16BIT, 0xC988, 0x0F00}, /* CAM_PORT_MIPI_TIMING_T_HS_ZERO */ + /* CAM_PORT_MIPI_TIMING_T_HS_EXIT_HS_TRAIL */ + {MISENSOR_16BIT, 0xC98A, 0x0B07}, + /* CAM_PORT_MIPI_TIMING_T_CLK_POST_CLK_PRE */ + {MISENSOR_16BIT, 0xC98C, 0x0D01}, + /* CAM_PORT_MIPI_TIMING_T_CLK_TRAIL_CLK_ZERO */ + {MISENSOR_16BIT, 0xC98E, 0x071D}, + {MISENSOR_16BIT, 0xC990, 0x0006}, /* CAM_PORT_MIPI_TIMING_T_LPX */ + {MISENSOR_16BIT, 0xC992, 0x0A0C}, /* CAM_PORT_MIPI_TIMING_INIT_TIMING */ + {MISENSOR_16BIT, 0x3C5A, 0x0009}, /* MIPI_DELAY_TRIM */ + {MISENSOR_16BIT, 0xC86C, 0x0210}, /* CAM_OUTPUT_FORMAT */ + {MISENSOR_16BIT, 0xA804, 0x0000}, /* AE_TRACK_ALGO */ + /* default exposure */ + {MISENSOR_16BIT, 0x3012, 0x0110}, /* COMMAND_REGISTER */ + {MISENSOR_TOK_TERM, 0, 0}, + +}; + +static struct misensor_reg const mt9m114_antiflicker_50hz[] = { + {MISENSOR_16BIT, 0x098E, 0xC88B}, + {MISENSOR_8BIT, 0xC88B, 0x32}, + {MISENSOR_8BIT, 0xDC00, 0x28}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_antiflicker_60hz[] = { + {MISENSOR_16BIT, 0x098E, 0xC88B}, + {MISENSOR_8BIT, 0xC88B, 0x3C}, + {MISENSOR_8BIT, 0xDC00, 0x28}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_iq[] = { + /* [Step3-Recommended] [Sensor optimization] */ + {MISENSOR_16BIT, 0x316A, 0x8270}, + {MISENSOR_16BIT, 0x316C, 0x8270}, + {MISENSOR_16BIT, 0x3ED0, 0x2305}, + {MISENSOR_16BIT, 0x3ED2, 0x77CF}, + {MISENSOR_16BIT, 0x316E, 0x8202}, + {MISENSOR_16BIT, 0x3180, 0x87FF}, + {MISENSOR_16BIT, 0x30D4, 0x6080}, + {MISENSOR_16BIT, 0xA802, 0x0008}, + + /* This register is from vender to avoid low light color noise */ + {MISENSOR_16BIT, 0x31E0, 0x0001}, + + /* LOAD=Errata item 1 */ + {MISENSOR_16BIT, 0x3E14, 0xFF39}, + + /* LOAD=Errata item 2 */ + {MISENSOR_16BIT, 0x301A, 0x8234}, + + /* + * LOAD=Errata item 3 + * LOAD=Patch 0202; + * Feature Recommended; Black level correction fix + */ + {MISENSOR_16BIT, 0x0982, 0x0001}, + {MISENSOR_16BIT, 0x098A, 0x5000}, + {MISENSOR_16BIT, 0xD000, 0x70CF}, + {MISENSOR_16BIT, 0xD002, 0xFFFF}, + {MISENSOR_16BIT, 0xD004, 0xC5D4}, + {MISENSOR_16BIT, 0xD006, 0x903A}, + {MISENSOR_16BIT, 0xD008, 0x2144}, + {MISENSOR_16BIT, 0xD00A, 0x0C00}, + {MISENSOR_16BIT, 0xD00C, 0x2186}, + {MISENSOR_16BIT, 0xD00E, 0x0FF3}, + {MISENSOR_16BIT, 0xD010, 0xB844}, + {MISENSOR_16BIT, 0xD012, 0xB948}, + {MISENSOR_16BIT, 0xD014, 0xE082}, + {MISENSOR_16BIT, 0xD016, 0x20CC}, + {MISENSOR_16BIT, 0xD018, 0x80E2}, + {MISENSOR_16BIT, 0xD01A, 0x21CC}, + {MISENSOR_16BIT, 0xD01C, 0x80A2}, + {MISENSOR_16BIT, 0xD01E, 0x21CC}, + {MISENSOR_16BIT, 0xD020, 0x80E2}, + {MISENSOR_16BIT, 0xD022, 0xF404}, + {MISENSOR_16BIT, 0xD024, 0xD801}, + {MISENSOR_16BIT, 0xD026, 0xF003}, + {MISENSOR_16BIT, 0xD028, 0xD800}, + {MISENSOR_16BIT, 0xD02A, 0x7EE0}, + {MISENSOR_16BIT, 0xD02C, 0xC0F1}, + {MISENSOR_16BIT, 0xD02E, 0x08BA}, + + {MISENSOR_16BIT, 0xD030, 0x0600}, + {MISENSOR_16BIT, 0xD032, 0xC1A1}, + {MISENSOR_16BIT, 0xD034, 0x76CF}, + {MISENSOR_16BIT, 0xD036, 0xFFFF}, + {MISENSOR_16BIT, 0xD038, 0xC130}, + {MISENSOR_16BIT, 0xD03A, 0x6E04}, + {MISENSOR_16BIT, 0xD03C, 0xC040}, + {MISENSOR_16BIT, 0xD03E, 0x71CF}, + {MISENSOR_16BIT, 0xD040, 0xFFFF}, + {MISENSOR_16BIT, 0xD042, 0xC790}, + {MISENSOR_16BIT, 0xD044, 0x8103}, + {MISENSOR_16BIT, 0xD046, 0x77CF}, + {MISENSOR_16BIT, 0xD048, 0xFFFF}, + {MISENSOR_16BIT, 0xD04A, 0xC7C0}, + {MISENSOR_16BIT, 0xD04C, 0xE001}, + {MISENSOR_16BIT, 0xD04E, 0xA103}, + {MISENSOR_16BIT, 0xD050, 0xD800}, + {MISENSOR_16BIT, 0xD052, 0x0C6A}, + {MISENSOR_16BIT, 0xD054, 0x04E0}, + {MISENSOR_16BIT, 0xD056, 0xB89E}, + {MISENSOR_16BIT, 0xD058, 0x7508}, + {MISENSOR_16BIT, 0xD05A, 0x8E1C}, + {MISENSOR_16BIT, 0xD05C, 0x0809}, + {MISENSOR_16BIT, 0xD05E, 0x0191}, + + {MISENSOR_16BIT, 0xD060, 0xD801}, + {MISENSOR_16BIT, 0xD062, 0xAE1D}, + {MISENSOR_16BIT, 0xD064, 0xE580}, + {MISENSOR_16BIT, 0xD066, 0x20CA}, + {MISENSOR_16BIT, 0xD068, 0x0022}, + {MISENSOR_16BIT, 0xD06A, 0x20CF}, + {MISENSOR_16BIT, 0xD06C, 0x0522}, + {MISENSOR_16BIT, 0xD06E, 0x0C5C}, + {MISENSOR_16BIT, 0xD070, 0x04E2}, + {MISENSOR_16BIT, 0xD072, 0x21CA}, + {MISENSOR_16BIT, 0xD074, 0x0062}, + {MISENSOR_16BIT, 0xD076, 0xE580}, + {MISENSOR_16BIT, 0xD078, 0xD901}, + {MISENSOR_16BIT, 0xD07A, 0x79C0}, + {MISENSOR_16BIT, 0xD07C, 0xD800}, + {MISENSOR_16BIT, 0xD07E, 0x0BE6}, + {MISENSOR_16BIT, 0xD080, 0x04E0}, + {MISENSOR_16BIT, 0xD082, 0xB89E}, + {MISENSOR_16BIT, 0xD084, 0x70CF}, + {MISENSOR_16BIT, 0xD086, 0xFFFF}, + {MISENSOR_16BIT, 0xD088, 0xC8D4}, + {MISENSOR_16BIT, 0xD08A, 0x9002}, + {MISENSOR_16BIT, 0xD08C, 0x0857}, + {MISENSOR_16BIT, 0xD08E, 0x025E}, + + {MISENSOR_16BIT, 0xD090, 0xFFDC}, + {MISENSOR_16BIT, 0xD092, 0xE080}, + {MISENSOR_16BIT, 0xD094, 0x25CC}, + {MISENSOR_16BIT, 0xD096, 0x9022}, + {MISENSOR_16BIT, 0xD098, 0xF225}, + {MISENSOR_16BIT, 0xD09A, 0x1700}, + {MISENSOR_16BIT, 0xD09C, 0x108A}, + {MISENSOR_16BIT, 0xD09E, 0x73CF}, + {MISENSOR_16BIT, 0xD0A0, 0xFF00}, + {MISENSOR_16BIT, 0xD0A2, 0x3174}, + {MISENSOR_16BIT, 0xD0A4, 0x9307}, + {MISENSOR_16BIT, 0xD0A6, 0x2A04}, + {MISENSOR_16BIT, 0xD0A8, 0x103E}, + {MISENSOR_16BIT, 0xD0AA, 0x9328}, + {MISENSOR_16BIT, 0xD0AC, 0x2942}, + {MISENSOR_16BIT, 0xD0AE, 0x7140}, + {MISENSOR_16BIT, 0xD0B0, 0x2A04}, + {MISENSOR_16BIT, 0xD0B2, 0x107E}, + {MISENSOR_16BIT, 0xD0B4, 0x9349}, + {MISENSOR_16BIT, 0xD0B6, 0x2942}, + {MISENSOR_16BIT, 0xD0B8, 0x7141}, + {MISENSOR_16BIT, 0xD0BA, 0x2A04}, + {MISENSOR_16BIT, 0xD0BC, 0x10BE}, + {MISENSOR_16BIT, 0xD0BE, 0x934A}, + + {MISENSOR_16BIT, 0xD0C0, 0x2942}, + {MISENSOR_16BIT, 0xD0C2, 0x714B}, + {MISENSOR_16BIT, 0xD0C4, 0x2A04}, + {MISENSOR_16BIT, 0xD0C6, 0x10BE}, + {MISENSOR_16BIT, 0xD0C8, 0x130C}, + {MISENSOR_16BIT, 0xD0CA, 0x010A}, + {MISENSOR_16BIT, 0xD0CC, 0x2942}, + {MISENSOR_16BIT, 0xD0CE, 0x7142}, + {MISENSOR_16BIT, 0xD0D0, 0x2250}, + {MISENSOR_16BIT, 0xD0D2, 0x13CA}, + {MISENSOR_16BIT, 0xD0D4, 0x1B0C}, + {MISENSOR_16BIT, 0xD0D6, 0x0284}, + {MISENSOR_16BIT, 0xD0D8, 0xB307}, + {MISENSOR_16BIT, 0xD0DA, 0xB328}, + {MISENSOR_16BIT, 0xD0DC, 0x1B12}, + {MISENSOR_16BIT, 0xD0DE, 0x02C4}, + {MISENSOR_16BIT, 0xD0E0, 0xB34A}, + {MISENSOR_16BIT, 0xD0E2, 0xED88}, + {MISENSOR_16BIT, 0xD0E4, 0x71CF}, + {MISENSOR_16BIT, 0xD0E6, 0xFF00}, + {MISENSOR_16BIT, 0xD0E8, 0x3174}, + {MISENSOR_16BIT, 0xD0EA, 0x9106}, + {MISENSOR_16BIT, 0xD0EC, 0xB88F}, + {MISENSOR_16BIT, 0xD0EE, 0xB106}, + + {MISENSOR_16BIT, 0xD0F0, 0x210A}, + {MISENSOR_16BIT, 0xD0F2, 0x8340}, + {MISENSOR_16BIT, 0xD0F4, 0xC000}, + {MISENSOR_16BIT, 0xD0F6, 0x21CA}, + {MISENSOR_16BIT, 0xD0F8, 0x0062}, + {MISENSOR_16BIT, 0xD0FA, 0x20F0}, + {MISENSOR_16BIT, 0xD0FC, 0x0040}, + {MISENSOR_16BIT, 0xD0FE, 0x0B02}, + {MISENSOR_16BIT, 0xD100, 0x0320}, + {MISENSOR_16BIT, 0xD102, 0xD901}, + {MISENSOR_16BIT, 0xD104, 0x07F1}, + {MISENSOR_16BIT, 0xD106, 0x05E0}, + {MISENSOR_16BIT, 0xD108, 0xC0A1}, + {MISENSOR_16BIT, 0xD10A, 0x78E0}, + {MISENSOR_16BIT, 0xD10C, 0xC0F1}, + {MISENSOR_16BIT, 0xD10E, 0x71CF}, + {MISENSOR_16BIT, 0xD110, 0xFFFF}, + {MISENSOR_16BIT, 0xD112, 0xC7C0}, + {MISENSOR_16BIT, 0xD114, 0xD840}, + {MISENSOR_16BIT, 0xD116, 0xA900}, + {MISENSOR_16BIT, 0xD118, 0x71CF}, + {MISENSOR_16BIT, 0xD11A, 0xFFFF}, + {MISENSOR_16BIT, 0xD11C, 0xD02C}, + {MISENSOR_16BIT, 0xD11E, 0xD81E}, + + {MISENSOR_16BIT, 0xD120, 0x0A5A}, + {MISENSOR_16BIT, 0xD122, 0x04E0}, + {MISENSOR_16BIT, 0xD124, 0xDA00}, + {MISENSOR_16BIT, 0xD126, 0xD800}, + {MISENSOR_16BIT, 0xD128, 0xC0D1}, + {MISENSOR_16BIT, 0xD12A, 0x7EE0}, + + {MISENSOR_16BIT, 0x098E, 0x0000}, + {MISENSOR_16BIT, 0xE000, 0x010C}, + {MISENSOR_16BIT, 0xE002, 0x0202}, + {MISENSOR_16BIT, 0xE004, 0x4103}, + {MISENSOR_16BIT, 0xE006, 0x0202}, + {MISENSOR_16BIT, 0x0080, 0xFFF0}, + {MISENSOR_16BIT, 0x0080, 0xFFF1}, + + /* LOAD=Patch 0302; Feature Recommended; Adaptive Sensitivity */ + {MISENSOR_16BIT, 0x0982, 0x0001}, + {MISENSOR_16BIT, 0x098A, 0x512C}, + {MISENSOR_16BIT, 0xD12C, 0x70CF}, + {MISENSOR_16BIT, 0xD12E, 0xFFFF}, + {MISENSOR_16BIT, 0xD130, 0xC5D4}, + {MISENSOR_16BIT, 0xD132, 0x903A}, + {MISENSOR_16BIT, 0xD134, 0x2144}, + {MISENSOR_16BIT, 0xD136, 0x0C00}, + {MISENSOR_16BIT, 0xD138, 0x2186}, + {MISENSOR_16BIT, 0xD13A, 0x0FF3}, + {MISENSOR_16BIT, 0xD13C, 0xB844}, + {MISENSOR_16BIT, 0xD13E, 0x262F}, + {MISENSOR_16BIT, 0xD140, 0xF008}, + {MISENSOR_16BIT, 0xD142, 0xB948}, + {MISENSOR_16BIT, 0xD144, 0x21CC}, + {MISENSOR_16BIT, 0xD146, 0x8021}, + {MISENSOR_16BIT, 0xD148, 0xD801}, + {MISENSOR_16BIT, 0xD14A, 0xF203}, + {MISENSOR_16BIT, 0xD14C, 0xD800}, + {MISENSOR_16BIT, 0xD14E, 0x7EE0}, + {MISENSOR_16BIT, 0xD150, 0xC0F1}, + {MISENSOR_16BIT, 0xD152, 0x71CF}, + {MISENSOR_16BIT, 0xD154, 0xFFFF}, + {MISENSOR_16BIT, 0xD156, 0xC610}, + {MISENSOR_16BIT, 0xD158, 0x910E}, + {MISENSOR_16BIT, 0xD15A, 0x208C}, + {MISENSOR_16BIT, 0xD15C, 0x8014}, + {MISENSOR_16BIT, 0xD15E, 0xF418}, + {MISENSOR_16BIT, 0xD160, 0x910F}, + {MISENSOR_16BIT, 0xD162, 0x208C}, + {MISENSOR_16BIT, 0xD164, 0x800F}, + {MISENSOR_16BIT, 0xD166, 0xF414}, + {MISENSOR_16BIT, 0xD168, 0x9116}, + {MISENSOR_16BIT, 0xD16A, 0x208C}, + {MISENSOR_16BIT, 0xD16C, 0x800A}, + {MISENSOR_16BIT, 0xD16E, 0xF410}, + {MISENSOR_16BIT, 0xD170, 0x9117}, + {MISENSOR_16BIT, 0xD172, 0x208C}, + {MISENSOR_16BIT, 0xD174, 0x8807}, + {MISENSOR_16BIT, 0xD176, 0xF40C}, + {MISENSOR_16BIT, 0xD178, 0x9118}, + {MISENSOR_16BIT, 0xD17A, 0x2086}, + {MISENSOR_16BIT, 0xD17C, 0x0FF3}, + {MISENSOR_16BIT, 0xD17E, 0xB848}, + {MISENSOR_16BIT, 0xD180, 0x080D}, + {MISENSOR_16BIT, 0xD182, 0x0090}, + {MISENSOR_16BIT, 0xD184, 0xFFEA}, + {MISENSOR_16BIT, 0xD186, 0xE081}, + {MISENSOR_16BIT, 0xD188, 0xD801}, + {MISENSOR_16BIT, 0xD18A, 0xF203}, + {MISENSOR_16BIT, 0xD18C, 0xD800}, + {MISENSOR_16BIT, 0xD18E, 0xC0D1}, + {MISENSOR_16BIT, 0xD190, 0x7EE0}, + {MISENSOR_16BIT, 0xD192, 0x78E0}, + {MISENSOR_16BIT, 0xD194, 0xC0F1}, + {MISENSOR_16BIT, 0xD196, 0x71CF}, + {MISENSOR_16BIT, 0xD198, 0xFFFF}, + {MISENSOR_16BIT, 0xD19A, 0xC610}, + {MISENSOR_16BIT, 0xD19C, 0x910E}, + {MISENSOR_16BIT, 0xD19E, 0x208C}, + {MISENSOR_16BIT, 0xD1A0, 0x800A}, + {MISENSOR_16BIT, 0xD1A2, 0xF418}, + {MISENSOR_16BIT, 0xD1A4, 0x910F}, + {MISENSOR_16BIT, 0xD1A6, 0x208C}, + {MISENSOR_16BIT, 0xD1A8, 0x8807}, + {MISENSOR_16BIT, 0xD1AA, 0xF414}, + {MISENSOR_16BIT, 0xD1AC, 0x9116}, + {MISENSOR_16BIT, 0xD1AE, 0x208C}, + {MISENSOR_16BIT, 0xD1B0, 0x800A}, + {MISENSOR_16BIT, 0xD1B2, 0xF410}, + {MISENSOR_16BIT, 0xD1B4, 0x9117}, + {MISENSOR_16BIT, 0xD1B6, 0x208C}, + {MISENSOR_16BIT, 0xD1B8, 0x8807}, + {MISENSOR_16BIT, 0xD1BA, 0xF40C}, + {MISENSOR_16BIT, 0xD1BC, 0x9118}, + {MISENSOR_16BIT, 0xD1BE, 0x2086}, + {MISENSOR_16BIT, 0xD1C0, 0x0FF3}, + {MISENSOR_16BIT, 0xD1C2, 0xB848}, + {MISENSOR_16BIT, 0xD1C4, 0x080D}, + {MISENSOR_16BIT, 0xD1C6, 0x0090}, + {MISENSOR_16BIT, 0xD1C8, 0xFFD9}, + {MISENSOR_16BIT, 0xD1CA, 0xE080}, + {MISENSOR_16BIT, 0xD1CC, 0xD801}, + {MISENSOR_16BIT, 0xD1CE, 0xF203}, + {MISENSOR_16BIT, 0xD1D0, 0xD800}, + {MISENSOR_16BIT, 0xD1D2, 0xF1DF}, + {MISENSOR_16BIT, 0xD1D4, 0x9040}, + {MISENSOR_16BIT, 0xD1D6, 0x71CF}, + {MISENSOR_16BIT, 0xD1D8, 0xFFFF}, + {MISENSOR_16BIT, 0xD1DA, 0xC5D4}, + {MISENSOR_16BIT, 0xD1DC, 0xB15A}, + {MISENSOR_16BIT, 0xD1DE, 0x9041}, + {MISENSOR_16BIT, 0xD1E0, 0x73CF}, + {MISENSOR_16BIT, 0xD1E2, 0xFFFF}, + {MISENSOR_16BIT, 0xD1E4, 0xC7D0}, + {MISENSOR_16BIT, 0xD1E6, 0xB140}, + {MISENSOR_16BIT, 0xD1E8, 0x9042}, + {MISENSOR_16BIT, 0xD1EA, 0xB141}, + {MISENSOR_16BIT, 0xD1EC, 0x9043}, + {MISENSOR_16BIT, 0xD1EE, 0xB142}, + {MISENSOR_16BIT, 0xD1F0, 0x9044}, + {MISENSOR_16BIT, 0xD1F2, 0xB143}, + {MISENSOR_16BIT, 0xD1F4, 0x9045}, + {MISENSOR_16BIT, 0xD1F6, 0xB147}, + {MISENSOR_16BIT, 0xD1F8, 0x9046}, + {MISENSOR_16BIT, 0xD1FA, 0xB148}, + {MISENSOR_16BIT, 0xD1FC, 0x9047}, + {MISENSOR_16BIT, 0xD1FE, 0xB14B}, + {MISENSOR_16BIT, 0xD200, 0x9048}, + {MISENSOR_16BIT, 0xD202, 0xB14C}, + {MISENSOR_16BIT, 0xD204, 0x9049}, + {MISENSOR_16BIT, 0xD206, 0x1958}, + {MISENSOR_16BIT, 0xD208, 0x0084}, + {MISENSOR_16BIT, 0xD20A, 0x904A}, + {MISENSOR_16BIT, 0xD20C, 0x195A}, + {MISENSOR_16BIT, 0xD20E, 0x0084}, + {MISENSOR_16BIT, 0xD210, 0x8856}, + {MISENSOR_16BIT, 0xD212, 0x1B36}, + {MISENSOR_16BIT, 0xD214, 0x8082}, + {MISENSOR_16BIT, 0xD216, 0x8857}, + {MISENSOR_16BIT, 0xD218, 0x1B37}, + {MISENSOR_16BIT, 0xD21A, 0x8082}, + {MISENSOR_16BIT, 0xD21C, 0x904C}, + {MISENSOR_16BIT, 0xD21E, 0x19A7}, + {MISENSOR_16BIT, 0xD220, 0x009C}, + {MISENSOR_16BIT, 0xD222, 0x881A}, + {MISENSOR_16BIT, 0xD224, 0x7FE0}, + {MISENSOR_16BIT, 0xD226, 0x1B54}, + {MISENSOR_16BIT, 0xD228, 0x8002}, + {MISENSOR_16BIT, 0xD22A, 0x78E0}, + {MISENSOR_16BIT, 0xD22C, 0x71CF}, + {MISENSOR_16BIT, 0xD22E, 0xFFFF}, + {MISENSOR_16BIT, 0xD230, 0xC350}, + {MISENSOR_16BIT, 0xD232, 0xD828}, + {MISENSOR_16BIT, 0xD234, 0xA90B}, + {MISENSOR_16BIT, 0xD236, 0x8100}, + {MISENSOR_16BIT, 0xD238, 0x01C5}, + {MISENSOR_16BIT, 0xD23A, 0x0320}, + {MISENSOR_16BIT, 0xD23C, 0xD900}, + {MISENSOR_16BIT, 0xD23E, 0x78E0}, + {MISENSOR_16BIT, 0xD240, 0x220A}, + {MISENSOR_16BIT, 0xD242, 0x1F80}, + {MISENSOR_16BIT, 0xD244, 0xFFFF}, + {MISENSOR_16BIT, 0xD246, 0xD4E0}, + {MISENSOR_16BIT, 0xD248, 0xC0F1}, + {MISENSOR_16BIT, 0xD24A, 0x0811}, + {MISENSOR_16BIT, 0xD24C, 0x0051}, + {MISENSOR_16BIT, 0xD24E, 0x2240}, + {MISENSOR_16BIT, 0xD250, 0x1200}, + {MISENSOR_16BIT, 0xD252, 0xFFE1}, + {MISENSOR_16BIT, 0xD254, 0xD801}, + {MISENSOR_16BIT, 0xD256, 0xF006}, + {MISENSOR_16BIT, 0xD258, 0x2240}, + {MISENSOR_16BIT, 0xD25A, 0x1900}, + {MISENSOR_16BIT, 0xD25C, 0xFFDE}, + {MISENSOR_16BIT, 0xD25E, 0xD802}, + {MISENSOR_16BIT, 0xD260, 0x1A05}, + {MISENSOR_16BIT, 0xD262, 0x1002}, + {MISENSOR_16BIT, 0xD264, 0xFFF2}, + {MISENSOR_16BIT, 0xD266, 0xF195}, + {MISENSOR_16BIT, 0xD268, 0xC0F1}, + {MISENSOR_16BIT, 0xD26A, 0x0E7E}, + {MISENSOR_16BIT, 0xD26C, 0x05C0}, + {MISENSOR_16BIT, 0xD26E, 0x75CF}, + {MISENSOR_16BIT, 0xD270, 0xFFFF}, + {MISENSOR_16BIT, 0xD272, 0xC84C}, + {MISENSOR_16BIT, 0xD274, 0x9502}, + {MISENSOR_16BIT, 0xD276, 0x77CF}, + {MISENSOR_16BIT, 0xD278, 0xFFFF}, + {MISENSOR_16BIT, 0xD27A, 0xC344}, + {MISENSOR_16BIT, 0xD27C, 0x2044}, + {MISENSOR_16BIT, 0xD27E, 0x008E}, + {MISENSOR_16BIT, 0xD280, 0xB8A1}, + {MISENSOR_16BIT, 0xD282, 0x0926}, + {MISENSOR_16BIT, 0xD284, 0x03E0}, + {MISENSOR_16BIT, 0xD286, 0xB502}, + {MISENSOR_16BIT, 0xD288, 0x9502}, + {MISENSOR_16BIT, 0xD28A, 0x952E}, + {MISENSOR_16BIT, 0xD28C, 0x7E05}, + {MISENSOR_16BIT, 0xD28E, 0xB5C2}, + {MISENSOR_16BIT, 0xD290, 0x70CF}, + {MISENSOR_16BIT, 0xD292, 0xFFFF}, + {MISENSOR_16BIT, 0xD294, 0xC610}, + {MISENSOR_16BIT, 0xD296, 0x099A}, + {MISENSOR_16BIT, 0xD298, 0x04A0}, + {MISENSOR_16BIT, 0xD29A, 0xB026}, + {MISENSOR_16BIT, 0xD29C, 0x0E02}, + {MISENSOR_16BIT, 0xD29E, 0x0560}, + {MISENSOR_16BIT, 0xD2A0, 0xDE00}, + {MISENSOR_16BIT, 0xD2A2, 0x0A12}, + {MISENSOR_16BIT, 0xD2A4, 0x0320}, + {MISENSOR_16BIT, 0xD2A6, 0xB7C4}, + {MISENSOR_16BIT, 0xD2A8, 0x0B36}, + {MISENSOR_16BIT, 0xD2AA, 0x03A0}, + {MISENSOR_16BIT, 0xD2AC, 0x70C9}, + {MISENSOR_16BIT, 0xD2AE, 0x9502}, + {MISENSOR_16BIT, 0xD2B0, 0x7608}, + {MISENSOR_16BIT, 0xD2B2, 0xB8A8}, + {MISENSOR_16BIT, 0xD2B4, 0xB502}, + {MISENSOR_16BIT, 0xD2B6, 0x70CF}, + {MISENSOR_16BIT, 0xD2B8, 0x0000}, + {MISENSOR_16BIT, 0xD2BA, 0x5536}, + {MISENSOR_16BIT, 0xD2BC, 0x7860}, + {MISENSOR_16BIT, 0xD2BE, 0x2686}, + {MISENSOR_16BIT, 0xD2C0, 0x1FFB}, + {MISENSOR_16BIT, 0xD2C2, 0x9502}, + {MISENSOR_16BIT, 0xD2C4, 0x78C5}, + {MISENSOR_16BIT, 0xD2C6, 0x0631}, + {MISENSOR_16BIT, 0xD2C8, 0x05E0}, + {MISENSOR_16BIT, 0xD2CA, 0xB502}, + {MISENSOR_16BIT, 0xD2CC, 0x72CF}, + {MISENSOR_16BIT, 0xD2CE, 0xFFFF}, + {MISENSOR_16BIT, 0xD2D0, 0xC5D4}, + {MISENSOR_16BIT, 0xD2D2, 0x923A}, + {MISENSOR_16BIT, 0xD2D4, 0x73CF}, + {MISENSOR_16BIT, 0xD2D6, 0xFFFF}, + {MISENSOR_16BIT, 0xD2D8, 0xC7D0}, + {MISENSOR_16BIT, 0xD2DA, 0xB020}, + {MISENSOR_16BIT, 0xD2DC, 0x9220}, + {MISENSOR_16BIT, 0xD2DE, 0xB021}, + {MISENSOR_16BIT, 0xD2E0, 0x9221}, + {MISENSOR_16BIT, 0xD2E2, 0xB022}, + {MISENSOR_16BIT, 0xD2E4, 0x9222}, + {MISENSOR_16BIT, 0xD2E6, 0xB023}, + {MISENSOR_16BIT, 0xD2E8, 0x9223}, + {MISENSOR_16BIT, 0xD2EA, 0xB024}, + {MISENSOR_16BIT, 0xD2EC, 0x9227}, + {MISENSOR_16BIT, 0xD2EE, 0xB025}, + {MISENSOR_16BIT, 0xD2F0, 0x9228}, + {MISENSOR_16BIT, 0xD2F2, 0xB026}, + {MISENSOR_16BIT, 0xD2F4, 0x922B}, + {MISENSOR_16BIT, 0xD2F6, 0xB027}, + {MISENSOR_16BIT, 0xD2F8, 0x922C}, + {MISENSOR_16BIT, 0xD2FA, 0xB028}, + {MISENSOR_16BIT, 0xD2FC, 0x1258}, + {MISENSOR_16BIT, 0xD2FE, 0x0101}, + {MISENSOR_16BIT, 0xD300, 0xB029}, + {MISENSOR_16BIT, 0xD302, 0x125A}, + {MISENSOR_16BIT, 0xD304, 0x0101}, + {MISENSOR_16BIT, 0xD306, 0xB02A}, + {MISENSOR_16BIT, 0xD308, 0x1336}, + {MISENSOR_16BIT, 0xD30A, 0x8081}, + {MISENSOR_16BIT, 0xD30C, 0xA836}, + {MISENSOR_16BIT, 0xD30E, 0x1337}, + {MISENSOR_16BIT, 0xD310, 0x8081}, + {MISENSOR_16BIT, 0xD312, 0xA837}, + {MISENSOR_16BIT, 0xD314, 0x12A7}, + {MISENSOR_16BIT, 0xD316, 0x0701}, + {MISENSOR_16BIT, 0xD318, 0xB02C}, + {MISENSOR_16BIT, 0xD31A, 0x1354}, + {MISENSOR_16BIT, 0xD31C, 0x8081}, + {MISENSOR_16BIT, 0xD31E, 0x7FE0}, + {MISENSOR_16BIT, 0xD320, 0xA83A}, + {MISENSOR_16BIT, 0xD322, 0x78E0}, + {MISENSOR_16BIT, 0xD324, 0xC0F1}, + {MISENSOR_16BIT, 0xD326, 0x0DC2}, + {MISENSOR_16BIT, 0xD328, 0x05C0}, + {MISENSOR_16BIT, 0xD32A, 0x7608}, + {MISENSOR_16BIT, 0xD32C, 0x09BB}, + {MISENSOR_16BIT, 0xD32E, 0x0010}, + {MISENSOR_16BIT, 0xD330, 0x75CF}, + {MISENSOR_16BIT, 0xD332, 0xFFFF}, + {MISENSOR_16BIT, 0xD334, 0xD4E0}, + {MISENSOR_16BIT, 0xD336, 0x8D21}, + {MISENSOR_16BIT, 0xD338, 0x8D00}, + {MISENSOR_16BIT, 0xD33A, 0x2153}, + {MISENSOR_16BIT, 0xD33C, 0x0003}, + {MISENSOR_16BIT, 0xD33E, 0xB8C0}, + {MISENSOR_16BIT, 0xD340, 0x8D45}, + {MISENSOR_16BIT, 0xD342, 0x0B23}, + {MISENSOR_16BIT, 0xD344, 0x0000}, + {MISENSOR_16BIT, 0xD346, 0xEA8F}, + {MISENSOR_16BIT, 0xD348, 0x0915}, + {MISENSOR_16BIT, 0xD34A, 0x001E}, + {MISENSOR_16BIT, 0xD34C, 0xFF81}, + {MISENSOR_16BIT, 0xD34E, 0xE808}, + {MISENSOR_16BIT, 0xD350, 0x2540}, + {MISENSOR_16BIT, 0xD352, 0x1900}, + {MISENSOR_16BIT, 0xD354, 0xFFDE}, + {MISENSOR_16BIT, 0xD356, 0x8D00}, + {MISENSOR_16BIT, 0xD358, 0xB880}, + {MISENSOR_16BIT, 0xD35A, 0xF004}, + {MISENSOR_16BIT, 0xD35C, 0x8D00}, + {MISENSOR_16BIT, 0xD35E, 0xB8A0}, + {MISENSOR_16BIT, 0xD360, 0xAD00}, + {MISENSOR_16BIT, 0xD362, 0x8D05}, + {MISENSOR_16BIT, 0xD364, 0xE081}, + {MISENSOR_16BIT, 0xD366, 0x20CC}, + {MISENSOR_16BIT, 0xD368, 0x80A2}, + {MISENSOR_16BIT, 0xD36A, 0xDF00}, + {MISENSOR_16BIT, 0xD36C, 0xF40A}, + {MISENSOR_16BIT, 0xD36E, 0x71CF}, + {MISENSOR_16BIT, 0xD370, 0xFFFF}, + {MISENSOR_16BIT, 0xD372, 0xC84C}, + {MISENSOR_16BIT, 0xD374, 0x9102}, + {MISENSOR_16BIT, 0xD376, 0x7708}, + {MISENSOR_16BIT, 0xD378, 0xB8A6}, + {MISENSOR_16BIT, 0xD37A, 0x2786}, + {MISENSOR_16BIT, 0xD37C, 0x1FFE}, + {MISENSOR_16BIT, 0xD37E, 0xB102}, + {MISENSOR_16BIT, 0xD380, 0x0B42}, + {MISENSOR_16BIT, 0xD382, 0x0180}, + {MISENSOR_16BIT, 0xD384, 0x0E3E}, + {MISENSOR_16BIT, 0xD386, 0x0180}, + {MISENSOR_16BIT, 0xD388, 0x0F4A}, + {MISENSOR_16BIT, 0xD38A, 0x0160}, + {MISENSOR_16BIT, 0xD38C, 0x70C9}, + {MISENSOR_16BIT, 0xD38E, 0x8D05}, + {MISENSOR_16BIT, 0xD390, 0xE081}, + {MISENSOR_16BIT, 0xD392, 0x20CC}, + {MISENSOR_16BIT, 0xD394, 0x80A2}, + {MISENSOR_16BIT, 0xD396, 0xF429}, + {MISENSOR_16BIT, 0xD398, 0x76CF}, + {MISENSOR_16BIT, 0xD39A, 0xFFFF}, + {MISENSOR_16BIT, 0xD39C, 0xC84C}, + {MISENSOR_16BIT, 0xD39E, 0x082D}, + {MISENSOR_16BIT, 0xD3A0, 0x0051}, + {MISENSOR_16BIT, 0xD3A2, 0x70CF}, + {MISENSOR_16BIT, 0xD3A4, 0xFFFF}, + {MISENSOR_16BIT, 0xD3A6, 0xC90C}, + {MISENSOR_16BIT, 0xD3A8, 0x8805}, + {MISENSOR_16BIT, 0xD3AA, 0x09B6}, + {MISENSOR_16BIT, 0xD3AC, 0x0360}, + {MISENSOR_16BIT, 0xD3AE, 0xD908}, + {MISENSOR_16BIT, 0xD3B0, 0x2099}, + {MISENSOR_16BIT, 0xD3B2, 0x0802}, + {MISENSOR_16BIT, 0xD3B4, 0x9634}, + {MISENSOR_16BIT, 0xD3B6, 0xB503}, + {MISENSOR_16BIT, 0xD3B8, 0x7902}, + {MISENSOR_16BIT, 0xD3BA, 0x1523}, + {MISENSOR_16BIT, 0xD3BC, 0x1080}, + {MISENSOR_16BIT, 0xD3BE, 0xB634}, + {MISENSOR_16BIT, 0xD3C0, 0xE001}, + {MISENSOR_16BIT, 0xD3C2, 0x1D23}, + {MISENSOR_16BIT, 0xD3C4, 0x1002}, + {MISENSOR_16BIT, 0xD3C6, 0xF00B}, + {MISENSOR_16BIT, 0xD3C8, 0x9634}, + {MISENSOR_16BIT, 0xD3CA, 0x9503}, + {MISENSOR_16BIT, 0xD3CC, 0x6038}, + {MISENSOR_16BIT, 0xD3CE, 0xB614}, + {MISENSOR_16BIT, 0xD3D0, 0x153F}, + {MISENSOR_16BIT, 0xD3D2, 0x1080}, + {MISENSOR_16BIT, 0xD3D4, 0xE001}, + {MISENSOR_16BIT, 0xD3D6, 0x1D3F}, + {MISENSOR_16BIT, 0xD3D8, 0x1002}, + {MISENSOR_16BIT, 0xD3DA, 0xFFA4}, + {MISENSOR_16BIT, 0xD3DC, 0x9602}, + {MISENSOR_16BIT, 0xD3DE, 0x7F05}, + {MISENSOR_16BIT, 0xD3E0, 0xD800}, + {MISENSOR_16BIT, 0xD3E2, 0xB6E2}, + {MISENSOR_16BIT, 0xD3E4, 0xAD05}, + {MISENSOR_16BIT, 0xD3E6, 0x0511}, + {MISENSOR_16BIT, 0xD3E8, 0x05E0}, + {MISENSOR_16BIT, 0xD3EA, 0xD800}, + {MISENSOR_16BIT, 0xD3EC, 0xC0F1}, + {MISENSOR_16BIT, 0xD3EE, 0x0CFE}, + {MISENSOR_16BIT, 0xD3F0, 0x05C0}, + {MISENSOR_16BIT, 0xD3F2, 0x0A96}, + {MISENSOR_16BIT, 0xD3F4, 0x05A0}, + {MISENSOR_16BIT, 0xD3F6, 0x7608}, + {MISENSOR_16BIT, 0xD3F8, 0x0C22}, + {MISENSOR_16BIT, 0xD3FA, 0x0240}, + {MISENSOR_16BIT, 0xD3FC, 0xE080}, + {MISENSOR_16BIT, 0xD3FE, 0x20CA}, + {MISENSOR_16BIT, 0xD400, 0x0F82}, + {MISENSOR_16BIT, 0xD402, 0x0000}, + {MISENSOR_16BIT, 0xD404, 0x190B}, + {MISENSOR_16BIT, 0xD406, 0x0C60}, + {MISENSOR_16BIT, 0xD408, 0x05A2}, + {MISENSOR_16BIT, 0xD40A, 0x21CA}, + {MISENSOR_16BIT, 0xD40C, 0x0022}, + {MISENSOR_16BIT, 0xD40E, 0x0C56}, + {MISENSOR_16BIT, 0xD410, 0x0240}, + {MISENSOR_16BIT, 0xD412, 0xE806}, + {MISENSOR_16BIT, 0xD414, 0x0E0E}, + {MISENSOR_16BIT, 0xD416, 0x0220}, + {MISENSOR_16BIT, 0xD418, 0x70C9}, + {MISENSOR_16BIT, 0xD41A, 0xF048}, + {MISENSOR_16BIT, 0xD41C, 0x0896}, + {MISENSOR_16BIT, 0xD41E, 0x0440}, + {MISENSOR_16BIT, 0xD420, 0x0E96}, + {MISENSOR_16BIT, 0xD422, 0x0400}, + {MISENSOR_16BIT, 0xD424, 0x0966}, + {MISENSOR_16BIT, 0xD426, 0x0380}, + {MISENSOR_16BIT, 0xD428, 0x75CF}, + {MISENSOR_16BIT, 0xD42A, 0xFFFF}, + {MISENSOR_16BIT, 0xD42C, 0xD4E0}, + {MISENSOR_16BIT, 0xD42E, 0x8D00}, + {MISENSOR_16BIT, 0xD430, 0x084D}, + {MISENSOR_16BIT, 0xD432, 0x001E}, + {MISENSOR_16BIT, 0xD434, 0xFF47}, + {MISENSOR_16BIT, 0xD436, 0x080D}, + {MISENSOR_16BIT, 0xD438, 0x0050}, + {MISENSOR_16BIT, 0xD43A, 0xFF57}, + {MISENSOR_16BIT, 0xD43C, 0x0841}, + {MISENSOR_16BIT, 0xD43E, 0x0051}, + {MISENSOR_16BIT, 0xD440, 0x8D04}, + {MISENSOR_16BIT, 0xD442, 0x9521}, + {MISENSOR_16BIT, 0xD444, 0xE064}, + {MISENSOR_16BIT, 0xD446, 0x790C}, + {MISENSOR_16BIT, 0xD448, 0x702F}, + {MISENSOR_16BIT, 0xD44A, 0x0CE2}, + {MISENSOR_16BIT, 0xD44C, 0x05E0}, + {MISENSOR_16BIT, 0xD44E, 0xD964}, + {MISENSOR_16BIT, 0xD450, 0x72CF}, + {MISENSOR_16BIT, 0xD452, 0xFFFF}, + {MISENSOR_16BIT, 0xD454, 0xC700}, + {MISENSOR_16BIT, 0xD456, 0x9235}, + {MISENSOR_16BIT, 0xD458, 0x0811}, + {MISENSOR_16BIT, 0xD45A, 0x0043}, + {MISENSOR_16BIT, 0xD45C, 0xFF3D}, + {MISENSOR_16BIT, 0xD45E, 0x080D}, + {MISENSOR_16BIT, 0xD460, 0x0051}, + {MISENSOR_16BIT, 0xD462, 0xD801}, + {MISENSOR_16BIT, 0xD464, 0xFF77}, + {MISENSOR_16BIT, 0xD466, 0xF025}, + {MISENSOR_16BIT, 0xD468, 0x9501}, + {MISENSOR_16BIT, 0xD46A, 0x9235}, + {MISENSOR_16BIT, 0xD46C, 0x0911}, + {MISENSOR_16BIT, 0xD46E, 0x0003}, + {MISENSOR_16BIT, 0xD470, 0xFF49}, + {MISENSOR_16BIT, 0xD472, 0x080D}, + {MISENSOR_16BIT, 0xD474, 0x0051}, + {MISENSOR_16BIT, 0xD476, 0xD800}, + {MISENSOR_16BIT, 0xD478, 0xFF72}, + {MISENSOR_16BIT, 0xD47A, 0xF01B}, + {MISENSOR_16BIT, 0xD47C, 0x0886}, + {MISENSOR_16BIT, 0xD47E, 0x03E0}, + {MISENSOR_16BIT, 0xD480, 0xD801}, + {MISENSOR_16BIT, 0xD482, 0x0EF6}, + {MISENSOR_16BIT, 0xD484, 0x03C0}, + {MISENSOR_16BIT, 0xD486, 0x0F52}, + {MISENSOR_16BIT, 0xD488, 0x0340}, + {MISENSOR_16BIT, 0xD48A, 0x0DBA}, + {MISENSOR_16BIT, 0xD48C, 0x0200}, + {MISENSOR_16BIT, 0xD48E, 0x0AF6}, + {MISENSOR_16BIT, 0xD490, 0x0440}, + {MISENSOR_16BIT, 0xD492, 0x0C22}, + {MISENSOR_16BIT, 0xD494, 0x0400}, + {MISENSOR_16BIT, 0xD496, 0x0D72}, + {MISENSOR_16BIT, 0xD498, 0x0440}, + {MISENSOR_16BIT, 0xD49A, 0x0DC2}, + {MISENSOR_16BIT, 0xD49C, 0x0200}, + {MISENSOR_16BIT, 0xD49E, 0x0972}, + {MISENSOR_16BIT, 0xD4A0, 0x0440}, + {MISENSOR_16BIT, 0xD4A2, 0x0D3A}, + {MISENSOR_16BIT, 0xD4A4, 0x0220}, + {MISENSOR_16BIT, 0xD4A6, 0xD820}, + {MISENSOR_16BIT, 0xD4A8, 0x0BFA}, + {MISENSOR_16BIT, 0xD4AA, 0x0260}, + {MISENSOR_16BIT, 0xD4AC, 0x70C9}, + {MISENSOR_16BIT, 0xD4AE, 0x0451}, + {MISENSOR_16BIT, 0xD4B0, 0x05C0}, + {MISENSOR_16BIT, 0xD4B2, 0x78E0}, + {MISENSOR_16BIT, 0xD4B4, 0xD900}, + {MISENSOR_16BIT, 0xD4B6, 0xF00A}, + {MISENSOR_16BIT, 0xD4B8, 0x70CF}, + {MISENSOR_16BIT, 0xD4BA, 0xFFFF}, + {MISENSOR_16BIT, 0xD4BC, 0xD520}, + {MISENSOR_16BIT, 0xD4BE, 0x7835}, + {MISENSOR_16BIT, 0xD4C0, 0x8041}, + {MISENSOR_16BIT, 0xD4C2, 0x8000}, + {MISENSOR_16BIT, 0xD4C4, 0xE102}, + {MISENSOR_16BIT, 0xD4C6, 0xA040}, + {MISENSOR_16BIT, 0xD4C8, 0x09F1}, + {MISENSOR_16BIT, 0xD4CA, 0x8114}, + {MISENSOR_16BIT, 0xD4CC, 0x71CF}, + {MISENSOR_16BIT, 0xD4CE, 0xFFFF}, + {MISENSOR_16BIT, 0xD4D0, 0xD4E0}, + {MISENSOR_16BIT, 0xD4D2, 0x70CF}, + {MISENSOR_16BIT, 0xD4D4, 0xFFFF}, + {MISENSOR_16BIT, 0xD4D6, 0xC594}, + {MISENSOR_16BIT, 0xD4D8, 0xB03A}, + {MISENSOR_16BIT, 0xD4DA, 0x7FE0}, + {MISENSOR_16BIT, 0xD4DC, 0xD800}, + {MISENSOR_16BIT, 0xD4DE, 0x0000}, + {MISENSOR_16BIT, 0xD4E0, 0x0000}, + {MISENSOR_16BIT, 0xD4E2, 0x0500}, + {MISENSOR_16BIT, 0xD4E4, 0x0500}, + {MISENSOR_16BIT, 0xD4E6, 0x0200}, + {MISENSOR_16BIT, 0xD4E8, 0x0330}, + {MISENSOR_16BIT, 0xD4EA, 0x0000}, + {MISENSOR_16BIT, 0xD4EC, 0x0000}, + {MISENSOR_16BIT, 0xD4EE, 0x03CD}, + {MISENSOR_16BIT, 0xD4F0, 0x050D}, + {MISENSOR_16BIT, 0xD4F2, 0x01C5}, + {MISENSOR_16BIT, 0xD4F4, 0x03B3}, + {MISENSOR_16BIT, 0xD4F6, 0x00E0}, + {MISENSOR_16BIT, 0xD4F8, 0x01E3}, + {MISENSOR_16BIT, 0xD4FA, 0x0280}, + {MISENSOR_16BIT, 0xD4FC, 0x01E0}, + {MISENSOR_16BIT, 0xD4FE, 0x0109}, + {MISENSOR_16BIT, 0xD500, 0x0080}, + {MISENSOR_16BIT, 0xD502, 0x0500}, + {MISENSOR_16BIT, 0xD504, 0x0000}, + {MISENSOR_16BIT, 0xD506, 0x0000}, + {MISENSOR_16BIT, 0xD508, 0x0000}, + {MISENSOR_16BIT, 0xD50A, 0x0000}, + {MISENSOR_16BIT, 0xD50C, 0x0000}, + {MISENSOR_16BIT, 0xD50E, 0x0000}, + {MISENSOR_16BIT, 0xD510, 0x0000}, + {MISENSOR_16BIT, 0xD512, 0x0000}, + {MISENSOR_16BIT, 0xD514, 0x0000}, + {MISENSOR_16BIT, 0xD516, 0x0000}, + {MISENSOR_16BIT, 0xD518, 0x0000}, + {MISENSOR_16BIT, 0xD51A, 0x0000}, + {MISENSOR_16BIT, 0xD51C, 0x0000}, + {MISENSOR_16BIT, 0xD51E, 0x0000}, + {MISENSOR_16BIT, 0xD520, 0xFFFF}, + {MISENSOR_16BIT, 0xD522, 0xC9B4}, + {MISENSOR_16BIT, 0xD524, 0xFFFF}, + {MISENSOR_16BIT, 0xD526, 0xD324}, + {MISENSOR_16BIT, 0xD528, 0xFFFF}, + {MISENSOR_16BIT, 0xD52A, 0xCA34}, + {MISENSOR_16BIT, 0xD52C, 0xFFFF}, + {MISENSOR_16BIT, 0xD52E, 0xD3EC}, + {MISENSOR_16BIT, 0x098E, 0x0000}, + {MISENSOR_16BIT, 0xE000, 0x04B4}, + {MISENSOR_16BIT, 0xE002, 0x0302}, + {MISENSOR_16BIT, 0xE004, 0x4103}, + {MISENSOR_16BIT, 0xE006, 0x0202}, + {MISENSOR_16BIT, 0x0080, 0xFFF0}, + {MISENSOR_16BIT, 0x0080, 0xFFF1}, + + /* PGA parameter and APGA + * [Step4-APGA] [TP101_MT9M114_APGA] + */ + {MISENSOR_16BIT, 0x098E, 0x495E}, + {MISENSOR_16BIT, 0xC95E, 0x0000}, + {MISENSOR_16BIT, 0x3640, 0x02B0}, + {MISENSOR_16BIT, 0x3642, 0x8063}, + {MISENSOR_16BIT, 0x3644, 0x78D0}, + {MISENSOR_16BIT, 0x3646, 0x50CC}, + {MISENSOR_16BIT, 0x3648, 0x3511}, + {MISENSOR_16BIT, 0x364A, 0x0110}, + {MISENSOR_16BIT, 0x364C, 0xBD8A}, + {MISENSOR_16BIT, 0x364E, 0x0CD1}, + {MISENSOR_16BIT, 0x3650, 0x24ED}, + {MISENSOR_16BIT, 0x3652, 0x7C11}, + {MISENSOR_16BIT, 0x3654, 0x0150}, + {MISENSOR_16BIT, 0x3656, 0x124C}, + {MISENSOR_16BIT, 0x3658, 0x3130}, + {MISENSOR_16BIT, 0x365A, 0x508C}, + {MISENSOR_16BIT, 0x365C, 0x21F1}, + {MISENSOR_16BIT, 0x365E, 0x0090}, + {MISENSOR_16BIT, 0x3660, 0xBFCA}, + {MISENSOR_16BIT, 0x3662, 0x0A11}, + {MISENSOR_16BIT, 0x3664, 0x4F4B}, + {MISENSOR_16BIT, 0x3666, 0x28B1}, + {MISENSOR_16BIT, 0x3680, 0x50A9}, + {MISENSOR_16BIT, 0x3682, 0xA04B}, + {MISENSOR_16BIT, 0x3684, 0x0E2D}, + {MISENSOR_16BIT, 0x3686, 0x73EC}, + {MISENSOR_16BIT, 0x3688, 0x164F}, + {MISENSOR_16BIT, 0x368A, 0xF829}, + {MISENSOR_16BIT, 0x368C, 0xC1A8}, + {MISENSOR_16BIT, 0x368E, 0xB0EC}, + {MISENSOR_16BIT, 0x3690, 0xE76A}, + {MISENSOR_16BIT, 0x3692, 0x69AF}, + {MISENSOR_16BIT, 0x3694, 0x378C}, + {MISENSOR_16BIT, 0x3696, 0xA70D}, + {MISENSOR_16BIT, 0x3698, 0x884F}, + {MISENSOR_16BIT, 0x369A, 0xEE8B}, + {MISENSOR_16BIT, 0x369C, 0x5DEF}, + {MISENSOR_16BIT, 0x369E, 0x27CC}, + {MISENSOR_16BIT, 0x36A0, 0xCAAC}, + {MISENSOR_16BIT, 0x36A2, 0x840E}, + {MISENSOR_16BIT, 0x36A4, 0xDAA9}, + {MISENSOR_16BIT, 0x36A6, 0xF00C}, + {MISENSOR_16BIT, 0x36C0, 0x1371}, + {MISENSOR_16BIT, 0x36C2, 0x272F}, + {MISENSOR_16BIT, 0x36C4, 0x2293}, + {MISENSOR_16BIT, 0x36C6, 0xE6D0}, + {MISENSOR_16BIT, 0x36C8, 0xEC32}, + {MISENSOR_16BIT, 0x36CA, 0x11B1}, + {MISENSOR_16BIT, 0x36CC, 0x7BAF}, + {MISENSOR_16BIT, 0x36CE, 0x5813}, + {MISENSOR_16BIT, 0x36D0, 0xB871}, + {MISENSOR_16BIT, 0x36D2, 0x8913}, + {MISENSOR_16BIT, 0x36D4, 0x4610}, + {MISENSOR_16BIT, 0x36D6, 0x7EEE}, + {MISENSOR_16BIT, 0x36D8, 0x0DF3}, + {MISENSOR_16BIT, 0x36DA, 0xB84F}, + {MISENSOR_16BIT, 0x36DC, 0xB532}, + {MISENSOR_16BIT, 0x36DE, 0x1171}, + {MISENSOR_16BIT, 0x36E0, 0x13CF}, + {MISENSOR_16BIT, 0x36E2, 0x22F3}, + {MISENSOR_16BIT, 0x36E4, 0xE090}, + {MISENSOR_16BIT, 0x36E6, 0x8133}, + {MISENSOR_16BIT, 0x3700, 0x88AE}, + {MISENSOR_16BIT, 0x3702, 0x00EA}, + {MISENSOR_16BIT, 0x3704, 0x344F}, + {MISENSOR_16BIT, 0x3706, 0xEC88}, + {MISENSOR_16BIT, 0x3708, 0x3E91}, + {MISENSOR_16BIT, 0x370A, 0xF12D}, + {MISENSOR_16BIT, 0x370C, 0xB0EF}, + {MISENSOR_16BIT, 0x370E, 0x77CD}, + {MISENSOR_16BIT, 0x3710, 0x7930}, + {MISENSOR_16BIT, 0x3712, 0x5C12}, + {MISENSOR_16BIT, 0x3714, 0x500C}, + {MISENSOR_16BIT, 0x3716, 0x22CE}, + {MISENSOR_16BIT, 0x3718, 0x2370}, + {MISENSOR_16BIT, 0x371A, 0x258F}, + {MISENSOR_16BIT, 0x371C, 0x3D30}, + {MISENSOR_16BIT, 0x371E, 0x370C}, + {MISENSOR_16BIT, 0x3720, 0x03ED}, + {MISENSOR_16BIT, 0x3722, 0x9AD0}, + {MISENSOR_16BIT, 0x3724, 0x7ECF}, + {MISENSOR_16BIT, 0x3726, 0x1093}, + {MISENSOR_16BIT, 0x3740, 0x2391}, + {MISENSOR_16BIT, 0x3742, 0xAAD0}, + {MISENSOR_16BIT, 0x3744, 0x28F2}, + {MISENSOR_16BIT, 0x3746, 0xBA4F}, + {MISENSOR_16BIT, 0x3748, 0xC536}, + {MISENSOR_16BIT, 0x374A, 0x1472}, + {MISENSOR_16BIT, 0x374C, 0xD110}, + {MISENSOR_16BIT, 0x374E, 0x2933}, + {MISENSOR_16BIT, 0x3750, 0xD0D1}, + {MISENSOR_16BIT, 0x3752, 0x9F37}, + {MISENSOR_16BIT, 0x3754, 0x34D1}, + {MISENSOR_16BIT, 0x3756, 0x1C6C}, + {MISENSOR_16BIT, 0x3758, 0x3FD2}, + {MISENSOR_16BIT, 0x375A, 0xCB72}, + {MISENSOR_16BIT, 0x375C, 0xBA96}, + {MISENSOR_16BIT, 0x375E, 0x1551}, + {MISENSOR_16BIT, 0x3760, 0xB74F}, + {MISENSOR_16BIT, 0x3762, 0x1672}, + {MISENSOR_16BIT, 0x3764, 0x84F1}, + {MISENSOR_16BIT, 0x3766, 0xC2D6}, + {MISENSOR_16BIT, 0x3782, 0x01E0}, + {MISENSOR_16BIT, 0x3784, 0x0280}, + {MISENSOR_16BIT, 0x37C0, 0xA6EA}, + {MISENSOR_16BIT, 0x37C2, 0x874B}, + {MISENSOR_16BIT, 0x37C4, 0x85CB}, + {MISENSOR_16BIT, 0x37C6, 0x968A}, + {MISENSOR_16BIT, 0x098E, 0x0000}, + {MISENSOR_16BIT, 0xC960, 0x0AF0}, + {MISENSOR_16BIT, 0xC962, 0x79E2}, + {MISENSOR_16BIT, 0xC964, 0x5EC8}, + {MISENSOR_16BIT, 0xC966, 0x791F}, + {MISENSOR_16BIT, 0xC968, 0x76EE}, + {MISENSOR_16BIT, 0xC96A, 0x0FA0}, + {MISENSOR_16BIT, 0xC96C, 0x7DFA}, + {MISENSOR_16BIT, 0xC96E, 0x7DAF}, + {MISENSOR_16BIT, 0xC970, 0x7E02}, + {MISENSOR_16BIT, 0xC972, 0x7E0A}, + {MISENSOR_16BIT, 0xC974, 0x1964}, + {MISENSOR_16BIT, 0xC976, 0x7CDC}, + {MISENSOR_16BIT, 0xC978, 0x7838}, + {MISENSOR_16BIT, 0xC97A, 0x7C2F}, + {MISENSOR_16BIT, 0xC97C, 0x7792}, + {MISENSOR_16BIT, 0xC95E, 0x0003}, + + /* [Step4-APGA] */ + {MISENSOR_16BIT, 0x098E, 0x0000}, + {MISENSOR_16BIT, 0xC95E, 0x0003}, + + /* [Step5-AWB_CCM]1: LOAD=CCM */ + {MISENSOR_16BIT, 0xC892, 0x0267}, + {MISENSOR_16BIT, 0xC894, 0xFF1A}, + {MISENSOR_16BIT, 0xC896, 0xFFB3}, + {MISENSOR_16BIT, 0xC898, 0xFF80}, + {MISENSOR_16BIT, 0xC89A, 0x0166}, + {MISENSOR_16BIT, 0xC89C, 0x0003}, + {MISENSOR_16BIT, 0xC89E, 0xFF9A}, + {MISENSOR_16BIT, 0xC8A0, 0xFEB4}, + {MISENSOR_16BIT, 0xC8A2, 0x024D}, + {MISENSOR_16BIT, 0xC8A4, 0x01BF}, + {MISENSOR_16BIT, 0xC8A6, 0xFF01}, + {MISENSOR_16BIT, 0xC8A8, 0xFFF3}, + {MISENSOR_16BIT, 0xC8AA, 0xFF75}, + {MISENSOR_16BIT, 0xC8AC, 0x0198}, + {MISENSOR_16BIT, 0xC8AE, 0xFFFD}, + {MISENSOR_16BIT, 0xC8B0, 0xFF9A}, + {MISENSOR_16BIT, 0xC8B2, 0xFEE7}, + {MISENSOR_16BIT, 0xC8B4, 0x02A8}, + {MISENSOR_16BIT, 0xC8B6, 0x01D9}, + {MISENSOR_16BIT, 0xC8B8, 0xFF26}, + {MISENSOR_16BIT, 0xC8BA, 0xFFF3}, + {MISENSOR_16BIT, 0xC8BC, 0xFFB3}, + {MISENSOR_16BIT, 0xC8BE, 0x0132}, + {MISENSOR_16BIT, 0xC8C0, 0xFFE8}, + {MISENSOR_16BIT, 0xC8C2, 0xFFDA}, + {MISENSOR_16BIT, 0xC8C4, 0xFECD}, + {MISENSOR_16BIT, 0xC8C6, 0x02C2}, + {MISENSOR_16BIT, 0xC8C8, 0x0075}, + {MISENSOR_16BIT, 0xC8CA, 0x011C}, + {MISENSOR_16BIT, 0xC8CC, 0x009A}, + {MISENSOR_16BIT, 0xC8CE, 0x0105}, + {MISENSOR_16BIT, 0xC8D0, 0x00A4}, + {MISENSOR_16BIT, 0xC8D2, 0x00AC}, + {MISENSOR_16BIT, 0xC8D4, 0x0A8C}, + {MISENSOR_16BIT, 0xC8D6, 0x0F0A}, + {MISENSOR_16BIT, 0xC8D8, 0x1964}, + + /* LOAD=AWB */ + {MISENSOR_16BIT, 0xC914, 0x0000}, + {MISENSOR_16BIT, 0xC916, 0x0000}, + {MISENSOR_16BIT, 0xC918, 0x04FF}, + {MISENSOR_16BIT, 0xC91A, 0x02CF}, + {MISENSOR_16BIT, 0xC904, 0x0033}, + {MISENSOR_16BIT, 0xC906, 0x0040}, + {MISENSOR_8BIT, 0xC8F2, 0x03}, + {MISENSOR_8BIT, 0xC8F3, 0x02}, + {MISENSOR_16BIT, 0xC906, 0x003C}, + {MISENSOR_16BIT, 0xC8F4, 0x0000}, + {MISENSOR_16BIT, 0xC8F6, 0x0000}, + {MISENSOR_16BIT, 0xC8F8, 0x0000}, + {MISENSOR_16BIT, 0xC8FA, 0xE724}, + {MISENSOR_16BIT, 0xC8FC, 0x1583}, + {MISENSOR_16BIT, 0xC8FE, 0x2045}, + {MISENSOR_16BIT, 0xC900, 0x05DC}, + {MISENSOR_16BIT, 0xC902, 0x007C}, + {MISENSOR_8BIT, 0xC90C, 0x80}, + {MISENSOR_8BIT, 0xC90D, 0x80}, + {MISENSOR_8BIT, 0xC90E, 0x80}, + {MISENSOR_8BIT, 0xC90F, 0x88}, + {MISENSOR_8BIT, 0xC910, 0x80}, + {MISENSOR_8BIT, 0xC911, 0x80}, + + /* LOAD=Step7-CPIPE_Preference */ + {MISENSOR_16BIT, 0xC926, 0x0020}, + {MISENSOR_16BIT, 0xC928, 0x009A}, + {MISENSOR_16BIT, 0xC946, 0x0070}, + {MISENSOR_16BIT, 0xC948, 0x00F3}, + {MISENSOR_16BIT, 0xC952, 0x0020}, + {MISENSOR_16BIT, 0xC954, 0x009A}, + {MISENSOR_8BIT, 0xC92A, 0x80}, + {MISENSOR_8BIT, 0xC92B, 0x4B}, + {MISENSOR_8BIT, 0xC92C, 0x00}, + {MISENSOR_8BIT, 0xC92D, 0xFF}, + {MISENSOR_8BIT, 0xC92E, 0x3C}, + {MISENSOR_8BIT, 0xC92F, 0x02}, + {MISENSOR_8BIT, 0xC930, 0x06}, + {MISENSOR_8BIT, 0xC931, 0x64}, + {MISENSOR_8BIT, 0xC932, 0x01}, + {MISENSOR_8BIT, 0xC933, 0x0C}, + {MISENSOR_8BIT, 0xC934, 0x3C}, + {MISENSOR_8BIT, 0xC935, 0x3C}, + {MISENSOR_8BIT, 0xC936, 0x3C}, + {MISENSOR_8BIT, 0xC937, 0x0F}, + {MISENSOR_8BIT, 0xC938, 0x64}, + {MISENSOR_8BIT, 0xC939, 0x64}, + {MISENSOR_8BIT, 0xC93A, 0x64}, + {MISENSOR_8BIT, 0xC93B, 0x32}, + {MISENSOR_16BIT, 0xC93C, 0x0020}, + {MISENSOR_16BIT, 0xC93E, 0x009A}, + {MISENSOR_16BIT, 0xC940, 0x00DC}, + {MISENSOR_8BIT, 0xC942, 0x38}, + {MISENSOR_8BIT, 0xC943, 0x30}, + {MISENSOR_8BIT, 0xC944, 0x50}, + {MISENSOR_8BIT, 0xC945, 0x19}, + {MISENSOR_16BIT, 0xC94A, 0x0230}, + {MISENSOR_16BIT, 0xC94C, 0x0010}, + {MISENSOR_16BIT, 0xC94E, 0x01CD}, + {MISENSOR_8BIT, 0xC950, 0x05}, + {MISENSOR_8BIT, 0xC951, 0x40}, + {MISENSOR_8BIT, 0xC87B, 0x1B}, + {MISENSOR_8BIT, 0xC878, 0x0E}, + {MISENSOR_16BIT, 0xC890, 0x0080}, + {MISENSOR_16BIT, 0xC886, 0x0100}, + {MISENSOR_16BIT, 0xC87C, 0x005A}, + {MISENSOR_8BIT, 0xB42A, 0x05}, + {MISENSOR_8BIT, 0xA80A, 0x20}, + + /* Speed up AE/AWB */ + {MISENSOR_16BIT, 0x098E, 0x2802}, + {MISENSOR_16BIT, 0xA802, 0x0008}, + {MISENSOR_8BIT, 0xC908, 0x01}, + {MISENSOR_8BIT, 0xC879, 0x01}, + {MISENSOR_8BIT, 0xC909, 0x02}, + {MISENSOR_8BIT, 0xA80A, 0x18}, + {MISENSOR_8BIT, 0xA80B, 0x18}, + {MISENSOR_8BIT, 0xAC16, 0x18}, + {MISENSOR_8BIT, 0xC878, 0x0E}, + + {MISENSOR_TOK_TERM, 0, 0} +}; + +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov2680.c b/drivers/staging/media/atomisp/i2c/ov2680.c new file mode 100644 index 0000000..5660910 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov2680.c @@ -0,0 +1,1559 @@ +/* + * Support for OmniVision OV2680 1080p HD camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/string.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kmod.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/moduleparam.h> +#include <media/v4l2-device.h> +#include <linux/io.h> +#include <linux/acpi.h> +#include "../include/linux/atomisp_gmin_platform.h" + +#include "ov2680.h" + +static int h_flag = 0; +static int v_flag = 0; +static enum atomisp_bayer_order ov2680_bayer_order_mapping[] = { + atomisp_bayer_order_bggr, + atomisp_bayer_order_grbg, + atomisp_bayer_order_gbrg, + atomisp_bayer_order_rggb, +}; + +/* i2c read/write stuff */ +static int ov2680_read_reg(struct i2c_client *client, + u16 data_length, u16 reg, u16 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[6]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != OV2680_8BIT && data_length != OV2680_16BIT + && data_length != OV2680_32BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0 , sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg >> 8); + data[1] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == OV2680_8BIT) + *val = (u8)data[0]; + else if (data_length == OV2680_16BIT) + *val = be16_to_cpu(*(u16 *)&data[0]); + else + *val = be32_to_cpu(*(u32 *)&data[0]); + //dev_dbg(&client->dev, "++++i2c read adr%x = %x\n", reg,*val); + return 0; +} + +static int ov2680_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + //dev_dbg(&client->dev, "+++i2c write reg=%x->%x\n", data[0]*256 +data[1],data[2]); + return ret == num_msg ? 0 : -EIO; +} + +static int ov2680_write_reg(struct i2c_client *client, u16 data_length, + u16 reg, u16 val) +{ + int ret; + unsigned char data[4] = {0}; + u16 *wreg = (u16 *)data; + const u16 len = data_length + sizeof(u16); /* 16-bit address + data */ + + if (data_length != OV2680_8BIT && data_length != OV2680_16BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = cpu_to_be16(reg); + + if (data_length == OV2680_8BIT) { + data[2] = (u8)(val); + } else { + /* OV2680_16BIT */ + u16 *wdata = (u16 *)&data[2]; + *wdata = cpu_to_be16(val); + } + + ret = ov2680_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * ov2680_write_reg_array - Initializes a list of OV2680 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __ov2680_flush_reg_array, __ov2680_buf_reg_array() and + * __ov2680_write_reg_is_consecutive() are internal functions to + * ov2680_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __ov2680_flush_reg_array(struct i2c_client *client, + struct ov2680_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u16) + ctrl->index; /* 16-bit address + data */ + ctrl->buffer.addr = cpu_to_be16(ctrl->buffer.addr); + ctrl->index = 0; + + return ov2680_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __ov2680_buf_reg_array(struct i2c_client *client, + struct ov2680_write_ctrl *ctrl, + const struct ov2680_reg *next) +{ + int size; + u16 *data16; + + switch (next->type) { + case OV2680_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case OV2680_16BIT: + size = 2; + data16 = (u16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u16) >= OV2680_MAX_WRITE_BUF_SIZE) + return __ov2680_flush_reg_array(client, ctrl); + + return 0; +} + +static int __ov2680_write_reg_is_consecutive(struct i2c_client *client, + struct ov2680_write_ctrl *ctrl, + const struct ov2680_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +static int ov2680_write_reg_array(struct i2c_client *client, + const struct ov2680_reg *reglist) +{ + const struct ov2680_reg *next = reglist; + struct ov2680_write_ctrl ctrl; + int err; + dev_dbg(&client->dev, "++++write reg array\n"); + ctrl.index = 0; + for (; next->type != OV2680_TOK_TERM; next++) { + switch (next->type & OV2680_TOK_MASK) { + case OV2680_TOK_DELAY: + err = __ov2680_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + dev_dbg(&client->dev, "+++ov2680_write_reg_array reg=%x->%x\n", next->reg,next->val); + if (!__ov2680_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __ov2680_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __ov2680_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __ov2680_flush_reg_array(client, &ctrl); +} +static int ov2680_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + + *val = (OV2680_FOCAL_LENGTH_NUM << 16) | OV2680_FOCAL_LENGTH_DEM; + return 0; +} + +static int ov2680_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for ov2680*/ + + *val = (OV2680_F_NUMBER_DEFAULT_NUM << 16) | OV2680_F_NUMBER_DEM; + return 0; +} + +static int ov2680_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + + *val = (OV2680_F_NUMBER_DEFAULT_NUM << 24) | + (OV2680_F_NUMBER_DEM << 16) | + (OV2680_F_NUMBER_DEFAULT_NUM << 8) | OV2680_F_NUMBER_DEM; + return 0; +} + +static int ov2680_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + dev_dbg(&client->dev, "++++ov2680_g_bin_factor_x\n"); + *val = ov2680_res[dev->fmt_idx].bin_factor_x; + + return 0; +} + +static int ov2680_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + *val = ov2680_res[dev->fmt_idx].bin_factor_y; + dev_dbg(&client->dev, "++++ov2680_g_bin_factor_y\n"); + return 0; +} + + +static int ov2680_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct ov2680_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct atomisp_sensor_mode_data *buf = &info->data; + unsigned int pix_clk_freq_hz; + u16 reg_val; + int ret; + dev_dbg(&client->dev, "++++ov2680_get_intg_factor\n"); + if (!info) + return -EINVAL; + + /* pixel clock */ + pix_clk_freq_hz = res->pix_clk_freq * 1000000; + + dev->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + buf->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + + /* get integration time */ + buf->coarse_integration_time_min = OV2680_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + OV2680_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = OV2680_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + OV2680_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = OV2680_FINE_INTG_TIME_MIN; + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = ov2680_read_reg(client, OV2680_16BIT, + OV2680_HORIZONTAL_START_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = reg_val; + + ret = ov2680_read_reg(client, OV2680_16BIT, + OV2680_VERTICAL_START_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = reg_val; + + ret = ov2680_read_reg(client, OV2680_16BIT, + OV2680_HORIZONTAL_END_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_end = reg_val; + + ret = ov2680_read_reg(client, OV2680_16BIT, + OV2680_VERTICAL_END_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_end = reg_val; + + ret = ov2680_read_reg(client, OV2680_16BIT, + OV2680_HORIZONTAL_OUTPUT_SIZE_H, ®_val); + if (ret) + return ret; + buf->output_width = reg_val; + + ret = ov2680_read_reg(client, OV2680_16BIT, + OV2680_VERTICAL_OUTPUT_SIZE_H, ®_val); + if (ret) + return ret; + buf->output_height = reg_val; + + buf->binning_factor_x = res->bin_factor_x ? + (res->bin_factor_x * 2) : 1; + buf->binning_factor_y = res->bin_factor_y ? + (res->bin_factor_y * 2) : 1; + return 0; +} + +static long __ov2680_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2680_device *dev = to_ov2680_sensor(sd); + u16 vts,hts; + int ret,exp_val; + + dev_dbg(&client->dev, "+++++++__ov2680_set_exposure coarse_itg %d, gain %d, digitgain %d++\n",coarse_itg, gain, digitgain); + + hts = ov2680_res[dev->fmt_idx].pixels_per_line; + vts = ov2680_res[dev->fmt_idx].lines_per_frame; + + /* group hold */ + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_GROUP_ACCESS, 0x00); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_GROUP_ACCESS); + return ret; + } + + /* Increase the VTS to match exposure + MARGIN */ + if (coarse_itg > vts - OV2680_INTEGRATION_TIME_MARGIN) + vts = (u16) coarse_itg + OV2680_INTEGRATION_TIME_MARGIN; + + ret = ov2680_write_reg(client, OV2680_16BIT, OV2680_TIMING_VTS_H, vts); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_TIMING_VTS_H); + return ret; + } + + /* set exposure */ + + /* Lower four bit should be 0*/ + exp_val = coarse_itg << 4; + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_EXPOSURE_L, exp_val & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_EXPOSURE_L); + return ret; + } + + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_EXPOSURE_M, (exp_val >> 8) & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_EXPOSURE_M); + return ret; + } + + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_EXPOSURE_H, (exp_val >> 16) & 0x0F); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_EXPOSURE_H); + return ret; + } + + /* Analog gain */ + ret = ov2680_write_reg(client, OV2680_16BIT, OV2680_AGC_H, gain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_AGC_H); + return ret; + } + /* Digital gain */ + if (digitgain) { + ret = ov2680_write_reg(client, OV2680_16BIT, + OV2680_MWB_RED_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_MWB_RED_GAIN_H); + return ret; + } + + ret = ov2680_write_reg(client, OV2680_16BIT, + OV2680_MWB_GREEN_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_MWB_RED_GAIN_H); + return ret; + } + + ret = ov2680_write_reg(client, OV2680_16BIT, + OV2680_MWB_BLUE_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_MWB_RED_GAIN_H); + return ret; + } + } + + /* End group */ + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_GROUP_ACCESS, 0x10); + if (ret) + return ret; + + /* Delay launch group */ + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_GROUP_ACCESS, 0xa0); + if (ret) + return ret; + return ret; +} + +static int ov2680_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ov2680_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long ov2680_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + u16 coarse_itg = exposure->integration_time[0]; + u16 analog_gain = exposure->gain[0]; + u16 digital_gain = exposure->gain[1]; + + /* we should not accept the invalid value below */ + if (analog_gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + + // EXPOSURE CONTROL DISABLED FOR INITIAL CHECKIN, TUNING DOESN'T WORK + return ov2680_set_exposure(sd, coarse_itg, analog_gain, digital_gain); +} + + + + + +static long ov2680_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return ov2680_s_exposure(sd, arg); + + default: + return -EINVAL; + } + return 0; +} + +/* This returns the exposure time being used. This should only be used + * for filling in EXIF data, not for actual image processing. + */ +static int ov2680_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 reg_v, reg_v2; + int ret; + + /* get exposure */ + ret = ov2680_read_reg(client, OV2680_8BIT, + OV2680_EXPOSURE_L, + ®_v); + if (ret) + goto err; + + ret = ov2680_read_reg(client, OV2680_8BIT, + OV2680_EXPOSURE_M, + ®_v2); + if (ret) + goto err; + + reg_v += reg_v2 << 8; + ret = ov2680_read_reg(client, OV2680_8BIT, + OV2680_EXPOSURE_H, + ®_v2); + if (ret) + goto err; + + *value = reg_v + (((u32)reg_v2 << 16)); +err: + return ret; +} + +static u32 ov2680_translate_bayer_order(enum atomisp_bayer_order code) +{ + switch (code) { + case atomisp_bayer_order_rggb: + return MEDIA_BUS_FMT_SRGGB10_1X10; + case atomisp_bayer_order_grbg: + return MEDIA_BUS_FMT_SGRBG10_1X10; + case atomisp_bayer_order_bggr: + return MEDIA_BUS_FMT_SBGGR10_1X10; + case atomisp_bayer_order_gbrg: + return MEDIA_BUS_FMT_SGBRG10_1X10; + } + return 0; +} + +static int ov2680_v_flip(struct v4l2_subdev *sd, s32 value) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct camera_mipi_info *ov2680_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u16 val; + u8 index; + dev_dbg(&client->dev, "@%s: value:%d\n", __func__, value); + ret = ov2680_read_reg(client, OV2680_8BIT, OV2680_FLIP_REG, &val); + if (ret) + return ret; + if (value) { + val |= OV2680_FLIP_MIRROR_BIT_ENABLE; + } else { + val &= ~OV2680_FLIP_MIRROR_BIT_ENABLE; + } + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_FLIP_REG, val); + if (ret) + return ret; + index = (v_flag>0?OV2680_FLIP_BIT:0) | (h_flag>0?OV2680_MIRROR_BIT:0); + ov2680_info = v4l2_get_subdev_hostdata(sd); + if (ov2680_info) { + ov2680_info->raw_bayer_order = ov2680_bayer_order_mapping[index]; + dev->format.code = ov2680_translate_bayer_order( + ov2680_info->raw_bayer_order); + } + return ret; +} + +static int ov2680_h_flip(struct v4l2_subdev *sd, s32 value) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct camera_mipi_info *ov2680_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u16 val; + u8 index; + dev_dbg(&client->dev, "@%s: value:%d\n", __func__, value); + + ret = ov2680_read_reg(client, OV2680_8BIT, OV2680_MIRROR_REG, &val); + if (ret) + return ret; + if (value) { + val |= OV2680_FLIP_MIRROR_BIT_ENABLE; + } else { + val &= ~OV2680_FLIP_MIRROR_BIT_ENABLE; + } + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_MIRROR_REG, val); + if (ret) + return ret; + index = (v_flag>0?OV2680_FLIP_BIT:0) | (h_flag>0?OV2680_MIRROR_BIT:0); + ov2680_info = v4l2_get_subdev_hostdata(sd); + if (ov2680_info) { + ov2680_info->raw_bayer_order = ov2680_bayer_order_mapping[index]; + dev->format.code = ov2680_translate_bayer_order( + ov2680_info->raw_bayer_order); + } + return ret; +} + +static int ov2680_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov2680_device *dev = + container_of(ctrl->handler, struct ov2680_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + dev_dbg(&client->dev, "%s: CID_VFLIP:%d.\n", + __func__, ctrl->val); + ret = ov2680_v_flip(&dev->sd, ctrl->val); + break; + case V4L2_CID_HFLIP: + dev_dbg(&client->dev, "%s: CID_HFLIP:%d.\n", + __func__, ctrl->val); + ret = ov2680_h_flip(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int ov2680_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov2680_device *dev = + container_of(ctrl->handler, struct ov2680_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = ov2680_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = ov2680_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = ov2680_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = ov2680_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_HORZ: + ret = ov2680_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = ov2680_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = ov2680_s_ctrl, + .g_volatile_ctrl = ov2680_g_volatile_ctrl +}; + +struct v4l2_ctrl_config ov2680_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = OV2680_FOCAL_LENGTH_DEFAULT, + .max = OV2680_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = OV2680_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = OV2680_F_NUMBER_DEFAULT, + .max = OV2680_F_NUMBER_DEFAULT, + .step = 0x01, + .def = OV2680_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = OV2680_F_NUMBER_RANGE, + .max = OV2680_F_NUMBER_RANGE, + .step = 0x01, + .def = OV2680_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "horizontal binning factor", + .min = 0, + .max = OV2680_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vertical binning factor", + .min = 0, + .max = OV2680_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flip", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Mirror", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, +}; + +static int ov2680_init_registers(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + ret = ov2680_write_reg(client, OV2680_8BIT, OV2680_SW_RESET, 0x01); + ret |= ov2680_write_reg_array(client, ov2680_global_setting); + + return ret; +} + +static int ov2680_init(struct v4l2_subdev *sd) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + + int ret; + + mutex_lock(&dev->input_lock); + + /* restore settings */ + ov2680_res = ov2680_res_preview; + N_RES = N_RES_PREVIEW; + + ret = ov2680_init_registers(sd); + + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = 0; + struct ov2680_device *dev = to_ov2680_sensor(sd); + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + if (flag) { + ret |= dev->platform_data->v1p8_ctrl(sd, 1); + ret |= dev->platform_data->v2p8_ctrl(sd, 1); + usleep_range(10000, 15000); + } + + if (!flag || ret) { + ret |= dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct ov2680_device *dev = to_ov2680_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + /* The OV2680 documents only one GPIO input (#XSHUTDN), but + * existing integrations often wire two (reset/power_down) + * because that is the way other sensors work. There is no + * way to tell how it is wired internally, so existing + * firmwares expose both and we drive them symmetrically. */ + if (flag) { + ret = dev->platform_data->gpio0_ctrl(sd, 1); + usleep_range(10000, 15000); + ret |= dev->platform_data->gpio1_ctrl(sd, 1); + usleep_range(10000, 15000); + } else { + ret = dev->platform_data->gpio1_ctrl(sd, 0); + ret |= dev->platform_data->gpio0_ctrl(sd, 0); + } + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* according to DS, at least 5ms is needed between DOVDD and PWDN */ + usleep_range(5000, 6000); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 1); + if (ret) + goto fail_power; + } + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* according to DS, 20ms is needed between PWDN and i2c access */ + msleep(20); + + return 0; + +fail_clk: + gpio_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + h_flag = 0; + v_flag = 0; + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int ov2680_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + + if (on == 0){ + ret = power_down(sd); + } else { + ret = power_up(sd); + if (!ret) + return ov2680_init(sd); + } + return ret; +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between resolution and w/h. + * res->width/height smaller than w/h wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 600 +static int distance(struct ov2680_resolution *res, u32 w, u32 h) +{ + unsigned int w_ratio = (res->width << 13) / w; + unsigned int h_ratio; + int match; + + if (h == 0) + return -1; + h_ratio = (res->height << 13) / h; + if (h_ratio == 0) + return -1; + match = abs(((w_ratio << 13) / h_ratio) - ((int)8192)); + + + if ((w_ratio < (int)8192) || (h_ratio < (int)8192) || + (match > LARGEST_ALLOWED_RATIO_MISMATCH)) + return -1; + + return w_ratio + h_ratio; +} + +/* Return the nearest higher resolution index */ +static int nearest_resolution_index(int w, int h) +{ + int i; + int idx = -1; + int dist; + int min_dist = INT_MAX; + struct ov2680_resolution *tmp_res = NULL; + + for (i = 0; i < N_RES; i++) { + tmp_res = &ov2680_res[i]; + dist = distance(tmp_res, w, h); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + } + } + + return idx; +} + +static int get_resolution_index(int w, int h) +{ + int i; + + for (i = 0; i < N_RES; i++) { + if (w != ov2680_res[i].width) + continue; + if (h != ov2680_res[i].height) + continue; + + return i; + } + + return -1; +} + +static int ov2680_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *ov2680_info = NULL; + int ret = 0; + int idx = 0; + dev_dbg(&client->dev, "+++++ov2680_s_mbus_fmt+++++l\n"); + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + ov2680_info = v4l2_get_subdev_hostdata(sd); + if (!ov2680_info) + return -EINVAL; + + mutex_lock(&dev->input_lock); + idx = nearest_resolution_index(fmt->width, fmt->height); + if (idx == -1) { + /* return the largest resolution */ + fmt->width = ov2680_res[N_RES - 1].width; + fmt->height = ov2680_res[N_RES - 1].height; + } else { + fmt->width = ov2680_res[idx].width; + fmt->height = ov2680_res[idx].height; + } + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + dev->fmt_idx = get_resolution_index(fmt->width, fmt->height); + dev_dbg(&client->dev, "+++++get_resolution_index=%d+++++l\n", + dev->fmt_idx); + if (dev->fmt_idx == -1) { + dev_err(&client->dev, "get resolution fail\n"); + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + v4l2_info(client, "__s_mbus_fmt i=%d, w=%d, h=%d\n", dev->fmt_idx, + fmt->width, fmt->height); + dev_dbg(&client->dev, "__s_mbus_fmt i=%d, w=%d, h=%d\n", + dev->fmt_idx, fmt->width, fmt->height); + + ret = ov2680_write_reg_array(client, ov2680_res[dev->fmt_idx].regs); + if (ret) + dev_err(&client->dev, "ov2680 write resolution register err\n"); + + ret = ov2680_get_intg_factor(client, ov2680_info, + &ov2680_res[dev->fmt_idx]); + if (ret) { + dev_err(&client->dev, "failed to get integration_factor\n"); + goto err; + } + + /*recall flip functions to avoid flip registers + * were overridden by default setting + */ + if (h_flag) + ov2680_h_flip(sd, h_flag); + if (v_flag) + ov2680_v_flip(sd, v_flag); + + v4l2_info(client, "\n%s idx %d \n", __func__, dev->fmt_idx); + + /*ret = startup(sd); + * if (ret) + * dev_err(&client->dev, "ov2680 startup err\n"); + */ +err: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov2680_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov2680_device *dev = to_ov2680_sensor(sd); + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + fmt->width = ov2680_res[dev->fmt_idx].width; + fmt->height = ov2680_res[dev->fmt_idx].height; + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + + return 0; +} + +static int ov2680_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u16 high, low; + int ret; + u16 id; + u8 revision; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ret = ov2680_read_reg(client, OV2680_8BIT, + OV2680_SC_CMMN_CHIP_ID_H, &high); + if (ret) { + dev_err(&client->dev, "sensor_id_high = 0x%x\n", high); + return -ENODEV; + } + ret = ov2680_read_reg(client, OV2680_8BIT, + OV2680_SC_CMMN_CHIP_ID_L, &low); + id = ((((u16) high) << 8) | (u16) low); + + if (id != OV2680_ID) { + dev_err(&client->dev, "sensor ID error 0x%x\n", id); + return -ENODEV; + } + + ret = ov2680_read_reg(client, OV2680_8BIT, + OV2680_SC_CMMN_SUB_ID, &high); + revision = (u8) high & 0x0f; + + dev_err(&client->dev, "sensor_revision id = 0x%x\n", id); + dev_err(&client->dev, "detect ov2680 success\n"); + dev_err(&client->dev, "################5##########\n"); + return 0; +} + +static int ov2680_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + mutex_lock(&dev->input_lock); + if(enable ) + dev_dbg(&client->dev, "ov2680_s_stream one \n"); + else + dev_dbg(&client->dev, "ov2680_s_stream off \n"); + + ret = ov2680_write_reg(client, OV2680_8BIT, OV2680_SW_STREAM, + enable ? OV2680_START_STREAMING : + OV2680_STOP_STREAMING); +#if 0 + /* restore settings */ + ov2680_res = ov2680_res_preview; + N_RES = N_RES_PREVIEW; +#endif + + //otp valid at stream on state + //if(!dev->otp_data) + // dev->otp_data = ov2680_otp_read(sd); + + mutex_unlock(&dev->input_lock); + + return ret; +} + + +static int ov2680_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!platform_data) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + /* power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov2680 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "ov2680 power-up err.\n"); + goto fail_power_on; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = ov2680_detect(client); + if (ret) { + dev_err(&client->dev, "ov2680_detect err s_config.\n"); + goto fail_csi_cfg; + } + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov2680 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + return 0; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov2680_g_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (!param) + return -EINVAL; + + if (param->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(&client->dev, "unsupported buffer type.\n"); + return -EINVAL; + } + + memset(param, 0, sizeof(*param)); + param->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + if (dev->fmt_idx >= 0 && dev->fmt_idx < N_RES) { + param->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + param->parm.capture.timeperframe.numerator = 1; + param->parm.capture.capturemode = dev->run_mode; + param->parm.capture.timeperframe.denominator = + ov2680_res[dev->fmt_idx].fps; + } + return 0; +} + +static int ov2680_s_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + dev->run_mode = param->parm.capture.capturemode; + + v4l2_info(client, "\n%s:run_mode :%x\n", __func__, dev->run_mode); + + mutex_lock(&dev->input_lock); + switch (dev->run_mode) { + case CI_MODE_VIDEO: + ov2680_res = ov2680_res_video; + N_RES = N_RES_VIDEO; + break; + case CI_MODE_STILL_CAPTURE: + ov2680_res = ov2680_res_still; + N_RES = N_RES_STILL; + break; + default: + ov2680_res = ov2680_res_preview; + N_RES = N_RES_PREVIEW; + } + mutex_unlock(&dev->input_lock); + return 0; +} + +static int ov2680_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = ov2680_res[dev->fmt_idx].fps; + + return 0; +} + +static int ov2680_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + return 0; +} + +static int ov2680_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = ov2680_res[index].width; + fse->min_height = ov2680_res[index].height; + fse->max_width = ov2680_res[index].width; + fse->max_height = ov2680_res[index].height; + + return 0; + +} + +static int ov2680_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = ov2680_res[dev->fmt_idx].skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_video_ops ov2680_video_ops = { + .s_stream = ov2680_s_stream, + .g_parm = ov2680_g_parm, + .s_parm = ov2680_s_parm, + .g_frame_interval = ov2680_g_frame_interval, +}; + +static const struct v4l2_subdev_sensor_ops ov2680_sensor_ops = { + .g_skip_frames = ov2680_g_skip_frames, +}; + +static const struct v4l2_subdev_core_ops ov2680_core_ops = { + .s_power = ov2680_s_power, + .ioctl = ov2680_ioctl, +}; + +static const struct v4l2_subdev_pad_ops ov2680_pad_ops = { + .enum_mbus_code = ov2680_enum_mbus_code, + .enum_frame_size = ov2680_enum_frame_size, + .get_fmt = ov2680_get_fmt, + .set_fmt = ov2680_set_fmt, +}; + +static const struct v4l2_subdev_ops ov2680_ops = { + .core = &ov2680_core_ops, + .video = &ov2680_video_ops, + .pad = &ov2680_pad_ops, + .sensor = &ov2680_sensor_ops, +}; + +static int ov2680_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov2680_device *dev = to_ov2680_sensor(sd); + dev_dbg(&client->dev, "ov2680_remove...\n"); + + dev->platform_data->csi_cfg(sd, 0); + + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); + + return 0; +} + +static int ov2680_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ov2680_device *dev; + int ret; + void *pdata; + unsigned int i; + + printk("++++ov2680_probe++++\n"); + dev_info(&client->dev, "++++ov2680_probe++++\n"); + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + dev->fmt_idx = 0; + v4l2_i2c_subdev_init(&(dev->sd), client, &ov2680_ops); + + if (ACPI_COMPANION(&client->dev)) + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_bggr); + else + pdata = client->dev.platform_data; + + if (!pdata) { + ret = -EINVAL; + goto out_free; + } + + ret = ov2680_s_config(&dev->sd, client->irq, pdata); + if (ret) + goto out_free; + + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) + goto out_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(ov2680_controls)); + if (ret) { + ov2680_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(ov2680_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &ov2680_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + ov2680_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + { + ov2680_remove(client); + dev_dbg(&client->dev, "+++ remove ov2680 \n"); + } + return ret; +out_free: + dev_dbg(&client->dev, "+++ out free \n"); + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +static struct acpi_device_id ov2680_acpi_match[] = { + {"XXOV2680"}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, ov2680_acpi_match); + + +MODULE_DEVICE_TABLE(i2c, ov2680_id); +static struct i2c_driver ov2680_driver = { + .driver = { + .owner = THIS_MODULE, + .name = OV2680_NAME, + .acpi_match_table = ACPI_PTR(ov2680_acpi_match), + + }, + .probe = ov2680_probe, + .remove = ov2680_remove, + .id_table = ov2680_id, +}; + +static int init_ov2680(void) +{ + return i2c_add_driver(&ov2680_driver); +} + +static void exit_ov2680(void) +{ + + i2c_del_driver(&ov2680_driver); +} + +module_init(init_ov2680); +module_exit(exit_ov2680); + +MODULE_AUTHOR("Jacky Wang <Jacky_wang@ovt.com>"); +MODULE_DESCRIPTION("A low-level driver for OmniVision 2680 sensors"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/staging/media/atomisp/i2c/ov2680.h b/drivers/staging/media/atomisp/i2c/ov2680.h new file mode 100644 index 0000000..944fe8e --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov2680.h @@ -0,0 +1,940 @@ +/* + * Support for OmniVision OV2680 5M camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __OV2680_H__ +#define __OV2680_H__ +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/i2c.h> +#include <linux/delay.h> +#include <linux/videodev2.h> +#include <linux/spinlock.h> +#include <media/v4l2-subdev.h> +#include <media/v4l2-device.h> +#include <media/v4l2-ctrls.h> +#include <linux/v4l2-mediabus.h> +#include <media/media-entity.h> + +#include "../include/linux/atomisp_platform.h" + +#define OV2680_NAME "ov2680" +#define OV2680B_NAME "ov2680b" +#define OV2680F_NAME "ov2680f" + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 0x2 +#define I2C_RETRY_COUNT 5 + +#define OV2680_FOCAL_LENGTH_NUM 334 /*3.34mm*/ +#define OV2680_FOCAL_LENGTH_DEM 100 +#define OV2680_F_NUMBER_DEFAULT_NUM 24 +#define OV2680_F_NUMBER_DEM 10 + +#define OV2680_BIN_FACTOR_MAX 4 + +#define MAX_FMTS 1 + +/* sensor_mode_data read_mode adaptation */ +#define OV2680_READ_MODE_BINNING_ON 0x0400 +#define OV2680_READ_MODE_BINNING_OFF 0x00 +#define OV2680_INTEGRATION_TIME_MARGIN 8 + +#define OV2680_MAX_EXPOSURE_VALUE 0xFFF1 +#define OV2680_MAX_GAIN_VALUE 0xFF + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV2680_FOCAL_LENGTH_DEFAULT 0x1B70064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV2680_F_NUMBER_DEFAULT 0x18000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define OV2680_F_NUMBER_RANGE 0x180a180a +#define OV2680_ID 0x2680 + +#define OV2680_FINE_INTG_TIME_MIN 0 +#define OV2680_FINE_INTG_TIME_MAX_MARGIN 0 +#define OV2680_COARSE_INTG_TIME_MIN 1 +#define OV2680_COARSE_INTG_TIME_MAX_MARGIN 6 + +/* + * OV2680 System control registers + */ +#define OV2680_SW_SLEEP 0x0100 +#define OV2680_SW_RESET 0x0103 +#define OV2680_SW_STREAM 0x0100 + +#define OV2680_SC_CMMN_CHIP_ID_H 0x300A +#define OV2680_SC_CMMN_CHIP_ID_L 0x300B +#define OV2680_SC_CMMN_SCCB_ID 0x302B /* 0x300C*/ +#define OV2680_SC_CMMN_SUB_ID 0x302A /* process, version*/ + +#define OV2680_GROUP_ACCESS 0x3208 /*Bit[7:4] Group control, Bit[3:0] Group ID*/ + +#define OV2680_EXPOSURE_H 0x3500 /*Bit[3:0] Bit[19:16] of exposure, remaining 16 bits lies in Reg0x3501&Reg0x3502*/ +#define OV2680_EXPOSURE_M 0x3501 +#define OV2680_EXPOSURE_L 0x3502 +#define OV2680_AGC_H 0x350A /*Bit[1:0] means Bit[9:8] of gain*/ +#define OV2680_AGC_L 0x350B /*Bit[7:0] of gain*/ + +#define OV2680_HORIZONTAL_START_H 0x3800 /*Bit[11:8]*/ +#define OV2680_HORIZONTAL_START_L 0x3801 /*Bit[7:0]*/ +#define OV2680_VERTICAL_START_H 0x3802 /*Bit[11:8]*/ +#define OV2680_VERTICAL_START_L 0x3803 /*Bit[7:0]*/ +#define OV2680_HORIZONTAL_END_H 0x3804 /*Bit[11:8]*/ +#define OV2680_HORIZONTAL_END_L 0x3805 /*Bit[7:0]*/ +#define OV2680_VERTICAL_END_H 0x3806 /*Bit[11:8]*/ +#define OV2680_VERTICAL_END_L 0x3807 /*Bit[7:0]*/ +#define OV2680_HORIZONTAL_OUTPUT_SIZE_H 0x3808 /*Bit[3:0]*/ +#define OV2680_HORIZONTAL_OUTPUT_SIZE_L 0x3809 /*Bit[7:0]*/ +#define OV2680_VERTICAL_OUTPUT_SIZE_H 0x380a /*Bit[3:0]*/ +#define OV2680_VERTICAL_OUTPUT_SIZE_L 0x380b /*Bit[7:0]*/ +#define OV2680_TIMING_HTS_H 0x380C /*High 8-bit, and low 8-bit HTS address is 0x380d*/ +#define OV2680_TIMING_HTS_L 0x380D /*High 8-bit, and low 8-bit HTS address is 0x380d*/ +#define OV2680_TIMING_VTS_H 0x380e /*High 8-bit, and low 8-bit HTS address is 0x380f*/ +#define OV2680_TIMING_VTS_L 0x380f /*High 8-bit, and low 8-bit HTS address is 0x380f*/ +#define OV2680_FRAME_OFF_NUM 0x4202 + +/*Flip/Mirror*/ +#define OV2680_FLIP_REG 0x3820 +#define OV2680_MIRROR_REG 0x3821 +#define OV2680_FLIP_BIT 1 +#define OV2680_MIRROR_BIT 2 +#define OV2680_FLIP_MIRROR_BIT_ENABLE 4 + +#define OV2680_MWB_RED_GAIN_H 0x5004/*0x3400*/ +#define OV2680_MWB_GREEN_GAIN_H 0x5006/*0x3402*/ +#define OV2680_MWB_BLUE_GAIN_H 0x5008/*0x3404*/ +#define OV2680_MWB_GAIN_MAX 0x0fff + +#define OV2680_START_STREAMING 0x01 +#define OV2680_STOP_STREAMING 0x00 + + +#define OV2680_INVALID_CONFIG 0xffffffff + + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct ov2680_resolution { + u8 *desc; + const struct ov2680_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u32 skip_frames; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; +}; + +struct ov2680_format { + u8 *desc; + u32 pixelformat; + struct ov2680_reg *regs; +}; + + /* + * ov2680 device structure. + */ + struct ov2680_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + struct v4l2_ctrl_handler ctrl_handler; + struct camera_sensor_platform_data *platform_data; + struct timespec timestamp_t_focus_abs; + int vt_pix_clk_freq_mhz; + int fmt_idx; + int run_mode; + u8 res; + u8 type; + }; + + enum ov2680_tok_type { + OV2680_8BIT = 0x0001, + OV2680_16BIT = 0x0002, + OV2680_32BIT = 0x0004, + OV2680_TOK_TERM = 0xf000, /* terminating token for reg list */ + OV2680_TOK_DELAY = 0xfe00, /* delay token for reg list */ + OV2680_TOK_MASK = 0xfff0 + }; + + /** + * struct ov2680_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ + struct ov2680_reg { + enum ov2680_tok_type type; + u16 reg; + u32 val; /* @set value for read/mod/write, @mask */ + }; + + #define to_ov2680_sensor(x) container_of(x, struct ov2680_device, sd) + + #define OV2680_MAX_WRITE_BUF_SIZE 30 + + struct ov2680_write_buffer { + u16 addr; + u8 data[OV2680_MAX_WRITE_BUF_SIZE]; + }; + + struct ov2680_write_ctrl { + int index; + struct ov2680_write_buffer buffer; + }; + + static const struct i2c_device_id ov2680_id[] = { + {OV2680B_NAME, 0}, + {OV2680F_NAME, 0}, + {} + }; + + static struct ov2680_reg const ov2680_global_setting[] = { + {OV2680_8BIT, 0x0103, 0x01}, + {OV2680_8BIT, 0x3002, 0x00}, + {OV2680_8BIT, 0x3016, 0x1c}, + {OV2680_8BIT, 0x3018, 0x44}, + {OV2680_8BIT, 0x3020, 0x00}, + {OV2680_8BIT, 0x3080, 0x02}, + {OV2680_8BIT, 0x3082, 0x45}, + {OV2680_8BIT, 0x3084, 0x09}, + {OV2680_8BIT, 0x3085, 0x04}, + {OV2680_8BIT, 0x3503, 0x03}, + {OV2680_8BIT, 0x350b, 0x36}, + {OV2680_8BIT, 0x3600, 0xb4}, + {OV2680_8BIT, 0x3603, 0x39}, + {OV2680_8BIT, 0x3604, 0x24}, + {OV2680_8BIT, 0x3605, 0x00}, + {OV2680_8BIT, 0x3620, 0x26}, + {OV2680_8BIT, 0x3621, 0x37}, + {OV2680_8BIT, 0x3622, 0x04}, + {OV2680_8BIT, 0x3628, 0x00}, + {OV2680_8BIT, 0x3705, 0x3c}, + {OV2680_8BIT, 0x370c, 0x50}, + {OV2680_8BIT, 0x370d, 0xc0}, + {OV2680_8BIT, 0x3718, 0x88}, + {OV2680_8BIT, 0x3720, 0x00}, + {OV2680_8BIT, 0x3721, 0x00}, + {OV2680_8BIT, 0x3722, 0x00}, + {OV2680_8BIT, 0x3723, 0x00}, + {OV2680_8BIT, 0x3738, 0x00}, + {OV2680_8BIT, 0x3717, 0x58}, + {OV2680_8BIT, 0x3781, 0x80}, + {OV2680_8BIT, 0x3789, 0x60}, + {OV2680_8BIT, 0x3800, 0x00}, + {OV2680_8BIT, 0x3819, 0x04}, + {OV2680_8BIT, 0x4000, 0x81}, + {OV2680_8BIT, 0x4001, 0x40}, + {OV2680_8BIT, 0x4602, 0x02}, + {OV2680_8BIT, 0x481f, 0x36}, + {OV2680_8BIT, 0x4825, 0x36}, + {OV2680_8BIT, 0x4837, 0x18}, + {OV2680_8BIT, 0x5002, 0x30}, + {OV2680_8BIT, 0x5004, 0x04},//manual awb 1x + {OV2680_8BIT, 0x5005, 0x00}, + {OV2680_8BIT, 0x5006, 0x04}, + {OV2680_8BIT, 0x5007, 0x00}, + {OV2680_8BIT, 0x5008, 0x04}, + {OV2680_8BIT, 0x5009, 0x00}, + {OV2680_8BIT, 0x5080, 0x00}, + {OV2680_8BIT, 0x3701, 0x64}, //add on 14/05/13 + {OV2680_8BIT, 0x3784, 0x0c}, //based OV2680_R1A_AM10.ovt add on 14/06/13 + {OV2680_8BIT, 0x5780, 0x3e}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13 + {OV2680_8BIT, 0x5781, 0x0f}, + {OV2680_8BIT, 0x5782, 0x04}, + {OV2680_8BIT, 0x5783, 0x02}, + {OV2680_8BIT, 0x5784, 0x01}, + {OV2680_8BIT, 0x5785, 0x01}, + {OV2680_8BIT, 0x5786, 0x00}, + {OV2680_8BIT, 0x5787, 0x04}, + {OV2680_8BIT, 0x5788, 0x02}, + {OV2680_8BIT, 0x5789, 0x00}, + {OV2680_8BIT, 0x578a, 0x01}, + {OV2680_8BIT, 0x578b, 0x02}, + {OV2680_8BIT, 0x578c, 0x03}, + {OV2680_8BIT, 0x578d, 0x03}, + {OV2680_8BIT, 0x578e, 0x08}, + {OV2680_8BIT, 0x578f, 0x0c}, + {OV2680_8BIT, 0x5790, 0x08}, + {OV2680_8BIT, 0x5791, 0x04}, + {OV2680_8BIT, 0x5792, 0x00}, + {OV2680_8BIT, 0x5793, 0x00}, + {OV2680_8BIT, 0x5794, 0x03}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13 + {OV2680_8BIT, 0x0100, 0x00}, //stream off + + {OV2680_TOK_TERM, 0, 0} + }; + + + /* + * 176x144 30fps VBlanking 1lane 10Bit (binning) + */ + static struct ov2680_reg const ov2680_QCIF_30fps[] = { + {OV2680_8BIT, 0x3086, 0x01}, + {OV2680_8BIT, 0x3501, 0x24}, + {OV2680_8BIT, 0x3502, 0x40}, + {OV2680_8BIT, 0x370a, 0x23}, + {OV2680_8BIT, 0x3801, 0xa0}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x78}, + {OV2680_8BIT, 0x3804, 0x05}, + {OV2680_8BIT, 0x3805, 0xaf}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0x47}, + {OV2680_8BIT, 0x3808, 0x00}, + {OV2680_8BIT, 0x3809, 0xC0}, + {OV2680_8BIT, 0x380a, 0x00}, + {OV2680_8BIT, 0x380b, 0xa0}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xb0}, + {OV2680_8BIT, 0x380e, 0x02}, + {OV2680_8BIT, 0x380f, 0x84}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x04}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x04}, + {OV2680_8BIT, 0x3814, 0x31}, + {OV2680_8BIT, 0x3815, 0x31}, + {OV2680_8BIT, 0x4000, 0x81}, + {OV2680_8BIT, 0x4001, 0x40}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x03}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc2}, + {OV2680_8BIT, 0x3821, 0x01}, + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 352x288 30fps VBlanking 1lane 10Bit (binning) + */ + static struct ov2680_reg const ov2680_CIF_30fps[] = { + {OV2680_8BIT, 0x3086, 0x01}, + {OV2680_8BIT, 0x3501, 0x24}, + {OV2680_8BIT, 0x3502, 0x40}, + {OV2680_8BIT, 0x370a, 0x23}, + {OV2680_8BIT, 0x3801, 0xa0}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x78}, + {OV2680_8BIT, 0x3804, 0x03}, + {OV2680_8BIT, 0x3805, 0x8f}, + {OV2680_8BIT, 0x3806, 0x02}, + {OV2680_8BIT, 0x3807, 0xe7}, + {OV2680_8BIT, 0x3808, 0x01}, + {OV2680_8BIT, 0x3809, 0x70}, + {OV2680_8BIT, 0x380a, 0x01}, + {OV2680_8BIT, 0x380b, 0x30}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xb0}, + {OV2680_8BIT, 0x380e, 0x02}, + {OV2680_8BIT, 0x380f, 0x84}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x04}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x04}, + {OV2680_8BIT, 0x3814, 0x31}, + {OV2680_8BIT, 0x3815, 0x31}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x03}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc2}, + {OV2680_8BIT, 0x3821, 0x01}, + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 336x256 30fps VBlanking 1lane 10Bit (binning) + */ + static struct ov2680_reg const ov2680_QVGA_30fps[] = { + {OV2680_8BIT, 0x3086, 0x01}, + {OV2680_8BIT, 0x3501, 0x24}, + {OV2680_8BIT, 0x3502, 0x40}, + {OV2680_8BIT, 0x370a, 0x23}, + {OV2680_8BIT, 0x3801, 0xa0}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x78}, + {OV2680_8BIT, 0x3804, 0x03}, + {OV2680_8BIT, 0x3805, 0x4f}, + {OV2680_8BIT, 0x3806, 0x02}, + {OV2680_8BIT, 0x3807, 0x87}, + {OV2680_8BIT, 0x3808, 0x01}, + {OV2680_8BIT, 0x3809, 0x50}, + {OV2680_8BIT, 0x380a, 0x01}, + {OV2680_8BIT, 0x380b, 0x00}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xb0}, + {OV2680_8BIT, 0x380e, 0x02}, + {OV2680_8BIT, 0x380f, 0x84}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x04}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x04}, + {OV2680_8BIT, 0x3814, 0x31}, + {OV2680_8BIT, 0x3815, 0x31}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x03}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc2}, + {OV2680_8BIT, 0x3821, 0x01}, + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + + + /* + * 656x496 30fps VBlanking 1lane 10Bit (binning) + */ + static struct ov2680_reg const ov2680_656x496_30fps[] = { + {OV2680_8BIT, 0x3086, 0x01}, + {OV2680_8BIT, 0x3501, 0x24}, + {OV2680_8BIT, 0x3502, 0x40}, + {OV2680_8BIT, 0x370a, 0x23}, + {OV2680_8BIT, 0x3801, 0xa0}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x78}, + {OV2680_8BIT, 0x3804, 0x05}, + {OV2680_8BIT, 0x3805, 0xcf}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0x67}, + {OV2680_8BIT, 0x3808, 0x02}, + {OV2680_8BIT, 0x3809, 0x90}, + {OV2680_8BIT, 0x380a, 0x01}, + {OV2680_8BIT, 0x380b, 0xf0}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xb0}, + {OV2680_8BIT, 0x380e, 0x02}, + {OV2680_8BIT, 0x380f, 0x84}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x04}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x04}, + {OV2680_8BIT, 0x3814, 0x31}, + {OV2680_8BIT, 0x3815, 0x31}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x03}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc2}, + {OV2680_8BIT, 0x3821, 0x01}, + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + /* + * 800x600 30fps VBlanking 1lane 10Bit (binning) + */ + static struct ov2680_reg const ov2680_720x592_30fps[] = { + {OV2680_8BIT, 0x3086, 0x01}, + {OV2680_8BIT, 0x3501, 0x26}, + {OV2680_8BIT, 0x3502, 0x40}, + {OV2680_8BIT, 0x370a, 0x23}, + {OV2680_8BIT, 0x3801, 0x00}, // X_ADDR_START; + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x00}, // Y_ADDR_START; + {OV2680_8BIT, 0x3804, 0x05}, + {OV2680_8BIT, 0x3805, 0xaf}, // X_ADDR_END; + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0xaf}, // Y_ADDR_END; + {OV2680_8BIT, 0x3808, 0x02}, + {OV2680_8BIT, 0x3809, 0xd0}, // X_OUTPUT_SIZE; + {OV2680_8BIT, 0x380a, 0x02}, + {OV2680_8BIT, 0x380b, 0x50}, // Y_OUTPUT_SIZE; + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xac}, // HTS; + {OV2680_8BIT, 0x380e, 0x02}, + {OV2680_8BIT, 0x380f, 0x84}, // VTS; + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x00}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x00}, + {OV2680_8BIT, 0x3814, 0x31}, + {OV2680_8BIT, 0x3815, 0x31}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x03}, + {OV2680_8BIT, 0x5708, 0x00}, + {OV2680_8BIT, 0x5704, 0x02}, + {OV2680_8BIT, 0x5705, 0xd0}, // X_WIN; + {OV2680_8BIT, 0x5706, 0x02}, + {OV2680_8BIT, 0x5707, 0x50}, // Y_WIN; + {OV2680_8BIT, 0x3820, 0xc2}, // FLIP_FORMAT; + {OV2680_8BIT, 0x3821, 0x01}, // MIRROR_FORMAT; + {OV2680_8BIT, 0x5090, 0x00}, // PRE ISP CTRL16, default value is 0x0C; + // BIT[3]: Mirror order, BG or GB; + // BIT[2]: Flip order, BR or RB; + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 800x600 30fps VBlanking 1lane 10Bit (binning) + */ + static struct ov2680_reg const ov2680_800x600_30fps[] = { + {OV2680_8BIT, 0x3086, 0x01}, + {OV2680_8BIT, 0x3501, 0x26}, + {OV2680_8BIT, 0x3502, 0x40}, + {OV2680_8BIT, 0x370a, 0x23}, + {OV2680_8BIT, 0x3801, 0x00}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x00}, + {OV2680_8BIT, 0x3804, 0x06}, + {OV2680_8BIT, 0x3805, 0x4f}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0xbf}, + {OV2680_8BIT, 0x3808, 0x03}, + {OV2680_8BIT, 0x3809, 0x20}, + {OV2680_8BIT, 0x380a, 0x02}, + {OV2680_8BIT, 0x380b, 0x58}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xac}, + {OV2680_8BIT, 0x380e, 0x02}, + {OV2680_8BIT, 0x380f, 0x84}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x00}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x00}, + {OV2680_8BIT, 0x3814, 0x31}, + {OV2680_8BIT, 0x3815, 0x31}, + {OV2680_8BIT, 0x5708, 0x00}, + {OV2680_8BIT, 0x5704, 0x03}, + {OV2680_8BIT, 0x5705, 0x20}, + {OV2680_8BIT, 0x5706, 0x02}, + {OV2680_8BIT, 0x5707, 0x58}, + {OV2680_8BIT, 0x3820, 0xc2}, + {OV2680_8BIT, 0x3821, 0x01}, + {OV2680_8BIT, 0x5090, 0x00}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x03}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 720p=1280*720 30fps VBlanking 1lane 10Bit (no-Scaling) + */ + static struct ov2680_reg const ov2680_720p_30fps[] = { + {OV2680_8BIT, 0x3086, 0x00}, + {OV2680_8BIT, 0x3501, 0x48}, + {OV2680_8BIT, 0x3502, 0xe0}, + {OV2680_8BIT, 0x370a, 0x21}, + {OV2680_8BIT, 0x3801, 0xa0}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0xf2}, + {OV2680_8BIT, 0x3804, 0x05}, + {OV2680_8BIT, 0x3805, 0xbf}, + {OV2680_8BIT, 0x3806, 0x03}, + {OV2680_8BIT, 0x3807, 0xdd}, + {OV2680_8BIT, 0x3808, 0x05}, + {OV2680_8BIT, 0x3809, 0x10}, + {OV2680_8BIT, 0x380a, 0x02}, + {OV2680_8BIT, 0x380b, 0xe0}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xa8}, + {OV2680_8BIT, 0x380e, 0x05}, + {OV2680_8BIT, 0x380f, 0x0e}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x08}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x06}, + {OV2680_8BIT, 0x3814, 0x11}, + {OV2680_8BIT, 0x3815, 0x11}, + {OV2680_8BIT, 0x4008, 0x02}, + {OV2680_8BIT, 0x4009, 0x09}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc0}, + {OV2680_8BIT, 0x3821, 0x00}, + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 1296x976 30fps VBlanking 1lane 10Bit(no-scaling) + */ + static struct ov2680_reg const ov2680_1296x976_30fps[] = { + {OV2680_8BIT, 0x3086, 0x00}, + {OV2680_8BIT, 0x3501, 0x48}, + {OV2680_8BIT, 0x3502, 0xe0}, + {OV2680_8BIT, 0x370a, 0x21}, + {OV2680_8BIT, 0x3801, 0xa0}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x78}, + {OV2680_8BIT, 0x3804, 0x05}, + {OV2680_8BIT, 0x3805, 0xbf}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0x57}, + {OV2680_8BIT, 0x3808, 0x05}, + {OV2680_8BIT, 0x3809, 0x10}, + {OV2680_8BIT, 0x380a, 0x03}, + {OV2680_8BIT, 0x380b, 0xd0}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xa8}, + {OV2680_8BIT, 0x380e, 0x05}, + {OV2680_8BIT, 0x380f, 0x0e}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x08}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x08}, + {OV2680_8BIT, 0x3814, 0x11}, + {OV2680_8BIT, 0x3815, 0x11}, + {OV2680_8BIT, 0x4008, 0x02}, + {OV2680_8BIT, 0x4009, 0x09}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc0}, + {OV2680_8BIT, 0x3821, 0x00}, //miror/flip + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 1456*1096 30fps VBlanking 1lane 10bit(no-scaling) + */ + static struct ov2680_reg const ov2680_1456x1096_30fps[]= { + {OV2680_8BIT, 0x3086, 0x00}, + {OV2680_8BIT, 0x3501, 0x48}, + {OV2680_8BIT, 0x3502, 0xe0}, + {OV2680_8BIT, 0x370a, 0x21}, + {OV2680_8BIT, 0x3801, 0x90}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x78}, + {OV2680_8BIT, 0x3804, 0x06}, + {OV2680_8BIT, 0x3805, 0x4f}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0xC0}, + {OV2680_8BIT, 0x3808, 0x05}, + {OV2680_8BIT, 0x3809, 0xb0}, + {OV2680_8BIT, 0x380a, 0x04}, + {OV2680_8BIT, 0x380b, 0x48}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xa8}, + {OV2680_8BIT, 0x380e, 0x05}, + {OV2680_8BIT, 0x380f, 0x0e}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x08}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x00}, + {OV2680_8BIT, 0x3814, 0x11}, + {OV2680_8BIT, 0x3815, 0x11}, + {OV2680_8BIT, 0x4008, 0x02}, + {OV2680_8BIT, 0x4009, 0x09}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc0}, + {OV2680_8BIT, 0x3821, 0x00}, + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + *1616x916 30fps VBlanking 1lane 10bit + */ + + static struct ov2680_reg const ov2680_1616x916_30fps[] = { + + {OV2680_8BIT, 0x3086, 0x00}, + {OV2680_8BIT, 0x3501, 0x48}, + {OV2680_8BIT, 0x3502, 0xe0}, + {OV2680_8BIT, 0x370a, 0x21}, + {OV2680_8BIT, 0x3801, 0x00}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x96}, + {OV2680_8BIT, 0x3804, 0x06}, + {OV2680_8BIT, 0x3805, 0x4f}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0x39}, + {OV2680_8BIT, 0x3808, 0x06}, + {OV2680_8BIT, 0x3809, 0x50}, + {OV2680_8BIT, 0x380a, 0x03}, + {OV2680_8BIT, 0x380b, 0x94}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xa8}, + {OV2680_8BIT, 0x380e, 0x05}, + {OV2680_8BIT, 0x380f, 0x0e}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x00}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x08}, + {OV2680_8BIT, 0x3814, 0x11}, + {OV2680_8BIT, 0x3815, 0x11}, + {OV2680_8BIT, 0x4008, 0x02}, + {OV2680_8BIT, 0x4009, 0x09}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x06}, + {OV2680_8BIT, 0x5705, 0x50}, + {OV2680_8BIT, 0x5706, 0x03}, + {OV2680_8BIT, 0x5707, 0x94}, + {OV2680_8BIT, 0x3820, 0xc0}, + {OV2680_8BIT, 0x3821, 0x00}, + // {OV2680_8BIT, 0x5090, 0x0C}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 1612x1212 30fps VBlanking 1lane 10Bit + */ + static struct ov2680_reg const ov2680_1616x1082_30fps[] = { + {OV2680_8BIT, 0x3086, 0x00}, + {OV2680_8BIT, 0x3501, 0x48}, + {OV2680_8BIT, 0x3502, 0xe0}, + {OV2680_8BIT, 0x370a, 0x21}, + {OV2680_8BIT, 0x3801, 0x00}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x86}, + {OV2680_8BIT, 0x3804, 0x06}, + {OV2680_8BIT, 0x3805, 0x4f}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0xbf}, + {OV2680_8BIT, 0x3808, 0x06}, + {OV2680_8BIT, 0x3809, 0x50}, + {OV2680_8BIT, 0x380a, 0x04}, + {OV2680_8BIT, 0x380b, 0x3a}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xa8}, + {OV2680_8BIT, 0x380e, 0x05}, + {OV2680_8BIT, 0x380f, 0x0e}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x00}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x00}, + {OV2680_8BIT, 0x3814, 0x11}, + {OV2680_8BIT, 0x3815, 0x11}, + {OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x06}, + {OV2680_8BIT, 0x5705, 0x50}, + {OV2680_8BIT, 0x5706, 0x04}, + {OV2680_8BIT, 0x5707, 0x3a}, + {OV2680_8BIT, 0x3820, 0xc0}, + {OV2680_8BIT, 0x3821, 0x00}, + // {OV2680_8BIT, 0x5090, 0x0C}, + {OV2680_8BIT, 0x4008, 0x02}, + {OV2680_8BIT, 0x4009, 0x09}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_TOK_TERM, 0, 0} + }; + /* + * 1616x1216 30fps VBlanking 1lane 10Bit + */ + static struct ov2680_reg const ov2680_1616x1216_30fps[] = { + {OV2680_8BIT, 0x3086, 0x00}, + {OV2680_8BIT, 0x3501, 0x48}, + {OV2680_8BIT, 0x3502, 0xe0}, + {OV2680_8BIT, 0x370a, 0x21}, + {OV2680_8BIT, 0x3801, 0x00}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x00}, + {OV2680_8BIT, 0x3804, 0x06}, + {OV2680_8BIT, 0x3805, 0x4f}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0xbf}, + {OV2680_8BIT, 0x3808, 0x06}, + {OV2680_8BIT, 0x3809, 0x50},//50},//4line for mirror and flip + {OV2680_8BIT, 0x380a, 0x04}, + {OV2680_8BIT, 0x380b, 0xc0},//c0}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xa8}, + {OV2680_8BIT, 0x380e, 0x05}, + {OV2680_8BIT, 0x380f, 0x0e}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x00}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x00}, + {OV2680_8BIT, 0x3814, 0x11}, + {OV2680_8BIT, 0x3815, 0x11}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x0b}, + {OV2680_8BIT, 0x5081, 0x01}, + {OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x06}, + {OV2680_8BIT, 0x5705, 0x50}, + {OV2680_8BIT, 0x5706, 0x04}, + {OV2680_8BIT, 0x5707, 0xcc}, + {OV2680_8BIT, 0x3820, 0xc0}, + {OV2680_8BIT, 0x3821, 0x00}, + // {OV2680_8BIT, 0x5090, 0x0C}, + {OV2680_TOK_TERM, 0, 0} + }; + + static struct ov2680_resolution ov2680_res_preview[] = { + { + .desc = "ov2680_1616x1216_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 66, + .fps = 30, + .used = 0, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x1216_30fps, + }, + { + .desc = "ov2680_1616x916_30fps", + .width = 1616, + .height = 916, + .fps = 30, + .pix_clk_freq = 66, + .used = 0, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x916_30fps, + }, +}; +#define N_RES_PREVIEW (ARRAY_SIZE(ov2680_res_preview)) + +static struct ov2680_resolution ov2680_res_still[] = { + { + .desc = "ov2680_1616x1216_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 66, + .fps = 30, + .used = 0, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x1216_30fps, + }, + { + .desc = "ov2680_1616x916_30fps", + .width = 1616, + .height = 916, + .fps = 30, + .pix_clk_freq = 66, + .used = 0, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x916_30fps, + }, +}; +#define N_RES_STILL (ARRAY_SIZE(ov2680_res_still)) + +static struct ov2680_resolution ov2680_res_video[] = { + { + .desc = "ov2680_1616x1216_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 66, + .fps = 30, + .used = 0, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x1216_30fps, + }, + { + .desc = "ov2680_720p_30fps", + .width = 1616, + .height = 916, + .fps = 30, + .pix_clk_freq = 66, + .used = 0, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x916_30fps, + }, +}; +#define N_RES_VIDEO (ARRAY_SIZE(ov2680_res_video)) + +static struct ov2680_resolution *ov2680_res = ov2680_res_preview; +static int N_RES = N_RES_PREVIEW; + + +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov2722.c b/drivers/staging/media/atomisp/i2c/ov2722.c new file mode 100644 index 0000000..b7afade --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov2722.c @@ -0,0 +1,1373 @@ +/* + * Support for OmniVision OV2722 1080p HD camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/string.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kmod.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/moduleparam.h> +#include <media/v4l2-device.h> +#include "../include/linux/atomisp_gmin_platform.h" +#include <linux/acpi.h> +#include <linux/io.h> + +#include "ov2722.h" + +/* i2c read/write stuff */ +static int ov2722_read_reg(struct i2c_client *client, + u16 data_length, u16 reg, u16 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[6]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != OV2722_8BIT && data_length != OV2722_16BIT + && data_length != OV2722_32BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0 , sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg >> 8); + data[1] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == OV2722_8BIT) + *val = (u8)data[0]; + else if (data_length == OV2722_16BIT) + *val = be16_to_cpu(*(u16 *)&data[0]); + else + *val = be32_to_cpu(*(u32 *)&data[0]); + + return 0; +} + +static int ov2722_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int ov2722_write_reg(struct i2c_client *client, u16 data_length, + u16 reg, u16 val) +{ + int ret; + unsigned char data[4] = {0}; + u16 *wreg = (u16 *)data; + const u16 len = data_length + sizeof(u16); /* 16-bit address + data */ + + if (data_length != OV2722_8BIT && data_length != OV2722_16BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = cpu_to_be16(reg); + + if (data_length == OV2722_8BIT) { + data[2] = (u8)(val); + } else { + /* OV2722_16BIT */ + u16 *wdata = (u16 *)&data[2]; + *wdata = cpu_to_be16(val); + } + + ret = ov2722_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * ov2722_write_reg_array - Initializes a list of OV2722 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __ov2722_flush_reg_array, __ov2722_buf_reg_array() and + * __ov2722_write_reg_is_consecutive() are internal functions to + * ov2722_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __ov2722_flush_reg_array(struct i2c_client *client, + struct ov2722_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u16) + ctrl->index; /* 16-bit address + data */ + ctrl->buffer.addr = cpu_to_be16(ctrl->buffer.addr); + ctrl->index = 0; + + return ov2722_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __ov2722_buf_reg_array(struct i2c_client *client, + struct ov2722_write_ctrl *ctrl, + const struct ov2722_reg *next) +{ + int size; + u16 *data16; + + switch (next->type) { + case OV2722_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case OV2722_16BIT: + size = 2; + data16 = (u16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u16) >= OV2722_MAX_WRITE_BUF_SIZE) + return __ov2722_flush_reg_array(client, ctrl); + + return 0; +} + +static int __ov2722_write_reg_is_consecutive(struct i2c_client *client, + struct ov2722_write_ctrl *ctrl, + const struct ov2722_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +static int ov2722_write_reg_array(struct i2c_client *client, + const struct ov2722_reg *reglist) +{ + const struct ov2722_reg *next = reglist; + struct ov2722_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != OV2722_TOK_TERM; next++) { + switch (next->type & OV2722_TOK_MASK) { + case OV2722_TOK_DELAY: + err = __ov2722_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__ov2722_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __ov2722_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __ov2722_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __ov2722_flush_reg_array(client, &ctrl); +} +static int ov2722_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV2722_FOCAL_LENGTH_NUM << 16) | OV2722_FOCAL_LENGTH_DEM; + return 0; +} + +static int ov2722_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (OV2722_F_NUMBER_DEFAULT_NUM << 16) | OV2722_F_NUMBER_DEM; + return 0; +} + +static int ov2722_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV2722_F_NUMBER_DEFAULT_NUM << 24) | + (OV2722_F_NUMBER_DEM << 16) | + (OV2722_F_NUMBER_DEFAULT_NUM << 8) | OV2722_F_NUMBER_DEM; + return 0; +} + +static int ov2722_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct ov2722_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov2722_device *dev = NULL; + struct atomisp_sensor_mode_data *buf = &info->data; + const unsigned int ext_clk_freq_hz = 19200000; + const unsigned int pll_invariant_div = 10; + unsigned int pix_clk_freq_hz; + u16 pre_pll_clk_div; + u16 pll_multiplier; + u16 op_pix_clk_div; + u16 reg_val; + int ret; + + if (!info) + return -EINVAL; + + dev = to_ov2722_sensor(sd); + + /* pixel clock calculattion */ + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_PLL_CTRL3, &pre_pll_clk_div); + if (ret) + return ret; + + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_PLL_MULTIPLIER, &pll_multiplier); + if (ret) + return ret; + + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_PLL_DEBUG_OPT, &op_pix_clk_div); + if (ret) + return ret; + + pre_pll_clk_div = (pre_pll_clk_div & 0x70) >> 4; + if (0 == pre_pll_clk_div) + return -EINVAL; + + pll_multiplier = pll_multiplier & 0x7f; + op_pix_clk_div = op_pix_clk_div & 0x03; + pix_clk_freq_hz = ext_clk_freq_hz / pre_pll_clk_div * pll_multiplier + * op_pix_clk_div / pll_invariant_div; + + dev->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + buf->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + + /* get integration time */ + buf->coarse_integration_time_min = OV2722_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + OV2722_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = OV2722_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + OV2722_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = OV2722_FINE_INTG_TIME_MIN; + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_H_CROP_START_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_V_CROP_START_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_H_CROP_END_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_end = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_V_CROP_END_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_end = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_H_OUTSIZE_H, ®_val); + if (ret) + return ret; + buf->output_width = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_V_OUTSIZE_H, ®_val); + if (ret) + return ret; + buf->output_height = reg_val; + + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static long __ov2722_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2722_device *dev = to_ov2722_sensor(sd); + u16 hts, vts; + int ret; + + dev_dbg(&client->dev, "set_exposure without group hold\n"); + + /* clear VTS_DIFF on manual mode */ + ret = ov2722_write_reg(client, OV2722_16BIT, OV2722_VTS_DIFF_H, 0); + if (ret) + return ret; + + hts = dev->pixels_per_line; + vts = dev->lines_per_frame; + + if ((coarse_itg + OV2722_COARSE_INTG_TIME_MAX_MARGIN) > vts) + vts = coarse_itg + OV2722_COARSE_INTG_TIME_MAX_MARGIN; + + coarse_itg <<= 4; + digitgain <<= 2; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_VTS_H, vts); + if (ret) + return ret; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_HTS_H, hts); + if (ret) + return ret; + + /* set exposure */ + ret = ov2722_write_reg(client, OV2722_8BIT, + OV2722_AEC_PK_EXPO_L, + coarse_itg & 0xff); + if (ret) + return ret; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_AEC_PK_EXPO_H, + (coarse_itg >> 8) & 0xfff); + if (ret) + return ret; + + /* set analog gain */ + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_AGC_ADJ_H, gain); + if (ret) + return ret; + + /* set digital gain */ + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_MWB_GAIN_R_H, digitgain); + if (ret) + return ret; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_MWB_GAIN_G_H, digitgain); + if (ret) + return ret; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_MWB_GAIN_B_H, digitgain); + + return ret; +} + +static int ov2722_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ov2722_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long ov2722_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + int exp = exposure->integration_time[0]; + int gain = exposure->gain[0]; + int digitgain = exposure->gain[1]; + + /* we should not accept the invalid value below. */ + if (gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + + return ov2722_set_exposure(sd, exp, gain, digitgain); +} + +static long ov2722_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return ov2722_s_exposure(sd, arg); + default: + return -EINVAL; + } + return 0; +} + +/* This returns the exposure time being used. This should only be used + * for filling in EXIF data, not for actual image processing. + */ +static int ov2722_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 reg_v, reg_v2; + int ret; + + /* get exposure */ + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_AEC_PK_EXPO_L, + ®_v); + if (ret) + goto err; + + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_AEC_PK_EXPO_M, + ®_v2); + if (ret) + goto err; + + reg_v += reg_v2 << 8; + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_AEC_PK_EXPO_H, + ®_v2); + if (ret) + goto err; + + *value = reg_v + (((u32)reg_v2 << 16)); +err: + return ret; +} + +static int ov2722_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov2722_device *dev = + container_of(ctrl->handler, struct ov2722_device, ctrl_handler); + int ret = 0; + unsigned int val; + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = ov2722_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = ov2722_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = ov2722_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = ov2722_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_LINK_FREQ: + val = ov2722_res[dev->fmt_idx].mipi_freq; + if (val == 0) + return -EINVAL; + + ctrl->val = val * 1000; /* To Hz */ + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .g_volatile_ctrl = ov2722_g_volatile_ctrl +}; + +struct v4l2_ctrl_config ov2722_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = OV2722_FOCAL_LENGTH_DEFAULT, + .max = OV2722_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = OV2722_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = OV2722_F_NUMBER_DEFAULT, + .max = OV2722_F_NUMBER_DEFAULT, + .step = 0x01, + .def = OV2722_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = OV2722_F_NUMBER_RANGE, + .max = OV2722_F_NUMBER_RANGE, + .step = 0x01, + .def = OV2722_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_LINK_FREQ, + .name = "Link Frequency", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 1, + .max = 1500000 * 1000, + .step = 1, + .def = 1, + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, + }, +}; + +static int ov2722_init(struct v4l2_subdev *sd) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + + mutex_lock(&dev->input_lock); + + /* restore settings */ + ov2722_res = ov2722_res_preview; + N_RES = N_RES_PREVIEW; + + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = -1; + struct ov2722_device *dev = to_ov2722_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + if (flag) { + ret = dev->platform_data->v1p8_ctrl(sd, 1); + if (ret == 0) { + ret = dev->platform_data->v2p8_ctrl(sd, 1); + if (ret) + dev->platform_data->v1p8_ctrl(sd, 0); + } + } else { + ret = dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + int ret = -1; + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + /* Note: the GPIO order is asymmetric: always RESET# + * before PWDN# when turning it on or off. + */ + ret = dev->platform_data->gpio0_ctrl(sd, flag); + /* + *ov2722 PWDN# active high when pull down,opposite to the convention + */ + ret |= dev->platform_data->gpio1_ctrl(sd, !flag); + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* according to DS, at least 5ms is needed between DOVDD and PWDN */ + usleep_range(5000, 6000); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + goto fail_power; + } + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* according to DS, 20ms is needed between PWDN and i2c access */ + msleep(20); + + return 0; + +fail_clk: + gpio_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int ov2722_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + if (on == 0) + return power_down(sd); + else { + ret = power_up(sd); + if (!ret) + return ov2722_init(sd); + } + return ret; +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between resolution and w/h. + * res->width/height smaller than w/h wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 800 +static int distance(struct ov2722_resolution *res, u32 w, u32 h) +{ + unsigned int w_ratio = (res->width << 13) / w; + unsigned int h_ratio; + int match; + + if (h == 0) + return -1; + h_ratio = (res->height << 13) / h; + if (h_ratio == 0) + return -1; + match = abs(((w_ratio << 13) / h_ratio) - 8192); + + if ((w_ratio < 8192) || (h_ratio < 8192) || + (match > LARGEST_ALLOWED_RATIO_MISMATCH)) + return -1; + + return w_ratio + h_ratio; +} + +/* Return the nearest higher resolution index */ +static int nearest_resolution_index(int w, int h) +{ + int i; + int idx = -1; + int dist; + int min_dist = INT_MAX; + struct ov2722_resolution *tmp_res = NULL; + + for (i = 0; i < N_RES; i++) { + tmp_res = &ov2722_res[i]; + dist = distance(tmp_res, w, h); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + } + } + + return idx; +} + +static int get_resolution_index(int w, int h) +{ + int i; + + for (i = 0; i < N_RES; i++) { + if (w != ov2722_res[i].width) + continue; + if (h != ov2722_res[i].height) + continue; + + return i; + } + + return -1; +} + +/* TODO: remove it. */ +static int startup(struct v4l2_subdev *sd) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + ret = ov2722_write_reg(client, OV2722_8BIT, + OV2722_SW_RESET, 0x01); + if (ret) { + dev_err(&client->dev, "ov2722 reset err.\n"); + return ret; + } + + ret = ov2722_write_reg_array(client, ov2722_res[dev->fmt_idx].regs); + if (ret) { + dev_err(&client->dev, "ov2722 write register err.\n"); + return ret; + } + + return ret; +} + +static int ov2722_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *ov2722_info = NULL; + int ret = 0; + int idx; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + ov2722_info = v4l2_get_subdev_hostdata(sd); + if (!ov2722_info) + return -EINVAL; + + mutex_lock(&dev->input_lock); + idx = nearest_resolution_index(fmt->width, fmt->height); + if (idx == -1) { + /* return the largest resolution */ + fmt->width = ov2722_res[N_RES - 1].width; + fmt->height = ov2722_res[N_RES - 1].height; + } else { + fmt->width = ov2722_res[idx].width; + fmt->height = ov2722_res[idx].height; + } + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + dev->fmt_idx = get_resolution_index(fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + dev_err(&client->dev, "get resolution fail\n"); + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + dev->pixels_per_line = ov2722_res[dev->fmt_idx].pixels_per_line; + dev->lines_per_frame = ov2722_res[dev->fmt_idx].lines_per_frame; + + ret = startup(sd); + if (ret) { + int i = 0; + dev_err(&client->dev, "ov2722 startup err, retry to power up\n"); + for (i = 0; i < OV2722_POWER_UP_RETRY_NUM; i++) { + dev_err(&client->dev, + "ov2722 retry to power up %d/%d times, result: ", + i + 1, OV2722_POWER_UP_RETRY_NUM); + power_down(sd); + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "power up failed, continue\n"); + continue; + } + ret = startup(sd); + if (ret) { + dev_err(&client->dev, " startup FAILED!\n"); + } else { + dev_err(&client->dev, " startup SUCCESS!\n"); + break; + } + } + if (ret) { + dev_err(&client->dev, "ov2722 startup err\n"); + goto err; + } + } + + ret = ov2722_get_intg_factor(client, ov2722_info, + &ov2722_res[dev->fmt_idx]); + if (ret) + dev_err(&client->dev, "failed to get integration_factor\n"); + +err: + mutex_unlock(&dev->input_lock); + return ret; +} +static int ov2722_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov2722_device *dev = to_ov2722_sensor(sd); + + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + fmt->width = ov2722_res[dev->fmt_idx].width; + fmt->height = ov2722_res[dev->fmt_idx].height; + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + + return 0; +} + +static int ov2722_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u16 high, low; + int ret; + u16 id; + u8 revision; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_CHIP_ID_H, &high); + if (ret) { + dev_err(&client->dev, "sensor_id_high = 0x%x\n", high); + return -ENODEV; + } + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_CHIP_ID_L, &low); + id = (high << 8) | low; + + if ((id != OV2722_ID) && (id != OV2720_ID)) { + dev_err(&client->dev, "sensor ID error\n"); + return -ENODEV; + } + + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_SUB_ID, &high); + revision = (u8) high & 0x0f; + + dev_dbg(&client->dev, "sensor_revision = 0x%x\n", revision); + dev_dbg(&client->dev, "detect ov2722 success\n"); + return 0; +} + +static int ov2722_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + mutex_lock(&dev->input_lock); + + ret = ov2722_write_reg(client, OV2722_8BIT, OV2722_SW_STREAM, + enable ? OV2722_START_STREAMING : + OV2722_STOP_STREAMING); + + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov2722_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!platform_data) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) { + dev_err(&client->dev, "platform init err\n"); + goto platform_init_failed; + } + } + + /* power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov2722 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "ov2722 power-up err.\n"); + goto fail_power_on; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = ov2722_detect(client); + if (ret) { + dev_err(&client->dev, "ov2722_detect err s_config.\n"); + goto fail_csi_cfg; + } + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov2722 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + return 0; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); +platform_init_failed: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov2722_g_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (!param) + return -EINVAL; + + if (param->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(&client->dev, "unsupported buffer type.\n"); + return -EINVAL; + } + + memset(param, 0, sizeof(*param)); + param->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + if (dev->fmt_idx >= 0 && dev->fmt_idx < N_RES) { + param->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + param->parm.capture.timeperframe.numerator = 1; + param->parm.capture.capturemode = dev->run_mode; + param->parm.capture.timeperframe.denominator = + ov2722_res[dev->fmt_idx].fps; + } + return 0; +} + +static int ov2722_s_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + dev->run_mode = param->parm.capture.capturemode; + + mutex_lock(&dev->input_lock); + switch (dev->run_mode) { + case CI_MODE_VIDEO: + ov2722_res = ov2722_res_video; + N_RES = N_RES_VIDEO; + break; + case CI_MODE_STILL_CAPTURE: + ov2722_res = ov2722_res_still; + N_RES = N_RES_STILL; + break; + default: + ov2722_res = ov2722_res_preview; + N_RES = N_RES_PREVIEW; + } + mutex_unlock(&dev->input_lock); + return 0; +} + +static int ov2722_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = ov2722_res[dev->fmt_idx].fps; + + return 0; +} + +static int ov2722_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + return 0; +} + +static int ov2722_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = ov2722_res[index].width; + fse->min_height = ov2722_res[index].height; + fse->max_width = ov2722_res[index].width; + fse->max_height = ov2722_res[index].height; + + return 0; + +} + + +static int ov2722_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = ov2722_res[dev->fmt_idx].skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops ov2722_sensor_ops = { + .g_skip_frames = ov2722_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops ov2722_video_ops = { + .s_stream = ov2722_s_stream, + .g_parm = ov2722_g_parm, + .s_parm = ov2722_s_parm, + .g_frame_interval = ov2722_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops ov2722_core_ops = { + .s_power = ov2722_s_power, + .ioctl = ov2722_ioctl, +}; + +static const struct v4l2_subdev_pad_ops ov2722_pad_ops = { + .enum_mbus_code = ov2722_enum_mbus_code, + .enum_frame_size = ov2722_enum_frame_size, + .get_fmt = ov2722_get_fmt, + .set_fmt = ov2722_set_fmt, +}; + +static const struct v4l2_subdev_ops ov2722_ops = { + .core = &ov2722_core_ops, + .video = &ov2722_video_ops, + .pad = &ov2722_pad_ops, + .sensor = &ov2722_sensor_ops, +}; + +static int ov2722_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov2722_device *dev = to_ov2722_sensor(sd); + dev_dbg(&client->dev, "ov2722_remove...\n"); + + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + + dev->platform_data->csi_cfg(sd, 0); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + v4l2_device_unregister_subdev(sd); + + atomisp_gmin_remove_subdev(sd); + + media_entity_cleanup(&dev->sd.entity); + kfree(dev); + + return 0; +} + +static int __ov2722_init_ctrl_handler(struct ov2722_device *dev) +{ + struct v4l2_ctrl_handler *hdl; + unsigned int i; + hdl = &dev->ctrl_handler; + v4l2_ctrl_handler_init(&dev->ctrl_handler, ARRAY_SIZE(ov2722_controls)); + for (i = 0; i < ARRAY_SIZE(ov2722_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &ov2722_controls[i], + NULL); + + dev->link_freq = v4l2_ctrl_find(&dev->ctrl_handler, V4L2_CID_LINK_FREQ); + + if (dev->ctrl_handler.error || !dev->link_freq) + return dev->ctrl_handler.error; + + dev->sd.ctrl_handler = hdl; + + return 0; +} + +static int ov2722_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ov2722_device *dev; + void *ovpdev; + int ret; + struct acpi_device *adev; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + dev->fmt_idx = 0; + v4l2_i2c_subdev_init(&(dev->sd), client, &ov2722_ops); + + ovpdev = client->dev.platform_data; + adev = ACPI_COMPANION(&client->dev); + if (adev) { + adev->power.flags.power_resources = 0; + ovpdev = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_grbg); + } + + ret = ov2722_s_config(&dev->sd, client->irq, ovpdev); + if (ret) + goto out_free; + + ret = __ov2722_init_ctrl_handler(dev); + if (ret) + goto out_ctrl_handler_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + ov2722_remove(client); + + if (ACPI_HANDLE(&client->dev)) + ret = atomisp_register_i2c_module(&dev->sd, ovpdev, RAW_CAMERA); + + return ret; + +out_ctrl_handler_free: + v4l2_ctrl_handler_free(&dev->ctrl_handler); + +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +MODULE_DEVICE_TABLE(i2c, ov2722_id); + +static struct acpi_device_id ov2722_acpi_match[] = { + { "INT33FB" }, + {}, +}; + +MODULE_DEVICE_TABLE(acpi, ov2722_acpi_match); + +static struct i2c_driver ov2722_driver = { + .driver = { + .name = OV2722_NAME, + .acpi_match_table = ACPI_PTR(ov2722_acpi_match), + }, + .probe = ov2722_probe, + .remove = ov2722_remove, + .id_table = ov2722_id, +}; + +static int init_ov2722(void) +{ + return i2c_add_driver(&ov2722_driver); +} + +static void exit_ov2722(void) +{ + + i2c_del_driver(&ov2722_driver); +} + +module_init(init_ov2722); +module_exit(exit_ov2722); + +MODULE_AUTHOR("Wei Liu <wei.liu@intel.com>"); +MODULE_DESCRIPTION("A low-level driver for OmniVision 2722 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/ov2722.h b/drivers/staging/media/atomisp/i2c/ov2722.h new file mode 100644 index 0000000..b0d4096 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov2722.h @@ -0,0 +1,1267 @@ +/* + * Support for OmniVision OV2722 1080p HD camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __OV2722_H__ +#define __OV2722_H__ +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/i2c.h> +#include <linux/delay.h> +#include <linux/videodev2.h> +#include <linux/spinlock.h> +#include <media/v4l2-subdev.h> +#include <media/v4l2-device.h> +#include <linux/v4l2-mediabus.h> +#include <media/media-entity.h> +#include <media/v4l2-ctrls.h> + +#include "../include/linux/atomisp_platform.h" + +#define OV2722_NAME "ov2722" + +#define OV2722_POWER_UP_RETRY_NUM 5 + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 0x2 +#define I2C_RETRY_COUNT 5 + +#define OV2722_FOCAL_LENGTH_NUM 278 /*2.78mm*/ +#define OV2722_FOCAL_LENGTH_DEM 100 +#define OV2722_F_NUMBER_DEFAULT_NUM 26 +#define OV2722_F_NUMBER_DEM 10 + +#define MAX_FMTS 1 + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV2722_F_NUMBER_DEFAULT 0x1a000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define OV2722_F_NUMBER_RANGE 0x1a0a1a0a +#define OV2720_ID 0x2720 +#define OV2722_ID 0x2722 + +#define OV2722_FINE_INTG_TIME_MIN 0 +#define OV2722_FINE_INTG_TIME_MAX_MARGIN 0 +#define OV2722_COARSE_INTG_TIME_MIN 1 +#define OV2722_COARSE_INTG_TIME_MAX_MARGIN 4 + +/* + * OV2722 System control registers + */ +#define OV2722_SW_SLEEP 0x0100 +#define OV2722_SW_RESET 0x0103 +#define OV2722_SW_STREAM 0x0100 + +#define OV2722_SC_CMMN_CHIP_ID_H 0x300A +#define OV2722_SC_CMMN_CHIP_ID_L 0x300B +#define OV2722_SC_CMMN_SCCB_ID 0x300C +#define OV2722_SC_CMMN_SUB_ID 0x302A /* process, version*/ + +#define OV2722_SC_CMMN_PAD_OEN0 0x3000 +#define OV2722_SC_CMMN_PAD_OEN1 0x3001 +#define OV2722_SC_CMMN_PAD_OEN2 0x3002 +#define OV2722_SC_CMMN_PAD_OUT0 0x3008 +#define OV2722_SC_CMMN_PAD_OUT1 0x3009 +#define OV2722_SC_CMMN_PAD_OUT2 0x300D +#define OV2722_SC_CMMN_PAD_SEL0 0x300E +#define OV2722_SC_CMMN_PAD_SEL1 0x300F +#define OV2722_SC_CMMN_PAD_SEL2 0x3010 + +#define OV2722_SC_CMMN_PAD_PK 0x3011 +#define OV2722_SC_CMMN_A_PWC_PK_O_13 0x3013 +#define OV2722_SC_CMMN_A_PWC_PK_O_14 0x3014 + +#define OV2722_SC_CMMN_CLKRST0 0x301A +#define OV2722_SC_CMMN_CLKRST1 0x301B +#define OV2722_SC_CMMN_CLKRST2 0x301C +#define OV2722_SC_CMMN_CLKRST3 0x301D +#define OV2722_SC_CMMN_CLKRST4 0x301E +#define OV2722_SC_CMMN_CLKRST5 0x3005 +#define OV2722_SC_CMMN_PCLK_DIV_CTRL 0x3007 +#define OV2722_SC_CMMN_CLOCK_SEL 0x3020 +#define OV2722_SC_SOC_CLKRST5 0x3040 + +#define OV2722_SC_CMMN_PLL_CTRL0 0x3034 +#define OV2722_SC_CMMN_PLL_CTRL1 0x3035 +#define OV2722_SC_CMMN_PLL_CTRL2 0x3039 +#define OV2722_SC_CMMN_PLL_CTRL3 0x3037 +#define OV2722_SC_CMMN_PLL_MULTIPLIER 0x3036 +#define OV2722_SC_CMMN_PLL_DEBUG_OPT 0x3038 +#define OV2722_SC_CMMN_PLLS_CTRL0 0x303A +#define OV2722_SC_CMMN_PLLS_CTRL1 0x303B +#define OV2722_SC_CMMN_PLLS_CTRL2 0x303C +#define OV2722_SC_CMMN_PLLS_CTRL3 0x303D + +#define OV2722_SC_CMMN_MIPI_PHY_16 0x3016 +#define OV2722_SC_CMMN_MIPI_PHY_17 0x3017 +#define OV2722_SC_CMMN_MIPI_SC_CTRL_18 0x3018 +#define OV2722_SC_CMMN_MIPI_SC_CTRL_19 0x3019 +#define OV2722_SC_CMMN_MIPI_SC_CTRL_21 0x3021 +#define OV2722_SC_CMMN_MIPI_SC_CTRL_22 0x3022 + +#define OV2722_AEC_PK_EXPO_H 0x3500 +#define OV2722_AEC_PK_EXPO_M 0x3501 +#define OV2722_AEC_PK_EXPO_L 0x3502 +#define OV2722_AEC_MANUAL_CTRL 0x3503 +#define OV2722_AGC_ADJ_H 0x3508 +#define OV2722_AGC_ADJ_L 0x3509 +#define OV2722_VTS_DIFF_H 0x350c +#define OV2722_VTS_DIFF_L 0x350d +#define OV2722_GROUP_ACCESS 0x3208 +#define OV2722_HTS_H 0x380c +#define OV2722_HTS_L 0x380d +#define OV2722_VTS_H 0x380e +#define OV2722_VTS_L 0x380f + +#define OV2722_MWB_GAIN_R_H 0x5186 +#define OV2722_MWB_GAIN_R_L 0x5187 +#define OV2722_MWB_GAIN_G_H 0x5188 +#define OV2722_MWB_GAIN_G_L 0x5189 +#define OV2722_MWB_GAIN_B_H 0x518a +#define OV2722_MWB_GAIN_B_L 0x518b + +#define OV2722_H_CROP_START_H 0x3800 +#define OV2722_H_CROP_START_L 0x3801 +#define OV2722_V_CROP_START_H 0x3802 +#define OV2722_V_CROP_START_L 0x3803 +#define OV2722_H_CROP_END_H 0x3804 +#define OV2722_H_CROP_END_L 0x3805 +#define OV2722_V_CROP_END_H 0x3806 +#define OV2722_V_CROP_END_L 0x3807 +#define OV2722_H_OUTSIZE_H 0x3808 +#define OV2722_H_OUTSIZE_L 0x3809 +#define OV2722_V_OUTSIZE_H 0x380a +#define OV2722_V_OUTSIZE_L 0x380b + +#define OV2722_START_STREAMING 0x01 +#define OV2722_STOP_STREAMING 0x00 + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct ov2722_resolution { + u8 *desc; + const struct ov2722_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u32 skip_frames; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; + int mipi_freq; +}; + +struct ov2722_format { + u8 *desc; + u32 pixelformat; + struct ov2722_reg *regs; +}; + +/* + * ov2722 device structure. + */ +struct ov2722_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + + struct camera_sensor_platform_data *platform_data; + int vt_pix_clk_freq_mhz; + int fmt_idx; + int run_mode; + u16 pixels_per_line; + u16 lines_per_frame; + u8 res; + u8 type; + + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *link_freq; +}; + +enum ov2722_tok_type { + OV2722_8BIT = 0x0001, + OV2722_16BIT = 0x0002, + OV2722_32BIT = 0x0004, + OV2722_TOK_TERM = 0xf000, /* terminating token for reg list */ + OV2722_TOK_DELAY = 0xfe00, /* delay token for reg list */ + OV2722_TOK_MASK = 0xfff0 +}; + +/** + * struct ov2722_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct ov2722_reg { + enum ov2722_tok_type type; + u16 reg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +#define to_ov2722_sensor(x) container_of(x, struct ov2722_device, sd) + +#define OV2722_MAX_WRITE_BUF_SIZE 30 + +struct ov2722_write_buffer { + u16 addr; + u8 data[OV2722_MAX_WRITE_BUF_SIZE]; +}; + +struct ov2722_write_ctrl { + int index; + struct ov2722_write_buffer buffer; +}; + +static const struct i2c_device_id ov2722_id[] = { + {OV2722_NAME, 0}, + {} +}; + +/* + * Register settings for various resolution + */ +static struct ov2722_reg const ov2722_QVGA_30fps[] = { + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x0c}, + {OV2722_8BIT, 0x373a, 0x1c}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x0c}, + {OV2722_8BIT, 0x3705, 0x06}, + {OV2722_8BIT, 0x3730, 0x0e}, + {OV2722_8BIT, 0x3704, 0x1c}, + {OV2722_8BIT, 0x3f06, 0x00}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0x46}, + {OV2722_8BIT, 0x371e, 0x00}, + {OV2722_8BIT, 0x371f, 0x63}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x01}, + {OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32 */ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0x95}, /* H crop end: 1685 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x27}, /* V crop end: 1063 */ + {OV2722_8BIT, 0x3808, 0x01}, + {OV2722_8BIT, 0x3809, 0x50}, /* H output size: 336 */ + {OV2722_8BIT, 0x380a, 0x01}, + {OV2722_8BIT, 0x380b, 0x00}, /* V output size: 256 */ + + /* H blank timing */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0xc0}, + {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ + {OV2722_8BIT, 0x3814, 0x71}, + {OV2722_8BIT, 0x3815, 0x71}, + {OV2722_8BIT, 0x3612, 0x49}, + {OV2722_8BIT, 0x3618, 0x00}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0xc3}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x77}, + {OV2722_8BIT, 0x3a0d, 0x00}, + {OV2722_8BIT, 0x3a0e, 0x00}, + {OV2722_8BIT, 0x4520, 0x09}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x63}, + {OV2722_8BIT, 0x3634, 0x24}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xff}, + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ + {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ + {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ + {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + + /* Added for power optimization */ + {OV2722_8BIT, 0x3000, 0x00}, + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3011, 0x22}, + {OV2722_8BIT, 0x3a00, 0x58}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x46}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x10}, + {OV2722_TOK_TERM, 0, 0}, + +}; + +static struct ov2722_reg const ov2722_480P_30fps[] = { + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x18}, + {OV2722_8BIT, 0x373a, 0x3c}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x1d}, + {OV2722_8BIT, 0x3705, 0x12}, + {OV2722_8BIT, 0x3730, 0x1f}, + {OV2722_8BIT, 0x3704, 0x3f}, + {OV2722_8BIT, 0x3f06, 0x1d}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0x83}, + {OV2722_8BIT, 0x371e, 0x00}, + {OV2722_8BIT, 0x371f, 0xbd}, + {OV2722_8BIT, 0x3708, 0x63}, + {OV2722_8BIT, 0x3709, 0x52}, + {OV2722_8BIT, 0x3800, 0x00}, + {OV2722_8BIT, 0x3801, 0xf2}, /* H crop start: 322 - 80 = 242*/ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32*/ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0xBB}, /* H crop end: 1643 + 80 = 1723*/ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x03}, /* V crop end: 1027*/ + {OV2722_8BIT, 0x3808, 0x02}, + {OV2722_8BIT, 0x3809, 0xE0}, /* H output size: 656 +80 = 736*/ + {OV2722_8BIT, 0x380a, 0x01}, + {OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */ + + /* H blank timing */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ + {OV2722_8BIT, 0x3814, 0x31}, + {OV2722_8BIT, 0x3815, 0x31}, + {OV2722_8BIT, 0x3612, 0x4b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x02}, + {OV2722_8BIT, 0x3a09, 0x67}, + {OV2722_8BIT, 0x3a0a, 0x02}, + {OV2722_8BIT, 0x3a0b, 0x00}, + {OV2722_8BIT, 0x3a0d, 0x00}, + {OV2722_8BIT, 0x3a0e, 0x00}, + {OV2722_8BIT, 0x4520, 0x0a}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x63}, + {OV2722_8BIT, 0x3634, 0x24}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xff}, + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ + {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ + {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ + {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + + /* Added for power optimization */ + {OV2722_8BIT, 0x3000, 0x00}, + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3011, 0x22}, + {OV2722_8BIT, 0x3a00, 0x58}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x46}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x10}, + {OV2722_TOK_TERM, 0, 0}, +}; + +static struct ov2722_reg const ov2722_VGA_30fps[] = { + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x18}, + {OV2722_8BIT, 0x373a, 0x3c}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x1d}, + {OV2722_8BIT, 0x3705, 0x12}, + {OV2722_8BIT, 0x3730, 0x1f}, + {OV2722_8BIT, 0x3704, 0x3f}, + {OV2722_8BIT, 0x3f06, 0x1d}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0x83}, + {OV2722_8BIT, 0x371e, 0x00}, + {OV2722_8BIT, 0x371f, 0xbd}, + {OV2722_8BIT, 0x3708, 0x63}, + {OV2722_8BIT, 0x3709, 0x52}, + {OV2722_8BIT, 0x3800, 0x01}, + {OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32*/ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0x6B}, /* H crop end: 1643*/ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x03}, /* V crop end: 1027*/ + {OV2722_8BIT, 0x3808, 0x02}, + {OV2722_8BIT, 0x3809, 0x90}, /* H output size: 656 */ + {OV2722_8BIT, 0x380a, 0x01}, + {OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */ + + /* H blank timing */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ + {OV2722_8BIT, 0x3814, 0x31}, + {OV2722_8BIT, 0x3815, 0x31}, + {OV2722_8BIT, 0x3612, 0x4b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x02}, + {OV2722_8BIT, 0x3a09, 0x67}, + {OV2722_8BIT, 0x3a0a, 0x02}, + {OV2722_8BIT, 0x3a0b, 0x00}, + {OV2722_8BIT, 0x3a0d, 0x00}, + {OV2722_8BIT, 0x3a0e, 0x00}, + {OV2722_8BIT, 0x4520, 0x0a}, + {OV2722_8BIT, 0x4837, 0x29}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x63}, + {OV2722_8BIT, 0x3634, 0x24}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xff}, + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ + {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ + {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ + {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + + /* Added for power optimization */ + {OV2722_8BIT, 0x3000, 0x00}, + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3011, 0x22}, + {OV2722_8BIT, 0x3a00, 0x58}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x46}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x10}, + {OV2722_TOK_TERM, 0, 0}, +}; + +static struct ov2722_reg const ov2722_1632_1092_30fps[] = { + {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for + a whole frame complete.(vblank) */ + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x10}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x0d}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x00}, + {OV2722_8BIT, 0x3801, 0x9E}, /* H crop start: 158 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ + {OV2722_8BIT, 0x3804, 0x07}, + {OV2722_8BIT, 0x3805, 0x05}, /* H crop end: 1797 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ + + {OV2722_8BIT, 0x3808, 0x06}, + {OV2722_8BIT, 0x3809, 0x60}, /* H output size: 1632 */ + {OV2722_8BIT, 0x380a, 0x04}, + {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x0b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x23}, + {OV2722_8BIT, 0x3634, 0x54}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ + {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, + {OV2722_8BIT, 0x5184, 0xb0}, + {OV2722_8BIT, 0x5185, 0xb0}, + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */ + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x3F}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x00}, + {OV2722_TOK_TERM, 0, 0} +}; + +static struct ov2722_reg const ov2722_1452_1092_30fps[] = { + {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for + a whole frame complete.(vblank) */ + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x10}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x0d}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x00}, + {OV2722_8BIT, 0x3801, 0xF8}, /* H crop start: 248 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0xab}, /* H crop end: 1707 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ + {OV2722_8BIT, 0x3808, 0x05}, + {OV2722_8BIT, 0x3809, 0xac}, /* H output size: 1452 */ + {OV2722_8BIT, 0x380a, 0x04}, + {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x0b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x23}, + {OV2722_8BIT, 0x3634, 0x54}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ + {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, + {OV2722_8BIT, 0x5184, 0xb0}, + {OV2722_8BIT, 0x5185, 0xb0}, + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */ + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x3F}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x00}, + {OV2722_TOK_TERM, 0, 0} +}; +static struct ov2722_reg const ov2722_1M3_30fps[] = { + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x10}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x0d}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x01}, + {OV2722_8BIT, 0x3801, 0x4a}, /* H crop start: 330 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x03}, /* V crop start: 3 */ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0xe1}, /* H crop end: 1761 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x47}, /* V crop end: 1095 */ + {OV2722_8BIT, 0x3808, 0x05}, + {OV2722_8BIT, 0x3809, 0x88}, /* H output size: 1416 */ + {OV2722_8BIT, 0x380a, 0x04}, + {OV2722_8BIT, 0x380b, 0x0a}, /* V output size: 1034 */ + + /* H blank timing */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x05}, /* H window offset: 5 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* flip isp */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x0b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x23}, + {OV2722_8BIT, 0x3634, 0x54}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcf}, + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ + {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ + {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ + {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + + /* Added for power optimization */ + {OV2722_8BIT, 0x3000, 0x00}, + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x46}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x10}, + {OV2722_TOK_TERM, 0, 0}, +}; + +static struct ov2722_reg const ov2722_1080p_30fps[] = { + {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for a whole + frame complete.(vblank) */ + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x2b}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x28}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x00}, + {OV2722_8BIT, 0x3801, 0x08}, /* H crop start: 8 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ + {OV2722_8BIT, 0x3804, 0x07}, + {OV2722_8BIT, 0x3805, 0x9b}, /* H crop end: 1947 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ + {OV2722_8BIT, 0x3808, 0x07}, + {OV2722_8BIT, 0x3809, 0x8c}, /* H output size: 1932 */ + {OV2722_8BIT, 0x380a, 0x04}, + {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x14}, /* H timing: 2068 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0x5a}, /* V timing: 1114 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x4b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x63}, + {OV2722_8BIT, 0x3634, 0x24}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcd}, /* manual 3a */ + {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, + {OV2722_8BIT, 0x5184, 0xb0}, + {OV2722_8BIT, 0x5185, 0xb0}, + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x24}, /* 345.6 MHz */ + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3011, 0x22}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x3F}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x00}, + {OV2722_TOK_TERM, 0, 0} +}; + +static struct ov2722_reg const ov2722_720p_30fps[] = { + {OV2722_8BIT, 0x3021, 0x03}, + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x10}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x0d}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x01}, + {OV2722_8BIT, 0x3801, 0x40}, /* H crop start: 320 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0xb1}, /* V crop start: 177 */ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0x55}, /* H crop end: 1621 */ + {OV2722_8BIT, 0x3806, 0x03}, + {OV2722_8BIT, 0x3807, 0x95}, /* V crop end: 918 */ + {OV2722_8BIT, 0x3808, 0x05}, + {OV2722_8BIT, 0x3809, 0x10}, /* H output size: 0x0788==1928 */ + {OV2722_8BIT, 0x380a, 0x02}, + {OV2722_8BIT, 0x380b, 0xe0}, /* output size: 0x02DE==734 */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H timing: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa3}, /* V timing: 1187 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x0b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x23}, + {OV2722_8BIT, 0x3634, 0x54}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ + {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, + {OV2722_8BIT, 0x5184, 0xb0}, + {OV2722_8BIT, 0x5185, 0xb0}, + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, /* {0x3036, 0x2c}, //422.4 MHz */ + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x3F}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x00}, + {OV2722_TOK_TERM, 0, 0}, +}; + +struct ov2722_resolution ov2722_res_preview[] = { + { + .desc = "ov2722_1632_1092_30fps", + .width = 1632, + .height = 1092, + .fps = 30, + .pix_clk_freq = 85, + .used = 0, + .pixels_per_line = 2260, + .lines_per_frame = 1244, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1632_1092_30fps, + .mipi_freq = 422400, + }, + { + .desc = "ov2722_1452_1092_30fps", + .width = 1452, + .height = 1092, + .fps = 30, + .pix_clk_freq = 85, + .used = 0, + .pixels_per_line = 2260, + .lines_per_frame = 1244, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1452_1092_30fps, + .mipi_freq = 422400, + }, + { + .desc = "ov2722_1080P_30fps", + .width = 1932, + .height = 1092, + .pix_clk_freq = 69, + .fps = 30, + .used = 0, + .pixels_per_line = 2068, + .lines_per_frame = 1114, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1080p_30fps, + .mipi_freq = 345600, + }, +}; +#define N_RES_PREVIEW (ARRAY_SIZE(ov2722_res_preview)) + +struct ov2722_resolution ov2722_res_still[] = { + { + .desc = "ov2722_480P_30fps", + .width = 1632, + .height = 1092, + .fps = 30, + .pix_clk_freq = 85, + .used = 0, + .pixels_per_line = 2260, + .lines_per_frame = 1244, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1632_1092_30fps, + .mipi_freq = 422400, + }, + { + .desc = "ov2722_1452_1092_30fps", + .width = 1452, + .height = 1092, + .fps = 30, + .pix_clk_freq = 85, + .used = 0, + .pixels_per_line = 2260, + .lines_per_frame = 1244, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1452_1092_30fps, + .mipi_freq = 422400, + }, + { + .desc = "ov2722_1080P_30fps", + .width = 1932, + .height = 1092, + .pix_clk_freq = 69, + .fps = 30, + .used = 0, + .pixels_per_line = 2068, + .lines_per_frame = 1114, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1080p_30fps, + .mipi_freq = 345600, + }, +}; +#define N_RES_STILL (ARRAY_SIZE(ov2722_res_still)) + +struct ov2722_resolution ov2722_res_video[] = { + { + .desc = "ov2722_QVGA_30fps", + .width = 336, + .height = 256, + .fps = 30, + .pix_clk_freq = 73, + .used = 0, + .pixels_per_line = 2048, + .lines_per_frame = 1184, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_QVGA_30fps, + .mipi_freq = 364800, + }, + { + .desc = "ov2722_480P_30fps", + .width = 736, + .height = 496, + .fps = 30, + .pix_clk_freq = 73, + .used = 0, + .pixels_per_line = 2048, + .lines_per_frame = 1184, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_480P_30fps, + }, + { + .desc = "ov2722_1080P_30fps", + .width = 1932, + .height = 1092, + .pix_clk_freq = 69, + .fps = 30, + .used = 0, + .pixels_per_line = 2068, + .lines_per_frame = 1114, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1080p_30fps, + .mipi_freq = 345600, + }, +}; +#define N_RES_VIDEO (ARRAY_SIZE(ov2722_res_video)) + +static struct ov2722_resolution *ov2722_res = ov2722_res_preview; +static int N_RES = N_RES_PREVIEW; +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov5693/Kconfig b/drivers/staging/media/atomisp/i2c/ov5693/Kconfig new file mode 100644 index 0000000..9fb1bff --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/Kconfig @@ -0,0 +1,11 @@ +config VIDEO_OV5693 + tristate "Omnivision ov5693 sensor support" + depends on I2C && VIDEO_V4L2 + ---help--- + This is a Video4Linux2 sensor-level driver for the Micron + ov5693 5 Mpixel camera. + + ov5693 is video camera sensor. + + It currently only works with the atomisp driver. + diff --git a/drivers/staging/media/atomisp/i2c/ov5693/Makefile b/drivers/staging/media/atomisp/i2c/ov5693/Makefile new file mode 100644 index 0000000..fceb9e9 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_VIDEO_OV5693) += ov5693.o + +ccflags-y += -Werror diff --git a/drivers/staging/media/atomisp/i2c/ov5693/ad5823.h b/drivers/staging/media/atomisp/i2c/ov5693/ad5823.h new file mode 100644 index 0000000..2dd8949 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/ad5823.h @@ -0,0 +1,67 @@ +/* + * Support for AD5823 VCM. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __AD5823_H__ +#define __AD5823_H__ + +#include <linux/types.h> + + +#define AD5823_VCM_ADDR 0x0c + +#define AD5823_REG_RESET 0x01 +#define AD5823_REG_MODE 0x02 +#define AD5823_REG_VCM_MOVE_TIME 0x03 +#define AD5823_REG_VCM_CODE_MSB 0x04 +#define AD5823_REG_VCM_CODE_LSB 0x05 +#define AD5823_REG_VCM_THRESHOLD_MSB 0x06 +#define AD5823_REG_VCM_THRESHOLD_LSB 0x07 + +#define AD5823_REG_LENGTH 0x1 + +#define AD5823_RING_CTRL_ENABLE 0x04 +#define AD5823_RING_CTRL_DISABLE 0x00 + +#define AD5823_RESONANCE_PERIOD 100000 +#define AD5823_RESONANCE_COEF 512 +#define AD5823_HIGH_FREQ_RANGE 0x80 + +#define VCM_CODE_MSB_MASK 0xfc +#define AD5823_INIT_FOCUS_POS 350 + +enum ad5823_tok_type { + AD5823_8BIT = 0x1, + AD5823_16BIT = 0x2, +}; + +enum ad5823_vcm_mode { + AD5823_ARC_RES0 = 0x0, /* Actuator response control RES1 */ + AD5823_ARC_RES1 = 0x1, /* Actuator response control RES0.5 */ + AD5823_ARC_RES2 = 0x2, /* Actuator response control RES2 */ + AD5823_ESRC = 0x3, /* Enhanced slew rate control */ + AD5823_DIRECT = 0x4, /* Direct control */ +}; + +#define AD5823_INVALID_CONFIG 0xffffffff +#define AD5823_MAX_FOCUS_POS 1023 +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov5693/ov5693.c b/drivers/staging/media/atomisp/i2c/ov5693/ov5693.c new file mode 100644 index 0000000..5e9dafe --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/ov5693.c @@ -0,0 +1,2066 @@ +/* + * Support for OmniVision OV5693 1080p HD camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/string.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kmod.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/moduleparam.h> +#include <media/v4l2-device.h> +#include <linux/io.h> +#include <linux/acpi.h> +#include "../../include/linux/atomisp_gmin_platform.h" + +#include "ov5693.h" +#include "ad5823.h" + +#define __cci_delay(t) \ + do { \ + if ((t) < 10) { \ + usleep_range((t) * 1000, ((t) + 1) * 1000); \ + } else { \ + msleep((t)); \ + } \ + } while (0) + +/* Value 30ms reached through experimentation on byt ecs. + * The DS specifies a much lower value but when using a smaller value + * the I2C bus sometimes locks up permanently when starting the camera. + * This issue could not be reproduced on cht, so we can reduce the + * delay value to a lower value when insmod. + */ +static uint up_delay = 30; +module_param(up_delay, uint, 0644); +MODULE_PARM_DESC(up_delay, "Delay prior to the first CCI transaction for ov5693"); + +static int vcm_ad_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + int err; + struct i2c_msg msg; + u8 buf[2]; + + buf[0] = reg; + buf[1] = val; + + msg.addr = VCM_ADDR; + msg.flags = 0; + msg.len = 2; + msg.buf = &buf[0]; + + err = i2c_transfer(client->adapter, &msg, 1); + if (err != 1) { + dev_err(&client->dev, "%s: vcm i2c fail, err code = %d\n", + __func__, err); + return -EIO; + } + return 0; +} + +static int ad5823_i2c_write(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2]; + buf[0] = reg; + buf[1] = val; + msg.addr = AD5823_VCM_ADDR; + msg.flags = 0; + msg.len = 0x02; + msg.buf = &buf[0]; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +static int ad5823_i2c_read(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2]; + buf[0] = reg; + buf[1] = 0; + + msg[0].addr = AD5823_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 0x01; + msg[0].buf = &buf[0]; + + msg[1].addr = 0x0c; + msg[1].flags = I2C_M_RD; + msg[1].len = 0x01; + msg[1].buf = &buf[1]; + *val = 0; + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + return 0; +} + + +static const uint32_t ov5693_embedded_effective_size = 28; + +/* i2c read/write stuff */ +static int ov5693_read_reg(struct i2c_client *client, + u16 data_length, u16 reg, u16 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[6]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != OV5693_8BIT && data_length != OV5693_16BIT + && data_length != OV5693_32BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0 , sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg >> 8); + data[1] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == OV5693_8BIT) + *val = (u8)data[0]; + else if (data_length == OV5693_16BIT) + *val = be16_to_cpu(*(u16 *)&data[0]); + else + *val = be32_to_cpu(*(u32 *)&data[0]); + + return 0; +} + +static int ov5693_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int vcm_dw_i2c_write(struct i2c_client *client, u16 data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + u16 val; + + val = cpu_to_be16(data); + msg.addr = VCM_ADDR; + msg.flags = 0; + msg.len = OV5693_16BIT; + msg.buf = (u8 *)&val; + + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +/* Theory: per datasheet, the two VCMs both allow for a 2-byte read. + * The DW9714 doesn't actually specify what this does (it has a + * two-byte write-only protocol, but specifies the read sequence as + * legal), but it returns the same data (zeroes) always, after an + * undocumented initial NAK. The AD5823 has a one-byte address + * register to which all writes go, and subsequent reads will cycle + * through the 8 bytes of registers. Notably, the default values (the + * device is always power-cycled affirmatively, so we can rely on + * these) in AD5823 are not pairwise repetitions of the same 16 bit + * word. So all we have to do is sequentially read two bytes at a + * time and see if we detect a difference in any of the first four + * pairs. */ +static int vcm_detect(struct i2c_client *client) +{ + int i, ret; + struct i2c_msg msg; + u16 data0 = 0, data; + for (i = 0; i < 4; i++) { + msg.addr = VCM_ADDR; + msg.flags = I2C_M_RD; + msg.len = sizeof(data); + msg.buf = (u8 *)&data; + ret = i2c_transfer(client->adapter, &msg, 1); + + /* DW9714 always fails the first read and returns + * zeroes for subsequent ones */ + if (i == 0 && ret == -EREMOTEIO) { + data0 = 0; + continue; + } + + if (i == 0) + data0 = data; + + if (data != data0) + return VCM_AD5823; + } + return ret == 1 ? VCM_DW9714 : ret; +} + +static int ov5693_write_reg(struct i2c_client *client, u16 data_length, + u16 reg, u16 val) +{ + int ret; + unsigned char data[4] = {0}; + u16 *wreg = (u16 *)data; + const u16 len = data_length + sizeof(u16); /* 16-bit address + data */ + + if (data_length != OV5693_8BIT && data_length != OV5693_16BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = cpu_to_be16(reg); + + if (data_length == OV5693_8BIT) { + data[2] = (u8)(val); + } else { + /* OV5693_16BIT */ + u16 *wdata = (u16 *)&data[2]; + *wdata = cpu_to_be16(val); + } + + ret = ov5693_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * ov5693_write_reg_array - Initializes a list of OV5693 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __ov5693_flush_reg_array, __ov5693_buf_reg_array() and + * __ov5693_write_reg_is_consecutive() are internal functions to + * ov5693_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __ov5693_flush_reg_array(struct i2c_client *client, + struct ov5693_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u16) + ctrl->index; /* 16-bit address + data */ + ctrl->buffer.addr = cpu_to_be16(ctrl->buffer.addr); + ctrl->index = 0; + + return ov5693_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __ov5693_buf_reg_array(struct i2c_client *client, + struct ov5693_write_ctrl *ctrl, + const struct ov5693_reg *next) +{ + int size; + u16 *data16; + + switch (next->type) { + case OV5693_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case OV5693_16BIT: + size = 2; + data16 = (u16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u16) >= OV5693_MAX_WRITE_BUF_SIZE) + return __ov5693_flush_reg_array(client, ctrl); + + return 0; +} + +static int __ov5693_write_reg_is_consecutive(struct i2c_client *client, + struct ov5693_write_ctrl *ctrl, + const struct ov5693_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +static int ov5693_write_reg_array(struct i2c_client *client, + const struct ov5693_reg *reglist) +{ + const struct ov5693_reg *next = reglist; + struct ov5693_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != OV5693_TOK_TERM; next++) { + switch (next->type & OV5693_TOK_MASK) { + case OV5693_TOK_DELAY: + err = __ov5693_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__ov5693_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __ov5693_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __ov5693_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, + "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __ov5693_flush_reg_array(client, &ctrl); +} +static int ov5693_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV5693_FOCAL_LENGTH_NUM << 16) | OV5693_FOCAL_LENGTH_DEM; + return 0; +} + +static int ov5693_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (OV5693_F_NUMBER_DEFAULT_NUM << 16) | OV5693_F_NUMBER_DEM; + return 0; +} + +static int ov5693_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV5693_F_NUMBER_DEFAULT_NUM << 24) | + (OV5693_F_NUMBER_DEM << 16) | + (OV5693_F_NUMBER_DEFAULT_NUM << 8) | OV5693_F_NUMBER_DEM; + return 0; +} + +static int ov5693_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + + *val = ov5693_res[dev->fmt_idx].bin_factor_x; + + return 0; +} + +static int ov5693_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + + *val = ov5693_res[dev->fmt_idx].bin_factor_y; + + return 0; +} + +static int ov5693_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct ov5693_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct atomisp_sensor_mode_data *buf = &info->data; + unsigned int pix_clk_freq_hz; + u16 reg_val; + int ret; + + if (info == NULL) + return -EINVAL; + + /* pixel clock */ + pix_clk_freq_hz = res->pix_clk_freq * 1000000; + + dev->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + buf->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + + /* get integration time */ + buf->coarse_integration_time_min = OV5693_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + OV5693_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = OV5693_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + OV5693_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = OV5693_FINE_INTG_TIME_MIN; + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_HORIZONTAL_START_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_VERTICAL_START_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_HORIZONTAL_END_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_end = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_VERTICAL_END_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_end = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_HORIZONTAL_OUTPUT_SIZE_H, ®_val); + if (ret) + return ret; + buf->output_width = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_VERTICAL_OUTPUT_SIZE_H, ®_val); + if (ret) + return ret; + buf->output_height = reg_val; + + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static long __ov5693_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov5693_device *dev = to_ov5693_sensor(sd); + u16 vts, hts; + int ret, exp_val; + + hts = ov5693_res[dev->fmt_idx].pixels_per_line; + vts = ov5693_res[dev->fmt_idx].lines_per_frame; + /*If coarse_itg is larger than 1<<15, can not write to reg directly. + The way is to write coarse_itg/2 to the reg, meanwhile write 2*hts + to the reg. */ + if (coarse_itg > (1 << 15)) { + hts = hts * 2; + coarse_itg = (int)coarse_itg / 2; + } + /* group hold */ + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_GROUP_ACCESS, 0x00); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_GROUP_ACCESS); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_TIMING_HTS_H, (hts >> 8) & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_TIMING_HTS_H); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_TIMING_HTS_L, hts & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_TIMING_HTS_L); + return ret; + } + /* Increase the VTS to match exposure + MARGIN */ + if (coarse_itg > vts - OV5693_INTEGRATION_TIME_MARGIN) + vts = (u16) coarse_itg + OV5693_INTEGRATION_TIME_MARGIN; + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_TIMING_VTS_H, (vts >> 8) & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_TIMING_VTS_H); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_TIMING_VTS_L, vts & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_TIMING_VTS_L); + return ret; + } + + /* set exposure */ + + /* Lower four bit should be 0*/ + exp_val = coarse_itg << 4; + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_L, exp_val & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_EXPOSURE_L); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_M, (exp_val >> 8) & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_EXPOSURE_M); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_H, (exp_val >> 16) & 0x0F); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_EXPOSURE_H); + return ret; + } + + /* Analog gain */ + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_AGC_L, gain & 0xff); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_AGC_L); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_AGC_H, (gain >> 8) & 0xff); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_AGC_H); + return ret; + } + + /* Digital gain */ + if (digitgain) { + ret = ov5693_write_reg(client, OV5693_16BIT, + OV5693_MWB_RED_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_MWB_RED_GAIN_H); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_16BIT, + OV5693_MWB_GREEN_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_MWB_RED_GAIN_H); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_16BIT, + OV5693_MWB_BLUE_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_MWB_RED_GAIN_H); + return ret; + } + } + + /* End group */ + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_GROUP_ACCESS, 0x10); + if (ret) + return ret; + + /* Delay launch group */ + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_GROUP_ACCESS, 0xa0); + if (ret) + return ret; + return ret; +} + +static int ov5693_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ov5693_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long ov5693_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + u16 coarse_itg = exposure->integration_time[0]; + u16 analog_gain = exposure->gain[0]; + u16 digital_gain = exposure->gain[1]; + + /* we should not accept the invalid value below */ + if (analog_gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + return ov5693_set_exposure(sd, coarse_itg, analog_gain, digital_gain); +} + +static int ov5693_read_otp_reg_array(struct i2c_client *client, u16 size, + u16 addr, u8 * buf) +{ + u16 index; + int ret; + u16 *pVal = 0; + + for (index = 0; index <= size; index++) { + pVal = (u16 *) (buf + index); + ret = + ov5693_read_reg(client, OV5693_8BIT, addr + index, + pVal); + if (ret) + return ret; + } + + return 0; +} + +static int __ov5693_otp_read(struct v4l2_subdev *sd, u8 * buf) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov5693_device *dev = to_ov5693_sensor(sd); + int ret; + int i; + u8 *b = buf; + dev->otp_size = 0; + for (i = 1; i < OV5693_OTP_BANK_MAX; i++) { + /*set bank NO and OTP read mode. */ + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_OTP_BANK_REG, (i | 0xc0)); //[7:6] 2'b11 [5:0] bank no + if (ret) { + dev_err(&client->dev, "failed to prepare OTP page\n"); + return ret; + } + //pr_debug("write 0x%x->0x%x\n",OV5693_OTP_BANK_REG,(i|0xc0)); + + /*enable read */ + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_OTP_READ_REG, OV5693_OTP_MODE_READ); // enable :1 + if (ret) { + dev_err(&client->dev, + "failed to set OTP reading mode page"); + return ret; + } + //pr_debug("write 0x%x->0x%x\n",OV5693_OTP_READ_REG,OV5693_OTP_MODE_READ); + + /* Reading the OTP data array */ + ret = ov5693_read_otp_reg_array(client, OV5693_OTP_BANK_SIZE, + OV5693_OTP_START_ADDR, + b); + if (ret) { + dev_err(&client->dev, "failed to read OTP data\n"); + return ret; + } + + //pr_debug("BANK[%2d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", i, *b, *(b+1), *(b+2), *(b+3), *(b+4), *(b+5), *(b+6), *(b+7), *(b+8), *(b+9), *(b+10), *(b+11), *(b+12), *(b+13), *(b+14), *(b+15)); + + //Intel OTP map, try to read 320byts first. + if (21 == i) { + if ((*b) == 0) { + dev->otp_size = 320; + break; + } else { + b = buf; + continue; + } + } else if (24 == i) { //if the first 320bytes data doesn't not exist, try to read the next 32bytes data. + if ((*b) == 0) { + dev->otp_size = 32; + break; + } else { + b = buf; + continue; + } + } else if (27 == i) { //if the prvious 32bytes data doesn't exist, try to read the next 32bytes data again. + if ((*b) == 0) { + dev->otp_size = 32; + break; + } else { + dev->otp_size = 0; // no OTP data. + break; + } + } + + b = b + OV5693_OTP_BANK_SIZE; + } + return 0; +} + +/* + * Read otp data and store it into a kmalloced buffer. + * The caller must kfree the buffer when no more needed. + * @size: set to the size of the returned otp data. + */ +static void *ov5693_otp_read(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 *buf; + int ret; + + buf = devm_kzalloc(&client->dev, (OV5693_OTP_DATA_SIZE + 16), GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + //otp valid after mipi on and sw stream on + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_FRAME_OFF_NUM, 0x00); + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_SW_STREAM, OV5693_START_STREAMING); + + ret = __ov5693_otp_read(sd, buf); + + //mipi off and sw stream off after otp read + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_FRAME_OFF_NUM, 0x0f); + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_SW_STREAM, OV5693_STOP_STREAMING); + + /* Driver has failed to find valid data */ + if (ret) { + dev_err(&client->dev, "sensor found no valid OTP data\n"); + return ERR_PTR(ret); + } + + return buf; +} + +static int ov5693_g_priv_int_data(struct v4l2_subdev *sd, + struct v4l2_private_int_data *priv) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov5693_device *dev = to_ov5693_sensor(sd); + u8 __user *to = priv->data; + u32 read_size = priv->size; + int ret; + + /* No need to copy data if size is 0 */ + if (!read_size) + goto out; + + if (IS_ERR(dev->otp_data)) { + dev_err(&client->dev, "OTP data not available"); + return PTR_ERR(dev->otp_data); + } + + /* Correct read_size value only if bigger than maximum */ + if (read_size > OV5693_OTP_DATA_SIZE) + read_size = OV5693_OTP_DATA_SIZE; + + ret = copy_to_user(to, dev->otp_data, read_size); + if (ret) { + dev_err(&client->dev, "%s: failed to copy OTP data to user\n", + __func__); + return -EFAULT; + } + + pr_debug("%s read_size:%d\n", __func__, read_size); + +out: + /* Return correct size */ + priv->size = dev->otp_size; + + return 0; + +} + +static long ov5693_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return ov5693_s_exposure(sd, arg); + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + return ov5693_g_priv_int_data(sd, arg); + default: + return -EINVAL; + } + return 0; +} + +/* This returns the exposure time being used. This should only be used + for filling in EXIF data, not for actual image processing. */ +static int ov5693_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 reg_v, reg_v2; + int ret; + + /* get exposure */ + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_L, + ®_v); + if (ret) + goto err; + + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_M, + ®_v2); + if (ret) + goto err; + + reg_v += reg_v2 << 8; + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_H, + ®_v2); + if (ret) + goto err; + + *value = reg_v + (((u32)reg_v2 << 16)); +err: + return ret; +} + +int ad5823_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = -EINVAL; + u8 vcm_code; + + ret = ad5823_i2c_read(client, AD5823_REG_VCM_CODE_MSB, &vcm_code); + if (ret) + return ret; + + /* set reg VCM_CODE_MSB Bit[1:0] */ + vcm_code = (vcm_code & VCM_CODE_MSB_MASK) | + ((val >> 8) & ~VCM_CODE_MSB_MASK); + ret = ad5823_i2c_write(client, AD5823_REG_VCM_CODE_MSB, vcm_code); + if (ret) + return ret; + + /* set reg VCM_CODE_LSB Bit[7:0] */ + ret = ad5823_i2c_write(client, AD5823_REG_VCM_CODE_LSB, (val & 0xff)); + if (ret) + return ret; + + /* set required vcm move time */ + vcm_code = AD5823_RESONANCE_PERIOD / AD5823_RESONANCE_COEF + - AD5823_HIGH_FREQ_RANGE; + ret = ad5823_i2c_write(client, AD5823_REG_VCM_MOVE_TIME, vcm_code); + + return ret; +} + +int ad5823_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + int ret; + + value = min(value, AD5823_MAX_FOCUS_POS); + ret = ad5823_t_focus_vcm(sd, value); + + return ret; +} + +static int ov5693_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + dev_dbg(&client->dev, "%s: FOCUS_POS: 0x%x\n", __func__, value); + value = clamp(value, 0, OV5693_VCM_MAX_FOCUS_POS); + if (dev->vcm == VCM_DW9714) { + if (dev->vcm_update) { + ret = vcm_dw_i2c_write(client, VCM_PROTECTION_OFF); + if (ret) + return ret; + ret = vcm_dw_i2c_write(client, DIRECT_VCM); + if (ret) + return ret; + ret = vcm_dw_i2c_write(client, VCM_PROTECTION_ON); + if (ret) + return ret; + dev->vcm_update = false; + } + ret = vcm_dw_i2c_write(client, + vcm_val(value, VCM_DEFAULT_S)); + } else if (dev->vcm == VCM_AD5823) { + ad5823_t_focus_abs(sd, value); + } + if (ret == 0) { + dev->number_of_steps = value - dev->focus; + dev->focus = value; + getnstimeofday(&(dev->timestamp_t_focus_abs)); + } else + dev_err(&client->dev, + "%s: i2c failed. ret %d\n", __func__, ret); + + return ret; +} + +static int ov5693_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + return ov5693_t_focus_abs(sd, dev->focus + value); +} + +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) +static int ov5693_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + u32 status = 0; + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct timespec temptime; + const struct timespec timedelay = { + 0, + min((u32)abs(dev->number_of_steps) * DELAY_PER_STEP_NS, + (u32)DELAY_MAX_PER_STEP_NS), + }; + + getnstimeofday(&temptime); + temptime = timespec_sub(temptime, (dev->timestamp_t_focus_abs)); + if (timespec_compare(&temptime, &timedelay) <= 0) { + status |= ATOMISP_FOCUS_STATUS_MOVING; + status |= ATOMISP_FOCUS_HP_IN_PROGRESS; + } else { + status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + status |= ATOMISP_FOCUS_HP_COMPLETE; + } + + *value = status; + + return 0; +} + +static int ov5693_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + s32 val; + + ov5693_q_focus_status(sd, &val); + + if (val & ATOMISP_FOCUS_STATUS_MOVING) + *value = dev->focus - dev->number_of_steps; + else + *value = dev->focus; + + return 0; +} + +static int ov5693_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + dev->number_of_steps = value; + dev->vcm_update = true; + return 0; +} + +static int ov5693_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + dev->number_of_steps = value; + dev->vcm_update = true; + return 0; +} + +static int ov5693_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov5693_device *dev = + container_of(ctrl->handler, struct ov5693_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_FOCUS_ABSOLUTE: + dev_dbg(&client->dev, "%s: CID_FOCUS_ABSOLUTE:%d.\n", + __func__, ctrl->val); + ret = ov5693_t_focus_abs(&dev->sd, ctrl->val); + break; + case V4L2_CID_FOCUS_RELATIVE: + dev_dbg(&client->dev, "%s: CID_FOCUS_RELATIVE:%d.\n", + __func__, ctrl->val); + ret = ov5693_t_focus_rel(&dev->sd, ctrl->val); + break; + case V4L2_CID_VCM_SLEW: + ret = ov5693_t_vcm_slew(&dev->sd, ctrl->val); + break; + case V4L2_CID_VCM_TIMEING: + ret = ov5693_t_vcm_timing(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int ov5693_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov5693_device *dev = + container_of(ctrl->handler, struct ov5693_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = ov5693_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = ov5693_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = ov5693_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = ov5693_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCUS_ABSOLUTE: + ret = ov5693_q_focus_abs(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCUS_STATUS: + ret = ov5693_q_focus_status(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_HORZ: + ret = ov5693_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = ov5693_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = ov5693_s_ctrl, + .g_volatile_ctrl = ov5693_g_volatile_ctrl +}; + +struct v4l2_ctrl_config ov5693_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = OV5693_FOCAL_LENGTH_DEFAULT, + .max = OV5693_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = OV5693_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = OV5693_F_NUMBER_DEFAULT, + .max = OV5693_F_NUMBER_DEFAULT, + .step = 0x01, + .def = OV5693_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = OV5693_F_NUMBER_RANGE, + .max = OV5693_F_NUMBER_RANGE, + .step = 0x01, + .def = OV5693_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus move absolute", + .min = 0, + .max = OV5693_VCM_MAX_FOCUS_POS, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_RELATIVE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus move relative", + .min = OV5693_VCM_MAX_FOCUS_NEG, + .max = OV5693_VCM_MAX_FOCUS_POS, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_STATUS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus status", + .min = 0, + .max = 100, /* allow enum to grow in the future */ + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VCM_SLEW, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vcm slew", + .min = 0, + .max = OV5693_VCM_SLEW_STEP_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VCM_TIMEING, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vcm step time", + .min = 0, + .max = OV5693_VCM_SLEW_TIME_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "horizontal binning factor", + .min = 0, + .max = OV5693_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vertical binning factor", + .min = 0, + .max = OV5693_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, +}; + +static int ov5693_init(struct v4l2_subdev *sd) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + pr_info("%s\n", __func__); + mutex_lock(&dev->input_lock); + dev->vcm_update = false; + + if (dev->vcm == VCM_AD5823) { + ret = vcm_ad_i2c_wr8(client, 0x01, 0x01); /* vcm init test */ + if (ret) + dev_err(&client->dev, + "vcm reset failed\n"); + /*change the mode*/ + ret = ad5823_i2c_write(client, AD5823_REG_VCM_CODE_MSB, + AD5823_RING_CTRL_ENABLE); + if (ret) + dev_err(&client->dev, + "vcm enable ringing failed\n"); + ret = ad5823_i2c_write(client, AD5823_REG_MODE, + AD5823_ARC_RES1); + if (ret) + dev_err(&client->dev, + "vcm change mode failed\n"); + } + + /*change initial focus value for ad5823*/ + if (dev->vcm == VCM_AD5823) { + dev->focus = AD5823_INIT_FOCUS_POS; + ov5693_t_focus_abs(sd, AD5823_INIT_FOCUS_POS); + } else { + dev->focus = 0; + ov5693_t_focus_abs(sd, 0); + } + + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct ov5693_device *dev = to_ov5693_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + /* This driver assumes "internal DVDD, PWDNB tied to DOVDD". + * In this set up only gpio0 (XSHUTDN) should be available + * but in some products (for example ECS) gpio1 (PWDNB) is + * also available. If gpio1 is available we emulate it being + * tied to DOVDD here. */ + if (flag) { + ret = dev->platform_data->v2p8_ctrl(sd, 1); + dev->platform_data->gpio1_ctrl(sd, 1); + if (ret == 0) { + ret = dev->platform_data->v1p8_ctrl(sd, 1); + if (ret) { + dev->platform_data->gpio1_ctrl(sd, 0); + ret = dev->platform_data->v2p8_ctrl(sd, 0); + } + } + } else { + dev->platform_data->gpio1_ctrl(sd, 0); + ret = dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct ov5693_device *dev = to_ov5693_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + ret = dev->platform_data->gpio0_ctrl(sd, flag); + + return ret; +} + +static int __power_up(struct v4l2_subdev *sd) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (NULL == dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* according to DS, at least 5ms is needed between DOVDD and PWDN */ + /* add this delay time to 10~11ms*/ + usleep_range(10000, 11000); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 1); + if (ret) + goto fail_power; + } + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + __cci_delay(up_delay); + + return 0; + +fail_clk: + gpio_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + dev->focus = OV5693_INVALID_CONFIG; + if (NULL == dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + static const int retry_count = 4; + int i, ret; + + for (i = 0; i < retry_count; i++) { + ret = __power_up(sd); + if (!ret) + return 0; + + power_down(sd); + } + return ret; +} + +static int ov5693_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + + pr_info("%s: on %d\n", __func__, on); + if (on == 0) + return power_down(sd); + else { + ret = power_up(sd); + if (!ret) { + ret = ov5693_init(sd); + /* restore settings */ + ov5693_res = ov5693_res_preview; + N_RES = N_RES_PREVIEW; + } + } + return ret; +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between res_w/res_h and w/h. + * distance = (res_w/res_h - w/h) / (w/h) * 8192 + * res->width/height smaller than w/h wouldn't be considered. + * The gap of ratio larger than 1/8 wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 1024 +static int distance(struct ov5693_resolution *res, u32 w, u32 h) +{ + int ratio; + int distance; + + if (w == 0 || h == 0 || + res->width < w || res->height < h) + return -1; + + ratio = res->width << 13; + ratio /= w; + ratio *= h; + ratio /= res->height; + + distance = abs(ratio - 8192); + + if (distance > LARGEST_ALLOWED_RATIO_MISMATCH) + return -1; + + return distance; +} + +/* Return the nearest higher resolution index + * Firstly try to find the approximate aspect ratio resolution + * If we find multiple same AR resolutions, choose the + * minimal size. + */ +static int nearest_resolution_index(int w, int h) +{ + int i; + int idx = -1; + int dist; + int min_dist = INT_MAX; + int min_res_w = INT_MAX; + struct ov5693_resolution *tmp_res = NULL; + + for (i = 0; i < N_RES; i++) { + tmp_res = &ov5693_res[i]; + dist = distance(tmp_res, w, h); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + min_res_w = ov5693_res[i].width; + continue; + } + if (dist == min_dist && ov5693_res[i].width < min_res_w) + idx = i; + } + + return idx; +} + +static int get_resolution_index(int w, int h) +{ + int i; + + for (i = 0; i < N_RES; i++) { + if (w != ov5693_res[i].width) + continue; + if (h != ov5693_res[i].height) + continue; + + return i; + } + + return -1; +} + +/* TODO: remove it. */ +static int startup(struct v4l2_subdev *sd) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_SW_RESET, 0x01); + if (ret) { + dev_err(&client->dev, "ov5693 reset err.\n"); + return ret; + } + + ret = ov5693_write_reg_array(client, ov5693_global_setting); + if (ret) { + dev_err(&client->dev, "ov5693 write register err.\n"); + return ret; + } + + ret = ov5693_write_reg_array(client, ov5693_res[dev->fmt_idx].regs); + if (ret) { + dev_err(&client->dev, "ov5693 write register err.\n"); + return ret; + } + + return ret; +} + +static int ov5693_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *ov5693_info = NULL; + int ret = 0; + int idx; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + ov5693_info = v4l2_get_subdev_hostdata(sd); + if (ov5693_info == NULL) + return -EINVAL; + + mutex_lock(&dev->input_lock); + idx = nearest_resolution_index(fmt->width, fmt->height); + if (idx == -1) { + /* return the largest resolution */ + fmt->width = ov5693_res[N_RES - 1].width; + fmt->height = ov5693_res[N_RES - 1].height; + } else { + fmt->width = ov5693_res[idx].width; + fmt->height = ov5693_res[idx].height; + } + + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + dev->fmt_idx = get_resolution_index(fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + dev_err(&client->dev, "get resolution fail\n"); + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + ret = startup(sd); + if (ret) { + int i = 0; + dev_err(&client->dev, "ov5693 startup err, retry to power up\n"); + for (i = 0; i < OV5693_POWER_UP_RETRY_NUM; i++) { + dev_err(&client->dev, + "ov5693 retry to power up %d/%d times, result: ", + i+1, OV5693_POWER_UP_RETRY_NUM); + power_down(sd); + ret = power_up(sd); + if (!ret) { + mutex_unlock(&dev->input_lock); + ov5693_init(sd); + mutex_lock(&dev->input_lock); + } else { + dev_err(&client->dev, "power up failed, continue\n"); + continue; + } + ret = startup(sd); + if (ret) { + dev_err(&client->dev, " startup FAILED!\n"); + } else { + dev_err(&client->dev, " startup SUCCESS!\n"); + break; + } + } + } + + /* + * After sensor settings are set to HW, sometimes stream is started. + * This would cause ISP timeout because ISP is not ready to receive + * data yet. So add stop streaming here. + */ + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_SW_STREAM, + OV5693_STOP_STREAMING); + if (ret) + dev_warn(&client->dev, "ov5693 stream off err\n"); + + ret = ov5693_get_intg_factor(client, ov5693_info, + &ov5693_res[dev->fmt_idx]); + if (ret) { + dev_err(&client->dev, "failed to get integration_factor\n"); + goto err; + } + + ov5693_info->metadata_width = fmt->width * 10 / 8; + ov5693_info->metadata_height = 1; + ov5693_info->metadata_effective_width = &ov5693_embedded_effective_size; + +err: + mutex_unlock(&dev->input_lock); + return ret; +} +static int ov5693_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov5693_device *dev = to_ov5693_sensor(sd); + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + fmt->width = ov5693_res[dev->fmt_idx].width; + fmt->height = ov5693_res[dev->fmt_idx].height; + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + + return 0; +} + +static int ov5693_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u16 high, low; + int ret; + u16 id; + u8 revision; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_SC_CMMN_CHIP_ID_H, &high); + if (ret) { + dev_err(&client->dev, "sensor_id_high = 0x%x\n", high); + return -ENODEV; + } + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_SC_CMMN_CHIP_ID_L, &low); + id = ((((u16) high) << 8) | (u16) low); + + if (id != OV5693_ID) { + dev_err(&client->dev, "sensor ID error 0x%x\n", id); + return -ENODEV; + } + + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_SC_CMMN_SUB_ID, &high); + revision = (u8) high & 0x0f; + + dev_dbg(&client->dev, "sensor_revision = 0x%x\n", revision); + dev_dbg(&client->dev, "detect ov5693 success\n"); + return 0; +} + +static int ov5693_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + mutex_lock(&dev->input_lock); + + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_SW_STREAM, + enable ? OV5693_START_STREAMING : + OV5693_STOP_STREAMING); + + mutex_unlock(&dev->input_lock); + + return ret; +} + + +static int ov5693_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (platform_data == NULL) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + /* power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov5693 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "ov5693 power-up err.\n"); + goto fail_power_on; + } + + if (!dev->vcm) + dev->vcm = vcm_detect(client); + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = ov5693_detect(client); + if (ret) { + dev_err(&client->dev, "ov5693_detect err s_config.\n"); + goto fail_csi_cfg; + } + + dev->otp_data = ov5693_otp_read(sd); + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov5693 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + return ret; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov5693_g_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (!param) + return -EINVAL; + + if (param->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(&client->dev, "unsupported buffer type.\n"); + return -EINVAL; + } + + memset(param, 0, sizeof(*param)); + param->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + if (dev->fmt_idx >= 0 && dev->fmt_idx < N_RES) { + param->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + param->parm.capture.timeperframe.numerator = 1; + param->parm.capture.capturemode = dev->run_mode; + param->parm.capture.timeperframe.denominator = + ov5693_res[dev->fmt_idx].fps; + } + return 0; +} + +static int ov5693_s_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + dev->run_mode = param->parm.capture.capturemode; + + mutex_lock(&dev->input_lock); + switch (dev->run_mode) { + case CI_MODE_VIDEO: + ov5693_res = ov5693_res_video; + N_RES = N_RES_VIDEO; + break; + case CI_MODE_STILL_CAPTURE: + ov5693_res = ov5693_res_still; + N_RES = N_RES_STILL; + break; + default: + ov5693_res = ov5693_res_preview; + N_RES = N_RES_PREVIEW; + } + mutex_unlock(&dev->input_lock); + return 0; +} + +static int ov5693_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = ov5693_res[dev->fmt_idx].fps; + + return 0; +} + +static int ov5693_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + return 0; +} + +static int ov5693_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = ov5693_res[index].width; + fse->min_height = ov5693_res[index].height; + fse->max_width = ov5693_res[index].width; + fse->max_height = ov5693_res[index].height; + + return 0; + +} + +static const struct v4l2_subdev_video_ops ov5693_video_ops = { + .s_stream = ov5693_s_stream, + .g_parm = ov5693_g_parm, + .s_parm = ov5693_s_parm, + .g_frame_interval = ov5693_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops ov5693_core_ops = { + .s_power = ov5693_s_power, + .ioctl = ov5693_ioctl, +}; + +static const struct v4l2_subdev_pad_ops ov5693_pad_ops = { + .enum_mbus_code = ov5693_enum_mbus_code, + .enum_frame_size = ov5693_enum_frame_size, + .get_fmt = ov5693_get_fmt, + .set_fmt = ov5693_set_fmt, +}; + +static const struct v4l2_subdev_ops ov5693_ops = { + .core = &ov5693_core_ops, + .video = &ov5693_video_ops, + .pad = &ov5693_pad_ops, +}; + +static int ov5693_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov5693_device *dev = to_ov5693_sensor(sd); + dev_dbg(&client->dev, "ov5693_remove...\n"); + + dev->platform_data->csi_cfg(sd, 0); + + v4l2_device_unregister_subdev(sd); + + atomisp_gmin_remove_subdev(sd); + + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); + + return 0; +} + +static int ov5693_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ov5693_device *dev; + int i2c; + int ret = 0; + void *pdata = client->dev.platform_data; + struct acpi_device *adev; + unsigned int i; + + /* Firmware workaround: Some modules use a "secondary default" + * address of 0x10 which doesn't appear on schematics, and + * some BIOS versions haven't gotten the memo. Work around + * via config. */ + i2c = gmin_get_var_int(&client->dev, "I2CAddr", -1); + if (i2c != -1) { + dev_info(&client->dev, + "Overriding firmware-provided I2C address (0x%x) with 0x%x\n", + client->addr, i2c); + client->addr = i2c; + } + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + dev->fmt_idx = 0; + v4l2_i2c_subdev_init(&(dev->sd), client, &ov5693_ops); + + adev = ACPI_COMPANION(&client->dev); + if (adev) { + adev->power.flags.power_resources = 0; + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_bggr); + } + + if (!pdata) + goto out_free; + + ret = ov5693_s_config(&dev->sd, client->irq, pdata); + if (ret) + goto out_free; + + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) + goto out_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(ov5693_controls)); + if (ret) { + ov5693_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(ov5693_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &ov5693_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + ov5693_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + ov5693_remove(client); + + return ret; +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +MODULE_DEVICE_TABLE(i2c, ov5693_id); + +static struct acpi_device_id ov5693_acpi_match[] = { + {"INT33BE"}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, ov5693_acpi_match); + +static struct i2c_driver ov5693_driver = { + .driver = { + .name = OV5693_NAME, + .acpi_match_table = ACPI_PTR(ov5693_acpi_match), + }, + .probe = ov5693_probe, + .remove = ov5693_remove, + .id_table = ov5693_id, +}; + +static int init_ov5693(void) +{ + return i2c_add_driver(&ov5693_driver); +} + +static void exit_ov5693(void) +{ + + i2c_del_driver(&ov5693_driver); +} + +module_init(init_ov5693); +module_exit(exit_ov5693); + +MODULE_DESCRIPTION("A low-level driver for OmniVision 5693 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/ov5693/ov5693.h b/drivers/staging/media/atomisp/i2c/ov5693/ov5693.h new file mode 100644 index 0000000..d88ac17 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/ov5693.h @@ -0,0 +1,1381 @@ +/* + * Support for OmniVision OV5693 5M camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __OV5693_H__ +#define __OV5693_H__ +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/i2c.h> +#include <linux/delay.h> +#include <linux/videodev2.h> +#include <linux/spinlock.h> +#include <media/v4l2-subdev.h> +#include <media/v4l2-device.h> +#include <media/v4l2-ctrls.h> +#include <linux/v4l2-mediabus.h> +#include <media/media-entity.h> + +#include "../../include/linux/atomisp_platform.h" + +#define OV5693_NAME "ov5693" + +#define OV5693_POWER_UP_RETRY_NUM 5 + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 0x2 +#define I2C_RETRY_COUNT 5 + +#define OV5693_FOCAL_LENGTH_NUM 334 /*3.34mm*/ +#define OV5693_FOCAL_LENGTH_DEM 100 +#define OV5693_F_NUMBER_DEFAULT_NUM 24 +#define OV5693_F_NUMBER_DEM 10 + +#define MAX_FMTS 1 + +/* sensor_mode_data read_mode adaptation */ +#define OV5693_READ_MODE_BINNING_ON 0x0400 +#define OV5693_READ_MODE_BINNING_OFF 0x00 +#define OV5693_INTEGRATION_TIME_MARGIN 8 + +#define OV5693_MAX_EXPOSURE_VALUE 0xFFF1 +#define OV5693_MAX_GAIN_VALUE 0xFF + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV5693_FOCAL_LENGTH_DEFAULT 0x1B70064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV5693_F_NUMBER_DEFAULT 0x18000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define OV5693_F_NUMBER_RANGE 0x180a180a +#define OV5693_ID 0x5690 + +#define OV5693_FINE_INTG_TIME_MIN 0 +#define OV5693_FINE_INTG_TIME_MAX_MARGIN 0 +#define OV5693_COARSE_INTG_TIME_MIN 1 +#define OV5693_COARSE_INTG_TIME_MAX_MARGIN 6 + +#define OV5693_BIN_FACTOR_MAX 4 +/* + * OV5693 System control registers + */ +#define OV5693_SW_SLEEP 0x0100 +#define OV5693_SW_RESET 0x0103 +#define OV5693_SW_STREAM 0x0100 + +#define OV5693_SC_CMMN_CHIP_ID_H 0x300A +#define OV5693_SC_CMMN_CHIP_ID_L 0x300B +#define OV5693_SC_CMMN_SCCB_ID 0x300C +#define OV5693_SC_CMMN_SUB_ID 0x302A /* process, version*/ +/*Bit[7:4] Group control, Bit[3:0] Group ID*/ +#define OV5693_GROUP_ACCESS 0x3208 +/* +*Bit[3:0] Bit[19:16] of exposure, +*remaining 16 bits lies in Reg0x3501&Reg0x3502 +*/ +#define OV5693_EXPOSURE_H 0x3500 +#define OV5693_EXPOSURE_M 0x3501 +#define OV5693_EXPOSURE_L 0x3502 +/*Bit[1:0] means Bit[9:8] of gain*/ +#define OV5693_AGC_H 0x350A +#define OV5693_AGC_L 0x350B /*Bit[7:0] of gain*/ + +#define OV5693_HORIZONTAL_START_H 0x3800 /*Bit[11:8]*/ +#define OV5693_HORIZONTAL_START_L 0x3801 /*Bit[7:0]*/ +#define OV5693_VERTICAL_START_H 0x3802 /*Bit[11:8]*/ +#define OV5693_VERTICAL_START_L 0x3803 /*Bit[7:0]*/ +#define OV5693_HORIZONTAL_END_H 0x3804 /*Bit[11:8]*/ +#define OV5693_HORIZONTAL_END_L 0x3805 /*Bit[7:0]*/ +#define OV5693_VERTICAL_END_H 0x3806 /*Bit[11:8]*/ +#define OV5693_VERTICAL_END_L 0x3807 /*Bit[7:0]*/ +#define OV5693_HORIZONTAL_OUTPUT_SIZE_H 0x3808 /*Bit[3:0]*/ +#define OV5693_HORIZONTAL_OUTPUT_SIZE_L 0x3809 /*Bit[7:0]*/ +#define OV5693_VERTICAL_OUTPUT_SIZE_H 0x380a /*Bit[3:0]*/ +#define OV5693_VERTICAL_OUTPUT_SIZE_L 0x380b /*Bit[7:0]*/ +/*High 8-bit, and low 8-bit HTS address is 0x380d*/ +#define OV5693_TIMING_HTS_H 0x380C +/*High 8-bit, and low 8-bit HTS address is 0x380d*/ +#define OV5693_TIMING_HTS_L 0x380D +/*High 8-bit, and low 8-bit HTS address is 0x380f*/ +#define OV5693_TIMING_VTS_H 0x380e +/*High 8-bit, and low 8-bit HTS address is 0x380f*/ +#define OV5693_TIMING_VTS_L 0x380f + +#define OV5693_MWB_RED_GAIN_H 0x3400 +#define OV5693_MWB_GREEN_GAIN_H 0x3402 +#define OV5693_MWB_BLUE_GAIN_H 0x3404 +#define OV5693_MWB_GAIN_MAX 0x0fff + +#define OV5693_START_STREAMING 0x01 +#define OV5693_STOP_STREAMING 0x00 + +#define VCM_ADDR 0x0c +#define VCM_CODE_MSB 0x04 + +#define OV5693_INVALID_CONFIG 0xffffffff + +#define OV5693_VCM_SLEW_STEP 0x30F0 +#define OV5693_VCM_SLEW_STEP_MAX 0x7 +#define OV5693_VCM_SLEW_STEP_MASK 0x7 +#define OV5693_VCM_CODE 0x30F2 +#define OV5693_VCM_SLEW_TIME 0x30F4 +#define OV5693_VCM_SLEW_TIME_MAX 0xffff +#define OV5693_VCM_ENABLE 0x8000 + +#define OV5693_VCM_MAX_FOCUS_NEG -1023 +#define OV5693_VCM_MAX_FOCUS_POS 1023 + +#define DLC_ENABLE 1 +#define DLC_DISABLE 0 +#define VCM_PROTECTION_OFF 0xeca3 +#define VCM_PROTECTION_ON 0xdc51 +#define VCM_DEFAULT_S 0x0 +#define vcm_step_s(a) (u8)(a & 0xf) +#define vcm_step_mclk(a) (u8)((a >> 4) & 0x3) +#define vcm_dlc_mclk(dlc, mclk) (u16)((dlc << 3) | mclk | 0xa104) +#define vcm_tsrc(tsrc) (u16)(tsrc << 3 | 0xf200) +#define vcm_val(data, s) (u16)(data << 4 | s) +#define DIRECT_VCM vcm_dlc_mclk(0, 0) + +/* Defines for OTP Data Registers */ +#define OV5693_FRAME_OFF_NUM 0x4202 +#define OV5693_OTP_BYTE_MAX 32 //change to 32 as needed by otpdata +#define OV5693_OTP_SHORT_MAX 16 +#define OV5693_OTP_START_ADDR 0x3D00 +#define OV5693_OTP_END_ADDR 0x3D0F +#define OV5693_OTP_DATA_SIZE 320 +#define OV5693_OTP_PROGRAM_REG 0x3D80 +#define OV5693_OTP_READ_REG 0x3D81 // 1:Enable 0:disable +#define OV5693_OTP_BANK_REG 0x3D84 //otp bank and mode +#define OV5693_OTP_READY_REG_DONE 1 +#define OV5693_OTP_BANK_MAX 28 +#define OV5693_OTP_BANK_SIZE 16 //16 bytes per bank +#define OV5693_OTP_READ_ONETIME 16 +#define OV5693_OTP_MODE_READ 1 + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct ov5693_resolution { + u8 *desc; + const struct ov5693_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; +}; + +struct ov5693_format { + u8 *desc; + u32 pixelformat; + struct ov5693_reg *regs; +}; + +enum vcm_type { + VCM_UNKNOWN, + VCM_AD5823, + VCM_DW9714, +}; + +/* + * ov5693 device structure. + */ +struct ov5693_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + struct v4l2_ctrl_handler ctrl_handler; + + struct camera_sensor_platform_data *platform_data; + struct timespec timestamp_t_focus_abs; + int vt_pix_clk_freq_mhz; + int fmt_idx; + int run_mode; + int otp_size; + u8 *otp_data; + u32 focus; + s16 number_of_steps; + u8 res; + u8 type; + bool vcm_update; + enum vcm_type vcm; +}; + +enum ov5693_tok_type { + OV5693_8BIT = 0x0001, + OV5693_16BIT = 0x0002, + OV5693_32BIT = 0x0004, + OV5693_TOK_TERM = 0xf000, /* terminating token for reg list */ + OV5693_TOK_DELAY = 0xfe00, /* delay token for reg list */ + OV5693_TOK_MASK = 0xfff0 +}; + +/** + * struct ov5693_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct ov5693_reg { + enum ov5693_tok_type type; + u16 reg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +#define to_ov5693_sensor(x) container_of(x, struct ov5693_device, sd) + +#define OV5693_MAX_WRITE_BUF_SIZE 30 + +struct ov5693_write_buffer { + u16 addr; + u8 data[OV5693_MAX_WRITE_BUF_SIZE]; +}; + +struct ov5693_write_ctrl { + int index; + struct ov5693_write_buffer buffer; +}; + +static const struct i2c_device_id ov5693_id[] = { + {OV5693_NAME, 0}, + {} +}; + +static struct ov5693_reg const ov5693_global_setting[] = { + {OV5693_8BIT, 0x0103, 0x01}, + {OV5693_8BIT, 0x3001, 0x0a}, + {OV5693_8BIT, 0x3002, 0x80}, + {OV5693_8BIT, 0x3006, 0x00}, + {OV5693_8BIT, 0x3011, 0x21}, + {OV5693_8BIT, 0x3012, 0x09}, + {OV5693_8BIT, 0x3013, 0x10}, + {OV5693_8BIT, 0x3014, 0x00}, + {OV5693_8BIT, 0x3015, 0x08}, + {OV5693_8BIT, 0x3016, 0xf0}, + {OV5693_8BIT, 0x3017, 0xf0}, + {OV5693_8BIT, 0x3018, 0xf0}, + {OV5693_8BIT, 0x301b, 0xb4}, + {OV5693_8BIT, 0x301d, 0x02}, + {OV5693_8BIT, 0x3021, 0x00}, + {OV5693_8BIT, 0x3022, 0x01}, + {OV5693_8BIT, 0x3028, 0x44}, + {OV5693_8BIT, 0x3098, 0x02}, + {OV5693_8BIT, 0x3099, 0x19}, + {OV5693_8BIT, 0x309a, 0x02}, + {OV5693_8BIT, 0x309b, 0x01}, + {OV5693_8BIT, 0x309c, 0x00}, + {OV5693_8BIT, 0x30a0, 0xd2}, + {OV5693_8BIT, 0x30a2, 0x01}, + {OV5693_8BIT, 0x30b2, 0x00}, + {OV5693_8BIT, 0x30b3, 0x7d}, + {OV5693_8BIT, 0x30b4, 0x03}, + {OV5693_8BIT, 0x30b5, 0x04}, + {OV5693_8BIT, 0x30b6, 0x01}, + {OV5693_8BIT, 0x3104, 0x21}, + {OV5693_8BIT, 0x3106, 0x00}, + {OV5693_8BIT, 0x3400, 0x04}, + {OV5693_8BIT, 0x3401, 0x00}, + {OV5693_8BIT, 0x3402, 0x04}, + {OV5693_8BIT, 0x3403, 0x00}, + {OV5693_8BIT, 0x3404, 0x04}, + {OV5693_8BIT, 0x3405, 0x00}, + {OV5693_8BIT, 0x3406, 0x01}, + {OV5693_8BIT, 0x3500, 0x00}, + {OV5693_8BIT, 0x3503, 0x07}, + {OV5693_8BIT, 0x3504, 0x00}, + {OV5693_8BIT, 0x3505, 0x00}, + {OV5693_8BIT, 0x3506, 0x00}, + {OV5693_8BIT, 0x3507, 0x02}, + {OV5693_8BIT, 0x3508, 0x00}, + {OV5693_8BIT, 0x3509, 0x10}, + {OV5693_8BIT, 0x350a, 0x00}, + {OV5693_8BIT, 0x350b, 0x40}, + {OV5693_8BIT, 0x3601, 0x0a}, + {OV5693_8BIT, 0x3602, 0x38}, + {OV5693_8BIT, 0x3612, 0x80}, + {OV5693_8BIT, 0x3620, 0x54}, + {OV5693_8BIT, 0x3621, 0xc7}, + {OV5693_8BIT, 0x3622, 0x0f}, + {OV5693_8BIT, 0x3625, 0x10}, + {OV5693_8BIT, 0x3630, 0x55}, + {OV5693_8BIT, 0x3631, 0xf4}, + {OV5693_8BIT, 0x3632, 0x00}, + {OV5693_8BIT, 0x3633, 0x34}, + {OV5693_8BIT, 0x3634, 0x02}, + {OV5693_8BIT, 0x364d, 0x0d}, + {OV5693_8BIT, 0x364f, 0xdd}, + {OV5693_8BIT, 0x3660, 0x04}, + {OV5693_8BIT, 0x3662, 0x10}, + {OV5693_8BIT, 0x3663, 0xf1}, + {OV5693_8BIT, 0x3665, 0x00}, + {OV5693_8BIT, 0x3666, 0x20}, + {OV5693_8BIT, 0x3667, 0x00}, + {OV5693_8BIT, 0x366a, 0x80}, + {OV5693_8BIT, 0x3680, 0xe0}, + {OV5693_8BIT, 0x3681, 0x00}, + {OV5693_8BIT, 0x3700, 0x42}, + {OV5693_8BIT, 0x3701, 0x14}, + {OV5693_8BIT, 0x3702, 0xa0}, + {OV5693_8BIT, 0x3703, 0xd8}, + {OV5693_8BIT, 0x3704, 0x78}, + {OV5693_8BIT, 0x3705, 0x02}, + {OV5693_8BIT, 0x370a, 0x00}, + {OV5693_8BIT, 0x370b, 0x20}, + {OV5693_8BIT, 0x370c, 0x0c}, + {OV5693_8BIT, 0x370d, 0x11}, + {OV5693_8BIT, 0x370e, 0x00}, + {OV5693_8BIT, 0x370f, 0x40}, + {OV5693_8BIT, 0x3710, 0x00}, + {OV5693_8BIT, 0x371a, 0x1c}, + {OV5693_8BIT, 0x371b, 0x05}, + {OV5693_8BIT, 0x371c, 0x01}, + {OV5693_8BIT, 0x371e, 0xa1}, + {OV5693_8BIT, 0x371f, 0x0c}, + {OV5693_8BIT, 0x3721, 0x00}, + {OV5693_8BIT, 0x3724, 0x10}, + {OV5693_8BIT, 0x3726, 0x00}, + {OV5693_8BIT, 0x372a, 0x01}, + {OV5693_8BIT, 0x3730, 0x10}, + {OV5693_8BIT, 0x3738, 0x22}, + {OV5693_8BIT, 0x3739, 0xe5}, + {OV5693_8BIT, 0x373a, 0x50}, + {OV5693_8BIT, 0x373b, 0x02}, + {OV5693_8BIT, 0x373c, 0x41}, + {OV5693_8BIT, 0x373f, 0x02}, + {OV5693_8BIT, 0x3740, 0x42}, + {OV5693_8BIT, 0x3741, 0x02}, + {OV5693_8BIT, 0x3742, 0x18}, + {OV5693_8BIT, 0x3743, 0x01}, + {OV5693_8BIT, 0x3744, 0x02}, + {OV5693_8BIT, 0x3747, 0x10}, + {OV5693_8BIT, 0x374c, 0x04}, + {OV5693_8BIT, 0x3751, 0xf0}, + {OV5693_8BIT, 0x3752, 0x00}, + {OV5693_8BIT, 0x3753, 0x00}, + {OV5693_8BIT, 0x3754, 0xc0}, + {OV5693_8BIT, 0x3755, 0x00}, + {OV5693_8BIT, 0x3756, 0x1a}, + {OV5693_8BIT, 0x3758, 0x00}, + {OV5693_8BIT, 0x3759, 0x0f}, + {OV5693_8BIT, 0x376b, 0x44}, + {OV5693_8BIT, 0x375c, 0x04}, + {OV5693_8BIT, 0x3774, 0x10}, + {OV5693_8BIT, 0x3776, 0x00}, + {OV5693_8BIT, 0x377f, 0x08}, + {OV5693_8BIT, 0x3780, 0x22}, + {OV5693_8BIT, 0x3781, 0x0c}, + {OV5693_8BIT, 0x3784, 0x2c}, + {OV5693_8BIT, 0x3785, 0x1e}, + {OV5693_8BIT, 0x378f, 0xf5}, + {OV5693_8BIT, 0x3791, 0xb0}, + {OV5693_8BIT, 0x3795, 0x00}, + {OV5693_8BIT, 0x3796, 0x64}, + {OV5693_8BIT, 0x3797, 0x11}, + {OV5693_8BIT, 0x3798, 0x30}, + {OV5693_8BIT, 0x3799, 0x41}, + {OV5693_8BIT, 0x379a, 0x07}, + {OV5693_8BIT, 0x379b, 0xb0}, + {OV5693_8BIT, 0x379c, 0x0c}, + {OV5693_8BIT, 0x37c5, 0x00}, + {OV5693_8BIT, 0x37c6, 0x00}, + {OV5693_8BIT, 0x37c7, 0x00}, + {OV5693_8BIT, 0x37c9, 0x00}, + {OV5693_8BIT, 0x37ca, 0x00}, + {OV5693_8BIT, 0x37cb, 0x00}, + {OV5693_8BIT, 0x37de, 0x00}, + {OV5693_8BIT, 0x37df, 0x00}, + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3810, 0x00}, + {OV5693_8BIT, 0x3812, 0x00}, + {OV5693_8BIT, 0x3823, 0x00}, + {OV5693_8BIT, 0x3824, 0x00}, + {OV5693_8BIT, 0x3825, 0x00}, + {OV5693_8BIT, 0x3826, 0x00}, + {OV5693_8BIT, 0x3827, 0x00}, + {OV5693_8BIT, 0x382a, 0x04}, + {OV5693_8BIT, 0x3a04, 0x06}, + {OV5693_8BIT, 0x3a05, 0x14}, + {OV5693_8BIT, 0x3a06, 0x00}, + {OV5693_8BIT, 0x3a07, 0xfe}, + {OV5693_8BIT, 0x3b00, 0x00}, + {OV5693_8BIT, 0x3b02, 0x00}, + {OV5693_8BIT, 0x3b03, 0x00}, + {OV5693_8BIT, 0x3b04, 0x00}, + {OV5693_8BIT, 0x3b05, 0x00}, + {OV5693_8BIT, 0x3e07, 0x20}, + {OV5693_8BIT, 0x4000, 0x08}, + {OV5693_8BIT, 0x4001, 0x04}, + {OV5693_8BIT, 0x4002, 0x45}, + {OV5693_8BIT, 0x4004, 0x08}, + {OV5693_8BIT, 0x4005, 0x18}, + {OV5693_8BIT, 0x4006, 0x20}, + {OV5693_8BIT, 0x4008, 0x24}, + {OV5693_8BIT, 0x4009, 0x10}, + {OV5693_8BIT, 0x400c, 0x00}, + {OV5693_8BIT, 0x400d, 0x00}, + {OV5693_8BIT, 0x4058, 0x00}, + {OV5693_8BIT, 0x404e, 0x37}, + {OV5693_8BIT, 0x404f, 0x8f}, + {OV5693_8BIT, 0x4058, 0x00}, + {OV5693_8BIT, 0x4101, 0xb2}, + {OV5693_8BIT, 0x4303, 0x00}, + {OV5693_8BIT, 0x4304, 0x08}, + {OV5693_8BIT, 0x4307, 0x31}, + {OV5693_8BIT, 0x4311, 0x04}, + {OV5693_8BIT, 0x4315, 0x01}, + {OV5693_8BIT, 0x4511, 0x05}, + {OV5693_8BIT, 0x4512, 0x01}, + {OV5693_8BIT, 0x4806, 0x00}, + {OV5693_8BIT, 0x4816, 0x52}, + {OV5693_8BIT, 0x481f, 0x30}, + {OV5693_8BIT, 0x4826, 0x2c}, + {OV5693_8BIT, 0x4831, 0x64}, + {OV5693_8BIT, 0x4d00, 0x04}, + {OV5693_8BIT, 0x4d01, 0x71}, + {OV5693_8BIT, 0x4d02, 0xfd}, + {OV5693_8BIT, 0x4d03, 0xf5}, + {OV5693_8BIT, 0x4d04, 0x0c}, + {OV5693_8BIT, 0x4d05, 0xcc}, + {OV5693_8BIT, 0x4837, 0x0a}, + {OV5693_8BIT, 0x5000, 0x06}, + {OV5693_8BIT, 0x5001, 0x01}, + {OV5693_8BIT, 0x5003, 0x20}, + {OV5693_8BIT, 0x5046, 0x0a}, + {OV5693_8BIT, 0x5013, 0x00}, + {OV5693_8BIT, 0x5046, 0x0a}, + {OV5693_8BIT, 0x5780, 0x1c}, + {OV5693_8BIT, 0x5786, 0x20}, + {OV5693_8BIT, 0x5787, 0x10}, + {OV5693_8BIT, 0x5788, 0x18}, + {OV5693_8BIT, 0x578a, 0x04}, + {OV5693_8BIT, 0x578b, 0x02}, + {OV5693_8BIT, 0x578c, 0x02}, + {OV5693_8BIT, 0x578e, 0x06}, + {OV5693_8BIT, 0x578f, 0x02}, + {OV5693_8BIT, 0x5790, 0x02}, + {OV5693_8BIT, 0x5791, 0xff}, + {OV5693_8BIT, 0x5842, 0x01}, + {OV5693_8BIT, 0x5843, 0x2b}, + {OV5693_8BIT, 0x5844, 0x01}, + {OV5693_8BIT, 0x5845, 0x92}, + {OV5693_8BIT, 0x5846, 0x01}, + {OV5693_8BIT, 0x5847, 0x8f}, + {OV5693_8BIT, 0x5848, 0x01}, + {OV5693_8BIT, 0x5849, 0x0c}, + {OV5693_8BIT, 0x5e00, 0x00}, + {OV5693_8BIT, 0x5e10, 0x0c}, + {OV5693_8BIT, 0x0100, 0x00}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 654x496 30fps 17ms VBlanking 2lane 10Bit (Scaling) + */ +static struct ov5693_reg const ov5693_654x496[] = { + {OV5693_8BIT, 0x3501, 0x3d}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc7}, + {OV5693_8BIT, 0x3803, 0x00}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x02}, + {OV5693_8BIT, 0x3809, 0x90}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0xf0}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x08}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 1296x976 30fps 17ms VBlanking 2lane 10Bit (Scaling) +*DS from 2592x1952 +*/ +static struct ov5693_reg const ov5693_1296x976[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3803, 0x00}, + + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xA3}, + + {OV5693_8BIT, 0x3808, 0x05}, + {OV5693_8BIT, 0x3809, 0x10}, + {OV5693_8BIT, 0x380a, 0x03}, + {OV5693_8BIT, 0x380b, 0xD0}, + + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + + {OV5693_8BIT, 0x3810, 0x00}, + {OV5693_8BIT, 0x3811, 0x10}, + {OV5693_8BIT, 0x3812, 0x00}, + {OV5693_8BIT, 0x3813, 0x02}, + + {OV5693_8BIT, 0x3814, 0x11}, /*X subsample control*/ + {OV5693_8BIT, 0x3815, 0x11}, /*Y subsample control*/ + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, /* scale is auto enabled */ + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} + +}; + + +/* + * 336x256 30fps 17ms VBlanking 2lane 10Bit (Scaling) + DS from 2564x1956 + */ +static struct ov5693_reg const ov5693_336x256[] = { + {OV5693_8BIT, 0x3501, 0x3d}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc7}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x01}, + {OV5693_8BIT, 0x3809, 0x50}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0x00}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x1E}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 336x256 30fps 17ms VBlanking 2lane 10Bit (Scaling) + DS from 2368x1956 + */ +static struct ov5693_reg const ov5693_368x304[] = { + {OV5693_8BIT, 0x3501, 0x3d}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc7}, + {OV5693_8BIT, 0x3808, 0x01}, + {OV5693_8BIT, 0x3809, 0x70}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0x30}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x80}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * ov5693_192x160 30fps 17ms VBlanking 2lane 10Bit (Scaling) + DS from 2460x1956 + */ +static struct ov5693_reg const ov5693_192x160[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x80}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xA3}, + {OV5693_8BIT, 0x3808, 0x00}, + {OV5693_8BIT, 0x3809, 0xC0}, + {OV5693_8BIT, 0x380a, 0x00}, + {OV5693_8BIT, 0x380b, 0xA0}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x40}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + + +static struct ov5693_reg const ov5693_736x496[] = { + {OV5693_8BIT, 0x3501, 0x3d}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc7}, + {OV5693_8BIT, 0x3803, 0x68}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0x3b}, + {OV5693_8BIT, 0x3808, 0x02}, + {OV5693_8BIT, 0x3809, 0xe0}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0xf0}, + {OV5693_8BIT, 0x380c, 0x0a}, /*hts*/ + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, /*vts*/ + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x08}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* +static struct ov5693_reg const ov5693_736x496[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0x00}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x02}, + {OV5693_8BIT, 0x3809, 0xe0}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0xf0}, + {OV5693_8BIT, 0x380c, 0x0d}, + {OV5693_8BIT, 0x380d, 0xb0}, + {OV5693_8BIT, 0x380e, 0x05}, + {OV5693_8BIT, 0x380f, 0xf2}, + {OV5693_8BIT, 0x3811, 0x08}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x01}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; +*/ +/* + * 976x556 30fps 8.8ms VBlanking 2lane 10Bit (Scaling) + */ +static struct ov5693_reg const ov5693_976x556[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa7}, + {OV5693_8BIT, 0x3808, 0x03}, + {OV5693_8BIT, 0x3809, 0xd0}, + {OV5693_8BIT, 0x380a, 0x02}, + {OV5693_8BIT, 0x380b, 0x2C}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x10}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/*DS from 2624x1492*/ +static struct ov5693_reg const ov5693_1296x736[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3803, 0x00}, + + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xA3}, + + {OV5693_8BIT, 0x3808, 0x05}, + {OV5693_8BIT, 0x3809, 0x10}, + {OV5693_8BIT, 0x380a, 0x02}, + {OV5693_8BIT, 0x380b, 0xe0}, + + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + + {OV5693_8BIT, 0x3813, 0xE8}, + + {OV5693_8BIT, 0x3814, 0x11}, /*X subsample control*/ + {OV5693_8BIT, 0x3815, 0x11}, /*Y subsample control*/ + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, /* scale is auto enabled */ + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_1636p_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa7}, + {OV5693_8BIT, 0x3808, 0x06}, + {OV5693_8BIT, 0x3809, 0x64}, + {OV5693_8BIT, 0x380a, 0x04}, + {OV5693_8BIT, 0x380b, 0x48}, + {OV5693_8BIT, 0x380c, 0x0a}, /*hts*/ + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, /*vts*/ + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x02}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_1616x1216_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x80}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, /*{3800,3801} Array X start*/ + {OV5693_8BIT, 0x3801, 0x08}, /* 04 //{3800,3801} Array X start*/ + {OV5693_8BIT, 0x3802, 0x00}, /*{3802,3803} Array Y start*/ + {OV5693_8BIT, 0x3803, 0x04}, /* 00 //{3802,3803} Array Y start*/ + {OV5693_8BIT, 0x3804, 0x0a}, /*{3804,3805} Array X end*/ + {OV5693_8BIT, 0x3805, 0x37}, /* 3b //{3804,3805} Array X end*/ + {OV5693_8BIT, 0x3806, 0x07}, /*{3806,3807} Array Y end*/ + {OV5693_8BIT, 0x3807, 0x9f}, /* a3 //{3806,3807} Array Y end*/ + {OV5693_8BIT, 0x3808, 0x06}, /*{3808,3809} Final output H size*/ + {OV5693_8BIT, 0x3809, 0x50}, /*{3808,3809} Final output H size*/ + {OV5693_8BIT, 0x380a, 0x04}, /*{380a,380b} Final output V size*/ + {OV5693_8BIT, 0x380b, 0xc0}, /*{380a,380b} Final output V size*/ + {OV5693_8BIT, 0x380c, 0x0a}, /*{380c,380d} HTS*/ + {OV5693_8BIT, 0x380d, 0x80}, /*{380c,380d} HTS*/ + {OV5693_8BIT, 0x380e, 0x07}, /*{380e,380f} VTS*/ + {OV5693_8BIT, 0x380f, 0xc0}, /* bc //{380e,380f} VTS*/ + {OV5693_8BIT, 0x3810, 0x00}, /*{3810,3811} windowing X offset*/ + {OV5693_8BIT, 0x3811, 0x10}, /*{3810,3811} windowing X offset*/ + {OV5693_8BIT, 0x3812, 0x00}, /*{3812,3813} windowing Y offset*/ + {OV5693_8BIT, 0x3813, 0x06}, /*{3812,3813} windowing Y offset*/ + {OV5693_8BIT, 0x3814, 0x11}, /*X subsample control*/ + {OV5693_8BIT, 0x3815, 0x11}, /*Y subsample control*/ + {OV5693_8BIT, 0x3820, 0x00}, /*FLIP/Binnning control*/ + {OV5693_8BIT, 0x3821, 0x1e}, /*MIRROR control*/ + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + + +/* + * 1940x1096 30fps 8.8ms VBlanking 2lane 10bit (Scaling) + */ +static struct ov5693_reg const ov5693_1940x1096[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa7}, + {OV5693_8BIT, 0x3808, 0x07}, + {OV5693_8BIT, 0x3809, 0x94}, + {OV5693_8BIT, 0x380a, 0x04}, + {OV5693_8BIT, 0x380b, 0x48}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x02}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_2592x1456_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa4}, + {OV5693_8BIT, 0x3808, 0x0a}, + {OV5693_8BIT, 0x3809, 0x20}, + {OV5693_8BIT, 0x380a, 0x05}, + {OV5693_8BIT, 0x380b, 0xb0}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x10}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_2576x1456_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa4}, + {OV5693_8BIT, 0x3808, 0x0a}, + {OV5693_8BIT, 0x3809, 0x10}, + {OV5693_8BIT, 0x380a, 0x05}, + {OV5693_8BIT, 0x380b, 0xb0}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x18}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 2592x1944 30fps 0.6ms VBlanking 2lane 10Bit + */ +static struct ov5693_reg const ov5693_2592x1944_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0x00}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x0a}, + {OV5693_8BIT, 0x3809, 0x20}, + {OV5693_8BIT, 0x380a, 0x07}, + {OV5693_8BIT, 0x380b, 0x98}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x10}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 11:9 Full FOV Output, expected FOV Res: 2346x1920 + * ISP Effect Res: 1408x1152 + * Sensor out: 1424x1168, DS From: 2380x1952 + * + * WA: Left Offset: 8, Hor scal: 64 + */ +static struct ov5693_reg const ov5693_1424x1168_30fps[] = { + {OV5693_8BIT, 0x3501, 0x3b}, /* long exposure[15:8] */ + {OV5693_8BIT, 0x3502, 0x80}, /* long exposure[7:0] */ + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, /* TIMING_X_ADDR_START */ + {OV5693_8BIT, 0x3801, 0x50}, /* 80 */ + {OV5693_8BIT, 0x3802, 0x00}, /* TIMING_Y_ADDR_START */ + {OV5693_8BIT, 0x3803, 0x02}, /* 2 */ + {OV5693_8BIT, 0x3804, 0x09}, /* TIMING_X_ADDR_END */ + {OV5693_8BIT, 0x3805, 0xdd}, /* 2525 */ + {OV5693_8BIT, 0x3806, 0x07}, /* TIMING_Y_ADDR_END */ + {OV5693_8BIT, 0x3807, 0xa1}, /* 1953 */ + {OV5693_8BIT, 0x3808, 0x05}, /* TIMING_X_OUTPUT_SIZE */ + {OV5693_8BIT, 0x3809, 0x90}, /* 1424 */ + {OV5693_8BIT, 0x380a, 0x04}, /* TIMING_Y_OUTPUT_SIZE */ + {OV5693_8BIT, 0x380b, 0x90}, /* 1168 */ + {OV5693_8BIT, 0x380c, 0x0a}, /* TIMING_HTS */ + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, /* TIMING_VTS */ + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3810, 0x00}, /* TIMING_ISP_X_WIN */ + {OV5693_8BIT, 0x3811, 0x02}, /* 2 */ + {OV5693_8BIT, 0x3812, 0x00}, /* TIMING_ISP_Y_WIN */ + {OV5693_8BIT, 0x3813, 0x00}, /* 0 */ + {OV5693_8BIT, 0x3814, 0x11}, /* TIME_X_INC */ + {OV5693_8BIT, 0x3815, 0x11}, /* TIME_Y_INC */ + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, /* scale is auto enabled */ + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 3:2 Full FOV Output, expected FOV Res: 2560x1706 + * ISP Effect Res: 720x480 + * Sensor out: 736x496, DS From 2616x1764 + */ +static struct ov5693_reg const ov5693_736x496_30fps[] = { + {OV5693_8BIT, 0x3501, 0x3b}, /* long exposure[15:8] */ + {OV5693_8BIT, 0x3502, 0x80}, /* long exposure[7:0] */ + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, /* TIMING_X_ADDR_START */ + {OV5693_8BIT, 0x3801, 0x02}, /* 2 */ + {OV5693_8BIT, 0x3802, 0x00}, /* TIMING_Y_ADDR_START */ + {OV5693_8BIT, 0x3803, 0x62}, /* 98 */ + {OV5693_8BIT, 0x3804, 0x0a}, /* TIMING_X_ADDR_END */ + {OV5693_8BIT, 0x3805, 0x3b}, /* 2619 */ + {OV5693_8BIT, 0x3806, 0x07}, /* TIMING_Y_ADDR_END */ + {OV5693_8BIT, 0x3807, 0x43}, /* 1859 */ + {OV5693_8BIT, 0x3808, 0x02}, /* TIMING_X_OUTPUT_SIZE */ + {OV5693_8BIT, 0x3809, 0xe0}, /* 736 */ + {OV5693_8BIT, 0x380a, 0x01}, /* TIMING_Y_OUTPUT_SIZE */ + {OV5693_8BIT, 0x380b, 0xf0}, /* 496 */ + {OV5693_8BIT, 0x380c, 0x0a}, /* TIMING_HTS */ + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, /* TIMING_VTS */ + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3810, 0x00}, /* TIMING_ISP_X_WIN */ + {OV5693_8BIT, 0x3811, 0x02}, /* 2 */ + {OV5693_8BIT, 0x3812, 0x00}, /* TIMING_ISP_Y_WIN */ + {OV5693_8BIT, 0x3813, 0x00}, /* 0 */ + {OV5693_8BIT, 0x3814, 0x11}, /* TIME_X_INC */ + {OV5693_8BIT, 0x3815, 0x11}, /* TIME_Y_INC */ + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, /* scale is auto enabled */ + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_2576x1936_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0x00}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x0a}, + {OV5693_8BIT, 0x3809, 0x10}, + {OV5693_8BIT, 0x380a, 0x07}, + {OV5693_8BIT, 0x380b, 0x90}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x18}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +struct ov5693_resolution ov5693_res_preview[] = { + { + .desc = "ov5693_736x496_30fps", + .width = 736, + .height = 496, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_736x496_30fps, + }, + { + .desc = "ov5693_1616x1216_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1616x1216_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2576, + .height = 1456, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2576x1456_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2576, + .height = 1936, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2576x1936_30fps, + }, +}; +#define N_RES_PREVIEW (ARRAY_SIZE(ov5693_res_preview)) + +struct ov5693_resolution ov5693_res_still[] = { + { + .desc = "ov5693_736x496_30fps", + .width = 736, + .height = 496, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_736x496_30fps, + }, + { + .desc = "ov5693_1424x1168_30fps", + .width = 1424, + .height = 1168, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1424x1168_30fps, + }, + { + .desc = "ov5693_1616x1216_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1616x1216_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2592, + .height = 1456, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2592x1456_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2592, + .height = 1944, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2592x1944_30fps, + }, +}; +#define N_RES_STILL (ARRAY_SIZE(ov5693_res_still)) + +struct ov5693_resolution ov5693_res_video[] = { + { + .desc = "ov5693_736x496_30fps", + .width = 736, + .height = 496, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 1, + .regs = ov5693_736x496, + }, + { + .desc = "ov5693_336x256_30fps", + .width = 336, + .height = 256, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 1, + .regs = ov5693_336x256, + }, + { + .desc = "ov5693_368x304_30fps", + .width = 368, + .height = 304, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 1, + .regs = ov5693_368x304, + }, + { + .desc = "ov5693_192x160_30fps", + .width = 192, + .height = 160, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 1, + .regs = ov5693_192x160, + }, + { + .desc = "ov5693_1296x736_30fps", + .width = 1296, + .height = 736, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 0, + .regs = ov5693_1296x736, + }, + { + .desc = "ov5693_1296x976_30fps", + .width = 1296, + .height = 976, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 0, + .regs = ov5693_1296x976, + }, + { + .desc = "ov5693_1636P_30fps", + .width = 1636, + .height = 1096, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1636p_30fps, + }, + { + .desc = "ov5693_1080P_30fps", + .width = 1940, + .height = 1096, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1940x1096, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2592, + .height = 1456, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2592x1456_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2592, + .height = 1944, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2592x1944_30fps, + }, +}; +#define N_RES_VIDEO (ARRAY_SIZE(ov5693_res_video)) + +static struct ov5693_resolution *ov5693_res = ov5693_res_preview; +static int N_RES = N_RES_PREVIEW; +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov8858.c b/drivers/staging/media/atomisp/i2c/ov8858.c new file mode 100644 index 0000000..9574bc4 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov8858.c @@ -0,0 +1,2221 @@ +/* + * Support for OmniVision ov8858 camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include <linux/delay.h> +#include <linux/module.h> +#include <media/v4l2-device.h> +#include <linux/acpi.h> +#include "../include/linux/atomisp_gmin_platform.h" +#ifdef CONFIG_PLATFORM_BTNS +#include "ov8858_btns.h" +#else +#include "ov8858.h" +#endif +static int ov8858_i2c_read(struct i2c_client *client, u16 len, u16 addr, + u8 *buf) +{ + struct i2c_msg msg[2]; + u8 address[2]; + int err; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no adapter\n", __func__); + return -ENODEV; + } + + dev_dbg(&client->dev, "%s: len = %d, addr = 0x%04x\n", + __func__, len, addr); + + memset(msg, 0, sizeof(msg)); + + address[0] = (addr >> 8) & 0xff; + address[1] = addr & 0xff; + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = address; + + msg[1].addr = client->addr; + msg[1].len = len; + msg[1].flags = I2C_M_RD; + msg[1].buf = buf; + + err = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); + if (err != 2) { + if (err >= 0) + err = -EIO; + goto error; + } + + return 0; +error: + dev_err(&client->dev, "reading from address 0x%x error %d", addr, err); + return err; +} + +static int ov8858_read_reg(struct i2c_client *client, u16 type, u16 reg, + u16 *val) +{ + u8 data[OV8858_SHORT_MAX]; + int err; + + dev_dbg(&client->dev, "%s: type = %d, reg = 0x%04x\n", + __func__, type, reg); + + /* read only 8 and 16 bit values */ + if (type != OV8858_8BIT && type != OV8858_16BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(data, 0, sizeof(data)); + + err = ov8858_i2c_read(client, type, reg, data); + if (err) + goto error; + + /* high byte comes first */ + if (type == OV8858_8BIT) + *val = (u8)data[0]; + else + *val = data[0] << 8 | data[1]; + + dev_dbg(&client->dev, "%s: val = 0x%04x\n", __func__, *val); + + return 0; + +error: + dev_err(&client->dev, "read from offset 0x%x error %d", reg, err); + return err; +} + +static int ov8858_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int +ov8858_write_reg(struct i2c_client *client, u16 data_length, u16 reg, u16 val) +{ + int ret; + unsigned char data[4] = {0}; + u16 *wreg; + const u16 len = data_length + sizeof(u16); /* 16-bit address + data */ + + dev_dbg(&client->dev, + "%s: data_length = %d, reg = 0x%04x, val = 0x%04x\n", + __func__, data_length, reg, val); + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no adapter\n", __func__); + return -ENODEV; + } + + if (data_length != OV8858_8BIT && data_length != OV8858_16BIT) { + dev_err(&client->dev, "%s error, invalid length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + wreg = (u16 *)data; + *wreg = cpu_to_be16(reg); + + if (data_length == OV8858_8BIT) { + data[2] = (u8)(val); + } else { + /* OV8858_16BIT */ + u16 *wdata = (u16 *)&data[2]; + *wdata = be16_to_cpu(val); + } + + ret = ov8858_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * ov8858_write_reg_array - Initializes a list of registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __ov8858_flush_reg_array(), __ov8858_buf_reg_array() and + * __ov8858_write_reg_is_consecutive() are internal functions to + * ov8858_write_reg_array() and should be not used anywhere else. + * + */ +static int __ov8858_flush_reg_array(struct i2c_client *client, + struct ov8858_write_ctrl *ctrl) +{ + u16 size; + if (ctrl->index == 0) + return 0; + + size = sizeof(u16) + ctrl->index; /* 16-bit address + data */ + ctrl->buffer.addr = cpu_to_be16(ctrl->buffer.addr); + ctrl->index = 0; + + return ov8858_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __ov8858_buf_reg_array(struct i2c_client *client, + struct ov8858_write_ctrl *ctrl, + const struct ov8858_reg *next) +{ + int size; + u16 *data16; + + switch (next->type) { + case OV8858_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case OV8858_16BIT: + size = 2; + data16 = (u16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->sreg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u16) >= OV8858_MAX_WRITE_BUF_SIZE) + __ov8858_flush_reg_array(client, ctrl); + + return 0; +} + +static int +__ov8858_write_reg_is_consecutive(struct i2c_client *client, + struct ov8858_write_ctrl *ctrl, + const struct ov8858_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->sreg; +} + +static int ov8858_write_reg_array(struct i2c_client *client, + const struct ov8858_reg *reglist) +{ + const struct ov8858_reg *next = reglist; + struct ov8858_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != OV8858_TOK_TERM; next++) { + switch (next->type & OV8858_TOK_MASK) { + case OV8858_TOK_DELAY: + err = __ov8858_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceeding + */ + if (!__ov8858_write_reg_is_consecutive(client, + &ctrl, next)) { + err = __ov8858_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __ov8858_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, "%s: write error\n", + __func__); + return err; + } + break; + } + } + + return __ov8858_flush_reg_array(client, &ctrl); +} + +static int __ov8858_min_fps_diff(int fps, + const struct ov8858_fps_setting *fps_list) +{ + int diff = INT_MAX; + int i; + + if (fps == 0) + return 0; + + for (i = 0; i < MAX_FPS_OPTIONS_SUPPORTED; i++) { + if (!fps_list[i].fps) + break; + if (abs(fps_list[i].fps - fps) < diff) + diff = abs(fps_list[i].fps - fps); + } + + return diff; +} + +static int __ov8858_nearest_fps_index(int fps, + const struct ov8858_fps_setting *fps_list) +{ + int fps_index = 0; + int i; + + for (i = 0; i < MAX_FPS_OPTIONS_SUPPORTED; i++) { + if (!fps_list[i].fps) + break; + if (abs(fps_list[i].fps - fps) + < abs(fps_list[fps_index].fps - fps)) + fps_index = i; + } + return fps_index; +} + +static int __ov8858_update_frame_timing(struct v4l2_subdev *sd, + u16 *hts, u16 *vts) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + + dev_dbg(&client->dev, "%s OV8858_TIMING_HTS=0x%04x\n", + __func__, *hts); + + /* HTS = pixel_per_line / 2 */ + ret = ov8858_write_reg(client, OV8858_16BIT, + OV8858_TIMING_HTS, *hts >> 1); + if (ret) + return ret; + dev_dbg(&client->dev, "%s OV8858_TIMING_VTS=0x%04x\n", + __func__, *vts); + + return ov8858_write_reg(client, OV8858_16BIT, OV8858_TIMING_VTS, *vts); +} + +static int __ov8858_set_exposure(struct v4l2_subdev *sd, int exposure, int gain, + int dig_gain, u16 *hts, u16 *vts) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int exp_val, ret; + dev_dbg(&client->dev, "%s, exposure = %d, gain=%d, dig_gain=%d\n", + __func__, exposure, gain, dig_gain); + + if (dev->limit_exposure_flag) { + if (exposure > *vts - OV8858_INTEGRATION_TIME_MARGIN) + exposure = *vts - OV8858_INTEGRATION_TIME_MARGIN; + } else { + if (*vts < exposure + OV8858_INTEGRATION_TIME_MARGIN) + *vts = (u16) exposure + OV8858_INTEGRATION_TIME_MARGIN; + } + + ret = __ov8858_update_frame_timing(sd, hts, vts); + if (ret) + return ret; + + /* For ov8858, the low 4 bits are fraction bits and must be kept 0 */ + exp_val = exposure << 4; + ret = ov8858_write_reg(client, OV8858_8BIT, + OV8858_LONG_EXPO+2, exp_val & 0xFF); + if (ret) + return ret; + + ret = ov8858_write_reg(client, OV8858_8BIT, + OV8858_LONG_EXPO+1, (exp_val >> 8) & 0xFF); + if (ret) + return ret; + + ret = ov8858_write_reg(client, OV8858_8BIT, + OV8858_LONG_EXPO, (exp_val >> 16) & 0x0F); + if (ret) + return ret; + + /* Digital gain : to all MWB channel gains */ + if (dig_gain) { + ret = ov8858_write_reg(client, OV8858_16BIT, + OV8858_MWB_RED_GAIN_H, dig_gain); + if (ret) + return ret; + + ret = ov8858_write_reg(client, OV8858_16BIT, + OV8858_MWB_GREEN_GAIN_H, dig_gain); + if (ret) + return ret; + + ret = ov8858_write_reg(client, OV8858_16BIT, + OV8858_MWB_BLUE_GAIN_H, dig_gain); + if (ret) + return ret; + } + + ret = ov8858_write_reg(client, OV8858_16BIT, OV8858_LONG_GAIN, + gain & 0x07ff); + if (ret) + return ret; + + dev->gain = gain; + dev->exposure = exposure; + dev->digital_gain = dig_gain; + + return 0; +} + +static int ov8858_set_exposure(struct v4l2_subdev *sd, int exposure, int gain, + int dig_gain) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + const struct ov8858_resolution *res; + u16 hts, vts; + int ret; + + mutex_lock(&dev->input_lock); + + /* Validate exposure: cannot exceed 16bit value */ + exposure = clamp_t(int, exposure, 0, OV8858_MAX_EXPOSURE_VALUE); + + /* Validate gain: must not exceed maximum 8bit value */ + gain = clamp_t(int, gain, 0, OV8858_MAX_GAIN_VALUE); + + /* Validate digital gain: must not exceed 12 bit value*/ + dig_gain = clamp_t(int, dig_gain, 0, OV8858_MWB_GAIN_MAX); + + res = &dev->curr_res_table[dev->fmt_idx]; + /* + * Vendor: HTS reg value is half the total pixel line + */ + hts = res->fps_options[dev->fps_index].pixels_per_line; + vts = res->fps_options[dev->fps_index].lines_per_frame; + + ret = __ov8858_set_exposure(sd, exposure, gain, dig_gain, &hts, &vts); + + mutex_unlock(&dev->input_lock); + + return ret; +} + +/* + When exposure gain value set to sensor, the sensor changed value. + So we need the function to get real value + */ +static int ov8858_g_update_exposure(struct v4l2_subdev *sd, + struct atomisp_update_exposure *exposure) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int gain = exposure->gain; + + dev_dbg(&client->dev, "%s: gain: %d, digi_gain: %d\n", __func__, + exposure->gain, exposure->digi_gain); + exposure->update_digi_gain = dev->digital_gain; + /* This real gain value fetching function is provided by vendor */ + exposure->update_gain = (((gain & 0x700) >> 8) + 1) * (gain & 0xFF); + + return 0; +} + +static int ov8858_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + return ov8858_set_exposure(sd, exposure->integration_time[0], + exposure->gain[0], exposure->gain[1]); +} + +static int ov8858_priv_int_data_init(struct v4l2_subdev *sd) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u32 size = OV8858_OTP_END_ADDR - OV8858_OTP_START_ADDR + 1; + int r; + u16 isp_ctrl2 = 0; + + if (!dev->otp_data) { + dev->otp_data = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!dev->otp_data) { + dev_err(&client->dev, "%s: can't allocate memory", + __func__); + r = -ENOMEM; + goto error3; + } + + /* Streaming has to be on */ + r = ov8858_write_reg(client, OV8858_8BIT, OV8858_STREAM_MODE, + 0x01); + if (r) + goto error2; + + /* Turn off Dead Pixel Correction */ + r = ov8858_read_reg(client, OV8858_8BIT, + OV8858_OTP_ISP_CTRL2, &isp_ctrl2); + if (r) + goto error1; + + r = ov8858_write_reg(client, OV8858_8BIT, OV8858_OTP_ISP_CTRL2, + isp_ctrl2 & ~OV8858_OTP_DPC_ENABLE); + if (r) + goto error1; + + /* Enable partial OTP read mode */ + r = ov8858_write_reg(client, OV8858_8BIT, OV8858_OTP_MODE_CTRL, + OV8858_OTP_MODE_PROGRAM_DISABLE | + OV8858_OTP_MODE_MANUAL); + if (r) + goto error1; + + /* Set address range of OTP memory to read */ + r = ov8858_write_reg(client, OV8858_16BIT, + OV8858_OTP_START_ADDR_REG, + OV8858_OTP_START_ADDR); + if (r) + goto error1; + + r = ov8858_write_reg(client, OV8858_16BIT, + OV8858_OTP_END_ADDR_REG, + OV8858_OTP_END_ADDR); + if (r) + goto error1; + + /* Load the OTP data into the OTP buffer */ + r = ov8858_write_reg(client, OV8858_8BIT, OV8858_OTP_LOAD_CTRL, + OV8858_OTP_LOAD_ENABLE); + if (r) + goto error1; + + /* Wait for the data to load into the buffer */ + usleep_range(5000, 5500); + + /* Read the OTP data from the buffer */ + r = ov8858_i2c_read(client, size, OV8858_OTP_START_ADDR, + dev->otp_data); + if (r) + goto error1; + + /* Turn on Dead Pixel Correction */ + r = ov8858_write_reg(client, OV8858_8BIT, OV8858_OTP_ISP_CTRL2, + isp_ctrl2 | OV8858_OTP_DPC_ENABLE); + if (r) + goto error1; + + /* Stop streaming */ + r = ov8858_write_reg(client, 1, OV8858_STREAM_MODE, 0x00); + if (r) { + dev_err(&client->dev, "%s: cannot turn off streaming\n", + __func__); + goto error1; + } + } + + + return 0; + +error1: + /* Turn on Dead Pixel Correction and set streaming off */ + ov8858_write_reg(client, OV8858_8BIT, OV8858_OTP_ISP_CTRL2, + isp_ctrl2 | OV8858_OTP_DPC_ENABLE); + ov8858_write_reg(client, 1, OV8858_STREAM_MODE, 0x00); +error2: + devm_kfree(&client->dev, dev->otp_data); + dev->otp_data = NULL; +error3: + dev_err(&client->dev, "%s: OTP reading failed\n", __func__); + return r; +} + +static int ov8858_g_priv_int_data(struct v4l2_subdev *sd, + struct v4l2_private_int_data *priv) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u32 size = OV8858_OTP_END_ADDR - OV8858_OTP_START_ADDR + 1; + int r; + + mutex_lock(&dev->input_lock); + + if (!dev->otp_data) { + dev_err(&client->dev, "%s: otp data is NULL\n", __func__); + mutex_unlock(&dev->input_lock); + return -EFAULT; + } + + if (copy_to_user(priv->data, dev->otp_data, + min_t(__u32, priv->size, size))) { + r = -EFAULT; + dev_err(&client->dev, "%s: OTP reading failed\n", __func__); + mutex_unlock(&dev->input_lock); + return r; + } + + priv->size = size; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int __ov8858_init(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov8858_device *dev = to_ov8858_sensor(sd); + int ret; + dev_dbg(&client->dev, "%s\n", __func__); + + /* Sets the default FPS */ + dev->fps_index = 0; + + /* Set default exposure values (initially start values) */ + dev->exposure = 256; + dev->gain = 16; + dev->digital_gain = 1024; + dev->limit_exposure_flag = false; + + dev_dbg(&client->dev, "%s: Writing basic settings to ov8858\n", + __func__); + ret = ov8858_write_reg_array(client, ov8858_BasicSettings); + if (ret) + return ret; + + return ov8858_priv_int_data_init(sd); +} + +static int ov8858_init(struct v4l2_subdev *sd, u32 val) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ov8858_init(sd); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static void ov8858_uninit(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct v4l2_ctrl *ctrl; + dev_dbg(&client->dev, "%s:\n", __func__); + + dev->exposure = 0; + dev->gain = 0; + dev->digital_gain = 0; + dev->limit_exposure_flag = false; + mutex_unlock(&dev->input_lock); + ctrl = v4l2_ctrl_find(sd->ctrl_handler, + V4L2_CID_EXPOSURE_AUTO_PRIORITY); + if (ctrl) + v4l2_ctrl_s_ctrl(ctrl, V4L2_EXPOSURE_AUTO); + mutex_lock(&dev->input_lock); +} + +static int ov8858_g_comp_delay(struct v4l2_subdev *sd, unsigned int *usec) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov8858_device *dev = to_ov8858_sensor(sd); + int ret = 0, exposure; + u16 vts, data; + + if (dev->exposure == 0) { + ret = ov8858_read_reg(client, OV8858_16BIT, + OV8858_LONG_EXPO + 1, &data); + if (ret) + return ret; + exposure = data; + exposure >>= 4; + } else { + exposure = dev->exposure; + } + + ret = ov8858_read_reg(client, OV8858_16BIT, OV8858_TIMING_VTS, &vts); + if (ret || vts == 0) + vts = OV8858_DEPTH_VTS_CONST; + + *usec = (exposure * 33333 / vts); + if (*usec > OV8858_DEPTH_COMP_CONST) + *usec = *usec - OV8858_DEPTH_COMP_CONST; + else + *usec = OV8858_DEPTH_COMP_CONST; + + return 0; +} + +static long ov8858_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return ov8858_s_exposure(sd, (struct atomisp_exposure *)arg); + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + return ov8858_g_priv_int_data(sd, arg); + case ATOMISP_IOC_G_DEPTH_SYNC_COMP: + return ov8858_g_comp_delay(sd, (unsigned int *)arg); + case ATOMISP_IOC_G_UPDATE_EXPOSURE: + return ov8858_g_update_exposure(sd, + (struct atomisp_update_exposure *)arg); + default: + dev_dbg(&client->dev, "Unhandled command 0x%X\n", cmd); + return -EINVAL; + } +} + +static int __power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = 0; + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + if (dev->platform_data->v1p2_ctrl) { + ret = dev->platform_data->v1p2_ctrl(sd, flag); + if (ret) { + dev_err(&client->dev, + "failed to power %s 1.2v power rail\n", + flag ? "up" : "down"); + return ret; + } + } + + if (dev->platform_data->v2p8_ctrl) { + ret = dev->platform_data->v2p8_ctrl(sd, flag); + if (ret) { + dev_err(&client->dev, + "failed to power %s 2.8v power rail\n", + flag ? "up" : "down"); + return ret; + } + } + + if (dev->platform_data->v1p8_ctrl) { + ret = dev->platform_data->v1p8_ctrl(sd, flag); + if (ret) { + dev_err(&client->dev, + "failed to power %s 1.8v power rail\n", + flag ? "up" : "down"); + if (dev->platform_data->v2p8_ctrl) + dev->platform_data->v2p8_ctrl(sd, 0); + return ret; + } + } + + if (flag) + msleep(20); /* Wait for power lines to stabilize */ + return ret; +} + +static int __gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + struct i2c_client *client; + struct ov8858_device *dev; + + if (!sd) + return -EINVAL; + + client = v4l2_get_subdevdata(sd); + dev = to_ov8858_sensor(sd); + + if (!client || !dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + if (dev->platform_data->gpio0_ctrl) + return dev->platform_data->gpio0_ctrl(sd, flag); + + dev_err(&client->dev, "failed to find platform gpio callback\n"); + + return -EINVAL; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov8858_device *dev = to_ov8858_sensor(sd); + int ret; + dev_dbg(&client->dev, "%s\n", __func__); + + /* Enable power */ + ret = __power_ctrl(sd, 1); + if (ret) { + dev_err(&client->dev, "power rail on failed %d.\n", ret); + goto fail_power; + } + + /* Enable clock */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) { + dev_err(&client->dev, "flisclk on failed %d\n", ret); + goto fail_clk; + } + + /* Release reset */ + ret = __gpio_ctrl(sd, 1); + if (ret) { + dev_err(&client->dev, "gpio on failed %d\n", ret); + goto fail_gpio; + } + + /* Minumum delay is 8192 clock cycles before first i2c transaction, + * which is 1.37 ms at the lowest allowed clock rate 6 MHz */ + usleep_range(2000, 2500); + return 0; + +fail_gpio: + dev->platform_data->flisclk_ctrl(sd, 0); +fail_clk: + __power_ctrl(sd, 0); +fail_power: + dev_err(&client->dev, "Sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + dev_dbg(&client->dev, "%s\n", __func__); + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk off failed\n"); + + ret = __gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio off failed\n"); + + ret = __power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "power rail off failed.\n"); + + return ret; +} + +static int __ov8858_s_power(struct v4l2_subdev *sd, int on) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + int ret, r = 0; + + if (on == 0) { + ov8858_uninit(sd); + if (dev->vcm_driver && dev->vcm_driver->power_down) + r = dev->vcm_driver->power_down(sd); + ret = power_down(sd); + if (r != 0 && ret == 0) + ret = r; + } else { + ret = power_up(sd); + if (ret) + power_down(sd); + if (dev->vcm_driver && dev->vcm_driver->power_up) { + ret = dev->vcm_driver->power_up(sd); + if (ret) { + power_down(sd); + return ret; + } + } + return __ov8858_init(sd); + } + + return ret; +} + +static int ov8858_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + struct ov8858_device *dev = to_ov8858_sensor(sd); + + mutex_lock(&dev->input_lock); + ret = __ov8858_s_power(sd, on); + mutex_unlock(&dev->input_lock); + + /* + * FIXME: Compatibility with old behaviour: return to preview + * when the device is power cycled. + */ + if (!ret && on) + v4l2_ctrl_s_ctrl(dev->run_mode, ATOMISP_RUN_MODE_PREVIEW); + + return ret; +} + +/* + * Return value of the specified register, first try getting it from + * the register list and if not found, get from the sensor via i2c. + */ +static int ov8858_get_register(struct v4l2_subdev *sd, int reg, int type, + const struct ov8858_reg *reglist) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + const struct ov8858_reg *next; + u16 val; + + /* Try if the values are in the register list */ + for (next = reglist; next->type != OV8858_TOK_TERM; next++) { + if (next->sreg == reg) { + if (type == OV8858_8BIT) + return next->val; + + if (type == OV8858_16BIT && + next[1].type != OV8858_TOK_TERM) + return next[0].val << 8 | next[1].val; + } + } + + /* If not, read from sensor */ + if (ov8858_read_reg(client, type, reg, &val)) { + dev_err(&client->dev, "failed to read register 0x%08x\n", reg); + return -EIO; + } + + return val; +} + +static inline int ov8858_get_register_16bit(struct v4l2_subdev *sd, int reg, + const struct ov8858_reg *reglist) +{ + return ov8858_get_register(sd, reg, OV8858_16BIT, reglist); +} + +static inline int ov8858_get_register_8bit(struct v4l2_subdev *sd, int reg, + const struct ov8858_reg *reglist) +{ + return ov8858_get_register(sd, reg, OV8858_8BIT, reglist); +} + +static int __ov8858_get_pll1_values(struct v4l2_subdev *sd, + int *value, + const struct ov8858_reg *reglist) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int prediv_idx; + unsigned int multiplier; + unsigned int sys_prediv; + unsigned int prediv_coef[] = {2, 3, 4, 5, 6, 8, 12, 16}; + int ret; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL1_PREDIV0, reglist); + if (ret < 0) + return ret; + + if (ret & OV8858_PLL1_PREDIV0_MASK) + *value /= 2; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL1_PREDIV, reglist); + + if (ret < 0) + return ret; + + prediv_idx = ret & OV8858_PLL1_PREDIV_MASK; + *value = *value * 2 / prediv_coef[prediv_idx]; + + ret = ov8858_get_register_16bit(sd, OV8858_PLL1_MULTIPLIER, reglist); + if (ret < 0) + return ret; + + multiplier = ret; + *value *= multiplier & OV8858_PLL1_MULTIPLIER_MASK; + ret = ov8858_get_register_8bit(sd, OV8858_PLL1_SYS_PRE_DIV, reglist); + + if (ret < 0) + return ret; + + sys_prediv = ret & OV8858_PLL1_SYS_PRE_DIV_MASK; + *value /= (sys_prediv + 3); + ret = ov8858_get_register_8bit(sd, OV8858_PLL1_SYS_DIVIDER, reglist); + + if (ret < 0) + return ret; + + if (ret & OV8858_PLL1_SYS_DIVIDER_MASK) + *value /= 2; + + dev_dbg(&client->dev, "%s: *value: %d\n", __func__, *value); + + return 0; +} + +static int __ov8858_get_pll2a_values(struct v4l2_subdev *sd, int *value, + const struct ov8858_reg *reglist) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int prediv_idx; + unsigned int multiplier; + unsigned int prediv_coef[] = {2, 3, 4, 5, 6, 8, 12, 16}; + int ret; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL2_PREDIV0, reglist); + if (ret < 0) + return ret; + + if (ret & OV8858_PLL2_PREDIV0_MASK) + *value /= 2; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL2_PREDIV, reglist); + if (ret < 0) + return ret; + + prediv_idx = (ret & OV8858_PLL2_PREDIV_MASK); + *value = *value * 2 / prediv_coef[prediv_idx]; + + ret = ov8858_get_register_16bit(sd, OV8858_PLL2_MULTIPLIER, reglist); + if (ret < 0) + return ret; + + multiplier = ret; + *value *= multiplier & OV8858_PLL2_MULTIPLIER_MASK; + dev_dbg(&client->dev, "%s: *value: %d\n", __func__, *value); + + return 0; +} +static int __ov8858_get_pll2b_values(struct v4l2_subdev *sd, int *value, + const struct ov8858_reg *reglist) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int dac_divider; + int ret; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL2_DAC_DIVIDER, reglist); + if (ret < 0) + return ret; + + dac_divider = (ret & OV8858_PLL2_DAC_DIVIDER_MASK) + 1; + *value /= dac_divider; + + dev_dbg(&client->dev, "%s: *value: %d\n", __func__, *value); + + return 0; +} +static int __ov8858_get_pll2c_values(struct v4l2_subdev *sd, int *value, + const struct ov8858_reg *reglist) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int sys_pre_div; + unsigned int sys_divider_idx; + unsigned int sys_divider_coef[] = {2, 3, 4, 5, 6, 7, 8, 10}; + int ret; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL2_SYS_PRE_DIV, reglist); + if (ret < 0) + return ret; + + sys_pre_div = (ret & OV8858_PLL2_SYS_PRE_DIV_MASK) + 1; + *value /= sys_pre_div; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL2_SYS_DIVIDER, reglist); + if (ret < 0) + return ret; + + sys_divider_idx = ret & OV8858_PLL2_SYS_DIVIDER_MASK; + *value *= 2 / sys_divider_coef[sys_divider_idx]; + + dev_dbg(&client->dev, "%s: *value: %d\n", __func__, *value); + + return 0; +} + +static int ov8858_get_intg_factor(struct v4l2_subdev *sd, + struct camera_mipi_info *info, + const struct ov8858_reg *reglist) +{ + const unsigned int ext_clk = 19200000; /* Hz */ + struct atomisp_sensor_mode_data *m = &info->data; + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct device *d = &client->dev; + const struct ov8858_resolution *res = + &dev->curr_res_table[dev->fmt_idx]; + unsigned int pll_sclksel1; + unsigned int pll_sclksel2; + unsigned int sys_pre_div; + unsigned int sclk_pdiv; + unsigned int sclk = ext_clk; + u16 hts; + int ret; + + memset(&info->data, 0, sizeof(info->data)); + + ret = ov8858_get_register_8bit(sd, OV8858_PLL_SCLKSEL1, reglist); + if (ret < 0) + return ret; + + dev_dbg(d, "%s: OV8858_PLL_SCLKSEL1: 0x%02x\n", __func__, ret); + pll_sclksel1 = ret & OV8858_PLL_SCLKSEL1_MASK; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL_SCLKSEL2, reglist); + if (ret < 0) + return ret; + + dev_dbg(d, "%s: OV8858_PLL_SCLKSEL2: 0x%02x\n", __func__, ret); + pll_sclksel2 = ret & OV8858_PLL_SCLKSEL2_MASK; + + if (pll_sclksel2) { + ret = __ov8858_get_pll2a_values(sd, &sclk, reglist); + if (ret < 0) + return ret; + ret = __ov8858_get_pll2b_values(sd, &sclk, reglist); + if (ret < 0) + return ret; + } else if (pll_sclksel1) { + ret = __ov8858_get_pll2a_values(sd, &sclk, reglist); + if (ret < 0) + return ret; + ret = __ov8858_get_pll2c_values(sd, &sclk, reglist); + if (ret < 0) + return ret; + } else { + ret = __ov8858_get_pll1_values(sd, &sclk, reglist); + if (ret < 0) + return ret; + } + + ret = ov8858_get_register_8bit(sd, OV8858_SRB_HOST_INPUT_DIS, reglist); + if (ret < 0) + return ret; + + dev_dbg(d, "%s: OV8858_SRB_HOST_INPUT_DIS: 0x%02x\n", __func__, ret); + + sys_pre_div = ret & OV8858_SYS_PRE_DIV_MASK; + sys_pre_div >>= OV8858_SYS_PRE_DIV_OFFSET; + + if (sys_pre_div == 1) + sclk /= 2; + else if (sys_pre_div == 2) + sclk /= 4; + + sclk_pdiv = ret & OV8858_SCLK_PDIV_MASK; + sclk_pdiv >>= OV8858_SCLK_PDIV_OFFSET; + + if (sclk_pdiv > 1) + sclk /= sclk_pdiv; + + dev_dbg(d, "%s: sclk: %d\n", __func__, sclk); + + dev->vt_pix_clk_freq_mhz = sclk; + m->vt_pix_clk_freq_mhz = sclk; + + /* HTS and VTS */ + m->frame_length_lines = + res->fps_options[dev->fps_index].lines_per_frame; + m->line_length_pck = res->fps_options[dev->fps_index].pixels_per_line; + + m->coarse_integration_time_min = 0; + m->coarse_integration_time_max_margin = OV8858_INTEGRATION_TIME_MARGIN; + ret = ov8858_read_reg(client, OV8858_16BIT, OV8858_TIMING_HTS, &hts); + if (ret < 0) + return ret; + m->hts = hts; + dev_dbg(&client->dev, "%s: get HTS %d\n", __func__, hts); + + /* OV Sensor do not use fine integration time. */ + m->fine_integration_time_min = 0; + m->fine_integration_time_max_margin = 0; + + /* + * read_mode indicate whether binning is used for calculating + * the correct exposure value from the user side. So adapt the + * read mode values accordingly. + */ + m->read_mode = res->bin_factor_x ? + OV8858_READ_MODE_BINNING_ON : OV8858_READ_MODE_BINNING_OFF; + + ret = ov8858_get_register_8bit(sd, OV8858_H_INC_ODD, res->regs); + if (ret < 0) + return ret; + m->binning_factor_x = (ret + 1) / 2; + + ret = ov8858_get_register_8bit(sd, OV8858_V_INC_ODD, res->regs); + if (ret < 0) + return ret; + m->binning_factor_y = (ret + 1) / 2; + + /* Get the cropping and output resolution to ISP for this mode. */ + ret = ov8858_get_register_16bit(sd, OV8858_HORIZONTAL_START_H, + res->regs); + if (ret < 0) + return ret; + + m->crop_horizontal_start = ret; + + ret = ov8858_get_register_16bit(sd, OV8858_VERTICAL_START_H, res->regs); + if (ret < 0) + return ret; + + m->crop_vertical_start = ret; + + ret = ov8858_get_register_16bit(sd, OV8858_HORIZONTAL_END_H, res->regs); + if (ret < 0) + return ret; + + m->crop_horizontal_end = ret; + + ret = ov8858_get_register_16bit(sd, OV8858_VERTICAL_END_H, res->regs); + if (ret < 0) + return ret; + + m->crop_vertical_end = ret; + + ret = ov8858_get_register_16bit(sd, OV8858_HORIZONTAL_OUTPUT_SIZE_H, + res->regs); + if (ret < 0) + return ret; + + m->output_width = ret; + + ret = ov8858_get_register_16bit(sd, OV8858_VERTICAL_OUTPUT_SIZE_H, + res->regs); + if (ret < 0) + return ret; + + m->output_height = ret; + + return 0; +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between res_w/res_h and w/h. + * distance = (res_w/res_h - w/h) / (w/h) * 8192 + * res->width/height smaller than w/h wouldn't be considered. + * The gap of ratio larger than 1/8 wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 1024 +static int distance(struct ov8858_resolution const *res, const u32 w, + const u32 h) +{ + int ratio; + int distance; + + if (w == 0 || h == 0 || + res->width < w || res->height < h) + return -1; + + ratio = res->width << 13; + ratio /= w; + ratio *= h; + ratio /= res->height; + + distance = abs(ratio - 8192); + + if (distance > LARGEST_ALLOWED_RATIO_MISMATCH) + return -1; + return distance; +} + +/* + * Returns the nearest higher resolution index. + * @w: width + * @h: height + * matching is done based on enveloping resolution and + * aspect ratio. If the aspect ratio cannot be matched + * to any index, -1 is returned. + */ +static int nearest_resolution_index(struct v4l2_subdev *sd, int w, int h) +{ + int i; + int idx = -1; + int dist; + int fps_diff; + int min_fps_diff = INT_MAX; + int min_dist = INT_MAX; + int min_res_w = INT_MAX; + const struct ov8858_resolution *tmp_res = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov8858_device *dev = to_ov8858_sensor(sd); + dev_dbg(&client->dev, "%s: w=%d, h=%d\n", __func__, w, h); + + for (i = 0; i < dev->entries_curr_table; i++) { + tmp_res = &dev->curr_res_table[i]; + dist = distance(tmp_res, w, h); + dev_dbg(&client->dev, + "%s[%d]: %dx%d distance=%d\n", tmp_res->desc, + i, tmp_res->width, tmp_res->height, dist); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + min_res_w = tmp_res->width; + min_fps_diff = __ov8858_min_fps_diff(dev->fps, + tmp_res->fps_options); + idx = i; + } + if (dist == min_dist) { + fps_diff = __ov8858_min_fps_diff(dev->fps, + tmp_res->fps_options); + if (fps_diff < min_fps_diff) { + min_fps_diff = fps_diff; + idx = i; + } + if (tmp_res->width < min_res_w) { + min_res_w = tmp_res->width; + idx = i; + } + } + } + + return idx; +} + +static int ov8858_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct camera_mipi_info *ov8858_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + const struct ov8858_resolution *res; + int ret; + int idx; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + ov8858_info = v4l2_get_subdev_hostdata(sd); + if (ov8858_info == NULL) + return -EINVAL; + + mutex_lock(&dev->input_lock); + + if ((fmt->width > OV8858_RES_WIDTH_MAX) || + (fmt->height > OV8858_RES_HEIGHT_MAX)) { + fmt->width = OV8858_RES_WIDTH_MAX; + fmt->height = OV8858_RES_HEIGHT_MAX; + } else { + idx = nearest_resolution_index(sd, fmt->width, fmt->height); + + /* + * nearest_resolution_index() doesn't return smaller + * resolutions. If it fails, it means the requested resolution + * is higher than we can support. Fallback to highest possible + * resolution in this case. + */ + if (idx == -1) + idx = dev->entries_curr_table - 1; + + fmt->width = dev->curr_res_table[idx].width; + fmt->height = dev->curr_res_table[idx].height; + } + + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + dev->fmt_idx = nearest_resolution_index(sd, fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + ret = -EINVAL; + goto out; + } + res = &dev->curr_res_table[dev->fmt_idx]; + dev_dbg(&client->dev, "%s: selected width = %d, height = %d\n", + __func__, res->width, res->height); + + /* Adjust the FPS selection based on the resolution selected */ + dev->fps_index = __ov8858_nearest_fps_index(dev->fps, res->fps_options); + dev->fps = res->fps_options[dev->fps_index].fps; + dev->regs = res->fps_options[dev->fps_index].regs; + if (!dev->regs) + dev->regs = res->regs; + + ret = ov8858_write_reg_array(client, dev->regs); + if (ret) + goto out; + + dev->pixels_per_line = res->fps_options[dev->fps_index].pixels_per_line; + dev->lines_per_frame = res->fps_options[dev->fps_index].lines_per_frame; + + /* ov8858 only support RGB RAW10 output */ + ov8858_info->metadata_width = res->width * 10 / 8; + ov8858_info->metadata_height = 2; + ov8858_info->metadata_format = ATOMISP_INPUT_FORMAT_EMBEDDED; + + /* Set the initial exposure */ + ret = __ov8858_set_exposure(sd, dev->exposure, dev->gain, + dev->digital_gain, &dev->pixels_per_line, + &dev->lines_per_frame); + if (ret) + goto out; + + ret = ov8858_get_intg_factor(sd, ov8858_info, dev->regs); + +out: + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int ov8858_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov8858_device *dev = to_ov8858_sensor(sd); + + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + mutex_lock(&dev->input_lock); + fmt->width = dev->curr_res_table[dev->fmt_idx].width; + fmt->height = dev->curr_res_table[dev->fmt_idx].height; + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int ov8858_detect(struct i2c_client *client, u16 *id) +{ + struct i2c_adapter *adapter = client->adapter; + u16 id_hi = 0; + u16 id_low = 0; + int ret; + + /* i2c check */ + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + dev_dbg(&client->dev, "%s: I2C functionality ok\n", __func__); + ret = ov8858_read_reg(client, OV8858_8BIT, OV8858_CHIP_ID_HIGH, &id_hi); + if (ret) + return ret; + dev_dbg(&client->dev, "%s: id_high = 0x%04x\n", __func__, id_hi); + ret = ov8858_read_reg(client, OV8858_8BIT, OV8858_CHIP_ID_LOW, &id_low); + if (ret) + return ret; + dev_dbg(&client->dev, "%s: id_low = 0x%04x\n", __func__, id_low); + *id = (id_hi << 8) | id_low; + + dev_dbg(&client->dev, "%s: chip_id = 0x%04x\n", __func__, *id); + + dev_info(&client->dev, "%s: chip_id = 0x%04x\n", __func__, *id); + if (*id != OV8858_CHIP_ID) + return -ENODEV; + + /* Stream off now. */ + return ov8858_write_reg(client, OV8858_8BIT, OV8858_STREAM_MODE, 0); +} + +static void __ov8858_print_timing(struct v4l2_subdev *sd) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 width = dev->curr_res_table[dev->fmt_idx].width; + u16 height = dev->curr_res_table[dev->fmt_idx].height; + + dev_dbg(&client->dev, "Dump ov8858 timing in stream on:\n"); + dev_dbg(&client->dev, "width: %d:\n", width); + dev_dbg(&client->dev, "height: %d:\n", height); + dev_dbg(&client->dev, "pixels_per_line: %d:\n", dev->pixels_per_line); + dev_dbg(&client->dev, "line per frame: %d:\n", dev->lines_per_frame); + dev_dbg(&client->dev, "pix freq: %d:\n", dev->vt_pix_clk_freq_mhz); + /* updated formula: pixels_per_line = 2 * HTS */ + /* updated formula: fps = SCLK / (VTS * HTS) */ + dev_dbg(&client->dev, "init fps: %d:\n", dev->vt_pix_clk_freq_mhz / + (dev->pixels_per_line / 2) / dev->lines_per_frame); + dev_dbg(&client->dev, "HBlank: %d nS:\n", + 1000 * (dev->pixels_per_line - width) / + (dev->vt_pix_clk_freq_mhz / 1000000)); + dev_dbg(&client->dev, "VBlank: %d uS:\n", + (dev->lines_per_frame - height) * dev->pixels_per_line / + (dev->vt_pix_clk_freq_mhz / 1000000)); +} + +/* + * ov8858 stream on/off + */ +static int ov8858_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u16 val; + dev_dbg(&client->dev, "%s: enable = %d\n", __func__, enable); + + /* Set orientation */ + ret = ov8858_read_reg(client, OV8858_8BIT, OV8858_FORMAT2, &val); + if (ret) + return ret; + + ret = ov8858_write_reg(client, OV8858_8BIT, OV8858_FORMAT2, + dev->hflip ? val | OV8858_FLIP_ENABLE : + val & ~OV8858_FLIP_ENABLE); + if (ret) + return ret; + + ret = ov8858_read_reg(client, OV8858_8BIT, OV8858_FORMAT1, &val); + if (ret) + return ret; + + ret = ov8858_write_reg(client, OV8858_8BIT, OV8858_FORMAT1, + dev->vflip ? val | OV8858_FLIP_ENABLE : + val & ~OV8858_FLIP_ENABLE); + if (ret) + return ret; + + mutex_lock(&dev->input_lock); + if (enable) { + __ov8858_print_timing(sd); + ret = ov8858_write_reg_array(client, ov8858_streaming); + if (ret != 0) { + dev_err(&client->dev, "write_reg_array err\n"); + goto out; + } + dev->streaming = 1; + } else { + ret = ov8858_write_reg_array(client, ov8858_soft_standby); + if (ret != 0) { + dev_err(&client->dev, "write_reg_array err\n"); + goto out; + } + dev->streaming = 0; + dev->fps_index = 0; + dev->fps = 0; + } +out: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int __update_ov8858_device_settings(struct ov8858_device *dev, + u16 sensor_id) +{ + if (sensor_id == OV8858_CHIP_ID) +#ifdef CONFIG_PLATFORM_BTNS + dev->vcm_driver = &ov8858_vcms[OV8858_ID_DEFAULT]; +#else + dev->vcm_driver = &ov8858_vcms[OV8858_SUNNY]; +#endif + else + return -ENODEV; + + if (dev->vcm_driver && dev->vcm_driver->init) + return dev->vcm_driver->init(&dev->sd); + + return 0; +} + +static int ov8858_s_config(struct v4l2_subdev *sd, + int irq, void *pdata) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 sensor_id; + int ret; + + if (pdata == NULL) + return -ENODEV; + + dev->platform_data = pdata; + + mutex_lock(&dev->input_lock); + + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) { + mutex_unlock(&dev->input_lock); + dev_err(&client->dev, "platform init error %d!\n", ret); + return ret; + } + } + + ret = __ov8858_s_power(sd, 1); + if (ret) { + dev_err(&client->dev, "power-up error %d!\n", ret); + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = ov8858_detect(client, &sensor_id); + if (ret) { + dev_err(&client->dev, "detect error %d!\n", ret); + goto fail_detect; + } + + dev->sensor_id = sensor_id; + + /* power off sensor */ + ret = __ov8858_s_power(sd, 0); + if (ret) { + dev->platform_data->csi_cfg(sd, 0); + dev_err(&client->dev, "__ov8858_s_power-down error %d!\n", ret); + goto fail_update; + } + + /* Resolution settings depend on sensor type and platform */ + ret = __update_ov8858_device_settings(dev, dev->sensor_id); + if (ret) { + dev->platform_data->csi_cfg(sd, 0); + dev_err(&client->dev, "__update_ov8858_device_settings error %d!\n", ret); + goto fail_update; + } + + mutex_unlock(&dev->input_lock); + return ret; + +fail_detect: + dev->platform_data->csi_cfg(sd, 0); +fail_csi_cfg: + __ov8858_s_power(sd, 0); +fail_update: + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + mutex_unlock(&dev->input_lock); + dev_err(&client->dev, "sensor power-gating failed\n"); + return ret; +} + +static int +ov8858_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index) + return -EINVAL; + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + + return 0; +} + +static int +ov8858_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + struct ov8858_device *dev = to_ov8858_sensor(sd); + + mutex_lock(&dev->input_lock); + if (index >= dev->entries_curr_table) { + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + fse->min_width = dev->curr_res_table[index].width; + fse->min_height = dev->curr_res_table[index].height; + fse->max_width = dev->curr_res_table[index].width; + fse->max_height = dev->curr_res_table[index].height; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int ov8858_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov8858_device *dev = container_of( + ctrl->handler, struct ov8858_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + + /* input_lock is taken by the control framework, so it + * doesn't need to be taken here. + */ + + switch (ctrl->id) { + case V4L2_CID_RUN_MODE: + switch (ctrl->val) { + case ATOMISP_RUN_MODE_VIDEO: + dev->curr_res_table = ov8858_res_video; + dev->entries_curr_table = ARRAY_SIZE(ov8858_res_video); + break; + case ATOMISP_RUN_MODE_STILL_CAPTURE: + dev->curr_res_table = ov8858_res_still; + dev->entries_curr_table = ARRAY_SIZE(ov8858_res_still); + break; + default: + dev->curr_res_table = ov8858_res_preview; + dev->entries_curr_table = + ARRAY_SIZE(ov8858_res_preview); + } + + dev->fmt_idx = 0; + dev->fps_index = 0; + + return 0; + case V4L2_CID_FOCUS_ABSOLUTE: + if (dev->vcm_driver && dev->vcm_driver->t_focus_abs) + return dev->vcm_driver->t_focus_abs(&dev->sd, + ctrl->val); + return 0; + case V4L2_CID_EXPOSURE_AUTO_PRIORITY: + if (ctrl->val == V4L2_EXPOSURE_AUTO) + dev->limit_exposure_flag = false; + else if (ctrl->val == V4L2_EXPOSURE_APERTURE_PRIORITY) + dev->limit_exposure_flag = true; + return 0; + case V4L2_CID_HFLIP: + dev->hflip = ctrl->val; + return 0; + case V4L2_CID_VFLIP: + dev->vflip = ctrl->val; + return 0; + default: + dev_err(&client->dev, "%s: Error: Invalid ctrl: 0x%X\n", + __func__, ctrl->id); + return -EINVAL; + } +} + +static int ov8858_g_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov8858_device *dev = container_of( + ctrl->handler, struct ov8858_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int r_odd, r_even; + int i = dev->fmt_idx; + + switch (ctrl->id) { + case V4L2_CID_FOCUS_STATUS: + if (dev->vcm_driver && dev->vcm_driver->q_focus_status) + return dev->vcm_driver->q_focus_status(&dev->sd, + &(ctrl->val)); + return 0; + case V4L2_CID_BIN_FACTOR_HORZ: + r_odd = ov8858_get_register_8bit(&dev->sd, OV8858_H_INC_ODD, + dev->curr_res_table[i].regs); + if (r_odd < 0) + return r_odd; + r_even = ov8858_get_register_8bit(&dev->sd, OV8858_H_INC_EVEN, + dev->curr_res_table[i].regs); + if (r_even < 0) + return r_even; + ctrl->val = fls(r_odd + (r_even)) - 2; + return 0; + + case V4L2_CID_BIN_FACTOR_VERT: + r_odd = ov8858_get_register_8bit(&dev->sd, OV8858_V_INC_ODD, + dev->curr_res_table[i].regs); + if (r_odd < 0) + return r_odd; + r_even = ov8858_get_register_8bit(&dev->sd, OV8858_V_INC_EVEN, + dev->curr_res_table[i].regs); + if (r_even < 0) + return r_even; + ctrl->val = fls(r_odd + (r_even)) - 2; + return 0; + case V4L2_CID_HFLIP: + ctrl->val = dev->hflip; + break; + case V4L2_CID_VFLIP: + ctrl->val = dev->vflip; + break; + case V4L2_CID_EXPOSURE_ABSOLUTE: + ctrl->val = dev->exposure; + break; + default: + dev_warn(&client->dev, + "%s: Error: Invalid ctrl: 0x%X\n", __func__, ctrl->id); + return -EINVAL; + } + + return 0; +} + +static int +ov8858_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + const struct ov8858_resolution *res = + &dev->curr_res_table[dev->fmt_idx]; + + mutex_lock(&dev->input_lock); + interval->interval.denominator = res->fps_options[dev->fps_index].fps; + interval->interval.numerator = 1; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int __ov8858_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + const struct ov8858_resolution *res = + &dev->curr_res_table[dev->fmt_idx]; + struct camera_mipi_info *info = NULL; + unsigned int fps_index; + int ret = 0; + int fps; + + info = v4l2_get_subdev_hostdata(sd); + if (info == NULL) + return -EINVAL; + + if (!interval->interval.numerator) + interval->interval.numerator = 1; + + fps = interval->interval.denominator / interval->interval.numerator; + + /* No need to proceed further if we are not streaming */ + if (!dev->streaming) { + /* Save the new FPS and use it while selecting setting */ + dev->fps = fps; + return 0; + } + + /* Ignore if we are already using the required FPS. */ + if (fps == res->fps_options[dev->fps_index].fps) + return 0; + + fps_index = __ov8858_nearest_fps_index(fps, res->fps_options); + + if (res->fps_options[fps_index].regs && + res->fps_options[fps_index].regs != dev->regs) { + dev_err(&client->dev, + "Sensor is streaming, can't apply new configuration\n"); + return -EBUSY; + } + + dev->fps_index = fps_index; + dev->fps = res->fps_options[dev->fps_index].fps; + + /* Update the new frametimings based on FPS */ + dev->pixels_per_line = + res->fps_options[dev->fps_index].pixels_per_line; + dev->lines_per_frame = + res->fps_options[dev->fps_index].lines_per_frame; + + /* update frametiming. Conside the curren exposure/gain as well */ + ret = __ov8858_update_frame_timing(sd, + &dev->pixels_per_line, &dev->lines_per_frame); + if (ret) + return ret; + + /* Update the new values so that user side knows the current settings */ + ret = ov8858_get_intg_factor(sd, info, dev->regs); + if (ret) + return ret; + + interval->interval.denominator = res->fps_options[dev->fps_index].fps; + interval->interval.numerator = 1; + __ov8858_print_timing(sd); + + return ret; +} + +static int ov8858_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ov8858_s_frame_interval(sd, interval); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int ov8858_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = dev->curr_res_table[dev->fmt_idx].skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops ov8858_sensor_ops = { + .g_skip_frames = ov8858_g_skip_frames, +}; + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = ov8858_s_ctrl, + .g_volatile_ctrl = ov8858_g_ctrl, +}; + +static const struct v4l2_subdev_video_ops ov8858_video_ops = { + .s_stream = ov8858_s_stream, + .g_frame_interval = ov8858_g_frame_interval, + .s_frame_interval = ov8858_s_frame_interval, +}; + +static const struct v4l2_subdev_core_ops ov8858_core_ops = { + .s_power = ov8858_s_power, + .ioctl = ov8858_ioctl, + .init = ov8858_init, +}; + +static const struct v4l2_subdev_pad_ops ov8858_pad_ops = { + .enum_mbus_code = ov8858_enum_mbus_code, + .enum_frame_size = ov8858_enum_frame_size, + .get_fmt = ov8858_get_fmt, + .set_fmt = ov8858_set_fmt, +}; + +static const struct v4l2_subdev_ops ov8858_ops = { + .core = &ov8858_core_ops, + .video = &ov8858_video_ops, + .pad = &ov8858_pad_ops, + .sensor = &ov8858_sensor_ops, +}; + +static const struct media_entity_operations ov_entity_ops = { + .link_setup = NULL, +}; + +static int ov8858_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov8858_device *dev = to_ov8858_sensor(sd); + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + dev->platform_data->csi_cfg(sd, 0); + v4l2_device_unregister_subdev(sd); + kfree(dev); + + return 0; +} + +static const char * const ctrl_run_mode_menu[] = { + NULL, + "Video", + "Still capture", + "Continuous capture", + "Preview", +}; + +static const struct v4l2_ctrl_config ctrl_run_mode = { + .ops = &ctrl_ops, + .id = V4L2_CID_RUN_MODE, + .name = "run mode", + .type = V4L2_CTRL_TYPE_MENU, + .min = 1, + .def = 4, + .max = 4, + .qmenu = ctrl_run_mode_menu, +}; + +static const struct v4l2_ctrl_config ctrls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .name = "Vertical flip", + .type = V4L2_CTRL_TYPE_BOOLEAN, + .min = false, + .max = true, + .step = 1, + }, { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .name = "Horizontal flip", + .type = V4L2_CTRL_TYPE_BOOLEAN, + .min = false, + .max = true, + .step = 1, + }, { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .name = "Absolute exposure", + .type = V4L2_CTRL_TYPE_INTEGER, + .max = 0xffff, + .min = 0x0, + .step = 1, + .def = 0x00, + .flags = V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_VOLATILE, + }, { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_ABSOLUTE, + .name = "Focus absolute", + .type = V4L2_CTRL_TYPE_INTEGER, + .step = 1, + .max = OV8858_MAX_FOCUS_POS, + }, { + /* This one is junk: see the spec for proper use of this CID. */ + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_STATUS, + .name = "Focus status", + .type = V4L2_CTRL_TYPE_INTEGER, + .step = 1, + .max = 100, + .flags = V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_VOLATILE, + }, { + /* This is crap. For compatibility use only. */ + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .name = "Focal lenght", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = (OV8858_FOCAL_LENGTH_NUM << 16) | + OV8858_FOCAL_LENGTH_DEM, + .max = (OV8858_FOCAL_LENGTH_NUM << 16) | + OV8858_FOCAL_LENGTH_DEM, + .step = 1, + .def = (OV8858_FOCAL_LENGTH_NUM << 16) | + OV8858_FOCAL_LENGTH_DEM, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + }, { + /* This one is crap, too. For compatibility use only. */ + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .name = "F-number", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = (OV8858_F_NUMBER_DEFAULT_NUM << 16) | + OV8858_F_NUMBER_DEM, + .max = (OV8858_F_NUMBER_DEFAULT_NUM << 16) | + OV8858_F_NUMBER_DEM, + .step = 1, + .def = (OV8858_F_NUMBER_DEFAULT_NUM << 16) | + OV8858_F_NUMBER_DEM, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + }, { + /* + * The most utter crap. _Never_ use this, even for + * compatibility reasons! + */ + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .name = "F-number range", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = (OV8858_F_NUMBER_DEFAULT_NUM << 24) | + (OV8858_F_NUMBER_DEM << 16) | + (OV8858_F_NUMBER_DEFAULT_NUM << 8) | + OV8858_F_NUMBER_DEM, + .max = (OV8858_F_NUMBER_DEFAULT_NUM << 24) | + (OV8858_F_NUMBER_DEM << 16) | + (OV8858_F_NUMBER_DEFAULT_NUM << 8) | + OV8858_F_NUMBER_DEM, + .step = 1, + .def = (OV8858_F_NUMBER_DEFAULT_NUM << 24) | + (OV8858_F_NUMBER_DEM << 16) | + (OV8858_F_NUMBER_DEFAULT_NUM << 8) | + OV8858_F_NUMBER_DEM, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + }, { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .name = "Horizontal binning factor", + .type = V4L2_CTRL_TYPE_INTEGER, + .max = OV8858_BIN_FACTOR_MAX, + .step = 1, + .flags = V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_VOLATILE, + }, { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .name = "Vertical binning factor", + .type = V4L2_CTRL_TYPE_INTEGER, + .max = OV8858_BIN_FACTOR_MAX, + .step = 1, + .flags = V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_VOLATILE, + }, { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_AUTO_PRIORITY, + .name = "Exposure auto priority", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = V4L2_EXPOSURE_AUTO, + .max = V4L2_EXPOSURE_APERTURE_PRIORITY, + .step = 1, + } +}; + +static int ov8858_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ov8858_device *dev; + unsigned int i; + int ret = 0; + struct camera_sensor_platform_data *pdata; + + dev_dbg(&client->dev, "%s:\n", __func__); + + /* allocate sensor device & init sub device */ + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "%s: out of memory\n", __func__); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + if (id) + dev->i2c_id = id->driver_data; + dev->fmt_idx = 0; + dev->sensor_id = OV_ID_DEFAULT; + dev->vcm_driver = &ov8858_vcms[OV8858_ID_DEFAULT]; + + v4l2_i2c_subdev_init(&(dev->sd), client, &ov8858_ops); + + if (ACPI_COMPANION(&client->dev)) { + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_bggr); + if (!pdata) { + dev_err(&client->dev, + "%s: failed to get acpi platform data\n", + __func__); + goto out_free; + } + ret = ov8858_s_config(&dev->sd, client->irq, pdata); + if (ret) { + dev_err(&client->dev, + "%s: failed to set config\n", __func__); + goto out_free; + } + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) { + dev_err(&client->dev, + "%s: failed to register subdev\n", __func__); + goto out_free; + } + } + /* + * sd->name is updated with sensor driver name by the v4l2. + * change it to sensor name in this case. + */ + snprintf(dev->sd.name, sizeof(dev->sd.name), "%s%x %d-%04x", + OV_SUBDEV_PREFIX, dev->sensor_id, + i2c_adapter_id(client->adapter), client->addr); + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; + dev->sd.entity.ops = &ov_entity_ops; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + ret = v4l2_ctrl_handler_init(&dev->ctrl_handler, ARRAY_SIZE(ctrls) + 1); + if (ret) { + ov8858_remove(client); + return ret; + } + + dev->run_mode = v4l2_ctrl_new_custom(&dev->ctrl_handler, + &ctrl_run_mode, NULL); + + for (i = 0; i < ARRAY_SIZE(ctrls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &ctrls[i], NULL); + + if (dev->ctrl_handler.error) { + ov8858_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + v4l2_ctrl_handler_setup(&dev->ctrl_handler); + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) { + ov8858_remove(client); + return ret; + } + + return 0; + +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +static const struct i2c_device_id ov8858_id[] = { + {OV8858_NAME, 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, ov8858_id); + +static struct acpi_device_id ov8858_acpi_match[] = { + {"INT3477"}, + {}, +}; + +static struct i2c_driver ov8858_driver = { + .driver = { + .name = OV8858_NAME, + .acpi_match_table = ACPI_PTR(ov8858_acpi_match), + }, + .probe = ov8858_probe, + .remove = ov8858_remove, + .id_table = ov8858_id, +}; + +static __init int ov8858_init_mod(void) +{ + return i2c_add_driver(&ov8858_driver); +} + +static __exit void ov8858_exit_mod(void) +{ + i2c_del_driver(&ov8858_driver); +} + +module_init(ov8858_init_mod); +module_exit(ov8858_exit_mod); + +MODULE_DESCRIPTION("A low-level driver for Omnivision OV8858 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/ov8858.h b/drivers/staging/media/atomisp/i2c/ov8858.h new file mode 100644 index 0000000..9be6a0e --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov8858.h @@ -0,0 +1,1482 @@ +/* + * Support for the Omnivision OV8858 camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __OV8858_H__ +#define __OV8858_H__ +#include "../include/linux/atomisp_platform.h" +#include <media/v4l2-ctrls.h> + +#define I2C_MSG_LENGTH 0x2 + +/* + * This should be added into include/linux/videodev2.h + * NOTE: This is most likely not used anywhere. + */ +#define V4L2_IDENT_OV8858 V4L2_IDENT_UNKNOWN + +/* + * Indexes for VCM driver lists + */ +#define OV8858_ID_DEFAULT 0 +#define OV8858_SUNNY 1 + +#define OV8858_OTP_START_ADDR 0x7010 +#define OV8858_OTP_END_ADDR 0x7186 + +/* + * ov8858 System control registers + */ + +#define OV8858_OTP_LOAD_CTRL 0x3D81 +#define OV8858_OTP_MODE_CTRL 0x3D84 +#define OV8858_OTP_START_ADDR_REG 0x3D88 +#define OV8858_OTP_END_ADDR_REG 0x3D8A +#define OV8858_OTP_ISP_CTRL2 0x5002 + +#define OV8858_OTP_MODE_MANUAL BIT(6) +#define OV8858_OTP_MODE_PROGRAM_DISABLE BIT(7) +#define OV8858_OTP_LOAD_ENABLE BIT(0) +#define OV8858_OTP_DPC_ENABLE BIT(3) + +#define OV8858_PLL1_PREDIV0 0x030A +#define OV8858_PLL1_PREDIV 0x0300 +#define OV8858_PLL1_MULTIPLIER 0x0301 +#define OV8858_PLL1_SYS_PRE_DIV 0x0305 +#define OV8858_PLL1_SYS_DIVIDER 0x0306 + +#define OV8858_PLL1_PREDIV0_MASK BIT(0) +#define OV8858_PLL1_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2)) +#define OV8858_PLL1_MULTIPLIER_MASK 0x01FF +#define OV8858_PLL1_SYS_PRE_DIV_MASK (BIT(0) | BIT(1)) +#define OV8858_PLL1_SYS_DIVIDER_MASK BIT(0) + +#define OV8858_PLL2_PREDIV0 0x0312 +#define OV8858_PLL2_PREDIV 0x030B +#define OV8858_PLL2_MULTIPLIER 0x030C +#define OV8858_PLL2_DAC_DIVIDER 0x0312 +#define OV8858_PLL2_SYS_PRE_DIV 0x030F +#define OV8858_PLL2_SYS_DIVIDER 0x030E + +#define OV8858_PLL2_PREDIV0_MASK BIT(4) +#define OV8858_PLL2_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2)) +#define OV8858_PLL2_MULTIPLIER_MASK 0x01FF +#define OV8858_PLL2_DAC_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define OV8858_PLL2_SYS_PRE_DIV_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define OV8858_PLL2_SYS_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2)) + +#define OV8858_PLL_SCLKSEL1 0x3032 +#define OV8858_PLL_SCLKSEL2 0x3033 +#define OV8858_SRB_HOST_INPUT_DIS 0x3106 + +#define OV8858_PLL_SCLKSEL1_MASK BIT(7) +#define OV8858_PLL_SCLKSEL2_MASK BIT(1) + +#define OV8858_SYS_PRE_DIV_OFFSET 2 +#define OV8858_SYS_PRE_DIV_MASK (BIT(2) | BIT(3)) +#define OV8858_SCLK_PDIV_OFFSET 4 +#define OV8858_SCLK_PDIV_MASK (BIT(4) | BIT(5) | BIT(6) | BIT(7)) + +#define OV8858_TIMING_HTS 0x380C +#define OV8858_TIMING_VTS 0x380E + +#define OV8858_HORIZONTAL_START_H 0x3800 +#define OV8858_VERTICAL_START_H 0x3802 +#define OV8858_HORIZONTAL_END_H 0x3804 +#define OV8858_VERTICAL_END_H 0x3806 +#define OV8858_HORIZONTAL_OUTPUT_SIZE_H 0x3808 +#define OV8858_VERTICAL_OUTPUT_SIZE_H 0x380A + +#define OV8858_GROUP_ACCESS 0x3208 +#define OV8858_GROUP_ZERO 0x00 +#define OV8858_GROUP_ACCESS_HOLD_START 0x00 +#define OV8858_GROUP_ACCESS_HOLD_END 0x10 +#define OV8858_GROUP_ACCESS_DELAY_LAUNCH 0xA0 +#define OV8858_GROUP_ACCESS_QUICK_LAUNCH 0xE0 + +#define OV_SUBDEV_PREFIX "ov" +#define OV_ID_DEFAULT 0x0000 +#define OV8858_NAME "ov8858" +#define OV8858_CHIP_ID 0x8858 + +#define OV8858_LONG_EXPO 0x3500 +#define OV8858_LONG_GAIN 0x3508 +#define OV8858_LONG_DIGI_GAIN 0x350A +#define OV8858_SHORT_GAIN 0x350C +#define OV8858_SHORT_DIGI_GAIN 0x350E + +#define OV8858_FORMAT1 0x3820 +#define OV8858_FORMAT2 0x3821 + +#define OV8858_FLIP_ENABLE 0x06 + +#define OV8858_MWB_RED_GAIN_H 0x5032 +#define OV8858_MWB_GREEN_GAIN_H 0x5034 +#define OV8858_MWB_BLUE_GAIN_H 0x5036 +#define OV8858_MWB_GAIN_MAX 0x0FFF + +#define OV8858_CHIP_ID_HIGH 0x300B +#define OV8858_CHIP_ID_LOW 0x300C +#define OV8858_STREAM_MODE 0x0100 + +#define OV8858_FOCAL_LENGTH_NUM 294 /* 2.94mm */ +#define OV8858_FOCAL_LENGTH_DEM 100 +#define OV8858_F_NUMBER_DEFAULT_NUM 24 /* 2.4 */ +#define OV8858_F_NUMBER_DEM 10 + +#define OV8858_H_INC_ODD 0x3814 +#define OV8858_H_INC_EVEN 0x3815 +#define OV8858_V_INC_ODD 0x382A +#define OV8858_V_INC_EVEN 0x382B + +#define OV8858_READ_MODE_BINNING_ON 0x0400 /* ToDo: Check this */ +#define OV8858_READ_MODE_BINNING_OFF 0x00 /* ToDo: Check this */ +#define OV8858_BIN_FACTOR_MAX 2 +#define OV8858_INTEGRATION_TIME_MARGIN 14 + +#define OV8858_MAX_VTS_VALUE 0xFFFF +#define OV8858_MAX_EXPOSURE_VALUE \ + (OV8858_MAX_VTS_VALUE - OV8858_INTEGRATION_TIME_MARGIN) +#define OV8858_MAX_GAIN_VALUE 0x07FF + +#define OV8858_MAX_FOCUS_POS 1023 + +#define OV8858_TEST_PATTERN_REG 0x5E00 + +struct ov8858_vcm { + int (*power_up)(struct v4l2_subdev *sd); + int (*power_down)(struct v4l2_subdev *sd); + int (*init)(struct v4l2_subdev *sd); + int (*t_focus_vcm)(struct v4l2_subdev *sd, u16 val); + int (*t_focus_abs)(struct v4l2_subdev *sd, s32 value); + int (*t_focus_rel)(struct v4l2_subdev *sd, s32 value); + int (*q_focus_status)(struct v4l2_subdev *sd, s32 *value); + int (*q_focus_abs)(struct v4l2_subdev *sd, s32 *value); + int (*t_vcm_slew)(struct v4l2_subdev *sd, s32 value); + int (*t_vcm_timing)(struct v4l2_subdev *sd, s32 value); +}; + +/* + * Defines for register writes and register array processing + * */ +#define OV8858_BYTE_MAX 32 +#define OV8858_SHORT_MAX 16 +#define OV8858_TOK_MASK 0xFFF0 + +#define MAX_FPS_OPTIONS_SUPPORTED 3 + +#define OV8858_DEPTH_COMP_CONST 2200 +#define OV8858_DEPTH_VTS_CONST 2573 + +enum ov8858_tok_type { + OV8858_8BIT = 0x0001, + OV8858_16BIT = 0x0002, + OV8858_TOK_TERM = 0xF000, /* terminating token for reg list */ + OV8858_TOK_DELAY = 0xFE00 /* delay token for reg list */ +}; + +/* + * If register address or register width is not 32 bit width, + * user needs to convert it manually + */ +struct s_register_setting { + u32 reg; + u32 val; +}; + +/** + * struct ov8858_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct ov8858_reg { + enum ov8858_tok_type type; + u16 sreg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +struct ov8858_fps_setting { + int fps; + unsigned short pixels_per_line; + unsigned short lines_per_frame; + const struct ov8858_reg *regs; /* regs that the fps setting needs */ +}; + +struct ov8858_resolution { + u8 *desc; + const struct ov8858_reg *regs; + int res; + int width; + int height; + bool used; + u8 bin_factor_x; + u8 bin_factor_y; + unsigned short skip_frames; + const struct ov8858_fps_setting fps_options[MAX_FPS_OPTIONS_SUPPORTED]; +}; + +/* + * ov8858 device structure + * */ +struct ov8858_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + + struct camera_sensor_platform_data *platform_data; + struct mutex input_lock; /* serialize sensor's ioctl */ + int fmt_idx; + int streaming; + int vt_pix_clk_freq_mhz; + int fps_index; + u16 sensor_id; /* Sensor id from registers */ + u16 i2c_id; /* Sensor id from i2c_device_id */ + int exposure; + int gain; + u16 digital_gain; + u16 pixels_per_line; + u16 lines_per_frame; + u8 fps; + u8 *otp_data; + /* Prevent the framerate from being lowered in low light scenes. */ + int limit_exposure_flag; + bool hflip; + bool vflip; + + const struct ov8858_reg *regs; + struct ov8858_vcm *vcm_driver; + const struct ov8858_resolution *curr_res_table; + int entries_curr_table; + + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *run_mode; +}; + +#define to_ov8858_sensor(x) container_of(x, struct ov8858_device, sd) + +#define OV8858_MAX_WRITE_BUF_SIZE 32 +struct ov8858_write_buffer { + u16 addr; + u8 data[OV8858_MAX_WRITE_BUF_SIZE]; +}; + +struct ov8858_write_ctrl { + int index; + struct ov8858_write_buffer buffer; +}; + +static const struct ov8858_reg ov8858_soft_standby[] = { + {OV8858_8BIT, 0x0100, 0x00}, + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_streaming[] = { + {OV8858_8BIT, 0x0100, 0x01}, + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_param_hold[] = { + {OV8858_8BIT, OV8858_GROUP_ACCESS, + OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_START}, + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_param_update[] = { + {OV8858_8BIT, OV8858_GROUP_ACCESS, + OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_END}, + {OV8858_8BIT, OV8858_GROUP_ACCESS, + OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_DELAY_LAUNCH}, + {OV8858_TOK_TERM, 0, 0} +}; + +extern int dw9718_vcm_power_up(struct v4l2_subdev *sd); +extern int dw9718_vcm_power_down(struct v4l2_subdev *sd); +extern int dw9718_vcm_init(struct v4l2_subdev *sd); +extern int dw9718_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int vcm_power_up(struct v4l2_subdev *sd); +extern int vcm_power_down(struct v4l2_subdev *sd); + +static struct ov8858_vcm ov8858_vcms[] = { + [OV8858_SUNNY] = { + .power_up = dw9718_vcm_power_up, + .power_down = dw9718_vcm_power_down, + .init = dw9718_vcm_init, + .t_focus_vcm = dw9718_t_focus_vcm, + .t_focus_abs = dw9718_t_focus_abs, + .t_focus_rel = dw9718_t_focus_rel, + .q_focus_status = dw9718_q_focus_status, + .q_focus_abs = dw9718_q_focus_abs, + .t_vcm_slew = dw9718_t_vcm_slew, + .t_vcm_timing = dw9718_t_vcm_timing, + }, + [OV8858_ID_DEFAULT] = { + .power_up = NULL, + .power_down = NULL, + }, +}; + + +#define OV8858_RES_WIDTH_MAX 3280 +#define OV8858_RES_HEIGHT_MAX 2464 + +static struct ov8858_reg ov8858_BasicSettings[] = { + {OV8858_8BIT, 0x0103, 0x01}, /* software_reset */ + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + /* PLL settings */ + {OV8858_8BIT, 0x0300, 0x05}, /* pll1_pre_div = /4 */ + {OV8858_8BIT, 0x0302, 0xAF}, /* pll1_multiplier = 175 */ + {OV8858_8BIT, 0x0303, 0x00}, /* pll1_divm = /(1 + 0) */ + {OV8858_8BIT, 0x0304, 0x03}, /* pll1_div_mipi = /8 */ + {OV8858_8BIT, 0x030B, 0x02}, /* pll2_pre_div = /2 */ + {OV8858_8BIT, 0x030D, 0x4E}, /* pll2_r_divp = 78 */ + {OV8858_8BIT, 0x030E, 0x00}, /* pll2_r_divs = /1 */ + {OV8858_8BIT, 0x030F, 0x04}, /* pll2_r_divsp = /(1 + 4) */ + /* pll2_pre_div0 = /1, pll2_r_divdac = /(1 + 1) */ + {OV8858_8BIT, 0x0312, 0x01}, + {OV8858_8BIT, 0x031E, 0x0C}, /* pll1_no_lat = 1, mipi_bitsel_man = 0 */ + + /* PAD OEN2, VSYNC out enable=0x80, disable=0x00 */ + {OV8858_8BIT, 0x3002, 0x80}, + /* PAD OUT2, VSYNC pulse direction low-to-high = 1 */ + {OV8858_8BIT, 0x3007, 0x01}, + /* PAD SEL2, VSYNC out value = 0 */ + {OV8858_8BIT, 0x300D, 0x00}, + /* PAD OUT2, VSYNC out select = 0 */ + {OV8858_8BIT, 0x3010, 0x00}, + + /* Npump clock div = /2, Ppump clock div = /4 */ + {OV8858_8BIT, 0x3015, 0x01}, + /* + * mipi_lane_mode = 1+3, mipi_lvds_sel = 1 = MIPI enable, + * r_phy_pd_mipi_man = 0, lane_dis_option = 0 + */ + {OV8858_8BIT, 0x3018, 0x72}, + /* Clock switch output = normal, pclk_div = /1 */ + {OV8858_8BIT, 0x3020, 0x93}, + /* + * lvds_mode_o = 0, clock lane disable when pd_mipi = 0, + * pd_mipi enable when rst_sync = 1 + */ + {OV8858_8BIT, 0x3022, 0x01}, + {OV8858_8BIT, 0x3031, 0x0A}, /* mipi_bit_sel = 10 */ + {OV8858_8BIT, 0x3034, 0x00}, /* Unknown */ + /* sclk_div = /1, sclk_pre_div = /1, chip debug = 1 */ + {OV8858_8BIT, 0x3106, 0x01}, + + {OV8858_8BIT, 0x3305, 0xF1}, /* Unknown */ + {OV8858_8BIT, 0x3307, 0x04}, /* Unknown */ + {OV8858_8BIT, 0x3308, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3309, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x330A, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330B, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x330C, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330D, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330E, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330F, 0x40}, /* Unknown */ + + {OV8858_8BIT, 0x3500, 0x00}, /* long exposure = 0x9A20 */ + {OV8858_8BIT, 0x3501, 0x9A}, /* long exposure = 0x9A20 */ + {OV8858_8BIT, 0x3502, 0x20}, /* long exposure = 0x9A20 */ + /* + * Digital fraction gain delay option = Delay 1 frame, + * Gain change delay option = Delay 1 frame, + * Gain delay option = Delay 1 frame, + * Gain manual as sensor gain = Input gain as real gain format, + * Exposure delay option (must be 0 = Delay 1 frame, + * Exposure change delay option (must be 0) = Delay 1 frame + */ + {OV8858_8BIT, 0x3503, 0x00}, + {OV8858_8BIT, 0x3505, 0x80}, /* gain conversation option */ + /* + * [10:7] are integer gain, [6:0] are fraction gain. For example: + * 0x80 is 1x gain, 0x100 is 2x gain, 0x1C0 is 3.5x gain + */ + {OV8858_8BIT, 0x3508, 0x02}, /* long gain = 0x0200 */ + {OV8858_8BIT, 0x3509, 0x00}, /* long gain = 0x0200 */ + {OV8858_8BIT, 0x350C, 0x00}, /* short gain = 0x0080 */ + {OV8858_8BIT, 0x350D, 0x80}, /* short gain = 0x0080 */ + {OV8858_8BIT, 0x3510, 0x00}, /* short exposure = 0x000200 */ + {OV8858_8BIT, 0x3511, 0x02}, /* short exposure = 0x000200 */ + {OV8858_8BIT, 0x3512, 0x00}, /* short exposure = 0x000200 */ + + {OV8858_8BIT, 0x3600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3601, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3602, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3603, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3604, 0x22}, /* Unknown */ + {OV8858_8BIT, 0x3605, 0x30}, /* Unknown */ + {OV8858_8BIT, 0x3606, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3607, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3608, 0x11}, /* Unknown */ + {OV8858_8BIT, 0x3609, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x360A, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x360B, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x360C, 0xDC}, /* Unknown */ + {OV8858_8BIT, 0x360D, 0x40}, /* Unknown */ + {OV8858_8BIT, 0x360E, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x360F, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3610, 0x07}, /* Unknown */ + {OV8858_8BIT, 0x3611, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3612, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x3613, 0x80}, /* Unknown */ + {OV8858_8BIT, 0x3614, 0x58}, /* Unknown */ + {OV8858_8BIT, 0x3615, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3616, 0x4A}, /* Unknown */ + {OV8858_8BIT, 0x3617, 0x90}, /* Unknown */ + {OV8858_8BIT, 0x3618, 0x56}, /* Unknown */ + {OV8858_8BIT, 0x3619, 0x70}, /* Unknown */ + {OV8858_8BIT, 0x361A, 0x99}, /* Unknown */ + {OV8858_8BIT, 0x361B, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x361C, 0x07}, /* Unknown */ + {OV8858_8BIT, 0x361D, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x361E, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x361F, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3633, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3634, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3635, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3636, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3638, 0xFF}, /* Unknown */ + {OV8858_8BIT, 0x3645, 0x13}, /* Unknown */ + {OV8858_8BIT, 0x3646, 0x83}, /* Unknown */ + {OV8858_8BIT, 0x364A, 0x07}, /* Unknown */ + + {OV8858_8BIT, 0x3700, 0x30}, /* Unknown */ + {OV8858_8BIT, 0x3701, 0x18}, /* Unknown */ + {OV8858_8BIT, 0x3702, 0x50}, /* Unknown */ + {OV8858_8BIT, 0x3703, 0x32}, /* Unknown */ + {OV8858_8BIT, 0x3704, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x3705, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3706, 0x6A}, /* Unknown */ + {OV8858_8BIT, 0x3707, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3708, 0x48}, /* Unknown */ + {OV8858_8BIT, 0x3709, 0x66}, /* Unknown */ + {OV8858_8BIT, 0x370A, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x370B, 0x6A}, /* Unknown */ + {OV8858_8BIT, 0x370C, 0x07}, /* Unknown */ + {OV8858_8BIT, 0x3712, 0x44}, /* Unknown */ + {OV8858_8BIT, 0x3714, 0x24}, /* Unknown */ + {OV8858_8BIT, 0x3718, 0x14}, /* Unknown */ + {OV8858_8BIT, 0x3719, 0x31}, /* Unknown */ + {OV8858_8BIT, 0x371E, 0x31}, /* Unknown */ + {OV8858_8BIT, 0x371F, 0x7F}, /* Unknown */ + {OV8858_8BIT, 0x3720, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x3721, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x3724, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3725, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3726, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3728, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x3729, 0x03}, /* Unknown */ + {OV8858_8BIT, 0x372A, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x372B, 0xA6}, /* Unknown */ + {OV8858_8BIT, 0x372C, 0xA6}, /* Unknown */ + {OV8858_8BIT, 0x372D, 0xA6}, /* Unknown */ + {OV8858_8BIT, 0x372E, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x372F, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3730, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3731, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3732, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x3733, 0x10}, /* Unknown */ + {OV8858_8BIT, 0x3734, 0x40}, /* Unknown */ + {OV8858_8BIT, 0x3736, 0x30}, /* Unknown */ + {OV8858_8BIT, 0x373A, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x373B, 0x0B}, /* Unknown */ + {OV8858_8BIT, 0x373C, 0x14}, /* Unknown */ + {OV8858_8BIT, 0x373E, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3755, 0x10}, /* Unknown */ + {OV8858_8BIT, 0x3758, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3759, 0x4C}, /* Unknown */ + {OV8858_8BIT, 0x375A, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x375B, 0x26}, /* Unknown */ + {OV8858_8BIT, 0x375C, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x375D, 0x04}, /* Unknown */ + {OV8858_8BIT, 0x375E, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x375F, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x3760, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3761, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3762, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3763, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3766, 0xFF}, /* Unknown */ + {OV8858_8BIT, 0x3768, 0x22}, /* Unknown */ + {OV8858_8BIT, 0x3769, 0x44}, /* Unknown */ + {OV8858_8BIT, 0x376A, 0x44}, /* Unknown */ + {OV8858_8BIT, 0x376B, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x376F, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3772, 0x46}, /* Unknown */ + {OV8858_8BIT, 0x3773, 0x04}, /* Unknown */ + {OV8858_8BIT, 0x3774, 0x2C}, /* Unknown */ + {OV8858_8BIT, 0x3775, 0x13}, /* Unknown */ + {OV8858_8BIT, 0x3776, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3777, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x37A0, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x37A1, 0x7A}, /* Unknown */ + {OV8858_8BIT, 0x37A2, 0x7A}, /* Unknown */ + {OV8858_8BIT, 0x37A3, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A4, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A5, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A6, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A7, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x37A8, 0x98}, /* Unknown */ + {OV8858_8BIT, 0x37A9, 0x98}, /* Unknown */ + {OV8858_8BIT, 0x37AA, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x37AB, 0x5C}, /* Unknown */ + {OV8858_8BIT, 0x37AC, 0x5C}, /* Unknown */ + {OV8858_8BIT, 0x37AD, 0x55}, /* Unknown */ + {OV8858_8BIT, 0x37AE, 0x19}, /* Unknown */ + {OV8858_8BIT, 0x37AF, 0x19}, /* Unknown */ + {OV8858_8BIT, 0x37B0, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B1, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B2, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B3, 0x84}, /* Unknown */ + {OV8858_8BIT, 0x37B4, 0x84}, /* Unknown */ + {OV8858_8BIT, 0x37B5, 0x66}, /* Unknown */ + {OV8858_8BIT, 0x37B6, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B7, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B8, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B9, 0xFF}, /* Unknown */ + + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high */ + {OV8858_8BIT, 0x3809, 0xC0}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x90}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3810, 0x00}, /* h_win offset high */ + {OV8858_8BIT, 0x3811, 0x04}, /* h_win offset low */ + {OV8858_8BIT, 0x3812, 0x00}, /* v_win offset high */ + {OV8858_8BIT, 0x3813, 0x02}, /* v_win offset low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3837, 0x18}, /* Unknown */ + {OV8858_8BIT, 0x3841, 0xFF}, /* AUTO_SIZE_CTRL */ + {OV8858_8BIT, 0x3846, 0x48}, /* Unknown */ + + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3D8C, 0x73}, /* OTP_SETTING_STT_ADDRESS */ + {OV8858_8BIT, 0x3D8D, 0xDE}, /* OTP_SETTING_STT_ADDRESS */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x3F0A, 0x80}, /* PSRAM control register */ + + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4300, 0xFF}, /* clip_max[11:4] = 0xFFF */ + {OV8858_8BIT, 0x4301, 0x00}, /* clip_min[11:4] = 0 */ + {OV8858_8BIT, 0x4302, 0x0F}, /* clip_min/max[3:0] */ + {OV8858_8BIT, 0x4307, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4316, 0x00}, /* CTRL16 = default */ + {OV8858_8BIT, 0x4503, 0x18}, /* Unknown */ + {OV8858_8BIT, 0x4500, 0x38}, /* Unknown */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + /* wkup_dly = Mark1 wakeup delay/2^10 = 0x25 */ + {OV8858_8BIT, 0x4808, 0x25}, + {OV8858_8BIT, 0x4816, 0x52}, /* Embedded data type*/ + {OV8858_8BIT, 0x481F, 0x32}, /* clk_prepare_min = 0x32 */ + {OV8858_8BIT, 0x4825, 0x3A}, /* lpx_p_min = 0x3A */ + {OV8858_8BIT, 0x4826, 0x40}, /* hs_prepare_min = 0x40 */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_8BIT, 0x4850, 0x10}, /* LANE SEL01 */ + {OV8858_8BIT, 0x4851, 0x32}, /* LANE SEL02 */ + + {OV8858_8BIT, 0x4B00, 0x2A}, /* Unknown */ + {OV8858_8BIT, 0x4B0D, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4D00, 0x04}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D01, 0x18}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D02, 0xC3}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D03, 0xFF}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D04, 0xFF}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D05, 0xFF}, /* TPM_CTRL_REG */ + + /* + * Lens correction (LENC) function enable = 0 + * Slave sensor AWB Gain function enable = 1 + * Slave sensor AWB Statistics function enable = 1 + * Master sensor AWB Gain function enable = 1 + * Master sensor AWB Statistics function enable = 1 + * Black DPC function enable = 1 + * White DPC function enable =1 + */ + {OV8858_8BIT, 0x5000, 0x7E}, + {OV8858_8BIT, 0x5001, 0x01}, /* BLC function enable = 1 */ + /* + * Horizontal scale function enable = 0 + * WBMATCH bypass mode = Select slave sensor's gain + * WBMATCH function enable = 0 + * Master MWB gain support RGBC = 0 + * OTP_DPC function enable = 1 + * Manual mode of VarioPixel function enable = 0 + * Manual enable of VarioPixel function enable = 0 + * Use VSYNC to latch ISP modules's function enable signals = 0 + */ + {OV8858_8BIT, 0x5002, 0x08}, + /* + * Bypass all ISP modules after BLC module = 0 + * DPC_DBC buffer control enable = 1 + * WBMATCH VSYNC selection = Select master sensor's VSYNC fall + * Select master AWB gain to embed line = AWB gain before manual mode + * Enable BLC's input flip_i signal = 0 + */ + {OV8858_8BIT, 0x5003, 0x20}, + {OV8858_8BIT, 0x5041, 0x1D}, /* ISP CTRL41 - embedded data=on */ + {OV8858_8BIT, 0x5046, 0x12}, /* ISP CTRL46 = default */ + /* + * Tail enable = 1 + * Saturate cross cluster enable = 1 + * Remove cross cluster enable = 1 + * Enable to remove connected defect pixels in same channel = 1 + * Enable to remove connected defect pixels in different channel = 1 + * Smooth enable, use average G for recovery = 1 + * Black/white sensor mode enable = 0 + * Manual mode enable = 0 + */ + {OV8858_8BIT, 0x5780, 0xFC}, + {OV8858_8BIT, 0x5784, 0x0C}, /* DPC CTRL04 */ + {OV8858_8BIT, 0x5787, 0x40}, /* DPC CTRL07 */ + {OV8858_8BIT, 0x5788, 0x08}, /* DPC CTRL08 */ + {OV8858_8BIT, 0x578A, 0x02}, /* DPC CTRL0A */ + {OV8858_8BIT, 0x578B, 0x01}, /* DPC CTRL0B */ + {OV8858_8BIT, 0x578C, 0x01}, /* DPC CTRL0C */ + {OV8858_8BIT, 0x578E, 0x02}, /* DPC CTRL0E */ + {OV8858_8BIT, 0x578F, 0x01}, /* DPC CTRL0F */ + {OV8858_8BIT, 0x5790, 0x01}, /* DPC CTRL10 */ + {OV8858_8BIT, 0x5901, 0x00}, /* VAP CTRL01 = default */ + /* WINC CTRL08 = embedded data in 1st line*/ + {OV8858_8BIT, 0x5A08, 0x00}, + {OV8858_8BIT, 0x5B00, 0x02}, /* OTP CTRL00 */ + {OV8858_8BIT, 0x5B01, 0x10}, /* OTP CTRL01 */ + {OV8858_8BIT, 0x5B02, 0x03}, /* OTP CTRL02 */ + {OV8858_8BIT, 0x5B03, 0xCF}, /* OTP CTRL03 */ + {OV8858_8BIT, 0x5B05, 0x6C}, /* OTP CTRL05 = default */ + {OV8858_8BIT, 0x5E00, 0x00}, /* PRE CTRL00 = default */ + {OV8858_8BIT, 0x5E01, 0x41}, /* PRE_CTRL01 = default */ + + {OV8858_TOK_TERM, 0, 0} +}; + +/*****************************STILL********************************/ + +static const struct ov8858_reg ov8858_8M[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low 3283 */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 2464 */ + {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0xa0}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_3276x1848[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x10}, /* h_crop_start low 0c->10*/ + {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x42}, /* v_crop_start low 3e->42*/ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3276 x 1848 */ + {OV8858_8BIT, 0x3809, 0xCC}, /* h_output_size low d0->cc*/ + {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x38}, /* v_output_size low 3c->38*/ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_6M[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x3E}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 1852 */ + {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x3C}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1080P_60[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/ + {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x04}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xEC}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x07}, /* Anchor left end = 0x072D */ + {OV8858_8BIT, 0x4023, 0x2D}, /* Anchor left end = 0x072D */ + {OV8858_8BIT, 0x4024, 0x07}, /* Anchor right start = 0x079E */ + {OV8858_8BIT, 0x4025, 0x9E}, /* Anchor right start = 0x079E */ + {OV8858_8BIT, 0x4026, 0x07}, /* Anchor right end = 0x079F */ + {OV8858_8BIT, 0x4027, 0x9F}, /* Anchor right end = 0x079F */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1080P_30[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/ + {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x07}, /* Anchor left end = 0x072D */ + {OV8858_8BIT, 0x4023, 0x2D}, /* Anchor left end = 0x072D */ + {OV8858_8BIT, 0x4024, 0x07}, /* Anchor right start = 0x079E */ + {OV8858_8BIT, 0x4025, 0x9E}, /* Anchor right start = 0x079E */ + {OV8858_8BIT, 0x4026, 0x07}, /* Anchor right end = 0x079F */ + {OV8858_8BIT, 0x4027, 0x9F}, /* Anchor right end = 0x079F */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1640x1232[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1232 */ + {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0xD0}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x10}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x04}, /* Anchor left end = 0x04B9 */ + {OV8858_8BIT, 0x4023, 0xB9}, /* Anchor left end = 0x04B9 */ + {OV8858_8BIT, 0x4024, 0x05}, /* Anchor right start = 0x052A */ + {OV8858_8BIT, 0x4025, 0x2A}, /* Anchor right start = 0x052A */ + {OV8858_8BIT, 0x4026, 0x05}, /* Anchor right end = 0x052B */ + {OV8858_8BIT, 0x4027, 0x2B}, /* Anchor right end = 0x052B */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x04}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x08}, /* Bottom black line start = 8 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1640x1096[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1096 */ + {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x10}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x04}, /* Anchor left end = 0x04B9 */ + {OV8858_8BIT, 0x4023, 0xB9}, /* Anchor left end = 0x04B9 */ + {OV8858_8BIT, 0x4024, 0x05}, /* Anchor right start = 0x052A */ + {OV8858_8BIT, 0x4025, 0x2A}, /* Anchor right start = 0x052A */ + {OV8858_8BIT, 0x4026, 0x05}, /* Anchor right end = 0x052B */ + {OV8858_8BIT, 0x4027, 0x2B}, /* Anchor right end = 0x052B */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x04}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x08}, /* Bottom black line start = 8 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + + +static const struct ov8858_reg ov8858_1640x926[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 926 */ + {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x03}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x9E}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x10}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x04}, /* Anchor left end = 0x04B9 */ + {OV8858_8BIT, 0x4023, 0xB9}, /* Anchor left end = 0x04B9 */ + {OV8858_8BIT, 0x4024, 0x05}, /* Anchor right start = 0x052A */ + {OV8858_8BIT, 0x4025, 0x2A}, /* Anchor right start = 0x052A */ + {OV8858_8BIT, 0x4026, 0x05}, /* Anchor right end = 0x052B */ + {OV8858_8BIT, 0x4027, 0x2B}, /* Anchor right end = 0x052B */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x04}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x08}, /* Bottom black line start = 8 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static struct ov8858_resolution ov8858_res_preview[] = { + { + .desc = "ov8858_1640x926_PREVIEW", + .width = 1640, + .height = 926, + .used = 0, + .regs = ov8858_1640x926, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x1232_PREVIEW", + .width = 1640, + .height = 1232, + .used = 0, + .regs = ov8858_1640x1232, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_3276x1848_PREVIEW", + .width = 3276, + .height = 1848, + .used = 0, + .regs = ov8858_3276x1848, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_8M_PREVIEW", + .width = 3280, + .height = 2464, + .used = 0, + .regs = ov8858_8M, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, +}; + +static struct ov8858_resolution ov8858_res_still[] = { + { + .desc = "ov8858_1640x1232_STILL", + .width = 1640, + .height = 1232, + .used = 0, + .regs = ov8858_1640x1232, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x926_STILL", + .width = 1640, + .height = 926, + .used = 0, + .regs = ov8858_1640x926, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_3276X1848_STILL", + .width = 3276, + .height = 1848, + .used = 0, + .regs = ov8858_3276x1848, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_8M_STILL", + .width = 3280, + .height = 2464, + .used = 0, + .regs = ov8858_8M, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + /* Pixel clock: 149.76MHZ */ + .fps = 10, + .pixels_per_line = 3880, + .lines_per_frame = 3859, + }, + { + } + }, + }, +}; + +static struct ov8858_resolution ov8858_res_video[] = { + { + .desc = "ov8858_1640x926_VIDEO", + .width = 1640, + .height = 926, + .used = 0, + .regs = ov8858_1640x926, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x1232_VIDEO", + .width = 1640, + .height = 1232, + .used = 0, + .regs = ov8858_1640x1232, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x1096_VIDEO", + .width = 1640, + .height = 1096, + .used = 0, + .regs = ov8858_1640x1096, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_6M_VIDEO", + .width = 3280, + .height = 1852, + .used = 0, + .regs = ov8858_6M, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_8M_VIDEO", + .width = 3280, + .height = 2464, + .used = 0, + .regs = ov8858_8M, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, +}; + +#endif /* __OV8858_H__ */ diff --git a/drivers/staging/media/atomisp/i2c/ov8858_btns.h b/drivers/staging/media/atomisp/i2c/ov8858_btns.h new file mode 100644 index 0000000..09e3cdc --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov8858_btns.h @@ -0,0 +1,1284 @@ +/* + * Support for the Omnivision OV8858 camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __OV8858_H__ +#define __OV8858_H__ +#include "../include/linux/atomisp_platform.h" +#include <media/v4l2-ctrls.h> + +#define I2C_MSG_LENGTH 0x2 + +/* + * This should be added into include/linux/videodev2.h + * NOTE: This is most likely not used anywhere. + */ +#define V4L2_IDENT_OV8858 V4L2_IDENT_UNKNOWN + +/* + * Indexes for VCM driver lists + */ +#define OV8858_ID_DEFAULT 0 +#define OV8858_SUNNY 1 + +#define OV8858_OTP_START_ADDR 0x7010 +#define OV8858_OTP_END_ADDR 0x7186 + +/* + * ov8858 System control registers + */ + +#define OV8858_OTP_LOAD_CTRL 0x3D81 +#define OV8858_OTP_MODE_CTRL 0x3D84 +#define OV8858_OTP_START_ADDR_REG 0x3D88 +#define OV8858_OTP_END_ADDR_REG 0x3D8A +#define OV8858_OTP_ISP_CTRL2 0x5002 + +#define OV8858_OTP_MODE_MANUAL BIT(6) +#define OV8858_OTP_MODE_PROGRAM_DISABLE BIT(7) +#define OV8858_OTP_LOAD_ENABLE BIT(0) +#define OV8858_OTP_DPC_ENABLE BIT(3) + +#define OV8858_PLL1_PREDIV0 0x030A +#define OV8858_PLL1_PREDIV 0x0300 +#define OV8858_PLL1_MULTIPLIER 0x0301 +#define OV8858_PLL1_SYS_PRE_DIV 0x0305 +#define OV8858_PLL1_SYS_DIVIDER 0x0306 + +#define OV8858_PLL1_PREDIV0_MASK BIT(0) +#define OV8858_PLL1_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2)) +#define OV8858_PLL1_MULTIPLIER_MASK 0x01FF +#define OV8858_PLL1_SYS_PRE_DIV_MASK (BIT(0) | BIT(1)) +#define OV8858_PLL1_SYS_DIVIDER_MASK BIT(0) + +#define OV8858_PLL2_PREDIV0 0x0312 +#define OV8858_PLL2_PREDIV 0x030B +#define OV8858_PLL2_MULTIPLIER 0x030C +#define OV8858_PLL2_DAC_DIVIDER 0x0312 +#define OV8858_PLL2_SYS_PRE_DIV 0x030F +#define OV8858_PLL2_SYS_DIVIDER 0x030E + +#define OV8858_PLL2_PREDIV0_MASK BIT(4) +#define OV8858_PLL2_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2)) +#define OV8858_PLL2_MULTIPLIER_MASK 0x01FF +#define OV8858_PLL2_DAC_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define OV8858_PLL2_SYS_PRE_DIV_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define OV8858_PLL2_SYS_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2)) + +#define OV8858_PLL_SCLKSEL1 0x3032 +#define OV8858_PLL_SCLKSEL2 0x3033 +#define OV8858_SRB_HOST_INPUT_DIS 0x3106 + +#define OV8858_PLL_SCLKSEL1_MASK BIT(7) +#define OV8858_PLL_SCLKSEL2_MASK BIT(1) + +#define OV8858_SYS_PRE_DIV_OFFSET 2 +#define OV8858_SYS_PRE_DIV_MASK (BIT(2) | BIT(3)) +#define OV8858_SCLK_PDIV_OFFSET 4 +#define OV8858_SCLK_PDIV_MASK (BIT(4) | BIT(5) | BIT(6) | BIT(7)) + +#define OV8858_TIMING_HTS 0x380C +#define OV8858_TIMING_VTS 0x380E + +#define OV8858_HORIZONTAL_START_H 0x3800 +#define OV8858_VERTICAL_START_H 0x3802 +#define OV8858_HORIZONTAL_END_H 0x3804 +#define OV8858_VERTICAL_END_H 0x3806 +#define OV8858_HORIZONTAL_OUTPUT_SIZE_H 0x3808 +#define OV8858_VERTICAL_OUTPUT_SIZE_H 0x380A + +#define OV8858_GROUP_ACCESS 0x3208 +#define OV8858_GROUP_ZERO 0x00 +#define OV8858_GROUP_ACCESS_HOLD_START 0x00 +#define OV8858_GROUP_ACCESS_HOLD_END 0x10 +#define OV8858_GROUP_ACCESS_DELAY_LAUNCH 0xA0 +#define OV8858_GROUP_ACCESS_QUICK_LAUNCH 0xE0 + +#define OV_SUBDEV_PREFIX "ov" +#define OV_ID_DEFAULT 0x0000 +#define OV8858_NAME "ov8858" +#define OV8858_CHIP_ID 0x8858 + +#define OV8858_LONG_EXPO 0x3500 +#define OV8858_LONG_GAIN 0x3508 +#define OV8858_LONG_DIGI_GAIN 0x350A +#define OV8858_SHORT_GAIN 0x350C +#define OV8858_SHORT_DIGI_GAIN 0x350E + +#define OV8858_FORMAT1 0x3820 +#define OV8858_FORMAT2 0x3821 + +#define OV8858_FLIP_ENABLE 0x06 + +#define OV8858_MWB_RED_GAIN_H 0x5032 +#define OV8858_MWB_GREEN_GAIN_H 0x5034 +#define OV8858_MWB_BLUE_GAIN_H 0x5036 +#define OV8858_MWB_GAIN_MAX 0x0FFF + +#define OV8858_CHIP_ID_HIGH 0x300B +#define OV8858_CHIP_ID_LOW 0x300C +#define OV8858_STREAM_MODE 0x0100 + +#define OV8858_FOCAL_LENGTH_NUM 294 /* 2.94mm */ +#define OV8858_FOCAL_LENGTH_DEM 100 +#define OV8858_F_NUMBER_DEFAULT_NUM 24 /* 2.4 */ +#define OV8858_F_NUMBER_DEM 10 + +#define OV8858_H_INC_ODD 0x3814 +#define OV8858_H_INC_EVEN 0x3815 +#define OV8858_V_INC_ODD 0x382A +#define OV8858_V_INC_EVEN 0x382B + +#define OV8858_READ_MODE_BINNING_ON 0x0400 /* ToDo: Check this */ +#define OV8858_READ_MODE_BINNING_OFF 0x00 /* ToDo: Check this */ +#define OV8858_BIN_FACTOR_MAX 2 +#define OV8858_INTEGRATION_TIME_MARGIN 14 + +#define OV8858_MAX_VTS_VALUE 0xFFFF +#define OV8858_MAX_EXPOSURE_VALUE \ + (OV8858_MAX_VTS_VALUE - OV8858_INTEGRATION_TIME_MARGIN) +#define OV8858_MAX_GAIN_VALUE 0x07FF + +#define OV8858_MAX_FOCUS_POS 1023 + +#define OV8858_TEST_PATTERN_REG 0x5E00 + +struct ov8858_vcm { + int (*power_up)(struct v4l2_subdev *sd); + int (*power_down)(struct v4l2_subdev *sd); + int (*init)(struct v4l2_subdev *sd); + int (*t_focus_vcm)(struct v4l2_subdev *sd, u16 val); + int (*t_focus_abs)(struct v4l2_subdev *sd, s32 value); + int (*t_focus_rel)(struct v4l2_subdev *sd, s32 value); + int (*q_focus_status)(struct v4l2_subdev *sd, s32 *value); + int (*q_focus_abs)(struct v4l2_subdev *sd, s32 *value); + int (*t_vcm_slew)(struct v4l2_subdev *sd, s32 value); + int (*t_vcm_timing)(struct v4l2_subdev *sd, s32 value); +}; + +/* + * Defines for register writes and register array processing + * */ +#define OV8858_BYTE_MAX 32 +#define OV8858_SHORT_MAX 16 +#define OV8858_TOK_MASK 0xFFF0 + +#define MAX_FPS_OPTIONS_SUPPORTED 3 + +#define OV8858_DEPTH_COMP_CONST 2200 +#define OV8858_DEPTH_VTS_CONST 2573 + +enum ov8858_tok_type { + OV8858_8BIT = 0x0001, + OV8858_16BIT = 0x0002, + OV8858_TOK_TERM = 0xF000, /* terminating token for reg list */ + OV8858_TOK_DELAY = 0xFE00 /* delay token for reg list */ +}; + +/* + * If register address or register width is not 32 bit width, + * user needs to convert it manually + */ +struct s_register_setting { + u32 reg; + u32 val; +}; + +/** + * struct ov8858_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct ov8858_reg { + enum ov8858_tok_type type; + u16 sreg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +struct ov8858_fps_setting { + int fps; + unsigned short pixels_per_line; + unsigned short lines_per_frame; + const struct ov8858_reg *regs; /* regs that the fps setting needs */ +}; + +struct ov8858_resolution { + u8 *desc; + const struct ov8858_reg *regs; + int res; + int width; + int height; + bool used; + u8 bin_factor_x; + u8 bin_factor_y; + unsigned short skip_frames; + const struct ov8858_fps_setting fps_options[MAX_FPS_OPTIONS_SUPPORTED]; +}; + +/* + * ov8858 device structure + * */ +struct ov8858_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + + struct camera_sensor_platform_data *platform_data; + struct mutex input_lock; /* serialize sensor's ioctl */ + int fmt_idx; + int streaming; + int vt_pix_clk_freq_mhz; + int fps_index; + u16 sensor_id; /* Sensor id from registers */ + u16 i2c_id; /* Sensor id from i2c_device_id */ + int exposure; + int gain; + u16 digital_gain; + u16 pixels_per_line; + u16 lines_per_frame; + u8 fps; + u8 *otp_data; + /* Prevent the framerate from being lowered in low light scenes. */ + int limit_exposure_flag; + bool hflip; + bool vflip; + + const struct ov8858_reg *regs; + struct ov8858_vcm *vcm_driver; + const struct ov8858_resolution *curr_res_table; + int entries_curr_table; + + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *run_mode; +}; + +#define to_ov8858_sensor(x) container_of(x, struct ov8858_device, sd) + +#define OV8858_MAX_WRITE_BUF_SIZE 32 +struct ov8858_write_buffer { + u16 addr; + u8 data[OV8858_MAX_WRITE_BUF_SIZE]; +}; + +struct ov8858_write_ctrl { + int index; + struct ov8858_write_buffer buffer; +}; + +static const struct ov8858_reg ov8858_soft_standby[] = { + {OV8858_8BIT, 0x0100, 0x00}, + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_streaming[] = { + {OV8858_8BIT, 0x0100, 0x01}, + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_param_hold[] = { + {OV8858_8BIT, OV8858_GROUP_ACCESS, + OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_START}, + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_param_update[] = { + {OV8858_8BIT, OV8858_GROUP_ACCESS, + OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_END}, + {OV8858_8BIT, OV8858_GROUP_ACCESS, + OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_DELAY_LAUNCH}, + {OV8858_TOK_TERM, 0, 0} +}; + +extern int dw9718_vcm_power_up(struct v4l2_subdev *sd); +extern int dw9718_vcm_power_down(struct v4l2_subdev *sd); +extern int dw9718_vcm_init(struct v4l2_subdev *sd); +extern int dw9718_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int vcm_power_up(struct v4l2_subdev *sd); +extern int vcm_power_down(struct v4l2_subdev *sd); + +static struct ov8858_vcm ov8858_vcms[] = { + [OV8858_SUNNY] = { + .power_up = dw9718_vcm_power_up, + .power_down = dw9718_vcm_power_down, + .init = dw9718_vcm_init, + .t_focus_vcm = dw9718_t_focus_vcm, + .t_focus_abs = dw9718_t_focus_abs, + .t_focus_rel = dw9718_t_focus_rel, + .q_focus_status = dw9718_q_focus_status, + .q_focus_abs = dw9718_q_focus_abs, + .t_vcm_slew = dw9718_t_vcm_slew, + .t_vcm_timing = dw9718_t_vcm_timing, + }, + [OV8858_ID_DEFAULT] = { + .power_up = NULL, + .power_down = NULL, + }, +}; + + +#define OV8858_RES_WIDTH_MAX 3280 +#define OV8858_RES_HEIGHT_MAX 2464 + +static struct ov8858_reg ov8858_BasicSettings[] = { + {OV8858_8BIT, 0x0103, 0x01}, /* software_reset */ + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + /* PLL settings */ + {OV8858_8BIT, 0x0300, 0x05}, /* pll1_pre_div = /4 */ + {OV8858_8BIT, 0x0302, 0xAF}, /* pll1_multiplier = 175 */ + {OV8858_8BIT, 0x0303, 0x00}, /* pll1_divm = /(1 + 0) */ + {OV8858_8BIT, 0x0304, 0x03}, /* pll1_div_mipi = /8 */ + {OV8858_8BIT, 0x030B, 0x02}, /* pll2_pre_div = /2 */ + {OV8858_8BIT, 0x030D, 0x4E}, /* pll2_r_divp = 78 */ + {OV8858_8BIT, 0x030E, 0x00}, /* pll2_r_divs = /1 */ + {OV8858_8BIT, 0x030F, 0x04}, /* pll2_r_divsp = /(1 + 4) */ + /* pll2_pre_div0 = /1, pll2_r_divdac = /(1 + 1) */ + {OV8858_8BIT, 0x0312, 0x01}, + {OV8858_8BIT, 0x031E, 0x0C}, /* pll1_no_lat = 1, mipi_bitsel_man = 0 */ + + /* PAD OEN2, VSYNC out enable=0x80, disable=0x00 */ + {OV8858_8BIT, 0x3002, 0x80}, + /* PAD OUT2, VSYNC pulse direction low-to-high = 1 */ + {OV8858_8BIT, 0x3007, 0x01}, + /* PAD SEL2, VSYNC out value = 0 */ + {OV8858_8BIT, 0x300D, 0x00}, + /* PAD OUT2, VSYNC out select = 0 */ + {OV8858_8BIT, 0x3010, 0x00}, + + /* Npump clock div = /2, Ppump clock div = /4 */ + {OV8858_8BIT, 0x3015, 0x01}, + /* + * mipi_lane_mode = 1+3, mipi_lvds_sel = 1 = MIPI enable, + * r_phy_pd_mipi_man = 0, lane_dis_option = 0 + */ + {OV8858_8BIT, 0x3018, 0x72}, + /* Clock switch output = normal, pclk_div = /1 */ + {OV8858_8BIT, 0x3020, 0x93}, + /* + * lvds_mode_o = 0, clock lane disable when pd_mipi = 0, + * pd_mipi enable when rst_sync = 1 + */ + {OV8858_8BIT, 0x3022, 0x01}, + {OV8858_8BIT, 0x3031, 0x0A}, /* mipi_bit_sel = 10 */ + {OV8858_8BIT, 0x3034, 0x00}, /* Unknown */ + /* sclk_div = /1, sclk_pre_div = /1, chip debug = 1 */ + {OV8858_8BIT, 0x3106, 0x01}, + + {OV8858_8BIT, 0x3305, 0xF1}, /* Unknown */ + {OV8858_8BIT, 0x3307, 0x04}, /* Unknown */ + {OV8858_8BIT, 0x3308, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3309, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x330A, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330B, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x330C, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330D, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330E, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330F, 0x40}, /* Unknown */ + + {OV8858_8BIT, 0x3500, 0x00}, /* long exposure = 0x9A20 */ + {OV8858_8BIT, 0x3501, 0x9A}, /* long exposure = 0x9A20 */ + {OV8858_8BIT, 0x3502, 0x20}, /* long exposure = 0x9A20 */ + /* + * Digital fraction gain delay option = Delay 1 frame, + * Gain change delay option = Delay 1 frame, + * Gain delay option = Delay 1 frame, + * Gain manual as sensor gain = Input gain as real gain format, + * Exposure delay option (must be 0 = Delay 1 frame, + * Exposure change delay option (must be 0) = Delay 1 frame + */ + {OV8858_8BIT, 0x3503, 0x00}, + {OV8858_8BIT, 0x3505, 0x80}, /* gain conversation option */ + /* + * [10:7] are integer gain, [6:0] are fraction gain. For example: + * 0x80 is 1x gain, 0x100 is 2x gain, 0x1C0 is 3.5x gain + */ + {OV8858_8BIT, 0x3508, 0x02}, /* long gain = 0x0200 */ + {OV8858_8BIT, 0x3509, 0x00}, /* long gain = 0x0200 */ + {OV8858_8BIT, 0x350C, 0x00}, /* short gain = 0x0080 */ + {OV8858_8BIT, 0x350D, 0x80}, /* short gain = 0x0080 */ + {OV8858_8BIT, 0x3510, 0x00}, /* short exposure = 0x000200 */ + {OV8858_8BIT, 0x3511, 0x02}, /* short exposure = 0x000200 */ + {OV8858_8BIT, 0x3512, 0x00}, /* short exposure = 0x000200 */ + + {OV8858_8BIT, 0x3600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3601, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3602, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3603, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3604, 0x22}, /* Unknown */ + {OV8858_8BIT, 0x3605, 0x30}, /* Unknown */ + {OV8858_8BIT, 0x3606, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3607, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3608, 0x11}, /* Unknown */ + {OV8858_8BIT, 0x3609, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x360A, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x360B, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x360C, 0xDC}, /* Unknown */ + {OV8858_8BIT, 0x360D, 0x40}, /* Unknown */ + {OV8858_8BIT, 0x360E, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x360F, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3610, 0x07}, /* Unknown */ + {OV8858_8BIT, 0x3611, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3612, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x3613, 0x80}, /* Unknown */ + {OV8858_8BIT, 0x3614, 0x58}, /* Unknown */ + {OV8858_8BIT, 0x3615, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3616, 0x4A}, /* Unknown */ + {OV8858_8BIT, 0x3617, 0x90}, /* Unknown */ + {OV8858_8BIT, 0x3618, 0x56}, /* Unknown */ + {OV8858_8BIT, 0x3619, 0x70}, /* Unknown */ + {OV8858_8BIT, 0x361A, 0x99}, /* Unknown */ + {OV8858_8BIT, 0x361B, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x361C, 0x07}, /* Unknown */ + {OV8858_8BIT, 0x361D, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x361E, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x361F, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3633, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3634, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3635, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3636, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3638, 0xFF}, /* Unknown */ + {OV8858_8BIT, 0x3645, 0x13}, /* Unknown */ + {OV8858_8BIT, 0x3646, 0x83}, /* Unknown */ + {OV8858_8BIT, 0x364A, 0x07}, /* Unknown */ + + {OV8858_8BIT, 0x3700, 0x30}, /* Unknown */ + {OV8858_8BIT, 0x3701, 0x18}, /* Unknown */ + {OV8858_8BIT, 0x3702, 0x50}, /* Unknown */ + {OV8858_8BIT, 0x3703, 0x32}, /* Unknown */ + {OV8858_8BIT, 0x3704, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x3705, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3706, 0x6A}, /* Unknown */ + {OV8858_8BIT, 0x3707, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3708, 0x48}, /* Unknown */ + {OV8858_8BIT, 0x3709, 0x66}, /* Unknown */ + {OV8858_8BIT, 0x370A, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x370B, 0x6A}, /* Unknown */ + {OV8858_8BIT, 0x370C, 0x07}, /* Unknown */ + {OV8858_8BIT, 0x3712, 0x44}, /* Unknown */ + {OV8858_8BIT, 0x3714, 0x24}, /* Unknown */ + {OV8858_8BIT, 0x3718, 0x14}, /* Unknown */ + {OV8858_8BIT, 0x3719, 0x31}, /* Unknown */ + {OV8858_8BIT, 0x371E, 0x31}, /* Unknown */ + {OV8858_8BIT, 0x371F, 0x7F}, /* Unknown */ + {OV8858_8BIT, 0x3720, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x3721, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x3724, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3725, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3726, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3728, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x3729, 0x03}, /* Unknown */ + {OV8858_8BIT, 0x372A, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x372B, 0xA6}, /* Unknown */ + {OV8858_8BIT, 0x372C, 0xA6}, /* Unknown */ + {OV8858_8BIT, 0x372D, 0xA6}, /* Unknown */ + {OV8858_8BIT, 0x372E, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x372F, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3730, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3731, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3732, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x3733, 0x10}, /* Unknown */ + {OV8858_8BIT, 0x3734, 0x40}, /* Unknown */ + {OV8858_8BIT, 0x3736, 0x30}, /* Unknown */ + {OV8858_8BIT, 0x373A, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x373B, 0x0B}, /* Unknown */ + {OV8858_8BIT, 0x373C, 0x14}, /* Unknown */ + {OV8858_8BIT, 0x373E, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3755, 0x10}, /* Unknown */ + {OV8858_8BIT, 0x3758, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3759, 0x4C}, /* Unknown */ + {OV8858_8BIT, 0x375A, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x375B, 0x26}, /* Unknown */ + {OV8858_8BIT, 0x375C, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x375D, 0x04}, /* Unknown */ + {OV8858_8BIT, 0x375E, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x375F, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x3760, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3761, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3762, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3763, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3766, 0xFF}, /* Unknown */ + {OV8858_8BIT, 0x3768, 0x22}, /* Unknown */ + {OV8858_8BIT, 0x3769, 0x44}, /* Unknown */ + {OV8858_8BIT, 0x376A, 0x44}, /* Unknown */ + {OV8858_8BIT, 0x376B, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x376F, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3772, 0x46}, /* Unknown */ + {OV8858_8BIT, 0x3773, 0x04}, /* Unknown */ + {OV8858_8BIT, 0x3774, 0x2C}, /* Unknown */ + {OV8858_8BIT, 0x3775, 0x13}, /* Unknown */ + {OV8858_8BIT, 0x3776, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3777, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x37A0, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x37A1, 0x7A}, /* Unknown */ + {OV8858_8BIT, 0x37A2, 0x7A}, /* Unknown */ + {OV8858_8BIT, 0x37A3, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A4, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A5, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A6, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A7, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x37A8, 0x98}, /* Unknown */ + {OV8858_8BIT, 0x37A9, 0x98}, /* Unknown */ + {OV8858_8BIT, 0x37AA, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x37AB, 0x5C}, /* Unknown */ + {OV8858_8BIT, 0x37AC, 0x5C}, /* Unknown */ + {OV8858_8BIT, 0x37AD, 0x55}, /* Unknown */ + {OV8858_8BIT, 0x37AE, 0x19}, /* Unknown */ + {OV8858_8BIT, 0x37AF, 0x19}, /* Unknown */ + {OV8858_8BIT, 0x37B0, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B1, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B2, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B3, 0x84}, /* Unknown */ + {OV8858_8BIT, 0x37B4, 0x84}, /* Unknown */ + {OV8858_8BIT, 0x37B5, 0x66}, /* Unknown */ + {OV8858_8BIT, 0x37B6, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B7, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B8, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B9, 0xFF}, /* Unknown */ + + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high */ + {OV8858_8BIT, 0x3809, 0xC0}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x90}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3810, 0x00}, /* h_win offset high */ + {OV8858_8BIT, 0x3811, 0x04}, /* h_win offset low */ + {OV8858_8BIT, 0x3812, 0x00}, /* v_win offset high */ + {OV8858_8BIT, 0x3813, 0x02}, /* v_win offset low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3837, 0x18}, /* Unknown */ + {OV8858_8BIT, 0x3841, 0xFF}, /* AUTO_SIZE_CTRL */ + {OV8858_8BIT, 0x3846, 0x48}, /* Unknown */ + + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3D8C, 0x73}, /* OTP_SETTING_STT_ADDRESS */ + {OV8858_8BIT, 0x3D8D, 0xDE}, /* OTP_SETTING_STT_ADDRESS */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x3F0A, 0x80}, /* PSRAM control register */ + + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x400A, 0x01}, + {OV8858_8BIT, 0x4011, 0x20}, /* BLC CTRL11 = 0x20 */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x0C}, /* Anchor left end = 0x0C60 */ + {OV8858_8BIT, 0x4023, 0x60}, /* Anchor left end = 0x0C60 */ + {OV8858_8BIT, 0x4024, 0x0F}, /* Anchor right start = 0x0F36 */ + {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0F36 */ + {OV8858_8BIT, 0x4026, 0x0F}, /* Anchor right end = 0x0F37 */ + {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0F37 */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x04}, /* Top zero line number = 4 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x00}, /* Bottom zero start line = 0 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x04}, /* Bottom black line start = 4 */ + {OV8858_8BIT, 0x402F, 0x08}, /* Bottom black line number = 8 */ + + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4300, 0xFF}, /* clip_max[11:4] = 0xFFF */ + {OV8858_8BIT, 0x4301, 0x00}, /* clip_min[11:4] = 0 */ + {OV8858_8BIT, 0x4302, 0x0F}, /* clip_min/max[3:0] */ + {OV8858_8BIT, 0x4307, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4316, 0x00}, /* CTRL16 = default */ + {OV8858_8BIT, 0x4503, 0x18}, /* Unknown */ + {OV8858_8BIT, 0x4500, 0x38}, /* Unknown */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + /* wkup_dly = Mark1 wakeup delay/2^10 = 0x25 */ + {OV8858_8BIT, 0x4808, 0x25}, + {OV8858_8BIT, 0x4816, 0x52}, /* Embedded data type*/ + {OV8858_8BIT, 0x481F, 0x32}, /* clk_prepare_min = 0x32 */ + {OV8858_8BIT, 0x4825, 0x3A}, /* lpx_p_min = 0x3A */ + {OV8858_8BIT, 0x4826, 0x40}, /* hs_prepare_min = 0x40 */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_8BIT, 0x4850, 0x10}, /* LANE SEL01 */ + {OV8858_8BIT, 0x4851, 0x32}, /* LANE SEL02 */ + + {OV8858_8BIT, 0x4B00, 0x2A}, /* Unknown */ + {OV8858_8BIT, 0x4B0D, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4D00, 0x04}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D01, 0x18}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D02, 0xC3}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D03, 0xFF}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D04, 0xFF}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D05, 0xFF}, /* TPM_CTRL_REG */ + + /* + * Lens correction (LENC) function enable = 0 + * Slave sensor AWB Gain function enable = 1 + * Slave sensor AWB Statistics function enable = 1 + * Master sensor AWB Gain function enable = 1 + * Master sensor AWB Statistics function enable = 1 + * Black DPC function enable = 1 + * White DPC function enable =1 + */ + {OV8858_8BIT, 0x5000, 0x7E}, + {OV8858_8BIT, 0x5001, 0x01}, /* BLC function enable = 1 */ + /* + * Horizontal scale function enable = 0 + * WBMATCH bypass mode = Select slave sensor's gain + * WBMATCH function enable = 0 + * Master MWB gain support RGBC = 0 + * OTP_DPC function enable = 1 + * Manual mode of VarioPixel function enable = 0 + * Manual enable of VarioPixel function enable = 0 + * Use VSYNC to latch ISP modules's function enable signals = 0 + */ + {OV8858_8BIT, 0x5002, 0x08}, + /* + * Bypass all ISP modules after BLC module = 0 + * DPC_DBC buffer control enable = 1 + * WBMATCH VSYNC selection = Select master sensor's VSYNC fall + * Select master AWB gain to embed line = AWB gain before manual mode + * Enable BLC's input flip_i signal = 0 + */ + {OV8858_8BIT, 0x5003, 0x20}, + {OV8858_8BIT, 0x5041, 0x1D}, /* ISP CTRL41 - embedded data=on */ + {OV8858_8BIT, 0x5046, 0x12}, /* ISP CTRL46 = default */ + /* + * Tail enable = 1 + * Saturate cross cluster enable = 1 + * Remove cross cluster enable = 1 + * Enable to remove connected defect pixels in same channel = 1 + * Enable to remove connected defect pixels in different channel = 1 + * Smooth enable, use average G for recovery = 1 + * Black/white sensor mode enable = 0 + * Manual mode enable = 0 + */ + {OV8858_8BIT, 0x5780, 0xFC}, + {OV8858_8BIT, 0x5784, 0x0C}, /* DPC CTRL04 */ + {OV8858_8BIT, 0x5787, 0x40}, /* DPC CTRL07 */ + {OV8858_8BIT, 0x5788, 0x08}, /* DPC CTRL08 */ + {OV8858_8BIT, 0x578A, 0x02}, /* DPC CTRL0A */ + {OV8858_8BIT, 0x578B, 0x01}, /* DPC CTRL0B */ + {OV8858_8BIT, 0x578C, 0x01}, /* DPC CTRL0C */ + {OV8858_8BIT, 0x578E, 0x02}, /* DPC CTRL0E */ + {OV8858_8BIT, 0x578F, 0x01}, /* DPC CTRL0F */ + {OV8858_8BIT, 0x5790, 0x01}, /* DPC CTRL10 */ + {OV8858_8BIT, 0x5901, 0x00}, /* VAP CTRL01 = default */ + /* WINC CTRL08 = embedded data in 1st line*/ + {OV8858_8BIT, 0x5A08, 0x00}, + {OV8858_8BIT, 0x5B00, 0x02}, /* OTP CTRL00 */ + {OV8858_8BIT, 0x5B01, 0x10}, /* OTP CTRL01 */ + {OV8858_8BIT, 0x5B02, 0x03}, /* OTP CTRL02 */ + {OV8858_8BIT, 0x5B03, 0xCF}, /* OTP CTRL03 */ + {OV8858_8BIT, 0x5B05, 0x6C}, /* OTP CTRL05 = default */ + {OV8858_8BIT, 0x5E00, 0x00}, /* PRE CTRL00 = default */ + {OV8858_8BIT, 0x5E01, 0x41}, /* PRE_CTRL01 = default */ + + {OV8858_TOK_TERM, 0, 0} +}; + +/*****************************STILL********************************/ + +static const struct ov8858_reg ov8858_8M[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low 3283 */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 2464 */ + {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0xa0}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_3276x1848[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x10}, /* h_crop_start low 0c->10*/ + {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x42}, /* v_crop_start low 3e->42*/ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3276 x 1848 */ + {OV8858_8BIT, 0x3809, 0xCC}, /* h_output_size low d0->cc*/ + {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x38}, /* v_output_size low 3c->38*/ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_6M[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x3E}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 1852 */ + {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x3C}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1080P_60[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/ + {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x04}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xEC}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1080P_30[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/ + {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1640x1232[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1232 */ + {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0xD0}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1640x1096[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1096 */ + {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + + +static const struct ov8858_reg ov8858_1640x926[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 926 */ + {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x03}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x9E}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static struct ov8858_resolution ov8858_res_preview[] = { + { + .desc = "ov8858_1640x926_PREVIEW", + .width = 1640, + .height = 926, + .used = 0, + .regs = ov8858_1640x926, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x1232_PREVIEW", + .width = 1640, + .height = 1232, + .used = 0, + .regs = ov8858_1640x1232, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1936x1096_PREVIEW", + .width = 1936, + .height = 1096, + .used = 0, + .regs = ov8858_1080P_30, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_3276x1848_PREVIEW", + .width = 3276, + .height = 1848, + .used = 0, + .regs = ov8858_3276x1848, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_8M_PREVIEW", + .width = 3280, + .height = 2464, + .used = 0, + .regs = ov8858_8M, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, +}; + +static struct ov8858_resolution ov8858_res_still[] = { + { + .desc = "ov8858_1640x1232_STILL", + .width = 1640, + .height = 1232, + .used = 0, + .regs = ov8858_1640x1232, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x926_STILL", + .width = 1640, + .height = 926, + .used = 0, + .regs = ov8858_1640x926, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_3276X1848_STILL", + .width = 3276, + .height = 1848, + .used = 0, + .regs = ov8858_3276x1848, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_8M_STILL", + .width = 3280, + .height = 2464, + .used = 0, + .regs = ov8858_8M, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + /* Pixel clock: 149.76MHZ */ + .fps = 10, + .pixels_per_line = 3880, + .lines_per_frame = 3859, + }, + { + } + }, + }, +}; + +static struct ov8858_resolution ov8858_res_video[] = { + { + .desc = "ov8858_1640x926_VIDEO", + .width = 1640, + .height = 926, + .used = 0, + .regs = ov8858_1640x926, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x1232_VIDEO", + .width = 1640, + .height = 1232, + .used = 0, + .regs = ov8858_1640x1232, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x1096_VIDEO", + .width = 1640, + .height = 1096, + .used = 0, + .regs = ov8858_1640x1096, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1080P_30_VIDEO", + .width = 1936, + .height = 1096, + .used = 0, + .regs = ov8858_1080P_30, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, +}; + +#endif /* __OV8858_H__ */ |
