diff options
Diffstat (limited to 'drivers/staging/media/atomisp/i2c/imx')
27 files changed, 15067 insertions, 0 deletions
diff --git a/drivers/staging/media/atomisp/i2c/imx/Kconfig b/drivers/staging/media/atomisp/i2c/imx/Kconfig new file mode 100644 index 0000000..a39eeb3 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/Kconfig @@ -0,0 +1,9 @@ +config VIDEO_IMX + tristate "sony imx sensor support" + depends on I2C && VIDEO_V4L2 && VIDEO_MSRLIST_HELPER && m + ---help--- + This is a Video4Linux2 sensor-level driver for the Sony + IMX RAW sensor. + + It currently depends on internal V4L2 extensions defined in + atomisp driver. diff --git a/drivers/staging/media/atomisp/i2c/imx/Makefile b/drivers/staging/media/atomisp/i2c/imx/Makefile new file mode 100644 index 0000000..1d7f7ab --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/Makefile @@ -0,0 +1,8 @@ +obj-$(CONFIG_VIDEO_IMX) += imx1x5.o + +imx1x5-objs := imx.o drv201.o ad5816g.o dw9714.o dw9719.o dw9718.o vcm.o otp.o otp_imx.o otp_brcc064_e2prom.o otp_e2prom.o + +ov8858_driver-objs := ../ov8858.o dw9718.o vcm.o +obj-$(CONFIG_VIDEO_OV8858) += ov8858_driver.o + +ccflags-y += -Werror diff --git a/drivers/staging/media/atomisp/i2c/imx/ad5816g.c b/drivers/staging/media/atomisp/i2c/imx/ad5816g.c new file mode 100644 index 0000000..d68ebb4 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/ad5816g.c @@ -0,0 +1,225 @@ +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/kmod.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/types.h> +#include <media/v4l2-device.h> + +#include "ad5816g.h" + +struct ad5816g_device ad5816g_dev; + +static int ad5816g_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2]; + buf[0] = reg; + buf[1] = 0; + + msg[0].addr = AD5816G_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &buf[0]; + + msg[1].addr = AD5816G_VCM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf[1]; + *val = 0; + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + return 0; +} + +static int ad5816g_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2]; + buf[0] = reg; + buf[1] = val; + msg.addr = AD5816G_VCM_ADDR; + msg.flags = 0; + msg.len = 2; + msg.buf = &buf[0]; + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +static int ad5816g_i2c_wr16(struct i2c_client *client, u8 reg, u16 val) +{ + struct i2c_msg msg; + u8 buf[3]; + buf[0] = reg; + buf[1] = (u8)(val >> 8); + buf[2] = (u8)(val & 0xff); + msg.addr = AD5816G_VCM_ADDR; + msg.flags = 0; + msg.len = 3; + msg.buf = &buf[0]; + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +static int ad5816g_set_arc_mode(struct i2c_client *client) +{ + int ret; + + ret = ad5816g_i2c_wr8(client, AD5816G_CONTROL, AD5816G_ARC_EN); + if (ret) + return ret; + + ret = ad5816g_i2c_wr8(client, AD5816G_MODE, + AD5816G_MODE_2_5M_SWITCH_CLOCK); + if (ret) + return ret; + + ret = ad5816g_i2c_wr8(client, AD5816G_VCM_FREQ, AD5816G_DEF_FREQ); + return ret; +} + +int ad5816g_vcm_power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 ad5816g_id; + + /* Enable power */ + ret = ad5816g_dev.platform_data->power_ctrl(sd, 1); + if (ret) + return ret; + /* waiting time AD5816G(vcm) - t1 + t2 + * t1(1ms) -Time from VDD high to first i2c cmd + * t2(100us) - exit power-down mode time + */ + usleep_range(1100, 2200); + /* Detect device */ + ret = ad5816g_i2c_rd8(client, AD5816G_IC_INFO, &ad5816g_id); + if (ret < 0) + goto fail_powerdown; + if (ad5816g_id != AD5816G_ID) { + ret = -ENXIO; + goto fail_powerdown; + } + ret = ad5816g_set_arc_mode(client); + if (ret) + return ret; + + /* set the VCM_THRESHOLD */ + ret = ad5816g_i2c_wr8(client, AD5816G_VCM_THRESHOLD, + AD5816G_DEF_THRESHOLD); + + return ret; + +fail_powerdown: + ad5816g_dev.platform_data->power_ctrl(sd, 0); + return ret; +} + +int ad5816g_vcm_power_down(struct v4l2_subdev *sd) +{ + return ad5816g_dev.platform_data->power_ctrl(sd, 0); +} + + +int ad5816g_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 data = val & VCM_CODE_MASK; + + return ad5816g_i2c_wr16(client, AD5816G_VCM_CODE_MSB, data); +} + +int ad5816g_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + int ret; + + value = clamp(value, 0, AD5816G_MAX_FOCUS_POS); + ret = ad5816g_t_focus_vcm(sd, value); + if (ret == 0) { + ad5816g_dev.number_of_steps = value - ad5816g_dev.focus; + ad5816g_dev.focus = value; + getnstimeofday(&(ad5816g_dev.timestamp_t_focus_abs)); + } + + return ret; +} + +int ad5816g_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + + return ad5816g_t_focus_abs(sd, ad5816g_dev.focus + value); +} + +int ad5816g_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + u32 status = 0; + struct timespec temptime; + const struct timespec timedelay = { + 0, + min_t(u32, abs(ad5816g_dev.number_of_steps) * DELAY_PER_STEP_NS, + DELAY_MAX_PER_STEP_NS), + }; + + ktime_get_ts(&temptime); + + temptime = timespec_sub(temptime, (ad5816g_dev.timestamp_t_focus_abs)); + + if (timespec_compare(&temptime, &timedelay) <= 0) { + status |= ATOMISP_FOCUS_STATUS_MOVING; + status |= ATOMISP_FOCUS_HP_IN_PROGRESS; + } else { + status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + status |= ATOMISP_FOCUS_HP_COMPLETE; + } + *value = status; + + return 0; +} + +int ad5816g_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + s32 val; + + ad5816g_q_focus_status(sd, &val); + + if (val & ATOMISP_FOCUS_STATUS_MOVING) + *value = ad5816g_dev.focus - ad5816g_dev.number_of_steps; + else + *value = ad5816g_dev.focus; + + return 0; +} + +int ad5816g_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int ad5816g_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int ad5816g_vcm_init(struct v4l2_subdev *sd) +{ + ad5816g_dev.platform_data = camera_get_af_platform_data(); + return (NULL == ad5816g_dev.platform_data) ? -ENODEV : 0; + +} + + diff --git a/drivers/staging/media/atomisp/i2c/imx/ad5816g.h b/drivers/staging/media/atomisp/i2c/imx/ad5816g.h new file mode 100644 index 0000000..f995c2e --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/ad5816g.h @@ -0,0 +1,49 @@ +#ifndef __AD5816G_H__ +#define __AD5816G_H__ + +#include "../../include/linux/atomisp_platform.h" +#include <linux/types.h> +#include <linux/time.h> + +#define AD5816G_VCM_ADDR 0x0e + +/* ad5816g device structure */ +struct ad5816g_device { + const struct camera_af_platform_data *platform_data; + struct timespec timestamp_t_focus_abs; + struct timespec focus_time; /* Time when focus was last time set */ + s32 focus; /* Current focus value */ + s16 number_of_steps; +}; + +#define AD5816G_INVALID_CONFIG 0xffffffff +#define AD5816G_MAX_FOCUS_POS 1023 +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) + +/* Register Definitions */ +#define AD5816G_IC_INFO 0x00 +#define AD5816G_IC_VERSION 0x01 +#define AD5816G_CONTROL 0x02 +#define AD5816G_VCM_CODE_MSB 0x03 +#define AD5816G_VCM_CODE_LSB 0x04 +#define AD5816G_STATUS 0x05 +#define AD5816G_MODE 0x06 +#define AD5816G_VCM_FREQ 0x07 +#define AD5816G_VCM_THRESHOLD 0x08 + +/* ARC MODE ENABLE */ +#define AD5816G_ARC_EN 0x02 +/* ARC RES2 MODE */ +#define AD5816G_ARC_RES2 0x01 +/* ARC VCM FREQ - 78.1Hz */ +#define AD5816G_DEF_FREQ 0x7a +/* ARC VCM THRESHOLD - 0x08 << 1 */ +#define AD5816G_DEF_THRESHOLD 0x64 +#define AD5816G_ID 0x24 +#define VCM_CODE_MASK 0x03ff + +#define AD5816G_MODE_2_5M_SWITCH_CLOCK 0x14 + +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/common.h b/drivers/staging/media/atomisp/i2c/imx/common.h new file mode 100644 index 0000000..7e525ce --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/common.h @@ -0,0 +1,65 @@ +#ifndef __COMMON_H__ +#define __COMMON_H__ + +#define MAX_FPS_OPTIONS_SUPPORTED 3 +#define I2C_MSG_LENGTH 0x2 +#define E2PROM_2ADDR 0x80000000 +#define E2PROM_ADDR_MASK 0x7fffffff + +/* Defines for register writes and register array processing */ +#define IMX_BYTE_MAX 32 +#define IMX_SHORT_MAX 16 +#define I2C_RETRY_COUNT 5 +#define IMX_TOK_MASK 0xfff0 + +enum imx_tok_type { + IMX_8BIT = 0x0001, + IMX_16BIT = 0x0002, + IMX_TOK_TERM = 0xf000, /* terminating token for reg list */ + IMX_TOK_DELAY = 0xfe00 /* delay token for reg list */ +}; + +/** + * struct imx_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct imx_reg { + enum imx_tok_type type; + u16 sreg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +struct imx_fps_setting { + int fps; + unsigned short pixels_per_line; + unsigned short lines_per_frame; + int mipi_freq; /* MIPI lane frequency in kHz */ + const struct imx_reg *regs; /* regs that the fps setting needs */ +}; + +struct imx_resolution { + const struct imx_fps_setting fps_options[MAX_FPS_OPTIONS_SUPPORTED]; + u8 *desc; + const struct imx_reg *regs; + int res; + int width; + int height; + int fps; + unsigned short pixels_per_line; + unsigned short lines_per_frame; + int mipi_freq; /* MIPI lane frequency in kHz */ + unsigned short skip_frames; + u8 bin_factor_x; + u8 bin_factor_y; + bool used; +}; + +#define GROUPED_PARAMETER_HOLD_ENABLE {IMX_8BIT, 0x0104, 0x1} +#define GROUPED_PARAMETER_HOLD_DISABLE {IMX_8BIT, 0x0104, 0x0} + +int imx_write_reg(struct i2c_client *client, u16 data_length, u16 reg, u16 val); +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/drv201.c b/drivers/staging/media/atomisp/i2c/imx/drv201.c new file mode 100644 index 0000000..915e401 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/drv201.c @@ -0,0 +1,218 @@ +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/kmod.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/types.h> +#include <media/v4l2-device.h> +#include <asm/intel-mid.h> + +#include "drv201.h" + +static struct drv201_device drv201_dev; + +static int drv201_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2]; + buf[0] = reg; + buf[1] = 0; + + msg[0].addr = DRV201_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &buf[0]; + + msg[1].addr = DRV201_VCM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf[1]; + *val = 0; + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + return 0; +} + +static int drv201_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2]; + buf[0] = reg; + buf[1] = val; + msg.addr = DRV201_VCM_ADDR; + msg.flags = 0; + msg.len = 2; + msg.buf = &buf[0]; + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +static int drv201_i2c_wr16(struct i2c_client *client, u8 reg, u16 val) +{ + struct i2c_msg msg; + u8 buf[3]; + buf[0] = reg; + buf[1] = (u8)(val >> 8); + buf[2] = (u8)(val & 0xff); + msg.addr = DRV201_VCM_ADDR; + msg.flags = 0; + msg.len = 3; + msg.buf = &buf[0]; + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +int drv201_vcm_power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 value; + + /* Enable power */ + ret = drv201_dev.platform_data->power_ctrl(sd, 1); + if (ret) + return ret; + /* Wait for VBAT to stabilize */ + udelay(1); + /* + * Jiggle SCL pin to wake up device. + * Drv201 expect SCL from low to high to wake device up. + * So the 1st access to i2c would fail. + * Using following function to wake device up. + */ + drv201_i2c_wr8(client, DRV201_CONTROL, DRV201_RESET); + + /* Need 100us to transit from SHUTDOWN to STANDBY*/ + usleep_range(WAKEUP_DELAY_US, WAKEUP_DELAY_US * 10); + + /* Reset device */ + ret = drv201_i2c_wr8(client, DRV201_CONTROL, DRV201_RESET); + if (ret < 0) + goto fail_powerdown; + + /* Detect device */ + ret = drv201_i2c_rd8(client, DRV201_CONTROL, &value); + if (ret < 0) + goto fail_powerdown; + if (value != DEFAULT_CONTROL_VAL) { + ret = -ENXIO; + goto fail_powerdown; + } + + drv201_dev.focus = DRV201_MAX_FOCUS_POS; + drv201_dev.initialized = true; + + return 0; +fail_powerdown: + drv201_dev.platform_data->power_ctrl(sd, 0); + return ret; +} + +int drv201_vcm_power_down(struct v4l2_subdev *sd) +{ + return drv201_dev.platform_data->power_ctrl(sd, 0); +} + + +int drv201_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 data = val & VCM_CODE_MASK; + + if (!drv201_dev.initialized) + return -ENODEV; + return drv201_i2c_wr16(client, DRV201_VCM_CURRENT, data); +} + +int drv201_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + int ret; + + value = clamp(value, 0, DRV201_MAX_FOCUS_POS); + ret = drv201_t_focus_vcm(sd, value); + if (ret == 0) { + drv201_dev.number_of_steps = value - drv201_dev.focus; + drv201_dev.focus = value; + getnstimeofday(&(drv201_dev.timestamp_t_focus_abs)); + } + + return ret; +} + +int drv201_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + return drv201_t_focus_abs(sd, drv201_dev.focus + value); +} + +int drv201_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + u32 status = 0; + struct timespec temptime; + const struct timespec timedelay = { + 0, + min_t(u32, abs(drv201_dev.number_of_steps)*DELAY_PER_STEP_NS, + DELAY_MAX_PER_STEP_NS), + }; + + ktime_get_ts(&temptime); + + temptime = timespec_sub(temptime, (drv201_dev.timestamp_t_focus_abs)); + + if (timespec_compare(&temptime, &timedelay) <= 0) { + status |= ATOMISP_FOCUS_STATUS_MOVING; + status |= ATOMISP_FOCUS_HP_IN_PROGRESS; + } else { + status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + status |= ATOMISP_FOCUS_HP_COMPLETE; + } + *value = status; + + return 0; +} + +int drv201_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + s32 val; + + drv201_q_focus_status(sd, &val); + + if (val & ATOMISP_FOCUS_STATUS_MOVING) + *value = drv201_dev.focus - drv201_dev.number_of_steps; + else + *value = drv201_dev.focus; + + return 0; +} + +int drv201_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int drv201_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int drv201_vcm_init(struct v4l2_subdev *sd) +{ + drv201_dev.platform_data = camera_get_af_platform_data(); + return (NULL == drv201_dev.platform_data) ? -ENODEV : 0; +} + + + diff --git a/drivers/staging/media/atomisp/i2c/imx/drv201.h b/drivers/staging/media/atomisp/i2c/imx/drv201.h new file mode 100644 index 0000000..8fc0ad1 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/drv201.h @@ -0,0 +1,38 @@ +#ifndef __DRV201_H__ +#define __DRV201_H__ + +#include "../../include/linux/atomisp_platform.h" +#include <linux/types.h> +#include <linux/time.h> + +#define DRV201_VCM_ADDR 0x0e + +/* drv201 device structure */ +struct drv201_device { + const struct camera_af_platform_data *platform_data; + struct timespec timestamp_t_focus_abs; + struct timespec focus_time; /* Time when focus was last time set */ + s32 focus; /* Current focus value */ + s16 number_of_steps; + bool initialized; /* true if drv201 is detected */ +}; + +#define DRV201_INVALID_CONFIG 0xffffffff +#define DRV201_MAX_FOCUS_POS 1023 +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) + +#define DRV201_CONTROL 2 +#define DRV201_VCM_CURRENT 3 +#define DRV201_STATUS 5 +#define DRV201_MODE 6 +#define DRV201_VCM_FREQ 7 + +#define DEFAULT_CONTROL_VAL 2 +#define DRV201_RESET 1 +#define WAKEUP_DELAY_US 100 +#define VCM_CODE_MASK 0x03ff + +#endif + + diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9714.c b/drivers/staging/media/atomisp/i2c/imx/dw9714.c new file mode 100644 index 0000000..b7dee1b --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9714.c @@ -0,0 +1,235 @@ +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/kmod.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/types.h> +#include <media/v4l2-device.h> +#include <asm/intel-mid.h> + +#include "dw9714.h" + +static struct dw9714_device dw9714_dev; +static int dw9714_i2c_write(struct i2c_client *client, u16 data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + u16 val; + + val = cpu_to_be16(data); + msg.addr = DW9714_VCM_ADDR; + msg.flags = 0; + msg.len = DW9714_16BIT; + msg.buf = (u8 *)&val; + + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +int dw9714_vcm_power_up(struct v4l2_subdev *sd) +{ + int ret; + + /* Enable power */ + ret = dw9714_dev.platform_data->power_ctrl(sd, 1); + /* waiting time requested by DW9714A(vcm) */ + usleep_range(12000, 12500); + return ret; +} + +int dw9714_vcm_power_down(struct v4l2_subdev *sd) +{ + return dw9714_dev.platform_data->power_ctrl(sd, 0); +} + + +int dw9714_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = -EINVAL; + u8 mclk = vcm_step_mclk(dw9714_dev.vcm_settings.step_setting); + u8 s = vcm_step_s(dw9714_dev.vcm_settings.step_setting); + + /* + * For different mode, VCM_PROTECTION_OFF/ON required by the + * control procedure. For DW9714_DIRECT/DLC mode, slew value is + * VCM_DEFAULT_S(0). + */ + switch (dw9714_dev.vcm_mode) { + case DW9714_DIRECT: + if (dw9714_dev.vcm_settings.update) { + ret = dw9714_i2c_write(client, VCM_PROTECTION_OFF); + if (ret) + return ret; + ret = dw9714_i2c_write(client, DIRECT_VCM); + if (ret) + return ret; + ret = dw9714_i2c_write(client, VCM_PROTECTION_ON); + if (ret) + return ret; + dw9714_dev.vcm_settings.update = false; + } + ret = dw9714_i2c_write(client, + vcm_val(val, VCM_DEFAULT_S)); + break; + case DW9714_LSC: + if (dw9714_dev.vcm_settings.update) { + ret = dw9714_i2c_write(client, VCM_PROTECTION_OFF); + if (ret) + return ret; + ret = dw9714_i2c_write(client, + vcm_dlc_mclk(DLC_DISABLE, mclk)); + if (ret) + return ret; + ret = dw9714_i2c_write(client, + vcm_tsrc(dw9714_dev.vcm_settings.t_src)); + if (ret) + return ret; + ret = dw9714_i2c_write(client, VCM_PROTECTION_ON); + if (ret) + return ret; + dw9714_dev.vcm_settings.update = false; + } + ret = dw9714_i2c_write(client, vcm_val(val, s)); + break; + case DW9714_DLC: + if (dw9714_dev.vcm_settings.update) { + ret = dw9714_i2c_write(client, VCM_PROTECTION_OFF); + if (ret) + return ret; + ret = dw9714_i2c_write(client, + vcm_dlc_mclk(DLC_ENABLE, mclk)); + if (ret) + return ret; + ret = dw9714_i2c_write(client, + vcm_tsrc(dw9714_dev.vcm_settings.t_src)); + if (ret) + return ret; + ret = dw9714_i2c_write(client, VCM_PROTECTION_ON); + if (ret) + return ret; + dw9714_dev.vcm_settings.update = false; + } + ret = dw9714_i2c_write(client, + vcm_val(val, VCM_DEFAULT_S)); + break; + } + return ret; +} + +int dw9714_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + int ret; + + value = clamp(value, 0, DW9714_MAX_FOCUS_POS); + ret = dw9714_t_focus_vcm(sd, value); + if (ret == 0) { + dw9714_dev.number_of_steps = value - dw9714_dev.focus; + dw9714_dev.focus = value; + getnstimeofday(&(dw9714_dev.timestamp_t_focus_abs)); + } + + return ret; +} + +int dw9714_t_focus_abs_init(struct v4l2_subdev *sd) +{ + int ret; + + ret = dw9714_t_focus_vcm(sd, DW9714_DEFAULT_FOCUS_POS); + if (ret == 0) { + dw9714_dev.number_of_steps = + DW9714_DEFAULT_FOCUS_POS - dw9714_dev.focus; + dw9714_dev.focus = DW9714_DEFAULT_FOCUS_POS; + getnstimeofday(&(dw9714_dev.timestamp_t_focus_abs)); + } + + return ret; +} + +int dw9714_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + + return dw9714_t_focus_abs(sd, dw9714_dev.focus + value); +} + +int dw9714_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + u32 status = 0; + struct timespec temptime; + const struct timespec timedelay = { + 0, + min_t(u32, abs(dw9714_dev.number_of_steps)*DELAY_PER_STEP_NS, + DELAY_MAX_PER_STEP_NS), + }; + + ktime_get_ts(&temptime); + + temptime = timespec_sub(temptime, (dw9714_dev.timestamp_t_focus_abs)); + + if (timespec_compare(&temptime, &timedelay) <= 0) { + status |= ATOMISP_FOCUS_STATUS_MOVING; + status |= ATOMISP_FOCUS_HP_IN_PROGRESS; + } else { + status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + status |= ATOMISP_FOCUS_HP_COMPLETE; + } + *value = status; + + return 0; +} + +int dw9714_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + s32 val; + + dw9714_q_focus_status(sd, &val); + + if (val & ATOMISP_FOCUS_STATUS_MOVING) + *value = dw9714_dev.focus - dw9714_dev.number_of_steps; + else + *value = dw9714_dev.focus; + + return 0; +} + +int dw9714_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + dw9714_dev.vcm_settings.step_setting = value; + dw9714_dev.vcm_settings.update = true; + + return 0; +} + +int dw9714_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + dw9714_dev.vcm_settings.t_src = value; + dw9714_dev.vcm_settings.update = true; + + return 0; +} + +int dw9714_vcm_init(struct v4l2_subdev *sd) +{ + + /* set VCM to home position and vcm mode to direct*/ + dw9714_dev.vcm_mode = DW9714_DIRECT; + dw9714_dev.vcm_settings.update = false; + dw9714_dev.platform_data = camera_get_af_platform_data(); + return (NULL == dw9714_dev.platform_data) ? -ENODEV : 0; + +} + diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9714.h b/drivers/staging/media/atomisp/i2c/imx/dw9714.h new file mode 100644 index 0000000..5a98a9c --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9714.h @@ -0,0 +1,63 @@ +#ifndef __DW9714_H__ +#define __DW9714_H__ + +#include "../../include/linux/atomisp_platform.h" +#include <linux/types.h> + + +#define DW9714_VCM_ADDR 0x0c + +enum dw9714_tok_type { + DW9714_8BIT = 0x0001, + DW9714_16BIT = 0x0002, +}; + +struct dw9714_vcm_settings { + u16 code; /* bit[9:0]: Data[9:0] */ + u8 t_src; /* bit[4:0]: T_SRC[4:0] */ + u8 step_setting; /* bit[3:0]: S[3:0]/bit[5:4]: MCLK[1:0] */ + bool update; +}; + +enum dw9714_vcm_mode { + DW9714_DIRECT = 0x1, /* direct control */ + DW9714_LSC = 0x2, /* linear slope control */ + DW9714_DLC = 0x3, /* dual level control */ +}; + +/* dw9714 device structure */ +struct dw9714_device { + struct dw9714_vcm_settings vcm_settings; + struct timespec timestamp_t_focus_abs; + enum dw9714_vcm_mode vcm_mode; + s16 number_of_steps; + bool initialized; /* true if dw9714 is detected */ + s32 focus; /* Current focus value */ + struct timespec focus_time; /* Time when focus was last time set */ + __u8 buffer[4]; /* Used for i2c transactions */ + const struct camera_af_platform_data *platform_data; +}; + +#define DW9714_INVALID_CONFIG 0xffffffff +#define DW9714_MAX_FOCUS_POS 1023 +#define DW9714_DEFAULT_FOCUS_POS 290 + + +/* MCLK[1:0] = 01 T_SRC[4:0] = 00001 S[3:0] = 0111 */ +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) + +#define DLC_ENABLE 1 +#define DLC_DISABLE 0 +#define VCM_PROTECTION_OFF 0xeca3 +#define VCM_PROTECTION_ON 0xdc51 +#define VCM_DEFAULT_S 0x0 + +#define vcm_step_s(a) (u8)(a & 0xf) +#define vcm_step_mclk(a) (u8)((a >> 4) & 0x3) +#define vcm_dlc_mclk(dlc, mclk) (u16)((dlc << 3) | mclk | 0xa104) +#define vcm_tsrc(tsrc) (u16)(tsrc << 3 | 0xf200) +#define vcm_val(data, s) (u16)(data << 4 | s) +#define DIRECT_VCM vcm_dlc_mclk(0, 0) + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9718.c b/drivers/staging/media/atomisp/i2c/imx/dw9718.c new file mode 100644 index 0000000..65a1fcf --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9718.c @@ -0,0 +1,238 @@ +/* + * Support for dw9718 vcm driver. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include <linux/delay.h> +#include "dw9718.h" + +static struct dw9718_device dw9718_dev; + +static int dw9718_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2] = { reg }; + + msg[0].addr = DW9718_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = buf; + + msg[1].addr = DW9718_VCM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf[1]; + *val = 0; + + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + + return 0; +} + +static int dw9718_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2] = { reg, val}; + + msg.addr = DW9718_VCM_ADDR; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + + return 0; +} + +static int dw9718_i2c_wr16(struct i2c_client *client, u8 reg, u16 val) +{ + struct i2c_msg msg; + u8 buf[3] = { reg, (u8)(val >> 8), (u8)(val & 0xff)}; + + msg.addr = DW9718_VCM_ADDR; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + + return 0; +} + +int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + value = clamp(value, 0, DW9718_MAX_FOCUS_POS); + ret = dw9718_i2c_wr16(client, DW9718_DATA_M, value); + /*pr_info("%s: value = %d\n", __func__, value);*/ + if (ret < 0) + return ret; + + getnstimeofday(&dw9718_dev.focus_time); + dw9718_dev.focus = value; + + return 0; +} + +int dw9718_vcm_power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 value; + + if (dw9718_dev.power_on) + return 0; + + /* Enable power */ + ret = dw9718_dev.platform_data->power_ctrl(sd, 1); + if (ret) { + dev_err(&client->dev, "DW9718_PD power_ctrl failed %d\n", ret); + return ret; + } + /* Wait for VBAT to stabilize */ + udelay(100); + + /* Detect device */ + ret = dw9718_i2c_rd8(client, DW9718_SACT, &value); + if (ret < 0) { + dev_err(&client->dev, "read DW9718_SACT failed %d\n", ret); + goto fail_powerdown; + } + /* + * WORKAROUND: for module P8V12F-203 which are used on + * Cherrytrail Refresh Davis Reef AoB, register SACT is not + * returning default value as spec. But VCM works as expected and + * root cause is still under discussion with vendor. + * workaround here to avoid aborting the power up sequence and just + * give a warning about this error. + */ + if (value != DW9718_SACT_DEFAULT_VAL) + dev_warn(&client->dev, "%s error, incorrect ID\n", __func__); + + /* Initialize according to recommended settings */ + ret = dw9718_i2c_wr8(client, DW9718_CONTROL, + DW9718_CONTROL_SW_LINEAR | + DW9718_CONTROL_S_SAC4 | + DW9718_CONTROL_OCP_DISABLE | + DW9718_CONTROL_UVLO_DISABLE); + if (ret < 0) { + dev_err(&client->dev, "write DW9718_CONTROL failed %d\n", ret); + goto fail_powerdown; + } + ret = dw9718_i2c_wr8(client, DW9718_SACT, + DW9718_SACT_MULT_TWO | + DW9718_SACT_PERIOD_8_8MS); + if (ret < 0) { + dev_err(&client->dev, "write DW9718_SACT failed %d\n", ret); + goto fail_powerdown; + } + + ret = dw9718_t_focus_abs(sd, dw9718_dev.focus); + if (ret) + return ret; + dw9718_dev.initialized = true; + dw9718_dev.power_on = 1; + + return 0; + +fail_powerdown: + dev_err(&client->dev, "%s error, powerup failed\n", __func__); + dw9718_dev.platform_data->power_ctrl(sd, 0); + return ret; +} + +int dw9718_vcm_power_down(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!dw9718_dev.power_on) + return 0; + + ret = dw9718_dev.platform_data->power_ctrl(sd, 0); + if (ret) { + dev_err(&client->dev, "%s power_ctrl failed\n", + __func__); + return ret; + } + dw9718_dev.power_on = 0; + + return 0; +} + +int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + static const struct timespec move_time = { + .tv_sec = 0, + .tv_nsec = 60000000 + }; + struct timespec current_time, finish_time, delta_time; + + getnstimeofday(¤t_time); + finish_time = timespec_add(dw9718_dev.focus_time, move_time); + delta_time = timespec_sub(current_time, finish_time); + if (delta_time.tv_sec >= 0 && delta_time.tv_nsec >= 0) { + *value = ATOMISP_FOCUS_HP_COMPLETE | + ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + } else { + *value = ATOMISP_FOCUS_STATUS_MOVING | + ATOMISP_FOCUS_HP_IN_PROGRESS; + } + + return 0; +} + +int dw9718_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + return -EINVAL; +} + +int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + return dw9718_t_focus_abs(sd, dw9718_dev.focus + value); +} + +int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + *value = dw9718_dev.focus; + return 0; +} +int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int dw9718_vcm_init(struct v4l2_subdev *sd) +{ + dw9718_dev.platform_data = camera_get_af_platform_data(); + dw9718_dev.focus = DW9718_DEFAULT_FOCUS_POSITION; + dw9718_dev.power_on = 0; + return (NULL == dw9718_dev.platform_data) ? -ENODEV : 0; +} diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9718.h b/drivers/staging/media/atomisp/i2c/imx/dw9718.h new file mode 100644 index 0000000..4a1040c --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9718.h @@ -0,0 +1,64 @@ +/* + * Support for dw9719 vcm driver. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __DW9718_H__ +#define __DW9718_H__ + +#include "../../include/linux/atomisp_platform.h" +#include <linux/types.h> + +#define DW9718_VCM_ADDR (0x18 >> 1) + +/* dw9718 device structure */ +struct dw9718_device { + struct timespec timestamp_t_focus_abs; + s16 number_of_steps; + bool initialized; /* true if dw9718 is detected */ + s32 focus; /* Current focus value */ + struct timespec focus_time; /* Time when focus was last time set */ + __u8 buffer[4]; /* Used for i2c transactions */ + const struct camera_af_platform_data *platform_data; + __u8 power_on; +}; + +#define DW9718_MAX_FOCUS_POS 1023 + +/* Register addresses */ +#define DW9718_PD 0x00 +#define DW9718_CONTROL 0x01 +#define DW9718_DATA_M 0x02 +#define DW9718_DATA_L 0x03 +#define DW9718_SW 0x04 +#define DW9718_SACT 0x05 +#define DW9718_FLAG 0x10 + +#define DW9718_CONTROL_SW_LINEAR BIT(0) +#define DW9718_CONTROL_S_SAC4 (BIT(1) | BIT(3)) +#define DW9718_CONTROL_OCP_DISABLE BIT(4) +#define DW9718_CONTROL_UVLO_DISABLE BIT(5) + +#define DW9718_SACT_MULT_TWO 0x00 +#define DW9718_SACT_PERIOD_8_8MS 0x19 +#define DW9718_SACT_DEFAULT_VAL 0x60 + +#define DW9718_DEFAULT_FOCUS_POSITION 300 + +#endif /* __DW9718_H__ */ diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9719.c b/drivers/staging/media/atomisp/i2c/imx/dw9719.c new file mode 100644 index 0000000..eca2d76 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9719.c @@ -0,0 +1,209 @@ +/* + * Support for dw9719 vcm driver. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include <linux/delay.h> +#include "dw9719.h" + +static struct dw9719_device dw9719_dev; + +static int dw9719_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2] = { reg }; + + msg[0].addr = DW9719_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = buf; + + msg[1].addr = DW9719_VCM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf[1]; + *val = 0; + + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + + return 0; +} + +static int dw9719_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2] = { reg, val }; + + msg.addr = DW9719_VCM_ADDR; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + + return 0; +} + +static int dw9719_i2c_wr16(struct i2c_client *client, u8 reg, u16 val) +{ + struct i2c_msg msg; + u8 buf[3] = { reg, (u8)(val >> 8), (u8)(val & 0xff)}; + + msg.addr = DW9719_VCM_ADDR; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + + return 0; +} + +int dw9719_vcm_power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 value; + + /* Enable power */ + ret = dw9719_dev.platform_data->power_ctrl(sd, 1); + /* waiting time requested by DW9714A(vcm) */ + if (ret) + return ret; + /* Wait for VBAT to stabilize */ + udelay(1); + + /* + * Jiggle SCL pin to wake up device. + */ + ret = dw9719_i2c_wr8(client, DW9719_CONTROL, 1); + /* Need 100us to transit from SHUTDOWN to STANDBY*/ + usleep_range(100, 1000); + + /* Enable the ringing compensation */ + ret = dw9719_i2c_wr8(client, DW9719_CONTROL, DW9719_ENABLE_RINGING); + if (ret < 0) + goto fail_powerdown; + + /* Use SAC3 mode */ + ret = dw9719_i2c_wr8(client, DW9719_MODE, DW9719_MODE_SAC3); + if (ret < 0) + goto fail_powerdown; + + /* Set the resonance frequency */ + ret = dw9719_i2c_wr8(client, DW9719_VCM_FREQ, DW9719_DEFAULT_VCM_FREQ); + if (ret < 0) + goto fail_powerdown; + + /* Detect device */ + ret = dw9719_i2c_rd8(client, DW9719_INFO, &value); + if (ret < 0) + goto fail_powerdown; + if (value != DW9719_ID) { + ret = -ENXIO; + goto fail_powerdown; + } + dw9719_dev.focus = 0; + dw9719_dev.initialized = true; + + return 0; + +fail_powerdown: + dw9719_dev.platform_data->power_ctrl(sd, 0); + return ret; +} + +int dw9719_vcm_power_down(struct v4l2_subdev *sd) +{ + return dw9719_dev.platform_data->power_ctrl(sd, 0); +} + +int dw9719_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + static const struct timespec move_time = { + + .tv_sec = 0, + .tv_nsec = 60000000 + }; + struct timespec current_time, finish_time, delta_time; + + getnstimeofday(¤t_time); + finish_time = timespec_add(dw9719_dev.focus_time, move_time); + delta_time = timespec_sub(current_time, finish_time); + if (delta_time.tv_sec >= 0 && delta_time.tv_nsec >= 0) { + *value = ATOMISP_FOCUS_HP_COMPLETE | + ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + } else { + *value = ATOMISP_FOCUS_STATUS_MOVING | + ATOMISP_FOCUS_HP_IN_PROGRESS; + } + + return 0; +} + +int dw9719_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + return -EINVAL; +} + +int dw9719_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + value = clamp(value, 0, DW9719_MAX_FOCUS_POS); + ret = dw9719_i2c_wr16(client, DW9719_VCM_CURRENT, value); + if (ret < 0) + return ret; + + getnstimeofday(&dw9719_dev.focus_time); + dw9719_dev.focus = value; + + return 0; +} + +int dw9719_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + return dw9719_t_focus_abs(sd, dw9719_dev.focus + value); +} + +int dw9719_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + *value = dw9719_dev.focus; + return 0; +} +int dw9719_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int dw9719_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int dw9719_vcm_init(struct v4l2_subdev *sd) +{ + dw9719_dev.platform_data = camera_get_af_platform_data(); + return (NULL == dw9719_dev.platform_data) ? -ENODEV : 0; +} diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9719.h b/drivers/staging/media/atomisp/i2c/imx/dw9719.h new file mode 100644 index 0000000..711f412 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9719.h @@ -0,0 +1,58 @@ +/* + * Support for dw9719 vcm driver. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __DW9719_H__ +#define __DW9719_H__ + +#include "../../include/linux/atomisp_platform.h" +#include <linux/types.h> + +#define DW9719_VCM_ADDR (0x18 >> 1) + +/* dw9719 device structure */ +struct dw9719_device { + struct timespec timestamp_t_focus_abs; + s16 number_of_steps; + bool initialized; /* true if dw9719 is detected */ + s32 focus; /* Current focus value */ + struct timespec focus_time; /* Time when focus was last time set */ + __u8 buffer[4]; /* Used for i2c transactions */ + const struct camera_af_platform_data *platform_data; +}; + +#define DW9719_INVALID_CONFIG 0xffffffff +#define DW9719_MAX_FOCUS_POS 1023 +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) + +#define DW9719_INFO 0 +#define DW9719_ID 0xF1 +#define DW9719_CONTROL 2 +#define DW9719_VCM_CURRENT 3 + +#define DW9719_MODE 6 +#define DW9719_VCM_FREQ 7 + +#define DW9719_MODE_SAC3 0x40 +#define DW9719_DEFAULT_VCM_FREQ 0x04 +#define DW9719_ENABLE_RINGING 0x02 + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/imx.c b/drivers/staging/media/atomisp/i2c/imx/imx.c new file mode 100644 index 0000000..408a7b9 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx.c @@ -0,0 +1,2512 @@ +/* + * Support for Sony imx 8MP camera sensor. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <asm/intel-mid.h> +#include "../../include/linux/atomisp_platform.h" +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include "../../include/linux/libmsrlisthelper.h" +#include <linux/mm.h> +#include <linux/kmod.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/types.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include "imx.h" + +/* + * The imx135 embedded data info: + * embedded data line num: 2 + * line 0 effective data size(byte): 76 + * line 1 effective data size(byte): 113 + */ +static const uint32_t + imx135_embedded_effective_size[IMX135_EMBEDDED_DATA_LINE_NUM] + = {76, 113}; + +static enum atomisp_bayer_order imx_bayer_order_mapping[] = { + atomisp_bayer_order_rggb, + atomisp_bayer_order_grbg, + atomisp_bayer_order_gbrg, + atomisp_bayer_order_bggr +}; + +static const unsigned int +IMX227_BRACKETING_LUT_FRAME_ENTRY[IMX_MAX_AE_LUT_LENGTH] = { + 0x0E10, 0x0E1E, 0x0E2C, 0x0E3A, 0x0E48}; + +static int +imx_read_reg(struct i2c_client *client, u16 len, u16 reg, u16 *val) +{ + struct i2c_msg msg[2]; + u16 data[IMX_SHORT_MAX]; + int ret, i; + int retry = 0; + + if (len > IMX_BYTE_MAX) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + do { + memset(msg, 0 , sizeof(msg)); + memset(data, 0 , sizeof(data)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = (u8 *)data; + /* high byte goes first */ + data[0] = cpu_to_be16(reg); + + msg[1].addr = client->addr; + msg[1].len = len; + msg[1].flags = I2C_M_RD; + msg[1].buf = (u8 *)data; + + ret = i2c_transfer(client->adapter, msg, 2); + if (ret != 2) { + dev_err(&client->dev, + "retrying i2c read from offset 0x%x error %d... %d\n", + reg, ret, retry); + msleep(20); + } + } while (ret != 2 && retry++ < I2C_RETRY_COUNT); + + if (ret != 2) + return -EIO; + + /* high byte comes first */ + if (len == IMX_8BIT) { + *val = (u8)data[0]; + } else { + /* 16-bit access is default when len > 1 */ + for (i = 0; i < (len >> 1); i++) + val[i] = be16_to_cpu(data[i]); + } + + return 0; +} + +static int imx_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + int ret; + int retry = 0; + + do { + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret != 1) { + dev_err(&client->dev, + "retrying i2c write transfer... %d\n", retry); + msleep(20); + } + } while (ret != 1 && retry++ < I2C_RETRY_COUNT); + + return ret == 1 ? 0 : -EIO; +} + +int +imx_write_reg(struct i2c_client *client, u16 data_length, u16 reg, u16 val) +{ + int ret; + unsigned char data[4] = {0}; + u16 *wreg = (u16 *)data; + const u16 len = data_length + sizeof(u16); /* 16-bit address + data */ + + if (data_length != IMX_8BIT && data_length != IMX_16BIT) { + v4l2_err(client, "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = cpu_to_be16(reg); + + if (data_length == IMX_8BIT) + data[2] = (u8)(val); + else { + /* IMX_16BIT */ + u16 *wdata = (u16 *)&data[2]; + *wdata = cpu_to_be16(val); + } + + ret = imx_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * imx_write_reg_array - Initializes a list of imx registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __imx_flush_reg_array, __imx_buf_reg_array() and + * __imx_write_reg_is_consecutive() are internal functions to + * imx_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __imx_flush_reg_array(struct i2c_client *client, + struct imx_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u16) + ctrl->index; /* 16-bit address + data */ + ctrl->buffer.addr = cpu_to_be16(ctrl->buffer.addr); + ctrl->index = 0; + + return imx_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __imx_buf_reg_array(struct i2c_client *client, + struct imx_write_ctrl *ctrl, + const struct imx_reg *next) +{ + int size; + u16 *data16; + + switch (next->type) { + case IMX_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case IMX_16BIT: + size = 2; + data16 = (u16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->sreg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u16) >= IMX_MAX_WRITE_BUF_SIZE) + return __imx_flush_reg_array(client, ctrl); + + return 0; +} + +static int +__imx_write_reg_is_consecutive(struct i2c_client *client, + struct imx_write_ctrl *ctrl, + const struct imx_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->sreg; +} + +static int imx_write_reg_array(struct i2c_client *client, + const struct imx_reg *reglist) +{ + const struct imx_reg *next = reglist; + struct imx_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != IMX_TOK_TERM; next++) { + switch (next->type & IMX_TOK_MASK) { + case IMX_TOK_DELAY: + err = __imx_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__imx_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __imx_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __imx_buf_reg_array(client, &ctrl, next); + if (err) { + v4l2_err(client, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __imx_flush_reg_array(client, &ctrl); +} + +static int __imx_min_fps_diff(int fps, const struct imx_fps_setting *fps_list) +{ + int diff = INT_MAX; + int i; + + if (fps == 0) + return 0; + + for (i = 0; i < MAX_FPS_OPTIONS_SUPPORTED; i++) { + if (!fps_list[i].fps) + break; + if (abs(fps_list[i].fps - fps) < diff) + diff = abs(fps_list[i].fps - fps); + } + + return diff; +} + +static int __imx_nearest_fps_index(int fps, + const struct imx_fps_setting *fps_list) +{ + int fps_index = 0; + int i; + + for (i = 0; i < MAX_FPS_OPTIONS_SUPPORTED; i++) { + if (!fps_list[i].fps) + break; + if (abs(fps_list[i].fps - fps) + < abs(fps_list[fps_index].fps - fps)) + fps_index = i; + } + return fps_index; +} + +/* + * This is to choose the nearest fps setting above the requested fps + * fps_list should be in ascendant order. + */ +static int __imx_above_nearest_fps_index(int fps, + const struct imx_fps_setting *fps_list) +{ + int fps_index = 0; + int i; + + for (i = 0; i < MAX_FPS_OPTIONS_SUPPORTED; i++) { + if (!fps_list[i].fps) + break; + if (fps <= fps_list[i].fps) { + fps_index = i; + break; + } + } + + return fps_index; +} + +static int imx_get_lanes(struct v4l2_subdev *sd) +{ + struct camera_mipi_info *imx_info = v4l2_get_subdev_hostdata(sd); + + if (!imx_info) + return -ENOSYS; + if (imx_info->num_lanes < 1 || imx_info->num_lanes > 4 || + imx_info->num_lanes == 3) + return -EINVAL; + + return imx_info->num_lanes; +} + +static int __imx_update_exposure_timing(struct i2c_client *client, u16 exposure, + u16 llp, u16 fll) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx_device *dev = to_imx_sensor(sd); + int ret = 0; + + if (dev->sensor_id != IMX227_ID) { + /* Increase the VTS to match exposure + margin */ + if (exposure > fll - IMX_INTEGRATION_TIME_MARGIN) + fll = exposure + IMX_INTEGRATION_TIME_MARGIN; + } + + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->line_length_pixels, llp); + if (ret) + return ret; + + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->frame_length_lines, fll); + if (ret) + return ret; + + if (exposure) + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->coarse_integration_time, exposure); + + return ret; +} + +static int __imx_update_gain(struct v4l2_subdev *sd, u16 gain) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + /* set global gain */ + ret = imx_write_reg(client, IMX_8BIT, dev->reg_addr->global_gain, gain); + if (ret) + return ret; + + /* set short analog gain */ + if (dev->sensor_id == IMX135_ID) + ret = imx_write_reg(client, IMX_8BIT, IMX_SHORT_AGC_GAIN, gain); + + return ret; +} + +static int __imx_update_digital_gain(struct i2c_client *client, u16 digitgain) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx_device *dev = to_imx_sensor(sd); + struct imx_write_buffer digit_gain; + + digit_gain.addr = cpu_to_be16(dev->reg_addr->dgc_adj); + digit_gain.data[0] = (digitgain >> 8) & 0xFF; + digit_gain.data[1] = digitgain & 0xFF; + + if (dev->sensor_id == IMX219_ID) { + return imx_i2c_write(client, IMX219_DGC_LEN, (u8 *)&digit_gain); + } else if (dev->sensor_id == IMX227_ID) { + return imx_i2c_write(client, IMX227_DGC_LEN, (u8 *)&digit_gain); + } else { + digit_gain.data[2] = (digitgain >> 8) & 0xFF; + digit_gain.data[3] = digitgain & 0xFF; + digit_gain.data[4] = (digitgain >> 8) & 0xFF; + digit_gain.data[5] = digitgain & 0xFF; + digit_gain.data[6] = (digitgain >> 8) & 0xFF; + digit_gain.data[7] = digitgain & 0xFF; + return imx_i2c_write(client, IMX_DGC_LEN, (u8 *)&digit_gain); + } + return 0; +} + +static int imx_set_exposure_gain(struct v4l2_subdev *sd, u16 coarse_itg, + u16 gain, u16 digitgain) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int lanes = imx_get_lanes(sd); + unsigned int digitgain_scaled; + int ret = 0; + + /* Validate exposure: cannot exceed VTS-4 where VTS is 16bit */ + coarse_itg = clamp_t(u16, coarse_itg, 0, IMX_MAX_EXPOSURE_SUPPORTED); + + /* Validate gain: must not exceed maximum 8bit value */ + gain = clamp_t(u16, gain, 0, IMX_MAX_GLOBAL_GAIN_SUPPORTED); + + mutex_lock(&dev->input_lock); + + if (dev->sensor_id == IMX227_ID) { + ret = imx_write_reg_array(client, imx_param_hold); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + } + + /* For imx175, setting gain must be delayed by one */ + if ((dev->sensor_id == IMX175_ID) && dev->digital_gain) + digitgain_scaled = dev->digital_gain; + else + digitgain_scaled = digitgain; + /* imx132 with two lanes needs more gain to saturate at max */ + if (dev->sensor_id == IMX132_ID && lanes > 1) { + digitgain_scaled *= IMX132_2LANES_GAINFACT; + digitgain_scaled >>= IMX132_2LANES_GAINFACT_SHIFT; + } + /* Validate digital gain: must not exceed 12 bit value*/ + digitgain_scaled = clamp_t(unsigned int, digitgain_scaled, + 0, IMX_MAX_DIGITAL_GAIN_SUPPORTED); + + ret = __imx_update_exposure_timing(client, coarse_itg, + dev->pixels_per_line, dev->lines_per_frame); + if (ret) + goto out; + dev->coarse_itg = coarse_itg; + + if (dev->sensor_id == IMX175_ID) + ret = __imx_update_gain(sd, dev->gain); + else + ret = __imx_update_gain(sd, gain); + if (ret) + goto out; + dev->gain = gain; + + ret = __imx_update_digital_gain(client, digitgain_scaled); + if (ret) + goto out; + dev->digital_gain = digitgain; + +out: + if (dev->sensor_id == IMX227_ID) + ret = imx_write_reg_array(client, imx_param_update); + mutex_unlock(&dev->input_lock); + return ret; +} + +static long imx_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + return imx_set_exposure_gain(sd, exposure->integration_time[0], + exposure->gain[0], exposure->gain[1]); +} + +/* FIXME -To be updated with real OTP reading */ +static int imx_g_priv_int_data(struct v4l2_subdev *sd, + struct v4l2_private_int_data *priv) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + u8 __user *to = priv->data; + u32 read_size = priv->size; + int ret; + + /* No need to copy data if size is 0 */ + if (!read_size) + goto out; + + if (IS_ERR(dev->otp_data)) { + dev_err(&client->dev, "OTP data not available"); + return PTR_ERR(dev->otp_data); + } + /* Correct read_size value only if bigger than maximum */ + if (read_size > dev->otp_driver->size) + read_size = dev->otp_driver->size; + + ret = copy_to_user(to, dev->otp_data, read_size); + if (ret) { + dev_err(&client->dev, "%s: failed to copy OTP data to user\n", + __func__); + return -EFAULT; + } +out: + /* Return correct size */ + priv->size = dev->otp_driver->size; + + return 0; +} + +static int __imx_init(struct v4l2_subdev *sd, u32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + int lanes = imx_get_lanes(sd); + int ret; + + if (dev->sensor_id == IMX_ID_DEFAULT) + return 0; + + /* The default is no flip at sensor initialization */ + dev->h_flip->cur.val = 0; + dev->v_flip->cur.val = 0; + /* Sets the default FPS */ + dev->fps_index = 0; + dev->curr_res_table = dev->mode_tables->res_preview; + dev->entries_curr_table = dev->mode_tables->n_res_preview; + + ret = imx_write_reg_array(client, dev->mode_tables->init_settings); + if (ret) + return ret; + + if (dev->sensor_id == IMX132_ID && lanes > 0) { + static const u8 imx132_rglanesel[] = { + IMX132_RGLANESEL_1LANE, /* 1 lane */ + IMX132_RGLANESEL_2LANES, /* 2 lanes */ + IMX132_RGLANESEL_1LANE, /* undefined */ + IMX132_RGLANESEL_4LANES, /* 4 lanes */ + }; + ret = imx_write_reg(client, IMX_8BIT, + IMX132_RGLANESEL, imx132_rglanesel[lanes - 1]); + } + + return ret; +} + +static int imx_init(struct v4l2_subdev *sd, u32 val) +{ + struct imx_device *dev = to_imx_sensor(sd); + int ret = 0; + + mutex_lock(&dev->input_lock); + ret = __imx_init(sd, val); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long imx_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return imx_s_exposure(sd, arg); + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + return imx_g_priv_int_data(sd, arg); + default: + return -EINVAL; + } + return 0; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + int ret; + + /* power control */ + ret = dev->platform_data->power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* gpio ctrl */ + ret = dev->platform_data->gpio_ctrl(sd, 1); + if (ret) { + dev_err(&client->dev, "gpio failed\n"); + goto fail_gpio; + } + + return 0; +fail_gpio: + dev->platform_data->gpio_ctrl(sd, 0); +fail_clk: + dev->platform_data->flisclk_ctrl(sd, 0); +fail_power: + dev->platform_data->power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = dev->platform_data->gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed\n"); + + /* power control */ + ret = dev->platform_data->power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int __imx_s_power(struct v4l2_subdev *sd, int on) +{ + struct imx_device *dev = to_imx_sensor(sd); + int ret = 0; + int r = 0; + + if (on == 0) { + ret = power_down(sd); + if (dev->vcm_driver && dev->vcm_driver->power_down) + r = dev->vcm_driver->power_down(sd); + if (ret == 0) + ret = r; + dev->power = 0; + } else { + if (dev->vcm_driver && dev->vcm_driver->power_up) + ret = dev->vcm_driver->power_up(sd); + if (ret) + return ret; + ret = power_up(sd); + if (!ret) { + dev->power = 1; + return __imx_init(sd, 0); + } + } + + return ret; +} + +static int imx_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + ret = __imx_s_power(sd, on); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int imx_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct imx_reg *reglist) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx_device *dev = to_imx_sensor(sd); + int lanes = imx_get_lanes(sd); + u32 vt_pix_clk_div; + u32 vt_sys_clk_div; + u32 pre_pll_clk_div; + u32 pll_multiplier; + + const int ext_clk_freq_hz = 19200000; + struct atomisp_sensor_mode_data *buf = &info->data; + int ret; + u16 data[IMX_INTG_BUF_COUNT]; + + u32 vt_pix_clk_freq_mhz; + u32 coarse_integration_time_min; + u32 coarse_integration_time_max_margin; + u32 read_mode; + u32 div; + + if (info == NULL) + return -EINVAL; + + memset(data, 0, IMX_INTG_BUF_COUNT * sizeof(u16)); + ret = imx_read_reg(client, 1, IMX_VT_PIX_CLK_DIV, data); + if (ret) + return ret; + vt_pix_clk_div = data[0] & IMX_MASK_5BIT; + + if (dev->sensor_id == IMX132_ID || dev->sensor_id == IMX208_ID) { + static const int rgpltd[] = { 2, 4, 1, 1 }; + ret = imx_read_reg(client, 1, IMX132_208_VT_RGPLTD, data); + if (ret) + return ret; + vt_sys_clk_div = rgpltd[data[0] & IMX_MASK_2BIT]; + } else { + ret = imx_read_reg(client, 1, IMX_VT_SYS_CLK_DIV, data); + if (ret) + return ret; + vt_sys_clk_div = data[0] & IMX_MASK_2BIT; + } + ret = imx_read_reg(client, 1, IMX_PRE_PLL_CLK_DIV, data); + if (ret) + return ret; + pre_pll_clk_div = data[0] & IMX_MASK_4BIT; + + ret = imx_read_reg(client, 2, + (dev->sensor_id == IMX132_ID || + dev->sensor_id == IMX219_ID || + dev->sensor_id == IMX208_ID) ? + IMX132_208_219_PLL_MULTIPLIER : IMX_PLL_MULTIPLIER, data); + if (ret) + return ret; + pll_multiplier = data[0] & IMX_MASK_11BIT; + + memset(data, 0, IMX_INTG_BUF_COUNT * sizeof(u16)); + ret = imx_read_reg(client, 4, IMX_COARSE_INTG_TIME_MIN, data); + if (ret) + return ret; + coarse_integration_time_min = data[0]; + coarse_integration_time_max_margin = data[1]; + + /* Get the cropping and output resolution to ISP for this mode. */ + ret = imx_read_reg(client, 2, dev->reg_addr->horizontal_start_h, data); + if (ret) + return ret; + buf->crop_horizontal_start = data[0]; + + ret = imx_read_reg(client, 2, dev->reg_addr->vertical_start_h, data); + if (ret) + return ret; + buf->crop_vertical_start = data[0]; + + ret = imx_read_reg(client, 2, dev->reg_addr->horizontal_end_h, data); + if (ret) + return ret; + buf->crop_horizontal_end = data[0]; + + ret = imx_read_reg(client, 2, dev->reg_addr->vertical_end_h, data); + if (ret) + return ret; + buf->crop_vertical_end = data[0]; + + ret = imx_read_reg(client, 2, + dev->reg_addr->horizontal_output_size_h, data); + if (ret) + return ret; + buf->output_width = data[0]; + + ret = imx_read_reg(client, 2, + dev->reg_addr->vertical_output_size_h, data); + if (ret) + return ret; + buf->output_height = data[0]; + + memset(data, 0, IMX_INTG_BUF_COUNT * sizeof(u16)); + if (dev->sensor_id == IMX132_ID || dev->sensor_id == IMX208_ID || + dev->sensor_id == IMX219_ID) + read_mode = 0; + else { + if (dev->sensor_id == IMX227_ID) + ret = imx_read_reg(client, 1, IMX227_READ_MODE, data); + else + ret = imx_read_reg(client, 1, IMX_READ_MODE, data); + + if (ret) + return ret; + read_mode = data[0] & IMX_MASK_2BIT; + } + + div = pre_pll_clk_div*vt_sys_clk_div*vt_pix_clk_div; + if (div == 0) + return -EINVAL; + + if (dev->sensor_id == IMX132_ID || dev->sensor_id == IMX208_ID) + vt_pix_clk_freq_mhz = ext_clk_freq_hz / div; + else if (dev->sensor_id == IMX227_ID) { + /* according to IMX227 datasheet: + * vt_pix_freq_mhz = * num_of_vt_lanes(4) * ivt_pix_clk_freq_mhz + */ + vt_pix_clk_freq_mhz = + (u64)4 * ext_clk_freq_hz * pll_multiplier; + do_div(vt_pix_clk_freq_mhz, div); + } else + vt_pix_clk_freq_mhz = 2 * ext_clk_freq_hz / div; + + vt_pix_clk_freq_mhz *= pll_multiplier; + if (dev->sensor_id == IMX132_ID && lanes > 0) + vt_pix_clk_freq_mhz *= lanes; + + dev->vt_pix_clk_freq_mhz = vt_pix_clk_freq_mhz; + + buf->vt_pix_clk_freq_mhz = vt_pix_clk_freq_mhz; + buf->coarse_integration_time_min = coarse_integration_time_min; + buf->coarse_integration_time_max_margin = + coarse_integration_time_max_margin; + + buf->fine_integration_time_min = IMX_FINE_INTG_TIME; + buf->fine_integration_time_max_margin = IMX_FINE_INTG_TIME; + buf->fine_integration_time_def = IMX_FINE_INTG_TIME; + buf->frame_length_lines = dev->lines_per_frame; + buf->line_length_pck = dev->pixels_per_line; + buf->read_mode = read_mode; + + if (dev->sensor_id == IMX132_ID || dev->sensor_id == IMX208_ID || + dev->sensor_id == IMX219_ID) { + buf->binning_factor_x = 1; + buf->binning_factor_y = 1; + } else { + if (dev->sensor_id == IMX227_ID) + ret = imx_read_reg(client, 1, IMX227_BINNING_ENABLE, + data); + else + ret = imx_read_reg(client, 1, IMX_BINNING_ENABLE, data); + + if (ret) + return ret; + /* 1:binning enabled, 0:disabled */ + if (data[0] == 1) { + if (dev->sensor_id == IMX227_ID) + ret = imx_read_reg(client, 1, + IMX227_BINNING_TYPE, data); + else + ret = imx_read_reg(client, 1, + IMX_BINNING_TYPE, data); + + if (ret) + return ret; + buf->binning_factor_x = data[0] >> 4 & 0x0f; + if (!buf->binning_factor_x) + buf->binning_factor_x = 1; + buf->binning_factor_y = data[0] & 0xf; + if (!buf->binning_factor_y) + buf->binning_factor_y = 1; + /* WOWRKAROUND, NHD setting for IMX227 should have 4x4 + * binning but the register setting does not reflect + * this, I am asking vendor why this happens. this is + * workaround for INTEL BZ 216560. + */ + if (dev->sensor_id == IMX227_ID) { + if (dev->curr_res_table[dev->fmt_idx].width == + 376 && + dev->curr_res_table[dev->fmt_idx].height == + 656) { + buf->binning_factor_x = 4; + buf->binning_factor_y = 4; + } + } + } else { + buf->binning_factor_x = 1; + buf->binning_factor_y = 1; + } + } + + return 0; +} + +/* This returns the exposure time being used. This should only be used + for filling in EXIF data, not for actual image processing. */ +static int imx_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + u16 coarse; + int ret; + + /* the fine integration time is currently not calculated */ + ret = imx_read_reg(client, IMX_16BIT, + dev->reg_addr->coarse_integration_time, &coarse); + *value = coarse; + + return ret; +} + +static int imx_test_pattern(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + int ret; + + if (dev->power == 0) + return 0; + + ret = imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_COLOR_R, + (u16)(dev->tp_r->val >> 22)); + if (ret) + return ret; + + ret = imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_COLOR_GR, + (u16)(dev->tp_gr->val >> 22)); + if (ret) + return ret; + + ret = imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_COLOR_GB, + (u16)(dev->tp_gb->val >> 22)); + if (ret) + return ret; + + ret = imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_COLOR_B, + (u16)(dev->tp_b->val >> 22)); + if (ret) + return ret; + + return imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_MODE, + (u16)(dev->tp_mode->val)); +} + +static u32 imx_translate_bayer_order(enum atomisp_bayer_order code) +{ + switch (code) { + case atomisp_bayer_order_rggb: + return MEDIA_BUS_FMT_SRGGB10_1X10; + case atomisp_bayer_order_grbg: + return MEDIA_BUS_FMT_SGRBG10_1X10; + case atomisp_bayer_order_bggr: + return MEDIA_BUS_FMT_SBGGR10_1X10; + case atomisp_bayer_order_gbrg: + return MEDIA_BUS_FMT_SGBRG10_1X10; + } + return 0; +} + +static int imx_v_flip(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct camera_mipi_info *imx_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u16 val; + + if (dev->power == 0) + return -EIO; + + ret = imx_write_reg_array(client, dev->param_hold); + if (ret) + return ret; + + ret = imx_read_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, &val); + if (ret) + return ret; + if (value) + val |= IMX_VFLIP_BIT; + else + val &= ~IMX_VFLIP_BIT; + + ret = imx_write_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, val); + if (ret) + return ret; + + imx_info = v4l2_get_subdev_hostdata(sd); + if (imx_info) { + val &= (IMX_VFLIP_BIT|IMX_HFLIP_BIT); + imx_info->raw_bayer_order = imx_bayer_order_mapping[val]; + dev->format.code = imx_translate_bayer_order( + imx_info->raw_bayer_order); + } + + return imx_write_reg_array(client, dev->param_update); +} + +static int imx_h_flip(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct camera_mipi_info *imx_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u16 val; + + if (dev->power == 0) + return -EIO; + + ret = imx_write_reg_array(client, dev->param_hold); + if (ret) + return ret; + ret = imx_read_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, &val); + if (ret) + return ret; + if (value) + val |= IMX_HFLIP_BIT; + else + val &= ~IMX_HFLIP_BIT; + ret = imx_write_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, val); + if (ret) + return ret; + + imx_info = v4l2_get_subdev_hostdata(sd); + if (imx_info) { + val &= (IMX_VFLIP_BIT|IMX_HFLIP_BIT); + imx_info->raw_bayer_order = imx_bayer_order_mapping[val]; + dev->format.code = imx_translate_bayer_order( + imx_info->raw_bayer_order); + } + + return imx_write_reg_array(client, dev->param_update); +} + +static int imx_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (IMX_FOCAL_LENGTH_NUM << 16) | IMX_FOCAL_LENGTH_DEM; + return 0; +} + +static int imx_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (IMX_F_NUMBER_DEFAULT_NUM << 16) | IMX_F_NUMBER_DEM; + return 0; +} + +static int imx_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (IMX_F_NUMBER_DEFAULT_NUM << 24) | + (IMX_F_NUMBER_DEM << 16) | + (IMX_F_NUMBER_DEFAULT_NUM << 8) | IMX_F_NUMBER_DEM; + return 0; +} + +static int imx_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct imx_device *dev = to_imx_sensor(sd); + + *val = dev->curr_res_table[dev->fmt_idx].bin_factor_x; + + return 0; +} + +static int imx_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct imx_device *dev = to_imx_sensor(sd); + + *val = dev->curr_res_table[dev->fmt_idx].bin_factor_y; + + return 0; +} + +int imx_vcm_power_up(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->power_up) + return dev->vcm_driver->power_up(sd); + return 0; +} + +int imx_vcm_power_down(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->power_down) + return dev->vcm_driver->power_down(sd); + return 0; +} + +int imx_vcm_init(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->init) + return dev->vcm_driver->init(sd); + return 0; +} + +int imx_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_focus_vcm) + return dev->vcm_driver->t_focus_vcm(sd, val); + return 0; +} + +int imx_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_focus_abs) + return dev->vcm_driver->t_focus_abs(sd, value); + return 0; +} +int imx_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_focus_rel) + return dev->vcm_driver->t_focus_rel(sd, value); + return 0; +} + +int imx_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->q_focus_status) + return dev->vcm_driver->q_focus_status(sd, value); + return 0; +} + +int imx_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->q_focus_abs) + return dev->vcm_driver->q_focus_abs(sd, value); + return 0; +} + +int imx_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_vcm_slew) + return dev->vcm_driver->t_vcm_slew(sd, value); + return 0; +} + +int imx_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_vcm_timing) + return dev->vcm_driver->t_vcm_timing(sd, value); + return 0; +} + +static int imx_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct imx_device *dev = container_of( + ctrl->handler, struct imx_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_TEST_PATTERN: + ret = imx_test_pattern(&dev->sd); + break; + case V4L2_CID_VFLIP: + dev_dbg(&client->dev, "%s: CID_VFLIP:%d.\n", + __func__, ctrl->val); + ret = imx_v_flip(&dev->sd, ctrl->val); + break; + case V4L2_CID_HFLIP: + dev_dbg(&client->dev, "%s: CID_HFLIP:%d.\n", + __func__, ctrl->val); + ret = imx_h_flip(&dev->sd, ctrl->val); + break; + case V4L2_CID_FOCUS_ABSOLUTE: + ret = imx_t_focus_abs(&dev->sd, ctrl->val); + break; + case V4L2_CID_FOCUS_RELATIVE: + ret = imx_t_focus_rel(&dev->sd, ctrl->val); + break; + case V4L2_CID_VCM_SLEW: + ret = imx_t_vcm_slew(&dev->sd, ctrl->val); + break; + case V4L2_CID_VCM_TIMEING: + ret = imx_t_vcm_timing(&dev->sd, ctrl->val); + break; + } + + return ret; +} + +static int imx_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct imx_device *dev = container_of( + ctrl->handler, struct imx_device, ctrl_handler); + int ret = 0; + unsigned int val; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = imx_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCUS_ABSOLUTE: + ret = imx_q_focus_abs(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCUS_STATUS: + ret = imx_q_focus_status(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = imx_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = imx_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = imx_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_HORZ: + ret = imx_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = imx_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + case V4L2_CID_VBLANK: + ctrl->val = dev->lines_per_frame - + dev->curr_res_table[dev->fmt_idx].height; + break; + case V4L2_CID_HBLANK: + ctrl->val = dev->pixels_per_line - + dev->curr_res_table[dev->fmt_idx].width; + break; + case V4L2_CID_PIXEL_RATE: + ctrl->val = dev->vt_pix_clk_freq_mhz; + break; + case V4L2_CID_LINK_FREQ: + val = dev->curr_res_table[dev->fmt_idx]. + fps_options[dev->fps_index].mipi_freq; + if (val == 0) + val = dev->curr_res_table[dev->fmt_idx].mipi_freq; + if (val == 0) + return -EINVAL; + ctrl->val = val * 1000; /* To Hz */ + break; + default: + return -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = imx_s_ctrl, + .g_volatile_ctrl = imx_g_volatile_ctrl +}; + +static const struct v4l2_ctrl_config imx_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern", + .min = 0, + .max = 0xffff, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_COLOR_R, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern solid color R", + .min = INT_MIN, + .max = INT_MAX, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_COLOR_GR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern solid color GR", + .min = INT_MIN, + .max = INT_MAX, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_COLOR_GB, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern solid color GB", + .min = INT_MIN, + .max = INT_MAX, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_COLOR_B, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern solid color B", + .min = INT_MIN, + .max = INT_MAX, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flip", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Mirror", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus move absolute", + .min = 0, + .max = IMX_MAX_FOCUS_POS, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_RELATIVE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus move relative", + .min = IMX_MAX_FOCUS_NEG, + .max = IMX_MAX_FOCUS_POS, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_STATUS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus status", + .min = 0, + .max = 100, /* allow enum to grow in the future */ + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VCM_SLEW, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vcm slew", + .min = 0, + .max = IMX_VCM_SLEW_STEP_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VCM_TIMEING, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vcm step time", + .min = 0, + .max = IMX_VCM_SLEW_TIME_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = IMX_FOCAL_LENGTH_DEFAULT, + .max = IMX_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = IMX_FOCAL_LENGTH_DEFAULT, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = IMX_F_NUMBER_DEFAULT, + .max = IMX_F_NUMBER_DEFAULT, + .step = 0x01, + .def = IMX_F_NUMBER_DEFAULT, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = IMX_F_NUMBER_RANGE, + .max = IMX_F_NUMBER_RANGE, + .step = 0x01, + .def = IMX_F_NUMBER_RANGE, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "horizontal binning factor", + .min = 0, + .max = IMX_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vertical binning factor", + .min = 0, + .max = IMX_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_LINK_FREQ, + .name = "Link Frequency", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 1, + .max = 1500000 * 1000, + .step = 1, + .def = 1, + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_PIXEL_RATE, + .name = "Pixel Rate", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = INT_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HBLANK, + .name = "Horizontal Blanking", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = SHRT_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VBLANK, + .name = "Vertical Blanking", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = SHRT_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .name = "Horizontal Flip", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 1, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .name = "Vertical Flip", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 1, + .step = 1, + .def = 0, + .flags = 0, + }, +}; + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between resolution and w/h. + * res->width/height smaller than w/h wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 600 +static int distance(struct imx_resolution const *res, u32 w, u32 h, + bool keep_ratio) +{ + unsigned int w_ratio; + unsigned int h_ratio; + int match; + unsigned int allowed_ratio_mismatch = LARGEST_ALLOWED_RATIO_MISMATCH; + + if (!keep_ratio) + allowed_ratio_mismatch = ~0; + + if (w == 0) + return -1; + w_ratio = (res->width << 13) / w; + if (h == 0) + return -1; + h_ratio = (res->height << 13) / h; + if (h_ratio == 0) + return -1; + match = abs(((w_ratio << 13) / h_ratio) - ((int)8192)); + + if ((w_ratio < (int)8192) || (h_ratio < (int)8192) || + (match > allowed_ratio_mismatch)) + return -1; + + return w_ratio + h_ratio; +} + +/* Return the nearest higher resolution index */ +static int nearest_resolution_index(struct v4l2_subdev *sd, int w, int h) +{ + int i; + int idx = -1; + int dist; + int fps_diff; + int min_fps_diff = INT_MAX; + int min_dist = INT_MAX; + const struct imx_resolution *tmp_res = NULL; + struct imx_device *dev = to_imx_sensor(sd); + bool again = 1; +retry: + for (i = 0; i < dev->entries_curr_table; i++) { + tmp_res = &dev->curr_res_table[i]; + dist = distance(tmp_res, w, h, again); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + } + if (dist == min_dist) { + fps_diff = __imx_min_fps_diff(dev->targetfps, + tmp_res->fps_options); + if (fps_diff < min_fps_diff) { + min_fps_diff = fps_diff; + idx = i; + } + } + } + + /* + * FIXME! + * only IMX135 for Saltbay and IMX227 use this algorithm + */ + if (idx == -1 && again == true && dev->new_res_sel_method) { + again = false; + goto retry; + } + return idx; +} + +/* Call with ctrl_handler.lock hold */ +static int __adjust_hvblank(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + u16 new_frame_length_lines, new_line_length_pck; + int ret; + + /* + * No need to adjust h/v blank if not set dbg value + * Note that there is no other checking on the h/v blank value, + * as h/v blank can be set to any value above zero for debug purpose + */ + if (!dev->v_blank->val || !dev->h_blank->val) + return 0; + + new_frame_length_lines = dev->curr_res_table[dev->fmt_idx].height + + dev->v_blank->val; + new_line_length_pck = dev->curr_res_table[dev->fmt_idx].width + + dev->h_blank->val; + + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->line_length_pixels, new_line_length_pck); + if (ret) + return ret; + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->frame_length_lines, new_frame_length_lines); + if (ret) + return ret; + + dev->lines_per_frame = new_frame_length_lines; + dev->pixels_per_line = new_line_length_pck; + + return 0; +} + +static int imx_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct imx_device *dev = to_imx_sensor(sd); + struct camera_mipi_info *imx_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + const struct imx_resolution *res; + int lanes = imx_get_lanes(sd); + int ret; + u16 data, val; + int idx; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + imx_info = v4l2_get_subdev_hostdata(sd); + if (imx_info == NULL) + return -EINVAL; + if ((fmt->width > imx_max_res[dev->sensor_id].res_max_width) + || (fmt->height > imx_max_res[dev->sensor_id].res_max_height)) { + fmt->width = imx_max_res[dev->sensor_id].res_max_width; + fmt->height = imx_max_res[dev->sensor_id].res_max_height; + } else { + idx = nearest_resolution_index(sd, fmt->width, fmt->height); + + /* + * nearest_resolution_index() doesn't return smaller + * resolutions. If it fails, it means the requested + * resolution is higher than wecan support. Fallback + * to highest possible resolution in this case. + */ + if (idx == -1) + idx = dev->entries_curr_table - 1; + + fmt->width = dev->curr_res_table[idx].width; + fmt->height = dev->curr_res_table[idx].height; + } + + fmt->code = dev->format.code; + if(format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + return 0; + } + mutex_lock(&dev->input_lock); + + dev->fmt_idx = nearest_resolution_index(sd, fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + ret = -EINVAL; + goto out; + } + res = &dev->curr_res_table[dev->fmt_idx]; + + /* Adjust the FPS selection based on the resolution selected */ + dev->fps_index = __imx_nearest_fps_index(dev->targetfps, + res->fps_options); + dev->fps = res->fps_options[dev->fps_index].fps; + dev->regs = res->fps_options[dev->fps_index].regs; + if (!dev->regs) + dev->regs = res->regs; + + ret = imx_write_reg_array(client, dev->regs); + if (ret) + goto out; + + if (dev->sensor_id == IMX132_ID && lanes > 0) { + static const u8 imx132_rgpltd[] = { + 2, /* 1 lane: /1 */ + 0, /* 2 lanes: /2 */ + 0, /* undefined */ + 1, /* 4 lanes: /4 */ + }; + ret = imx_write_reg(client, IMX_8BIT, IMX132_208_VT_RGPLTD, + imx132_rgpltd[lanes - 1]); + if (ret) + goto out; + } + + dev->pixels_per_line = res->fps_options[dev->fps_index].pixels_per_line; + dev->lines_per_frame = res->fps_options[dev->fps_index].lines_per_frame; + + /* dbg h/v blank time */ + __adjust_hvblank(sd); + + ret = __imx_update_exposure_timing(client, dev->coarse_itg, + dev->pixels_per_line, dev->lines_per_frame); + if (ret) + goto out; + + ret = __imx_update_gain(sd, dev->gain); + if (ret) + goto out; + + ret = __imx_update_digital_gain(client, dev->digital_gain); + if (ret) + goto out; + + ret = imx_write_reg_array(client, dev->param_update); + if (ret) + goto out; + + ret = imx_get_intg_factor(client, imx_info, dev->regs); + if (ret) + goto out; + + ret = imx_read_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, &val); + if (ret) + goto out; + val &= (IMX_VFLIP_BIT|IMX_HFLIP_BIT); + imx_info->raw_bayer_order = imx_bayer_order_mapping[val]; + dev->format.code = imx_translate_bayer_order( + imx_info->raw_bayer_order); + + /* + * Fill meta data info. add imx135 metadata setting for RAW10 format + */ + switch (dev->sensor_id) { + case IMX135_ID: + ret = imx_read_reg(client, 2, + IMX135_OUTPUT_DATA_FORMAT_REG, &data); + if (ret) + goto out; + /* + * The IMX135 can support various resolutions like + * RAW6/8/10/12/14. + * 1.The data format is RAW10: + * matadata width = current resolution width(pixel) * 10 / 8 + * 2.The data format is RAW6 or RAW8: + * matadata width = current resolution width(pixel); + * 3.other data format(RAW12/14 etc): + * TBD. + */ + if (data == IMX135_OUTPUT_FORMAT_RAW10) + /* the data format is RAW10. */ + imx_info->metadata_width = res->width * 10 / 8; + else + /* The data format is RAW6/8/12/14/ etc. */ + imx_info->metadata_width = res->width; + + imx_info->metadata_height = IMX135_EMBEDDED_DATA_LINE_NUM; + + if (imx_info->metadata_effective_width == NULL) + imx_info->metadata_effective_width = + imx135_embedded_effective_size; + + break; + case IMX227_ID: + ret = imx_read_reg(client, 2, IMX227_OUTPUT_DATA_FORMAT_REG, + &data); + if (ret) + goto out; + if (data == IMX227_OUTPUT_FORMAT_RAW10) + /* the data format is RAW10. */ + imx_info->metadata_width = res->width * 10 / 8; + else + /* The data format is RAW6/8/12/14/ etc. */ + imx_info->metadata_width = res->width; + + imx_info->metadata_height = IMX227_EMBEDDED_DATA_LINE_NUM; + + if (imx_info->metadata_effective_width == NULL) + imx_info->metadata_effective_width = + imx227_embedded_effective_size; + + break; + default: + imx_info->metadata_width = 0; + imx_info->metadata_height = 0; + imx_info->metadata_effective_width = NULL; + break; + } + +out: + mutex_unlock(&dev->input_lock); + return ret; +} + + +static int imx_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct imx_device *dev = to_imx_sensor(sd); + + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + mutex_lock(&dev->input_lock); + fmt->width = dev->curr_res_table[dev->fmt_idx].width; + fmt->height = dev->curr_res_table[dev->fmt_idx].height; + fmt->code = dev->format.code; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int imx_detect(struct i2c_client *client, u16 *id, u8 *revision) +{ + struct i2c_adapter *adapter = client->adapter; + + /* i2c check */ + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + /* check sensor chip ID */ + if (imx_read_reg(client, IMX_16BIT, IMX132_175_208_219_CHIP_ID, id)) { + v4l2_err(client, "sensor_id = 0x%x\n", *id); + return -ENODEV; + } + + if (*id == IMX132_ID || *id == IMX175_ID || + *id == IMX208_ID || *id == IMX219_ID) + goto found; + + if (imx_read_reg(client, IMX_16BIT, IMX134_135_227_CHIP_ID, id)) { + v4l2_err(client, "sensor_id = 0x%x\n", *id); + return -ENODEV; + } + if (*id != IMX134_ID && *id != IMX135_ID && *id != IMX227_ID) { + v4l2_err(client, "no imx sensor found\n"); + return -ENODEV; + } +found: + v4l2_info(client, "sensor_id = 0x%x\n", *id); + + /* TODO - need to be updated */ + *revision = 0; + + return 0; +} + +static void __imx_print_timing(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 width = dev->curr_res_table[dev->fmt_idx].width; + u16 height = dev->curr_res_table[dev->fmt_idx].height; + + dev_dbg(&client->dev, "Dump imx timing in stream on:\n"); + dev_dbg(&client->dev, "width: %d:\n", width); + dev_dbg(&client->dev, "height: %d:\n", height); + dev_dbg(&client->dev, "pixels_per_line: %d:\n", dev->pixels_per_line); + dev_dbg(&client->dev, "line per frame: %d:\n", dev->lines_per_frame); + dev_dbg(&client->dev, "pix freq: %d:\n", dev->vt_pix_clk_freq_mhz); + dev_dbg(&client->dev, "init fps: %d:\n", dev->vt_pix_clk_freq_mhz / + dev->pixels_per_line / dev->lines_per_frame); + dev_dbg(&client->dev, "HBlank: %d nS:\n", + 1000 * (dev->pixels_per_line - width) / + (dev->vt_pix_clk_freq_mhz / 1000000)); + dev_dbg(&client->dev, "VBlank: %d uS:\n", + (dev->lines_per_frame - height) * dev->pixels_per_line / + (dev->vt_pix_clk_freq_mhz / 1000000)); +} + +/* + * imx stream on/off + */ +static int imx_s_stream(struct v4l2_subdev *sd, int enable) +{ + int ret; + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + if (enable) { + /* Noise reduction & dead pixel applied before streaming */ + if (dev->fw == NULL) { + dev_warn(&client->dev, "No MSR loaded from library"); + } else { + ret = apply_msr_data(client, dev->fw); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + } + ret = imx_test_pattern(sd); + if (ret) { + v4l2_err(client, "Configure test pattern failed.\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + __imx_print_timing(sd); + ret = imx_write_reg_array(client, imx_streaming); + if (ret != 0) { + v4l2_err(client, "write_reg_array err\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + dev->streaming = 1; + if (dev->vcm_driver && dev->vcm_driver->t_focus_abs_init) + dev->vcm_driver->t_focus_abs_init(sd); + } else { + ret = imx_write_reg_array(client, imx_soft_standby); + if (ret != 0) { + v4l2_err(client, "write_reg_array err\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + dev->streaming = 0; + dev->targetfps = 0; + } + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int __update_imx_device_settings(struct imx_device *dev, u16 sensor_id) +{ + /* IMX on other platform is not supported yet */ + return -EINVAL; +} + +static int imx_s_config(struct v4l2_subdev *sd, + int irq, void *pdata) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 sensor_revision; + u16 sensor_id; + int ret; + if (pdata == NULL) + return -ENODEV; + + dev->platform_data = pdata; + + mutex_lock(&dev->input_lock); + + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) { + mutex_unlock(&dev->input_lock); + dev_err(&client->dev, "imx platform init err\n"); + return ret; + } + } + /* + * power off the module first. + * + * As first power on by board have undecided state of power/gpio pins. + */ + ret = __imx_s_power(sd, 0); + if (ret) { + v4l2_err(client, "imx power-down err.\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = __imx_s_power(sd, 1); + if (ret) { + v4l2_err(client, "imx power-up err.\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = imx_detect(client, &sensor_id, &sensor_revision); + if (ret) { + v4l2_err(client, "imx_detect err s_config.\n"); + goto fail_detect; + } + + dev->sensor_id = sensor_id; + dev->sensor_revision = sensor_revision; + + /* Resolution settings depend on sensor type and platform */ + ret = __update_imx_device_settings(dev, dev->sensor_id); + if (ret) + goto fail_detect; + /* Read sensor's OTP data */ + dev->otp_data = dev->otp_driver->otp_read(sd, + dev->otp_driver->dev_addr, dev->otp_driver->start_addr, + dev->otp_driver->size); + + /* power off sensor */ + ret = __imx_s_power(sd, 0); + + mutex_unlock(&dev->input_lock); + if (ret) + v4l2_err(client, "imx power-down err.\n"); + + return ret; + +fail_detect: + dev->platform_data->csi_cfg(sd, 0); +fail_csi_cfg: + __imx_s_power(sd, 0); + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + mutex_unlock(&dev->input_lock); + dev_err(&client->dev, "sensor power-gating failed\n"); + return ret; +} + +static int +imx_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (code->index >= MAX_FMTS) + return -EINVAL; + + mutex_lock(&dev->input_lock); + code->code = dev->format.code; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int +imx_enum_frame_size(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + if (index >= dev->entries_curr_table) { + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + fse->min_width = dev->curr_res_table[index].width; + fse->min_height = dev->curr_res_table[index].height; + fse->max_width = dev->curr_res_table[index].width; + fse->max_height = dev->curr_res_table[index].height; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int +imx_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param) +{ + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + dev->run_mode = param->parm.capture.capturemode; + + switch (dev->run_mode) { + case CI_MODE_VIDEO: + dev->curr_res_table = dev->mode_tables->res_video; + dev->entries_curr_table = dev->mode_tables->n_res_video; + break; + case CI_MODE_STILL_CAPTURE: + dev->curr_res_table = dev->mode_tables->res_still; + dev->entries_curr_table = dev->mode_tables->n_res_still; + break; + default: + dev->curr_res_table = dev->mode_tables->res_preview; + dev->entries_curr_table = dev->mode_tables->n_res_preview; + } + mutex_unlock(&dev->input_lock); + return 0; +} + +int +imx_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + interval->interval.denominator = dev->fps; + interval->interval.numerator = 1; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int __imx_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + const struct imx_resolution *res = + &dev->curr_res_table[dev->fmt_idx]; + struct camera_mipi_info *imx_info = NULL; + unsigned short pixels_per_line; + unsigned short lines_per_frame; + unsigned int fps_index; + int fps; + int ret = 0; + + + imx_info = v4l2_get_subdev_hostdata(sd); + if (imx_info == NULL) + return -EINVAL; + + if (!interval->interval.numerator) + interval->interval.numerator = 1; + + fps = interval->interval.denominator / interval->interval.numerator; + + if (!fps) + return -EINVAL; + + dev->targetfps = fps; + /* No need to proceed further if we are not streaming */ + if (!dev->streaming) + return 0; + + /* Ignore if we are already using the required FPS. */ + if (fps == dev->fps) + return 0; + + /* + * Start here, sensor is already streaming, so adjust fps dynamically + */ + fps_index = __imx_above_nearest_fps_index(fps, res->fps_options); + if (fps > res->fps_options[fps_index].fps) { + /* + * if does not have high fps setting, not support increase fps + * by adjust lines per frame. + */ + dev_err(&client->dev, "Could not support fps: %d.\n", fps); + return -EINVAL; + } + + if (res->fps_options[fps_index].regs && + res->fps_options[fps_index].regs != dev->regs) { + /* + * if need a new setting, but the new setting has difference + * with current setting, not use this one, as may have + * unexpected result, e.g. PLL, IQ. + */ + dev_dbg(&client->dev, + "Sensor is streaming, not apply new sensor setting\n"); + if (fps > res->fps_options[dev->fps_index].fps) { + /* + * Does not support increase fps based on low fps + * setting, as the high fps setting could not be used, + * and fps requested is above current setting fps. + */ + dev_warn(&client->dev, + "Could not support fps: %d, keep current: %d.\n", + fps, dev->fps); + return 0; + } + } else { + dev->fps_index = fps_index; + dev->fps = res->fps_options[dev->fps_index].fps; + } + + /* Update the new frametimings based on FPS */ + pixels_per_line = res->fps_options[dev->fps_index].pixels_per_line; + lines_per_frame = res->fps_options[dev->fps_index].lines_per_frame; + + if (fps > res->fps_options[fps_index].fps) { + /* + * if does not have high fps setting, not support increase fps + * by adjust lines per frame. + */ + dev_warn(&client->dev, "Could not support fps: %d. Use:%d.\n", + fps, res->fps_options[fps_index].fps); + goto done; + } + + /* if the new setting does not match exactly */ + if (dev->fps != fps) { +#define MAX_LINES_PER_FRAME 0xffff + dev_dbg(&client->dev, "adjusting fps using lines_per_frame\n"); + /* + * FIXME! + * 1: check DS on max value of lines_per_frame + * 2: consider use pixel per line for more range? + */ + if (dev->lines_per_frame * dev->fps / fps > + MAX_LINES_PER_FRAME) { + dev_warn(&client->dev, + "adjust lines_per_frame out of range, try to use max value.\n"); + lines_per_frame = MAX_LINES_PER_FRAME; + } else { + lines_per_frame = lines_per_frame * dev->fps / fps; + } + } +done: + /* Update the new frametimings based on FPS */ + dev->pixels_per_line = pixels_per_line; + dev->lines_per_frame = lines_per_frame; + + /* Update the new values so that user side knows the current settings */ + ret = __imx_update_exposure_timing(client, + dev->coarse_itg, dev->pixels_per_line, dev->lines_per_frame); + if (ret) + return ret; + + dev->fps = fps; + + ret = imx_get_intg_factor(client, imx_info, dev->regs); + if (ret) + return ret; + + interval->interval.denominator = res->fps_options[dev->fps_index].fps; + interval->interval.numerator = 1; + __imx_print_timing(sd); + + return ret; +} + +static int imx_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct imx_device *dev = to_imx_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __imx_s_frame_interval(sd, interval); + mutex_unlock(&dev->input_lock); + + return ret; +} +static int imx_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = dev->curr_res_table[dev->fmt_idx].skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops imx_sensor_ops = { + .g_skip_frames = imx_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops imx_video_ops = { + .s_stream = imx_s_stream, + .s_parm = imx_s_parm, + .g_frame_interval = imx_g_frame_interval, + .s_frame_interval = imx_s_frame_interval, +}; + +static const struct v4l2_subdev_core_ops imx_core_ops = { + .s_power = imx_s_power, + .ioctl = imx_ioctl, + .init = imx_init, +}; + +static const struct v4l2_subdev_pad_ops imx_pad_ops = { + .enum_mbus_code = imx_enum_mbus_code, + .enum_frame_size = imx_enum_frame_size, + .get_fmt = imx_get_fmt, + .set_fmt = imx_set_fmt, +}; + +static const struct v4l2_subdev_ops imx_ops = { + .core = &imx_core_ops, + .video = &imx_video_ops, + .pad = &imx_pad_ops, + .sensor = &imx_sensor_ops, +}; + +static const struct media_entity_operations imx_entity_ops = { + .link_setup = NULL, +}; + +static int imx_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx_device *dev = to_imx_sensor(sd); + + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + dev->platform_data->csi_cfg(sd, 0); + v4l2_device_unregister_subdev(sd); + release_msr_list(client, dev->fw); + kfree(dev); + + return 0; +} + +static int __imx_init_ctrl_handler(struct imx_device *dev) +{ + struct v4l2_ctrl_handler *hdl; + int i; + + hdl = &dev->ctrl_handler; + + v4l2_ctrl_handler_init(&dev->ctrl_handler, ARRAY_SIZE(imx_controls)); + + for (i = 0; i < ARRAY_SIZE(imx_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, + &imx_controls[i], NULL); + + dev->pixel_rate = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_PIXEL_RATE); + dev->h_blank = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_HBLANK); + dev->v_blank = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_VBLANK); + dev->link_freq = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_LINK_FREQ); + dev->h_flip = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_HFLIP); + dev->v_flip = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_VFLIP); + dev->tp_mode = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN); + dev->tp_r = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN_COLOR_R); + dev->tp_gr = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN_COLOR_GR); + dev->tp_gb = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN_COLOR_GB); + dev->tp_b = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN_COLOR_B); + + if (dev->ctrl_handler.error || dev->pixel_rate == NULL + || dev->h_blank == NULL || dev->v_blank == NULL + || dev->h_flip == NULL || dev->v_flip == NULL + || dev->link_freq == NULL) { + return dev->ctrl_handler.error; + } + + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = hdl; + v4l2_ctrl_handler_setup(&dev->ctrl_handler); + + return 0; +} + +static void imx_update_reg_info(struct imx_device *dev) +{ + if (dev->sensor_id == IMX219_ID) { + dev->reg_addr = &imx219_addr; + dev->param_hold = imx219_param_hold; + dev->param_update = imx219_param_update; + } else { + dev->reg_addr = &imx_addr; + dev->param_hold = imx_param_hold; + dev->param_update = imx_param_update; + } +} + +static int imx_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct imx_device *dev; + struct camera_mipi_info *imx_info = NULL; + int ret; + char *msr_file_name = NULL; + + /* allocate sensor device & init sub device */ + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + v4l2_err(client, "%s: out of memory\n", __func__); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + dev->i2c_id = id->driver_data; + dev->fmt_idx = 0; + dev->sensor_id = IMX_ID_DEFAULT; + dev->vcm_driver = &imx_vcms[IMX_ID_DEFAULT]; + dev->digital_gain = 256; + + v4l2_i2c_subdev_init(&(dev->sd), client, &imx_ops); + + if (client->dev.platform_data) { + ret = imx_s_config(&dev->sd, client->irq, + client->dev.platform_data); + if (ret) + goto out_free; + } + imx_info = v4l2_get_subdev_hostdata(&dev->sd); + + /* + * sd->name is updated with sensor driver name by the v4l2. + * change it to sensor name in this case. + */ + imx_update_reg_info(dev); + snprintf(dev->sd.name, sizeof(dev->sd.name), "%s%x %d-%04x", + IMX_SUBDEV_PREFIX, dev->sensor_id, + i2c_adapter_id(client->adapter), client->addr); + + ret = __imx_init_ctrl_handler(dev); + if (ret) + goto out_ctrl_handler_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = imx_translate_bayer_order( + imx_info->raw_bayer_order); + dev->sd.entity.ops = &imx_entity_ops; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) { + imx_remove(client); + return ret; + } + + /* Load the Noise reduction, Dead pixel registers from cpf file*/ + if (dev->platform_data->msr_file_name != NULL) + msr_file_name = dev->platform_data->msr_file_name(); + if (msr_file_name) { + ret = load_msr_list(client, msr_file_name, &dev->fw); + if (ret) { + imx_remove(client); + return ret; + } + } else { + dev_warn(&client->dev, "Drvb file not present"); + } + + return ret; + +out_ctrl_handler_free: + v4l2_ctrl_handler_free(&dev->ctrl_handler); + +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +static const struct i2c_device_id imx_ids[] = { + {IMX_NAME_175, IMX175_ID}, + {IMX_NAME_135, IMX135_ID}, + {IMX_NAME_135_FUJI, IMX135_FUJI_ID}, + {IMX_NAME_134, IMX134_ID}, + {IMX_NAME_132, IMX132_ID}, + {IMX_NAME_208, IMX208_ID}, + {IMX_NAME_219, IMX219_ID}, + {IMX_NAME_227, IMX227_ID}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, imx_ids); + +static struct i2c_driver imx_driver = { + .driver = { + .name = IMX_DRIVER, + }, + .probe = imx_probe, + .remove = imx_remove, + .id_table = imx_ids, +}; + +static __init int init_imx(void) +{ + return i2c_add_driver(&imx_driver); +} + +static __exit void exit_imx(void) +{ + i2c_del_driver(&imx_driver); +} + +module_init(init_imx); +module_exit(exit_imx); + +MODULE_DESCRIPTION("A low-level driver for Sony IMX sensors"); +MODULE_AUTHOR("Shenbo Huang <shenbo.huang@intel.com>"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx.h b/drivers/staging/media/atomisp/i2c/imx/imx.h new file mode 100644 index 0000000..36b3f3a --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx.h @@ -0,0 +1,766 @@ +/* + * Support for Sony IMX camera sensor. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __IMX_H__ +#define __IMX_H__ +#include "../../include/linux/atomisp_platform.h" +#include "../../include/linux/atomisp.h" +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/kernel.h> +#include <linux/spinlock.h> +#include <linux/types.h> +#include <linux/videodev2.h> +#include <linux/v4l2-mediabus.h> +#include <media/media-entity.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include <media/v4l2-subdev.h> +#include "imx175.h" +#include "imx135.h" +#include "imx134.h" +#include "imx132.h" +#include "imx208.h" +#include "imx219.h" +#include "imx227.h" + +#define IMX_MCLK 192 + +/* TODO - This should be added into include/linux/videodev2.h */ +#ifndef V4L2_IDENT_IMX +#define V4L2_IDENT_IMX 8245 +#endif + +#define IMX_MAX_AE_LUT_LENGTH 5 +/* + * imx System control registers + */ +#define IMX_MASK_5BIT 0x1F +#define IMX_MASK_4BIT 0xF +#define IMX_MASK_3BIT 0x7 +#define IMX_MASK_2BIT 0x3 +#define IMX_MASK_8BIT 0xFF +#define IMX_MASK_11BIT 0x7FF +#define IMX_INTG_BUF_COUNT 2 + +#define IMX_FINE_INTG_TIME 0x1E8 + +#define IMX_VT_PIX_CLK_DIV 0x0301 +#define IMX_VT_SYS_CLK_DIV 0x0303 +#define IMX_PRE_PLL_CLK_DIV 0x0305 +#define IMX227_IOP_PRE_PLL_CLK_DIV 0x030D +#define IMX227_PLL_MULTIPLIER 0x0306 +#define IMX227_IOP_PLL_MULTIPLIER 0x030E +#define IMX227_PLL_MULTI_DRIVE 0x0310 +#define IMX227_OP_PIX_CLK_DIV 0x0309 +#define IMX227_OP_SYS_CLK_DIV 0x030B +#define IMX_PLL_MULTIPLIER 0x030C +#define IMX_OP_PIX_DIV 0x0309 +#define IMX_OP_SYS_DIV 0x030B +#define IMX_FRAME_LENGTH_LINES 0x0340 +#define IMX_LINE_LENGTH_PIXELS 0x0342 +#define IMX_COARSE_INTG_TIME_MIN 0x1004 +#define IMX_COARSE_INTG_TIME_MAX 0x1006 +#define IMX_BINNING_ENABLE 0x0390 +#define IMX227_BINNING_ENABLE 0x0900 +#define IMX_BINNING_TYPE 0x0391 +#define IMX227_BINNING_TYPE 0x0901 +#define IMX_READ_MODE 0x0390 +#define IMX227_READ_MODE 0x0900 + +#define IMX_HORIZONTAL_START_H 0x0344 +#define IMX_VERTICAL_START_H 0x0346 +#define IMX_HORIZONTAL_END_H 0x0348 +#define IMX_VERTICAL_END_H 0x034a +#define IMX_HORIZONTAL_OUTPUT_SIZE_H 0x034c +#define IMX_VERTICAL_OUTPUT_SIZE_H 0x034e + +/* Post Divider setting register for imx132 and imx208 */ +#define IMX132_208_VT_RGPLTD 0x30A4 + +/* Multiplier setting register for imx132, imx208, and imx219 */ +#define IMX132_208_219_PLL_MULTIPLIER 0x0306 + +#define IMX_COARSE_INTEGRATION_TIME 0x0202 +#define IMX_TEST_PATTERN_MODE 0x0600 +#define IMX_TEST_PATTERN_COLOR_R 0x0602 +#define IMX_TEST_PATTERN_COLOR_GR 0x0604 +#define IMX_TEST_PATTERN_COLOR_B 0x0606 +#define IMX_TEST_PATTERN_COLOR_GB 0x0608 +#define IMX_IMG_ORIENTATION 0x0101 +#define IMX_VFLIP_BIT 2 +#define IMX_HFLIP_BIT 1 +#define IMX_GLOBAL_GAIN 0x0205 +#define IMX_SHORT_AGC_GAIN 0x0233 +#define IMX_DGC_ADJ 0x020E +#define IMX_DGC_LEN 10 +#define IMX227_DGC_LEN 4 +#define IMX_MAX_EXPOSURE_SUPPORTED 0xfffb +#define IMX_MAX_GLOBAL_GAIN_SUPPORTED 0x00ff +#define IMX_MAX_DIGITAL_GAIN_SUPPORTED 0x0fff + +#define MAX_FMTS 1 +#define IMX_OTP_DATA_SIZE 1280 + +#define IMX_SUBDEV_PREFIX "imx" +#define IMX_DRIVER "imx1x5" + +/* Sensor ids from identification register */ +#define IMX_NAME_134 "imx134" +#define IMX_NAME_135 "imx135" +#define IMX_NAME_175 "imx175" +#define IMX_NAME_132 "imx132" +#define IMX_NAME_208 "imx208" +#define IMX_NAME_219 "imx219" +#define IMX_NAME_227 "imx227" +#define IMX175_ID 0x0175 +#define IMX135_ID 0x0135 +#define IMX134_ID 0x0134 +#define IMX132_ID 0x0132 +#define IMX208_ID 0x0208 +#define IMX219_ID 0x0219 +#define IMX227_ID 0x0227 + +/* Sensor id based on i2c_device_id table + * (Fuji module can not be detected based on sensor registers) */ +#define IMX135_FUJI_ID 0x0136 +#define IMX_NAME_135_FUJI "imx135fuji" + +/* imx175 - use dw9714 vcm */ +#define IMX175_MERRFLD 0x175 +#define IMX175_VALLEYVIEW 0x176 +#define IMX135_SALTBAY 0x135 +#define IMX135_VICTORIABAY 0x136 +#define IMX132_SALTBAY 0x132 +#define IMX134_VALLEYVIEW 0x134 +#define IMX208_MOFD_PD2 0x208 +#define IMX219_MFV0_PRH 0x219 +#define IMX227_SAND 0x227 + +/* otp - specific settings */ +#define E2PROM_ADDR 0xa0 +#define E2PROM_LITEON_12P1BA869D_ADDR 0xa0 +#define E2PROM_ABICO_SS89A839_ADDR 0xa8 +#define DEFAULT_OTP_SIZE 1280 +#define IMX135_OTP_SIZE 1280 +#define IMX219_OTP_SIZE 2048 +#define IMX227_OTP_SIZE 2560 +#define E2PROM_LITEON_12P1BA869D_SIZE 544 + +#define IMX_ID_DEFAULT 0x0000 +#define IMX132_175_208_219_CHIP_ID 0x0000 +#define IMX134_135_CHIP_ID 0x0016 +#define IMX134_135_227_CHIP_ID 0x0016 + +#define IMX175_RES_WIDTH_MAX 3280 +#define IMX175_RES_HEIGHT_MAX 2464 +#define IMX135_RES_WIDTH_MAX 4208 +#define IMX135_RES_HEIGHT_MAX 3120 +#define IMX132_RES_WIDTH_MAX 1936 +#define IMX132_RES_HEIGHT_MAX 1096 +#define IMX134_RES_WIDTH_MAX 3280 +#define IMX134_RES_HEIGHT_MAX 2464 +#define IMX208_RES_WIDTH_MAX 1936 +#define IMX208_RES_HEIGHT_MAX 1096 +#define IMX219_RES_WIDTH_MAX 3280 +#define IMX219_RES_HEIGHT_MAX 2464 +#define IMX227_RES_WIDTH_MAX 2400 +#define IMX227_RES_HEIGHT_MAX 2720 + +/* Defines for lens/VCM */ +#define IMX_FOCAL_LENGTH_NUM 369 /*3.69mm*/ +#define IMX_FOCAL_LENGTH_DEM 100 +#define IMX_F_NUMBER_DEFAULT_NUM 22 +#define IMX_F_NUMBER_DEM 10 +#define IMX_INVALID_CONFIG 0xffffffff +#define IMX_MAX_FOCUS_POS 1023 +#define IMX_MAX_FOCUS_NEG (-1023) +#define IMX_VCM_SLEW_STEP_MAX 0x3f +#define IMX_VCM_SLEW_TIME_MAX 0x1f + +#define IMX_BIN_FACTOR_MAX 4 +#define IMX_INTEGRATION_TIME_MARGIN 4 +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define IMX_FOCAL_LENGTH_DEFAULT 0x1710064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define IMX_F_NUMBER_DEFAULT 0x16000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define IMX_F_NUMBER_RANGE 0x160a160a + +struct imx_vcm { + int (*power_up)(struct v4l2_subdev *sd); + int (*power_down)(struct v4l2_subdev *sd); + int (*init)(struct v4l2_subdev *sd); + int (*t_focus_vcm)(struct v4l2_subdev *sd, u16 val); + int (*t_focus_abs)(struct v4l2_subdev *sd, s32 value); + int (*t_focus_abs_init)(struct v4l2_subdev *sd); + int (*t_focus_rel)(struct v4l2_subdev *sd, s32 value); + int (*q_focus_status)(struct v4l2_subdev *sd, s32 *value); + int (*q_focus_abs)(struct v4l2_subdev *sd, s32 *value); + int (*t_vcm_slew)(struct v4l2_subdev *sd, s32 value); + int (*t_vcm_timing)(struct v4l2_subdev *sd, s32 value); +}; + +struct imx_otp { + void * (*otp_read)(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); + u32 start_addr; + u32 size; + u8 dev_addr; +}; + +struct max_res { + int res_max_width; + int res_max_height; +}; + +struct max_res imx_max_res[] = { + [IMX175_ID] = { + .res_max_width = IMX175_RES_WIDTH_MAX, + .res_max_height = IMX175_RES_HEIGHT_MAX, + }, + [IMX135_ID] = { + .res_max_width = IMX135_RES_WIDTH_MAX, + .res_max_height = IMX135_RES_HEIGHT_MAX, + }, + [IMX132_ID] = { + .res_max_width = IMX132_RES_WIDTH_MAX, + .res_max_height = IMX132_RES_HEIGHT_MAX, + }, + [IMX134_ID] = { + .res_max_width = IMX134_RES_WIDTH_MAX, + .res_max_height = IMX134_RES_HEIGHT_MAX, + }, + [IMX208_ID] = { + .res_max_width = IMX208_RES_WIDTH_MAX, + .res_max_height = IMX208_RES_HEIGHT_MAX, + }, + [IMX219_ID] = { + .res_max_width = IMX219_RES_WIDTH_MAX, + .res_max_height = IMX219_RES_HEIGHT_MAX, + }, + [IMX227_ID] = { + .res_max_width = IMX227_RES_WIDTH_MAX, + .res_max_height = IMX227_RES_HEIGHT_MAX, + }, +}; + +struct imx_settings { + struct imx_reg const *init_settings; + struct imx_resolution *res_preview; + struct imx_resolution *res_still; + struct imx_resolution *res_video; + int n_res_preview; + int n_res_still; + int n_res_video; +}; + +struct imx_settings imx_sets[] = { + [IMX175_MERRFLD] = { + .init_settings = imx175_init_settings, + .res_preview = imx175_res_preview, + .res_still = imx175_res_still, + .res_video = imx175_res_video, + .n_res_preview = ARRAY_SIZE(imx175_res_preview), + .n_res_still = ARRAY_SIZE(imx175_res_still), + .n_res_video = ARRAY_SIZE(imx175_res_video), + }, + [IMX175_VALLEYVIEW] = { + .init_settings = imx175_init_settings, + .res_preview = imx175_res_preview, + .res_still = imx175_res_still, + .res_video = imx175_res_video, + .n_res_preview = ARRAY_SIZE(imx175_res_preview), + .n_res_still = ARRAY_SIZE(imx175_res_still), + .n_res_video = ARRAY_SIZE(imx175_res_video), + }, + [IMX135_SALTBAY] = { + .init_settings = imx135_init_settings, + .res_preview = imx135_res_preview, + .res_still = imx135_res_still, + .res_video = imx135_res_video, + .n_res_preview = ARRAY_SIZE(imx135_res_preview), + .n_res_still = ARRAY_SIZE(imx135_res_still), + .n_res_video = ARRAY_SIZE(imx135_res_video), + }, + [IMX135_VICTORIABAY] = { + .init_settings = imx135_init_settings, + .res_preview = imx135_res_preview_mofd, + .res_still = imx135_res_still_mofd, + .res_video = imx135_res_video, + .n_res_preview = ARRAY_SIZE(imx135_res_preview_mofd), + .n_res_still = ARRAY_SIZE(imx135_res_still_mofd), + .n_res_video = ARRAY_SIZE(imx135_res_video), + }, + [IMX132_SALTBAY] = { + .init_settings = imx132_init_settings, + .res_preview = imx132_res_preview, + .res_still = imx132_res_still, + .res_video = imx132_res_video, + .n_res_preview = ARRAY_SIZE(imx132_res_preview), + .n_res_still = ARRAY_SIZE(imx132_res_still), + .n_res_video = ARRAY_SIZE(imx132_res_video), + }, + [IMX134_VALLEYVIEW] = { + .init_settings = imx134_init_settings, + .res_preview = imx134_res_preview, + .res_still = imx134_res_still, + .res_video = imx134_res_video, + .n_res_preview = ARRAY_SIZE(imx134_res_preview), + .n_res_still = ARRAY_SIZE(imx134_res_still), + .n_res_video = ARRAY_SIZE(imx134_res_video), + }, + [IMX208_MOFD_PD2] = { + .init_settings = imx208_init_settings, + .res_preview = imx208_res_preview, + .res_still = imx208_res_still, + .res_video = imx208_res_video, + .n_res_preview = ARRAY_SIZE(imx208_res_preview), + .n_res_still = ARRAY_SIZE(imx208_res_still), + .n_res_video = ARRAY_SIZE(imx208_res_video), + }, + [IMX219_MFV0_PRH] = { + .init_settings = imx219_init_settings, + .res_preview = imx219_res_preview, + .res_still = imx219_res_still, + .res_video = imx219_res_video, + .n_res_preview = ARRAY_SIZE(imx219_res_preview), + .n_res_still = ARRAY_SIZE(imx219_res_still), + .n_res_video = ARRAY_SIZE(imx219_res_video), + }, + [IMX227_SAND] = { + .init_settings = imx227_init_settings, + .res_preview = imx227_res_preview, + .res_still = imx227_res_still, + .res_video = imx227_res_video, + .n_res_preview = ARRAY_SIZE(imx227_res_preview), + .n_res_still = ARRAY_SIZE(imx227_res_still), + .n_res_video = ARRAY_SIZE(imx227_res_video), + }, +}; + +struct imx_reg_addr { + u16 frame_length_lines; + u16 line_length_pixels; + u16 horizontal_start_h; + u16 vertical_start_h; + u16 horizontal_end_h; + u16 vertical_end_h; + u16 horizontal_output_size_h; + u16 vertical_output_size_h; + u16 coarse_integration_time; + u16 img_orientation; + u16 global_gain; + u16 dgc_adj; +}; + +struct imx_reg_addr imx_addr = { + IMX_FRAME_LENGTH_LINES, + IMX_LINE_LENGTH_PIXELS, + IMX_HORIZONTAL_START_H, + IMX_VERTICAL_START_H, + IMX_HORIZONTAL_END_H, + IMX_VERTICAL_END_H, + IMX_HORIZONTAL_OUTPUT_SIZE_H, + IMX_VERTICAL_OUTPUT_SIZE_H, + IMX_COARSE_INTEGRATION_TIME, + IMX_IMG_ORIENTATION, + IMX_GLOBAL_GAIN, + IMX_DGC_ADJ, +}; + +struct imx_reg_addr imx219_addr = { + IMX219_FRAME_LENGTH_LINES, + IMX219_LINE_LENGTH_PIXELS, + IMX219_HORIZONTAL_START_H, + IMX219_VERTICAL_START_H, + IMX219_HORIZONTAL_END_H, + IMX219_VERTICAL_END_H, + IMX219_HORIZONTAL_OUTPUT_SIZE_H, + IMX219_VERTICAL_OUTPUT_SIZE_H, + IMX219_COARSE_INTEGRATION_TIME, + IMX219_IMG_ORIENTATION, + IMX219_GLOBAL_GAIN, + IMX219_DGC_ADJ, +}; + +#define v4l2_format_capture_type_entry(_width, _height, \ + _pixelformat, _bytesperline, _colorspace) \ + {\ + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,\ + .fmt.pix.width = (_width),\ + .fmt.pix.height = (_height),\ + .fmt.pix.pixelformat = (_pixelformat),\ + .fmt.pix.bytesperline = (_bytesperline),\ + .fmt.pix.colorspace = (_colorspace),\ + .fmt.pix.sizeimage = (_height)*(_bytesperline),\ + } + +#define s_output_format_entry(_width, _height, _pixelformat, \ + _bytesperline, _colorspace, _fps) \ + {\ + .v4l2_fmt = v4l2_format_capture_type_entry(_width, \ + _height, _pixelformat, _bytesperline, \ + _colorspace),\ + .fps = (_fps),\ + } + +#define s_output_format_reg_entry(_width, _height, _pixelformat, \ + _bytesperline, _colorspace, _fps, _reg_setting) \ + {\ + .s_fmt = s_output_format_entry(_width, _height,\ + _pixelformat, _bytesperline, \ + _colorspace, _fps),\ + .reg_setting = (_reg_setting),\ + } + +/* imx device structure */ +struct imx_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct camera_sensor_platform_data *platform_data; + struct mutex input_lock; /* serialize sensor's ioctl */ + int fmt_idx; + int status; + int streaming; + int power; + int run_mode; + int vt_pix_clk_freq_mhz; + int fps_index; + u32 focus; + u16 sensor_id; /* Sensor id from registers */ + u16 i2c_id; /* Sensor id from i2c_device_id */ + u16 coarse_itg; + u16 fine_itg; + u16 digital_gain; + u16 gain; + u16 pixels_per_line; + u16 lines_per_frame; + u8 targetfps; + u8 fps; + const struct imx_reg *regs; + u8 res; + u8 type; + u8 sensor_revision; + u8 *otp_data; + struct imx_settings *mode_tables; + struct imx_vcm *vcm_driver; + struct imx_otp *otp_driver; + const struct imx_resolution *curr_res_table; + int entries_curr_table; + const struct firmware *fw; + struct imx_reg_addr *reg_addr; + const struct imx_reg *param_hold; + const struct imx_reg *param_update; + + /* used for h/b blank tuning */ + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *h_blank; + struct v4l2_ctrl *v_blank; + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *h_flip; + struct v4l2_ctrl *v_flip; + + /* Test pattern control */ + struct v4l2_ctrl *tp_mode; + struct v4l2_ctrl *tp_r; + struct v4l2_ctrl *tp_gr; + struct v4l2_ctrl *tp_gb; + struct v4l2_ctrl *tp_b; + + /* FIXME! */ + bool new_res_sel_method; +}; + +#define to_imx_sensor(x) container_of(x, struct imx_device, sd) + +#define IMX_MAX_WRITE_BUF_SIZE 32 +struct imx_write_buffer { + u16 addr; + u8 data[IMX_MAX_WRITE_BUF_SIZE]; +}; + +struct imx_write_ctrl { + int index; + struct imx_write_buffer buffer; +}; + +static const struct imx_reg imx_soft_standby[] = { + {IMX_8BIT, 0x0100, 0x00}, + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx_streaming[] = { + {IMX_8BIT, 0x0100, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx_param_hold[] = { + {IMX_8BIT, 0x0104, 0x01}, /* GROUPED_PARAMETER_HOLD */ + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx_param_update[] = { + {IMX_8BIT, 0x0104, 0x00}, /* GROUPED_PARAMETER_HOLD */ + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx219_param_hold[] = { + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx219_param_update[] = { + {IMX_TOK_TERM, 0, 0} +}; + +extern int ad5816g_vcm_power_up(struct v4l2_subdev *sd); +extern int ad5816g_vcm_power_down(struct v4l2_subdev *sd); +extern int ad5816g_vcm_init(struct v4l2_subdev *sd); + +extern int ad5816g_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int ad5816g_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int ad5816g_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int ad5816g_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int ad5816g_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int ad5816g_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int ad5816g_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int drv201_vcm_power_up(struct v4l2_subdev *sd); +extern int drv201_vcm_power_down(struct v4l2_subdev *sd); +extern int drv201_vcm_init(struct v4l2_subdev *sd); + +extern int drv201_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int drv201_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int drv201_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int drv201_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int drv201_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int drv201_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int drv201_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int dw9714_vcm_power_up(struct v4l2_subdev *sd); +extern int dw9714_vcm_power_down(struct v4l2_subdev *sd); +extern int dw9714_vcm_init(struct v4l2_subdev *sd); + +extern int dw9714_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int dw9714_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int dw9714_t_focus_abs_init(struct v4l2_subdev *sd); +extern int dw9714_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int dw9714_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int dw9714_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int dw9714_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int dw9714_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int dw9719_vcm_power_up(struct v4l2_subdev *sd); +extern int dw9719_vcm_power_down(struct v4l2_subdev *sd); +extern int dw9719_vcm_init(struct v4l2_subdev *sd); + +extern int dw9719_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int dw9719_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int dw9719_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int dw9719_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int dw9719_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int dw9719_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int dw9719_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int dw9718_vcm_power_up(struct v4l2_subdev *sd); +extern int dw9718_vcm_power_down(struct v4l2_subdev *sd); +extern int dw9718_vcm_init(struct v4l2_subdev *sd); + +extern int dw9718_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int vcm_power_up(struct v4l2_subdev *sd); +extern int vcm_power_down(struct v4l2_subdev *sd); + +struct imx_vcm imx_vcms[] = { + [IMX175_MERRFLD] = { + .power_up = drv201_vcm_power_up, + .power_down = drv201_vcm_power_down, + .init = drv201_vcm_init, + .t_focus_vcm = drv201_t_focus_vcm, + .t_focus_abs = drv201_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = drv201_t_focus_rel, + .q_focus_status = drv201_q_focus_status, + .q_focus_abs = drv201_q_focus_abs, + .t_vcm_slew = drv201_t_vcm_slew, + .t_vcm_timing = drv201_t_vcm_timing, + }, + [IMX175_VALLEYVIEW] = { + .power_up = dw9714_vcm_power_up, + .power_down = dw9714_vcm_power_down, + .init = dw9714_vcm_init, + .t_focus_vcm = dw9714_t_focus_vcm, + .t_focus_abs = dw9714_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = dw9714_t_focus_rel, + .q_focus_status = dw9714_q_focus_status, + .q_focus_abs = dw9714_q_focus_abs, + .t_vcm_slew = dw9714_t_vcm_slew, + .t_vcm_timing = dw9714_t_vcm_timing, + }, + [IMX135_SALTBAY] = { + .power_up = ad5816g_vcm_power_up, + .power_down = ad5816g_vcm_power_down, + .init = ad5816g_vcm_init, + .t_focus_vcm = ad5816g_t_focus_vcm, + .t_focus_abs = ad5816g_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = ad5816g_t_focus_rel, + .q_focus_status = ad5816g_q_focus_status, + .q_focus_abs = ad5816g_q_focus_abs, + .t_vcm_slew = ad5816g_t_vcm_slew, + .t_vcm_timing = ad5816g_t_vcm_timing, + }, + [IMX135_VICTORIABAY] = { + .power_up = dw9719_vcm_power_up, + .power_down = dw9719_vcm_power_down, + .init = dw9719_vcm_init, + .t_focus_vcm = dw9719_t_focus_vcm, + .t_focus_abs = dw9719_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = dw9719_t_focus_rel, + .q_focus_status = dw9719_q_focus_status, + .q_focus_abs = dw9719_q_focus_abs, + .t_vcm_slew = dw9719_t_vcm_slew, + .t_vcm_timing = dw9719_t_vcm_timing, + }, + [IMX134_VALLEYVIEW] = { + .power_up = dw9714_vcm_power_up, + .power_down = dw9714_vcm_power_down, + .init = dw9714_vcm_init, + .t_focus_vcm = dw9714_t_focus_vcm, + .t_focus_abs = dw9714_t_focus_abs, + .t_focus_abs_init = dw9714_t_focus_abs_init, + .t_focus_rel = dw9714_t_focus_rel, + .q_focus_status = dw9714_q_focus_status, + .q_focus_abs = dw9714_q_focus_abs, + .t_vcm_slew = dw9714_t_vcm_slew, + .t_vcm_timing = dw9714_t_vcm_timing, + }, + [IMX219_MFV0_PRH] = { + .power_up = dw9718_vcm_power_up, + .power_down = dw9718_vcm_power_down, + .init = dw9718_vcm_init, + .t_focus_vcm = dw9718_t_focus_vcm, + .t_focus_abs = dw9718_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = dw9718_t_focus_rel, + .q_focus_status = dw9718_q_focus_status, + .q_focus_abs = dw9718_q_focus_abs, + .t_vcm_slew = dw9718_t_vcm_slew, + .t_vcm_timing = dw9718_t_vcm_timing, + }, + [IMX_ID_DEFAULT] = { + .power_up = NULL, + .power_down = NULL, + .t_focus_abs_init = NULL, + }, +}; + +extern void *dummy_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *imx_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *e2prom_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *brcc064_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *imx227_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *e2prom_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +struct imx_otp imx_otps[] = { + [IMX175_MERRFLD] = { + .otp_read = imx_otp_read, + .dev_addr = E2PROM_ADDR, + .start_addr = 0, + .size = DEFAULT_OTP_SIZE, + }, + [IMX175_VALLEYVIEW] = { + .otp_read = e2prom_otp_read, + .dev_addr = E2PROM_ABICO_SS89A839_ADDR, + .start_addr = E2PROM_2ADDR, + .size = DEFAULT_OTP_SIZE, + }, + [IMX135_SALTBAY] = { + .otp_read = e2prom_otp_read, + .dev_addr = E2PROM_ADDR, + .start_addr = 0, + .size = DEFAULT_OTP_SIZE, + }, + [IMX135_VICTORIABAY] = { + .otp_read = imx_otp_read, + .size = DEFAULT_OTP_SIZE, + }, + [IMX134_VALLEYVIEW] = { + .otp_read = e2prom_otp_read, + .dev_addr = E2PROM_LITEON_12P1BA869D_ADDR, + .start_addr = 0, + .size = E2PROM_LITEON_12P1BA869D_SIZE, + }, + [IMX132_SALTBAY] = { + .otp_read = dummy_otp_read, + .size = DEFAULT_OTP_SIZE, + }, + [IMX208_MOFD_PD2] = { + .otp_read = dummy_otp_read, + .size = DEFAULT_OTP_SIZE, + }, + [IMX219_MFV0_PRH] = { + .otp_read = brcc064_otp_read, + .dev_addr = E2PROM_ADDR, + .start_addr = 0, + .size = IMX219_OTP_SIZE, + }, + [IMX227_SAND] = { + .otp_read = imx227_otp_read, + .size = IMX227_OTP_SIZE, + }, + [IMX_ID_DEFAULT] = { + .otp_read = dummy_otp_read, + .size = DEFAULT_OTP_SIZE, + }, +}; + +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx132.h b/drivers/staging/media/atomisp/i2c/imx/imx132.h new file mode 100644 index 0000000..98f047b --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx132.h @@ -0,0 +1,566 @@ +/* + * Support for Sony IMX camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __IMX132_H__ +#define __IMX132_H__ +#include "common.h" + +/********************** registers define ********************************/ +#define IMX132_RGLANESEL 0x3301 /* Number of lanes */ +#define IMX132_RGLANESEL_1LANE 0x01 +#define IMX132_RGLANESEL_2LANES 0x00 +#define IMX132_RGLANESEL_4LANES 0x03 + +#define IMX132_2LANES_GAINFACT 2096 /* 524/256 * 2^10 */ +#define IMX132_2LANES_GAINFACT_SHIFT 10 + +/********************** settings for imx from vendor*********************/ +static struct imx_reg imx132_1080p_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + /* PLL setting */ + {IMX_8BIT, 0x0305, 0x02}, + {IMX_8BIT, 0x0307, 0x50}, + {IMX_8BIT, 0x30A4, 0x02}, + {IMX_8BIT, 0x303C, 0x3C}, + /* Mode setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x14}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x32}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0xA3}, + {IMX_8BIT, 0x034A, 0x04}, + {IMX_8BIT, 0x034B, 0x79}, + {IMX_8BIT, 0x034C, 0x07}, + {IMX_8BIT, 0x034D, 0x90}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x48}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x303D, 0x10}, + {IMX_8BIT, 0x303E, 0x5A}, + {IMX_8BIT, 0x3040, 0x00}, + {IMX_8BIT, 0x3041, 0x00}, + {IMX_8BIT, 0x3048, 0x00}, + {IMX_8BIT, 0x304C, 0x2F}, + {IMX_8BIT, 0x304D, 0x02}, + {IMX_8BIT, 0x3064, 0x92}, + {IMX_8BIT, 0x306A, 0x10}, + {IMX_8BIT, 0x309B, 0x00}, + {IMX_8BIT, 0x309E, 0x41}, + {IMX_8BIT, 0x30A0, 0x10}, + {IMX_8BIT, 0x30A1, 0x0B}, + {IMX_8BIT, 0x30B2, 0x00}, + {IMX_8BIT, 0x30D5, 0x00}, + {IMX_8BIT, 0x30D6, 0x00}, + {IMX_8BIT, 0x30D7, 0x00}, + {IMX_8BIT, 0x30D8, 0x00}, + {IMX_8BIT, 0x30D9, 0x00}, + {IMX_8BIT, 0x30DA, 0x00}, + {IMX_8BIT, 0x30DB, 0x00}, + {IMX_8BIT, 0x30DC, 0x00}, + {IMX_8BIT, 0x30DD, 0x00}, + {IMX_8BIT, 0x30DE, 0x00}, + {IMX_8BIT, 0x3102, 0x0C}, + {IMX_8BIT, 0x3103, 0x33}, + {IMX_8BIT, 0x3104, 0x18}, + {IMX_8BIT, 0x3105, 0x00}, + {IMX_8BIT, 0x3106, 0x65}, + {IMX_8BIT, 0x3107, 0x00}, + {IMX_8BIT, 0x3108, 0x06}, + {IMX_8BIT, 0x3109, 0x04}, + {IMX_8BIT, 0x310A, 0x04}, + {IMX_8BIT, 0x315C, 0x3D}, + {IMX_8BIT, 0x315D, 0x3C}, + {IMX_8BIT, 0x316E, 0x3E}, + {IMX_8BIT, 0x316F, 0x3D}, + /* Global timing */ + {IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */ + {IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */ + {IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */ + {IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */ + {IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */ + {IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */ + {IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */ + {IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */ + {IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */ + {IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */ + {IMX_8BIT, 0x330E, 0x03}, + {IMX_8BIT, 0x3318, 0x62}, + {IMX_8BIT, 0x3322, 0x09}, + {IMX_8BIT, 0x3342, 0x00}, + {IMX_8BIT, 0x3348, 0xE0}, + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx132_1456x1096_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + /* PLL setting */ + {IMX_8BIT, 0x0305, 0x02}, + {IMX_8BIT, 0x0307, 0x50}, + {IMX_8BIT, 0x30A4, 0x02}, + {IMX_8BIT, 0x303C, 0x3C}, + /* Mode setting */ + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0x04}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x32}, + {IMX_8BIT, 0x0348, 0x06}, + {IMX_8BIT, 0x0349, 0xB3}, + {IMX_8BIT, 0x034A, 0x04}, + {IMX_8BIT, 0x034B, 0x79}, + {IMX_8BIT, 0x034C, 0x05}, + {IMX_8BIT, 0x034D, 0xB0}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x48}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x303D, 0x10}, + {IMX_8BIT, 0x303E, 0x5A}, + {IMX_8BIT, 0x3040, 0x00}, + {IMX_8BIT, 0x3041, 0x00}, + {IMX_8BIT, 0x3048, 0x00}, + {IMX_8BIT, 0x304C, 0x2F}, + {IMX_8BIT, 0x304D, 0x02}, + {IMX_8BIT, 0x3064, 0x92}, + {IMX_8BIT, 0x306A, 0x10}, + {IMX_8BIT, 0x309B, 0x00}, + {IMX_8BIT, 0x309E, 0x41}, + {IMX_8BIT, 0x30A0, 0x10}, + {IMX_8BIT, 0x30A1, 0x0B}, + {IMX_8BIT, 0x30B2, 0x00}, + {IMX_8BIT, 0x30D5, 0x00}, + {IMX_8BIT, 0x30D6, 0x00}, + {IMX_8BIT, 0x30D7, 0x00}, + {IMX_8BIT, 0x30D8, 0x00}, + {IMX_8BIT, 0x30D9, 0x00}, + {IMX_8BIT, 0x30DA, 0x00}, + {IMX_8BIT, 0x30DB, 0x00}, + {IMX_8BIT, 0x30DC, 0x00}, + {IMX_8BIT, 0x30DD, 0x00}, + {IMX_8BIT, 0x30DE, 0x00}, + {IMX_8BIT, 0x3102, 0x0C}, + {IMX_8BIT, 0x3103, 0x33}, + {IMX_8BIT, 0x3104, 0x18}, + {IMX_8BIT, 0x3105, 0x00}, + {IMX_8BIT, 0x3106, 0x65}, + {IMX_8BIT, 0x3107, 0x00}, + {IMX_8BIT, 0x3108, 0x06}, + {IMX_8BIT, 0x3109, 0x04}, + {IMX_8BIT, 0x310A, 0x04}, + {IMX_8BIT, 0x315C, 0x3D}, + {IMX_8BIT, 0x315D, 0x3C}, + {IMX_8BIT, 0x316E, 0x3E}, + {IMX_8BIT, 0x316F, 0x3D}, + /* Global timing */ + {IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */ + {IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */ + {IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */ + {IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */ + {IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */ + {IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */ + {IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */ + {IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */ + {IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */ + {IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */ + {IMX_8BIT, 0x330E, 0x03}, + {IMX_8BIT, 0x3318, 0x62}, + {IMX_8BIT, 0x3322, 0x09}, + {IMX_8BIT, 0x3342, 0x00}, + {IMX_8BIT, 0x3348, 0xE0}, + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx132_1636x1096_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + /* PLL setting */ + {IMX_8BIT, 0x0305, 0x02}, + {IMX_8BIT, 0x0307, 0x50}, + {IMX_8BIT, 0x30A4, 0x02}, + {IMX_8BIT, 0x303C, 0x3C}, + /* Mode setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0xAA}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x32}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0x0D}, + {IMX_8BIT, 0x034A, 0x04}, + {IMX_8BIT, 0x034B, 0x79}, + {IMX_8BIT, 0x034C, 0x06}, + {IMX_8BIT, 0x034D, 0x64}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x48}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x303D, 0x10}, + {IMX_8BIT, 0x303E, 0x5A}, + {IMX_8BIT, 0x3040, 0x00}, + {IMX_8BIT, 0x3041, 0x00}, + {IMX_8BIT, 0x3048, 0x00}, + {IMX_8BIT, 0x304C, 0x2F}, + {IMX_8BIT, 0x304D, 0x02}, + {IMX_8BIT, 0x3064, 0x92}, + {IMX_8BIT, 0x306A, 0x10}, + {IMX_8BIT, 0x309B, 0x00}, + {IMX_8BIT, 0x309E, 0x41}, + {IMX_8BIT, 0x30A0, 0x10}, + {IMX_8BIT, 0x30A1, 0x0B}, + {IMX_8BIT, 0x30B2, 0x00}, + {IMX_8BIT, 0x30D5, 0x00}, + {IMX_8BIT, 0x30D6, 0x00}, + {IMX_8BIT, 0x30D7, 0x00}, + {IMX_8BIT, 0x30D8, 0x00}, + {IMX_8BIT, 0x30D9, 0x00}, + {IMX_8BIT, 0x30DA, 0x00}, + {IMX_8BIT, 0x30DB, 0x00}, + {IMX_8BIT, 0x30DC, 0x00}, + {IMX_8BIT, 0x30DD, 0x00}, + {IMX_8BIT, 0x30DE, 0x00}, + {IMX_8BIT, 0x3102, 0x0C}, + {IMX_8BIT, 0x3103, 0x33}, + {IMX_8BIT, 0x3104, 0x18}, + {IMX_8BIT, 0x3105, 0x00}, + {IMX_8BIT, 0x3106, 0x65}, + {IMX_8BIT, 0x3107, 0x00}, + {IMX_8BIT, 0x3108, 0x06}, + {IMX_8BIT, 0x3109, 0x04}, + {IMX_8BIT, 0x310A, 0x04}, + {IMX_8BIT, 0x315C, 0x3D}, + {IMX_8BIT, 0x315D, 0x3C}, + {IMX_8BIT, 0x316E, 0x3E}, + {IMX_8BIT, 0x316F, 0x3D}, + /* Global timing */ + {IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */ + {IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */ + {IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */ + {IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */ + {IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */ + {IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */ + {IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */ + {IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */ + {IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */ + {IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */ + {IMX_8BIT, 0x330E, 0x03}, + {IMX_8BIT, 0x3318, 0x62}, + {IMX_8BIT, 0x3322, 0x09}, + {IMX_8BIT, 0x3342, 0x00}, + {IMX_8BIT, 0x3348, 0xE0}, + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx132_1336x1096_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + /* PLL setting */ + {IMX_8BIT, 0x0305, 0x02}, + {IMX_8BIT, 0x0307, 0x50}, + {IMX_8BIT, 0x30A4, 0x02}, + {IMX_8BIT, 0x303C, 0x3C}, + /* Mode setting */ + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0x2C}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x32}, + {IMX_8BIT, 0x0348, 0x06}, + {IMX_8BIT, 0x0349, 0x77}, + {IMX_8BIT, 0x034A, 0x04}, + {IMX_8BIT, 0x034B, 0x79}, + {IMX_8BIT, 0x034C, 0x05}, + {IMX_8BIT, 0x034D, 0x38}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x48}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x303D, 0x10}, + {IMX_8BIT, 0x303E, 0x5A}, + {IMX_8BIT, 0x3040, 0x00}, + {IMX_8BIT, 0x3041, 0x00}, + {IMX_8BIT, 0x3048, 0x00}, + {IMX_8BIT, 0x304C, 0x2F}, + {IMX_8BIT, 0x304D, 0x02}, + {IMX_8BIT, 0x3064, 0x92}, + {IMX_8BIT, 0x306A, 0x10}, + {IMX_8BIT, 0x309B, 0x00}, + {IMX_8BIT, 0x309E, 0x41}, + {IMX_8BIT, 0x30A0, 0x10}, + {IMX_8BIT, 0x30A1, 0x0B}, + {IMX_8BIT, 0x30B2, 0x00}, + {IMX_8BIT, 0x30D5, 0x00}, + {IMX_8BIT, 0x30D6, 0x00}, + {IMX_8BIT, 0x30D7, 0x00}, + {IMX_8BIT, 0x30D8, 0x00}, + {IMX_8BIT, 0x30D9, 0x00}, + {IMX_8BIT, 0x30DA, 0x00}, + {IMX_8BIT, 0x30DB, 0x00}, + {IMX_8BIT, 0x30DC, 0x00}, + {IMX_8BIT, 0x30DD, 0x00}, + {IMX_8BIT, 0x30DE, 0x00}, + {IMX_8BIT, 0x3102, 0x0C}, + {IMX_8BIT, 0x3103, 0x33}, + {IMX_8BIT, 0x3104, 0x18}, + {IMX_8BIT, 0x3105, 0x00}, + {IMX_8BIT, 0x3106, 0x65}, + {IMX_8BIT, 0x3107, 0x00}, + {IMX_8BIT, 0x3108, 0x06}, + {IMX_8BIT, 0x3109, 0x04}, + {IMX_8BIT, 0x310A, 0x04}, + {IMX_8BIT, 0x315C, 0x3D}, + {IMX_8BIT, 0x315D, 0x3C}, + {IMX_8BIT, 0x316E, 0x3E}, + {IMX_8BIT, 0x316F, 0x3D}, + /* Global timing */ + {IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */ + {IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */ + {IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */ + {IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */ + {IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */ + {IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */ + {IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */ + {IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */ + {IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */ + {IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */ + {IMX_8BIT, 0x330E, 0x03}, + {IMX_8BIT, 0x3318, 0x62}, + {IMX_8BIT, 0x3322, 0x09}, + {IMX_8BIT, 0x3342, 0x00}, + {IMX_8BIT, 0x3348, 0xE0}, + + {IMX_TOK_TERM, 0, 0}, +}; + +/********************** settings for imx - reference *********************/ +static struct imx_reg const imx132_init_settings[] = { + /* sw reset */ + { IMX_8BIT, 0x0100, 0x00 }, + { IMX_8BIT, 0x0103, 0x01 }, + { IMX_TOK_DELAY, 0, 5}, + { IMX_8BIT, 0x0103, 0x00 }, + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + GROUPED_PARAMETER_HOLD_DISABLE, + { IMX_TOK_TERM, 0, 0} +}; + +struct imx_resolution imx132_res_preview[] = { + { + .desc = "imx132_1080p_30fps", + .regs = imx132_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, +}; + +struct imx_resolution imx132_res_still[] = { + { + .desc = "imx132_1080p_30fps", + .regs = imx132_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, +}; + +struct imx_resolution imx132_res_video[] = { + { + .desc = "imx132_1336x1096_30fps", + .regs = imx132_1336x1096_30fps, + .width = 1336, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, + { + .desc = "imx132_1456x1096_30fps", + .regs = imx132_1456x1096_30fps, + .width = 1456, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, + { + .desc = "imx132_1636x1096_30fps", + .regs = imx132_1636x1096_30fps, + .width = 1636, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, + { + .desc = "imx132_1080p_30fps", + .regs = imx132_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, +}; +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx134.h b/drivers/staging/media/atomisp/i2c/imx/imx134.h new file mode 100644 index 0000000..cf35197 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx134.h @@ -0,0 +1,2464 @@ +#ifndef __IMX134_H__ +#define __IMX134_H__ + +/********************** imx134 setting - version 1 *********************/ +static struct imx_reg const imx134_init_settings[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Basic settings */ + { IMX_8BIT, 0x0105, 0x01 }, + { IMX_8BIT, 0x0220, 0x01 }, + { IMX_8BIT, 0x3302, 0x11 }, + { IMX_8BIT, 0x3833, 0x20 }, + { IMX_8BIT, 0x3893, 0x00 }, + { IMX_8BIT, 0x3906, 0x08 }, + { IMX_8BIT, 0x3907, 0x01 }, + { IMX_8BIT, 0x391B, 0x01 }, + { IMX_8BIT, 0x3C09, 0x01 }, + { IMX_8BIT, 0x600A, 0x00 }, + + /* Analog settings */ + { IMX_8BIT, 0x3008, 0xB0 }, + { IMX_8BIT, 0x320A, 0x01 }, + { IMX_8BIT, 0x320D, 0x10 }, + { IMX_8BIT, 0x3216, 0x2E }, + { IMX_8BIT, 0x322C, 0x02 }, + { IMX_8BIT, 0x3409, 0x0C }, + { IMX_8BIT, 0x340C, 0x2D }, + { IMX_8BIT, 0x3411, 0x39 }, + { IMX_8BIT, 0x3414, 0x1E }, + { IMX_8BIT, 0x3427, 0x04 }, + { IMX_8BIT, 0x3480, 0x1E }, + { IMX_8BIT, 0x3484, 0x1E }, + { IMX_8BIT, 0x3488, 0x1E }, + { IMX_8BIT, 0x348C, 0x1E }, + { IMX_8BIT, 0x3490, 0x1E }, + { IMX_8BIT, 0x3494, 0x1E }, + { IMX_8BIT, 0x3511, 0x8F }, + { IMX_8BIT, 0x3617, 0x2D }, + + GROUPED_PARAMETER_HOLD_DISABLE, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 3280x2464 8M 30fps, vendor provide */ +static struct imx_reg const imx134_8M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* clock setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0345, 0x00 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3279 */ + { IMX_8BIT, 0x0349, 0xCF }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0x9F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x0C }, /* x_output_size[15:8]: 3280*/ + { IMX_8BIT, 0x034D, 0xD0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x09 }, /* y_output_size[15:8]:2464 */ + { IMX_8BIT, 0x034F, 0xA0 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0C }, + { IMX_8BIT, 0x0355, 0xD0 }, + { IMX_8BIT, 0x0356, 0x09 }, + { IMX_8BIT, 0x0357, 0xA0 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x0C }, + { IMX_8BIT, 0x3311, 0xD0 }, + { IMX_8BIT, 0x3312, 0x09 }, + { IMX_8BIT, 0x3313, 0xA0 }, + { IMX_8BIT, 0x331C, 0x01 }, + { IMX_8BIT, 0x331D, 0xAE }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global timing setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration time setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/2 binning 30fps 1640x1232, vendor provide */ +static struct imx_reg const imx134_1640_1232_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0345, 0x00 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3279 */ + { IMX_8BIT, 0x0349, 0xCF }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0x9F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x06 }, /* x_output_size[15:8]:1640 */ + { IMX_8BIT, 0x034D, 0x68 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x04 }, /* y_output_size[15:8]:1232 */ + { IMX_8BIT, 0x034F, 0xD0 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x68 }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0xD0 }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x68 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0xD0 }, + + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x06 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/4 binning 30fps 820x616, vendor provide */ +static struct imx_reg const imx134_820_616_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x44 }, /* 4x4 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0345, 0x00 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3279 */ + { IMX_8BIT, 0x0349, 0xCF }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0x9F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x03 }, /* x_output_size[15:8]:820 */ + { IMX_8BIT, 0x034D, 0x34 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:616 */ + { IMX_8BIT, 0x034F, 0x68 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x03 }, + { IMX_8BIT, 0x0355, 0x34 }, + { IMX_8BIT, 0x0356, 0x02 }, + { IMX_8BIT, 0x0357, 0x68 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x03 }, + { IMX_8BIT, 0x3311, 0x34 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x68 }, + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/4 binning 30fps 820x552 */ +static struct imx_reg const imx134_820_552_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x44 }, /* 4x4 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0345, 0x00 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:128 */ + { IMX_8BIT, 0x0347, 0x80 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3280-1 */ + { IMX_8BIT, 0x0349, 0xCF }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2208+128-1 */ + { IMX_8BIT, 0x034B, 0x1F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x03 }, /* x_output_size[15:8]: */ + { IMX_8BIT, 0x034D, 0x34 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:616 */ + { IMX_8BIT, 0x034F, 0x28 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x03 }, + { IMX_8BIT, 0x0355, 0x34 }, + { IMX_8BIT, 0x0356, 0x02 }, + { IMX_8BIT, 0x0357, 0x28 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x03 }, + { IMX_8BIT, 0x3311, 0x34 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x28 }, + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/4 binning 30fps 720x592 */ +static struct imx_reg const imx134_720_592_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x44 }, /* 4x4 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:200 */ + { IMX_8BIT, 0x0345, 0xC8 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:40 */ + { IMX_8BIT, 0x0347, 0x28 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:2880+200-1 */ + { IMX_8BIT, 0x0349, 0x07 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2368+40-1 */ + { IMX_8BIT, 0x034B, 0x67 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x02 }, /* x_output_size[15:8]: */ + { IMX_8BIT, 0x034D, 0xD0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:616 */ + { IMX_8BIT, 0x034F, 0x50 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x02 }, + { IMX_8BIT, 0x0355, 0xD0 }, + { IMX_8BIT, 0x0356, 0x02 }, + { IMX_8BIT, 0x0357, 0x50 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x02 }, + { IMX_8BIT, 0x3311, 0xD0 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x50 }, + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +static struct imx_reg const imx134_752_616_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x44 }, /* 4x4 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:136 */ + { IMX_8BIT, 0x0345, 0x88 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3145+134-1 */ + { IMX_8BIT, 0x0349, 0x47 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0x9F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x02 }, /* x_output_size[15:8]: 752*/ + { IMX_8BIT, 0x034D, 0xF0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:616 */ + { IMX_8BIT, 0x034F, 0x68 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + + { IMX_8BIT, 0x0354, 0x02 }, + { IMX_8BIT, 0x0355, 0xF0 }, + { IMX_8BIT, 0x0356, 0x02 }, + { IMX_8BIT, 0x0357, 0x68 }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x02 }, + { IMX_8BIT, 0x3311, 0xF0 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x68 }, + + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 1424x1168 */ +static struct imx_reg const imx134_1424_1168_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* binning */ + { IMX_8BIT, 0x0391, 0x11 }, /* no binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x22 }, /* 34/16=2.125 */ + { IMX_8BIT, 0x4082, 0x00 }, /* ?? */ + { IMX_8BIT, 0x4083, 0x00 }, /* ?? */ + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:136 */ + { IMX_8BIT, 0x0345, 0x80 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3145+134-1 */ + { IMX_8BIT, 0x0349, 0x51 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0xB1 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x05 }, /* x_output_size[15:8]: 1424*/ + { IMX_8BIT, 0x034D, 0x90 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x04 }, /* y_output_size[15:8]:1168 */ + { IMX_8BIT, 0x034F, 0x90 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + + { IMX_8BIT, 0x0354, 0x0B }, + { IMX_8BIT, 0x0355, 0xD2 }, + { IMX_8BIT, 0x0356, 0x09 }, + { IMX_8BIT, 0x0357, 0xB2 }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x05 }, + { IMX_8BIT, 0x3311, 0x90 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x90 }, + + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x05 }, + { IMX_8BIT, 0x4085, 0x90 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x90 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/4 binning, 16/35 down scaling, 30fps, dvs */ +static struct imx_reg const imx134_240_196_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /*4x4 binning */ + { IMX_8BIT, 0x0391, 0x44 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x23 }, /* down scaling = 16/35 */ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x02 }, /* x_addr_start[15:8]:590 */ + { IMX_8BIT, 0x0345, 0x4E }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:366 */ + { IMX_8BIT, 0x0347, 0x6E }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0A }, /* x_addr_end[15:8]:2104+590-1 */ + { IMX_8BIT, 0x0349, 0x85 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:1720+366-1 */ + { IMX_8BIT, 0x034B, 0x25 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x00 }, /* x_output_size[15:8]: 240*/ + { IMX_8BIT, 0x034D, 0xF0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x00 }, /* y_output_size[15:8]:196 */ + { IMX_8BIT, 0x034F, 0xC4 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x02 }, /* crop_x: 526 */ + { IMX_8BIT, 0x0355, 0x0E }, + { IMX_8BIT, 0x0356, 0x01 }, /* crop_y: 430 */ + { IMX_8BIT, 0x0357, 0xAE }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x00 }, + { IMX_8BIT, 0x3311, 0xF0 }, + { IMX_8BIT, 0x3312, 0x00 }, + { IMX_8BIT, 0x3313, 0xC4 }, + + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x4C }, + + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0xF0 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0xC4 }, + + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x0A }, + { IMX_8BIT, 0x0203, 0x88 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/2 binning, 16/38 downscaling, 30fps, dvs */ +static struct imx_reg const imx134_448_366_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* 2x2 binning */ + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x26 }, /* down scaling = 16/38 */ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x02 }, /* x_addr_start[15:8]:590 */ + { IMX_8BIT, 0x0345, 0x4E }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:366 */ + { IMX_8BIT, 0x0347, 0x6E }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0A }, /* x_addr_end[15:8]:2128+590-1 */ + { IMX_8BIT, 0x0349, 0x9D }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:1740+366-1 */ + { IMX_8BIT, 0x034B, 0x39 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x01 }, /* x_output_size[15:8]: 448*/ + { IMX_8BIT, 0x034D, 0xC0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x01 }, /* y_output_size[15:8]:366 */ + { IMX_8BIT, 0x034F, 0x6E }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x04 }, /* crop_x: 1064 */ + { IMX_8BIT, 0x0355, 0x28 }, + { IMX_8BIT, 0x0356, 0x03 }, /* crop_y: 870 */ + { IMX_8BIT, 0x0357, 0x66 }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x01 }, + { IMX_8BIT, 0x3311, 0xC0 }, + { IMX_8BIT, 0x3312, 0x01 }, + { IMX_8BIT, 0x3313, 0x6E }, + + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + + { IMX_8BIT, 0x4084, 0x01 }, + { IMX_8BIT, 0x4085, 0xC0 }, + { IMX_8BIT, 0x4086, 0x01 }, + { IMX_8BIT, 0x4087, 0x6E }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 2336x1312, 30fps, for 1080p dvs, vendor provide */ +static struct imx_reg const imx134_2336_1312_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* disable binning */ + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x16 }, /* down scaling = 16/22 = 8/11 */ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:34 */ + { IMX_8BIT, 0x0345, 0x22 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:332 */ + { IMX_8BIT, 0x0347, 0x4C }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3245 */ + { IMX_8BIT, 0x0349, 0xAD }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2135 */ + { IMX_8BIT, 0x034B, 0x57 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x09 }, /* x_output_size[15:8]:2336 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x05 }, /* y_output_size[15:8]:1312 */ + { IMX_8BIT, 0x034F, 0x20 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0C }, + { IMX_8BIT, 0x0355, 0x8C }, + { IMX_8BIT, 0x0356, 0x07 }, + { IMX_8BIT, 0x0357, 0x0C }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x09 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x05 }, + { IMX_8BIT, 0x3313, 0x20 }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xEB }, + { IMX_8BIT, 0x4084, 0x09 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x05 }, + { IMX_8BIT, 0x4087, 0x20 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 1920x1080, 30fps, for 720p still capture */ +static struct imx_reg const imx134_1936_1096_30fps_v1[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* disable binning */ + { IMX_8BIT, 0x0391, 0x11 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1A }, /* downscaling 16/26*/ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:64 */ + { IMX_8BIT, 0x0345, 0x40 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:340 */ + { IMX_8BIT, 0x0347, 0x54 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3209 */ + { IMX_8BIT, 0x0349, 0x89 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2121 */ + { IMX_8BIT, 0x034B, 0x49 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x07 }, /* x_output_size[15:8]:1936 */ + { IMX_8BIT, 0x034D, 0x90 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x04 }, /* y_output_size[15:8]:1096 */ + { IMX_8BIT, 0x034F, 0x48 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0C }, /* crop x:3146 */ + { IMX_8BIT, 0x0355, 0x4A }, + { IMX_8BIT, 0x0356, 0x06 }, /* xrop y:1782 */ + { IMX_8BIT, 0x0357, 0xF6 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x07 }, + { IMX_8BIT, 0x3311, 0x80 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x38 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x1E }, + { IMX_8BIT, 0x4084, 0x07 }, + { IMX_8BIT, 0x4085, 0x80 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x38 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 1920x1080, 30fps, for 720p still capture, vendor provide */ +static struct imx_reg const imx134_1936_1096_30fps_v2[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* disable binning */ + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1B }, /* downscaling 16/27*/ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:64 */ + { IMX_8BIT, 0x0345, 0x06 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:340 */ + { IMX_8BIT, 0x0347, 0x34 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3209 */ + { IMX_8BIT, 0x0349, 0xC9 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2121 */ + { IMX_8BIT, 0x034B, 0x6F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x07 }, /* x_output_size[15:8]:1936 */ + { IMX_8BIT, 0x034D, 0x90 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x04 }, /* y_output_size[15:8]:1096 */ + { IMX_8BIT, 0x034F, 0x48 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0C }, /* crop x:3146 */ + { IMX_8BIT, 0x0355, 0xC4 }, + { IMX_8BIT, 0x0356, 0x07 }, /* xrop y:1782 */ + { IMX_8BIT, 0x0357, 0x3A }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x07 }, /* decide by mode and output size */ + { IMX_8BIT, 0x3311, 0x90 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x48 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x1E }, + { IMX_8BIT, 0x4084, 0x07 }, + { IMX_8BIT, 0x4085, 0x90 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x48 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 1296x736, 30fps, for 720p still capture, vendor provide */ +static struct imx_reg const imx134_1296_736_30fps_v2[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x14 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:40 */ + { IMX_8BIT, 0x0345, 0x14 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:332 */ + { IMX_8BIT, 0x0347, 0x38 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3239 */ + { IMX_8BIT, 0x0349, 0xBB }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2131 */ + { IMX_8BIT, 0x034B, 0x67 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x05 }, /* x_output_size[15:8]:1280 */ + { IMX_8BIT, 0x034D, 0x10 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:720 */ + { IMX_8BIT, 0x034F, 0xE0 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x54 }, + { IMX_8BIT, 0x0356, 0x03 }, + { IMX_8BIT, 0x0357, 0x98 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x05 }, + { IMX_8BIT, 0x3311, 0x10 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0xE0 }, + { IMX_8BIT, 0x331C, 0x01 }, + { IMX_8BIT, 0x331D, 0x10 }, + { IMX_8BIT, 0x4084, 0x05 }, + { IMX_8BIT, 0x4085, 0x10 }, + { IMX_8BIT, 0x4086, 0x02 }, + { IMX_8BIT, 0x4087, 0xE0 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 1280x720, 30fps, for 720p dvs, vendor provide */ +static struct imx_reg const imx134_1568_880_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:72 */ + { IMX_8BIT, 0x0345, 0x48 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:356 */ + { IMX_8BIT, 0x0347, 0x64 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3207 */ + { IMX_8BIT, 0x0349, 0x87 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2115 */ + { IMX_8BIT, 0x034B, 0x43 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x06 }, /* x_output_size[15:8]:1568 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x03 }, /* y_output_size[15:8]:880 */ + { IMX_8BIT, 0x034F, 0x70 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x03 }, + { IMX_8BIT, 0x0357, 0x70 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x70 }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xF2 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +static struct imx_reg const imx134_1568_876_60fps_0625[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0x8F }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:72 */ + { IMX_8BIT, 0x0345, 0x48 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:356 */ + { IMX_8BIT, 0x0347, 0x64 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3207 */ + { IMX_8BIT, 0x0349, 0x87 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2115 */ + { IMX_8BIT, 0x034B, 0x3B }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x06 }, /* x_output_size[15:8]:1568 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x03 }, /* y_output_size[15:8]:880 */ + { IMX_8BIT, 0x034F, 0x6C }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x03 }, + { IMX_8BIT, 0x0357, 0x6C }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x6C }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xF2 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x6F }, + { IMX_8BIT, 0x0831, 0x27 }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x2F }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x2F }, + { IMX_8BIT, 0x0836, 0x9F }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + + +/* 4 lane for 720p dvs, vendor provide */ +static struct imx_reg const imx134_1568_880[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xC8 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:72 */ + { IMX_8BIT, 0x0345, 0x48 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:356 */ + { IMX_8BIT, 0x0347, 0x64 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3207 */ + { IMX_8BIT, 0x0349, 0x87 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2115 */ + { IMX_8BIT, 0x034B, 0x43 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x06 }, /* x_output_size[15:8]:1568 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x03 }, /* y_output_size[15:8]:880 */ + { IMX_8BIT, 0x034F, 0x70 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x03 }, + { IMX_8BIT, 0x0357, 0x70 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x70 }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xF2 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x5F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x37 }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xBF }, + { IMX_8BIT, 0x0837, 0x3F }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; +/* 4 lane for 480p dvs, default 60fps, vendor provide */ +static struct imx_reg const imx134_880_592[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xC8 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1D }, /* downscaling ratio = 16/29 */ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:44 */ + { IMX_8BIT, 0x0345, 0x2C }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:160 */ + { IMX_8BIT, 0x0347, 0xA0 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3235 */ + { IMX_8BIT, 0x0349, 0xA3 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2307 */ + { IMX_8BIT, 0x034B, 0x03 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x03 }, /* x_output_size[15:8]:880 */ + { IMX_8BIT, 0x034D, 0x70 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:592 */ + { IMX_8BIT, 0x034F, 0x50 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x3C }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x32 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x03 }, + { IMX_8BIT, 0x3311, 0x70 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x50 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x4C }, + { IMX_8BIT, 0x4084, 0x03 }, + { IMX_8BIT, 0x4085, 0x70 }, + { IMX_8BIT, 0x4086, 0x02 }, + { IMX_8BIT, 0x4087, 0x50 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x5F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x37 }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xBF }, + { IMX_8BIT, 0x0837, 0x3F }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x05 }, + { IMX_8BIT, 0x0203, 0x42 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; +static struct imx_reg const imx134_2336_1308_60fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xC8 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x11 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x01 }, /* x_addr_start[15:8]:72 */ + { IMX_8BIT, 0x0345, 0xD8 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x02 }, /* y_addr_start[15:8]:356 */ + { IMX_8BIT, 0x0347, 0x44 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0A }, /* x_addr_end[15:8]:3207 */ + { IMX_8BIT, 0x0349, 0xF7 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x07 }, /* y_addr_end[15:8]:2107 */ + { IMX_8BIT, 0x034B, 0x5F+4 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x09 }, /* x_output_size[15:8]:1568 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x05 }, /* y_output_size[15:8]:876 */ + { IMX_8BIT, 0x034F, 0x1C+4 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x09 }, + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x05 }, + { IMX_8BIT, 0x0357, 0x1C+4 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x09 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x05 }, + { IMX_8BIT, 0x3313, 0x1C+4 }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xE8 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x5F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x37 }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xBF }, + { IMX_8BIT, 0x0837, 0x3F }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x05 }, + { IMX_8BIT, 0x0203, 0x42 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +struct imx_resolution imx134_res_preview[] = { + { + .desc = "imx134_CIF_30fps", + .regs = imx134_720_592_30fps, + .width = 720, + .height = 592, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_820_552_30fps_preview", + .regs = imx134_820_552_30fps, + .width = 820, + .height = 552, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_820_616_preview_30fps", + .regs = imx134_820_616_30fps, + .width = 820, + .height = 616, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_1080p_preview_30fps", + .regs = imx134_1936_1096_30fps_v2, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, + { + .desc = "imx134_1640_1232_preview_30fps", + .regs = imx134_1640_1232_30fps, + .width = 1640, + .height = 1232, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_8M_preview_30fps", + .regs = imx134_8M_30fps, + .width = 3280, + .height = 2464, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, +}; + +struct imx_resolution imx134_res_still[] = { + { + .desc = "imx134_CIF_30fps", + .regs = imx134_1424_1168_30fps, + .width = 1424, + .height = 1168, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_VGA_still_30fps", + .regs = imx134_1640_1232_30fps, + .width = 1640, + .height = 1232, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_1080p_still_30fps", + .regs = imx134_1936_1096_30fps_v2, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, + { + .desc = "imx134_1640_1232_still_30fps", + .regs = imx134_1640_1232_30fps, + .width = 1640, + .height = 1232, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_8M_still_30fps", + .regs = imx134_8M_30fps, + .width = 3280, + .height = 2464, + .fps_options = { + { + /* WORKAROUND for FW performance limitation */ + .fps = 8, + .pixels_per_line = 6400, + .lines_per_frame = 5312, + }, + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, +}; + +struct imx_resolution imx134_res_video[] = { + { + .desc = "imx134_QCIF_DVS_30fps", + .regs = imx134_240_196_30fps, + .width = 240, + .height = 196, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_CIF_DVS_30fps", + .regs = imx134_448_366_30fps, + .width = 448, + .height = 366, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_VGA_30fps", + .regs = imx134_820_616_30fps, + .width = 820, + .height = 616, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_480p", + .regs = imx134_880_592, + .width = 880, + .height = 592, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2700, + }, + { + .fps = 60, + .pixels_per_line = 3600, + .lines_per_frame = 1350, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_1568_880", + .regs = imx134_1568_880, + .width = 1568, + .height = 880, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2700, + }, + { + .fps = 60, + .pixels_per_line = 3600, + .lines_per_frame = 1350, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_1080p_dvs_30fps", + .regs = imx134_2336_1312_30fps, + .width = 2336, + .height = 1312, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, + { + .desc = "imx134_1080p_dvs_60fps", + .regs = imx134_2336_1308_60fps, + .width = 2336, + .height = 1312, + .fps_options = { + { + .fps = 60, + .pixels_per_line = 3600, + .lines_per_frame = 1350, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, + { + /*This setting only be used for SDV mode*/ + .desc = "imx134_8M_sdv_30fps", + .regs = imx134_8M_30fps, + .width = 3280, + .height = 2464, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, +}; + +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx135.h b/drivers/staging/media/atomisp/i2c/imx/imx135.h new file mode 100644 index 0000000..58b43af --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx135.h @@ -0,0 +1,3374 @@ +/* + * Support for Sony IMX camera sensor. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __IMX135_H__ +#define __IMX135_H__ + +#include "common.h" + +#define IMX_SC_CMMN_CHIP_ID_H 0x0016 +#define IMX_SC_CMMN_CHIP_ID_L 0x0017 + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define IMX_FOCAL_LENGTH_DEFAULT 0x1710064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define IMX_F_NUMBER_DEFAULT 0x16000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define IMX_F_NUMBER_RANGE 0x160a160a + +#define GROUPED_PARAMETER_HOLD_ENABLE {IMX_8BIT, 0x0104, 0x1} +#define GROUPED_PARAMETER_HOLD_DISABLE {IMX_8BIT, 0x0104, 0x0} + +#define IMX135_EMBEDDED_DATA_LINE_NUM 2 +#define IMX135_OUTPUT_DATA_FORMAT_REG 0x0112 +#define IMX135_OUTPUT_FORMAT_RAW10 0x0a0a +/* + * We use three different MIPI rates for our modes based on the resolution and + * FPS requirements. So we have three PLL configurationa and these are based + * on the EMC friendly MIPI values. + * + * Maximum clock: Pix clock @ 360.96MHz MIPI @ 451.2MHz 902.4mbps + * Reduced clock: Pix clock @ 273.00MHz MIPI @ 342.0MHz 684.0mbps + * Binning modes: Pix clock @ 335.36MHz MIPI @ 209.6MHz 419.2mbps + * Global Timing registers are based on the data rates and these are part of + * the below clock definitions. + */ +/* MIPI 499.2MHz 998.4mbps PIXCLK: 399.36MHz */ +#define PLL_SETTINGS_FOR_MIPI_499_2MHZ_SALTBAY \ + {IMX_8BIT, 0x011e, 0x13}, \ + {IMX_8BIT, 0x011f, 0x33}, \ + {IMX_8BIT, 0x0301, 0x05}, \ + {IMX_8BIT, 0x0303, 0x01}, \ + {IMX_8BIT, 0x0305, 0x0c}, \ + {IMX_8BIT, 0x0309, 0x05}, \ + {IMX_8BIT, 0x030b, 0x01}, \ + {IMX_8BIT, 0x030c, 0x02}, \ + {IMX_8BIT, 0x030d, 0x70}, \ + {IMX_8BIT, 0x030e, 0x01}, \ + {IMX_8BIT, 0x3a06, 0x11}, \ + {IMX_8BIT, 0x0830, 0x7f}, \ + {IMX_8BIT, 0x0831, 0x37}, \ + {IMX_8BIT, 0x0832, 0x67}, \ + {IMX_8BIT, 0x0833, 0x3f}, \ + {IMX_8BIT, 0x0834, 0x3f}, \ + {IMX_8BIT, 0x0835, 0x47}, \ + {IMX_8BIT, 0x0836, 0xdf}, \ + {IMX_8BIT, 0x0837, 0x47}, \ + {IMX_8BIT, 0x0839, 0x1f}, \ + {IMX_8BIT, 0x083a, 0x17}, \ + {IMX_8BIT, 0x083b, 0x02} + +/* MIPI 451.2MHz 902.4mbps PIXCLK: 360.96MHz */ +#define PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY \ + {IMX_8BIT, 0x011e, 0x13}, \ + {IMX_8BIT, 0x011f, 0x33}, \ + {IMX_8BIT, 0x0301, 0x05}, \ + {IMX_8BIT, 0x0303, 0x01}, \ + {IMX_8BIT, 0x0305, 0x0c}, \ + {IMX_8BIT, 0x0309, 0x05}, \ + {IMX_8BIT, 0x030b, 0x01}, \ + {IMX_8BIT, 0x030c, 0x02}, \ + {IMX_8BIT, 0x030d, 0x34}, \ + {IMX_8BIT, 0x030e, 0x01}, \ + {IMX_8BIT, 0x3a06, 0x11}, \ + {IMX_8BIT, 0x0830, 0x7f}, \ + {IMX_8BIT, 0x0831, 0x37}, \ + {IMX_8BIT, 0x0832, 0x67}, \ + {IMX_8BIT, 0x0833, 0x3f}, \ + {IMX_8BIT, 0x0834, 0x3f}, \ + {IMX_8BIT, 0x0835, 0x47}, \ + {IMX_8BIT, 0x0836, 0xdf}, \ + {IMX_8BIT, 0x0837, 0x47}, \ + {IMX_8BIT, 0x0839, 0x1f}, \ + {IMX_8BIT, 0x083a, 0x17}, \ + {IMX_8BIT, 0x083b, 0x02} + +/* MIPI 209.6MHz, 419.2mbps PIXCLK: 335.36 MHz */ +#define PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY \ + {IMX_8BIT, 0x011e, 0x13}, \ + {IMX_8BIT, 0x011f, 0x33}, \ + {IMX_8BIT, 0x0301, 0x05}, \ + {IMX_8BIT, 0x0303, 0x01}, \ + {IMX_8BIT, 0x0305, 0x06}, \ + {IMX_8BIT, 0x0309, 0x05}, \ + {IMX_8BIT, 0x030b, 0x02}, \ + {IMX_8BIT, 0x030c, 0x01}, \ + {IMX_8BIT, 0x030d, 0x06}, \ + {IMX_8BIT, 0x030e, 0x01}, \ + {IMX_8BIT, 0x3a06, 0x12}, \ + {IMX_8BIT, 0x0830, 0x5f}, \ + {IMX_8BIT, 0x0831, 0x1f}, \ + {IMX_8BIT, 0x0832, 0x3f}, \ + {IMX_8BIT, 0x0833, 0x1f}, \ + {IMX_8BIT, 0x0834, 0x1f}, \ + {IMX_8BIT, 0x0835, 0x17}, \ + {IMX_8BIT, 0x0836, 0x67}, \ + {IMX_8BIT, 0x0837, 0x27}, \ + {IMX_8BIT, 0x0839, 0x1f}, \ + {IMX_8BIT, 0x083a, 0x17}, \ + {IMX_8BIT, 0x083b, 0x02} + +/* MIPI 342MHz 684mbps PIXCLK: 273.6MHz */ +#define PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY \ + {IMX_8BIT, 0x011e, 0x13}, \ + {IMX_8BIT, 0x011f, 0x33}, \ + {IMX_8BIT, 0x0301, 0x05}, \ + {IMX_8BIT, 0x0303, 0x01}, \ + {IMX_8BIT, 0x0305, 0x08}, \ + {IMX_8BIT, 0x0309, 0x05}, \ + {IMX_8BIT, 0x030b, 0x01}, \ + {IMX_8BIT, 0x030c, 0x01}, \ + {IMX_8BIT, 0x030d, 0x1d}, \ + {IMX_8BIT, 0x030e, 0x01}, \ + {IMX_8BIT, 0x3a06, 0x11}, \ + {IMX_8BIT, 0x0830, 0x77}, \ + {IMX_8BIT, 0x0831, 0x2f}, \ + {IMX_8BIT, 0x0832, 0x4f}, \ + {IMX_8BIT, 0x0833, 0x37}, \ + {IMX_8BIT, 0x0834, 0x2f}, \ + {IMX_8BIT, 0x0835, 0x37}, \ + {IMX_8BIT, 0x0836, 0xa7}, \ + {IMX_8BIT, 0x0837, 0x37}, \ + {IMX_8BIT, 0x0839, 0x1f}, \ + {IMX_8BIT, 0x083a, 0x17}, \ + {IMX_8BIT, 0x083b, 0x02} + +/* Basic settings: Applied only once after the sensor power up */ +static struct imx_reg const imx135_init_settings[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + { IMX_8BIT, 0x0220, 0x01}, + { IMX_8BIT, 0x3008, 0xB0}, + { IMX_8BIT, 0x320A, 0x01}, + { IMX_8BIT, 0x320D, 0x10}, + { IMX_8BIT, 0x3216, 0x2E}, + { IMX_8BIT, 0x3230, 0x0A}, + { IMX_8BIT, 0x3228, 0x05}, + { IMX_8BIT, 0x3229, 0x02}, + { IMX_8BIT, 0x322C, 0x02}, + { IMX_8BIT, 0x3302, 0x10}, + { IMX_8BIT, 0x3390, 0x45}, + { IMX_8BIT, 0x3409, 0x0C}, + { IMX_8BIT, 0x340B, 0xF5}, + { IMX_8BIT, 0x340C, 0x2D}, + { IMX_8BIT, 0x3412, 0x41}, + { IMX_8BIT, 0x3413, 0xAD}, + { IMX_8BIT, 0x3414, 0x1E}, + { IMX_8BIT, 0x3427, 0x04}, + { IMX_8BIT, 0x3480, 0x1E}, + { IMX_8BIT, 0x3484, 0x1E}, + { IMX_8BIT, 0x3488, 0x1E}, + { IMX_8BIT, 0x348C, 0x1E}, + { IMX_8BIT, 0x3490, 0x1E}, + { IMX_8BIT, 0x3494, 0x1E}, + { IMX_8BIT, 0x349C, 0x38}, + { IMX_8BIT, 0x34A3, 0x38}, + { IMX_8BIT, 0x3511, 0x8F}, + { IMX_8BIT, 0x3518, 0x00}, + { IMX_8BIT, 0x3519, 0x94}, + { IMX_8BIT, 0x3833, 0x20}, + { IMX_8BIT, 0x3893, 0x01}, + { IMX_8BIT, 0x38C2, 0x08}, + { IMX_8BIT, 0x38C3, 0x08}, + { IMX_8BIT, 0x3C09, 0x01}, + { IMX_8BIT, 0x4000, 0x0E}, + { IMX_8BIT, 0x4300, 0x00}, + { IMX_8BIT, 0x4316, 0x12}, + { IMX_8BIT, 0x4317, 0x22}, + { IMX_8BIT, 0x4318, 0x00}, + { IMX_8BIT, 0x4319, 0x00}, + { IMX_8BIT, 0x431A, 0x00}, + { IMX_8BIT, 0x4324, 0x03}, + { IMX_8BIT, 0x4325, 0x20}, + { IMX_8BIT, 0x4326, 0x03}, + { IMX_8BIT, 0x4327, 0x84}, + { IMX_8BIT, 0x4328, 0x03}, + { IMX_8BIT, 0x4329, 0x20}, + { IMX_8BIT, 0x432A, 0x03}, + { IMX_8BIT, 0x432B, 0x84}, + { IMX_8BIT, 0x432C, 0x01}, + { IMX_8BIT, 0x4401, 0x3F}, + { IMX_8BIT, 0x4402, 0xFF}, + { IMX_8BIT, 0x4412, 0x3F}, + { IMX_8BIT, 0x4413, 0xFF}, + { IMX_8BIT, 0x441D, 0x28}, + { IMX_8BIT, 0x4444, 0x00}, + { IMX_8BIT, 0x4445, 0x00}, + { IMX_8BIT, 0x4446, 0x3F}, + { IMX_8BIT, 0x4447, 0xFF}, + { IMX_8BIT, 0x4452, 0x00}, + { IMX_8BIT, 0x4453, 0xA0}, + { IMX_8BIT, 0x4454, 0x08}, + { IMX_8BIT, 0x4455, 0x00}, + { IMX_8BIT, 0x4458, 0x18}, + { IMX_8BIT, 0x4459, 0x18}, + { IMX_8BIT, 0x445A, 0x3F}, + { IMX_8BIT, 0x445B, 0x3A}, + { IMX_8BIT, 0x4462, 0x00}, + { IMX_8BIT, 0x4463, 0x00}, + { IMX_8BIT, 0x4464, 0x00}, + { IMX_8BIT, 0x4465, 0x00}, + { IMX_8BIT, 0x446E, 0x01}, + { IMX_8BIT, 0x4500, 0x1F}, + { IMX_8BIT, 0x600a, 0x00}, + { IMX_8BIT, 0x380a, 0x00}, + { IMX_8BIT, 0x380b, 0x00}, + { IMX_8BIT, 0x4103, 0x00}, + { IMX_8BIT, 0x4243, 0x9a}, + { IMX_8BIT, 0x4330, 0x01}, + { IMX_8BIT, 0x4331, 0x90}, + { IMX_8BIT, 0x4332, 0x02}, + { IMX_8BIT, 0x4333, 0x58}, + { IMX_8BIT, 0x4334, 0x03}, + { IMX_8BIT, 0x4335, 0x20}, + { IMX_8BIT, 0x4336, 0x03}, + { IMX_8BIT, 0x4337, 0x84}, + { IMX_8BIT, 0x433C, 0x01}, + { IMX_8BIT, 0x4340, 0x02}, + { IMX_8BIT, 0x4341, 0x58}, + { IMX_8BIT, 0x4342, 0x03}, + { IMX_8BIT, 0x4343, 0x52}, + { IMX_8BIT, 0x4364, 0x0b}, + { IMX_8BIT, 0x4368, 0x00}, + { IMX_8BIT, 0x4369, 0x0f}, + { IMX_8BIT, 0x436a, 0x03}, + { IMX_8BIT, 0x436b, 0xa8}, + { IMX_8BIT, 0x436c, 0x00}, + { IMX_8BIT, 0x436d, 0x00}, + { IMX_8BIT, 0x436e, 0x00}, + { IMX_8BIT, 0x436f, 0x06}, + { IMX_8BIT, 0x4281, 0x21}, + { IMX_8BIT, 0x4282, 0x18}, + { IMX_8BIT, 0x4283, 0x04}, + { IMX_8BIT, 0x4284, 0x08}, + { IMX_8BIT, 0x4287, 0x7f}, + { IMX_8BIT, 0x4288, 0x08}, + { IMX_8BIT, 0x428c, 0x08}, + { IMX_8BIT, 0x4297, 0x00}, + { IMX_8BIT, 0x4299, 0x7E}, + { IMX_8BIT, 0x42A4, 0xFB}, + { IMX_8BIT, 0x42A5, 0x7E}, + { IMX_8BIT, 0x42A6, 0xDF}, + { IMX_8BIT, 0x42A7, 0xB7}, + { IMX_8BIT, 0x42AF, 0x03}, + { IMX_8BIT, 0x4207, 0x03}, + { IMX_8BIT, 0x4218, 0x00}, + { IMX_8BIT, 0x421B, 0x20}, + { IMX_8BIT, 0x421F, 0x04}, + { IMX_8BIT, 0x4222, 0x02}, + { IMX_8BIT, 0x4223, 0x22}, + { IMX_8BIT, 0x422E, 0x54}, + { IMX_8BIT, 0x422F, 0xFB}, + { IMX_8BIT, 0x4230, 0xFF}, + { IMX_8BIT, 0x4231, 0xFE}, + { IMX_8BIT, 0x4232, 0xFF}, + { IMX_8BIT, 0x4235, 0x58}, + { IMX_8BIT, 0x4236, 0xF7}, + { IMX_8BIT, 0x4237, 0xFD}, + { IMX_8BIT, 0x4239, 0x4E}, + { IMX_8BIT, 0x423A, 0xFC}, + { IMX_8BIT, 0x423B, 0xFD}, + { IMX_8BIT, 0x4300, 0x00}, + { IMX_8BIT, 0x4316, 0x12}, + { IMX_8BIT, 0x4317, 0x22}, + { IMX_8BIT, 0x4318, 0x00}, + { IMX_8BIT, 0x4319, 0x00}, + { IMX_8BIT, 0x431A, 0x00}, + { IMX_8BIT, 0x4324, 0x03}, + { IMX_8BIT, 0x4325, 0x20}, + { IMX_8BIT, 0x4326, 0x03}, + { IMX_8BIT, 0x4327, 0x84}, + { IMX_8BIT, 0x4328, 0x03}, + { IMX_8BIT, 0x4329, 0x20}, + { IMX_8BIT, 0x432A, 0x03}, + { IMX_8BIT, 0x432B, 0x20}, + { IMX_8BIT, 0x432C, 0x01}, + { IMX_8BIT, 0x432D, 0x01}, + { IMX_8BIT, 0x4338, 0x02}, + { IMX_8BIT, 0x4339, 0x00}, + { IMX_8BIT, 0x433A, 0x00}, + { IMX_8BIT, 0x433B, 0x02}, + { IMX_8BIT, 0x435A, 0x03}, + { IMX_8BIT, 0x435B, 0x84}, + { IMX_8BIT, 0x435E, 0x01}, + { IMX_8BIT, 0x435F, 0xFF}, + { IMX_8BIT, 0x4360, 0x01}, + { IMX_8BIT, 0x4361, 0xF4}, + { IMX_8BIT, 0x4362, 0x03}, + { IMX_8BIT, 0x4363, 0x84}, + { IMX_8BIT, 0x437B, 0x01}, + { IMX_8BIT, 0x4400, 0x00}, /* STATS off ISP do not support STATS*/ + { IMX_8BIT, 0x4401, 0x3F}, + { IMX_8BIT, 0x4402, 0xFF}, + { IMX_8BIT, 0x4404, 0x13}, + { IMX_8BIT, 0x4405, 0x26}, + { IMX_8BIT, 0x4406, 0x07}, + { IMX_8BIT, 0x4408, 0x20}, + { IMX_8BIT, 0x4409, 0xE5}, + { IMX_8BIT, 0x440A, 0xFB}, + { IMX_8BIT, 0x440C, 0xF6}, + { IMX_8BIT, 0x440D, 0xEA}, + { IMX_8BIT, 0x440E, 0x20}, + { IMX_8BIT, 0x4410, 0x00}, + { IMX_8BIT, 0x4411, 0x00}, + { IMX_8BIT, 0x4412, 0x3F}, + { IMX_8BIT, 0x4413, 0xFF}, + { IMX_8BIT, 0x4414, 0x1F}, + { IMX_8BIT, 0x4415, 0xFF}, + { IMX_8BIT, 0x4416, 0x20}, + { IMX_8BIT, 0x4417, 0x00}, + { IMX_8BIT, 0x4418, 0x1F}, + { IMX_8BIT, 0x4419, 0xFF}, + { IMX_8BIT, 0x441A, 0x20}, + { IMX_8BIT, 0x441B, 0x00}, + { IMX_8BIT, 0x441D, 0x40}, + { IMX_8BIT, 0x441E, 0x1E}, + { IMX_8BIT, 0x441F, 0x38}, + { IMX_8BIT, 0x4420, 0x01}, + { IMX_8BIT, 0x4444, 0x00}, + { IMX_8BIT, 0x4445, 0x00}, + { IMX_8BIT, 0x4446, 0x1D}, + { IMX_8BIT, 0x4447, 0xF9}, + { IMX_8BIT, 0x4452, 0x00}, + { IMX_8BIT, 0x4453, 0xA0}, + { IMX_8BIT, 0x4454, 0x08}, + { IMX_8BIT, 0x4455, 0x00}, + { IMX_8BIT, 0x4456, 0x0F}, + { IMX_8BIT, 0x4457, 0xFF}, + { IMX_8BIT, 0x4458, 0x18}, + { IMX_8BIT, 0x4459, 0x18}, + { IMX_8BIT, 0x445A, 0x3F}, + { IMX_8BIT, 0x445B, 0x3A}, + { IMX_8BIT, 0x445C, 0x00}, + { IMX_8BIT, 0x445D, 0x28}, + { IMX_8BIT, 0x445E, 0x01}, + { IMX_8BIT, 0x445F, 0x90}, + { IMX_8BIT, 0x4460, 0x00}, + { IMX_8BIT, 0x4461, 0x60}, + { IMX_8BIT, 0x4462, 0x00}, + { IMX_8BIT, 0x4463, 0x00}, + { IMX_8BIT, 0x4464, 0x00}, + { IMX_8BIT, 0x4465, 0x00}, + { IMX_8BIT, 0x446C, 0x00}, + { IMX_8BIT, 0x446D, 0x00}, + { IMX_8BIT, 0x446E, 0x00}, + { IMX_8BIT, 0x452A, 0x02}, + { IMX_8BIT, 0x0712, 0x01}, + { IMX_8BIT, 0x0713, 0x00}, + { IMX_8BIT, 0x0714, 0x01}, + { IMX_8BIT, 0x0715, 0x00}, + { IMX_8BIT, 0x0716, 0x01}, + { IMX_8BIT, 0x0717, 0x00}, + { IMX_8BIT, 0x0718, 0x01}, + { IMX_8BIT, 0x0719, 0x00}, + { IMX_8BIT, 0x4500, 0x1F }, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + { IMX_8BIT, 0x0205, 0x00}, + { IMX_8BIT, 0x020E, 0x01}, + { IMX_8BIT, 0x020F, 0x00}, + { IMX_8BIT, 0x0210, 0x02}, + { IMX_8BIT, 0x0211, 0x00}, + { IMX_8BIT, 0x0212, 0x02}, + { IMX_8BIT, 0x0213, 0x00}, + { IMX_8BIT, 0x0214, 0x01}, + { IMX_8BIT, 0x0215, 0x00}, + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00}, + { IMX_8BIT, 0x0231, 0x00}, + { IMX_8BIT, 0x0233, 0x00}, + { IMX_8BIT, 0x0234, 0x00}, + { IMX_8BIT, 0x0235, 0x40}, + { IMX_8BIT, 0x0238, 0x00}, + { IMX_8BIT, 0x0239, 0x04}, + { IMX_8BIT, 0x023B, 0x00}, + { IMX_8BIT, 0x023C, 0x01}, + { IMX_8BIT, 0x33B0, 0x04}, + { IMX_8BIT, 0x33B1, 0x00}, + { IMX_8BIT, 0x33B3, 0x00}, + { IMX_8BIT, 0x33B4, 0x01}, + { IMX_8BIT, 0x3800, 0x00}, + GROUPED_PARAMETER_HOLD_DISABLE, + { IMX_TOK_TERM, 0, 0} +}; + +/********* Preview, continuous capture and still modes *****************/ + +static struct imx_reg const imx135_13m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size Setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 0, 0, 4207,3119 4208x3120 */ + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x00}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x6F}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x2F}, + {IMX_8BIT, 0x034C, 0x10}, + {IMX_8BIT, 0x034D, 0x70}, + {IMX_8BIT, 0x034E, 0x0C}, + {IMX_8BIT, 0x034F, 0x30}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* 4208x3120 */ + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x0C}, + {IMX_8BIT, 0x0357, 0x30}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x10}, + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x0C}, + {IMX_8BIT, 0x3313, 0x30}, + {IMX_8BIT, 0x331C, 0x00}, + {IMX_8BIT, 0x331D, 0x10}, + {IMX_8BIT, 0x4084, 0x00}, /* If scaling, Fill this */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +/* 13MP reduced pixel clock MIPI 342MHz is EMC friendly*/ +static struct imx_reg const imx135_13m_for_mipi_342[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size Setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x00}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x6F}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x2F}, + {IMX_8BIT, 0x034C, 0x10}, + {IMX_8BIT, 0x034D, 0x70}, + {IMX_8BIT, 0x034E, 0x0C}, + {IMX_8BIT, 0x034F, 0x30}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x0C}, + {IMX_8BIT, 0x0357, 0x30}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x10}, + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x0C}, + {IMX_8BIT, 0x3313, 0x30}, + {IMX_8BIT, 0x331C, 0x00}, + {IMX_8BIT, 0x331D, 0x10}, + {IMX_8BIT, 0x4084, 0x00}, /* If scaling, Fill this */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_10m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 0, 376, 4207, 2743 */ + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x78}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x6f}, + {IMX_8BIT, 0x034A, 0x0a}, + {IMX_8BIT, 0x034B, 0xb7}, + {IMX_8BIT, 0x034C, 0x10}, /* 4208x2368 */ + {IMX_8BIT, 0x034D, 0x70}, + {IMX_8BIT, 0x034E, 0x09}, + {IMX_8BIT, 0x034F, 0x40}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0x40}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x10}, + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0x40}, + {IMX_8BIT, 0x331C, 0x01}, + {IMX_8BIT, 0x331D, 0x68}, + {IMX_8BIT, 0x4084, 0x00}, + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_10m_for_mipi_342[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 0, 376, 4207, 2743 */ + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x78}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x6f}, + {IMX_8BIT, 0x034A, 0x0a}, + {IMX_8BIT, 0x034B, 0xb7}, + {IMX_8BIT, 0x034C, 0x10}, /* 4208x2368 */ + {IMX_8BIT, 0x034D, 0x70}, + {IMX_8BIT, 0x034E, 0x09}, + {IMX_8BIT, 0x034F, 0x40}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0x40}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x10}, + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0x40}, + {IMX_8BIT, 0x331C, 0x01}, + {IMX_8BIT, 0x331D, 0x68}, + {IMX_8BIT, 0x4084, 0x00}, + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 8.5 DS from (3:2)8m cropped setting. + * + * The 8m(3:2) cropped setting is 2992x2448 effective res. + * The ISP effect cropped setting should be 1408x1152 effect res. + * + * Consider ISP 16x16 padding: + * sensor outputs 368x304 + * cropped region is 3128x2584 + */ +static struct imx_reg const imx135_368x304_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, /* no binning */ + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* resize */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x88}, /* 136/16=8.5 */ + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x02}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0x1C}, /* 540 */ + {IMX_8BIT, 0x0346, 0x01}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x0C}, /* 268 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0x53}, /* 3667 */ + {IMX_8BIT, 0x034A, 0x0B}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0x23}, /* 2851 */ + {IMX_8BIT, 0x034C, 0x01}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x70}, /* 368 */ + {IMX_8BIT, 0x034E, 0x01}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0x30}, /* 304 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0C}, /* Cut out siz same as the size after crop */ + {IMX_8BIT, 0x0355, 0x38}, + {IMX_8BIT, 0x0356, 0x0A}, + {IMX_8BIT, 0x0357, 0x18}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x01}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x01}, + {IMX_8BIT, 0x3313, 0x30}, + {IMX_8BIT, 0x331C, 0x02}, /* ?? */ + {IMX_8BIT, 0x331D, 0xD0}, + {IMX_8BIT, 0x4084, 0x01}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x70}, + {IMX_8BIT, 0x4086, 0x01}, + {IMX_8BIT, 0x4087, 0x30}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 1/4 binning from 8m cropped setting. + * + * The 8m cropped setting is 3264x2448 effective res. + * The xga cropped setting should be 816x612 effect res. + * + * Consider ISP 16x16 padding: + * sensor outputs 832x628 + * cropped region is 3328x2512 + */ +static struct imx_reg const imx135_xga_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x44}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, +/* {IMX_8BIT, 0x4203, 0xFF}, */ + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0xB8}, /* 440 */ + {IMX_8BIT, 0x0346, 0x01}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x30}, /* 304 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0xB7}, /* 4207-440=3767 */ + {IMX_8BIT, 0x034A, 0x0A}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0xFF}, /* 3119-304=2815 */ + {IMX_8BIT, 0x034C, 0x03}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x40}, /* 832 */ + {IMX_8BIT, 0x034E, 0x02}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0x74}, /* 628 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x03}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0x40}, + {IMX_8BIT, 0x0356, 0x02}, + {IMX_8BIT, 0x0357, 0x74}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x03}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x40}, + {IMX_8BIT, 0x3312, 0x02}, + {IMX_8BIT, 0x3313, 0x74}, + {IMX_8BIT, 0x331C, 0x02}, /* ?? */ + {IMX_8BIT, 0x331D, 0x21}, + {IMX_8BIT, 0x4084, 0x03}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x40}, + {IMX_8BIT, 0x4086, 0x02}, + {IMX_8BIT, 0x4087, 0x74}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 28/16 DS from (16:9)8m cropped setting. + * + * The 8m(16:9) cropped setting is 3360x1890 effective res. + * - this is larger then the expected 3264x1836 FOV + * + * Consider ISP 16x16 padding: + * sensor outputs 1936x1096 + * cropped region is 3388x1918 + */ +static struct imx_reg const imx135_1936x1096_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, /* no binning */ + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* resize */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x1C}, /* 28/16 */ + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0x9A}, /* 410 */ + {IMX_8BIT, 0x0346, 0x02}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x58}, /* 600 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0xD5}, /* 3797 */ + {IMX_8BIT, 0x034A, 0x09}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0xD5}, /* 2517 */ + {IMX_8BIT, 0x034C, 0x07}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x90}, /* 1936 */ + {IMX_8BIT, 0x034E, 0x04}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0x48}, /* 1096 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0D}, /* Cut out siz same as the size after crop */ + {IMX_8BIT, 0x0355, 0x3C}, + {IMX_8BIT, 0x0356, 0x07}, + {IMX_8BIT, 0x0357, 0x7E}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x07}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x90}, + {IMX_8BIT, 0x3312, 0x04}, + {IMX_8BIT, 0x3313, 0x48}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0xAA}, + {IMX_8BIT, 0x4084, 0x07}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x90}, + {IMX_8BIT, 0x4086, 0x04}, + {IMX_8BIT, 0x4087, 0x48}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 2.125 DS from (3:2)8m cropped setting. + * + * The 8m(3:2) cropped setting is 2992x2448 effective res. + * The ISP effect cropped setting should be 1408x1152 effect res. + * + * Consider ISP 16x16 padding: + * sensor outputs 1424x1168 + * cropped region is 3026x2482 + */ +static struct imx_reg const imx135_1424x1168_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, /* no binning */ + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* resize */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x22}, /* 34/16=2.125 */ + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x02}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0x4E}, /* 590 */ + {IMX_8BIT, 0x0346, 0x01}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x3E}, /* 318 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0x1F}, /* 3615 */ + {IMX_8BIT, 0x034A, 0x0A}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0xEF}, /* 2799 */ + {IMX_8BIT, 0x034C, 0x05}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x90}, /* 1424 */ + {IMX_8BIT, 0x034E, 0x04}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0x90}, /* 1168 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0B}, /* Cut out siz same as the size after crop */ + {IMX_8BIT, 0x0355, 0xD2}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0xB2}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x05}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x90}, + {IMX_8BIT, 0x3312, 0x04}, + {IMX_8BIT, 0x3313, 0x90}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0xAA}, + {IMX_8BIT, 0x4084, 0x05}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x90}, + {IMX_8BIT, 0x4086, 0x04}, + {IMX_8BIT, 0x4087, 0x90}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 1/2 binning from 8m cropped setting. + * + * The 8m cropped setting is 3264x2448 effective res. + * The 2m cropped setting should be 1632x1224 effect res. + * + * Consider ISP 16x16 padding: + * sensor outputs 1648x1240 + * cropped region is 3296x2480 + */ +static struct imx_reg const imx135_2m_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x22}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0xC8}, /* 464(1D0) -> 456(1C8)*/ + {IMX_8BIT, 0x0346, 0x01}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x40}, /* 320 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0xA7}, /* 4207-456=3751 */ + {IMX_8BIT, 0x034A, 0x0A}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0xEF}, /* 3119-320=2799 */ + {IMX_8BIT, 0x034C, 0x06}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x70}, /* 1648 */ + {IMX_8BIT, 0x034E, 0x04}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0xD8}, /* 1240 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x06}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x04}, + {IMX_8BIT, 0x0357, 0xD8}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x06}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x04}, + {IMX_8BIT, 0x3313, 0xD8}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0xAA}, + {IMX_8BIT, 0x4084, 0x00}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * 8M Cropped 16:9 setting + * + * Effect res: 3264x1836 + * Sensor out: 3280x1852 + */ +static struct imx_reg const imx135_6m_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xD0}, + {IMX_8BIT, 0x0346, 0x02}, /* 634 */ + {IMX_8BIT, 0x0347, 0x7A}, + {IMX_8BIT, 0x0348, 0x0E}, + {IMX_8BIT, 0x0349, 0x9F}, + {IMX_8BIT, 0x034A, 0x09}, /* 2485 */ + {IMX_8BIT, 0x034B, 0xB5}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x07}, /* 1852 */ + {IMX_8BIT, 0x034F, 0x3C}, + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0C}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0xD0}, + {IMX_8BIT, 0x0356, 0x07}, + {IMX_8BIT, 0x0357, 0x3C}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x0C}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x07}, + {IMX_8BIT, 0x3313, 0x3C}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0x10}, + {IMX_8BIT, 0x4084, 0x00}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_8m_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xD0}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x48}, + {IMX_8BIT, 0x0348, 0x0E}, + {IMX_8BIT, 0x0349, 0x9F}, + {IMX_8BIT, 0x034A, 0x0A}, + {IMX_8BIT, 0x034B, 0xE7}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x09}, /* 2464 */ + {IMX_8BIT, 0x034F, 0xA0}, + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0C}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0xD0}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0xA0}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x0C}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0xA0}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0x10}, + {IMX_8BIT, 0x4084, 0x00}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_8m_scaled_from_12m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* Scaling */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x14}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x36}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x14}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x39}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x1B}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280x2464 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x09}, + {IMX_8BIT, 0x034F, 0xA0}, + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0x04}, + {IMX_8BIT, 0x0356, 0x0C}, + {IMX_8BIT, 0x0357, 0x08}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x0C}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0xA0}, + {IMX_8BIT, 0x331C, 0x02}, /* ?? */ + {IMX_8BIT, 0x331D, 0xA0}, + {IMX_8BIT, 0x4084, 0x0C}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0xD0}, + {IMX_8BIT, 0x4086, 0x09}, + {IMX_8BIT, 0x4087, 0xA0}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_8m_scaled_from_12m_for_mipi342[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* Scaling */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x14}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x36}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x14}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x39}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x1B}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280x2464 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x09}, + {IMX_8BIT, 0x034F, 0xA0}, + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0x04}, + {IMX_8BIT, 0x0356, 0x0C}, + {IMX_8BIT, 0x0357, 0x08}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x0C}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0xA0}, + {IMX_8BIT, 0x331C, 0x02}, /* ?? */ + {IMX_8BIT, 0x331D, 0xA0}, + {IMX_8BIT, 0x4084, 0x0C}, /* Resize IMG Hand V size-> Scaling related?*/ + {IMX_8BIT, 0x4085, 0xD0}, + {IMX_8BIT, 0x4086, 0x09}, + {IMX_8BIT, 0x4087, 0xA0}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_6m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x14}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 36, 194, 1039, a9f 4100x2316 */ + {IMX_8BIT, 0x0345, 0x36}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x94}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x39}, + {IMX_8BIT, 0x034A, 0x0A}, + {IMX_8BIT, 0x034B, 0x9F}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280x1852 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x07}, + {IMX_8BIT, 0x034F, 0x3C}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* 4100x2316 */ + {IMX_8BIT, 0x0355, 0x04}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0x0C}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x0C}, + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x07}, + {IMX_8BIT, 0x3313, 0x3C}, + {IMX_8BIT, 0x331C, 0x02}, + {IMX_8BIT, 0x331D, 0xA0}, + {IMX_8BIT, 0x4084, 0x0C}, + {IMX_8BIT, 0x4085, 0xD0}, + {IMX_8BIT, 0x4086, 0x07}, + {IMX_8BIT, 0x4087, 0x3C}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_6m_for_mipi_342[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x14}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 36, 194, 1039, a9f 4100x2316 */ + {IMX_8BIT, 0x0345, 0x36}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x94}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x39}, + {IMX_8BIT, 0x034A, 0x0A}, + {IMX_8BIT, 0x034B, 0x9F}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280x1852 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x07}, + {IMX_8BIT, 0x034F, 0x3C}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* 4100x2316 */ + {IMX_8BIT, 0x0355, 0x04}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0x0C}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x0C}, + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x07}, + {IMX_8BIT, 0x3313, 0x3C}, + {IMX_8BIT, 0x331C, 0x02}, + {IMX_8BIT, 0x331D, 0xA0}, + {IMX_8BIT, 0x4084, 0x0C}, + {IMX_8BIT, 0x4085, 0xD0}, + {IMX_8BIT, 0x4086, 0x07}, + {IMX_8BIT, 0x4087, 0x3C}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * FOV is: 3280x2464, larger then 3264x2448. + * Sensor output: 336x256 + * Cropping region: 3444x2624 + */ +static struct imx_reg const imx135_336x256[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x22}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* 2x binning */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x52}, /* scaling: 82/16 */ + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, /* x_start: 374 */ + {IMX_8BIT, 0x0345, 0x76}, + {IMX_8BIT, 0x0346, 0x00}, /* y_start: 248 */ + {IMX_8BIT, 0x0347, 0xF8}, + {IMX_8BIT, 0x0348, 0x0E}, /* x_end: 3817 */ + {IMX_8BIT, 0x0349, 0xE9}, + {IMX_8BIT, 0x034A, 0x0B}, /* y_end: 2871 */ + {IMX_8BIT, 0x034B, 0x37}, + {IMX_8BIT, 0x034C, 0x01}, /* x_out: 336 */ + {IMX_8BIT, 0x034D, 0x50}, + {IMX_8BIT, 0x034E, 0x01}, /* y_out: 256 */ + {IMX_8BIT, 0x034F, 0x00}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x06}, /* dig x_out: 1722 */ + {IMX_8BIT, 0x0355, 0xBA}, + {IMX_8BIT, 0x0356, 0x05}, /* dig y_out: 1312 */ + {IMX_8BIT, 0x0357, 0x20}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x01}, /* ?: x_out */ + {IMX_8BIT, 0x3311, 0x50}, + {IMX_8BIT, 0x3312, 0x01}, /* ?: y_out */ + {IMX_8BIT, 0x3313, 0x00}, + {IMX_8BIT, 0x331C, 0x02}, + {IMX_8BIT, 0x331D, 0x4E}, + {IMX_8BIT, 0x4084, 0x01}, /* ?: x_out */ + {IMX_8BIT, 0x4085, 0x50}, + {IMX_8BIT, 0x4086, 0x01}, /* ?: y_out */ + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_1m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x22}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x1F}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x58}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x28}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x17}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x07}, + {IMX_8BIT, 0x034C, 0x04}, + {IMX_8BIT, 0x034D, 0x10}, + {IMX_8BIT, 0x034E, 0x03}, + {IMX_8BIT, 0x034F, 0x10}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x07}, + {IMX_8BIT, 0x0355, 0xE0}, + {IMX_8BIT, 0x0356, 0x05}, + {IMX_8BIT, 0x0357, 0xF0}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x04}, + {IMX_8BIT, 0x3311, 0x10}, + {IMX_8BIT, 0x3312, 0x03}, + {IMX_8BIT, 0x3313, 0x10}, + {IMX_8BIT, 0x331C, 0x02}, + {IMX_8BIT, 0x331D, 0x4E}, + {IMX_8BIT, 0x4084, 0x04}, + {IMX_8BIT, 0x4085, 0x10}, + {IMX_8BIT, 0x4086, 0x03}, + {IMX_8BIT, 0x4087, 0x10}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_3m_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, /* Binning */ + {IMX_8BIT, 0x0391, 0x22}, /* 2x2 binning */ + {IMX_8BIT, 0x0392, 0x00}, /* average */ + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x28}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x08}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x47}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x27}, + {IMX_8BIT, 0x034C, 0x08}, + {IMX_8BIT, 0x034D, 0x10}, + {IMX_8BIT, 0x034E, 0x06}, + {IMX_8BIT, 0x034F, 0x10}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x08}, + {IMX_8BIT, 0x0355, 0x10}, + {IMX_8BIT, 0x0356, 0x06}, + {IMX_8BIT, 0x0357, 0x10}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x08}, + {IMX_8BIT, 0x3311, 0x10}, + {IMX_8BIT, 0x3312, 0x06}, + {IMX_8BIT, 0x3313, 0x10}, + {IMX_8BIT, 0x331C, 0x00}, + {IMX_8BIT, 0x331D, 0xAA}, + {IMX_8BIT, 0x4084, 0x00}, + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +/* 1080P 1936x1104 */ +static struct imx_reg const imx135_1080p_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x22}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x11}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x2E}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x84}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x41}, + {IMX_8BIT, 0x034A, 0x0A}, + {IMX_8BIT, 0x034B, 0xAF}, + {IMX_8BIT, 0x034C, 0x07}, + {IMX_8BIT, 0x034D, 0x90}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x50}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x08}, + {IMX_8BIT, 0x0355, 0x0A}, + {IMX_8BIT, 0x0356, 0x04}, + {IMX_8BIT, 0x0357, 0x96}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x07}, + {IMX_8BIT, 0x3311, 0x90}, + {IMX_8BIT, 0x3312, 0x04}, + {IMX_8BIT, 0x3313, 0x50}, + {IMX_8BIT, 0x331C, 0x01}, + {IMX_8BIT, 0x331D, 0x00}, + {IMX_8BIT, 0x4084, 0x07}, + {IMX_8BIT, 0x4085, 0x90}, + {IMX_8BIT, 0x4086, 0x04}, + {IMX_8BIT, 0x4087, 0x50}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static const struct imx_reg imx135_1080p_nodvs_fullfov_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 168,464,4039,2655: 3872x2192 */ + { IMX_8BIT, 0x0345, 0xA8 }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0xD0 }, + { IMX_8BIT, 0x0348, 0x0F }, + { IMX_8BIT, 0x0349, 0xC7 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0x5F }, + { IMX_8BIT, 0x034C, 0x07 }, /*1936 x 1096 */ + { IMX_8BIT, 0x034D, 0x90 }, + { IMX_8BIT, 0x034E, 0x04 }, + { IMX_8BIT, 0x034F, 0x48 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x07 }, /*1936 x 1096 */ + { IMX_8BIT, 0x0355, 0x90 }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x48 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x07 }, + { IMX_8BIT, 0x3311, 0x90 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x48 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0xB0 }, + { IMX_8BIT, 0x4084, 0x07 }, + { IMX_8BIT, 0x4085, 0x90 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x48 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* 1080P NODVS 1936x1096 */ +static const struct imx_reg imx135_1080p_nodvs_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x11 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 46,396,4161,2727: 4116x2332 */ + { IMX_8BIT, 0x0345, 0x2E }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x8C }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x41 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0xA7 }, + { IMX_8BIT, 0x034C, 0x07 }, /*1936 x 1096 */ + { IMX_8BIT, 0x034D, 0x90 }, + { IMX_8BIT, 0x034E, 0x04 }, + { IMX_8BIT, 0x034F, 0x48 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /* 2058x1166 */ + { IMX_8BIT, 0x0355, 0x0A }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x8E }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x07 }, + { IMX_8BIT, 0x3311, 0x90 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x48 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0xB0 }, + { IMX_8BIT, 0x4084, 0x07 }, + { IMX_8BIT, 0x4085, 0x90 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x48 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* 1080P 10%DVS 2104x1184 */ +static const struct imx_reg imx135_1080p_10_dvs_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 0,376,4207,2743: 4208x2368 */ + { IMX_8BIT, 0x0345, 0x00 }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x78 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x6F }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0xB7 }, + { IMX_8BIT, 0x034C, 0x08 }, /* 2104 x 1184 */ + { IMX_8BIT, 0x034D, 0x38 }, + { IMX_8BIT, 0x034E, 0x04 }, + { IMX_8BIT, 0x034F, 0xA0 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /* 2104 x 1184 */ + { IMX_8BIT, 0x0355, 0x38 }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0xA0 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x08 }, + { IMX_8BIT, 0x3311, 0x38 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0xA0 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0xB0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx135_720pdvs_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x15 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 46,404,4161,2715: 4116x2312 */ + { IMX_8BIT, 0x0345, 0x2E }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x94 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x41 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0x9B }, + { IMX_8BIT, 0x034C, 0x06 }, /*1568 x 880 */ + { IMX_8BIT, 0x034D, 0x20 }, + { IMX_8BIT, 0x034E, 0x03 }, + { IMX_8BIT, 0x034F, 0x70 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /*2058 x 1156 */ + { IMX_8BIT, 0x0355, 0x0A }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x84 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x70 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x4C }, + { IMX_8BIT, 0x4084, 0x06 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x03 }, + { IMX_8BIT, 0x4087, 0x70 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/******************* Video Modes ******************/ + +/* 1080P DVS 2336x1320 */ +static const struct imx_reg imx135_2336x1320_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1C }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 60,404,4147,2715: 4088x2312 */ + { IMX_8BIT, 0x0345, 0x3C }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x94 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x33 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0x9B }, + { IMX_8BIT, 0x034C, 0x09 }, /*2336 x 1320 */ + { IMX_8BIT, 0x034D, 0x20 }, + { IMX_8BIT, 0x034E, 0x05 }, + { IMX_8BIT, 0x034F, 0x28 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0F }, /* 4088x2312 */ + { IMX_8BIT, 0x0355, 0xF8 }, + { IMX_8BIT, 0x0356, 0x09 }, + { IMX_8BIT, 0x0357, 0x08 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x09 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x05 }, + { IMX_8BIT, 0x3313, 0x28 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0xE2 }, + { IMX_8BIT, 0x4084, 0x09 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x05 }, + { IMX_8BIT, 0x4087, 0x28 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* 1080P DVS 2336x1320 Cropped */ +static const struct imx_reg imx135_2336x1320_cropped_mipi499[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_499_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1C }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x03 }, /* 936,900,3271,2219: 2336x1320 */ + { IMX_8BIT, 0x0345, 0xA8 }, + { IMX_8BIT, 0x0346, 0x03 }, + { IMX_8BIT, 0x0347, 0x84 }, + { IMX_8BIT, 0x0348, 0x0C }, + { IMX_8BIT, 0x0349, 0xC7 }, + { IMX_8BIT, 0x034A, 0x08 }, + { IMX_8BIT, 0x034B, 0xAB }, + { IMX_8BIT, 0x034C, 0x09 }, /* 2336 x 1320 */ + { IMX_8BIT, 0x034D, 0x20 }, + { IMX_8BIT, 0x034E, 0x05 }, + { IMX_8BIT, 0x034F, 0x28 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x09 }, /* 2336 x 1320 */ + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x05 }, + { IMX_8BIT, 0x0357, 0x28 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x09 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x05 }, + { IMX_8BIT, 0x3313, 0x28 }, + { IMX_8BIT, 0x331C, 0x00 }, + { IMX_8BIT, 0x331D, 0xB4 }, + { IMX_8BIT, 0x4084, 0x09 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x05 }, + { IMX_8BIT, 0x4087, 0x28 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* 720P DVS 1568 x 880 */ +static const struct imx_reg imx135_720p_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x15 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 46,404,4161,2715: 4116x2312 */ + { IMX_8BIT, 0x0345, 0x2e }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x94 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x41 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0x9B }, + { IMX_8BIT, 0x034C, 0x06 }, /*1568 x 880 */ + { IMX_8BIT, 0x034D, 0x20 }, + { IMX_8BIT, 0x034E, 0x03 }, + { IMX_8BIT, 0x034F, 0x70 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /* 2058x1156 */ + { IMX_8BIT, 0x0355, 0x0a }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x84 }, + { IMX_8BIT, 0x301D, 0x30 }, /* TODO! */ + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x70 }, + { IMX_8BIT, 0x331C, 0x01 }, /* TODO! */ + { IMX_8BIT, 0x331D, 0xd6 }, /* TODO! */ + { IMX_8BIT, 0x4084, 0x06 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x03 }, + { IMX_8BIT, 0x4087, 0x70 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* wvga: H : 1640 V : 1024 */ +static const struct imx_reg imx135_wvga_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x22 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x14 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, + {IMX_8BIT, 0x0345, 0x36 }, + {IMX_8BIT, 0x0346, 0x01 }, + {IMX_8BIT, 0x0347, 0x18 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x39 }, + {IMX_8BIT, 0x034A, 0x0B }, + {IMX_8BIT, 0x034B, 0x17 }, + {IMX_8BIT, 0x034C, 0x06 }, + {IMX_8BIT, 0x034D, 0x68 }, + {IMX_8BIT, 0x034E, 0x04 }, + {IMX_8BIT, 0x034F, 0x00 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x08 }, + {IMX_8BIT, 0x0355, 0x02 }, + {IMX_8BIT, 0x0356, 0x05 }, + {IMX_8BIT, 0x0357, 0x00 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x06 }, + {IMX_8BIT, 0x3311, 0x68 }, + {IMX_8BIT, 0x3312, 0x04 }, + {IMX_8BIT, 0x3313, 0x00 }, + {IMX_8BIT, 0x331C, 0x01 }, + {IMX_8BIT, 0x331D, 0xBD }, + {IMX_8BIT, 0x4084, 0x06 }, + {IMX_8BIT, 0x4085, 0x68 }, + {IMX_8BIT, 0x4086, 0x04 }, + {IMX_8BIT, 0x4087, 0x00 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* 480P 1036 x 696 */ +static const struct imx_reg imx135_480p_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x00 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x10 },/* No scal */ + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 52,20,4155, 3099 4144x2784*/ + {IMX_8BIT, 0x0345, 0x20 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0xA8 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x4F }, + {IMX_8BIT, 0x034A, 0x0B }, + {IMX_8BIT, 0x034B, 0x88 }, + {IMX_8BIT, 0x034C, 0x04 }, /* 1036 * 696 */ + {IMX_8BIT, 0x034D, 0x0C }, + {IMX_8BIT, 0x034E, 0x02 }, + {IMX_8BIT, 0x034F, 0xB8 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x04 }, /* 1036x696 */ + {IMX_8BIT, 0x0355, 0x0C }, + {IMX_8BIT, 0x0356, 0x02 }, + {IMX_8BIT, 0x0357, 0xB8 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x04 }, + {IMX_8BIT, 0x3311, 0x0C }, + {IMX_8BIT, 0x3312, 0x02 }, + {IMX_8BIT, 0x3313, 0xB8 }, + {IMX_8BIT, 0x331C, 0x02 }, + {IMX_8BIT, 0x331D, 0x21 }, + {IMX_8BIT, 0x4084, 0x04 }, + {IMX_8BIT, 0x4085, 0x0C }, + {IMX_8BIT, 0x4086, 0x02 }, + {IMX_8BIT, 0x4087, 0xB8 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* 480P DVS 936 x 602 */ +static const struct imx_reg imx135_480p_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x23 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 56,244,4151,2877: 4096x2634 */ + { IMX_8BIT, 0x0345, 0x38 }, + { IMX_8BIT, 0x0346, 0x00 }, + { IMX_8BIT, 0x0347, 0xf4 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x37 }, + { IMX_8BIT, 0x034A, 0x0b }, + { IMX_8BIT, 0x034B, 0x3d }, + { IMX_8BIT, 0x034C, 0x03 }, /* 936 x 602 */ + { IMX_8BIT, 0x034D, 0xa8 }, + { IMX_8BIT, 0x034E, 0x02 }, + { IMX_8BIT, 0x034F, 0x5a }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /* 2058x1156 */ + { IMX_8BIT, 0x0355, 0x00 }, + { IMX_8BIT, 0x0356, 0x05 }, + { IMX_8BIT, 0x0357, 0x25 }, + { IMX_8BIT, 0x301D, 0x30 }, /* TODO! */ + { IMX_8BIT, 0x3310, 0x03 }, + { IMX_8BIT, 0x3311, 0xa8 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x5a }, + { IMX_8BIT, 0x331C, 0x01 }, /* TODO! */ + { IMX_8BIT, 0x331D, 0xd6 }, + { IMX_8BIT, 0x4084, 0x03 }, + { IMX_8BIT, 0x4085, 0xa8 }, + { IMX_8BIT, 0x4086, 0x02 }, + { IMX_8BIT, 0x4087, 0x5a }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* VGA: H : 1036 V : 780 */ +static const struct imx_reg imx135_vga_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x00 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x10 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 52,20,4155, 3099 4144x3120*/ + {IMX_8BIT, 0x0345, 0x20 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x00 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x4F }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x2F }, + {IMX_8BIT, 0x034C, 0x04 }, /* 1036x780 */ + {IMX_8BIT, 0x034D, 0x0C }, + {IMX_8BIT, 0x034E, 0x03 }, + {IMX_8BIT, 0x034F, 0x0C }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x04 }, /* 1036x780 */ + {IMX_8BIT, 0x0355, 0x0C }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x0C }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x04 }, + {IMX_8BIT, 0x3311, 0x0C }, + {IMX_8BIT, 0x3312, 0x03 }, + {IMX_8BIT, 0x3313, 0x0C }, + {IMX_8BIT, 0x331C, 0x02 }, + {IMX_8BIT, 0x331D, 0x21 }, + {IMX_8BIT, 0x4084, 0x04 }, + {IMX_8BIT, 0x4085, 0x0C }, + {IMX_8BIT, 0x4086, 0x03 }, + {IMX_8BIT, 0x4087, 0x0C }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* VGA: H : 820 V : 616 */ +static const struct imx_reg imx135_vga_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x14 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 52,20,4155, 3099 4104x3080*/ + {IMX_8BIT, 0x0345, 0x34 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x14 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x3B }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x1B }, + {IMX_8BIT, 0x034C, 0x03 }, /* 820x616 */ + {IMX_8BIT, 0x034D, 0x34 }, + {IMX_8BIT, 0x034E, 0x02 }, + {IMX_8BIT, 0x034F, 0x68 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x04 }, /* 1026x770 */ + {IMX_8BIT, 0x0355, 0x02 }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x02 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x03 }, + {IMX_8BIT, 0x3311, 0x34 }, + {IMX_8BIT, 0x3312, 0x02 }, + {IMX_8BIT, 0x3313, 0x68 }, + {IMX_8BIT, 0x331C, 0x02 }, + {IMX_8BIT, 0x331D, 0x21 }, + {IMX_8BIT, 0x4084, 0x03 }, + {IMX_8BIT, 0x4085, 0x34 }, + {IMX_8BIT, 0x4086, 0x02 }, + {IMX_8BIT, 0x4087, 0x68 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* VGA: H : 436 V : 360 */ +static const struct imx_reg imx135_436x360_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x22 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 212,0,3995,3119 3784x3120 */ + {IMX_8BIT, 0x0345, 0xD4 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x00 }, + {IMX_8BIT, 0x0348, 0x0F }, + {IMX_8BIT, 0x0349, 0x9B }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x2F }, + + {IMX_8BIT, 0x034C, 0x01 }, /* 436x360 */ + {IMX_8BIT, 0x034D, 0xB4 }, + {IMX_8BIT, 0x034E, 0x01 }, + {IMX_8BIT, 0x034F, 0x68 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x12 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x0C }, + + {IMX_8BIT, 0x0354, 0x03 }, /* 928x768 crop from 946x780*/ + {IMX_8BIT, 0x0355, 0xA0 }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x00 }, + + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x01 }, + {IMX_8BIT, 0x3311, 0xB4 }, + {IMX_8BIT, 0x3312, 0x01 }, + {IMX_8BIT, 0x3313, 0x68 }, + {IMX_8BIT, 0x331C, 0x02 }, + {IMX_8BIT, 0x331D, 0x21 }, + {IMX_8BIT, 0x4084, 0x01 }, + {IMX_8BIT, 0x4085, 0xB4 }, + {IMX_8BIT, 0x4086, 0x01 }, + {IMX_8BIT, 0x4087, 0x68 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* QVGA: H : 408 V : 308 */ +static const struct imx_reg imx135_qvga__dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x28 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 64,20,4143,3099 4080x3080 */ + {IMX_8BIT, 0x0345, 0x40 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x14 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x2F }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x1B }, + {IMX_8BIT, 0x034C, 0x01 }, /* 408x308 */ + {IMX_8BIT, 0x034D, 0x98 }, + {IMX_8BIT, 0x034E, 0x01 }, + {IMX_8BIT, 0x034F, 0x34 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x03 }, /* 1020x770 */ + {IMX_8BIT, 0x0355, 0xFC }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x02 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x01 }, + {IMX_8BIT, 0x3311, 0x98 }, + {IMX_8BIT, 0x3312, 0x01 }, + {IMX_8BIT, 0x3313, 0x34 }, + {IMX_8BIT, 0x331C, 0x01 }, + {IMX_8BIT, 0x331D, 0x68 }, + {IMX_8BIT, 0x4084, 0x01 }, + {IMX_8BIT, 0x4085, 0x98 }, + {IMX_8BIT, 0x4086, 0x01 }, + {IMX_8BIT, 0x4087, 0x34 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* CIF H : 368 V : 304 */ +static const struct imx_reg imx135_cif_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x28 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01 }, /* 264,42,3943,3081 3680x3040 */ + {IMX_8BIT, 0x0345, 0x08 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x2a }, + {IMX_8BIT, 0x0348, 0x0F }, + {IMX_8BIT, 0x0349, 0x67 }, + {IMX_8BIT, 0x034A, 0x0c }, + {IMX_8BIT, 0x034B, 0x09 }, + {IMX_8BIT, 0x034C, 0x01 }, /* 368x304 */ + {IMX_8BIT, 0x034D, 0x70 }, + {IMX_8BIT, 0x034E, 0x01 }, + {IMX_8BIT, 0x034F, 0x30 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x03 }, /* 920x760 */ + {IMX_8BIT, 0x0355, 0x98 }, + {IMX_8BIT, 0x0356, 0x02 }, + {IMX_8BIT, 0x0357, 0xf8 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x01 }, + {IMX_8BIT, 0x3311, 0x70 }, + {IMX_8BIT, 0x3312, 0x01 }, + {IMX_8BIT, 0x3313, 0x30 }, + {IMX_8BIT, 0x331C, 0x02 }, /* TODO! binning 4x4 must be 021c? */ + {IMX_8BIT, 0x331D, 0x1C }, + {IMX_8BIT, 0x4084, 0x01 }, + {IMX_8BIT, 0x4085, 0x70 }, + {IMX_8BIT, 0x4086, 0x01 }, + {IMX_8BIT, 0x4087, 0x30 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* CIF H : 1888 V : 1548 */ +static const struct imx_reg imx135_cif_binning_1888x1548[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x22 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x00 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x10 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 264,42, 3776x3096 */ + {IMX_8BIT, 0x0345, 0xD8 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x0C }, + {IMX_8BIT, 0x0348, 0x0F }, + {IMX_8BIT, 0x0349, 0x97 }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x23 }, + {IMX_8BIT, 0x034C, 0x07 }, /* 1888x1548 */ + {IMX_8BIT, 0x034D, 0x60 }, + {IMX_8BIT, 0x034E, 0x06 }, + {IMX_8BIT, 0x034F, 0x0C }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x07 }, /* 1888x1548 */ + {IMX_8BIT, 0x0355, 0x60 }, + {IMX_8BIT, 0x0356, 0x06 }, + {IMX_8BIT, 0x0357, 0x0C }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x07 }, + {IMX_8BIT, 0x3311, 0x60 }, + {IMX_8BIT, 0x3312, 0x06 }, + {IMX_8BIT, 0x3313, 0x0C }, + {IMX_8BIT, 0x331C, 0x02 }, /* TODO! binning 4x4 must be 021c? */ + {IMX_8BIT, 0x331D, 0x1C }, + {IMX_8BIT, 0x4084, 0x07 }, + {IMX_8BIT, 0x4085, 0x60 }, + {IMX_8BIT, 0x4086, 0x06 }, + {IMX_8BIT, 0x4087, 0x0C }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* QCIF H : 216 V : 176 */ +static const struct imx_reg imx135_qcif_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x46 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 212,20,3995,3099 3784x3080 */ + {IMX_8BIT, 0x0345, 0xD4 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x14 }, + {IMX_8BIT, 0x0348, 0x0F }, + {IMX_8BIT, 0x0349, 0x9B }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x1B }, + {IMX_8BIT, 0x034C, 0x00 }, /* 216x176 */ + {IMX_8BIT, 0x034D, 0xD8 }, + {IMX_8BIT, 0x034E, 0x00 }, + {IMX_8BIT, 0x034F, 0xB0 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x03 }, /* 946x770 */ + {IMX_8BIT, 0x0355, 0xB2 }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x02 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x00 }, + {IMX_8BIT, 0x3311, 0xD8 }, + {IMX_8BIT, 0x3312, 0x00 }, + {IMX_8BIT, 0x3313, 0xB0 }, + {IMX_8BIT, 0x331C, 0x02 }, /* TODO! binning 4x4 must be 021c */ + {IMX_8BIT, 0x331D, 0x1C }, + {IMX_8BIT, 0x4084, 0x00 }, + {IMX_8BIT, 0x4085, 0xD8 }, + {IMX_8BIT, 0x4086, 0x00 }, + {IMX_8BIT, 0x4087, 0xB0 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* + * ISP Scaling is now supported in offine capture use cases. Because of that + * we need only few modes to cover the different aspect ratios from the + * sensor and the ISP will scale it based on the requested resolution from HAL. + * + * There is a performance impact when continuous view finder option is chose + * for resolutions above 8MP. So 8MP and 6MP resolution are kept, so that lower + * than these take 8MP or 6MP espectively for down scaling based on the + * aspect ratio. + */ +struct imx_resolution imx135_res_preview_mofd[] = { + { + .desc = "imx135_cif_binning_preview", + .regs = imx135_cif_binning, + .width = 368, + .height = 304, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 9114, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_vga_binning_preview", + .regs = imx135_vga_binning, + .width = 1036, + .height = 780, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_480p_preview", + .regs = imx135_480p_binning, + .width = 1036, + .height = 696, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_1080p_binning_preview", + .regs = imx135_1080p_binning, + .width = 1936, + .height = 1104, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_3m__cont_cap", + .regs = imx135_3m_binning, + .width = 2064, + .height = 1552, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_6m_cont_cap", + .regs = imx135_6m, + .width = 3280, + .height = 1852, + .fps_options = { + { /* Binning Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_8m_scaled_from_12m__cont_cap", + .regs = imx135_8m_scaled_from_12m, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 24, + .pixels_per_line = 4572, + .lines_per_frame = 3280, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_10m__cont_cap", + .regs = imx135_10m, + .width = 4208, + .height = 2368, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2632, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_13m__cont_cap", + .regs = imx135_13m, + .width = 4208, + .height = 3120, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 24, + .pixels_per_line = 4572, + .lines_per_frame = 3290, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, +}; + +struct imx_resolution imx135_res_preview[] = { + { + .desc = "imx135_xga_cropped_video", + .regs = imx135_xga_cropped, + .width = 832, + .height = 628, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_2m_cropped_video", + .regs = imx135_2m_cropped, + .width = 1648, + .height = 1240, + .fps_options = { + { /* Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_1936x1096_cropped", + .regs = imx135_1936x1096_cropped, + .width = 1936, + .height = 1096, + .fps_options = { + { /* Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_8m_cropped_video", + .regs = imx135_8m_cropped, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, +}; + +/* + * ISP Scaling is now supported in online capture use cases. Because of that + * we need only few modes to cover the different aspect ratios from the + * sensor and the ISP will scale it based on the requested resolution from HAL. + * + * There is a performance impact when continuous view finder option is chose + * for resolutions above 8MP. So 8MP and 6MP resolution are kept, so that lower + * than these take 8MP or 6MP espectively for down scaling based on the + * aspect ratio. + */ +struct imx_resolution imx135_res_still_mofd[] = { + { + .desc = "imx135_cif_binning_still", + .regs = imx135_cif_binning_1888x1548, + .width = 1888, + .height = 1548, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 209600, + }, + { + .desc = "imx135_vga_binning_preview", + .regs = imx135_vga_binning, + .width = 1036, + .height = 780, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_480p_preview", + .regs = imx135_480p_binning, + .width = 1036, + .height = 696, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_1080p_binning_still", + .regs = imx135_1080p_binning, + .width = 1936, + .height = 1104, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 15, + .pixels_per_line = 9114, + .lines_per_frame = 2453, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_3m__still", + .regs = imx135_3m_binning, + .width = 2064, + .height = 1552, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 15, + .pixels_per_line = 9114, + .lines_per_frame = 2453, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_6m_for_mipi_342_still", + .regs = imx135_6m_for_mipi_342, + .width = 3280, + .height = 1852, + .fps_options = { + { /* Pixel clock: 273.6MHz */ + .fps = 11, + .pixels_per_line = 9114, + .lines_per_frame = 2664, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 342000, + }, + { + .desc = "imx135_8m_scaled_from_12m_for_mipi342_still", + .regs = imx135_8m_scaled_from_12m_for_mipi342, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 273.6MHz */ + .fps = 8, + .pixels_per_line = 7672, + .lines_per_frame = 4458, + }, + { /* Pixel clock: 273.6MHz */ + .fps = 15, + .pixels_per_line = 5500, + .lines_per_frame = 3314, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 342000, + }, + { + .desc = "imx135_10m_for_mipi_342_still", + .regs = imx135_10m_for_mipi_342, + .width = 4208, + .height = 2368, + .fps_options = { + { /* Pixel clock: 273.6MHz */ + .fps = 11, + .pixels_per_line = 9144, + .lines_per_frame = 2664, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 342000, + }, + { + .desc = "imx135_13m_still", + .regs = imx135_13m_for_mipi_342, + .width = 4208, + .height = 3120, + .fps_options = { + { /* Pixel clock: 273.6MHz */ + .fps = 5, + .pixels_per_line = 9144, + .lines_per_frame = 5990, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 342000, + }, +}; + +struct imx_resolution imx135_res_still[] = { + { + .desc = "imx135_qvga", + .regs = imx135_336x256, + .width = 336, + .height = 256, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_cif", + .regs = imx135_368x304_cropped, + .width = 368, + .height = 304, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_xga_cropped_video", + .regs = imx135_xga_cropped, + .width = 832, + .height = 628, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_2M_for_11:9", + .regs = imx135_1424x1168_cropped, + .width = 1424, + .height = 1168, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_2m_cropped_video", + .regs = imx135_2m_cropped, + .width = 1648, + .height = 1240, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 15, + .pixels_per_line = 6466, + .lines_per_frame = 3710, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_6m_cropped_video", + .regs = imx135_6m_cropped, + .width = 3280, + .height = 1852, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 8, + .pixels_per_line = 8850, + .lines_per_frame = 5080, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_8m_cropped_video", + .regs = imx135_8m_cropped, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 8, + .pixels_per_line = 8850, + .lines_per_frame = 5080, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, +}; + +/* + * ISP scaling is not supported in case of video modes. So we need to have + * separate sensor mode for video use cases + */ +struct imx_resolution imx135_res_video[] = { + /* For binning modes pix clock is 335.36 MHz. */ + { + .desc = "imx135_qcif_dvs_binning_video", + .regs = imx135_qcif_dvs_binning, + .width = 216, + .height = 176, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_cif_binning_video", + .regs = imx135_cif_binning, + .width = 368, + .height = 304, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_qvga__dvs_binning_video", + .regs = imx135_qvga__dvs_binning, + .width = 408, + .height = 308, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_436x360_binning_video", + .regs = imx135_436x360_binning, + .width = 436, + .height = 360, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_vga_dvs_binning_video", + .regs = imx135_vga_dvs_binning, + .width = 820, + .height = 616, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_480p_dvs_binning_video", + .regs = imx135_480p_dvs_binning, + .width = 936, + .height = 602, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 209600, + }, + { + .desc = "imx135_720P_dvs_video", + .regs = imx135_720pdvs_max_clock, + .width = 1568, + .height = 880, + .fps_options = { + {/* Pixel Clock : 360.96 MHz */ + .fps = 30, + .pixels_per_line = 5850, + .lines_per_frame = 2000, + }, + {/* Pixel Clock : 360.96 MHz */ + .fps = 60, + .pixels_per_line = 4572, + .lines_per_frame = 1310, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 451200, + }, + { + .desc = "imx135_wvga_dvs_binning_video", + .regs = imx135_wvga_dvs_binning, + .width = 1640, + .height = 1024, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 209600, + }, + { + .desc = "imx135_1936_1096_fullfov_max_clock", + .regs = imx135_1080p_nodvs_max_clock, + .width = 1936, + .height = 1096, + .fps_options = { + {/* Pixel Clock : 360.96 MHz */ + .fps = 30, + .pixels_per_line = 5850, + .lines_per_frame = 2000, + }, + {/* Pixel Clock : 360.96 MHz */ + .fps = 60, + .pixels_per_line = 4572, + .lines_per_frame = 1310, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 451200, + }, + { + .desc = "imx135_1080P_dvs_video", + .regs = imx135_2336x1320_max_clock, + .width = 2336, + .height = 1320, + .fps_options = { + {/* Pixel Clock : 360.96 MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2632, + .regs = imx135_2336x1320_max_clock, + .mipi_freq = 451200, + }, + {/* Pixel Clock : 399.36MHz */ + .fps = 60, + .pixels_per_line = 4754, + .lines_per_frame = 1400, + .regs = imx135_2336x1320_cropped_mipi499, + .mipi_freq = 499200, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_6m_cont_cap", + .regs = imx135_6m, + .width = 3280, + .height = 1852, + .fps_options = { + { /* Binning Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_8m_cropped_video", + .regs = imx135_8m_cropped, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, +}; + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/imx175.h b/drivers/staging/media/atomisp/i2c/imx/imx175.h new file mode 100644 index 0000000..5f409cc --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx175.h @@ -0,0 +1,1959 @@ +#ifndef __IMX175_H__ +#define __IMX175_H__ +#include "common.h" + +/************************** settings for imx *************************/ +static struct imx_reg const imx_STILL_8M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0C}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD0}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x09}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xA0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_8M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0C}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD0}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x09}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xA0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_3M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x08}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x06}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x10}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x19}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_3M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x08}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x06}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x10}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x19}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + + +static struct imx_reg const imx_STILL_5M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0A}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x07}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x90}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x14}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_5M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0A}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x07}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x90}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x14}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_6M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x32}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x6D}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0C}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD0}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x07}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x3C}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_6M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x32}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x6D}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0C}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD0}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x07}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x3C}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_2M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x8C}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x68}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xD0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_2M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x8C}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x68}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xD0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_PREVIEW_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x06}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x05}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x48}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x70}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x03}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x34}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x68}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x03}, + {IMX_8BIT, 0x33D5, 0x34}, + {IMX_8BIT, 0x33D6, 0x02}, + {IMX_8BIT, 0x33D7, 0x68}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_WIDE_PREVIEW_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x06}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0D}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x70}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x10}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x00}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x14}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x8C}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x68}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xBC}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x68}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0xBC}, + {IMX_TOK_TERM, 0, 0} +}; + +/*****************************video************************/ +static struct imx_reg const imx_1080p_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x06}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x4C}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xA4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x11}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0xC6}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0xDB}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x02}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x42}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0A}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xEA}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x07}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x61}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x09}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x05}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x20}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_1080p_no_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x08}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xD5}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x07}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xD0}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0F}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x3C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x34}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x6B}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x07}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x94}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x44}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x1B}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_1080p_no_dvs_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x08}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xD5}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xA6}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x18}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x9C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x34}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x6B}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x07}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x94}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x44}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x1B}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; +/*****************************video************************/ +static struct imx_reg const imx_720p_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x13}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x9C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0xD7}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x02}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x3E}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0A}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xEE}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x07}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x65}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x70}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x18}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_480p_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x13}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x9C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0xD4}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0xC8}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0A}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xF1}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x07}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0xDB}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x03}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x70}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x50}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x15}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_720p_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x05}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x48}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x14}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x28}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x48}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x64}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0x87}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x3B}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x20}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x6C}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_720p_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x08}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xCA}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x18}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x38}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x48}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x64}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0x87}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x3B}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x20}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x6C}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_WVGA_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x13}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x9C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0xD0}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0xCF}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x68}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x00}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; +static struct imx_reg const imx_CIF_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x11}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0xDB}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x01}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x70}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x01}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x30}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_VGA_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x11}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x94}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x03}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x34}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x68}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_VGA_strong_dvs_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x07}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x9E}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x1C}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0xB6}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x03}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x34}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x68}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_QVGA_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x06}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x05}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x48}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x70}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x03}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x38}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x02}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x68}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x09}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0x97}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x07}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x37}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x01}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x98}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x01}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x34}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x01}, + {IMX_8BIT, 0x33D5, 0x98}, + {IMX_8BIT, 0x33D6, 0x01}, + {IMX_8BIT, 0x33D7, 0x34}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_QCIF_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x06}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x05}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x48}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x70}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x04}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0xB8}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x03}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x70}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x08}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0x17}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x06}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x2F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x00}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD8}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x00}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xB0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x00}, + {IMX_8BIT, 0x33D5, 0xD8}, + {IMX_8BIT, 0x33D6, 0x00}, + {IMX_8BIT, 0x33D7, 0xB0}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx175_init_settings[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0103, 0x01}, + /* misc control */ + {IMX_8BIT, 0x3020, 0x10}, + {IMX_8BIT, 0x302D, 0x02}, + {IMX_8BIT, 0x302F, 0x80}, + {IMX_8BIT, 0x3032, 0xA3}, + {IMX_8BIT, 0x3033, 0x20}, + {IMX_8BIT, 0x3034, 0x24}, + {IMX_8BIT, 0x3041, 0x15}, + {IMX_8BIT, 0x3042, 0x87}, + {IMX_8BIT, 0x3050, 0x35}, + {IMX_8BIT, 0x3056, 0x57}, + {IMX_8BIT, 0x305D, 0x41}, + {IMX_8BIT, 0x3097, 0x69}, + {IMX_8BIT, 0x3109, 0x41}, + {IMX_8BIT, 0x3148, 0x3F}, + {IMX_8BIT, 0x330F, 0x07}, + /* csi & inck */ + {IMX_8BIT, 0x3364, 0x00}, + {IMX_8BIT, 0x3368, 0x13}, + {IMX_8BIT, 0x3369, 0x33}, + /* znr */ + {IMX_8BIT, 0x4100, 0x0E}, + {IMX_8BIT, 0x4104, 0x32}, + {IMX_8BIT, 0x4105, 0x32}, + {IMX_8BIT, 0x4108, 0x01}, + {IMX_8BIT, 0x4109, 0x7C}, + {IMX_8BIT, 0x410A, 0x00}, + {IMX_8BIT, 0x410B, 0x00}, + GROUPED_PARAMETER_HOLD_DISABLE, + {IMX_TOK_TERM, 0, 0} +}; +/* TODO settings of preview/still/video will be updated with new use case */ +struct imx_resolution imx175_res_preview[] = { + { + .desc = "CIF_strong_dvs_30fps", + .regs = imx_CIF_strong_dvs_30fps, + .width = 368, + .height = 304, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x11DB, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 261500, + + }, + { + .desc = "VGA_strong_dvs_30fps", + .regs = imx_VGA_strong_dvs_30fps, + .width = 820, + .height = 616, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x11DB, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "WIDE_PREVIEW_30fps", + .regs = imx_WIDE_PREVIEW_30fps, + .width = 1640, + .height = 956, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x1000, + .lines_per_frame = 0x0D70, + }, + { + } + }, + .mipi_freq = 174500, + }, + { + .desc = "STILL_720p_30fps", + .regs = imx_STILL_720p_30fps, + .width = 1568, + .height = 876, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x1428, + .lines_per_frame = 0x0548, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "STILL_2M_30fps", + .regs = imx_STILL_2M_30fps, + .width = 1640, + .height = 1232, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "1080p_strong_dvs_30fps", + .regs = imx_1080p_no_dvs_30fps, + .width = 1940, + .height = 1092, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0F3C, + .lines_per_frame = 0x07D0, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "STILL_3M_30fps", + .regs = imx_STILL_3M_30fps, + .width = 2064, + .height = 1552, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_5M_30fps", + .regs = imx_STILL_5M_30fps, + .width = 2576, + .height = 1936, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_6M_30fps", + .regs = imx_STILL_6M_30fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_8M_30fps", + .regs = imx_STILL_8M_30fps, + .width = 3280, + .height = 2464, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, +}; + +struct imx_resolution imx175_res_still[] = { + { + .desc = "CIF_strong_dvs_30fps", + .regs = imx_CIF_strong_dvs_30fps, + .width = 368, + .height = 304, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x11DB, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 261000, + }, + { + .desc = "VGA_strong_dvs_15fps", + .regs = imx_VGA_strong_dvs_15fps, + .width = 820, + .height = 616, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1C86, + .lines_per_frame = 0x079E, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "imx_STILL_720p_15fps", + .regs = imx_STILL_720p_15fps, + .width = 1568, + .height = 876, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1838, + .lines_per_frame = 0x08CA, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "STILL_2M_15fps", + .regs = imx_STILL_2M_15fps, + .width = 1640, + .height = 1232, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "1080p_strong_dvs_15fps", + .regs = imx_1080p_no_dvs_15fps, + .width = 1940, + .height = 1092, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x189C, + .lines_per_frame = 0x09A6, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "STILL_3M_15fps", + .regs = imx_STILL_3M_15fps, + .width = 2064, + .height = 1552, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_5M_15fps", + .regs = imx_STILL_5M_15fps, + .width = 2576, + .height = 1936, + .fps = 15, + .pixels_per_line = 0x1646, /* consistent with regs arrays */ + .lines_per_frame = 0x0BB8, /* consistent with regs arrays */ + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_6M_15fps", + .regs = imx_STILL_6M_15fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_8M_15fps", + .regs = imx_STILL_8M_15fps, + .width = 3280, + .height = 2464, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, +}; + +struct imx_resolution imx175_res_video[] = { + { + .desc = "QCIF_strong_dvs_30fps", + .regs = imx_QCIF_strong_dvs_30fps, + .width = 216, + .height = 176, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D70, + .lines_per_frame = 0x0548, + }, + { + } + }, + .mipi_freq = 174500, + }, + { + .desc = "QVGA_strong_dvs_30fps", + .regs = imx_QVGA_strong_dvs_30fps, + .width = 408, + .height = 308, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D70, + .lines_per_frame = 0x0548, + }, + { + } + }, + .mipi_freq = 174500, + }, + { + .desc = "VGA_strong_dvs_30fps", + .regs = imx_VGA_strong_dvs_30fps, + .width = 820, + .height = 616, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x1194, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "720p_strong_dvs_30fps", + .regs = imx_720p_strong_dvs_30fps, + .width = 1552, + .height = 880, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x139C, + .lines_per_frame = 0x0600, + }, + { + .fps = 60, + .pixels_per_line = 0xD70, + .lines_per_frame = 0x444, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "480p_strong_dvs_30fps", + .regs = imx_480p_strong_dvs_30fps, + .width = 880, + .height = 592, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x139C, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "WVGA_strong_dvs_30fps", + .regs = imx_WVGA_strong_dvs_30fps, + .width = 1640, + .height = 1024, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x139C, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "1080p_strong_dvs_30fps", + .regs = imx_1080p_strong_dvs_30fps, + .width = 2320, + .height = 1312, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x11C6, + .lines_per_frame = 0x06A4, + }, + { + } + }, + .mipi_freq = 292500, + }, +}; + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/imx208.h b/drivers/staging/media/atomisp/i2c/imx/imx208.h new file mode 100644 index 0000000..fed387f --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx208.h @@ -0,0 +1,550 @@ +/* + * Support for Sony IMX camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __IMX208_H__ +#define __IMX208_H__ +#include "common.h" + +/********************** settings for imx from vendor*********************/ +static struct imx_reg imx208_1080p_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x07}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x8F}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x04}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x47}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x07}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0x90}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0x48}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x01}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x01}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x00}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x00}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x61}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx208_1296x736_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x40}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0xB4}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x06}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x4F}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x03}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x93}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x05}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0xE0}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x01}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x01}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x00}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x00}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x61}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx208_1296x976_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x40}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0x3C}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x06}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x4F}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x04}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x0B}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x05}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0xD0}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x01}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x01}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x00}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x00}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x61}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx208_336x256_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x02}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x78}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0x24}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x05}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x17}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x03}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x23}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x01}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0x50}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x01}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0x00}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x03}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x03}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x01}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x03}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x66}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx208_192x160_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x02}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x48}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0xE4}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x05}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x47}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x03}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x63}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x00}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0xC0}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x00}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0xA0}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x03}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x05}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x03}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x05}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x01}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x03}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x11}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x74}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; +/********************** settings for imx - reference *********************/ +static struct imx_reg const imx208_init_settings[] = { + { IMX_TOK_TERM, 0, 0} +}; + +struct imx_resolution imx208_res_preview[] = { + { + .desc = "imx208_1080p_30fps", + .regs = imx208_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x976_30fps", + .regs = imx208_1296x976_30fps, + .width = 1296, + .height = 976, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x736_30fps", + .regs = imx208_1296x736_30fps, + .width = 1296, + .height = 736, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_336x256_30fps", + .regs = imx208_336x256_30fps, + .width = 336, + .height = 256, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .skip_frames = 2, + .mipi_freq = 201600, + }, + { + .desc = "imx208_192x160_30fps", + .regs = imx208_192x160_30fps, + .width = 192, + .height = 160, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .skip_frames = 2, + .mipi_freq = 100800, + }, +}; + +struct imx_resolution imx208_res_still[] = { + { + .desc = "imx208_1080p_30fps", + .regs = imx208_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x976_30fps", + .regs = imx208_1296x976_30fps, + .width = 1296, + .height = 976, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x736_30fps", + .regs = imx208_1296x736_30fps, + .width = 1296, + .height = 736, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_336x256_30fps", + .regs = imx208_336x256_30fps, + .width = 336, + .height = 256, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .skip_frames = 2, + .mipi_freq = 201600, + }, + { + .desc = "imx208_192x160_30fps", + .regs = imx208_192x160_30fps, + .width = 192, + .height = 160, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .skip_frames = 2, + .mipi_freq = 100800, + }, +}; + +struct imx_resolution imx208_res_video[] = { + { + .desc = "imx208_1080p_30fps", + .regs = imx208_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x976_30fps", + .regs = imx208_1296x976_30fps, + .width = 1296, + .height = 976, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x736_30fps", + .regs = imx208_1296x736_30fps, + .width = 1296, + .height = 736, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_336x256_30fps", + .regs = imx208_336x256_30fps, + .width = 336, + .height = 256, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .skip_frames = 2, + .mipi_freq = 201600, + }, + { + .desc = "imx208_192x160_30fps", + .regs = imx208_192x160_30fps, + .width = 192, + .height = 160, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .skip_frames = 2, + .mipi_freq = 100800, + }, +}; +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx219.h b/drivers/staging/media/atomisp/i2c/imx/imx219.h new file mode 100644 index 0000000..52df582 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx219.h @@ -0,0 +1,227 @@ +#ifndef __IMX219_H__ +#define __IMX219_H__ +#include "common.h" + +#define IMX219_FRAME_LENGTH_LINES 0x0160 +#define IMX219_LINE_LENGTH_PIXELS 0x0162 +#define IMX219_HORIZONTAL_START_H 0x0164 +#define IMX219_VERTICAL_START_H 0x0168 +#define IMX219_HORIZONTAL_END_H 0x0166 +#define IMX219_VERTICAL_END_H 0x016A +#define IMX219_HORIZONTAL_OUTPUT_SIZE_H 0x016c +#define IMX219_VERTICAL_OUTPUT_SIZE_H 0x016E +#define IMX219_COARSE_INTEGRATION_TIME 0x015A +#define IMX219_IMG_ORIENTATION 0x0172 +#define IMX219_GLOBAL_GAIN 0x0157 +#define IMX219_DGC_ADJ 0x0158 + +#define IMX219_DGC_LEN 4 + +/************************** settings for imx *************************/ +static struct imx_reg const imx219_STILL_8M_30fps[] = { + {IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x0C}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x300A, 0xFF}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x300B, 0xFF}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x09}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x0114, 0x03}, /*CSI_LANE_MODE[1:0}*/ + {IMX_8BIT, 0x0128, 0x00}, /*DPHY_CNTRL*/ + {IMX_8BIT, 0x012A, 0x13}, /*EXCK_FREQ[15:8]*/ + {IMX_8BIT, 0x012B, 0x34}, /*EXCK_FREQ[7:0]*/ + {IMX_8BIT, 0x0160, 0x0A}, /*FRM_LENGTH_A[15:8]*/ + {IMX_8BIT, 0x0161, 0x94}, /*FRM_LENGTH_A[7:0]*/ + {IMX_8BIT, 0x0162, 0x0D}, /*LINE_LENGTH_A[15:8]*/ + {IMX_8BIT, 0x0163, 0x78}, /*LINE_LENGTH_A[7:0]*/ + {IMX_8BIT, 0x0164, 0x00}, /*X_ADD_STA_A[11:8]*/ + {IMX_8BIT, 0x0165, 0x00}, /*X_ADD_STA_A[7:0]*/ + {IMX_8BIT, 0x0166, 0x0C}, /*X_ADD_END_A[11:8]*/ + {IMX_8BIT, 0x0167, 0xCF}, /*X_ADD_END_A[7:0]*/ + {IMX_8BIT, 0x0168, 0x00}, /*Y_ADD_STA_A[11:8]*/ + {IMX_8BIT, 0x0169, 0x00}, /*Y_ADD_STA_A[7:0]*/ + {IMX_8BIT, 0x016A, 0x09}, /*Y_ADD_END_A[11:8]*/ + {IMX_8BIT, 0x016B, 0x9F}, /*Y_ADD_END_A[7:0]*/ + {IMX_8BIT, 0x016C, 0x0C}, /*X_OUTPUT_SIZE_A[11:8]*/ + {IMX_8BIT, 0x016D, 0xD0}, /*X_OUTPUT_SIZE_A[7:0]*/ + {IMX_8BIT, 0x016E, 0x09}, /*Y_OUTPUT_SIZE_A[11:8]*/ + {IMX_8BIT, 0x016F, 0xA0}, /*Y_OUTPUT_SIZE_A[7:0]*/ + {IMX_8BIT, 0x0170, 0x01}, /*X_ODD_INC_A[2:0]*/ + {IMX_8BIT, 0x0171, 0x01}, /*Y_ODD_INC_A[2:0]*/ + {IMX_8BIT, 0x0174, 0x00}, /*BINNING_MODE_H_A*/ + {IMX_8BIT, 0x0175, 0x00}, /*BINNING_MODE_V_A*/ + {IMX_8BIT, 0x018C, 0x0A}, /*CSI_DATA_FORMAT_A[15:8]*/ + {IMX_8BIT, 0x018D, 0x0A}, /*CSI_DATA_FORMAT_A[7:0]*/ + {IMX_8BIT, 0x0301, 0x05}, /*VTPXCK_DIV*/ + {IMX_8BIT, 0x0303, 0x01}, /*VTSYCK_DIV*/ + {IMX_8BIT, 0x0304, 0x02}, /*PREPLLCK_VT_DIV[3:0]*/ + {IMX_8BIT, 0x0305, 0x02}, /*PREPLLCK_OP_DIV[3:0]*/ + {IMX_8BIT, 0x0306, 0x00}, /*PLL_VT_MPY[10:8]*/ + {IMX_8BIT, 0x0307, 0x49}, /*PLL_VT_MPY[7:0]*/ + {IMX_8BIT, 0x0309, 0x0A}, /*OPPXCK_DIV[4:0]*/ + {IMX_8BIT, 0x030B, 0x01}, /*OPSYCK_DIV*/ + {IMX_8BIT, 0x030C, 0x00}, /*PLL_OP_MPY[10:8]*/ + {IMX_8BIT, 0x030D, 0x4C}, /*PLL_OP_MPY[7:0]*/ + {IMX_8BIT, 0x4767, 0x0F}, /*CIS Tuning*/ + {IMX_8BIT, 0x4750, 0x14}, /*CIS Tuning*/ + {IMX_8BIT, 0x47B4, 0x14}, /*CIS Tuning*/ + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx219_STILL_6M_30fps[] = { + {IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x0C}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x300A, 0xFF}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x300B, 0xFF}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x09}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x0114, 0x03}, /*CSI_LANE_MODE[1:0}*/ + {IMX_8BIT, 0x0128, 0x00}, /*DPHY_CNTRL*/ + {IMX_8BIT, 0x012A, 0x13}, /*EXCK_FREQ[15:8]*/ + {IMX_8BIT, 0x012B, 0x34}, /*EXCK_FREQ[7:0]*/ + {IMX_8BIT, 0x0160, 0x07}, /*FRM_LENGTH_A[15:8]*/ + {IMX_8BIT, 0x0161, 0x64}, /*FRM_LENGTH_A[7:0]*/ + {IMX_8BIT, 0x0162, 0x0D}, /*LINE_LENGTH_A[15:8]*/ + {IMX_8BIT, 0x0163, 0x78}, /*LINE_LENGTH_A[7:0]*/ + {IMX_8BIT, 0x0164, 0x00}, /*X_ADD_STA_A[11:8]*/ + {IMX_8BIT, 0x0165, 0x00}, /*X_ADD_STA_A[7:0]*/ + {IMX_8BIT, 0x0166, 0x0C}, /*X_ADD_END_A[11:8]*/ + {IMX_8BIT, 0x0167, 0xCF}, /*X_ADD_END_A[7:0]*/ + {IMX_8BIT, 0x0168, 0x01}, /*Y_ADD_STA_A[11:8]*/ + {IMX_8BIT, 0x0169, 0x32}, /*Y_ADD_STA_A[7:0]*/ + {IMX_8BIT, 0x016A, 0x08}, /*Y_ADD_END_A[11:8]*/ + {IMX_8BIT, 0x016B, 0x6D}, /*Y_ADD_END_A[7:0]*/ + {IMX_8BIT, 0x016C, 0x0C}, /*X_OUTPUT_SIZE_A[11:8]*/ + {IMX_8BIT, 0x016D, 0xD0}, /*X_OUTPUT_SIZE_A[7:0]*/ + {IMX_8BIT, 0x016E, 0x07}, /*Y_OUTPUT_SIZE_A[11:8]*/ + {IMX_8BIT, 0x016F, 0x3C}, /*Y_OUTPUT_SIZE_A[7:0]*/ + {IMX_8BIT, 0x0170, 0x01}, /*X_ODD_INC_A[2:0]*/ + {IMX_8BIT, 0x0171, 0x01}, /*Y_ODD_INC_A[2:0]*/ + {IMX_8BIT, 0x0174, 0x00}, /*BINNING_MODE_H_A*/ + {IMX_8BIT, 0x0175, 0x00}, /*BINNING_MODE_V_A*/ + {IMX_8BIT, 0x018C, 0x0A}, /*CSI_DATA_FORMAT_A[15:8]*/ + {IMX_8BIT, 0x018D, 0x0A}, /*CSI_DATA_FORMAT_A[7:0]*/ + {IMX_8BIT, 0x0301, 0x05}, /*VTPXCK_DIV*/ + {IMX_8BIT, 0x0303, 0x01}, /*VTSYCK_DIV*/ + {IMX_8BIT, 0x0304, 0x02}, /*PREPLLCK_VT_DIV[3:0]*/ + {IMX_8BIT, 0x0305, 0x02}, /*PREPLLCK_OP_DIV[3:0]*/ + {IMX_8BIT, 0x0306, 0x00}, /*PLL_VT_MPY[10:8]*/ + {IMX_8BIT, 0x0307, 0x33}, /*PLL_VT_MPY[7:0]*/ + {IMX_8BIT, 0x0309, 0x0A}, /*OPPXCK_DIV[4:0]*/ + {IMX_8BIT, 0x030B, 0x01}, /*OPSYCK_DIV*/ + {IMX_8BIT, 0x030C, 0x00}, /*PLL_OP_MPY[10:8]*/ + {IMX_8BIT, 0x030D, 0x36}, /*PLL_OP_MPY[7:0]*/ + {IMX_8BIT, 0x4767, 0x0F}, /*CIS Tuning*/ + {IMX_8BIT, 0x4750, 0x14}, /*CIS Tuning*/ + {IMX_8BIT, 0x47B4, 0x14}, /*CIS Tuning*/ + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx219_init_settings[] = { + {IMX_TOK_TERM, 0, 0} +}; + +struct imx_resolution imx219_res_preview[] = { + { + .desc = "STILL_6M_30fps", + .regs = imx219_STILL_6M_30fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0764, + }, + { + } + }, + .mipi_freq = 259000, + }, + { + .desc = "STILL_8M_30fps", + .regs = imx219_STILL_8M_30fps, + .width = 3280, + .height = 2464, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0A94, + }, + { + } + }, + .mipi_freq = 365000, + }, +}; + +struct imx_resolution imx219_res_still[] = { + { + .desc = "STILL_6M_30fps", + .regs = imx219_STILL_6M_30fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0764, + }, + { + } + }, + .mipi_freq = 259000, + }, + { + .desc = "STILL_8M_30fps", + .regs = imx219_STILL_8M_30fps, + .width = 3280, + .height = 2464, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0A94, + }, + { + } + }, + .mipi_freq = 365000, + }, +}; + +struct imx_resolution imx219_res_video[] = { + { + .desc = "STILL_6M_30fps", + .regs = imx219_STILL_6M_30fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0764, + }, + { + } + }, + .mipi_freq = 259000, + }, +}; + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/imx227.h b/drivers/staging/media/atomisp/i2c/imx/imx227.h new file mode 100644 index 0000000..10e5b86 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx227.h @@ -0,0 +1,726 @@ +#ifndef __IMX227_H__ +#define __IMX227_H__ + +#include "common.h" + +#define IMX227_EMBEDDED_DATA_LINE_NUM 2 +#define IMX227_OUTPUT_DATA_FORMAT_REG 0x0112 +#define IMX227_OUTPUT_FORMAT_RAW10 0x0a0a + +/* AE Bracketing Registers */ +#define IMX227_BRACKETING_LUT_MODE_BIT_CONTINUE_STREAMING 0x1 +#define IMX227_BRACKETING_LUT_MODE_BIT_LOOP_MODE 0x2 + +#define IMX227_BRACKETING_LUT_CONTROL 0x0E00 +#define IMX227_BRACKETING_LUT_MODE 0x0E01 +#define IMX227_BRACKETING_LUT_ENTRY_CONTROL 0x0E02 + +/* + * The imx135 embedded data info: + * embedded data line num: 2 + * line 0 effective data size(byte): 76 + * line 1 effective data size(byte): 113 + */ +static const uint32_t +imx227_embedded_effective_size[IMX227_EMBEDDED_DATA_LINE_NUM] = {160, 62}; + +/************************** settings for imx *************************/ +/* Full Output Mode */ +static struct imx_reg const imx_STILL_6_5M_25fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x6259, 0x06}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xd0}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* 4:3 Output Mode */ +static struct imx_reg const imx_STILL_5_5M_3X4_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0xb0}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x00}, + {IMX_8BIT, 0x0348, 0x08}, + {IMX_8BIT, 0x0349, 0xaf}, + {IMX_8BIT, 0x034a, 0x0a}, + {IMX_8BIT, 0x034b, 0x9f}, + {IMX_8BIT, 0x034c, 0x08}, + {IMX_8BIT, 0x034d, 0x00}, + {IMX_8BIT, 0x034e, 0x0a}, + {IMX_8BIT, 0x034f, 0xa0}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xd8}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Square Output Mode */ +static struct imx_reg const imx_STILL_5_7M_1X1_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0xa0}, + {IMX_8BIT, 0x0348, 0x09}, + {IMX_8BIT, 0x0349, 0x5f}, + {IMX_8BIT, 0x034a, 0x09}, + {IMX_8BIT, 0x034b, 0xff}, + {IMX_8BIT, 0x034c, 0x09}, + {IMX_8BIT, 0x034d, 0x60}, + {IMX_8BIT, 0x034e, 0x09}, + {IMX_8BIT, 0x034f, 0x60}, + + {IMX_8BIT, 0x6259, 0x06}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xd4}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Full Frame 1080P Mode (use ISP scaler)*/ +static struct imx_reg const imx_VIDEO_4M_9X16_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xdc}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Cropped 1080P Mode */ +static struct imx_reg const imx_VIDEO_2M_9X16_45fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x02}, + {IMX_8BIT, 0x0345, 0x8a}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x88}, + {IMX_8BIT, 0x0348, 0x06}, + {IMX_8BIT, 0x0349, 0xd1}, + {IMX_8BIT, 0x034a, 0x09}, + {IMX_8BIT, 0x034b, 0x17}, + {IMX_8BIT, 0x034c, 0x04}, + {IMX_8BIT, 0x034d, 0x48}, + {IMX_8BIT, 0x034e, 0x07}, + {IMX_8BIT, 0x034f, 0x90}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x01}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x00}, + {IMX_8BIT, 0x040c, 0x04}, + {IMX_8BIT, 0x040d, 0x48}, + {IMX_8BIT, 0x040e, 0x07}, + {IMX_8BIT, 0x040f, 0x90}, + + {IMX_8BIT, 0x0900, 0x00}, + {IMX_8BIT, 0x0901, 0x00}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xdc}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Moment mode */ +static struct imx_reg const imx_VIDEO_1_3M_3X4_60fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xd9}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* High Speed 3:4 mode */ +static struct imx_reg const imx_VIDEO_VGA_3X4_120fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x9004, 0xca}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + + +/* Binned 720P mode */ +static struct imx_reg const imx_VIDEO_1M_9X16_60fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xd0}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x40}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0x8f}, + {IMX_8BIT, 0x034a, 0x0a}, + {IMX_8BIT, 0x034b, 0x5f}, + {IMX_8BIT, 0x034c, 0x02}, + {IMX_8BIT, 0x034d, 0xe0}, + {IMX_8BIT, 0x034e, 0x05}, + {IMX_8BIT, 0x034f, 0x10}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x01}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x00}, + {IMX_8BIT, 0x040c, 0x02}, + {IMX_8BIT, 0x040d, 0xe0}, + {IMX_8BIT, 0x040e, 0x05}, + {IMX_8BIT, 0x040f, 0x10}, + + {IMX_8BIT, 0x0900, 0x01}, + {IMX_8BIT, 0x0901, 0x22}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xdd}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Binned 496x868 mode */ +static struct imx_reg const imx_VIDEO_496x868_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x02}, + {IMX_8BIT, 0x0345, 0xc0}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0xec}, + {IMX_8BIT, 0x0348, 0x06}, + {IMX_8BIT, 0x0349, 0x9f}, + {IMX_8BIT, 0x034a, 0x08}, + {IMX_8BIT, 0x034b, 0xb3}, + {IMX_8BIT, 0x034c, 0x01}, + {IMX_8BIT, 0x034d, 0xf0}, + {IMX_8BIT, 0x034e, 0x03}, + {IMX_8BIT, 0x034f, 0x64}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x01}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x00}, + {IMX_8BIT, 0x040c, 0x01}, + {IMX_8BIT, 0x040d, 0xf0}, + {IMX_8BIT, 0x040e, 0x03}, + {IMX_8BIT, 0x040f, 0x64}, + + {IMX_8BIT, 0x0900, 0x01}, + {IMX_8BIT, 0x0901, 0x22}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xdd}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + + +/* Hangout mode */ +static struct imx_reg const imx_PREVIEW_374X652_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xc0}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x30}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0x9f}, + {IMX_8BIT, 0x034a, 0x0a}, + {IMX_8BIT, 0x034b, 0x6f}, + {IMX_8BIT, 0x034c, 0x01}, + {IMX_8BIT, 0x034d, 0x78}, + {IMX_8BIT, 0x034e, 0x02}, + {IMX_8BIT, 0x034f, 0x90}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x03}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x03}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x02}, + {IMX_8BIT, 0x040c, 0x01}, + {IMX_8BIT, 0x040d, 0x76}, + {IMX_8BIT, 0x040e, 0x02}, + {IMX_8BIT, 0x040f, 0x8c}, + + {IMX_8BIT, 0x0900, 0x01}, + {IMX_8BIT, 0x0901, 0x22}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xde}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_VIDEO_NHD_9X16_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xc0}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x30}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0x9f}, + {IMX_8BIT, 0x034a, 0x0a}, + {IMX_8BIT, 0x034b, 0x6f}, + {IMX_8BIT, 0x034c, 0x01}, + {IMX_8BIT, 0x034d, 0x78}, + {IMX_8BIT, 0x034e, 0x02}, + {IMX_8BIT, 0x034f, 0x90}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x03}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x03}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x00}, + {IMX_8BIT, 0x040c, 0x01}, + {IMX_8BIT, 0x040d, 0x78}, + {IMX_8BIT, 0x040e, 0x02}, + {IMX_8BIT, 0x040f, 0x90}, + + {IMX_8BIT, 0x0900, 0x01}, + {IMX_8BIT, 0x0901, 0x22}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xde}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + + +static struct imx_reg const imx227_init_settings[] = { + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0306, 0x00}, + {IMX_8BIT, 0x0307, 0xBB}, + {IMX_8BIT, 0x030E, 0x03}, + {IMX_8BIT, 0x030F, 0x0D}, + {IMX_8BIT, 0x463b, 0x30}, + {IMX_8BIT, 0x463e, 0x05}, + {IMX_8BIT, 0x4612, 0x66}, + {IMX_8BIT, 0x4815, 0x65}, + {IMX_8BIT, 0x4991, 0x00}, + {IMX_8BIT, 0x4992, 0x01}, + {IMX_8BIT, 0x4993, 0xff}, + {IMX_8BIT, 0x458b, 0x00}, + {IMX_8BIT, 0x452a, 0x02}, + {IMX_8BIT, 0x4a7c, 0x00}, + {IMX_8BIT, 0x4a7d, 0x1c}, + {IMX_8BIT, 0x4a7e, 0x00}, + {IMX_8BIT, 0x4a7f, 0x17}, + {IMX_8BIT, 0x462C, 0x2E}, + {IMX_8BIT, 0x461B, 0x28}, + {IMX_8BIT, 0x4663, 0x29}, + {IMX_8BIT, 0x461A, 0x7C}, + {IMX_8BIT, 0x4619, 0x28}, + {IMX_8BIT, 0x4667, 0x22}, + {IMX_8BIT, 0x466B, 0x23}, + {IMX_8BIT, 0x40AD, 0xFF}, + {IMX_8BIT, 0x40BE, 0x00}, + {IMX_8BIT, 0x40BF, 0x6E}, + {IMX_8BIT, 0x40CE, 0x00}, + {IMX_8BIT, 0x40CF, 0x0A}, + {IMX_8BIT, 0x40CA, 0x00}, + {IMX_8BIT, 0x40CB, 0x1F}, + {IMX_8BIT, 0x4D16, 0x00}, + {IMX_8BIT, 0x6204, 0x01}, + {IMX_8BIT, 0x6209, 0x00}, + {IMX_8BIT, 0x621F, 0x01}, + {IMX_8BIT, 0x621E, 0x10}, + GROUPED_PARAMETER_HOLD_DISABLE, + {IMX_TOK_TERM, 0, 0} +}; + +/* TODO settings of preview/still/video will be updated with new use case */ +struct imx_resolution imx227_res_preview[] = { + { + .desc = "imx_PREVIEW_374X652_30fps", + .regs = imx_PREVIEW_374X652_30fps, + .width = 374, + .height = 652, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C0A, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_496x868_30fps", + .regs = imx_VIDEO_496x868_30fps, + .width = 496, + .height = 868, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + } + }, + }, + { + .desc = "imx_STILL_5_5M_3X4_30fps", + .regs = imx_STILL_5_5M_3X4_30fps, + .width = 2048, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0ED8, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + + }, + { + .desc = "imx_STILL_5_7M_1X1_30fps", + .regs = imx_STILL_5_7M_1X1_30fps, + .width = 2400, + .height = 2400, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x1130, + .lines_per_frame = 0x0A1E, + }, + { + } + }, + + }, + { + .desc = "imx_STILL_6_5M_25fps", + .regs = imx_STILL_6_5M_25fps, + .width = 2400, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 25, + .pixels_per_line = 0x1130, + .lines_per_frame = 0x0C24, + }, + { + } + }, + } +}; + +struct imx_resolution imx227_res_still[] = { + { + .desc = "imx_STILL_5_5M_3X4_30fps", + .regs = imx_STILL_5_5M_3X4_30fps, + .width = 2048, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 6, + .pixels_per_line = 0x2130, + .lines_per_frame = 0x1A22, + }, + { + .fps = 30, + .pixels_per_line = 0x0ED8, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + + }, + { + .desc = "imx_STILL_5_7M_1X1_30fps", + .regs = imx_STILL_5_7M_1X1_30fps, + .width = 2400, + .height = 2400, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 6, + .pixels_per_line = 0x266E, + .lines_per_frame = 0x1704, + }, + { + .fps = 30, + .pixels_per_line = 0x1130, + .lines_per_frame = 0x0A1E, + }, + { + } + }, + + }, + { + .desc = "imx_STILL_6_5M_25fps", + .regs = imx_STILL_6_5M_25fps, + .width = 2400, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 25, + .pixels_per_line = 0x1130, + .lines_per_frame = 0x0C24, + }, + { + } + }, + }, +}; + +struct imx_resolution imx227_res_video[] = { + { + .desc = "imx_VIDEO_4M_9X16_30fps", + .regs = imx_VIDEO_4M_9X16_30fps, + .width = 1536, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + } + }, + + }, + { + .desc = "imx_VIDEO_2M_9X16_45fps", + .regs = imx_VIDEO_2M_9X16_45fps, + .width = 1096, + .height = 1936, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + .fps = 45, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0800, + }, + { + } + }, + + }, + { + .desc = "imx_VIDEO_1_3M_3X4_60fps", + .regs = imx_VIDEO_1_3M_3X4_60fps, + .width = 1024, + .height = 1360, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 60, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0604, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_496x868_30fps", + .regs = imx_VIDEO_496x868_30fps, + .width = 496, + .height = 868, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_1M_9X16_60fps", + .regs = imx_VIDEO_1M_9X16_60fps, + .width = 736, + .height = 1296, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 60, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0604, + }, + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C10, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_VGA_3X4_120fps", + .regs = imx_VIDEO_VGA_3X4_120fps, + .width = 512, + .height = 680, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 120, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0302, + }, + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_NHD_9X16_30fps", + .regs = imx_VIDEO_NHD_9X16_30fps, + .width = 376, + .height = 656, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C0A, + }, + { + } + }, + }, +}; + +#endif /* __IMX227_H__ */ diff --git a/drivers/staging/media/atomisp/i2c/imx/otp.c b/drivers/staging/media/atomisp/i2c/imx/otp.c new file mode 100644 index 0000000..4622750 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/otp.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/i2c.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/string.h> +#include <linux/types.h> +#include <media/v4l2-device.h> + +void *dummy_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 *buf; + + buf = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + return buf; +} diff --git a/drivers/staging/media/atomisp/i2c/imx/otp_brcc064_e2prom.c b/drivers/staging/media/atomisp/i2c/imx/otp_brcc064_e2prom.c new file mode 100644 index 0000000..b11f90c --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/otp_brcc064_e2prom.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/types.h> +#include <media/v4l2-device.h> +#include "common.h" + +/* + * Read EEPROM data from brcc064 and store + * it into a kmalloced buffer. On error return NULL. + * @size: set to the size of the returned EEPROM data. + */ +void *brcc064_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int e2prom_i2c_addr = dev_addr >> 1; + static const unsigned int max_read_size = 30; + int addr; + u32 s_addr = start_addr & E2PROM_ADDR_MASK; + unsigned char *buffer; + + buffer = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buffer) + return NULL; + + for (addr = s_addr; addr < size; addr += max_read_size) { + struct i2c_msg msg[2]; + unsigned int i2c_addr = e2prom_i2c_addr; + u16 addr_buf; + int r; + + msg[0].flags = 0; + msg[0].addr = i2c_addr; + addr_buf = cpu_to_be16(addr & 0xFFFF); + msg[0].len = 2; + msg[0].buf = (u8 *)&addr_buf; + + msg[1].addr = i2c_addr; + msg[1].flags = I2C_M_RD; + msg[1].len = min(max_read_size, size - addr); + msg[1].buf = &buffer[addr]; + + r = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); + if (r != ARRAY_SIZE(msg)) { + dev_err(&client->dev, "read failed at 0x%03x\n", addr); + return NULL; + } + } + return buffer; + +} + + diff --git a/drivers/staging/media/atomisp/i2c/imx/otp_e2prom.c b/drivers/staging/media/atomisp/i2c/imx/otp_e2prom.c new file mode 100644 index 0000000..73d041f --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/otp_e2prom.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/types.h> +#include <media/v4l2-device.h> +#include "common.h" + +/* + * Read EEPROM data from the gerneral e2prom chip(eg. + * CAT24C08, CAT24C128, le24l042cs, and store + * it into a kmalloced buffer. On error return NULL. + * @size: set to the size of the returned EEPROM data. + */ +void *e2prom_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int e2prom_i2c_addr = dev_addr >> 1; + static const unsigned int max_read_size = 30; + int addr; + u32 s_addr = start_addr & E2PROM_ADDR_MASK; + bool two_addr = (start_addr & E2PROM_2ADDR) >> 31; + char *buffer; + + buffer = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buffer) + return NULL; + + for (addr = s_addr; addr < size; addr += max_read_size) { + struct i2c_msg msg[2]; + unsigned int i2c_addr = e2prom_i2c_addr; + u16 addr_buf; + int r; + + msg[0].flags = 0; + if (two_addr) { + msg[0].addr = i2c_addr; + addr_buf = cpu_to_be16(addr & 0xFFFF); + msg[0].len = 2; + msg[0].buf = (u8 *)&addr_buf; + } else { + i2c_addr |= (addr >> 8) & 0x7; + msg[0].addr = i2c_addr; + addr_buf = addr & 0xFF; + msg[0].len = 1; + msg[0].buf = (u8 *)&addr_buf; + } + + msg[1].addr = i2c_addr; + msg[1].flags = I2C_M_RD; + msg[1].len = min(max_read_size, size - addr); + msg[1].buf = &buffer[addr]; + + r = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); + if (r != ARRAY_SIZE(msg)) { + dev_err(&client->dev, "read failed at 0x%03x\n", addr); + return NULL; + } + } + return buffer; +} + + diff --git a/drivers/staging/media/atomisp/i2c/imx/otp_imx.c b/drivers/staging/media/atomisp/i2c/imx/otp_imx.c new file mode 100644 index 0000000..1ca27c2 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/otp_imx.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/types.h> +#include <media/v4l2-device.h> +#include <asm/intel-mid.h> +#include "common.h" + +/* Defines for OTP Data Registers */ +#define IMX_OTP_START_ADDR 0x3B04 +#define IMX_OTP_PAGE_SIZE 64 +#define IMX_OTP_READY_REG 0x3B01 +#define IMX_OTP_PAGE_REG 0x3B02 +#define IMX_OTP_MODE_REG 0x3B00 +#define IMX_OTP_PAGE_MAX 20 +#define IMX_OTP_READY_REG_DONE 1 +#define IMX_OTP_READ_ONETIME 32 +#define IMX_OTP_MODE_READ 1 +#define IMX227_OTP_START_ADDR 0x0A04 +#define IMX227_OTP_ENABLE_REG 0x0A00 +#define IMX227_OTP_READY_REG 0x0A01 +#define IMX227_OTP_PAGE_REG 0x0A02 +#define IMX227_OTP_READY_REG_DONE 1 +#define IMX227_OTP_MODE_READ 1 + +static int +imx_read_otp_data(struct i2c_client *client, u16 len, u16 reg, void *val) +{ + struct i2c_msg msg[2]; + u16 data[IMX_SHORT_MAX] = { 0 }; + int err; + + if (len > IMX_BYTE_MAX) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0 , sizeof(msg)); + memset(data, 0 , sizeof(data)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = (u8 *)data; + /* high byte goes first */ + data[0] = cpu_to_be16(reg); + + msg[1].addr = client->addr; + msg[1].len = len; + msg[1].flags = I2C_M_RD; + msg[1].buf = (u8 *)data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + goto error; + } + + memcpy(val, data, len); + return 0; + +error: + dev_err(&client->dev, "read from offset 0x%x error %d", reg, err); + return err; +} + +static int imx_read_otp_reg_array(struct i2c_client *client, u16 size, u16 addr, + u8 *buf) +{ + u16 index; + int ret; + + for (index = 0; index + IMX_OTP_READ_ONETIME <= size; + index += IMX_OTP_READ_ONETIME) { + ret = imx_read_otp_data(client, IMX_OTP_READ_ONETIME, + addr + index, &buf[index]); + if (ret) + return ret; + } + return 0; +} + +void *imx_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 *buf; + int ret; + int i; + + buf = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < IMX_OTP_PAGE_MAX; i++) { + + /*set page NO.*/ + ret = imx_write_reg(client, IMX_8BIT, + IMX_OTP_PAGE_REG, i & 0xff); + if (ret) + goto fail; + + /*set read mode*/ + ret = imx_write_reg(client, IMX_8BIT, + IMX_OTP_MODE_REG, IMX_OTP_MODE_READ); + if (ret) + goto fail; + + /* Reading the OTP data array */ + ret = imx_read_otp_reg_array(client, IMX_OTP_PAGE_SIZE, + IMX_OTP_START_ADDR, buf + i * IMX_OTP_PAGE_SIZE); + if (ret) + goto fail; + } + + return buf; +fail: + /* Driver has failed to find valid data */ + dev_err(&client->dev, "sensor found no valid OTP data\n"); + return ERR_PTR(ret); +} + +void *imx227_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 *buf; + int ret; + int i; + + buf = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < IMX_OTP_PAGE_MAX; i++) { + + /*set page NO.*/ + ret = imx_write_reg(client, IMX_8BIT, + IMX227_OTP_PAGE_REG, i & 0xff); + if (ret) + goto fail; + + /*set read mode*/ + ret = imx_write_reg(client, IMX_8BIT, + IMX227_OTP_ENABLE_REG, IMX227_OTP_MODE_READ); + if (ret) + goto fail; + + /* Reading the OTP data array */ + ret = imx_read_otp_reg_array(client, IMX_OTP_PAGE_SIZE, + IMX227_OTP_START_ADDR, buf + i * IMX_OTP_PAGE_SIZE); + if (ret) + goto fail; + } + + return buf; +fail: + /* Driver has failed to find valid data */ + dev_err(&client->dev, "sensor found no valid OTP data\n"); + return ERR_PTR(ret); +} + diff --git a/drivers/staging/media/atomisp/i2c/imx/vcm.c b/drivers/staging/media/atomisp/i2c/imx/vcm.c new file mode 100644 index 0000000..2d2df04 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/vcm.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <linux/errno.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <media/v4l2-device.h> +#include "../../include/linux/atomisp_platform.h" + +int vcm_power_up(struct v4l2_subdev *sd) +{ + const struct camera_af_platform_data *vcm_platform_data; + + vcm_platform_data = camera_get_af_platform_data(); + if (NULL == vcm_platform_data) + return -ENODEV; + /* Enable power */ + return vcm_platform_data->power_ctrl(sd, 1); +} + +int vcm_power_down(struct v4l2_subdev *sd) +{ + const struct camera_af_platform_data *vcm_platform_data; + + vcm_platform_data = camera_get_af_platform_data(); + if (NULL == vcm_platform_data) + return -ENODEV; + return vcm_platform_data->power_ctrl(sd, 0); +} + |
