diff options
Diffstat (limited to 'drivers/staging/dgnc/dgnc_neo.h')
| -rw-r--r-- | drivers/staging/dgnc/dgnc_neo.h | 85 |
1 files changed, 51 insertions, 34 deletions
diff --git a/drivers/staging/dgnc/dgnc_neo.h b/drivers/staging/dgnc/dgnc_neo.h index 77ecd9b..c30a2c2 100644 --- a/drivers/staging/dgnc/dgnc_neo.h +++ b/drivers/staging/dgnc/dgnc_neo.h @@ -13,43 +13,62 @@ * PURPOSE. See the GNU General Public License for more details. */ -#ifndef __DGNC_NEO_H -#define __DGNC_NEO_H +#ifndef _DGNC_NEO_H +#define _DGNC_NEO_H #include "dgnc_driver.h" -/* - * Per channel/port NEO UART structure - * Base Structure Entries Usage Meanings to Host +/** + * struct neo_uart_struct - Per channel/port NEO UART structure + * + * key - W = read write + * - R = read only + * - U = unused * - * W = read write R = read only - * U = Unused. + * @txrx: (RW) Holding Register. + * @ier: (RW) Interrupt Enable Register. + * @isr_fcr: (RW) Interrupt Status Reg/Fifo Control Register. + * @lcr: (RW) Line Control Register. + * @mcr: (RW) Modem Control Register. + * @lsr: (RW) Line Status Register. + * @msr: (RW) Modem Status Register. + * @spr: (RW) Scratch Pad Register. + * @fctr: (RW) Feature Control Register. + * @efr: (RW) Enhanced Function Register. + * @tfifo: (RW) Transmit FIFO Register. + * @rfifo: (RW) Receive FIFO Register. + * @xoffchar1: (RW) XOff Character 1 Register. + * @xoffchar2: (RW) XOff Character 2 Register. + * @xonchar1: (RW) Xon Character 1 Register. + * @xonchar2: (RW) XOn Character 2 Register. + * @reserved1: (U) Reserved by Exar. + * @txrxburst: (RW) 64 bytes of RX/TX FIFO Data. + * @reserved2: (U) Reserved by Exar. + * @rxburst_with_errors: (R) bytes of RX FIFO Data + LSR. */ - struct neo_uart_struct { - u8 txrx; /* WR RHR/THR - Holding Reg */ - u8 ier; /* WR IER - Interrupt Enable Reg */ - u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo - * Control Reg - */ - u8 lcr; /* WR LCR - Line Control Reg */ - u8 mcr; /* WR MCR - Modem Control Reg */ - u8 lsr; /* WR LSR - Line Status Reg */ - u8 msr; /* WR MSR - Modem Status Reg */ - u8 spr; /* WR SPR - Scratch Pad Reg */ - u8 fctr; /* WR FCTR - Feature Control Reg */ - u8 efr; /* WR EFR - Enhanced Function Reg */ - u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */ - u8 rfifo; /* WR RXCNT/RXTRG - Receive FIFO Reg */ - u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */ - u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */ - u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */ - u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */ - - u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */ - u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */ - u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */ - u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */ + u8 txrx; + u8 ier; + u8 isr_fcr; + + u8 lcr; + u8 mcr; + u8 lsr; + u8 msr; + u8 spr; + u8 fctr; + u8 efr; + u8 tfifo; + u8 rfifo; + u8 xoffchar1; + u8 xoffchar2; + u8 xonchar1; + u8 xonchar2; + + u8 reserved1[0x2ff - 0x200]; + u8 txrxburst[64]; + u8 reserved2[0x37f - 0x340]; + u8 rxburst_with_errors[64]; }; /* Where to read the extended interrupt register (32bits instead of 8bits) */ @@ -151,8 +170,6 @@ struct neo_uart_struct { #define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */ #define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */ -/* Our Global Variables */ - extern struct board_ops dgnc_neo_ops; -#endif +#endif /* _DGNC_NEO_H */ |
