diff options
Diffstat (limited to 'drivers/staging/comedi/drivers/cb_pcimdas.c')
-rw-r--r-- | drivers/staging/comedi/drivers/cb_pcimdas.c | 370 |
1 files changed, 289 insertions, 81 deletions
diff --git a/drivers/staging/comedi/drivers/cb_pcimdas.c b/drivers/staging/comedi/drivers/cb_pcimdas.c index 70dd2c9..c458e50 100644 --- a/drivers/staging/comedi/drivers/cb_pcimdas.c +++ b/drivers/staging/comedi/drivers/cb_pcimdas.c @@ -42,37 +42,112 @@ */ #include <linux/module.h> -#include <linux/pci.h> #include <linux/interrupt.h> -#include "../comedidev.h" +#include "../comedi_pci.h" +#include "comedi_8254.h" #include "plx9052.h" #include "8255.h" -/* Registers for the PCIM-DAS1602/16 and PCIe-DAS1602/16 */ - -/* DAC Offsets */ -#define ADC_TRIG 0 -#define DAC0_OFFSET 2 -#define DAC1_OFFSET 4 - -/* AI and Counter Constants */ -#define MUX_LIMITS 0 -#define MAIN_CONN_DIO 1 -#define ADC_STAT 2 -#define ADC_CONV_STAT 3 -#define ADC_INT 4 -#define ADC_PACER 5 -#define BURST_MODE 6 -#define PROG_GAIN 7 -#define CLK8254_1_DATA 8 -#define CLK8254_2_DATA 9 -#define CLK8254_3_DATA 10 -#define CLK8254_CONTROL 11 -#define USER_COUNTER 12 -#define RESID_COUNT_H 13 -#define RESID_COUNT_L 14 +/* + * PCI Bar 1 Register map + * see plx9052.h for register and bit defines + */ + +/* + * PCI Bar 2 Register map (devpriv->daqio) + */ +#define PCIMDAS_AI_REG 0x00 +#define PCIMDAS_AI_SOFTTRIG_REG 0x00 +#define PCIMDAS_AO_REG(x) (0x02 + ((x) * 2)) + +/* + * PCI Bar 3 Register map (devpriv->BADR3) + */ +#define PCIMDAS_MUX_REG 0x00 +#define PCIMDAS_MUX(_lo, _hi) ((_lo) | ((_hi) << 4)) +#define PCIMDAS_DI_DO_REG 0x01 +#define PCIMDAS_STATUS_REG 0x02 +#define PCIMDAS_STATUS_EOC BIT(7) +#define PCIMDAS_STATUS_UB BIT(6) +#define PCIMDAS_STATUS_MUX BIT(5) +#define PCIMDAS_STATUS_CLK BIT(4) +#define PCIMDAS_STATUS_TO_CURR_MUX(x) ((x) & 0xf) +#define PCIMDAS_CONV_STATUS_REG 0x03 +#define PCIMDAS_CONV_STATUS_EOC BIT(7) +#define PCIMDAS_CONV_STATUS_EOB BIT(6) +#define PCIMDAS_CONV_STATUS_EOA BIT(5) +#define PCIMDAS_CONV_STATUS_FNE BIT(4) +#define PCIMDAS_CONV_STATUS_FHF BIT(3) +#define PCIMDAS_CONV_STATUS_OVERRUN BIT(2) +#define PCIMDAS_IRQ_REG 0x04 +#define PCIMDAS_IRQ_INTE BIT(7) +#define PCIMDAS_IRQ_INT BIT(6) +#define PCIMDAS_IRQ_OVERRUN BIT(4) +#define PCIMDAS_IRQ_EOA BIT(3) +#define PCIMDAS_IRQ_EOA_INT_SEL BIT(2) +#define PCIMDAS_IRQ_INTSEL(x) ((x) << 0) +#define PCIMDAS_IRQ_INTSEL_EOC PCIMDAS_IRQ_INTSEL(0) +#define PCIMDAS_IRQ_INTSEL_FNE PCIMDAS_IRQ_INTSEL(1) +#define PCIMDAS_IRQ_INTSEL_EOB PCIMDAS_IRQ_INTSEL(2) +#define PCIMDAS_IRQ_INTSEL_FHF_EOA PCIMDAS_IRQ_INTSEL(3) +#define PCIMDAS_PACER_REG 0x05 +#define PCIMDAS_PACER_GATE_STATUS BIT(6) +#define PCIMDAS_PACER_GATE_POL BIT(5) +#define PCIMDAS_PACER_GATE_LATCH BIT(4) +#define PCIMDAS_PACER_GATE_EN BIT(3) +#define PCIMDAS_PACER_EXT_PACER_POL BIT(2) +#define PCIMDAS_PACER_SRC(x) ((x) << 0) +#define PCIMDAS_PACER_SRC_POLLED PCIMDAS_PACER_SRC(0) +#define PCIMDAS_PACER_SRC_EXT PCIMDAS_PACER_SRC(2) +#define PCIMDAS_PACER_SRC_INT PCIMDAS_PACER_SRC(3) +#define PCIMDAS_PACER_SRC_MASK (3 << 0) +#define PCIMDAS_BURST_REG 0x06 +#define PCIMDAS_BURST_BME BIT(1) +#define PCIMDAS_BURST_CONV_EN BIT(0) +#define PCIMDAS_GAIN_REG 0x07 +#define PCIMDAS_8254_BASE 0x08 +#define PCIMDAS_USER_CNTR_REG 0x0c +#define PCIMDAS_USER_CNTR_CTR1_CLK_SEL BIT(0) +#define PCIMDAS_RESIDUE_MSB_REG 0x0d +#define PCIMDAS_RESIDUE_LSB_REG 0x0e + +/* + * PCI Bar 4 Register map (dev->iobase) + */ +#define PCIMDAS_8255_BASE 0x00 + +static const struct comedi_lrange cb_pcimdas_ai_bip_range = { + 4, { + BIP_RANGE(10), + BIP_RANGE(5), + BIP_RANGE(2.5), + BIP_RANGE(1.25) + } +}; + +static const struct comedi_lrange cb_pcimdas_ai_uni_range = { + 4, { + UNI_RANGE(10), + UNI_RANGE(5), + UNI_RANGE(2.5), + UNI_RANGE(1.25) + } +}; + +/* + * The Analog Output range is not programmable. The DAC ranges are + * jumper-settable on the board. The settings are not software-readable. + */ +static const struct comedi_lrange cb_pcimdas_ao_range = { + 4, { + BIP_RANGE(10), + BIP_RANGE(5), + UNI_RANGE(10), + UNI_RANGE(5) + } +}; /* * this structure is for data unique to this hardware driver. If @@ -94,59 +169,47 @@ static int cb_pcimdas_ai_eoc(struct comedi_device *dev, struct cb_pcimdas_private *devpriv = dev->private; unsigned int status; - status = inb(devpriv->BADR3 + 2); - if ((status & 0x80) == 0) + status = inb(devpriv->BADR3 + PCIMDAS_STATUS_REG); + if ((status & PCIMDAS_STATUS_EOC) == 0) return 0; return -EBUSY; } -static int cb_pcimdas_ai_rinsn(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int cb_pcimdas_ai_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { struct cb_pcimdas_private *devpriv = dev->private; + unsigned int chan = CR_CHAN(insn->chanspec); + unsigned int range = CR_RANGE(insn->chanspec); int n; unsigned int d; - int chan = CR_CHAN(insn->chanspec); - unsigned short chanlims; - int maxchans; int ret; /* only support sw initiated reads from a single channel */ - /* check channel number */ - if ((inb(devpriv->BADR3 + 2) & 0x20) == 0) /* differential mode */ - maxchans = s->n_chan / 2; - else - maxchans = s->n_chan; - - if (chan > (maxchans - 1)) - return -ETIMEDOUT; /* *** Wrong error code. Fixme. */ - /* configure for sw initiated read */ - d = inb(devpriv->BADR3 + 5); - if ((d & 0x03) > 0) { /* only reset if needed. */ - d = d & 0xfd; - outb(d, devpriv->BADR3 + 5); + d = inb(devpriv->BADR3 + PCIMDAS_PACER_REG); + if ((d & PCIMDAS_PACER_SRC_MASK) != PCIMDAS_PACER_SRC_POLLED) { + d &= ~PCIMDAS_PACER_SRC_MASK; + d |= PCIMDAS_PACER_SRC_POLLED; + outb(d, devpriv->BADR3 + PCIMDAS_PACER_REG); } /* set bursting off, conversions on */ - outb(0x01, devpriv->BADR3 + 6); + outb(PCIMDAS_BURST_CONV_EN, devpriv->BADR3 + PCIMDAS_BURST_REG); - /* set range to 10V. UP/BP is controlled by a switch on the board */ - outb(0x00, devpriv->BADR3 + 7); + /* set range */ + outb(range, devpriv->BADR3 + PCIMDAS_GAIN_REG); - /* - * write channel limits to multiplexer, set Low (bits 0-3) and - * High (bits 4-7) channels to chan. - */ - chanlims = chan | (chan << 4); - outb(chanlims, devpriv->BADR3 + 0); + /* set mux for single channel scan */ + outb(PCIMDAS_MUX(chan, chan), devpriv->BADR3 + PCIMDAS_MUX_REG); /* convert n samples */ for (n = 0; n < insn->n; n++) { /* trigger conversion */ - outw(0, devpriv->daqio + 0); + outw(0, devpriv->daqio + PCIMDAS_AI_SOFTTRIG_REG); /* wait for conversion to end */ ret = comedi_timeout(dev, s, insn, cb_pcimdas_ai_eoc, 0); @@ -154,7 +217,7 @@ static int cb_pcimdas_ai_rinsn(struct comedi_device *dev, return ret; /* read data */ - data[n] = inw(devpriv->daqio + 0); + data[n] = inw(devpriv->daqio + PCIMDAS_AI_REG); } /* return the number of samples read/written */ @@ -169,20 +232,128 @@ static int cb_pcimdas_ao_insn_write(struct comedi_device *dev, struct cb_pcimdas_private *devpriv = dev->private; unsigned int chan = CR_CHAN(insn->chanspec); unsigned int val = s->readback[chan]; - unsigned int reg = (chan) ? DAC1_OFFSET : DAC0_OFFSET; int i; for (i = 0; i < insn->n; i++) { val = data[i]; - outw(val, devpriv->daqio + reg); + outw(val, devpriv->daqio + PCIMDAS_AO_REG(chan)); } s->readback[chan] = val; return insn->n; } +static int cb_pcimdas_di_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + struct cb_pcimdas_private *devpriv = dev->private; + unsigned int val; + + val = inb(devpriv->BADR3 + PCIMDAS_DI_DO_REG); + + data[1] = val & 0x0f; + + return insn->n; +} + +static int cb_pcimdas_do_insn_write(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + struct cb_pcimdas_private *devpriv = dev->private; + + if (comedi_dio_update_state(s, data)) + outb(s->state, devpriv->BADR3 + PCIMDAS_DI_DO_REG); + + data[1] = s->state; + + return insn->n; +} + +static int cb_pcimdas_counter_insn_config(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + struct cb_pcimdas_private *devpriv = dev->private; + unsigned int ctrl; + + switch (data[0]) { + case INSN_CONFIG_SET_CLOCK_SRC: + switch (data[1]) { + case 0: /* internal 100 kHz clock */ + ctrl = PCIMDAS_USER_CNTR_CTR1_CLK_SEL; + break; + case 1: /* external clk on pin 21 */ + ctrl = 0; + break; + default: + return -EINVAL; + } + outb(ctrl, devpriv->BADR3 + PCIMDAS_USER_CNTR_REG); + break; + case INSN_CONFIG_GET_CLOCK_SRC: + ctrl = inb(devpriv->BADR3 + PCIMDAS_USER_CNTR_REG); + if (ctrl & PCIMDAS_USER_CNTR_CTR1_CLK_SEL) { + data[1] = 0; + data[2] = I8254_OSC_BASE_100KHZ; + } else { + data[1] = 1; + data[2] = 0; + } + break; + default: + return -EINVAL; + } + + return insn->n; +} + +static unsigned int cb_pcimdas_pacer_clk(struct comedi_device *dev) +{ + struct cb_pcimdas_private *devpriv = dev->private; + unsigned int status; + + /* The Pacer Clock jumper selects a 10 MHz or 1 MHz clock */ + status = inb(devpriv->BADR3 + PCIMDAS_STATUS_REG); + if (status & PCIMDAS_STATUS_CLK) + return I8254_OSC_BASE_10MHZ; + return I8254_OSC_BASE_1MHZ; +} + +static bool cb_pcimdas_is_ai_se(struct comedi_device *dev) +{ + struct cb_pcimdas_private *devpriv = dev->private; + unsigned int status; + + /* + * The number of Analog Input channels is set with the + * Analog Input Mode Switch on the board. The board can + * have 16 single-ended or 8 differential channels. + */ + status = inb(devpriv->BADR3 + PCIMDAS_STATUS_REG); + return status & PCIMDAS_STATUS_MUX; +} + +static bool cb_pcimdas_is_ai_uni(struct comedi_device *dev) +{ + struct cb_pcimdas_private *devpriv = dev->private; + unsigned int status; + + /* + * The Analog Input range polarity is set with the + * Analog Input Polarity Switch on the board. The + * inputs can be set to Unipolar or Bipolar ranges. + */ + status = inb(devpriv->BADR3 + PCIMDAS_STATUS_REG); + return status & PCIMDAS_STATUS_UB; +} + static int cb_pcimdas_auto_attach(struct comedi_device *dev, - unsigned long context_unused) + unsigned long context_unused) { struct pci_dev *pcidev = comedi_to_pci_dev(dev); struct cb_pcimdas_private *devpriv; @@ -201,42 +372,79 @@ static int cb_pcimdas_auto_attach(struct comedi_device *dev, devpriv->BADR3 = pci_resource_start(pcidev, 3); dev->iobase = pci_resource_start(pcidev, 4); - ret = comedi_alloc_subdevices(dev, 3); + dev->pacer = comedi_8254_init(devpriv->BADR3 + PCIMDAS_8254_BASE, + cb_pcimdas_pacer_clk(dev), + I8254_IO8, 0); + if (!dev->pacer) + return -ENOMEM; + + ret = comedi_alloc_subdevices(dev, 6); if (ret) return ret; + /* Analog Input subdevice */ s = &dev->subdevices[0]; - /* dev->read_subdev=s; */ - /* analog input subdevice */ - s->type = COMEDI_SUBD_AI; - s->subdev_flags = SDF_READABLE | SDF_GROUND; - s->n_chan = 16; - s->maxdata = 0xffff; - s->range_table = &range_unknown; - s->len_chanlist = 1; /* This is the maximum chanlist length that */ - /* the board can handle */ - s->insn_read = cb_pcimdas_ai_rinsn; + s->type = COMEDI_SUBD_AI; + s->subdev_flags = SDF_READABLE; + if (cb_pcimdas_is_ai_se(dev)) { + s->subdev_flags |= SDF_GROUND; + s->n_chan = 16; + } else { + s->subdev_flags |= SDF_DIFF; + s->n_chan = 8; + } + s->maxdata = 0xffff; + s->range_table = cb_pcimdas_is_ai_uni(dev) ? &cb_pcimdas_ai_uni_range + : &cb_pcimdas_ai_bip_range; + s->insn_read = cb_pcimdas_ai_insn_read; + /* Analog Output subdevice */ s = &dev->subdevices[1]; - /* analog output subdevice */ - s->type = COMEDI_SUBD_AO; - s->subdev_flags = SDF_WRITABLE; - s->n_chan = 2; - s->maxdata = 0xfff; - /* ranges are hardware settable, but not software readable. */ - s->range_table = &range_unknown; - s->insn_write = cb_pcimdas_ao_insn_write; + s->type = COMEDI_SUBD_AO; + s->subdev_flags = SDF_WRITABLE; + s->n_chan = 2; + s->maxdata = 0xfff; + s->range_table = &cb_pcimdas_ao_range; + s->insn_write = cb_pcimdas_ao_insn_write; ret = comedi_alloc_subdev_readback(s); if (ret) return ret; + /* Digital I/O subdevice */ s = &dev->subdevices[2]; - /* digital i/o subdevice */ - ret = subdev_8255_init(dev, s, NULL, 0x00); + ret = subdev_8255_init(dev, s, NULL, PCIMDAS_8255_BASE); if (ret) return ret; + /* Digital Input subdevice (main connector) */ + s = &dev->subdevices[3]; + s->type = COMEDI_SUBD_DI; + s->subdev_flags = SDF_READABLE; + s->n_chan = 4; + s->maxdata = 1; + s->range_table = &range_digital; + s->insn_read = cb_pcimdas_di_insn_read; + + /* Digital Output subdevice (main connector) */ + s = &dev->subdevices[4]; + s->type = COMEDI_SUBD_DO; + s->subdev_flags = SDF_WRITABLE; + s->n_chan = 4; + s->maxdata = 1; + s->range_table = &range_digital; + s->insn_write = cb_pcimdas_do_insn_write; + + /* Counter subdevice (8254) */ + s = &dev->subdevices[5]; + comedi_8254_subdevice_init(s, dev->pacer); + + dev->pacer->insn_config = cb_pcimdas_counter_insn_config; + + /* counters 1 and 2 are used internally for the pacer */ + comedi_8254_set_busy(dev->pacer, 1, true); + comedi_8254_set_busy(dev->pacer, 2, true); + return 0; } |