diff options
Diffstat (limited to 'drivers/staging/brcm80211/util')
-rw-r--r-- | drivers/staging/brcm80211/util/aiutils.c | 708 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/bcmotp.c | 965 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/bcmsrom.c | 2076 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/bcmutils.c | 1044 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/bcmwifi.c | 189 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/hnddma.c | 2690 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/hndpmu.c | 2693 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/linux_osl.c | 424 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/nicpci.c | 881 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/nvram/nvram_ro.c | 212 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/qmath.c | 681 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/sbutils.c | 585 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/siutils.c | 2021 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/siutils_priv.h | 32 |
14 files changed, 15201 insertions, 0 deletions
diff --git a/drivers/staging/brcm80211/util/aiutils.c b/drivers/staging/brcm80211/util/aiutils.c new file mode 100644 index 0000000..75a7e3a --- /dev/null +++ b/drivers/staging/brcm80211/util/aiutils.c @@ -0,0 +1,708 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <bcmdefs.h> +#include <osl.h> +#include <linuxver.h> +#include <bcmutils.h> +#include <siutils.h> +#include <hndsoc.h> +#include <sbchipc.h> +#include <pcicfg.h> +#include <bcmdevs.h> + +#define BCM47162_DMP() ((CHIPID(sih->chip) == BCM47162_CHIP_ID) && \ + (CHIPREV(sih->chiprev) == 0) && \ + (sii->coreid[sii->curidx] == MIPS74K_CORE_ID)) + +/* EROM parsing */ + +static u32 +get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match) +{ + u32 ent; + uint inv = 0, nom = 0; + + while (true) { + ent = R_REG(si_osh(sih), *eromptr); + (*eromptr)++; + + if (mask == 0) + break; + + if ((ent & ER_VALID) == 0) { + inv++; + continue; + } + + if (ent == (ER_END | ER_VALID)) + break; + + if ((ent & mask) == match) + break; + + nom++; + } + + SI_VMSG(("%s: Returning ent 0x%08x\n", __func__, ent)); + if (inv + nom) { + SI_VMSG((" after %d invalid and %d non-matching entries\n", + inv, nom)); + } + return ent; +} + +static u32 +get_asd(si_t *sih, u32 **eromptr, uint sp, uint ad, uint st, + u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh) +{ + u32 asd, sz, szd; + + asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID); + if (((asd & ER_TAG1) != ER_ADD) || + (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) || + ((asd & AD_ST_MASK) != st)) { + /* This is not what we want, "push" it back */ + (*eromptr)--; + return 0; + } + *addrl = asd & AD_ADDR_MASK; + if (asd & AD_AG32) + *addrh = get_erom_ent(sih, eromptr, 0, 0); + else + *addrh = 0; + *sizeh = 0; + sz = asd & AD_SZ_MASK; + if (sz == AD_SZ_SZD) { + szd = get_erom_ent(sih, eromptr, 0, 0); + *sizel = szd & SD_SZ_MASK; + if (szd & SD_SG32) + *sizeh = get_erom_ent(sih, eromptr, 0, 0); + } else + *sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT); + + SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n", + sp, ad, st, *sizeh, *sizel, *addrh, *addrl)); + + return asd; +} + +static void ai_hwfixup(si_info_t *sii) +{ +} + +/* parse the enumeration rom to identify all cores */ +void ai_scan(si_t *sih, void *regs, uint devid) +{ + si_info_t *sii = SI_INFO(sih); + chipcregs_t *cc = (chipcregs_t *) regs; + u32 erombase, *eromptr, *eromlim; + + erombase = R_REG(sii->osh, &cc->eromptr); + + switch (BUSTYPE(sih->bustype)) { + case SI_BUS: + eromptr = (u32 *) REG_MAP(erombase, SI_CORE_SIZE); + break; + + case PCI_BUS: + /* Set wrappers address */ + sii->curwrap = (void *)((unsigned long)regs + SI_CORE_SIZE); + + /* Now point the window at the erom */ + OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase); + eromptr = regs; + break; + +#ifdef BCMSDIO + case SPI_BUS: + case SDIO_BUS: +#endif /* BCMSDIO */ + eromptr = (u32 *)(unsigned long)erombase; + break; + + default: + SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n", + sih->bustype)); + ASSERT(0); + return; + } + eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32)); + + SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim)); + while (eromptr < eromlim) { + u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp; + u32 mpd, asd, addrl, addrh, sizel, sizeh; + u32 *base; + uint i, j, idx; + bool br; + + br = false; + + /* Grok a component */ + cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI); + if (cia == (ER_END | ER_VALID)) { + SI_VMSG(("Found END of erom after %d cores\n", + sii->numcores)); + ai_hwfixup(sii); + return; + } + base = eromptr - 1; + cib = get_erom_ent(sih, &eromptr, 0, 0); + + if ((cib & ER_TAG) != ER_CI) { + SI_ERROR(("CIA not followed by CIB\n")); + goto error; + } + + cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT; + mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT; + crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT; + nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT; + nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT; + nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT; + nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT; + + SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " "nsw = %d, nmp = %d & nsp = %d\n", mfg, cid, crev, base, nmw, nsw, nmp, nsp)); + + if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0)) + continue; + if ((nmw + nsw == 0)) { + /* A component which is not a core */ + if (cid == OOB_ROUTER_CORE_ID) { + asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, + &addrl, &addrh, &sizel, &sizeh); + if (asd != 0) { + sii->oob_router = addrl; + } + } + continue; + } + + idx = sii->numcores; +/* sii->eromptr[idx] = base; */ + sii->cia[idx] = cia; + sii->cib[idx] = cib; + sii->coreid[idx] = cid; + + for (i = 0; i < nmp; i++) { + mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID); + if ((mpd & ER_TAG) != ER_MP) { + SI_ERROR(("Not enough MP entries for component 0x%x\n", cid)); + goto error; + } + SI_VMSG((" Master port %d, mp: %d id: %d\n", i, + (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT, + (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT)); + } + + /* First Slave Address Descriptor should be port 0: + * the main register space for the core + */ + asd = + get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, + &sizel, &sizeh); + if (asd == 0) { + /* Try again to see if it is a bridge */ + asd = + get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, + &addrh, &sizel, &sizeh); + if (asd != 0) + br = true; + else if ((addrh != 0) || (sizeh != 0) + || (sizel != SI_CORE_SIZE)) { + SI_ERROR(("First Slave ASD for core 0x%04x malformed " "(0x%08x)\n", cid, asd)); + goto error; + } + } + sii->coresba[idx] = addrl; + sii->coresba_size[idx] = sizel; + /* Get any more ASDs in port 0 */ + j = 1; + do { + asd = + get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, + &addrh, &sizel, &sizeh); + if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) { + sii->coresba2[idx] = addrl; + sii->coresba2_size[idx] = sizel; + } + j++; + } while (asd != 0); + + /* Go through the ASDs for other slave ports */ + for (i = 1; i < nsp; i++) { + j = 0; + do { + asd = + get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE, + &addrl, &addrh, &sizel, &sizeh); + } while (asd != 0); + if (j == 0) { + SI_ERROR((" SP %d has no address descriptors\n", + i)); + goto error; + } + } + + /* Now get master wrappers */ + for (i = 0; i < nmw; i++) { + asd = + get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl, + &addrh, &sizel, &sizeh); + if (asd == 0) { + SI_ERROR(("Missing descriptor for MW %d\n", i)); + goto error; + } + if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) { + SI_ERROR(("Master wrapper %d is not 4KB\n", i)); + goto error; + } + if (i == 0) + sii->wrapba[idx] = addrl; + } + + /* And finally slave wrappers */ + for (i = 0; i < nsw; i++) { + uint fwp = (nsp == 1) ? 0 : 1; + asd = + get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP, + &addrl, &addrh, &sizel, &sizeh); + if (asd == 0) { + SI_ERROR(("Missing descriptor for SW %d\n", i)); + goto error; + } + if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) { + SI_ERROR(("Slave wrapper %d is not 4KB\n", i)); + goto error; + } + if ((nmw == 0) && (i == 0)) + sii->wrapba[idx] = addrl; + } + + /* Don't record bridges */ + if (br) + continue; + + /* Done with core */ + sii->numcores++; + } + + SI_ERROR(("Reached end of erom without finding END")); + + error: + sii->numcores = 0; + return; +} + +/* This function changes the logical "focus" to the indicated core. + * Return the current core's virtual address. + */ +void *ai_setcoreidx(si_t *sih, uint coreidx) +{ + si_info_t *sii = SI_INFO(sih); + u32 addr = sii->coresba[coreidx]; + u32 wrap = sii->wrapba[coreidx]; + void *regs; + + if (coreidx >= sii->numcores) + return NULL; + + /* + * If the user has provided an interrupt mask enabled function, + * then assert interrupts are disabled before switching the core. + */ + ASSERT((sii->intrsenabled_fn == NULL) + || !(*(sii)->intrsenabled_fn) ((sii)->intr_arg)); + + switch (BUSTYPE(sih->bustype)) { + case SI_BUS: + /* map new one */ + if (!sii->regs[coreidx]) { + sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE); + ASSERT(GOODREGS(sii->regs[coreidx])); + } + sii->curmap = regs = sii->regs[coreidx]; + if (!sii->wrappers[coreidx]) { + sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE); + ASSERT(GOODREGS(sii->wrappers[coreidx])); + } + sii->curwrap = sii->wrappers[coreidx]; + break; + + case PCI_BUS: + /* point bar0 window */ + OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, addr); + regs = sii->curmap; + /* point bar0 2nd 4KB window */ + OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, wrap); + break; + +#ifdef BCMSDIO + case SPI_BUS: + case SDIO_BUS: +#endif /* BCMSDIO */ + sii->curmap = regs = (void *)(unsigned long)addr; + sii->curwrap = (void *)(unsigned long)wrap; + break; + + default: + ASSERT(0); + regs = NULL; + break; + } + + sii->curmap = regs; + sii->curidx = coreidx; + + return regs; +} + +/* Return the number of address spaces in current core */ +int ai_numaddrspaces(si_t *sih) +{ + return 2; +} + +/* Return the address of the nth address space in the current core */ +u32 ai_addrspace(si_t *sih, uint asidx) +{ + si_info_t *sii; + uint cidx; + + sii = SI_INFO(sih); + cidx = sii->curidx; + + if (asidx == 0) + return sii->coresba[cidx]; + else if (asidx == 1) + return sii->coresba2[cidx]; + else { + SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx)); + return 0; + } +} + +/* Return the size of the nth address space in the current core */ +u32 ai_addrspacesize(si_t *sih, uint asidx) +{ + si_info_t *sii; + uint cidx; + + sii = SI_INFO(sih); + cidx = sii->curidx; + + if (asidx == 0) + return sii->coresba_size[cidx]; + else if (asidx == 1) + return sii->coresba2_size[cidx]; + else { + SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx)); + return 0; + } +} + +uint ai_flag(si_t *sih) +{ + si_info_t *sii; + aidmp_t *ai; + + sii = SI_INFO(sih); + if (BCM47162_DMP()) { + SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __func__)); + return sii->curidx; + } + ai = sii->curwrap; + + return R_REG(sii->osh, &ai->oobselouta30) & 0x1f; +} + +void ai_setint(si_t *sih, int siflag) +{ +} + +void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val) +{ + si_info_t *sii = SI_INFO(sih); + u32 *w = (u32 *) sii->curwrap; + W_REG(sii->osh, w + (offset / 4), val); + return; +} + +uint ai_corevendor(si_t *sih) +{ + si_info_t *sii; + u32 cia; + + sii = SI_INFO(sih); + cia = sii->cia[sii->curidx]; + return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT; +} + +uint ai_corerev(si_t *sih) +{ + si_info_t *sii; + u32 cib; + + sii = SI_INFO(sih); + cib = sii->cib[sii->curidx]; + return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT; +} + +bool ai_iscoreup(si_t *sih) +{ + si_info_t *sii; + aidmp_t *ai; + + sii = SI_INFO(sih); + ai = sii->curwrap; + + return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) == + SICF_CLOCK_EN) + && ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0)); +} + +/* + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation, + * switch back to the original core, and return the new value. + * + * When using the silicon backplane, no fiddling with interrupts or core switches is needed. + * + * Also, when using pci/pcie, we can optimize away the core switching for pci registers + * and (on newer pci cores) chipcommon registers. + */ +uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) +{ + uint origidx = 0; + u32 *r = NULL; + uint w; + uint intr_val = 0; + bool fast = false; + si_info_t *sii; + + sii = SI_INFO(sih); + + ASSERT(GOODIDX(coreidx)); + ASSERT(regoff < SI_CORE_SIZE); + ASSERT((val & ~mask) == 0); + + if (coreidx >= SI_MAXCORES) + return 0; + + if (BUSTYPE(sih->bustype) == SI_BUS) { + /* If internal bus, we can always get at everything */ + fast = true; + /* map if does not exist */ + if (!sii->regs[coreidx]) { + sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx], + SI_CORE_SIZE); + ASSERT(GOODREGS(sii->regs[coreidx])); + } + r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff); + } else if (BUSTYPE(sih->bustype) == PCI_BUS) { + /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */ + + if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) { + /* Chipc registers are mapped at 12KB */ + + fast = true; + r = (u32 *) ((char *)sii->curmap + + PCI_16KB0_CCREGS_OFFSET + regoff); + } else if (sii->pub.buscoreidx == coreidx) { + /* pci registers are at either in the last 2KB of an 8KB window + * or, in pcie and pci rev 13 at 8KB + */ + fast = true; + if (SI_FAST(sii)) + r = (u32 *) ((char *)sii->curmap + + PCI_16KB0_PCIREGS_OFFSET + + regoff); + else + r = (u32 *) ((char *)sii->curmap + + ((regoff >= SBCONFIGOFF) ? + PCI_BAR0_PCISBR_OFFSET : + PCI_BAR0_PCIREGS_OFFSET) + + regoff); + } + } + + if (!fast) { + INTR_OFF(sii, intr_val); + + /* save current core index */ + origidx = si_coreidx(&sii->pub); + + /* switch core */ + r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx) + + regoff); + } + ASSERT(r != NULL); + + /* mask and set */ + if (mask || val) { + w = (R_REG(sii->osh, r) & ~mask) | val; + W_REG(sii->osh, r, w); + } + + /* readback */ + w = R_REG(sii->osh, r); + + if (!fast) { + /* restore core index */ + if (origidx != coreidx) + ai_setcoreidx(&sii->pub, origidx); + + INTR_RESTORE(sii, intr_val); + } + + return w; +} + +void ai_core_disable(si_t *sih, u32 bits) +{ + si_info_t *sii; + volatile u32 dummy; + aidmp_t *ai; + + sii = SI_INFO(sih); + + ASSERT(GOODREGS(sii->curwrap)); + ai = sii->curwrap; + + /* if core is already in reset, just return */ + if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) + return; + + W_REG(sii->osh, &ai->ioctrl, bits); + dummy = R_REG(sii->osh, &ai->ioctrl); + udelay(10); + + W_REG(sii->osh, &ai->resetctrl, AIRC_RESET); + udelay(1); +} + +/* reset and re-enable a core + * inputs: + * bits - core specific bits that are set during and after reset sequence + * resetbits - core specific bits that are set only during reset sequence + */ +void ai_core_reset(si_t *sih, u32 bits, u32 resetbits) +{ + si_info_t *sii; + aidmp_t *ai; + volatile u32 dummy; + + sii = SI_INFO(sih); + ASSERT(GOODREGS(sii->curwrap)); + ai = sii->curwrap; + + /* + * Must do the disable sequence first to work for arbitrary current core state. + */ + ai_core_disable(sih, (bits | resetbits)); + + /* + * Now do the initialization sequence. + */ + W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN)); + dummy = R_REG(sii->osh, &ai->ioctrl); + W_REG(sii->osh, &ai->resetctrl, 0); + udelay(1); + + W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN)); + dummy = R_REG(sii->osh, &ai->ioctrl); + udelay(1); +} + +void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val) +{ + si_info_t *sii; + aidmp_t *ai; + u32 w; + + sii = SI_INFO(sih); + + if (BCM47162_DMP()) { + SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0", + __func__)); + return; + } + + ASSERT(GOODREGS(sii->curwrap)); + ai = sii->curwrap; + + ASSERT((val & ~mask) == 0); + + if (mask || val) { + w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val); + W_REG(sii->osh, &ai->ioctrl, w); + } +} + +u32 ai_core_cflags(si_t *sih, u32 mask, u32 val) +{ + si_info_t *sii; + aidmp_t *ai; + u32 w; + + sii = SI_INFO(sih); + if (BCM47162_DMP()) { + SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0", + __func__)); + return 0; + } + + ASSERT(GOODREGS(sii->curwrap)); + ai = sii->curwrap; + + ASSERT((val & ~mask) == 0); + + if (mask || val) { + w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val); + W_REG(sii->osh, &ai->ioctrl, w); + } + + return R_REG(sii->osh, &ai->ioctrl); +} + +u32 ai_core_sflags(si_t *sih, u32 mask, u32 val) +{ + si_info_t *sii; + aidmp_t *ai; + u32 w; + + sii = SI_INFO(sih); + if (BCM47162_DMP()) { + SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0", __func__)); + return 0; + } + + ASSERT(GOODREGS(sii->curwrap)); + ai = sii->curwrap; + + ASSERT((val & ~mask) == 0); + ASSERT((mask & ~SISF_CORE_BITS) == 0); + + if (mask || val) { + w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val); + W_REG(sii->osh, &ai->iostatus, w); + } + + return R_REG(sii->osh, &ai->iostatus); +} + diff --git a/drivers/staging/brcm80211/util/bcmotp.c b/drivers/staging/brcm80211/util/bcmotp.c new file mode 100644 index 0000000..c909832 --- /dev/null +++ b/drivers/staging/brcm80211/util/bcmotp.c @@ -0,0 +1,965 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <bcmdefs.h> +#include <osl.h> +#include <linuxver.h> +#include <bcmdevs.h> +#include <bcmutils.h> +#include <siutils.h> +#include <bcmendian.h> +#include <hndsoc.h> +#include <sbchipc.h> +#include <bcmotp.h> +#include "siutils_priv.h" + +/* + * There are two different OTP controllers so far: + * 1. new IPX OTP controller: chipc 21, >=23 + * 2. older HND OTP controller: chipc 12, 17, 22 + * + * Define BCMHNDOTP to include support for the HND OTP controller. + * Define BCMIPXOTP to include support for the IPX OTP controller. + * + * NOTE 1: More than one may be defined + * NOTE 2: If none are defined, the default is to include them all. + */ + +#if !defined(BCMHNDOTP) && !defined(BCMIPXOTP) +#define BCMHNDOTP 1 +#define BCMIPXOTP 1 +#endif + +#define OTPTYPE_HND(ccrev) ((ccrev) < 21 || (ccrev) == 22) +#define OTPTYPE_IPX(ccrev) ((ccrev) == 21 || (ccrev) >= 23) + +#define OTPP_TRIES 10000000 /* # of tries for OTPP */ + +#ifdef BCMIPXOTP +#define MAXNUMRDES 9 /* Maximum OTP redundancy entries */ +#endif + +/* OTP common function type */ +typedef int (*otp_status_t) (void *oh); +typedef int (*otp_size_t) (void *oh); +typedef void *(*otp_init_t) (si_t *sih); +typedef u16(*otp_read_bit_t) (void *oh, chipcregs_t *cc, uint off); +typedef int (*otp_read_region_t) (si_t *sih, int region, u16 *data, + uint *wlen); +typedef int (*otp_nvread_t) (void *oh, char *data, uint *len); + +/* OTP function struct */ +typedef struct otp_fn_s { + otp_size_t size; + otp_read_bit_t read_bit; + otp_init_t init; + otp_read_region_t read_region; + otp_nvread_t nvread; + otp_status_t status; +} otp_fn_t; + +typedef struct { + uint ccrev; /* chipc revision */ + otp_fn_t *fn; /* OTP functions */ + si_t *sih; /* Saved sb handle */ + osl_t *osh; + +#ifdef BCMIPXOTP + /* IPX OTP section */ + u16 wsize; /* Size of otp in words */ + u16 rows; /* Geometry */ + u16 cols; /* Geometry */ + u32 status; /* Flag bits (lock/prog/rv). + * (Reflected only when OTP is power cycled) + */ + u16 hwbase; /* hardware subregion offset */ + u16 hwlim; /* hardware subregion boundary */ + u16 swbase; /* software subregion offset */ + u16 swlim; /* software subregion boundary */ + u16 fbase; /* fuse subregion offset */ + u16 flim; /* fuse subregion boundary */ + int otpgu_base; /* offset to General Use Region */ +#endif /* BCMIPXOTP */ + +#ifdef BCMHNDOTP + /* HND OTP section */ + uint size; /* Size of otp in bytes */ + uint hwprot; /* Hardware protection bits */ + uint signvalid; /* Signature valid bits */ + int boundary; /* hw/sw boundary */ +#endif /* BCMHNDOTP */ +} otpinfo_t; + +static otpinfo_t otpinfo; + +/* + * IPX OTP Code + * + * Exported functions: + * ipxotp_status() + * ipxotp_size() + * ipxotp_init() + * ipxotp_read_bit() + * ipxotp_read_region() + * ipxotp_nvread() + * + */ + +#ifdef BCMIPXOTP + +#define HWSW_RGN(rgn) (((rgn) == OTP_HW_RGN) ? "h/w" : "s/w") + +/* OTP layout */ +/* CC revs 21, 24 and 27 OTP General Use Region word offset */ +#define REVA4_OTPGU_BASE 12 + +/* CC revs 23, 25, 26, 28 and above OTP General Use Region word offset */ +#define REVB8_OTPGU_BASE 20 + +/* CC rev 36 OTP General Use Region word offset */ +#define REV36_OTPGU_BASE 12 + +/* Subregion word offsets in General Use region */ +#define OTPGU_HSB_OFF 0 +#define OTPGU_SFB_OFF 1 +#define OTPGU_CI_OFF 2 +#define OTPGU_P_OFF 3 +#define OTPGU_SROM_OFF 4 + +/* Flag bit offsets in General Use region */ +#define OTPGU_HWP_OFF 60 +#define OTPGU_SWP_OFF 61 +#define OTPGU_CIP_OFF 62 +#define OTPGU_FUSEP_OFF 63 +#define OTPGU_CIP_MSK 0x4000 +#define OTPGU_P_MSK 0xf000 +#define OTPGU_P_SHIFT (OTPGU_HWP_OFF % 16) + +/* OTP Size */ +#define OTP_SZ_FU_324 ((roundup(324, 8))/8) /* 324 bits */ +#define OTP_SZ_FU_288 (288/8) /* 288 bits */ +#define OTP_SZ_FU_216 (216/8) /* 216 bits */ +#define OTP_SZ_FU_72 (72/8) /* 72 bits */ +#define OTP_SZ_CHECKSUM (16/8) /* 16 bits */ +#define OTP4315_SWREG_SZ 178 /* 178 bytes */ +#define OTP_SZ_FU_144 (144/8) /* 144 bits */ + +static int ipxotp_status(void *oh) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + return (int)(oi->status); +} + +/* Return size in bytes */ +static int ipxotp_size(void *oh) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + return (int)oi->wsize * 2; +} + +static u16 ipxotp_otpr(void *oh, chipcregs_t *cc, uint wn) +{ + otpinfo_t *oi; + + oi = (otpinfo_t *) oh; + + ASSERT(wn < oi->wsize); + ASSERT(cc != NULL); + + return R_REG(oi->osh, &cc->sromotp[wn]); +} + +static u16 ipxotp_read_bit(void *oh, chipcregs_t *cc, uint off) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + uint k, row, col; + u32 otpp, st; + + row = off / oi->cols; + col = off % oi->cols; + + otpp = OTPP_START_BUSY | + ((OTPPOC_READ << OTPP_OC_SHIFT) & OTPP_OC_MASK) | + ((row << OTPP_ROW_SHIFT) & OTPP_ROW_MASK) | + ((col << OTPP_COL_SHIFT) & OTPP_COL_MASK); + W_REG(oi->osh, &cc->otpprog, otpp); + + for (k = 0; + ((st = R_REG(oi->osh, &cc->otpprog)) & OTPP_START_BUSY) + && (k < OTPP_TRIES); k++) + ; + if (k >= OTPP_TRIES) { + return 0xffff; + } + if (st & OTPP_READERR) { + return 0xffff; + } + st = (st & OTPP_VALUE_MASK) >> OTPP_VALUE_SHIFT; + + return (int)st; +} + +/* Calculate max HW/SW region byte size by substracting fuse region and checksum size, + * osizew is oi->wsize (OTP size - GU size) in words + */ +static int ipxotp_max_rgnsz(si_t *sih, int osizew) +{ + int ret = 0; + + switch (CHIPID(sih->chip)) { + case BCM43224_CHIP_ID: + case BCM43225_CHIP_ID: + ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM; + break; + case BCM4313_CHIP_ID: + ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM; + break; + default: + ASSERT(0); /* Don't konw about this chip */ + } + + return ret; +} + +static void _ipxotp_init(otpinfo_t *oi, chipcregs_t *cc) +{ + uint k; + u32 otpp, st; + + /* record word offset of General Use Region for various chipcommon revs */ + if (oi->sih->ccrev == 21 || oi->sih->ccrev == 24 + || oi->sih->ccrev == 27) { + oi->otpgu_base = REVA4_OTPGU_BASE; + } else if (oi->sih->ccrev == 36) { + /* OTP size greater than equal to 2KB (128 words), otpgu_base is similar to rev23 */ + if (oi->wsize >= 128) + oi->otpgu_base = REVB8_OTPGU_BASE; + else + oi->otpgu_base = REV36_OTPGU_BASE; + } else if (oi->sih->ccrev == 23 || oi->sih->ccrev >= 25) { + oi->otpgu_base = REVB8_OTPGU_BASE; + } + + /* First issue an init command so the status is up to date */ + otpp = + OTPP_START_BUSY | ((OTPPOC_INIT << OTPP_OC_SHIFT) & OTPP_OC_MASK); + + W_REG(oi->osh, &cc->otpprog, otpp); + for (k = 0; + ((st = R_REG(oi->osh, &cc->otpprog)) & OTPP_START_BUSY) + && (k < OTPP_TRIES); k++) + ; + if (k >= OTPP_TRIES) { + return; + } + + /* Read OTP lock bits and subregion programmed indication bits */ + oi->status = R_REG(oi->osh, &cc->otpstatus); + + if ((CHIPID(oi->sih->chip) == BCM43224_CHIP_ID) + || (CHIPID(oi->sih->chip) == BCM43225_CHIP_ID)) { + u32 p_bits; + p_bits = + (ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_P_OFF) & + OTPGU_P_MSK) + >> OTPGU_P_SHIFT; + oi->status |= (p_bits << OTPS_GUP_SHIFT); + } + + /* + * h/w region base and fuse region limit are fixed to the top and + * the bottom of the general use region. Everything else can be flexible. + */ + oi->hwbase = oi->otpgu_base + OTPGU_SROM_OFF; + oi->hwlim = oi->wsize; + if (oi->status & OTPS_GUP_HW) { + oi->hwlim = + ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_HSB_OFF) / 16; + oi->swbase = oi->hwlim; + } else + oi->swbase = oi->hwbase; + + /* subtract fuse and checksum from beginning */ + oi->swlim = ipxotp_max_rgnsz(oi->sih, oi->wsize) / 2; + + if (oi->status & OTPS_GUP_SW) { + oi->swlim = + ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_SFB_OFF) / 16; + oi->fbase = oi->swlim; + } else + oi->fbase = oi->swbase; + + oi->flim = oi->wsize; +} + +static void *ipxotp_init(si_t *sih) +{ + uint idx; + chipcregs_t *cc; + otpinfo_t *oi; + + /* Make sure we're running IPX OTP */ + ASSERT(OTPTYPE_IPX(sih->ccrev)); + if (!OTPTYPE_IPX(sih->ccrev)) + return NULL; + + /* Make sure OTP is not disabled */ + if (si_is_otp_disabled(sih)) { + return NULL; + } + + /* Make sure OTP is powered up */ + if (!si_is_otp_powered(sih)) { + return NULL; + } + + oi = &otpinfo; + + /* Check for otp size */ + switch ((sih->cccaps & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) { + case 0: + /* Nothing there */ + return NULL; + case 1: /* 32x64 */ + oi->rows = 32; + oi->cols = 64; + oi->wsize = 128; + break; + case 2: /* 64x64 */ + oi->rows = 64; + oi->cols = 64; + oi->wsize = 256; + break; + case 5: /* 96x64 */ + oi->rows = 96; + oi->cols = 64; + oi->wsize = 384; + break; + case 7: /* 16x64 *//* 1024 bits */ + oi->rows = 16; + oi->cols = 64; + oi->wsize = 64; + break; + default: + /* Don't know the geometry */ + return NULL; + } + + /* Retrieve OTP region info */ + idx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + _ipxotp_init(oi, cc); + + si_setcoreidx(sih, idx); + + return (void *)oi; +} + +static int ipxotp_read_region(void *oh, int region, u16 *data, uint *wlen) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + uint idx; + chipcregs_t *cc; + uint base, i, sz; + + /* Validate region selection */ + switch (region) { + case OTP_HW_RGN: + sz = (uint) oi->hwlim - oi->hwbase; + if (!(oi->status & OTPS_GUP_HW)) { + *wlen = sz; + return BCME_NOTFOUND; + } + if (*wlen < sz) { + *wlen = sz; + return BCME_BUFTOOSHORT; + } + base = oi->hwbase; + break; + case OTP_SW_RGN: + sz = ((uint) oi->swlim - oi->swbase); + if (!(oi->status & OTPS_GUP_SW)) { + *wlen = sz; + return BCME_NOTFOUND; + } + if (*wlen < sz) { + *wlen = sz; + return BCME_BUFTOOSHORT; + } + base = oi->swbase; + break; + case OTP_CI_RGN: + sz = OTPGU_CI_SZ; + if (!(oi->status & OTPS_GUP_CI)) { + *wlen = sz; + return BCME_NOTFOUND; + } + if (*wlen < sz) { + *wlen = sz; + return BCME_BUFTOOSHORT; + } + base = oi->otpgu_base + OTPGU_CI_OFF; + break; + case OTP_FUSE_RGN: + sz = (uint) oi->flim - oi->fbase; + if (!(oi->status & OTPS_GUP_FUSE)) { + *wlen = sz; + return BCME_NOTFOUND; + } + if (*wlen < sz) { + *wlen = sz; + return BCME_BUFTOOSHORT; + } + base = oi->fbase; + break; + case OTP_ALL_RGN: + sz = ((uint) oi->flim - oi->hwbase); + if (!(oi->status & (OTPS_GUP_HW | OTPS_GUP_SW))) { + *wlen = sz; + return BCME_NOTFOUND; + } + if (*wlen < sz) { + *wlen = sz; + return BCME_BUFTOOSHORT; + } + base = oi->hwbase; + break; + default: + return BCME_BADARG; + } + + idx = si_coreidx(oi->sih); + cc = si_setcoreidx(oi->sih, SI_CC_IDX); + ASSERT(cc != NULL); + + /* Read the data */ + for (i = 0; i < sz; i++) + data[i] = ipxotp_otpr(oh, cc, base + i); + + si_setcoreidx(oi->sih, idx); + *wlen = sz; + return 0; +} + +static int ipxotp_nvread(void *oh, char *data, uint *len) +{ + return BCME_UNSUPPORTED; +} + +static otp_fn_t ipxotp_fn = { + (otp_size_t) ipxotp_size, + (otp_read_bit_t) ipxotp_read_bit, + + (otp_init_t) ipxotp_init, + (otp_read_region_t) ipxotp_read_region, + (otp_nvread_t) ipxotp_nvread, + + (otp_status_t) ipxotp_status +}; + +#endif /* BCMIPXOTP */ + +/* + * HND OTP Code + * + * Exported functions: + * hndotp_status() + * hndotp_size() + * hndotp_init() + * hndotp_read_bit() + * hndotp_read_region() + * hndotp_nvread() + * + */ + +#ifdef BCMHNDOTP + +/* Fields in otpstatus */ +#define OTPS_PROGFAIL 0x80000000 +#define OTPS_PROTECT 0x00000007 +#define OTPS_HW_PROTECT 0x00000001 +#define OTPS_SW_PROTECT 0x00000002 +#define OTPS_CID_PROTECT 0x00000004 +#define OTPS_RCEV_MSK 0x00003f00 +#define OTPS_RCEV_SHIFT 8 + +/* Fields in the otpcontrol register */ +#define OTPC_RECWAIT 0xff000000 +#define OTPC_PROGWAIT 0x00ffff00 +#define OTPC_PRW_SHIFT 8 +#define OTPC_MAXFAIL 0x00000038 +#define OTPC_VSEL 0x00000006 +#define OTPC_SELVL 0x00000001 + +/* OTP regions (Word offsets from otp size) */ +#define OTP_SWLIM_OFF (-4) +#define OTP_CIDBASE_OFF 0 +#define OTP_CIDLIM_OFF 4 + +/* Predefined OTP words (Word offset from otp size) */ +#define OTP_BOUNDARY_OFF (-4) +#define OTP_HWSIGN_OFF (-3) +#define OTP_SWSIGN_OFF (-2) +#define OTP_CIDSIGN_OFF (-1) +#define OTP_CID_OFF 0 +#define OTP_PKG_OFF 1 +#define OTP_FID_OFF 2 +#define OTP_RSV_OFF 3 +#define OTP_LIM_OFF 4 +#define OTP_RD_OFF 4 /* Redundancy row starts here */ +#define OTP_RC0_OFF 28 /* Redundancy control word 1 */ +#define OTP_RC1_OFF 32 /* Redundancy control word 2 */ +#define OTP_RC_LIM_OFF 36 /* Redundancy control word end */ + +#define OTP_HW_REGION OTPS_HW_PROTECT +#define OTP_SW_REGION OTPS_SW_PROTECT +#define OTP_CID_REGION OTPS_CID_PROTECT + +#if OTP_HW_REGION != OTP_HW_RGN +#error "incompatible OTP_HW_RGN" +#endif +#if OTP_SW_REGION != OTP_SW_RGN +#error "incompatible OTP_SW_RGN" +#endif +#if OTP_CID_REGION != OTP_CI_RGN +#error "incompatible OTP_CI_RGN" +#endif + +/* Redundancy entry definitions */ +#define OTP_RCE_ROW_SZ 6 +#define OTP_RCE_SIGN_MASK 0x7fff +#define OTP_RCE_ROW_MASK 0x3f +#define OTP_RCE_BITS 21 +#define OTP_RCE_SIGN_SZ 15 +#define OTP_RCE_BIT0 1 + +#define OTP_WPR 4 +#define OTP_SIGNATURE 0x578a +#define OTP_MAGIC 0x4e56 + +static int hndotp_status(void *oh) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + return (int)(oi->hwprot | oi->signvalid); +} + +static int hndotp_size(void *oh) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + return (int)(oi->size); +} + +static u16 hndotp_otpr(void *oh, chipcregs_t *cc, uint wn) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + osl_t *osh; + volatile u16 *ptr; + + ASSERT(wn < ((oi->size / 2) + OTP_RC_LIM_OFF)); + ASSERT(cc != NULL); + + osh = si_osh(oi->sih); + + ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP); + return R_REG(osh, &ptr[wn]); +} + +static u16 hndotp_otproff(void *oh, chipcregs_t *cc, int woff) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + osl_t *osh; + volatile u16 *ptr; + + ASSERT(woff >= (-((int)oi->size / 2))); + ASSERT(woff < OTP_LIM_OFF); + ASSERT(cc != NULL); + + osh = si_osh(oi->sih); + + ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP); + + return R_REG(osh, &ptr[(oi->size / 2) + woff]); +} + +static u16 hndotp_read_bit(void *oh, chipcregs_t *cc, uint idx) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + uint k, row, col; + u32 otpp, st; + osl_t *osh; + + osh = si_osh(oi->sih); + row = idx / 65; + col = idx % 65; + + otpp = OTPP_START_BUSY | OTPP_READ | + ((row << OTPP_ROW_SHIFT) & OTPP_ROW_MASK) | (col & OTPP_COL_MASK); + + W_REG(osh, &cc->otpprog, otpp); + st = R_REG(osh, &cc->otpprog); + for (k = 0; + ((st & OTPP_START_BUSY) == OTPP_START_BUSY) && (k < OTPP_TRIES); + k++) + st = R_REG(osh, &cc->otpprog); + + if (k >= OTPP_TRIES) { + return 0xffff; + } + if (st & OTPP_READERR) { + return 0xffff; + } + st = (st & OTPP_VALUE_MASK) >> OTPP_VALUE_SHIFT; + return (u16) st; +} + +static void *hndotp_init(si_t *sih) +{ + uint idx; + chipcregs_t *cc; + otpinfo_t *oi; + u32 cap = 0, clkdiv, otpdiv = 0; + void *ret = NULL; + osl_t *osh; + + oi = &otpinfo; + + idx = si_coreidx(sih); + osh = si_osh(oi->sih); + + /* Check for otp */ + cc = si_setcoreidx(sih, SI_CC_IDX); + if (cc != NULL) { + cap = R_REG(osh, &cc->capabilities); + if ((cap & CC_CAP_OTPSIZE) == 0) { + /* Nothing there */ + goto out; + } + + /* As of right now, support only 4320a2, 4311a1 and 4312 */ + ASSERT((oi->ccrev == 12) || (oi->ccrev == 17) + || (oi->ccrev == 22)); + if (! + ((oi->ccrev == 12) || (oi->ccrev == 17) + || (oi->ccrev == 22))) + return NULL; + + /* Read the OTP byte size. chipcommon rev >= 18 has RCE so the size is + * 8 row (64 bytes) smaller + */ + oi->size = + 1 << (((cap & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) + + CC_CAP_OTPSIZE_BASE); + if (oi->ccrev >= 18) + oi->size -= ((OTP_RC0_OFF - OTP_BOUNDARY_OFF) * 2); + + oi->hwprot = (int)(R_REG(osh, &cc->otpstatus) & OTPS_PROTECT); + oi->boundary = -1; + + /* Check the region signature */ + if (hndotp_otproff(oi, cc, OTP_HWSIGN_OFF) == OTP_SIGNATURE) { + oi->signvalid |= OTP_HW_REGION; + oi->boundary = hndotp_otproff(oi, cc, OTP_BOUNDARY_OFF); + } + + if (hndotp_otproff(oi, cc, OTP_SWSIGN_OFF) == OTP_SIGNATURE) + oi->signvalid |= OTP_SW_REGION; + + if (hndotp_otproff(oi, cc, OTP_CIDSIGN_OFF) == OTP_SIGNATURE) + oi->signvalid |= OTP_CID_REGION; + + /* Set OTP clkdiv for stability */ + if (oi->ccrev == 22) + otpdiv = 12; + + if (otpdiv) { + clkdiv = R_REG(osh, &cc->clkdiv); + clkdiv = + (clkdiv & ~CLKD_OTP) | (otpdiv << CLKD_OTP_SHIFT); + W_REG(osh, &cc->clkdiv, clkdiv); + } + udelay(10); + + ret = (void *)oi; + } + + out: /* All done */ + si_setcoreidx(sih, idx); + + return ret; +} + +static int hndotp_read_region(void *oh, int region, u16 *data, uint *wlen) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + u32 idx, st; + chipcregs_t *cc; + int i; + + /* Only support HW region (no active chips use HND OTP SW region) */ + ASSERT(region == OTP_HW_REGION); + + /* Region empty? */ + st = oi->hwprot | oi->signvalid; + if ((st & region) == 0) + return BCME_NOTFOUND; + + *wlen = + ((int)*wlen < oi->boundary / 2) ? *wlen : (uint) oi->boundary / 2; + + idx = si_coreidx(oi->sih); + cc = si_setcoreidx(oi->sih, SI_CC_IDX); + ASSERT(cc != NULL); + + for (i = 0; i < (int)*wlen; i++) + data[i] = hndotp_otpr(oh, cc, i); + + si_setcoreidx(oi->sih, idx); + + return 0; +} + +static int hndotp_nvread(void *oh, char *data, uint *len) +{ + int rc = 0; + otpinfo_t *oi = (otpinfo_t *) oh; + u32 base, bound, lim = 0, st; + int i, chunk, gchunks, tsz = 0; + u32 idx; + chipcregs_t *cc; + uint offset; + u16 *rawotp = NULL; + + /* save the orig core */ + idx = si_coreidx(oi->sih); + cc = si_setcoreidx(oi->sih, SI_CC_IDX); + ASSERT(cc != NULL); + + st = hndotp_status(oh); + if (!(st & (OTP_HW_REGION | OTP_SW_REGION))) { + rc = -1; + goto out; + } + + /* Read the whole otp so we can easily manipulate it */ + lim = hndotp_size(oh); + rawotp = kmalloc(lim, GFP_ATOMIC); + if (rawotp == NULL) { + rc = -2; + goto out; + } + for (i = 0; i < (int)(lim / 2); i++) + rawotp[i] = hndotp_otpr(oh, cc, i); + + if ((st & OTP_HW_REGION) == 0) { + /* This could be a programming failure in the first + * chunk followed by one or more good chunks + */ + for (i = 0; i < (int)(lim / 2); i++) + if (rawotp[i] == OTP_MAGIC) + break; + + if (i < (int)(lim / 2)) { + base = i; + bound = (i * 2) + rawotp[i + 1]; + } else { + rc = -3; + goto out; + } + } else { + bound = rawotp[(lim / 2) + OTP_BOUNDARY_OFF]; + + /* There are two cases: 1) The whole otp is used as nvram + * and 2) There is a hardware header followed by nvram. + */ + if (rawotp[0] == OTP_MAGIC) { + base = 0; + } else + base = bound; + } + + /* Find and copy the data */ + + chunk = 0; + gchunks = 0; + i = base / 2; + offset = 0; + while ((i < (int)(lim / 2)) && (rawotp[i] == OTP_MAGIC)) { + int dsz, rsz = rawotp[i + 1]; + + if (((i * 2) + rsz) >= (int)lim) { + /* Bad length, try to find another chunk anyway */ + rsz = 6; + } + if (hndcrc16((u8 *) &rawotp[i], rsz, + CRC16_INIT_VALUE) == CRC16_GOOD_VALUE) { + /* Good crc, copy the vars */ + gchunks++; + dsz = rsz - 6; + tsz += dsz; + if (offset + dsz >= *len) { + goto out; + } + bcopy((char *)&rawotp[i + 2], &data[offset], dsz); + offset += dsz; + /* Remove extra null characters at the end */ + while (offset > 1 && + data[offset - 1] == 0 && data[offset - 2] == 0) + offset--; + i += rsz / 2; + } else { + /* bad length or crc didn't check, try to find the next set */ + if (rawotp[i + (rsz / 2)] == OTP_MAGIC) { + /* Assume length is good */ + i += rsz / 2; + } else { + while (++i < (int)(lim / 2)) + if (rawotp[i] == OTP_MAGIC) + break; + } + } + chunk++; + } + + *len = offset; + + out: + if (rawotp) + kfree(rawotp); + si_setcoreidx(oi->sih, idx); + + return rc; +} + +static otp_fn_t hndotp_fn = { + (otp_size_t) hndotp_size, + (otp_read_bit_t) hndotp_read_bit, + + (otp_init_t) hndotp_init, + (otp_read_region_t) hndotp_read_region, + (otp_nvread_t) hndotp_nvread, + + (otp_status_t) hndotp_status +}; + +#endif /* BCMHNDOTP */ + +/* + * Common Code: Compiled for IPX / HND / AUTO + * otp_status() + * otp_size() + * otp_read_bit() + * otp_init() + * otp_read_region() + * otp_nvread() + */ + +int otp_status(void *oh) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + + return oi->fn->status(oh); +} + +int otp_size(void *oh) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + + return oi->fn->size(oh); +} + +u16 otp_read_bit(void *oh, uint offset) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + uint idx = si_coreidx(oi->sih); + chipcregs_t *cc = si_setcoreidx(oi->sih, SI_CC_IDX); + u16 readBit = (u16) oi->fn->read_bit(oh, cc, offset); + si_setcoreidx(oi->sih, idx); + return readBit; +} + +void *otp_init(si_t *sih) +{ + otpinfo_t *oi; + void *ret = NULL; + + oi = &otpinfo; + bzero(oi, sizeof(otpinfo_t)); + + oi->ccrev = sih->ccrev; + +#ifdef BCMIPXOTP + if (OTPTYPE_IPX(oi->ccrev)) + oi->fn = &ipxotp_fn; +#endif + +#ifdef BCMHNDOTP + if (OTPTYPE_HND(oi->ccrev)) + oi->fn = &hndotp_fn; +#endif + + if (oi->fn == NULL) { + return NULL; + } + + oi->sih = sih; + oi->osh = si_osh(oi->sih); + + ret = (oi->fn->init) (sih); + + return ret; +} + +int +otp_read_region(si_t *sih, int region, u16 *data, + uint *wlen) { + bool wasup = false; + void *oh; + int err = 0; + + wasup = si_is_otp_powered(sih); + if (!wasup) + si_otp_power(sih, true); + + if (!si_is_otp_powered(sih) || si_is_otp_disabled(sih)) { + err = BCME_NOTREADY; + goto out; + } + + oh = otp_init(sih); + if (oh == NULL) { + err = BCME_ERROR; + goto out; + } + + err = (((otpinfo_t *) oh)->fn->read_region) (oh, region, data, wlen); + + out: + if (!wasup) + si_otp_power(sih, false); + + return err; +} + +int otp_nvread(void *oh, char *data, uint *len) +{ + otpinfo_t *oi = (otpinfo_t *) oh; + + return oi->fn->nvread(oh, data, len); +} diff --git a/drivers/staging/brcm80211/util/bcmsrom.c b/drivers/staging/brcm80211/util/bcmsrom.c new file mode 100644 index 0000000..1282ef7 --- /dev/null +++ b/drivers/staging/brcm80211/util/bcmsrom.c @@ -0,0 +1,2076 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include <linux/kernel.h> +#include <linux/string.h> +#include <bcmdefs.h> +#include <osl.h> +#include <linuxver.h> +#include <stdarg.h> +#include <bcmutils.h> +#include <hndsoc.h> +#include <sbchipc.h> +#include <bcmdevs.h> +#include <bcmendian.h> +#include <pcicfg.h> +#include <siutils.h> +#include <bcmsrom.h> +#include <bcmsrom_tbl.h> +#ifdef BCMSDIO +#include <bcmsdh.h> +#include <sdio.h> +#endif + +#include <bcmnvram.h> +#include <bcmotp.h> + +#if defined(BCMSDIO) +#include <sbsdio.h> +#include <sbhnddma.h> +#include <sbsdpcmdev.h> +#endif + +#include <proto/ethernet.h> /* for sprom content groking */ + +#define BS_ERROR(args) + +#define SROM_OFFSET(sih) ((sih->ccrev > 31) ? \ + (((sih->cccaps & CC_CAP_SROM) == 0) ? NULL : \ + ((u8 *)curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP)) : \ + ((u8 *)curmap + PCI_BAR0_SPROM_OFFSET)) + +#if defined(BCMDBG) +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */ +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */ +#endif + +typedef struct varbuf { + char *base; /* pointer to buffer base */ + char *buf; /* pointer to current position */ + unsigned int size; /* current (residual) size in bytes */ +} varbuf_t; +extern char *_vars; +extern uint _varsz; + +#define SROM_CIS_SINGLE 1 + +static int initvars_srom_si(si_t *sih, osl_t *osh, void *curmap, char **vars, + uint *count); +static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, + varbuf_t *b); +static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, + uint *count); +static int initvars_flash_si(si_t *sih, char **vars, uint *count); +#ifdef BCMSDIO +static int initvars_cis_sdio(osl_t *osh, char **vars, uint *count); +static int sprom_cmd_sdio(osl_t *osh, u8 cmd); +static int sprom_read_sdio(osl_t *osh, u16 addr, u16 *data); +#endif /* BCMSDIO */ +static int sprom_read_pci(osl_t *osh, si_t *sih, u16 *sprom, uint wordoff, + u16 *buf, uint nwords, bool check_crc); +#if defined(BCMNVRAMR) +static int otp_read_pci(osl_t *osh, si_t *sih, u16 *buf, uint bufsz); +#endif +static u16 srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, u32 cmd, + uint wordoff, u16 data); + +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, + uint *count); +static int initvars_flash(si_t *sih, osl_t *osh, char **vp, uint len); + +/* Initialization of varbuf structure */ +static void varbuf_init(varbuf_t *b, char *buf, uint size) +{ + b->size = size; + b->base = b->buf = buf; +} + +/* append a null terminated var=value string */ +static int varbuf_append(varbuf_t *b, const char *fmt, ...) +{ + va_list ap; + int r; + size_t len; + char *s; + + if (b->size < 2) + return 0; + + va_start(ap, fmt); + r = vsnprintf(b->buf, b->size, fmt, ap); + va_end(ap); + + /* C99 snprintf behavior returns r >= size on overflow, + * others return -1 on overflow. + * All return -1 on format error. + * We need to leave room for 2 null terminations, one for the current var + * string, and one for final null of the var table. So check that the + * strlen written, r, leaves room for 2 chars. + */ + if ((r == -1) || (r > (int)(b->size - 2))) { + b->size = 0; + return 0; + } + + /* Remove any earlier occurrence of the same variable */ + s = strchr(b->buf, '='); + if (s != NULL) { + len = (size_t) (s - b->buf); + for (s = b->base; s < b->buf;) { + if ((bcmp(s, b->buf, len) == 0) && s[len] == '=') { + len = strlen(s) + 1; + memmove(s, (s + len), + ((b->buf + r + 1) - (s + len))); + b->buf -= len; + b->size += (unsigned int)len; + break; + } + + while (*s++) + ; + } + } + + /* skip over this string's null termination */ + r++; + b->size -= r; + b->buf += r; + + return r; +} + +/* + * Initialize local vars from the right source for this platform. + * Return 0 on success, nonzero on error. + */ +int srom_var_init(si_t *sih, uint bustype, void *curmap, osl_t *osh, + char **vars, uint *count) +{ + uint len; + + len = 0; + + ASSERT(bustype == BUSTYPE(bustype)); + if (vars == NULL || count == NULL) + return 0; + + *vars = NULL; + *count = 0; + + switch (BUSTYPE(bustype)) { + case SI_BUS: + case JTAG_BUS: + return initvars_srom_si(sih, osh, curmap, vars, count); + + case PCI_BUS: + ASSERT(curmap != NULL); + if (curmap == NULL) + return -1; + + return initvars_srom_pci(sih, curmap, vars, count); + +#ifdef BCMSDIO + case SDIO_BUS: + return initvars_cis_sdio(osh, vars, count); +#endif /* BCMSDIO */ + + default: + ASSERT(0); + } + return -1; +} + +/* support only 16-bit word read from srom */ +int +srom_read(si_t *sih, uint bustype, void *curmap, osl_t *osh, + uint byteoff, uint nbytes, u16 *buf, bool check_crc) +{ + uint off, nw; +#ifdef BCMSDIO + uint i; +#endif /* BCMSDIO */ + + ASSERT(bustype == BUSTYPE(bustype)); + + /* check input - 16-bit access only */ + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > SROM_MAX) + return 1; + + off = byteoff / 2; + nw = nbytes / 2; + + if (BUSTYPE(bustype) == PCI_BUS) { + if (!curmap) + return 1; + + if (si_is_sprom_available(sih)) { + u16 *srom; + + srom = (u16 *) SROM_OFFSET(sih); + if (srom == NULL) + return 1; + + if (sprom_read_pci + (osh, sih, srom, off, buf, nw, check_crc)) + return 1; + } +#if defined(BCMNVRAMR) + else { + if (otp_read_pci(osh, sih, buf, SROM_MAX)) + return 1; + } +#endif +#ifdef BCMSDIO + } else if (BUSTYPE(bustype) == SDIO_BUS) { + off = byteoff / 2; + nw = nbytes / 2; + for (i = 0; i < nw; i++) { + if (sprom_read_sdio + (osh, (u16) (off + i), (u16 *) (buf + i))) + return 1; + } +#endif /* BCMSDIO */ + } else if (BUSTYPE(bustype) == SI_BUS) { + return 1; + } else { + return 1; + } + + return 0; +} + +static const char vstr_manf[] = "manf=%s"; +static const char vstr_productname[] = "productname=%s"; +static const char vstr_manfid[] = "manfid=0x%x"; +static const char vstr_prodid[] = "prodid=0x%x"; +#ifdef BCMSDIO +static const char vstr_sdmaxspeed[] = "sdmaxspeed=%d"; +static const char vstr_sdmaxblk[][13] = { +"sdmaxblk0=%d", "sdmaxblk1=%d", "sdmaxblk2=%d"}; +#endif +static const char vstr_regwindowsz[] = "regwindowsz=%d"; +static const char vstr_sromrev[] = "sromrev=%d"; +static const char vstr_chiprev[] = "chiprev=%d"; +static const char vstr_subvendid[] = "subvendid=0x%x"; +static const char vstr_subdevid[] = "subdevid=0x%x"; +static const char vstr_boardrev[] = "boardrev=0x%x"; +static const char vstr_aa2g[] = "aa2g=0x%x"; +static const char vstr_aa5g[] = "aa5g=0x%x"; +static const char vstr_ag[] = "ag%d=0x%x"; +static const char vstr_cc[] = "cc=%d"; +static const char vstr_opo[] = "opo=%d"; +static const char vstr_pa0b[][9] = { +"pa0b0=%d", "pa0b1=%d", "pa0b2=%d"}; + +static const char vstr_pa0itssit[] = "pa0itssit=%d"; +static const char vstr_pa0maxpwr[] = "pa0maxpwr=%d"; +static const char vstr_pa1b[][9] = { +"pa1b0=%d", "pa1b1=%d", "pa1b2=%d"}; + +static const char vstr_pa1lob[][11] = { +"pa1lob0=%d", "pa1lob1=%d", "pa1lob2=%d"}; + +static const char vstr_pa1hib[][11] = { +"pa1hib0=%d", "pa1hib1=%d", "pa1hib2=%d"}; + +static const char vstr_pa1itssit[] = "pa1itssit=%d"; +static const char vstr_pa1maxpwr[] = "pa1maxpwr=%d"; +static const char vstr_pa1lomaxpwr[] = "pa1lomaxpwr=%d"; +static const char vstr_pa1himaxpwr[] = "pa1himaxpwr=%d"; +static const char vstr_oem[] = + "oem=%02x%02x%02x%02x%02x%02x%02x%02x"; +static const char vstr_boardflags[] = "boardflags=0x%x"; +static const char vstr_boardflags2[] = "boardflags2=0x%x"; +static const char vstr_ledbh[] = "ledbh%d=0x%x"; +static const char vstr_noccode[] = "ccode=0x0"; +static const char vstr_ccode[] = "ccode=%c%c"; +static const char vstr_cctl[] = "cctl=0x%x"; +static const char vstr_cckpo[] = "cckpo=0x%x"; +static const char vstr_ofdmpo[] = "ofdmpo=0x%x"; +static const char vstr_rdlid[] = "rdlid=0x%x"; +static const char vstr_rdlrndis[] = "rdlrndis=%d"; +static const char vstr_rdlrwu[] = "rdlrwu=%d"; +static const char vstr_usbfs[] = "usbfs=%d"; +static const char vstr_wpsgpio[] = "wpsgpio=%d"; +static const char vstr_wpsled[] = "wpsled=%d"; +static const char vstr_rdlsn[] = "rdlsn=%d"; +static const char vstr_rssismf2g[] = "rssismf2g=%d"; +static const char vstr_rssismc2g[] = "rssismc2g=%d"; +static const char vstr_rssisav2g[] = "rssisav2g=%d"; +static const char vstr_bxa2g[] = "bxa2g=%d"; +static const char vstr_rssismf5g[] = "rssismf5g=%d"; +static const char vstr_rssismc5g[] = "rssismc5g=%d"; +static const char vstr_rssisav5g[] = "rssisav5g=%d"; +static const char vstr_bxa5g[] = "bxa5g=%d"; +static const char vstr_tri2g[] = "tri2g=%d"; +static const char vstr_tri5gl[] = "tri5gl=%d"; +static const char vstr_tri5g[] = "tri5g=%d"; +static const char vstr_tri5gh[] = "tri5gh=%d"; +static const char vstr_rxpo2g[] = "rxpo2g=%d"; +static const char vstr_rxpo5g[] = "rxpo5g=%d"; +static const char vstr_boardtype[] = "boardtype=0x%x"; +static const char vstr_leddc[] = "leddc=0x%04x"; +static const char vstr_vendid[] = "vendid=0x%x"; +static const char vstr_devid[] = "devid=0x%x"; +static const char vstr_xtalfreq[] = "xtalfreq=%d"; +static const char vstr_txchain[] = "txchain=0x%x"; +static const char vstr_rxchain[] = "rxchain=0x%x"; +static const char vstr_antswitch[] = "antswitch=0x%x"; +static const char vstr_regrev[] = "regrev=0x%x"; +static const char vstr_antswctl2g[] = "antswctl2g=0x%x"; +static const char vstr_triso2g[] = "triso2g=0x%x"; +static const char vstr_pdetrange2g[] = "pdetrange2g=0x%x"; +static const char vstr_extpagain2g[] = "extpagain2g=0x%x"; +static const char vstr_tssipos2g[] = "tssipos2g=0x%x"; +static const char vstr_antswctl5g[] = "antswctl5g=0x%x"; +static const char vstr_triso5g[] = "triso5g=0x%x"; +static const char vstr_pdetrange5g[] = "pdetrange5g=0x%x"; +static const char vstr_extpagain5g[] = "extpagain5g=0x%x"; +static const char vstr_tssipos5g[] = "tssipos5g=0x%x"; +static const char vstr_maxp2ga0[] = "maxp2ga0=0x%x"; +static const char vstr_itt2ga0[] = "itt2ga0=0x%x"; +static const char vstr_pa[] = "pa%dgw%da%d=0x%x"; +static const char vstr_pahl[] = "pa%dg%cw%da%d=0x%x"; +static const char vstr_maxp5ga0[] = "maxp5ga0=0x%x"; +static const char vstr_itt5ga0[] = "itt5ga0=0x%x"; +static const char vstr_maxp5gha0[] = "maxp5gha0=0x%x"; +static const char vstr_maxp5gla0[] = "maxp5gla0=0x%x"; +static const char vstr_maxp2ga1[] = "maxp2ga1=0x%x"; +static const char vstr_itt2ga1[] = "itt2ga1=0x%x"; +static const char vstr_maxp5ga1[] = "maxp5ga1=0x%x"; +static const char vstr_itt5ga1[] = "itt5ga1=0x%x"; +static const char vstr_maxp5gha1[] = "maxp5gha1=0x%x"; +static const char vstr_maxp5gla1[] = "maxp5gla1=0x%x"; +static const char vstr_cck2gpo[] = "cck2gpo=0x%x"; +static const char vstr_ofdm2gpo[] = "ofdm2gpo=0x%x"; +static const char vstr_ofdm5gpo[] = "ofdm5gpo=0x%x"; +static const char vstr_ofdm5glpo[] = "ofdm5glpo=0x%x"; +static const char vstr_ofdm5ghpo[] = "ofdm5ghpo=0x%x"; +static const char vstr_cddpo[] = "cddpo=0x%x"; +static const char vstr_stbcpo[] = "stbcpo=0x%x"; +static const char vstr_bw40po[] = "bw40po=0x%x"; +static const char vstr_bwduppo[] = "bwduppo=0x%x"; +static const char vstr_mcspo[] = "mcs%dgpo%d=0x%x"; +static const char vstr_mcspohl[] = "mcs%dg%cpo%d=0x%x"; +static const char vstr_custom[] = "customvar%d=0x%x"; +static const char vstr_cckdigfilttype[] = "cckdigfilttype=%d"; +static const char vstr_boardnum[] = "boardnum=%d"; +static const char vstr_macaddr[] = "macaddr=%s"; +static const char vstr_usbepnum[] = "usbepnum=0x%x"; +static const char vstr_end[] = "END\0"; + +u8 patch_pair; + +/* For dongle HW, accept partial calibration parameters */ +#define BCMDONGLECASE(n) + +int srom_parsecis(osl_t *osh, u8 *pcis[], uint ciscnt, char **vars, uint *count) +{ + char eabuf[32]; + char *base; + varbuf_t b; + u8 *cis, tup, tlen, sromrev = 1; + int i, j; + bool ag_init = false; + u32 w32; + uint funcid; + uint cisnum; + s32 boardnum; + int err; + bool standard_cis; + + ASSERT(vars != NULL); + ASSERT(count != NULL); + + boardnum = -1; + + base = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC); + ASSERT(base != NULL); + if (!base) + return -2; + + varbuf_init(&b, base, MAXSZ_NVRAM_VARS); + bzero(base, MAXSZ_NVRAM_VARS); + eabuf[0] = '\0'; + for (cisnum = 0; cisnum < ciscnt; cisnum++) { + cis = *pcis++; + i = 0; + funcid = 0; + standard_cis = true; + do { + if (standard_cis) { + tup = cis[i++]; + if (tup == CISTPL_NULL || tup == CISTPL_END) + tlen = 0; + else + tlen = cis[i++]; + } else { + if (cis[i] == CISTPL_NULL + || cis[i] == CISTPL_END) { + tlen = 0; + tup = cis[i]; + } else { + tlen = cis[i]; + tup = CISTPL_BRCM_HNBU; + } + ++i; + } + if ((i + tlen) >= CIS_SIZE) + break; + + switch (tup) { + case CISTPL_VERS_1: + /* assume the strings are good if the version field checks out */ + if (((cis[i + 1] << 8) + cis[i]) >= 0x0008) { + varbuf_append(&b, vstr_manf, + &cis[i + 2]); + varbuf_append(&b, vstr_productname, + &cis[i + 3 + + strlen((char *) + &cis[i + + 2])]); + break; + } + + case CISTPL_MANFID: + varbuf_append(&b, vstr_manfid, + (cis[i + 1] << 8) + cis[i]); + varbuf_append(&b, vstr_prodid, + (cis[i + 3] << 8) + cis[i + 2]); + break; + + case CISTPL_FUNCID: + funcid = cis[i]; + break; + + case CISTPL_FUNCE: + switch (funcid) { + case CISTPL_FID_SDIO: +#ifdef BCMSDIO + if (cis[i] == 0) { + u8 spd = cis[i + 3]; + static int base[] = { + -1, 10, 12, 13, 15, 20, + 25, 30, + 35, 40, 45, 50, 55, 60, + 70, 80 + }; + static int mult[] = { + 10, 100, 1000, 10000, + -1, -1, -1, -1 + }; + ASSERT((mult[spd & 0x7] != -1) + && + (base + [(spd >> 3) & 0x0f])); + varbuf_append(&b, + vstr_sdmaxblk[0], + (cis[i + 2] << 8) + + cis[i + 1]); + varbuf_append(&b, + vstr_sdmaxspeed, + (mult[spd & 0x7] * + base[(spd >> 3) & + 0x0f])); + } else if (cis[i] == 1) { + varbuf_append(&b, + vstr_sdmaxblk + [cisnum], + (cis[i + 13] << 8) + | cis[i + 12]); + } +#endif /* BCMSDIO */ + funcid = 0; + break; + default: + /* set macaddr if HNBU_MACADDR not seen yet */ + if (eabuf[0] == '\0' + && cis[i] == LAN_NID + && !(ETHER_ISNULLADDR(&cis[i + 2])) + && !(ETHER_ISMULTI(&cis[i + 2]))) { + ASSERT(cis[i + 1] == + ETHER_ADDR_LEN); + snprintf(eabuf, sizeof(eabuf), + "%pM", &cis[i + 2]); + + /* set boardnum if HNBU_BOARDNUM not seen yet */ + if (boardnum == -1) + boardnum = + (cis[i + 6] << 8) + + cis[i + 7]; + } + break; + } + break; + + case CISTPL_CFTABLE: + varbuf_append(&b, vstr_regwindowsz, + (cis[i + 7] << 8) | cis[i + 6]); + break; + + case CISTPL_BRCM_HNBU: + switch (cis[i]) { + case HNBU_SROMREV: + sromrev = cis[i + 1]; + varbuf_append(&b, vstr_sromrev, + sromrev); + break; + + case HNBU_XTALFREQ: + varbuf_append(&b, vstr_xtalfreq, + (cis[i + 4] << 24) | + (cis[i + 3] << 16) | + (cis[i + 2] << 8) | + cis[i + 1]); + break; + + case HNBU_CHIPID: + varbuf_append(&b, vstr_vendid, + (cis[i + 2] << 8) + + cis[i + 1]); + varbuf_append(&b, vstr_devid, + (cis[i + 4] << 8) + + cis[i + 3]); + if (tlen >= 7) { + varbuf_append(&b, vstr_chiprev, + (cis[i + 6] << 8) + + cis[i + 5]); + } + if (tlen >= 9) { + varbuf_append(&b, + vstr_subvendid, + (cis[i + 8] << 8) + + cis[i + 7]); + } + if (tlen >= 11) { + varbuf_append(&b, vstr_subdevid, + (cis[i + 10] << 8) + + cis[i + 9]); + /* subdevid doubles for boardtype */ + varbuf_append(&b, + vstr_boardtype, + (cis[i + 10] << 8) + + cis[i + 9]); + } + break; + + case HNBU_BOARDNUM: + boardnum = + (cis[i + 2] << 8) + cis[i + 1]; + break; + + case HNBU_PATCH: + { + char vstr_paddr[16]; + char vstr_pdata[16]; + + /* retrieve the patch pairs + * from tlen/6; where 6 is + * sizeof(patch addr(2)) + + * sizeof(patch data(4)). + */ + patch_pair = tlen / 6; + + for (j = 0; j < patch_pair; j++) { + snprintf(vstr_paddr, + sizeof + (vstr_paddr), + "pa%d=0x%%x", + j); + snprintf(vstr_pdata, + sizeof + (vstr_pdata), + "pd%d=0x%%x", + j); + + varbuf_append(&b, + vstr_paddr, + (cis + [i + + (j * + 6) + + 2] << 8) + | cis[i + + (j * + 6) + + + 1]); + + varbuf_append(&b, + vstr_pdata, + (cis + [i + + (j * + 6) + + 6] << + 24) | + (cis + [i + + (j * + 6) + + 5] << + 16) | + (cis + [i + + (j * + 6) + + 4] << 8) + | cis[i + + (j * + 6) + + + 3]); + } + } + break; + + case HNBU_BOARDREV: + if (tlen == 2) + varbuf_append(&b, vstr_boardrev, + cis[i + 1]); + else + varbuf_append(&b, vstr_boardrev, + (cis[i + 2] << 8) + + cis[i + 1]); + break; + + case HNBU_BOARDFLAGS: + w32 = (cis[i + 2] << 8) + cis[i + 1]; + if (tlen >= 5) + w32 |= + ((cis[i + 4] << 24) + + (cis[i + 3] << 16)); + varbuf_append(&b, vstr_boardflags, w32); + + if (tlen >= 7) { + w32 = + (cis[i + 6] << 8) + cis[i + + 5]; + if (tlen >= 9) + w32 |= + ((cis[i + 8] << 24) + + + (cis[i + 7] << + 16)); + varbuf_append(&b, + vstr_boardflags2, + w32); + } + break; + + case HNBU_USBFS: + varbuf_append(&b, vstr_usbfs, + cis[i + 1]); + break; + + case HNBU_BOARDTYPE: + varbuf_append(&b, vstr_boardtype, + (cis[i + 2] << 8) + + cis[i + 1]); + break; + + case HNBU_HNBUCIS: + /* + * what follows is a nonstandard HNBU CIS + * that lacks CISTPL_BRCM_HNBU tags + * + * skip 0xff (end of standard CIS) + * after this tuple + */ + tlen++; + standard_cis = false; + break; + + case HNBU_USBEPNUM: + varbuf_append(&b, vstr_usbepnum, + (cis[i + 2] << 8) | cis[i + + + 1]); + break; + + case HNBU_AA: + varbuf_append(&b, vstr_aa2g, + cis[i + 1]); + if (tlen >= 3) + varbuf_append(&b, vstr_aa5g, + cis[i + 2]); + break; + + case HNBU_AG: + varbuf_append(&b, vstr_ag, 0, + cis[i + 1]); + if (tlen >= 3) + varbuf_append(&b, vstr_ag, 1, + cis[i + 2]); + if (tlen >= 4) + varbuf_append(&b, vstr_ag, 2, + cis[i + 3]); + if (tlen >= 5) + varbuf_append(&b, vstr_ag, 3, + cis[i + 4]); + ag_init = true; + break; + + case HNBU_ANT5G: + varbuf_append(&b, vstr_aa5g, + cis[i + 1]); + varbuf_append(&b, vstr_ag, 1, + cis[i + 2]); + break; + + case HNBU_CC: + ASSERT(sromrev == 1); + varbuf_append(&b, vstr_cc, cis[i + 1]); + break; + + case HNBU_PAPARMS: + switch (tlen) { + case 2: + ASSERT(sromrev == 1); + varbuf_append(&b, + vstr_pa0maxpwr, + cis[i + 1]); + break; + case 10: + ASSERT(sromrev >= 2); + varbuf_append(&b, vstr_opo, + cis[i + 9]); + /* FALLTHROUGH */ + case 9: + varbuf_append(&b, + vstr_pa0maxpwr, + cis[i + 8]); + /* FALLTHROUGH */ + BCMDONGLECASE(8) + varbuf_append(&b, + vstr_pa0itssit, + cis[i + 7]); + /* FALLTHROUGH */ + BCMDONGLECASE(7) + for (j = 0; j < 3; j++) { + varbuf_append(&b, + vstr_pa0b + [j], + (cis + [i + + (j * + 2) + + 2] << 8) + + cis[i + + (j * + 2) + + + 1]); + } + break; + default: + ASSERT((tlen == 2) + || (tlen == 9) + || (tlen == 10)); + break; + } + break; + + case HNBU_PAPARMS5G: + ASSERT((sromrev == 2) + || (sromrev == 3)); + switch (tlen) { + case 23: + varbuf_append(&b, + vstr_pa1himaxpwr, + cis[i + 22]); + varbuf_append(&b, + vstr_pa1lomaxpwr, + cis[i + 21]); + varbuf_append(&b, + vstr_pa1maxpwr, + cis[i + 20]); + /* FALLTHROUGH */ + case 20: + varbuf_append(&b, + vstr_pa1itssit, + cis[i + 19]); + /* FALLTHROUGH */ + case 19: + for (j = 0; j < 3; j++) { + varbuf_append(&b, + vstr_pa1b + [j], + (cis + [i + + (j * + 2) + + 2] << 8) + + cis[i + + (j * + 2) + + + 1]); + } + for (j = 3; j < 6; j++) { + varbuf_append(&b, + vstr_pa1lob + [j - 3], + (cis + [i + + (j * + 2) + + 2] << 8) + + cis[i + + (j * + 2) + + + 1]); + } + for (j = 6; j < 9; j++) { + varbuf_append(&b, + vstr_pa1hib + [j - 6], + (cis + [i + + (j * + 2) + + 2] << 8) + + cis[i + + (j * + 2) + + + 1]); + } + break; + default: + ASSERT((tlen == 19) || + (tlen == 20) + || (tlen == 23)); + break; + } + break; + + case HNBU_OEM: + ASSERT(sromrev == 1); + varbuf_append(&b, vstr_oem, + cis[i + 1], cis[i + 2], + cis[i + 3], cis[i + 4], + cis[i + 5], cis[i + 6], + cis[i + 7], cis[i + 8]); + break; + + case HNBU_LEDS: + for (j = 1; j <= 4; j++) { + if (cis[i + j] != 0xff) { + varbuf_append(&b, + vstr_ledbh, + j - 1, + cis[i + + j]); + } + } + break; + + case HNBU_CCODE: + ASSERT(sromrev > 1); + if ((cis[i + 1] == 0) + || (cis[i + 2] == 0)) + varbuf_append(&b, vstr_noccode); + else + varbuf_append(&b, vstr_ccode, + cis[i + 1], + cis[i + 2]); + varbuf_append(&b, vstr_cctl, + cis[i + 3]); + break; + + case HNBU_CCKPO: + ASSERT(sromrev > 2); + varbuf_append(&b, vstr_cckpo, + (cis[i + 2] << 8) | cis[i + + + 1]); + break; + + case HNBU_OFDMPO: + ASSERT(sromrev > 2); + varbuf_append(&b, vstr_ofdmpo, + (cis[i + 4] << 24) | + (cis[i + 3] << 16) | + (cis[i + 2] << 8) | + cis[i + 1]); + break; + + case HNBU_WPS: + varbuf_append(&b, vstr_wpsgpio, + cis[i + 1]); + if (tlen >= 3) + varbuf_append(&b, vstr_wpsled, + cis[i + 2]); + break; + + case HNBU_RSSISMBXA2G: + ASSERT(sromrev == 3); + varbuf_append(&b, vstr_rssismf2g, + cis[i + 1] & 0xf); + varbuf_append(&b, vstr_rssismc2g, + (cis[i + 1] >> 4) & 0xf); + varbuf_append(&b, vstr_rssisav2g, + cis[i + 2] & 0x7); + varbuf_append(&b, vstr_bxa2g, + (cis[i + 2] >> 3) & 0x3); + break; + + case HNBU_RSSISMBXA5G: + ASSERT(sromrev == 3); + varbuf_append(&b, vstr_rssismf5g, + cis[i + 1] & 0xf); + varbuf_append(&b, vstr_rssismc5g, + (cis[i + 1] >> 4) & 0xf); + varbuf_append(&b, vstr_rssisav5g, + cis[i + 2] & 0x7); + varbuf_append(&b, vstr_bxa5g, + (cis[i + 2] >> 3) & 0x3); + break; + + case HNBU_TRI2G: + ASSERT(sromrev == 3); + varbuf_append(&b, vstr_tri2g, + cis[i + 1]); + break; + + case HNBU_TRI5G: + ASSERT(sromrev == 3); + varbuf_append(&b, vstr_tri5gl, + cis[i + 1]); + varbuf_append(&b, vstr_tri5g, + cis[i + 2]); + varbuf_append(&b, vstr_tri5gh, + cis[i + 3]); + break; + + case HNBU_RXPO2G: + ASSERT(sromrev == 3); + varbuf_append(&b, vstr_rxpo2g, + cis[i + 1]); + break; + + case HNBU_RXPO5G: + ASSERT(sromrev == 3); + varbuf_append(&b, vstr_rxpo5g, + cis[i + 1]); + break; + + case HNBU_MACADDR: + if (!(ETHER_ISNULLADDR(&cis[i + 1])) && + !(ETHER_ISMULTI(&cis[i + 1]))) { + snprintf(eabuf, sizeof(eabuf), + "%pM", &cis[i + 1]); + + /* set boardnum if HNBU_BOARDNUM not seen yet */ + if (boardnum == -1) + boardnum = + (cis[i + 5] << 8) + + cis[i + 6]; + } + break; + + case HNBU_LEDDC: + /* CIS leddc only has 16bits, convert it to 32bits */ + w32 = ((cis[i + 2] << 24) | /* oncount */ + (cis[i + 1] << 8)); /* offcount */ + varbuf_append(&b, vstr_leddc, w32); + break; + + case HNBU_CHAINSWITCH: + varbuf_append(&b, vstr_txchain, + cis[i + 1]); + varbuf_append(&b, vstr_rxchain, + cis[i + 2]); + varbuf_append(&b, vstr_antswitch, + (cis[i + 4] << 8) + + cis[i + 3]); + break; + + case HNBU_REGREV: + varbuf_append(&b, vstr_regrev, + cis[i + 1]); + break; + + case HNBU_FEM:{ + u16 fem = + (cis[i + 2] << 8) + cis[i + + 1]; + varbuf_append(&b, + vstr_antswctl2g, + (fem & + SROM8_FEM_ANTSWLUT_MASK) + >> + SROM8_FEM_ANTSWLUT_SHIFT); + varbuf_append(&b, vstr_triso2g, + (fem & + SROM8_FEM_TR_ISO_MASK) + >> + SROM8_FEM_TR_ISO_SHIFT); + varbuf_append(&b, + vstr_pdetrange2g, + (fem & + SROM8_FEM_PDET_RANGE_MASK) + >> + SROM8_FEM_PDET_RANGE_SHIFT); + varbuf_append(&b, + vstr_extpagain2g, + (fem & + SROM8_FEM_EXTPA_GAIN_MASK) + >> + SROM8_FEM_EXTPA_GAIN_SHIFT); + varbuf_append(&b, + vstr_tssipos2g, + (fem & + SROM8_FEM_TSSIPOS_MASK) + >> + SROM8_FEM_TSSIPOS_SHIFT); + if (tlen < 5) + break; + + fem = + (cis[i + 4] << 8) + cis[i + + 3]; + varbuf_append(&b, + vstr_antswctl5g, + (fem & + SROM8_FEM_ANTSWLUT_MASK) + >> + SROM8_FEM_ANTSWLUT_SHIFT); + varbuf_append(&b, vstr_triso5g, + (fem & + SROM8_FEM_TR_ISO_MASK) + >> + SROM8_FEM_TR_ISO_SHIFT); + varbuf_append(&b, + vstr_pdetrange5g, + (fem & + SROM8_FEM_PDET_RANGE_MASK) + >> + SROM8_FEM_PDET_RANGE_SHIFT); + varbuf_append(&b, + vstr_extpagain5g, + (fem & + SROM8_FEM_EXTPA_GAIN_MASK) + >> + SROM8_FEM_EXTPA_GAIN_SHIFT); + varbuf_append(&b, + vstr_tssipos5g, + (fem & + SROM8_FEM_TSSIPOS_MASK) + >> + SROM8_FEM_TSSIPOS_SHIFT); + break; + } + + case HNBU_PAPARMS_C0: + varbuf_append(&b, vstr_maxp2ga0, + cis[i + 1]); + varbuf_append(&b, vstr_itt2ga0, + cis[i + 2]); + varbuf_append(&b, vstr_pa, 2, 0, 0, + (cis[i + 4] << 8) + + cis[i + 3]); + varbuf_append(&b, vstr_pa, 2, 1, 0, + (cis[i + 6] << 8) + + cis[i + 5]); + varbuf_append(&b, vstr_pa, 2, 2, 0, + (cis[i + 8] << 8) + + cis[i + 7]); + if (tlen < 31) + break; + + varbuf_append(&b, vstr_maxp5ga0, + cis[i + 9]); + varbuf_append(&b, vstr_itt5ga0, + cis[i + 10]); + varbuf_append(&b, vstr_maxp5gha0, + cis[i + 11]); + varbuf_append(&b, vstr_maxp5gla0, + cis[i + 12]); + varbuf_append(&b, vstr_pa, 5, 0, 0, + (cis[i + 14] << 8) + + cis[i + 13]); + varbuf_append(&b, vstr_pa, 5, 1, 0, + (cis[i + 16] << 8) + + cis[i + 15]); + varbuf_append(&b, vstr_pa, 5, 2, 0, + (cis[i + 18] << 8) + + cis[i + 17]); + varbuf_append(&b, vstr_pahl, 5, 'l', 0, + 0, + (cis[i + 20] << 8) + + cis[i + 19]); + varbuf_append(&b, vstr_pahl, 5, 'l', 1, + 0, + (cis[i + 22] << 8) + + cis[i + 21]); + varbuf_append(&b, vstr_pahl, 5, 'l', 2, + 0, + (cis[i + 24] << 8) + + cis[i + 23]); + varbuf_append(&b, vstr_pahl, 5, 'h', 0, + 0, + (cis[i + 26] << 8) + + cis[i + 25]); + varbuf_append(&b, vstr_pahl, 5, 'h', 1, + 0, + (cis[i + 28] << 8) + + cis[i + 27]); + varbuf_append(&b, vstr_pahl, 5, 'h', 2, + 0, + (cis[i + 30] << 8) + + cis[i + 29]); + break; + + case HNBU_PAPARMS_C1: + varbuf_append(&b, vstr_maxp2ga1, + cis[i + 1]); + varbuf_append(&b, vstr_itt2ga1, + cis[i + 2]); + varbuf_append(&b, vstr_pa, 2, 0, 1, + (cis[i + 4] << 8) + + cis[i + 3]); + varbuf_append(&b, vstr_pa, 2, 1, 1, + (cis[i + 6] << 8) + + cis[i + 5]); + varbuf_append(&b, vstr_pa, 2, 2, 1, + (cis[i + 8] << 8) + + cis[i + 7]); + if (tlen < 31) + break; + + varbuf_append(&b, vstr_maxp5ga1, + cis[i + 9]); + varbuf_append(&b, vstr_itt5ga1, + cis[i + 10]); + varbuf_append(&b, vstr_maxp5gha1, + cis[i + 11]); + varbuf_append(&b, vstr_maxp5gla1, + cis[i + 12]); + varbuf_append(&b, vstr_pa, 5, 0, 1, + (cis[i + 14] << 8) + + cis[i + 13]); + varbuf_append(&b, vstr_pa, 5, 1, 1, + (cis[i + 16] << 8) + + cis[i + 15]); + varbuf_append(&b, vstr_pa, 5, 2, 1, + (cis[i + 18] << 8) + + cis[i + 17]); + varbuf_append(&b, vstr_pahl, 5, 'l', 0, + 1, + (cis[i + 20] << 8) + + cis[i + 19]); + varbuf_append(&b, vstr_pahl, 5, 'l', 1, + 1, + (cis[i + 22] << 8) + + cis[i + 21]); + varbuf_append(&b, vstr_pahl, 5, 'l', 2, + 1, + (cis[i + 24] << 8) + + cis[i + 23]); + varbuf_append(&b, vstr_pahl, 5, 'h', 0, + 1, + (cis[i + 26] << 8) + + cis[i + 25]); + varbuf_append(&b, vstr_pahl, 5, 'h', 1, + 1, + (cis[i + 28] << 8) + + cis[i + 27]); + varbuf_append(&b, vstr_pahl, 5, 'h', 2, + 1, + (cis[i + 30] << 8) + + cis[i + 29]); + break; + + case HNBU_PO_CCKOFDM: + varbuf_append(&b, vstr_cck2gpo, + (cis[i + 2] << 8) + + cis[i + 1]); + varbuf_append(&b, vstr_ofdm2gpo, + (cis[i + 6] << 24) + + (cis[i + 5] << 16) + + (cis[i + 4] << 8) + + cis[i + 3]); + if (tlen < 19) + break; + + varbuf_append(&b, vstr_ofdm5gpo, + (cis[i + 10] << 24) + + (cis[i + 9] << 16) + + (cis[i + 8] << 8) + + cis[i + 7]); + varbuf_append(&b, vstr_ofdm5glpo, + (cis[i + 14] << 24) + + (cis[i + 13] << 16) + + (cis[i + 12] << 8) + + cis[i + 11]); + varbuf_append(&b, vstr_ofdm5ghpo, + (cis[i + 18] << 24) + + (cis[i + 17] << 16) + + (cis[i + 16] << 8) + + cis[i + 15]); + break; + + case HNBU_PO_MCS2G: + for (j = 0; j <= (tlen / 2); j++) { + varbuf_append(&b, vstr_mcspo, 2, + j, + (cis + [i + 2 + + 2 * j] << 8) + + cis[i + 1 + + 2 * j]); + } + break; + + case HNBU_PO_MCS5GM: + for (j = 0; j <= (tlen / 2); j++) { + varbuf_append(&b, vstr_mcspo, 5, + j, + (cis + [i + 2 + + 2 * j] << 8) + + cis[i + 1 + + 2 * j]); + } + break; + + case HNBU_PO_MCS5GLH: + for (j = 0; j <= (tlen / 4); j++) { + varbuf_append(&b, vstr_mcspohl, + 5, 'l', j, + (cis + [i + 2 + + 2 * j] << 8) + + cis[i + 1 + + 2 * j]); + } + + for (j = 0; j <= (tlen / 4); j++) { + varbuf_append(&b, vstr_mcspohl, + 5, 'h', j, + (cis + [i + + ((tlen / 2) + + 2) + + 2 * j] << 8) + + cis[i + + ((tlen / 2) + + 1) + 2 * j]); + } + + break; + + case HNBU_PO_CDD: + varbuf_append(&b, vstr_cddpo, + (cis[i + 2] << 8) + + cis[i + 1]); + break; + + case HNBU_PO_STBC: + varbuf_append(&b, vstr_stbcpo, + (cis[i + 2] << 8) + + cis[i + 1]); + break; + + case HNBU_PO_40M: + varbuf_append(&b, vstr_bw40po, + (cis[i + 2] << 8) + + cis[i + 1]); + break; + + case HNBU_PO_40MDUP: + varbuf_append(&b, vstr_bwduppo, + (cis[i + 2] << 8) + + cis[i + 1]); + break; + + case HNBU_OFDMPO5G: + varbuf_append(&b, vstr_ofdm5gpo, + (cis[i + 4] << 24) + + (cis[i + 3] << 16) + + (cis[i + 2] << 8) + + cis[i + 1]); + varbuf_append(&b, vstr_ofdm5glpo, + (cis[i + 8] << 24) + + (cis[i + 7] << 16) + + (cis[i + 6] << 8) + + cis[i + 5]); + varbuf_append(&b, vstr_ofdm5ghpo, + (cis[i + 12] << 24) + + (cis[i + 11] << 16) + + (cis[i + 10] << 8) + + cis[i + 9]); + break; + + case HNBU_CUSTOM1: + varbuf_append(&b, vstr_custom, 1, + ((cis[i + 4] << 24) + + (cis[i + 3] << 16) + + (cis[i + 2] << 8) + + cis[i + 1])); + break; + +#if defined(BCMSDIO) + case HNBU_SROM3SWRGN: + if (tlen >= 73) { + u16 srom[35]; + u8 srev = cis[i + 1 + 70]; + ASSERT(srev == 3); + /* make tuple value 16-bit aligned and parse it */ + bcopy(&cis[i + 1], srom, + sizeof(srom)); + _initvars_srom_pci(srev, srom, + SROM3_SWRGN_OFF, + &b); + /* 2.4G antenna gain is included in SROM */ + ag_init = true; + /* Ethernet MAC address is included in SROM */ + eabuf[0] = 0; + boardnum = -1; + } + /* create extra variables */ + if (tlen >= 75) + varbuf_append(&b, vstr_vendid, + (cis[i + 1 + 73] + << 8) + cis[i + + 1 + + 72]); + if (tlen >= 77) + varbuf_append(&b, vstr_devid, + (cis[i + 1 + 75] + << 8) + cis[i + + 1 + + 74]); + if (tlen >= 79) + varbuf_append(&b, vstr_xtalfreq, + (cis[i + 1 + 77] + << 8) + cis[i + + 1 + + 76]); + break; +#endif /* defined(BCMSDIO) */ + + case HNBU_CCKFILTTYPE: + varbuf_append(&b, vstr_cckdigfilttype, + (cis[i + 1])); + break; + } + + break; + } + i += tlen; + } while (tup != CISTPL_END); + } + + if (boardnum != -1) { + varbuf_append(&b, vstr_boardnum, boardnum); + } + + if (eabuf[0]) { + varbuf_append(&b, vstr_macaddr, eabuf); + } + + /* if there is no antenna gain field, set default */ + if (getvar(NULL, "ag0") == NULL && ag_init == false) { + varbuf_append(&b, vstr_ag, 0, 0xff); + } + + /* final nullbyte terminator */ + ASSERT(b.size >= 1); + *b.buf++ = '\0'; + + ASSERT(b.buf - base <= MAXSZ_NVRAM_VARS); + err = initvars_table(osh, base, b.buf, vars, count); + + kfree(base); + return err; +} + +/* In chips with chipcommon rev 32 and later, the srom is in chipcommon, + * not in the bus cores. + */ +static u16 +srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, u32 cmd, uint wordoff, + u16 data) +{ + chipcregs_t *cc = (chipcregs_t *) ccregs; + uint wait_cnt = 1000; + + if ((cmd == SRC_OP_READ) || (cmd == SRC_OP_WRITE)) { + W_REG(osh, &cc->sromaddress, wordoff * 2); + if (cmd == SRC_OP_WRITE) + W_REG(osh, &cc->sromdata, data); + } + + W_REG(osh, &cc->sromcontrol, SRC_START | cmd); + + while (wait_cnt--) { + if ((R_REG(osh, &cc->sromcontrol) & SRC_BUSY) == 0) + break; + } + + if (!wait_cnt) { + BS_ERROR(("%s: Command 0x%x timed out\n", __func__, cmd)); + return 0xffff; + } + if (cmd == SRC_OP_READ) + return (u16) R_REG(osh, &cc->sromdata); + else + return 0xffff; +} + +/* + * Read in and validate sprom. + * Return 0 on success, nonzero on error. + */ +static int +sprom_read_pci(osl_t *osh, si_t *sih, u16 *sprom, uint wordoff, + u16 *buf, uint nwords, bool check_crc) +{ + int err = 0; + uint i; + void *ccregs = NULL; + + /* read the sprom */ + for (i = 0; i < nwords; i++) { + + if (sih->ccrev > 31 && ISSIM_ENAB(sih)) { + /* use indirect since direct is too slow on QT */ + if ((sih->cccaps & CC_CAP_SROM) == 0) + return 1; + + ccregs = (void *)((u8 *) sprom - CC_SROM_OTP); + buf[i] = + srom_cc_cmd(sih, osh, ccregs, SRC_OP_READ, + wordoff + i, 0); + + } else { + if (ISSIM_ENAB(sih)) + buf[i] = R_REG(osh, &sprom[wordoff + i]); + + buf[i] = R_REG(osh, &sprom[wordoff + i]); + } + + } + + /* bypass crc checking for simulation to allow srom hack */ + if (ISSIM_ENAB(sih)) + return err; + + if (check_crc) { + + if (buf[0] == 0xffff) { + /* The hardware thinks that an srom that starts with 0xffff + * is blank, regardless of the rest of the content, so declare + * it bad. + */ + BS_ERROR(("%s: buf[0] = 0x%x, returning bad-crc\n", + __func__, buf[0])); + return 1; + } + + /* fixup the endianness so crc8 will pass */ + htol16_buf(buf, nwords * 2); + if (hndcrc8((u8 *) buf, nwords * 2, CRC8_INIT_VALUE) != + CRC8_GOOD_VALUE) { + /* DBG only pci always read srom4 first, then srom8/9 */ + /* BS_ERROR(("%s: bad crc\n", __func__)); */ + err = 1; + } + /* now correct the endianness of the byte array */ + ltoh16_buf(buf, nwords * 2); + } + return err; +} + +#if defined(BCMNVRAMR) +static int otp_read_pci(osl_t *osh, si_t *sih, u16 *buf, uint bufsz) +{ + u8 *otp; + uint sz = OTP_SZ_MAX / 2; /* size in words */ + int err = 0; + + ASSERT(bufsz <= OTP_SZ_MAX); + + otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC); + if (otp == NULL) { + return BCME_ERROR; + } + + err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz); + + bcopy(otp, buf, bufsz); + + if (otp) + kfree(otp); + + /* Check CRC */ + if (buf[0] == 0xffff) { + /* The hardware thinks that an srom that starts with 0xffff + * is blank, regardless of the rest of the content, so declare + * it bad. + */ + BS_ERROR(("%s: buf[0] = 0x%x, returning bad-crc\n", __func__, + buf[0])); + return 1; + } + + /* fixup the endianness so crc8 will pass */ + htol16_buf(buf, bufsz); + if (hndcrc8((u8 *) buf, SROM4_WORDS * 2, CRC8_INIT_VALUE) != + CRC8_GOOD_VALUE) { + BS_ERROR(("%s: bad crc\n", __func__)); + err = 1; + } + /* now correct the endianness of the byte array */ + ltoh16_buf(buf, bufsz); + + return err; +} +#endif /* defined(BCMNVRAMR) */ +/* +* Create variable table from memory. +* Return 0 on success, nonzero on error. +*/ +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, + uint *count) +{ + int c = (int)(end - start); + + /* do it only when there is more than just the null string */ + if (c > 1) { + char *vp = kmalloc(c, GFP_ATOMIC); + ASSERT(vp != NULL); + if (!vp) + return BCME_NOMEM; + bcopy(start, vp, c); + *vars = vp; + *count = c; + } else { + *vars = NULL; + *count = 0; + } + + return 0; +} + +/* + * Find variables with <devpath> from flash. 'base' points to the beginning + * of the table upon enter and to the end of the table upon exit when success. + * Return 0 on success, nonzero on error. + */ +static int initvars_flash(si_t *sih, osl_t *osh, char **base, uint len) +{ + char *vp = *base; + char *flash; + int err; + char *s; + uint l, dl, copy_len; + char devpath[SI_DEVPATH_BUFSZ]; + + /* allocate memory and read in flash */ + flash = kmalloc(NVRAM_SPACE, GFP_ATOMIC); + if (!flash) + return BCME_NOMEM; + err = nvram_getall(flash, NVRAM_SPACE); + if (err) + goto exit; + + si_devpath(sih, devpath, sizeof(devpath)); + + /* grab vars with the <devpath> prefix in name */ + dl = strlen(devpath); + for (s = flash; s && *s; s += l + 1) { + l = strlen(s); + + /* skip non-matching variable */ + if (strncmp(s, devpath, dl)) + continue; + + /* is there enough room to copy? */ + copy_len = l - dl + 1; + if (len < copy_len) { + err = BCME_BUFTOOSHORT; + goto exit; + } + + /* no prefix, just the name=value */ + strncpy(vp, &s[dl], copy_len); + vp += copy_len; + len -= copy_len; + } + + /* add null string as terminator */ + if (len < 1) { + err = BCME_BUFTOOSHORT; + goto exit; + } + *vp++ = '\0'; + + *base = vp; + + exit: kfree(flash); + return err; +} + +/* + * Initialize nonvolatile variable table from flash. + * Return 0 on success, nonzero on error. + */ +static int initvars_flash_si(si_t *sih, char **vars, uint *count) +{ + osl_t *osh = si_osh(sih); + char *vp, *base; + int err; + + ASSERT(vars != NULL); + ASSERT(count != NULL); + + base = vp = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC); + ASSERT(vp != NULL); + if (!vp) + return BCME_NOMEM; + + err = initvars_flash(sih, osh, &vp, MAXSZ_NVRAM_VARS); + if (err == 0) + err = initvars_table(osh, base, vp, vars, count); + + kfree(base); + + return err; +} + +/* Parse SROM and create name=value pairs. 'srom' points to + * the SROM word array. 'off' specifies the offset of the + * first word 'srom' points to, which should be either 0 or + * SROM3_SWRG_OFF (full SROM or software region). + */ + +static uint mask_shift(u16 mask) +{ + uint i; + for (i = 0; i < (sizeof(mask) << 3); i++) { + if (mask & (1 << i)) + return i; + } + ASSERT(mask); + return 0; +} + +static uint mask_width(u16 mask) +{ + int i; + for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) { + if (mask & (1 << i)) + return (uint) (i - mask_shift(mask) + 1); + } + ASSERT(mask); + return 0; +} + +#if defined(BCMDBG) +static bool mask_valid(u16 mask) +{ + uint shift = mask_shift(mask); + uint width = mask_width(mask); + return mask == ((~0 << shift) & ~(~0 << (shift + width))); +} +#endif /* BCMDBG */ + +static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b) +{ + u16 w; + u32 val; + const sromvar_t *srv; + uint width; + uint flags; + u32 sr = (1 << sromrev); + + varbuf_append(b, "sromrev=%d", sromrev); + + for (srv = pci_sromvars; srv->name != NULL; srv++) { + const char *name; + + if ((srv->revmask & sr) == 0) + continue; + + if (srv->off < off) + continue; + + flags = srv->flags; + name = srv->name; + + /* This entry is for mfgc only. Don't generate param for it, */ + if (flags & SRFL_NOVAR) + continue; + + if (flags & SRFL_ETHADDR) { + struct ether_addr ea; + + ea.octet[0] = (srom[srv->off - off] >> 8) & 0xff; + ea.octet[1] = srom[srv->off - off] & 0xff; + ea.octet[2] = (srom[srv->off + 1 - off] >> 8) & 0xff; + ea.octet[3] = srom[srv->off + 1 - off] & 0xff; + ea.octet[4] = (srom[srv->off + 2 - off] >> 8) & 0xff; + ea.octet[5] = srom[srv->off + 2 - off] & 0xff; + + varbuf_append(b, "%s=%pM", name, ea.octet); + } else { + ASSERT(mask_valid(srv->mask)); + ASSERT(mask_width(srv->mask)); + + w = srom[srv->off - off]; + val = (w & srv->mask) >> mask_shift(srv->mask); + width = mask_width(srv->mask); + + while (srv->flags & SRFL_MORE) { + srv++; + ASSERT(srv->name != NULL); + + if (srv->off == 0 || srv->off < off) + continue; + + ASSERT(mask_valid(srv->mask)); + ASSERT(mask_width(srv->mask)); + + w = srom[srv->off - off]; + val += + ((w & srv->mask) >> mask_shift(srv-> + mask)) << + width; + width += mask_width(srv->mask); + } + + if ((flags & SRFL_NOFFS) + && ((int)val == (1 << width) - 1)) + continue; + + if (flags & SRFL_CCODE) { + if (val == 0) + varbuf_append(b, "ccode="); + else + varbuf_append(b, "ccode=%c%c", + (val >> 8), (val & 0xff)); + } + /* LED Powersave duty cycle has to be scaled: + *(oncount >> 24) (offcount >> 8) + */ + else if (flags & SRFL_LEDDC) { + u32 w32 = (((val >> 8) & 0xff) << 24) | /* oncount */ + (((val & 0xff)) << 8); /* offcount */ + varbuf_append(b, "leddc=%d", w32); + } else if (flags & SRFL_PRHEX) + varbuf_append(b, "%s=0x%x", name, val); + else if ((flags & SRFL_PRSIGN) + && (val & (1 << (width - 1)))) + varbuf_append(b, "%s=%d", name, + (int)(val | (~0 << width))); + else + varbuf_append(b, "%s=%u", name, val); + } + } + + if (sromrev >= 4) { + /* Do per-path variables */ + uint p, pb, psz; + + if (sromrev >= 8) { + pb = SROM8_PATH0; + psz = SROM8_PATH1 - SROM8_PATH0; + } else { + pb = SROM4_PATH0; + psz = SROM4_PATH1 - SROM4_PATH0; + } + + for (p = 0; p < MAX_PATH_SROM; p++) { + for (srv = perpath_pci_sromvars; srv->name != NULL; + srv++) { + if ((srv->revmask & sr) == 0) + continue; + + if (pb + srv->off < off) + continue; + + /* This entry is for mfgc only. Don't generate param for it, */ + if (srv->flags & SRFL_NOVAR) + continue; + + w = srom[pb + srv->off - off]; + + ASSERT(mask_valid(srv->mask)); + val = (w & srv->mask) >> mask_shift(srv->mask); + width = mask_width(srv->mask); + + /* Cheating: no per-path var is more than 1 word */ + + if ((srv->flags & SRFL_NOFFS) + && ((int)val == (1 << width) - 1)) + continue; + + if (srv->flags & SRFL_PRHEX) + varbuf_append(b, "%s%d=0x%x", srv->name, + p, val); + else + varbuf_append(b, "%s%d=%d", srv->name, + p, val); + } + pb += psz; + } + } +} + +/* + * Initialize nonvolatile variable table from sprom. + * Return 0 on success, nonzero on error. + */ +static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, uint *count) +{ + u16 *srom, *sromwindow; + u8 sromrev = 0; + u32 sr; + varbuf_t b; + char *vp, *base = NULL; + osl_t *osh = si_osh(sih); + bool flash = false; + int err = 0; + + /* + * Apply CRC over SROM content regardless SROM is present or not, + * and use variable <devpath>sromrev's existance in flash to decide + * if we should return an error when CRC fails or read SROM variables + * from flash. + */ + srom = kmalloc(SROM_MAX, GFP_ATOMIC); + ASSERT(srom != NULL); + if (!srom) + return -2; + + sromwindow = (u16 *) SROM_OFFSET(sih); + if (si_is_sprom_available(sih)) { + err = + sprom_read_pci(osh, sih, sromwindow, 0, srom, SROM_WORDS, + true); + + if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) || + (((sih->buscoretype == PCIE_CORE_ID) + && (sih->buscorerev >= 6)) + || ((sih->buscoretype == PCI_CORE_ID) + && (sih->buscorerev >= 0xe)))) { + /* sromrev >= 4, read more */ + err = + sprom_read_pci(osh, sih, sromwindow, 0, srom, + SROM4_WORDS, true); + sromrev = srom[SROM4_CRCREV] & 0xff; + if (err) + BS_ERROR(("%s: srom %d, bad crc\n", __func__, + sromrev)); + + } else if (err == 0) { + /* srom is good and is rev < 4 */ + /* top word of sprom contains version and crc8 */ + sromrev = srom[SROM_CRCREV] & 0xff; + /* bcm4401 sroms misprogrammed */ + if (sromrev == 0x10) + sromrev = 1; + } + } +#if defined(BCMNVRAMR) + /* Use OTP if SPROM not available */ + else if ((err = otp_read_pci(osh, sih, srom, SROM_MAX)) == 0) { + /* OTP only contain SROM rev8/rev9 for now */ + sromrev = srom[SROM4_CRCREV] & 0xff; + } +#endif + else { + err = 1; + BS_ERROR(("Neither SPROM nor OTP has valid image\n")); + } + + /* We want internal/wltest driver to come up with default sromvars so we can + * program a blank SPROM/OTP. + */ + if (err) { + char *value; + u32 val; + val = 0; + + value = si_getdevpathvar(sih, "sromrev"); + if (value) { + sromrev = (u8) simple_strtoul(value, NULL, 0); + flash = true; + goto varscont; + } + + BS_ERROR(("%s, SROM CRC Error\n", __func__)); + + value = si_getnvramflvar(sih, "sromrev"); + if (value) { + err = 0; + goto errout; + } + + { + err = -1; + goto errout; + } + } + + varscont: + /* Bitmask for the sromrev */ + sr = 1 << sromrev; + + /* srom version check: Current valid versions: 1, 2, 3, 4, 5, 8, 9 */ + if ((sr & 0x33e) == 0) { + err = -2; + goto errout; + } + + ASSERT(vars != NULL); + ASSERT(count != NULL); + + base = vp = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC); + ASSERT(vp != NULL); + if (!vp) { + err = -2; + goto errout; + } + + /* read variables from flash */ + if (flash) { + err = initvars_flash(sih, osh, &vp, MAXSZ_NVRAM_VARS); + if (err) + goto errout; + goto varsdone; + } + + varbuf_init(&b, base, MAXSZ_NVRAM_VARS); + + /* parse SROM into name=value pairs. */ + _initvars_srom_pci(sromrev, srom, 0, &b); + + /* final nullbyte terminator */ + ASSERT(b.size >= 1); + vp = b.buf; + *vp++ = '\0'; + + ASSERT((vp - base) <= MAXSZ_NVRAM_VARS); + + varsdone: + err = initvars_table(osh, base, vp, vars, count); + + errout: + if (base) + kfree(base); + + kfree(srom); + return err; +} + +#ifdef BCMSDIO +/* + * Read the SDIO cis and call parsecis to initialize the vars. + * Return 0 on success, nonzero on error. + */ +static int initvars_cis_sdio(osl_t *osh, char **vars, uint *count) +{ + u8 *cis[SBSDIO_NUM_FUNCTION + 1]; + uint fn, numfn; + int rc = 0; + + numfn = bcmsdh_query_iofnum(NULL); + ASSERT(numfn <= SDIOD_MAX_IOFUNCS); + + for (fn = 0; fn <= numfn; fn++) { + cis[fn] = kzalloc(SBSDIO_CIS_SIZE_LIMIT, GFP_ATOMIC); + if (cis[fn] == NULL) { + rc = -1; + break; + } + + if (bcmsdh_cis_read(NULL, fn, cis[fn], SBSDIO_CIS_SIZE_LIMIT) != + 0) { + kfree(cis[fn]); + rc = -2; + break; + } + } + + if (!rc) + rc = srom_parsecis(osh, cis, fn, vars, count); + + while (fn-- > 0) + kfree(cis[fn]); + + return rc; +} + +/* set SDIO sprom command register */ +static int sprom_cmd_sdio(osl_t *osh, u8 cmd) +{ + u8 status = 0; + uint wait_cnt = 1000; + + /* write sprom command register */ + bcmsdh_cfg_write(NULL, SDIO_FUNC_1, SBSDIO_SPROM_CS, cmd, NULL); + + /* wait status */ + while (wait_cnt--) { + status = + bcmsdh_cfg_read(NULL, SDIO_FUNC_1, SBSDIO_SPROM_CS, NULL); + if (status & SBSDIO_SPROM_DONE) + return 0; + } + + return 1; +} + +/* read a word from the SDIO srom */ +static int sprom_read_sdio(osl_t *osh, u16 addr, u16 *data) +{ + u8 addr_l, addr_h, data_l, data_h; + + addr_l = (u8) ((addr * 2) & 0xff); + addr_h = (u8) (((addr * 2) >> 8) & 0xff); + + /* set address */ + bcmsdh_cfg_write(NULL, SDIO_FUNC_1, SBSDIO_SPROM_ADDR_HIGH, addr_h, + NULL); + bcmsdh_cfg_write(NULL, SDIO_FUNC_1, SBSDIO_SPROM_ADDR_LOW, addr_l, + NULL); + + /* do read */ + if (sprom_cmd_sdio(osh, SBSDIO_SPROM_READ)) + return 1; + + /* read data */ + data_h = + bcmsdh_cfg_read(NULL, SDIO_FUNC_1, SBSDIO_SPROM_DATA_HIGH, NULL); + data_l = + bcmsdh_cfg_read(NULL, SDIO_FUNC_1, SBSDIO_SPROM_DATA_LOW, NULL); + + *data = (data_h << 8) | data_l; + return 0; +} +#endif /* BCMSDIO */ + +static int initvars_srom_si(si_t *sih, osl_t *osh, void *curmap, char **vars, + uint *varsz) +{ + /* Search flash nvram section for srom variables */ + return initvars_flash_si(sih, vars, varsz); +} diff --git a/drivers/staging/brcm80211/util/bcmutils.c b/drivers/staging/brcm80211/util/bcmutils.c new file mode 100644 index 0000000..9789ea4 --- /dev/null +++ b/drivers/staging/brcm80211/util/bcmutils.c @@ -0,0 +1,1044 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <linux/ctype.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <bcmdefs.h> +#include <stdarg.h> +#include <osl.h> +#include <linuxver.h> +#include <bcmutils.h> +#include <siutils.h> +#include <bcmnvram.h> +#include <bcmendian.h> +#include <bcmdevs.h> +#include <proto/ethernet.h> +#include <proto/802.1d.h> +#include <proto/802.11.h> + + +/* copy a buffer into a pkt buffer chain */ +uint pktfrombuf(osl_t *osh, void *p, uint offset, int len, unsigned char *buf) +{ + uint n, ret = 0; + + /* skip 'offset' bytes */ + for (; p && offset; p = PKTNEXT(p)) { + if (offset < (uint) PKTLEN(p)) + break; + offset -= PKTLEN(p); + } + + if (!p) + return 0; + + /* copy the data */ + for (; p && len; p = PKTNEXT(p)) { + n = min((uint) PKTLEN(p) - offset, (uint) len); + bcopy(buf, PKTDATA(p) + offset, n); + buf += n; + len -= n; + ret += n; + offset = 0; + } + + return ret; +} +/* return total length of buffer chain */ +uint BCMFASTPATH pkttotlen(osl_t *osh, void *p) +{ + uint total; + + total = 0; + for (; p; p = PKTNEXT(p)) + total += PKTLEN(p); + return total; +} + +/* + * osl multiple-precedence packet queue + * hi_prec is always >= the number of the highest non-empty precedence + */ +void *BCMFASTPATH pktq_penq(struct pktq *pq, int prec, void *p) +{ + struct pktq_prec *q; + + ASSERT(prec >= 0 && prec < pq->num_prec); + ASSERT(PKTLINK(p) == NULL); /* queueing chains not allowed */ + + ASSERT(!pktq_full(pq)); + ASSERT(!pktq_pfull(pq, prec)); + + q = &pq->q[prec]; + + if (q->head) + PKTSETLINK(q->tail, p); + else + q->head = p; + + q->tail = p; + q->len++; + + pq->len++; + + if (pq->hi_prec < prec) + pq->hi_prec = (u8) prec; + + return p; +} + +void *BCMFASTPATH pktq_penq_head(struct pktq *pq, int prec, void *p) +{ + struct pktq_prec *q; + + ASSERT(prec >= 0 && prec < pq->num_prec); + ASSERT(PKTLINK(p) == NULL); /* queueing chains not allowed */ + + ASSERT(!pktq_full(pq)); + ASSERT(!pktq_pfull(pq, prec)); + + q = &pq->q[prec]; + + if (q->head == NULL) + q->tail = p; + + PKTSETLINK(p, q->head); + q->head = p; + q->len++; + + pq->len++; + + if (pq->hi_prec < prec) + pq->hi_prec = (u8) prec; + + return p; +} + +void *BCMFASTPATH pktq_pdeq(struct pktq *pq, int prec) +{ + struct pktq_prec *q; + void *p; + + ASSERT(prec >= 0 && prec < pq->num_prec); + + q = &pq->q[prec]; + + p = q->head; + if (p == NULL) + return NULL; + + q->head = PKTLINK(p); + if (q->head == NULL) + q->tail = NULL; + + q->len--; + + pq->len--; + + PKTSETLINK(p, NULL); + + return p; +} + +void *BCMFASTPATH pktq_pdeq_tail(struct pktq *pq, int prec) +{ + struct pktq_prec *q; + void *p, *prev; + + ASSERT(prec >= 0 && prec < pq->num_prec); + + q = &pq->q[prec]; + + p = q->head; + if (p == NULL) + return NULL; + + for (prev = NULL; p != q->tail; p = PKTLINK(p)) + prev = p; + + if (prev) + PKTSETLINK(prev, NULL); + else + q->head = NULL; + + q->tail = prev; + q->len--; + + pq->len--; + + return p; +} + +#ifdef BRCM_FULLMAC +void pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir) +{ + struct pktq_prec *q; + void *p; + + q = &pq->q[prec]; + p = q->head; + while (p) { + q->head = PKTLINK(p); + PKTSETLINK(p, NULL); + PKTFREE(osh, p, dir); + q->len--; + pq->len--; + p = q->head; + } + ASSERT(q->len == 0); + q->tail = NULL; +} + +void pktq_flush(osl_t *osh, struct pktq *pq, bool dir) +{ + int prec; + for (prec = 0; prec < pq->num_prec; prec++) + pktq_pflush(osh, pq, prec, dir); + ASSERT(pq->len == 0); +} +#else /* !BRCM_FULLMAC */ +void +pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir, ifpkt_cb_t fn, + int arg) +{ + struct pktq_prec *q; + void *p, *prev = NULL; + + q = &pq->q[prec]; + p = q->head; + while (p) { + if (fn == NULL || (*fn) (p, arg)) { + bool head = (p == q->head); + if (head) + q->head = PKTLINK(p); + else + PKTSETLINK(prev, PKTLINK(p)); + PKTSETLINK(p, NULL); + PKTFREE(osh, p, dir); + q->len--; + pq->len--; + p = (head ? q->head : PKTLINK(prev)); + } else { + prev = p; + p = PKTLINK(p); + } + } + + if (q->head == NULL) { + ASSERT(q->len == 0); + q->tail = NULL; + } +} + +void pktq_flush(osl_t *osh, struct pktq *pq, bool dir, ifpkt_cb_t fn, int arg) +{ + int prec; + for (prec = 0; prec < pq->num_prec; prec++) + pktq_pflush(osh, pq, prec, dir, fn, arg); + if (fn == NULL) + ASSERT(pq->len == 0); +} +#endif /* BRCM_FULLMAC */ + +void pktq_init(struct pktq *pq, int num_prec, int max_len) +{ + int prec; + + ASSERT(num_prec > 0 && num_prec <= PKTQ_MAX_PREC); + + /* pq is variable size; only zero out what's requested */ + bzero(pq, + offsetof(struct pktq, q) + (sizeof(struct pktq_prec) * num_prec)); + + pq->num_prec = (u16) num_prec; + + pq->max = (u16) max_len; + + for (prec = 0; prec < num_prec; prec++) + pq->q[prec].max = pq->max; +} + +void *pktq_peek_tail(struct pktq *pq, int *prec_out) +{ + int prec; + + if (pq->len == 0) + return NULL; + + for (prec = 0; prec < pq->hi_prec; prec++) + if (pq->q[prec].head) + break; + + if (prec_out) + *prec_out = prec; + + return pq->q[prec].tail; +} + +/* Return sum of lengths of a specific set of precedences */ +int pktq_mlen(struct pktq *pq, uint prec_bmp) +{ + int prec, len; + + len = 0; + + for (prec = 0; prec <= pq->hi_prec; prec++) + if (prec_bmp & (1 << prec)) + len += pq->q[prec].len; + + return len; +} +/* Priority dequeue from a specific set of precedences */ +void *BCMFASTPATH pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out) +{ + struct pktq_prec *q; + void *p; + int prec; + + if (pq->len == 0) + return NULL; + + while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL) + pq->hi_prec--; + + while ((prec_bmp & (1 << prec)) == 0 || pq->q[prec].head == NULL) + if (prec-- == 0) + return NULL; + + q = &pq->q[prec]; + + p = q->head; + if (p == NULL) + return NULL; + + q->head = PKTLINK(p); + if (q->head == NULL) + q->tail = NULL; + + q->len--; + + if (prec_out) + *prec_out = prec; + + pq->len--; + + PKTSETLINK(p, NULL); + + return p; +} + +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */ +int bcm_ether_atoe(char *p, struct ether_addr *ea) +{ + int i = 0; + + for (;;) { + ea->octet[i++] = (char)simple_strtoul(p, &p, 16); + if (!*p++ || i == 6) + break; + } + + return i == 6; +} + +/* + * Search the name=value vars for a specific one and return its value. + * Returns NULL if not found. + */ +char *getvar(char *vars, const char *name) +{ + char *s; + int len; + + if (!name) + return NULL; + + len = strlen(name); + if (len == 0) + return NULL; + + /* first look in vars[] */ + for (s = vars; s && *s;) { + if ((bcmp(s, name, len) == 0) && (s[len] == '=')) + return &s[len + 1]; + + while (*s++) + ; + } +#ifdef BRCM_FULLMAC + return NULL; +#else + /* then query nvram */ + return nvram_get(name); +#endif +} + +/* + * Search the vars for a specific one and return its value as + * an integer. Returns 0 if not found. + */ +int getintvar(char *vars, const char *name) +{ + char *val; + + val = getvar(vars, name); + if (val == NULL) + return 0; + + return simple_strtoul(val, NULL, 0); +} + +#if defined(BCMDBG) +/* pretty hex print a pkt buffer chain */ +void prpkt(const char *msg, osl_t *osh, void *p0) +{ + void *p; + + if (msg && (msg[0] != '\0')) + printf("%s:\n", msg); + + for (p = p0; p; p = PKTNEXT(p)) + prhex(NULL, PKTDATA(p), PKTLEN(p)); +} +#endif /* defined(BCMDBG) */ + +static char bcm_undeferrstr[BCME_STRLEN]; + +static const char *bcmerrorstrtable[] = BCMERRSTRINGTABLE; + +/* Convert the error codes into related error strings */ +const char *bcmerrorstr(int bcmerror) +{ + /* check if someone added a bcmerror code but + forgot to add errorstring */ + ASSERT(ABS(BCME_LAST) == (ARRAY_SIZE(bcmerrorstrtable) - 1)); + + if (bcmerror > 0 || bcmerror < BCME_LAST) { + snprintf(bcm_undeferrstr, BCME_STRLEN, "Undefined error %d", + bcmerror); + return bcm_undeferrstr; + } + + ASSERT(strlen(bcmerrorstrtable[-bcmerror]) < BCME_STRLEN); + + return bcmerrorstrtable[-bcmerror]; +} + +/* iovar table lookup */ +const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name) +{ + const bcm_iovar_t *vi; + const char *lookup_name; + + /* skip any ':' delimited option prefixes */ + lookup_name = strrchr(name, ':'); + if (lookup_name != NULL) + lookup_name++; + else + lookup_name = name; + + ASSERT(table != NULL); + + for (vi = table; vi->name; vi++) { + if (!strcmp(vi->name, lookup_name)) + return vi; + } + /* ran to end of table */ + + return NULL; /* var name not found */ +} + +int bcm_iovar_lencheck(const bcm_iovar_t *vi, void *arg, int len, bool set) +{ + int bcmerror = 0; + + /* length check on io buf */ + switch (vi->type) { + case IOVT_BOOL: + case IOVT_INT8: + case IOVT_INT16: + case IOVT_INT32: + case IOVT_UINT8: + case IOVT_UINT16: + case IOVT_UINT32: + /* all integers are s32 sized args at the ioctl interface */ + if (len < (int)sizeof(int)) { + bcmerror = BCME_BUFTOOSHORT; + } + break; + + case IOVT_BUFFER: + /* buffer must meet minimum length requirement */ + if (len < vi->minlen) { + bcmerror = BCME_BUFTOOSHORT; + } + break; + + case IOVT_VOID: + if (!set) { + /* Cannot return nil... */ + bcmerror = BCME_UNSUPPORTED; + } else if (len) { + /* Set is an action w/o parameters */ + bcmerror = BCME_BUFTOOLONG; + } + break; + + default: + /* unknown type for length check in iovar info */ + ASSERT(0); + bcmerror = BCME_UNSUPPORTED; + } + + return bcmerror; +} + +/******************************************************************************* + * crc8 + * + * Computes a crc8 over the input data using the polynomial: + * + * x^8 + x^7 +x^6 + x^4 + x^2 + 1 + * + * The caller provides the initial value (either CRC8_INIT_VALUE + * or the previous returned value) to allow for processing of + * discontiguous blocks of data. When generating the CRC the + * caller is responsible for complementing the final return value + * and inserting it into the byte stream. When checking, a final + * return value of CRC8_GOOD_VALUE indicates a valid CRC. + * + * Reference: Dallas Semiconductor Application Note 27 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms", + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd., + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt + * + * **************************************************************************** + */ + +static const u8 crc8_table[256] = { + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B, + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21, + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF, + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5, + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14, + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E, + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80, + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA, + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95, + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF, + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01, + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B, + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA, + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0, + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E, + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34, + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0, + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A, + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54, + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E, + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF, + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5, + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B, + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61, + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E, + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74, + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA, + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0, + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41, + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B, + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5, + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F +}; + +#define CRC_INNER_LOOP(n, c, x) \ + ((c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]) + +u8 hndcrc8(u8 *pdata, /* pointer to array of data to process */ + uint nbytes, /* number of input data bytes to process */ + u8 crc /* either CRC8_INIT_VALUE or previous return value */ + ) { + /* hard code the crc loop instead of using CRC_INNER_LOOP macro + * to avoid the undefined and unnecessary (u8 >> 8) operation. + */ + while (nbytes-- > 0) + crc = crc8_table[(crc ^ *pdata++) & 0xff]; + + return crc; +} + +/******************************************************************************* + * crc16 + * + * Computes a crc16 over the input data using the polynomial: + * + * x^16 + x^12 +x^5 + 1 + * + * The caller provides the initial value (either CRC16_INIT_VALUE + * or the previous returned value) to allow for processing of + * discontiguous blocks of data. When generating the CRC the + * caller is responsible for complementing the final return value + * and inserting it into the byte stream. When checking, a final + * return value of CRC16_GOOD_VALUE indicates a valid CRC. + * + * Reference: Dallas Semiconductor Application Note 27 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms", + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd., + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt + * + * **************************************************************************** + */ + +static const u16 crc16_table[256] = { + 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF, + 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7, + 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E, + 0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876, + 0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD, + 0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5, + 0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C, + 0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974, + 0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB, + 0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3, + 0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A, + 0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72, + 0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9, + 0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1, + 0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738, + 0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70, + 0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7, + 0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF, + 0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036, + 0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E, + 0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5, + 0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD, + 0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134, + 0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C, + 0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3, + 0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB, + 0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232, + 0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A, + 0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1, + 0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9, + 0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330, + 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78 +}; + +u16 hndcrc16(u8 *pdata, /* pointer to array of data to process */ + uint nbytes, /* number of input data bytes to process */ + u16 crc /* either CRC16_INIT_VALUE or previous return value */ + ) { + while (nbytes-- > 0) + CRC_INNER_LOOP(16, crc, *pdata++); + return crc; +} + +static const u32 crc32_table[256] = { + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3, + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5, + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59, + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F, + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01, + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB, + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F, + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD, + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7, + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79, + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713, + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777, + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45, + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF, + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D +}; + +u32 hndcrc32(u8 *pdata, /* pointer to array of data to process */ + uint nbytes, /* number of input data bytes to process */ + u32 crc /* either CRC32_INIT_VALUE or previous + return value */ +) +{ + u8 *pend; +#ifdef __mips__ + u8 tmp[4]; + unsigned long *tptr = (unsigned long *) tmp; + + /* in case the beginning of the buffer isn't aligned */ + pend = (u8 *) ((uint) (pdata + 3) & 0xfffffffc); + nbytes -= (pend - pdata); + while (pdata < pend) + CRC_INNER_LOOP(32, crc, *pdata++); + + /* handle bulk of data as 32-bit words */ + pend = pdata + (nbytes & 0xfffffffc); + while (pdata < pend) { + *tptr = *(unsigned long *) pdata; + pdata += sizeof(unsigned long *); + CRC_INNER_LOOP(32, crc, tmp[0]); + CRC_INNER_LOOP(32, crc, tmp[1]); + CRC_INNER_LOOP(32, crc, tmp[2]); + CRC_INNER_LOOP(32, crc, tmp[3]); + } + + /* 1-3 bytes at end of buffer */ + pend = pdata + (nbytes & 0x03); + while (pdata < pend) + CRC_INNER_LOOP(32, crc, *pdata++); +#else + pend = pdata + nbytes; + while (pdata < pend) + CRC_INNER_LOOP(32, crc, *pdata++); +#endif /* __mips__ */ + + return crc; +} +/* + * Traverse a string of 1-byte tag/1-byte length/variable-length value + * triples, returning a pointer to the substring whose first element + * matches tag + */ +bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key) +{ + bcm_tlv_t *elt; + int totlen; + + elt = (bcm_tlv_t *) buf; + totlen = buflen; + + /* find tagged parameter */ + while (totlen >= 2) { + int len = elt->len; + + /* validate remaining totlen */ + if ((elt->id == key) && (totlen >= (len + 2))) + return elt; + + elt = (bcm_tlv_t *) ((u8 *) elt + (len + 2)); + totlen -= (len + 2); + } + + return NULL; +} + + +#if defined(BCMDBG) +int +bcm_format_flags(const bcm_bit_desc_t *bd, u32 flags, char *buf, int len) +{ + int i; + char *p = buf; + char hexstr[16]; + int slen = 0, nlen = 0; + u32 bit; + const char *name; + + if (len < 2 || !buf) + return 0; + + buf[0] = '\0'; + + for (i = 0; flags != 0; i++) { + bit = bd[i].bit; + name = bd[i].name; + if (bit == 0 && flags != 0) { + /* print any unnamed bits */ + snprintf(hexstr, 16, "0x%X", flags); + name = hexstr; + flags = 0; /* exit loop */ + } else if ((flags & bit) == 0) + continue; + flags &= ~bit; + nlen = strlen(name); + slen += nlen; + /* count btwn flag space */ + if (flags != 0) + slen += 1; + /* need NULL char as well */ + if (len <= slen) + break; + /* copy NULL char but don't count it */ + strncpy(p, name, nlen + 1); + p += nlen; + /* copy btwn flag space and NULL char */ + if (flags != 0) + p += snprintf(p, 2, " "); + len -= slen; + } + + /* indicate the str was too short */ + if (flags != 0) { + if (len < 2) + p -= 2 - len; /* overwrite last char */ + p += snprintf(p, 2, ">"); + } + + return (int)(p - buf); +} + +/* print bytes formatted as hex to a string. return the resulting string length */ +int bcm_format_hex(char *str, const void *bytes, int len) +{ + int i; + char *p = str; + const u8 *src = (const u8 *)bytes; + + for (i = 0; i < len; i++) { + p += snprintf(p, 3, "%02X", *src); + src++; + } + return (int)(p - str); +} +#endif /* defined(BCMDBG) */ + +/* pretty hex print a contiguous buffer */ +void prhex(const char *msg, unsigned char *buf, uint nbytes) +{ + char line[128], *p; + int len = sizeof(line); + int nchar; + uint i; + + if (msg && (msg[0] != '\0')) + printf("%s:\n", msg); + + p = line; + for (i = 0; i < nbytes; i++) { + if (i % 16 == 0) { + nchar = snprintf(p, len, " %04d: ", i); /* line prefix */ + p += nchar; + len -= nchar; + } + if (len > 0) { + nchar = snprintf(p, len, "%02x ", buf[i]); + p += nchar; + len -= nchar; + } + + if (i % 16 == 15) { + printf("%s\n", line); /* flush line */ + p = line; + len = sizeof(line); + } + } + + /* flush last partial line */ + if (p != line) + printf("%s\n", line); +} + +char *bcm_chipname(uint chipid, char *buf, uint len) +{ + const char *fmt; + + fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x"; + snprintf(buf, len, fmt, chipid); + return buf; +} + +uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen) +{ + uint len; + + len = strlen(name) + 1; + + if ((len + datalen) > buflen) + return 0; + + strncpy(buf, name, buflen); + + /* append data onto the end of the name string */ + memcpy(&buf[len], data, datalen); + len += datalen; + + return len; +} + +/* Quarter dBm units to mW + * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153 + * Table is offset so the last entry is largest mW value that fits in + * a u16. + */ + +#define QDBM_OFFSET 153 /* Offset for first entry */ +#define QDBM_TABLE_LEN 40 /* Table size */ + +/* Smallest mW value that will round up to the first table entry, QDBM_OFFSET. + * Value is ( mW(QDBM_OFFSET - 1) + mW(QDBM_OFFSET) ) / 2 + */ +#define QDBM_TABLE_LOW_BOUND 6493 /* Low bound */ + +/* Largest mW value that will round down to the last table entry, + * QDBM_OFFSET + QDBM_TABLE_LEN-1. + * Value is ( mW(QDBM_OFFSET + QDBM_TABLE_LEN - 1) + + * mW(QDBM_OFFSET + QDBM_TABLE_LEN) ) / 2. + */ +#define QDBM_TABLE_HIGH_BOUND 64938 /* High bound */ + +static const u16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = { +/* qdBm: +0 +1 +2 +3 +4 +5 +6 +7 */ +/* 153: */ 6683, 7079, 7499, 7943, 8414, 8913, 9441, 10000, +/* 161: */ 10593, 11220, 11885, 12589, 13335, 14125, 14962, 15849, +/* 169: */ 16788, 17783, 18836, 19953, 21135, 22387, 23714, 25119, +/* 177: */ 26607, 28184, 29854, 31623, 33497, 35481, 37584, 39811, +/* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096 +}; + +u16 bcm_qdbm_to_mw(u8 qdbm) +{ + uint factor = 1; + int idx = qdbm - QDBM_OFFSET; + + if (idx >= QDBM_TABLE_LEN) { + /* clamp to max u16 mW value */ + return 0xFFFF; + } + + /* scale the qdBm index up to the range of the table 0-40 + * where an offset of 40 qdBm equals a factor of 10 mW. + */ + while (idx < 0) { + idx += 40; + factor *= 10; + } + + /* return the mW value scaled down to the correct factor of 10, + * adding in factor/2 to get proper rounding. + */ + return (nqdBm_to_mW_map[idx] + factor / 2) / factor; +} +u8 bcm_mw_to_qdbm(u16 mw) +{ + u8 qdbm; + int offset; + uint mw_uint = mw; + uint boundary; + + /* handle boundary case */ + if (mw_uint <= 1) + return 0; + + offset = QDBM_OFFSET; + + /* move mw into the range of the table */ + while (mw_uint < QDBM_TABLE_LOW_BOUND) { + mw_uint *= 10; + offset -= 40; + } + + for (qdbm = 0; qdbm < QDBM_TABLE_LEN - 1; qdbm++) { + boundary = nqdBm_to_mW_map[qdbm] + (nqdBm_to_mW_map[qdbm + 1] - + nqdBm_to_mW_map[qdbm]) / 2; + if (mw_uint < boundary) + break; + } + + qdbm += (u8) offset; + + return qdbm; +} +uint bcm_bitcount(u8 *bitmap, uint length) +{ + uint bitcount = 0, i; + u8 tmp; + for (i = 0; i < length; i++) { + tmp = bitmap[i]; + while (tmp) { + bitcount++; + tmp &= (tmp - 1); + } + } + return bitcount; +} +/* Initialization of bcmstrbuf structure */ +void bcm_binit(struct bcmstrbuf *b, char *buf, uint size) +{ + b->origsize = b->size = size; + b->origbuf = b->buf = buf; +} + +/* Buffer sprintf wrapper to guard against buffer overflow */ +int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...) +{ + va_list ap; + int r; + + va_start(ap, fmt); + r = vsnprintf(b->buf, b->size, fmt, ap); + + /* Non Ansi C99 compliant returns -1, + * Ansi compliant return r >= b->size, + * bcmstdlib returns 0, handle all + */ + if ((r == -1) || (r >= (int)b->size) || (r == 0)) { + b->size = 0; + } else { + b->size -= r; + b->buf += r; + } + + va_end(ap); + + return r; +} + diff --git a/drivers/staging/brcm80211/util/bcmwifi.c b/drivers/staging/brcm80211/util/bcmwifi.c new file mode 100644 index 0000000..1bb6c78 --- /dev/null +++ b/drivers/staging/brcm80211/util/bcmwifi.c @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include <linux/ctype.h> +#include <linux/kernel.h> +#include <bcmdefs.h> +#include <bcmutils.h> +#include <bcmwifi.h> + +/* + * Verify the chanspec is using a legal set of parameters, i.e. that the + * chanspec specified a band, bw, ctl_sb and channel and that the + * combination could be legal given any set of circumstances. + * RETURNS: true is the chanspec is malformed, false if it looks good. + */ +bool wf_chspec_malformed(chanspec_t chanspec) +{ + /* must be 2G or 5G band */ + if (!CHSPEC_IS5G(chanspec) && !CHSPEC_IS2G(chanspec)) + return true; + /* must be 20 or 40 bandwidth */ + if (!CHSPEC_IS40(chanspec) && !CHSPEC_IS20(chanspec)) + return true; + + /* 20MHZ b/w must have no ctl sb, 40 must have a ctl sb */ + if (CHSPEC_IS20(chanspec)) { + if (!CHSPEC_SB_NONE(chanspec)) + return true; + } else { + if (!CHSPEC_SB_UPPER(chanspec) && !CHSPEC_SB_LOWER(chanspec)) + return true; + } + + return false; +} + +/* + * This function returns the channel number that control traffic is being sent on, for legacy + * channels this is just the channel number, for 40MHZ channels it is the upper or lowre 20MHZ + * sideband depending on the chanspec selected + */ +u8 wf_chspec_ctlchan(chanspec_t chspec) +{ + u8 ctl_chan; + + /* Is there a sideband ? */ + if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_NONE) { + return CHSPEC_CHANNEL(chspec); + } else { + /* we only support 40MHZ with sidebands */ + ASSERT(CHSPEC_BW(chspec) == WL_CHANSPEC_BW_40); + /* chanspec channel holds the centre frequency, use that and the + * side band information to reconstruct the control channel number + */ + if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_UPPER) { + /* control chan is the upper 20 MHZ SB of the 40MHZ channel */ + ctl_chan = UPPER_20_SB(CHSPEC_CHANNEL(chspec)); + } else { + ASSERT(CHSPEC_CTL_SB(chspec) == + WL_CHANSPEC_CTL_SB_LOWER); + /* control chan is the lower 20 MHZ SB of the 40MHZ channel */ + ctl_chan = LOWER_20_SB(CHSPEC_CHANNEL(chspec)); + } + } + + return ctl_chan; +} + +chanspec_t wf_chspec_ctlchspec(chanspec_t chspec) +{ + chanspec_t ctl_chspec = 0; + u8 channel; + + ASSERT(!wf_chspec_malformed(chspec)); + + /* Is there a sideband ? */ + if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_NONE) { + return chspec; + } else { + if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_UPPER) { + channel = UPPER_20_SB(CHSPEC_CHANNEL(chspec)); + } else { + channel = LOWER_20_SB(CHSPEC_CHANNEL(chspec)); + } + ctl_chspec = + channel | WL_CHANSPEC_BW_20 | WL_CHANSPEC_CTL_SB_NONE; + ctl_chspec |= CHSPEC_BAND(chspec); + } + return ctl_chspec; +} + +/* + * Return the channel number for a given frequency and base frequency. + * The returned channel number is relative to the given base frequency. + * If the given base frequency is zero, a base frequency of 5 GHz is assumed for + * frequencies from 5 - 6 GHz, and 2.407 GHz is assumed for 2.4 - 2.5 GHz. + * + * Frequency is specified in MHz. + * The base frequency is specified as (start_factor * 500 kHz). + * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for + * 2.4 GHz and 5 GHz bands. + * + * The returned channel will be in the range [1, 14] in the 2.4 GHz band + * and [0, 200] otherwise. + * -1 is returned if the start_factor is WF_CHAN_FACTOR_2_4_G and the + * frequency is not a 2.4 GHz channel, or if the frequency is not and even + * multiple of 5 MHz from the base frequency to the base plus 1 GHz. + * + * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2 + */ +int wf_mhz2channel(uint freq, uint start_factor) +{ + int ch = -1; + uint base; + int offset; + + /* take the default channel start frequency */ + if (start_factor == 0) { + if (freq >= 2400 && freq <= 2500) + start_factor = WF_CHAN_FACTOR_2_4_G; + else if (freq >= 5000 && freq <= 6000) + start_factor = WF_CHAN_FACTOR_5_G; + } + + if (freq == 2484 && start_factor == WF_CHAN_FACTOR_2_4_G) + return 14; + + base = start_factor / 2; + + /* check that the frequency is in 1GHz range of the base */ + if ((freq < base) || (freq > base + 1000)) + return -1; + + offset = freq - base; + ch = offset / 5; + + /* check that frequency is a 5MHz multiple from the base */ + if (offset != (ch * 5)) + return -1; + + /* restricted channel range check for 2.4G */ + if (start_factor == WF_CHAN_FACTOR_2_4_G && (ch < 1 || ch > 13)) + return -1; + + return ch; +} + +/* + * Return the center frequency in MHz of the given channel and base frequency. + * The channel number is interpreted relative to the given base frequency. + * + * The valid channel range is [1, 14] in the 2.4 GHz band and [0, 200] otherwise. + * The base frequency is specified as (start_factor * 500 kHz). + * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_4_G, and WF_CHAN_FACTOR_5_G + * are defined for 2.4 GHz, 4 GHz, and 5 GHz bands. + * The channel range of [1, 14] is only checked for a start_factor of + * WF_CHAN_FACTOR_2_4_G (4814 = 2407 * 2). + * Odd start_factors produce channels on .5 MHz boundaries, in which case + * the answer is rounded down to an integral MHz. + * -1 is returned for an out of range channel. + * + * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2 + */ +int wf_channel2mhz(uint ch, uint start_factor) +{ + int freq; + + if ((start_factor == WF_CHAN_FACTOR_2_4_G && (ch < 1 || ch > 14)) || + (ch > 200)) + freq = -1; + else if ((start_factor == WF_CHAN_FACTOR_2_4_G) && (ch == 14)) + freq = 2484; + else + freq = ch * 5 + start_factor / 2; + + return freq; +} diff --git a/drivers/staging/brcm80211/util/hnddma.c b/drivers/staging/brcm80211/util/hnddma.c new file mode 100644 index 0000000..fe503e7 --- /dev/null +++ b/drivers/staging/brcm80211/util/hnddma.c @@ -0,0 +1,2690 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linuxver.h> +#include <bcmdefs.h> +#include <bcmdevs.h> +#include <osl.h> +#include <bcmendian.h> +#include <hndsoc.h> +#include <bcmutils.h> +#include <siutils.h> + +#include <sbhnddma.h> +#include <hnddma.h> + +/* debug/trace */ +#ifdef BCMDBG +#define DMA_ERROR(args) \ + do { \ + if (!(*di->msg_level & 1)) \ + ; \ + else \ + printf args; \ + } while (0) +#define DMA_TRACE(args) \ + do { \ + if (!(*di->msg_level & 2)) \ + ; \ + else \ + printf args; \ + } while (0) +#else +#define DMA_ERROR(args) +#define DMA_TRACE(args) +#endif /* BCMDBG */ + +#define DMA_NONE(args) + +#define d32txregs dregs.d32_u.txregs_32 +#define d32rxregs dregs.d32_u.rxregs_32 +#define txd32 dregs.d32_u.txd_32 +#define rxd32 dregs.d32_u.rxd_32 + +#define d64txregs dregs.d64_u.txregs_64 +#define d64rxregs dregs.d64_u.rxregs_64 +#define txd64 dregs.d64_u.txd_64 +#define rxd64 dregs.d64_u.rxd_64 + +/* default dma message level (if input msg_level pointer is null in dma_attach()) */ +static uint dma_msg_level; + +#define MAXNAMEL 8 /* 8 char names */ + +#define DI_INFO(dmah) ((dma_info_t *)dmah) + +/* dma engine software state */ +typedef struct dma_info { + struct hnddma_pub hnddma; /* exported structure, don't use hnddma_t, + * which could be const + */ + uint *msg_level; /* message level pointer */ + char name[MAXNAMEL]; /* callers name for diag msgs */ + + void *osh; /* os handle */ + si_t *sih; /* sb handle */ + + bool dma64; /* this dma engine is operating in 64-bit mode */ + bool addrext; /* this dma engine supports DmaExtendedAddrChanges */ + + union { + struct { + dma32regs_t *txregs_32; /* 32-bit dma tx engine registers */ + dma32regs_t *rxregs_32; /* 32-bit dma rx engine registers */ + dma32dd_t *txd_32; /* pointer to dma32 tx descriptor ring */ + dma32dd_t *rxd_32; /* pointer to dma32 rx descriptor ring */ + } d32_u; + struct { + dma64regs_t *txregs_64; /* 64-bit dma tx engine registers */ + dma64regs_t *rxregs_64; /* 64-bit dma rx engine registers */ + dma64dd_t *txd_64; /* pointer to dma64 tx descriptor ring */ + dma64dd_t *rxd_64; /* pointer to dma64 rx descriptor ring */ + } d64_u; + } dregs; + + u16 dmadesc_align; /* alignment requirement for dma descriptors */ + + u16 ntxd; /* # tx descriptors tunable */ + u16 txin; /* index of next descriptor to reclaim */ + u16 txout; /* index of next descriptor to post */ + void **txp; /* pointer to parallel array of pointers to packets */ + osldma_t *tx_dmah; /* DMA TX descriptor ring handle */ + hnddma_seg_map_t *txp_dmah; /* DMA MAP meta-data handle */ + dmaaddr_t txdpa; /* Aligned physical address of descriptor ring */ + dmaaddr_t txdpaorig; /* Original physical address of descriptor ring */ + u16 txdalign; /* #bytes added to alloc'd mem to align txd */ + u32 txdalloc; /* #bytes allocated for the ring */ + u32 xmtptrbase; /* When using unaligned descriptors, the ptr register + * is not just an index, it needs all 13 bits to be + * an offset from the addr register. + */ + + u16 nrxd; /* # rx descriptors tunable */ + u16 rxin; /* index of next descriptor to reclaim */ + u16 rxout; /* index of next descriptor to post */ + void **rxp; /* pointer to parallel array of pointers to packets */ + osldma_t *rx_dmah; /* DMA RX descriptor ring handle */ + hnddma_seg_map_t *rxp_dmah; /* DMA MAP meta-data handle */ + dmaaddr_t rxdpa; /* Aligned physical address of descriptor ring */ + dmaaddr_t rxdpaorig; /* Original physical address of descriptor ring */ + u16 rxdalign; /* #bytes added to alloc'd mem to align rxd */ + u32 rxdalloc; /* #bytes allocated for the ring */ + u32 rcvptrbase; /* Base for ptr reg when using unaligned descriptors */ + + /* tunables */ + unsigned int rxbufsize; /* rx buffer size in bytes, + * not including the extra headroom + */ + uint rxextrahdrroom; /* extra rx headroom, reverseved to assist upper stack + * e.g. some rx pkt buffers will be bridged to tx side + * without byte copying. The extra headroom needs to be + * large enough to fit txheader needs. + * Some dongle driver may not need it. + */ + uint nrxpost; /* # rx buffers to keep posted */ + unsigned int rxoffset; /* rxcontrol offset */ + uint ddoffsetlow; /* add to get dma address of descriptor ring, low 32 bits */ + uint ddoffsethigh; /* high 32 bits */ + uint dataoffsetlow; /* add to get dma address of data buffer, low 32 bits */ + uint dataoffsethigh; /* high 32 bits */ + bool aligndesc_4k; /* descriptor base need to be aligned or not */ +} dma_info_t; + +/* + * If BCMDMA32 is defined, hnddma will support both 32-bit and 64-bit DMA engines. + * Otherwise it will support only 64-bit. + * + * DMA32_ENAB indicates whether hnddma is compiled with support for 32-bit DMA engines. + * DMA64_ENAB indicates whether hnddma is compiled with support for 64-bit DMA engines. + * + * DMA64_MODE indicates whether the current DMA engine is running as 64-bit. + */ +#ifdef BCMDMA32 +#define DMA32_ENAB(di) 1 +#define DMA64_ENAB(di) 1 +#define DMA64_MODE(di) ((di)->dma64) +#else /* !BCMDMA32 */ +#define DMA32_ENAB(di) 0 +#define DMA64_ENAB(di) 1 +#define DMA64_MODE(di) 1 +#endif /* !BCMDMA32 */ + +/* DMA Scatter-gather list is supported. Note this is limited to TX direction only */ +#ifdef BCMDMASGLISTOSL +#define DMASGLIST_ENAB true +#else +#define DMASGLIST_ENAB false +#endif /* BCMDMASGLISTOSL */ + +/* descriptor bumping macros */ +#define XXD(x, n) ((x) & ((n) - 1)) /* faster than %, but n must be power of 2 */ +#define TXD(x) XXD((x), di->ntxd) +#define RXD(x) XXD((x), di->nrxd) +#define NEXTTXD(i) TXD((i) + 1) +#define PREVTXD(i) TXD((i) - 1) +#define NEXTRXD(i) RXD((i) + 1) +#define PREVRXD(i) RXD((i) - 1) + +#define NTXDACTIVE(h, t) TXD((t) - (h)) +#define NRXDACTIVE(h, t) RXD((t) - (h)) + +/* macros to convert between byte offsets and indexes */ +#define B2I(bytes, type) ((bytes) / sizeof(type)) +#define I2B(index, type) ((index) * sizeof(type)) + +#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */ +#define PCI32ADDR_HIGH_SHIFT 30 /* address[31:30] */ + +#define PCI64ADDR_HIGH 0x80000000 /* address[63] */ +#define PCI64ADDR_HIGH_SHIFT 31 /* address[63] */ + +/* Common prototypes */ +static bool _dma_isaddrext(dma_info_t *di); +static bool _dma_descriptor_align(dma_info_t *di); +static bool _dma_alloc(dma_info_t *di, uint direction); +static void _dma_detach(dma_info_t *di); +static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa); +static void _dma_rxinit(dma_info_t *di); +static void *_dma_rx(dma_info_t *di); +static bool _dma_rxfill(dma_info_t *di); +static void _dma_rxreclaim(dma_info_t *di); +static void _dma_rxenable(dma_info_t *di); +static void *_dma_getnextrxp(dma_info_t *di, bool forceall); +static void _dma_rx_param_get(dma_info_t *di, u16 *rxoffset, + u16 *rxbufsize); + +static void _dma_txblock(dma_info_t *di); +static void _dma_txunblock(dma_info_t *di); +static uint _dma_txactive(dma_info_t *di); +static uint _dma_rxactive(dma_info_t *di); +static uint _dma_txpending(dma_info_t *di); +static uint _dma_txcommitted(dma_info_t *di); + +static void *_dma_peeknexttxp(dma_info_t *di); +static void *_dma_peeknextrxp(dma_info_t *di); +static unsigned long _dma_getvar(dma_info_t *di, const char *name); +static void _dma_counterreset(dma_info_t *di); +static void _dma_fifoloopbackenable(dma_info_t *di); +static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags); +static u8 dma_align_sizetobits(uint size); +static void *dma_ringalloc(osl_t *osh, u32 boundary, uint size, + u16 *alignbits, uint *alloced, + dmaaddr_t *descpa, osldma_t **dmah); + +/* Prototypes for 32-bit routines */ +static bool dma32_alloc(dma_info_t *di, uint direction); +static bool dma32_txreset(dma_info_t *di); +static bool dma32_rxreset(dma_info_t *di); +static bool dma32_txsuspendedidle(dma_info_t *di); +static int dma32_txfast(dma_info_t *di, void *p0, bool commit); +static void *dma32_getnexttxp(dma_info_t *di, txd_range_t range); +static void *dma32_getnextrxp(dma_info_t *di, bool forceall); +static void dma32_txrotate(dma_info_t *di); +static bool dma32_rxidle(dma_info_t *di); +static void dma32_txinit(dma_info_t *di); +static bool dma32_txenabled(dma_info_t *di); +static void dma32_txsuspend(dma_info_t *di); +static void dma32_txresume(dma_info_t *di); +static bool dma32_txsuspended(dma_info_t *di); +static void dma32_txreclaim(dma_info_t *di, txd_range_t range); +static bool dma32_txstopped(dma_info_t *di); +static bool dma32_rxstopped(dma_info_t *di); +static bool dma32_rxenabled(dma_info_t *di); + +static bool _dma32_addrext(osl_t *osh, dma32regs_t *dma32regs); + +/* Prototypes for 64-bit routines */ +static bool dma64_alloc(dma_info_t *di, uint direction); +static bool dma64_txreset(dma_info_t *di); +static bool dma64_rxreset(dma_info_t *di); +static bool dma64_txsuspendedidle(dma_info_t *di); +static int dma64_txfast(dma_info_t *di, void *p0, bool commit); +static int dma64_txunframed(dma_info_t *di, void *p0, uint len, bool commit); +static void *dma64_getpos(dma_info_t *di, bool direction); +static void *dma64_getnexttxp(dma_info_t *di, txd_range_t range); +static void *dma64_getnextrxp(dma_info_t *di, bool forceall); +static void dma64_txrotate(dma_info_t *di); + +static bool dma64_rxidle(dma_info_t *di); +static void dma64_txinit(dma_info_t *di); +static bool dma64_txenabled(dma_info_t *di); +static void dma64_txsuspend(dma_info_t *di); +static void dma64_txresume(dma_info_t *di); +static bool dma64_txsuspended(dma_info_t *di); +static void dma64_txreclaim(dma_info_t *di, txd_range_t range); +static bool dma64_txstopped(dma_info_t *di); +static bool dma64_rxstopped(dma_info_t *di); +static bool dma64_rxenabled(dma_info_t *di); +static bool _dma64_addrext(osl_t *osh, dma64regs_t *dma64regs); + +static inline u32 parity32(u32 data); + +const di_fcn_t dma64proc = { + (di_detach_t) _dma_detach, + (di_txinit_t) dma64_txinit, + (di_txreset_t) dma64_txreset, + (di_txenabled_t) dma64_txenabled, + (di_txsuspend_t) dma64_txsuspend, + (di_txresume_t) dma64_txresume, + (di_txsuspended_t) dma64_txsuspended, + (di_txsuspendedidle_t) dma64_txsuspendedidle, + (di_txfast_t) dma64_txfast, + (di_txunframed_t) dma64_txunframed, + (di_getpos_t) dma64_getpos, + (di_txstopped_t) dma64_txstopped, + (di_txreclaim_t) dma64_txreclaim, + (di_getnexttxp_t) dma64_getnexttxp, + (di_peeknexttxp_t) _dma_peeknexttxp, + (di_txblock_t) _dma_txblock, + (di_txunblock_t) _dma_txunblock, + (di_txactive_t) _dma_txactive, + (di_txrotate_t) dma64_txrotate, + + (di_rxinit_t) _dma_rxinit, + (di_rxreset_t) dma64_rxreset, + (di_rxidle_t) dma64_rxidle, + (di_rxstopped_t) dma64_rxstopped, + (di_rxenable_t) _dma_rxenable, + (di_rxenabled_t) dma64_rxenabled, + (di_rx_t) _dma_rx, + (di_rxfill_t) _dma_rxfill, + (di_rxreclaim_t) _dma_rxreclaim, + (di_getnextrxp_t) _dma_getnextrxp, + (di_peeknextrxp_t) _dma_peeknextrxp, + (di_rxparam_get_t) _dma_rx_param_get, + + (di_fifoloopbackenable_t) _dma_fifoloopbackenable, + (di_getvar_t) _dma_getvar, + (di_counterreset_t) _dma_counterreset, + (di_ctrlflags_t) _dma_ctrlflags, + NULL, + NULL, + NULL, + (di_rxactive_t) _dma_rxactive, + (di_txpending_t) _dma_txpending, + (di_txcommitted_t) _dma_txcommitted, + 39 +}; + +static const di_fcn_t dma32proc = { + (di_detach_t) _dma_detach, + (di_txinit_t) dma32_txinit, + (di_txreset_t) dma32_txreset, + (di_txenabled_t) dma32_txenabled, + (di_txsuspend_t) dma32_txsuspend, + (di_txresume_t) dma32_txresume, + (di_txsuspended_t) dma32_txsuspended, + (di_txsuspendedidle_t) dma32_txsuspendedidle, + (di_txfast_t) dma32_txfast, + NULL, + NULL, + (di_txstopped_t) dma32_txstopped, + (di_txreclaim_t) dma32_txreclaim, + (di_getnexttxp_t) dma32_getnexttxp, + (di_peeknexttxp_t) _dma_peeknexttxp, + (di_txblock_t) _dma_txblock, + (di_txunblock_t) _dma_txunblock, + (di_txactive_t) _dma_txactive, + (di_txrotate_t) dma32_txrotate, + + (di_rxinit_t) _dma_rxinit, + (di_rxreset_t) dma32_rxreset, + (di_rxidle_t) dma32_rxidle, + (di_rxstopped_t) dma32_rxstopped, + (di_rxenable_t) _dma_rxenable, + (di_rxenabled_t) dma32_rxenabled, + (di_rx_t) _dma_rx, + (di_rxfill_t) _dma_rxfill, + (di_rxreclaim_t) _dma_rxreclaim, + (di_getnextrxp_t) _dma_getnextrxp, + (di_peeknextrxp_t) _dma_peeknextrxp, + (di_rxparam_get_t) _dma_rx_param_get, + + (di_fifoloopbackenable_t) _dma_fifoloopbackenable, + (di_getvar_t) _dma_getvar, + (di_counterreset_t) _dma_counterreset, + (di_ctrlflags_t) _dma_ctrlflags, + NULL, + NULL, + NULL, + (di_rxactive_t) _dma_rxactive, + (di_txpending_t) _dma_txpending, + (di_txcommitted_t) _dma_txcommitted, + 39 +}; + +hnddma_t *dma_attach(osl_t *osh, char *name, si_t *sih, void *dmaregstx, + void *dmaregsrx, uint ntxd, uint nrxd, uint rxbufsize, + int rxextheadroom, uint nrxpost, uint rxoffset, + uint *msg_level) +{ + dma_info_t *di; + uint size; + + /* allocate private info structure */ + di = kzalloc(sizeof(dma_info_t), GFP_ATOMIC); + if (di == NULL) { +#ifdef BCMDBG + printf("dma_attach: out of memory\n"); +#endif + return NULL; + } + + di->msg_level = msg_level ? msg_level : &dma_msg_level; + + /* old chips w/o sb is no longer supported */ + ASSERT(sih != NULL); + + if (DMA64_ENAB(di)) + di->dma64 = + ((si_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64); + else + di->dma64 = 0; + + /* check arguments */ + ASSERT(ISPOWEROF2(ntxd)); + ASSERT(ISPOWEROF2(nrxd)); + + if (nrxd == 0) + ASSERT(dmaregsrx == NULL); + if (ntxd == 0) + ASSERT(dmaregstx == NULL); + + /* init dma reg pointer */ + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + ASSERT(ntxd <= D64MAXDD); + ASSERT(nrxd <= D64MAXDD); + di->d64txregs = (dma64regs_t *) dmaregstx; + di->d64rxregs = (dma64regs_t *) dmaregsrx; + di->hnddma.di_fn = (const di_fcn_t *)&dma64proc; + } else if (DMA32_ENAB(di)) { + ASSERT(ntxd <= D32MAXDD); + ASSERT(nrxd <= D32MAXDD); + di->d32txregs = (dma32regs_t *) dmaregstx; + di->d32rxregs = (dma32regs_t *) dmaregsrx; + di->hnddma.di_fn = (const di_fcn_t *)&dma32proc; + } else { + DMA_ERROR(("dma_attach: driver doesn't support 32-bit DMA\n")); + ASSERT(0); + goto fail; + } + + /* Default flags (which can be changed by the driver calling dma_ctrlflags + * before enable): For backwards compatibility both Rx Overflow Continue + * and Parity are DISABLED. + * supports it. + */ + di->hnddma.di_fn->ctrlflags(&di->hnddma, DMA_CTRL_ROC | DMA_CTRL_PEN, + 0); + + DMA_TRACE(("%s: dma_attach: %s osh %p flags 0x%x ntxd %d nrxd %d rxbufsize %d " "rxextheadroom %d nrxpost %d rxoffset %d dmaregstx %p dmaregsrx %p\n", name, (DMA64_MODE(di) ? "DMA64" : "DMA32"), osh, di->hnddma.dmactrlflags, ntxd, nrxd, rxbufsize, rxextheadroom, nrxpost, rxoffset, dmaregstx, dmaregsrx)); + + /* make a private copy of our callers name */ + strncpy(di->name, name, MAXNAMEL); + di->name[MAXNAMEL - 1] = '\0'; + + di->osh = osh; + di->sih = sih; + + /* save tunables */ + di->ntxd = (u16) ntxd; + di->nrxd = (u16) nrxd; + + /* the actual dma size doesn't include the extra headroom */ + di->rxextrahdrroom = + (rxextheadroom == -1) ? BCMEXTRAHDROOM : rxextheadroom; + if (rxbufsize > BCMEXTRAHDROOM) + di->rxbufsize = (u16) (rxbufsize - di->rxextrahdrroom); + else + di->rxbufsize = (u16) rxbufsize; + + di->nrxpost = (u16) nrxpost; + di->rxoffset = (u8) rxoffset; + + /* + * figure out the DMA physical address offset for dd and data + * PCI/PCIE: they map silicon backplace address to zero based memory, need offset + * Other bus: use zero + * SI_BUS BIGENDIAN kludge: use sdram swapped region for data buffer, not descriptor + */ + di->ddoffsetlow = 0; + di->dataoffsetlow = 0; + /* for pci bus, add offset */ + if (sih->bustype == PCI_BUS) { + if ((sih->buscoretype == PCIE_CORE_ID) && DMA64_MODE(di)) { + /* pcie with DMA64 */ + di->ddoffsetlow = 0; + di->ddoffsethigh = SI_PCIE_DMA_H32; + } else { + /* pci(DMA32/DMA64) or pcie with DMA32 */ + di->ddoffsetlow = SI_PCI_DMA; + di->ddoffsethigh = 0; + } + di->dataoffsetlow = di->ddoffsetlow; + di->dataoffsethigh = di->ddoffsethigh; + } +#if defined(__mips__) && defined(IL_BIGENDIAN) + di->dataoffsetlow = di->dataoffsetlow + SI_SDRAM_SWAPPED; +#endif /* defined(__mips__) && defined(IL_BIGENDIAN) */ + /* WAR64450 : DMACtl.Addr ext fields are not supported in SDIOD core. */ + if ((si_coreid(sih) == SDIOD_CORE_ID) + && ((si_corerev(sih) > 0) && (si_corerev(sih) <= 2))) + di->addrext = 0; + else if ((si_coreid(sih) == I2S_CORE_ID) && + ((si_corerev(sih) == 0) || (si_corerev(sih) == 1))) + di->addrext = 0; + else + di->addrext = _dma_isaddrext(di); + + /* does the descriptors need to be aligned and if yes, on 4K/8K or not */ + di->aligndesc_4k = _dma_descriptor_align(di); + if (di->aligndesc_4k) { + if (DMA64_MODE(di)) { + di->dmadesc_align = D64RINGALIGN_BITS; + if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2)) { + /* for smaller dd table, HW relax the alignment requirement */ + di->dmadesc_align = D64RINGALIGN_BITS - 1; + } + } else + di->dmadesc_align = D32RINGALIGN_BITS; + } else + di->dmadesc_align = 4; /* 16 byte alignment */ + + DMA_NONE(("DMA descriptor align_needed %d, align %d\n", + di->aligndesc_4k, di->dmadesc_align)); + + /* allocate tx packet pointer vector */ + if (ntxd) { + size = ntxd * sizeof(void *); + di->txp = kzalloc(size, GFP_ATOMIC); + if (di->txp == NULL) { + DMA_ERROR(("%s: dma_attach: out of tx memory\n", di->name)); + goto fail; + } + } + + /* allocate rx packet pointer vector */ + if (nrxd) { + size = nrxd * sizeof(void *); + di->rxp = kzalloc(size, GFP_ATOMIC); + if (di->rxp == NULL) { + DMA_ERROR(("%s: dma_attach: out of rx memory\n", di->name)); + goto fail; + } + } + + /* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */ + if (ntxd) { + if (!_dma_alloc(di, DMA_TX)) + goto fail; + } + + /* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */ + if (nrxd) { + if (!_dma_alloc(di, DMA_RX)) + goto fail; + } + + if ((di->ddoffsetlow != 0) && !di->addrext) { + if (PHYSADDRLO(di->txdpa) > SI_PCI_DMA_SZ) { + DMA_ERROR(("%s: dma_attach: txdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->txdpa))); + goto fail; + } + if (PHYSADDRLO(di->rxdpa) > SI_PCI_DMA_SZ) { + DMA_ERROR(("%s: dma_attach: rxdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->rxdpa))); + goto fail; + } + } + + DMA_TRACE(("ddoffsetlow 0x%x ddoffsethigh 0x%x dataoffsetlow 0x%x dataoffsethigh " "0x%x addrext %d\n", di->ddoffsetlow, di->ddoffsethigh, di->dataoffsetlow, di->dataoffsethigh, di->addrext)); + + /* allocate DMA mapping vectors */ + if (DMASGLIST_ENAB) { + if (ntxd) { + size = ntxd * sizeof(hnddma_seg_map_t); + di->txp_dmah = kzalloc(size, GFP_ATOMIC); + if (di->txp_dmah == NULL) + goto fail; + } + + if (nrxd) { + size = nrxd * sizeof(hnddma_seg_map_t); + di->rxp_dmah = kzalloc(size, GFP_ATOMIC); + if (di->rxp_dmah == NULL) + goto fail; + } + } + + return (hnddma_t *) di; + + fail: + _dma_detach(di); + return NULL; +} + +/* init the tx or rx descriptor */ +static inline void +dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, dmaaddr_t pa, uint outidx, + u32 *flags, u32 bufcount) +{ + /* dma32 uses 32-bit control to fit both flags and bufcounter */ + *flags = *flags | (bufcount & CTRL_BC_MASK); + + if ((di->dataoffsetlow == 0) || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) { + W_SM(&ddring[outidx].addr, + BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow)); + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*flags)); + } else { + /* address extension */ + u32 ae; + ASSERT(di->addrext); + ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT; + PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH; + + *flags |= (ae << CTRL_AE_SHIFT); + W_SM(&ddring[outidx].addr, + BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow)); + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*flags)); + } +} + +/* Check for odd number of 1's */ +static inline u32 parity32(u32 data) +{ + data ^= data >> 16; + data ^= data >> 8; + data ^= data >> 4; + data ^= data >> 2; + data ^= data >> 1; + + return data & 1; +} + +#define DMA64_DD_PARITY(dd) parity32((dd)->addrlow ^ (dd)->addrhigh ^ (dd)->ctrl1 ^ (dd)->ctrl2) + +static inline void +dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx, + u32 *flags, u32 bufcount) +{ + u32 ctrl2 = bufcount & D64_CTRL2_BC_MASK; + + /* PCI bus with big(>1G) physical address, use address extension */ +#if defined(__mips__) && defined(IL_BIGENDIAN) + if ((di->dataoffsetlow == SI_SDRAM_SWAPPED) + || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) { +#else + if ((di->dataoffsetlow == 0) || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) { +#endif /* defined(__mips__) && defined(IL_BIGENDIAN) */ + ASSERT((PHYSADDRHI(pa) & PCI64ADDR_HIGH) == 0); + + W_SM(&ddring[outidx].addrlow, + BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow)); + W_SM(&ddring[outidx].addrhigh, + BUS_SWAP32(PHYSADDRHI(pa) + di->dataoffsethigh)); + W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags)); + W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2)); + } else { + /* address extension for 32-bit PCI */ + u32 ae; + ASSERT(di->addrext); + + ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT; + PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH; + ASSERT(PHYSADDRHI(pa) == 0); + + ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE; + W_SM(&ddring[outidx].addrlow, + BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow)); + W_SM(&ddring[outidx].addrhigh, + BUS_SWAP32(0 + di->dataoffsethigh)); + W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags)); + W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2)); + } + if (di->hnddma.dmactrlflags & DMA_CTRL_PEN) { + if (DMA64_DD_PARITY(&ddring[outidx])) { + W_SM(&ddring[outidx].ctrl2, + BUS_SWAP32(ctrl2 | D64_CTRL2_PARITY)); + } + } +} + +static bool _dma32_addrext(osl_t *osh, dma32regs_t *dma32regs) +{ + u32 w; + + OR_REG(osh, &dma32regs->control, XC_AE); + w = R_REG(osh, &dma32regs->control); + AND_REG(osh, &dma32regs->control, ~XC_AE); + return (w & XC_AE) == XC_AE; +} + +static bool _dma_alloc(dma_info_t *di, uint direction) +{ + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + return dma64_alloc(di, direction); + } else if (DMA32_ENAB(di)) { + return dma32_alloc(di, direction); + } else + ASSERT(0); +} + +/* !! may be called with core in reset */ +static void _dma_detach(dma_info_t *di) +{ + + DMA_TRACE(("%s: dma_detach\n", di->name)); + + /* shouldn't be here if descriptors are unreclaimed */ + ASSERT(di->txin == di->txout); + ASSERT(di->rxin == di->rxout); + + /* free dma descriptor rings */ + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + if (di->txd64) + DMA_FREE_CONSISTENT(di->osh, + ((s8 *)di->txd64 - + di->txdalign), di->txdalloc, + (di->txdpaorig), &di->tx_dmah); + if (di->rxd64) + DMA_FREE_CONSISTENT(di->osh, + ((s8 *)di->rxd64 - + di->rxdalign), di->rxdalloc, + (di->rxdpaorig), &di->rx_dmah); + } else if (DMA32_ENAB(di)) { + if (di->txd32) + DMA_FREE_CONSISTENT(di->osh, + ((s8 *)di->txd32 - + di->txdalign), di->txdalloc, + (di->txdpaorig), &di->tx_dmah); + if (di->rxd32) + DMA_FREE_CONSISTENT(di->osh, + ((s8 *)di->rxd32 - + di->rxdalign), di->rxdalloc, + (di->rxdpaorig), &di->rx_dmah); + } else + ASSERT(0); + + /* free packet pointer vectors */ + if (di->txp) + kfree((void *)di->txp); + if (di->rxp) + kfree((void *)di->rxp); + + /* free tx packet DMA handles */ + if (di->txp_dmah) + kfree(di->txp_dmah); + + /* free rx packet DMA handles */ + if (di->rxp_dmah) + kfree(di->rxp_dmah); + + /* free our private info structure */ + kfree((void *)di); + +} + +static bool _dma_descriptor_align(dma_info_t *di) +{ + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + u32 addrl; + + /* Check to see if the descriptors need to be aligned on 4K/8K or not */ + if (di->d64txregs != NULL) { + W_REG(di->osh, &di->d64txregs->addrlow, 0xff0); + addrl = R_REG(di->osh, &di->d64txregs->addrlow); + if (addrl != 0) + return false; + } else if (di->d64rxregs != NULL) { + W_REG(di->osh, &di->d64rxregs->addrlow, 0xff0); + addrl = R_REG(di->osh, &di->d64rxregs->addrlow); + if (addrl != 0) + return false; + } + } + return true; +} + +/* return true if this dma engine supports DmaExtendedAddrChanges, otherwise false */ +static bool _dma_isaddrext(dma_info_t *di) +{ + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + /* DMA64 supports full 32- or 64-bit operation. AE is always valid */ + + /* not all tx or rx channel are available */ + if (di->d64txregs != NULL) { + if (!_dma64_addrext(di->osh, di->d64txregs)) { + DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have AE set\n", di->name)); + ASSERT(0); + } + return true; + } else if (di->d64rxregs != NULL) { + if (!_dma64_addrext(di->osh, di->d64rxregs)) { + DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have AE set\n", di->name)); + ASSERT(0); + } + return true; + } + return false; + } else if (DMA32_ENAB(di)) { + if (di->d32txregs) + return _dma32_addrext(di->osh, di->d32txregs); + else if (di->d32rxregs) + return _dma32_addrext(di->osh, di->d32rxregs); + } else + ASSERT(0); + + return false; +} + +/* initialize descriptor table base address */ +static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa) +{ + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + if (!di->aligndesc_4k) { + if (direction == DMA_TX) + di->xmtptrbase = PHYSADDRLO(pa); + else + di->rcvptrbase = PHYSADDRLO(pa); + } + + if ((di->ddoffsetlow == 0) + || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) { + if (direction == DMA_TX) { + W_REG(di->osh, &di->d64txregs->addrlow, + (PHYSADDRLO(pa) + di->ddoffsetlow)); + W_REG(di->osh, &di->d64txregs->addrhigh, + (PHYSADDRHI(pa) + di->ddoffsethigh)); + } else { + W_REG(di->osh, &di->d64rxregs->addrlow, + (PHYSADDRLO(pa) + di->ddoffsetlow)); + W_REG(di->osh, &di->d64rxregs->addrhigh, + (PHYSADDRHI(pa) + di->ddoffsethigh)); + } + } else { + /* DMA64 32bits address extension */ + u32 ae; + ASSERT(di->addrext); + ASSERT(PHYSADDRHI(pa) == 0); + + /* shift the high bit(s) from pa to ae */ + ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> + PCI32ADDR_HIGH_SHIFT; + PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH; + + if (direction == DMA_TX) { + W_REG(di->osh, &di->d64txregs->addrlow, + (PHYSADDRLO(pa) + di->ddoffsetlow)); + W_REG(di->osh, &di->d64txregs->addrhigh, + di->ddoffsethigh); + SET_REG(di->osh, &di->d64txregs->control, + D64_XC_AE, (ae << D64_XC_AE_SHIFT)); + } else { + W_REG(di->osh, &di->d64rxregs->addrlow, + (PHYSADDRLO(pa) + di->ddoffsetlow)); + W_REG(di->osh, &di->d64rxregs->addrhigh, + di->ddoffsethigh); + SET_REG(di->osh, &di->d64rxregs->control, + D64_RC_AE, (ae << D64_RC_AE_SHIFT)); + } + } + + } else if (DMA32_ENAB(di)) { + ASSERT(PHYSADDRHI(pa) == 0); + if ((di->ddoffsetlow == 0) + || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) { + if (direction == DMA_TX) + W_REG(di->osh, &di->d32txregs->addr, + (PHYSADDRLO(pa) + di->ddoffsetlow)); + else + W_REG(di->osh, &di->d32rxregs->addr, + (PHYSADDRLO(pa) + di->ddoffsetlow)); + } else { + /* dma32 address extension */ + u32 ae; + ASSERT(di->addrext); + + /* shift the high bit(s) from pa to ae */ + ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> + PCI32ADDR_HIGH_SHIFT; + PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH; + + if (direction == DMA_TX) { + W_REG(di->osh, &di->d32txregs->addr, + (PHYSADDRLO(pa) + di->ddoffsetlow)); + SET_REG(di->osh, &di->d32txregs->control, XC_AE, + ae << XC_AE_SHIFT); + } else { + W_REG(di->osh, &di->d32rxregs->addr, + (PHYSADDRLO(pa) + di->ddoffsetlow)); + SET_REG(di->osh, &di->d32rxregs->control, RC_AE, + ae << RC_AE_SHIFT); + } + } + } else + ASSERT(0); +} + +static void _dma_fifoloopbackenable(dma_info_t *di) +{ + DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name)); + + if (DMA64_ENAB(di) && DMA64_MODE(di)) + OR_REG(di->osh, &di->d64txregs->control, D64_XC_LE); + else if (DMA32_ENAB(di)) + OR_REG(di->osh, &di->d32txregs->control, XC_LE); + else + ASSERT(0); +} + +static void _dma_rxinit(dma_info_t *di) +{ + DMA_TRACE(("%s: dma_rxinit\n", di->name)); + + if (di->nrxd == 0) + return; + + di->rxin = di->rxout = 0; + + /* clear rx descriptor ring */ + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + BZERO_SM((void *)di->rxd64, + (di->nrxd * sizeof(dma64dd_t))); + + /* DMA engine with out alignment requirement requires table to be inited + * before enabling the engine + */ + if (!di->aligndesc_4k) + _dma_ddtable_init(di, DMA_RX, di->rxdpa); + + _dma_rxenable(di); + + if (di->aligndesc_4k) + _dma_ddtable_init(di, DMA_RX, di->rxdpa); + } else if (DMA32_ENAB(di)) { + BZERO_SM((void *)di->rxd32, + (di->nrxd * sizeof(dma32dd_t))); + _dma_rxenable(di); + _dma_ddtable_init(di, DMA_RX, di->rxdpa); + } else + ASSERT(0); +} + +static void _dma_rxenable(dma_info_t *di) +{ + uint dmactrlflags = di->hnddma.dmactrlflags; + + DMA_TRACE(("%s: dma_rxenable\n", di->name)); + + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + u32 control = + (R_REG(di->osh, &di->d64rxregs->control) & D64_RC_AE) | + D64_RC_RE; + + if ((dmactrlflags & DMA_CTRL_PEN) == 0) + control |= D64_RC_PD; + + if (dmactrlflags & DMA_CTRL_ROC) + control |= D64_RC_OC; + + W_REG(di->osh, &di->d64rxregs->control, + ((di->rxoffset << D64_RC_RO_SHIFT) | control)); + } else if (DMA32_ENAB(di)) { + u32 control = + (R_REG(di->osh, &di->d32rxregs->control) & RC_AE) | RC_RE; + + if ((dmactrlflags & DMA_CTRL_PEN) == 0) + control |= RC_PD; + + if (dmactrlflags & DMA_CTRL_ROC) + control |= RC_OC; + + W_REG(di->osh, &di->d32rxregs->control, + ((di->rxoffset << RC_RO_SHIFT) | control)); + } else + ASSERT(0); +} + +static void +_dma_rx_param_get(dma_info_t *di, u16 *rxoffset, u16 *rxbufsize) +{ + /* the normal values fit into 16 bits */ + *rxoffset = (u16) di->rxoffset; + *rxbufsize = (u16) di->rxbufsize; +} + +/* !! rx entry routine + * returns a pointer to the next frame received, or NULL if there are no more + * if DMA_CTRL_RXMULTI is defined, DMA scattering(multiple buffers) is supported + * with pkts chain + * otherwise, it's treated as giant pkt and will be tossed. + * The DMA scattering starts with normal DMA header, followed by first buffer data. + * After it reaches the max size of buffer, the data continues in next DMA descriptor + * buffer WITHOUT DMA header + */ +static void *BCMFASTPATH _dma_rx(dma_info_t *di) +{ + void *p, *head, *tail; + uint len; + uint pkt_len; + int resid = 0; + + next_frame: + head = _dma_getnextrxp(di, false); + if (head == NULL) + return NULL; + + len = ltoh16(*(u16 *) (PKTDATA(head))); + DMA_TRACE(("%s: dma_rx len %d\n", di->name, len)); + +#if defined(__mips__) + if (!len) { + while (!(len = *(u16 *) OSL_UNCACHED(PKTDATA(head)))) + udelay(1); + + *(u16 *) PKTDATA(head) = htol16((u16) len); + } +#endif /* defined(__mips__) */ + + /* set actual length */ + pkt_len = min((di->rxoffset + len), di->rxbufsize); + PKTSETLEN(head, pkt_len); + resid = len - (di->rxbufsize - di->rxoffset); + + /* check for single or multi-buffer rx */ + if (resid > 0) { + tail = head; + while ((resid > 0) && (p = _dma_getnextrxp(di, false))) { + PKTSETNEXT(tail, p); + pkt_len = min(resid, (int)di->rxbufsize); + PKTSETLEN(p, pkt_len); + + tail = p; + resid -= di->rxbufsize; + } + +#ifdef BCMDBG + if (resid > 0) { + uint cur; + ASSERT(p == NULL); + cur = (DMA64_ENAB(di) && DMA64_MODE(di)) ? + B2I(((R_REG(di->osh, &di->d64rxregs->status0) & + D64_RS0_CD_MASK) - + di->rcvptrbase) & D64_RS0_CD_MASK, + dma64dd_t) : B2I(R_REG(di->osh, + &di->d32rxregs-> + status) & RS_CD_MASK, + dma32dd_t); + DMA_ERROR(("_dma_rx, rxin %d rxout %d, hw_curr %d\n", + di->rxin, di->rxout, cur)); + } +#endif /* BCMDBG */ + + if ((di->hnddma.dmactrlflags & DMA_CTRL_RXMULTI) == 0) { + DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", + di->name, len)); + PKTFREE(di->osh, head, false); + di->hnddma.rxgiants++; + goto next_frame; + } + } + + return head; +} + +/* post receive buffers + * return false is refill failed completely and ring is empty + * this will stall the rx dma and user might want to call rxfill again asap + * This unlikely happens on memory-rich NIC, but often on memory-constrained dongle + */ +static bool BCMFASTPATH _dma_rxfill(dma_info_t *di) +{ + void *p; + u16 rxin, rxout; + u32 flags = 0; + uint n; + uint i; + dmaaddr_t pa; + uint extra_offset = 0; + bool ring_empty; + + ring_empty = false; + + /* + * Determine how many receive buffers we're lacking + * from the full complement, allocate, initialize, + * and post them, then update the chip rx lastdscr. + */ + + rxin = di->rxin; + rxout = di->rxout; + + n = di->nrxpost - NRXDACTIVE(rxin, rxout); + + DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n)); + + if (di->rxbufsize > BCMEXTRAHDROOM) + extra_offset = di->rxextrahdrroom; + + for (i = 0; i < n; i++) { + /* the di->rxbufsize doesn't include the extra headroom, we need to add it to the + size to be allocated + */ + + p = osl_pktget(di->osh, di->rxbufsize + extra_offset); + + if (p == NULL) { + DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", + di->name)); + if (i == 0) { + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + if (dma64_rxidle(di)) { + DMA_ERROR(("%s: rxfill64: ring is empty !\n", di->name)); + ring_empty = true; + } + } else if (DMA32_ENAB(di)) { + if (dma32_rxidle(di)) { + DMA_ERROR(("%s: rxfill32: ring is empty !\n", di->name)); + ring_empty = true; + } + } else + ASSERT(0); + } + di->hnddma.rxnobuf++; + break; + } + /* reserve an extra headroom, if applicable */ + if (extra_offset) + PKTPULL(p, extra_offset); + + /* Do a cached write instead of uncached write since DMA_MAP + * will flush the cache. + */ + *(u32 *) (PKTDATA(p)) = 0; + + if (DMASGLIST_ENAB) + bzero(&di->rxp_dmah[rxout], sizeof(hnddma_seg_map_t)); + + pa = DMA_MAP(di->osh, PKTDATA(p), + di->rxbufsize, DMA_RX, p, &di->rxp_dmah[rxout]); + + ASSERT(IS_ALIGNED(PHYSADDRLO(pa), 4)); + + /* save the free packet pointer */ + ASSERT(di->rxp[rxout] == NULL); + di->rxp[rxout] = p; + + /* reset flags for each descriptor */ + flags = 0; + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + if (rxout == (di->nrxd - 1)) + flags = D64_CTRL1_EOT; + + dma64_dd_upd(di, di->rxd64, pa, rxout, &flags, + di->rxbufsize); + } else if (DMA32_ENAB(di)) { + if (rxout == (di->nrxd - 1)) + flags = CTRL_EOT; + + ASSERT(PHYSADDRHI(pa) == 0); + dma32_dd_upd(di, di->rxd32, pa, rxout, &flags, + di->rxbufsize); + } else + ASSERT(0); + rxout = NEXTRXD(rxout); + } + + di->rxout = rxout; + + /* update the chip lastdscr pointer */ + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + W_REG(di->osh, &di->d64rxregs->ptr, + di->rcvptrbase + I2B(rxout, dma64dd_t)); + } else if (DMA32_ENAB(di)) { + W_REG(di->osh, &di->d32rxregs->ptr, I2B(rxout, dma32dd_t)); + } else + ASSERT(0); + + return ring_empty; +} + +/* like getnexttxp but no reclaim */ +static void *_dma_peeknexttxp(dma_info_t *di) +{ + uint end, i; + + if (di->ntxd == 0) + return NULL; + + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + end = + B2I(((R_REG(di->osh, &di->d64txregs->status0) & + D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK, + dma64dd_t); + } else if (DMA32_ENAB(di)) { + end = + B2I(R_REG(di->osh, &di->d32txregs->status) & XS_CD_MASK, + dma32dd_t); + } else + ASSERT(0); + + for (i = di->txin; i != end; i = NEXTTXD(i)) + if (di->txp[i]) + return di->txp[i]; + + return NULL; +} + +/* like getnextrxp but not take off the ring */ +static void *_dma_peeknextrxp(dma_info_t *di) +{ + uint end, i; + + if (di->nrxd == 0) + return NULL; + + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + end = + B2I(((R_REG(di->osh, &di->d64rxregs->status0) & + D64_RS0_CD_MASK) - di->rcvptrbase) & D64_RS0_CD_MASK, + dma64dd_t); + } else if (DMA32_ENAB(di)) { + end = + B2I(R_REG(di->osh, &di->d32rxregs->status) & RS_CD_MASK, + dma32dd_t); + } else + ASSERT(0); + + for (i = di->rxin; i != end; i = NEXTRXD(i)) + if (di->rxp[i]) + return di->rxp[i]; + + return NULL; +} + +static void _dma_rxreclaim(dma_info_t *di) +{ + void *p; + + /* "unused local" warning suppression for OSLs that + * define PKTFREE() without using the di->osh arg + */ + di = di; + + DMA_TRACE(("%s: dma_rxreclaim\n", di->name)); + + while ((p = _dma_getnextrxp(di, true))) + PKTFREE(di->osh, p, false); +} + +static void *BCMFASTPATH _dma_getnextrxp(dma_info_t *di, bool forceall) +{ + if (di->nrxd == 0) + return NULL; + + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + return dma64_getnextrxp(di, forceall); + } else if (DMA32_ENAB(di)) { + return dma32_getnextrxp(di, forceall); + } else + ASSERT(0); +} + +static void _dma_txblock(dma_info_t *di) +{ + di->hnddma.txavail = 0; +} + +static void _dma_txunblock(dma_info_t *di) +{ + di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1; +} + +static uint _dma_txactive(dma_info_t *di) +{ + return NTXDACTIVE(di->txin, di->txout); +} + +static uint _dma_txpending(dma_info_t *di) +{ + uint curr; + + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + curr = + B2I(((R_REG(di->osh, &di->d64txregs->status0) & + D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK, + dma64dd_t); + } else if (DMA32_ENAB(di)) { + curr = + B2I(R_REG(di->osh, &di->d32txregs->status) & XS_CD_MASK, + dma32dd_t); + } else + ASSERT(0); + + return NTXDACTIVE(curr, di->txout); +} + +static uint _dma_txcommitted(dma_info_t *di) +{ + uint ptr; + uint txin = di->txin; + + if (txin == di->txout) + return 0; + + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + ptr = B2I(R_REG(di->osh, &di->d64txregs->ptr), dma64dd_t); + } else if (DMA32_ENAB(di)) { + ptr = B2I(R_REG(di->osh, &di->d32txregs->ptr), dma32dd_t); + } else + ASSERT(0); + + return NTXDACTIVE(di->txin, ptr); +} + +static uint _dma_rxactive(dma_info_t *di) +{ + return NRXDACTIVE(di->rxin, di->rxout); +} + +static void _dma_counterreset(dma_info_t *di) +{ + /* reset all software counter */ + di->hnddma.rxgiants = 0; + di->hnddma.rxnobuf = 0; + di->hnddma.txnobuf = 0; +} + +static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags) +{ + uint dmactrlflags = di->hnddma.dmactrlflags; + + if (di == NULL) { + DMA_ERROR(("%s: _dma_ctrlflags: NULL dma handle\n", di->name)); + return 0; + } + + ASSERT((flags & ~mask) == 0); + + dmactrlflags &= ~mask; + dmactrlflags |= flags; + + /* If trying to enable parity, check if parity is actually supported */ + if (dmactrlflags & DMA_CTRL_PEN) { + u32 control; + + if (DMA64_ENAB(di) && DMA64_MODE(di)) { + control = R_REG(di->osh, &di->d64txregs->control); + W_REG(di->osh, &di->d64txregs->control, + control | D64_XC_PD); + if (R_REG(di->osh, &di->d64txregs->control) & D64_XC_PD) { + /* We *can* disable it so it is supported, + * restore control register + */ + W_REG(di->osh, &di->d64txregs->control, + control); + } else { + /* Not supported, don't allow it to be enabled */ + dmactrlflags &= ~DMA_CTRL_PEN; + } + } else if (DMA32_ENAB(di)) { + control = R_REG(di->osh, &di->d32txregs->control); + W_REG(di->osh, &di->d32txregs->control, + control | XC_PD); + if (R_REG(di->osh, &di->d32txregs->control) & XC_PD) { + W_REG(di->osh, &di->d32txregs->control, + control); + } else { + /* Not supported, don't allow it to be enabled */ + dmactrlflags &= ~DMA_CTRL_PEN; + } + } else + ASSERT(0); + } + + di->hnddma.dmactrlflags = dmactrlflags; + + return dmactrlflags; +} + +/* get the address of the var in order to change later */ +static unsigned long _dma_getvar(dma_info_t *di, const char *name) +{ + if (!strcmp(name, "&txavail")) + return (unsigned long)&(di->hnddma.txavail); + else { + ASSERT(0); + } + return 0; +} + +void dma_txpioloopback(osl_t *osh, dma32regs_t *regs) +{ + OR_REG(osh, ®s->control, XC_LE); +} + +static +u8 dma_align_sizetobits(uint size) +{ + u8 bitpos = 0; + ASSERT(size); + ASSERT(!(size & (size - 1))); + while (size >>= 1) { + bitpos++; + } + return bitpos; +} + +/* This function ensures that the DMA descriptor ring will not get allocated + * across Page boundary. If the allocation is done across the page boundary + * at the first time, then it is freed and the allocation is done at + * descriptor ring size aligned location. This will ensure that the ring will + * not cross page boundary + */ +static void *dma_ringalloc(osl_t *osh, u32 boundary, uint size, + u16 *alignbits, uint *alloced, + dmaaddr_t *descpa, osldma_t **dmah) +{ + void *va; + u32 desc_strtaddr; + u32 alignbytes = 1 << *alignbits; + + va = DMA_ALLOC_CONSISTENT(osh, size, *alignbits, alloced, descpa, + dmah); + if (NULL == va) + return NULL; + + desc_strtaddr = (u32) roundup((unsigned long)va, alignbytes); + if (((desc_strtaddr + size - 1) & boundary) != (desc_strtaddr + & boundary)) { + *alignbits = dma_align_sizetobits(size); + DMA_FREE_CONSISTENT(osh, va, size, *descpa, dmah); + va = DMA_ALLOC_CONSISTENT(osh, size, *alignbits, alloced, + descpa, dmah); + } + return va; +} + +/* 32-bit DMA functions */ + +static void dma32_txinit(dma_info_t *di) +{ + u32 control = XC_XE; + + DMA_TRACE(("%s: dma_txinit\n", di->name)); + + if (di->ntxd == 0) + return; + + di->txin = di->txout = 0; + di->hnddma.txavail = di->ntxd - 1; + + /* clear tx descriptor ring */ + BZERO_SM((void *)di->txd32, (di->ntxd * sizeof(dma32dd_t))); + + if ((di->hnddma.dmactrlflags & DMA_CTRL_PEN) == 0) + control |= XC_PD; + W_REG(di->osh, &di->d32txregs->control, control); + _dma_ddtable_init(di, DMA_TX, di->txdpa); +} + +static bool dma32_txenabled(dma_info_t *di) +{ + u32 xc; + + /* If the chip is dead, it is not enabled :-) */ + xc = R_REG(di->osh, &di->d32txregs->control); + return (xc != 0xffffffff) && (xc & XC_XE); +} + +static void dma32_txsuspend(dma_info_t *di) +{ + DMA_TRACE(("%s: dma_txsuspend\n", di->name)); + + if (di->ntxd == 0) + return; + + OR_REG(di->osh, &di->d32txregs->control, XC_SE); +} + +static void dma32_txresume(dma_info_t *di) +{ + DMA_TRACE(("%s: dma_txresume\n", di->name)); + + if (di->ntxd == 0) + return; + + AND_REG(di->osh, &di->d32txregs->control, ~XC_SE); +} + +static bool dma32_txsuspended(dma_info_t *di) +{ + return (di->ntxd == 0) + || ((R_REG(di->osh, &di->d32txregs->control) & XC_SE) == XC_SE); +} + +static void dma32_txreclaim(dma_info_t *di, txd_range_t range) +{ + void *p; + + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, + (range == HNDDMA_RANGE_ALL) ? "all" : + ((range == + HNDDMA_RANGE_TRANSMITTED) ? "transmitted" : + "transfered"))); + + if (di->txin == di->txout) + return; + + while ((p = dma32_getnexttxp(di, range))) + PKTFREE(di->osh, p, true); +} + +static bool dma32_txstopped(dma_info_t *di) +{ + return ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) == + XS_XS_STOPPED); +} + +static bool dma32_rxstopped(dma_info_t *di) +{ + return ((R_REG(di->osh, &di->d32rxregs->status) & RS_RS_MASK) == + RS_RS_STOPPED); +} + +static bool dma32_alloc(dma_info_t *di, uint direction) +{ + uint size; + uint ddlen; + void *va; + uint alloced; + u16 align; + u16 align_bits; + + ddlen = sizeof(dma32dd_t); + + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen); + + alloced = 0; + align_bits = di->dmadesc_align; + align = (1 << align_bits); + + if (direction == DMA_TX) { + va = dma_ringalloc(di->osh, D32RINGALIGN, size, &align_bits, + &alloced, &di->txdpaorig, &di->tx_dmah); + if (va == NULL) { + DMA_ERROR(("%s: dma_alloc: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name)); + return false; + } + + PHYSADDRHISET(di->txdpa, 0); + ASSERT(PHYSADDRHI(di->txdpaorig) == 0); + di->txd32 = (dma32dd_t *) roundup((unsigned long)va, align); + di->txdalign = + (uint) ((s8 *)di->txd32 - (s8 *) va); + + PHYSADDRLOSET(di->txdpa, + PHYSADDRLO(di->txdpaorig) + di->txdalign); + /* Make sure that alignment didn't overflow */ + ASSERT(PHYSADDRLO(di->txdpa) >= PHYSADDRLO(di->txdpaorig)); + + di->txdalloc = alloced; + ASSERT(IS_ALIGNED((unsigned long)di->txd32, align)); + } else { + va = dma_ringalloc(di->osh, D32RINGALIGN, size, &align_bits, + &alloced, &di->rxdpaorig, &di->rx_dmah); + if (va == NULL) { + DMA_ERROR(("%s: dma_alloc: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name)); + return false; + } + + PHYSADDRHISET(di->rxdpa, 0); + ASSERT(PHYSADDRHI(di->rxdpaorig) == 0); + di->rxd32 = (dma32dd_t *) roundup((unsigned long)va, align); + di->rxdalign = + (uint) ((s8 *)di->rxd32 - (s8 *) va); + + PHYSADDRLOSET(di->rxdpa, + PHYSADDRLO(di->rxdpaorig) + di->rxdalign); + /* Make sure that alignment didn't overflow */ + ASSERT(PHYSADDRLO(di->rxdpa) >= PHYSADDRLO(di->rxdpaorig)); + di->rxdalloc = alloced; + ASSERT(IS_ALIGNED((unsigned long)di->rxd32, align)); + } + + return true; +} + +static bool dma32_txreset(dma_info_t *di) +{ + u32 status; + + if (di->ntxd == 0) + return true; + + /* suspend tx DMA first */ + W_REG(di->osh, &di->d32txregs->control, XC_SE); + SPINWAIT(((status = + (R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK)) + != XS_XS_DISABLED) && (status != XS_XS_IDLE) + && (status != XS_XS_STOPPED), (10000)); + + W_REG(di->osh, &di->d32txregs->control, 0); + SPINWAIT(((status = (R_REG(di->osh, + &di->d32txregs->status) & XS_XS_MASK)) != + XS_XS_DISABLED), 10000); + + /* wait for the last transaction to complete */ + udelay(300); + + return status == XS_XS_DISABLED; +} + +static bool dma32_rxidle(dma_info_t *di) +{ + DMA_TRACE(("%s: dma_rxidle\n", di->name)); + + if (di->nrxd == 0) + return true; + + return ((R_REG(di->osh, &di->d32rxregs->status) & RS_CD_MASK) == + R_REG(di->osh, &di->d32rxregs->ptr)); +} + +static bool dma32_rxreset(dma_info_t *di) +{ + u32 status; + + if (di->nrxd == 0) + return true; + + W_REG(di->osh, &di->d32rxregs->control, 0); + SPINWAIT(((status = (R_REG(di->osh, + &di->d32rxregs->status) & RS_RS_MASK)) != + RS_RS_DISABLED), 10000); + + return status == RS_RS_DISABLED; +} + +static bool dma32_rxenabled(dma_info_t *di) +{ + u32 rc; + + rc = R_REG(di->osh, &di->d32rxregs->control); + return (rc != 0xffffffff) && (rc & RC_RE); +} + +static bool dma32_txsuspendedidle(dma_info_t *di) +{ + if (di->ntxd == 0) + return true; + + if (!(R_REG(di->osh, &di->d32txregs->control) & XC_SE)) + return 0; + + if ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) != XS_XS_IDLE) + return 0; + + udelay(2); + return ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) == + XS_XS_IDLE); +} + +/* !! tx entry routine + * supports full 32bit dma engine buffer addressing so + * dma buffers can cross 4 Kbyte page boundaries. + * + * WARNING: call must check the return value for error. + * the error(toss frames) could be fatal and cause many subsequent hard to debug problems + */ +static int dma32_txfast(dma_info_t *di, void *p0, bool commit) +{ + void *p, *next; + unsigned char *data; + uint len; + u16 txout; + u32 flags = 0; + dmaaddr_t pa; + + DMA_TRACE(("%s: dma_txfast\n", di->name)); + + txout = di->txout; + + /* + * Walk the chain of packet buffers + * allocating and initializing transmit descriptor entries. + */ + for (p = p0; p; p = next) { + uint nsegs, j; + hnddma_seg_map_t *map; + + data = PKTDATA(p); + len = PKTLEN(p); +#ifdef BCM_DMAPAD + len += PKTDMAPAD(di->osh, p); +#endif + next = PKTNEXT(p); + + /* return nonzero if out of tx descriptors */ + if (NEXTTXD(txout) == di->txin) + goto outoftxd; + + if (len == 0) + continue; + + if (DMASGLIST_ENAB) + bzero(&di->txp_dmah[txout], sizeof(hnddma_seg_map_t)); + + /* get physical address of buffer start */ + pa = DMA_MAP(di->osh, data, len, DMA_TX, p, + &di->txp_dmah[txout]); + + if (DMASGLIST_ENAB) { + map = &di->txp_dmah[txout]; + + /* See if all the segments can be accounted for */ + if (map->nsegs > + (uint) (di->ntxd - NTXDACTIVE(di->txin, di->txout) - + 1)) + goto outoftxd; + + nsegs = map->nsegs; + } else + nsegs = 1; + + for (j = 1; j <= nsegs; j++) { + flags = 0; + if (p == p0 && j == 1) + flags |= CTRL_SOF; + + /* With a DMA segment list, Descriptor table is filled + * using the segment list instead of looping over + * buffers in multi-chain DMA. Therefore, EOF for SGLIST is when + * end of segment list is reached. + */ + if ((!DMASGLIST_ENAB && next == NULL) || + (DMASGLIST_ENAB && j == nsegs)) + flags |= (CTRL_IOC | CTRL_EOF); + if (txout == (di->ntxd - 1)) + flags |= CTRL_EOT; + + if (DMASGLIST_ENAB) { + len = map->segs[j - 1].length; + pa = map->segs[j - 1].addr; + } + ASSERT(PHYSADDRHI(pa) == 0); + + dma32_dd_upd(di, di->txd32, pa, txout, &flags, len); + ASSERT(di->txp[txout] == NULL); + + txout = NEXTTXD(txout); + } + + /* See above. No need to loop over individual buffers */ + if (DMASGLIST_ENAB) + break; + } + + /* if last txd eof not set, fix it */ + if (!(flags & CTRL_EOF)) + W_SM(&di->txd32[PREVTXD(txout)].ctrl, + BUS_SWAP32(flags | CTRL_IOC | CTRL_EOF)); + + /* save the packet */ + di->txp[PREVTXD(txout)] = p0; + + /* bump the tx descriptor index */ + di->txout = txout; + + /* kick the chip */ + if (commit) + W_REG(di->osh, &di->d32txregs->ptr, I2B(txout, dma32dd_t)); + + /* tx flow control */ + di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1; + + return 0; + + outoftxd: + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name)); + PKTFREE(di->osh, p0, true); + di->hnddma.txavail = 0; + di->hnddma.txnobuf++; + return -1; +} + +/* + * Reclaim next completed txd (txds if using chained buffers) in the range + * specified and return associated packet. + * If range is HNDDMA_RANGE_TRANSMITTED, reclaim descriptors that have be + * transmitted as noted by the hardware "CurrDescr" pointer. + * If range is HNDDMA_RANGE_TRANSFERED, reclaim descriptors that have be + * transfered by the DMA as noted by the hardware "ActiveDescr" pointer. + * If range is HNDDMA_RANGE_ALL, reclaim all txd(s) posted to the ring and + * return associated packet regardless of the value of hardware pointers. + */ +static void *dma32_getnexttxp(dma_info_t *di, txd_range_t range) +{ + u16 start, end, i; + u16 active_desc; + void *txp; + + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, + (range == HNDDMA_RANGE_ALL) ? "all" : + ((range == + HNDDMA_RANGE_TRANSMITTED) ? "transmitted" : + "transfered"))); + + if (di->ntxd == 0) + return NULL; + + txp = NULL; + + start = di->txin; + if (range == HNDDMA_RANGE_ALL) + end = di->txout; + else { + dma32regs_t *dregs = di->d32txregs; + + end = + (u16) B2I(R_REG(di->osh, &dregs->status) & XS_CD_MASK, + dma32dd_t); + + if (range == HNDDMA_RANGE_TRANSFERED) { + active_desc = + (u16) ((R_REG(di->osh, &dregs->status) & + XS_AD_MASK) >> XS_AD_SHIFT); + active_desc = (u16) B2I(active_desc, dma32dd_t); + if (end != active_desc) + end = PREVTXD(active_desc); + } + } + + if ((start == 0) && (end > di->txout)) + goto bogus; + + for (i = start; i != end && !txp; i = NEXTTXD(i)) { + dmaaddr_t pa; + hnddma_seg_map_t *map = NULL; + uint size, j, nsegs; + + PHYSADDRLOSET(pa, + (BUS_SWAP32(R_SM(&di->txd32[i].addr)) - + di->dataoffsetlow)); + PHYSADDRHISET(pa, 0); + + if (DMASGLIST_ENAB) { + map = &di->txp_dmah[i]; + size = map->origsize; + nsegs = map->nsegs; + } else { + size = + (BUS_SWAP32(R_SM(&di->txd32[i].ctrl)) & + CTRL_BC_MASK); + nsegs = 1; + } + + for (j = nsegs; j > 0; j--) { + W_SM(&di->txd32[i].addr, 0xdeadbeef); + + txp = di->txp[i]; + di->txp[i] = NULL; + if (j > 1) + i = NEXTTXD(i); + } + + DMA_UNMAP(di->osh, pa, size, DMA_TX, txp, map); + } + + di->txin = i; + + /* tx flow control */ + di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1; + + return txp; + + bogus: + DMA_NONE(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n", start, end, di->txout, forceall)); + return NULL; +} + +static void *dma32_getnextrxp(dma_info_t *di, bool forceall) +{ + uint i, curr; + void *rxp; + dmaaddr_t pa; + /* if forcing, dma engine must be disabled */ + ASSERT(!forceall || !dma32_rxenabled(di)); + + i = di->rxin; + + /* return if no packets posted */ + if (i == di->rxout) + return NULL; + + curr = + B2I(R_REG(di->osh, &di->d32rxregs->status) & RS_CD_MASK, dma32dd_t); + + /* ignore curr if forceall */ + if (!forceall && (i == curr)) + return NULL; + + /* get the packet pointer that corresponds to the rx descriptor */ + rxp = di->rxp[i]; + ASSERT(rxp); + di->rxp[i] = NULL; + + PHYSADDRLOSET(pa, + (BUS_SWAP32(R_SM(&di->rxd32[i].addr)) - + di->dataoffsetlow)); + PHYSADDRHISET(pa, 0); + + /* clear this packet from the descriptor ring */ + DMA_UNMAP(di->osh, pa, di->rxbufsize, DMA_RX, rxp, &di->rxp_dmah[i]); + + W_SM(&di->rxd32[i].addr, 0xdeadbeef); + + di->rxin = NEXTRXD(i); + + return rxp; +} + +/* + * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin). + */ +static void dma32_txrotate(dma_info_t *di) +{ + u16 ad; + uint nactive; + uint rot; + u16 old, new; + u32 w; + u16 first, last; + + ASSERT(dma32_txsuspendedidle(di)); + + nactive = _dma_txactive(di); + ad = (u16) (B2I + (((R_REG(di->osh, &di->d32txregs->status) & XS_AD_MASK) + >> XS_AD_SHIFT), dma32dd_t)); + rot = TXD(ad - di->txin); + + ASSERT(rot < di->ntxd); + + /* full-ring case is a lot harder - don't worry about this */ + if (rot >= (di->ntxd - nactive)) { + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name)); + return; + } + + first = di->txin; + last = PREVTXD(di->txout); + + /* move entries starting at last and moving backwards to first */ + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) { + new = TXD(old + rot); + + /* + * Move the tx dma descriptor. + * EOT is set only in the last entry in the ring. + */ + w = BUS_SWAP32(R_SM(&di->txd32[old].ctrl)) & ~CTRL_EOT; + if (new == (di->ntxd - 1)) + w |= CTRL_EOT; + W_SM(&di->txd32[new].ctrl, BUS_SWAP32(w)); + W_SM(&di->txd32[new].addr, R_SM(&di->txd32[old].addr)); + + /* zap the old tx dma descriptor address field */ + W_SM(&di->txd32[old].addr, BUS_SWAP32(0xdeadbeef)); + + /* move the corresponding txp[] entry */ + ASSERT(di->txp[new] == NULL); + di->txp[new] = di->txp[old]; + + /* Move the segment map as well */ + if (DMASGLIST_ENAB) { + bcopy(&di->txp_dmah[old], &di->txp_dmah[new], + sizeof(hnddma_seg_map_t)); + bzero(&di->txp_dmah[old], sizeof(hnddma_seg_map_t)); + } + + di->txp[old] = NULL; + } + + /* update txin and txout */ + di->txin = ad; + di->txout = TXD(di->txout + rot); + di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1; + + /* kick the chip */ + W_REG(di->osh, &di->d32txregs->ptr, I2B(di->txout, dma32dd_t)); +} + +/* 64-bit DMA functions */ + +static void dma64_txinit(dma_info_t *di) +{ + u32 control = D64_XC_XE; + + DMA_TRACE(("%s: dma_txinit\n", di->name)); + + if (di->ntxd == 0) + return; + + di->txin = di->txout = 0; + di->hnddma.txavail = di->ntxd - 1; + + /* clear tx descriptor ring */ + BZERO_SM((void *)di->txd64, (di->ntxd * sizeof(dma64dd_t))); + + /* DMA engine with out alignment requirement requires table to be inited + * before enabling the engine + */ + if (!di->aligndesc_4k) + _dma_ddtable_init(di, DMA_TX, di->txdpa); + + if ((di->hnddma.dmactrlflags & DMA_CTRL_PEN) == 0) + control |= D64_XC_PD; + OR_REG(di->osh, &di->d64txregs->control, control); + + /* DMA engine with alignment requirement requires table to be inited + * before enabling the engine + */ + if (di->aligndesc_4k) + _dma_ddtable_init(di, DMA_TX, di->txdpa); +} + +static bool dma64_txenabled(dma_info_t *di) +{ + u32 xc; + + /* If the chip is dead, it is not enabled :-) */ + xc = R_REG(di->osh, &di->d64txregs->control); + return (xc != 0xffffffff) && (xc & D64_XC_XE); +} + +static void dma64_txsuspend(dma_info_t *di) +{ + DMA_TRACE(("%s: dma_txsuspend\n", di->name)); + + if (di->ntxd == 0) + return; + + OR_REG(di->osh, &di->d64txregs->control, D64_XC_SE); +} + +static void dma64_txresume(dma_info_t *di) +{ + DMA_TRACE(("%s: dma_txresume\n", di->name)); + + if (di->ntxd == 0) + return; + + AND_REG(di->osh, &di->d64txregs->control, ~D64_XC_SE); +} + +static bool dma64_txsuspended(dma_info_t *di) +{ + return (di->ntxd == 0) || + ((R_REG(di->osh, &di->d64txregs->control) & D64_XC_SE) == + D64_XC_SE); +} + +static void BCMFASTPATH dma64_txreclaim(dma_info_t *di, txd_range_t range) +{ + void *p; + + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, + (range == HNDDMA_RANGE_ALL) ? "all" : + ((range == + HNDDMA_RANGE_TRANSMITTED) ? "transmitted" : + "transfered"))); + + if (di->txin == di->txout) + return; + + while ((p = dma64_getnexttxp(di, range))) { + /* For unframed data, we don't have any packets to free */ + if (!(di->hnddma.dmactrlflags & DMA_CTRL_UNFRAMED)) + PKTFREE(di->osh, p, true); + } +} + +static bool dma64_txstopped(dma_info_t *di) +{ + return ((R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK) == + D64_XS0_XS_STOPPED); +} + +static bool dma64_rxstopped(dma_info_t *di) +{ + return ((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_RS_MASK) == + D64_RS0_RS_STOPPED); +} + +static bool dma64_alloc(dma_info_t *di, uint direction) +{ + u16 size; + uint ddlen; + void *va; + uint alloced = 0; + u16 align; + u16 align_bits; + + ddlen = sizeof(dma64dd_t); + + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen); + align_bits = di->dmadesc_align; + align = (1 << align_bits); + + if (direction == DMA_TX) { + va = dma_ringalloc(di->osh, D64RINGALIGN, size, &align_bits, + &alloced, &di->txdpaorig, &di->tx_dmah); + if (va == NULL) { + DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name)); + return false; + } + align = (1 << align_bits); + di->txd64 = (dma64dd_t *) roundup((unsigned long)va, align); + di->txdalign = (uint) ((s8 *)di->txd64 - (s8 *) va); + PHYSADDRLOSET(di->txdpa, + PHYSADDRLO(di->txdpaorig) + di->txdalign); + /* Make sure that alignment didn't overflow */ + ASSERT(PHYSADDRLO(di->txdpa) >= PHYSADDRLO(di->txdpaorig)); + + PHYSADDRHISET(di->txdpa, PHYSADDRHI(di->txdpaorig)); + di->txdalloc = alloced; + ASSERT(IS_ALIGNED((unsigned long)di->txd64, align)); + } else { + va = dma_ringalloc(di->osh, D64RINGALIGN, size, &align_bits, + &alloced, &di->rxdpaorig, &di->rx_dmah); + if (va == NULL) { + DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name)); + return false; + } + align = (1 << align_bits); + di->rxd64 = (dma64dd_t *) roundup((unsigned long)va, align); + di->rxdalign = (uint) ((s8 *)di->rxd64 - (s8 *) va); + PHYSADDRLOSET(di->rxdpa, + PHYSADDRLO(di->rxdpaorig) + di->rxdalign); + /* Make sure that alignment didn't overflow */ + ASSERT(PHYSADDRLO(di->rxdpa) >= PHYSADDRLO(di->rxdpaorig)); + + PHYSADDRHISET(di->rxdpa, PHYSADDRHI(di->rxdpaorig)); + di->rxdalloc = alloced; + ASSERT(IS_ALIGNED((unsigned long)di->rxd64, align)); + } + + return true; +} + +static bool dma64_txreset(dma_info_t *di) +{ + u32 status; + + if (di->ntxd == 0) + return true; + + /* suspend tx DMA first */ + W_REG(di->osh, &di->d64txregs->control, D64_XC_SE); + SPINWAIT(((status = + (R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK)) + != D64_XS0_XS_DISABLED) && (status != D64_XS0_XS_IDLE) + && (status != D64_XS0_XS_STOPPED), 10000); + + W_REG(di->osh, &di->d64txregs->control, 0); + SPINWAIT(((status = + (R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK)) + != D64_XS0_XS_DISABLED), 10000); + + /* wait for the last transaction to complete */ + udelay(300); + + return status == D64_XS0_XS_DISABLED; +} + +static bool dma64_rxidle(dma_info_t *di) +{ + DMA_TRACE(("%s: dma_rxidle\n", di->name)); + + if (di->nrxd == 0) + return true; + + return ((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK) == + (R_REG(di->osh, &di->d64rxregs->ptr) & D64_RS0_CD_MASK)); +} + +static bool dma64_rxreset(dma_info_t *di) +{ + u32 status; + + if (di->nrxd == 0) + return true; + + W_REG(di->osh, &di->d64rxregs->control, 0); + SPINWAIT(((status = + (R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_RS_MASK)) + != D64_RS0_RS_DISABLED), 10000); + + return status == D64_RS0_RS_DISABLED; +} + +static bool dma64_rxenabled(dma_info_t *di) +{ + u32 rc; + + rc = R_REG(di->osh, &di->d64rxregs->control); + return (rc != 0xffffffff) && (rc & D64_RC_RE); +} + +static bool dma64_txsuspendedidle(dma_info_t *di) +{ + + if (di->ntxd == 0) + return true; + + if (!(R_REG(di->osh, &di->d64txregs->control) & D64_XC_SE)) + return 0; + + if ((R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK) == + D64_XS0_XS_IDLE) + return 1; + + return 0; +} + +/* Useful when sending unframed data. This allows us to get a progress report from the DMA. + * We return a pointer to the beginning of the DATA buffer of the current descriptor. + * If DMA is idle, we return NULL. + */ +static void *dma64_getpos(dma_info_t *di, bool direction) +{ + void *va; + bool idle; + u32 cd_offset; + + if (direction == DMA_TX) { + cd_offset = + R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_CD_MASK; + idle = !NTXDACTIVE(di->txin, di->txout); + va = di->txp[B2I(cd_offset, dma64dd_t)]; + } else { + cd_offset = + R_REG(di->osh, &di->d64rxregs->status0) & D64_XS0_CD_MASK; + idle = !NRXDACTIVE(di->rxin, di->rxout); + va = di->rxp[B2I(cd_offset, dma64dd_t)]; + } + + /* If DMA is IDLE, return NULL */ + if (idle) { + DMA_TRACE(("%s: DMA idle, return NULL\n", __func__)); + va = NULL; + } + + return va; +} + +/* TX of unframed data + * + * Adds a DMA ring descriptor for the data pointed to by "buf". + * This is for DMA of a buffer of data and is unlike other hnddma TX functions + * that take a pointer to a "packet" + * Each call to this is results in a single descriptor being added for "len" bytes of + * data starting at "buf", it doesn't handle chained buffers. + */ +static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit) +{ + u16 txout; + u32 flags = 0; + dmaaddr_t pa; /* phys addr */ + + txout = di->txout; + + /* return nonzero if out of tx descriptors */ + if (NEXTTXD(txout) == di->txin) + goto outoftxd; + + if (len == 0) + return 0; + + pa = DMA_MAP(di->osh, buf, len, DMA_TX, NULL, &di->txp_dmah[txout]); + + flags = (D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF); + + if (txout == (di->ntxd - 1)) + flags |= D64_CTRL1_EOT; + + dma64_dd_upd(di, di->txd64, pa, txout, &flags, len); + ASSERT(di->txp[txout] == NULL); + + /* save the buffer pointer - used by dma_getpos */ + di->txp[txout] = buf; + + txout = NEXTTXD(txout); + /* bump the tx descriptor index */ + di->txout = txout; + + /* kick the chip */ + if (commit) { + W_REG(di->osh, &di->d64txregs->ptr, + di->xmtptrbase + I2B(txout, dma64dd_t)); + } + + /* tx flow control */ + di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1; + + return 0; + + outoftxd: + DMA_ERROR(("%s: %s: out of txds !!!\n", di->name, __func__)); + di->hnddma.txavail = 0; + di->hnddma.txnobuf++; + return -1; +} + +/* !! tx entry routine + * WARNING: call must check the return value for error. + * the error(toss frames) could be fatal and cause many subsequent hard to debug problems + */ +static int BCMFASTPATH dma64_txfast(dma_info_t *di, void *p0, bool commit) +{ + void *p, *next; + unsigned char *data; + uint len; + u16 txout; + u32 flags = 0; + dmaaddr_t pa; + + DMA_TRACE(("%s: dma_txfast\n", di->name)); + + txout = di->txout; + + /* + * Walk the chain of packet buffers + * allocating and initializing transmit descriptor entries. + */ + for (p = p0; p; p = next) { + uint nsegs, j; + hnddma_seg_map_t *map; + + data = PKTDATA(p); + len = PKTLEN(p); +#ifdef BCM_DMAPAD + len += PKTDMAPAD(di->osh, p); +#endif /* BCM_DMAPAD */ + next = PKTNEXT(p); + + /* return nonzero if out of tx descriptors */ + if (NEXTTXD(txout) == di->txin) + goto outoftxd; + + if (len == 0) + continue; + + /* get physical address of buffer start */ + if (DMASGLIST_ENAB) + bzero(&di->txp_dmah[txout], sizeof(hnddma_seg_map_t)); + + pa = DMA_MAP(di->osh, data, len, DMA_TX, p, + &di->txp_dmah[txout]); + + if (DMASGLIST_ENAB) { + map = &di->txp_dmah[txout]; + + /* See if all the segments can be accounted for */ + if (map->nsegs > + (uint) (di->ntxd - NTXDACTIVE(di->txin, di->txout) - + 1)) + goto outoftxd; + + nsegs = map->nsegs; + } else + nsegs = 1; + + for (j = 1; j <= nsegs; j++) { + flags = 0; + if (p == p0 && j == 1) + flags |= D64_CTRL1_SOF; + + /* With a DMA segment list, Descriptor table is filled + * using the segment list instead of looping over + * buffers in multi-chain DMA. Therefore, EOF for SGLIST is when + * end of segment list is reached. + */ + if ((!DMASGLIST_ENAB && next == NULL) || + (DMASGLIST_ENAB && j == nsegs)) + flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF); + if (txout == (di->ntxd - 1)) + flags |= D64_CTRL1_EOT; + + if (DMASGLIST_ENAB) { + len = map->segs[j - 1].length; + pa = map->segs[j - 1].addr; + } + dma64_dd_upd(di, di->txd64, pa, txout, &flags, len); + ASSERT(di->txp[txout] == NULL); + + txout = NEXTTXD(txout); + } + + /* See above. No need to loop over individual buffers */ + if (DMASGLIST_ENAB) + break; + } + + /* if last txd eof not set, fix it */ + if (!(flags & D64_CTRL1_EOF)) + W_SM(&di->txd64[PREVTXD(txout)].ctrl1, + BUS_SWAP32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF)); + + /* save the packet */ + di->txp[PREVTXD(txout)] = p0; + + /* bump the tx descriptor index */ + di->txout = txout; + + /* kick the chip */ + if (commit) + W_REG(di->osh, &di->d64txregs->ptr, + di->xmtptrbase + I2B(txout, dma64dd_t)); + + /* tx flow control */ + di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1; + + return 0; + + outoftxd: + DMA_ERROR(("%s: dma_txfast: out of txds !!!\n", di->name)); + PKTFREE(di->osh, p0, true); + di->hnddma.txavail = 0; + di->hnddma.txnobuf++; + return -1; +} + +/* + * Reclaim next completed txd (txds if using chained buffers) in the range + * specified and return associated packet. + * If range is HNDDMA_RANGE_TRANSMITTED, reclaim descriptors that have be + * transmitted as noted by the hardware "CurrDescr" pointer. + * If range is HNDDMA_RANGE_TRANSFERED, reclaim descriptors that have be + * transfered by the DMA as noted by the hardware "ActiveDescr" pointer. + * If range is HNDDMA_RANGE_ALL, reclaim all txd(s) posted to the ring and + * return associated packet regardless of the value of hardware pointers. + */ +static void *BCMFASTPATH dma64_getnexttxp(dma_info_t *di, txd_range_t range) +{ + u16 start, end, i; + u16 active_desc; + void *txp; + + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, + (range == HNDDMA_RANGE_ALL) ? "all" : + ((range == + HNDDMA_RANGE_TRANSMITTED) ? "transmitted" : + "transfered"))); + + if (di->ntxd == 0) + return NULL; + + txp = NULL; + + start = di->txin; + if (range == HNDDMA_RANGE_ALL) + end = di->txout; + else { + dma64regs_t *dregs = di->d64txregs; + + end = + (u16) (B2I + (((R_REG(di->osh, &dregs->status0) & + D64_XS0_CD_MASK) - + di->xmtptrbase) & D64_XS0_CD_MASK, dma64dd_t)); + + if (range == HNDDMA_RANGE_TRANSFERED) { + active_desc = + (u16) (R_REG(di->osh, &dregs->status1) & + D64_XS1_AD_MASK); + active_desc = + (active_desc - di->xmtptrbase) & D64_XS0_CD_MASK; + active_desc = B2I(active_desc, dma64dd_t); + if (end != active_desc) + end = PREVTXD(active_desc); + } + } + + if ((start == 0) && (end > di->txout)) + goto bogus; + + for (i = start; i != end && !txp; i = NEXTTXD(i)) { + dmaaddr_t pa; + hnddma_seg_map_t *map = NULL; + uint size, j, nsegs; + + PHYSADDRLOSET(pa, + (BUS_SWAP32(R_SM(&di->txd64[i].addrlow)) - + di->dataoffsetlow)); + PHYSADDRHISET(pa, + (BUS_SWAP32(R_SM(&di->txd64[i].addrhigh)) - + di->dataoffsethigh)); + + if (DMASGLIST_ENAB) { + map = &di->txp_dmah[i]; + size = map->origsize; + nsegs = map->nsegs; + } else { + size = + (BUS_SWAP32(R_SM(&di->txd64[i].ctrl2)) & + D64_CTRL2_BC_MASK); + nsegs = 1; + } + + for (j = nsegs; j > 0; j--) { + W_SM(&di->txd64[i].addrlow, 0xdeadbeef); + W_SM(&di->txd64[i].addrhigh, 0xdeadbeef); + + txp = di->txp[i]; + di->txp[i] = NULL; + if (j > 1) + i = NEXTTXD(i); + } + + DMA_UNMAP(di->osh, pa, size, DMA_TX, txp, map); + } + + di->txin = i; + + /* tx flow control */ + di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1; + + return txp; + + bogus: + DMA_NONE(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n", start, end, di->txout, forceall)); + return NULL; +} + +static void *BCMFASTPATH dma64_getnextrxp(dma_info_t *di, bool forceall) +{ + uint i, curr; + void *rxp; + dmaaddr_t pa; + + /* if forcing, dma engine must be disabled */ + ASSERT(!forceall || !dma64_rxenabled(di)); + + i = di->rxin; + + /* return if no packets posted */ + if (i == di->rxout) + return NULL; + + curr = + B2I(((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK) - + di->rcvptrbase) & D64_RS0_CD_MASK, dma64dd_t); + + /* ignore curr if forceall */ + if (!forceall && (i == curr)) + return NULL; + + /* get the packet pointer that corresponds to the rx descriptor */ + rxp = di->rxp[i]; + ASSERT(rxp); + di->rxp[i] = NULL; + + PHYSADDRLOSET(pa, + (BUS_SWAP32(R_SM(&di->rxd64[i].addrlow)) - + di->dataoffsetlow)); + PHYSADDRHISET(pa, + (BUS_SWAP32(R_SM(&di->rxd64[i].addrhigh)) - + di->dataoffsethigh)); + + /* clear this packet from the descriptor ring */ + DMA_UNMAP(di->osh, pa, di->rxbufsize, DMA_RX, rxp, &di->rxp_dmah[i]); + + W_SM(&di->rxd64[i].addrlow, 0xdeadbeef); + W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef); + + di->rxin = NEXTRXD(i); + + return rxp; +} + +static bool _dma64_addrext(osl_t *osh, dma64regs_t * dma64regs) +{ + u32 w; + OR_REG(osh, &dma64regs->control, D64_XC_AE); + w = R_REG(osh, &dma64regs->control); + AND_REG(osh, &dma64regs->control, ~D64_XC_AE); + return (w & D64_XC_AE) == D64_XC_AE; +} + +/* + * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin). + */ +static void dma64_txrotate(dma_info_t *di) +{ + u16 ad; + uint nactive; + uint rot; + u16 old, new; + u32 w; + u16 first, last; + + ASSERT(dma64_txsuspendedidle(di)); + + nactive = _dma_txactive(di); + ad = (u16) (B2I + ((((R_REG(di->osh, &di->d64txregs->status1) & + D64_XS1_AD_MASK) + - di->xmtptrbase) & D64_XS1_AD_MASK), dma64dd_t)); + rot = TXD(ad - di->txin); + + ASSERT(rot < di->ntxd); + + /* full-ring case is a lot harder - don't worry about this */ + if (rot >= (di->ntxd - nactive)) { + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name)); + return; + } + + first = di->txin; + last = PREVTXD(di->txout); + + /* move entries starting at last and moving backwards to first */ + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) { + new = TXD(old + rot); + + /* + * Move the tx dma descriptor. + * EOT is set only in the last entry in the ring. + */ + w = BUS_SWAP32(R_SM(&di->txd64[old].ctrl1)) & ~D64_CTRL1_EOT; + if (new == (di->ntxd - 1)) + w |= D64_CTRL1_EOT; + W_SM(&di->txd64[new].ctrl1, BUS_SWAP32(w)); + + w = BUS_SWAP32(R_SM(&di->txd64[old].ctrl2)); + W_SM(&di->txd64[new].ctrl2, BUS_SWAP32(w)); + + W_SM(&di->txd64[new].addrlow, R_SM(&di->txd64[old].addrlow)); + W_SM(&di->txd64[new].addrhigh, R_SM(&di->txd64[old].addrhigh)); + + /* zap the old tx dma descriptor address field */ + W_SM(&di->txd64[old].addrlow, BUS_SWAP32(0xdeadbeef)); + W_SM(&di->txd64[old].addrhigh, BUS_SWAP32(0xdeadbeef)); + + /* move the corresponding txp[] entry */ + ASSERT(di->txp[new] == NULL); + di->txp[new] = di->txp[old]; + + /* Move the map */ + if (DMASGLIST_ENAB) { + bcopy(&di->txp_dmah[old], &di->txp_dmah[new], + sizeof(hnddma_seg_map_t)); + bzero(&di->txp_dmah[old], sizeof(hnddma_seg_map_t)); + } + + di->txp[old] = NULL; + } + + /* update txin and txout */ + di->txin = ad; + di->txout = TXD(di->txout + rot); + di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1; + + /* kick the chip */ + W_REG(di->osh, &di->d64txregs->ptr, + di->xmtptrbase + I2B(di->txout, dma64dd_t)); +} + +uint dma_addrwidth(si_t *sih, void *dmaregs) +{ + dma32regs_t *dma32regs; + osl_t *osh; + + osh = si_osh(sih); + + /* Perform 64-bit checks only if we want to advertise 64-bit (> 32bit) capability) */ + /* DMA engine is 64-bit capable */ + if ((si_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64) { + /* backplane are 64-bit capable */ + if (si_backplane64(sih)) + /* If bus is System Backplane or PCIE then we can access 64-bits */ + if ((BUSTYPE(sih->bustype) == SI_BUS) || + ((BUSTYPE(sih->bustype) == PCI_BUS) && + (sih->buscoretype == PCIE_CORE_ID))) + return DMADDRWIDTH_64; + + /* DMA64 is always 32-bit capable, AE is always true */ + ASSERT(_dma64_addrext(osh, (dma64regs_t *) dmaregs)); + + return DMADDRWIDTH_32; + } + + /* Start checking for 32-bit / 30-bit addressing */ + dma32regs = (dma32regs_t *) dmaregs; + + /* For System Backplane, PCIE bus or addrext feature, 32-bits ok */ + if ((BUSTYPE(sih->bustype) == SI_BUS) || + ((BUSTYPE(sih->bustype) == PCI_BUS) + && sih->buscoretype == PCIE_CORE_ID) + || (_dma32_addrext(osh, dma32regs))) + return DMADDRWIDTH_32; + + /* Fallthru */ + return DMADDRWIDTH_30; +} diff --git a/drivers/staging/brcm80211/util/hndpmu.c b/drivers/staging/brcm80211/util/hndpmu.c new file mode 100644 index 0000000..a8f3306 --- /dev/null +++ b/drivers/staging/brcm80211/util/hndpmu.c @@ -0,0 +1,2693 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include <linux/kernel.h> +#include <linux/string.h> +#include <linuxver.h> +#include <bcmdefs.h> +#include <osl.h> +#include <bcmutils.h> +#include <siutils.h> +#include <bcmdevs.h> +#include <hndsoc.h> +#include <sbchipc.h> +#include <hndpmu.h> +#include "siutils_priv.h" + +#define PMU_ERROR(args) + +#ifdef BCMDBG +#define PMU_MSG(args) printf args +#else +#define PMU_MSG(args) +#endif /* BCMDBG */ + +/* To check in verbose debugging messages not intended + * to be on except on private builds. + */ +#define PMU_NONE(args) + +/* PLL controls/clocks */ +static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, + u32 xtal); +static u32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc); +static u32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc); + +/* PMU resources */ +static bool si_pmu_res_depfltr_bb(si_t *sih); +static bool si_pmu_res_depfltr_ncb(si_t *sih); +static bool si_pmu_res_depfltr_paldo(si_t *sih); +static bool si_pmu_res_depfltr_npaldo(si_t *sih); +static u32 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, + u32 rsrcs, bool all); +static uint si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc, + u8 rsrc); +static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax); +static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, + osl_t *osh, u8 spuravoid); + +static void si_pmu_set_4330_plldivs(si_t *sih); + +/* FVCO frequency */ +#define FVCO_880 880000 /* 880MHz */ +#define FVCO_1760 1760000 /* 1760MHz */ +#define FVCO_1440 1440000 /* 1440MHz */ +#define FVCO_960 960000 /* 960MHz */ + +/* Read/write a chipcontrol reg */ +u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val) +{ + si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol_addr), ~0, + reg); + return si_corereg(sih, SI_CC_IDX, + offsetof(chipcregs_t, chipcontrol_data), mask, val); +} + +/* Read/write a regcontrol reg */ +u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val) +{ + si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr), ~0, + reg); + return si_corereg(sih, SI_CC_IDX, + offsetof(chipcregs_t, regcontrol_data), mask, val); +} + +/* Read/write a pllcontrol reg */ +u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val) +{ + si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pllcontrol_addr), ~0, + reg); + return si_corereg(sih, SI_CC_IDX, + offsetof(chipcregs_t, pllcontrol_data), mask, val); +} + +/* PMU PLL update */ +void si_pmu_pllupd(si_t *sih) +{ + si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmucontrol), + PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD); +} + +/* Setup switcher voltage */ +void si_pmu_set_switcher_voltage(si_t *sih, osl_t *osh, u8 bb_voltage, + u8 rf_voltage) +{ + chipcregs_t *cc; + uint origidx; + + ASSERT(sih->cccaps & CC_CAP_PMU); + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + W_REG(osh, &cc->regcontrol_addr, 0x01); + W_REG(osh, &cc->regcontrol_data, (u32) (bb_voltage & 0x1f) << 22); + + W_REG(osh, &cc->regcontrol_addr, 0x00); + W_REG(osh, &cc->regcontrol_data, (u32) (rf_voltage & 0x1f) << 14); + + /* Return to original core */ + si_setcoreidx(sih, origidx); +} + +void si_pmu_set_ldo_voltage(si_t *sih, osl_t *osh, u8 ldo, u8 voltage) +{ + u8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0; + u8 addr = 0; + + ASSERT(sih->cccaps & CC_CAP_PMU); + + switch (CHIPID(sih->chip)) { + case BCM4336_CHIP_ID: + switch (ldo) { + case SET_LDO_VOLTAGE_CLDO_PWM: + addr = 4; + rc_shift = 1; + mask = 0xf; + break; + case SET_LDO_VOLTAGE_CLDO_BURST: + addr = 4; + rc_shift = 5; + mask = 0xf; + break; + case SET_LDO_VOLTAGE_LNLDO1: + addr = 4; + rc_shift = 17; + mask = 0xf; + break; + default: + ASSERT(false); + return; + } + break; + case BCM4330_CHIP_ID: + switch (ldo) { + case SET_LDO_VOLTAGE_CBUCK_PWM: + addr = 3; + rc_shift = 0; + mask = 0x1f; + break; + default: + ASSERT(false); + break; + } + break; + default: + ASSERT(false); + return; + } + + shift = sr_cntl_shift + rc_shift; + + si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr), + ~0, addr); + si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_data), + mask << shift, (voltage & mask) << shift); +} + +/* d11 slow to fast clock transition time in slow clock cycles */ +#define D11SCC_SLOW2FAST_TRANSITION 2 + +u16 si_pmu_fast_pwrup_delay(si_t *sih, osl_t *osh) +{ + uint delay = PMU_MAX_TRANSITION_DLY; + chipcregs_t *cc; + uint origidx; +#ifdef BCMDBG + char chn[8]; + chn[0] = 0; /* to suppress compile error */ +#endif + + ASSERT(sih->cccaps & CC_CAP_PMU); + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + switch (CHIPID(sih->chip)) { + case BCM43224_CHIP_ID: + case BCM43225_CHIP_ID: + case BCM43421_CHIP_ID: + case BCM43235_CHIP_ID: + case BCM43236_CHIP_ID: + case BCM43238_CHIP_ID: + case BCM4331_CHIP_ID: + case BCM6362_CHIP_ID: + case BCM4313_CHIP_ID: + delay = ISSIM_ENAB(sih) ? 70 : 3700; + break; + case BCM4329_CHIP_ID: + if (ISSIM_ENAB(sih)) + delay = 70; + else { + u32 ilp = si_ilp_clock(sih); + delay = + (si_pmu_res_uptime(sih, osh, cc, RES4329_HT_AVAIL) + + D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - + 1) / ilp); + delay = (11 * delay) / 10; + } + break; + case BCM4319_CHIP_ID: + delay = ISSIM_ENAB(sih) ? 70 : 3700; + break; + case BCM4336_CHIP_ID: + if (ISSIM_ENAB(sih)) + delay = 70; + else { + u32 ilp = si_ilp_clock(sih); + delay = + (si_pmu_res_uptime(sih, osh, cc, RES4336_HT_AVAIL) + + D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - + 1) / ilp); + delay = (11 * delay) / 10; + } + break; + case BCM4330_CHIP_ID: + if (ISSIM_ENAB(sih)) + delay = 70; + else { + u32 ilp = si_ilp_clock(sih); + delay = + (si_pmu_res_uptime(sih, osh, cc, RES4330_HT_AVAIL) + + D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - + 1) / ilp); + delay = (11 * delay) / 10; + } + break; + default: + break; + } + /* Return to original core */ + si_setcoreidx(sih, origidx); + + return (u16) delay; +} + +u32 si_pmu_force_ilp(si_t *sih, osl_t *osh, bool force) +{ + chipcregs_t *cc; + uint origidx; + u32 oldpmucontrol; + + ASSERT(sih->cccaps & CC_CAP_PMU); + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + oldpmucontrol = R_REG(osh, &cc->pmucontrol); + if (force) + W_REG(osh, &cc->pmucontrol, oldpmucontrol & + ~(PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN)); + else + W_REG(osh, &cc->pmucontrol, oldpmucontrol | + (PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN)); + + /* Return to original core */ + si_setcoreidx(sih, origidx); + + return oldpmucontrol; +} + +/* Setup resource up/down timers */ +typedef struct { + u8 resnum; + u16 updown; +} pmu_res_updown_t; + +/* Change resource dependancies masks */ +typedef struct { + u32 res_mask; /* resources (chip specific) */ + s8 action; /* action */ + u32 depend_mask; /* changes to the dependancies mask */ + bool(*filter) (si_t *sih); /* action is taken when filter is NULL or return true */ +} pmu_res_depend_t; + +/* Resource dependancies mask change action */ +#define RES_DEPEND_SET 0 /* Override the dependancies mask */ +#define RES_DEPEND_ADD 1 /* Add to the dependancies mask */ +#define RES_DEPEND_REMOVE -1 /* Remove from the dependancies mask */ + +static const pmu_res_updown_t bcm4328a0_res_updown[] = { + { + RES4328_EXT_SWITCHER_PWM, 0x0101}, { + RES4328_BB_SWITCHER_PWM, 0x1f01}, { + RES4328_BB_SWITCHER_BURST, 0x010f}, { + RES4328_BB_EXT_SWITCHER_BURST, 0x0101}, { + RES4328_ILP_REQUEST, 0x0202}, { + RES4328_RADIO_SWITCHER_PWM, 0x0f01}, { + RES4328_RADIO_SWITCHER_BURST, 0x0f01}, { + RES4328_ROM_SWITCH, 0x0101}, { + RES4328_PA_REF_LDO, 0x0f01}, { + RES4328_RADIO_LDO, 0x0f01}, { + RES4328_AFE_LDO, 0x0f01}, { + RES4328_PLL_LDO, 0x0f01}, { + RES4328_BG_FILTBYP, 0x0101}, { + RES4328_TX_FILTBYP, 0x0101}, { + RES4328_RX_FILTBYP, 0x0101}, { + RES4328_XTAL_PU, 0x0101}, { + RES4328_XTAL_EN, 0xa001}, { + RES4328_BB_PLL_FILTBYP, 0x0101}, { + RES4328_RF_PLL_FILTBYP, 0x0101}, { + RES4328_BB_PLL_PU, 0x0701} +}; + +static const pmu_res_depend_t bcm4328a0_res_depend[] = { + /* Adjust ILP request resource not to force ext/BB switchers into burst mode */ + { + PMURES_BIT(RES4328_ILP_REQUEST), + RES_DEPEND_SET, + PMURES_BIT(RES4328_EXT_SWITCHER_PWM) | + PMURES_BIT(RES4328_BB_SWITCHER_PWM), NULL} +}; + +static const pmu_res_updown_t bcm4325a0_res_updown_qt[] = { + { + RES4325_HT_AVAIL, 0x0300}, { + RES4325_BBPLL_PWRSW_PU, 0x0101}, { + RES4325_RFPLL_PWRSW_PU, 0x0101}, { + RES4325_ALP_AVAIL, 0x0100}, { + RES4325_XTAL_PU, 0x1000}, { + RES4325_LNLDO1_PU, 0x0800}, { + RES4325_CLDO_CBUCK_PWM, 0x0101}, { + RES4325_CBUCK_PWM, 0x0803} +}; + +static const pmu_res_updown_t bcm4325a0_res_updown[] = { + { + RES4325_XTAL_PU, 0x1501} +}; + +static const pmu_res_depend_t bcm4325a0_res_depend[] = { + /* Adjust OTP PU resource dependencies - remove BB BURST */ + { + PMURES_BIT(RES4325_OTP_PU), + RES_DEPEND_REMOVE, + PMURES_BIT(RES4325_BUCK_BOOST_BURST), NULL}, + /* Adjust ALP/HT Avail resource dependencies - bring up BB along if it is used. */ + { + PMURES_BIT(RES4325_ALP_AVAIL) | PMURES_BIT(RES4325_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4325_BUCK_BOOST_BURST) | + PMURES_BIT(RES4325_BUCK_BOOST_PWM), si_pmu_res_depfltr_bb}, + /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */ + { + PMURES_BIT(RES4325_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4325_RX_PWRSW_PU) | + PMURES_BIT(RES4325_TX_PWRSW_PU) | + PMURES_BIT(RES4325_LOGEN_PWRSW_PU) | + PMURES_BIT(RES4325_AFE_PWRSW_PU), NULL}, + /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */ + { + PMURES_BIT(RES4325_ILP_REQUEST) | + PMURES_BIT(RES4325_ABUCK_BURST) | + PMURES_BIT(RES4325_ABUCK_PWM) | + PMURES_BIT(RES4325_LNLDO1_PU) | + PMURES_BIT(RES4325C1_LNLDO2_PU) | + PMURES_BIT(RES4325_XTAL_PU) | + PMURES_BIT(RES4325_ALP_AVAIL) | + PMURES_BIT(RES4325_RX_PWRSW_PU) | + PMURES_BIT(RES4325_TX_PWRSW_PU) | + PMURES_BIT(RES4325_RFPLL_PWRSW_PU) | + PMURES_BIT(RES4325_LOGEN_PWRSW_PU) | + PMURES_BIT(RES4325_AFE_PWRSW_PU) | + PMURES_BIT(RES4325_BBPLL_PWRSW_PU) | + PMURES_BIT(RES4325_HT_AVAIL), RES_DEPEND_REMOVE, + PMURES_BIT(RES4325B0_CBUCK_LPOM) | + PMURES_BIT(RES4325B0_CBUCK_BURST) | + PMURES_BIT(RES4325B0_CBUCK_PWM), si_pmu_res_depfltr_ncb} +}; + +static const pmu_res_updown_t bcm4315a0_res_updown_qt[] = { + { + RES4315_HT_AVAIL, 0x0101}, { + RES4315_XTAL_PU, 0x0100}, { + RES4315_LNLDO1_PU, 0x0100}, { + RES4315_PALDO_PU, 0x0100}, { + RES4315_CLDO_PU, 0x0100}, { + RES4315_CBUCK_PWM, 0x0100}, { + RES4315_CBUCK_BURST, 0x0100}, { + RES4315_CBUCK_LPOM, 0x0100} +}; + +static const pmu_res_updown_t bcm4315a0_res_updown[] = { + { + RES4315_XTAL_PU, 0x2501} +}; + +static const pmu_res_depend_t bcm4315a0_res_depend[] = { + /* Adjust OTP PU resource dependencies - not need PALDO unless write */ + { + PMURES_BIT(RES4315_OTP_PU), + RES_DEPEND_REMOVE, + PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_npaldo}, + /* Adjust ALP/HT Avail resource dependencies - bring up PALDO along if it is used. */ + { + PMURES_BIT(RES4315_ALP_AVAIL) | PMURES_BIT(RES4315_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_paldo}, + /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */ + { + PMURES_BIT(RES4315_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4315_RX_PWRSW_PU) | + PMURES_BIT(RES4315_TX_PWRSW_PU) | + PMURES_BIT(RES4315_LOGEN_PWRSW_PU) | + PMURES_BIT(RES4315_AFE_PWRSW_PU), NULL}, + /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */ + { + PMURES_BIT(RES4315_CLDO_PU) | PMURES_BIT(RES4315_ILP_REQUEST) | + PMURES_BIT(RES4315_LNLDO1_PU) | + PMURES_BIT(RES4315_OTP_PU) | + PMURES_BIT(RES4315_LNLDO2_PU) | + PMURES_BIT(RES4315_XTAL_PU) | + PMURES_BIT(RES4315_ALP_AVAIL) | + PMURES_BIT(RES4315_RX_PWRSW_PU) | + PMURES_BIT(RES4315_TX_PWRSW_PU) | + PMURES_BIT(RES4315_RFPLL_PWRSW_PU) | + PMURES_BIT(RES4315_LOGEN_PWRSW_PU) | + PMURES_BIT(RES4315_AFE_PWRSW_PU) | + PMURES_BIT(RES4315_BBPLL_PWRSW_PU) | + PMURES_BIT(RES4315_HT_AVAIL), RES_DEPEND_REMOVE, + PMURES_BIT(RES4315_CBUCK_LPOM) | + PMURES_BIT(RES4315_CBUCK_BURST) | + PMURES_BIT(RES4315_CBUCK_PWM), si_pmu_res_depfltr_ncb} +}; + + /* 4329 specific. needs to come back this issue later */ +static const pmu_res_updown_t bcm4329_res_updown[] = { + { + RES4329_XTAL_PU, 0x1501} +}; + +static const pmu_res_depend_t bcm4329_res_depend[] = { + /* Adjust HT Avail resource dependencies */ + { + PMURES_BIT(RES4329_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4329_CBUCK_LPOM) | + PMURES_BIT(RES4329_CBUCK_BURST) | + PMURES_BIT(RES4329_CBUCK_PWM) | + PMURES_BIT(RES4329_CLDO_PU) | + PMURES_BIT(RES4329_PALDO_PU) | + PMURES_BIT(RES4329_LNLDO1_PU) | + PMURES_BIT(RES4329_XTAL_PU) | + PMURES_BIT(RES4329_ALP_AVAIL) | + PMURES_BIT(RES4329_RX_PWRSW_PU) | + PMURES_BIT(RES4329_TX_PWRSW_PU) | + PMURES_BIT(RES4329_RFPLL_PWRSW_PU) | + PMURES_BIT(RES4329_LOGEN_PWRSW_PU) | + PMURES_BIT(RES4329_AFE_PWRSW_PU) | + PMURES_BIT(RES4329_BBPLL_PWRSW_PU), NULL} +}; + +static const pmu_res_updown_t bcm4319a0_res_updown_qt[] = { + { + RES4319_HT_AVAIL, 0x0101}, { + RES4319_XTAL_PU, 0x0100}, { + RES4319_LNLDO1_PU, 0x0100}, { + RES4319_PALDO_PU, 0x0100}, { + RES4319_CLDO_PU, 0x0100}, { + RES4319_CBUCK_PWM, 0x0100}, { + RES4319_CBUCK_BURST, 0x0100}, { + RES4319_CBUCK_LPOM, 0x0100} +}; + +static const pmu_res_updown_t bcm4319a0_res_updown[] = { + { + RES4319_XTAL_PU, 0x3f01} +}; + +static const pmu_res_depend_t bcm4319a0_res_depend[] = { + /* Adjust OTP PU resource dependencies - not need PALDO unless write */ + { + PMURES_BIT(RES4319_OTP_PU), + RES_DEPEND_REMOVE, + PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_npaldo}, + /* Adjust HT Avail resource dependencies - bring up PALDO along if it is used. */ + { + PMURES_BIT(RES4319_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_paldo}, + /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */ + { + PMURES_BIT(RES4319_HT_AVAIL), + RES_DEPEND_ADD, + PMURES_BIT(RES4319_RX_PWRSW_PU) | + PMURES_BIT(RES4319_TX_PWRSW_PU) | + PMURES_BIT(RES4319_RFPLL_PWRSW_PU) | + PMURES_BIT(RES4319_LOGEN_PWRSW_PU) | + PMURES_BIT(RES4319_AFE_PWRSW_PU), NULL} +}; + +static const pmu_res_updown_t bcm4336a0_res_updown_qt[] = { + { + RES4336_HT_AVAIL, 0x0101}, { + RES4336_XTAL_PU, 0x0100}, { + RES4336_CLDO_PU, 0x0100}, { + RES4336_CBUCK_PWM, 0x0100}, { + RES4336_CBUCK_BURST, 0x0100}, { + RES4336_CBUCK_LPOM, 0x0100} +}; + +static const pmu_res_updown_t bcm4336a0_res_updown[] = { + { + RES4336_HT_AVAIL, 0x0D01} +}; + +static const pmu_res_depend_t bcm4336a0_res_depend[] = { + /* Just a dummy entry for now */ + { + PMURES_BIT(RES4336_RSVD), RES_DEPEND_ADD, 0, NULL} +}; + +static const pmu_res_updown_t bcm4330a0_res_updown_qt[] = { + { + RES4330_HT_AVAIL, 0x0101}, { + RES4330_XTAL_PU, 0x0100}, { + RES4330_CLDO_PU, 0x0100}, { + RES4330_CBUCK_PWM, 0x0100}, { + RES4330_CBUCK_BURST, 0x0100}, { + RES4330_CBUCK_LPOM, 0x0100} +}; + +static const pmu_res_updown_t bcm4330a0_res_updown[] = { + { + RES4330_HT_AVAIL, 0x0e02} +}; + +static const pmu_res_depend_t bcm4330a0_res_depend[] = { + /* Just a dummy entry for now */ + { + PMURES_BIT(RES4330_HT_AVAIL), RES_DEPEND_ADD, 0, NULL} +}; + +/* true if the power topology uses the buck boost to provide 3.3V to VDDIO_RF and WLAN PA */ +static bool si_pmu_res_depfltr_bb(si_t *sih) +{ + return (sih->boardflags & BFL_BUCKBOOST) != 0; +} + +/* true if the power topology doesn't use the cbuck. Key on chiprev also if the chip is BCM4325. */ +static bool si_pmu_res_depfltr_ncb(si_t *sih) +{ + + return (sih->boardflags & BFL_NOCBUCK) != 0; +} + +/* true if the power topology uses the PALDO */ +static bool si_pmu_res_depfltr_paldo(si_t *sih) +{ + return (sih->boardflags & BFL_PALDO) != 0; +} + +/* true if the power topology doesn't use the PALDO */ +static bool si_pmu_res_depfltr_npaldo(si_t *sih) +{ + return (sih->boardflags & BFL_PALDO) == 0; +} + +#define BCM94325_BBVDDIOSD_BOARDS(sih) (sih->boardtype == BCM94325DEVBU_BOARD || \ + sih->boardtype == BCM94325BGABU_BOARD) + +/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */ +static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax) +{ + u32 min_mask = 0, max_mask = 0; + uint rsrcs; + char *val; + + /* # resources */ + rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; + + /* determine min/max rsrc masks */ + switch (CHIPID(sih->chip)) { + case BCM43224_CHIP_ID: + case BCM43225_CHIP_ID: + case BCM43421_CHIP_ID: + case BCM43235_CHIP_ID: + case BCM43236_CHIP_ID: + case BCM43238_CHIP_ID: + case BCM4331_CHIP_ID: + case BCM6362_CHIP_ID: + /* ??? */ + break; + + case BCM4329_CHIP_ID: + /* 4329 spedific issue. Needs to come back this issue later */ + /* Down to save the power. */ + min_mask = + PMURES_BIT(RES4329_CBUCK_LPOM) | + PMURES_BIT(RES4329_CLDO_PU); + /* Allow (but don't require) PLL to turn on */ + max_mask = 0x3ff63e; + break; + case BCM4319_CHIP_ID: + /* We only need a few resources to be kept on all the time */ + min_mask = PMURES_BIT(RES4319_CBUCK_LPOM) | + PMURES_BIT(RES4319_CLDO_PU); + + /* Allow everything else to be turned on upon requests */ + max_mask = ~(~0 << rsrcs); + break; + case BCM4336_CHIP_ID: + /* Down to save the power. */ + min_mask = + PMURES_BIT(RES4336_CBUCK_LPOM) | PMURES_BIT(RES4336_CLDO_PU) + | PMURES_BIT(RES4336_LDO3P3_PU) | PMURES_BIT(RES4336_OTP_PU) + | PMURES_BIT(RES4336_DIS_INT_RESET_PD); + /* Allow (but don't require) PLL to turn on */ + max_mask = 0x1ffffff; + break; + + case BCM4330_CHIP_ID: + /* Down to save the power. */ + min_mask = + PMURES_BIT(RES4330_CBUCK_LPOM) | PMURES_BIT(RES4330_CLDO_PU) + | PMURES_BIT(RES4330_DIS_INT_RESET_PD) | + PMURES_BIT(RES4330_LDO3P3_PU) | PMURES_BIT(RES4330_OTP_PU); + /* Allow (but don't require) PLL to turn on */ + max_mask = 0xfffffff; + break; + + case BCM4313_CHIP_ID: + min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) | + PMURES_BIT(RES4313_XTAL_PU_RSRC) | + PMURES_BIT(RES4313_ALP_AVAIL_RSRC) | + PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC); + max_mask = 0xffff; + break; + default: + break; + } + + /* Apply nvram override to min mask */ + val = getvar(NULL, "rmin"); + if (val != NULL) { + PMU_MSG(("Applying rmin=%s to min_mask\n", val)); + min_mask = (u32) simple_strtoul(val, NULL, 0); + } + /* Apply nvram override to max mask */ + val = getvar(NULL, "rmax"); + if (val != NULL) { + PMU_MSG(("Applying rmax=%s to max_mask\n", val)); + max_mask = (u32) simple_strtoul(val, NULL, 0); + } + + *pmin = min_mask; + *pmax = max_mask; +} + +/* initialize PMU resources */ +void si_pmu_res_init(si_t *sih, osl_t *osh) +{ + chipcregs_t *cc; + uint origidx; + const pmu_res_updown_t *pmu_res_updown_table = NULL; + uint pmu_res_updown_table_sz = 0; + const pmu_res_depend_t *pmu_res_depend_table = NULL; + uint pmu_res_depend_table_sz = 0; + u32 min_mask = 0, max_mask = 0; + char name[8], *val; + uint i, rsrcs; + + ASSERT(sih->cccaps & CC_CAP_PMU); + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + switch (CHIPID(sih->chip)) { + case BCM4329_CHIP_ID: + /* Optimize resources up/down timers */ + if (ISSIM_ENAB(sih)) { + pmu_res_updown_table = NULL; + pmu_res_updown_table_sz = 0; + } else { + pmu_res_updown_table = bcm4329_res_updown; + pmu_res_updown_table_sz = ARRAY_SIZE(bcm4329_res_updown); + } + /* Optimize resources dependencies */ + pmu_res_depend_table = bcm4329_res_depend; + pmu_res_depend_table_sz = ARRAY_SIZE(bcm4329_res_depend); + break; + + case BCM4319_CHIP_ID: + /* Optimize resources up/down timers */ + if (ISSIM_ENAB(sih)) { + pmu_res_updown_table = bcm4319a0_res_updown_qt; + pmu_res_updown_table_sz = + ARRAY_SIZE(bcm4319a0_res_updown_qt); + } else { + pmu_res_updown_table = bcm4319a0_res_updown; + pmu_res_updown_table_sz = + ARRAY_SIZE(bcm4319a0_res_updown); + } + /* Optimize resources dependancies masks */ + pmu_res_depend_table = bcm4319a0_res_depend; + pmu_res_depend_table_sz = ARRAY_SIZE(bcm4319a0_res_depend); + break; + + case BCM4336_CHIP_ID: + /* Optimize resources up/down timers */ + if (ISSIM_ENAB(sih)) { + pmu_res_updown_table = bcm4336a0_res_updown_qt; + pmu_res_updown_table_sz = + ARRAY_SIZE(bcm4336a0_res_updown_qt); + } else { + pmu_res_updown_table = bcm4336a0_res_updown; + pmu_res_updown_table_sz = + ARRAY_SIZE(bcm4336a0_res_updown); + } + /* Optimize resources dependancies masks */ + pmu_res_depend_table = bcm4336a0_res_depend; + pmu_res_depend_table_sz = ARRAY_SIZE(bcm4336a0_res_depend); + break; + + case BCM4330_CHIP_ID: + /* Optimize resources up/down timers */ + if (ISSIM_ENAB(sih)) { + pmu_res_updown_table = bcm4330a0_res_updown_qt; + pmu_res_updown_table_sz = + ARRAY_SIZE(bcm4330a0_res_updown_qt); + } else { + pmu_res_updown_table = bcm4330a0_res_updown; + pmu_res_updown_table_sz = + ARRAY_SIZE(bcm4330a0_res_updown); + } + /* Optimize resources dependancies masks */ + pmu_res_depend_table = bcm4330a0_res_depend; + pmu_res_depend_table_sz = ARRAY_SIZE(bcm4330a0_res_depend); + break; + + default: + break; + } + + /* # resources */ + rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; + + /* Program up/down timers */ + while (pmu_res_updown_table_sz--) { + ASSERT(pmu_res_updown_table != NULL); + PMU_MSG(("Changing rsrc %d res_updn_timer to 0x%x\n", + pmu_res_updown_table[pmu_res_updown_table_sz].resnum, + pmu_res_updown_table[pmu_res_updown_table_sz].updown)); + W_REG(osh, &cc->res_table_sel, + pmu_res_updown_table[pmu_res_updown_table_sz].resnum); + W_REG(osh, &cc->res_updn_timer, + pmu_res_updown_table[pmu_res_updown_table_sz].updown); + } + /* Apply nvram overrides to up/down timers */ + for (i = 0; i < rsrcs; i++) { + snprintf(name, sizeof(name), "r%dt", i); + val = getvar(NULL, name); + if (val == NULL) + continue; + PMU_MSG(("Applying %s=%s to rsrc %d res_updn_timer\n", name, + val, i)); + W_REG(osh, &cc->res_table_sel, (u32) i); + W_REG(osh, &cc->res_updn_timer, + (u32) simple_strtoul(val, NULL, 0)); + } + + /* Program resource dependencies table */ + while (pmu_res_depend_table_sz--) { + ASSERT(pmu_res_depend_table != NULL); + if (pmu_res_depend_table[pmu_res_depend_table_sz].filter != NULL + && !(pmu_res_depend_table[pmu_res_depend_table_sz]. + filter) (sih)) + continue; + for (i = 0; i < rsrcs; i++) { + if ((pmu_res_depend_table[pmu_res_depend_table_sz]. + res_mask & PMURES_BIT(i)) == 0) + continue; + W_REG(osh, &cc->res_table_sel, i); + switch (pmu_res_depend_table[pmu_res_depend_table_sz]. + action) { + case RES_DEPEND_SET: + PMU_MSG(("Changing rsrc %d res_dep_mask to 0x%x\n", i, pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask)); + W_REG(osh, &cc->res_dep_mask, + pmu_res_depend_table + [pmu_res_depend_table_sz].depend_mask); + break; + case RES_DEPEND_ADD: + PMU_MSG(("Adding 0x%x to rsrc %d res_dep_mask\n", pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask, i)); + OR_REG(osh, &cc->res_dep_mask, + pmu_res_depend_table + [pmu_res_depend_table_sz].depend_mask); + break; + case RES_DEPEND_REMOVE: + PMU_MSG(("Removing 0x%x from rsrc %d res_dep_mask\n", pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask, i)); + AND_REG(osh, &cc->res_dep_mask, + ~pmu_res_depend_table + [pmu_res_depend_table_sz].depend_mask); + break; + default: + ASSERT(0); + break; + } + } + } + /* Apply nvram overrides to dependancies masks */ + for (i = 0; i < rsrcs; i++) { + snprintf(name, sizeof(name), "r%dd", i); + val = getvar(NULL, name); + if (val == NULL) + continue; + PMU_MSG(("Applying %s=%s to rsrc %d res_dep_mask\n", name, val, + i)); + W_REG(osh, &cc->res_table_sel, (u32) i); + W_REG(osh, &cc->res_dep_mask, + (u32) simple_strtoul(val, NULL, 0)); + } + + /* Determine min/max rsrc masks */ + si_pmu_res_masks(sih, &min_mask, &max_mask); + + /* It is required to program max_mask first and then min_mask */ + + /* Program max resource mask */ + + if (max_mask) { + PMU_MSG(("Changing max_res_mask to 0x%x\n", max_mask)); + W_REG(osh, &cc->max_res_mask, max_mask); + } + + /* Program min resource mask */ + + if (min_mask) { + PMU_MSG(("Changing min_res_mask to 0x%x\n", min_mask)); + W_REG(osh, &cc->min_res_mask, min_mask); + } + + /* Add some delay; allow resources to come up and settle. */ + mdelay(2); + + /* Return to original core */ + si_setcoreidx(sih, origidx); +} + +/* setup pll and query clock speed */ +typedef struct { + u16 freq; + u8 xf; + u8 wbint; + u32 wbfrac; +} pmu0_xtaltab0_t; + +/* the following table is based on 880Mhz fvco */ +static const pmu0_xtaltab0_t pmu0_xtaltab0[] = { + { + 12000, 1, 73, 349525}, { + 13000, 2, 67, 725937}, { + 14400, 3, 61, 116508}, { + 15360, 4, 57, 305834}, { + 16200, 5, 54, 336579}, { + 16800, 6, 52, 399457}, { + 19200, 7, 45, 873813}, { + 19800, 8, 44, 466033}, { + 20000, 9, 44, 0}, { + 25000, 10, 70, 419430}, { + 26000, 11, 67, 725937}, { + 30000, 12, 58, 699050}, { + 38400, 13, 45, 873813}, { + 40000, 14, 45, 0}, { + 0, 0, 0, 0} +}; + +#define PMU0_XTAL0_DEFAULT 8 + +/* setup pll and query clock speed */ +typedef struct { + u16 fref; + u8 xf; + u8 p1div; + u8 p2div; + u8 ndiv_int; + u32 ndiv_frac; +} pmu1_xtaltab0_t; + +static const pmu1_xtaltab0_t pmu1_xtaltab0_880_4329[] = { + { + 12000, 1, 3, 22, 0x9, 0xFFFFEF}, { + 13000, 2, 1, 6, 0xb, 0x483483}, { + 14400, 3, 1, 10, 0xa, 0x1C71C7}, { + 15360, 4, 1, 5, 0xb, 0x755555}, { + 16200, 5, 1, 10, 0x5, 0x6E9E06}, { + 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, { + 19200, 7, 1, 4, 0xb, 0x755555}, { + 19800, 8, 1, 11, 0x4, 0xA57EB}, { + 20000, 9, 1, 11, 0x4, 0x0}, { + 24000, 10, 3, 11, 0xa, 0x0}, { + 25000, 11, 5, 16, 0xb, 0x0}, { + 26000, 12, 1, 1, 0x21, 0xD89D89}, { + 30000, 13, 3, 8, 0xb, 0x0}, { + 37400, 14, 3, 1, 0x46, 0x969696}, { + 38400, 15, 1, 1, 0x16, 0xEAAAAA}, { + 40000, 16, 1, 2, 0xb, 0}, { + 0, 0, 0, 0, 0, 0} +}; + +/* the following table is based on 880Mhz fvco */ +static const pmu1_xtaltab0_t pmu1_xtaltab0_880[] = { + { + 12000, 1, 3, 22, 0x9, 0xFFFFEF}, { + 13000, 2, 1, 6, 0xb, 0x483483}, { + 14400, 3, 1, 10, 0xa, 0x1C71C7}, { + 15360, 4, 1, 5, 0xb, 0x755555}, { + 16200, 5, 1, 10, 0x5, 0x6E9E06}, { + 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, { + 19200, 7, 1, 4, 0xb, 0x755555}, { + 19800, 8, 1, 11, 0x4, 0xA57EB}, { + 20000, 9, 1, 11, 0x4, 0x0}, { + 24000, 10, 3, 11, 0xa, 0x0}, { + 25000, 11, 5, 16, 0xb, 0x0}, { + 26000, 12, 1, 2, 0x10, 0xEC4EC4}, { + 30000, 13, 3, 8, 0xb, 0x0}, { + 33600, 14, 1, 2, 0xd, 0x186186}, { + 38400, 15, 1, 2, 0xb, 0x755555}, { + 40000, 16, 1, 2, 0xb, 0}, { + 0, 0, 0, 0, 0, 0} +}; + +#define PMU1_XTALTAB0_880_12000K 0 +#define PMU1_XTALTAB0_880_13000K 1 +#define PMU1_XTALTAB0_880_14400K 2 +#define PMU1_XTALTAB0_880_15360K 3 +#define PMU1_XTALTAB0_880_16200K 4 +#define PMU1_XTALTAB0_880_16800K 5 +#define PMU1_XTALTAB0_880_19200K 6 +#define PMU1_XTALTAB0_880_19800K 7 +#define PMU1_XTALTAB0_880_20000K 8 +#define PMU1_XTALTAB0_880_24000K 9 +#define PMU1_XTALTAB0_880_25000K 10 +#define PMU1_XTALTAB0_880_26000K 11 +#define PMU1_XTALTAB0_880_30000K 12 +#define PMU1_XTALTAB0_880_37400K 13 +#define PMU1_XTALTAB0_880_38400K 14 +#define PMU1_XTALTAB0_880_40000K 15 + +/* the following table is based on 1760Mhz fvco */ +static const pmu1_xtaltab0_t pmu1_xtaltab0_1760[] = { + { + 12000, 1, 3, 44, 0x9, 0xFFFFEF}, { + 13000, 2, 1, 12, 0xb, 0x483483}, { + 14400, 3, 1, 20, 0xa, 0x1C71C7}, { + 15360, 4, 1, 10, 0xb, 0x755555}, { + 16200, 5, 1, 20, 0x5, 0x6E9E06}, { + 16800, 6, 1, 20, 0x5, 0x3Cf3Cf}, { + 19200, 7, 1, 18, 0x5, 0x17B425}, { + 19800, 8, 1, 22, 0x4, 0xA57EB}, { + 20000, 9, 1, 22, 0x4, 0x0}, { + 24000, 10, 3, 22, 0xa, 0x0}, { + 25000, 11, 5, 32, 0xb, 0x0}, { + 26000, 12, 1, 4, 0x10, 0xEC4EC4}, { + 30000, 13, 3, 16, 0xb, 0x0}, { + 38400, 14, 1, 10, 0x4, 0x955555}, { + 40000, 15, 1, 4, 0xb, 0}, { + 0, 0, 0, 0, 0, 0} +}; + +/* table index */ +#define PMU1_XTALTAB0_1760_12000K 0 +#define PMU1_XTALTAB0_1760_13000K 1 +#define PMU1_XTALTAB0_1760_14400K 2 +#define PMU1_XTALTAB0_1760_15360K 3 +#define PMU1_XTALTAB0_1760_16200K 4 +#define PMU1_XTALTAB0_1760_16800K 5 +#define PMU1_XTALTAB0_1760_19200K 6 +#define PMU1_XTALTAB0_1760_19800K 7 +#define PMU1_XTALTAB0_1760_20000K 8 +#define PMU1_XTALTAB0_1760_24000K 9 +#define PMU1_XTALTAB0_1760_25000K 10 +#define PMU1_XTALTAB0_1760_26000K 11 +#define PMU1_XTALTAB0_1760_30000K 12 +#define PMU1_XTALTAB0_1760_38400K 13 +#define PMU1_XTALTAB0_1760_40000K 14 + +/* the following table is based on 1440Mhz fvco */ +static const pmu1_xtaltab0_t pmu1_xtaltab0_1440[] = { + { + 12000, 1, 1, 1, 0x78, 0x0}, { + 13000, 2, 1, 1, 0x6E, 0xC4EC4E}, { + 14400, 3, 1, 1, 0x64, 0x0}, { + 15360, 4, 1, 1, 0x5D, 0xC00000}, { + 16200, 5, 1, 1, 0x58, 0xE38E38}, { + 16800, 6, 1, 1, 0x55, 0xB6DB6D}, { + 19200, 7, 1, 1, 0x4B, 0}, { + 19800, 8, 1, 1, 0x48, 0xBA2E8B}, { + 20000, 9, 1, 1, 0x48, 0x0}, { + 25000, 10, 1, 1, 0x39, 0x999999}, { + 26000, 11, 1, 1, 0x37, 0x627627}, { + 30000, 12, 1, 1, 0x30, 0x0}, { + 37400, 13, 2, 1, 0x4D, 0x15E76}, { + 38400, 13, 2, 1, 0x4B, 0x0}, { + 40000, 14, 2, 1, 0x48, 0x0}, { + 48000, 15, 2, 1, 0x3c, 0x0}, { + 0, 0, 0, 0, 0, 0} +}; + +/* table index */ +#define PMU1_XTALTAB0_1440_12000K 0 +#define PMU1_XTALTAB0_1440_13000K 1 +#define PMU1_XTALTAB0_1440_14400K 2 +#define PMU1_XTALTAB0_1440_15360K 3 +#define PMU1_XTALTAB0_1440_16200K 4 +#define PMU1_XTALTAB0_1440_16800K 5 +#define PMU1_XTALTAB0_1440_19200K 6 +#define PMU1_XTALTAB0_1440_19800K 7 +#define PMU1_XTALTAB0_1440_20000K 8 +#define PMU1_XTALTAB0_1440_25000K 9 +#define PMU1_XTALTAB0_1440_26000K 10 +#define PMU1_XTALTAB0_1440_30000K 11 +#define PMU1_XTALTAB0_1440_37400K 12 +#define PMU1_XTALTAB0_1440_38400K 13 +#define PMU1_XTALTAB0_1440_40000K 14 +#define PMU1_XTALTAB0_1440_48000K 15 + +#define XTAL_FREQ_24000MHZ 24000 +#define XTAL_FREQ_30000MHZ 30000 +#define XTAL_FREQ_37400MHZ 37400 +#define XTAL_FREQ_48000MHZ 48000 + +static const pmu1_xtaltab0_t pmu1_xtaltab0_960[] = { + { + 12000, 1, 1, 1, 0x50, 0x0}, { + 13000, 2, 1, 1, 0x49, 0xD89D89}, { + 14400, 3, 1, 1, 0x42, 0xAAAAAA}, { + 15360, 4, 1, 1, 0x3E, 0x800000}, { + 16200, 5, 1, 1, 0x39, 0x425ED0}, { + 16800, 6, 1, 1, 0x39, 0x249249}, { + 19200, 7, 1, 1, 0x32, 0x0}, { + 19800, 8, 1, 1, 0x30, 0x7C1F07}, { + 20000, 9, 1, 1, 0x30, 0x0}, { + 25000, 10, 1, 1, 0x26, 0x666666}, { + 26000, 11, 1, 1, 0x24, 0xEC4EC4}, { + 30000, 12, 1, 1, 0x20, 0x0}, { + 37400, 13, 2, 1, 0x33, 0x563EF9}, { + 38400, 14, 2, 1, 0x32, 0x0}, { + 40000, 15, 2, 1, 0x30, 0x0}, { + 48000, 16, 2, 1, 0x28, 0x0}, { + 0, 0, 0, 0, 0, 0} +}; + +/* table index */ +#define PMU1_XTALTAB0_960_12000K 0 +#define PMU1_XTALTAB0_960_13000K 1 +#define PMU1_XTALTAB0_960_14400K 2 +#define PMU1_XTALTAB0_960_15360K 3 +#define PMU1_XTALTAB0_960_16200K 4 +#define PMU1_XTALTAB0_960_16800K 5 +#define PMU1_XTALTAB0_960_19200K 6 +#define PMU1_XTALTAB0_960_19800K 7 +#define PMU1_XTALTAB0_960_20000K 8 +#define PMU1_XTALTAB0_960_25000K 9 +#define PMU1_XTALTAB0_960_26000K 10 +#define PMU1_XTALTAB0_960_30000K 11 +#define PMU1_XTALTAB0_960_37400K 12 +#define PMU1_XTALTAB0_960_38400K 13 +#define PMU1_XTALTAB0_960_40000K 14 +#define PMU1_XTALTAB0_960_48000K 15 + +/* select xtal table for each chip */ +static const pmu1_xtaltab0_t *si_pmu1_xtaltab0(si_t *sih) +{ +#ifdef BCMDBG + char chn[8]; +#endif + switch (CHIPID(sih->chip)) { + case BCM4329_CHIP_ID: + return pmu1_xtaltab0_880_4329; + case BCM4319_CHIP_ID: + return pmu1_xtaltab0_1440; + case BCM4336_CHIP_ID: + return pmu1_xtaltab0_960; + case BCM4330_CHIP_ID: + if (CST4330_CHIPMODE_SDIOD(sih->chipst)) + return pmu1_xtaltab0_960; + else + return pmu1_xtaltab0_1440; + default: + PMU_MSG(("si_pmu1_xtaltab0: Unknown chipid %s\n", + bcm_chipname(sih->chip, chn, 8))); + break; + } + ASSERT(0); + return NULL; +} + +/* select default xtal frequency for each chip */ +static const pmu1_xtaltab0_t *si_pmu1_xtaldef0(si_t *sih) +{ +#ifdef BCMDBG + char chn[8]; +#endif + + switch (CHIPID(sih->chip)) { + case BCM4329_CHIP_ID: + /* Default to 38400Khz */ + return &pmu1_xtaltab0_880_4329[PMU1_XTALTAB0_880_38400K]; + case BCM4319_CHIP_ID: + /* Default to 30000Khz */ + return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_30000K]; + case BCM4336_CHIP_ID: + /* Default to 26000Khz */ + return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_26000K]; + case BCM4330_CHIP_ID: + /* Default to 37400Khz */ + if (CST4330_CHIPMODE_SDIOD(sih->chipst)) + return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_37400K]; + else + return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_37400K]; + default: + PMU_MSG(("si_pmu1_xtaldef0: Unknown chipid %s\n", + bcm_chipname(sih->chip, chn, 8))); + break; + } + ASSERT(0); + return NULL; +} + +/* select default pll fvco for each chip */ +static u32 si_pmu1_pllfvco0(si_t *sih) +{ +#ifdef BCMDBG + char chn[8]; +#endif + + switch (CHIPID(sih->chip)) { + case BCM4329_CHIP_ID: + return FVCO_880; + case BCM4319_CHIP_ID: + return FVCO_1440; + case BCM4336_CHIP_ID: + return FVCO_960; + case BCM4330_CHIP_ID: + if (CST4330_CHIPMODE_SDIOD(sih->chipst)) + return FVCO_960; + else + return FVCO_1440; + default: + PMU_MSG(("si_pmu1_pllfvco0: Unknown chipid %s\n", + bcm_chipname(sih->chip, chn, 8))); + break; + } + ASSERT(0); + return 0; +} + +/* query alp/xtal clock frequency */ +static u32 +si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc) +{ + const pmu1_xtaltab0_t *xt; + u32 xf; + + /* Find the frequency in the table */ + xf = (R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >> + PCTL_XTALFREQ_SHIFT; + for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++) + if (xt->xf == xf) + break; + /* Could not find it so assign a default value */ + if (xt == NULL || xt->fref == 0) + xt = si_pmu1_xtaldef0(sih); + ASSERT(xt != NULL && xt->fref != 0); + + return xt->fref * 1000; +} + +/* Set up PLL registers in the PMU as per the crystal speed. + * XtalFreq field in pmucontrol register being 0 indicates the PLL + * is not programmed and the h/w default is assumed to work, in which + * case the xtal frequency is unknown to the s/w so we need to call + * si_pmu1_xtaldef0() wherever it is needed to return a default value. + */ +static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 xtal) +{ + const pmu1_xtaltab0_t *xt; + u32 tmp; + u32 buf_strength = 0; + u8 ndiv_mode = 1; + + /* Use h/w default PLL config */ + if (xtal == 0) { + PMU_MSG(("Unspecified xtal frequency, skip PLL configuration\n")); + return; + } + + /* Find the frequency in the table */ + for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++) + if (xt->fref == xtal) + break; + + /* Check current PLL state, bail out if it has been programmed or + * we don't know how to program it. + */ + if (xt == NULL || xt->fref == 0) { + PMU_MSG(("Unsupported xtal frequency %d.%d MHz, skip PLL configuration\n", xtal / 1000, xtal % 1000)); + return; + } + /* for 4319 bootloader already programs the PLL but bootloader does not program the + PLL4 and PLL5. So Skip this check for 4319 + */ + if ((((R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >> + PCTL_XTALFREQ_SHIFT) == xt->xf) && + !((CHIPID(sih->chip) == BCM4319_CHIP_ID) + || (CHIPID(sih->chip) == BCM4330_CHIP_ID))) { + PMU_MSG(("PLL already programmed for %d.%d MHz\n", + xt->fref / 1000, xt->fref % 1000)); + return; + } + + PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf)); + PMU_MSG(("Programming PLL for %d.%d MHz\n", xt->fref / 1000, + xt->fref % 1000)); + + switch (CHIPID(sih->chip)) { + case BCM4329_CHIP_ID: + /* Change the BBPLL drive strength to 8 for all channels */ + buf_strength = 0x888888; + AND_REG(osh, &cc->min_res_mask, + ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) | + PMURES_BIT(RES4329_HT_AVAIL))); + AND_REG(osh, &cc->max_res_mask, + ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) | + PMURES_BIT(RES4329_HT_AVAIL))); + SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, + PMU_MAX_TRANSITION_DLY); + ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL)); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); + if (xt->fref == 38400) + tmp = 0x200024C0; + else if (xt->fref == 37400) + tmp = 0x20004500; + else if (xt->fref == 26000) + tmp = 0x200024C0; + else + tmp = 0x200005C0; /* Chip Dflt Settings */ + W_REG(osh, &cc->pllcontrol_data, tmp); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); + tmp = + R_REG(osh, + &cc->pllcontrol_data) & PMU1_PLL0_PC5_CLK_DRV_MASK; + if ((xt->fref == 38400) || (xt->fref == 37400) + || (xt->fref == 26000)) + tmp |= 0x15; + else + tmp |= 0x25; /* Chip Dflt Settings */ + W_REG(osh, &cc->pllcontrol_data, tmp); + break; + + case BCM4319_CHIP_ID: + /* Change the BBPLL drive strength to 2 for all channels */ + buf_strength = 0x222222; + + /* Make sure the PLL is off */ + /* WAR65104: Disable the HT_AVAIL resource first and then + * after a delay (more than downtime for HT_AVAIL) remove the + * BBPLL resource; backplane clock moves to ALP from HT. + */ + AND_REG(osh, &cc->min_res_mask, + ~(PMURES_BIT(RES4319_HT_AVAIL))); + AND_REG(osh, &cc->max_res_mask, + ~(PMURES_BIT(RES4319_HT_AVAIL))); + + udelay(100); + AND_REG(osh, &cc->min_res_mask, + ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU))); + AND_REG(osh, &cc->max_res_mask, + ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU))); + + udelay(100); + SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, + PMU_MAX_TRANSITION_DLY); + ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL)); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); + tmp = 0x200005c0; + W_REG(osh, &cc->pllcontrol_data, tmp); + break; + + case BCM4336_CHIP_ID: + AND_REG(osh, &cc->min_res_mask, + ~(PMURES_BIT(RES4336_HT_AVAIL) | + PMURES_BIT(RES4336_MACPHY_CLKAVAIL))); + AND_REG(osh, &cc->max_res_mask, + ~(PMURES_BIT(RES4336_HT_AVAIL) | + PMURES_BIT(RES4336_MACPHY_CLKAVAIL))); + udelay(100); + SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, + PMU_MAX_TRANSITION_DLY); + ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL)); + break; + + case BCM4330_CHIP_ID: + AND_REG(osh, &cc->min_res_mask, + ~(PMURES_BIT(RES4330_HT_AVAIL) | + PMURES_BIT(RES4330_MACPHY_CLKAVAIL))); + AND_REG(osh, &cc->max_res_mask, + ~(PMURES_BIT(RES4330_HT_AVAIL) | + PMURES_BIT(RES4330_MACPHY_CLKAVAIL))); + udelay(100); + SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, + PMU_MAX_TRANSITION_DLY); + ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL)); + break; + + default: + ASSERT(0); + } + + PMU_MSG(("Done masking\n")); + + /* Write p1div and p2div to pllcontrol[0] */ + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); + tmp = R_REG(osh, &cc->pllcontrol_data) & + ~(PMU1_PLL0_PC0_P1DIV_MASK | PMU1_PLL0_PC0_P2DIV_MASK); + tmp |= + ((xt-> + p1div << PMU1_PLL0_PC0_P1DIV_SHIFT) & PMU1_PLL0_PC0_P1DIV_MASK) | + ((xt-> + p2div << PMU1_PLL0_PC0_P2DIV_SHIFT) & PMU1_PLL0_PC0_P2DIV_MASK); + W_REG(osh, &cc->pllcontrol_data, tmp); + + if ((CHIPID(sih->chip) == BCM4330_CHIP_ID)) + si_pmu_set_4330_plldivs(sih); + + if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) + && (CHIPREV(sih->chiprev) == 0)) { + + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); + tmp = R_REG(osh, &cc->pllcontrol_data); + tmp = tmp & (~DOT11MAC_880MHZ_CLK_DIVISOR_MASK); + tmp = tmp | DOT11MAC_880MHZ_CLK_DIVISOR_VAL; + W_REG(osh, &cc->pllcontrol_data, tmp); + } + if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) || + (CHIPID(sih->chip) == BCM4336_CHIP_ID) || + (CHIPID(sih->chip) == BCM4330_CHIP_ID)) + ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MFB; + else + ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MASH; + + /* Write ndiv_int and ndiv_mode to pllcontrol[2] */ + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); + tmp = R_REG(osh, &cc->pllcontrol_data) & + ~(PMU1_PLL0_PC2_NDIV_INT_MASK | PMU1_PLL0_PC2_NDIV_MODE_MASK); + tmp |= + ((xt-> + ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT) & + PMU1_PLL0_PC2_NDIV_INT_MASK) | ((ndiv_mode << + PMU1_PLL0_PC2_NDIV_MODE_SHIFT) & + PMU1_PLL0_PC2_NDIV_MODE_MASK); + W_REG(osh, &cc->pllcontrol_data, tmp); + + /* Write ndiv_frac to pllcontrol[3] */ + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); + tmp = R_REG(osh, &cc->pllcontrol_data) & ~PMU1_PLL0_PC3_NDIV_FRAC_MASK; + tmp |= ((xt->ndiv_frac << PMU1_PLL0_PC3_NDIV_FRAC_SHIFT) & + PMU1_PLL0_PC3_NDIV_FRAC_MASK); + W_REG(osh, &cc->pllcontrol_data, tmp); + + /* Write clock driving strength to pllcontrol[5] */ + if (buf_strength) { + PMU_MSG(("Adjusting PLL buffer drive strength: %x\n", + buf_strength)); + + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); + tmp = + R_REG(osh, + &cc->pllcontrol_data) & ~PMU1_PLL0_PC5_CLK_DRV_MASK; + tmp |= (buf_strength << PMU1_PLL0_PC5_CLK_DRV_SHIFT); + W_REG(osh, &cc->pllcontrol_data, tmp); + } + + PMU_MSG(("Done pll\n")); + + /* to operate the 4319 usb in 24MHz/48MHz; chipcontrol[2][84:83] needs + * to be updated. + */ + if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) + && (xt->fref != XTAL_FREQ_30000MHZ)) { + W_REG(osh, &cc->chipcontrol_addr, PMU1_PLL0_CHIPCTL2); + tmp = + R_REG(osh, + &cc->chipcontrol_data) & ~CCTL_4319USB_XTAL_SEL_MASK; + if (xt->fref == XTAL_FREQ_24000MHZ) { + tmp |= + (CCTL_4319USB_24MHZ_PLL_SEL << + CCTL_4319USB_XTAL_SEL_SHIFT); + } else if (xt->fref == XTAL_FREQ_48000MHZ) { + tmp |= + (CCTL_4319USB_48MHZ_PLL_SEL << + CCTL_4319USB_XTAL_SEL_SHIFT); + } + W_REG(osh, &cc->chipcontrol_data, tmp); + } + + /* Flush deferred pll control registers writes */ + if (sih->pmurev >= 2) + OR_REG(osh, &cc->pmucontrol, PCTL_PLL_PLLCTL_UPD); + + /* Write XtalFreq. Set the divisor also. */ + tmp = R_REG(osh, &cc->pmucontrol) & + ~(PCTL_ILP_DIV_MASK | PCTL_XTALFREQ_MASK); + tmp |= (((((xt->fref + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) & + PCTL_ILP_DIV_MASK) | + ((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK); + + if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) + && CHIPREV(sih->chiprev) == 0) { + /* clear the htstretch before clearing HTReqEn */ + AND_REG(osh, &cc->clkstretch, ~CSTRETCH_HT); + tmp &= ~PCTL_HT_REQ_EN; + } + + W_REG(osh, &cc->pmucontrol, tmp); +} + +/* query the CPU clock frequency */ +static u32 +si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc) +{ + u32 tmp, m1div; +#ifdef BCMDBG + u32 ndiv_int, ndiv_frac, p2div, p1div, fvco; + u32 fref; +#endif + u32 FVCO = si_pmu1_pllfvco0(sih); + + /* Read m1div from pllcontrol[1] */ + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); + tmp = R_REG(osh, &cc->pllcontrol_data); + m1div = (tmp & PMU1_PLL0_PC1_M1DIV_MASK) >> PMU1_PLL0_PC1_M1DIV_SHIFT; + +#ifdef BCMDBG + /* Read p2div/p1div from pllcontrol[0] */ + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); + tmp = R_REG(osh, &cc->pllcontrol_data); + p2div = (tmp & PMU1_PLL0_PC0_P2DIV_MASK) >> PMU1_PLL0_PC0_P2DIV_SHIFT; + p1div = (tmp & PMU1_PLL0_PC0_P1DIV_MASK) >> PMU1_PLL0_PC0_P1DIV_SHIFT; + + /* Calculate fvco based on xtal freq and ndiv and pdiv */ + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); + tmp = R_REG(osh, &cc->pllcontrol_data); + ndiv_int = + (tmp & PMU1_PLL0_PC2_NDIV_INT_MASK) >> PMU1_PLL0_PC2_NDIV_INT_SHIFT; + + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); + tmp = R_REG(osh, &cc->pllcontrol_data); + ndiv_frac = + (tmp & PMU1_PLL0_PC3_NDIV_FRAC_MASK) >> + PMU1_PLL0_PC3_NDIV_FRAC_SHIFT; + + fref = si_pmu1_alpclk0(sih, osh, cc) / 1000; + + fvco = (fref * ndiv_int) << 8; + fvco += (fref * (ndiv_frac >> 12)) >> 4; + fvco += (fref * (ndiv_frac & 0xfff)) >> 12; + fvco >>= 8; + fvco *= p2div; + fvco /= p1div; + fvco /= 1000; + fvco *= 1000; + + PMU_MSG(("si_pmu1_cpuclk0: ndiv_int %u ndiv_frac %u p2div %u p1div %u fvco %u\n", ndiv_int, ndiv_frac, p2div, p1div, fvco)); + + FVCO = fvco; +#endif /* BCMDBG */ + + /* Return ARM/SB clock */ + return FVCO / m1div * 1000; +} + +/* initialize PLL */ +void si_pmu_pll_init(si_t *sih, osl_t *osh, uint xtalfreq) +{ + chipcregs_t *cc; + uint origidx; +#ifdef BCMDBG + char chn[8]; +#endif + + ASSERT(sih->cccaps & CC_CAP_PMU); + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + switch (CHIPID(sih->chip)) { + case BCM4329_CHIP_ID: + if (xtalfreq == 0) + xtalfreq = 38400; + si_pmu1_pllinit0(sih, osh, cc, xtalfreq); + break; + case BCM4313_CHIP_ID: + case BCM43224_CHIP_ID: + case BCM43225_CHIP_ID: + case BCM43421_CHIP_ID: + case BCM43235_CHIP_ID: + case BCM43236_CHIP_ID: + case BCM43238_CHIP_ID: + case BCM4331_CHIP_ID: + case BCM6362_CHIP_ID: + /* ??? */ + break; + case BCM4319_CHIP_ID: + case BCM4336_CHIP_ID: + case BCM4330_CHIP_ID: + si_pmu1_pllinit0(sih, osh, cc, xtalfreq); + break; + default: + PMU_MSG(("No PLL init done for chip %s rev %d pmurev %d\n", + bcm_chipname(sih->chip, chn, 8), sih->chiprev, + sih->pmurev)); + break; + } + +#ifdef BCMDBG_FORCEHT + OR_REG(osh, &cc->clk_ctl_st, CCS_FORCEHT); +#endif + + /* Return to original core */ + si_setcoreidx(sih, origidx); +} + +/* query alp/xtal clock frequency */ +u32 si_pmu_alp_clock(si_t *sih, osl_t *osh) +{ + chipcregs_t *cc; + uint origidx; + u32 clock = ALP_CLOCK; +#ifdef BCMDBG + char chn[8]; +#endif + + ASSERT(sih->cccaps & CC_CAP_PMU); + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + switch (CHIPID(sih->chip)) { + case BCM43224_CHIP_ID: + case BCM43225_CHIP_ID: + case BCM43421_CHIP_ID: + case BCM43235_CHIP_ID: + case BCM43236_CHIP_ID: + case BCM43238_CHIP_ID: + case BCM4331_CHIP_ID: + case BCM6362_CHIP_ID: + case BCM4716_CHIP_ID: + case BCM4748_CHIP_ID: + case BCM47162_CHIP_ID: + case BCM4313_CHIP_ID: + case BCM5357_CHIP_ID: + /* always 20Mhz */ + clock = 20000 * 1000; + break; + case BCM4329_CHIP_ID: + case BCM4319_CHIP_ID: + case BCM4336_CHIP_ID: + case BCM4330_CHIP_ID: + + clock = si_pmu1_alpclk0(sih, osh, cc); + break; + case BCM5356_CHIP_ID: + /* always 25Mhz */ + clock = 25000 * 1000; + break; + default: + PMU_MSG(("No ALP clock specified " + "for chip %s rev %d pmurev %d, using default %d Hz\n", + bcm_chipname(sih->chip, chn, 8), sih->chiprev, + sih->pmurev, clock)); + break; + } + + /* Return to original core */ + si_setcoreidx(sih, origidx); + return clock; +} + +/* Find the output of the "m" pll divider given pll controls that start with + * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. + */ +static u32 +si_pmu5_clock(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0, + uint m) { + u32 tmp, div, ndiv, p1, p2, fc; + + if ((pll0 & 3) || (pll0 > PMU4716_MAINPLL_PLL0)) { + PMU_ERROR(("%s: Bad pll0: %d\n", __func__, pll0)); + return 0; + } + + /* Strictly there is an m5 divider, but I'm not sure we use it */ + if ((m == 0) || (m > 4)) { + PMU_ERROR(("%s: Bad m divider: %d\n", __func__, m)); + return 0; + } + + if (CHIPID(sih->chip) == BCM5357_CHIP_ID) { + /* Detect failure in clock setting */ + if ((R_REG(osh, &cc->chipstatus) & 0x40000) != 0) { + return 133 * 1000000; + } + } + + W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_P1P2_OFF); + (void)R_REG(osh, &cc->pllcontrol_addr); + tmp = R_REG(osh, &cc->pllcontrol_data); + p1 = (tmp & PMU5_PLL_P1_MASK) >> PMU5_PLL_P1_SHIFT; + p2 = (tmp & PMU5_PLL_P2_MASK) >> PMU5_PLL_P2_SHIFT; + + W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_M14_OFF); + (void)R_REG(osh, &cc->pllcontrol_addr); + tmp = R_REG(osh, &cc->pllcontrol_data); + div = (tmp >> ((m - 1) * PMU5_PLL_MDIV_WIDTH)) & PMU5_PLL_MDIV_MASK; + + W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_NM5_OFF); + (void)R_REG(osh, &cc->pllcontrol_addr); + tmp = R_REG(osh, &cc->pllcontrol_data); + ndiv = (tmp & PMU5_PLL_NDIV_MASK) >> PMU5_PLL_NDIV_SHIFT; + + /* Do calculation in Mhz */ + fc = si_pmu_alp_clock(sih, osh) / 1000000; + fc = (p1 * ndiv * fc) / p2; + + PMU_NONE(("%s: p1=%d, p2=%d, ndiv=%d(0x%x), m%d=%d; fc=%d, clock=%d\n", + __func__, p1, p2, ndiv, ndiv, m, div, fc, fc / div)); + + /* Return clock in Hertz */ + return (fc / div) * 1000000; +} + +/* query backplane clock frequency */ +/* For designs that feed the same clock to both backplane + * and CPU just return the CPU clock speed. + */ +u32 si_pmu_si_clock(si_t *sih, osl_t *osh) +{ + chipcregs_t *cc; + uint origidx; + u32 clock = HT_CLOCK; +#ifdef BCMDBG + char chn[8]; +#endif + + ASSERT(sih->cccaps & CC_CAP_PMU); + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + switch (CHIPID(sih->chip)) { + case BCM43224_CHIP_ID: + case BCM43225_CHIP_ID: + case BCM43421_CHIP_ID: + case BCM4331_CHIP_ID: + case BCM6362_CHIP_ID: + /* 96MHz backplane clock */ + clock = 96000 * 1000; + break; + case BCM4716_CHIP_ID: + case BCM4748_CHIP_ID: + case BCM47162_CHIP_ID: + clock = + si_pmu5_clock(sih, osh, cc, PMU4716_MAINPLL_PLL0, + PMU5_MAINPLL_SI); + break; + case BCM4329_CHIP_ID: + if (CHIPREV(sih->chiprev) == 0) + clock = 38400 * 1000; + else + clock = si_pmu1_cpuclk0(sih, osh, cc); + break; + case BCM4319_CHIP_ID: + case BCM4336_CHIP_ID: + case BCM4330_CHIP_ID: + clock = si_pmu1_cpuclk0(sih, osh, cc); + break; + case BCM4313_CHIP_ID: + /* 80MHz backplane clock */ + clock = 80000 * 1000; + break; + case BCM43235_CHIP_ID: + case BCM43236_CHIP_ID: + case BCM43238_CHIP_ID: + clock = + (cc->chipstatus & CST43236_BP_CLK) ? (120000 * + 1000) : (96000 * + 1000); + break; + case BCM5356_CHIP_ID: + clock = + si_pmu5_clock(sih, osh, cc, PMU5356_MAINPLL_PLL0, + PMU5_MAINPLL_SI); + break; + case BCM5357_CHIP_ID: + clock = + si_pmu5_clock(sih, osh, cc, PMU5357_MAINPLL_PLL0, + PMU5_MAINPLL_SI); + break; + default: + PMU_MSG(("No backplane clock specified " + "for chip %s rev %d pmurev %d, using default %d Hz\n", + bcm_chipname(sih->chip, chn, 8), sih->chiprev, + sih->pmurev, clock)); + break; + } + + /* Return to original core */ + si_setcoreidx(sih, origidx); + return clock; +} + +/* query CPU clock frequency */ +u32 si_pmu_cpu_clock(si_t *sih, osl_t *osh) +{ + chipcregs_t *cc; + uint origidx; + u32 clock; + + ASSERT(sih->cccaps & CC_CAP_PMU); + + if ((sih->pmurev >= 5) && + !((CHIPID(sih->chip) == BCM4329_CHIP_ID) || + (CHIPID(sih->chip) == BCM4319_CHIP_ID) || + (CHIPID(sih->chip) == BCM43236_CHIP_ID) || + (CHIPID(sih->chip) == BCM4336_CHIP_ID) || + (CHIPID(sih->chip) == BCM4330_CHIP_ID))) { + uint pll; + + switch (CHIPID(sih->chip)) { + case BCM5356_CHIP_ID: + pll = PMU5356_MAINPLL_PLL0; + break; + case BCM5357_CHIP_ID: + pll = PMU5357_MAINPLL_PLL0; + break; + default: + pll = PMU4716_MAINPLL_PLL0; + break; + } + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_CPU); + + /* Return to original core */ + si_setcoreidx(sih, origidx); + } else + clock = si_pmu_si_clock(sih, osh); + + return clock; +} + +/* query memory clock frequency */ +u32 si_pmu_mem_clock(si_t *sih, osl_t *osh) +{ + chipcregs_t *cc; + uint origidx; + u32 clock; + + ASSERT(sih->cccaps & CC_CAP_PMU); + + if ((sih->pmurev >= 5) && + !((CHIPID(sih->chip) == BCM4329_CHIP_ID) || + (CHIPID(sih->chip) == BCM4319_CHIP_ID) || + (CHIPID(sih->chip) == BCM4330_CHIP_ID) || + (CHIPID(sih->chip) == BCM4336_CHIP_ID) || + (CHIPID(sih->chip) == BCM43236_CHIP_ID))) { + uint pll; + + switch (CHIPID(sih->chip)) { + case BCM5356_CHIP_ID: + pll = PMU5356_MAINPLL_PLL0; + break; + case BCM5357_CHIP_ID: + pll = PMU5357_MAINPLL_PLL0; + break; + default: + pll = PMU4716_MAINPLL_PLL0; + break; + } + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_MEM); + + /* Return to original core */ + si_setcoreidx(sih, origidx); + } else { + clock = si_pmu_si_clock(sih, osh); + } + + return clock; +} + +/* Measure ILP clock frequency */ +#define ILP_CALC_DUR 10 /* ms, make sure 1000 can be divided by it. */ + +static u32 ilpcycles_per_sec; + +u32 si_pmu_ilp_clock(si_t *sih, osl_t *osh) +{ + if (ISSIM_ENAB(sih)) + return ILP_CLOCK; + + if (ilpcycles_per_sec == 0) { + u32 start, end, delta; + u32 origidx = si_coreidx(sih); + chipcregs_t *cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + start = R_REG(osh, &cc->pmutimer); + mdelay(ILP_CALC_DUR); + end = R_REG(osh, &cc->pmutimer); + delta = end - start; + ilpcycles_per_sec = delta * (1000 / ILP_CALC_DUR); + si_setcoreidx(sih, origidx); + } + + return ilpcycles_per_sec; +} + +/* SDIO Pad drive strength to select value mappings */ +typedef struct { + u8 strength; /* Pad Drive Strength in mA */ + u8 sel; /* Chip-specific select value */ +} sdiod_drive_str_t; + +/* SDIO Drive Strength to sel value table for PMU Rev 1 */ +static const sdiod_drive_str_t sdiod_drive_strength_tab1[] = { + { + 4, 0x2}, { + 2, 0x3}, { + 1, 0x0}, { + 0, 0x0} + }; + +/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */ +static const sdiod_drive_str_t sdiod_drive_strength_tab2[] = { + { + 12, 0x7}, { + 10, 0x6}, { + 8, 0x5}, { + 6, 0x4}, { + 4, 0x2}, { + 2, 0x1}, { + 0, 0x0} + }; + +/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */ +static const sdiod_drive_str_t sdiod_drive_strength_tab3[] = { + { + 32, 0x7}, { + 26, 0x6}, { + 22, 0x5}, { + 16, 0x4}, { + 12, 0x3}, { + 8, 0x2}, { + 4, 0x1}, { + 0, 0x0} + }; + +#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) + +void +si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, + u32 drivestrength) { + chipcregs_t *cc; + uint origidx, intr_val = 0; + sdiod_drive_str_t *str_tab = NULL; + u32 str_mask = 0; + u32 str_shift = 0; +#ifdef BCMDBG + char chn[8]; +#endif + + if (!(sih->cccaps & CC_CAP_PMU)) { + return; + } + + /* Remember original core before switch to chipc */ + cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx, + &intr_val); + + switch (SDIOD_DRVSTR_KEY(sih->chip, sih->pmurev)) { + case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1): + str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab1; + str_mask = 0x30000000; + str_shift = 28; + break; + case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2): + case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3): + str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab2; + str_mask = 0x00003800; + str_shift = 11; + break; + case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8): + str_tab = (sdiod_drive_str_t *) &sdiod_drive_strength_tab3; + str_mask = 0x00003800; + str_shift = 11; + break; + + default: + PMU_MSG(("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n", bcm_chipname(sih->chip, chn, 8), sih->chiprev, sih->pmurev)); + + break; + } + + if (str_tab != NULL) { + u32 drivestrength_sel = 0; + u32 cc_data_temp; + int i; + + for (i = 0; str_tab[i].strength != 0; i++) { + if (drivestrength >= str_tab[i].strength) { + drivestrength_sel = str_tab[i].sel; + break; + } + } + + W_REG(osh, &cc->chipcontrol_addr, 1); + cc_data_temp = R_REG(osh, &cc->chipcontrol_data); + cc_data_temp &= ~str_mask; + drivestrength_sel <<= str_shift; + cc_data_temp |= drivestrength_sel; + W_REG(osh, &cc->chipcontrol_data, cc_data_temp); + + PMU_MSG(("SDIO: %dmA drive strength selected, set to 0x%08x\n", + drivestrength, cc_data_temp)); + } + + /* Return to original core */ + si_restore_core(sih, origidx, intr_val); +} + +/* initialize PMU */ +void si_pmu_init(si_t *sih, osl_t *osh) +{ + chipcregs_t *cc; + uint origidx; + + ASSERT(sih->cccaps & CC_CAP_PMU); + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + if (sih->pmurev == 1) + AND_REG(osh, &cc->pmucontrol, ~PCTL_NOILP_ON_WAIT); + else if (sih->pmurev >= 2) + OR_REG(osh, &cc->pmucontrol, PCTL_NOILP_ON_WAIT); + + if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) && (sih->chiprev == 2)) { + /* Fix for 4329b0 bad LPOM state. */ + W_REG(osh, &cc->regcontrol_addr, 2); + OR_REG(osh, &cc->regcontrol_data, 0x100); + + W_REG(osh, &cc->regcontrol_addr, 3); + OR_REG(osh, &cc->regcontrol_data, 0x4); + } + + /* Return to original core */ + si_setcoreidx(sih, origidx); +} + +/* Return up time in ILP cycles for the given resource. */ +static uint +si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc, + u8 rsrc) { + u32 deps; + uint up, i, dup, dmax; + u32 min_mask = 0, max_mask = 0; + + /* uptime of resource 'rsrc' */ + W_REG(osh, &cc->res_table_sel, rsrc); + up = (R_REG(osh, &cc->res_updn_timer) >> 8) & 0xff; + + /* direct dependancies of resource 'rsrc' */ + deps = si_pmu_res_deps(sih, osh, cc, PMURES_BIT(rsrc), false); + for (i = 0; i <= PMURES_MAX_RESNUM; i++) { + if (!(deps & PMURES_BIT(i))) + continue; + deps &= ~si_pmu_res_deps(sih, osh, cc, PMURES_BIT(i), true); + } + si_pmu_res_masks(sih, &min_mask, &max_mask); + deps &= ~min_mask; + + /* max uptime of direct dependancies */ + dmax = 0; + for (i = 0; i <= PMURES_MAX_RESNUM; i++) { + if (!(deps & PMURES_BIT(i))) + continue; + dup = si_pmu_res_uptime(sih, osh, cc, (u8) i); + if (dmax < dup) + dmax = dup; + } + + PMU_MSG(("si_pmu_res_uptime: rsrc %u uptime %u(deps 0x%08x uptime %u)\n", rsrc, up, deps, dmax)); + + return up + dmax + PMURES_UP_TRANSITION; +} + +/* Return dependancies (direct or all/indirect) for the given resources */ +static u32 +si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 rsrcs, + bool all) +{ + u32 deps = 0; + u32 i; + + for (i = 0; i <= PMURES_MAX_RESNUM; i++) { + if (!(rsrcs & PMURES_BIT(i))) + continue; + W_REG(osh, &cc->res_table_sel, i); + deps |= R_REG(osh, &cc->res_dep_mask); + } + + return !all ? deps : (deps + ? (deps | + si_pmu_res_deps(sih, osh, cc, deps, + true)) : 0); +} + +/* power up/down OTP through PMU resources */ +void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on) +{ + chipcregs_t *cc; + uint origidx; + u32 rsrcs = 0; /* rsrcs to turn on/off OTP power */ + + ASSERT(sih->cccaps & CC_CAP_PMU); + + /* Don't do anything if OTP is disabled */ + if (si_is_otp_disabled(sih)) { + PMU_MSG(("si_pmu_otp_power: OTP is disabled\n")); + return; + } + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + switch (CHIPID(sih->chip)) { + case BCM4329_CHIP_ID: + rsrcs = PMURES_BIT(RES4329_OTP_PU); + break; + case BCM4319_CHIP_ID: + rsrcs = PMURES_BIT(RES4319_OTP_PU); + break; + case BCM4336_CHIP_ID: + rsrcs = PMURES_BIT(RES4336_OTP_PU); + break; + case BCM4330_CHIP_ID: + rsrcs = PMURES_BIT(RES4330_OTP_PU); + break; + default: + break; + } + + if (rsrcs != 0) { + u32 otps; + + /* Figure out the dependancies (exclude min_res_mask) */ + u32 deps = si_pmu_res_deps(sih, osh, cc, rsrcs, true); + u32 min_mask = 0, max_mask = 0; + si_pmu_res_masks(sih, &min_mask, &max_mask); + deps &= ~min_mask; + /* Turn on/off the power */ + if (on) { + PMU_MSG(("Adding rsrc 0x%x to min_res_mask\n", + rsrcs | deps)); + OR_REG(osh, &cc->min_res_mask, (rsrcs | deps)); + SPINWAIT(!(R_REG(osh, &cc->res_state) & rsrcs), + PMU_MAX_TRANSITION_DLY); + ASSERT(R_REG(osh, &cc->res_state) & rsrcs); + } else { + PMU_MSG(("Removing rsrc 0x%x from min_res_mask\n", + rsrcs | deps)); + AND_REG(osh, &cc->min_res_mask, ~(rsrcs | deps)); + } + + SPINWAIT((((otps = R_REG(osh, &cc->otpstatus)) & OTPS_READY) != + (on ? OTPS_READY : 0)), 100); + ASSERT((otps & OTPS_READY) == (on ? OTPS_READY : 0)); + if ((otps & OTPS_READY) != (on ? OTPS_READY : 0)) + PMU_MSG(("OTP ready bit not %s after wait\n", + (on ? "ON" : "OFF"))); + } + + /* Return to original core */ + si_setcoreidx(sih, origidx); +} + +void si_pmu_rcal(si_t *sih, osl_t *osh) +{ + chipcregs_t *cc; + uint origidx; + + ASSERT(sih->cccaps & CC_CAP_PMU); + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + switch (CHIPID(sih->chip)) { + case BCM4329_CHIP_ID:{ + u8 rcal_code; + u32 val; + + /* Kick RCal */ + W_REG(osh, &cc->chipcontrol_addr, 1); + + /* Power Down RCAL Block */ + AND_REG(osh, &cc->chipcontrol_data, ~0x04); + + /* Power Up RCAL block */ + OR_REG(osh, &cc->chipcontrol_data, 0x04); + + /* Wait for completion */ + SPINWAIT(0 == (R_REG(osh, &cc->chipstatus) & 0x08), + 10 * 1000 * 1000); + ASSERT(R_REG(osh, &cc->chipstatus) & 0x08); + + /* Drop the LSB to convert from 5 bit code to 4 bit code */ + rcal_code = + (u8) (R_REG(osh, &cc->chipstatus) >> 5) & 0x0f; + + PMU_MSG(("RCal completed, status 0x%x, code 0x%x\n", + R_REG(osh, &cc->chipstatus), rcal_code)); + + /* Write RCal code into pmu_vreg_ctrl[32:29] */ + W_REG(osh, &cc->regcontrol_addr, 0); + val = + R_REG(osh, + &cc-> + regcontrol_data) & ~((u32) 0x07 << 29); + val |= (u32) (rcal_code & 0x07) << 29; + W_REG(osh, &cc->regcontrol_data, val); + W_REG(osh, &cc->regcontrol_addr, 1); + val = R_REG(osh, &cc->regcontrol_data) & ~(u32) 0x01; + val |= (u32) ((rcal_code >> 3) & 0x01); + W_REG(osh, &cc->regcontrol_data, val); + + /* Write RCal code into pmu_chip_ctrl[33:30] */ + W_REG(osh, &cc->chipcontrol_addr, 0); + val = + R_REG(osh, + &cc-> + chipcontrol_data) & ~((u32) 0x03 << 30); + val |= (u32) (rcal_code & 0x03) << 30; + W_REG(osh, &cc->chipcontrol_data, val); + W_REG(osh, &cc->chipcontrol_addr, 1); + val = + R_REG(osh, &cc->chipcontrol_data) & ~(u32) 0x03; + val |= (u32) ((rcal_code >> 2) & 0x03); + W_REG(osh, &cc->chipcontrol_data, val); + + /* Set override in pmu_chip_ctrl[29] */ + W_REG(osh, &cc->chipcontrol_addr, 0); + OR_REG(osh, &cc->chipcontrol_data, (0x01 << 29)); + + /* Power off RCal block */ + W_REG(osh, &cc->chipcontrol_addr, 1); + AND_REG(osh, &cc->chipcontrol_data, ~0x04); + + break; + } + default: + break; + } + + /* Return to original core */ + si_setcoreidx(sih, origidx); +} + +void si_pmu_spuravoid(si_t *sih, osl_t *osh, u8 spuravoid) +{ + chipcregs_t *cc; + uint origidx, intr_val; + u32 tmp = 0; + + /* Remember original core before switch to chipc */ + cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx, + &intr_val); + ASSERT(cc != NULL); + + /* force the HT off */ + if (CHIPID(sih->chip) == BCM4336_CHIP_ID) { + tmp = R_REG(osh, &cc->max_res_mask); + tmp &= ~RES4336_HT_AVAIL; + W_REG(osh, &cc->max_res_mask, tmp); + /* wait for the ht to really go away */ + SPINWAIT(((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) == 0), + 10000); + ASSERT((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) == 0); + } + + /* update the pll changes */ + si_pmu_spuravoid_pllupdate(sih, cc, osh, spuravoid); + + /* enable HT back on */ + if (CHIPID(sih->chip) == BCM4336_CHIP_ID) { + tmp = R_REG(osh, &cc->max_res_mask); + tmp |= RES4336_HT_AVAIL; + W_REG(osh, &cc->max_res_mask, tmp); + } + + /* Return to original core */ + si_restore_core(sih, origidx, intr_val); +} + +static void +si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh, + u8 spuravoid) +{ + u32 tmp = 0; + u8 phypll_offset = 0; + u8 bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 }; + u8 bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc }; + + switch (CHIPID(sih->chip)) { + case BCM5357_CHIP_ID: + case BCM43235_CHIP_ID: + case BCM43236_CHIP_ID: + case BCM43238_CHIP_ID: + + /* BCM5357 needs to touch PLL1_PLLCTL[02], so offset PLL0_PLLCTL[02] by 6 */ + phypll_offset = (CHIPID(sih->chip) == BCM5357_CHIP_ID) ? 6 : 0; + + /* RMW only the P1 divider */ + W_REG(osh, &cc->pllcontrol_addr, + PMU1_PLL0_PLLCTL0 + phypll_offset); + tmp = R_REG(osh, &cc->pllcontrol_data); + tmp &= (~(PMU1_PLL0_PC0_P1DIV_MASK)); + tmp |= + (bcm5357_bcm43236_p1div[spuravoid] << + PMU1_PLL0_PC0_P1DIV_SHIFT); + W_REG(osh, &cc->pllcontrol_data, tmp); + + /* RMW only the int feedback divider */ + W_REG(osh, &cc->pllcontrol_addr, + PMU1_PLL0_PLLCTL2 + phypll_offset); + tmp = R_REG(osh, &cc->pllcontrol_data); + tmp &= ~(PMU1_PLL0_PC2_NDIV_INT_MASK); + tmp |= + (bcm5357_bcm43236_ndiv[spuravoid]) << + PMU1_PLL0_PC2_NDIV_INT_SHIFT; + W_REG(osh, &cc->pllcontrol_data, tmp); + + tmp = 1 << 10; + break; + + case BCM4331_CHIP_ID: + if (spuravoid == 2) { + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); + W_REG(osh, &cc->pllcontrol_data, 0x11500014); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); + W_REG(osh, &cc->pllcontrol_data, 0x0FC00a08); + } else if (spuravoid == 1) { + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); + W_REG(osh, &cc->pllcontrol_data, 0x11500014); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); + W_REG(osh, &cc->pllcontrol_data, 0x0F600a08); + } else { + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); + W_REG(osh, &cc->pllcontrol_data, 0x11100014); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); + W_REG(osh, &cc->pllcontrol_data, 0x03000a08); + } + tmp = 1 << 10; + break; + + case BCM43224_CHIP_ID: + case BCM43225_CHIP_ID: + case BCM43421_CHIP_ID: + case BCM6362_CHIP_ID: + if (spuravoid == 1) { + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); + W_REG(osh, &cc->pllcontrol_data, 0x11500010); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); + W_REG(osh, &cc->pllcontrol_data, 0x000C0C06); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); + W_REG(osh, &cc->pllcontrol_data, 0x0F600a08); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); + W_REG(osh, &cc->pllcontrol_data, 0x00000000); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); + W_REG(osh, &cc->pllcontrol_data, 0x2001E920); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); + W_REG(osh, &cc->pllcontrol_data, 0x88888815); + } else { + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); + W_REG(osh, &cc->pllcontrol_data, 0x11100010); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); + W_REG(osh, &cc->pllcontrol_data, 0x000c0c06); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); + W_REG(osh, &cc->pllcontrol_data, 0x03000a08); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); + W_REG(osh, &cc->pllcontrol_data, 0x00000000); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); + W_REG(osh, &cc->pllcontrol_data, 0x200005c0); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); + W_REG(osh, &cc->pllcontrol_data, 0x88888815); + } + tmp = 1 << 10; + break; + + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); + W_REG(osh, &cc->pllcontrol_data, 0x11100008); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); + W_REG(osh, &cc->pllcontrol_data, 0x0c000c06); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); + W_REG(osh, &cc->pllcontrol_data, 0x03000a08); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); + W_REG(osh, &cc->pllcontrol_data, 0x00000000); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); + W_REG(osh, &cc->pllcontrol_data, 0x200005c0); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); + W_REG(osh, &cc->pllcontrol_data, 0x88888855); + + tmp = 1 << 10; + break; + + case BCM4716_CHIP_ID: + case BCM4748_CHIP_ID: + case BCM47162_CHIP_ID: + if (spuravoid == 1) { + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); + W_REG(osh, &cc->pllcontrol_data, 0x11500060); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); + W_REG(osh, &cc->pllcontrol_data, 0x080C0C06); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); + W_REG(osh, &cc->pllcontrol_data, 0x0F600000); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); + W_REG(osh, &cc->pllcontrol_data, 0x00000000); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); + W_REG(osh, &cc->pllcontrol_data, 0x2001E924); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); + W_REG(osh, &cc->pllcontrol_data, 0x88888815); + } else { + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); + W_REG(osh, &cc->pllcontrol_data, 0x11100060); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); + W_REG(osh, &cc->pllcontrol_data, 0x080c0c06); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); + W_REG(osh, &cc->pllcontrol_data, 0x03000000); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); + W_REG(osh, &cc->pllcontrol_data, 0x00000000); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); + W_REG(osh, &cc->pllcontrol_data, 0x200005c0); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); + W_REG(osh, &cc->pllcontrol_data, 0x88888815); + } + + tmp = 3 << 9; + break; + + case BCM4319_CHIP_ID: + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); + W_REG(osh, &cc->pllcontrol_data, 0x11100070); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); + W_REG(osh, &cc->pllcontrol_data, 0x1014140a); + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); + W_REG(osh, &cc->pllcontrol_data, 0x88888854); + + if (spuravoid == 1) { /* spur_avoid ON, enable 41/82/164Mhz clock mode */ + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); + W_REG(osh, &cc->pllcontrol_data, 0x05201828); + } else { /* enable 40/80/160Mhz clock mode */ + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); + W_REG(osh, &cc->pllcontrol_data, 0x05001828); + } + break; + case BCM4336_CHIP_ID: + /* Looks like these are only for default xtal freq 26MHz */ + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); + W_REG(osh, &cc->pllcontrol_data, 0x02100020); + + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); + W_REG(osh, &cc->pllcontrol_data, 0x0C0C0C0C); + + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); + W_REG(osh, &cc->pllcontrol_data, 0x01240C0C); + + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); + W_REG(osh, &cc->pllcontrol_data, 0x202C2820); + + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); + W_REG(osh, &cc->pllcontrol_data, 0x88888825); + + W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); + if (spuravoid == 1) { + W_REG(osh, &cc->pllcontrol_data, 0x00EC4EC4); + } else { + W_REG(osh, &cc->pllcontrol_data, 0x00762762); + } + + tmp = PCTL_PLL_PLLCTL_UPD; + break; + + default: + PMU_ERROR(("%s: unknown spuravoidance settings for chip %s, not changing PLL\n", __func__, bcm_chipname(sih->chip, chn, 8))); + break; + } + + tmp |= R_REG(osh, &cc->pmucontrol); + W_REG(osh, &cc->pmucontrol, tmp); +} + +bool si_pmu_is_otp_powered(si_t *sih, osl_t *osh) +{ + uint idx; + chipcregs_t *cc; + bool st; + + /* Remember original core before switch to chipc */ + idx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + switch (CHIPID(sih->chip)) { + case BCM4329_CHIP_ID: + st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4329_OTP_PU)) + != 0; + break; + case BCM4319_CHIP_ID: + st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4319_OTP_PU)) + != 0; + break; + case BCM4336_CHIP_ID: + st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4336_OTP_PU)) + != 0; + break; + case BCM4330_CHIP_ID: + st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4330_OTP_PU)) + != 0; + break; + + /* These chip doesn't use PMU bit to power up/down OTP. OTP always on. + * Use OTP_INIT command to reset/refresh state. + */ + case BCM43224_CHIP_ID: + case BCM43225_CHIP_ID: + case BCM43421_CHIP_ID: + case BCM43236_CHIP_ID: + case BCM43235_CHIP_ID: + case BCM43238_CHIP_ID: + st = true; + break; + default: + st = true; + break; + } + + /* Return to original core */ + si_setcoreidx(sih, idx); + return st; +} + +void +#if defined(BCMDBG) +si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable) +#else +si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable) +#endif +{ + chipcregs_t *cc; + uint origidx; + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + /* Return to original core */ + si_setcoreidx(sih, origidx); +} + +/* initialize PMU chip controls and other chip level stuff */ +void si_pmu_chip_init(si_t *sih, osl_t *osh) +{ + uint origidx; + + ASSERT(sih->cccaps & CC_CAP_PMU); + +#ifdef CHIPC_UART_ALWAYS_ON + si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, clk_ctl_st), + CCS_FORCEALP, CCS_FORCEALP); +#endif /* CHIPC_UART_ALWAYS_ON */ + + /* Gate off SPROM clock and chip select signals */ + si_pmu_sprom_enable(sih, osh, false); + + /* Remember original core */ + origidx = si_coreidx(sih); + + /* Return to original core */ + si_setcoreidx(sih, origidx); +} + +/* initialize PMU switch/regulators */ +void si_pmu_swreg_init(si_t *sih, osl_t *osh) +{ + ASSERT(sih->cccaps & CC_CAP_PMU); + + switch (CHIPID(sih->chip)) { + case BCM4336_CHIP_ID: + /* Reduce CLDO PWM output voltage to 1.2V */ + si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_PWM, 0xe); + /* Reduce CLDO BURST output voltage to 1.2V */ + si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_BURST, + 0xe); + /* Reduce LNLDO1 output voltage to 1.2V */ + si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO1, 0xe); + if (CHIPREV(sih->chiprev) == 0) + si_pmu_regcontrol(sih, 2, 0x400000, 0x400000); + break; + + case BCM4330_CHIP_ID: + /* CBUCK Voltage is 1.8 by default and set that to 1.5 */ + si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, 0); + break; + default: + break; + } +} + +void si_pmu_radio_enable(si_t *sih, bool enable) +{ + ASSERT(sih->cccaps & CC_CAP_PMU); + + switch (CHIPID(sih->chip)) { + case BCM4319_CHIP_ID: + if (enable) + si_write_wrapperreg(sih, AI_OOBSELOUTB74, + (u32) 0x868584); + else + si_write_wrapperreg(sih, AI_OOBSELOUTB74, + (u32) 0x060584); + break; + } +} + +/* Wait for a particular clock level to be on the backplane */ +u32 +si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, u32 clk, + u32 delay) +{ + chipcregs_t *cc; + uint origidx; + + ASSERT(sih->cccaps & CC_CAP_PMU); + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + if (delay) + SPINWAIT(((R_REG(osh, &cc->pmustatus) & clk) != clk), delay); + + /* Return to original core */ + si_setcoreidx(sih, origidx); + + return R_REG(osh, &cc->pmustatus) & clk; +} + +/* + * Measures the ALP clock frequency in KHz. Returns 0 if not possible. + * Possible only if PMU rev >= 10 and there is an external LPO 32768Hz crystal. + */ + +#define EXT_ILP_HZ 32768 + +u32 si_pmu_measure_alpclk(si_t *sih, osl_t *osh) +{ + chipcregs_t *cc; + uint origidx; + u32 alp_khz; + + if (sih->pmurev < 10) + return 0; + + ASSERT(sih->cccaps & CC_CAP_PMU); + + /* Remember original core before switch to chipc */ + origidx = si_coreidx(sih); + cc = si_setcoreidx(sih, SI_CC_IDX); + ASSERT(cc != NULL); + + if (R_REG(osh, &cc->pmustatus) & PST_EXTLPOAVAIL) { + u32 ilp_ctr, alp_hz; + + /* Enable the reg to measure the freq, in case disabled before */ + W_REG(osh, &cc->pmu_xtalfreq, + 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT); + + /* Delay for well over 4 ILP clocks */ + udelay(1000); + + /* Read the latched number of ALP ticks per 4 ILP ticks */ + ilp_ctr = + R_REG(osh, + &cc->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK; + + /* Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT bit to save power */ + W_REG(osh, &cc->pmu_xtalfreq, 0); + + /* Calculate ALP frequency */ + alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4; + + /* Round to nearest 100KHz, and at the same time convert to KHz */ + alp_khz = (alp_hz + 50000) / 100000 * 100; + } else + alp_khz = 0; + + /* Return to original core */ + si_setcoreidx(sih, origidx); + + return alp_khz; +} + +static void si_pmu_set_4330_plldivs(si_t *sih) +{ + u32 FVCO = si_pmu1_pllfvco0(sih) / 1000; + u32 m1div, m2div, m3div, m4div, m5div, m6div; + u32 pllc1, pllc2; + + m2div = m3div = m4div = m6div = FVCO / 80; + m5div = FVCO / 160; + + if (CST4330_CHIPMODE_SDIOD(sih->chipst)) + m1div = FVCO / 80; + else + m1div = FVCO / 90; + pllc1 = + (m1div << PMU1_PLL0_PC1_M1DIV_SHIFT) | (m2div << + PMU1_PLL0_PC1_M2DIV_SHIFT) | + (m3div << PMU1_PLL0_PC1_M3DIV_SHIFT) | (m4div << + PMU1_PLL0_PC1_M4DIV_SHIFT); + si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, ~0, pllc1); + + pllc2 = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0); + pllc2 &= ~(PMU1_PLL0_PC2_M5DIV_MASK | PMU1_PLL0_PC2_M6DIV_MASK); + pllc2 |= + ((m5div << PMU1_PLL0_PC2_M5DIV_SHIFT) | + (m6div << PMU1_PLL0_PC2_M6DIV_SHIFT)); + si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2, ~0, pllc2); +} diff --git a/drivers/staging/brcm80211/util/linux_osl.c b/drivers/staging/brcm80211/util/linux_osl.c new file mode 100644 index 0000000..2bb5b87 --- /dev/null +++ b/drivers/staging/brcm80211/util/linux_osl.c @@ -0,0 +1,424 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <linux/delay.h> +#include <linux/fs.h> +#ifdef mips +#include <asm/paccess.h> +#endif /* mips */ +#include <bcmendian.h> +#include <linuxver.h> +#include <bcmdefs.h> +#include <osl.h> +#include <bcmutils.h> +#include <pcicfg.h> + + +#define PCI_CFG_RETRY 10 + +#define OS_HANDLE_MAGIC 0x1234abcd /* Magic # to recognise osh */ +#define BCM_MEM_FILENAME_LEN 24 /* Mem. filename length */ + +struct osl_info { + osl_pubinfo_t pub; + uint magic; + void *pdev; + uint failed; + uint bustype; +}; + +/* Global ASSERT type flag */ +u32 g_assert_type; + +#ifdef BRCM_FULLMAC +static s16 linuxbcmerrormap[] = { 0, /* 0 */ + -EINVAL, /* BCME_ERROR */ + -EINVAL, /* BCME_BADARG */ + -EINVAL, /* BCME_BADOPTION */ + -EINVAL, /* BCME_NOTUP */ + -EINVAL, /* BCME_NOTDOWN */ + -EINVAL, /* BCME_NOTAP */ + -EINVAL, /* BCME_NOTSTA */ + -EINVAL, /* BCME_BADKEYIDX */ + -EINVAL, /* BCME_RADIOOFF */ + -EINVAL, /* BCME_NOTBANDLOCKED */ + -EINVAL, /* BCME_NOCLK */ + -EINVAL, /* BCME_BADRATESET */ + -EINVAL, /* BCME_BADBAND */ + -E2BIG, /* BCME_BUFTOOSHORT */ + -E2BIG, /* BCME_BUFTOOLONG */ + -EBUSY, /* BCME_BUSY */ + -EINVAL, /* BCME_NOTASSOCIATED */ + -EINVAL, /* BCME_BADSSIDLEN */ + -EINVAL, /* BCME_OUTOFRANGECHAN */ + -EINVAL, /* BCME_BADCHAN */ + -EFAULT, /* BCME_BADADDR */ + -ENOMEM, /* BCME_NORESOURCE */ + -EOPNOTSUPP, /* BCME_UNSUPPORTED */ + -EMSGSIZE, /* BCME_BADLENGTH */ + -EINVAL, /* BCME_NOTREADY */ + -EPERM, /* BCME_NOTPERMITTED */ + -ENOMEM, /* BCME_NOMEM */ + -EINVAL, /* BCME_ASSOCIATED */ + -ERANGE, /* BCME_RANGE */ + -EINVAL, /* BCME_NOTFOUND */ + -EINVAL, /* BCME_WME_NOT_ENABLED */ + -EINVAL, /* BCME_TSPEC_NOTFOUND */ + -EINVAL, /* BCME_ACM_NOTSUPPORTED */ + -EINVAL, /* BCME_NOT_WME_ASSOCIATION */ + -EIO, /* BCME_SDIO_ERROR */ + -ENODEV, /* BCME_DONGLE_DOWN */ + -EINVAL, /* BCME_VERSION */ + -EIO, /* BCME_TXFAIL */ + -EIO, /* BCME_RXFAIL */ + -EINVAL, /* BCME_NODEVICE */ + -EINVAL, /* BCME_NMODE_DISABLED */ + -ENODATA, /* BCME_NONRESIDENT */ + +/* When an new error code is added to bcmutils.h, add os + * spcecific error translation here as well + */ +/* check if BCME_LAST changed since the last time this function was updated */ +#if BCME_LAST != -42 +#error "You need to add a OS error translation in the linuxbcmerrormap \ + for new error code defined in bcmutils.h" +#endif +}; + +/* translate bcmerrors into linux errors */ +int osl_error(int bcmerror) +{ + if (bcmerror > 0) + bcmerror = 0; + else if (bcmerror < BCME_LAST) + bcmerror = BCME_ERROR; + + /* Array bounds covered by ASSERT in osl_attach */ + return linuxbcmerrormap[-bcmerror]; +} +#endif /* BRCM_FULLMAC */ + +osl_t *osl_attach(void *pdev, uint bustype, bool pkttag) +{ + osl_t *osh; + + osh = kmalloc(sizeof(osl_t), GFP_ATOMIC); + ASSERT(osh); + + bzero(osh, sizeof(osl_t)); + +#ifdef BRCM_FULLMAC + /* Check that error map has the right number of entries in it */ + ASSERT(ABS(BCME_LAST) == (ARRAY_SIZE(linuxbcmerrormap) - 1)); +#endif /* BRCM_FULLMAC */ + + osh->magic = OS_HANDLE_MAGIC; + osh->failed = 0; + osh->pdev = pdev; + osh->pub.pkttag = pkttag; + osh->bustype = bustype; + + switch (bustype) { + case PCI_BUS: + case SI_BUS: + case PCMCIA_BUS: + osh->pub.mmbus = true; + break; + case JTAG_BUS: + case SDIO_BUS: + case USB_BUS: + case SPI_BUS: + case RPC_BUS: + osh->pub.mmbus = false; + break; + default: + ASSERT(false); + break; + } + +#if defined(BCMDBG) && !defined(BRCM_FULLMAC) + if (pkttag) { + struct sk_buff *skb; + ASSERT(OSL_PKTTAG_SZ <= sizeof(skb->cb)); + } +#endif + return osh; +} + +void osl_detach(osl_t *osh) +{ + if (osh == NULL) + return; + + ASSERT(osh->magic == OS_HANDLE_MAGIC); + kfree(osh); +} + +/* Return a new packet. zero out pkttag */ +void *BCMFASTPATH osl_pktget(osl_t *osh, uint len) +{ + struct sk_buff *skb; + + skb = dev_alloc_skb(len); + if (skb) { + skb_put(skb, len); + skb->priority = 0; + + osh->pub.pktalloced++; + } + + return (void *)skb; +} + +/* Free the driver packet. Free the tag if present */ +void BCMFASTPATH osl_pktfree(osl_t *osh, void *p, bool send) +{ + struct sk_buff *skb, *nskb; + int nest = 0; + + skb = (struct sk_buff *)p; + ASSERT(skb); + + if (send && osh->pub.tx_fn) + osh->pub.tx_fn(osh->pub.tx_ctx, p, 0); + + /* perversion: we use skb->next to chain multi-skb packets */ + while (skb) { + nskb = skb->next; + skb->next = NULL; + + if (skb->destructor) + /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if + * destructor exists + */ + dev_kfree_skb_any(skb); + else + /* can free immediately (even in_irq()) if destructor + * does not exist + */ + dev_kfree_skb(skb); + + osh->pub.pktalloced--; + nest++; + skb = nskb; + } +} + +u32 osl_pci_read_config(osl_t *osh, uint offset, uint size) +{ + uint val = 0; + uint retry = PCI_CFG_RETRY; + + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC))); + + /* only 4byte access supported */ + ASSERT(size == 4); + + do { + pci_read_config_dword(osh->pdev, offset, &val); + if (val != 0xffffffff) + break; + } while (retry--); + +#ifdef BCMDBG + if (retry < PCI_CFG_RETRY) + printk("PCI CONFIG READ access to %d required %d retries\n", + offset, (PCI_CFG_RETRY - retry)); +#endif /* BCMDBG */ + + return val; +} + +void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val) +{ + uint retry = PCI_CFG_RETRY; + + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC))); + + /* only 4byte access supported */ + ASSERT(size == 4); + + do { + pci_write_config_dword(osh->pdev, offset, val); + if (offset != PCI_BAR0_WIN) + break; + if (osl_pci_read_config(osh, offset, size) == val) + break; + } while (retry--); + +#if defined(BCMDBG) && !defined(BRCM_FULLMAC) + if (retry < PCI_CFG_RETRY) + printk("PCI CONFIG WRITE access to %d required %d retries\n", + offset, (PCI_CFG_RETRY - retry)); +#endif /* BCMDBG */ +} + +/* return bus # for the pci device pointed by osh->pdev */ +uint osl_pci_bus(osl_t *osh) +{ + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev); + + return ((struct pci_dev *)osh->pdev)->bus->number; +} + +/* return slot # for the pci device pointed by osh->pdev */ +uint osl_pci_slot(osl_t *osh) +{ + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev); + + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn); +} + +uint osl_dma_consistent_align(void) +{ + return PAGE_SIZE; +} + +void *osl_dma_alloc_consistent(osl_t *osh, uint size, u16 align_bits, + uint *alloced, unsigned long *pap) +{ + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC))); + + if (align_bits) { + u16 align = (1 << align_bits); + if (!IS_ALIGNED(DMA_CONSISTENT_ALIGN, align)) + size += align; + *alloced = size; + } + return pci_alloc_consistent(osh->pdev, size, (dma_addr_t *) pap); +} + +void osl_dma_free_consistent(osl_t *osh, void *va, uint size, unsigned long pa) +{ + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC))); + + pci_free_consistent(osh->pdev, size, va, (dma_addr_t) pa); +} + +uint BCMFASTPATH osl_dma_map(osl_t *osh, void *va, uint size, int direction) +{ + int dir; + + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC))); + dir = (direction == DMA_TX) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE; + return pci_map_single(osh->pdev, va, size, dir); +} + +void BCMFASTPATH osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction) +{ + int dir; + + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC))); + dir = (direction == DMA_TX) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE; + pci_unmap_single(osh->pdev, (u32) pa, size, dir); +} + +#if defined(BCMDBG_ASSERT) +void osl_assert(char *exp, char *file, int line) +{ + char tempbuf[256]; + char *basename; + + basename = strrchr(file, '/'); + /* skip the '/' */ + if (basename) + basename++; + + if (!basename) + basename = file; + +#ifdef BCMDBG_ASSERT + snprintf(tempbuf, 256, + "assertion \"%s\" failed: file \"%s\", line %d\n", exp, + basename, line); + + /* Print assert message and give it time to be written to /var/log/messages */ + if (!in_interrupt()) { + const int delay = 3; + printk(KERN_ERR "%s", tempbuf); + printk(KERN_ERR "panic in %d seconds\n", delay); + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(delay * HZ); + } + + switch (g_assert_type) { + case 0: + panic(KERN_ERR "%s", tempbuf); + break; + case 1: + printk(KERN_ERR "%s", tempbuf); + BUG(); + break; + case 2: + printk(KERN_ERR "%s", tempbuf); + break; + default: + break; + } +#endif /* BCMDBG_ASSERT */ + +} +#endif /* defined(BCMDBG_ASSERT) */ + +#if defined(BCMSDIO) && !defined(BRCM_FULLMAC) +u8 osl_readb(osl_t *osh, volatile u8 *r) +{ + osl_rreg_fn_t rreg = ((osl_pubinfo_t *) osh)->rreg_fn; + void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx; + + return (u8) ((rreg) (ctx, (void *)r, sizeof(u8))); +} + +u16 osl_readw(osl_t *osh, volatile u16 *r) +{ + osl_rreg_fn_t rreg = ((osl_pubinfo_t *) osh)->rreg_fn; + void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx; + + return (u16) ((rreg) (ctx, (void *)r, sizeof(u16))); +} + +u32 osl_readl(osl_t *osh, volatile u32 *r) +{ + osl_rreg_fn_t rreg = ((osl_pubinfo_t *) osh)->rreg_fn; + void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx; + + return (u32) ((rreg) (ctx, (void *)r, sizeof(u32))); +} + +void osl_writeb(osl_t *osh, volatile u8 *r, u8 v) +{ + osl_wreg_fn_t wreg = ((osl_pubinfo_t *) osh)->wreg_fn; + void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx; + + ((wreg) (ctx, (void *)r, v, sizeof(u8))); +} + +void osl_writew(osl_t *osh, volatile u16 *r, u16 v) +{ + osl_wreg_fn_t wreg = ((osl_pubinfo_t *) osh)->wreg_fn; + void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx; + + ((wreg) (ctx, (void *)r, v, sizeof(u16))); +} + +void osl_writel(osl_t *osh, volatile u32 *r, u32 v) +{ + osl_wreg_fn_t wreg = ((osl_pubinfo_t *) osh)->wreg_fn; + void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx; + + ((wreg) (ctx, (void *)r, v, sizeof(u32))); +} +#endif /* BCMSDIO */ diff --git a/drivers/staging/brcm80211/util/nicpci.c b/drivers/staging/brcm80211/util/nicpci.c new file mode 100644 index 0000000..23f86dd --- /dev/null +++ b/drivers/staging/brcm80211/util/nicpci.c @@ -0,0 +1,881 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <linux/string.h> +#include <linuxver.h> +#include <bcmdefs.h> +#include <osl.h> +#include <bcmutils.h> +#include <siutils.h> +#include <hndsoc.h> +#include <bcmdevs.h> +#include <sbchipc.h> +#include <pci_core.h> +#include <pcie_core.h> +#include <nicpci.h> +#include <pcicfg.h> + +typedef struct { + union { + sbpcieregs_t *pcieregs; + struct sbpciregs *pciregs; + } regs; /* Memory mapped register to the core */ + + si_t *sih; /* System interconnect handle */ + osl_t *osh; /* OSL handle */ + u8 pciecap_lcreg_offset; /* PCIE capability LCreg offset in the config space */ + bool pcie_pr42767; + u8 pcie_polarity; + u8 pcie_war_aspm_ovr; /* Override ASPM/Clkreq settings */ + + u8 pmecap_offset; /* PM Capability offset in the config space */ + bool pmecap; /* Capable of generating PME */ +} pcicore_info_t; + +/* debug/trace */ +#define PCI_ERROR(args) +#define PCIE_PUB(sih) ((BUSTYPE((sih)->bustype) == PCI_BUS) && ((sih)->buscoretype == PCIE_CORE_ID)) + +/* routines to access mdio slave device registers */ +static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk); +static int pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, + bool write, uint *val); +static int pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint readdr, + uint val); +static int pcie_mdioread(pcicore_info_t *pi, uint physmedia, uint readdr, + uint *ret_val); + +static void pcie_extendL1timer(pcicore_info_t *pi, bool extend); +static void pcie_clkreq_upd(pcicore_info_t *pi, uint state); + +static void pcie_war_aspm_clkreq(pcicore_info_t *pi); +static void pcie_war_serdes(pcicore_info_t *pi); +static void pcie_war_noplldown(pcicore_info_t *pi); +static void pcie_war_polarity(pcicore_info_t *pi); +static void pcie_war_pci_setup(pcicore_info_t *pi); + +static bool pcicore_pmecap(pcicore_info_t *pi); + +#define PCIE_ASPM(sih) ((PCIE_PUB(sih)) && (((sih)->buscorerev >= 3) && ((sih)->buscorerev <= 5))) + +#define DWORD_ALIGN(x) (x & ~(0x03)) +#define BYTE_POS(x) (x & 0x3) +#define WORD_POS(x) (x & 0x1) + +#define BYTE_SHIFT(x) (8 * BYTE_POS(x)) +#define WORD_SHIFT(x) (16 * WORD_POS(x)) + +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF) +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF) + +#define read_pci_cfg_byte(a) \ + (BYTE_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xff) + +#define read_pci_cfg_word(a) \ + (WORD_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xffff) + +#define write_pci_cfg_byte(a, val) do { \ + u32 tmpval; \ + tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFF << BYTE_POS(a)) | \ + val << BYTE_POS(a); \ + OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \ + } while (0) + +#define write_pci_cfg_word(a, val) do { \ + u32 tmpval; \ + tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFFFF << WORD_POS(a)) | \ + val << WORD_POS(a); \ + OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \ + } while (0) + +/* delay needed between the mdio control/ mdiodata register data access */ +#define PR28829_DELAY() udelay(10) + +/* Initialize the PCI core. It's caller's responsibility to make sure that this is done + * only once + */ +void *pcicore_init(si_t *sih, osl_t *osh, void *regs) +{ + pcicore_info_t *pi; + + ASSERT(sih->bustype == PCI_BUS); + + /* alloc pcicore_info_t */ + pi = kzalloc(sizeof(pcicore_info_t), GFP_ATOMIC); + if (pi == NULL) { + PCI_ERROR(("pci_attach: malloc failed!\n")); + return NULL; + } + + pi->sih = sih; + pi->osh = osh; + + if (sih->buscoretype == PCIE_CORE_ID) { + u8 cap_ptr; + pi->regs.pcieregs = (sbpcieregs_t *) regs; + cap_ptr = + pcicore_find_pci_capability(pi->osh, PCI_CAP_PCIECAP_ID, + NULL, NULL); + ASSERT(cap_ptr); + pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET; + } else + pi->regs.pciregs = (struct sbpciregs *) regs; + + return pi; +} + +void pcicore_deinit(void *pch) +{ + pcicore_info_t *pi = (pcicore_info_t *) pch; + + if (pi == NULL) + return; + kfree(pi); +} + +/* return cap_offset if requested capability exists in the PCI config space */ +/* Note that it's caller's responsibility to make sure it's a pci bus */ +u8 +pcicore_find_pci_capability(osl_t *osh, u8 req_cap_id, unsigned char *buf, + u32 *buflen) +{ + u8 cap_id; + u8 cap_ptr = 0; + u32 bufsize; + u8 byte_val; + + /* check for Header type 0 */ + byte_val = read_pci_cfg_byte(PCI_CFG_HDR); + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL) + goto end; + + /* check if the capability pointer field exists */ + byte_val = read_pci_cfg_byte(PCI_CFG_STAT); + if (!(byte_val & PCI_CAPPTR_PRESENT)) + goto end; + + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR); + /* check if the capability pointer is 0x00 */ + if (cap_ptr == 0x00) + goto end; + + /* loop thr'u the capability list and see if the pcie capabilty exists */ + + cap_id = read_pci_cfg_byte(cap_ptr); + + while (cap_id != req_cap_id) { + cap_ptr = read_pci_cfg_byte((cap_ptr + 1)); + if (cap_ptr == 0x00) + break; + cap_id = read_pci_cfg_byte(cap_ptr); + } + if (cap_id != req_cap_id) { + goto end; + } + /* found the caller requested capability */ + if ((buf != NULL) && (buflen != NULL)) { + u8 cap_data; + + bufsize = *buflen; + if (!bufsize) + goto end; + *buflen = 0; + /* copy the cpability data excluding cap ID and next ptr */ + cap_data = cap_ptr + 2; + if ((bufsize + cap_data) > SZPCR) + bufsize = SZPCR - cap_data; + *buflen = bufsize; + while (bufsize--) { + *buf = read_pci_cfg_byte(cap_data); + cap_data++; + buf++; + } + } + end: + return cap_ptr; +} + +/* ***** Register Access API */ +uint +pcie_readreg(osl_t *osh, sbpcieregs_t *pcieregs, uint addrtype, uint offset) +{ + uint retval = 0xFFFFFFFF; + + ASSERT(pcieregs != NULL); + + switch (addrtype) { + case PCIE_CONFIGREGS: + W_REG(osh, (&pcieregs->configaddr), offset); + (void)R_REG(osh, (&pcieregs->configaddr)); + retval = R_REG(osh, &(pcieregs->configdata)); + break; + case PCIE_PCIEREGS: + W_REG(osh, &(pcieregs->pcieindaddr), offset); + (void)R_REG(osh, (&pcieregs->pcieindaddr)); + retval = R_REG(osh, &(pcieregs->pcieinddata)); + break; + default: + ASSERT(0); + break; + } + + return retval; +} + +uint +pcie_writereg(osl_t *osh, sbpcieregs_t *pcieregs, uint addrtype, uint offset, + uint val) +{ + ASSERT(pcieregs != NULL); + + switch (addrtype) { + case PCIE_CONFIGREGS: + W_REG(osh, (&pcieregs->configaddr), offset); + W_REG(osh, (&pcieregs->configdata), val); + break; + case PCIE_PCIEREGS: + W_REG(osh, (&pcieregs->pcieindaddr), offset); + W_REG(osh, (&pcieregs->pcieinddata), val); + break; + default: + ASSERT(0); + break; + } + return 0; +} + +static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk) +{ + sbpcieregs_t *pcieregs = pi->regs.pcieregs; + uint mdiodata, i = 0; + uint pcie_serdes_spinwait = 200; + + mdiodata = + MDIODATA_START | MDIODATA_WRITE | (MDIODATA_DEV_ADDR << + MDIODATA_DEVADDR_SHF) | + (MDIODATA_BLK_ADDR << MDIODATA_REGADDR_SHF) | MDIODATA_TA | (blk << + 4); + W_REG(pi->osh, &pcieregs->mdiodata, mdiodata); + + PR28829_DELAY(); + /* retry till the transaction is complete */ + while (i < pcie_serdes_spinwait) { + if (R_REG(pi->osh, &(pcieregs->mdiocontrol)) & + MDIOCTL_ACCESS_DONE) { + break; + } + udelay(1000); + i++; + } + + if (i >= pcie_serdes_spinwait) { + PCI_ERROR(("pcie_mdiosetblock: timed out\n")); + return false; + } + + return true; +} + +static int +pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write, + uint *val) +{ + sbpcieregs_t *pcieregs = pi->regs.pcieregs; + uint mdiodata; + uint i = 0; + uint pcie_serdes_spinwait = 10; + + /* enable mdio access to SERDES */ + W_REG(pi->osh, (&pcieregs->mdiocontrol), + MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL); + + if (pi->sih->buscorerev >= 10) { + /* new serdes is slower in rw, using two layers of reg address mapping */ + if (!pcie_mdiosetblock(pi, physmedia)) + return 1; + mdiodata = (MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) | + (regaddr << MDIODATA_REGADDR_SHF); + pcie_serdes_spinwait *= 20; + } else { + mdiodata = (physmedia << MDIODATA_DEVADDR_SHF_OLD) | + (regaddr << MDIODATA_REGADDR_SHF_OLD); + } + + if (!write) + mdiodata |= (MDIODATA_START | MDIODATA_READ | MDIODATA_TA); + else + mdiodata |= + (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA | *val); + + W_REG(pi->osh, &pcieregs->mdiodata, mdiodata); + + PR28829_DELAY(); + + /* retry till the transaction is complete */ + while (i < pcie_serdes_spinwait) { + if (R_REG(pi->osh, &(pcieregs->mdiocontrol)) & + MDIOCTL_ACCESS_DONE) { + if (!write) { + PR28829_DELAY(); + *val = + (R_REG(pi->osh, &(pcieregs->mdiodata)) & + MDIODATA_MASK); + } + /* Disable mdio access to SERDES */ + W_REG(pi->osh, (&pcieregs->mdiocontrol), 0); + return 0; + } + udelay(1000); + i++; + } + + PCI_ERROR(("pcie_mdioop: timed out op: %d\n", write)); + /* Disable mdio access to SERDES */ + W_REG(pi->osh, (&pcieregs->mdiocontrol), 0); + return 1; +} + +/* use the mdio interface to read from mdio slaves */ +static int +pcie_mdioread(pcicore_info_t *pi, uint physmedia, uint regaddr, uint *regval) +{ + return pcie_mdioop(pi, physmedia, regaddr, false, regval); +} + +/* use the mdio interface to write to mdio slaves */ +static int +pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint regaddr, uint val) +{ + return pcie_mdioop(pi, physmedia, regaddr, true, &val); +} + +/* ***** Support functions ***** */ +u8 pcie_clkreq(void *pch, u32 mask, u32 val) +{ + pcicore_info_t *pi = (pcicore_info_t *) pch; + u32 reg_val; + u8 offset; + + offset = pi->pciecap_lcreg_offset; + if (!offset) + return 0; + + reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(u32)); + /* set operation */ + if (mask) { + if (val) + reg_val |= PCIE_CLKREQ_ENAB; + else + reg_val &= ~PCIE_CLKREQ_ENAB; + OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(u32), reg_val); + reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(u32)); + } + if (reg_val & PCIE_CLKREQ_ENAB) + return 1; + else + return 0; +} + +static void pcie_extendL1timer(pcicore_info_t *pi, bool extend) +{ + u32 w; + si_t *sih = pi->sih; + osl_t *osh = pi->osh; + sbpcieregs_t *pcieregs = pi->regs.pcieregs; + + if (!PCIE_PUB(sih) || sih->buscorerev < 7) + return; + + w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG); + if (extend) + w |= PCIE_ASPMTIMER_EXTEND; + else + w &= ~PCIE_ASPMTIMER_EXTEND; + pcie_writereg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG, w); + w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG); +} + +/* centralized clkreq control policy */ +static void pcie_clkreq_upd(pcicore_info_t *pi, uint state) +{ + si_t *sih = pi->sih; + ASSERT(PCIE_PUB(sih)); + + switch (state) { + case SI_DOATTACH: + if (PCIE_ASPM(sih)) + pcie_clkreq((void *)pi, 1, 0); + break; + case SI_PCIDOWN: + if (sih->buscorerev == 6) { /* turn on serdes PLL down */ + si_corereg(sih, SI_CC_IDX, + offsetof(chipcregs_t, chipcontrol_addr), ~0, + 0); + si_corereg(sih, SI_CC_IDX, + offsetof(chipcregs_t, chipcontrol_data), + ~0x40, 0); + } else if (pi->pcie_pr42767) { + pcie_clkreq((void *)pi, 1, 1); + } + break; + case SI_PCIUP: + if (sih->buscorerev == 6) { /* turn off serdes PLL down */ + si_corereg(sih, SI_CC_IDX, + offsetof(chipcregs_t, chipcontrol_addr), ~0, + 0); + si_corereg(sih, SI_CC_IDX, + offsetof(chipcregs_t, chipcontrol_data), + ~0x40, 0x40); + } else if (PCIE_ASPM(sih)) { /* disable clkreq */ + pcie_clkreq((void *)pi, 1, 0); + } + break; + default: + ASSERT(0); + break; + } +} + +/* ***** PCI core WARs ***** */ +/* Done only once at attach time */ +static void pcie_war_polarity(pcicore_info_t *pi) +{ + u32 w; + + if (pi->pcie_polarity != 0) + return; + + w = pcie_readreg(pi->osh, pi->regs.pcieregs, PCIE_PCIEREGS, + PCIE_PLP_STATUSREG); + + /* Detect the current polarity at attach and force that polarity and + * disable changing the polarity + */ + if ((w & PCIE_PLP_POLARITYINV_STAT) == 0) + pi->pcie_polarity = (SERDES_RX_CTRL_FORCE); + else + pi->pcie_polarity = + (SERDES_RX_CTRL_FORCE | SERDES_RX_CTRL_POLARITY); +} + +/* enable ASPM and CLKREQ if srom doesn't have it */ +/* Needs to happen when update to shadow SROM is needed + * : Coming out of 'standby'/'hibernate' + * : If pcie_war_aspm_ovr state changed + */ +static void pcie_war_aspm_clkreq(pcicore_info_t *pi) +{ + sbpcieregs_t *pcieregs = pi->regs.pcieregs; + si_t *sih = pi->sih; + u16 val16, *reg16; + u32 w; + + if (!PCIE_ASPM(sih)) + return; + + /* bypass this on QT or VSIM */ + if (!ISSIM_ENAB(sih)) { + + reg16 = &pcieregs->sprom[SRSH_ASPM_OFFSET]; + val16 = R_REG(pi->osh, reg16); + + val16 &= ~SRSH_ASPM_ENB; + if (pi->pcie_war_aspm_ovr == PCIE_ASPM_ENAB) + val16 |= SRSH_ASPM_ENB; + else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L1_ENAB) + val16 |= SRSH_ASPM_L1_ENB; + else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L0s_ENAB) + val16 |= SRSH_ASPM_L0s_ENB; + + W_REG(pi->osh, reg16, val16); + + w = OSL_PCI_READ_CONFIG(pi->osh, pi->pciecap_lcreg_offset, + sizeof(u32)); + w &= ~PCIE_ASPM_ENAB; + w |= pi->pcie_war_aspm_ovr; + OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset, + sizeof(u32), w); + } + + reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV5]; + val16 = R_REG(pi->osh, reg16); + + if (pi->pcie_war_aspm_ovr != PCIE_ASPM_DISAB) { + val16 |= SRSH_CLKREQ_ENB; + pi->pcie_pr42767 = true; + } else + val16 &= ~SRSH_CLKREQ_ENB; + + W_REG(pi->osh, reg16, val16); +} + +/* Apply the polarity determined at the start */ +/* Needs to happen when coming out of 'standby'/'hibernate' */ +static void pcie_war_serdes(pcicore_info_t *pi) +{ + u32 w = 0; + + if (pi->pcie_polarity != 0) + pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL, + pi->pcie_polarity); + + pcie_mdioread(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, &w); + if (w & PLL_CTRL_FREQDET_EN) { + w &= ~PLL_CTRL_FREQDET_EN; + pcie_mdiowrite(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, w); + } +} + +/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */ +/* Needs to happen when coming out of 'standby'/'hibernate' */ +static void pcie_misc_config_fixup(pcicore_info_t *pi) +{ + sbpcieregs_t *pcieregs = pi->regs.pcieregs; + u16 val16, *reg16; + + reg16 = &pcieregs->sprom[SRSH_PCIE_MISC_CONFIG]; + val16 = R_REG(pi->osh, reg16); + + if ((val16 & SRSH_L23READY_EXIT_NOPERST) == 0) { + val16 |= SRSH_L23READY_EXIT_NOPERST; + W_REG(pi->osh, reg16, val16); + } +} + +/* quick hack for testing */ +/* Needs to happen when coming out of 'standby'/'hibernate' */ +static void pcie_war_noplldown(pcicore_info_t *pi) +{ + sbpcieregs_t *pcieregs = pi->regs.pcieregs; + u16 *reg16; + + ASSERT(pi->sih->buscorerev == 7); + + /* turn off serdes PLL down */ + si_corereg(pi->sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol), + CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN); + + /* clear srom shadow backdoor */ + reg16 = &pcieregs->sprom[SRSH_BD_OFFSET]; + W_REG(pi->osh, reg16, 0); +} + +/* Needs to happen when coming out of 'standby'/'hibernate' */ +static void pcie_war_pci_setup(pcicore_info_t *pi) +{ + si_t *sih = pi->sih; + osl_t *osh = pi->osh; + sbpcieregs_t *pcieregs = pi->regs.pcieregs; + u32 w; + + if ((sih->buscorerev == 0) || (sih->buscorerev == 1)) { + w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS, + PCIE_TLP_WORKAROUNDSREG); + w |= 0x8; + pcie_writereg(osh, pcieregs, PCIE_PCIEREGS, + PCIE_TLP_WORKAROUNDSREG, w); + } + + if (sih->buscorerev == 1) { + w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG); + w |= (0x40); + pcie_writereg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w); + } + + if (sih->buscorerev == 0) { + pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128); + pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100); + pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466); + } else if (PCIE_ASPM(sih)) { + /* Change the L1 threshold for better performance */ + w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS, + PCIE_DLLP_PMTHRESHREG); + w &= ~(PCIE_L1THRESHOLDTIME_MASK); + w |= (PCIE_L1THRESHOLD_WARVAL << PCIE_L1THRESHOLDTIME_SHIFT); + pcie_writereg(osh, pcieregs, PCIE_PCIEREGS, + PCIE_DLLP_PMTHRESHREG, w); + + pcie_war_serdes(pi); + + pcie_war_aspm_clkreq(pi); + } else if (pi->sih->buscorerev == 7) + pcie_war_noplldown(pi); + + /* Note that the fix is actually in the SROM, that's why this is open-ended */ + if (pi->sih->buscorerev >= 6) + pcie_misc_config_fixup(pi); +} + +void pcie_war_ovr_aspm_update(void *pch, u8 aspm) +{ + pcicore_info_t *pi = (pcicore_info_t *) pch; + + if (!PCIE_ASPM(pi->sih)) + return; + + /* Validate */ + if (aspm > PCIE_ASPM_ENAB) + return; + + pi->pcie_war_aspm_ovr = aspm; + + /* Update the current state */ + pcie_war_aspm_clkreq(pi); +} + +/* ***** Functions called during driver state changes ***** */ +void pcicore_attach(void *pch, char *pvars, int state) +{ + pcicore_info_t *pi = (pcicore_info_t *) pch; + si_t *sih = pi->sih; + + /* Determine if this board needs override */ + if (PCIE_ASPM(sih)) { + if ((u32) getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR) { + pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB; + } else { + pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB; + } + } + + /* These need to happen in this order only */ + pcie_war_polarity(pi); + + pcie_war_serdes(pi); + + pcie_war_aspm_clkreq(pi); + + pcie_clkreq_upd(pi, state); + +} + +void pcicore_hwup(void *pch) +{ + pcicore_info_t *pi = (pcicore_info_t *) pch; + + if (!pi || !PCIE_PUB(pi->sih)) + return; + + pcie_war_pci_setup(pi); +} + +void pcicore_up(void *pch, int state) +{ + pcicore_info_t *pi = (pcicore_info_t *) pch; + + if (!pi || !PCIE_PUB(pi->sih)) + return; + + /* Restore L1 timer for better performance */ + pcie_extendL1timer(pi, true); + + pcie_clkreq_upd(pi, state); +} + +/* When the device is going to enter D3 state (or the system is going to enter S3/S4 states */ +void pcicore_sleep(void *pch) +{ + pcicore_info_t *pi = (pcicore_info_t *) pch; + u32 w; + + if (!pi || !PCIE_ASPM(pi->sih)) + return; + + w = OSL_PCI_READ_CONFIG(pi->osh, pi->pciecap_lcreg_offset, + sizeof(u32)); + w &= ~PCIE_CAP_LCREG_ASPML1; + OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset, sizeof(u32), + w); + + pi->pcie_pr42767 = false; +} + +void pcicore_down(void *pch, int state) +{ + pcicore_info_t *pi = (pcicore_info_t *) pch; + + if (!pi || !PCIE_PUB(pi->sih)) + return; + + pcie_clkreq_upd(pi, state); + + /* Reduce L1 timer for better power savings */ + pcie_extendL1timer(pi, false); +} + +/* ***** Wake-on-wireless-LAN (WOWL) support functions ***** */ +/* Just uses PCI config accesses to find out, when needed before sb_attach is done */ +bool pcicore_pmecap_fast(osl_t *osh) +{ + u8 cap_ptr; + u32 pmecap; + + cap_ptr = + pcicore_find_pci_capability(osh, PCI_CAP_POWERMGMTCAP_ID, NULL, + NULL); + + if (!cap_ptr) + return false; + + pmecap = OSL_PCI_READ_CONFIG(osh, cap_ptr, sizeof(u32)); + + return (pmecap & PME_CAP_PM_STATES) != 0; +} + +/* return true if PM capability exists in the pci config space + * Uses and caches the information using core handle + */ +static bool pcicore_pmecap(pcicore_info_t *pi) +{ + u8 cap_ptr; + u32 pmecap; + + if (!pi->pmecap_offset) { + cap_ptr = + pcicore_find_pci_capability(pi->osh, + PCI_CAP_POWERMGMTCAP_ID, NULL, + NULL); + if (!cap_ptr) + return false; + + pi->pmecap_offset = cap_ptr; + + pmecap = + OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset, + sizeof(u32)); + + /* At least one state can generate PME */ + pi->pmecap = (pmecap & PME_CAP_PM_STATES) != 0; + } + + return pi->pmecap; +} + +/* Enable PME generation */ +void pcicore_pmeen(void *pch) +{ + pcicore_info_t *pi = (pcicore_info_t *) pch; + u32 w; + + /* if not pmecapable return */ + if (!pcicore_pmecap(pi)) + return; + + w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, + sizeof(u32)); + w |= (PME_CSR_PME_EN); + OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, + sizeof(u32), w); +} + +/* + * Return true if PME status set + */ +bool pcicore_pmestat(void *pch) +{ + pcicore_info_t *pi = (pcicore_info_t *) pch; + u32 w; + + if (!pcicore_pmecap(pi)) + return false; + + w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, + sizeof(u32)); + + return (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT; +} + +/* Disable PME generation, clear the PME status bit if set + */ +void pcicore_pmeclr(void *pch) +{ + pcicore_info_t *pi = (pcicore_info_t *) pch; + u32 w; + + if (!pcicore_pmecap(pi)) + return; + + w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, + sizeof(u32)); + + PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w)); + + /* PMESTAT is cleared by writing 1 to it */ + w &= ~(PME_CSR_PME_EN); + + OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, + sizeof(u32), w); +} + +u32 pcie_lcreg(void *pch, u32 mask, u32 val) +{ + pcicore_info_t *pi = (pcicore_info_t *) pch; + u8 offset; + + offset = pi->pciecap_lcreg_offset; + if (!offset) + return 0; + + /* set operation */ + if (mask) + OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(u32), val); + + return OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(u32)); +} + +u32 +pcicore_pciereg(void *pch, u32 offset, u32 mask, u32 val, uint type) +{ + u32 reg_val = 0; + pcicore_info_t *pi = (pcicore_info_t *) pch; + sbpcieregs_t *pcieregs = pi->regs.pcieregs; + osl_t *osh = pi->osh; + + if (mask) { + PCI_ERROR(("PCIEREG: 0x%x writeval 0x%x\n", offset, val)); + pcie_writereg(osh, pcieregs, type, offset, val); + } + + /* Should not read register 0x154 */ + if (pi->sih->buscorerev <= 5 && offset == PCIE_DLLP_PCIE11 + && type == PCIE_PCIEREGS) + return reg_val; + + reg_val = pcie_readreg(osh, pcieregs, type, offset); + PCI_ERROR(("PCIEREG: 0x%x readval is 0x%x\n", offset, reg_val)); + + return reg_val; +} + +u32 +pcicore_pcieserdesreg(void *pch, u32 mdioslave, u32 offset, u32 mask, + u32 val) +{ + u32 reg_val = 0; + pcicore_info_t *pi = (pcicore_info_t *) pch; + + if (mask) { + PCI_ERROR(("PCIEMDIOREG: 0x%x writeval 0x%x\n", offset, val)); + pcie_mdiowrite(pi, mdioslave, offset, val); + } + + if (pcie_mdioread(pi, mdioslave, offset, ®_val)) + reg_val = 0xFFFFFFFF; + PCI_ERROR(("PCIEMDIOREG: dev 0x%x offset 0x%x read 0x%x\n", mdioslave, + offset, reg_val)); + + return reg_val; +} diff --git a/drivers/staging/brcm80211/util/nvram/nvram_ro.c b/drivers/staging/brcm80211/util/nvram/nvram_ro.c new file mode 100644 index 0000000..f80375c --- /dev/null +++ b/drivers/staging/brcm80211/util/nvram/nvram_ro.c @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <linux/slab.h> +#include <linux/string.h> +#include <bcmdefs.h> +#include <osl.h> +#include <bcmutils.h> +#include <siutils.h> +#include <bcmendian.h> +#include <bcmnvram.h> +#include <sbchipc.h> +#include <bcmsrom.h> +#include <bcmotp.h> +#include <bcmdevs.h> +#include <hndsoc.h> + +#define NVR_MSG(x) + +typedef struct _vars { + struct _vars *next; + int bufsz; /* allocated size */ + int size; /* actual vars size */ + char *vars; +} vars_t; + +#define VARS_T_OH sizeof(vars_t) + +static vars_t *vars; + +#define NVRAM_FILE 1 + +static char *findvar(char *vars, char *lim, const char *name); + +#if defined(FLASH) +/* copy flash to ram */ +static void get_flash_nvram(si_t *sih, struct nvram_header *nvh) +{ + osl_t *osh; + uint nvs, bufsz; + vars_t *new; + + osh = si_osh(sih); + + nvs = R_REG(osh, &nvh->len) - sizeof(struct nvram_header); + bufsz = nvs + VARS_T_OH; + + new = kmalloc(bufsz, GFP_ATOMIC); + if (new == NULL) { + NVR_MSG(("Out of memory for flash vars\n")); + return; + } + new->vars = (char *)new + VARS_T_OH; + + new->bufsz = bufsz; + new->size = nvs; + new->next = vars; + vars = new; + + bcopy((char *)(&nvh[1]), new->vars, nvs); + + NVR_MSG(("%s: flash nvram @ %p, copied %d bytes to %p\n", __func__, + nvh, nvs, new->vars)); +} +#endif /* FLASH */ + +int nvram_init(void *si) +{ + + /* Make sure we read nvram in flash just once before freeing the memory */ + if (vars != NULL) { + NVR_MSG(("nvram_init: called again without calling nvram_exit()\n")); + return 0; + } + return 0; +} + +int nvram_append(void *si, char *varlst, uint varsz) +{ + uint bufsz = VARS_T_OH; + vars_t *new; + + new = kmalloc(bufsz, GFP_ATOMIC); + if (new == NULL) + return BCME_NOMEM; + + new->vars = varlst; + new->bufsz = bufsz; + new->size = varsz; + new->next = vars; + vars = new; + + return BCME_OK; +} + +void nvram_exit(void *si) +{ + vars_t *this, *next; + si_t *sih; + + sih = (si_t *) si; + this = vars; + + if (this) + kfree(this->vars); + + while (this) { + next = this->next; + kfree(this); + this = next; + } + vars = NULL; +} + +static char *findvar(char *vars, char *lim, const char *name) +{ + char *s; + int len; + + len = strlen(name); + + for (s = vars; (s < lim) && *s;) { + if ((bcmp(s, name, len) == 0) && (s[len] == '=')) + return &s[len + 1]; + + while (*s++) + ; + } + + return NULL; +} + +char *nvram_get(const char *name) +{ + char *v = NULL; + vars_t *cur; + + for (cur = vars; cur; cur = cur->next) { + v = findvar(cur->vars, cur->vars + cur->size, name); + if (v) + break; + } + + return v; +} + +int nvram_set(const char *name, const char *value) +{ + return 0; +} + +int nvram_unset(const char *name) +{ + return 0; +} + +int nvram_reset(void *si) +{ + return 0; +} + +int nvram_commit(void) +{ + return 0; +} + +int nvram_getall(char *buf, int count) +{ + int len, resid = count; + vars_t *this; + + this = vars; + while (this) { + char *from, *lim, *to; + int acc; + + from = this->vars; + lim = (char *)(this->vars + this->size); + to = buf; + acc = 0; + while ((from < lim) && (*from)) { + len = strlen(from) + 1; + if (resid < (acc + len)) + return BCME_BUFTOOSHORT; + bcopy(from, to, len); + acc += len; + from += len; + to += len; + } + + resid -= acc; + buf += acc; + this = this->next; + } + if (resid < 1) + return BCME_BUFTOOSHORT; + *buf = '\0'; + return 0; +} diff --git a/drivers/staging/brcm80211/util/qmath.c b/drivers/staging/brcm80211/util/qmath.c new file mode 100644 index 0000000..40c9929 --- /dev/null +++ b/drivers/staging/brcm80211/util/qmath.c @@ -0,0 +1,681 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <linux/types.h> +#include "qmath.h" + +/* +Description: This function saturate input 32 bit number into a 16 bit number. +If input number is greater than 0x7fff then output is saturated to 0x7fff. +else if input number is less than 0xffff8000 then output is saturated to 0xffff8000 +else output is same as input. +*/ +s16 qm_sat32(s32 op) +{ + s16 result; + if (op > (s32) 0x7fff) { + result = 0x7fff; + } else if (op < (s32) 0xffff8000) { + result = (s16) (0x8000); + } else { + result = (s16) op; + } + return result; +} + +/* +Description: This function multiply two input 16 bit numbers and return the 32 bit result. +This multiplication is similar to compiler multiplication. This operation is defined if +16 bit multiplication on the processor platform is cheaper than 32 bit multiplication (as +the most of qmath functions can be replaced with processor intrinsic instructions). +*/ +s32 qm_mul321616(s16 op1, s16 op2) +{ + return (s32) (op1) * (s32) (op2); +} + +/* +Description: This function make 16 bit multiplication and return the result in 16 bits. +To fit the result into 16 bits the 32 bit multiplication result is right +shifted by 16 bits. +*/ +s16 qm_mul16(s16 op1, s16 op2) +{ + s32 result; + result = ((s32) (op1) * (s32) (op2)); + return (s16) (result >> 16); +} + +/* +Description: This function multiply two 16 bit numbers and return the result in 32 bits. +This function remove the extra sign bit created by the multiplication by leftshifting the +32 bit multiplication result by 1 bit before returning the result. So the output is +twice that of compiler multiplication. (i.e. qm_muls321616(2,3)=12). +When both input 16 bit numbers are 0x8000, then the result is saturated to 0x7fffffff. +*/ +s32 qm_muls321616(s16 op1, s16 op2) +{ + s32 result; + if (op1 == (s16) (0x8000) && op2 == (s16) (0x8000)) { + result = 0x7fffffff; + } else { + result = ((s32) (op1) * (s32) (op2)); + result = result << 1; + } + return result; +} + +/* +Description: This function make 16 bit unsigned multiplication. To fit the output into +16 bits the 32 bit multiplication result is right shifted by 16 bits. +*/ +u16 qm_mulu16(u16 op1, u16 op2) +{ + return (u16) (((u32) op1 * (u32) op2) >> 16); +} + +/* +Description: This function make 16 bit multiplication and return the result in 16 bits. +To fit the multiplication result into 16 bits the multiplication result is right shifted by +15 bits. Right shifting 15 bits instead of 16 bits is done to remove the extra sign bit formed +due to the multiplication. +When both the 16bit inputs are 0x8000 then the output is saturated to 0x7fffffff. +*/ +s16 qm_muls16(s16 op1, s16 op2) +{ + s32 result; + if (op1 == (s16) 0x8000 && op2 == (s16) 0x8000) { + result = 0x7fffffff; + } else { + result = ((s32) (op1) * (s32) (op2)); + } + return (s16) (result >> 15); +} + +/* +Description: This function add two 32 bit numbers and return the 32bit result. +If the result overflow 32 bits, the output will be saturated to 32bits. +*/ +s32 qm_add32(s32 op1, s32 op2) +{ + s32 result; + result = op1 + op2; + if (op1 < 0 && op2 < 0 && result > 0) { + result = 0x80000000; + } else if (op1 > 0 && op2 > 0 && result < 0) { + result = 0x7fffffff; + } + return result; +} + +/* +Description: This function add two 16 bit numbers and return the 16bit result. +If the result overflow 16 bits, the output will be saturated to 16bits. +*/ +s16 qm_add16(s16 op1, s16 op2) +{ + s16 result; + s32 temp = (s32) op1 + (s32) op2; + if (temp > (s32) 0x7fff) { + result = (s16) 0x7fff; + } else if (temp < (s32) 0xffff8000) { + result = (s16) 0xffff8000; + } else { + result = (s16) temp; + } + return result; +} + +/* +Description: This function make 16 bit subtraction and return the 16bit result. +If the result overflow 16 bits, the output will be saturated to 16bits. +*/ +s16 qm_sub16(s16 op1, s16 op2) +{ + s16 result; + s32 temp = (s32) op1 - (s32) op2; + if (temp > (s32) 0x7fff) { + result = (s16) 0x7fff; + } else if (temp < (s32) 0xffff8000) { + result = (s16) 0xffff8000; + } else { + result = (s16) temp; + } + return result; +} + +/* +Description: This function make 32 bit subtraction and return the 32bit result. +If the result overflow 32 bits, the output will be saturated to 32bits. +*/ +s32 qm_sub32(s32 op1, s32 op2) +{ + s32 result; + result = op1 - op2; + if (op1 >= 0 && op2 < 0 && result < 0) { + result = 0x7fffffff; + } else if (op1 < 0 && op2 > 0 && result > 0) { + result = 0x80000000; + } + return result; +} + +/* +Description: This function multiply input 16 bit numbers and accumulate the result +into the input 32 bit number and return the 32 bit accumulated result. +If the accumulation result in overflow, then the output will be saturated. +*/ +s32 qm_mac321616(s32 acc, s16 op1, s16 op2) +{ + s32 result; + result = qm_add32(acc, qm_mul321616(op1, op2)); + return result; +} + +/* +Description: This function make a 32 bit saturated left shift when the specified shift +is +ve. This function will make a 32 bit right shift when the specified shift is -ve. +This function return the result after shifting operation. +*/ +s32 qm_shl32(s32 op, int shift) +{ + int i; + s32 result; + result = op; + if (shift > 31) + shift = 31; + else if (shift < -31) + shift = -31; + if (shift >= 0) { + for (i = 0; i < shift; i++) { + result = qm_add32(result, result); + } + } else { + result = result >> (-shift); + } + return result; +} + +/* +Description: This function make a 32 bit right shift when shift is +ve. +This function make a 32 bit saturated left shift when shift is -ve. This function +return the result of the shift operation. +*/ +s32 qm_shr32(s32 op, int shift) +{ + return qm_shl32(op, -shift); +} + +/* +Description: This function make a 16 bit saturated left shift when the specified shift +is +ve. This function will make a 16 bit right shift when the specified shift is -ve. +This function return the result after shifting operation. +*/ +s16 qm_shl16(s16 op, int shift) +{ + int i; + s16 result; + result = op; + if (shift > 15) + shift = 15; + else if (shift < -15) + shift = -15; + if (shift > 0) { + for (i = 0; i < shift; i++) { + result = qm_add16(result, result); + } + } else { + result = result >> (-shift); + } + return result; +} + +/* +Description: This function make a 16 bit right shift when shift is +ve. +This function make a 16 bit saturated left shift when shift is -ve. This function +return the result of the shift operation. +*/ +s16 qm_shr16(s16 op, int shift) +{ + return qm_shl16(op, -shift); +} + +/* +Description: This function return the number of redundant sign bits in a 16 bit number. +Example: qm_norm16(0x0080) = 7. +*/ +s16 qm_norm16(s16 op) +{ + u16 u16extraSignBits; + if (op == 0) { + return 15; + } else { + u16extraSignBits = 0; + while ((op >> 15) == (op >> 14)) { + u16extraSignBits++; + op = op << 1; + } + } + return u16extraSignBits; +} + +/* +Description: This function return the number of redundant sign bits in a 32 bit number. +Example: qm_norm32(0x00000080) = 23 +*/ +s16 qm_norm32(s32 op) +{ + u16 u16extraSignBits; + if (op == 0) { + return 31; + } else { + u16extraSignBits = 0; + while ((op >> 31) == (op >> 30)) { + u16extraSignBits++; + op = op << 1; + } + } + return u16extraSignBits; +} + +/* +Description: This function divide two 16 bit unsigned numbers. +The numerator should be less than denominator. So the quotient is always less than 1. +This function return the quotient in q.15 format. +*/ +s16 qm_div_s(s16 num, s16 denom) +{ + s16 var_out; + s16 iteration; + s32 L_num; + s32 L_denom; + L_num = (num) << 15; + L_denom = (denom) << 15; + for (iteration = 0; iteration < 15; iteration++) { + L_num <<= 1; + if (L_num >= L_denom) { + L_num = qm_sub32(L_num, L_denom); + L_num = qm_add32(L_num, 1); + } + } + var_out = (s16) (L_num & 0x7fff); + return var_out; +} + +/* +Description: This function compute the absolute value of a 16 bit number. +*/ +s16 qm_abs16(s16 op) +{ + if (op < 0) { + if (op == (s16) 0xffff8000) { + return 0x7fff; + } else { + return -op; + } + } else { + return op; + } +} + +/* +Description: This function divide two 16 bit numbers. +The quotient is returned through return value. +The qformat of the quotient is returned through the pointer (qQuotient) passed +to this function. The qformat of quotient is adjusted appropriately such that +the quotient occupies all 16 bits. +*/ +s16 qm_div16(s16 num, s16 denom, s16 *qQuotient) +{ + s16 sign; + s16 nNum, nDenom; + sign = num ^ denom; + num = qm_abs16(num); + denom = qm_abs16(denom); + nNum = qm_norm16(num); + nDenom = qm_norm16(denom); + num = qm_shl16(num, nNum - 1); + denom = qm_shl16(denom, nDenom); + *qQuotient = nNum - 1 - nDenom + 15; + if (sign >= 0) { + return qm_div_s(num, denom); + } else { + return -qm_div_s(num, denom); + } +} + +/* +Description: This function compute absolute value of a 32 bit number. +*/ +s32 qm_abs32(s32 op) +{ + if (op < 0) { + if (op == (s32) 0x80000000) { + return 0x7fffffff; + } else { + return -op; + } + } else { + return op; + } +} + +/* +Description: This function divide two 32 bit numbers. The division is performed +by considering only important 16 bits in 32 bit numbers. +The quotient is returned through return value. +The qformat of the quotient is returned through the pointer (qquotient) passed +to this function. The qformat of quotient is adjusted appropriately such that +the quotient occupies all 16 bits. +*/ +s16 qm_div163232(s32 num, s32 denom, s16 *qquotient) +{ + s32 sign; + s16 nNum, nDenom; + sign = num ^ denom; + num = qm_abs32(num); + denom = qm_abs32(denom); + nNum = qm_norm32(num); + nDenom = qm_norm32(denom); + num = qm_shl32(num, nNum - 1); + denom = qm_shl32(denom, nDenom); + *qquotient = nNum - 1 - nDenom + 15; + if (sign >= 0) { + return qm_div_s((s16) (num >> 16), (s16) (denom >> 16)); + } else { + return -qm_div_s((s16) (num >> 16), (s16) (denom >> 16)); + } +} + +/* +Description: This function multiply a 32 bit number with a 16 bit number. +The multiplicaton result is right shifted by 16 bits to fit the result +into 32 bit output. +*/ +s32 qm_mul323216(s32 op1, s16 op2) +{ + s16 hi; + u16 lo; + s32 result; + hi = op1 >> 16; + lo = (s16) (op1 & 0xffff); + result = qm_mul321616(hi, op2); + result = result + (qm_mulsu321616(op2, lo) >> 16); + return result; +} + +/* +Description: This function multiply signed 16 bit number with unsigned 16 bit number and return +the result in 32 bits. +*/ +s32 qm_mulsu321616(s16 op1, u16 op2) +{ + return (s32) (op1) * op2; +} + +/* +Description: This function multiply 32 bit number with 16 bit number. The multiplication result is +right shifted by 15 bits to fit the result into 32 bits. Right shifting by only 15 bits instead of +16 bits is done to remove the extra sign bit formed by multiplication from the return value. +When the input numbers are 0x80000000, 0x8000 the return value is saturated to 0x7fffffff. +*/ +s32 qm_muls323216(s32 op1, s16 op2) +{ + s16 hi; + u16 lo; + s32 result; + hi = op1 >> 16; + lo = (s16) (op1 & 0xffff); + result = qm_muls321616(hi, op2); + result = qm_add32(result, (qm_mulsu321616(op2, lo) >> 15)); + return result; +} + +/* +Description: This function multiply two 32 bit numbers. The multiplication result is right +shifted by 32 bits to fit the multiplication result into 32 bits. The right shifted +multiplication result is returned as output. +*/ +s32 qm_mul32(s32 a, s32 b) +{ + s16 hi1, hi2; + u16 lo1, lo2; + s32 result; + hi1 = a >> 16; + hi2 = b >> 16; + lo1 = (u16) (a & 0xffff); + lo2 = (u16) (b & 0xffff); + result = qm_mul321616(hi1, hi2); + result = result + (qm_mulsu321616(hi1, lo2) >> 16); + result = result + (qm_mulsu321616(hi2, lo1) >> 16); + return result; +} + +/* +Description: This function multiply two 32 bit numbers. The multiplication result is +right shifted by 31 bits to fit the multiplication result into 32 bits. The right +shifted multiplication result is returned as output. Right shifting by only 31 bits +instead of 32 bits is done to remove the extra sign bit formed by multiplication. +When the input numbers are 0x80000000, 0x80000000 the return value is saturated to +0x7fffffff. +*/ +s32 qm_muls32(s32 a, s32 b) +{ + s16 hi1, hi2; + u16 lo1, lo2; + s32 result; + hi1 = a >> 16; + hi2 = b >> 16; + lo1 = (u16) (a & 0xffff); + lo2 = (u16) (b & 0xffff); + result = qm_muls321616(hi1, hi2); + result = qm_add32(result, (qm_mulsu321616(hi1, lo2) >> 15)); + result = qm_add32(result, (qm_mulsu321616(hi2, lo1) >> 15)); + result = qm_add32(result, (qm_mulu16(lo1, lo2) >> 15)); + return result; +} + +/* This table is log2(1+(i/32)) where i=[0:1:31], in q.15 format */ +static const s16 log_table[] = { + 0, + 1455, + 2866, + 4236, + 5568, + 6863, + 8124, + 9352, + 10549, + 11716, + 12855, + 13968, + 15055, + 16117, + 17156, + 18173, + 19168, + 20143, + 21098, + 22034, + 22952, + 23852, + 24736, + 25604, + 26455, + 27292, + 28114, + 28922, + 29717, + 30498, + 31267, + 32024 +}; + +#define LOG_TABLE_SIZE 32 /* log_table size */ +#define LOG2_LOG_TABLE_SIZE 5 /* log2(log_table size) */ +#define Q_LOG_TABLE 15 /* qformat of log_table */ +#define LOG10_2 19728 /* log10(2) in q.16 */ + +/* +Description: +This routine takes the input number N and its q format qN and compute +the log10(N). This routine first normalizes the input no N. Then N is in mag*(2^x) format. +mag is any number in the range 2^30-(2^31 - 1). Then log2(mag * 2^x) = log2(mag) + x is computed. +From that log10(mag * 2^x) = log2(mag * 2^x) * log10(2) is computed. +This routine looks the log2 value in the table considering LOG2_LOG_TABLE_SIZE+1 MSBs. +As the MSB is always 1, only next LOG2_OF_LOG_TABLE_SIZE MSBs are used for table lookup. +Next 16 MSBs are used for interpolation. +Inputs: +N - number to which log10 has to be found. +qN - q format of N +log10N - address where log10(N) will be written. +qLog10N - address where log10N qformat will be written. +Note/Problem: +For accurate results input should be in normalized or near normalized form. +*/ +void qm_log10(s32 N, s16 qN, s16 *log10N, s16 *qLog10N) +{ + s16 s16norm, s16tableIndex, s16errorApproximation; + u16 u16offset; + s32 s32log; + + /* Logerithm of negative values is undefined. + * assert N is greater than 0. + */ + /* ASSERT(N > 0); */ + + /* normalize the N. */ + s16norm = qm_norm32(N); + N = N << s16norm; + + /* The qformat of N after normalization. + * -30 is added to treat the no as between 1.0 to 2.0 + * i.e. after adding the -30 to the qformat the decimal point will be + * just rigtht of the MSB. (i.e. after sign bit and 1st MSB). i.e. + * at the right side of 30th bit. + */ + qN = qN + s16norm - 30; + + /* take the table index as the LOG2_OF_LOG_TABLE_SIZE bits right of the MSB */ + s16tableIndex = (s16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE))); + + /* remove the MSB. the MSB is always 1 after normalization. */ + s16tableIndex = + s16tableIndex & (s16) ((1 << LOG2_LOG_TABLE_SIZE) - 1); + + /* remove the (1+LOG2_OF_LOG_TABLE_SIZE) MSBs in the N. */ + N = N & ((1 << (32 - (2 + LOG2_LOG_TABLE_SIZE))) - 1); + + /* take the offset as the 16 MSBS after table index. + */ + u16offset = (u16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE + 16))); + + /* look the log value in the table. */ + s32log = log_table[s16tableIndex]; /* q.15 format */ + + /* interpolate using the offset. */ + s16errorApproximation = (s16) qm_mulu16(u16offset, (u16) (log_table[s16tableIndex + 1] - log_table[s16tableIndex])); /* q.15 */ + + s32log = qm_add16((s16) s32log, s16errorApproximation); /* q.15 format */ + + /* adjust for the qformat of the N as + * log2(mag * 2^x) = log2(mag) + x + */ + s32log = qm_add32(s32log, ((s32) -qN) << 15); /* q.15 format */ + + /* normalize the result. */ + s16norm = qm_norm32(s32log); + + /* bring all the important bits into lower 16 bits */ + s32log = qm_shl32(s32log, s16norm - 16); /* q.15+s16norm-16 format */ + + /* compute the log10(N) by multiplying log2(N) with log10(2). + * as log10(mag * 2^x) = log2(mag * 2^x) * log10(2) + * log10N in q.15+s16norm-16+1 (LOG10_2 is in q.16) + */ + *log10N = qm_muls16((s16) s32log, (s16) LOG10_2); + + /* write the q format of the result. */ + *qLog10N = 15 + s16norm - 16 + 1; + + return; +} + +/* +Description: +This routine compute 1/N. +This routine reformates the given no N as N * 2^qN where N is in between 0.5 and 1.0 +in q.15 format in 16 bits. So the problem now boils down to finding the inverse of a +q.15 no in 16 bits which is in the range of 0.5 to 1.0. The output is always between +2.0 to 1. So the output is 2.0 to 1.0 in q.30 format. Once the final output format is found +by taking the qN into account. Inverse is found with newton rapson method. Initially +inverse (x) is guessed as 1/0.75 (with appropriate sign). The new guess is calculated +using the formula x' = 2*x - N*x*x. After 4 or 5 iterations the inverse is very close to +inverse of N. +Inputs: +N - number to which 1/N has to be found. +qn - q format of N. +sqrtN - address where 1/N has to be written. +qsqrtN - address where q format of 1/N has to be written. +*/ +#define qx 29 +void qm_1byN(s32 N, s16 qN, s32 *result, s16 *qResult) +{ + s16 normN; + s32 s32firstTerm, s32secondTerm, x; + int i; + + normN = qm_norm32(N); + + /* limit N to least significant 16 bits. 15th bit is the sign bit. */ + N = qm_shl32(N, normN - 16); + qN = qN + normN - 16 - 15; + /* -15 is added to treat N as 16 bit q.15 number in the range from 0.5 to 1 */ + + /* Take the initial guess as 1/0.75 in qx format with appropriate sign. */ + if (N >= 0) { + x = (s32) ((1 / 0.75) * (1 << qx)); + /* input no is in the range 0.5 to 1. So 1/0.75 is taken as initial guess. */ + } else { + x = (s32) ((1 / -0.75) * (1 << qx)); + /* input no is in the range -0.5 to -1. So 1/-0.75 is taken as initial guess. */ + } + + /* iterate the equation x = 2*x - N*x*x for 4 times. */ + for (i = 0; i < 4; i++) { + s32firstTerm = qm_shl32(x, 1); /* s32firstTerm = 2*x in q.29 */ + s32secondTerm = + qm_muls321616((s16) (s32firstTerm >> 16), + (s16) (s32firstTerm >> 16)); + /* s32secondTerm = x*x in q.(29+1-16)*2+1 */ + s32secondTerm = + qm_muls321616((s16) (s32secondTerm >> 16), (s16) N); + /* s32secondTerm = N*x*x in q.((29+1-16)*2+1)-16+15+1 i.e. in q.29 */ + x = qm_sub32(s32firstTerm, s32secondTerm); + /* can be added directly as both are in q.29 */ + } + + /* Bring the x to q.30 format. */ + *result = qm_shl32(x, 1); + /* giving the output in q.30 format for q.15 input in 16 bits. */ + + /* compute the final q format of the result. */ + *qResult = -qN + 30; /* adjusting the q format of actual output */ + + return; +} + +#undef qx diff --git a/drivers/staging/brcm80211/util/sbutils.c b/drivers/staging/brcm80211/util/sbutils.c new file mode 100644 index 0000000..e4c0bab --- /dev/null +++ b/drivers/staging/brcm80211/util/sbutils.c @@ -0,0 +1,585 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <linux/types.h> +#include <bcmdefs.h> +#include <osl.h> +#include <bcmutils.h> +#include <siutils.h> +#include <bcmdevs.h> +#include <hndsoc.h> +#include <sbchipc.h> +#include <pci_core.h> +#include <pcicfg.h> +#include <sbpcmcia.h> +#include "siutils_priv.h" + +/* local prototypes */ +static uint _sb_coreidx(si_info_t *sii, u32 sba); +static uint _sb_scan(si_info_t *sii, u32 sba, void *regs, uint bus, + u32 sbba, uint ncores); +static u32 _sb_coresba(si_info_t *sii); +static void *_sb_setcoreidx(si_info_t *sii, uint coreidx); + +#define SET_SBREG(sii, r, mask, val) \ + W_SBREG((sii), (r), ((R_SBREG((sii), (r)) & ~(mask)) | (val))) +#define REGS2SB(va) (sbconfig_t *) ((s8 *)(va) + SBCONFIGOFF) + +/* sonicsrev */ +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT) +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT) + +#define R_SBREG(sii, sbr) sb_read_sbreg((sii), (sbr)) +#define W_SBREG(sii, sbr, v) sb_write_sbreg((sii), (sbr), (v)) +#define AND_SBREG(sii, sbr, v) \ + W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) & (v))) +#define OR_SBREG(sii, sbr, v) \ + W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) | (v))) + +static u32 sb_read_sbreg(si_info_t *sii, volatile u32 *sbr) +{ + return R_REG(sii->osh, sbr); +} + +static void sb_write_sbreg(si_info_t *sii, volatile u32 *sbr, u32 v) +{ + W_REG(sii->osh, sbr, v); +} + +uint sb_coreid(si_t *sih) +{ + si_info_t *sii; + sbconfig_t *sb; + + sii = SI_INFO(sih); + sb = REGS2SB(sii->curmap); + + return (R_SBREG(sii, &sb->sbidhigh) & SBIDH_CC_MASK) >> + SBIDH_CC_SHIFT; +} + +/* return core index of the core with address 'sba' */ +static uint _sb_coreidx(si_info_t *sii, u32 sba) +{ + uint i; + + for (i = 0; i < sii->numcores; i++) + if (sba == sii->coresba[i]) + return i; + return BADIDX; +} + +/* return core address of the current core */ +static u32 _sb_coresba(si_info_t *sii) +{ + u32 sbaddr = 0; + + switch (BUSTYPE(sii->pub.bustype)) { + case SPI_BUS: + case SDIO_BUS: + sbaddr = (u32)(unsigned long)sii->curmap; + break; + default: + ASSERT(0); + break; + } + + return sbaddr; +} + +uint sb_corerev(si_t *sih) +{ + si_info_t *sii; + sbconfig_t *sb; + uint sbidh; + + sii = SI_INFO(sih); + sb = REGS2SB(sii->curmap); + sbidh = R_SBREG(sii, &sb->sbidhigh); + + return SBCOREREV(sbidh); +} + +bool sb_iscoreup(si_t *sih) +{ + si_info_t *sii; + sbconfig_t *sb; + + sii = SI_INFO(sih); + sb = REGS2SB(sii->curmap); + + return (R_SBREG(sii, &sb->sbtmstatelow) & + (SBTML_RESET | SBTML_REJ_MASK | + (SICF_CLOCK_EN << SBTML_SICF_SHIFT))) == + (SICF_CLOCK_EN << SBTML_SICF_SHIFT); +} + +/* + * Switch to 'coreidx', issue a single arbitrary 32bit + * register mask&set operation, + * switch back to the original core, and return the new value. + * + * When using the silicon backplane, no fidleing with interrupts + * or core switches are needed. + * + * Also, when using pci/pcie, we can optimize away the core switching + * for pci registers + * and (on newer pci cores) chipcommon registers. + */ +uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) +{ + uint origidx = 0; + u32 *r = NULL; + uint w; + uint intr_val = 0; + bool fast = false; + si_info_t *sii; + + sii = SI_INFO(sih); + + ASSERT(GOODIDX(coreidx)); + ASSERT(regoff < SI_CORE_SIZE); + ASSERT((val & ~mask) == 0); + + if (coreidx >= SI_MAXCORES) + return 0; + + if (!fast) { + INTR_OFF(sii, intr_val); + + /* save current core index */ + origidx = si_coreidx(&sii->pub); + + /* switch core */ + r = (u32 *) ((unsigned char *) sb_setcoreidx(&sii->pub, coreidx) + + regoff); + } + ASSERT(r != NULL); + + /* mask and set */ + if (mask || val) { + if (regoff >= SBCONFIGOFF) { + w = (R_SBREG(sii, r) & ~mask) | val; + W_SBREG(sii, r, w); + } else { + w = (R_REG(sii->osh, r) & ~mask) | val; + W_REG(sii->osh, r, w); + } + } + + /* readback */ + if (regoff >= SBCONFIGOFF) + w = R_SBREG(sii, r); + else + w = R_REG(sii->osh, r); + + if (!fast) { + /* restore core index */ + if (origidx != coreidx) + sb_setcoreidx(&sii->pub, origidx); + + INTR_RESTORE(sii, intr_val); + } + + return w; +} + +/* Scan the enumeration space to find all cores starting from the given + * bus 'sbba'. Append coreid and other info to the lists in 'si'. 'sba' + * is the default core address at chip POR time and 'regs' is the virtual + * address that the default core is mapped at. 'ncores' is the number of + * cores expected on bus 'sbba'. It returns the total number of cores + * starting from bus 'sbba', inclusive. + */ +#define SB_MAXBUSES 2 +static uint _sb_scan(si_info_t *sii, u32 sba, void *regs, uint bus, u32 sbba, + uint numcores) +{ + uint next; + uint ncc = 0; + uint i; + + if (bus >= SB_MAXBUSES) { + SI_ERROR(("_sb_scan: bus 0x%08x at level %d is too deep to " + "scan\n", sbba, bus)); + return 0; + } + SI_MSG(("_sb_scan: scan bus 0x%08x assume %u cores\n", + sbba, numcores)); + + /* Scan all cores on the bus starting from core 0. + * Core addresses must be contiguous on each bus. + */ + for (i = 0, next = sii->numcores; + i < numcores && next < SB_BUS_MAXCORES; i++, next++) { + sii->coresba[next] = sbba + (i * SI_CORE_SIZE); + + /* change core to 'next' and read its coreid */ + sii->curmap = _sb_setcoreidx(sii, next); + sii->curidx = next; + + sii->coreid[next] = sb_coreid(&sii->pub); + + /* core specific processing... */ + /* chipc provides # cores */ + if (sii->coreid[next] == CC_CORE_ID) { + chipcregs_t *cc = (chipcregs_t *) sii->curmap; + u32 ccrev = sb_corerev(&sii->pub); + + /* determine numcores - this is the + total # cores in the chip */ + if (((ccrev == 4) || (ccrev >= 6))) + numcores = + (R_REG(sii->osh, &cc->chipid) & CID_CC_MASK) + >> CID_CC_SHIFT; + else { + /* Older chips */ + SI_ERROR(("sb_chip2numcores: unsupported chip " + "0x%x\n", CHIPID(sii->pub.chip))); + ASSERT(0); + numcores = 1; + } + + SI_VMSG(("_sb_scan: %u cores in the chip %s\n", + numcores, sii->pub.issim ? "QT" : "")); + } + /* scan bridged SB(s) and add results to the end of the list */ + else if (sii->coreid[next] == OCP_CORE_ID) { + sbconfig_t *sb = REGS2SB(sii->curmap); + u32 nsbba = R_SBREG(sii, &sb->sbadmatch1); + uint nsbcc; + + sii->numcores = next + 1; + + if ((nsbba & 0xfff00000) != SI_ENUM_BASE) + continue; + nsbba &= 0xfffff000; + if (_sb_coreidx(sii, nsbba) != BADIDX) + continue; + + nsbcc = + (R_SBREG(sii, &sb->sbtmstatehigh) & 0x000f0000) >> + 16; + nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc); + if (sbba == SI_ENUM_BASE) + numcores -= nsbcc; + ncc += nsbcc; + } + } + + SI_MSG(("_sb_scan: found %u cores on bus 0x%08x\n", i, sbba)); + + sii->numcores = i + ncc; + return sii->numcores; +} + +/* scan the sb enumerated space to identify all cores */ +void sb_scan(si_t *sih, void *regs, uint devid) +{ + si_info_t *sii; + u32 origsba; + sbconfig_t *sb; + + sii = SI_INFO(sih); + sb = REGS2SB(sii->curmap); + + sii->pub.socirev = + (R_SBREG(sii, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT; + + /* Save the current core info and validate it later till we know + * for sure what is good and what is bad. + */ + origsba = _sb_coresba(sii); + + /* scan all SB(s) starting from SI_ENUM_BASE */ + sii->numcores = _sb_scan(sii, origsba, regs, 0, SI_ENUM_BASE, 1); +} + +/* + * This function changes logical "focus" to the indicated core; + * must be called with interrupts off. + * Moreover, callers should keep interrupts off during switching out of + * and back to d11 core + */ +void *sb_setcoreidx(si_t *sih, uint coreidx) +{ + si_info_t *sii; + + sii = SI_INFO(sih); + + if (coreidx >= sii->numcores) + return NULL; + + /* + * If the user has provided an interrupt mask enabled function, + * then assert interrupts are disabled before switching the core. + */ + ASSERT((sii->intrsenabled_fn == NULL) + || !(*(sii)->intrsenabled_fn) ((sii)->intr_arg)); + + sii->curmap = _sb_setcoreidx(sii, coreidx); + sii->curidx = coreidx; + + return sii->curmap; +} + +/* This function changes the logical "focus" to the indicated core. + * Return the current core's virtual address. + */ +static void *_sb_setcoreidx(si_info_t *sii, uint coreidx) +{ + u32 sbaddr = sii->coresba[coreidx]; + void *regs; + + switch (BUSTYPE(sii->pub.bustype)) { +#ifdef BCMSDIO + case SPI_BUS: + case SDIO_BUS: + /* map new one */ + if (!sii->regs[coreidx]) { + sii->regs[coreidx] = (void *)sbaddr; + ASSERT(GOODREGS(sii->regs[coreidx])); + } + regs = sii->regs[coreidx]; + break; +#endif /* BCMSDIO */ + default: + ASSERT(0); + regs = NULL; + break; + } + + return regs; +} + +/* traverse all cores to find and clear source of serror */ +static void sb_serr_clear(si_info_t *sii) +{ + sbconfig_t *sb; + uint origidx; + uint i, intr_val = 0; + void *corereg = NULL; + + INTR_OFF(sii, intr_val); + origidx = si_coreidx(&sii->pub); + + for (i = 0; i < sii->numcores; i++) { + corereg = sb_setcoreidx(&sii->pub, i); + if (NULL != corereg) { + sb = REGS2SB(corereg); + if ((R_SBREG(sii, &sb->sbtmstatehigh)) & SBTMH_SERR) { + AND_SBREG(sii, &sb->sbtmstatehigh, ~SBTMH_SERR); + SI_ERROR(("sb_serr_clear: SError core 0x%x\n", + sb_coreid(&sii->pub))); + } + } + } + + sb_setcoreidx(&sii->pub, origidx); + INTR_RESTORE(sii, intr_val); +} + +/* + * Check if any inband, outband or timeout errors has happened and clear them. + * Must be called with chip clk on ! + */ +bool sb_taclear(si_t *sih, bool details) +{ + si_info_t *sii; + sbconfig_t *sb; + uint origidx; + uint intr_val = 0; + bool rc = false; + u32 inband = 0, serror = 0, timeout = 0; + void *corereg = NULL; + volatile u32 imstate, tmstate; + + sii = SI_INFO(sih); + + if ((BUSTYPE(sii->pub.bustype) == SDIO_BUS) || + (BUSTYPE(sii->pub.bustype) == SPI_BUS)) { + + INTR_OFF(sii, intr_val); + origidx = si_coreidx(sih); + + corereg = si_setcore(sih, PCMCIA_CORE_ID, 0); + if (NULL == corereg) + corereg = si_setcore(sih, SDIOD_CORE_ID, 0); + if (NULL != corereg) { + sb = REGS2SB(corereg); + + imstate = R_SBREG(sii, &sb->sbimstate); + if ((imstate != 0xffffffff) + && (imstate & (SBIM_IBE | SBIM_TO))) { + AND_SBREG(sii, &sb->sbimstate, + ~(SBIM_IBE | SBIM_TO)); + /* inband = imstate & SBIM_IBE; cmd error */ + timeout = imstate & SBIM_TO; + } + tmstate = R_SBREG(sii, &sb->sbtmstatehigh); + if ((tmstate != 0xffffffff) + && (tmstate & SBTMH_INT_STATUS)) { + sb_serr_clear(sii); + serror = 1; + OR_SBREG(sii, &sb->sbtmstatelow, SBTML_INT_ACK); + AND_SBREG(sii, &sb->sbtmstatelow, + ~SBTML_INT_ACK); + } + } + + sb_setcoreidx(sih, origidx); + INTR_RESTORE(sii, intr_val); + } + + if (inband | timeout | serror) { + rc = true; + SI_ERROR(("sb_taclear: inband 0x%x, serror 0x%x, timeout " + "0x%x!\n", inband, serror, timeout)); + } + + return rc; +} + +void sb_core_disable(si_t *sih, u32 bits) +{ + si_info_t *sii; + volatile u32 dummy; + sbconfig_t *sb; + + sii = SI_INFO(sih); + + ASSERT(GOODREGS(sii->curmap)); + sb = REGS2SB(sii->curmap); + + /* if core is already in reset, just return */ + if (R_SBREG(sii, &sb->sbtmstatelow) & SBTML_RESET) + return; + + /* if clocks are not enabled, put into reset and return */ + if ((R_SBREG(sii, &sb->sbtmstatelow) & + (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) == 0) + goto disable; + + /* set target reject and spin until busy is clear + (preserve core-specific bits) */ + OR_SBREG(sii, &sb->sbtmstatelow, SBTML_REJ); + dummy = R_SBREG(sii, &sb->sbtmstatelow); + udelay(1); + SPINWAIT((R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000); + if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY) + SI_ERROR(("%s: target state still busy\n", __func__)); + + if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) { + OR_SBREG(sii, &sb->sbimstate, SBIM_RJ); + dummy = R_SBREG(sii, &sb->sbimstate); + udelay(1); + SPINWAIT((R_SBREG(sii, &sb->sbimstate) & SBIM_BY), 100000); + } + + /* set reset and reject while enabling the clocks */ + W_SBREG(sii, &sb->sbtmstatelow, + (((bits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) | + SBTML_REJ | SBTML_RESET)); + dummy = R_SBREG(sii, &sb->sbtmstatelow); + udelay(10); + + /* don't forget to clear the initiator reject bit */ + if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) + AND_SBREG(sii, &sb->sbimstate, ~SBIM_RJ); + +disable: + /* leave reset and reject asserted */ + W_SBREG(sii, &sb->sbtmstatelow, + ((bits << SBTML_SICF_SHIFT) | SBTML_REJ | SBTML_RESET)); + udelay(1); +} + +/* reset and re-enable a core + * inputs: + * bits - core specific bits that are set during and after reset sequence + * resetbits - core specific bits that are set only during reset sequence + */ +void sb_core_reset(si_t *sih, u32 bits, u32 resetbits) +{ + si_info_t *sii; + sbconfig_t *sb; + volatile u32 dummy; + + sii = SI_INFO(sih); + ASSERT(GOODREGS(sii->curmap)); + sb = REGS2SB(sii->curmap); + + /* + * Must do the disable sequence first to work for + * arbitrary current core state. + */ + sb_core_disable(sih, (bits | resetbits)); + + /* + * Now do the initialization sequence. + */ + + /* set reset while enabling the clock and + forcing them on throughout the core */ + W_SBREG(sii, &sb->sbtmstatelow, + (((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) << + SBTML_SICF_SHIFT) | SBTML_RESET)); + dummy = R_SBREG(sii, &sb->sbtmstatelow); + udelay(1); + + if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_SERR) + W_SBREG(sii, &sb->sbtmstatehigh, 0); + + dummy = R_SBREG(sii, &sb->sbimstate); + if (dummy & (SBIM_IBE | SBIM_TO)) + AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO)); + + /* clear reset and allow it to propagate throughout the core */ + W_SBREG(sii, &sb->sbtmstatelow, + ((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) << + SBTML_SICF_SHIFT)); + dummy = R_SBREG(sii, &sb->sbtmstatelow); + udelay(1); + + /* leave clock enabled */ + W_SBREG(sii, &sb->sbtmstatelow, + ((bits | SICF_CLOCK_EN) << SBTML_SICF_SHIFT)); + dummy = R_SBREG(sii, &sb->sbtmstatelow); + udelay(1); +} + +u32 sb_base(u32 admatch) +{ + u32 base; + uint type; + + type = admatch & SBAM_TYPE_MASK; + ASSERT(type < 3); + + base = 0; + + if (type == 0) { + base = admatch & SBAM_BASE0_MASK; + } else if (type == 1) { + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */ + base = admatch & SBAM_BASE1_MASK; + } else if (type == 2) { + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */ + base = admatch & SBAM_BASE2_MASK; + } + + return base; +} diff --git a/drivers/staging/brcm80211/util/siutils.c b/drivers/staging/brcm80211/util/siutils.c new file mode 100644 index 0000000..f3ea7e1 --- /dev/null +++ b/drivers/staging/brcm80211/util/siutils.c @@ -0,0 +1,2021 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <bcmdefs.h> +#include <osl.h> +#include <linuxver.h> +#include <bcmutils.h> +#include <siutils.h> +#include <bcmdevs.h> +#include <hndsoc.h> +#include <sbchipc.h> +#include <pci_core.h> +#include <pcie_core.h> +#include <nicpci.h> +#include <bcmnvram.h> +#include <bcmsrom.h> +#include <pcicfg.h> +#include <sbsocram.h> +#ifdef BCMSDIO +#include <bcmsdh.h> +#include <sdio.h> +#include <sbsdio.h> +#include <sbhnddma.h> +#include <sbsdpcmdev.h> +#include <bcmsdpcm.h> +#endif /* BCMSDIO */ +#include <hndpmu.h> + +/* this file now contains only definitions for sb functions, only necessary +*for devices using Sonics backplanes (bcm4329) +*/ + +/* if an amba SDIO device is supported, please further restrict the inclusion + * of this file + */ +#ifdef BCMSDIO +#include "siutils_priv.h" +#endif + +/* local prototypes */ +static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh, + void *regs, uint bustype, void *sdh, char **vars, + uint *varsz); +static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, + void *sdh); +static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, + u32 savewin, uint *origidx, void *regs); +static void si_nvram_process(si_info_t *sii, char *pvars); + +/* dev path concatenation util */ +static char *si_devpathvar(si_t *sih, char *var, int len, const char *name); +static bool _si_clkctl_cc(si_info_t *sii, uint mode); +static bool si_ispcie(si_info_t *sii); +static uint socram_banksize(si_info_t *sii, sbsocramregs_t *r, + u8 idx, u8 mtype); + +/* global variable to indicate reservation/release of gpio's */ +static u32 si_gpioreservation; + +/* + * Allocate a si handle. + * devid - pci device id (used to determine chip#) + * osh - opaque OS handle + * regs - virtual address of initial core registers + * bustype - pci/sb/sdio/etc + * vars - pointer to a pointer area for "environment" variables + * varsz - pointer to int to return the size of the vars + */ +si_t *si_attach(uint devid, osl_t *osh, void *regs, uint bustype, void *sdh, + char **vars, uint *varsz) +{ + si_info_t *sii; + + /* alloc si_info_t */ + sii = kmalloc(sizeof(si_info_t), GFP_ATOMIC); + if (sii == NULL) { + SI_ERROR(("si_attach: malloc failed!\n")); + return NULL; + } + + if (si_doattach(sii, devid, osh, regs, bustype, sdh, vars, varsz) == + NULL) { + kfree(sii); + return NULL; + } + sii->vars = vars ? *vars : NULL; + sii->varsz = varsz ? *varsz : 0; + + return (si_t *) sii; +} + +/* global kernel resource */ +static si_info_t ksii; + +static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, + void *sdh) +{ + +#ifndef BRCM_FULLMAC + /* kludge to enable the clock on the 4306 which lacks a slowclock */ + if (BUSTYPE(bustype) == PCI_BUS && !si_ispcie(sii)) + si_clkctl_xtal(&sii->pub, XTAL | PLL, ON); +#endif + +#if defined(BCMSDIO) + if (BUSTYPE(bustype) == SDIO_BUS) { + int err; + u8 clkset; + + /* Try forcing SDIO core to do ALPAvail request only */ + clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; + bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, + clkset, &err); + if (!err) { + u8 clkval; + + /* If register supported, wait for ALPAvail and then force ALP */ + clkval = + bcmsdh_cfg_read(sdh, SDIO_FUNC_1, + SBSDIO_FUNC1_CHIPCLKCSR, NULL); + if ((clkval & ~SBSDIO_AVBITS) == clkset) { + SPINWAIT(((clkval = + bcmsdh_cfg_read(sdh, SDIO_FUNC_1, + SBSDIO_FUNC1_CHIPCLKCSR, + NULL)), + !SBSDIO_ALPAV(clkval)), + PMU_MAX_TRANSITION_DLY); + if (!SBSDIO_ALPAV(clkval)) { + SI_ERROR(("timeout on ALPAV wait, clkval 0x%02x\n", clkval)); + return false; + } + clkset = + SBSDIO_FORCE_HW_CLKREQ_OFF | + SBSDIO_FORCE_ALP; + bcmsdh_cfg_write(sdh, SDIO_FUNC_1, + SBSDIO_FUNC1_CHIPCLKCSR, + clkset, &err); + udelay(65); + } + } + + /* Also, disable the extra SDIO pull-ups */ + bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0, + NULL); + } +#endif /* defined(BCMSDIO) */ + + return true; +} + +static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, + u32 savewin, uint *origidx, void *regs) +{ + bool pci, pcie; + uint i; + uint pciidx, pcieidx, pcirev, pcierev; + + cc = si_setcoreidx(&sii->pub, SI_CC_IDX); + ASSERT(cc); + + /* get chipcommon rev */ + sii->pub.ccrev = (int)si_corerev(&sii->pub); + + /* get chipcommon chipstatus */ + if (sii->pub.ccrev >= 11) + sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus); + + /* get chipcommon capabilites */ + sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities); + /* get chipcommon extended capabilities */ + +#ifndef BRCM_FULLMAC + if (sii->pub.ccrev >= 35) + sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext); +#endif + /* get pmu rev and caps */ + if (sii->pub.cccaps & CC_CAP_PMU) { + sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities); + sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK; + } + + /* + SI_MSG(("Chipc: rev %d, caps 0x%x, chipst 0x%x pmurev %d, pmucaps 0x%x\n", + sii->pub.ccrev, sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev, + sii->pub.pmucaps)); + */ + + /* figure out bus/orignal core idx */ + sii->pub.buscoretype = NODEV_CORE_ID; + sii->pub.buscorerev = NOREV; + sii->pub.buscoreidx = BADIDX; + + pci = pcie = false; + pcirev = pcierev = NOREV; + pciidx = pcieidx = BADIDX; + + for (i = 0; i < sii->numcores; i++) { + uint cid, crev; + + si_setcoreidx(&sii->pub, i); + cid = si_coreid(&sii->pub); + crev = si_corerev(&sii->pub); + + /* Display cores found */ + SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n", + i, cid, crev, sii->coresba[i], sii->regs[i])); + + if (BUSTYPE(bustype) == PCI_BUS) { + if (cid == PCI_CORE_ID) { + pciidx = i; + pcirev = crev; + pci = true; + } else if (cid == PCIE_CORE_ID) { + pcieidx = i; + pcierev = crev; + pcie = true; + } + } +#ifdef BCMSDIO + else if (((BUSTYPE(bustype) == SDIO_BUS) || + (BUSTYPE(bustype) == SPI_BUS)) && + ((cid == PCMCIA_CORE_ID) || (cid == SDIOD_CORE_ID))) { + sii->pub.buscorerev = crev; + sii->pub.buscoretype = cid; + sii->pub.buscoreidx = i; + } +#endif /* BCMSDIO */ + + /* find the core idx before entering this func. */ + if ((savewin && (savewin == sii->coresba[i])) || + (regs == sii->regs[i])) + *origidx = i; + } + +#ifdef BRCM_FULLMAC + SI_MSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, + sii->pub.buscoretype, sii->pub.buscorerev)); + + /* Make sure any on-chip ARM is off (in case strapping is wrong), + * or downloaded code was + * already running. + */ + if ((BUSTYPE(bustype) == SDIO_BUS) || (BUSTYPE(bustype) == SPI_BUS)) { + if (si_setcore(&sii->pub, ARM7S_CORE_ID, 0) || + si_setcore(&sii->pub, ARMCM3_CORE_ID, 0)) + si_core_disable(&sii->pub, 0); + } +#else + if (pci && pcie) { + if (si_ispcie(sii)) + pci = false; + else + pcie = false; + } + if (pci) { + sii->pub.buscoretype = PCI_CORE_ID; + sii->pub.buscorerev = pcirev; + sii->pub.buscoreidx = pciidx; + } else if (pcie) { + sii->pub.buscoretype = PCIE_CORE_ID; + sii->pub.buscorerev = pcierev; + sii->pub.buscoreidx = pcieidx; + } + + SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, + sii->pub.buscoretype, sii->pub.buscorerev)); + + /* fixup necessary chip/core configurations */ + if (BUSTYPE(sii->pub.bustype) == PCI_BUS) { + if (SI_FAST(sii)) { + if (!sii->pch) { + sii->pch = (void *)pcicore_init( + &sii->pub, sii->osh, + (void *)PCIEREGS(sii)); + if (sii->pch == NULL) + return false; + } + } + if (si_pci_fixcfg(&sii->pub)) { + SI_ERROR(("si_doattach: sb_pci_fixcfg failed\n")); + return false; + } + } +#endif + /* return to the original core */ + si_setcoreidx(&sii->pub, *origidx); + + return true; +} + +static __used void si_nvram_process(si_info_t *sii, char *pvars) +{ + uint w = 0; + + /* get boardtype and boardrev */ + switch (BUSTYPE(sii->pub.bustype)) { + case PCI_BUS: + /* do a pci config read to get subsystem id and subvendor id */ + w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(u32)); + /* Let nvram variables override subsystem Vend/ID */ + sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub, + "boardvendor"); + if (sii->pub.boardvendor == 0) + sii->pub.boardvendor = w & 0xffff; + else + SI_ERROR(("Overriding boardvendor: 0x%x instead of 0x%x\n", sii->pub.boardvendor, w & 0xffff)); + sii->pub.boardtype = (u16)si_getdevpathintvar(&sii->pub, + "boardtype"); + if (sii->pub.boardtype == 0) + sii->pub.boardtype = (w >> 16) & 0xffff; + else + SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n", sii->pub.boardtype, (w >> 16) & 0xffff)); + break; + +#ifdef BCMSDIO + case SDIO_BUS: +#endif + sii->pub.boardvendor = getintvar(pvars, "manfid"); + sii->pub.boardtype = getintvar(pvars, "prodid"); + break; + +#ifdef BCMSDIO + case SPI_BUS: + sii->pub.boardvendor = VENDOR_BROADCOM; + sii->pub.boardtype = SPI_BOARD; + break; +#endif + + case SI_BUS: + case JTAG_BUS: + sii->pub.boardvendor = VENDOR_BROADCOM; + sii->pub.boardtype = getintvar(pvars, "prodid"); + if (pvars == NULL || (sii->pub.boardtype == 0)) { + sii->pub.boardtype = getintvar(NULL, "boardtype"); + if (sii->pub.boardtype == 0) + sii->pub.boardtype = 0xffff; + } + break; + } + + if (sii->pub.boardtype == 0) { + SI_ERROR(("si_doattach: unknown board type\n")); + ASSERT(sii->pub.boardtype); + } + + sii->pub.boardflags = getintvar(pvars, "boardflags"); +} + +/* this is will make Sonics calls directly, since Sonics is no longer supported in the Si abstraction */ +/* this has been customized for the bcm 4329 ONLY */ +#ifdef BCMSDIO +static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh, + void *regs, uint bustype, void *sdh, + char **vars, uint *varsz) +{ + struct si_pub *sih = &sii->pub; + u32 w, savewin; + chipcregs_t *cc; + char *pvars = NULL; + uint origidx; + + ASSERT(GOODREGS(regs)); + + bzero((unsigned char *) sii, sizeof(si_info_t)); + + savewin = 0; + + sih->buscoreidx = BADIDX; + + sii->curmap = regs; + sii->sdh = sdh; + sii->osh = osh; + + /* find Chipcommon address */ + cc = (chipcregs_t *) sii->curmap; + sih->bustype = bustype; + + if (bustype != BUSTYPE(bustype)) { + SI_ERROR(("si_doattach: bus type %d does not match configured bus type %d\n", bustype, BUSTYPE(bustype))); + return NULL; + } + + /* bus/core/clk setup for register access */ + if (!si_buscore_prep(sii, bustype, devid, sdh)) { + SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n", + bustype)); + return NULL; + } + + /* ChipID recognition. + * We assume we can read chipid at offset 0 from the regs arg. + * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon), + * some way of recognizing them needs to be added here. + */ + w = R_REG(osh, &cc->chipid); + sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT; + /* Might as wll fill in chip id rev & pkg */ + sih->chip = w & CID_ID_MASK; + sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT; + sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT; + + if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) && + (sih->chippkg != BCM4329_289PIN_PKG_ID)) + sih->chippkg = BCM4329_182PIN_PKG_ID; + + sih->issim = IS_SIM(sih->chippkg); + + /* scan for cores */ + /* SI_MSG(("Found chip type SB (0x%08x)\n", w)); */ + sb_scan(&sii->pub, regs, devid); + + /* no cores found, bail out */ + if (sii->numcores == 0) { + SI_ERROR(("si_doattach: could not find any cores\n")); + return NULL; + } + /* bus/core/clk setup */ + origidx = SI_CC_IDX; + if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) { + SI_ERROR(("si_doattach: si_buscore_setup failed\n")); + goto exit; + } + +#ifdef BRCM_FULLMAC + pvars = NULL; +#else + /* Init nvram from flash if it exists */ + nvram_init((void *)&(sii->pub)); + + /* Init nvram from sprom/otp if they exist */ + if (srom_var_init + (&sii->pub, BUSTYPE(bustype), regs, sii->osh, vars, varsz)) { + SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n")); + goto exit; + } + pvars = vars ? *vars : NULL; + si_nvram_process(sii, pvars); +#endif + + /* === NVRAM, clock is ready === */ + +#ifdef BRCM_FULLMAC + if (sii->pub.ccrev >= 20) { +#endif + cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); + W_REG(osh, &cc->gpiopullup, 0); + W_REG(osh, &cc->gpiopulldown, 0); + sb_setcoreidx(sih, origidx); +#ifdef BRCM_FULLMAC + } +#endif + +#ifndef BRCM_FULLMAC + /* PMU specific initializations */ + if (PMUCTL_ENAB(sih)) { + u32 xtalfreq; + si_pmu_init(sih, sii->osh); + si_pmu_chip_init(sih, sii->osh); + xtalfreq = getintvar(pvars, "xtalfreq"); + /* If xtalfreq var not available, try to measure it */ + if (xtalfreq == 0) + xtalfreq = si_pmu_measure_alpclk(sih, sii->osh); + si_pmu_pll_init(sih, sii->osh, xtalfreq); + si_pmu_res_init(sih, sii->osh); + si_pmu_swreg_init(sih, sii->osh); + } + + /* setup the GPIO based LED powersave register */ + w = getintvar(pvars, "leddc"); + if (w == 0) + w = DEFAULT_GPIOTIMERVAL; + sb_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w); + +#ifdef BCMDBG + /* clear any previous epidiag-induced target abort */ + sb_taclear(sih, false); +#endif /* BCMDBG */ +#endif + + return sii; + + exit: + return NULL; +} + +#else /* BCMSDIO */ +static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh, + void *regs, uint bustype, void *sdh, + char **vars, uint *varsz) +{ + struct si_pub *sih = &sii->pub; + u32 w, savewin; + chipcregs_t *cc; + char *pvars = NULL; + uint origidx; + + ASSERT(GOODREGS(regs)); + + bzero((unsigned char *) sii, sizeof(si_info_t)); + + savewin = 0; + + sih->buscoreidx = BADIDX; + + sii->curmap = regs; + sii->sdh = sdh; + sii->osh = osh; + + /* check to see if we are a si core mimic'ing a pci core */ + if ((bustype == PCI_BUS) && + (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(u32)) == + 0xffffffff)) { + SI_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SI " "devid:0x%x\n", __func__, devid)); + bustype = SI_BUS; + } + + /* find Chipcommon address */ + if (bustype == PCI_BUS) { + savewin = + OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(u32)); + if (!GOODCOREADDR(savewin, SI_ENUM_BASE)) + savewin = SI_ENUM_BASE; + OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE); + cc = (chipcregs_t *) regs; + } else { + cc = (chipcregs_t *) REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE); + } + + sih->bustype = bustype; + if (bustype != BUSTYPE(bustype)) { + SI_ERROR(("si_doattach: bus type %d does not match configured bus type %d\n", bustype, BUSTYPE(bustype))); + return NULL; + } + + /* bus/core/clk setup for register access */ + if (!si_buscore_prep(sii, bustype, devid, sdh)) { + SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n", + bustype)); + return NULL; + } + + /* ChipID recognition. + * We assume we can read chipid at offset 0 from the regs arg. + * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon), + * some way of recognizing them needs to be added here. + */ + w = R_REG(osh, &cc->chipid); + sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT; + /* Might as wll fill in chip id rev & pkg */ + sih->chip = w & CID_ID_MASK; + sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT; + sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT; + + sih->issim = IS_SIM(sih->chippkg); + + /* scan for cores */ + if (CHIPTYPE(sii->pub.socitype) == SOCI_AI) { + SI_MSG(("Found chip type AI (0x%08x)\n", w)); + /* pass chipc address instead of original core base */ + ai_scan(&sii->pub, (void *)cc, devid); + } else { + SI_ERROR(("Found chip of unknown type (0x%08x)\n", w)); + return NULL; + } + /* no cores found, bail out */ + if (sii->numcores == 0) { + SI_ERROR(("si_doattach: could not find any cores\n")); + return NULL; + } + /* bus/core/clk setup */ + origidx = SI_CC_IDX; + if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) { + SI_ERROR(("si_doattach: si_buscore_setup failed\n")); + goto exit; + } + + /* assume current core is CC */ + if ((sii->pub.ccrev == 0x25) + && + ((CHIPID(sih->chip) == BCM43236_CHIP_ID + || CHIPID(sih->chip) == BCM43235_CHIP_ID + || CHIPID(sih->chip) == BCM43238_CHIP_ID) + && (CHIPREV(sii->pub.chiprev) <= 2))) { + + if ((cc->chipstatus & CST43236_BP_CLK) != 0) { + uint clkdiv; + clkdiv = R_REG(osh, &cc->clkdiv); + /* otp_clk_div is even number, 120/14 < 9mhz */ + clkdiv = (clkdiv & ~CLKD_OTP) | (14 << CLKD_OTP_SHIFT); + W_REG(osh, &cc->clkdiv, clkdiv); + SI_ERROR(("%s: set clkdiv to %x\n", __func__, clkdiv)); + } + udelay(10); + } + + /* Init nvram from flash if it exists */ + nvram_init((void *)&(sii->pub)); + + /* Init nvram from sprom/otp if they exist */ + if (srom_var_init + (&sii->pub, BUSTYPE(bustype), regs, sii->osh, vars, varsz)) { + SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n")); + goto exit; + } + pvars = vars ? *vars : NULL; + si_nvram_process(sii, pvars); + + /* === NVRAM, clock is ready === */ + cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); + W_REG(osh, &cc->gpiopullup, 0); + W_REG(osh, &cc->gpiopulldown, 0); + si_setcoreidx(sih, origidx); + + /* PMU specific initializations */ + if (PMUCTL_ENAB(sih)) { + u32 xtalfreq; + si_pmu_init(sih, sii->osh); + si_pmu_chip_init(sih, sii->osh); + xtalfreq = getintvar(pvars, "xtalfreq"); + /* If xtalfreq var not available, try to measure it */ + if (xtalfreq == 0) + xtalfreq = si_pmu_measure_alpclk(sih, sii->osh); + si_pmu_pll_init(sih, sii->osh, xtalfreq); + si_pmu_res_init(sih, sii->osh); + si_pmu_swreg_init(sih, sii->osh); + } + + /* setup the GPIO based LED powersave register */ + w = getintvar(pvars, "leddc"); + if (w == 0) + w = DEFAULT_GPIOTIMERVAL; + si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w); + + if (PCIE(sii)) { + ASSERT(sii->pch != NULL); + pcicore_attach(sii->pch, pvars, SI_DOATTACH); + } + + if ((CHIPID(sih->chip) == BCM43224_CHIP_ID) || + (CHIPID(sih->chip) == BCM43421_CHIP_ID)) { + /* enable 12 mA drive strenth for 43224 and set chipControl register bit 15 */ + if (CHIPREV(sih->chiprev) == 0) { + SI_MSG(("Applying 43224A0 WARs\n")); + si_corereg(sih, SI_CC_IDX, + offsetof(chipcregs_t, chipcontrol), + CCTRL43224_GPIO_TOGGLE, + CCTRL43224_GPIO_TOGGLE); + si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE, + CCTRL_43224A0_12MA_LED_DRIVE); + } + if (CHIPREV(sih->chiprev) >= 1) { + SI_MSG(("Applying 43224B0+ WARs\n")); + si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE, + CCTRL_43224B0_12MA_LED_DRIVE); + } + } + + if (CHIPID(sih->chip) == BCM4313_CHIP_ID) { + /* enable 12 mA drive strenth for 4313 and set chipControl register bit 1 */ + SI_MSG(("Applying 4313 WARs\n")); + si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE, + CCTRL_4313_12MA_LED_DRIVE); + } + + if (CHIPID(sih->chip) == BCM4331_CHIP_ID) { + /* Enable Ext PA lines depending on chip package option */ + si_chipcontrl_epa4331(sih, true); + } + + return sii; + exit: + if (BUSTYPE(sih->bustype) == PCI_BUS) { + if (sii->pch) + pcicore_deinit(sii->pch); + sii->pch = NULL; + } + + return NULL; +} +#endif /* BCMSDIO */ + +/* may be called with core in reset */ +void si_detach(si_t *sih) +{ + si_info_t *sii; + uint idx; + + struct si_pub *si_local = NULL; + bcopy(&sih, &si_local, sizeof(si_t **)); + + sii = SI_INFO(sih); + + if (sii == NULL) + return; + + if (BUSTYPE(sih->bustype) == SI_BUS) + for (idx = 0; idx < SI_MAXCORES; idx++) + if (sii->regs[idx]) { + REG_UNMAP(sii->regs[idx]); + sii->regs[idx] = NULL; + } + +#ifndef BRCM_FULLMAC + nvram_exit((void *)si_local); /* free up nvram buffers */ + + if (BUSTYPE(sih->bustype) == PCI_BUS) { + if (sii->pch) + pcicore_deinit(sii->pch); + sii->pch = NULL; + } +#endif +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS) + if (sii != &ksii) +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */ + kfree(sii); +} + +void *si_osh(si_t *sih) +{ + si_info_t *sii; + + sii = SI_INFO(sih); + return sii->osh; +} + +/* register driver interrupt disabling and restoring callback functions */ +void +si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn, + void *intrsenabled_fn, void *intr_arg) +{ + si_info_t *sii; + + sii = SI_INFO(sih); + sii->intr_arg = intr_arg; + sii->intrsoff_fn = (si_intrsoff_t) intrsoff_fn; + sii->intrsrestore_fn = (si_intrsrestore_t) intrsrestore_fn; + sii->intrsenabled_fn = (si_intrsenabled_t) intrsenabled_fn; + /* save current core id. when this function called, the current core + * must be the core which provides driver functions(il, et, wl, etc.) + */ + sii->dev_coreid = sii->coreid[sii->curidx]; +} + +void si_deregister_intr_callback(si_t *sih) +{ + si_info_t *sii; + + sii = SI_INFO(sih); + sii->intrsoff_fn = NULL; +} + +uint si_flag(si_t *sih) +{ + if (CHIPTYPE(sih->socitype) == SOCI_AI) + return ai_flag(sih); + else { + ASSERT(0); + return 0; + } +} + +void si_setint(si_t *sih, int siflag) +{ + if (CHIPTYPE(sih->socitype) == SOCI_AI) + ai_setint(sih, siflag); + else + ASSERT(0); +} + +#ifndef BCMSDIO +uint si_coreid(si_t *sih) +{ + si_info_t *sii; + + sii = SI_INFO(sih); + return sii->coreid[sii->curidx]; +} +#endif + +uint si_coreidx(si_t *sih) +{ + si_info_t *sii; + + sii = SI_INFO(sih); + return sii->curidx; +} + +bool si_backplane64(si_t *sih) +{ + return (sih->cccaps & CC_CAP_BKPLN64) != 0; +} + +#ifndef BCMSDIO +uint si_corerev(si_t *sih) +{ + if (CHIPTYPE(sih->socitype) == SOCI_AI) + return ai_corerev(sih); + else { + ASSERT(0); + return 0; + } +} +#endif + +/* return index of coreid or BADIDX if not found */ +uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit) +{ + si_info_t *sii; + uint found; + uint i; + + sii = SI_INFO(sih); + + found = 0; + + for (i = 0; i < sii->numcores; i++) + if (sii->coreid[i] == coreid) { + if (found == coreunit) + return i; + found++; + } + + return BADIDX; +} + +/* + * This function changes logical "focus" to the indicated core; + * must be called with interrupts off. + * Moreover, callers should keep interrupts off during switching out of and back to d11 core + */ +void *si_setcore(si_t *sih, uint coreid, uint coreunit) +{ + uint idx; + + idx = si_findcoreidx(sih, coreid, coreunit); + if (!GOODIDX(idx)) + return NULL; + + if (CHIPTYPE(sih->socitype) == SOCI_AI) + return ai_setcoreidx(sih, idx); + else { +#ifdef BCMSDIO + return sb_setcoreidx(sih, idx); +#else + ASSERT(0); + return NULL; +#endif + } +} + +#ifndef BCMSDIO +void *si_setcoreidx(si_t *sih, uint coreidx) +{ + if (CHIPTYPE(sih->socitype) == SOCI_AI) + return ai_setcoreidx(sih, coreidx); + else { + ASSERT(0); + return NULL; + } +} +#endif + +/* Turn off interrupt as required by sb_setcore, before switch core */ +void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val) +{ + void *cc; + si_info_t *sii; + + sii = SI_INFO(sih); + + if (SI_FAST(sii)) { + /* Overloading the origidx variable to remember the coreid, + * this works because the core ids cannot be confused with + * core indices. + */ + *origidx = coreid; + if (coreid == CC_CORE_ID) + return (void *)CCREGS_FAST(sii); + else if (coreid == sih->buscoretype) + return (void *)PCIEREGS(sii); + } + INTR_OFF(sii, *intr_val); + *origidx = sii->curidx; + cc = si_setcore(sih, coreid, 0); + ASSERT(cc != NULL); + + return cc; +} + +/* restore coreidx and restore interrupt */ +void si_restore_core(si_t *sih, uint coreid, uint intr_val) +{ + si_info_t *sii; + + sii = SI_INFO(sih); + if (SI_FAST(sii) + && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype))) + return; + + si_setcoreidx(sih, coreid); + INTR_RESTORE(sii, intr_val); +} + +u32 si_core_cflags(si_t *sih, u32 mask, u32 val) +{ + if (CHIPTYPE(sih->socitype) == SOCI_AI) + return ai_core_cflags(sih, mask, val); + else { + ASSERT(0); + return 0; + } +} + +u32 si_core_sflags(si_t *sih, u32 mask, u32 val) +{ + if (CHIPTYPE(sih->socitype) == SOCI_AI) + return ai_core_sflags(sih, mask, val); + else { + ASSERT(0); + return 0; + } +} + +bool si_iscoreup(si_t *sih) +{ + if (CHIPTYPE(sih->socitype) == SOCI_AI) + return ai_iscoreup(sih); + else { +#ifdef BCMSDIO + return sb_iscoreup(sih); +#else + ASSERT(0); + return false; +#endif + } +} + +void si_write_wrapperreg(si_t *sih, u32 offset, u32 val) +{ + /* only for 4319, no requirement for SOCI_SB */ + if (CHIPTYPE(sih->socitype) == SOCI_AI) { + ai_write_wrap_reg(sih, offset, val); + } +} + +uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) +{ + + if (CHIPTYPE(sih->socitype) == SOCI_AI) + return ai_corereg(sih, coreidx, regoff, mask, val); + else { +#ifdef BCMSDIO + return sb_corereg(sih, coreidx, regoff, mask, val); +#else + ASSERT(0); + return 0; +#endif + } +} + +void si_core_disable(si_t *sih, u32 bits) +{ + + if (CHIPTYPE(sih->socitype) == SOCI_AI) + ai_core_disable(sih, bits); +#ifdef BCMSDIO + else + sb_core_disable(sih, bits); +#endif +} + +void si_core_reset(si_t *sih, u32 bits, u32 resetbits) +{ + if (CHIPTYPE(sih->socitype) == SOCI_AI) + ai_core_reset(sih, bits, resetbits); +#ifdef BCMSDIO + else + sb_core_reset(sih, bits, resetbits); +#endif +} + +u32 si_alp_clock(si_t *sih) +{ + if (PMUCTL_ENAB(sih)) + return si_pmu_alp_clock(sih, si_osh(sih)); + + return ALP_CLOCK; +} + +u32 si_ilp_clock(si_t *sih) +{ + if (PMUCTL_ENAB(sih)) + return si_pmu_ilp_clock(sih, si_osh(sih)); + + return ILP_CLOCK; +} + +/* set chip watchdog reset timer to fire in 'ticks' */ +#ifdef BRCM_FULLMAC +void +si_watchdog(si_t *sih, uint ticks) +{ + if (PMUCTL_ENAB(sih)) { + + if ((sih->chip == BCM4319_CHIP_ID) && (sih->chiprev == 0) && + (ticks != 0)) { + si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, + clk_ctl_st), ~0, 0x2); + si_setcore(sih, USB20D_CORE_ID, 0); + si_core_disable(sih, 1); + si_setcore(sih, CC_CORE_ID, 0); + } + + if (ticks == 1) + ticks = 2; + si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog), + ~0, ticks); + } else { + /* instant NMI */ + si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog), + ~0, ticks); + } +} +#else +void si_watchdog(si_t *sih, uint ticks) +{ + uint nb, maxt; + + if (PMUCTL_ENAB(sih)) { + + if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) && + (CHIPREV(sih->chiprev) == 0) && (ticks != 0)) { + si_corereg(sih, SI_CC_IDX, + offsetof(chipcregs_t, clk_ctl_st), ~0, 0x2); + si_setcore(sih, USB20D_CORE_ID, 0); + si_core_disable(sih, 1); + si_setcore(sih, CC_CORE_ID, 0); + } + + nb = (sih->ccrev < 26) ? 16 : ((sih->ccrev >= 37) ? 32 : 24); + /* The mips compiler uses the sllv instruction, + * so we specially handle the 32-bit case. + */ + if (nb == 32) + maxt = 0xffffffff; + else + maxt = ((1 << nb) - 1); + + if (ticks == 1) + ticks = 2; + else if (ticks > maxt) + ticks = maxt; + + si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog), + ~0, ticks); + } else { + /* make sure we come up in fast clock mode; or if clearing, clear clock */ + si_clkctl_cc(sih, ticks ? CLK_FAST : CLK_DYNAMIC); + maxt = (1 << 28) - 1; + if (ticks > maxt) + ticks = maxt; + + si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog), ~0, + ticks); + } +} +#endif + +/* return the slow clock source - LPO, XTAL, or PCI */ +static uint si_slowclk_src(si_info_t *sii) +{ + chipcregs_t *cc; + + ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID); + + if (sii->pub.ccrev < 6) { + if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) && + (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(u32)) + & PCI_CFG_GPIO_SCS)) + return SCC_SS_PCI; + else + return SCC_SS_XTAL; + } else if (sii->pub.ccrev < 10) { + cc = (chipcregs_t *) si_setcoreidx(&sii->pub, sii->curidx); + return R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK; + } else /* Insta-clock */ + return SCC_SS_XTAL; +} + +/* return the ILP (slowclock) min or max frequency */ +static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc) +{ + u32 slowclk; + uint div; + + ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID); + + /* shouldn't be here unless we've established the chip has dynamic clk control */ + ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL); + + slowclk = si_slowclk_src(sii); + if (sii->pub.ccrev < 6) { + if (slowclk == SCC_SS_PCI) + return max_freq ? (PCIMAXFREQ / 64) + : (PCIMINFREQ / 64); + else + return max_freq ? (XTALMAXFREQ / 32) + : (XTALMINFREQ / 32); + } else if (sii->pub.ccrev < 10) { + div = 4 * + (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> + SCC_CD_SHIFT) + 1); + if (slowclk == SCC_SS_LPO) + return max_freq ? LPOMAXFREQ : LPOMINFREQ; + else if (slowclk == SCC_SS_XTAL) + return max_freq ? (XTALMAXFREQ / div) + : (XTALMINFREQ / div); + else if (slowclk == SCC_SS_PCI) + return max_freq ? (PCIMAXFREQ / div) + : (PCIMINFREQ / div); + else + ASSERT(0); + } else { + /* Chipc rev 10 is InstaClock */ + div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT; + div = 4 * (div + 1); + return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div); + } + return 0; +} + +static void si_clkctl_setdelay(si_info_t *sii, void *chipcregs) +{ + chipcregs_t *cc = (chipcregs_t *) chipcregs; + uint slowmaxfreq, pll_delay, slowclk; + uint pll_on_delay, fref_sel_delay; + + pll_delay = PLL_DELAY; + + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay + * since the xtal will also be powered down by dynamic clk control logic. + */ + + slowclk = si_slowclk_src(sii); + if (slowclk != SCC_SS_XTAL) + pll_delay += XTAL_ON_DELAY; + + /* Starting with 4318 it is ILP that is used for the delays */ + slowmaxfreq = + si_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? false : true, cc); + + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000; + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000; + + W_REG(sii->osh, &cc->pll_on_delay, pll_on_delay); + W_REG(sii->osh, &cc->fref_sel_delay, fref_sel_delay); +} + +/* initialize power control delay registers */ +void si_clkctl_init(si_t *sih) +{ + si_info_t *sii; + uint origidx = 0; + chipcregs_t *cc; + bool fast; + + if (!CCCTL_ENAB(sih)) + return; + + sii = SI_INFO(sih); + fast = SI_FAST(sii); + if (!fast) { + origidx = sii->curidx; + cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); + if (cc == NULL) + return; + } else { + cc = (chipcregs_t *) CCREGS_FAST(sii); + if (cc == NULL) + return; + } + ASSERT(cc != NULL); + + /* set all Instaclk chip ILP to 1 MHz */ + if (sih->ccrev >= 10) + SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK, + (ILP_DIV_1MHZ << SYCC_CD_SHIFT)); + + si_clkctl_setdelay(sii, (void *)cc); + + if (!fast) + si_setcoreidx(sih, origidx); +} + +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */ +u16 si_clkctl_fast_pwrup_delay(si_t *sih) +{ + si_info_t *sii; + uint origidx = 0; + chipcregs_t *cc; + uint slowminfreq; + u16 fpdelay; + uint intr_val = 0; + bool fast; + + sii = SI_INFO(sih); + if (PMUCTL_ENAB(sih)) { + INTR_OFF(sii, intr_val); + fpdelay = si_pmu_fast_pwrup_delay(sih, sii->osh); + INTR_RESTORE(sii, intr_val); + return fpdelay; + } + + if (!CCCTL_ENAB(sih)) + return 0; + + fast = SI_FAST(sii); + fpdelay = 0; + if (!fast) { + origidx = sii->curidx; + INTR_OFF(sii, intr_val); + cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); + if (cc == NULL) + goto done; + } else { + cc = (chipcregs_t *) CCREGS_FAST(sii); + if (cc == NULL) + goto done; + } + ASSERT(cc != NULL); + + slowminfreq = si_slowclk_freq(sii, false, cc); + fpdelay = (((R_REG(sii->osh, &cc->pll_on_delay) + 2) * 1000000) + + (slowminfreq - 1)) / slowminfreq; + + done: + if (!fast) { + si_setcoreidx(sih, origidx); + INTR_RESTORE(sii, intr_val); + } + return fpdelay; +} + +/* turn primary xtal and/or pll off/on */ +int si_clkctl_xtal(si_t *sih, uint what, bool on) +{ + si_info_t *sii; + u32 in, out, outen; + + sii = SI_INFO(sih); + + switch (BUSTYPE(sih->bustype)) { + +#ifdef BCMSDIO + case SDIO_BUS: + return -1; +#endif /* BCMSDIO */ + + case PCI_BUS: + /* pcie core doesn't have any mapping to control the xtal pu */ + if (PCIE(sii)) + return -1; + + in = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_IN, sizeof(u32)); + out = + OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(u32)); + outen = + OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUTEN, + sizeof(u32)); + + /* + * Avoid glitching the clock if GPRS is already using it. + * We can't actually read the state of the PLLPD so we infer it + * by the value of XTAL_PU which *is* readable via gpioin. + */ + if (on && (in & PCI_CFG_GPIO_XTAL)) + return 0; + + if (what & XTAL) + outen |= PCI_CFG_GPIO_XTAL; + if (what & PLL) + outen |= PCI_CFG_GPIO_PLL; + + if (on) { + /* turn primary xtal on */ + if (what & XTAL) { + out |= PCI_CFG_GPIO_XTAL; + if (what & PLL) + out |= PCI_CFG_GPIO_PLL; + OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, + sizeof(u32), out); + OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN, + sizeof(u32), outen); + udelay(XTAL_ON_DELAY); + } + + /* turn pll on */ + if (what & PLL) { + out &= ~PCI_CFG_GPIO_PLL; + OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, + sizeof(u32), out); + mdelay(2); + } + } else { + if (what & XTAL) + out &= ~PCI_CFG_GPIO_XTAL; + if (what & PLL) + out |= PCI_CFG_GPIO_PLL; + OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, + sizeof(u32), out); + OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN, + sizeof(u32), outen); + } + + default: + return -1; + } + + return 0; +} + +/* + * clock control policy function throught chipcommon + * + * set dynamic clk control mode (forceslow, forcefast, dynamic) + * returns true if we are forcing fast clock + * this is a wrapper over the next internal function + * to allow flexible policy settings for outside caller + */ +bool si_clkctl_cc(si_t *sih, uint mode) +{ + si_info_t *sii; + + sii = SI_INFO(sih); + + /* chipcommon cores prior to rev6 don't support dynamic clock control */ + if (sih->ccrev < 6) + return false; + + if (PCI_FORCEHT(sii)) + return mode == CLK_FAST; + + return _si_clkctl_cc(sii, mode); +} + +/* clk control mechanism through chipcommon, no policy checking */ +static bool _si_clkctl_cc(si_info_t *sii, uint mode) +{ + uint origidx = 0; + chipcregs_t *cc; + u32 scc; + uint intr_val = 0; + bool fast = SI_FAST(sii); + + /* chipcommon cores prior to rev6 don't support dynamic clock control */ + if (sii->pub.ccrev < 6) + return false; + + /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */ + ASSERT(sii->pub.ccrev != 10); + + if (!fast) { + INTR_OFF(sii, intr_val); + origidx = sii->curidx; + + if ((BUSTYPE(sii->pub.bustype) == SI_BUS) && + si_setcore(&sii->pub, MIPS33_CORE_ID, 0) && + (si_corerev(&sii->pub) <= 7) && (sii->pub.ccrev >= 10)) + goto done; + + cc = (chipcregs_t *) si_setcore(&sii->pub, CC_CORE_ID, 0); + } else { + cc = (chipcregs_t *) CCREGS_FAST(sii); + if (cc == NULL) + goto done; + } + ASSERT(cc != NULL); + + if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20)) + goto done; + + switch (mode) { + case CLK_FAST: /* FORCEHT, fast (pll) clock */ + if (sii->pub.ccrev < 10) { + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */ + si_clkctl_xtal(&sii->pub, XTAL, ON); + SET_REG(sii->osh, &cc->slow_clk_ctl, + (SCC_XC | SCC_FS | SCC_IP), SCC_IP); + } else if (sii->pub.ccrev < 20) { + OR_REG(sii->osh, &cc->system_clk_ctl, SYCC_HR); + } else { + OR_REG(sii->osh, &cc->clk_ctl_st, CCS_FORCEHT); + } + + /* wait for the PLL */ + if (PMUCTL_ENAB(&sii->pub)) { + u32 htavail = CCS_HTAVAIL; + SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) + == 0), PMU_MAX_TRANSITION_DLY); + ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail); + } else { + udelay(PLL_DELAY); + } + break; + + case CLK_DYNAMIC: /* enable dynamic clock control */ + if (sii->pub.ccrev < 10) { + scc = R_REG(sii->osh, &cc->slow_clk_ctl); + scc &= ~(SCC_FS | SCC_IP | SCC_XC); + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL) + scc |= SCC_XC; + W_REG(sii->osh, &cc->slow_clk_ctl, scc); + + /* for dynamic control, we have to release our xtal_pu "force on" */ + if (scc & SCC_XC) + si_clkctl_xtal(&sii->pub, XTAL, OFF); + } else if (sii->pub.ccrev < 20) { + /* Instaclock */ + AND_REG(sii->osh, &cc->system_clk_ctl, ~SYCC_HR); + } else { + AND_REG(sii->osh, &cc->clk_ctl_st, ~CCS_FORCEHT); + } + break; + + default: + ASSERT(0); + } + + done: + if (!fast) { + si_setcoreidx(&sii->pub, origidx); + INTR_RESTORE(sii, intr_val); + } + return mode == CLK_FAST; +} + +/* Build device path. Support SI, PCI, and JTAG for now. */ +int si_devpath(si_t *sih, char *path, int size) +{ + int slen; + + ASSERT(path != NULL); + ASSERT(size >= SI_DEVPATH_BUFSZ); + + if (!path || size <= 0) + return -1; + + switch (BUSTYPE(sih->bustype)) { + case SI_BUS: + case JTAG_BUS: + slen = snprintf(path, (size_t) size, "sb/%u/", si_coreidx(sih)); + break; + case PCI_BUS: + ASSERT((SI_INFO(sih))->osh != NULL); + slen = snprintf(path, (size_t) size, "pci/%u/%u/", + OSL_PCI_BUS((SI_INFO(sih))->osh), + OSL_PCI_SLOT((SI_INFO(sih))->osh)); + break; + +#ifdef BCMSDIO + case SDIO_BUS: + SI_ERROR(("si_devpath: device 0 assumed\n")); + slen = snprintf(path, (size_t) size, "sd/%u/", si_coreidx(sih)); + break; +#endif + default: + slen = -1; + ASSERT(0); + break; + } + + if (slen < 0 || slen >= size) { + path[0] = '\0'; + return -1; + } + + return 0; +} + +/* Get a variable, but only if it has a devpath prefix */ +char *si_getdevpathvar(si_t *sih, const char *name) +{ + char varname[SI_DEVPATH_BUFSZ + 32]; + + si_devpathvar(sih, varname, sizeof(varname), name); + + return getvar(NULL, varname); +} + +/* Get a variable, but only if it has a devpath prefix */ +int si_getdevpathintvar(si_t *sih, const char *name) +{ +#if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS) + return getintvar(NULL, name); +#else + char varname[SI_DEVPATH_BUFSZ + 32]; + + si_devpathvar(sih, varname, sizeof(varname), name); + + return getintvar(NULL, varname); +#endif +} + +char *si_getnvramflvar(si_t *sih, const char *name) +{ + return getvar(NULL, name); +} + +/* Concatenate the dev path with a varname into the given 'var' buffer + * and return the 'var' pointer. + * Nothing is done to the arguments if len == 0 or var is NULL, var is still returned. + * On overflow, the first char will be set to '\0'. + */ +static char *si_devpathvar(si_t *sih, char *var, int len, const char *name) +{ + uint path_len; + + if (!var || len <= 0) + return var; + + if (si_devpath(sih, var, len) == 0) { + path_len = strlen(var); + + if (strlen(name) + 1 > (uint) (len - path_len)) + var[0] = '\0'; + else + strncpy(var + path_len, name, len - path_len - 1); + } + + return var; +} + +/* return true if PCIE capability exists in the pci config space */ +static __used bool si_ispcie(si_info_t *sii) +{ + u8 cap_ptr; + + if (BUSTYPE(sii->pub.bustype) != PCI_BUS) + return false; + + cap_ptr = + pcicore_find_pci_capability(sii->osh, PCI_CAP_PCIECAP_ID, NULL, + NULL); + if (!cap_ptr) + return false; + + return true; +} + +#ifdef BCMSDIO +/* initialize the sdio core */ +void si_sdio_init(si_t *sih) +{ + si_info_t *sii = SI_INFO(sih); + + if (((sih->buscoretype == PCMCIA_CORE_ID) && (sih->buscorerev >= 8)) || + (sih->buscoretype == SDIOD_CORE_ID)) { + uint idx; + sdpcmd_regs_t *sdpregs; + + /* get the current core index */ + idx = sii->curidx; + ASSERT(idx == si_findcoreidx(sih, D11_CORE_ID, 0)); + + /* switch to sdio core */ + sdpregs = (sdpcmd_regs_t *) si_setcore(sih, PCMCIA_CORE_ID, 0); + if (!sdpregs) + sdpregs = + (sdpcmd_regs_t *) si_setcore(sih, SDIOD_CORE_ID, 0); + ASSERT(sdpregs); + + SI_MSG(("si_sdio_init: For PCMCIA/SDIO Corerev %d, enable ints from core %d " "through SD core %d (%p)\n", sih->buscorerev, idx, sii->curidx, sdpregs)); + + /* enable backplane error and core interrupts */ + W_REG(sii->osh, &sdpregs->hostintmask, I_SBINT); + W_REG(sii->osh, &sdpregs->sbintmask, + (I_SB_SERR | I_SB_RESPERR | (1 << idx))); + + /* switch back to previous core */ + si_setcoreidx(sih, idx); + } + + /* enable interrupts */ + bcmsdh_intr_enable(sii->sdh); + +} +#endif /* BCMSDIO */ + +bool si_pci_war16165(si_t *sih) +{ + si_info_t *sii; + + sii = SI_INFO(sih); + + return PCI(sii) && (sih->buscorerev <= 10); +} + +void si_pci_up(si_t *sih) +{ + si_info_t *sii; + + sii = SI_INFO(sih); + + /* if not pci bus, we're done */ + if (BUSTYPE(sih->bustype) != PCI_BUS) + return; + + if (PCI_FORCEHT(sii)) + _si_clkctl_cc(sii, CLK_FAST); + + if (PCIE(sii)) + pcicore_up(sii->pch, SI_PCIUP); + +} + +/* Unconfigure and/or apply various WARs when system is going to sleep mode */ +void si_pci_sleep(si_t *sih) +{ + si_info_t *sii; + + sii = SI_INFO(sih); + + pcicore_sleep(sii->pch); +} + +/* Unconfigure and/or apply various WARs when going down */ +void si_pci_down(si_t *sih) +{ + si_info_t *sii; + + sii = SI_INFO(sih); + + /* if not pci bus, we're done */ + if (BUSTYPE(sih->bustype) != PCI_BUS) + return; + + /* release FORCEHT since chip is going to "down" state */ + if (PCI_FORCEHT(sii)) + _si_clkctl_cc(sii, CLK_DYNAMIC); + + pcicore_down(sii->pch, SI_PCIDOWN); +} + +/* + * Configure the pci core for pci client (NIC) action + * coremask is the bitvec of cores by index to be enabled. + */ +void si_pci_setup(si_t *sih, uint coremask) +{ + si_info_t *sii; + struct sbpciregs *pciregs = NULL; + u32 siflag = 0, w; + uint idx = 0; + + sii = SI_INFO(sih); + + if (BUSTYPE(sii->pub.bustype) != PCI_BUS) + return; + + ASSERT(PCI(sii) || PCIE(sii)); + ASSERT(sii->pub.buscoreidx != BADIDX); + + if (PCI(sii)) { + /* get current core index */ + idx = sii->curidx; + + /* we interrupt on this backplane flag number */ + siflag = si_flag(sih); + + /* switch over to pci core */ + pciregs = (struct sbpciregs *)si_setcoreidx(sih, sii->pub.buscoreidx); + } + + /* + * Enable sb->pci interrupts. Assume + * PCI rev 2.3 support was added in pci core rev 6 and things changed.. + */ + if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) { + /* pci config write to set this core bit in PCIIntMask */ + w = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_MASK, sizeof(u32)); + w |= (coremask << PCI_SBIM_SHIFT); + OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_MASK, sizeof(u32), w); + } else { + /* set sbintvec bit for our flag number */ + si_setint(sih, siflag); + } + + if (PCI(sii)) { + OR_REG(sii->osh, &pciregs->sbtopci2, + (SBTOPCI_PREF | SBTOPCI_BURST)); + if (sii->pub.buscorerev >= 11) { + OR_REG(sii->osh, &pciregs->sbtopci2, + SBTOPCI_RC_READMULTI); + w = R_REG(sii->osh, &pciregs->clkrun); + W_REG(sii->osh, &pciregs->clkrun, + (w | PCI_CLKRUN_DSBL)); + w = R_REG(sii->osh, &pciregs->clkrun); + } + + /* switch back to previous core */ + si_setcoreidx(sih, idx); + } +} + +/* + * Fixup SROMless PCI device's configuration. + * The current core may be changed upon return. + */ +int si_pci_fixcfg(si_t *sih) +{ + uint origidx, pciidx; + struct sbpciregs *pciregs = NULL; + sbpcieregs_t *pcieregs = NULL; + void *regs = NULL; + u16 val16, *reg16 = NULL; + + si_info_t *sii = SI_INFO(sih); + + ASSERT(BUSTYPE(sii->pub.bustype) == PCI_BUS); + + /* Fixup PI in SROM shadow area to enable the correct PCI core access */ + /* save the current index */ + origidx = si_coreidx(&sii->pub); + + /* check 'pi' is correct and fix it if not */ + if (sii->pub.buscoretype == PCIE_CORE_ID) { + pcieregs = + (sbpcieregs_t *) si_setcore(&sii->pub, PCIE_CORE_ID, 0); + regs = pcieregs; + ASSERT(pcieregs != NULL); + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET]; + } else if (sii->pub.buscoretype == PCI_CORE_ID) { + pciregs = (struct sbpciregs *)si_setcore(&sii->pub, PCI_CORE_ID, 0); + regs = pciregs; + ASSERT(pciregs != NULL); + reg16 = &pciregs->sprom[SRSH_PI_OFFSET]; + } + pciidx = si_coreidx(&sii->pub); + val16 = R_REG(sii->osh, reg16); + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) { + val16 = + (u16) (pciidx << SRSH_PI_SHIFT) | (val16 & + ~SRSH_PI_MASK); + W_REG(sii->osh, reg16, val16); + } + + /* restore the original index */ + si_setcoreidx(&sii->pub, origidx); + + pcicore_hwup(sii->pch); + return 0; +} + +/* mask&set gpiocontrol bits */ +u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority) +{ + uint regoff; + + regoff = 0; + + /* gpios could be shared on router platforms + * ignore reservation if it's high priority (e.g., test apps) + */ + if ((priority != GPIO_HI_PRIORITY) && + (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { + mask = priority ? (si_gpioreservation & mask) : + ((si_gpioreservation | mask) & ~(si_gpioreservation)); + val &= mask; + } + + regoff = offsetof(chipcregs_t, gpiocontrol); + return si_corereg(sih, SI_CC_IDX, regoff, mask, val); +} + +/* Return the size of the specified SOCRAM bank */ +static uint +socram_banksize(si_info_t *sii, sbsocramregs_t *regs, u8 index, + u8 mem_type) +{ + uint banksize, bankinfo; + uint bankidx = index | (mem_type << SOCRAM_BANKIDX_MEMTYPE_SHIFT); + + ASSERT(mem_type <= SOCRAM_MEMTYPE_DEVRAM); + + W_REG(sii->osh, ®s->bankidx, bankidx); + bankinfo = R_REG(sii->osh, ®s->bankinfo); + banksize = + SOCRAM_BANKINFO_SZBASE * ((bankinfo & SOCRAM_BANKINFO_SZMASK) + 1); + return banksize; +} + +/* Return the RAM size of the SOCRAM core */ +u32 si_socram_size(si_t *sih) +{ + si_info_t *sii; + uint origidx; + uint intr_val = 0; + + sbsocramregs_t *regs; + bool wasup; + uint corerev; + u32 coreinfo; + uint memsize = 0; + + sii = SI_INFO(sih); + + /* Block ints and save current core */ + INTR_OFF(sii, intr_val); + origidx = si_coreidx(sih); + + /* Switch to SOCRAM core */ + regs = si_setcore(sih, SOCRAM_CORE_ID, 0); + if (!regs) + goto done; + + /* Get info for determining size */ + wasup = si_iscoreup(sih); + if (!wasup) + si_core_reset(sih, 0, 0); + corerev = si_corerev(sih); + coreinfo = R_REG(sii->osh, ®s->coreinfo); + + /* Calculate size from coreinfo based on rev */ + if (corerev == 0) + memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK)); + else if (corerev < 3) { + memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK)); + memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; + } else if ((corerev <= 7) || (corerev == 12)) { + uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; + uint bsz = (coreinfo & SRCI_SRBSZ_MASK); + uint lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT; + if (lss != 0) + nb--; + memsize = nb * (1 << (bsz + SR_BSZ_BASE)); + if (lss != 0) + memsize += (1 << ((lss - 1) + SR_BSZ_BASE)); + } else { + u8 i; + uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; + for (i = 0; i < nb; i++) + memsize += + socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM); + } + + /* Return to previous state and core */ + if (!wasup) + si_core_disable(sih, 0); + si_setcoreidx(sih, origidx); + + done: + INTR_RESTORE(sii, intr_val); + + return memsize; +} + +void si_chipcontrl_epa4331(si_t *sih, bool on) +{ + si_info_t *sii; + chipcregs_t *cc; + uint origidx; + u32 val; + + sii = SI_INFO(sih); + origidx = si_coreidx(sih); + + cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); + + val = R_REG(sii->osh, &cc->chipcontrol); + + if (on) { + if (sih->chippkg == 9 || sih->chippkg == 0xb) { + /* Ext PA Controls for 4331 12x9 Package */ + W_REG(sii->osh, &cc->chipcontrol, val | + (CCTRL4331_EXTPA_EN | + CCTRL4331_EXTPA_ON_GPIO2_5)); + } else { + /* Ext PA Controls for 4331 12x12 Package */ + W_REG(sii->osh, &cc->chipcontrol, + val | (CCTRL4331_EXTPA_EN)); + } + } else { + val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5); + W_REG(sii->osh, &cc->chipcontrol, val); + } + + si_setcoreidx(sih, origidx); +} + +/* Enable BT-COEX & Ex-PA for 4313 */ +void si_epa_4313war(si_t *sih) +{ + si_info_t *sii; + chipcregs_t *cc; + uint origidx; + + sii = SI_INFO(sih); + origidx = si_coreidx(sih); + + cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); + + /* EPA Fix */ + W_REG(sii->osh, &cc->gpiocontrol, + R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK); + + si_setcoreidx(sih, origidx); +} + +/* check if the device is removed */ +bool si_deviceremoved(si_t *sih) +{ + u32 w; + si_info_t *sii; + + sii = SI_INFO(sih); + + switch (BUSTYPE(sih->bustype)) { + case PCI_BUS: + ASSERT(sii->osh != NULL); + w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_VID, sizeof(u32)); + if ((w & 0xFFFF) != VENDOR_BROADCOM) + return true; + break; + } + return false; +} + +bool si_is_sprom_available(si_t *sih) +{ + if (sih->ccrev >= 31) { + si_info_t *sii; + uint origidx; + chipcregs_t *cc; + u32 sromctrl; + + if ((sih->cccaps & CC_CAP_SROM) == 0) + return false; + + sii = SI_INFO(sih); + origidx = sii->curidx; + cc = si_setcoreidx(sih, SI_CC_IDX); + sromctrl = R_REG(sii->osh, &cc->sromcontrol); + si_setcoreidx(sih, origidx); + return sromctrl & SRC_PRESENT; + } + + switch (CHIPID(sih->chip)) { + case BCM4329_CHIP_ID: + return (sih->chipst & CST4329_SPROM_SEL) != 0; + case BCM4319_CHIP_ID: + return (sih->chipst & CST4319_SPROM_SEL) != 0; + case BCM4336_CHIP_ID: + return (sih->chipst & CST4336_SPROM_PRESENT) != 0; + case BCM4330_CHIP_ID: + return (sih->chipst & CST4330_SPROM_PRESENT) != 0; + case BCM4313_CHIP_ID: + return (sih->chipst & CST4313_SPROM_PRESENT) != 0; + case BCM4331_CHIP_ID: + return (sih->chipst & CST4331_SPROM_PRESENT) != 0; + default: + return true; + } +} + +bool si_is_otp_disabled(si_t *sih) +{ + switch (CHIPID(sih->chip)) { + case BCM4329_CHIP_ID: + return (sih->chipst & CST4329_SPROM_OTP_SEL_MASK) == + CST4329_OTP_PWRDN; + case BCM4319_CHIP_ID: + return (sih->chipst & CST4319_SPROM_OTP_SEL_MASK) == + CST4319_OTP_PWRDN; + case BCM4336_CHIP_ID: + return (sih->chipst & CST4336_OTP_PRESENT) == 0; + case BCM4330_CHIP_ID: + return (sih->chipst & CST4330_OTP_PRESENT) == 0; + case BCM4313_CHIP_ID: + return (sih->chipst & CST4313_OTP_PRESENT) == 0; + /* These chips always have their OTP on */ + case BCM43224_CHIP_ID: + case BCM43225_CHIP_ID: + case BCM43421_CHIP_ID: + case BCM43235_CHIP_ID: + case BCM43236_CHIP_ID: + case BCM43238_CHIP_ID: + case BCM4331_CHIP_ID: + default: + return false; + } +} + +bool si_is_otp_powered(si_t *sih) +{ + if (PMUCTL_ENAB(sih)) + return si_pmu_is_otp_powered(sih, si_osh(sih)); + return true; +} + +void si_otp_power(si_t *sih, bool on) +{ + if (PMUCTL_ENAB(sih)) + si_pmu_otp_power(sih, si_osh(sih), on); + udelay(1000); +} + diff --git a/drivers/staging/brcm80211/util/siutils_priv.h b/drivers/staging/brcm80211/util/siutils_priv.h new file mode 100644 index 0000000..0284614 --- /dev/null +++ b/drivers/staging/brcm80211/util/siutils_priv.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _siutils_priv_h_ +#define _siutils_priv_h_ + +/* Silicon Backplane externs */ +extern void sb_scan(si_t *sih, void *regs, uint devid); +uint sb_coreid(si_t *sih); +uint sb_corerev(si_t *sih); +extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, + uint val); +extern bool sb_iscoreup(si_t *sih); +void *sb_setcoreidx(si_t *sih, uint coreidx); +extern u32 sb_base(u32 admatch); +extern void sb_core_reset(si_t *sih, u32 bits, u32 resetbits); +extern void sb_core_disable(si_t *sih, u32 bits); +extern bool sb_taclear(si_t *sih, bool details); +#endif /* _siutils_priv_h_ */ |