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path: root/drivers/net/wireless/iwlwifi/iwl-trans-pcie.c
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Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-trans-pcie.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans-pcie.c36
1 files changed, 19 insertions, 17 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-pcie.c b/drivers/net/wireless/iwlwifi/iwl-trans-pcie.c
index 14a32c4..76f05ea 100644
--- a/drivers/net/wireless/iwlwifi/iwl-trans-pcie.c
+++ b/drivers/net/wireless/iwlwifi/iwl-trans-pcie.c
@@ -79,7 +79,7 @@
#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
#define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
- (((1<<cfg(trans)->base_params->num_of_queues) - 1) &\
+ (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
(~(1<<(trans_pcie)->cmd_queue)))
static int iwl_trans_rx_alloc(struct iwl_trans *trans)
@@ -522,7 +522,7 @@ static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
/* Tx queues */
if (trans_pcie->txq) {
for (txq_id = 0;
- txq_id < cfg(trans)->base_params->num_of_queues; txq_id++)
+ txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
iwl_tx_queue_free(trans, txq_id);
}
@@ -547,7 +547,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
int txq_id, slots_num;
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
- u16 scd_bc_tbls_size = cfg(trans)->base_params->num_of_queues *
+ u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
sizeof(struct iwlagn_scd_bc_tbl);
/*It is not allowed to alloc twice, so warn when this happens.
@@ -571,7 +571,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
goto error;
}
- trans_pcie->txq = kcalloc(cfg(trans)->base_params->num_of_queues,
+ trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
sizeof(struct iwl_tx_queue), GFP_KERNEL);
if (!trans_pcie->txq) {
IWL_ERR(trans, "Not enough memory for txq\n");
@@ -580,7 +580,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
}
/* Alloc and init all Tx queues, including the command queue (#4/#9) */
- for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
+ for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
txq_id++) {
slots_num = (txq_id == trans_pcie->cmd_queue) ?
TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
@@ -626,7 +626,7 @@ static int iwl_tx_init(struct iwl_trans *trans)
spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
/* Alloc and init all Tx queues, including the command queue (#4/#9) */
- for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
+ for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
txq_id++) {
slots_num = (txq_id == trans_pcie->cmd_queue) ?
TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
@@ -749,9 +749,9 @@ static int iwl_apm_init(struct iwl_trans *trans)
iwl_apm_config(trans);
/* Configure analog phase-lock-loop before activating to D0A */
- if (cfg(trans)->base_params->pll_cfg_val)
+ if (trans->cfg->base_params->pll_cfg_val)
iwl_set_bit(trans, CSR_ANA_PLL_CFG,
- cfg(trans)->base_params->pll_cfg_val);
+ trans->cfg->base_params->pll_cfg_val);
/*
* Set "initialization complete" bit to move adapter from
@@ -861,7 +861,7 @@ static int iwl_nic_init(struct iwl_trans *trans)
if (iwl_tx_init(trans))
return -ENOMEM;
- if (cfg(trans)->base_params->shadow_reg_enable) {
+ if (trans->cfg->base_params->shadow_reg_enable) {
/* enable shadow regs in HW */
iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
0x800FFFFF);
@@ -1080,7 +1080,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
iwl_write_targ_mem(trans, a, 0);
for (; a < trans_pcie->scd_base_addr +
SCD_TRANS_TBL_OFFSET_QUEUE(
- cfg(trans)->base_params->num_of_queues);
+ trans->cfg->base_params->num_of_queues);
a += 4)
iwl_write_targ_mem(trans, a, 0);
@@ -1103,7 +1103,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
iwl_write_prph(trans, SCD_AGGR_SEL, 0);
/* initiate the queues */
- for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++) {
+ for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
@@ -1120,7 +1120,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
}
iwl_write_prph(trans, SCD_INTERRUPT_MASK,
- IWL_MASK(0, cfg(trans)->base_params->num_of_queues));
+ IWL_MASK(0, trans->cfg->base_params->num_of_queues));
/* Activate all Tx DMA/FIFO channels */
iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
@@ -1188,7 +1188,7 @@ static int iwl_trans_tx_stop(struct iwl_trans *trans)
}
/* Unmap DMA from host system and free skb's */
- for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
+ for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
txq_id++)
iwl_tx_queue_unmap(trans, txq_id);
@@ -1617,7 +1617,7 @@ static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
int ret = 0;
/* waiting for all the tx frames complete might take a while */
- for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
+ for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
if (cnt == trans_pcie->cmd_queue)
continue;
txq = &trans_pcie->txq[cnt];
@@ -1829,7 +1829,7 @@ static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
int ret;
size_t bufsz;
- bufsz = sizeof(char) * 64 * cfg(trans)->base_params->num_of_queues;
+ bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
if (!trans_pcie->txq) {
IWL_ERR(trans, "txq not ready\n");
@@ -1839,7 +1839,7 @@ static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
if (!buf)
return -ENOMEM;
- for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
+ for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
txq = &trans_pcie->txq[cnt];
q = &txq->q;
pos += scnprintf(buf + pos, bufsz - pos,
@@ -2085,7 +2085,8 @@ const struct iwl_trans_ops trans_ops_pcie = {
struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
struct pci_dev *pdev,
- const struct pci_device_id *ent)
+ const struct pci_device_id *ent,
+ const struct iwl_cfg *cfg)
{
struct iwl_trans_pcie *trans_pcie;
struct iwl_trans *trans;
@@ -2102,6 +2103,7 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
trans->ops = &trans_ops_pcie;
trans->shrd = shrd;
+ trans->cfg = cfg;
trans_pcie->trans = trans;
spin_lock_init(&trans_pcie->irq_lock);
init_waitqueue_head(&trans_pcie->ucode_write_waitq);
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