diff options
Diffstat (limited to 'drivers/net/ixgb/ixgb_hw.c')
| -rw-r--r-- | drivers/net/ixgb/ixgb_hw.c | 164 |
1 files changed, 61 insertions, 103 deletions
diff --git a/drivers/net/ixgb/ixgb_hw.c b/drivers/net/ixgb/ixgb_hw.c index ff67a84..397acab 100644 --- a/drivers/net/ixgb/ixgb_hw.c +++ b/drivers/net/ixgb/ixgb_hw.c @@ -30,9 +30,13 @@ * Shared functions for accessing and configuring the adapter */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include "ixgb_hw.h" #include "ixgb_ids.h" +#include <linux/etherdevice.h> + /* Local function prototypes */ static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr); @@ -120,13 +124,13 @@ ixgb_adapter_stop(struct ixgb_hw *hw) u32 ctrl_reg; u32 icr_reg; - DEBUGFUNC("ixgb_adapter_stop"); + ENTER(); /* If we are stopped or resetting exit gracefully and wait to be * started again before accessing the hardware. */ if (hw->adapter_stopped) { - DEBUGOUT("Exiting because the adapter is already stopped!!!\n"); + pr_debug("Exiting because the adapter is already stopped!!!\n"); return false; } @@ -136,7 +140,7 @@ ixgb_adapter_stop(struct ixgb_hw *hw) hw->adapter_stopped = true; /* Clear interrupt mask to stop board from generating interrupts */ - DEBUGOUT("Masking off all interrupts\n"); + pr_debug("Masking off all interrupts\n"); IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF); /* Disable the Transmit and Receive units. Then delay to allow @@ -152,12 +156,12 @@ ixgb_adapter_stop(struct ixgb_hw *hw) * the current PCI configuration. The global reset bit is self- * clearing, and should clear within a microsecond. */ - DEBUGOUT("Issuing a global reset to MAC\n"); + pr_debug("Issuing a global reset to MAC\n"); ctrl_reg = ixgb_mac_reset(hw); /* Clear interrupt mask to stop board from generating interrupts */ - DEBUGOUT("Masking off all interrupts\n"); + pr_debug("Masking off all interrupts\n"); IXGB_WRITE_REG(hw, IMC, 0xffffffff); /* Clear any pending interrupt events. */ @@ -183,7 +187,7 @@ ixgb_identify_xpak_vendor(struct ixgb_hw *hw) u16 vendor_name[5]; ixgb_xpak_vendor xpak_vendor; - DEBUGFUNC("ixgb_identify_xpak_vendor"); + ENTER(); /* Read the first few bytes of the vendor string from the XPAK NVR * registers. These are standard XENPAK/XPAK registers, so all XPAK @@ -222,12 +226,12 @@ ixgb_identify_phy(struct ixgb_hw *hw) ixgb_phy_type phy_type; ixgb_xpak_vendor xpak_vendor; - DEBUGFUNC("ixgb_identify_phy"); + ENTER(); /* Infer the transceiver/phy type from the device id */ switch (hw->device_id) { case IXGB_DEVICE_ID_82597EX: - DEBUGOUT("Identified TXN17401 optics\n"); + pr_debug("Identified TXN17401 optics\n"); phy_type = ixgb_phy_type_txn17401; break; @@ -237,30 +241,30 @@ ixgb_identify_phy(struct ixgb_hw *hw) * type of optics. */ xpak_vendor = ixgb_identify_xpak_vendor(hw); if (xpak_vendor == ixgb_xpak_vendor_intel) { - DEBUGOUT("Identified TXN17201 optics\n"); + pr_debug("Identified TXN17201 optics\n"); phy_type = ixgb_phy_type_txn17201; } else { - DEBUGOUT("Identified G6005 optics\n"); + pr_debug("Identified G6005 optics\n"); phy_type = ixgb_phy_type_g6005; } break; case IXGB_DEVICE_ID_82597EX_LR: - DEBUGOUT("Identified G6104 optics\n"); + pr_debug("Identified G6104 optics\n"); phy_type = ixgb_phy_type_g6104; break; case IXGB_DEVICE_ID_82597EX_CX4: - DEBUGOUT("Identified CX4\n"); + pr_debug("Identified CX4\n"); xpak_vendor = ixgb_identify_xpak_vendor(hw); if (xpak_vendor == ixgb_xpak_vendor_intel) { - DEBUGOUT("Identified TXN17201 optics\n"); + pr_debug("Identified TXN17201 optics\n"); phy_type = ixgb_phy_type_txn17201; } else { - DEBUGOUT("Identified G6005 optics\n"); + pr_debug("Identified G6005 optics\n"); phy_type = ixgb_phy_type_g6005; } break; default: - DEBUGOUT("Unknown physical layer module\n"); + pr_debug("Unknown physical layer module\n"); phy_type = ixgb_phy_type_unknown; break; } @@ -296,18 +300,18 @@ ixgb_init_hw(struct ixgb_hw *hw) u32 ctrl_reg; bool status; - DEBUGFUNC("ixgb_init_hw"); + ENTER(); /* Issue a global reset to the MAC. This will reset the chip's * transmit, receive, DMA, and link units. It will not effect * the current PCI configuration. The global reset bit is self- * clearing, and should clear within a microsecond. */ - DEBUGOUT("Issuing a global reset to MAC\n"); + pr_debug("Issuing a global reset to MAC\n"); ctrl_reg = ixgb_mac_reset(hw); - DEBUGOUT("Issuing an EE reset to MAC\n"); + pr_debug("Issuing an EE reset to MAC\n"); #ifdef HP_ZX1 /* Workaround for 82597EX reset errata */ IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST); @@ -335,7 +339,7 @@ ixgb_init_hw(struct ixgb_hw *hw) * If it is not valid, we fail hardware init. */ if (!mac_addr_valid(hw->curr_mac_addr)) { - DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n"); + pr_debug("MAC address invalid after ixgb_init_rx_addrs\n"); return(false); } @@ -346,7 +350,7 @@ ixgb_init_hw(struct ixgb_hw *hw) ixgb_get_bus_info(hw); /* Zero out the Multicast HASH table */ - DEBUGOUT("Zeroing the MTA\n"); + pr_debug("Zeroing the MTA\n"); for (i = 0; i < IXGB_MC_TBL_SIZE; i++) IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); @@ -379,7 +383,7 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw) { u32 i; - DEBUGFUNC("ixgb_init_rx_addrs"); + ENTER(); /* * If the current mac address is valid, assume it is a software override @@ -391,35 +395,24 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw) /* Get the MAC address from the eeprom for later reference */ ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr); - DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ", - hw->curr_mac_addr[0], - hw->curr_mac_addr[1], hw->curr_mac_addr[2]); - DEBUGOUT3("%.2X %.2X %.2X\n", - hw->curr_mac_addr[3], - hw->curr_mac_addr[4], hw->curr_mac_addr[5]); + pr_debug("Keeping Permanent MAC Addr = %pM\n", + hw->curr_mac_addr); } else { /* Setup the receive address. */ - DEBUGOUT("Overriding MAC Address in RAR[0]\n"); - DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", - hw->curr_mac_addr[0], - hw->curr_mac_addr[1], hw->curr_mac_addr[2]); - DEBUGOUT3("%.2X %.2X %.2X\n", - hw->curr_mac_addr[3], - hw->curr_mac_addr[4], hw->curr_mac_addr[5]); + pr_debug("Overriding MAC Address in RAR[0]\n"); + pr_debug("New MAC Addr = %pM\n", hw->curr_mac_addr); ixgb_rar_set(hw, hw->curr_mac_addr, 0); } /* Zero out the other 15 receive addresses. */ - DEBUGOUT("Clearing RAR[1-15]\n"); + pr_debug("Clearing RAR[1-15]\n"); for (i = 1; i < IXGB_RAR_ENTRIES; i++) { /* Write high reg first to disable the AV bit first */ IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); } - - return; } /****************************************************************************** @@ -444,65 +437,50 @@ ixgb_mc_addr_list_update(struct ixgb_hw *hw, u32 hash_value; u32 i; u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */ + u8 *mca; - DEBUGFUNC("ixgb_mc_addr_list_update"); + ENTER(); /* Set the new number of MC addresses that we are being requested to use. */ hw->num_mc_addrs = mc_addr_count; /* Clear RAR[1-15] */ - DEBUGOUT(" Clearing RAR[1-15]\n"); + pr_debug("Clearing RAR[1-15]\n"); for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) { IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); } /* Clear the MTA */ - DEBUGOUT(" Clearing MTA\n"); + pr_debug("Clearing MTA\n"); for (i = 0; i < IXGB_MC_TBL_SIZE; i++) IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); /* Add the new addresses */ + mca = mc_addr_list; for (i = 0; i < mc_addr_count; i++) { - DEBUGOUT(" Adding the multicast addresses:\n"); - DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, - mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)], - mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + - 1], - mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + - 2], - mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + - 3], - mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + - 4], - mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + - 5]); + pr_debug("Adding the multicast addresses:\n"); + pr_debug("MC Addr #%d = %pM\n", i, mca); /* Place this multicast address in the RAR if there is room, * * else put it in the MTA */ if (rar_used_count < IXGB_RAR_ENTRIES) { - ixgb_rar_set(hw, - mc_addr_list + - (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)), - rar_used_count); - DEBUGOUT1("Added a multicast address to RAR[%d]\n", i); + ixgb_rar_set(hw, mca, rar_used_count); + pr_debug("Added a multicast address to RAR[%d]\n", i); rar_used_count++; } else { - hash_value = ixgb_hash_mc_addr(hw, - mc_addr_list + - (i * - (IXGB_ETH_LENGTH_OF_ADDRESS - + pad))); + hash_value = ixgb_hash_mc_addr(hw, mca); - DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); + pr_debug("Hash value = 0x%03X\n", hash_value); ixgb_mta_set(hw, hash_value); } + + mca += IXGB_ETH_LENGTH_OF_ADDRESS + pad; } - DEBUGOUT("MC Update Complete\n"); - return; + pr_debug("MC Update Complete\n"); } /****************************************************************************** @@ -520,7 +498,7 @@ ixgb_hash_mc_addr(struct ixgb_hw *hw, { u32 hash_value = 0; - DEBUGFUNC("ixgb_hash_mc_addr"); + ENTER(); /* The portion of the address that is used for the hash table is * determined by the mc_filter_type setting. @@ -547,7 +525,7 @@ ixgb_hash_mc_addr(struct ixgb_hw *hw, break; default: /* Invalid mc_filter_type, what should we do? */ - DEBUGOUT("MC filter type param set incorrectly\n"); + pr_debug("MC filter type param set incorrectly\n"); ASSERT(0); break; } @@ -585,8 +563,6 @@ ixgb_mta_set(struct ixgb_hw *hw, mta_reg |= (1 << hash_bit); IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg); - - return; } /****************************************************************************** @@ -603,7 +579,7 @@ ixgb_rar_set(struct ixgb_hw *hw, { u32 rar_low, rar_high; - DEBUGFUNC("ixgb_rar_set"); + ENTER(); /* HW expects these in little endian so we reverse the byte order * from network order (big endian) to little endian @@ -619,7 +595,6 @@ ixgb_rar_set(struct ixgb_hw *hw, IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); - return; } /****************************************************************************** @@ -635,7 +610,6 @@ ixgb_write_vfta(struct ixgb_hw *hw, u32 value) { IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value); - return; } /****************************************************************************** @@ -650,7 +624,6 @@ ixgb_clear_vfta(struct ixgb_hw *hw) for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++) IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0); - return; } /****************************************************************************** @@ -666,7 +639,7 @@ ixgb_setup_fc(struct ixgb_hw *hw) u32 pap_reg = 0; /* by default, assume no pause time */ bool status = true; - DEBUGFUNC("ixgb_setup_fc"); + ENTER(); /* Get the current control reg 0 settings */ ctrl_reg = IXGB_READ_REG(hw, CTRL0); @@ -710,7 +683,7 @@ ixgb_setup_fc(struct ixgb_hw *hw) break; default: /* We should never get here. The value should be 0-3. */ - DEBUGOUT("Flow control param set incorrectly\n"); + pr_debug("Flow control param set incorrectly\n"); ASSERT(0); break; } @@ -940,7 +913,7 @@ ixgb_check_for_link(struct ixgb_hw *hw) u32 status_reg; u32 xpcss_reg; - DEBUGFUNC("ixgb_check_for_link"); + ENTER(); xpcss_reg = IXGB_READ_REG(hw, XPCSS); status_reg = IXGB_READ_REG(hw, STATUS); @@ -950,7 +923,7 @@ ixgb_check_for_link(struct ixgb_hw *hw) hw->link_up = true; } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) && (status_reg & IXGB_STATUS_LU)) { - DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n"); + pr_debug("XPCSS Not Aligned while Status:LU is set\n"); hw->link_up = ixgb_link_reset(hw); } else { /* @@ -981,8 +954,7 @@ bool ixgb_check_for_bad_link(struct ixgb_hw *hw) newRFC = IXGB_READ_REG(hw, RFC); if ((hw->lastLFC + 250 < newLFC) || (hw->lastRFC + 250 < newRFC)) { - DEBUGOUT - ("BAD LINK! too many LFC/RFC since last check\n"); + pr_debug("BAD LINK! too many LFC/RFC since last check\n"); bad_link_returncode = true; } hw->lastLFC = newLFC; @@ -1002,11 +974,11 @@ ixgb_clear_hw_cntrs(struct ixgb_hw *hw) { volatile u32 temp_reg; - DEBUGFUNC("ixgb_clear_hw_cntrs"); + ENTER(); /* if we are stopped or resetting exit gracefully */ if (hw->adapter_stopped) { - DEBUGOUT("Exiting because the adapter is stopped!!!\n"); + pr_debug("Exiting because the adapter is stopped!!!\n"); return; } @@ -1070,7 +1042,6 @@ ixgb_clear_hw_cntrs(struct ixgb_hw *hw) temp_reg = IXGB_READ_REG(hw, XOFFRXC); temp_reg = IXGB_READ_REG(hw, XOFFTXC); temp_reg = IXGB_READ_REG(hw, RJC); - return; } /****************************************************************************** @@ -1086,7 +1057,6 @@ ixgb_led_on(struct ixgb_hw *hw) /* To turn on the LED, clear software-definable pin 0 (SDP0). */ ctrl0_reg &= ~IXGB_CTRL0_SDP0; IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); - return; } /****************************************************************************** @@ -1102,7 +1072,6 @@ ixgb_led_off(struct ixgb_hw *hw) /* To turn off the LED, set software-definable pin 0 (SDP0). */ ctrl0_reg |= IXGB_CTRL0_SDP0; IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); - return; } /****************************************************************************** @@ -1142,8 +1111,6 @@ ixgb_get_bus_info(struct ixgb_hw *hw) hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ? ixgb_bus_width_64 : ixgb_bus_width_32; - - return; } /****************************************************************************** @@ -1156,26 +1123,21 @@ static bool mac_addr_valid(u8 *mac_addr) { bool is_valid = true; - DEBUGFUNC("mac_addr_valid"); + ENTER(); /* Make sure it is not a multicast address */ - if (IS_MULTICAST(mac_addr)) { - DEBUGOUT("MAC address is multicast\n"); + if (is_multicast_ether_addr(mac_addr)) { + pr_debug("MAC address is multicast\n"); is_valid = false; } /* Not a broadcast address */ - else if (IS_BROADCAST(mac_addr)) { - DEBUGOUT("MAC address is broadcast\n"); + else if (is_broadcast_ether_addr(mac_addr)) { + pr_debug("MAC address is broadcast\n"); is_valid = false; } /* Reject the zero address */ - else if (mac_addr[0] == 0 && - mac_addr[1] == 0 && - mac_addr[2] == 0 && - mac_addr[3] == 0 && - mac_addr[4] == 0 && - mac_addr[5] == 0) { - DEBUGOUT("MAC address is all zeros\n"); + else if (is_zero_ether_addr(mac_addr)) { + pr_debug("MAC address is all zeros\n"); is_valid = false; } return (is_valid); @@ -1235,8 +1197,6 @@ ixgb_optics_reset(struct ixgb_hw *hw) IXGB_PHY_ADDRESS, MDIO_MMD_PMAPMD); } - - return; } /****************************************************************************** @@ -1297,6 +1257,4 @@ ixgb_optics_reset_bcm(struct ixgb_hw *hw) /* SerDes needs extra delay */ msleep(IXGB_SUN_PHY_RESET_DELAY); - - return; } |
