diff options
Diffstat (limited to 'drivers/net/fddi/defxx.c')
| -rw-r--r-- | drivers/net/fddi/defxx.c | 40 |
1 files changed, 26 insertions, 14 deletions
diff --git a/drivers/net/fddi/defxx.c b/drivers/net/fddi/defxx.c index 15a18fb..caed6ee 100644 --- a/drivers/net/fddi/defxx.c +++ b/drivers/net/fddi/defxx.c @@ -466,7 +466,8 @@ static void dfx_get_bars(struct device *bdev, *bar_len = (bar | PI_MEM_ADD_MASK_M) + 1; } else { *bar_start = base_addr; - *bar_len = PI_ESIC_K_CSR_IO_LEN; + *bar_len = PI_ESIC_K_CSR_IO_LEN + + PI_ESIC_K_BURST_HOLDOFF_LEN; } } if (dfx_bus_tc) { @@ -683,6 +684,9 @@ static void dfx_bus_init(struct net_device *dev) if (dfx_bus_eisa) { unsigned long base_addr = to_eisa_device(bdev)->base_addr; + /* Disable the board before fiddling with the decoders. */ + outb(0, base_addr + PI_ESIC_K_SLOT_CNTRL); + /* Get the interrupt level from the ESIC chip. */ val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); val &= PI_CONFIG_STAT_0_M_IRQ; @@ -709,25 +713,33 @@ static void dfx_bus_init(struct net_device *dev) /* * Enable memory decoding (MEMCS0) and/or port decoding * (IOCS1/IOCS0) as appropriate in Function Control - * Register. One of the port chip selects seems to be - * used for the Burst Holdoff register, but this bit of - * documentation is missing and as yet it has not been - * determined which of the two. This is also the reason - * the size of the decoded port range is twice as large - * as one required by the PDQ. + * Register. IOCS0 is used for PDQ registers, taking 16 + * 32-bit words, while IOCS1 is used for the Burst Holdoff + * register, taking a single 32-bit word only. We use the + * slot-specific I/O range as per the ESIC spec, that is + * set bits 15:12 in the mask registers to mask them out. */ /* Set the decode range of the board. */ - val = ((bp->base.port >> 12) << PI_IO_CMP_V_SLOT); + val = 0; outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_0_1); - outb(0, base_addr + PI_ESIC_K_IO_ADD_CMP_0_0); - outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_1_1); - outb(0, base_addr + PI_ESIC_K_IO_ADD_CMP_1_0); - val = PI_ESIC_K_CSR_IO_LEN - 1; + val = PI_DEFEA_K_CSR_IO; + outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_0_0); + + val = PI_IO_CMP_M_SLOT; outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_0_1); - outb(0, base_addr + PI_ESIC_K_IO_ADD_MASK_0_0); + val = (PI_ESIC_K_CSR_IO_LEN - 1) & ~3; + outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_0_0); + + val = 0; + outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_1_1); + val = PI_DEFEA_K_BURST_HOLDOFF; + outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_1_0); + + val = PI_IO_CMP_M_SLOT; outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_1_1); - outb(0, base_addr + PI_ESIC_K_IO_ADD_MASK_1_0); + val = (PI_ESIC_K_BURST_HOLDOFF_LEN - 1) & ~3; + outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_1_0); /* Enable the decoders. */ val = PI_FUNCTION_CNTRL_M_IOCS1 | PI_FUNCTION_CNTRL_M_IOCS0; |
