diff options
Diffstat (limited to 'drivers/net/can/pch_can.c')
| -rw-r--r-- | drivers/net/can/pch_can.c | 939 |
1 files changed, 412 insertions, 527 deletions
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c index 6727182..a9b6a65 100644 --- a/drivers/net/can/pch_can.c +++ b/drivers/net/can/pch_can.c @@ -32,99 +32,91 @@ #include <linux/can/dev.h> #include <linux/can/error.h> -#define MAX_MSG_OBJ 32 -#define MSG_OBJ_RX 0 /* The receive message object flag. */ -#define MSG_OBJ_TX 1 /* The transmit message object flag. */ - -#define ENABLE 1 /* The enable flag */ -#define DISABLE 0 /* The disable flag */ -#define CAN_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */ -#define CAN_CTRL_IE 0x0002 /* The IE bit of CAN control register */ -#define CAN_CTRL_IE_SIE_EIE 0x000e -#define CAN_CTRL_CCE 0x0040 -#define CAN_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */ -#define CAN_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */ -#define CAN_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */ -#define CAN_CMASK_RX_TX_SET 0x00f3 -#define CAN_CMASK_RX_TX_GET 0x0073 -#define CAN_CMASK_ALL 0xff -#define CAN_CMASK_RDWR 0x80 -#define CAN_CMASK_ARB 0x20 -#define CAN_CMASK_CTRL 0x10 -#define CAN_CMASK_MASK 0x40 -#define CAN_CMASK_NEWDAT 0x04 -#define CAN_CMASK_CLRINTPND 0x08 - -#define CAN_IF_MCONT_NEWDAT 0x8000 -#define CAN_IF_MCONT_INTPND 0x2000 -#define CAN_IF_MCONT_UMASK 0x1000 -#define CAN_IF_MCONT_TXIE 0x0800 -#define CAN_IF_MCONT_RXIE 0x0400 -#define CAN_IF_MCONT_RMTEN 0x0200 -#define CAN_IF_MCONT_TXRQXT 0x0100 -#define CAN_IF_MCONT_EOB 0x0080 -#define CAN_IF_MCONT_DLC 0x000f -#define CAN_IF_MCONT_MSGLOST 0x4000 -#define CAN_MASK2_MDIR_MXTD 0xc000 -#define CAN_ID2_DIR 0x2000 -#define CAN_ID_MSGVAL 0x8000 - -#define CAN_STATUS_INT 0x8000 -#define CAN_IF_CREQ_BUSY 0x8000 -#define CAN_ID2_XTD 0x4000 - -#define CAN_REC 0x00007f00 -#define CAN_TEC 0x000000ff - -#define PCH_RX_OK 0x00000010 -#define PCH_TX_OK 0x00000008 -#define PCH_BUS_OFF 0x00000080 -#define PCH_EWARN 0x00000040 -#define PCH_EPASSIV 0x00000020 -#define PCH_LEC0 0x00000001 -#define PCH_LEC1 0x00000002 -#define PCH_LEC2 0x00000004 -#define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2) -#define PCH_STUF_ERR PCH_LEC0 -#define PCH_FORM_ERR PCH_LEC1 -#define PCH_ACK_ERR (PCH_LEC0 | PCH_LEC1) -#define PCH_BIT1_ERR PCH_LEC2 -#define PCH_BIT0_ERR (PCH_LEC0 | PCH_LEC2) -#define PCH_CRC_ERR (PCH_LEC1 | PCH_LEC2) +#define PCH_ENABLE 1 /* The enable flag */ +#define PCH_DISABLE 0 /* The disable flag */ +#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */ +#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */ +#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1)) +#define PCH_CTRL_CCE BIT(6) +#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */ +#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */ +#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */ + +#define PCH_CMASK_RX_TX_SET 0x00f3 +#define PCH_CMASK_RX_TX_GET 0x0073 +#define PCH_CMASK_ALL 0xff +#define PCH_CMASK_NEWDAT BIT(2) +#define PCH_CMASK_CLRINTPND BIT(3) +#define PCH_CMASK_CTRL BIT(4) +#define PCH_CMASK_ARB BIT(5) +#define PCH_CMASK_MASK BIT(6) +#define PCH_CMASK_RDWR BIT(7) +#define PCH_IF_MCONT_NEWDAT BIT(15) +#define PCH_IF_MCONT_MSGLOST BIT(14) +#define PCH_IF_MCONT_INTPND BIT(13) +#define PCH_IF_MCONT_UMASK BIT(12) +#define PCH_IF_MCONT_TXIE BIT(11) +#define PCH_IF_MCONT_RXIE BIT(10) +#define PCH_IF_MCONT_RMTEN BIT(9) +#define PCH_IF_MCONT_TXRQXT BIT(8) +#define PCH_IF_MCONT_EOB BIT(7) +#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15)) +#define PCH_ID2_DIR BIT(13) +#define PCH_ID2_XTD BIT(14) +#define PCH_ID_MSGVAL BIT(15) +#define PCH_IF_CREQ_BUSY BIT(15) + +#define PCH_STATUS_INT 0x8000 +#define PCH_REC 0x00007f00 +#define PCH_TEC 0x000000ff + +#define PCH_TX_OK BIT(3) +#define PCH_RX_OK BIT(4) +#define PCH_EPASSIV BIT(5) +#define PCH_EWARN BIT(6) +#define PCH_BUS_OFF BIT(7) /* bit position of certain controller bits. */ -#define BIT_BITT_BRP 0 -#define BIT_BITT_SJW 6 -#define BIT_BITT_TSEG1 8 -#define BIT_BITT_TSEG2 12 -#define BIT_IF1_MCONT_RXIE 10 -#define BIT_IF2_MCONT_TXIE 11 -#define BIT_BRPE_BRPE 6 -#define BIT_ES_TXERRCNT 0 -#define BIT_ES_RXERRCNT 8 -#define MSK_BITT_BRP 0x3f -#define MSK_BITT_SJW 0xc0 -#define MSK_BITT_TSEG1 0xf00 -#define MSK_BITT_TSEG2 0x7000 -#define MSK_BRPE_BRPE 0x3c0 -#define MSK_BRPE_GET 0x0f -#define MSK_CTRL_IE_SIE_EIE 0x07 -#define MSK_MCONT_TXIE 0x08 -#define MSK_MCONT_RXIE 0x10 -#define PCH_CAN_NO_TX_BUFF 1 -#define COUNTER_LIMIT 10 +#define PCH_BIT_BRP 0 +#define PCH_BIT_SJW 6 +#define PCH_BIT_TSEG1 8 +#define PCH_BIT_TSEG2 12 +#define PCH_BIT_BRPE_BRPE 6 +#define PCH_MSK_BITT_BRP 0x3f +#define PCH_MSK_BRPE_BRPE 0x3c0 +#define PCH_MSK_CTRL_IE_SIE_EIE 0x07 +#define PCH_COUNTER_LIMIT 10 #define PCH_CAN_CLK 50000000 /* 50MHz */ /* Define the number of message object. * PCH CAN communications are done via Message RAM. * The Message RAM consists of 32 message objects. */ -#define PCH_RX_OBJ_NUM 26 /* 1~ PCH_RX_OBJ_NUM is Rx*/ -#define PCH_TX_OBJ_NUM 6 /* PCH_RX_OBJ_NUM is RX ~ Tx*/ -#define PCH_OBJ_NUM (PCH_TX_OBJ_NUM + PCH_RX_OBJ_NUM) +#define PCH_RX_OBJ_NUM 26 +#define PCH_TX_OBJ_NUM 6 +#define PCH_RX_OBJ_START 1 +#define PCH_RX_OBJ_END PCH_RX_OBJ_NUM +#define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1) +#define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM) #define PCH_FIFO_THRESH 16 +enum pch_ifreg { + PCH_RX_IFREG, + PCH_TX_IFREG, +}; + +enum pch_can_err { + PCH_STUF_ERR = 1, + PCH_FORM_ERR, + PCH_ACK_ERR, + PCH_BIT1_ERR, + PCH_BIT0_ERR, + PCH_CRC_ERR, + PCH_LEC_ALL, +}; + enum pch_can_mode { PCH_CAN_ENABLE, PCH_CAN_DISABLE, @@ -134,6 +126,21 @@ enum pch_can_mode { PCH_CAN_RUN }; +struct pch_can_if_regs { + u32 creq; + u32 cmask; + u32 mask1; + u32 mask2; + u32 id1; + u32 id2; + u32 mcont; + u32 dataa1; + u32 dataa2; + u32 datab1; + u32 datab2; + u32 rsv[13]; +}; + struct pch_can_regs { u32 cont; u32 stat; @@ -142,38 +149,21 @@ struct pch_can_regs { u32 intr; u32 opt; u32 brpe; - u32 reserve1; - u32 if1_creq; - u32 if1_cmask; - u32 if1_mask1; - u32 if1_mask2; - u32 if1_id1; - u32 if1_id2; - u32 if1_mcont; - u32 if1_dataa1; - u32 if1_dataa2; - u32 if1_datab1; - u32 if1_datab2; - u32 reserve2; - u32 reserve3[12]; - u32 if2_creq; - u32 if2_cmask; - u32 if2_mask1; - u32 if2_mask2; - u32 if2_id1; - u32 if2_id2; - u32 if2_mcont; - u32 if2_dataa1; - u32 if2_dataa2; - u32 if2_datab1; - u32 if2_datab2; - u32 reserve4; - u32 reserve5[20]; + u32 reserve; + struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */ + u32 reserve1[8]; u32 treq1; u32 treq2; - u32 reserve6[2]; - u32 reserve7[56]; - u32 reserve8[3]; + u32 reserve2[6]; + u32 data1; + u32 data2; + u32 reserve3[6]; + u32 canipend1; + u32 canipend2; + u32 reserve4[6]; + u32 canmval1; + u32 canmval2; + u32 reserve5[37]; u32 srst; }; @@ -181,14 +171,13 @@ struct pch_can_priv { struct can_priv can; unsigned int can_num; struct pci_dev *dev; - unsigned int tx_enable[MAX_MSG_OBJ]; - unsigned int rx_enable[MAX_MSG_OBJ]; - unsigned int rx_link[MAX_MSG_OBJ]; + int tx_enable[PCH_TX_OBJ_END]; + int rx_enable[PCH_TX_OBJ_END]; + int rx_link[PCH_TX_OBJ_END]; unsigned int int_enables; unsigned int int_stat; struct net_device *ndev; - spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/ - unsigned int msg_obj[MAX_MSG_OBJ]; + unsigned int msg_obj[PCH_TX_OBJ_END]; struct pch_can_regs __iomem *regs; struct napi_struct napi; unsigned int tx_obj; /* Point next Tx Obj index */ @@ -228,11 +217,11 @@ static void pch_can_set_run_mode(struct pch_can_priv *priv, { switch (mode) { case PCH_CAN_RUN: - pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_INIT); + pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT); break; case PCH_CAN_STOP: - pch_can_bit_set(&priv->regs->cont, CAN_CTRL_INIT); + pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT); break; default: @@ -246,30 +235,30 @@ static void pch_can_set_optmode(struct pch_can_priv *priv) u32 reg_val = ioread32(&priv->regs->opt); if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) - reg_val |= CAN_OPT_SILENT; + reg_val |= PCH_OPT_SILENT; if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) - reg_val |= CAN_OPT_LBACK; + reg_val |= PCH_OPT_LBACK; - pch_can_bit_set(&priv->regs->cont, CAN_CTRL_OPT); + pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT); iowrite32(reg_val, &priv->regs->opt); } static void pch_can_set_int_custom(struct pch_can_priv *priv) { /* Clearing the IE, SIE and EIE bits of Can control register. */ - pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE); + pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); /* Appropriately setting them. */ pch_can_bit_set(&priv->regs->cont, - ((priv->int_enables & MSK_CTRL_IE_SIE_EIE) << 1)); + ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1)); } /* This function retrieves interrupt enabled for the CAN device. */ static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables) { /* Obtaining the status of IE, SIE and EIE interrupt bits. */ - *enables = ((ioread32(&priv->regs->cont) & CAN_CTRL_IE_SIE_EIE) >> 1); + *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1); } static void pch_can_set_int_enables(struct pch_can_priv *priv, @@ -277,19 +266,19 @@ static void pch_can_set_int_enables(struct pch_can_priv *priv, { switch (interrupt_no) { case PCH_CAN_ENABLE: - pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE); + pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE); break; case PCH_CAN_DISABLE: - pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE); + pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE); break; case PCH_CAN_ALL: - pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE); + pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); break; case PCH_CAN_NONE: - pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE); + pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); break; default: @@ -300,12 +289,12 @@ static void pch_can_set_int_enables(struct pch_can_priv *priv, static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num) { - u32 counter = COUNTER_LIMIT; + u32 counter = PCH_COUNTER_LIMIT; u32 ifx_creq; iowrite32(num, creq_addr); while (counter) { - ifx_creq = ioread32(creq_addr) & CAN_IF_CREQ_BUSY; + ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY; if (!ifx_creq) break; counter--; @@ -315,143 +304,76 @@ static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num) pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__); } -static void pch_can_set_rx_enable(struct pch_can_priv *priv, u32 buff_num, - u32 set) +static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, + u32 set, enum pch_ifreg dir) { - unsigned long flags; + u32 ie; + + if (dir) + ie = PCH_IF_MCONT_TXIE; + else + ie = PCH_IF_MCONT_RXIE; - spin_lock_irqsave(&priv->msgif_reg_lock, flags); /* Reading the receive buffer data from RAM to Interface1 registers */ - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask); - pch_can_check_if_busy(&priv->regs->if1_creq, buff_num); + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); + pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */ - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL, - &priv->regs->if1_cmask); + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL, + &priv->regs->ifregs[dir].cmask); - if (set == ENABLE) { + if (set == PCH_ENABLE) { /* Setting the MsgVal and RxIE bits */ - pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE); - pch_can_bit_set(&priv->regs->if1_id2, CAN_ID_MSGVAL); + pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie); + pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); - } else if (set == DISABLE) { + } else if (set == PCH_DISABLE) { /* Resetting the MsgVal and RxIE bits */ - pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE); - pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID_MSGVAL); + pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie); + pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); } - pch_can_check_if_busy(&priv->regs->if1_creq, buff_num); - spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); + pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); } -static void pch_can_rx_enable_all(struct pch_can_priv *priv) +static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set) { int i; /* Traversing to obtain the object configured as receivers. */ - for (i = 0; i < PCH_OBJ_NUM; i++) { - if (priv->msg_obj[i] == MSG_OBJ_RX) - pch_can_set_rx_enable(priv, i + 1, ENABLE); - } -} - -static void pch_can_rx_disable_all(struct pch_can_priv *priv) -{ - int i; - - /* Traversing to obtain the object configured as receivers. */ - for (i = 0; i < PCH_OBJ_NUM; i++) { - if (priv->msg_obj[i] == MSG_OBJ_RX) - pch_can_set_rx_enable(priv, i + 1, DISABLE); - } -} - -static void pch_can_set_tx_enable(struct pch_can_priv *priv, u32 buff_num, - u32 set) -{ - unsigned long flags; - - spin_lock_irqsave(&priv->msgif_reg_lock, flags); - /* Reading the Msg buffer from Message RAM to Interface2 registers. */ - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask); - pch_can_check_if_busy(&priv->regs->if2_creq, buff_num); - - /* Setting the IF2CMASK register for accessing the - MsgVal and TxIE bits */ - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL, - &priv->regs->if2_cmask); - - if (set == ENABLE) { - /* Setting the MsgVal and TxIE bits */ - pch_can_bit_set(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE); - pch_can_bit_set(&priv->regs->if2_id2, CAN_ID_MSGVAL); - } else if (set == DISABLE) { - /* Resetting the MsgVal and TxIE bits. */ - pch_can_bit_clear(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE); - pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID_MSGVAL); - } - - pch_can_check_if_busy(&priv->regs->if2_creq, buff_num); - spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); + for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) + pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG); } -static void pch_can_tx_enable_all(struct pch_can_priv *priv) +static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set) { int i; /* Traversing to obtain the object configured as transmit object. */ - for (i = 0; i < PCH_OBJ_NUM; i++) { - if (priv->msg_obj[i] == MSG_OBJ_TX) - pch_can_set_tx_enable(priv, i + 1, ENABLE); - } -} - -static void pch_can_tx_disable_all(struct pch_can_priv *priv) -{ - int i; - - /* Traversing to obtain the object configured as transmit object. */ - for (i = 0; i < PCH_OBJ_NUM; i++) { - if (priv->msg_obj[i] == MSG_OBJ_TX) - pch_can_set_tx_enable(priv, i + 1, DISABLE); - } + for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) + pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG); } -static void pch_can_get_rx_enable(struct pch_can_priv *priv, u32 buff_num, - u32 *enable) +static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, + enum pch_ifreg dir) { - unsigned long flags; + u32 ie, enable; - spin_lock_irqsave(&priv->msgif_reg_lock, flags); - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask); - pch_can_check_if_busy(&priv->regs->if1_creq, buff_num); - - if (((ioread32(&priv->regs->if1_id2)) & CAN_ID_MSGVAL) && - ((ioread32(&priv->regs->if1_mcont)) & - CAN_IF_MCONT_RXIE)) - *enable = ENABLE; + if (dir) + ie = PCH_IF_MCONT_RXIE; else - *enable = DISABLE; - spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); -} + ie = PCH_IF_MCONT_TXIE; -static void pch_can_get_tx_enable(struct pch_can_priv *priv, u32 buff_num, - u32 *enable) -{ - unsigned long flags; - - spin_lock_irqsave(&priv->msgif_reg_lock, flags); - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask); - pch_can_check_if_busy(&priv->regs->if2_creq, buff_num); + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); + pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); - if (((ioread32(&priv->regs->if2_id2)) & CAN_ID_MSGVAL) && - ((ioread32(&priv->regs->if2_mcont)) & - CAN_IF_MCONT_TXIE)) { - *enable = ENABLE; + if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) && + ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) { + enable = 1; } else { - *enable = DISABLE; + enable = 0; } - spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); + return enable; } static int pch_can_int_pending(struct pch_can_priv *priv) @@ -462,141 +384,131 @@ static int pch_can_int_pending(struct pch_can_priv *priv) static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num, u32 set) { - unsigned long flags; - - spin_lock_irqsave(&priv->msgif_reg_lock, flags); - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask); - pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num); - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL, &priv->regs->if1_cmask); - if (set == ENABLE) - pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB); + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); + pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, + &priv->regs->ifregs[0].cmask); + if (set == PCH_ENABLE) + pch_can_bit_clear(&priv->regs->ifregs[0].mcont, + PCH_IF_MCONT_EOB); else - pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB); + pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); - pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num); - spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); + pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); } static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num, u32 *link) { - unsigned long flags; - - spin_lock_irqsave(&priv->msgif_reg_lock, flags); - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask); - pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num); + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); + pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); - if (ioread32(&priv->regs->if1_mcont) & CAN_IF_MCONT_EOB) - *link = DISABLE; + if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB) + *link = PCH_DISABLE; else - *link = ENABLE; - spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); + *link = PCH_ENABLE; } static void pch_can_clear_buffers(struct pch_can_priv *priv) { int i; - for (i = 0; i < PCH_RX_OBJ_NUM; i++) { - iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if1_cmask); - iowrite32(0xffff, &priv->regs->if1_mask1); - iowrite32(0xffff, &priv->regs->if1_mask2); - iowrite32(0x0, &priv->regs->if1_id1); - iowrite32(0x0, &priv->regs->if1_id2); - iowrite32(0x0, &priv->regs->if1_mcont); - iowrite32(0x0, &priv->regs->if1_dataa1); - iowrite32(0x0, &priv->regs->if1_dataa2); - iowrite32(0x0, &priv->regs->if1_datab1); - iowrite32(0x0, &priv->regs->if1_datab2); - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | - CAN_CMASK_ARB | CAN_CMASK_CTRL, - &priv->regs->if1_cmask); - pch_can_check_if_busy(&priv->regs->if1_creq, i+1); + for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { + iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask); + iowrite32(0xffff, &priv->regs->ifregs[0].mask1); + iowrite32(0xffff, &priv->regs->ifregs[0].mask2); + iowrite32(0x0, &priv->regs->ifregs[0].id1); + iowrite32(0x0, &priv->regs->ifregs[0].id2); + iowrite32(0x0, &priv->regs->ifregs[0].mcont); + iowrite32(0x0, &priv->regs->ifregs[0].dataa1); + iowrite32(0x0, &priv->regs->ifregs[0].dataa2); + iowrite32(0x0, &priv->regs->ifregs[0].datab1); + iowrite32(0x0, &priv->regs->ifregs[0].datab2); + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | + PCH_CMASK_ARB | PCH_CMASK_CTRL, + &priv->regs->ifregs[0].cmask); + pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); } - for (i = i; i < PCH_OBJ_NUM; i++) { - iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if2_cmask); - iowrite32(0xffff, &priv->regs->if2_mask1); - iowrite32(0xffff, &priv->regs->if2_mask2); - iowrite32(0x0, &priv->regs->if2_id1); - iowrite32(0x0, &priv->regs->if2_id2); - iowrite32(0x0, &priv->regs->if2_mcont); - iowrite32(0x0, &priv->regs->if2_dataa1); - iowrite32(0x0, &priv->regs->if2_dataa2); - iowrite32(0x0, &priv->regs->if2_datab1); - iowrite32(0x0, &priv->regs->if2_datab2); - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | - CAN_CMASK_ARB | CAN_CMASK_CTRL, - &priv->regs->if2_cmask); - pch_can_check_if_busy(&priv->regs->if2_creq, i+1); + for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { + iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[1].cmask); + iowrite32(0xffff, &priv->regs->ifregs[1].mask1); + iowrite32(0xffff, &priv->regs->ifregs[1].mask2); + iowrite32(0x0, &priv->regs->ifregs[1].id1); + iowrite32(0x0, &priv->regs->ifregs[1].id2); + iowrite32(0x0, &priv->regs->ifregs[1].mcont); + iowrite32(0x0, &priv->regs->ifregs[1].dataa1); + iowrite32(0x0, &priv->regs->ifregs[1].dataa2); + iowrite32(0x0, &priv->regs->ifregs[1].datab1); + iowrite32(0x0, &priv->regs->ifregs[1].datab2); + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | + PCH_CMASK_ARB | PCH_CMASK_CTRL, + &priv->regs->ifregs[1].cmask); + pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); } } static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) { int i; - unsigned long flags; - spin_lock_irqsave(&priv->msgif_reg_lock, flags); + for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { + iowrite32(PCH_CMASK_RX_TX_GET, + &priv->regs->ifregs[0].cmask); + pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); - for (i = 0; i < PCH_OBJ_NUM; i++) { - if (priv->msg_obj[i] == MSG_OBJ_RX) { - iowrite32(CAN_CMASK_RX_TX_GET, - &priv->regs->if1_cmask); - pch_can_check_if_busy(&priv->regs->if1_creq, i+1); + iowrite32(0x0, &priv->regs->ifregs[0].id1); + iowrite32(0x0, &priv->regs->ifregs[0].id2); - iowrite32(0x0, &priv->regs->if1_id1); - iowrite32(0x0, &priv->regs->if1_id2); + pch_can_bit_set(&priv->regs->ifregs[0].mcont, + PCH_IF_MCONT_UMASK); - pch_can_bit_set(&priv->regs->if1_mcont, - CAN_IF_MCONT_UMASK); + /* Set FIFO mode set to 0 except last Rx Obj*/ + pch_can_bit_clear(&priv->regs->ifregs[0].mcont, + PCH_IF_MCONT_EOB); + /* In case FIFO mode, Last EoB of Rx Obj must be 1 */ + if (i == PCH_RX_OBJ_END) + pch_can_bit_set(&priv->regs->ifregs[0].mcont, + PCH_IF_MCONT_EOB); - /* Set FIFO mode set to 0 except last Rx Obj*/ - pch_can_bit_clear(&priv->regs->if1_mcont, - CAN_IF_MCONT_EOB); - /* In case FIFO mode, Last EoB of Rx Obj must be 1 */ - if (i == (PCH_RX_OBJ_NUM - 1)) - pch_can_bit_set(&priv->regs->if1_mcont, - CAN_IF_MCONT_EOB); + iowrite32(0, &priv->regs->ifregs[0].mask1); + pch_can_bit_clear(&priv->regs->ifregs[0].mask2, + 0x1fff | PCH_MASK2_MDIR_MXTD); - iowrite32(0, &priv->regs->if1_mask1); - pch_can_bit_clear(&priv->regs->if1_mask2, - 0x1fff | CAN_MASK2_MDIR_MXTD); + /* Setting CMASK for writing */ + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | + PCH_CMASK_ARB | PCH_CMASK_CTRL, + &priv->regs->ifregs[0].cmask); - /* Setting CMASK for writing */ - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | - CAN_CMASK_ARB | CAN_CMASK_CTRL, - &priv->regs->if1_cmask); + pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); + } - pch_can_check_if_busy(&priv->regs->if1_creq, i+1); - } else if (priv->msg_obj[i] == MSG_OBJ_TX) { - iowrite32(CAN_CMASK_RX_TX_GET, - &priv->regs->if2_cmask); - pch_can_check_if_busy(&priv->regs->if2_creq, i+1); + for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { + iowrite32(PCH_CMASK_RX_TX_GET, + &priv->regs->ifregs[1].cmask); + pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); - /* Resetting DIR bit for reception */ - iowrite32(0x0, &priv->regs->if2_id1); - iowrite32(0x0, &priv->regs->if2_id2); - pch_can_bit_set(&priv->regs->if2_id2, CAN_ID2_DIR); + /* Resetting DIR bit for reception */ + iowrite32(0x0, &priv->regs->ifregs[1].id1); + iowrite32(0x0, &priv->regs->ifregs[1].id2); + pch_can_bit_set(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); - /* Setting EOB bit for transmitter */ - iowrite32(CAN_IF_MCONT_EOB, &priv->regs->if2_mcont); + /* Setting EOB bit for transmitter */ + iowrite32(PCH_IF_MCONT_EOB, &priv->regs->ifregs[1].mcont); - pch_can_bit_set(&priv->regs->if2_mcont, - CAN_IF_MCONT_UMASK); + pch_can_bit_set(&priv->regs->ifregs[1].mcont, + PCH_IF_MCONT_UMASK); - iowrite32(0, &priv->regs->if2_mask1); - pch_can_bit_clear(&priv->regs->if2_mask2, 0x1fff); + iowrite32(0, &priv->regs->ifregs[1].mask1); + pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); - /* Setting CMASK for writing */ - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | - CAN_CMASK_ARB | CAN_CMASK_CTRL, - &priv->regs->if2_cmask); + /* Setting CMASK for writing */ + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | + PCH_CMASK_ARB | PCH_CMASK_CTRL, + &priv->regs->ifregs[1].cmask); - pch_can_check_if_busy(&priv->regs->if2_creq, i+1); - } + pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); } - spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); } static void pch_can_init(struct pch_can_priv *priv) @@ -623,50 +535,50 @@ static void pch_can_release(struct pch_can_priv *priv) pch_can_set_int_enables(priv, PCH_CAN_NONE); /* Disabling all the receive object. */ - pch_can_rx_disable_all(priv); + pch_can_set_rx_all(priv, 0); /* Disabling all the transmit object. */ - pch_can_tx_disable_all(priv); + pch_can_set_tx_all(priv, 0); } /* This function clears interrupt(s) from the CAN device. */ static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) { - if (mask == CAN_STATUS_INT) { + if (mask == PCH_STATUS_INT) { ioread32(&priv->regs->stat); return; } /* Clear interrupt for transmit object */ - if (priv->msg_obj[mask - 1] == MSG_OBJ_TX) { - /* Setting CMASK for clearing interrupts for - frame transmission. */ - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB, - &priv->regs->if2_cmask); - - /* Resetting the ID registers. */ - pch_can_bit_set(&priv->regs->if2_id2, - CAN_ID2_DIR | (0x7ff << 2)); - iowrite32(0x0, &priv->regs->if2_id1); - - /* Claring NewDat, TxRqst & IntPnd */ - pch_can_bit_clear(&priv->regs->if2_mcont, - CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND | - CAN_IF_MCONT_TXRQXT); - pch_can_check_if_busy(&priv->regs->if2_creq, mask); - } else if (priv->msg_obj[mask - 1] == MSG_OBJ_RX) { + if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { /* Setting CMASK for clearing the reception interrupts. */ - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB, - &priv->regs->if1_cmask); + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, + &priv->regs->ifregs[0].cmask); /* Clearing the Dir bit. */ - pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR); + pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); /* Clearing NewDat & IntPnd */ - pch_can_bit_clear(&priv->regs->if1_mcont, - CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND); + pch_can_bit_clear(&priv->regs->ifregs[0].mcont, + PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND); + + pch_can_check_if_busy(&priv->regs->ifregs[0].creq, mask); + } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) { + /* Setting CMASK for clearing interrupts for + frame transmission. */ + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, + &priv->regs->ifregs[1].cmask); + + /* Resetting the ID registers. */ + pch_can_bit_set(&priv->regs->ifregs[1].id2, + PCH_ID2_DIR | (0x7ff << 2)); + iowrite32(0x0, &priv->regs->ifregs[1].id1); - pch_can_check_if_busy(&priv->regs->if1_creq, mask); + /* Claring NewDat, TxRqst & IntPnd */ + pch_can_bit_clear(&priv->regs->ifregs[1].mcont, + PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | + PCH_IF_MCONT_TXRQXT); + pch_can_check_if_busy(&priv->regs->ifregs[1].creq, mask); } } @@ -688,7 +600,7 @@ static void pch_can_error(struct net_device *ndev, u32 status) struct sk_buff *skb; struct pch_can_priv *priv = netdev_priv(ndev); struct can_frame *cf; - u32 errc; + u32 errc, lec; struct net_device_stats *stats = &(priv->ndev->stats); enum can_state state = priv->can.state; @@ -697,8 +609,8 @@ static void pch_can_error(struct net_device *ndev, u32 status) return; if (status & PCH_BUS_OFF) { - pch_can_tx_disable_all(priv); - pch_can_rx_disable_all(priv); + pch_can_set_tx_all(priv, 0); + pch_can_set_rx_all(priv, 0); state = CAN_STATE_BUS_OFF; cf->can_id |= CAN_ERR_BUSOFF; can_bus_off(ndev); @@ -712,9 +624,9 @@ static void pch_can_error(struct net_device *ndev, u32 status) priv->can.can_stats.error_warning++; cf->can_id |= CAN_ERR_CRTL; errc = ioread32(&priv->regs->errc); - if (((errc & CAN_REC) >> 8) > 96) + if (((errc & PCH_REC) >> 8) > 96) cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; - if ((errc & CAN_TEC) > 96) + if ((errc & PCH_TEC) > 96) cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; dev_warn(&ndev->dev, "%s -> Error Counter is more than 96.\n", __func__); @@ -725,41 +637,45 @@ static void pch_can_error(struct net_device *ndev, u32 status) state = CAN_STATE_ERROR_PASSIVE; cf->can_id |= CAN_ERR_CRTL; errc = ioread32(&priv->regs->errc); - if (((errc & CAN_REC) >> 8) > 127) + if (((errc & PCH_REC) >> 8) > 127) cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; - if ((errc & CAN_TEC) > 127) + if ((errc & PCH_TEC) > 127) cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; dev_err(&ndev->dev, "%s -> CAN controller is ERROR PASSIVE .\n", __func__); } - if (status & PCH_LEC_ALL) { + lec = status & PCH_LEC_ALL; + switch (lec) { + case PCH_STUF_ERR: + cf->data[2] |= CAN_ERR_PROT_STUFF; priv->can.can_stats.bus_error++; stats->rx_errors++; - switch (status & PCH_LEC_ALL) { - case PCH_STUF_ERR: - cf->data[2] |= CAN_ERR_PROT_STUFF; - break; - case PCH_FORM_ERR: - cf->data[2] |= CAN_ERR_PROT_FORM; - break; - case PCH_ACK_ERR: - cf->data[2] |= CAN_ERR_PROT_LOC_ACK | - CAN_ERR_PROT_LOC_ACK_DEL; - break; - case PCH_BIT1_ERR: - case PCH_BIT0_ERR: - cf->data[2] |= CAN_ERR_PROT_BIT; - break; - case PCH_CRC_ERR: - cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | - CAN_ERR_PROT_LOC_CRC_DEL; - break; - default: - iowrite32(status | PCH_LEC_ALL, &priv->regs->stat); - break; - } - + break; + case PCH_FORM_ERR: + cf->data[2] |= CAN_ERR_PROT_FORM; + priv->can.can_stats.bus_error++; + stats->rx_errors++; + break; + case PCH_ACK_ERR: + cf->can_id |= CAN_ERR_ACK; + priv->can.can_stats.bus_error++; + stats->rx_errors++; + break; + case PCH_BIT1_ERR: + case PCH_BIT0_ERR: + cf->data[2] |= CAN_ERR_PROT_BIT; + priv->can.can_stats.bus_error++; + stats->rx_errors++; + break; + case PCH_CRC_ERR: + cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | + CAN_ERR_PROT_LOC_CRC_DEL; + priv->can.can_stats.bus_error++; + stats->rx_errors++; + break; + case PCH_LEC_ALL: /* Written by CPU. No error status */ + break; } priv->can.state = state; @@ -795,22 +711,22 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat) struct net_device_stats *stats = &(priv->ndev->stats); /* Reading the messsage object from the Message RAM */ - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask); - pch_can_check_if_busy(&priv->regs->if1_creq, int_stat); + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); + pch_can_check_if_busy(&priv->regs->ifregs[0].creq, int_stat); /* Reading the MCONT register. */ - reg = ioread32(&priv->regs->if1_mcont); + reg = ioread32(&priv->regs->ifregs[0].mcont); reg &= 0xffff; - for (k = int_stat; !(reg & CAN_IF_MCONT_EOB); k++) { + for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) { /* If MsgLost bit set. */ - if (reg & CAN_IF_MCONT_MSGLOST) { + if (reg & PCH_IF_MCONT_MSGLOST) { dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n"); - pch_can_bit_clear(&priv->regs->if1_mcont, - CAN_IF_MCONT_MSGLOST); - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL, - &priv->regs->if1_cmask); - pch_can_check_if_busy(&priv->regs->if1_creq, k); + pch_can_bit_clear(&priv->regs->ifregs[0].mcont, + PCH_IF_MCONT_MSGLOST); + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, + &priv->regs->ifregs[0].cmask); + pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); skb = alloc_can_err_skb(ndev, &cf); if (!skb) @@ -828,7 +744,7 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat) rcv_pkts++; goto RX_NEXT; } - if (!(reg & CAN_IF_MCONT_NEWDAT)) + if (!(reg & PCH_IF_MCONT_NEWDAT)) goto RX_NEXT; skb = alloc_can_skb(priv->ndev, &cf); @@ -836,29 +752,30 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat) return -ENOMEM; /* Get Received data */ - ide = ((ioread32(&priv->regs->if1_id2)) & CAN_ID2_XTD) >> 14; + ide = ((ioread32(&priv->regs->ifregs[0].id2)) & PCH_ID2_XTD) >> + 14; if (ide) { - id = (ioread32(&priv->regs->if1_id1) & 0xffff); - id |= (((ioread32(&priv->regs->if1_id2)) & + id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff); + id |= (((ioread32(&priv->regs->ifregs[0].id2)) & 0x1fff) << 16); cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; } else { - id = (((ioread32(&priv->regs->if1_id2)) & - (CAN_SFF_MASK << 2)) >> 2); + id = (((ioread32(&priv->regs->ifregs[0].id2)) & + (CAN_SFF_MASK << 2)) >> 2); cf->can_id = (id & CAN_SFF_MASK); } - rtr = (ioread32(&priv->regs->if1_id2) & CAN_ID2_DIR); + rtr = (ioread32(&priv->regs->ifregs[0].id2) & PCH_ID2_DIR); if (rtr) { cf->can_dlc = 0; cf->can_id |= CAN_RTR_FLAG; } else { - cf->can_dlc = ((ioread32(&priv->regs->if1_mcont)) & - 0x0f); + cf->can_dlc = + ((ioread32(&priv->regs->ifregs[0].mcont)) & 0x0f); } for (i = 0, j = 0; i < cf->can_dlc; j++) { - reg = ioread32(&priv->regs->if1_dataa1 + j*4); + reg = ioread32(&priv->regs->ifregs[0].dataa1 + j*4); cf->data[i++] = cpu_to_le32(reg & 0xff); if (i == cf->can_dlc) break; @@ -871,16 +788,17 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat) stats->rx_bytes += cf->can_dlc; if (k < PCH_FIFO_THRESH) { - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | - CAN_CMASK_ARB, &priv->regs->if1_cmask); + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | + PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask); /* Clearing the Dir bit. */ - pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR); + pch_can_bit_clear(&priv->regs->ifregs[0].id2, + PCH_ID2_DIR); /* Clearing NewDat & IntPnd */ - pch_can_bit_clear(&priv->regs->if1_mcont, - CAN_IF_MCONT_INTPND); - pch_can_check_if_busy(&priv->regs->if1_creq, k); + pch_can_bit_clear(&priv->regs->ifregs[0].mcont, + PCH_IF_MCONT_INTPND); + pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); } else if (k > PCH_FIFO_THRESH) { pch_can_int_clr(priv, k); } else if (k == PCH_FIFO_THRESH) { @@ -890,9 +808,9 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat) } RX_NEXT: /* Reading the messsage object from the Message RAM */ - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask); - pch_can_check_if_busy(&priv->regs->if1_creq, k + 1); - reg = ioread32(&priv->regs->if1_mcont); + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); + pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); + reg = ioread32(&priv->regs->ifregs[0].mcont); } return rcv_pkts; @@ -906,14 +824,13 @@ static int pch_can_rx_poll(struct napi_struct *napi, int quota) u32 int_stat; int rcv_pkts = 0; u32 reg_stat; - unsigned long flags; int_stat = pch_can_int_pending(priv); if (!int_stat) return 0; INT_STAT: - if (int_stat == CAN_STATUS_INT) { + if (int_stat == PCH_STATUS_INT) { reg_stat = ioread32(&priv->regs->stat); if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) { if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) @@ -921,11 +838,10 @@ INT_STAT: } if (reg_stat & PCH_TX_OK) { - spin_lock_irqsave(&priv->msgif_reg_lock, flags); - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask); - pch_can_check_if_busy(&priv->regs->if2_creq, + iowrite32(PCH_CMASK_RX_TX_GET, + &priv->regs->ifregs[1].cmask); + pch_can_check_if_busy(&priv->regs->ifregs[1].creq, ioread32(&priv->regs->intr)); - spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK); } @@ -933,37 +849,32 @@ INT_STAT: pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK); int_stat = pch_can_int_pending(priv); - if (int_stat == CAN_STATUS_INT) + if (int_stat == PCH_STATUS_INT) goto INT_STAT; } MSG_OBJ: - if ((int_stat >= 1) && (int_stat <= PCH_RX_OBJ_NUM)) { - spin_lock_irqsave(&priv->msgif_reg_lock, flags); + if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) { rcv_pkts = pch_can_rx_normal(ndev, int_stat); - spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); if (rcv_pkts < 0) return 0; - } else if ((int_stat > PCH_RX_OBJ_NUM) && (int_stat <= PCH_OBJ_NUM)) { - if (priv->msg_obj[int_stat - 1] == MSG_OBJ_TX) { - /* Handle transmission interrupt */ - can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_NUM - 1); - spin_lock_irqsave(&priv->msgif_reg_lock, flags); - iowrite32(CAN_CMASK_RX_TX_GET | CAN_CMASK_CLRINTPND, - &priv->regs->if2_cmask); - dlc = ioread32(&priv->regs->if2_mcont) & - CAN_IF_MCONT_DLC; - pch_can_check_if_busy(&priv->regs->if2_creq, int_stat); - spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); - if (dlc > 8) - dlc = 8; - stats->tx_bytes += dlc; - stats->tx_packets++; - } + } else if ((int_stat >= PCH_TX_OBJ_START) && + (int_stat <= PCH_TX_OBJ_END)) { + /* Handle transmission interrupt */ + can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1); + iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND, + &priv->regs->ifregs[1].cmask); + dlc = ioread32(&priv->regs->ifregs[1].mcont) & + PCH_IF_MCONT_DLC; + pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat); + if (dlc > 8) + dlc = 8; + stats->tx_bytes += dlc; + stats->tx_packets++; } int_stat = pch_can_int_pending(priv); - if (int_stat == CAN_STATUS_INT) + if (int_stat == PCH_STATUS_INT) goto INT_STAT; else if (int_stat >= 1 && int_stat <= 32) goto MSG_OBJ; @@ -983,17 +894,17 @@ static int pch_set_bittiming(struct net_device *ndev) u32 brp; /* Setting the CCE bit for accessing the Can Timing register. */ - pch_can_bit_set(&priv->regs->cont, CAN_CTRL_CCE); + pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE); brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1; - canbit = brp & MSK_BITT_BRP; - canbit |= (bt->sjw - 1) << BIT_BITT_SJW; - canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << BIT_BITT_TSEG1; - canbit |= (bt->phase_seg2 - 1) << BIT_BITT_TSEG2; - bepe = (brp & MSK_BRPE_BRPE) >> BIT_BRPE_BRPE; + canbit = brp & PCH_MSK_BITT_BRP; + canbit |= (bt->sjw - 1) << PCH_BIT_SJW; + canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1; + canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2; + bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE; iowrite32(canbit, &priv->regs->bitt); iowrite32(bepe, &priv->regs->brpe); - pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_CCE); + pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE); return 0; } @@ -1008,8 +919,8 @@ static void pch_can_start(struct net_device *ndev) pch_set_bittiming(ndev); pch_can_set_optmode(priv); - pch_can_tx_enable_all(priv); - pch_can_rx_enable_all(priv); + pch_can_set_tx_all(priv, 1); + pch_can_set_rx_all(priv, 1); /* Setting the CAN to run mode. */ pch_can_set_run_mode(priv, PCH_CAN_RUN); @@ -1113,7 +1024,6 @@ static int pch_get_msg_obj_sts(struct net_device *ndev, u32 obj_id) static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) { int i, j; - unsigned long flags; struct pch_can_priv *priv = netdev_priv(ndev); struct can_frame *cf = (struct can_frame *)skb->data; int tx_buffer_avail = 0; @@ -1121,72 +1031,68 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) if (can_dropped_invalid_skb(ndev, skb)) return NETDEV_TX_OK; - if (priv->tx_obj == (PCH_OBJ_NUM + 1)) { /* Point tail Obj */ + if (priv->tx_obj == PCH_TX_OBJ_END) { /* Point tail Obj */ while (pch_get_msg_obj_sts(ndev, (((1 << PCH_TX_OBJ_NUM)-1) << PCH_RX_OBJ_NUM))) udelay(500); - priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj ID */ + priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj ID */ tx_buffer_avail = priv->tx_obj; /* Point Tail of Tx Obj */ } else { tx_buffer_avail = priv->tx_obj; } priv->tx_obj++; - /* Attaining the lock. */ - spin_lock_irqsave(&priv->msgif_reg_lock, flags); - /* Reading the Msg Obj from the Msg RAM to the Interface register. */ - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask); - pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail); + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); + pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); /* Setting the CMASK register. */ - pch_can_bit_set(&priv->regs->if2_cmask, CAN_CMASK_ALL); + pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); /* If ID extended is set. */ - pch_can_bit_clear(&priv->regs->if2_id1, 0xffff); - pch_can_bit_clear(&priv->regs->if2_id2, 0x1fff | CAN_ID2_XTD); + pch_can_bit_clear(&priv->regs->ifregs[1].id1, 0xffff); + pch_can_bit_clear(&priv->regs->ifregs[1].id2, 0x1fff | PCH_ID2_XTD); if (cf->can_id & CAN_EFF_FLAG) { - pch_can_bit_set(&priv->regs->if2_id1, cf->can_id & 0xffff); - pch_can_bit_set(&priv->regs->if2_id2, - ((cf->can_id >> 16) & 0x1fff) | CAN_ID2_XTD); + pch_can_bit_set(&priv->regs->ifregs[1].id1, + cf->can_id & 0xffff); + pch_can_bit_set(&priv->regs->ifregs[1].id2, + ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD); } else { - pch_can_bit_set(&priv->regs->if2_id1, 0); - pch_can_bit_set(&priv->regs->if2_id2, + pch_can_bit_set(&priv->regs->ifregs[1].id1, 0); + pch_can_bit_set(&priv->regs->ifregs[1].id2, (cf->can_id & CAN_SFF_MASK) << 2); } /* If remote frame has to be transmitted.. */ if (cf->can_id & CAN_RTR_FLAG) - pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID2_DIR); + pch_can_bit_clear(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); for (i = 0, j = 0; i < cf->can_dlc; j++) { iowrite32(le32_to_cpu(cf->data[i++]), - (&priv->regs->if2_dataa1) + j*4); + (&priv->regs->ifregs[1].dataa1) + j*4); if (i == cf->can_dlc) break; iowrite32(le32_to_cpu(cf->data[i++] << 8), - (&priv->regs->if2_dataa1) + j*4); + (&priv->regs->ifregs[1].dataa1) + j*4); } - can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_NUM - 1); + can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_END - 1); /* Updating the size of the data. */ - pch_can_bit_clear(&priv->regs->if2_mcont, 0x0f); - pch_can_bit_set(&priv->regs->if2_mcont, cf->can_dlc); + pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 0x0f); + pch_can_bit_set(&priv->regs->ifregs[1].mcont, cf->can_dlc); /* Clearing IntPend, NewDat & TxRqst */ - pch_can_bit_clear(&priv->regs->if2_mcont, - CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND | - CAN_IF_MCONT_TXRQXT); + pch_can_bit_clear(&priv->regs->ifregs[1].mcont, + PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | + PCH_IF_MCONT_TXRQXT); /* Setting NewDat, TxRqst bits */ - pch_can_bit_set(&priv->regs->if2_mcont, - CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_TXRQXT); - - pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail); + pch_can_bit_set(&priv->regs->ifregs[1].mcont, + PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT); - spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); + pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); return NETDEV_TX_OK; } @@ -1244,27 +1150,20 @@ static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) pch_can_set_int_enables(priv, PCH_CAN_DISABLE); /* Save Tx buffer enable state */ - for (i = 0; i < PCH_OBJ_NUM; i++) { - if (priv->msg_obj[i] == MSG_OBJ_TX) - pch_can_get_tx_enable(priv, i + 1, - &(priv->tx_enable[i])); - } + for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) + priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG); /* Disable all Transmit buffers */ - pch_can_tx_disable_all(priv); + pch_can_set_tx_all(priv, 0); /* Save Rx buffer enable state */ - for (i = 0; i < PCH_OBJ_NUM; i++) { - if (priv->msg_obj[i] == MSG_OBJ_RX) { - pch_can_get_rx_enable(priv, i + 1, - &(priv->rx_enable[i])); - pch_can_get_rx_buffer_link(priv, i + 1, - &(priv->rx_link[i])); - } + for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { + priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG); + pch_can_get_rx_buffer_link(priv, i, &priv->rx_link[i]); } /* Disable all Receive buffers */ - pch_can_rx_disable_all(priv); + pch_can_set_rx_all(priv, 0); retval = pci_save_state(pdev); if (retval) { dev_err(&pdev->dev, "pci_save_state failed.\n"); @@ -1312,23 +1211,16 @@ static int pch_can_resume(struct pci_dev *pdev) pch_can_set_optmode(priv); /* Enabling the transmit buffer. */ - for (i = 0; i < PCH_OBJ_NUM; i++) { - if (priv->msg_obj[i] == MSG_OBJ_TX) { - pch_can_set_tx_enable(priv, i + 1, - priv->tx_enable[i]); - } - } + for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) + pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG); /* Configuring the receive buffer and enabling them. */ - for (i = 0; i < PCH_OBJ_NUM; i++) { - if (priv->msg_obj[i] == MSG_OBJ_RX) { - /* Restore buffer link */ - pch_can_set_rx_buffer_link(priv, i + 1, - priv->rx_link[i]); - - /* Restore buffer enables */ - pch_can_set_rx_enable(priv, i + 1, priv->rx_enable[i]); - } + for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { + /* Restore buffer link */ + pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]); + + /* Restore buffer enables */ + pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG); } /* Enable CAN Interrupts */ @@ -1349,8 +1241,8 @@ static int pch_can_get_berr_counter(const struct net_device *dev, { struct pch_can_priv *priv = netdev_priv(dev); - bec->txerr = ioread32(&priv->regs->errc) & CAN_TEC; - bec->rxerr = (ioread32(&priv->regs->errc) & CAN_REC) >> 8; + bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC; + bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8; return 0; } @@ -1361,7 +1253,6 @@ static int __devinit pch_can_probe(struct pci_dev *pdev, struct net_device *ndev; struct pch_can_priv *priv; int rc; - int index; void __iomem *addr; rc = pci_enable_device(pdev); @@ -1383,7 +1274,7 @@ static int __devinit pch_can_probe(struct pci_dev *pdev, goto probe_exit_ipmap; } - ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_NUM); + ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END); if (!ndev) { rc = -ENOMEM; dev_err(&pdev->dev, "Failed alloc_candev\n"); @@ -1399,7 +1290,7 @@ static int __devinit pch_can_probe(struct pci_dev *pdev, priv->can.do_get_berr_counter = pch_can_get_berr_counter; priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_LOOPBACK; - priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj */ + priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */ ndev->irq = pdev->irq; ndev->flags |= IFF_ECHO; @@ -1407,15 +1298,9 @@ static int __devinit pch_can_probe(struct pci_dev *pdev, pci_set_drvdata(pdev, ndev); SET_NETDEV_DEV(ndev, &pdev->dev); ndev->netdev_ops = &pch_can_netdev_ops; - priv->can.clock.freq = PCH_CAN_CLK; /* Hz */ - for (index = 0; index < PCH_RX_OBJ_NUM;) - priv->msg_obj[index++] = MSG_OBJ_RX; - - for (index = index; index < PCH_OBJ_NUM;) - priv->msg_obj[index++] = MSG_OBJ_TX; - netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_NUM); + netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_END); rc = register_candev(ndev); if (rc) { |
