diff options
Diffstat (limited to 'drivers/media')
302 files changed, 38722 insertions, 5815 deletions
diff --git a/drivers/media/common/siano/smsdvb-debugfs.c b/drivers/media/common/siano/smsdvb-debugfs.c index 0bb4430..2408d7e 100644 --- a/drivers/media/common/siano/smsdvb-debugfs.c +++ b/drivers/media/common/siano/smsdvb-debugfs.c @@ -1,6 +1,6 @@ /*********************************************************************** * - * Copyright(c) 2013 Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright(c) 2013 Mauro Carvalho Chehab * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/media/common/siano/smsir.c b/drivers/media/common/siano/smsir.c index b8c5cad..6d7c0c8 100644 --- a/drivers/media/common/siano/smsir.c +++ b/drivers/media/common/siano/smsir.c @@ -88,7 +88,7 @@ int sms_ir_init(struct smscore_device_t *coredev) dev->priv = coredev; dev->driver_type = RC_DRIVER_IR_RAW; - dev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(dev, RC_BIT_ALL); dev->map_name = sms_get_board(board_id)->rc_codes; dev->driver_name = MODULE_NAME; diff --git a/drivers/media/dvb-core/dvb-usb-ids.h b/drivers/media/dvb-core/dvb-usb-ids.h index f19a2cc..1bdc0e7 100644 --- a/drivers/media/dvb-core/dvb-usb-ids.h +++ b/drivers/media/dvb-core/dvb-usb-ids.h @@ -257,6 +257,7 @@ #define USB_PID_TERRATEC_T5 0x10a1 #define USB_PID_NOXON_DAB_STICK 0x00b3 #define USB_PID_NOXON_DAB_STICK_REV2 0x00e0 +#define USB_PID_NOXON_DAB_STICK_REV3 0x00b4 #define USB_PID_PINNACLE_EXPRESSCARD_320CX 0x022e #define USB_PID_PINNACLE_PCTV2000E 0x022c #define USB_PID_PINNACLE_PCTV_DVB_T_FLASH 0x0228 diff --git a/drivers/media/dvb-core/dvb_frontend.c b/drivers/media/dvb-core/dvb_frontend.c index 1f925e8..6ce435a 100644 --- a/drivers/media/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb-core/dvb_frontend.c @@ -1279,7 +1279,7 @@ static int dtv_property_process_get(struct dvb_frontend *fe, switch(tvp->cmd) { case DTV_ENUM_DELSYS: ncaps = 0; - while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { + while (ncaps < MAX_DELSYS && fe->ops.delsys[ncaps]) { tvp->u.buffer.data[ncaps] = fe->ops.delsys[ncaps]; ncaps++; } @@ -1596,7 +1596,7 @@ static int dvbv5_set_delivery_system(struct dvb_frontend *fe, * supported */ ncaps = 0; - while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { + while (ncaps < MAX_DELSYS && fe->ops.delsys[ncaps]) { if (fe->ops.delsys[ncaps] == desired_system) { c->delivery_system = desired_system; dev_dbg(fe->dvb->device, @@ -1628,7 +1628,7 @@ static int dvbv5_set_delivery_system(struct dvb_frontend *fe, * of the desired system */ ncaps = 0; - while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { + while (ncaps < MAX_DELSYS && fe->ops.delsys[ncaps]) { if (dvbv3_type(fe->ops.delsys[ncaps]) == type) delsys = fe->ops.delsys[ncaps]; ncaps++; @@ -1703,7 +1703,7 @@ static int dvbv3_set_delivery_system(struct dvb_frontend *fe) * DVBv3 standard */ ncaps = 0; - while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { + while (ncaps < MAX_DELSYS && fe->ops.delsys[ncaps]) { if (dvbv3_type(fe->ops.delsys[ncaps]) != DVBV3_UNKNOWN) { delsys = fe->ops.delsys[ncaps]; break; @@ -1882,6 +1882,8 @@ static int dtv_property_process_set(struct dvb_frontend *fe, c->lna = tvp->u.data; if (fe->ops.set_lna) r = fe->ops.set_lna(fe); + if (r < 0) + c->lna = LNA_AUTO; break; default: diff --git a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig index dd12a1e..025fc54 100644 --- a/drivers/media/dvb-frontends/Kconfig +++ b/drivers/media/dvb-frontends/Kconfig @@ -441,7 +441,7 @@ config DVB_RTL2830 config DVB_RTL2832 tristate "Realtek RTL2832 DVB-T" - depends on DVB_CORE && I2C + depends on DVB_CORE && I2C && I2C_MUX default m if !MEDIA_SUBDRV_AUTOSELECT help Say Y when you want to support this frontend. @@ -650,6 +650,8 @@ config DVB_TUNER_DIB0090 comment "SEC control devices for DVB-S" depends on DVB_CORE +source "drivers/media/dvb-frontends/drx39xyj/Kconfig" + config DVB_LNBP21 tristate "LNBP21/LNBH24 SEC controllers" depends on DVB_CORE && I2C @@ -733,14 +735,6 @@ config DVB_IX2505V help A DVB-S tuner module. Say Y when you want to support this frontend. -config DVB_IT913X_FE - tristate "it913x frontend and it9137 tuner" - depends on DVB_CORE && I2C - default m if !MEDIA_SUBDRV_AUTOSELECT - help - A DVB-T tuner module. - Say Y when you want to support this frontend. - config DVB_M88RS2000 tristate "M88RS2000 DVB-S demodulator and tuner" depends on DVB_CORE && I2C diff --git a/drivers/media/dvb-frontends/Makefile b/drivers/media/dvb-frontends/Makefile index 0c75a6a..282aba2 100644 --- a/drivers/media/dvb-frontends/Makefile +++ b/drivers/media/dvb-frontends/Makefile @@ -92,13 +92,13 @@ obj-$(CONFIG_DVB_HD29L2) += hd29l2.o obj-$(CONFIG_DVB_DS3000) += ds3000.o obj-$(CONFIG_DVB_TS2020) += ts2020.o obj-$(CONFIG_DVB_MB86A16) += mb86a16.o +obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj/ obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o obj-$(CONFIG_DVB_IX2505V) += ix2505v.o obj-$(CONFIG_DVB_STV0367) += stv0367.o obj-$(CONFIG_DVB_CXD2820R) += cxd2820r.o obj-$(CONFIG_DVB_DRXK) += drxk.o obj-$(CONFIG_DVB_TDA18271C2DD) += tda18271c2dd.o -obj-$(CONFIG_DVB_IT913X_FE) += it913x-fe.o obj-$(CONFIG_DVB_A8293) += a8293.o obj-$(CONFIG_DVB_TDA10071) += tda10071.o obj-$(CONFIG_DVB_RTL2830) += rtl2830.o diff --git a/drivers/media/dvb-frontends/af9033.c b/drivers/media/dvb-frontends/af9033.c index 65728c2..be4bec2 100644 --- a/drivers/media/dvb-frontends/af9033.c +++ b/drivers/media/dvb-frontends/af9033.c @@ -989,10 +989,62 @@ err: return ret; } +static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + + dev_dbg(&state->i2c->dev, "%s: onoff=%d\n", __func__, onoff); + + ret = af9033_wr_reg_mask(state, 0x80f993, onoff, 0x01); + if (ret < 0) + goto err; + + return 0; + +err: + dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); + + return ret; +} + +static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid, int onoff) +{ + struct af9033_state *state = fe->demodulator_priv; + int ret; + u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff}; + + dev_dbg(&state->i2c->dev, "%s: index=%d pid=%04x onoff=%d\n", + __func__, index, pid, onoff); + + if (pid > 0x1fff) + return 0; + + ret = af9033_wr_regs(state, 0x80f996, wbuf, 2); + if (ret < 0) + goto err; + + ret = af9033_wr_reg(state, 0x80f994, onoff); + if (ret < 0) + goto err; + + ret = af9033_wr_reg(state, 0x80f995, index); + if (ret < 0) + goto err; + + return 0; + +err: + dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); + + return ret; +} + static struct dvb_frontend_ops af9033_ops; struct dvb_frontend *af9033_attach(const struct af9033_config *config, - struct i2c_adapter *i2c) + struct i2c_adapter *i2c, + struct af9033_ops *ops) { int ret; struct af9033_state *state; @@ -1067,6 +1119,11 @@ struct dvb_frontend *af9033_attach(const struct af9033_config *config, memcpy(&state->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops)); state->fe.demodulator_priv = state; + if (ops) { + ops->pid_filter = af9033_pid_filter; + ops->pid_filter_ctrl = af9033_pid_filter_ctrl; + } + return &state->fe; err: diff --git a/drivers/media/dvb-frontends/af9033.h b/drivers/media/dvb-frontends/af9033.h index c286e8f..539f4db 100644 --- a/drivers/media/dvb-frontends/af9033.h +++ b/drivers/media/dvb-frontends/af9033.h @@ -78,16 +78,42 @@ struct af9033_config { }; +struct af9033_ops { + int (*pid_filter_ctrl)(struct dvb_frontend *fe, int onoff); + int (*pid_filter)(struct dvb_frontend *fe, int index, u16 pid, + int onoff); +}; + + #if IS_ENABLED(CONFIG_DVB_AF9033) -extern struct dvb_frontend *af9033_attach(const struct af9033_config *config, - struct i2c_adapter *i2c); +extern +struct dvb_frontend *af9033_attach(const struct af9033_config *config, + struct i2c_adapter *i2c, + struct af9033_ops *ops); + #else -static inline struct dvb_frontend *af9033_attach( - const struct af9033_config *config, struct i2c_adapter *i2c) +static inline +struct dvb_frontend *af9033_attach(const struct af9033_config *config, + struct i2c_adapter *i2c, + struct af9033_ops *ops) { pr_warn("%s: driver disabled by Kconfig\n", __func__); return NULL; } + +static inline int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff) +{ + pr_warn("%s: driver disabled by Kconfig\n", __func__); + return -ENODEV; +} + +static inline int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid, + int onoff) +{ + pr_warn("%s: driver disabled by Kconfig\n", __func__); + return -ENODEV; +} + #endif #endif /* AF9033_H */ diff --git a/drivers/media/dvb-frontends/drx39xyj/Kconfig b/drivers/media/dvb-frontends/drx39xyj/Kconfig new file mode 100644 index 0000000..15628eb --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/Kconfig @@ -0,0 +1,7 @@ +config DVB_DRX39XYJ + tristate "Micronas DRX-J demodulator" + depends on DVB_CORE && I2C + default m if DVB_FE_CUSTOMISE + help + An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want + to support this frontend. diff --git a/drivers/media/dvb-frontends/drx39xyj/Makefile b/drivers/media/dvb-frontends/drx39xyj/Makefile new file mode 100644 index 0000000..672e077 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/Makefile @@ -0,0 +1,6 @@ +drx39xyj-objs := drxj.o + +obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj.o + +ccflags-y += -I$(srctree)/drivers/media/dvb-core/ +ccflags-y += -I$(srctree)/drivers/media/tuners/ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h new file mode 100644 index 0000000..5b5421f --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h @@ -0,0 +1,139 @@ +/* + I2C API, implementation depends on board specifics + + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + + This module encapsulates I2C access.In some applications several devices + share one I2C bus. If these devices have the same I2C address some kind + off "switch" must be implemented to ensure error free communication with + one device. In case such a "switch" is used, the device ID can be used + to implement control over this "switch". +*/ + +#ifndef __BSPI2C_H__ +#define __BSPI2C_H__ + +#include "bsp_types.h" + +/* + * This structure contains the I2C address, the device ID and a user_data pointer. + * The user_data pointer can be used for application specific purposes. + */ +struct i2c_device_addr { + u16 i2c_addr; /* The I2C address of the device. */ + u16 i2c_dev_id; /* The device identifier. */ + void *user_data; /* User data pointer */ +}; + + +/** +* \def IS_I2C_10BIT( addr ) +* \brief Determine if I2C address 'addr' is a 10 bits address or not. +* \param addr The I2C address. +* \return int. +* \retval 0 if address is not a 10 bits I2C address. +* \retval 1 if address is a 10 bits I2C address. +*/ +#define IS_I2C_10BIT(addr) \ + (((addr) & 0xF8) == 0xF0) + +/*------------------------------------------------------------------------------ +Exported FUNCTIONS +------------------------------------------------------------------------------*/ + +/** +* \fn drxbsp_i2c_init() +* \brief Initialize I2C communication module. +* \return drx_status_t Return status. +* \retval 0 Initialization successful. +* \retval -EIO Initialization failed. +*/ + drx_status_t drxbsp_i2c_init(void); + +/** +* \fn drxbsp_i2c_term() +* \brief Terminate I2C communication module. +* \return drx_status_t Return status. +* \retval 0 Termination successful. +* \retval -EIO Termination failed. +*/ + drx_status_t drxbsp_i2c_term(void); + +/** +* \fn drx_status_t drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, +* u16 w_count, +* u8 *wData, +* struct i2c_device_addr *r_dev_addr, +* u16 r_count, +* u8 *r_data) +* \brief Read and/or write count bytes from I2C bus, store them in data[]. +* \param w_dev_addr The device i2c address and the device ID to write to +* \param w_count The number of bytes to write +* \param wData The array to write the data to +* \param r_dev_addr The device i2c address and the device ID to read from +* \param r_count The number of bytes to read +* \param r_data The array to read the data from +* \return drx_status_t Return status. +* \retval 0 Succes. +* \retval -EIO Failure. +* \retval -EINVAL Parameter 'wcount' is not zero but parameter +* 'wdata' contains NULL. +* Idem for 'rcount' and 'rdata'. +* Both w_dev_addr and r_dev_addr are NULL. +* +* This function must implement an atomic write and/or read action on the I2C bus +* No other process may use the I2C bus when this function is executing. +* The critical section of this function runs from and including the I2C +* write, up to and including the I2C read action. +* +* The device ID can be useful if several devices share an I2C address. +* It can be used to control a "switch" on the I2C bus to the correct device. +*/ + drx_status_t drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, + u16 w_count, + u8 *w_data, + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data); + +/** +* \fn drxbsp_i2c_error_text() +* \brief Returns a human readable error. +* Counter part of numerical drx_i2c_error_g. +* +* \return char* Pointer to human readable error text. +*/ + char *drxbsp_i2c_error_text(void); + +/** +* \var drx_i2c_error_g; +* \brief I2C specific error codes, platform dependent. +*/ + extern int drx_i2c_error_g; + +#endif /* __BSPI2C_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h new file mode 100644 index 0000000..cfd0b96 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -0,0 +1,45 @@ +/* + * Driver for Micronas DRX39xx family (drx3933j) + * + * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= + */ + +#ifndef DRX39XXJ_H +#define DRX39XXJ_H + +#include <linux/dvb/frontend.h> +#include "dvb_frontend.h" +#include "drx_driver.h" + +struct drx39xxj_state { + struct i2c_adapter *i2c; + struct drx_demod_instance *demod; + struct dvb_frontend frontend; + unsigned int i2c_gate_open:1; + const struct firmware *fw; +}; + +#if IS_ENABLED(CONFIG_DVB_DRX39XYJ) +struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c); +#else +static inline struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) { + return NULL; +}; +#endif + +#endif /* DVB_DUMMY_FE_H */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h new file mode 100644 index 0000000..354ec07 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h @@ -0,0 +1,256 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/******************************************************************************* +* FILENAME: $Id: drx_dap_fasi.h,v 1.5 2009/07/07 14:21:40 justin Exp $ +* +* DESCRIPTION: +* Part of DRX driver. +* Data access protocol: Fast Access Sequential Interface (fasi) +* Fast access, because of short addressing format (16 instead of 32 bits addr) +* Sequential, because of I2C. +* +* USAGE: +* Include. +* +* NOTES: +* +* +*******************************************************************************/ + +/*-------- compilation control switches --------------------------------------*/ + +#ifndef __DRX_DAP_FASI_H__ +#define __DRX_DAP_FASI_H__ + +/*-------- Required includes -------------------------------------------------*/ + +#include "drx_driver.h" + +/*-------- Defines, configuring the API --------------------------------------*/ + +/******************************************** +* Allowed address formats +********************************************/ + +/* +* Comments about short/long addressing format: +* +* The DAP FASI offers long address format (4 bytes) and short address format +* (2 bytes). The DAP can operate in 3 modes: +* (1) only short +* (2) only long +* (3) both long and short but short preferred and long only when necesarry +* +* These modes must be selected compile time via compile switches. +* Compile switch settings for the diffrent modes: +* (1) DRXDAPFASI_LONG_ADDR_ALLOWED=0, DRXDAPFASI_SHORT_ADDR_ALLOWED=1 +* (2) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=0 +* (3) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=1 +* +* The default setting will be (3) both long and short. +* The default setting will need no compile switches. +* The default setting must be overridden if compile switches are already +* defined. +* +*/ + +/* set default */ +#if !defined(DRXDAPFASI_LONG_ADDR_ALLOWED) +#define DRXDAPFASI_LONG_ADDR_ALLOWED 1 +#endif + +/* set default */ +#if !defined(DRXDAPFASI_SHORT_ADDR_ALLOWED) +#define DRXDAPFASI_SHORT_ADDR_ALLOWED 1 +#endif + +/* check */ +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && \ + (DRXDAPFASI_SHORT_ADDR_ALLOWED == 0)) +#error At least one of short- or long-addressing format must be allowed. +*; /* illegal statement to force compiler error */ +#endif + +/******************************************** +* Single/master multi master setting +********************************************/ +/* +* Comments about SINGLE MASTER/MULTI MASTER modes: +* +* Consider the two sides:1) the master and 2)the slave. +* +* Master: +* Single/multimaster operation set via DRXDAP_SINGLE_MASTER compile switch +* + single master mode means no use of repeated starts +* + multi master mode means use of repeated starts +* Default is single master. +* Default can be overriden by setting the compile switch DRXDAP_SINGLE_MASTER. +* +* Slave: +* Single/multi master selected via the flags in the FASI protocol. +* + single master means remember memory address between i2c packets +* + multimaster means flush memory address between i2c packets +* Default is single master, DAP FASI changes multi-master setting silently +* into single master setting. This cannot be overrriden. +* +*/ +/* set default */ +#ifndef DRXDAP_SINGLE_MASTER +#define DRXDAP_SINGLE_MASTER 0 +#endif + +/******************************************** +* Chunk/mode checking +********************************************/ +/* +* Comments about DRXDAP_MAX_WCHUNKSIZE in single or multi master mode and +* in combination with short and long addressing format. All text below +* assumes long addressing format. The table also includes information +* for short ADDRessing format. +* +* In single master mode, data can be written by sending the register address +* first, then two or four bytes of data in the next packet. +* Because the device address plus a register address equals five bytes, +* the mimimum chunk size must be five. +* If ten-bit I2C device addresses are used, the minimum chunk size must be six, +* because the I2C device address will then occupy two bytes when writing. +* +* Data in single master mode is transferred as follows: +* <S> <devW> a0 a1 a2 a3 <P> +* <S> <devW> d0 d1 [d2 d3] <P> +* .. +* or +* .. +* <S> <devW> a0 a1 a2 a3 <P> +* <S> <devR> --- <P> +* +* In multi-master mode, the data must immediately follow the address (an I2C +* stop resets the internal address), and hence the minimum chunk size is +* 1 <I2C address> + 4 (register address) + 2 (data to send) = 7 bytes (8 if +* 10-bit I2C device addresses are used). +* +* The 7-bit or 10-bit i2c address parameters is a runtime parameter. +* The other parameters can be limited via compile time switches. +* +*------------------------------------------------------------------------------- +* +* Minimum chunk size table (in bytes): +* +* +----------------+----------------+ +* | 7b i2c addr | 10b i2c addr | +* +----------------+----------------+ +* | single | multi | single | multi | +* ------+--------+-------+--------+-------+ +* short | 3 | 5 | 4 | 6 | +* long | 5 | 7 | 6 | 8 | +* ------+--------+-------+--------+-------+ +* +*/ + +/* set default */ +#if !defined(DRXDAP_MAX_WCHUNKSIZE) +#define DRXDAP_MAX_WCHUNKSIZE 254 +#endif + +/* check */ +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) +#if DRXDAP_SINGLE_MASTER +#define DRXDAP_MAX_WCHUNKSIZE_MIN 3 +#else +#define DRXDAP_MAX_WCHUNKSIZE_MIN 5 +#endif +#else +#if DRXDAP_SINGLE_MASTER +#define DRXDAP_MAX_WCHUNKSIZE_MIN 5 +#else +#define DRXDAP_MAX_WCHUNKSIZE_MIN 7 +#endif +#endif + +#if DRXDAP_MAX_WCHUNKSIZE < DRXDAP_MAX_WCHUNKSIZE_MIN +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) +#if DRXDAP_SINGLE_MASTER +#error DRXDAP_MAX_WCHUNKSIZE must be at least 3 in single master mode +*; /* illegal statement to force compiler error */ +#else +#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in multi master mode +*; /* illegal statement to force compiler error */ +#endif +#else +#if DRXDAP_SINGLE_MASTER +#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in single master mode +*; /* illegal statement to force compiler error */ +#else +#error DRXDAP_MAX_WCHUNKSIZE must be at least 7 in multi master mode +*; /* illegal statement to force compiler error */ +#endif +#endif +#endif + +/* set default */ +#if !defined(DRXDAP_MAX_RCHUNKSIZE) +#define DRXDAP_MAX_RCHUNKSIZE 254 +#endif + +/* check */ +#if DRXDAP_MAX_RCHUNKSIZE < 2 +#error DRXDAP_MAX_RCHUNKSIZE must be at least 2 +*; /* illegal statement to force compiler error */ +#endif + +/* check */ +#if DRXDAP_MAX_RCHUNKSIZE & 1 +#error DRXDAP_MAX_RCHUNKSIZE must be even +*; /* illegal statement to force compiler error */ +#endif + +/*-------- Public API functions ----------------------------------------------*/ + +extern struct drx_access_func drx_dap_fasi_funct_g; + +#define DRXDAP_FASI_RMW 0x10000000 +#define DRXDAP_FASI_BROADCAST 0x20000000 +#define DRXDAP_FASI_CLEARCRC 0x80000000 +#define DRXDAP_FASI_SINGLE_MASTER 0xC0000000 +#define DRXDAP_FASI_MULTI_MASTER 0x40000000 +#define DRXDAP_FASI_SMM_SWITCH 0x40000000 /* single/multi master switch */ +#define DRXDAP_FASI_MODEFLAGS 0xC0000000 +#define DRXDAP_FASI_FLAGS 0xF0000000 + +#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr)>>22)&0x3F) +#define DRXDAP_FASI_ADDR2BANK(addr) (((addr)>>16)&0x3F) +#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr)&0x7FFF) + +#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) +#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) +#define DRXDAP_FASI_OFFSET_TOO_LARGE(addr) (((addr) & 0x00008000) != 0) + +#endif /* __DRX_DAP_FASI_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h new file mode 100644 index 0000000..9076bf2 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -0,0 +1,2343 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef __DRXDRIVER_H__ +#define __DRXDRIVER_H__ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/firmware.h> +#include <linux/i2c.h> + +/* + * This structure contains the I2C address, the device ID and a user_data pointer. + * The user_data pointer can be used for application specific purposes. + */ +struct i2c_device_addr { + u16 i2c_addr; /* The I2C address of the device. */ + u16 i2c_dev_id; /* The device identifier. */ + void *user_data; /* User data pointer */ +}; + +/** +* \def IS_I2C_10BIT( addr ) +* \brief Determine if I2C address 'addr' is a 10 bits address or not. +* \param addr The I2C address. +* \return int. +* \retval 0 if address is not a 10 bits I2C address. +* \retval 1 if address is a 10 bits I2C address. +*/ +#define IS_I2C_10BIT(addr) \ + (((addr) & 0xF8) == 0xF0) + +/*------------------------------------------------------------------------------ +Exported FUNCTIONS +------------------------------------------------------------------------------*/ + +/** +* \fn drxbsp_i2c_init() +* \brief Initialize I2C communication module. +* \return int Return status. +* \retval 0 Initialization successful. +* \retval -EIO Initialization failed. +*/ +int drxbsp_i2c_init(void); + +/** +* \fn drxbsp_i2c_term() +* \brief Terminate I2C communication module. +* \return int Return status. +* \retval 0 Termination successful. +* \retval -EIO Termination failed. +*/ +int drxbsp_i2c_term(void); + +/** +* \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, +* u16 w_count, +* u8 * wData, +* struct i2c_device_addr *r_dev_addr, +* u16 r_count, +* u8 * r_data) +* \brief Read and/or write count bytes from I2C bus, store them in data[]. +* \param w_dev_addr The device i2c address and the device ID to write to +* \param w_count The number of bytes to write +* \param wData The array to write the data to +* \param r_dev_addr The device i2c address and the device ID to read from +* \param r_count The number of bytes to read +* \param r_data The array to read the data from +* \return int Return status. +* \retval 0 Succes. +* \retval -EIO Failure. +* \retval -EINVAL Parameter 'wcount' is not zero but parameter +* 'wdata' contains NULL. +* Idem for 'rcount' and 'rdata'. +* Both w_dev_addr and r_dev_addr are NULL. +* +* This function must implement an atomic write and/or read action on the I2C bus +* No other process may use the I2C bus when this function is executing. +* The critical section of this function runs from and including the I2C +* write, up to and including the I2C read action. +* +* The device ID can be useful if several devices share an I2C address. +* It can be used to control a "switch" on the I2C bus to the correct device. +*/ +int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, + u16 w_count, + u8 *wData, + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data); + +/** +* \fn drxbsp_i2c_error_text() +* \brief Returns a human readable error. +* Counter part of numerical drx_i2c_error_g. +* +* \return char* Pointer to human readable error text. +*/ +char *drxbsp_i2c_error_text(void); + +/** +* \var drx_i2c_error_g; +* \brief I2C specific error codes, platform dependent. +*/ +extern int drx_i2c_error_g; + +#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */ + +#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */ +#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */ +#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */ +#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */ +#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */ +#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */ +#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ + +#define TUNER_MODE_SUB_MAX 8 +#define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ + TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \ + TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ + TUNER_MODE_SUB6 | TUNER_MODE_SUB7) + + +enum tuner_lock_status { + TUNER_LOCKED, + TUNER_NOT_LOCKED +}; + +struct tuner_common { + char *name; /* Tuner brand & type name */ + s32 min_freq_rf; /* Lowest RF input frequency, in kHz */ + s32 max_freq_rf; /* Highest RF input frequency, in kHz */ + + u8 sub_mode; /* Index to sub-mode in use */ + char ***sub_mode_descriptions; /* Pointer to description of sub-modes */ + u8 sub_modes; /* Number of available sub-modes */ + + /* The following fields will be either 0, NULL or false and do not need + initialisation */ + void *self_check; /* gives proof of initialization */ + bool programmed; /* only valid if self_check is OK */ + s32 r_ffrequency; /* only valid if programmed */ + s32 i_ffrequency; /* only valid if programmed */ + + void *my_user_data; /* pointer to associated demod instance */ + u16 my_capabilities; /* value for storing application flags */ +}; + +struct tuner_instance; + +typedef int(*tuner_open_func_t) (struct tuner_instance *tuner); +typedef int(*tuner_close_func_t) (struct tuner_instance *tuner); + +typedef int(*tuner_set_frequency_func_t) (struct tuner_instance *tuner, + u32 mode, + s32 + frequency); + +typedef int(*tuner_get_frequency_func_t) (struct tuner_instance *tuner, + u32 mode, + s32 * + r_ffrequency, + s32 * + i_ffrequency); + +typedef int(*tuner_lock_status_func_t) (struct tuner_instance *tuner, + enum tuner_lock_status * + lock_stat); + +typedef int(*tune_ri2c_write_read_func_t) (struct tuner_instance *tuner, + struct i2c_device_addr * + w_dev_addr, u16 w_count, + u8 *wData, + struct i2c_device_addr * + r_dev_addr, u16 r_count, + u8 *r_data); + +struct tuner_ops { + tuner_open_func_t open_func; + tuner_close_func_t close_func; + tuner_set_frequency_func_t set_frequency_func; + tuner_get_frequency_func_t get_frequency_func; + tuner_lock_status_func_t lock_status_func; + tune_ri2c_write_read_func_t i2c_write_read_func; + +}; + +struct tuner_instance { + struct i2c_device_addr my_i2c_dev_addr; + struct tuner_common *my_common_attr; + void *my_ext_attr; + struct tuner_ops *my_funct; +}; + +int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, + u32 mode, + s32 frequency); + +int drxbsp_tuner_get_frequency(struct tuner_instance *tuner, + u32 mode, + s32 *r_ffrequency, + s32 *i_ffrequency); + +int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, + struct i2c_device_addr *w_dev_addr, + u16 w_count, + u8 *wData, + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data); + +/************** +* +* This section configures the DRX Data Access Protocols (DAPs). +* +**************/ + +/** +* \def DRXDAP_SINGLE_MASTER +* \brief Enable I2C single or I2C multimaster mode on host. +* +* Set to 1 to enable single master mode +* Set to 0 to enable multi master mode +* +* The actual DAP implementation may be restricted to only one of the modes. +* A compiler warning or error will be generated if the DAP implementation +* overides or cannot handle the mode defined below. +* +*/ +#ifndef DRXDAP_SINGLE_MASTER +#define DRXDAP_SINGLE_MASTER 1 +#endif + +/** +* \def DRXDAP_MAX_WCHUNKSIZE +* \brief Defines maximum chunksize of an i2c write action by host. +* +* This indicates the maximum size of data the I2C device driver is able to +* write at a time. This includes I2C device address and register addressing. +* +* This maximum size may be restricted by the actual DAP implementation. +* A compiler warning or error will be generated if the DAP implementation +* overides or cannot handle the chunksize defined below. +* +* Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data +* buffer. Do not undefine or choose too large, unless your system is able to +* handle a stack buffer of that size. +* +*/ +#ifndef DRXDAP_MAX_WCHUNKSIZE +#define DRXDAP_MAX_WCHUNKSIZE 60 +#endif + +/** +* \def DRXDAP_MAX_RCHUNKSIZE +* \brief Defines maximum chunksize of an i2c read action by host. +* +* This indicates the maximum size of data the I2C device driver is able to read +* at a time. Minimum value is 2. Also, the read chunk size must be even. +* +* This maximum size may be restricted by the actual DAP implementation. +* A compiler warning or error will be generated if the DAP implementation +* overides or cannot handle the chunksize defined below. +* +*/ +#ifndef DRXDAP_MAX_RCHUNKSIZE +#define DRXDAP_MAX_RCHUNKSIZE 60 +#endif + +/************** +* +* This section describes drxdriver defines. +* +**************/ + +/** +* \def DRX_UNKNOWN +* \brief Generic UNKNOWN value for DRX enumerated types. +* +* Used to indicate that the parameter value is unknown or not yet initalized. +*/ +#ifndef DRX_UNKNOWN +#define DRX_UNKNOWN (254) +#endif + +/** +* \def DRX_AUTO +* \brief Generic AUTO value for DRX enumerated types. +* +* Used to instruct the driver to automatically determine the value of the +* parameter. +*/ +#ifndef DRX_AUTO +#define DRX_AUTO (255) +#endif + +/************** +* +* This section describes flag definitions for the device capbilities. +* +**************/ + +/** +* \brief LNA capability flag +* +* Device has a Low Noise Amplifier +* +*/ +#define DRX_CAPABILITY_HAS_LNA (1UL << 0) +/** +* \brief OOB-RX capability flag +* +* Device has OOB-RX +* +*/ +#define DRX_CAPABILITY_HAS_OOBRX (1UL << 1) +/** +* \brief ATV capability flag +* +* Device has ATV +* +*/ +#define DRX_CAPABILITY_HAS_ATV (1UL << 2) +/** +* \brief DVB-T capability flag +* +* Device has DVB-T +* +*/ +#define DRX_CAPABILITY_HAS_DVBT (1UL << 3) +/** +* \brief ITU-B capability flag +* +* Device has ITU-B +* +*/ +#define DRX_CAPABILITY_HAS_ITUB (1UL << 4) +/** +* \brief Audio capability flag +* +* Device has Audio +* +*/ +#define DRX_CAPABILITY_HAS_AUD (1UL << 5) +/** +* \brief SAW switch capability flag +* +* Device has SAW switch +* +*/ +#define DRX_CAPABILITY_HAS_SAWSW (1UL << 6) +/** +* \brief GPIO1 capability flag +* +* Device has GPIO1 +* +*/ +#define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7) +/** +* \brief GPIO2 capability flag +* +* Device has GPIO2 +* +*/ +#define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8) +/** +* \brief IRQN capability flag +* +* Device has IRQN +* +*/ +#define DRX_CAPABILITY_HAS_IRQN (1UL << 9) +/** +* \brief 8VSB capability flag +* +* Device has 8VSB +* +*/ +#define DRX_CAPABILITY_HAS_8VSB (1UL << 10) +/** +* \brief SMA-TX capability flag +* +* Device has SMATX +* +*/ +#define DRX_CAPABILITY_HAS_SMATX (1UL << 11) +/** +* \brief SMA-RX capability flag +* +* Device has SMARX +* +*/ +#define DRX_CAPABILITY_HAS_SMARX (1UL << 12) +/** +* \brief ITU-A/C capability flag +* +* Device has ITU-A/C +* +*/ +#define DRX_CAPABILITY_HAS_ITUAC (1UL << 13) + +/*------------------------------------------------------------------------- +MACROS +-------------------------------------------------------------------------*/ +/* Macros to stringify the version number */ +#define DRX_VERSIONSTRING(MAJOR, MINOR, PATCH) \ + DRX_VERSIONSTRING_HELP(MAJOR)"." \ + DRX_VERSIONSTRING_HELP(MINOR)"." \ + DRX_VERSIONSTRING_HELP(PATCH) +#define DRX_VERSIONSTRING_HELP(NUM) #NUM + +/** +* \brief Macro to create byte array elements from 16 bit integers. +* This macro is used to create byte arrays for block writes. +* Block writes speed up I2C traffic between host and demod. +* The macro takes care of the required byte order in a 16 bits word. +* x->lowbyte(x), highbyte(x) +*/ +#define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ + ((u8)((((u16)x)>>8)&0xFF)) + +/** +* \brief Macro to sign extend signed 9 bit value to signed 16 bit value +*/ +#define DRX_S9TOS16(x) ((((u16)x)&0x100) ? ((s16)((u16)(x)|0xFF00)) : (x)) + +/** +* \brief Macro to sign extend signed 9 bit value to signed 16 bit value +*/ +#define DRX_S24TODRXFREQ(x) ((((u32) x) & 0x00800000UL) ? \ + ((s32) \ + (((u32) x) | 0xFF000000)) : \ + ((s32) x)) + +/** +* \brief Macro to convert 16 bit register value to a s32 +*/ +#define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \ + ((s32) \ + (((u32) x) | 0xFFFF0000)) : \ + ((s32) x)) + +/*------------------------------------------------------------------------- +ENUM +-------------------------------------------------------------------------*/ + +/** +* \enum enum drx_standard +* \brief Modulation standards. +*/ +enum drx_standard { + DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */ + DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */ + DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */ + DRX_STANDARD_PAL_SECAM_BG, + /**< Terrestrial analog PAL/SECAM B/G */ + DRX_STANDARD_PAL_SECAM_DK, + /**< Terrestrial analog PAL/SECAM D/K */ + DRX_STANDARD_PAL_SECAM_I, + /**< Terrestrial analog PAL/SECAM I */ + DRX_STANDARD_PAL_SECAM_L, + /**< Terrestrial analog PAL/SECAM L + with negative modulation */ + DRX_STANDARD_PAL_SECAM_LP, + /**< Terrestrial analog PAL/SECAM L + with positive modulation */ + DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */ + DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */ + DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */ + DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */ + DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */ + DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/ + DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, + /**< Standard unknown. */ + DRX_STANDARD_AUTO = DRX_AUTO + /**< Autodetect standard. */ +}; + +/** +* \enum enum drx_standard +* \brief Modulation sub-standards. +*/ +enum drx_substandard { + DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */ + DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, + DRX_SUBSTANDARD_ATV_DK_POLAND, + DRX_SUBSTANDARD_ATV_DK_CHINA, + DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, + /**< Sub-standard unknown. */ + DRX_SUBSTANDARD_AUTO = DRX_AUTO + /**< Auto (default) sub-standard */ +}; + +/** +* \enum enum drx_bandwidth +* \brief Channel bandwidth or channel spacing. +*/ +enum drx_bandwidth { + DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */ + DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */ + DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */ + DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, + /**< Bandwidth unknown. */ + DRX_BANDWIDTH_AUTO = DRX_AUTO + /**< Auto Set Bandwidth */ +}; + +/** +* \enum enum drx_mirror +* \brief Indicate if channel spectrum is mirrored or not. +*/ +enum drx_mirror { + DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */ + DRX_MIRROR_YES, /**< Spectrum is mirrored. */ + DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, + /**< Unknown if spectrum is mirrored. */ + DRX_MIRROR_AUTO = DRX_AUTO + /**< Autodetect if spectrum is mirrored. */ +}; + +/** +* \enum enum drx_modulation +* \brief Constellation type of the channel. +*/ +enum drx_modulation { + DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */ + DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */ + DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */ + DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */ + DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */ + DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */ + DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */ + DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */ + DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */ + DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */ + DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */ + DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, + /**< Constellation unknown. */ + DRX_CONSTELLATION_AUTO = DRX_AUTO + /**< Autodetect constellation. */ +}; + +/** +* \enum enum drx_hierarchy +* \brief Hierarchy of the channel. +*/ +enum drx_hierarchy { + DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */ + DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */ + DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */ + DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */ + DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, + /**< Hierarchy unknown. */ + DRX_HIERARCHY_AUTO = DRX_AUTO + /**< Autodetect hierarchy. */ +}; + +/** +* \enum enum drx_priority +* \brief Channel priority in case of hierarchical transmission. +*/ +enum drx_priority { + DRX_PRIORITY_LOW = 0, /**< Low priority channel. */ + DRX_PRIORITY_HIGH, /**< High priority channel. */ + DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN + /**< Priority unknown. */ +}; + +/** +* \enum enum drx_coderate +* \brief Channel priority in case of hierarchical transmission. +*/ +enum drx_coderate { + DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */ + DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */ + DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */ + DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */ + DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */ + DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, + /**< Code rate unknown. */ + DRX_CODERATE_AUTO = DRX_AUTO + /**< Autodetect code rate. */ +}; + +/** +* \enum enum drx_guard +* \brief Guard interval of a channel. +*/ +enum drx_guard { + DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */ + DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */ + DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */ + DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */ + DRX_GUARD_UNKNOWN = DRX_UNKNOWN, + /**< Guard interval unknown. */ + DRX_GUARD_AUTO = DRX_AUTO + /**< Autodetect guard interval. */ +}; + +/** +* \enum enum drx_fft_mode +* \brief FFT mode. +*/ +enum drx_fft_mode { + DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */ + DRX_FFTMODE_4K, /**< 4K FFT mode. */ + DRX_FFTMODE_8K, /**< 8K FFT mode. */ + DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, + /**< FFT mode unknown. */ + DRX_FFTMODE_AUTO = DRX_AUTO + /**< Autodetect FFT mode. */ +}; + +/** +* \enum enum drx_classification +* \brief Channel classification. +*/ +enum drx_classification { + DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */ + DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */ + DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */ + DRX_CLASSIFICATION_STATIC, /**< Static echo. */ + DRX_CLASSIFICATION_MOVING, /**< Moving echo. */ + DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */ + DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, + /**< Unknown classification */ + DRX_CLASSIFICATION_AUTO = DRX_AUTO + /**< Autodetect classification. */ +}; + +/** +* /enum enum drx_interleave_mode +* /brief Interleave modes +*/ +enum drx_interleave_mode { + DRX_INTERLEAVEMODE_I128_J1 = 0, + DRX_INTERLEAVEMODE_I128_J1_V2, + DRX_INTERLEAVEMODE_I128_J2, + DRX_INTERLEAVEMODE_I64_J2, + DRX_INTERLEAVEMODE_I128_J3, + DRX_INTERLEAVEMODE_I32_J4, + DRX_INTERLEAVEMODE_I128_J4, + DRX_INTERLEAVEMODE_I16_J8, + DRX_INTERLEAVEMODE_I128_J5, + DRX_INTERLEAVEMODE_I8_J16, + DRX_INTERLEAVEMODE_I128_J6, + DRX_INTERLEAVEMODE_RESERVED_11, + DRX_INTERLEAVEMODE_I128_J7, + DRX_INTERLEAVEMODE_RESERVED_13, + DRX_INTERLEAVEMODE_I128_J8, + DRX_INTERLEAVEMODE_RESERVED_15, + DRX_INTERLEAVEMODE_I12_J17, + DRX_INTERLEAVEMODE_I5_J4, + DRX_INTERLEAVEMODE_B52_M240, + DRX_INTERLEAVEMODE_B52_M720, + DRX_INTERLEAVEMODE_B52_M48, + DRX_INTERLEAVEMODE_B52_M0, + DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, + /**< Unknown interleave mode */ + DRX_INTERLEAVEMODE_AUTO = DRX_AUTO + /**< Autodetect interleave mode */ +}; + +/** +* \enum enum drx_carrier_mode +* \brief Channel Carrier Mode. +*/ +enum drx_carrier_mode { + DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */ + DRX_CARRIER_SINGLE, /**< Single carrier mode */ + DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, + /**< Carrier mode unknown. */ + DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */ +}; + +/** +* \enum enum drx_frame_mode +* \brief Channel Frame Mode. +*/ +enum drx_frame_mode { + DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */ + DRX_FRAMEMODE_595, /**< 595 */ + DRX_FRAMEMODE_945, /**< 945 with variable PN */ + DRX_FRAMEMODE_420_FIXED_PN, + /**< 420 with fixed PN */ + DRX_FRAMEMODE_945_FIXED_PN, + /**< 945 with fixed PN */ + DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, + /**< Frame mode unknown. */ + DRX_FRAMEMODE_AUTO = DRX_AUTO + /**< Autodetect frame mode */ +}; + +/** +* \enum enum drx_tps_frame +* \brief Frame number in current super-frame. +*/ +enum drx_tps_frame { + DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */ + DRX_TPS_FRAME2, /**< TPS frame 2. */ + DRX_TPS_FRAME3, /**< TPS frame 3. */ + DRX_TPS_FRAME4, /**< TPS frame 4. */ + DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN + /**< TPS frame unknown. */ +}; + +/** +* \enum enum drx_ldpc +* \brief TPS LDPC . +*/ +enum drx_ldpc { + DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */ + DRX_LDPC_0_6, /**< LDPC 0.6 */ + DRX_LDPC_0_8, /**< LDPC 0.8 */ + DRX_LDPC_UNKNOWN = DRX_UNKNOWN, + /**< LDPC unknown. */ + DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */ +}; + +/** +* \enum enum drx_pilot_mode +* \brief Pilot modes in DTMB. +*/ +enum drx_pilot_mode { + DRX_PILOT_ON = 0, /**< Pilot On */ + DRX_PILOT_OFF, /**< Pilot Off */ + DRX_PILOT_UNKNOWN = DRX_UNKNOWN, + /**< Pilot unknown. */ + DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */ +}; + +/** + * enum drxu_code_action - indicate if firmware has to be uploaded or verified. + * @UCODE_UPLOAD: Upload the microcode image to device + * @UCODE_VERIFY: Compare microcode image with code on device + */ +enum drxu_code_action { + UCODE_UPLOAD, + UCODE_VERIFY +}; + +/** +* \enum enum drx_lock_status * \brief Used to reflect current lock status of demodulator. +* +* The generic lock states have device dependent semantics. + + DRX_NEVER_LOCK = 0, + **< Device will never lock on this signal * + DRX_NOT_LOCKED, + **< Device has no lock at all * + DRX_LOCK_STATE_1, + **< Generic lock state * + DRX_LOCK_STATE_2, + **< Generic lock state * + DRX_LOCK_STATE_3, + **< Generic lock state * + DRX_LOCK_STATE_4, + **< Generic lock state * + DRX_LOCK_STATE_5, + **< Generic lock state * + DRX_LOCK_STATE_6, + **< Generic lock state * + DRX_LOCK_STATE_7, + **< Generic lock state * + DRX_LOCK_STATE_8, + **< Generic lock state * + DRX_LOCK_STATE_9, + **< Generic lock state * + DRX_LOCKED **< Device is in lock * +*/ + +enum drx_lock_status { + DRX_NEVER_LOCK = 0, + DRX_NOT_LOCKED, + DRX_LOCK_STATE_1, + DRX_LOCK_STATE_2, + DRX_LOCK_STATE_3, + DRX_LOCK_STATE_4, + DRX_LOCK_STATE_5, + DRX_LOCK_STATE_6, + DRX_LOCK_STATE_7, + DRX_LOCK_STATE_8, + DRX_LOCK_STATE_9, + DRX_LOCKED +}; + +/** +* \enum enum drx_uio* \brief Used to address a User IO (UIO). +*/ +enum drx_uio { + DRX_UIO1, + DRX_UIO2, + DRX_UIO3, + DRX_UIO4, + DRX_UIO5, + DRX_UIO6, + DRX_UIO7, + DRX_UIO8, + DRX_UIO9, + DRX_UIO10, + DRX_UIO11, + DRX_UIO12, + DRX_UIO13, + DRX_UIO14, + DRX_UIO15, + DRX_UIO16, + DRX_UIO17, + DRX_UIO18, + DRX_UIO19, + DRX_UIO20, + DRX_UIO21, + DRX_UIO22, + DRX_UIO23, + DRX_UIO24, + DRX_UIO25, + DRX_UIO26, + DRX_UIO27, + DRX_UIO28, + DRX_UIO29, + DRX_UIO30, + DRX_UIO31, + DRX_UIO32, + DRX_UIO_MAX = DRX_UIO32 +}; + +/** +* \enum enum drxuio_mode * \brief Used to configure the modus oprandi of a UIO. +* +* DRX_UIO_MODE_FIRMWARE is an old uio mode. +* It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9. +* To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to +* DRX_UIO_MODE_FIRMWARE0. +*/ +enum drxuio_mode { + DRX_UIO_MODE_DISABLE = 0x01, + /**< not used, pin is configured as input */ + DRX_UIO_MODE_READWRITE = 0x02, + /**< used for read/write by application */ + DRX_UIO_MODE_FIRMWARE = 0x04, + /**< controlled by firmware, function 0 */ + DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE, + /**< same as above */ + DRX_UIO_MODE_FIRMWARE1 = 0x08, + /**< controlled by firmware, function 1 */ + DRX_UIO_MODE_FIRMWARE2 = 0x10, + /**< controlled by firmware, function 2 */ + DRX_UIO_MODE_FIRMWARE3 = 0x20, + /**< controlled by firmware, function 3 */ + DRX_UIO_MODE_FIRMWARE4 = 0x40, + /**< controlled by firmware, function 4 */ + DRX_UIO_MODE_FIRMWARE5 = 0x80 + /**< controlled by firmware, function 5 */ +}; + +/** +* \enum enum drxoob_downstream_standard * \brief Used to select OOB standard. +* +* Based on ANSI 55-1 and 55-2 +*/ +enum drxoob_downstream_standard { + DRX_OOB_MODE_A = 0, + /**< ANSI 55-1 */ + DRX_OOB_MODE_B_GRADE_A, + /**< ANSI 55-2 A */ + DRX_OOB_MODE_B_GRADE_B + /**< ANSI 55-2 B */ +}; + +/*------------------------------------------------------------------------- +STRUCTS +-------------------------------------------------------------------------*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL CFG related data structures ========================================*/ +/*============================================================================*/ +/*============================================================================*/ + +#ifndef DRX_CFG_BASE +#define DRX_CFG_BASE 0 +#endif + +#define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */ +#define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) /* Packet Error */ +#define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) /* Symbol Clk Offset */ +#define DRX_CFG_SMA (DRX_CFG_BASE + 3) /* Smart Antenna */ +#define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) /* Pin safe mode */ +#define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) /* substandard */ +#define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) /* volume */ +#define DRX_CFG_AUD_RDS (DRX_CFG_BASE + 7) /* rds */ +#define DRX_CFG_AUD_AUTOSOUND (DRX_CFG_BASE + 8) /* ASS & ASC */ +#define DRX_CFG_AUD_ASS_THRES (DRX_CFG_BASE + 9) /* ASS Thresholds */ +#define DRX_CFG_AUD_DEVIATION (DRX_CFG_BASE + 10) /* Deviation */ +#define DRX_CFG_AUD_PRESCALE (DRX_CFG_BASE + 11) /* Prescale */ +#define DRX_CFG_AUD_MIXER (DRX_CFG_BASE + 12) /* Mixer */ +#define DRX_CFG_AUD_AVSYNC (DRX_CFG_BASE + 13) /* AVSync */ +#define DRX_CFG_AUD_CARRIER (DRX_CFG_BASE + 14) /* Audio carriers */ +#define DRX_CFG_I2S_OUTPUT (DRX_CFG_BASE + 15) /* I2S output */ +#define DRX_CFG_ATV_STANDARD (DRX_CFG_BASE + 16) /* ATV standard */ +#define DRX_CFG_SQI_SPEED (DRX_CFG_BASE + 17) /* SQI speed */ +#define DRX_CTRL_CFG_MAX (DRX_CFG_BASE + 18) /* never to be used */ + +#define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL related data structures ============================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/** + * struct drxu_code_info Parameters for microcode upload and verfiy. + * + * @mc_file: microcode file name + * + * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE + */ +struct drxu_code_info { + char *mc_file; +}; + +/** +* \struct drx_mc_version_rec_t +* \brief Microcode version record +* Version numbers are stored in BCD format, as usual: +* o major number = bits 31-20 (first three nibbles of MSW) +* o minor number = bits 19-16 (fourth nibble of MSW) +* o patch number = bits 15-0 (remaining nibbles in LSW) +* +* The device type indicates for which the device is meant. It is based on the +* JTAG ID, using everything except the bond ID and the metal fix. +* +* Special values: +* - mc_dev_type == 0 => any device allowed +* - mc_base_version == 0.0.0 => full microcode (mc_version is the version) +* - mc_base_version != 0.0.0 => patch microcode, the base microcode version +* (mc_version is the version) +*/ +#define AUX_VER_RECORD 0x8000 + +struct drx_mc_version_rec { + u16 aux_type; /* type of aux data - 0x8000 for version record */ + u32 mc_dev_type; /* device type, based on JTAG ID */ + u32 mc_version; /* version of microcode */ + u32 mc_base_version; /* in case of patch: the original microcode version */ +}; + +/*========================================*/ + +/** +* \struct drx_filter_info_t +* \brief Parameters for loading filter coefficients +* +* Used by DRX_CTRL_LOAD_FILTER +*/ +struct drx_filter_info { + u8 *data_re; + /**< pointer to coefficients for RE */ + u8 *data_im; + /**< pointer to coefficients for IM */ + u16 size_re; + /**< size of coefficients for RE */ + u16 size_im; + /**< size of coefficients for IM */ +}; + +/*========================================*/ + +/** +* \struct struct drx_channel * \brief The set of parameters describing a single channel. +* +* Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL. +* Only certain fields need to be used for a specfic standard. +* +*/ +struct drx_channel { + s32 frequency; + /**< frequency in kHz */ + enum drx_bandwidth bandwidth; + /**< bandwidth */ + enum drx_mirror mirror; /**< mirrored or not on RF */ + enum drx_modulation constellation; + /**< constellation */ + enum drx_hierarchy hierarchy; + /**< hierarchy */ + enum drx_priority priority; /**< priority */ + enum drx_coderate coderate; /**< coderate */ + enum drx_guard guard; /**< guard interval */ + enum drx_fft_mode fftmode; /**< fftmode */ + enum drx_classification classification; + /**< classification */ + u32 symbolrate; + /**< symbolrate in symbols/sec */ + enum drx_interleave_mode interleavemode; + /**< interleaveMode QAM */ + enum drx_ldpc ldpc; /**< ldpc */ + enum drx_carrier_mode carrier; /**< carrier */ + enum drx_frame_mode framemode; + /**< frame mode */ + enum drx_pilot_mode pilot; /**< pilot mode */ +}; + +/*========================================*/ + +enum drx_cfg_sqi_speed { + DRX_SQI_SPEED_FAST = 0, + DRX_SQI_SPEED_MEDIUM, + DRX_SQI_SPEED_SLOW, + DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN +}; + +/*========================================*/ + +/** +* \struct struct drx_complex * A complex number. +* +* Used by DRX_CTRL_CONSTEL. +*/ +struct drx_complex { + s16 im; + /**< Imaginary part. */ + s16 re; + /**< Real part. */ +}; + +/*========================================*/ + +/** +* \struct struct drx_frequency_plan * Array element of a frequency plan. +* +* Used by DRX_CTRL_SCAN_INIT. +*/ +struct drx_frequency_plan { + s32 first; + /**< First centre frequency in this band */ + s32 last; + /**< Last centre frequency in this band */ + s32 step; + /**< Stepping frequency in this band */ + enum drx_bandwidth bandwidth; + /**< Bandwidth within this frequency band */ + u16 ch_number; + /**< First channel number in this band, or first + index in ch_names */ + char **ch_names; + /**< Optional list of channel names in this + band */ +}; + +/*========================================*/ + +/** +* \struct struct drx_scan_param * Parameters for channel scan. +* +* Used by DRX_CTRL_SCAN_INIT. +*/ +struct drx_scan_param { + struct drx_frequency_plan *frequency_plan; + /**< Frequency plan (array)*/ + u16 frequency_plan_size; /**< Number of bands */ + u32 num_tries; /**< Max channels tried */ + s32 skip; /**< Minimum frequency step to take + after a channel is found */ + void *ext_params; /**< Standard specific params */ +}; + +/*========================================*/ + +/** +* \brief Scan commands. +* Used by scanning algorithms. +*/ +enum drx_scan_command { + DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */ + DRX_SCAN_COMMAND_NEXT, /**< Next scan */ + DRX_SCAN_COMMAND_STOP /**< Stop scanning */ +}; + +/*========================================*/ + +/** +* \brief Inner scan function prototype. +*/ +typedef int(*drx_scan_func_t) (void *scan_context, + enum drx_scan_command scan_command, + struct drx_channel *scan_channel, + bool *get_next_channel); + +/*========================================*/ + +/** +* \struct struct drxtps_info * TPS information, DVB-T specific. +* +* Used by DRX_CTRL_TPS_INFO. +*/ + struct drxtps_info { + enum drx_fft_mode fftmode; /**< Fft mode */ + enum drx_guard guard; /**< Guard interval */ + enum drx_modulation constellation; + /**< Constellation */ + enum drx_hierarchy hierarchy; + /**< Hierarchy */ + enum drx_coderate high_coderate; + /**< High code rate */ + enum drx_coderate low_coderate; + /**< Low cod rate */ + enum drx_tps_frame frame; /**< Tps frame */ + u8 length; /**< Length */ + u16 cell_id; /**< Cell id */ + }; + +/*========================================*/ + +/** +* \brief Power mode of device. +* +* Used by DRX_CTRL_SET_POWER_MODE. +*/ + enum drx_power_mode { + DRX_POWER_UP = 0, + /**< Generic , Power Up Mode */ + DRX_POWER_MODE_1, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_2, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_3, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_4, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_5, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_6, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_7, + /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_8, + /**< Device specific , Power Up Mode */ + + DRX_POWER_MODE_9, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_10, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_11, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_12, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_13, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_14, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_15, + /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_16, + /**< Device specific , Power Down Mode */ + DRX_POWER_DOWN = 255 + /**< Generic , Power Down Mode */ + }; + +/*========================================*/ + +/** +* \enum enum drx_module * \brief Software module identification. +* +* Used by DRX_CTRL_VERSION. +*/ + enum drx_module { + DRX_MODULE_DEVICE, + DRX_MODULE_MICROCODE, + DRX_MODULE_DRIVERCORE, + DRX_MODULE_DEVICEDRIVER, + DRX_MODULE_DAP, + DRX_MODULE_BSP_I2C, + DRX_MODULE_BSP_TUNER, + DRX_MODULE_BSP_HOST, + DRX_MODULE_UNKNOWN + }; + +/** +* \enum struct drx_version * \brief Version information of one software module. +* +* Used by DRX_CTRL_VERSION. +*/ + struct drx_version { + enum drx_module module_type; + /**< Type identifier of the module */ + char *module_name; + /**< Name or description of module */ + u16 v_major; /**< Major version number */ + u16 v_minor; /**< Minor version number */ + u16 v_patch; /**< Patch version number */ + char *v_string; /**< Version as text string */ + }; + +/** +* \enum struct drx_version_list * \brief List element of NULL terminated, linked list for version information. +* +* Used by DRX_CTRL_VERSION. +*/ +struct drx_version_list { + struct drx_version *version;/**< Version information */ + struct drx_version_list *next; + /**< Next list element */ +}; + +/*========================================*/ + +/** +* \brief Parameters needed to confiugure a UIO. +* +* Used by DRX_CTRL_UIO_CFG. +*/ + struct drxuio_cfg { + enum drx_uio uio; + /**< UIO identifier */ + enum drxuio_mode mode; + /**< UIO operational mode */ + }; + +/*========================================*/ + +/** +* \brief Parameters needed to read from or write to a UIO. +* +* Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE. +*/ + struct drxuio_data { + enum drx_uio uio; + /**< UIO identifier */ + bool value; + /**< UIO value (true=1, false=0) */ + }; + +/*========================================*/ + +/** +* \brief Parameters needed to configure OOB. +* +* Used by DRX_CTRL_SET_OOB. +*/ + struct drxoob { + s32 frequency; /**< Frequency in kHz */ + enum drxoob_downstream_standard standard; + /**< OOB standard */ + bool spectrum_inverted; /**< If true, then spectrum + is inverted */ + }; + +/*========================================*/ + +/** +* \brief Metrics from OOB. +* +* Used by DRX_CTRL_GET_OOB. +*/ + struct drxoob_status { + s32 frequency; /**< Frequency in Khz */ + enum drx_lock_status lock; /**< Lock status */ + u32 mer; /**< MER */ + s32 symbol_rate_offset; /**< Symbolrate offset in ppm */ + }; + +/*========================================*/ + +/** +* \brief Device dependent configuration data. +* +* Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. +* A sort of nested drx_ctrl() functionality for device specific controls. +*/ + struct drx_cfg { + u32 cfg_type; + /**< Function identifier */ + void *cfg_data; + /**< Function data */ + }; + +/*========================================*/ + +/** +* /struct DRXMpegStartWidth_t +* MStart width [nr MCLK cycles] for serial MPEG output. +*/ + + enum drxmpeg_str_width { + DRX_MPEG_STR_WIDTH_1, + DRX_MPEG_STR_WIDTH_8 + }; + +/* CTRL CFG MPEG ouput */ +/** +* \struct struct drx_cfg_mpeg_output * \brief Configuartion parameters for MPEG output control. +* +* Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and +* DRX_CTRL_GET_CFG. +*/ + + struct drx_cfg_mpeg_output { + bool enable_mpeg_output;/**< If true, enable MPEG output */ + bool insert_rs_byte; /**< If true, insert RS byte */ + bool enable_parallel; /**< If true, parallel out otherwise + serial */ + bool invert_data; /**< If true, invert DATA signals */ + bool invert_err; /**< If true, invert ERR signal */ + bool invert_str; /**< If true, invert STR signals */ + bool invert_val; /**< If true, invert VAL signals */ + bool invert_clk; /**< If true, invert CLK signals */ + bool static_clk; /**< If true, static MPEG clockrate + will be used, otherwise clockrate + will adapt to the bitrate of the + TS */ + u32 bitrate; /**< Maximum bitrate in b/s in case + static clockrate is selected */ + enum drxmpeg_str_width width_str; + /**< MPEG start width */ + }; + + +/*========================================*/ + +/** +* \struct struct drxi2c_data * \brief Data for I2C via 2nd or 3rd or etc I2C port. +* +* Used by DRX_CTRL_I2C_READWRITE. +* If port_nr is equal to primairy port_nr BSPI2C will be used. +* +*/ + struct drxi2c_data { + u16 port_nr; /**< I2C port number */ + struct i2c_device_addr *w_dev_addr; + /**< Write device address */ + u16 w_count; /**< Size of write data in bytes */ + u8 *wData; /**< Pointer to write data */ + struct i2c_device_addr *r_dev_addr; + /**< Read device address */ + u16 r_count; /**< Size of data to read in bytes */ + u8 *r_data; /**< Pointer to read buffer */ + }; + +/*========================================*/ + +/** +* \enum enum drx_aud_standard * \brief Audio standard identifier. +* +* Used by DRX_CTRL_SET_AUD. +*/ + enum drx_aud_standard { + DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */ + DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */ + DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */ + DRX_AUD_STANDARD_FM_STEREO,/**< set to FM-Stereo Radio */ + DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */ + DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */ + DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */ + DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */ + DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */ + DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */ + DRX_AUD_STANDARD_BG_NICAM_FM, + /**< set BG_NICAM_FM standard */ + DRX_AUD_STANDARD_L_NICAM_AM, + /**< set L_NICAM_AM standard */ + DRX_AUD_STANDARD_I_NICAM_FM, + /**< set I_NICAM_FM standard */ + DRX_AUD_STANDARD_D_K_NICAM_FM, + /**< set D_K_NICAM_FM standard */ + DRX_AUD_STANDARD_NOT_READY,/**< used to detect audio standard */ + DRX_AUD_STANDARD_AUTO = DRX_AUTO, + /**< Automatic Standard Detection */ + DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN + /**< used as auto and for readback */ + }; + +/* CTRL_AUD_GET_STATUS - struct drx_aud_status */ +/** +* \enum enum drx_aud_nicam_status * \brief Status of NICAM carrier. +*/ + enum drx_aud_nicam_status { + DRX_AUD_NICAM_DETECTED = 0, + /**< NICAM carrier detected */ + DRX_AUD_NICAM_NOT_DETECTED, + /**< NICAM carrier not detected */ + DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */ + }; + +/** +* \struct struct drx_aud_status * \brief Audio status characteristics. +*/ + struct drx_aud_status { + bool stereo; /**< stereo detection */ + bool carrier_a; /**< carrier A detected */ + bool carrier_b; /**< carrier B detected */ + bool sap; /**< sap / bilingual detection */ + bool rds; /**< RDS data array present */ + enum drx_aud_nicam_status nicam_status; + /**< status of NICAM carrier */ + s8 fm_ident; /**< FM Identification value */ + }; + +/* CTRL_AUD_READ_RDS - DRXRDSdata_t */ + +/** +* \struct DRXRDSdata_t +* \brief Raw RDS data array. +*/ + struct drx_cfg_aud_rds { + bool valid; /**< RDS data validation */ + u16 data[18]; /**< data from one RDS data array */ + }; + +/* DRX_CFG_AUD_VOLUME - struct drx_cfg_aud_volume - set/get */ +/** +* \enum DRXAudAVCDecayTime_t +* \brief Automatic volume control configuration. +*/ + enum drx_aud_avc_mode { + DRX_AUD_AVC_OFF, /**< Automatic volume control off */ + DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */ + DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */ + DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */ + DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */ + }; + +/** +* /enum DRXAudMaxAVCGain_t +* /brief Automatic volume control max gain in audio baseband. +*/ + enum drx_aud_avc_max_gain { + DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */ + DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */ + DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */ + }; + +/** +* /enum DRXAudMaxAVCAtten_t +* /brief Automatic volume control max attenuation in audio baseband. +*/ + enum drx_aud_avc_max_atten { + DRX_AUD_AVC_MAX_ATTEN_12DB, + /**< maximum AVC attenuation 12 dB */ + DRX_AUD_AVC_MAX_ATTEN_18DB, + /**< maximum AVC attenuation 18 dB */ + DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */ + }; +/** +* \struct struct drx_cfg_aud_volume * \brief Audio volume configuration. +*/ + struct drx_cfg_aud_volume { + bool mute; /**< mute overrides volume setting */ + s16 volume; /**< volume, range -114 to 12 dB */ + enum drx_aud_avc_mode avc_mode; /**< AVC auto volume control mode */ + u16 avc_ref_level; /**< AVC reference level */ + enum drx_aud_avc_max_gain avc_max_gain; + /**< AVC max gain selection */ + enum drx_aud_avc_max_atten avc_max_atten; + /**< AVC max attenuation selection */ + s16 strength_left; /**< quasi-peak, left speaker */ + s16 strength_right; /**< quasi-peak, right speaker */ + }; + +/* DRX_CFG_I2S_OUTPUT - struct drx_cfg_i2s_output - set/get */ +/** +* \enum enum drxi2s_mode * \brief I2S output mode. +*/ + enum drxi2s_mode { + DRX_I2S_MODE_MASTER, /**< I2S is in master mode */ + DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */ + }; + +/** +* \enum enum drxi2s_word_length * \brief Width of I2S data. +*/ + enum drxi2s_word_length { + DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */ + DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */ + }; + +/** +* \enum enum drxi2s_format * \brief Data wordstrobe alignment for I2S. +*/ + enum drxi2s_format { + DRX_I2S_FORMAT_WS_WITH_DATA, + /**< I2S data and wordstrobe are aligned */ + DRX_I2S_FORMAT_WS_ADVANCED + /**< I2S data one cycle after wordstrobe */ + }; + +/** +* \enum enum drxi2s_polarity * \brief Polarity of I2S data. +*/ + enum drxi2s_polarity { + DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */ + DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */ + }; + +/** +* \struct struct drx_cfg_i2s_output * \brief I2S output configuration. +*/ + struct drx_cfg_i2s_output { + bool output_enable; /**< I2S output enable */ + u32 frequency; /**< range from 8000-48000 Hz */ + enum drxi2s_mode mode; /**< I2S mode, master or slave */ + enum drxi2s_word_length word_length; + /**< I2S wordlength, 16 or 32 bits */ + enum drxi2s_polarity polarity;/**< I2S wordstrobe polarity */ + enum drxi2s_format format; /**< I2S wordstrobe delay to data */ + }; + +/* ------------------------------expert interface-----------------------------*/ +/** +* /enum enum drx_aud_fm_deemphasis * setting for FM-Deemphasis in audio demodulator. +* +*/ + enum drx_aud_fm_deemphasis { + DRX_AUD_FM_DEEMPH_50US, + DRX_AUD_FM_DEEMPH_75US, + DRX_AUD_FM_DEEMPH_OFF + }; + +/** +* /enum DRXAudDeviation_t +* setting for deviation mode in audio demodulator. +* +*/ + enum drx_cfg_aud_deviation { + DRX_AUD_DEVIATION_NORMAL, + DRX_AUD_DEVIATION_HIGH + }; + +/** +* /enum enum drx_no_carrier_option * setting for carrier, mute/noise. +* +*/ + enum drx_no_carrier_option { + DRX_NO_CARRIER_MUTE, + DRX_NO_CARRIER_NOISE + }; + +/** +* \enum DRXAudAutoSound_t +* \brief Automatic Sound +*/ + enum drx_cfg_aud_auto_sound { + DRX_AUD_AUTO_SOUND_OFF = 0, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF + }; + +/** +* \enum DRXAudASSThres_t +* \brief Automatic Sound Select Thresholds +*/ + struct drx_cfg_aud_ass_thres { + u16 a2; /* A2 Threshold for ASS configuration */ + u16 btsc; /* BTSC Threshold for ASS configuration */ + u16 nicam; /* Nicam Threshold for ASS configuration */ + }; + +/** +* \struct struct drx_aud_carrier * \brief Carrier detection related parameters +*/ + struct drx_aud_carrier { + u16 thres; /* carrier detetcion threshold for primary carrier (A) */ + enum drx_no_carrier_option opt; /* Mute or noise at no carrier detection (A) */ + s32 shift; /* DC level of incoming signal (A) */ + s32 dco; /* frequency adjustment (A) */ + }; + +/** +* \struct struct drx_cfg_aud_carriers * \brief combining carrier A & B to one struct +*/ + struct drx_cfg_aud_carriers { + struct drx_aud_carrier a; + struct drx_aud_carrier b; + }; + +/** +* /enum enum drx_aud_i2s_src * Selection of audio source +*/ + enum drx_aud_i2s_src { + DRX_AUD_SRC_MONO, + DRX_AUD_SRC_STEREO_OR_AB, + DRX_AUD_SRC_STEREO_OR_A, + DRX_AUD_SRC_STEREO_OR_B}; + +/** +* \enum enum drx_aud_i2s_matrix * \brief Used for selecting I2S output. +*/ + enum drx_aud_i2s_matrix { + DRX_AUD_I2S_MATRIX_A_MONO, + /**< A sound only, stereo or mono */ + DRX_AUD_I2S_MATRIX_B_MONO, + /**< B sound only, stereo or mono */ + DRX_AUD_I2S_MATRIX_STEREO, + /**< A+B sound, transparant */ + DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */}; + +/** +* /enum enum drx_aud_fm_matrix * setting for FM-Matrix in audio demodulator. +* +*/ + enum drx_aud_fm_matrix { + DRX_AUD_FM_MATRIX_NO_MATRIX, + DRX_AUD_FM_MATRIX_GERMAN, + DRX_AUD_FM_MATRIX_KOREAN, + DRX_AUD_FM_MATRIX_SOUND_A, + DRX_AUD_FM_MATRIX_SOUND_B}; + +/** +* \struct DRXAudMatrices_t +* \brief Mixer settings +*/ +struct drx_cfg_aud_mixer { + enum drx_aud_i2s_src source_i2s; + enum drx_aud_i2s_matrix matrix_i2s; + enum drx_aud_fm_matrix matrix_fm; +}; + +/** +* \enum DRXI2SVidSync_t +* \brief Audio/video synchronization, interacts with I2S mode. +* AUTO_1 and AUTO_2 are for automatic video standard detection with preference +* for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz) +*/ + enum drx_cfg_aud_av_sync { + DRX_AUD_AVSYNC_OFF,/**< audio/video synchronization is off */ + DRX_AUD_AVSYNC_NTSC, + /**< it is an NTSC system */ + DRX_AUD_AVSYNC_MONOCHROME, + /**< it is a MONOCHROME system */ + DRX_AUD_AVSYNC_PAL_SECAM + /**< it is a PAL/SECAM system */}; + +/** +* \struct struct drx_cfg_aud_prescale * \brief Prescalers +*/ +struct drx_cfg_aud_prescale { + u16 fm_deviation; + s16 nicam_gain; +}; + +/** +* \struct struct drx_aud_beep * \brief Beep +*/ +struct drx_aud_beep { + s16 volume; /* dB */ + u16 frequency; /* Hz */ + bool mute; +}; + +/** +* \enum enum drx_aud_btsc_detect * \brief BTSC detetcion mode +*/ + enum drx_aud_btsc_detect { + DRX_BTSC_STEREO, + DRX_BTSC_MONO_AND_SAP}; + +/** +* \struct struct drx_aud_data * \brief Audio data structure +*/ +struct drx_aud_data { + /* audio storage */ + bool audio_is_active; + enum drx_aud_standard audio_standard; + struct drx_cfg_i2s_output i2sdata; + struct drx_cfg_aud_volume volume; + enum drx_cfg_aud_auto_sound auto_sound; + struct drx_cfg_aud_ass_thres ass_thresholds; + struct drx_cfg_aud_carriers carriers; + struct drx_cfg_aud_mixer mixer; + enum drx_cfg_aud_deviation deviation; + enum drx_cfg_aud_av_sync av_sync; + struct drx_cfg_aud_prescale prescale; + enum drx_aud_fm_deemphasis deemph; + enum drx_aud_btsc_detect btsc_detect; + /* rds */ + u16 rds_data_counter; + bool rds_data_present; +}; + +/** +* \enum enum drx_qam_lock_range * \brief QAM lock range mode +*/ + enum drx_qam_lock_range { + DRX_QAM_LOCKRANGE_NORMAL, + DRX_QAM_LOCKRANGE_EXTENDED}; + +/*============================================================================*/ +/*============================================================================*/ +/*== Data access structures ==================================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* Address on device */ + typedef u32 dr_xaddr_t, *pdr_xaddr_t; + +/* Protocol specific flags */ + typedef u32 dr_xflags_t, *pdr_xflags_t; + +/* Write block of data to device */ + typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u16 datasize, /* size of data in bytes */ + u8 *data, /* data to send */ + u32 flags); + +/* Read block of data from device */ + typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u16 datasize, /* size of data in bytes */ + u8 *data, /* receive buffer */ + u32 flags); + +/* Write 8-bits value to device */ + typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u8 data, /* data to send */ + u32 flags); + +/* Read 8-bits value to device */ + typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u8 *data, /* receive buffer */ + u32 flags); + +/* Read modify write 8-bits value to device */ + typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 waddr, /* write address of register */ + u32 raddr, /* read address of register */ + u8 wdata, /* data to write */ + u8 *rdata); /* data to read */ + +/* Write 16-bits value to device */ + typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u16 data, /* data to send */ + u32 flags); + +/* Read 16-bits value to device */ + typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u16 *data, /* receive buffer */ + u32 flags); + +/* Read modify write 16-bits value to device */ + typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 waddr, /* write address of register */ + u32 raddr, /* read address of register */ + u16 wdata, /* data to write */ + u16 *rdata); /* data to read */ + +/* Write 32-bits value to device */ + typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u32 data, /* data to send */ + u32 flags); + +/* Read 32-bits value to device */ + typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u32 *data, /* receive buffer */ + u32 flags); + +/* Read modify write 32-bits value to device */ + typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 waddr, /* write address of register */ + u32 raddr, /* read address of register */ + u32 wdata, /* data to write */ + u32 *rdata); /* data to read */ + +/** +* \struct struct drx_access_func * \brief Interface to an access protocol. +*/ +struct drx_access_func { + drx_write_block_func_t write_block_func; + drx_read_block_func_t read_block_func; + drx_write_reg8func_t write_reg8func; + drx_read_reg8func_t read_reg8func; + drx_read_modify_write_reg8func_t read_modify_write_reg8func; + drx_write_reg16func_t write_reg16func; + drx_read_reg16func_t read_reg16func; + drx_read_modify_write_reg16func_t read_modify_write_reg16func; + drx_write_reg32func_t write_reg32func; + drx_read_reg32func_t read_reg32func; + drx_read_modify_write_reg32func_t read_modify_write_reg32func; +}; + +/* Register address and data for register dump function */ +struct drx_reg_dump { + u32 address; + u32 data; +}; + +/*============================================================================*/ +/*============================================================================*/ +/*== Demod instance data structures ==========================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \struct struct drx_common_attr * \brief Set of common attributes, shared by all DRX devices. +*/ + struct drx_common_attr { + /* Microcode (firmware) attributes */ + char *microcode_file; /**< microcode filename */ + bool verify_microcode; + /**< Use microcode verify or not. */ + struct drx_mc_version_rec mcversion; + /**< Version record of microcode from file */ + + /* Clocks and tuner attributes */ + s32 intermediate_freq; + /**< IF,if tuner instance not used. (kHz)*/ + s32 sys_clock_freq; + /**< Systemclock frequency. (kHz) */ + s32 osc_clock_freq; + /**< Oscillator clock frequency. (kHz) */ + s16 osc_clock_deviation; + /**< Oscillator clock deviation. (ppm) */ + bool mirror_freq_spect; + /**< Mirror IF frequency spectrum or not.*/ + + /* Initial MPEG output attributes */ + struct drx_cfg_mpeg_output mpeg_cfg; + /**< MPEG configuration */ + + bool is_opened; /**< if true instance is already opened. */ + + /* Channel scan */ + struct drx_scan_param *scan_param; + /**< scan parameters */ + u16 scan_freq_plan_index; + /**< next index in freq plan */ + s32 scan_next_frequency; + /**< next freq to scan */ + bool scan_ready; /**< scan ready flag */ + u32 scan_max_channels;/**< number of channels in freqplan */ + u32 scan_channels_scanned; + /**< number of channels scanned */ + /* Channel scan - inner loop: demod related */ + drx_scan_func_t scan_function; + /**< function to check channel */ + /* Channel scan - inner loop: SYSObj related */ + void *scan_context; /**< Context Pointer of SYSObj */ + /* Channel scan - parameters for default DTV scan function in core driver */ + u16 scan_demod_lock_timeout; + /**< millisecs to wait for lock */ + enum drx_lock_status scan_desired_lock; + /**< lock requirement for channel found */ + /* scan_active can be used by SetChannel to decide how to program the tuner, + fast or slow (but stable). Usually fast during scan. */ + bool scan_active; /**< true when scan routines are active */ + + /* Power management */ + enum drx_power_mode current_power_mode; + /**< current power management mode */ + + /* Tuner */ + u8 tuner_port_nr; /**< nr of I2C port to wich tuner is */ + s32 tuner_min_freq_rf; + /**< minimum RF input frequency, in kHz */ + s32 tuner_max_freq_rf; + /**< maximum RF input frequency, in kHz */ + bool tuner_rf_agc_pol; /**< if true invert RF AGC polarity */ + bool tuner_if_agc_pol; /**< if true invert IF AGC polarity */ + bool tuner_slow_mode; /**< if true invert IF AGC polarity */ + + struct drx_channel current_channel; + /**< current channel parameters */ + enum drx_standard current_standard; + /**< current standard selection */ + enum drx_standard prev_standard; + /**< previous standard selection */ + enum drx_standard di_cache_standard; + /**< standard in DI cache if available */ + bool use_bootloader; /**< use bootloader in open */ + u32 capabilities; /**< capabilities flags */ + u32 product_id; /**< product ID inc. metal fix number */}; + +/* +* Generic functions for DRX devices. +*/ + +struct drx_demod_instance; + +/** +* \struct struct drx_demod_instance * \brief Top structure of demodulator instance. +*/ +struct drx_demod_instance { + /**< data access protocol functions */ + struct i2c_device_addr *my_i2c_dev_addr; + /**< i2c address and device identifier */ + struct drx_common_attr *my_common_attr; + /**< common DRX attributes */ + void *my_ext_attr; /**< device specific attributes */ + /* generic demodulator data */ + + struct i2c_adapter *i2c; + const struct firmware *firmware; +}; + +/*------------------------------------------------------------------------- +MACROS +Conversion from enum values to human readable form. +-------------------------------------------------------------------------*/ + +/* standard */ + +#define DRX_STR_STANDARD(x) ( \ + (x == DRX_STANDARD_DVBT) ? "DVB-T" : \ + (x == DRX_STANDARD_8VSB) ? "8VSB" : \ + (x == DRX_STANDARD_NTSC) ? "NTSC" : \ + (x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \ + (x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \ + (x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \ + (x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \ + (x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \ + (x == DRX_STANDARD_ITU_A) ? "ITU-A" : \ + (x == DRX_STANDARD_ITU_B) ? "ITU-B" : \ + (x == DRX_STANDARD_ITU_C) ? "ITU-C" : \ + (x == DRX_STANDARD_ITU_D) ? "ITU-D" : \ + (x == DRX_STANDARD_FM) ? "FM" : \ + (x == DRX_STANDARD_DTMB) ? "DTMB" : \ + (x == DRX_STANDARD_AUTO) ? "Auto" : \ + (x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \ + "(Invalid)") + +/* channel */ + +#define DRX_STR_BANDWIDTH(x) ( \ + (x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \ + (x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \ + (x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \ + (x == DRX_BANDWIDTH_AUTO) ? "Auto" : \ + (x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_FFTMODE(x) ( \ + (x == DRX_FFTMODE_2K) ? "2k" : \ + (x == DRX_FFTMODE_4K) ? "4k" : \ + (x == DRX_FFTMODE_8K) ? "8k" : \ + (x == DRX_FFTMODE_AUTO) ? "Auto" : \ + (x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_GUARD(x) ( \ + (x == DRX_GUARD_1DIV32) ? "1/32nd" : \ + (x == DRX_GUARD_1DIV16) ? "1/16th" : \ + (x == DRX_GUARD_1DIV8) ? "1/8th" : \ + (x == DRX_GUARD_1DIV4) ? "1/4th" : \ + (x == DRX_GUARD_AUTO) ? "Auto" : \ + (x == DRX_GUARD_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_CONSTELLATION(x) ( \ + (x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \ + (x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \ + (x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \ + (x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \ + (x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \ + (x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \ + (x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \ + (x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \ + (x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \ + (x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \ + (x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \ + (x == DRX_CONSTELLATION_AUTO) ? "Auto" : \ + (x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_CODERATE(x) ( \ + (x == DRX_CODERATE_1DIV2) ? "1/2nd" : \ + (x == DRX_CODERATE_2DIV3) ? "2/3rd" : \ + (x == DRX_CODERATE_3DIV4) ? "3/4th" : \ + (x == DRX_CODERATE_5DIV6) ? "5/6th" : \ + (x == DRX_CODERATE_7DIV8) ? "7/8th" : \ + (x == DRX_CODERATE_AUTO) ? "Auto" : \ + (x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_HIERARCHY(x) ( \ + (x == DRX_HIERARCHY_NONE) ? "None" : \ + (x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \ + (x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \ + (x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \ + (x == DRX_HIERARCHY_AUTO) ? "Auto" : \ + (x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_PRIORITY(x) ( \ + (x == DRX_PRIORITY_LOW) ? "Low" : \ + (x == DRX_PRIORITY_HIGH) ? "High" : \ + (x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_MIRROR(x) ( \ + (x == DRX_MIRROR_NO) ? "Normal" : \ + (x == DRX_MIRROR_YES) ? "Mirrored" : \ + (x == DRX_MIRROR_AUTO) ? "Auto" : \ + (x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_CLASSIFICATION(x) ( \ + (x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \ + (x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \ + (x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \ + (x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \ + (x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \ + (x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \ + (x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \ + (x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \ + "(Invalid)") + +#define DRX_STR_INTERLEAVEMODE(x) ( \ + (x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \ + (x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \ + (x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \ + (x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \ + (x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \ + (x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \ + (x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \ + (x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \ + (x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \ + (x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \ + (x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \ + (x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \ + (x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \ + (x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \ + (x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \ + (x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \ + (x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \ + (x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \ + (x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \ + (x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \ + (x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \ + (x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \ + (x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \ + (x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \ + "(Invalid)") + +#define DRX_STR_LDPC(x) ( \ + (x == DRX_LDPC_0_4) ? "0.4" : \ + (x == DRX_LDPC_0_6) ? "0.6" : \ + (x == DRX_LDPC_0_8) ? "0.8" : \ + (x == DRX_LDPC_AUTO) ? "Auto" : \ + (x == DRX_LDPC_UNKNOWN) ? "Unknown" : \ + "(Invalid)") + +#define DRX_STR_CARRIER(x) ( \ + (x == DRX_CARRIER_MULTI) ? "Multi" : \ + (x == DRX_CARRIER_SINGLE) ? "Single" : \ + (x == DRX_CARRIER_AUTO) ? "Auto" : \ + (x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \ + "(Invalid)") + +#define DRX_STR_FRAMEMODE(x) ( \ + (x == DRX_FRAMEMODE_420) ? "420" : \ + (x == DRX_FRAMEMODE_595) ? "595" : \ + (x == DRX_FRAMEMODE_945) ? "945" : \ + (x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \ + (x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \ + (x == DRX_FRAMEMODE_AUTO) ? "Auto" : \ + (x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") + +#define DRX_STR_PILOT(x) ( \ + (x == DRX_PILOT_ON) ? "On" : \ + (x == DRX_PILOT_OFF) ? "Off" : \ + (x == DRX_PILOT_AUTO) ? "Auto" : \ + (x == DRX_PILOT_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +/* TPS */ + +#define DRX_STR_TPS_FRAME(x) ( \ + (x == DRX_TPS_FRAME1) ? "Frame1" : \ + (x == DRX_TPS_FRAME2) ? "Frame2" : \ + (x == DRX_TPS_FRAME3) ? "Frame3" : \ + (x == DRX_TPS_FRAME4) ? "Frame4" : \ + (x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \ + "(Invalid)") + +/* lock status */ + +#define DRX_STR_LOCKSTATUS(x) ( \ + (x == DRX_NEVER_LOCK) ? "Never" : \ + (x == DRX_NOT_LOCKED) ? "No" : \ + (x == DRX_LOCKED) ? "Locked" : \ + (x == DRX_LOCK_STATE_1) ? "Lock state 1" : \ + (x == DRX_LOCK_STATE_2) ? "Lock state 2" : \ + (x == DRX_LOCK_STATE_3) ? "Lock state 3" : \ + (x == DRX_LOCK_STATE_4) ? "Lock state 4" : \ + (x == DRX_LOCK_STATE_5) ? "Lock state 5" : \ + (x == DRX_LOCK_STATE_6) ? "Lock state 6" : \ + (x == DRX_LOCK_STATE_7) ? "Lock state 7" : \ + (x == DRX_LOCK_STATE_8) ? "Lock state 8" : \ + (x == DRX_LOCK_STATE_9) ? "Lock state 9" : \ + "(Invalid)") + +/* version information , modules */ +#define DRX_STR_MODULE(x) ( \ + (x == DRX_MODULE_DEVICE) ? "Device" : \ + (x == DRX_MODULE_MICROCODE) ? "Microcode" : \ + (x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \ + (x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \ + (x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \ + (x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \ + (x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \ + (x == DRX_MODULE_DAP) ? "Data Access Protocol" : \ + (x == DRX_MODULE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") + +#define DRX_STR_POWER_MODE(x) ( \ + (x == DRX_POWER_UP) ? "DRX_POWER_UP " : \ + (x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \ + (x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \ + (x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \ + (x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \ + (x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \ + (x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \ + (x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \ + (x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \ + (x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \ + (x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \ + (x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \ + (x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \ + (x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \ + (x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \ + (x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \ + (x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \ + (x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \ + "(Invalid)") + +#define DRX_STR_OOB_STANDARD(x) ( \ + (x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \ + (x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \ + (x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \ + "(Invalid)") + +#define DRX_STR_AUD_STANDARD(x) ( \ + (x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \ + (x == DRX_AUD_STANDARD_A2) ? "A2" : \ + (x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \ + (x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \ + (x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \ + (x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \ + (x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \ + (x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \ + (x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \ + (x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \ + (x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \ + (x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \ + (x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \ + (x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \ + (x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \ + (x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_AUD_STEREO(x) ( \ + (x == true) ? "Stereo" : \ + (x == false) ? "Mono" : \ + "(Invalid)") + +#define DRX_STR_AUD_SAP(x) ( \ + (x == true) ? "Present" : \ + (x == false) ? "Not present" : \ + "(Invalid)") + +#define DRX_STR_AUD_CARRIER(x) ( \ + (x == true) ? "Present" : \ + (x == false) ? "Not present" : \ + "(Invalid)") + +#define DRX_STR_AUD_RDS(x) ( \ + (x == true) ? "Available" : \ + (x == false) ? "Not Available" : \ + "(Invalid)") + +#define DRX_STR_AUD_NICAM_STATUS(x) ( \ + (x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \ + (x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \ + (x == DRX_AUD_NICAM_BAD) ? "Bad" : \ + "(Invalid)") + +#define DRX_STR_RDS_VALID(x) ( \ + (x == true) ? "Valid" : \ + (x == false) ? "Not Valid" : \ + "(Invalid)") + +/*------------------------------------------------------------------------- +Access macros +-------------------------------------------------------------------------*/ + +/** +* \brief Create a compilable reference to the microcode attribute +* \param d pointer to demod instance +* +* Used as main reference to an attribute field. +* Used by both macro implementation and function implementation. +* These macros are defined to avoid duplication of code in macro and function +* definitions that handle access of demod common or extended attributes. +* +*/ + +#define DRX_ATTR_MCRECORD(d) ((d)->my_common_attr->mcversion) +#define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->my_common_attr->mirror_freq_spect) +#define DRX_ATTR_CURRENTPOWERMODE(d)((d)->my_common_attr->current_power_mode) +#define DRX_ATTR_ISOPENED(d) ((d)->my_common_attr->is_opened) +#define DRX_ATTR_USEBOOTLOADER(d) ((d)->my_common_attr->use_bootloader) +#define DRX_ATTR_CURRENTSTANDARD(d) ((d)->my_common_attr->current_standard) +#define DRX_ATTR_PREVSTANDARD(d) ((d)->my_common_attr->prev_standard) +#define DRX_ATTR_CACHESTANDARD(d) ((d)->my_common_attr->di_cache_standard) +#define DRX_ATTR_CURRENTCHANNEL(d) ((d)->my_common_attr->current_channel) +#define DRX_ATTR_MICROCODE(d) ((d)->my_common_attr->microcode) +#define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode) +#define DRX_ATTR_CAPABILITIES(d) ((d)->my_common_attr->capabilities) +#define DRX_ATTR_PRODUCTID(d) ((d)->my_common_attr->product_id) +#define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->my_common_attr->intermediate_freq) +#define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->my_common_attr->sys_clock_freq) +#define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->my_common_attr->tuner_rf_agc_pol) +#define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->my_common_attr->tuner_if_agc_pol) +#define DRX_ATTR_TUNERSLOWMODE(d) ((d)->my_common_attr->tuner_slow_mode) +#define DRX_ATTR_TUNERSPORTNR(d) ((d)->my_common_attr->tuner_port_nr) +#define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr) +#define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id) +#define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD) + +/**************************/ + +/* Macros with device-specific handling are converted to CFG functions */ + +#define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \ + do { \ + struct drx_cfg config; \ + data_type cfg_data; \ + config.cfg_type = cfg_name; \ + config.cfg_data = &cfg_data; \ + cfg_data = value; \ + drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \ + } while (0) + +#define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \ + do { \ + int cfg_status; \ + struct drx_cfg config; \ + data_type cfg_data; \ + config.cfg_type = cfg_name; \ + config.cfg_data = &cfg_data; \ + cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \ + if (cfg_status == 0) { \ + value = cfg_data; \ + } else { \ + value = (data_type)error_value; \ + } \ + } while (0) + +/* Configuration functions for usage by Access (XS) Macros */ + +#ifndef DRX_XS_CFG_BASE +#define DRX_XS_CFG_BASE (500) +#endif + +#define DRX_XS_CFG_PRESET (DRX_XS_CFG_BASE + 0) +#define DRX_XS_CFG_AUD_BTSC_DETECT (DRX_XS_CFG_BASE + 1) +#define DRX_XS_CFG_QAM_LOCKRANGE (DRX_XS_CFG_BASE + 2) + +/* Access Macros with device-specific handling */ + +#define DRX_SET_PRESET(d, x) \ + DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*) +#define DRX_GET_PRESET(d, x) \ + DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR") + +#define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \ + DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect) +#define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \ + DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect, DRX_UNKNOWN) + +#define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \ + DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range) +#define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \ + DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range, DRX_UNKNOWN) + +/** +* \brief Macro to check if std is an ATV standard +* \retval true std is an ATV standard +* \retval false std is an ATV standard +*/ +#define DRX_ISATVSTD(std) (((std) == DRX_STANDARD_PAL_SECAM_BG) || \ + ((std) == DRX_STANDARD_PAL_SECAM_DK) || \ + ((std) == DRX_STANDARD_PAL_SECAM_I) || \ + ((std) == DRX_STANDARD_PAL_SECAM_L) || \ + ((std) == DRX_STANDARD_PAL_SECAM_LP) || \ + ((std) == DRX_STANDARD_NTSC) || \ + ((std) == DRX_STANDARD_FM)) + +/** +* \brief Macro to check if std is an QAM standard +* \retval true std is an QAM standards +* \retval false std is an QAM standards +*/ +#define DRX_ISQAMSTD(std) (((std) == DRX_STANDARD_ITU_A) || \ + ((std) == DRX_STANDARD_ITU_B) || \ + ((std) == DRX_STANDARD_ITU_C) || \ + ((std) == DRX_STANDARD_ITU_D)) + +/** +* \brief Macro to check if std is VSB standard +* \retval true std is VSB standard +* \retval false std is not VSB standard +*/ +#define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB) + +/** +* \brief Macro to check if std is DVBT standard +* \retval true std is DVBT standard +* \retval false std is not DVBT standard +*/ +#define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT) + +/*------------------------------------------------------------------------- +THE END +-------------------------------------------------------------------------*/ +#endif /* __DRXDRIVER_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h new file mode 100644 index 0000000..ff05a4f --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h @@ -0,0 +1,72 @@ +/* + ******************************************************************************* + * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE + * + * Filename: drx_driver_version.h + * Generated on: Mon Jan 18 12:09:23 2010 + * Generated by: IDF:x 1.3.0 + * Generated from: ../../../device/drxj/version + * Output start: [entry point] + * + * filename last modified re-use + * + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/* ----------------------------------------------------- + * version.idf Mon Jan 18 11:56:10 2010 - + * + */ + +#ifndef __DRX_DRIVER_VERSION__H__ +#define __DRX_DRIVER_VERSION__H__ INCLUDED + +#ifdef _REGISTERTABLE_ +#include <registertable.h> + extern register_table_t drx_driver_version[]; + extern register_table_info_t drx_driver_version_info[]; +#endif /* _REGISTERTABLE_ */ + +/* + *============================================================================== + * VERSION + * version@/var/cvs/projects/drxj.cvsroot/hostcode/drxdriver/device/drxj + *============================================================================== + */ + +#define VERSION__A 0x0 +#define VERSION_MAJOR 1 +#define VERSION_MINOR 0 +#define VERSION_PATCH 56 + +#endif /* __DRX_DRIVER_VERSION__H__ */ +/* + * End of file (drx_driver_version.h) + ******************************************************************************* + */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c new file mode 100644 index 0000000..9482954 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -0,0 +1,12400 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + + DRXJ specific implementation of DRX driver + authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen + + The Linux DVB Driver for Micronas DRX39xx family (drx3933j) was + written by Devin Heitmueller <devin.heitmueller@kernellabs.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +/*----------------------------------------------------------------------------- +INCLUDE FILES +----------------------------------------------------------------------------*/ + +#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <asm/div64.h> + +#include "dvb_frontend.h" +#include "drx39xxj.h" + +#include "drxj.h" +#include "drxj_map.h" + +/*============================================================================*/ +/*=== DEFINES ================================================================*/ +/*============================================================================*/ + +#define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw" + +/** +* \brief Maximum u32 value. +*/ +#ifndef MAX_U32 +#define MAX_U32 ((u32) (0xFFFFFFFFL)) +#endif + +/* Customer configurable hardware settings, etc */ +#ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH +#define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02 +#endif + +#ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH +#define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02 +#endif + +#ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH +#define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06 +#endif + +#ifndef OOB_CRX_DRIVE_STRENGTH +#define OOB_CRX_DRIVE_STRENGTH 0x02 +#endif + +#ifndef OOB_DRX_DRIVE_STRENGTH +#define OOB_DRX_DRIVE_STRENGTH 0x02 +#endif +/**** START DJCOMBO patches to DRXJ registermap constants *********************/ +/**** registermap 200706071303 from drxj **************************************/ +#define ATV_TOP_CR_AMP_TH_FM 0x0 +#define ATV_TOP_CR_AMP_TH_L 0xA +#define ATV_TOP_CR_AMP_TH_LP 0xA +#define ATV_TOP_CR_AMP_TH_BG 0x8 +#define ATV_TOP_CR_AMP_TH_DK 0x8 +#define ATV_TOP_CR_AMP_TH_I 0x8 +#define ATV_TOP_CR_CONT_CR_D_MN 0x18 +#define ATV_TOP_CR_CONT_CR_D_FM 0x0 +#define ATV_TOP_CR_CONT_CR_D_L 0x20 +#define ATV_TOP_CR_CONT_CR_D_LP 0x20 +#define ATV_TOP_CR_CONT_CR_D_BG 0x18 +#define ATV_TOP_CR_CONT_CR_D_DK 0x18 +#define ATV_TOP_CR_CONT_CR_D_I 0x18 +#define ATV_TOP_CR_CONT_CR_I_MN 0x80 +#define ATV_TOP_CR_CONT_CR_I_FM 0x0 +#define ATV_TOP_CR_CONT_CR_I_L 0x80 +#define ATV_TOP_CR_CONT_CR_I_LP 0x80 +#define ATV_TOP_CR_CONT_CR_I_BG 0x80 +#define ATV_TOP_CR_CONT_CR_I_DK 0x80 +#define ATV_TOP_CR_CONT_CR_I_I 0x80 +#define ATV_TOP_CR_CONT_CR_P_MN 0x4 +#define ATV_TOP_CR_CONT_CR_P_FM 0x0 +#define ATV_TOP_CR_CONT_CR_P_L 0x4 +#define ATV_TOP_CR_CONT_CR_P_LP 0x4 +#define ATV_TOP_CR_CONT_CR_P_BG 0x4 +#define ATV_TOP_CR_CONT_CR_P_DK 0x4 +#define ATV_TOP_CR_CONT_CR_P_I 0x4 +#define ATV_TOP_CR_OVM_TH_MN 0xA0 +#define ATV_TOP_CR_OVM_TH_FM 0x0 +#define ATV_TOP_CR_OVM_TH_L 0xA0 +#define ATV_TOP_CR_OVM_TH_LP 0xA0 +#define ATV_TOP_CR_OVM_TH_BG 0xA0 +#define ATV_TOP_CR_OVM_TH_DK 0xA0 +#define ATV_TOP_CR_OVM_TH_I 0xA0 +#define ATV_TOP_EQU0_EQU_C0_FM 0x0 +#define ATV_TOP_EQU0_EQU_C0_L 0x3 +#define ATV_TOP_EQU0_EQU_C0_LP 0x3 +#define ATV_TOP_EQU0_EQU_C0_BG 0x7 +#define ATV_TOP_EQU0_EQU_C0_DK 0x0 +#define ATV_TOP_EQU0_EQU_C0_I 0x3 +#define ATV_TOP_EQU1_EQU_C1_FM 0x0 +#define ATV_TOP_EQU1_EQU_C1_L 0x1F6 +#define ATV_TOP_EQU1_EQU_C1_LP 0x1F6 +#define ATV_TOP_EQU1_EQU_C1_BG 0x197 +#define ATV_TOP_EQU1_EQU_C1_DK 0x198 +#define ATV_TOP_EQU1_EQU_C1_I 0x1F6 +#define ATV_TOP_EQU2_EQU_C2_FM 0x0 +#define ATV_TOP_EQU2_EQU_C2_L 0x28 +#define ATV_TOP_EQU2_EQU_C2_LP 0x28 +#define ATV_TOP_EQU2_EQU_C2_BG 0xC5 +#define ATV_TOP_EQU2_EQU_C2_DK 0xB0 +#define ATV_TOP_EQU2_EQU_C2_I 0x28 +#define ATV_TOP_EQU3_EQU_C3_FM 0x0 +#define ATV_TOP_EQU3_EQU_C3_L 0x192 +#define ATV_TOP_EQU3_EQU_C3_LP 0x192 +#define ATV_TOP_EQU3_EQU_C3_BG 0x12E +#define ATV_TOP_EQU3_EQU_C3_DK 0x18E +#define ATV_TOP_EQU3_EQU_C3_I 0x192 +#define ATV_TOP_STD_MODE_MN 0x0 +#define ATV_TOP_STD_MODE_FM 0x1 +#define ATV_TOP_STD_MODE_L 0x0 +#define ATV_TOP_STD_MODE_LP 0x0 +#define ATV_TOP_STD_MODE_BG 0x0 +#define ATV_TOP_STD_MODE_DK 0x0 +#define ATV_TOP_STD_MODE_I 0x0 +#define ATV_TOP_STD_VID_POL_MN 0x0 +#define ATV_TOP_STD_VID_POL_FM 0x0 +#define ATV_TOP_STD_VID_POL_L 0x2 +#define ATV_TOP_STD_VID_POL_LP 0x2 +#define ATV_TOP_STD_VID_POL_BG 0x0 +#define ATV_TOP_STD_VID_POL_DK 0x0 +#define ATV_TOP_STD_VID_POL_I 0x0 +#define ATV_TOP_VID_AMP_MN 0x380 +#define ATV_TOP_VID_AMP_FM 0x0 +#define ATV_TOP_VID_AMP_L 0xF50 +#define ATV_TOP_VID_AMP_LP 0xF50 +#define ATV_TOP_VID_AMP_BG 0x380 +#define ATV_TOP_VID_AMP_DK 0x394 +#define ATV_TOP_VID_AMP_I 0x3D8 +#define IQM_CF_OUT_ENA_OFDM__M 0x4 +#define IQM_FS_ADJ_SEL_B_QAM 0x1 +#define IQM_FS_ADJ_SEL_B_OFF 0x0 +#define IQM_FS_ADJ_SEL_B_VSB 0x2 +#define IQM_RC_ADJ_SEL_B_OFF 0x0 +#define IQM_RC_ADJ_SEL_B_QAM 0x1 +#define IQM_RC_ADJ_SEL_B_VSB 0x2 +/**** END DJCOMBO patches to DRXJ registermap *********************************/ + +#include "drx_driver_version.h" + +/* #define DRX_DEBUG */ +#ifdef DRX_DEBUG +#include <stdio.h> +#endif + +/*----------------------------------------------------------------------------- +ENUMS +----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------- +DEFINES +----------------------------------------------------------------------------*/ +#ifndef DRXJ_WAKE_UP_KEY +#define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr) +#endif + +/** +* \def DRXJ_DEF_I2C_ADDR +* \brief Default I2C addres of a demodulator instance. +*/ +#define DRXJ_DEF_I2C_ADDR (0x52) + +/** +* \def DRXJ_DEF_DEMOD_DEV_ID +* \brief Default device identifier of a demodultor instance. +*/ +#define DRXJ_DEF_DEMOD_DEV_ID (1) + +/** +* \def DRXJ_SCAN_TIMEOUT +* \brief Timeout value for waiting on demod lock during channel scan (millisec). +*/ +#define DRXJ_SCAN_TIMEOUT 1000 + +/** +* \def HI_I2C_DELAY +* \brief HI timing delay for I2C timing (in nano seconds) +* +* Used to compute HI_CFG_DIV +*/ +#define HI_I2C_DELAY 42 + +/** +* \def HI_I2C_BRIDGE_DELAY +* \brief HI timing delay for I2C timing (in nano seconds) +* +* Used to compute HI_CFG_BDL +*/ +#define HI_I2C_BRIDGE_DELAY 750 + +/** +* \brief Time Window for MER and SER Measurement in Units of Segment duration. +*/ +#define VSB_TOP_MEASUREMENT_PERIOD 64 +#define SYMBOLS_PER_SEGMENT 832 + +/** +* \brief bit rate and segment rate constants used for SER and BER. +*/ +/* values taken from the QAM microcode */ +#define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0 +#define DRXJ_QAM_SL_SIG_POWER_QPSK 32768 +#define DRXJ_QAM_SL_SIG_POWER_QAM8 24576 +#define DRXJ_QAM_SL_SIG_POWER_QAM16 40960 +#define DRXJ_QAM_SL_SIG_POWER_QAM32 20480 +#define DRXJ_QAM_SL_SIG_POWER_QAM64 43008 +#define DRXJ_QAM_SL_SIG_POWER_QAM128 20992 +#define DRXJ_QAM_SL_SIG_POWER_QAM256 43520 +/** +* \brief Min supported symbolrates. +*/ +#ifndef DRXJ_QAM_SYMBOLRATE_MIN +#define DRXJ_QAM_SYMBOLRATE_MIN (520000) +#endif + +/** +* \brief Max supported symbolrates. +*/ +#ifndef DRXJ_QAM_SYMBOLRATE_MAX +#define DRXJ_QAM_SYMBOLRATE_MAX (7233000) +#endif + +/** +* \def DRXJ_QAM_MAX_WAITTIME +* \brief Maximal wait time for QAM auto constellation in ms +*/ +#ifndef DRXJ_QAM_MAX_WAITTIME +#define DRXJ_QAM_MAX_WAITTIME 900 +#endif + +#ifndef DRXJ_QAM_FEC_LOCK_WAITTIME +#define DRXJ_QAM_FEC_LOCK_WAITTIME 150 +#endif + +#ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME +#define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200 +#endif + +/** +* \def SCU status and results +* \brief SCU +*/ +#define DRX_SCU_READY 0 +#define DRXJ_MAX_WAITTIME 100 /* ms */ +#define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */ +#define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */ + +/** +* \def DRX_AUD_MAX_DEVIATION +* \brief Needed for calculation of prescale feature in AUD +*/ +#ifndef DRXJ_AUD_MAX_FM_DEVIATION +#define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */ +#endif + +/** +* \brief Needed for calculation of NICAM prescale feature in AUD +*/ +#ifndef DRXJ_AUD_MAX_NICAM_PRESCALE +#define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */ +#endif + +/** +* \brief Needed for calculation of NICAM prescale feature in AUD +*/ +#ifndef DRXJ_AUD_MAX_WAITTIME +#define DRXJ_AUD_MAX_WAITTIME 250 /* ms */ +#endif + +/* ATV config changed flags */ +#define DRXJ_ATV_CHANGED_COEF (0x00000001UL) +#define DRXJ_ATV_CHANGED_PEAK_FLT (0x00000008UL) +#define DRXJ_ATV_CHANGED_NOISE_FLT (0x00000010UL) +#define DRXJ_ATV_CHANGED_OUTPUT (0x00000020UL) +#define DRXJ_ATV_CHANGED_SIF_ATT (0x00000040UL) + +/* UIO define */ +#define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0 +#define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1 + +/* + * MICROCODE RELATED DEFINES + */ + +/* Magic word for checking correct Endianess of microcode data */ +#define DRX_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L')) + +/* CRC flag in ucode header, flags field. */ +#define DRX_UCODE_CRC_FLAG (0x0001) + +/* + * Maximum size of buffer used to verify the microcode. + * Must be an even number + */ +#define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE) + +#if DRX_UCODE_MAX_BUF_SIZE & 1 +#error DRX_UCODE_MAX_BUF_SIZE must be an even number +#endif + +/* + * Power mode macros + */ + +#define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \ + (mode == DRX_POWER_MODE_10) || \ + (mode == DRX_POWER_MODE_11) || \ + (mode == DRX_POWER_MODE_12) || \ + (mode == DRX_POWER_MODE_13) || \ + (mode == DRX_POWER_MODE_14) || \ + (mode == DRX_POWER_MODE_15) || \ + (mode == DRX_POWER_MODE_16) || \ + (mode == DRX_POWER_DOWN)) + +/* Pin safe mode macro */ +#define DRXJ_PIN_SAFE_MODE 0x0000 +/*============================================================================*/ +/*=== GLOBAL VARIABLEs =======================================================*/ +/*============================================================================*/ +/** +*/ + +/** +* \brief Temporary register definitions. +* (register definitions that are not yet available in register master) +*/ + +/******************************************************************************/ +/* Audio block 0x103 is write only. To avoid shadowing in driver accessing */ +/* RAM adresses directly. This must be READ ONLY to avoid problems. */ +/* Writing to the interface adresses is more than only writing the RAM */ +/* locations */ +/******************************************************************************/ +/** +* \brief RAM location of MODUS registers +*/ +#define AUD_DEM_RAM_MODUS_HI__A 0x10204A3 +#define AUD_DEM_RAM_MODUS_HI__M 0xF000 + +#define AUD_DEM_RAM_MODUS_LO__A 0x10204A4 +#define AUD_DEM_RAM_MODUS_LO__M 0x0FFF + +/** +* \brief RAM location of I2S config registers +*/ +#define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1 +#define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2 + +/** +* \brief RAM location of DCO config registers +*/ +#define AUD_DEM_RAM_DCO_B_HI__A 0x1020461 +#define AUD_DEM_RAM_DCO_B_LO__A 0x1020462 +#define AUD_DEM_RAM_DCO_A_HI__A 0x1020463 +#define AUD_DEM_RAM_DCO_A_LO__A 0x1020464 + +/** +* \brief RAM location of Threshold registers +*/ +#define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A +#define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB +#define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6 + +/** +* \brief RAM location of Carrier Threshold registers +*/ +#define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF +#define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0 + +/** +* \brief FM Matrix register fix +*/ +#ifdef AUD_DEM_WR_FM_MATRIX__A +#undef AUD_DEM_WR_FM_MATRIX__A +#endif +#define AUD_DEM_WR_FM_MATRIX__A 0x105006F + +/*============================================================================*/ +/** +* \brief Defines required for audio +*/ +#define AUD_VOLUME_ZERO_DB 115 +#define AUD_VOLUME_DB_MIN -60 +#define AUD_VOLUME_DB_MAX 12 +#define AUD_CARRIER_STRENGTH_QP_0DB 0x4000 +#define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 421 +#define AUD_MAX_AVC_REF_LEVEL 15 +#define AUD_I2S_FREQUENCY_MAX 48000UL +#define AUD_I2S_FREQUENCY_MIN 12000UL +#define AUD_RDS_ARRAY_SIZE 18 + +/** +* \brief Needed for calculation of prescale feature in AUD +*/ +#ifndef DRX_AUD_MAX_FM_DEVIATION +#define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */ +#endif + +/** +* \brief Needed for calculation of NICAM prescale feature in AUD +*/ +#ifndef DRX_AUD_MAX_NICAM_PRESCALE +#define DRX_AUD_MAX_NICAM_PRESCALE (9) /* dB */ +#endif + +/*============================================================================*/ +/* Values for I2S Master/Slave pin configurations */ +#define SIO_PDR_I2S_CL_CFG_MODE__MASTER 0x0004 +#define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER 0x0008 +#define SIO_PDR_I2S_CL_CFG_MODE__SLAVE 0x0004 +#define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE 0x0000 + +#define SIO_PDR_I2S_DA_CFG_MODE__MASTER 0x0003 +#define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER 0x0008 +#define SIO_PDR_I2S_DA_CFG_MODE__SLAVE 0x0003 +#define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE 0x0008 + +#define SIO_PDR_I2S_WS_CFG_MODE__MASTER 0x0004 +#define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER 0x0008 +#define SIO_PDR_I2S_WS_CFG_MODE__SLAVE 0x0004 +#define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE 0x0000 + +/*============================================================================*/ +/*=== REGISTER ACCESS MACROS =================================================*/ +/*============================================================================*/ + +/** +* This macro is used to create byte arrays for block writes. +* Block writes speed up I2C traffic between host and demod. +* The macro takes care of the required byte order in a 16 bits word. +* x -> lowbyte(x), highbyte(x) +*/ +#define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ + ((u8)((((u16)x)>>8)&0xFF)) +/** +* This macro is used to convert byte array to 16 bit register value for block read. +* Block read speed up I2C traffic between host and demod. +* The macro takes care of the required byte order in a 16 bits word. +*/ +#define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8))) + +/*============================================================================*/ +/*=== MISC DEFINES ===========================================================*/ +/*============================================================================*/ + +/*============================================================================*/ +/*=== HI COMMAND RELATED DEFINES =============================================*/ +/*============================================================================*/ + +/** +* \brief General maximum number of retries for ucode command interfaces +*/ +#define DRXJ_MAX_RETRIES (100) + +/*============================================================================*/ +/*=== STANDARD RELATED MACROS ================================================*/ +/*============================================================================*/ + +#define DRXJ_ISATVSTD(std) ((std == DRX_STANDARD_PAL_SECAM_BG) || \ + (std == DRX_STANDARD_PAL_SECAM_DK) || \ + (std == DRX_STANDARD_PAL_SECAM_I) || \ + (std == DRX_STANDARD_PAL_SECAM_L) || \ + (std == DRX_STANDARD_PAL_SECAM_LP) || \ + (std == DRX_STANDARD_NTSC) || \ + (std == DRX_STANDARD_FM)) + +#define DRXJ_ISQAMSTD(std) ((std == DRX_STANDARD_ITU_A) || \ + (std == DRX_STANDARD_ITU_B) || \ + (std == DRX_STANDARD_ITU_C) || \ + (std == DRX_STANDARD_ITU_D)) + +/*----------------------------------------------------------------------------- +GLOBAL VARIABLES +----------------------------------------------------------------------------*/ +/* + * DRXJ DAP structures + */ + +static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, + u32 addr, + u16 datasize, + u8 *data, u32 flags); + + +static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, + u32 waddr, + u32 raddr, + u16 wdata, u16 *rdata); + +static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 *data, u32 flags); + +static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, + u32 addr, + u32 *data, u32 flags); + +static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, + u32 addr, + u16 datasize, + u8 *data, u32 flags); + +static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 data, u32 flags); + +static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, + u32 addr, + u32 data, u32 flags); + +static struct drxj_data drxj_data_g = { + false, /* has_lna : true if LNA (aka PGA) present */ + false, /* has_oob : true if OOB supported */ + false, /* has_ntsc: true if NTSC supported */ + false, /* has_btsc: true if BTSC supported */ + false, /* has_smatx: true if SMA_TX pin is available */ + false, /* has_smarx: true if SMA_RX pin is available */ + false, /* has_gpio : true if GPIO pin is available */ + false, /* has_irqn : true if IRQN pin is available */ + 0, /* mfx A1/A2/A... */ + + /* tuner settings */ + false, /* tuner mirrors RF signal */ + /* standard/channel settings */ + DRX_STANDARD_UNKNOWN, /* current standard */ + DRX_CONSTELLATION_AUTO, /* constellation */ + 0, /* frequency in KHz */ + DRX_BANDWIDTH_UNKNOWN, /* curr_bandwidth */ + DRX_MIRROR_NO, /* mirror */ + + /* signal quality information: */ + /* default values taken from the QAM Programming guide */ + /* fec_bits_desired should not be less than 4000000 */ + 4000000, /* fec_bits_desired */ + 5, /* fec_vd_plen */ + 4, /* qam_vd_prescale */ + 0xFFFF, /* qamVDPeriod */ + 204 * 8, /* fec_rs_plen annex A */ + 1, /* fec_rs_prescale */ + FEC_RS_MEASUREMENT_PERIOD, /* fec_rs_period */ + true, /* reset_pkt_err_acc */ + 0, /* pkt_err_acc_start */ + + /* HI configuration */ + 0, /* hi_cfg_timing_div */ + 0, /* hi_cfg_bridge_delay */ + 0, /* hi_cfg_wake_up_key */ + 0, /* hi_cfg_ctrl */ + 0, /* HICfgTimeout */ + /* UIO configuartion */ + DRX_UIO_MODE_DISABLE, /* uio_sma_rx_mode */ + DRX_UIO_MODE_DISABLE, /* uio_sma_tx_mode */ + DRX_UIO_MODE_DISABLE, /* uioASELMode */ + DRX_UIO_MODE_DISABLE, /* uio_irqn_mode */ + /* FS setting */ + 0UL, /* iqm_fs_rate_ofs */ + false, /* pos_image */ + /* RC setting */ + 0UL, /* iqm_rc_rate_ofs */ + /* AUD information */ +/* false, * flagSetAUDdone */ +/* false, * detectedRDS */ +/* true, * flagASDRequest */ +/* false, * flagHDevClear */ +/* false, * flagHDevSet */ +/* (u16) 0xFFF, * rdsLastCount */ + + /* ATV configuartion */ + 0UL, /* flags cfg changes */ + /* shadow of ATV_TOP_EQU0__A */ + {-5, + ATV_TOP_EQU0_EQU_C0_FM, + ATV_TOP_EQU0_EQU_C0_L, + ATV_TOP_EQU0_EQU_C0_LP, + ATV_TOP_EQU0_EQU_C0_BG, + ATV_TOP_EQU0_EQU_C0_DK, + ATV_TOP_EQU0_EQU_C0_I}, + /* shadow of ATV_TOP_EQU1__A */ + {-50, + ATV_TOP_EQU1_EQU_C1_FM, + ATV_TOP_EQU1_EQU_C1_L, + ATV_TOP_EQU1_EQU_C1_LP, + ATV_TOP_EQU1_EQU_C1_BG, + ATV_TOP_EQU1_EQU_C1_DK, + ATV_TOP_EQU1_EQU_C1_I}, + /* shadow of ATV_TOP_EQU2__A */ + {210, + ATV_TOP_EQU2_EQU_C2_FM, + ATV_TOP_EQU2_EQU_C2_L, + ATV_TOP_EQU2_EQU_C2_LP, + ATV_TOP_EQU2_EQU_C2_BG, + ATV_TOP_EQU2_EQU_C2_DK, + ATV_TOP_EQU2_EQU_C2_I}, + /* shadow of ATV_TOP_EQU3__A */ + {-160, + ATV_TOP_EQU3_EQU_C3_FM, + ATV_TOP_EQU3_EQU_C3_L, + ATV_TOP_EQU3_EQU_C3_LP, + ATV_TOP_EQU3_EQU_C3_BG, + ATV_TOP_EQU3_EQU_C3_DK, + ATV_TOP_EQU3_EQU_C3_I}, + false, /* flag: true=bypass */ + ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */ + ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */ + true, /* flag CVBS ouput enable */ + false, /* flag SIF ouput enable */ + DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */ + { /* qam_rf_agc_cfg */ + DRX_STANDARD_ITU_B, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level */ + 0xFFFF, /* max_output_level */ + 0x0000, /* speed */ + 0x0000, /* top */ + 0x0000 /* c.o.c. */ + }, + { /* qam_if_agc_cfg */ + DRX_STANDARD_ITU_B, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level */ + 0xFFFF, /* max_output_level */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + { /* vsb_rf_agc_cfg */ + DRX_STANDARD_8VSB, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level */ + 0xFFFF, /* max_output_level */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + { /* vsb_if_agc_cfg */ + DRX_STANDARD_8VSB, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level */ + 0xFFFF, /* max_output_level */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + 0, /* qam_pga_cfg */ + 0, /* vsb_pga_cfg */ + { /* qam_pre_saw_cfg */ + DRX_STANDARD_ITU_B, /* standard */ + 0, /* reference */ + false /* use_pre_saw */ + }, + { /* vsb_pre_saw_cfg */ + DRX_STANDARD_8VSB, /* standard */ + 0, /* reference */ + false /* use_pre_saw */ + }, + + /* Version information */ +#ifndef _CH_ + { + "01234567890", /* human readable version microcode */ + "01234567890" /* human readable version device specific code */ + }, + { + { /* struct drx_version for microcode */ + DRX_MODULE_UNKNOWN, + (char *)(NULL), + 0, + 0, + 0, + (char *)(NULL) + }, + { /* struct drx_version for device specific code */ + DRX_MODULE_UNKNOWN, + (char *)(NULL), + 0, + 0, + 0, + (char *)(NULL) + } + }, + { + { /* struct drx_version_list for microcode */ + (struct drx_version *) (NULL), + (struct drx_version_list *) (NULL) + }, + { /* struct drx_version_list for device specific code */ + (struct drx_version *) (NULL), + (struct drx_version_list *) (NULL) + } + }, +#endif + false, /* smart_ant_inverted */ + /* Tracking filter setting for OOB */ + { + 12000, + 9300, + 6600, + 5280, + 3700, + 3000, + 2000, + 0}, + false, /* oob_power_on */ + 0, /* mpeg_ts_static_bitrate */ + false, /* disable_te_ihandling */ + false, /* bit_reverse_mpeg_outout */ + DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpeg_output_clock_rate */ + DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpeg_start_width */ + + /* Pre SAW & Agc configuration for ATV */ + { + DRX_STANDARD_NTSC, /* standard */ + 7, /* reference */ + true /* use_pre_saw */ + }, + { /* ATV RF-AGC */ + DRX_STANDARD_NTSC, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level (d.c.) */ + 0, /* max_output_level (d.c.) */ + 3, /* speed */ + 9500, /* top */ + 4000 /* cut-off current */ + }, + { /* ATV IF-AGC */ + DRX_STANDARD_NTSC, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level (d.c.) */ + 0, /* max_output_level (d.c.) */ + 3, /* speed */ + 2400, /* top */ + 0 /* c.o.c. (d.c.) */ + }, + 140, /* ATV PGA config */ + 0, /* curr_symbol_rate */ + + false, /* pdr_safe_mode */ + SIO_PDR_GPIO_CFG__PRE, /* pdr_safe_restore_val_gpio */ + SIO_PDR_VSYNC_CFG__PRE, /* pdr_safe_restore_val_v_sync */ + SIO_PDR_SMA_RX_CFG__PRE, /* pdr_safe_restore_val_sma_rx */ + SIO_PDR_SMA_TX_CFG__PRE, /* pdr_safe_restore_val_sma_tx */ + + 4, /* oob_pre_saw */ + DRXJ_OOB_LO_POW_MINUS10DB, /* oob_lo_pow */ + { + false /* aud_data, only first member */ + }, +}; + +/** +* \var drxj_default_addr_g +* \brief Default I2C address and device identifier. +*/ +static struct i2c_device_addr drxj_default_addr_g = { + DRXJ_DEF_I2C_ADDR, /* i2c address */ + DRXJ_DEF_DEMOD_DEV_ID /* device id */ +}; + +/** +* \var drxj_default_comm_attr_g +* \brief Default common attributes of a drxj demodulator instance. +*/ +static struct drx_common_attr drxj_default_comm_attr_g = { + NULL, /* ucode file */ + true, /* ucode verify switch */ + {0}, /* version record */ + + 44000, /* IF in kHz in case no tuner instance is used */ + (151875 - 0), /* system clock frequency in kHz */ + 0, /* oscillator frequency kHz */ + 0, /* oscillator deviation in ppm, signed */ + false, /* If true mirror frequency spectrum */ + { + /* MPEG output configuration */ + true, /* If true, enable MPEG ouput */ + false, /* If true, insert RS byte */ + false, /* If true, parallel out otherwise serial */ + false, /* If true, invert DATA signals */ + false, /* If true, invert ERR signal */ + false, /* If true, invert STR signals */ + false, /* If true, invert VAL signals */ + false, /* If true, invert CLK signals */ + true, /* If true, static MPEG clockrate will + be used, otherwise clockrate will + adapt to the bitrate of the TS */ + 19392658UL, /* Maximum bitrate in b/s in case + static clockrate is selected */ + DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */ + }, + /* Initilisations below can be ommited, they require no user input and + are initialy 0, NULL or false. The compiler will initialize them to these + values when ommited. */ + false, /* is_opened */ + + /* SCAN */ + NULL, /* no scan params yet */ + 0, /* current scan index */ + 0, /* next scan frequency */ + false, /* scan ready flag */ + 0, /* max channels to scan */ + 0, /* nr of channels scanned */ + NULL, /* default scan function */ + NULL, /* default context pointer */ + 0, /* millisec to wait for demod lock */ + DRXJ_DEMOD_LOCK, /* desired lock */ + false, + + /* Power management */ + DRX_POWER_UP, + + /* Tuner */ + 1, /* nr of I2C port to wich tuner is */ + 0L, /* minimum RF input frequency, in kHz */ + 0L, /* maximum RF input frequency, in kHz */ + false, /* Rf Agc Polarity */ + false, /* If Agc Polarity */ + false, /* tuner slow mode */ + + { /* current channel (all 0) */ + 0UL /* channel.frequency */ + }, + DRX_STANDARD_UNKNOWN, /* current standard */ + DRX_STANDARD_UNKNOWN, /* previous standard */ + DRX_STANDARD_UNKNOWN, /* di_cache_standard */ + false, /* use_bootloader */ + 0UL, /* capabilities */ + 0 /* mfx */ +}; + +/** +* \var drxj_default_demod_g +* \brief Default drxj demodulator instance. +*/ +static struct drx_demod_instance drxj_default_demod_g = { + &drxj_default_addr_g, /* i2c address & device id */ + &drxj_default_comm_attr_g, /* demod common attributes */ + &drxj_data_g /* demod device specific attributes */ +}; + +/** +* \brief Default audio data structure for DRK demodulator instance. +* +* This structure is DRXK specific. +* +*/ +static struct drx_aud_data drxj_default_aud_data_g = { + false, /* audio_is_active */ + DRX_AUD_STANDARD_AUTO, /* audio_standard */ + + /* i2sdata */ + { + false, /* output_enable */ + 48000, /* frequency */ + DRX_I2S_MODE_MASTER, /* mode */ + DRX_I2S_WORDLENGTH_32, /* word_length */ + DRX_I2S_POLARITY_RIGHT, /* polarity */ + DRX_I2S_FORMAT_WS_WITH_DATA /* format */ + }, + /* volume */ + { + true, /* mute; */ + 0, /* volume */ + DRX_AUD_AVC_OFF, /* avc_mode */ + 0, /* avc_ref_level */ + DRX_AUD_AVC_MAX_GAIN_12DB, /* avc_max_gain */ + DRX_AUD_AVC_MAX_ATTEN_24DB, /* avc_max_atten */ + 0, /* strength_left */ + 0 /* strength_right */ + }, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, /* auto_sound */ + /* ass_thresholds */ + { + 440, /* A2 */ + 12, /* BTSC */ + 700, /* NICAM */ + }, + /* carrier */ + { + /* a */ + { + 42, /* thres */ + DRX_NO_CARRIER_NOISE, /* opt */ + 0, /* shift */ + 0 /* dco */ + }, + /* b */ + { + 42, /* thres */ + DRX_NO_CARRIER_MUTE, /* opt */ + 0, /* shift */ + 0 /* dco */ + }, + + }, + /* mixer */ + { + DRX_AUD_SRC_STEREO_OR_A, /* source_i2s */ + DRX_AUD_I2S_MATRIX_STEREO, /* matrix_i2s */ + DRX_AUD_FM_MATRIX_SOUND_A /* matrix_fm */ + }, + DRX_AUD_DEVIATION_NORMAL, /* deviation */ + DRX_AUD_AVSYNC_OFF, /* av_sync */ + + /* prescale */ + { + DRX_AUD_MAX_FM_DEVIATION, /* fm_deviation */ + DRX_AUD_MAX_NICAM_PRESCALE /* nicam_gain */ + }, + DRX_AUD_FM_DEEMPH_75US, /* deemph */ + DRX_BTSC_STEREO, /* btsc_detect */ + 0, /* rds_data_counter */ + false /* rds_data_present */ +}; + +/*----------------------------------------------------------------------------- +STRUCTURES +----------------------------------------------------------------------------*/ +struct drxjeq_stat { + u16 eq_mse; + u8 eq_mode; + u8 eq_ctrl; + u8 eq_stat; +}; + +/* HI command */ +struct drxj_hi_cmd { + u16 cmd; + u16 param1; + u16 param2; + u16 param3; + u16 param4; + u16 param5; + u16 param6; +}; + +/*============================================================================*/ +/*=== MICROCODE RELATED STRUCTURES ===========================================*/ +/*============================================================================*/ + +/** + * struct drxu_code_block_hdr - Structure of the microcode block headers + * + * @addr: Destination address of the data in this block + * @size: Size of the block data following this header counted in + * 16 bits words + * @CRC: CRC value of the data block, only valid if CRC flag is + * set. + */ +struct drxu_code_block_hdr { + u32 addr; + u16 size; + u16 flags; + u16 CRC; +}; + +/*----------------------------------------------------------------------------- +FUNCTIONS +----------------------------------------------------------------------------*/ +/* Some prototypes */ +static int +hi_command(struct i2c_device_addr *dev_addr, + const struct drxj_hi_cmd *cmd, u16 *result); + +static int +ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat); + +static int +ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode); + +static int power_down_aud(struct drx_demod_instance *demod); + +static int +ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw); + +static int +ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain); + +/*============================================================================*/ +/*============================================================================*/ +/*== HELPER FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + + +/*============================================================================*/ + +/* +* \fn u32 frac28(u32 N, u32 D) +* \brief Compute: (1<<28)*N/D +* \param N 32 bits +* \param D 32 bits +* \return (1<<28)*N/D +* This function is used to avoid floating-point calculations as they may +* not be present on the target platform. + +* frac28 performs an unsigned 28/28 bits division to 32-bit fixed point +* fraction used for setting the Frequency Shifter registers. +* N and D can hold numbers up to width: 28-bits. +* The 4 bits integer part and the 28 bits fractional part are calculated. + +* Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999 + +* N: 0...(1<<28)-1 = 268435454 +* D: 0...(1<<28)-1 +* Q: 0...(1<<32)-1 +*/ +static u32 frac28(u32 N, u32 D) +{ + int i = 0; + u32 Q1 = 0; + u32 R0 = 0; + + R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */ + Q1 = N / D; /* integer part, only the 4 least significant bits + will be visible in the result */ + + /* division using radix 16, 7 nibbles in the result */ + for (i = 0; i < 7; i++) { + Q1 = (Q1 << 4) | R0 / D; + R0 = (R0 % D) << 4; + } + /* rounding */ + if ((R0 >> 3) >= D) + Q1++; + + return Q1; +} + +/** +* \fn u32 log1_times100( u32 x) +* \brief Compute: 100*log10(x) +* \param x 32 bits +* \return 100*log10(x) +* +* 100*log10(x) +* = 100*(log2(x)/log2(10))) +* = (100*(2^15)*log2(x))/((2^15)*log2(10)) +* = ((200*(2^15)*log2(x))/((2^15)*log2(10)))/2 +* = ((200*(2^15)*(log2(x/y)+log2(y)))/((2^15)*log2(10)))/2 +* = ((200*(2^15)*log2(x/y))+(200*(2^15)*log2(y)))/((2^15)*log2(10)))/2 +* +* where y = 2^k and 1<= (x/y) < 2 +*/ + +static u32 log1_times100(u32 x) +{ + static const u8 scale = 15; + static const u8 index_width = 5; + /* + log2lut[n] = (1<<scale) * 200 * log2( 1.0 + ( (1.0/(1<<INDEXWIDTH)) * n )) + 0 <= n < ((1<<INDEXWIDTH)+1) + */ + + static const u32 log2lut[] = { + 0, /* 0.000000 */ + 290941, /* 290941.300628 */ + 573196, /* 573196.476418 */ + 847269, /* 847269.179851 */ + 1113620, /* 1113620.489452 */ + 1372674, /* 1372673.576986 */ + 1624818, /* 1624817.752104 */ + 1870412, /* 1870411.981536 */ + 2109788, /* 2109787.962654 */ + 2343253, /* 2343252.817465 */ + 2571091, /* 2571091.461923 */ + 2793569, /* 2793568.696416 */ + 3010931, /* 3010931.055901 */ + 3223408, /* 3223408.452106 */ + 3431216, /* 3431215.635215 */ + 3634553, /* 3634553.498355 */ + 3833610, /* 3833610.244726 */ + 4028562, /* 4028562.434393 */ + 4219576, /* 4219575.925308 */ + 4406807, /* 4406806.721144 */ + 4590402, /* 4590401.736809 */ + 4770499, /* 4770499.491025 */ + 4947231, /* 4947230.734179 */ + 5120719, /* 5120719.018555 */ + 5291081, /* 5291081.217197 */ + 5458428, /* 5458427.996830 */ + 5622864, /* 5622864.249668 */ + 5784489, /* 5784489.488298 */ + 5943398, /* 5943398.207380 */ + 6099680, /* 6099680.215452 */ + 6253421, /* 6253420.939751 */ + 6404702, /* 6404701.706649 */ + 6553600, /* 6553600.000000 */ + }; + + u8 i = 0; + u32 y = 0; + u32 d = 0; + u32 k = 0; + u32 r = 0; + + if (x == 0) + return 0; + + /* Scale x (normalize) */ + /* computing y in log(x/y) = log(x) - log(y) */ + if ((x & (((u32) (-1)) << (scale + 1))) == 0) { + for (k = scale; k > 0; k--) { + if (x & (((u32) 1) << scale)) + break; + x <<= 1; + } + } else { + for (k = scale; k < 31; k++) { + if ((x & (((u32) (-1)) << (scale + 1))) == 0) + break; + x >>= 1; + } + } + /* + Now x has binary point between bit[scale] and bit[scale-1] + and 1.0 <= x < 2.0 */ + + /* correction for divison: log(x) = log(x/y)+log(y) */ + y = k * ((((u32) 1) << scale) * 200); + + /* remove integer part */ + x &= ((((u32) 1) << scale) - 1); + /* get index */ + i = (u8) (x >> (scale - index_width)); + /* compute delta (x-a) */ + d = x & ((((u32) 1) << (scale - index_width)) - 1); + /* compute log, multiplication ( d* (.. )) must be within range ! */ + y += log2lut[i] + + ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width)); + /* Conver to log10() */ + y /= 108853; /* (log2(10) << scale) */ + r = (y >> 1); + /* rounding */ + if (y & ((u32)1)) + r++; + + return r; + +} + +/** +* \fn u32 frac_times1e6( u16 N, u32 D) +* \brief Compute: (N/D) * 1000000. +* \param N nominator 16-bits. +* \param D denominator 32-bits. +* \return u32 +* \retval ((N/D) * 1000000), 32 bits +* +* No check on D=0! +*/ +static u32 frac_times1e6(u32 N, u32 D) +{ + u32 remainder = 0; + u32 frac = 0; + + /* + frac = (N * 1000000) / D + To let it fit in a 32 bits computation: + frac = (N * (1000000 >> 4)) / (D >> 4) + This would result in a problem in case D < 16 (div by 0). + So we do it more elaborate as shown below. + */ + frac = (((u32) N) * (1000000 >> 4)) / D; + frac <<= 4; + remainder = (((u32) N) * (1000000 >> 4)) % D; + remainder <<= 4; + frac += remainder / D; + remainder = remainder % D; + if ((remainder * 2) > D) + frac++; + + return frac; +} + +/*============================================================================*/ + + +/** +* \brief Values for NICAM prescaler gain. Computed from dB to integer +* and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20). +* +*/ +static const u16 nicam_presc_table_val[43] = { + 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, + 5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16, + 18, 20, 23, 25, 28, 32, 36, 40, 45, + 51, 57, 64, 71, 80, 90, 101, 113, 127 +}; + +/*============================================================================*/ +/*== END HELPER FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== DRXJ DAP FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/* + This layer takes care of some device specific register access protocols: + -conversion to short address format + -access to audio block + This layer is placed between the drx_dap_fasi and the rest of the drxj + specific implementation. This layer can use address map knowledge whereas + dap_fasi may not use memory map knowledge. + + * For audio currently only 16 bits read and write register access is + supported. More is not needed. RMW and 32 or 8 bit access on audio + registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast + single/multi master) will be ignored. + + TODO: check ignoring single/multimaster is ok for AUD access ? +*/ + +#define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false) +#define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */ +/*============================================================================*/ + +/** +* \fn bool is_handled_by_aud_tr_if( u32 addr ) +* \brief Check if this address is handled by the audio token ring interface. +* \param addr +* \return bool +* \retval true Yes, handled by audio token ring interface +* \retval false No, not handled by audio token ring interface +* +*/ +static +bool is_handled_by_aud_tr_if(u32 addr) +{ + bool retval = false; + + if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) && + (DRXDAP_FASI_ADDR2BANK(addr) > 1) && + (DRXDAP_FASI_ADDR2BANK(addr) < 6)) { + retval = true; + } + + return retval; +} + +/*============================================================================*/ + +int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, + u16 w_count, + u8 *wData, + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data) +{ + struct drx39xxj_state *state; + struct i2c_msg msg[2]; + unsigned int num_msgs; + + if (w_dev_addr == NULL) { + /* Read only */ + state = r_dev_addr->user_data; + msg[0].addr = r_dev_addr->i2c_addr >> 1; + msg[0].flags = I2C_M_RD; + msg[0].buf = r_data; + msg[0].len = r_count; + num_msgs = 1; + } else if (r_dev_addr == NULL) { + /* Write only */ + state = w_dev_addr->user_data; + msg[0].addr = w_dev_addr->i2c_addr >> 1; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = w_count; + num_msgs = 1; + } else { + /* Both write and read */ + state = w_dev_addr->user_data; + msg[0].addr = w_dev_addr->i2c_addr >> 1; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = w_count; + msg[1].addr = r_dev_addr->i2c_addr >> 1; + msg[1].flags = I2C_M_RD; + msg[1].buf = r_data; + msg[1].len = r_count; + num_msgs = 2; + } + + if (state->i2c == NULL) { + pr_err("i2c was zero, aborting\n"); + return 0; + } + if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { + pr_warn("drx3933: I2C write/read failed\n"); + return -EREMOTEIO; + } + +#ifdef DJH_DEBUG + if (w_dev_addr == NULL || r_dev_addr == NULL) + return 0; + + state = w_dev_addr->user_data; + + if (state->i2c == NULL) + return 0; + + msg[0].addr = w_dev_addr->i2c_addr; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = w_count; + msg[1].addr = r_dev_addr->i2c_addr; + msg[1].flags = I2C_M_RD; + msg[1].buf = r_data; + msg[1].len = r_count; + num_msgs = 2; + + pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", + w_dev_addr->i2c_addr, state->i2c, w_count, r_count); + + if (i2c_transfer(state->i2c, msg, 2) != 2) { + pr_warn("drx3933: I2C write/read failed\n"); + return -EREMOTEIO; + } +#endif + return 0; +} + +/*============================================================================*/ + +/****************************** +* +* int drxdap_fasi_read_block ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u16 datasize, -- number of bytes to read +* u8 *data, -- data to receive +* u32 flags) -- special device flags +* +* Read block data from chip address. Because the chip is word oriented, +* the number of bytes to read must be even. +* +* Make sure that the buffer to receive the data is large enough. +* +* Although this function expects an even number of bytes, it is still byte +* oriented, and the data read back is NOT translated to the endianness of +* the target platform. +* +* Output: +* - 0 if reading was successful +* in that case: data read is in *data. +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, + u32 addr, + u16 datasize, + u8 *data, u32 flags) +{ + u8 buf[4]; + u16 bufx; + int rc; + u16 overhead_size = 0; + + /* Check parameters ******************************************************* */ + if (dev_addr == NULL) + return -EINVAL; + + overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); + + if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || + ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && + DRXDAP_FASI_LONG_FORMAT(addr)) || + (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || + ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { + return -EINVAL; + } + + /* ReadModifyWrite & mode flag bits are not allowed */ + flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS); +#if DRXDAP_SINGLE_MASTER + flags |= DRXDAP_FASI_SINGLE_MASTER; +#endif + + /* Read block from I2C **************************************************** */ + do { + u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ? + datasize : DRXDAP_MAX_RCHUNKSIZE); + + bufx = 0; + + addr &= ~DRXDAP_FASI_FLAGS; + addr |= flags; + +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) + /* short format address preferred but long format otherwise */ + if (DRXDAP_FASI_LONG_FORMAT(addr)) { +#endif +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) + buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); + buf[bufx++] = (u8) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8) ((addr >> 7) & 0xFF); +#endif +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) + } else { +#endif +#if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) + buf[bufx++] = (u8) ((addr << 1) & 0xFF); + buf[bufx++] = + (u8) (((addr >> 16) & 0x0F) | + ((addr >> 18) & 0xF0)); +#endif +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) + } +#endif + +#if DRXDAP_SINGLE_MASTER + /* + * In single master mode, split the read and write actions. + * No special action is needed for write chunks here. + */ + rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, + NULL, 0, NULL); + if (rc == 0) + rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data); +#else + /* In multi master mode, do everything in one RW action */ + rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo, + data); +#endif + data += todo; + addr += (todo >> 1); + datasize -= todo; + } while (datasize && rc == 0); + + return rc; +} + + +/****************************** +* +* int drxdap_fasi_read_reg16 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u16 *data, -- data to receive +* u32 flags) -- special device flags +* +* Read one 16-bit register or memory location. The data received back is +* converted back to the target platform's endianness. +* +* Output: +* - 0 if reading was successful +* in that case: read data is at *data +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 *data, u32 flags) +{ + u8 buf[sizeof(*data)]; + int rc; + + if (!data) + return -EINVAL; + + rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); + *data = buf[0] + (((u16) buf[1]) << 8); + return rc; +} + +/****************************** +* +* int drxdap_fasi_read_reg32 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u32 *data, -- data to receive +* u32 flags) -- special device flags +* +* Read one 32-bit register or memory location. The data received back is +* converted back to the target platform's endianness. +* +* Output: +* - 0 if reading was successful +* in that case: read data is at *data +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, + u32 addr, + u32 *data, u32 flags) +{ + u8 buf[sizeof(*data)]; + int rc; + + if (!data) + return -EINVAL; + + rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); + *data = (((u32) buf[0]) << 0) + + (((u32) buf[1]) << 8) + + (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24); + return rc; +} + +/****************************** +* +* int drxdap_fasi_write_block ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u16 datasize, -- number of bytes to read +* u8 *data, -- data to receive +* u32 flags) -- special device flags +* +* Write block data to chip address. Because the chip is word oriented, +* the number of bytes to write must be even. +* +* Although this function expects an even number of bytes, it is still byte +* oriented, and the data being written is NOT translated from the endianness of +* the target platform. +* +* Output: +* - 0 if writing was successful +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, + u32 addr, + u16 datasize, + u8 *data, u32 flags) +{ + u8 buf[DRXDAP_MAX_WCHUNKSIZE]; + int st = -EIO; + int first_err = 0; + u16 overhead_size = 0; + u16 block_size = 0; + + /* Check parameters ******************************************************* */ + if (dev_addr == NULL) + return -EINVAL; + + overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); + + if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || + ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && + DRXDAP_FASI_LONG_FORMAT(addr)) || + (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || + ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) + return -EINVAL; + + flags &= DRXDAP_FASI_FLAGS; + flags &= ~DRXDAP_FASI_MODEFLAGS; +#if DRXDAP_SINGLE_MASTER + flags |= DRXDAP_FASI_SINGLE_MASTER; +#endif + + /* Write block to I2C ***************************************************** */ + block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1; + do { + u16 todo = 0; + u16 bufx = 0; + + /* Buffer device address */ + addr &= ~DRXDAP_FASI_FLAGS; + addr |= flags; +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) + /* short format address preferred but long format otherwise */ + if (DRXDAP_FASI_LONG_FORMAT(addr)) { +#endif +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) + buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); + buf[bufx++] = (u8) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8) ((addr >> 7) & 0xFF); +#endif +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) + } else { +#endif +#if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) + buf[bufx++] = (u8) ((addr << 1) & 0xFF); + buf[bufx++] = + (u8) (((addr >> 16) & 0x0F) | + ((addr >> 18) & 0xF0)); +#endif +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) + } +#endif + + /* + In single master mode block_size can be 0. In such a case this I2C + sequense will be visible: (1) write address {i2c addr, + 4 bytes chip address} (2) write data {i2c addr, 4 bytes data } + (3) write address (4) write data etc... + Addres must be rewriten because HI is reset after data transport and + expects an address. + */ + todo = (block_size < datasize ? block_size : datasize); + if (todo == 0) { + u16 overhead_size_i2c_addr = 0; + u16 data_block_size = 0; + + overhead_size_i2c_addr = + (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1); + data_block_size = + (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1; + + /* write device address */ + st = drxbsp_i2c_write_read(dev_addr, + (u16) (bufx), + buf, + (struct i2c_device_addr *)(NULL), + 0, (u8 *)(NULL)); + + if ((st != 0) && (first_err == 0)) { + /* at the end, return the first error encountered */ + first_err = st; + } + bufx = 0; + todo = + (data_block_size < + datasize ? data_block_size : datasize); + } + memcpy(&buf[bufx], data, todo); + /* write (address if can do and) data */ + st = drxbsp_i2c_write_read(dev_addr, + (u16) (bufx + todo), + buf, + (struct i2c_device_addr *)(NULL), + 0, (u8 *)(NULL)); + + if ((st != 0) && (first_err == 0)) { + /* at the end, return the first error encountered */ + first_err = st; + } + datasize -= todo; + data += todo; + addr += (todo >> 1); + } while (datasize); + + return first_err; +} + +/****************************** +* +* int drxdap_fasi_write_reg16 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u16 data, -- data to send +* u32 flags) -- special device flags +* +* Write one 16-bit register or memory location. The data being written is +* converted from the target platform's endianness to little endian. +* +* Output: +* - 0 if writing was successful +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 data, u32 flags) +{ + u8 buf[sizeof(data)]; + + buf[0] = (u8) ((data >> 0) & 0xFF); + buf[1] = (u8) ((data >> 8) & 0xFF); + + return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); +} + +/****************************** +* +* int drxdap_fasi_read_modify_write_reg16 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 waddr, -- address of chip register/memory +* u32 raddr, -- chip address to read back from +* u16 wdata, -- data to send +* u16 *rdata) -- data to receive back +* +* Write 16-bit data, then read back the original contents of that location. +* Requires long addressing format to be allowed. +* +* Before sending data, the data is converted to little endian. The +* data received back is converted back to the target platform's endianness. +* +* WARNING: This function is only guaranteed to work if there is one +* master on the I2C bus. +* +* Output: +* - 0 if reading was successful +* in that case: read back data is at *rdata +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, + u32 waddr, + u32 raddr, + u16 wdata, u16 *rdata) +{ + int rc = -EIO; + +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) + if (rdata == NULL) + return -EINVAL; + + rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); + if (rc == 0) + rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0); +#endif + + return rc; +} + +/****************************** +* +* int drxdap_fasi_write_reg32 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u32 data, -- data to send +* u32 flags) -- special device flags +* +* Write one 32-bit register or memory location. The data being written is +* converted from the target platform's endianness to little endian. +* +* Output: +* - 0 if writing was successful +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, + u32 addr, + u32 data, u32 flags) +{ + u8 buf[sizeof(data)]; + + buf[0] = (u8) ((data >> 0) & 0xFF); + buf[1] = (u8) ((data >> 8) & 0xFF); + buf[2] = (u8) ((data >> 16) & 0xFF); + buf[3] = (u8) ((data >> 24) & 0xFF); + + return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); +} + +/*============================================================================*/ + +/** +* \fn int drxj_dap_rm_write_reg16short +* \brief Read modify write 16 bits audio register using short format only. +* \param dev_addr +* \param waddr Address to write to +* \param raddr Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A) +* \param wdata Data to write +* \param rdata Buffer for data to read +* \return int +* \retval 0 Succes +* \retval -EIO Timeout, I2C error, illegal bank +* +* 16 bits register read modify write access using short addressing format only. +* Requires knowledge of the registermap, thus device dependent. +* Using DAP FASI directly to avoid endless recursion of RMWs to audio registers. +* +*/ + +/* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) + See comments drxj_dap_read_modify_write_reg16 */ +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0) +static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr, + u32 waddr, + u32 raddr, + u16 wdata, u16 *rdata) +{ + int rc; + + if (rdata == NULL) + return -EINVAL; + + /* Set RMW flag */ + rc = drxdap_fasi_write_reg16(dev_addr, + SIO_HI_RA_RAM_S0_FLG_ACC__A, + SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M, + 0x0000); + if (rc == 0) { + /* Write new data: triggers RMW */ + rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, + 0x0000); + } + if (rc == 0) { + /* Read old data */ + rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, + 0x0000); + } + if (rc == 0) { + /* Reset RMW flag */ + rc = drxdap_fasi_write_reg16(dev_addr, + SIO_HI_RA_RAM_S0_FLG_ACC__A, + 0, 0x0000); + } + + return rc; +} +#endif + +/*============================================================================*/ + +static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, + u32 waddr, + u32 raddr, + u16 wdata, u16 *rdata) +{ + /* TODO: correct short/long addressing format decision, + now long format has higher prio then short because short also + needs virt bnks (not impl yet) for certain audio registers */ +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) + return drxdap_fasi_read_modify_write_reg16(dev_addr, + waddr, + raddr, wdata, rdata); +#else + return drxj_dap_rm_write_reg16short(dev_addr, waddr, raddr, wdata, rdata); +#endif +} + + +/*============================================================================*/ + +/** +* \fn int drxj_dap_read_aud_reg16 +* \brief Read 16 bits audio register +* \param dev_addr +* \param addr +* \param data +* \return int +* \retval 0 Succes +* \retval -EIO Timeout, I2C error, illegal bank +* +* 16 bits register read access via audio token ring interface. +* +*/ +static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, + u32 addr, u16 *data) +{ + u32 start_timer = 0; + u32 current_timer = 0; + u32 delta_timer = 0; + u16 tr_status = 0; + int stat = -EIO; + + /* No read possible for bank 3, return with error */ + if (DRXDAP_FASI_ADDR2BANK(addr) == 3) { + stat = -EINVAL; + } else { + const u32 write_bit = ((dr_xaddr_t) 1) << 16; + + /* Force reset write bit */ + addr &= (~write_bit); + + /* Set up read */ + start_timer = jiffies_to_msecs(jiffies); + do { + /* RMW to aud TR IF until request is granted or timeout */ + stat = drxj_dap_read_modify_write_reg16(dev_addr, + addr, + SIO_HI_RA_RAM_S0_RMWBUF__A, + 0x0000, &tr_status); + + if (stat != 0) + break; + + current_timer = jiffies_to_msecs(jiffies); + delta_timer = current_timer - start_timer; + if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { + stat = -EIO; + break; + } + + } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) == + AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) || + ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) == + AUD_TOP_TR_CTR_FIFO_FULL_FULL)); + } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */ + + /* Wait for read ready status or timeout */ + if (stat == 0) { + start_timer = jiffies_to_msecs(jiffies); + + while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) != + AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) { + stat = drxj_dap_read_reg16(dev_addr, + AUD_TOP_TR_CTR__A, + &tr_status, 0x0000); + if (stat != 0) + break; + + current_timer = jiffies_to_msecs(jiffies); + delta_timer = current_timer - start_timer; + if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { + stat = -EIO; + break; + } + } /* while ( ... ) */ + } + + /* Read value */ + if (stat == 0) + stat = drxj_dap_read_modify_write_reg16(dev_addr, + AUD_TOP_TR_RD_REG__A, + SIO_HI_RA_RAM_S0_RMWBUF__A, + 0x0000, data); + return stat; +} + +/*============================================================================*/ + +static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 *data, u32 flags) +{ + int stat = -EIO; + + /* Check param */ + if ((dev_addr == NULL) || (data == NULL)) + return -EINVAL; + + if (is_handled_by_aud_tr_if(addr)) + stat = drxj_dap_read_aud_reg16(dev_addr, addr, data); + else + stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags); + + return stat; +} +/*============================================================================*/ + +/** +* \fn int drxj_dap_write_aud_reg16 +* \brief Write 16 bits audio register +* \param dev_addr +* \param addr +* \param data +* \return int +* \retval 0 Succes +* \retval -EIO Timeout, I2C error, illegal bank +* +* 16 bits register write access via audio token ring interface. +* +*/ +static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr, + u32 addr, u16 data) +{ + int stat = -EIO; + + /* No write possible for bank 2, return with error */ + if (DRXDAP_FASI_ADDR2BANK(addr) == 2) { + stat = -EINVAL; + } else { + u32 start_timer = 0; + u32 current_timer = 0; + u32 delta_timer = 0; + u16 tr_status = 0; + const u32 write_bit = ((dr_xaddr_t) 1) << 16; + + /* Force write bit */ + addr |= write_bit; + start_timer = jiffies_to_msecs(jiffies); + do { + /* RMW to aud TR IF until request is granted or timeout */ + stat = drxj_dap_read_modify_write_reg16(dev_addr, + addr, + SIO_HI_RA_RAM_S0_RMWBUF__A, + data, &tr_status); + if (stat != 0) + break; + + current_timer = jiffies_to_msecs(jiffies); + delta_timer = current_timer - start_timer; + if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { + stat = -EIO; + break; + } + + } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) == + AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) || + ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) == + AUD_TOP_TR_CTR_FIFO_FULL_FULL)); + + } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */ + + return stat; +} + +/*============================================================================*/ + +static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 data, u32 flags) +{ + int stat = -EIO; + + /* Check param */ + if (dev_addr == NULL) + return -EINVAL; + + if (is_handled_by_aud_tr_if(addr)) + stat = drxj_dap_write_aud_reg16(dev_addr, addr, data); + else + stat = drxdap_fasi_write_reg16(dev_addr, + addr, data, flags); + + return stat; +} + +/*============================================================================*/ + +/* Free data ram in SIO HI */ +#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 +#define SIO_HI_RA_RAM_USR_END__A 0x420060 + +#define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) +#define DRXJ_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) +#define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ +#define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE + +/** +* \fn int drxj_dap_atomic_read_write_block() +* \brief Basic access routine for atomic read or write access +* \param dev_addr pointer to i2c dev address +* \param addr destination/source address +* \param datasize size of data buffer in bytes +* \param data pointer to data buffer +* \return int +* \retval 0 Succes +* \retval -EIO Timeout, I2C error, illegal bank +* +*/ +static +int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, + u32 addr, + u16 datasize, + u8 *data, bool read_flag) +{ + struct drxj_hi_cmd hi_cmd; + int rc; + u16 word; + u16 dummy = 0; + u16 i = 0; + + /* Parameter check */ + if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8)) + return -EINVAL; + + /* Set up HI parameters to read or write n bytes */ + hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY; + hi_cmd.param1 = + (u16) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) + + DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START)); + hi_cmd.param2 = + (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START); + hi_cmd.param3 = (u16) ((datasize / 2) - 1); + if (!read_flag) + hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE; + else + hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ; + hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) + + DRXDAP_FASI_ADDR2BANK(addr)); + hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr); + + if (!read_flag) { + /* write data to buffer */ + for (i = 0; i < (datasize / 2); i++) { + + word = ((u16) data[2 * i]); + word += (((u16) data[(2 * i) + 1]) << 8); + drxj_dap_write_reg16(dev_addr, + (DRXJ_HI_ATOMIC_BUF_START + i), + word, 0); + } + } + + rc = hi_command(dev_addr, &hi_cmd, &dummy); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (read_flag) { + /* read data from buffer */ + for (i = 0; i < (datasize / 2); i++) { + drxj_dap_read_reg16(dev_addr, + (DRXJ_HI_ATOMIC_BUF_START + i), + &word, 0); + data[2 * i] = (u8) (word & 0xFF); + data[(2 * i) + 1] = (u8) (word >> 8); + } + } + + return 0; + +rw_error: + return -EIO; + +} + +/*============================================================================*/ + +/** +* \fn int drxj_dap_atomic_read_reg32() +* \brief Atomic read of 32 bits words +*/ +static +int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr, + u32 addr, + u32 *data, u32 flags) +{ + u8 buf[sizeof(*data)]; + int rc = -EIO; + u32 word = 0; + + if (!data) + return -EINVAL; + + rc = drxj_dap_atomic_read_write_block(dev_addr, addr, + sizeof(*data), buf, true); + + if (rc < 0) + return 0; + + word = (u32) buf[3]; + word <<= 8; + word |= (u32) buf[2]; + word <<= 8; + word |= (u32) buf[1]; + word <<= 8; + word |= (u32) buf[0]; + + *data = word; + + return rc; +} + +/*============================================================================*/ + +/*============================================================================*/ +/*== END DRXJ DAP FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== HOST INTERFACE FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \fn int hi_cfg_command() +* \brief Configure HI with settings stored in the demod structure. +* \param demod Demodulator. +* \return int. +* +* This routine was created because to much orthogonal settings have +* been put into one HI API function (configure). Especially the I2C bridge +* enable/disable should not need re-configuration of the HI. +* +*/ +static int hi_cfg_command(const struct drx_demod_instance *demod) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct drxj_hi_cmd hi_cmd; + u16 result = 0; + int rc; + + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG; + hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; + hi_cmd.param2 = ext_attr->hi_cfg_timing_div; + hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay; + hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key; + hi_cmd.param5 = ext_attr->hi_cfg_ctrl; + hi_cmd.param6 = ext_attr->hi_cfg_transmit; + + rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Reset power down flag (set one call only) */ + ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); + + return 0; + +rw_error: + return -EIO; +} + +/** +* \fn int hi_command() +* \brief Configure HI with settings stored in the demod structure. +* \param dev_addr I2C address. +* \param cmd HI command. +* \param result HI command result. +* \return int. +* +* Sends command to HI +* +*/ +static int +hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 *result) +{ + u16 wait_cmd = 0; + u16 nr_retries = 0; + bool powerdown_cmd = false; + int rc; + + /* Write parameters */ + switch (cmd->cmd) { + + case SIO_HI_RA_RAM_CMD_CONFIG: + case SIO_HI_RA_RAM_CMD_ATOMIC_COPY: + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* fallthrough */ + case SIO_HI_RA_RAM_CMD_BRDCTRL: + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* fallthrough */ + case SIO_HI_RA_RAM_CMD_NULL: + /* No parameters */ + break; + + default: + return -EINVAL; + break; + } + + /* Write command */ + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET) + msleep(1); + + /* Detect power down to ommit reading result */ + powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) && + (((cmd-> + param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) + == SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); + if (!powerdown_cmd) { + /* Wait until command rdy */ + do { + nr_retries++; + if (nr_retries > DRXJ_MAX_RETRIES) { + pr_err("timeout\n"); + goto rw_error; + } + + rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } while (wait_cmd != 0); + + /* Read result */ + rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + } + /* if ( powerdown_cmd == true ) */ + return 0; +rw_error: + return -EIO; +} + +/** +* \fn int init_hi( const struct drx_demod_instance *demod ) +* \brief Initialise and configurate HI. +* \param demod pointer to demod data. +* \return int Return status. +* \retval 0 Success. +* \retval -EIO Failure. +* +* Needs to know Psys (System Clock period) and Posc (Osc Clock period) +* Need to store configuration in driver because of the way I2C +* bridging is controlled. +* +*/ +static int init_hi(const struct drx_demod_instance *demod) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + int rc; + + ext_attr = (struct drxj_data *) demod->my_ext_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; + dev_addr = demod->my_i2c_dev_addr; + + /* PATCH for bug 5003, HI ucode v3.1.0 */ + rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Timing div, 250ns/Psys */ + /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ + ext_attr->hi_cfg_timing_div = + (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000; + /* Clipping */ + if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) + ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; + /* Bridge delay, uses oscilator clock */ + /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ + /* SDA brdige delay */ + ext_attr->hi_cfg_bridge_delay = + (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) / + 1000; + /* Clipping */ + if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) + ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; + /* SCL bridge delay, same as SDA for now */ + ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) << + SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B); + /* Wakeup key, setting the read flag (as suggest in the documentation) does + not always result into a working solution (barebones worked VI2C failed). + Not setting the bit works in all cases . */ + ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY; + /* port/bridge/power down ctrl */ + ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE); + /* transit mode time out delay and watch dog divider */ + ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE; + + rc = hi_cfg_command(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; + +rw_error: + return -EIO; +} + +/*============================================================================*/ +/*== END HOST INTERFACE FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== AUXILIARY FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \fn int get_device_capabilities() +* \brief Get and store device capabilities. +* \param demod Pointer to demodulator instance. +* \return int. +* \return 0 Success +* \retval -EIO Failure +* +* Depending on pulldowns on MDx pins the following internals are set: +* * common_attr->osc_clock_freq +* * ext_attr->has_lna +* * ext_attr->has_ntsc +* * ext_attr->has_btsc +* * ext_attr->has_oob +* +*/ +static int get_device_capabilities(struct drx_demod_instance *demod) +{ + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + u16 sio_pdr_ohw_cfg = 0; + u32 sio_top_jtagid_lo = 0; + u16 bid = 0; + int rc; + + common_attr = (struct drx_common_attr *) demod->my_common_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; + + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { + case 0: + /* ignore (bypass ?) */ + break; + case 1: + /* 27 MHz */ + common_attr->osc_clock_freq = 27000; + break; + case 2: + /* 20.25 MHz */ + common_attr->osc_clock_freq = 20250; + break; + case 3: + /* 4 MHz */ + common_attr->osc_clock_freq = 4000; + break; + default: + return -EIO; + } + + /* + Determine device capabilities + Based on pinning v47 + */ + rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF); + + switch ((sio_top_jtagid_lo >> 12) & 0xFF) { + case 0x31: + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + bid = (bid >> 10) & 0xf; + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + ext_attr->has_lna = true; + ext_attr->has_ntsc = false; + ext_attr->has_btsc = false; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = false; + ext_attr->has_gpio = false; + ext_attr->has_irqn = false; + break; + case 0x33: + ext_attr->has_lna = false; + ext_attr->has_ntsc = false; + ext_attr->has_btsc = false; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = false; + ext_attr->has_gpio = false; + ext_attr->has_irqn = false; + break; + case 0x45: + ext_attr->has_lna = true; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = false; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = false; + break; + case 0x46: + ext_attr->has_lna = false; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = false; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = false; + break; + case 0x41: + ext_attr->has_lna = true; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = false; + break; + case 0x43: + ext_attr->has_lna = false; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = false; + break; + case 0x32: + ext_attr->has_lna = true; + ext_attr->has_ntsc = false; + ext_attr->has_btsc = false; + ext_attr->has_oob = true; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = true; + break; + case 0x34: + ext_attr->has_lna = false; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = true; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = true; + break; + case 0x42: + ext_attr->has_lna = true; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = true; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = true; + break; + case 0x44: + ext_attr->has_lna = false; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = true; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = true; + break; + default: + /* Unknown device variant */ + return -EIO; + break; + } + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn int power_up_device() +* \brief Power up device. +* \param demod Pointer to demodulator instance. +* \return int. +* \return 0 Success +* \retval -EIO Failure, I2C or max retries reached +* +*/ + +#ifndef DRXJ_MAX_RETRIES_POWERUP +#define DRXJ_MAX_RETRIES_POWERUP 10 +#endif + +static int power_up_device(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + u8 data = 0; + u16 retry_count = 0; + struct i2c_device_addr wake_up_addr; + + dev_addr = demod->my_i2c_dev_addr; + wake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY; + wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id; + wake_up_addr.user_data = dev_addr->user_data; + /* + * I2C access may fail in this case: no ack + * dummy write must be used to wake uop device, dummy read must be used to + * reset HI state machine (avoiding actual writes) + */ + do { + data = 0; + drxbsp_i2c_write_read(&wake_up_addr, 1, &data, + (struct i2c_device_addr *)(NULL), 0, + (u8 *)(NULL)); + msleep(10); + retry_count++; + } while ((drxbsp_i2c_write_read + ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1, + &data) + != 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP)); + + /* Need some recovery time .... */ + msleep(10); + + if (retry_count == DRXJ_MAX_RETRIES_POWERUP) + return -EIO; + + return 0; +} + +/*----------------------------------------------------------------------------*/ +/* MPEG Output Configuration Functions - begin */ +/*----------------------------------------------------------------------------*/ +/** +* \fn int ctrl_set_cfg_mpeg_output() +* \brief Set MPEG output configuration of the device. +* \param devmod Pointer to demodulator instance. +* \param cfg_data Pointer to mpeg output configuaration. +* \return int. +* +* Configure MPEG output parameters. +* +*/ +static int +ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data) +{ + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); + int rc; + u16 fec_oc_reg_mode = 0; + u16 fec_oc_reg_ipr_mode = 0; + u16 fec_oc_reg_ipr_invert = 0; + u32 max_bit_rate = 0; + u32 rcn_rate = 0; + u32 nr_bits = 0; + u16 sio_pdr_md_cfg = 0; + /* data mask for the output data byte */ + u16 invert_data_mask = + FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | + FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | + FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | + FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; + + /* check arguments */ + if ((demod == NULL) || (cfg_data == NULL)) + return -EINVAL; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; + + if (cfg_data->enable_mpeg_output == true) { + /* quick and dirty patch to set MPEG incase current std is not + producing MPEG */ + switch (ext_attr->standard) { + case DRX_STANDARD_8VSB: + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + break; + default: + return 0; + } + + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + switch (ext_attr->standard) { + case DRX_STANDARD_8VSB: + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* 2048 bytes fifo ram */ + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Low Water Mark for synchronization */ + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* High Water Mark for synchronization */ + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + switch (ext_attr->constellation) { + case DRX_CONSTELLATION_QAM256: + nr_bits = 8; + break; + case DRX_CONSTELLATION_QAM128: + nr_bits = 7; + break; + case DRX_CONSTELLATION_QAM64: + nr_bits = 6; + break; + case DRX_CONSTELLATION_QAM32: + nr_bits = 5; + break; + case DRX_CONSTELLATION_QAM16: + nr_bits = 4; + break; + default: + return -EIO; + } /* ext_attr->constellation */ + /* max_bit_rate = symbol_rate * nr_bits * coef */ + /* coef = 188/204 */ + max_bit_rate = + (ext_attr->curr_symbol_rate / 8) * nr_bits * 188; + /* pass through b/c Annex A/c need following settings */ + case DRX_STANDARD_ITU_B: + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (cfg_data->static_clk == true) { + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + break; + } /* swtich (standard) */ + + /* Check insertion of the Reed-Solomon parity bytes */ + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (cfg_data->insert_rs_byte == true) { + /* enable parity symbol forward */ + fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M; + /* MVAL disable during parity bytes */ + fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; + switch (ext_attr->standard) { + case DRX_STANDARD_8VSB: + rcn_rate = 0x004854D3; + break; + case DRX_STANDARD_ITU_B: + fec_oc_reg_mode |= FEC_OC_MODE_TRANSPARENT__M; + switch (ext_attr->constellation) { + case DRX_CONSTELLATION_QAM256: + rcn_rate = 0x008945E7; + break; + case DRX_CONSTELLATION_QAM64: + rcn_rate = 0x005F64D4; + break; + default: + return -EIO; + } + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */ + rcn_rate = + (frac28 + (max_bit_rate, + (u32) (common_attr->sys_clock_freq / 8))) / + 188; + break; + default: + return -EIO; + } /* ext_attr->standard */ + } else { /* insert_rs_byte == false */ + + /* disable parity symbol forward */ + fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M); + /* MVAL enable during parity bytes */ + fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); + switch (ext_attr->standard) { + case DRX_STANDARD_8VSB: + rcn_rate = 0x0041605C; + break; + case DRX_STANDARD_ITU_B: + fec_oc_reg_mode &= (~FEC_OC_MODE_TRANSPARENT__M); + switch (ext_attr->constellation) { + case DRX_CONSTELLATION_QAM256: + rcn_rate = 0x0082D6A0; + break; + case DRX_CONSTELLATION_QAM64: + rcn_rate = 0x005AEC1A; + break; + default: + return -EIO; + } + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */ + rcn_rate = + (frac28 + (max_bit_rate, + (u32) (common_attr->sys_clock_freq / 8))) / + 204; + break; + default: + return -EIO; + } /* ext_attr->standard */ + } + + if (cfg_data->enable_parallel == true) { /* MPEG data output is paralel -> clear ipr_mode[0] */ + fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); + } else { /* MPEG data output is serial -> set ipr_mode[0] */ + fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M; + } + + /* Control slective inversion of output bits */ + if (cfg_data->invert_data == true) + fec_oc_reg_ipr_invert |= invert_data_mask; + else + fec_oc_reg_ipr_invert &= (~(invert_data_mask)); + + if (cfg_data->invert_err == true) + fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M; + else + fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M)); + + if (cfg_data->invert_str == true) + fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M; + else + fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); + + if (cfg_data->invert_val == true) + fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M; + else + fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); + + if (cfg_data->invert_clk == true) + fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M; + else + fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); + + + if (cfg_data->static_clk == true) { /* Static mode */ + u32 dto_rate = 0; + u32 bit_rate = 0; + u16 fec_oc_dto_burst_len = 0; + u16 fec_oc_dto_period = 0; + + fec_oc_dto_burst_len = FEC_OC_DTO_BURST_LEN__PRE; + + switch (ext_attr->standard) { + case DRX_STANDARD_8VSB: + fec_oc_dto_period = 4; + if (cfg_data->insert_rs_byte == true) + fec_oc_dto_burst_len = 208; + break; + case DRX_STANDARD_ITU_A: + { + u32 symbol_rate_th = 6400000; + if (cfg_data->insert_rs_byte == true) { + fec_oc_dto_burst_len = 204; + symbol_rate_th = 5900000; + } + if (ext_attr->curr_symbol_rate >= + symbol_rate_th) { + fec_oc_dto_period = 0; + } else { + fec_oc_dto_period = 1; + } + } + break; + case DRX_STANDARD_ITU_B: + fec_oc_dto_period = 1; + if (cfg_data->insert_rs_byte == true) + fec_oc_dto_burst_len = 128; + break; + case DRX_STANDARD_ITU_C: + fec_oc_dto_period = 1; + if (cfg_data->insert_rs_byte == true) + fec_oc_dto_burst_len = 204; + break; + default: + return -EIO; + } + bit_rate = + common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period + + 2); + dto_rate = + frac28(bit_rate, common_attr->sys_clock_freq * 1000); + dto_rate >>= 3; + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) + fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1; + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { /* Dynamic mode */ + + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Write appropriate registers with requested configuration */ + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* enabling for both parallel and serial now */ + /* Write magic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Set MPEG TS pads to outputmode */ + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + sio_pdr_md_cfg = + MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH << + SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B; + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (cfg_data->enable_parallel == true) { /* MPEG data output is paralel -> set MD1 to MD7 to output mode */ + sio_pdr_md_cfg = + MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH << + SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << + SIO_PDR_MD0_CFG_MODE__B; + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + /* Enable Monitor Bus output over MPEG pads and ctl input */ + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Write nomagic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + /* Write magic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Set MPEG TS pads to inputmode */ + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Enable Monitor Bus output over MPEG pads and ctl input */ + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Write nomagic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* save values for restore after re-acquire */ + common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output; + + return 0; +rw_error: + return -EIO; +} + +/*----------------------------------------------------------------------------*/ + + +/*----------------------------------------------------------------------------*/ +/* MPEG Output Configuration Functions - end */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* miscellaneous configuartions - begin */ +/*----------------------------------------------------------------------------*/ + +/** +* \fn int set_mpegtei_handling() +* \brief Activate MPEG TEI handling settings. +* \param devmod Pointer to demodulator instance. +* \return int. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static int set_mpegtei_handling(struct drx_demod_instance *demod) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + int rc; + u16 fec_oc_dpr_mode = 0; + u16 fec_oc_snc_mode = 0; + u16 fec_oc_ems_mode = 0; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* reset to default, allow TEI bit to be changed */ + fec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M); + fec_oc_snc_mode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M | + FEC_OC_SNC_MODE_CORR_DISABLE__M)); + fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M); + + if (ext_attr->disable_te_ihandling) { + /* do not change TEI bit */ + fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M; + fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M | + ((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B)); + fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B)); + } + + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/*----------------------------------------------------------------------------*/ +/** +* \fn int bit_reverse_mpeg_output() +* \brief Set MPEG output bit-endian settings. +* \param devmod Pointer to demodulator instance. +* \return int. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + int rc; + u16 fec_oc_ipr_mode = 0; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* reset to default (normal bit order) */ + fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M); + + if (ext_attr->bit_reverse_mpeg_outout) + fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; + + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/*----------------------------------------------------------------------------*/ +/** +* \fn int set_mpeg_start_width() +* \brief Set MPEG start width. +* \param devmod Pointer to demodulator instance. +* \return int. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static int set_mpeg_start_width(struct drx_demod_instance *demod) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; + int rc; + u16 fec_oc_comm_mb = 0; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + common_attr = demod->my_common_attr; + + if ((common_attr->mpeg_cfg.static_clk == true) + && (common_attr->mpeg_cfg.enable_parallel == false)) { + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON; + if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC) + fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON; + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + return 0; +rw_error: + return -EIO; +} + +/*----------------------------------------------------------------------------*/ +/* miscellaneous configuartions - end */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* UIO Configuration Functions - begin */ +/*----------------------------------------------------------------------------*/ +/** +* \fn int ctrl_set_uio_cfg() +* \brief Configure modus oprandi UIO. +* \param demod Pointer to demodulator instance. +* \param uio_cfg Pointer to a configuration setting for a certain UIO. +* \return int. +*/ +static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + int rc; + + if ((uio_cfg == NULL) || (demod == NULL)) + return -EINVAL; + + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + /* Write magic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + switch (uio_cfg->uio) { + /*====================================================================*/ + case DRX_UIO1: + /* DRX_UIO1: SMA_TX UIO-1 */ + if (!ext_attr->has_smatx) + return -EIO; + switch (uio_cfg->mode) { + case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */ + case DRX_UIO_MODE_FIRMWARE_SAW: /* falltrough */ + case DRX_UIO_MODE_READWRITE: + ext_attr->uio_sma_tx_mode = uio_cfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + ext_attr->uio_sma_tx_mode = uio_cfg->mode; + /* pad configuration register is set 0 - input mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EINVAL; + } /* switch ( uio_cfg->mode ) */ + break; + /*====================================================================*/ + case DRX_UIO2: + /* DRX_UIO2: SMA_RX UIO-2 */ + if (!ext_attr->has_smarx) + return -EIO; + switch (uio_cfg->mode) { + case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ + case DRX_UIO_MODE_READWRITE: + ext_attr->uio_sma_rx_mode = uio_cfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + ext_attr->uio_sma_rx_mode = uio_cfg->mode; + /* pad configuration register is set 0 - input mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EINVAL; + break; + } /* switch ( uio_cfg->mode ) */ + break; + /*====================================================================*/ + case DRX_UIO3: + /* DRX_UIO3: GPIO UIO-3 */ + if (!ext_attr->has_gpio) + return -EIO; + switch (uio_cfg->mode) { + case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ + case DRX_UIO_MODE_READWRITE: + ext_attr->uio_gpio_mode = uio_cfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + ext_attr->uio_gpio_mode = uio_cfg->mode; + /* pad configuration register is set 0 - input mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EINVAL; + break; + } /* switch ( uio_cfg->mode ) */ + break; + /*====================================================================*/ + case DRX_UIO4: + /* DRX_UIO4: IRQN UIO-4 */ + if (!ext_attr->has_irqn) + return -EIO; + switch (uio_cfg->mode) { + case DRX_UIO_MODE_READWRITE: + ext_attr->uio_irqn_mode = uio_cfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + /* pad configuration register is set 0 - input mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->uio_irqn_mode = uio_cfg->mode; + break; + case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ + default: + return -EINVAL; + break; + } /* switch ( uio_cfg->mode ) */ + break; + /*====================================================================*/ + default: + return -EINVAL; + } /* switch ( uio_cfg->uio ) */ + + /* Write magic word to disable pdr reg write */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn int ctrl_uio_write() +* \brief Write to a UIO. +* \param demod Pointer to demodulator instance. +* \param uio_data Pointer to data container for a certain UIO. +* \return int. +*/ +static int +ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + int rc; + u16 pin_cfg_value = 0; + u16 value = 0; + + if ((uio_data == NULL) || (demod == NULL)) + return -EINVAL; + + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + /* Write magic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + switch (uio_data->uio) { + /*====================================================================*/ + case DRX_UIO1: + /* DRX_UIO1: SMA_TX UIO-1 */ + if (!ext_attr->has_smatx) + return -EIO; + if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) + && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) { + return -EIO; + } + pin_cfg_value = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pin_cfg_value |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* use corresponding bit in io data output registar */ + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (!uio_data->value) + value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ + else + value |= 0x8000; /* write one to 15th bit - 1st UIO */ + + /* write back to io data output register */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + /*======================================================================*/ + case DRX_UIO2: + /* DRX_UIO2: SMA_RX UIO-2 */ + if (!ext_attr->has_smarx) + return -EIO; + if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) + return -EIO; + + pin_cfg_value = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pin_cfg_value |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* use corresponding bit in io data output registar */ + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (!uio_data->value) + value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ + else + value |= 0x4000; /* write one to 14th bit - 2nd UIO */ + + /* write back to io data output register */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + /*====================================================================*/ + case DRX_UIO3: + /* DRX_UIO3: ASEL UIO-3 */ + if (!ext_attr->has_gpio) + return -EIO; + if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) + return -EIO; + + pin_cfg_value = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pin_cfg_value |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* use corresponding bit in io data output registar */ + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (!uio_data->value) + value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ + else + value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ + + /* write back to io data output register */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + /*=====================================================================*/ + case DRX_UIO4: + /* DRX_UIO4: IRQN UIO-4 */ + if (!ext_attr->has_irqn) + return -EIO; + + if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) + return -EIO; + + pin_cfg_value = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pin_cfg_value |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* use corresponding bit in io data output registar */ + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (uio_data->value == false) + value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ + else + value |= 0x1000; /* write one to 12th bit - 4th UIO */ + + /* write back to io data output register */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + /*=====================================================================*/ + default: + return -EINVAL; + } /* switch ( uio_data->uio ) */ + + /* Write magic word to disable pdr reg write */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/*---------------------------------------------------------------------------*/ +/* UIO Configuration Functions - end */ +/*---------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* I2C Bridge Functions - begin */ +/*----------------------------------------------------------------------------*/ +/** +* \fn int ctrl_i2c_bridge() +* \brief Open or close the I2C switch to tuner. +* \param demod Pointer to demodulator instance. +* \param bridge_closed Pointer to bool indication if bridge is closed not. +* \return int. + +*/ +static int +ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed) +{ + struct drxj_hi_cmd hi_cmd; + u16 result = 0; + + /* check arguments */ + if (bridge_closed == NULL) + return -EINVAL; + + hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; + hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; + if (*bridge_closed) + hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED; + else + hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN; + + return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); +} + +/*----------------------------------------------------------------------------*/ +/* I2C Bridge Functions - end */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* Smart antenna Functions - begin */ +/*----------------------------------------------------------------------------*/ +/** +* \fn int smart_ant_init() +* \brief Initialize Smart Antenna. +* \param pointer to struct drx_demod_instance. +* \return int. +* +*/ +static int smart_ant_init(struct drx_demod_instance *demod) +{ + struct drxj_data *ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; + struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA }; + int rc; + u16 data = 0; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + /* Write magic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* init smart antenna */ + rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (ext_attr->smart_ant_inverted) { + rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* config SMA_TX pin to smart antenna mode */ + rc = ctrl_set_uio_cfg(demod, &uio_cfg); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Write magic word to disable pdr reg write */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd) +{ + int rc; + u16 cur_cmd = 0; + unsigned long timeout; + + /* Check param */ + if (cmd == NULL) + return -EINVAL; + + /* Wait until SCU command interface is ready to receive command */ + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (cur_cmd != DRX_SCU_READY) + return -EIO; + + switch (cmd->parameter_len) { + case 5: + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ + case 4: + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ + case 3: + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ + case 2: + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ + case 1: + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ + case 0: + /* do nothing */ + break; + default: + /* this number of parameters is not supported */ + return -EIO; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Wait until SCU has processed command */ + timeout = jiffies + msecs_to_jiffies(DRXJ_MAX_WAITTIME); + while (time_is_after_jiffies(timeout)) { + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (cur_cmd == DRX_SCU_READY) + break; + usleep_range(1000, 2000); + } + + if (cur_cmd != DRX_SCU_READY) + return -EIO; + + /* read results */ + if ((cmd->result_len > 0) && (cmd->result != NULL)) { + s16 err; + + switch (cmd->result_len) { + case 4: + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ + case 3: + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ + case 2: + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ + case 1: + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* fallthrough */ + case 0: + /* do nothing */ + break; + default: + /* this number of parameters is not supported */ + return -EIO; + } + + /* Check if an error was reported by SCU */ + err = cmd->result[0]; + + /* check a few fixed error codes */ + if ((err == (s16) SCU_RAM_PARAM_0_RESULT_UNKSTD) + || (err == (s16) SCU_RAM_PARAM_0_RESULT_UNKCMD) + || (err == (s16) SCU_RAM_PARAM_0_RESULT_INVPAR) + || (err == (s16) SCU_RAM_PARAM_0_RESULT_SIZE) + ) { + return -EINVAL; + } + /* here it is assumed that negative means error, and positive no error */ + else if (err < 0) + return -EIO; + else + return 0; + } + + return 0; + +rw_error: + return -EIO; +} + +/** +* \fn int DRXJ_DAP_SCUAtomicReadWriteBlock() +* \brief Basic access routine for SCU atomic read or write access +* \param dev_addr pointer to i2c dev address +* \param addr destination/source address +* \param datasize size of data buffer in bytes +* \param data pointer to data buffer +* \return int +* \retval 0 Succes +* \retval -EIO Timeout, I2C error, illegal bank +* +*/ +#define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2) +static +int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */ + u8 *data, bool read_flag) +{ + struct drxjscu_cmd scu_cmd; + int rc; + u16 set_param_parameters[15]; + u16 cmd_result[15]; + + /* Parameter check */ + if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16)) + return -EINVAL; + + set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr); + if (read_flag) { /* read */ + set_param_parameters[0] = ((~(0x0080)) & datasize); + scu_cmd.parameter_len = 2; + scu_cmd.result_len = datasize / 2 + 2; + } else { + int i = 0; + + set_param_parameters[0] = 0x0080 | datasize; + for (i = 0; i < (datasize / 2); i++) { + set_param_parameters[i + 2] = + (data[2 * i] | (data[(2 * i) + 1] << 8)); + } + scu_cmd.parameter_len = datasize / 2 + 2; + scu_cmd.result_len = 1; + } + + scu_cmd.command = + SCU_RAM_COMMAND_STANDARD_TOP | + SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS; + scu_cmd.result = cmd_result; + scu_cmd.parameter = set_param_parameters; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (read_flag) { + int i = 0; + /* read data from buffer */ + for (i = 0; i < (datasize / 2); i++) { + data[2 * i] = (u8) (scu_cmd.result[i + 2] & 0xFF); + data[(2 * i) + 1] = (u8) (scu_cmd.result[i + 2] >> 8); + } + } + + return 0; + +rw_error: + return -EIO; + +} + +/*============================================================================*/ + +/** +* \fn int DRXJ_DAP_AtomicReadReg16() +* \brief Atomic read of 16 bits words +*/ +static +int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 *data, u32 flags) +{ + u8 buf[2]; + int rc = -EIO; + u16 word = 0; + + if (!data) + return -EINVAL; + + rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true); + if (rc < 0) + return rc; + + word = (u16) (buf[0] + (buf[1] << 8)); + + *data = word; + + return rc; +} + +/*============================================================================*/ +/** +* \fn int drxj_dap_scu_atomic_write_reg16() +* \brief Atomic read of 16 bits words +*/ +static +int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 data, u32 flags) +{ + u8 buf[2]; + int rc = -EIO; + + buf[0] = (u8) (data & 0xff); + buf[1] = (u8) ((data >> 8) & 0xff); + + rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false); + + return rc; +} + +/* -------------------------------------------------------------------------- */ +/** +* \brief Measure result of ADC synchronisation +* \param demod demod instance +* \param count (returned) count +* \return int. +* \retval 0 Success +* \retval -EIO Failure: I2C error +* +*/ +static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count) +{ + struct i2c_device_addr *dev_addr = NULL; + int rc; + u16 data = 0; + + dev_addr = demod->my_i2c_dev_addr; + + /* Start measurement */ + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */ + msleep(1); + + *count = 0; + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (data == 127) + *count = *count + 1; + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (data == 127) + *count = *count + 1; + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (data == 127) + *count = *count + 1; + + return 0; +rw_error: + return -EIO; +} + +/** +* \brief Synchronize analog and digital clock domains +* \param demod demod instance +* \return int. +* \retval 0 Success +* \retval -EIO Failure: I2C error or failure to synchronize +* +* An IQM reset will also reset the results of this synchronization. +* After an IQM reset this routine needs to be called again. +* +*/ + +static int adc_synchronization(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = NULL; + int rc; + u16 count = 0; + + dev_addr = demod->my_i2c_dev_addr; + + rc = adc_sync_measurement(demod, &count); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (count == 1) { + /* Try sampling on a diffrent edge */ + u16 clk_neg = 0; + + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M; + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = adc_sync_measurement(demod, &count); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* TODO: implement fallback scenarios */ + if (count < 2) + return -EIO; + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ +/*== END AUXILIARY FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ +/** +* \fn int init_agc () +* \brief Initialize AGC for all standards. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \return int. +*/ +static int init_agc(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drx_common_attr *common_attr = NULL; + struct drxj_data *ext_attr = NULL; + struct drxj_cfg_agc *p_agc_rf_settings = NULL; + struct drxj_cfg_agc *p_agc_if_settings = NULL; + int rc; + u16 ingain_tgt_max = 0; + u16 clp_dir_to = 0; + u16 sns_sum_max = 0; + u16 clp_sum_max = 0; + u16 sns_dir_to = 0; + u16 ki_innergain_min = 0; + u16 agc_ki = 0; + u16 ki_max = 0; + u16 if_iaccu_hi_tgt_min = 0; + u16 data = 0; + u16 agc_ki_dgain = 0; + u16 ki_min = 0; + u16 clp_ctrl_mode = 0; + u16 agc_rf = 0; + u16 agc_if = 0; + + dev_addr = demod->my_i2c_dev_addr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + switch (ext_attr->standard) { + case DRX_STANDARD_8VSB: + clp_sum_max = 1023; + clp_dir_to = (u16) (-9); + sns_sum_max = 1023; + sns_dir_to = (u16) (-9); + ki_innergain_min = (u16) (-32768); + ki_max = 0x032C; + agc_ki_dgain = 0xC; + if_iaccu_hi_tgt_min = 2047; + ki_min = 0x0117; + ingain_tgt_max = 16383; + clp_ctrl_mode = 0; + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg); + p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg); + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_B: + ingain_tgt_max = 5119; + clp_sum_max = 1023; + clp_dir_to = (u16) (-5); + sns_sum_max = 127; + sns_dir_to = (u16) (-3); + ki_innergain_min = 0; + ki_max = 0x0657; + if_iaccu_hi_tgt_min = 2047; + agc_ki_dgain = 0x7; + ki_min = 0x0117; + clp_ctrl_mode = 0; + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + p_agc_if_settings = &(ext_attr->qam_if_agc_cfg); + p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + agc_ki &= 0xf000; + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; +#endif + default: + return -EINVAL; + } + + /* for new AGC interface */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Gain fed from inner to outer AGC */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* set to p_agc_settings->top before */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + agc_rf = 0x800 + p_agc_rf_settings->cut_off_current; + if (common_attr->tuner_rf_agc_pol == true) + agc_rf = 0x87ff - agc_rf; + + agc_if = 0x800; + if (common_attr->tuner_if_agc_pol == true) + agc_rf = 0x87ff - agc_rf; + + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Set/restore Ki DGAIN factor */ + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_DGAIN__M; + data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn int set_frequency () +* \brief Set frequency shift. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \param tuner_freq_offset residual frequency from tuner. +* \return int. +*/ +static int +set_frequency(struct drx_demod_instance *demod, + struct drx_channel *channel, s32 tuner_freq_offset) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxj_data *ext_attr = demod->my_ext_attr; + int rc; + s32 sampling_frequency = 0; + s32 frequency_shift = 0; + s32 if_freq_actual = 0; + s32 rf_freq_residual = -1 * tuner_freq_offset; + s32 adc_freq = 0; + s32 intermediate_freq = 0; + u32 iqm_fs_rate_ofs = 0; + bool adc_flip = true; + bool select_pos_image = false; + bool rf_mirror; + bool tuner_mirror; + bool image_to_select = true; + s32 fm_frequency_shift = 0; + + rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false; + tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true; + /* + Program frequency shifter + No need to account for mirroring on RF + */ + switch (ext_attr->standard) { + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_C: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_8VSB: + select_pos_image = true; + break; + case DRX_STANDARD_FM: + /* After IQM FS sound carrier must appear at 4 Mhz in spect. + Sound carrier is already 3Mhz above centre frequency due + to tuner setting so now add an extra shift of 1MHz... */ + fm_frequency_shift = 1000; + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: + select_pos_image = false; + break; + default: + return -EINVAL; + } + intermediate_freq = demod->my_common_attr->intermediate_freq; + sampling_frequency = demod->my_common_attr->sys_clock_freq / 3; + if (tuner_mirror) + if_freq_actual = intermediate_freq + rf_freq_residual + fm_frequency_shift; + else + if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift; + if (if_freq_actual > sampling_frequency / 2) { + /* adc mirrors */ + adc_freq = sampling_frequency - if_freq_actual; + adc_flip = true; + } else { + /* adc doesn't mirror */ + adc_freq = if_freq_actual; + adc_flip = false; + } + + frequency_shift = adc_freq; + image_to_select = + (bool) (rf_mirror ^ tuner_mirror ^ adc_flip ^ select_pos_image); + iqm_fs_rate_ofs = frac28(frequency_shift, sampling_frequency); + + if (image_to_select) + iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1; + + /* Program frequency shifter with tuner offset compensation */ + /* frequency_shift += tuner_freq_offset; TODO */ + rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; + ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image); + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn int get_acc_pkt_err() +* \brief Retrieve signal strength for VSB and QAM. +* \param demod Pointer to demod instance +* \param packet_err Pointer to packet error +* \return int. +* \retval 0 sig_strength contains valid data. +* \retval -EINVAL sig_strength is NULL. +* \retval -EIO Erroneous data, sig_strength contains invalid data. +*/ +#ifdef DRXJ_SIGNAL_ACCUM_ERR +static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) +{ + int rc; + static u16 pkt_err; + static u16 last_pkt_err; + u16 data = 0; + struct drxj_data *ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; + + ext_attr = (struct drxj_data *) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; + + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (ext_attr->reset_pkt_err_acc) { + last_pkt_err = data; + pkt_err = 0; + ext_attr->reset_pkt_err_acc = false; + } + + if (data < last_pkt_err) { + pkt_err += 0xffff - last_pkt_err; + pkt_err += data; + } else { + pkt_err += (data - last_pkt_err); + } + *packet_err = pkt_err; + last_pkt_err = data; + + return 0; +rw_error: + return -EIO; +} +#endif + + +/*============================================================================*/ + +/** +* \fn int set_agc_rf () +* \brief Configure RF AGC +* \param demod instance of demodulator. +* \param agc_settings AGC configuration structure +* \return int. +*/ +static int +set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + struct drxj_cfg_agc *p_agc_settings = NULL; + struct drx_common_attr *common_attr = NULL; + int rc; + drx_write_reg16func_t scu_wr16 = NULL; + drx_read_reg16func_t scu_rr16 = NULL; + + common_attr = (struct drx_common_attr *) demod->my_common_attr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + if (atomic) { + scu_rr16 = drxj_dap_scu_atomic_read_reg16; + scu_wr16 = drxj_dap_scu_atomic_write_reg16; + } else { + scu_rr16 = drxj_dap_read_reg16; + scu_wr16 = drxj_dap_write_reg16; + } + + /* Configure AGC only if standard is currently active */ + if ((ext_attr->standard == agc_settings->standard) || + (DRXJ_ISQAMSTD(ext_attr->standard) && + DRXJ_ISQAMSTD(agc_settings->standard)) || + (DRXJ_ISATVSTD(ext_attr->standard) && + DRXJ_ISATVSTD(agc_settings->standard))) { + u16 data = 0; + + switch (agc_settings->ctrl_mode) { + case DRX_AGC_CTRL_AUTO: + + /* Enable RF AGC DAC */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Enable SCU RF AGC loop */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_RF__M; + if (ext_attr->standard == DRX_STANDARD_8VSB) + data |= (2 << SCU_RAM_AGC_KI_RF__B); + else if (DRXJ_ISQAMSTD(ext_attr->standard)) + data |= (5 << SCU_RAM_AGC_KI_RF__B); + else + data |= (4 << SCU_RAM_AGC_KI_RF__B); + + if (common_attr->tuner_rf_agc_pol) + data |= SCU_RAM_AGC_KI_INV_RF_POL__M; + else + data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Set speed ( using complementary reduction value ) */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (agc_settings->standard == DRX_STANDARD_8VSB) + p_agc_settings = &(ext_attr->vsb_if_agc_cfg); + else if (DRXJ_ISQAMSTD(agc_settings->standard)) + p_agc_settings = &(ext_attr->qam_if_agc_cfg); + else if (DRXJ_ISATVSTD(agc_settings->standard)) + p_agc_settings = &(ext_attr->atv_if_agc_cfg); + else + return -EINVAL; + + /* Set TOP, only if IF-AGC is in AUTO mode */ + if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* Cut-Off current */ + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_AGC_CTRL_USER: + + /* Enable RF AGC DAC */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Disable SCU RF AGC loop */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_RF__M; + if (common_attr->tuner_rf_agc_pol) + data |= SCU_RAM_AGC_KI_INV_RF_POL__M; + else + data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Write value to output pin */ + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_AGC_CTRL_OFF: + + /* Disable RF AGC DAC */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Disable SCU RF AGC loop */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_RF__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EINVAL; + } /* switch ( agcsettings->ctrl_mode ) */ + } + + /* Store rf agc settings */ + switch (agc_settings->standard) { + case DRX_STANDARD_8VSB: + ext_attr->vsb_rf_agc_cfg = *agc_settings; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + ext_attr->qam_rf_agc_cfg = *agc_settings; + break; +#endif + default: + return -EIO; + } + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn int set_agc_if () +* \brief Configure If AGC +* \param demod instance of demodulator. +* \param agc_settings AGC configuration structure +* \return int. +*/ +static int +set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + struct drxj_cfg_agc *p_agc_settings = NULL; + struct drx_common_attr *common_attr = NULL; + drx_write_reg16func_t scu_wr16 = NULL; + drx_read_reg16func_t scu_rr16 = NULL; + int rc; + + common_attr = (struct drx_common_attr *) demod->my_common_attr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + if (atomic) { + scu_rr16 = drxj_dap_scu_atomic_read_reg16; + scu_wr16 = drxj_dap_scu_atomic_write_reg16; + } else { + scu_rr16 = drxj_dap_read_reg16; + scu_wr16 = drxj_dap_write_reg16; + } + + /* Configure AGC only if standard is currently active */ + if ((ext_attr->standard == agc_settings->standard) || + (DRXJ_ISQAMSTD(ext_attr->standard) && + DRXJ_ISQAMSTD(agc_settings->standard)) || + (DRXJ_ISATVSTD(ext_attr->standard) && + DRXJ_ISATVSTD(agc_settings->standard))) { + u16 data = 0; + + switch (agc_settings->ctrl_mode) { + case DRX_AGC_CTRL_AUTO: + /* Enable IF AGC DAC */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Enable SCU IF AGC loop */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data &= ~SCU_RAM_AGC_KI_IF__M; + if (ext_attr->standard == DRX_STANDARD_8VSB) + data |= (3 << SCU_RAM_AGC_KI_IF__B); + else if (DRXJ_ISQAMSTD(ext_attr->standard)) + data |= (6 << SCU_RAM_AGC_KI_IF__B); + else + data |= (5 << SCU_RAM_AGC_KI_IF__B); + + if (common_attr->tuner_if_agc_pol) + data |= SCU_RAM_AGC_KI_INV_IF_POL__M; + else + data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Set speed (using complementary reduction value) */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; + rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (agc_settings->standard == DRX_STANDARD_8VSB) + p_agc_settings = &(ext_attr->vsb_rf_agc_cfg); + else if (DRXJ_ISQAMSTD(agc_settings->standard)) + p_agc_settings = &(ext_attr->qam_rf_agc_cfg); + else if (DRXJ_ISATVSTD(agc_settings->standard)) + p_agc_settings = &(ext_attr->atv_rf_agc_cfg); + else + return -EINVAL; + + /* Restore TOP */ + if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + break; + + case DRX_AGC_CTRL_USER: + + /* Enable IF AGC DAC */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Disable SCU IF AGC loop */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + if (common_attr->tuner_if_agc_pol) + data |= SCU_RAM_AGC_KI_INV_IF_POL__M; + else + data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Write value to output pin */ + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + + case DRX_AGC_CTRL_OFF: + + /* Disable If AGC DAC */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Disable SCU IF AGC loop */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EINVAL; + } /* switch ( agcsettings->ctrl_mode ) */ + + /* always set the top to support configurations without if-loop */ + rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* Store if agc settings */ + switch (agc_settings->standard) { + case DRX_STANDARD_8VSB: + ext_attr->vsb_if_agc_cfg = *agc_settings; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + ext_attr->qam_if_agc_cfg = *agc_settings; + break; +#endif + default: + return -EIO; + } + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn int set_iqm_af () +* \brief Configure IQM AF registers +* \param demod instance of demodulator. +* \param active +* \return int. +*/ +static int set_iqm_af(struct drx_demod_instance *demod, bool active) +{ + u16 data = 0; + struct i2c_device_addr *dev_addr = NULL; + int rc; + + dev_addr = demod->my_i2c_dev_addr; + + /* Configure IQM */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (!active) + data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE)); + else + data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ +/*== END 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== 8VSB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \fn int power_down_vsb () +* \brief Powr down QAM related blocks. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \return int. +*/ +static int power_down_vsb(struct drx_demod_instance *demod, bool primary) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxjscu_cmd cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; + struct drx_cfg_mpeg_output cfg_mpeg_output; + int rc; + u16 cmd_result = 0; + + /* + STOP demodulator + reset of FEC and VSB HW + */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* stop all comm_exec */ + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (primary) { + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_iqm_af(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + cfg_mpeg_output.enable_mpeg_output = false; + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn int set_vsb_leak_n_gain () +* \brief Set ATSC demod. +* \param demod instance of demodulator. +* \return int. +*/ +static int set_vsb_leak_n_gain(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = NULL; + int rc; + + const u8 vsb_ffe_leak_gain_ram0[] = { + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO1 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO2 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO3 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO4 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO5 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO6 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO7 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO8 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO9 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO10 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO11 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO12 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO1 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO2 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO3 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO4 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO5 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO6 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO7 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO8 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO9 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO10 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO11 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO12 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO1 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO2 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO3 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO4 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO5 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO6 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO7 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO8 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO9 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO10 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO11 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO12 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO1 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO2 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO3 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO4 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO5 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO6 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO7 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO8 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO9 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO10 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO11 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO12 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO1 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO2 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO3 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO4 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO5 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO6 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO7 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO8 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO9 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO10 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO11 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO12 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO1 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO2 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO3 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO4 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO5 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO6 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO7 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO8 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO9 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO10 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO11 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO12 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO1 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO2 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO3 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO4 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO5 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO6 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO7 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO8 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO9 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO10 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO11 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO12 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO1 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO2 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO3 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO4 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO5 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO6 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO7 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO8 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO9 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO10 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO11 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO12 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO1 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO2 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO3 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO4 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO5 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO6 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO7 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO8 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO9 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO10 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO11 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO12 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN1 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN2 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN3 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN4 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN5 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN6 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN7 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN8 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN9 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN10 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN11 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN12 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN1 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN2 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN3 */ + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN4 */ + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN5 */ + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN6 */ + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN7 */ + DRXJ_16TO8(0x1010) /* FIRRCA1GAIN8 */ + }; + + const u8 vsb_ffe_leak_gain_ram1[] = { + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN9 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN10 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN11 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN12 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN1 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN2 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN3 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN4 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN5 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN6 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN7 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN8 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN9 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN10 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN11 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN12 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN1 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN2 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN3 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN4 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN5 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN6 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN7 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN8 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN9 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN10 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN11 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN12 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN1 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN2 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN3 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN4 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN5 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN6 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN7 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN8 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN9 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN10 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN11 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN12 */ + DRXJ_16TO8(0x001f), /* DFETRAINLKRATIO */ + DRXJ_16TO8(0x01ff), /* DFERCA1TRAINLKRATIO */ + DRXJ_16TO8(0x01ff), /* DFERCA1DATALKRATIO */ + DRXJ_16TO8(0x004f), /* DFERCA2TRAINLKRATIO */ + DRXJ_16TO8(0x004f), /* DFERCA2DATALKRATIO */ + DRXJ_16TO8(0x01ff), /* DFEDDM1TRAINLKRATIO */ + DRXJ_16TO8(0x01ff), /* DFEDDM1DATALKRATIO */ + DRXJ_16TO8(0x0352), /* DFEDDM2TRAINLKRATIO */ + DRXJ_16TO8(0x0352), /* DFEDDM2DATALKRATIO */ + DRXJ_16TO8(0x0000), /* DFETRAINGAIN */ + DRXJ_16TO8(0x2020), /* DFERCA1GAIN */ + DRXJ_16TO8(0x1010), /* DFERCA2GAIN */ + DRXJ_16TO8(0x1818), /* DFEDDM1GAIN */ + DRXJ_16TO8(0x1212) /* DFEDDM2GAIN */ + }; + + dev_addr = demod->my_i2c_dev_addr; + rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn int set_vsb() +* \brief Set 8VSB demod. +* \param demod instance of demodulator. +* \return int. +* +*/ +static int set_vsb(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = NULL; + int rc; + struct drx_common_attr *common_attr = NULL; + struct drxjscu_cmd cmd_scu; + struct drxj_data *ext_attr = NULL; + u16 cmd_result = 0; + u16 cmd_param = 0; + const u8 vsb_taps_re[] = { + DRXJ_16TO8(-2), /* re0 */ + DRXJ_16TO8(4), /* re1 */ + DRXJ_16TO8(1), /* re2 */ + DRXJ_16TO8(-4), /* re3 */ + DRXJ_16TO8(1), /* re4 */ + DRXJ_16TO8(4), /* re5 */ + DRXJ_16TO8(-3), /* re6 */ + DRXJ_16TO8(-3), /* re7 */ + DRXJ_16TO8(6), /* re8 */ + DRXJ_16TO8(1), /* re9 */ + DRXJ_16TO8(-9), /* re10 */ + DRXJ_16TO8(3), /* re11 */ + DRXJ_16TO8(12), /* re12 */ + DRXJ_16TO8(-9), /* re13 */ + DRXJ_16TO8(-15), /* re14 */ + DRXJ_16TO8(17), /* re15 */ + DRXJ_16TO8(19), /* re16 */ + DRXJ_16TO8(-29), /* re17 */ + DRXJ_16TO8(-22), /* re18 */ + DRXJ_16TO8(45), /* re19 */ + DRXJ_16TO8(25), /* re20 */ + DRXJ_16TO8(-70), /* re21 */ + DRXJ_16TO8(-28), /* re22 */ + DRXJ_16TO8(111), /* re23 */ + DRXJ_16TO8(30), /* re24 */ + DRXJ_16TO8(-201), /* re25 */ + DRXJ_16TO8(-31), /* re26 */ + DRXJ_16TO8(629) /* re27 */ + }; + + dev_addr = demod->my_i2c_dev_addr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + /* stop all comm_exec */ + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* reset demodulator */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_RESET; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->iqm_rc_rate_ofs = 0x00AD0D79; + rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* set higher threshold */ + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* burst detection on */ + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* drop thresholds by 1 dB */ + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* drop thresholds by 2 dB */ + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* cma on */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* GPIO */ + + /* Initialize the FEC Subsystem */ + rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + { + u16 fec_oc_snc_mode = 0; + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* output data even when not locked */ + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* set clip */ + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* no transparent, no A&C framing; parity is set in mpegoutput */ + { + u16 fec_oc_reg_mode = 0; + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* timeout counter for restarting */ + rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* bypass disabled */ + /* initialize RS packet error measurement parameters */ + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* init measurement period of MER/SER */ + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* B-Input to ADC, PGA+filter in standby */ + if (!ext_attr->has_lna) { + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* turn on IQMAF. It has to be in front of setAgc**() */ + rc = set_iqm_af(demod, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = adc_synchronization(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = init_agc(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + { + /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead + of only the gain */ + struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 }; + + vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg; + rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg)); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Mpeg output has to be in front of FEC active */ + rc = set_mpegtei_handling(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = bit_reverse_mpeg_output(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_mpeg_start_width(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + { + /* TODO: move to set_standard after hardware reset value problem is solved */ + /* Configure initial MPEG output */ + struct drx_cfg_mpeg_output cfg_mpeg_output; + + memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); + cfg_mpeg_output.enable_mpeg_output = true; + + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* TBD: what parameters should be set */ + cmd_param = 0x00; /* Default mode AGC on, etc */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; + cmd_scu.parameter_len = 1; + cmd_scu.result_len = 1; + cmd_scu.parameter = &cmd_param; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* start demodulator */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_START; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs) +* \brief Get the values of packet error in 8VSB mode +* \return Error code +*/ +static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, + u32 *pck_errs, u32 *pck_count) +{ + int rc; + u16 data = 0; + u16 period = 0; + u16 prescale = 0; + u16 packet_errors_mant = 0; + u16 packet_errors_exp = 0; + + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + packet_errors_mant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M; + packet_errors_exp = (data & FEC_RS_NR_FAILURES_EXP__M) + >> FEC_RS_NR_FAILURES_EXP__B; + period = FEC_RS_MEASUREMENT_PERIOD; + prescale = FEC_RS_MEASUREMENT_PRESCALE; + /* packet error rate = (error packet number) per second */ + /* 77.3 us is time for per packet */ + if (period * prescale == 0) { + pr_err("error: period and/or prescale is zero!\n"); + return -EIO; + } + *pck_errs = packet_errors_mant * (1 << packet_errors_exp); + *pck_count = period * prescale * 77; + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber) +* \brief Get the values of ber in VSB mode +* \return Error code +*/ +static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, + u32 *ber, u32 *cnt) +{ + int rc; + u16 data = 0; + u16 period = 0; + u16 prescale = 0; + u16 bit_errors_mant = 0; + u16 bit_errors_exp = 0; + + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + period = FEC_RS_MEASUREMENT_PERIOD; + prescale = FEC_RS_MEASUREMENT_PRESCALE; + + bit_errors_mant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M; + bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M) + >> FEC_RS_NR_BIT_ERRORS_EXP__B; + + *cnt = period * prescale * 207 * ((bit_errors_exp > 2) ? 1 : 8); + + if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700) + *ber = (*cnt) * 26570; + else { + if (period * prescale == 0) { + pr_err("error: period and/or prescale is zero!\n"); + return -EIO; + } + *ber = bit_errors_mant << ((bit_errors_exp > 2) ? + (bit_errors_exp - 3) : bit_errors_exp); + } + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) +* \brief Get the values of ber in VSB mode +* \return Error code +*/ +static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, + u32 *ber, u32 *cnt) +{ + u16 data = 0; + int rc; + + rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + return -EIO; + } + *ber = data; + *cnt = VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT; + + return 0; +} + +/** +* \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) +* \brief Get the values of MER +* \return Error code +*/ +static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) +{ + int rc; + u16 data_hi = 0; + + rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + *mer = + (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52)); + + return 0; +rw_error: + return -EIO; +} + + +/*============================================================================*/ +/*== END 8VSB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== QAM DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \fn int power_down_qam () +* \brief Powr down QAM related blocks. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \return int. +*/ +static int power_down_qam(struct drx_demod_instance *demod, bool primary) +{ + struct drxjscu_cmd cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; + int rc; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drx_cfg_mpeg_output cfg_mpeg_output; + struct drx_common_attr *common_attr = demod->my_common_attr; + u16 cmd_result = 0; + + /* + STOP demodulator + resets IQM, QAM and FEC HW blocks + */ + /* stop all comm_exec */ + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (primary) { + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_iqm_af(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); + cfg_mpeg_output.enable_mpeg_output = false; + + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ + +/** +* \fn int set_qam_measurement () +* \brief Setup of the QAM Measuremnt intervals for signal quality +* \param demod instance of demod. +* \param constellation current constellation. +* \return int. +* +* NOTE: +* Take into account that for certain settings the errorcounters can overflow. +* The implementation does not check this. +* +* TODO: overriding the ext_attr->fec_bits_desired by constellation dependent +* constants to get a measurement period of approx. 1 sec. Remove fec_bits_desired +* field ? +* +*/ +#ifndef DRXJ_VSB_ONLY +static int +set_qam_measurement(struct drx_demod_instance *demod, + enum drx_modulation constellation, u32 symbol_rate) +{ + struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */ + struct drxj_data *ext_attr = NULL; /* Global data container for DRXJ specif data */ + int rc; + u32 fec_bits_desired = 0; /* BER accounting period */ + u16 fec_rs_plen = 0; /* defines RS BER measurement period */ + u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ + u32 fec_rs_period = 0; /* Value for corresponding I2C register */ + u32 fec_rs_bit_cnt = 0; /* Actual precise amount of bits */ + u32 fec_oc_snc_fail_period = 0; /* Value for corresponding I2C register */ + u32 qam_vd_period = 0; /* Value for corresponding I2C register */ + u32 qam_vd_bit_cnt = 0; /* Actual precise amount of bits */ + u16 fec_vd_plen = 0; /* no of trellis symbols: VD SER measur period */ + u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */ + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + fec_bits_desired = ext_attr->fec_bits_desired; + fec_rs_prescale = ext_attr->fec_rs_prescale; + + switch (constellation) { + case DRX_CONSTELLATION_QAM16: + fec_bits_desired = 4 * symbol_rate; + break; + case DRX_CONSTELLATION_QAM32: + fec_bits_desired = 5 * symbol_rate; + break; + case DRX_CONSTELLATION_QAM64: + fec_bits_desired = 6 * symbol_rate; + break; + case DRX_CONSTELLATION_QAM128: + fec_bits_desired = 7 * symbol_rate; + break; + case DRX_CONSTELLATION_QAM256: + fec_bits_desired = 8 * symbol_rate; + break; + default: + return -EINVAL; + } + + /* Parameters for Reed-Solomon Decoder */ + /* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */ + /* rs_bit_cnt = fecrs_period*fecrs_prescale*plen */ + /* result is within 32 bit arithmetic -> */ + /* no need for mult or frac functions */ + + /* TODO: use constant instead of calculation and remove the fec_rs_plen in ext_attr */ + switch (ext_attr->standard) { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + fec_rs_plen = 204 * 8; + break; + case DRX_STANDARD_ITU_B: + fec_rs_plen = 128 * 7; + break; + default: + return -EINVAL; + } + + ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */ + fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen; /* temp storage */ + if (fec_rs_bit_cnt == 0) { + pr_err("error: fec_rs_bit_cnt is zero!\n"); + return -EIO; + } + fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1; /* ceil */ + if (ext_attr->standard != DRX_STANDARD_ITU_B) + fec_oc_snc_fail_period = fec_rs_period; + + /* limit to max 16 bit value (I2C register width) if needed */ + if (fec_rs_period > 0xFFFF) + fec_rs_period = 0xFFFF; + + /* write corresponding registers */ + switch (ext_attr->standard) { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + break; + case DRX_STANDARD_ITU_B: + switch (constellation) { + case DRX_CONSTELLATION_QAM64: + fec_rs_period = 31581; + fec_oc_snc_fail_period = 17932; + break; + case DRX_CONSTELLATION_QAM256: + fec_rs_period = 45446; + fec_oc_snc_fail_period = 25805; + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->fec_rs_period = (u16) fec_rs_period; + ext_attr->fec_rs_prescale = fec_rs_prescale; + rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + /* Parameters for Viterbi Decoder */ + /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */ + /* (qamvd_prescale*plen*(qam_constellation+1))) */ + /* vd_bit_cnt = qamvd_period*qamvd_prescale*plen */ + /* result is within 32 bit arithmetic -> */ + /* no need for mult or frac functions */ + + /* a(8 bit) * b(8 bit) = 16 bit result => mult32 not needed */ + fec_vd_plen = ext_attr->fec_vd_plen; + qam_vd_prescale = ext_attr->qam_vd_prescale; + qam_vd_bit_cnt = qam_vd_prescale * fec_vd_plen; /* temp storage */ + + switch (constellation) { + case DRX_CONSTELLATION_QAM64: + /* a(16 bit) * b(4 bit) = 20 bit result => mult32 not needed */ + qam_vd_period = + qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM64 + 1) + * (QAM_TOP_CONSTELLATION_QAM64 + 1); + break; + case DRX_CONSTELLATION_QAM256: + /* a(16 bit) * b(5 bit) = 21 bit result => mult32 not needed */ + qam_vd_period = + qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM256 + 1) + * (QAM_TOP_CONSTELLATION_QAM256 + 1); + break; + default: + return -EINVAL; + } + if (qam_vd_period == 0) { + pr_err("error: qam_vd_period is zero!\n"); + return -EIO; + } + qam_vd_period = fec_bits_desired / qam_vd_period; + /* limit to max 16 bit value (I2C register width) if needed */ + if (qam_vd_period > 0xFFFF) + qam_vd_period = 0xFFFF; + + /* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */ + qam_vd_bit_cnt *= qam_vd_period; + + rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->qam_vd_period = (u16) qam_vd_period; + ext_attr->qam_vd_prescale = qam_vd_prescale; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ + +/** +* \fn int set_qam16 () +* \brief QAM16 specific setup +* \param demod instance of demod. +* \return int. +*/ +static int set_qam16(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + const u8 qam_dq_qual_fun[] = { + DRXJ_16TO8(2), /* fun0 */ + DRXJ_16TO8(2), /* fun1 */ + DRXJ_16TO8(2), /* fun2 */ + DRXJ_16TO8(2), /* fun3 */ + DRXJ_16TO8(3), /* fun4 */ + DRXJ_16TO8(3), /* fun5 */ + }; + const u8 qam_eq_cma_rad[] = { + DRXJ_16TO8(13517), /* RAD0 */ + DRXJ_16TO8(13517), /* RAD1 */ + DRXJ_16TO8(13517), /* RAD2 */ + DRXJ_16TO8(13517), /* RAD3 */ + DRXJ_16TO8(13517), /* RAD4 */ + DRXJ_16TO8(13517), /* RAD5 */ + }; + + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ + +/** +* \fn int set_qam32 () +* \brief QAM32 specific setup +* \param demod instance of demod. +* \return int. +*/ +static int set_qam32(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + const u8 qam_dq_qual_fun[] = { + DRXJ_16TO8(3), /* fun0 */ + DRXJ_16TO8(3), /* fun1 */ + DRXJ_16TO8(3), /* fun2 */ + DRXJ_16TO8(3), /* fun3 */ + DRXJ_16TO8(4), /* fun4 */ + DRXJ_16TO8(4), /* fun5 */ + }; + const u8 qam_eq_cma_rad[] = { + DRXJ_16TO8(6707), /* RAD0 */ + DRXJ_16TO8(6707), /* RAD1 */ + DRXJ_16TO8(6707), /* RAD2 */ + DRXJ_16TO8(6707), /* RAD3 */ + DRXJ_16TO8(6707), /* RAD4 */ + DRXJ_16TO8(6707), /* RAD5 */ + }; + + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ + +/** +* \fn int set_qam64 () +* \brief QAM64 specific setup +* \param demod instance of demod. +* \return int. +*/ +static int set_qam64(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + const u8 qam_dq_qual_fun[] = { /* this is hw reset value. no necessary to re-write */ + DRXJ_16TO8(4), /* fun0 */ + DRXJ_16TO8(4), /* fun1 */ + DRXJ_16TO8(4), /* fun2 */ + DRXJ_16TO8(4), /* fun3 */ + DRXJ_16TO8(6), /* fun4 */ + DRXJ_16TO8(6), /* fun5 */ + }; + const u8 qam_eq_cma_rad[] = { + DRXJ_16TO8(13336), /* RAD0 */ + DRXJ_16TO8(12618), /* RAD1 */ + DRXJ_16TO8(11988), /* RAD2 */ + DRXJ_16TO8(13809), /* RAD3 */ + DRXJ_16TO8(13809), /* RAD4 */ + DRXJ_16TO8(15609), /* RAD5 */ + }; + + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ + +/** +* \fn int set_qam128 () +* \brief QAM128 specific setup +* \param demod: instance of demod. +* \return int. +*/ +static int set_qam128(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + const u8 qam_dq_qual_fun[] = { + DRXJ_16TO8(6), /* fun0 */ + DRXJ_16TO8(6), /* fun1 */ + DRXJ_16TO8(6), /* fun2 */ + DRXJ_16TO8(6), /* fun3 */ + DRXJ_16TO8(9), /* fun4 */ + DRXJ_16TO8(9), /* fun5 */ + }; + const u8 qam_eq_cma_rad[] = { + DRXJ_16TO8(6164), /* RAD0 */ + DRXJ_16TO8(6598), /* RAD1 */ + DRXJ_16TO8(6394), /* RAD2 */ + DRXJ_16TO8(6409), /* RAD3 */ + DRXJ_16TO8(6656), /* RAD4 */ + DRXJ_16TO8(7238), /* RAD5 */ + }; + + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ + +/** +* \fn int set_qam256 () +* \brief QAM256 specific setup +* \param demod: instance of demod. +* \return int. +*/ +static int set_qam256(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + const u8 qam_dq_qual_fun[] = { + DRXJ_16TO8(8), /* fun0 */ + DRXJ_16TO8(8), /* fun1 */ + DRXJ_16TO8(8), /* fun2 */ + DRXJ_16TO8(8), /* fun3 */ + DRXJ_16TO8(12), /* fun4 */ + DRXJ_16TO8(12), /* fun5 */ + }; + const u8 qam_eq_cma_rad[] = { + DRXJ_16TO8(12345), /* RAD0 */ + DRXJ_16TO8(12345), /* RAD1 */ + DRXJ_16TO8(13626), /* RAD2 */ + DRXJ_16TO8(12931), /* RAD3 */ + DRXJ_16TO8(14719), /* RAD4 */ + DRXJ_16TO8(15356), /* RAD5 */ + }; + + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ +#define QAM_SET_OP_ALL 0x1 +#define QAM_SET_OP_CONSTELLATION 0x2 +#define QAM_SET_OP_SPECTRUM 0X4 + +/** +* \fn int set_qam () +* \brief Set QAM demod. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return int. +*/ +static int +set_qam(struct drx_demod_instance *demod, + struct drx_channel *channel, s32 tuner_freq_offset, u32 op) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + struct drx_common_attr *common_attr = NULL; + int rc; + u32 adc_frequency = 0; + u32 iqm_rc_rate = 0; + u16 cmd_result = 0; + u16 lc_symbol_freq = 0; + u16 iqm_rc_stretch = 0; + u16 set_env_parameters = 0; + u16 set_param_parameters[2] = { 0 }; + struct drxjscu_cmd cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, + /* parameter */ NULL, + /* result */ NULL + }; + const u8 qam_a_taps[] = { + DRXJ_16TO8(-1), /* re0 */ + DRXJ_16TO8(1), /* re1 */ + DRXJ_16TO8(1), /* re2 */ + DRXJ_16TO8(-1), /* re3 */ + DRXJ_16TO8(-1), /* re4 */ + DRXJ_16TO8(2), /* re5 */ + DRXJ_16TO8(1), /* re6 */ + DRXJ_16TO8(-2), /* re7 */ + DRXJ_16TO8(0), /* re8 */ + DRXJ_16TO8(3), /* re9 */ + DRXJ_16TO8(-1), /* re10 */ + DRXJ_16TO8(-3), /* re11 */ + DRXJ_16TO8(4), /* re12 */ + DRXJ_16TO8(1), /* re13 */ + DRXJ_16TO8(-8), /* re14 */ + DRXJ_16TO8(4), /* re15 */ + DRXJ_16TO8(13), /* re16 */ + DRXJ_16TO8(-13), /* re17 */ + DRXJ_16TO8(-19), /* re18 */ + DRXJ_16TO8(28), /* re19 */ + DRXJ_16TO8(25), /* re20 */ + DRXJ_16TO8(-53), /* re21 */ + DRXJ_16TO8(-31), /* re22 */ + DRXJ_16TO8(96), /* re23 */ + DRXJ_16TO8(37), /* re24 */ + DRXJ_16TO8(-190), /* re25 */ + DRXJ_16TO8(-40), /* re26 */ + DRXJ_16TO8(619) /* re27 */ + }; + const u8 qam_b64_taps[] = { + DRXJ_16TO8(0), /* re0 */ + DRXJ_16TO8(-2), /* re1 */ + DRXJ_16TO8(1), /* re2 */ + DRXJ_16TO8(2), /* re3 */ + DRXJ_16TO8(-2), /* re4 */ + DRXJ_16TO8(0), /* re5 */ + DRXJ_16TO8(4), /* re6 */ + DRXJ_16TO8(-2), /* re7 */ + DRXJ_16TO8(-4), /* re8 */ + DRXJ_16TO8(4), /* re9 */ + DRXJ_16TO8(3), /* re10 */ + DRXJ_16TO8(-6), /* re11 */ + DRXJ_16TO8(0), /* re12 */ + DRXJ_16TO8(6), /* re13 */ + DRXJ_16TO8(-5), /* re14 */ + DRXJ_16TO8(-3), /* re15 */ + DRXJ_16TO8(11), /* re16 */ + DRXJ_16TO8(-4), /* re17 */ + DRXJ_16TO8(-19), /* re18 */ + DRXJ_16TO8(19), /* re19 */ + DRXJ_16TO8(28), /* re20 */ + DRXJ_16TO8(-45), /* re21 */ + DRXJ_16TO8(-36), /* re22 */ + DRXJ_16TO8(90), /* re23 */ + DRXJ_16TO8(42), /* re24 */ + DRXJ_16TO8(-185), /* re25 */ + DRXJ_16TO8(-46), /* re26 */ + DRXJ_16TO8(614) /* re27 */ + }; + const u8 qam_b256_taps[] = { + DRXJ_16TO8(-2), /* re0 */ + DRXJ_16TO8(4), /* re1 */ + DRXJ_16TO8(1), /* re2 */ + DRXJ_16TO8(-4), /* re3 */ + DRXJ_16TO8(0), /* re4 */ + DRXJ_16TO8(4), /* re5 */ + DRXJ_16TO8(-2), /* re6 */ + DRXJ_16TO8(-4), /* re7 */ + DRXJ_16TO8(5), /* re8 */ + DRXJ_16TO8(2), /* re9 */ + DRXJ_16TO8(-8), /* re10 */ + DRXJ_16TO8(2), /* re11 */ + DRXJ_16TO8(11), /* re12 */ + DRXJ_16TO8(-8), /* re13 */ + DRXJ_16TO8(-15), /* re14 */ + DRXJ_16TO8(16), /* re15 */ + DRXJ_16TO8(19), /* re16 */ + DRXJ_16TO8(-27), /* re17 */ + DRXJ_16TO8(-22), /* re18 */ + DRXJ_16TO8(44), /* re19 */ + DRXJ_16TO8(26), /* re20 */ + DRXJ_16TO8(-69), /* re21 */ + DRXJ_16TO8(-28), /* re22 */ + DRXJ_16TO8(110), /* re23 */ + DRXJ_16TO8(31), /* re24 */ + DRXJ_16TO8(-201), /* re25 */ + DRXJ_16TO8(-32), /* re26 */ + DRXJ_16TO8(628) /* re27 */ + }; + const u8 qam_c_taps[] = { + DRXJ_16TO8(-3), /* re0 */ + DRXJ_16TO8(3), /* re1 */ + DRXJ_16TO8(2), /* re2 */ + DRXJ_16TO8(-4), /* re3 */ + DRXJ_16TO8(0), /* re4 */ + DRXJ_16TO8(4), /* re5 */ + DRXJ_16TO8(-1), /* re6 */ + DRXJ_16TO8(-4), /* re7 */ + DRXJ_16TO8(3), /* re8 */ + DRXJ_16TO8(3), /* re9 */ + DRXJ_16TO8(-5), /* re10 */ + DRXJ_16TO8(0), /* re11 */ + DRXJ_16TO8(9), /* re12 */ + DRXJ_16TO8(-4), /* re13 */ + DRXJ_16TO8(-12), /* re14 */ + DRXJ_16TO8(10), /* re15 */ + DRXJ_16TO8(16), /* re16 */ + DRXJ_16TO8(-21), /* re17 */ + DRXJ_16TO8(-20), /* re18 */ + DRXJ_16TO8(37), /* re19 */ + DRXJ_16TO8(25), /* re20 */ + DRXJ_16TO8(-62), /* re21 */ + DRXJ_16TO8(-28), /* re22 */ + DRXJ_16TO8(105), /* re23 */ + DRXJ_16TO8(31), /* re24 */ + DRXJ_16TO8(-197), /* re25 */ + DRXJ_16TO8(-33), /* re26 */ + DRXJ_16TO8(626) /* re27 */ + }; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM256: + iqm_rc_rate = 0x00AE3562; + lc_symbol_freq = + QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256; + channel->symbolrate = 5360537; + iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_256; + break; + case DRX_CONSTELLATION_QAM64: + iqm_rc_rate = 0x00C05A0E; + lc_symbol_freq = 409; + channel->symbolrate = 5056941; + iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64; + break; + default: + return -EINVAL; + } + } else { + adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; + if (channel->symbolrate == 0) { + pr_err("error: channel symbolrate is zero!\n"); + return -EIO; + } + iqm_rc_rate = + (adc_frequency / channel->symbolrate) * (1 << 21) + + (frac28 + ((adc_frequency % channel->symbolrate), + channel->symbolrate) >> 7) - (1 << 23); + lc_symbol_freq = + (u16) (frac28 + (channel->symbolrate + + (adc_frequency >> 13), + adc_frequency) >> 16); + if (lc_symbol_freq > 511) + lc_symbol_freq = 511; + + iqm_rc_stretch = 21; + } + + if (ext_attr->standard == DRX_STANDARD_ITU_A) { + set_env_parameters = QAM_TOP_ANNEX_A; /* annex */ + set_param_parameters[0] = channel->constellation; /* constellation */ + set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ + } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { + set_env_parameters = QAM_TOP_ANNEX_B; /* annex */ + set_param_parameters[0] = channel->constellation; /* constellation */ + set_param_parameters[1] = channel->interleavemode; /* interleave mode */ + } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { + set_env_parameters = QAM_TOP_ANNEX_C; /* annex */ + set_param_parameters[0] = channel->constellation; /* constellation */ + set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ + } else { + return -EINVAL; + } + } + + if (op & QAM_SET_OP_ALL) { + /* + STEP 1: reset demodulator + resets IQM, QAM and FEC HW blocks + resets SCU variables + */ + /* stop all comm_exec */ + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_RESET; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { + /* + STEP 2: configure demodulator + -set env + -set params (resets IQM,QAM,FEC HW; initializes some SCU variables ) + */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + cmd_scu.parameter_len = 1; + cmd_scu.result_len = 1; + cmd_scu.parameter = &set_env_parameters; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; + cmd_scu.parameter_len = 2; + cmd_scu.result_len = 1; + cmd_scu.parameter = set_param_parameters; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* set symbol rate */ + rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->iqm_rc_rate_ofs = iqm_rc_rate; + rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + /* STEP 3: enable the system in a mode where the ADC provides valid signal + setup constellation independent registers */ + /* from qam_cmd.py script (qam_driver_b) */ + /* TODO: remove re-writes of HW reset values */ + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) { + rc = set_frequency(demod, channel, tuner_freq_offset); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { + + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + if (op & QAM_SET_OP_ALL) { + if (!ext_attr->has_lna) { + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* scu temporary shut down agc */ + + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + } else { + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM16: + case DRX_CONSTELLATION_QAM64: + case DRX_CONSTELLATION_QAM256: + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + break; + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM128: + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EIO; + } /* switch */ + } + + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* No more resets of the IQM, current standard correctly set => + now AGCs can be configured. */ + /* turn on IQMAF. It has to be in front of setAgc**() */ + rc = set_iqm_af(demod, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = adc_synchronization(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = init_agc(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + { + /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead + of only the gain */ + struct drxj_cfg_afe_gain qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 }; + + qam_pga_cfg.gain = ext_attr->qam_pga_cfg; + rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg)); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { + if (ext_attr->standard == DRX_STANDARD_ITU_A) { + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM64: + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_CONSTELLATION_QAM256: + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EIO; + } + } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* SETP 4: constellation specific setup */ + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM16: + rc = set_qam16(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_CONSTELLATION_QAM32: + rc = set_qam32(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_CONSTELLATION_QAM64: + rc = set_qam64(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_CONSTELLATION_QAM128: + rc = set_qam128(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_CONSTELLATION_QAM256: + rc = set_qam256(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EIO; + } /* switch */ + } + + if ((op & QAM_SET_OP_ALL)) { + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Mpeg output has to be in front of FEC active */ + rc = set_mpegtei_handling(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = bit_reverse_mpeg_output(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_mpeg_start_width(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + { + /* TODO: move to set_standard after hardware reset value problem is solved */ + /* Configure initial MPEG output */ + struct drx_cfg_mpeg_output cfg_mpeg_output; + + memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); + cfg_mpeg_output.enable_mpeg_output = true; + + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { + + /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_START; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ +static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod); + +static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxj_data *ext_attr = demod->my_ext_attr; + int rc; + u32 iqm_fs_rate_ofs = 0; + u32 iqm_fs_rate_lo = 0; + u16 qam_ctl_ena = 0; + u16 data = 0; + u16 equ_mode = 0; + u16 fsm_state = 0; + int i = 0; + int ofsofs = 0; + + /* Silence the controlling of lc, equ, and the acquisition state machine */ + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* freeze the frequency control loop */ + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs; + iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1; + iqm_fs_rate_ofs -= 2 * ofsofs; + + /* freeze dq/fq updating */ + rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data = (data & 0xfff9); + rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* lc_cp / _ci / _ca */ + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* flip the spec */ + rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; + ext_attr->pos_image = (ext_attr->pos_image) ? false : true; + + /* freeze dq/fq updating */ + rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + equ_mode = data; + data = (data & 0xfff9); + rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + for (i = 0; i < 28; i++) { + rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + for (i = 0; i < 24; i++) { + rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + data = equ_mode; + rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + i = 0; + while ((fsm_state != 4) && (i++ < 100)) { + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; + +} + +#define NO_LOCK 0x0 +#define DEMOD_LOCKED 0x1 +#define SYNC_FLIPPED 0x2 +#define SPEC_MIRRORED 0x4 +/** +* \fn int qam64auto () +* \brief auto do sync pattern switching and mirroring. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \param tuner_freq_offset: tuner frequency offset. +* \param lock_status: pointer to lock status. +* \return int. +*/ +static int +qam64auto(struct drx_demod_instance *demod, + struct drx_channel *channel, + s32 tuner_freq_offset, enum drx_lock_status *lock_status) +{ + struct drxj_data *ext_attr = demod->my_ext_attr; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drx39xxj_state *state = dev_addr->user_data; + struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; + int rc; + u32 lck_state = NO_LOCK; + u32 start_time = 0; + u32 d_locked_time = 0; + u32 timeout_ofs = 0; + u16 data = 0; + + /* external attributes for storing aquired channel constellation */ + *lock_status = DRX_NOT_LOCKED; + start_time = jiffies_to_msecs(jiffies); + lck_state = NO_LOCK; + do { + rc = ctrl_lock_status(demod, lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + switch (lck_state) { + case NO_LOCK: + if (*lock_status == DRXJ_DEMOD_LOCK) { + rc = ctrl_get_qam_sig_quality(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (p->cnr.stat[0].svalue > 20800) { + lck_state = DEMOD_LOCKED; + /* some delay to see if fec_lock possible TODO find the right value */ + timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */ + d_locked_time = jiffies_to_msecs(jiffies); + } + } + break; + case DEMOD_LOCKED: + if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ + ((jiffies_to_msecs(jiffies) - d_locked_time) > + DRXJ_QAM_FEC_LOCK_WAITTIME)) { + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + lck_state = SYNC_FLIPPED; + msleep(10); + } + break; + case SYNC_FLIPPED: + if (*lock_status == DRXJ_DEMOD_LOCK) { + if (channel->mirror == DRX_MIRROR_AUTO) { + /* flip sync pattern back */ + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* flip spectrum */ + ext_attr->mirror = DRX_MIRROR_YES; + rc = qam_flip_spec(demod, channel); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + lck_state = SPEC_MIRRORED; + /* reset timer TODO: still need 500ms? */ + start_time = d_locked_time = + jiffies_to_msecs(jiffies); + timeout_ofs = 0; + } else { /* no need to wait lock */ + + start_time = + jiffies_to_msecs(jiffies) - + DRXJ_QAM_MAX_WAITTIME - timeout_ofs; + } + } + break; + case SPEC_MIRRORED: + if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ + ((jiffies_to_msecs(jiffies) - d_locked_time) > + DRXJ_QAM_FEC_LOCK_WAITTIME)) { + rc = ctrl_get_qam_sig_quality(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (p->cnr.stat[0].svalue > 20800) { + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* no need to wait lock */ + start_time = + jiffies_to_msecs(jiffies) - + DRXJ_QAM_MAX_WAITTIME - timeout_ofs; + } + } + break; + default: + break; + } + msleep(10); + } while + ((*lock_status != DRX_LOCKED) && + (*lock_status != DRX_NEVER_LOCK) && + ((jiffies_to_msecs(jiffies) - start_time) < + (DRXJ_QAM_MAX_WAITTIME + timeout_ofs)) + ); + /* Returning control to apllication ... */ + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn int qam256auto () +* \brief auto do sync pattern switching and mirroring. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \param tuner_freq_offset: tuner frequency offset. +* \param lock_status: pointer to lock status. +* \return int. +*/ +static int +qam256auto(struct drx_demod_instance *demod, + struct drx_channel *channel, + s32 tuner_freq_offset, enum drx_lock_status *lock_status) +{ + struct drxj_data *ext_attr = demod->my_ext_attr; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drx39xxj_state *state = dev_addr->user_data; + struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; + int rc; + u32 lck_state = NO_LOCK; + u32 start_time = 0; + u32 d_locked_time = 0; + u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; + + /* external attributes for storing aquired channel constellation */ + *lock_status = DRX_NOT_LOCKED; + start_time = jiffies_to_msecs(jiffies); + lck_state = NO_LOCK; + do { + rc = ctrl_lock_status(demod, lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + switch (lck_state) { + case NO_LOCK: + if (*lock_status == DRXJ_DEMOD_LOCK) { + rc = ctrl_get_qam_sig_quality(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (p->cnr.stat[0].svalue > 26800) { + lck_state = DEMOD_LOCKED; + timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */ + d_locked_time = jiffies_to_msecs(jiffies); + } + } + break; + case DEMOD_LOCKED: + if (*lock_status == DRXJ_DEMOD_LOCK) { + if ((channel->mirror == DRX_MIRROR_AUTO) && + ((jiffies_to_msecs(jiffies) - d_locked_time) > + DRXJ_QAM_FEC_LOCK_WAITTIME)) { + ext_attr->mirror = DRX_MIRROR_YES; + rc = qam_flip_spec(demod, channel); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + lck_state = SPEC_MIRRORED; + /* reset timer TODO: still need 300ms? */ + start_time = jiffies_to_msecs(jiffies); + timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2; + } + } + break; + case SPEC_MIRRORED: + break; + default: + break; + } + msleep(10); + } while + ((*lock_status < DRX_LOCKED) && + (*lock_status != DRX_NEVER_LOCK) && + ((jiffies_to_msecs(jiffies) - start_time) < + (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))); + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn int set_qam_channel () +* \brief Set QAM channel according to the requested constellation. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return int. +*/ +static int +set_qam_channel(struct drx_demod_instance *demod, + struct drx_channel *channel, s32 tuner_freq_offset) +{ + struct drxj_data *ext_attr = NULL; + int rc; + enum drx_lock_status lock_status = DRX_NOT_LOCKED; + bool auto_flag = false; + + /* external attributes for storing aquired channel constellation */ + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + /* set QAM channel constellation */ + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM16: + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM128: + return -EINVAL; + case DRX_CONSTELLATION_QAM64: + case DRX_CONSTELLATION_QAM256: + if (ext_attr->standard != DRX_STANDARD_ITU_B) + return -EINVAL; + + ext_attr->constellation = channel->constellation; + if (channel->mirror == DRX_MIRROR_AUTO) + ext_attr->mirror = DRX_MIRROR_NO; + else + ext_attr->mirror = channel->mirror; + + rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (channel->constellation == DRX_CONSTELLATION_QAM64) + rc = qam64auto(demod, channel, tuner_freq_offset, + &lock_status); + else + rc = qam256auto(demod, channel, tuner_freq_offset, + &lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_CONSTELLATION_AUTO: /* for channel scan */ + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + u16 qam_ctl_ena = 0; + + auto_flag = true; + + /* try to lock default QAM constellation: QAM256 */ + channel->constellation = DRX_CONSTELLATION_QAM256; + ext_attr->constellation = DRX_CONSTELLATION_QAM256; + if (channel->mirror == DRX_MIRROR_AUTO) + ext_attr->mirror = DRX_MIRROR_NO; + else + ext_attr->mirror = channel->mirror; + rc = set_qam(demod, channel, tuner_freq_offset, + QAM_SET_OP_ALL); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = qam256auto(demod, channel, tuner_freq_offset, + &lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (lock_status >= DRX_LOCKED) { + channel->constellation = DRX_CONSTELLATION_AUTO; + break; + } + + /* QAM254 not locked. Try QAM64 constellation */ + channel->constellation = DRX_CONSTELLATION_QAM64; + ext_attr->constellation = DRX_CONSTELLATION_QAM64; + if (channel->mirror == DRX_MIRROR_AUTO) + ext_attr->mirror = DRX_MIRROR_NO; + else + ext_attr->mirror = channel->mirror; + + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + &qam_ctl_ena, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_FSM_STATE_TGT__A, + 0x2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* force to rate hunting */ + + rc = set_qam(demod, channel, tuner_freq_offset, + QAM_SET_OP_CONSTELLATION); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + qam_ctl_ena, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = qam64auto(demod, channel, tuner_freq_offset, + &lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + channel->constellation = DRX_CONSTELLATION_AUTO; + } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { + u16 qam_ctl_ena = 0; + + channel->constellation = DRX_CONSTELLATION_QAM64; + ext_attr->constellation = DRX_CONSTELLATION_QAM64; + auto_flag = true; + + if (channel->mirror == DRX_MIRROR_AUTO) + ext_attr->mirror = DRX_MIRROR_NO; + else + ext_attr->mirror = channel->mirror; + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + &qam_ctl_ena, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_FSM_STATE_TGT__A, + 0x2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* force to rate hunting */ + + rc = set_qam(demod, channel, tuner_freq_offset, + QAM_SET_OP_CONSTELLATION); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + qam_ctl_ena, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = qam64auto(demod, channel, tuner_freq_offset, + &lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + channel->constellation = DRX_CONSTELLATION_AUTO; + } else { + return -EINVAL; + } + break; + default: + return -EINVAL; + } + + return 0; +rw_error: + /* restore starting value */ + if (auto_flag) + channel->constellation = DRX_CONSTELLATION_AUTO; + return -EIO; +} + +/*============================================================================*/ + +/** +* \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr) +* \brief Get RS error count in QAM mode (used for post RS BER calculation) +* \return Error code +* +* precondition: measurement period & measurement prescale must be set +* +*/ +static int +get_qamrs_err_count(struct i2c_device_addr *dev_addr, + struct drxjrs_errors *rs_errors) +{ + int rc; + u16 nr_bit_errors = 0, + nr_symbol_errors = 0, + nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0; + + /* check arguments */ + if (dev_addr == NULL) + return -EINVAL; + + /* all reported errors are received in the */ + /* most recently finished measurment period */ + /* no of pre RS bit errors */ + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* no of symbol errors */ + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* no of packet errors */ + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* no of failures to decode */ + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* no of post RS bit erros */ + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* TODO: NOTE */ + /* These register values are fetched in non-atomic fashion */ + /* It is possible that the read values contain unrelated information */ + + rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M; + rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M; + rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M; + rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M; + rs_errors->nr_snc_par_fail_count = + nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M; + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ + +/** + * \fn int get_sig_strength() + * \brief Retrieve signal strength for VSB and QAM. + * \param demod Pointer to demod instance + * \param u16-t Pointer to signal strength data; range 0, .. , 100. + * \return int. + * \retval 0 sig_strength contains valid data. + * \retval -EINVAL sig_strength is NULL. + * \retval -EIO Erroneous data, sig_strength contains invalid data. + */ +#define DRXJ_AGC_TOP 0x2800 +#define DRXJ_AGC_SNS 0x1600 +#define DRXJ_RFAGC_MAX 0x3fff +#define DRXJ_RFAGC_MIN 0x800 + +static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + u16 rf_gain = 0; + u16 if_gain = 0; + u16 if_agc_sns = 0; + u16 if_agc_top = 0; + u16 rf_agc_max = 0; + u16 rf_agc_min = 0; + + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if_gain &= IQM_AF_AGC_IF__M; + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rf_gain &= IQM_AF_AGC_RF__M; + + if_agc_sns = DRXJ_AGC_SNS; + if_agc_top = DRXJ_AGC_TOP; + rf_agc_max = DRXJ_RFAGC_MAX; + rf_agc_min = DRXJ_RFAGC_MIN; + + if (if_gain > if_agc_top) { + if (rf_gain > rf_agc_max) + *sig_strength = 100; + else if (rf_gain > rf_agc_min) { + if (rf_agc_max == rf_agc_min) { + pr_err("error: rf_agc_max == rf_agc_min\n"); + return -EIO; + } + *sig_strength = + 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max - + rf_agc_min); + } else + *sig_strength = 75; + } else if (if_gain > if_agc_sns) { + if (if_agc_top == if_agc_sns) { + pr_err("error: if_agc_top == if_agc_sns\n"); + return -EIO; + } + *sig_strength = + 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns); + } else { + if (!if_agc_sns) { + pr_err("error: if_agc_sns is zero!\n"); + return -EIO; + } + *sig_strength = (20 * if_gain / if_agc_sns); + } + + if (*sig_strength <= 7) + *sig_strength = 0; + + return 0; + rw_error: + return -EIO; +} + +/** +* \fn int ctrl_get_qam_sig_quality() +* \brief Retreive QAM signal quality from device. +* \param devmod Pointer to demodulator instance. +* \param sig_quality Pointer to signal quality data. +* \return int. +* \retval 0 sig_quality contains valid data. +* \retval -EINVAL sig_quality is NULL. +* \retval -EIO Erroneous data, sig_quality contains invalid data. + +* Pre-condition: Device must be started and in lock. +*/ +static int +ctrl_get_qam_sig_quality(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxj_data *ext_attr = demod->my_ext_attr; + struct drx39xxj_state *state = dev_addr->user_data; + struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; + struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 }; + enum drx_modulation constellation = ext_attr->constellation; + int rc; + + u32 pre_bit_err_rs = 0; /* pre RedSolomon Bit Error Rate */ + u32 post_bit_err_rs = 0; /* post RedSolomon Bit Error Rate */ + u32 pkt_errs = 0; /* no of packet errors in RS */ + u16 qam_sl_err_power = 0; /* accumulated error between raw and sliced symbols */ + u16 qsym_err_vd = 0; /* quadrature symbol errors in QAM_VD */ + u16 fec_oc_period = 0; /* SNC sync failure measurement period */ + u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ + u16 fec_rs_period = 0; /* Value for corresponding I2C register */ + /* calculation constants */ + u32 rs_bit_cnt = 0; /* RedSolomon Bit Count */ + u32 qam_sl_sig_power = 0; /* used for MER, depends of QAM constellation */ + /* intermediate results */ + u32 e = 0; /* exponent value used for QAM BER/SER */ + u32 m = 0; /* mantisa value used for QAM BER/SER */ + u32 ber_cnt = 0; /* BER count */ + /* signal quality info */ + u32 qam_sl_mer = 0; /* QAM MER */ + u32 qam_pre_rs_ber = 0; /* Pre RedSolomon BER */ + u32 qam_post_rs_ber = 0; /* Post RedSolomon BER */ + u32 qam_vd_ser = 0; /* ViterbiDecoder SER */ + u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */ + u16 qam_vd_period = 0; /* Viterbi Measurement period */ + u32 vd_bit_cnt = 0; /* ViterbiDecoder Bit Count */ + + p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + + /* read the physical registers */ + /* Get the RS error data */ + rc = get_qamrs_err_count(dev_addr, &measuredrs_errors); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* get the register value needed for MER */ + rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* get the register value needed for post RS BER */ + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* get constants needed for signal quality calculation */ + fec_rs_period = ext_attr->fec_rs_period; + fec_rs_prescale = ext_attr->fec_rs_prescale; + rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen; + qam_vd_period = ext_attr->qam_vd_period; + qam_vd_prescale = ext_attr->qam_vd_prescale; + vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen; + + /* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */ + switch (constellation) { + case DRX_CONSTELLATION_QAM16: + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2; + break; + case DRX_CONSTELLATION_QAM32: + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2; + break; + case DRX_CONSTELLATION_QAM64: + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2; + break; + case DRX_CONSTELLATION_QAM128: + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2; + break; + case DRX_CONSTELLATION_QAM256: + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2; + break; + default: + return -EIO; + } + + /* ------------------------------ */ + /* MER Calculation */ + /* ------------------------------ */ + /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */ + + /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */ + if (qam_sl_err_power == 0) + qam_sl_mer = 0; + else + qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power); + + /* ----------------------------------------- */ + /* Pre Viterbi Symbol Error Rate Calculation */ + /* ----------------------------------------- */ + /* pre viterbi SER is good if it is bellow 0.025 */ + + /* get the register value */ + /* no of quadrature symbol errors */ + rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Extract the Exponent and the Mantisa */ + /* of number of quadrature symbol errors */ + e = (qsym_err_vd & QAM_VD_NR_QSYM_ERRORS_EXP__M) >> + QAM_VD_NR_QSYM_ERRORS_EXP__B; + m = (qsym_err_vd & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >> + QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B; + + if ((m << e) >> 3 > 549752) + qam_vd_ser = 500000 * vd_bit_cnt * ((e > 2) ? 1 : 8) / 8; + else + qam_vd_ser = m << ((e > 2) ? (e - 3) : e); + + /* --------------------------------------- */ + /* pre and post RedSolomon BER Calculation */ + /* --------------------------------------- */ + /* pre RS BER is good if it is below 3.5e-4 */ + + /* get the register values */ + pre_bit_err_rs = (u32) measuredrs_errors.nr_bit_errors; + pkt_errs = post_bit_err_rs = (u32) measuredrs_errors.nr_snc_par_fail_count; + + /* Extract the Exponent and the Mantisa of the */ + /* pre Reed-Solomon bit error count */ + e = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_EXP__M) >> + FEC_RS_NR_BIT_ERRORS_EXP__B; + m = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >> + FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B; + + ber_cnt = m << e; + + /*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */ + if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0) + qam_pre_rs_ber = 500000 * rs_bit_cnt >> e; + else + qam_pre_rs_ber = ber_cnt; + + /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */ + /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */ + /* + => c = (1000000*100*11.17)/1504 = + post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) / + (100 * FEC_OC_SNC_FAIL_PERIOD__A) + *100 and /100 is for more precision. + => (20 bits * 12 bits) /(16 bits * 7 bits) => safe in 32 bits computation + + Precision errors still possible. + */ + e = post_bit_err_rs * 742686; + m = fec_oc_period * 100; + if (fec_oc_period == 0) + qam_post_rs_ber = 0xFFFFFFFF; + else + qam_post_rs_ber = e / m; + + /* fill signal quality data structure */ + p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; + p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; + p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; + p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; + p->block_error.stat[0].scale = FE_SCALE_COUNTER; + p->cnr.stat[0].scale = FE_SCALE_DECIBEL; + + p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100; + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + p->pre_bit_error.stat[0].uvalue += qam_vd_ser; + p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8; + } else { + p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber; + p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e; + } + + p->post_bit_error.stat[0].uvalue += qam_post_rs_ber; + p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e; + + p->block_error.stat[0].uvalue += pkt_errs; + +#ifdef DRXJ_SIGNAL_ACCUM_ERR + rc = get_acc_pkt_err(demod, &sig_quality->packet_error); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } +#endif + + return 0; +rw_error: + p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + + return -EIO; +} + +#endif /* #ifndef DRXJ_VSB_ONLY */ + +/*============================================================================*/ +/*== END QAM DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== ATV DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/* + Implementation notes. + + NTSC/FM AGCs + + Four AGCs are used for NTSC: + (1) RF (used to attenuate the input signal in case of to much power) + (2) IF (used to attenuate the input signal in case of to much power) + (3) Video AGC (used to amplify the output signal in case input to low) + (4) SIF AGC (used to amplify the output signal in case input to low) + + Video AGC is coupled to RF and IF. SIF AGC is not coupled. It is assumed + that the coupling between Video AGC and the RF and IF AGCs also works in + favor of the SIF AGC. + + Three AGCs are used for FM: + (1) RF (used to attenuate the input signal in case of to much power) + (2) IF (used to attenuate the input signal in case of to much power) + (3) SIF AGC (used to amplify the output signal in case input to low) + + The SIF AGC is now coupled to the RF/IF AGCs. + The SIF AGC is needed for both SIF ouput and the internal SIF signal to + the AUD block. + + RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of + the ATV block. The AGC control algorithms are all implemented in + microcode. + + ATV SETTINGS + + (Shadow settings will not be used for now, they will be implemented + later on because of the schedule) + + Several HW/SCU "settings" can be used for ATV. The standard selection + will reset most of these settings. To avoid that the end user apllication + has to perform these settings each time the ATV or FM standards is + selected the driver will shadow these settings. This enables the end user + to perform the settings only once after a drx_open(). The driver must + write the shadow settings to HW/SCU incase: + ( setstandard FM/ATV) || + ( settings have changed && FM/ATV standard is active) + The shadow settings will be stored in the device specific data container. + A set of flags will be defined to flag changes in shadow settings. + A routine will be implemented to write all changed shadow settings to + HW/SCU. + + The "settings" will consist of: AGC settings, filter settings etc. + + Disadvantage of use of shadow settings: + Direct changes in HW/SCU registers will not be reflected in the + shadow settings and these changes will be overwritten during a next + update. This can happen during evaluation. This will not be a problem + for normal customer usage. +*/ +/* -------------------------------------------------------------------------- */ + +/** +* \fn int power_down_atv () +* \brief Power down ATV. +* \param demod instance of demodulator +* \param standard either NTSC or FM (sub strandard for ATV ) +* \return int. +* +* Stops and thus resets ATV and IQM block +* SIF and CVBS ADC are powered down +* Calls audio power down +*/ +static int +power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxjscu_cmd cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; + int rc; + u16 cmd_result = 0; + + /* ATV NTSC */ + + /* Stop ATV SCU (will reset ATV and IQM hardware */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Disable ATV outputs (ATV reset enables CVBS, undo this) */ + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (primary) { + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_iqm_af(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = power_down_aud(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ + +/** +* \brief Power up AUD. +* \param demod instance of demodulator +* \return int. +* +*/ +static int power_down_aud(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + int rc; + + dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + ext_attr->aud_data.audio_is_active = false; + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn int set_orx_nsu_aox() +* \brief Configure OrxNsuAox for OOB +* \param demod instance of demodulator. +* \param active +* \return int. +*/ +static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + u16 data = 0; + + /* Configure NSU_AOX */ + rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (!active) + data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON)); + else + data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON); + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return -EIO; +} + +/** +* \fn int ctrl_set_oob() +* \brief Set OOB channel to be used. +* \param demod instance of demodulator +* \param oob_param OOB parameters for channel setting. +* \frequency should be in KHz +* \return int. +* +* Accepts only. Returns error otherwise. +* Demapper value is written after scu_command START +* because START command causes COMM_EXEC transition +* from 0 to 1 which causes all registers to be +* overwritten with initial value +* +*/ + +/* Nyquist filter impulse response */ +#define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */ +#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */ +#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */ + +/* Coefficients for the nyquist fitler (total: 27 taps) */ +#define NYQFILTERLEN 27 + +static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param) +{ + int rc; + s32 freq = 0; /* KHz */ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + u16 i = 0; + bool mirror_freq_spect_oob = false; + u16 trk_filter_value = 0; + struct drxjscu_cmd scu_cmd; + u16 set_param_parameters[3]; + u16 cmd_result[2] = { 0, 0 }; + s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = { + IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */ + IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */ + IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */ + IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */ + }; + u8 mode_val[4] = { 2, 2, 0, 1 }; + u8 pfi_coeffs[4][6] = { + {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */ + {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */ + {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ + {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ + }; + u16 mode_index; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob; + + /* Check parameters */ + if (oob_param == NULL) { + /* power off oob module */ + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_STOP; + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_orx_nsu_aox(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + ext_attr->oob_power_on = false; + return 0; + } + + freq = oob_param->frequency; + if ((freq < 70000) || (freq > 130000)) + return -EIO; + freq = (freq - 50000) / 50; + + { + u16 index = 0; + u16 remainder = 0; + u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg; + + index = (u16) ((freq - 400) / 200); + remainder = (u16) ((freq - 400) % 200); + trk_filter_value = + trk_filtercfg[index] - (trk_filtercfg[index] - + trk_filtercfg[index + + 1]) / 10 * remainder / + 20; + } + + /*********/ + /* Stop */ + /*********/ + rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_STOP; + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /*********/ + /* Reset */ + /*********/ + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_RESET; + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /***********/ + /* SET_ENV */ + /***********/ + /* set frequency, spectrum inversion and data rate */ + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + scu_cmd.parameter_len = 3; + /* 1-data rate;2-frequency */ + switch (oob_param->standard) { + case DRX_OOB_MODE_A: + if ( + /* signal is transmitted inverted */ + ((oob_param->spectrum_inverted == true) && + /* and tuner is not mirroring the signal */ + (!mirror_freq_spect_oob)) | + /* or */ + /* signal is transmitted noninverted */ + ((oob_param->spectrum_inverted == false) && + /* and tuner is mirroring the signal */ + (mirror_freq_spect_oob)) + ) + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC; + else + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC; + break; + case DRX_OOB_MODE_B_GRADE_A: + if ( + /* signal is transmitted inverted */ + ((oob_param->spectrum_inverted == true) && + /* and tuner is not mirroring the signal */ + (!mirror_freq_spect_oob)) | + /* or */ + /* signal is transmitted noninverted */ + ((oob_param->spectrum_inverted == false) && + /* and tuner is mirroring the signal */ + (mirror_freq_spect_oob)) + ) + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC; + else + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC; + break; + case DRX_OOB_MODE_B_GRADE_B: + default: + if ( + /* signal is transmitted inverted */ + ((oob_param->spectrum_inverted == true) && + /* and tuner is not mirroring the signal */ + (!mirror_freq_spect_oob)) | + /* or */ + /* signal is transmitted noninverted */ + ((oob_param->spectrum_inverted == false) && + /* and tuner is mirroring the signal */ + (mirror_freq_spect_oob)) + ) + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC; + else + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC; + break; + } + set_param_parameters[1] = (u16) (freq & 0xFFFF); + set_param_parameters[2] = trk_filter_value; + scu_cmd.parameter = set_param_parameters; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6]; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write magic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write magic word to disable pdr reg write */ + + rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* ddc */ + rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* nsu */ + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* initialization for target mode */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Reset bits for timing and freq. recovery */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* PRE-Filter coefficients (PFI) */ + rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* NYQUIST-Filter coefficients (NYQ) */ + for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) { + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /*********/ + /* Start */ + /*********/ + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_START; + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = set_orx_nsu_aox(demod, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + ext_attr->oob_power_on = true; + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ +/*== END OOB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================= + ===== MC command related functions ========================================== + ===========================================================================*/ + +/*============================================================================= + ===== ctrl_set_channel() ========================================================== + ===========================================================================*/ +/** +* \fn int ctrl_set_channel() +* \brief Select a new transmission channel. +* \param demod instance of demod. +* \param channel Pointer to channel data. +* \return int. +* +* In case the tuner module is not used and in case of NTSC/FM the pogrammer +* must tune the tuner to the centre frequency of the NTSC/FM channel. +* +*/ +static int +ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) +{ + int rc; + s32 tuner_freq_offset = 0; + struct drxj_data *ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; +#ifndef DRXJ_VSB_ONLY + u32 min_symbol_rate = 0; + u32 max_symbol_rate = 0; + int bandwidth_temp = 0; + int bandwidth = 0; +#endif + /*== check arguments ======================================================*/ + if ((demod == NULL) || (channel == NULL)) + return -EINVAL; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + standard = ext_attr->standard; + + /* check valid standards */ + switch (standard) { + case DRX_STANDARD_8VSB: +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: +#endif /* DRXJ_VSB_ONLY */ + break; + case DRX_STANDARD_UNKNOWN: + default: + return -EINVAL; + } + + /* check bandwidth QAM annex B, NTSC and 8VSB */ + if ((standard == DRX_STANDARD_ITU_B) || + (standard == DRX_STANDARD_8VSB) || + (standard == DRX_STANDARD_NTSC)) { + switch (channel->bandwidth) { + case DRX_BANDWIDTH_6MHZ: + case DRX_BANDWIDTH_UNKNOWN: /* fall through */ + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + break; + case DRX_BANDWIDTH_8MHZ: /* fall through */ + case DRX_BANDWIDTH_7MHZ: /* fall through */ + default: + return -EINVAL; + } + } + + /* For QAM annex A and annex C: + -check symbolrate and constellation + -derive bandwidth from symbolrate (input bandwidth is ignored) + */ +#ifndef DRXJ_VSB_ONLY + if ((standard == DRX_STANDARD_ITU_A) || + (standard == DRX_STANDARD_ITU_C)) { + struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW }; + int bw_rolloff_factor = 0; + + bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113; + min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN; + max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX; + /* config SMA_TX pin to SAW switch mode */ + rc = ctrl_set_uio_cfg(demod, &uio_cfg); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (channel->symbolrate < min_symbol_rate || + channel->symbolrate > max_symbol_rate) { + return -EINVAL; + } + + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM16: /* fall through */ + case DRX_CONSTELLATION_QAM32: /* fall through */ + case DRX_CONSTELLATION_QAM64: /* fall through */ + case DRX_CONSTELLATION_QAM128: /* fall through */ + case DRX_CONSTELLATION_QAM256: + bandwidth_temp = channel->symbolrate * bw_rolloff_factor; + bandwidth = bandwidth_temp / 100; + + if ((bandwidth_temp % 100) >= 50) + bandwidth++; + + if (bandwidth <= 6100000) { + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + } else if ((bandwidth > 6100000) + && (bandwidth <= 7100000)) { + channel->bandwidth = DRX_BANDWIDTH_7MHZ; + } else if (bandwidth > 7100000) { + channel->bandwidth = DRX_BANDWIDTH_8MHZ; + } + break; + default: + return -EINVAL; + } + } + + /* For QAM annex B: + -check constellation + */ + if (standard == DRX_STANDARD_ITU_B) { + switch (channel->constellation) { + case DRX_CONSTELLATION_AUTO: + case DRX_CONSTELLATION_QAM256: + case DRX_CONSTELLATION_QAM64: + break; + default: + return -EINVAL; + } + + switch (channel->interleavemode) { + case DRX_INTERLEAVEMODE_I128_J1: + case DRX_INTERLEAVEMODE_I128_J1_V2: + case DRX_INTERLEAVEMODE_I128_J2: + case DRX_INTERLEAVEMODE_I64_J2: + case DRX_INTERLEAVEMODE_I128_J3: + case DRX_INTERLEAVEMODE_I32_J4: + case DRX_INTERLEAVEMODE_I128_J4: + case DRX_INTERLEAVEMODE_I16_J8: + case DRX_INTERLEAVEMODE_I128_J5: + case DRX_INTERLEAVEMODE_I8_J16: + case DRX_INTERLEAVEMODE_I128_J6: + case DRX_INTERLEAVEMODE_I128_J7: + case DRX_INTERLEAVEMODE_I128_J8: + case DRX_INTERLEAVEMODE_I12_J17: + case DRX_INTERLEAVEMODE_I5_J4: + case DRX_INTERLEAVEMODE_B52_M240: + case DRX_INTERLEAVEMODE_B52_M720: + case DRX_INTERLEAVEMODE_UNKNOWN: + case DRX_INTERLEAVEMODE_AUTO: + break; + default: + return -EINVAL; + } + } + + if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) { + /* SAW SW, user UIO is used for switchable SAW */ + struct drxuio_data uio1 = { DRX_UIO1, false }; + + switch (channel->bandwidth) { + case DRX_BANDWIDTH_8MHZ: + uio1.value = true; + break; + case DRX_BANDWIDTH_7MHZ: + uio1.value = false; + break; + case DRX_BANDWIDTH_6MHZ: + uio1.value = false; + break; + case DRX_BANDWIDTH_UNKNOWN: + default: + return -EINVAL; + } + + rc = ctrl_uio_write(demod, &uio1); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } +#endif /* DRXJ_VSB_ONLY */ + rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + tuner_freq_offset = 0; + + /*== Setup demod for specific standard ====================================*/ + switch (standard) { + case DRX_STANDARD_8VSB: + if (channel->mirror == DRX_MIRROR_AUTO) + ext_attr->mirror = DRX_MIRROR_NO; + else + ext_attr->mirror = channel->mirror; + rc = set_vsb(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_frequency(demod, channel, tuner_freq_offset); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + rc = set_qam_channel(demod, channel, tuner_freq_offset); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; +#endif + case DRX_STANDARD_UNKNOWN: + default: + return -EIO; + } + + /* flag the packet error counter reset */ + ext_attr->reset_pkt_err_acc = true; + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================= + ===== SigQuality() ========================================================== + ===========================================================================*/ + +/** +* \fn int ctrl_sig_quality() +* \brief Retreive signal quality form device. +* \param devmod Pointer to demodulator instance. +* \param sig_quality Pointer to signal quality data. +* \return int. +* \retval 0 sig_quality contains valid data. +* \retval -EINVAL sig_quality is NULL. +* \retval -EIO Erroneous data, sig_quality contains invalid data. + +*/ +static int +ctrl_sig_quality(struct drx_demod_instance *demod, + enum drx_lock_status lock_status) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxj_data *ext_attr = demod->my_ext_attr; + struct drx39xxj_state *state = dev_addr->user_data; + struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; + enum drx_standard standard = ext_attr->standard; + int rc; + u32 ber, cnt, err, pkt; + u16 mer, strength; + + rc = get_sig_strength(demod, &strength); + if (rc < 0) { + pr_err("error getting signal strength %d\n", rc); + p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->strength.stat[0].scale = FE_SCALE_RELATIVE; + p->strength.stat[0].uvalue = 65535UL * strength/ 100; + } + + switch (standard) { + case DRX_STANDARD_8VSB: +#ifdef DRXJ_SIGNAL_ACCUM_ERR + rc = get_acc_pkt_err(demod, &pkt); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } +#endif + if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { + p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt); + if (rc != 0) { + pr_err("error %d getting UCB\n", rc); + p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->block_error.stat[0].scale = FE_SCALE_COUNTER; + p->block_error.stat[0].uvalue += err; + p->block_count.stat[0].scale = FE_SCALE_COUNTER; + p->block_count.stat[0].uvalue += pkt; + } + + /* PostViterbi is compute in steps of 10^(-6) */ + rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt); + if (rc != 0) { + pr_err("error %d getting pre-ber\n", rc); + p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; + p->pre_bit_error.stat[0].uvalue += ber; + p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; + p->pre_bit_count.stat[0].uvalue += cnt; + } + + rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt); + if (rc != 0) { + pr_err("error %d getting post-ber\n", rc); + p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; + p->post_bit_error.stat[0].uvalue += ber; + p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; + p->post_bit_count.stat[0].uvalue += cnt; + } + rc = get_vsbmer(dev_addr, &mer); + if (rc != 0) { + pr_err("error %d getting MER\n", rc); + p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->cnr.stat[0].svalue = mer * 100; + p->cnr.stat[0].scale = FE_SCALE_DECIBEL; + } + } + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + rc = ctrl_get_qam_sig_quality(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; +#endif + default: + return -EIO; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ + +/** +* \fn int ctrl_lock_status() +* \brief Retreive lock status . +* \param dev_addr Pointer to demodulator device address. +* \param lock_stat Pointer to lock status structure. +* \return int. +* +*/ +static int +ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat) +{ + enum drx_standard standard = DRX_STANDARD_UNKNOWN; + struct drxj_data *ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; + struct drxjscu_cmd cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; + int rc; + u16 cmd_result[2] = { 0, 0 }; + u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; + + /* check arguments */ + if ((demod == NULL) || (lock_stat == NULL)) + return -EINVAL; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + standard = ext_attr->standard; + + *lock_stat = DRX_NOT_LOCKED; + + /* define the SCU command code */ + switch (standard) { + case DRX_STANDARD_8VSB: + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + demod_lock |= 0x6; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + break; +#endif + case DRX_STANDARD_UNKNOWN: /* fallthrough */ + default: + return -EIO; + } + + /* define the SCU command paramters and execute the command */ + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 2; + cmd_scu.parameter = NULL; + cmd_scu.result = cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* set the lock status */ + if (cmd_scu.result[1] < demod_lock) { + /* 0x0000 NOT LOCKED */ + *lock_stat = DRX_NOT_LOCKED; + } else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) { + *lock_stat = DRXJ_DEMOD_LOCK; + } else if (cmd_scu.result[1] < + SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) { + /* 0x8000 DEMOD + FEC LOCKED (system lock) */ + *lock_stat = DRX_LOCKED; + } else { + /* 0xC000 NEVER LOCKED */ + /* (system will never be able to lock to the signal) */ + *lock_stat = DRX_NEVER_LOCK; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ + +/** +* \fn int ctrl_set_standard() +* \brief Set modulation standard to be used. +* \param standard Modulation standard. +* \return int. +* +* Setup stuff for the desired demodulation standard. +* Disable and power down the previous selected demodulation standard +* +*/ +static int +ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) +{ + struct drxj_data *ext_attr = NULL; + int rc; + enum drx_standard prev_standard; + + /* check arguments */ + if ((standard == NULL) || (demod == NULL)) + return -EINVAL; + + ext_attr = (struct drxj_data *) demod->my_ext_attr; + prev_standard = ext_attr->standard; + + /* + Stop and power down previous standard + */ + switch (prev_standard) { +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + rc = power_down_qam(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; +#endif + case DRX_STANDARD_8VSB: + rc = power_down_vsb(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_STANDARD_UNKNOWN: + /* Do nothing */ + break; + case DRX_STANDARD_AUTO: /* fallthrough */ + default: + return -EINVAL; + } + + /* + Initialize channel independent registers + Power up new standard + */ + ext_attr->standard = *standard; + + switch (*standard) { +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + do { + u16 dummy; + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } while (0); + break; +#endif + case DRX_STANDARD_8VSB: + rc = set_vsb_leak_n_gain(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + ext_attr->standard = DRX_STANDARD_UNKNOWN; + return -EINVAL; + break; + } + + return 0; +rw_error: + /* Don't know what the standard is now ... try again */ + ext_attr->standard = DRX_STANDARD_UNKNOWN; + return -EIO; +} + +/*============================================================================*/ + +static void drxj_reset_mode(struct drxj_data *ext_attr) +{ + /* Initialize default AFE configuartion for QAM */ + if (ext_attr->has_lna) { + /* IF AGC off, PGA active */ +#ifndef DRXJ_VSB_ONLY + ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; + ext_attr->qam_pga_cfg = 140 + (11 * 13); +#endif + ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; + ext_attr->vsb_pga_cfg = 140 + (11 * 13); + } else { + /* IF AGC on, PGA not active */ +#ifndef DRXJ_VSB_ONLY + ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->qam_if_agc_cfg.min_output_level = 0; + ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF; + ext_attr->qam_if_agc_cfg.speed = 3; + ext_attr->qam_if_agc_cfg.top = 1297; + ext_attr->qam_pga_cfg = 140; +#endif + ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->vsb_if_agc_cfg.min_output_level = 0; + ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF; + ext_attr->vsb_if_agc_cfg.speed = 3; + ext_attr->vsb_if_agc_cfg.top = 1024; + ext_attr->vsb_pga_cfg = 140; + } + /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */ + /* mc has not used them */ +#ifndef DRXJ_VSB_ONLY + ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->qam_rf_agc_cfg.min_output_level = 0; + ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF; + ext_attr->qam_rf_agc_cfg.speed = 3; + ext_attr->qam_rf_agc_cfg.top = 9500; + ext_attr->qam_rf_agc_cfg.cut_off_current = 4000; + ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_pre_saw_cfg.reference = 0x07; + ext_attr->qam_pre_saw_cfg.use_pre_saw = true; +#endif + /* Initialize default AFE configuartion for VSB */ + ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->vsb_rf_agc_cfg.min_output_level = 0; + ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF; + ext_attr->vsb_rf_agc_cfg.speed = 3; + ext_attr->vsb_rf_agc_cfg.top = 9500; + ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000; + ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_pre_saw_cfg.reference = 0x07; + ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; +} + +/** +* \fn int ctrl_power_mode() +* \brief Set the power mode of the device to the specified power mode +* \param demod Pointer to demodulator instance. +* \param mode Pointer to new power mode. +* \return int. +* \retval 0 Success +* \retval -EIO I2C error or other failure +* \retval -EINVAL Invalid mode argument. +* +* +*/ +static int +ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) +{ + struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; + int rc; + u16 sio_cc_pwd_mode = 0; + + common_attr = (struct drx_common_attr *) demod->my_common_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; + + /* Check arguments */ + if (mode == NULL) + return -EINVAL; + + /* If already in requested power mode, do nothing */ + if (common_attr->current_power_mode == *mode) + return 0; + + switch (*mode) { + case DRX_POWER_UP: + case DRXJ_POWER_DOWN_MAIN_PATH: + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE; + break; + case DRXJ_POWER_DOWN_CORE: + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK; + break; + case DRXJ_POWER_DOWN_PLL: + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL; + break; + case DRX_POWER_DOWN: + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC; + break; + default: + /* Unknow sleep mode */ + return -EINVAL; + break; + } + + /* Check if device needs to be powered up */ + if ((common_attr->current_power_mode != DRX_POWER_UP)) { + rc = power_up_device(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + if ((*mode == DRX_POWER_UP)) { + /* Restore analog & pin configuartion */ + + /* Initialize default AFE configuartion for VSB */ + drxj_reset_mode(ext_attr); + } else { + /* Power down to requested mode */ + /* Backup some register settings */ + /* Set pins with possible pull-ups connected to them in input mode */ + /* Analog power down */ + /* ADC power down */ + /* Power down device */ + /* stop all comm_exec */ + /* + Stop and power down previous standard + */ + + switch (ext_attr->standard) { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + rc = power_down_qam(demod, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_STANDARD_8VSB: + rc = power_down_vsb(demod, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: + rc = power_down_atv(demod, ext_attr->standard, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_STANDARD_UNKNOWN: + /* Do nothing */ + break; + case DRX_STANDARD_AUTO: /* fallthrough */ + default: + return -EIO; + } + ext_attr->standard = DRX_STANDARD_UNKNOWN; + } + + if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) { + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if ((*mode != DRX_POWER_UP)) { + /* Initialize HI, wakeup key especially before put IC to sleep */ + rc = init_hi(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + rc = hi_cfg_command(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + } + + common_attr->current_power_mode = *mode; + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ +/*== CTRL Set/Get Config related functions ===================================*/ +/*============================================================================*/ + +/** +* \fn int ctrl_set_cfg_pre_saw() +* \brief Set Pre-saw reference. +* \param demod demod instance +* \param u16 * +* \return int. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static int +ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + int rc; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + /* check arguments */ + if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M) + ) { + return -EINVAL; + } + + /* Only if standard is currently active */ + if ((ext_attr->standard == pre_saw->standard) || + (DRXJ_ISQAMSTD(ext_attr->standard) && + DRXJ_ISQAMSTD(pre_saw->standard)) || + (DRXJ_ISATVSTD(ext_attr->standard) && + DRXJ_ISATVSTD(pre_saw->standard))) { + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* Store pre-saw settings */ + switch (pre_saw->standard) { + case DRX_STANDARD_8VSB: + ext_attr->vsb_pre_saw_cfg = *pre_saw; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + ext_attr->qam_pre_saw_cfg = *pre_saw; + break; +#endif + default: + return -EINVAL; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ + +/** +* \fn int ctrl_set_cfg_afe_gain() +* \brief Set AFE Gain. +* \param demod demod instance +* \param u16 * +* \return int. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static int +ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + int rc; + u8 gain = 0; + + /* check arguments */ + if (afe_gain == NULL) + return -EINVAL; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + switch (afe_gain->standard) { + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif + /* Do nothing */ + break; + default: + return -EINVAL; + } + + /* TODO PGA gain is also written by microcode (at least by QAM and VSB) + So I (PJ) think interface requires choice between auto, user mode */ + + if (afe_gain->gain >= 329) + gain = 15; + else if (afe_gain->gain <= 147) + gain = 0; + else + gain = (afe_gain->gain - 140 + 6) / 13; + + /* Only if standard is currently active */ + if (ext_attr->standard == afe_gain->standard) { + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* Store AFE Gain settings */ + switch (afe_gain->standard) { + case DRX_STANDARD_8VSB: + ext_attr->vsb_pga_cfg = gain * 13 + 140; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + ext_attr->qam_pga_cfg = gain * 13 + 140; + break; +#endif + default: + return -EIO; + } + + return 0; +rw_error: + return -EIO; +} + +/*============================================================================*/ + + +/*============================================================================= +===== EXPORTED FUNCTIONS ====================================================*/ + +static int drx_ctrl_u_code(struct drx_demod_instance *demod, + struct drxu_code_info *mc_info, + enum drxu_code_action action); + +/** +* \fn drxj_open() +* \brief Open the demod instance, configure device, configure drxdriver +* \return Status_t Return status. +* +* drxj_open() can be called with a NULL ucode image => no ucode upload. +* This means that drxj_open() must NOT contain SCU commands or, in general, +* rely on SCU or AUD ucode to be present. +* +*/ + +static int drxj_open(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + struct drx_common_attr *common_attr = NULL; + u32 driver_version = 0; + struct drxu_code_info ucode_info; + struct drx_cfg_mpeg_output cfg_mpeg_output; + int rc; + enum drx_power_mode power_mode = DRX_POWER_UP; + + if ((demod == NULL) || + (demod->my_common_attr == NULL) || + (demod->my_ext_attr == NULL) || + (demod->my_i2c_dev_addr == NULL) || + (demod->my_common_attr->is_opened)) { + return -EINVAL; + } + + /* Check arguments */ + if (demod->my_ext_attr == NULL) + return -EINVAL; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; + + rc = ctrl_power_mode(demod, &power_mode); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (power_mode != DRX_POWER_UP) { + rc = -EINVAL; + pr_err("failed to powerup device\n"); + goto rw_error; + } + + /* has to be in front of setIqmAf and setOrxNsuAox */ + rc = get_device_capabilities(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* + * Soft reset of sys- and osc-clockdomain + * + * HACK: On windows, it writes a 0x07 here, instead of just 0x03. + * As we didn't load the firmware here yet, we should do the same. + * Btw, this is coherent with DRX-K, where we send reset codes + * for modulation (OFTM, in DRX-k), SYS and OSC clock domains. + */ + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + msleep(1); + + /* TODO first make sure that everything keeps working before enabling this */ + /* PowerDownAnalogBlocks() */ + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = set_iqm_af(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_orx_nsu_aox(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = init_hi(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* disable mpegoutput pins */ + memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); + cfg_mpeg_output.enable_mpeg_output = false; + + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Stop AUD Inform SetAudio it will need to do all setting */ + rc = power_down_aud(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Stop SCU */ + rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Upload microcode */ + if (common_attr->microcode_file != NULL) { + /* Dirty trick to use common ucode upload & verify, + pretend device is already open */ + common_attr->is_opened = true; + ucode_info.mc_file = common_attr->microcode_file; + + if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) { + pr_err("Should powerup before loading the firmware."); + return -EINVAL; + } + + rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD); + if (rc != 0) { + pr_err("error %d while uploading the firmware\n", rc); + goto rw_error; + } + if (common_attr->verify_microcode == true) { + rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY); + if (rc != 0) { + pr_err("error %d while verifying the firmware\n", + rc); + goto rw_error; + } + } + common_attr->is_opened = false; + } + + /* Run SCU for a little while to initialize microcode version numbers */ + rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Initialize scan timeout */ + common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT; + common_attr->scan_desired_lock = DRX_LOCKED; + + drxj_reset_mode(ext_attr); + ext_attr->standard = DRX_STANDARD_UNKNOWN; + + rc = smart_ant_init(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Stamp driver version number in SCU data RAM in BCD code + Done to enable field application engineers to retreive drxdriver version + via I2C from SCU RAM + */ + driver_version = (VERSION_MAJOR / 100) % 10; + driver_version <<= 4; + driver_version += (VERSION_MAJOR / 10) % 10; + driver_version <<= 4; + driver_version += (VERSION_MAJOR % 10); + driver_version <<= 4; + driver_version += (VERSION_MINOR % 10); + driver_version <<= 4; + driver_version += (VERSION_PATCH / 1000) % 10; + driver_version <<= 4; + driver_version += (VERSION_PATCH / 100) % 10; + driver_version <<= 4; + driver_version += (VERSION_PATCH / 10) % 10; + driver_version <<= 4; + driver_version += (VERSION_PATCH % 10); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = ctrl_set_oob(demod, NULL); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* refresh the audio data structure with default */ + ext_attr->aud_data = drxj_default_aud_data_g; + + demod->my_common_attr->is_opened = true; + return 0; +rw_error: + common_attr->is_opened = false; + return -EIO; +} + +/*============================================================================*/ +/** +* \fn drxj_close() +* \brief Close the demod instance, power down the device +* \return Status_t Return status. +* +*/ +static int drxj_close(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + enum drx_power_mode power_mode = DRX_POWER_UP; + + if ((demod->my_common_attr == NULL) || + (demod->my_ext_attr == NULL) || + (demod->my_i2c_dev_addr == NULL) || + (!demod->my_common_attr->is_opened)) { + return -EINVAL; + } + + /* power up */ + rc = ctrl_power_mode(demod, &power_mode); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + power_mode = DRX_POWER_DOWN; + rc = ctrl_power_mode(demod, &power_mode); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + DRX_ATTR_ISOPENED(demod) = false; + + return 0; +rw_error: + DRX_ATTR_ISOPENED(demod) = false; + + return -EIO; +} + +/* + * Microcode related functions + */ + +/** + * drx_u_code_compute_crc - Compute CRC of block of microcode data. + * @block_data: Pointer to microcode data. + * @nr_words: Size of microcode block (number of 16 bits words). + * + * returns The computed CRC residue. + */ +static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words) +{ + u16 i = 0; + u16 j = 0; + u32 crc_word = 0; + u32 carry = 0; + + while (i < nr_words) { + crc_word |= (u32)be16_to_cpu(*(u32 *)(block_data)); + for (j = 0; j < 16; j++) { + crc_word <<= 1; + if (carry != 0) + crc_word ^= 0x80050000UL; + carry = crc_word & 0x80000000UL; + } + i++; + block_data += (sizeof(u16)); + } + return (u16)(crc_word >> 16); +} + +/** + * drx_check_firmware - checks if the loaded firmware is valid + * + * @demod: demod structure + * @mc_data: pointer to the start of the firmware + * @size: firmware size + */ +static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data, + unsigned size) +{ + struct drxu_code_block_hdr block_hdr; + int i; + unsigned count = 2 * sizeof(u16); + u32 mc_dev_type, mc_version, mc_base_version; + u16 mc_nr_of_blks = be16_to_cpu(*(u32 *)(mc_data + sizeof(u16))); + + /* + * Scan microcode blocks first for version info + * and firmware check + */ + + /* Clear version block */ + DRX_ATTR_MCRECORD(demod).aux_type = 0; + DRX_ATTR_MCRECORD(demod).mc_dev_type = 0; + DRX_ATTR_MCRECORD(demod).mc_version = 0; + DRX_ATTR_MCRECORD(demod).mc_base_version = 0; + + for (i = 0; i < mc_nr_of_blks; i++) { + if (count + 3 * sizeof(u16) + sizeof(u32) > size) + goto eof; + + /* Process block header */ + block_hdr.addr = be32_to_cpu(*(u32 *)(mc_data + count)); + count += sizeof(u32); + block_hdr.size = be16_to_cpu(*(u32 *)(mc_data + count)); + count += sizeof(u16); + block_hdr.flags = be16_to_cpu(*(u32 *)(mc_data + count)); + count += sizeof(u16); + block_hdr.CRC = be16_to_cpu(*(u32 *)(mc_data + count)); + count += sizeof(u16); + + pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", + count, block_hdr.addr, block_hdr.size, block_hdr.flags, + block_hdr.CRC); + + if (block_hdr.flags & 0x8) { + u8 *auxblk = ((void *)mc_data) + block_hdr.addr; + u16 auxtype; + + if (block_hdr.addr + sizeof(u16) > size) + goto eof; + + auxtype = be16_to_cpu(*(u32 *)(auxblk)); + + /* Aux block. Check type */ + if (DRX_ISMCVERTYPE(auxtype)) { + if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size) + goto eof; + + auxblk += sizeof(u16); + mc_dev_type = be32_to_cpu(*(u32 *)(auxblk)); + auxblk += sizeof(u32); + mc_version = be32_to_cpu(*(u32 *)(auxblk)); + auxblk += sizeof(u32); + mc_base_version = be32_to_cpu(*(u32 *)(auxblk)); + + DRX_ATTR_MCRECORD(demod).aux_type = auxtype; + DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type; + DRX_ATTR_MCRECORD(demod).mc_version = mc_version; + DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version; + + pr_info("Firmware dev %x, ver %x, base ver %x\n", + mc_dev_type, mc_version, mc_base_version); + + } + } else if (count + block_hdr.size * sizeof(u16) > size) + goto eof; + + count += block_hdr.size * sizeof(u16); + } + return 0; +eof: + pr_err("Firmware is truncated at pos %u/%u\n", count, size); + return -EINVAL; +} + +/** + * drx_ctrl_u_code - Handle microcode upload or verify. + * @dev_addr: Address of device. + * @mc_info: Pointer to information about microcode data. + * @action: Either UCODE_UPLOAD or UCODE_VERIFY + * + * This function returns: + * 0: + * - In case of UCODE_UPLOAD: code is successfully uploaded. + * - In case of UCODE_VERIFY: image on device is equal to + * image provided to this control function. + * -EIO: + * - In case of UCODE_UPLOAD: I2C error. + * - In case of UCODE_VERIFY: I2C error or image on device + * is not equal to image provided to this control function. + * -EINVAL: + * - Invalid arguments. + * - Provided image is corrupt + */ +static int drx_ctrl_u_code(struct drx_demod_instance *demod, + struct drxu_code_info *mc_info, + enum drxu_code_action action) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + u16 i = 0; + u16 mc_nr_of_blks = 0; + u16 mc_magic_word = 0; + const u8 *mc_data_init = NULL; + u8 *mc_data = NULL; + unsigned size; + char *mc_file; + + /* Check arguments */ + if (!mc_info || !mc_info->mc_file) + return -EINVAL; + + mc_file = mc_info->mc_file; + + if (!demod->firmware) { + const struct firmware *fw = NULL; + + rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); + if (rc < 0) { + pr_err("Couldn't read firmware %s\n", mc_file); + return rc; + } + demod->firmware = fw; + + if (demod->firmware->size < 2 * sizeof(u16)) { + rc = -EINVAL; + pr_err("Firmware is too short!\n"); + goto release; + } + + pr_info("Firmware %s, size %zu\n", + mc_file, demod->firmware->size); + } + + mc_data_init = demod->firmware->data; + size = demod->firmware->size; + + mc_data = (void *)mc_data_init; + /* Check data */ + mc_magic_word = be16_to_cpu(*(u32 *)(mc_data)); + mc_data += sizeof(u16); + mc_nr_of_blks = be16_to_cpu(*(u32 *)(mc_data)); + mc_data += sizeof(u16); + + if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { + rc = -EINVAL; + pr_err("Firmware magic word doesn't match\n"); + goto release; + } + + if (action == UCODE_UPLOAD) { + rc = drx_check_firmware(demod, (u8 *)mc_data_init, size); + if (rc) + goto release; + pr_info("Uploading firmware %s\n", mc_file); + } else { + pr_info("Verifying if firmware upload was ok.\n"); + } + + /* Process microcode blocks */ + for (i = 0; i < mc_nr_of_blks; i++) { + struct drxu_code_block_hdr block_hdr; + u16 mc_block_nr_bytes = 0; + + /* Process block header */ + block_hdr.addr = be32_to_cpu(*(u32 *)(mc_data)); + mc_data += sizeof(u32); + block_hdr.size = be16_to_cpu(*(u32 *)(mc_data)); + mc_data += sizeof(u16); + block_hdr.flags = be16_to_cpu(*(u32 *)(mc_data)); + mc_data += sizeof(u16); + block_hdr.CRC = be16_to_cpu(*(u32 *)(mc_data)); + mc_data += sizeof(u16); + + pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", + (unsigned)(mc_data - mc_data_init), block_hdr.addr, + block_hdr.size, block_hdr.flags, block_hdr.CRC); + + /* Check block header on: + - data larger than 64Kb + - if CRC enabled check CRC + */ + if ((block_hdr.size > 0x7FFF) || + (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) && + (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size))) + ) { + /* Wrong data ! */ + rc = -EINVAL; + pr_err("firmware CRC is wrong\n"); + goto release; + } + + if (!block_hdr.size) + continue; + + mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16)); + + /* Perform the desired action */ + switch (action) { + case UCODE_UPLOAD: /* Upload microcode */ + if (drxdap_fasi_write_block(dev_addr, + block_hdr.addr, + mc_block_nr_bytes, + mc_data, 0x0000)) { + rc = -EIO; + pr_err("error writing firmware at pos %u\n", + (unsigned)(mc_data - mc_data_init)); + goto release; + } + break; + case UCODE_VERIFY: { /* Verify uploaded microcode */ + int result = 0; + u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE]; + u32 bytes_to_comp = 0; + u32 bytes_left = mc_block_nr_bytes; + u32 curr_addr = block_hdr.addr; + u8 *curr_ptr = mc_data; + + while (bytes_left != 0) { + if (bytes_left > DRX_UCODE_MAX_BUF_SIZE) + bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE; + else + bytes_to_comp = bytes_left; + + if (drxdap_fasi_read_block(dev_addr, + curr_addr, + (u16)bytes_to_comp, + (u8 *)mc_data_buffer, + 0x0000)) { + pr_err("error reading firmware at pos %u\n", + (unsigned)(mc_data - mc_data_init)); + return -EIO; + } + + result = memcmp(curr_ptr, mc_data_buffer, + bytes_to_comp); + + if (result) { + pr_err("error verifying firmware at pos %u\n", + (unsigned)(mc_data - mc_data_init)); + return -EIO; + } + + curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2)); + curr_ptr =&(curr_ptr[bytes_to_comp]); + bytes_left -=((u32) bytes_to_comp); + } + break; + } + default: + return -EINVAL; + break; + + } + mc_data += mc_block_nr_bytes; + } + + return 0; + +release: + release_firmware(demod->firmware); + demod->firmware = NULL; + + return rc; +} + +/* + * The Linux DVB Driver for Micronas DRX39xx family (drx3933j) + * + * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com> + */ + +static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + int result; + enum drx_power_mode power_mode; + + if (enable) + power_mode = DRX_POWER_UP; + else + power_mode = DRX_POWER_DOWN; + + result = ctrl_power_mode(demod, &power_mode); + if (result != 0) { + pr_err("Power state change failed\n"); + return 0; + } + + return 0; +} + +static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + int result; + enum drx_lock_status lock_status; + + *status = 0; + + result = ctrl_lock_status(demod, &lock_status); + if (result != 0) { + pr_err("drx39xxj: could not get lock status!\n"); + *status = 0; + } + + switch (lock_status) { + case DRX_NEVER_LOCK: + *status = 0; + pr_err("drx says NEVER_LOCK\n"); + break; + case DRX_NOT_LOCKED: + *status = 0; + break; + case DRX_LOCK_STATE_1: + case DRX_LOCK_STATE_2: + case DRX_LOCK_STATE_3: + case DRX_LOCK_STATE_4: + case DRX_LOCK_STATE_5: + case DRX_LOCK_STATE_6: + case DRX_LOCK_STATE_7: + case DRX_LOCK_STATE_8: + case DRX_LOCK_STATE_9: + *status = FE_HAS_SIGNAL + | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC; + break; + case DRX_LOCKED: + *status = FE_HAS_SIGNAL + | FE_HAS_CARRIER + | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; + break; + default: + pr_err("Lock state unknown %d\n", lock_status); + } + ctrl_sig_quality(demod, lock_status); + + return 0; +} + +static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + + if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { + *ber = 0; + return 0; + } + + if (!p->pre_bit_count.stat[0].uvalue) { + if (!p->pre_bit_error.stat[0].uvalue) + *ber = 0; + else + *ber = 1000000; + } else { + *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue, + p->pre_bit_count.stat[0].uvalue); + } + return 0; +} + +static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, + u16 *strength) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + + if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { + *strength = 0; + return 0; + } + + *strength = p->strength.stat[0].uvalue; + return 0; +} + +static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + u64 tmp64; + + if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { + *snr = 0; + return 0; + } + + tmp64 = p->cnr.stat[0].svalue; + do_div(tmp64, 10); + *snr = tmp64; + return 0; +} + +static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucb) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + + if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { + *ucb = 0; + return 0; + } + + *ucb = p->block_error.stat[0].uvalue; + return 0; +} + +static int drx39xxj_set_frontend(struct dvb_frontend *fe) +{ +#ifdef DJH_DEBUG + int i; +#endif + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + enum drx_standard standard = DRX_STANDARD_8VSB; + struct drx_channel channel; + int result; + struct drxuio_data uio_data; + static const struct drx_channel def_channel = { + /* frequency */ 0, + /* bandwidth */ DRX_BANDWIDTH_6MHZ, + /* mirror */ DRX_MIRROR_NO, + /* constellation */ DRX_CONSTELLATION_AUTO, + /* hierarchy */ DRX_HIERARCHY_UNKNOWN, + /* priority */ DRX_PRIORITY_UNKNOWN, + /* coderate */ DRX_CODERATE_UNKNOWN, + /* guard */ DRX_GUARD_UNKNOWN, + /* fftmode */ DRX_FFTMODE_UNKNOWN, + /* classification */ DRX_CLASSIFICATION_AUTO, + /* symbolrate */ 5057000, + /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN, + /* ldpc */ DRX_LDPC_UNKNOWN, + /* carrier */ DRX_CARRIER_UNKNOWN, + /* frame mode */ DRX_FRAMEMODE_UNKNOWN + }; + u32 constellation = DRX_CONSTELLATION_AUTO; + + /* Bring the demod out of sleep */ + drx39xxj_set_powerstate(fe, 1); + + if (fe->ops.tuner_ops.set_params) { + u32 int_freq; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + /* Set tuner to desired frequency and standard */ + fe->ops.tuner_ops.set_params(fe); + + /* Use the tuner's IF */ + if (fe->ops.tuner_ops.get_if_frequency) { + fe->ops.tuner_ops.get_if_frequency(fe, &int_freq); + demod->my_common_attr->intermediate_freq = int_freq / 1000; + } + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + } + + switch (p->delivery_system) { + case SYS_ATSC: + standard = DRX_STANDARD_8VSB; + break; + case SYS_DVBC_ANNEX_B: + standard = DRX_STANDARD_ITU_B; + + switch (p->modulation) { + case QAM_64: + constellation = DRX_CONSTELLATION_QAM64; + break; + case QAM_256: + constellation = DRX_CONSTELLATION_QAM256; + break; + default: + constellation = DRX_CONSTELLATION_AUTO; + break; + } + break; + default: + return -EINVAL; + } + /* Set the standard (will be powered up if necessary */ + result = ctrl_set_standard(demod, &standard); + if (result != 0) { + pr_err("Failed to set standard! result=%02x\n", + result); + return -EINVAL; + } + + /* set channel parameters */ + channel = def_channel; + channel.frequency = p->frequency / 1000; + channel.bandwidth = DRX_BANDWIDTH_6MHZ; + channel.constellation = constellation; + + /* program channel */ + result = ctrl_set_channel(demod, &channel); + if (result != 0) { + pr_err("Failed to set channel!\n"); + return -EINVAL; + } + /* Just for giggles, let's shut off the LNA again.... */ + uio_data.uio = DRX_UIO1; + uio_data.value = false; + result = ctrl_uio_write(demod, &uio_data); + if (result != 0) { + pr_err("Failed to disable LNA!\n"); + return 0; + } + + /* After set_frontend, except for strength, stats aren't available */ + p->strength.stat[0].scale = FE_SCALE_RELATIVE; + + return 0; +} + +static int drx39xxj_sleep(struct dvb_frontend *fe) +{ + /* power-down the demodulator */ + return drx39xxj_set_powerstate(fe, 0); +} + +static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + bool i2c_gate_state; + int result; + +#ifdef DJH_DEBUG + pr_debug("i2c gate call: enable=%d state=%d\n", enable, + state->i2c_gate_open); +#endif + + if (enable) + i2c_gate_state = true; + else + i2c_gate_state = false; + + if (state->i2c_gate_open == enable) { + /* We're already in the desired state */ + return 0; + } + + result = ctrl_i2c_bridge(demod, &i2c_gate_state); + if (result != 0) { + pr_err("drx39xxj: could not open i2c gate [%d]\n", + result); + dump_stack(); + } else { + state->i2c_gate_open = enable; + } + return 0; +} + +static int drx39xxj_init(struct dvb_frontend *fe) +{ + /* Bring the demod out of sleep */ + drx39xxj_set_powerstate(fe, 1); + + return 0; +} + +static int drx39xxj_set_lna(struct dvb_frontend *fe) +{ + int result; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + struct drxj_data *ext_attr = demod->my_ext_attr; + struct drxuio_cfg uio_cfg; + struct drxuio_data uio_data; + + if (c->lna) { + if (!ext_attr->has_lna) { + pr_err("LNA is not supported on this device!\n"); + return -EINVAL; + + } + } + + /* Turn off the LNA */ + uio_cfg.uio = DRX_UIO1; + uio_cfg.mode = DRX_UIO_MODE_READWRITE; + /* Configure user-I/O #3: enable read/write */ + result = ctrl_set_uio_cfg(demod, &uio_cfg); + if (result) { + pr_err("Failed to setup LNA GPIO!\n"); + return result; + } + + uio_data.uio = DRX_UIO1; + uio_data.value = c->lna; + result = ctrl_uio_write(demod, &uio_data); + if (result != 0) { + pr_err("Failed to %sable LNA!\n", + c->lna ? "en" : "dis"); + return result; + } + + return 0; +} + +static int drx39xxj_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *tune) +{ + tune->min_delay_ms = 1000; + return 0; +} + +static void drx39xxj_release(struct dvb_frontend *fe) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + + drxj_close(demod); + + kfree(demod->my_ext_attr); + kfree(demod->my_common_attr); + kfree(demod->my_i2c_dev_addr); + if (demod->firmware) + release_firmware(demod->firmware); + kfree(demod); + kfree(state); +} + +static struct dvb_frontend_ops drx39xxj_ops; + +struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) +{ + struct drx39xxj_state *state = NULL; + struct i2c_device_addr *demod_addr = NULL; + struct drx_common_attr *demod_comm_attr = NULL; + struct drxj_data *demod_ext_attr = NULL; + struct drx_demod_instance *demod = NULL; + struct dtv_frontend_properties *p; + struct drxuio_cfg uio_cfg; + struct drxuio_data uio_data; + int result; + + /* allocate memory for the internal state */ + state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL); + if (state == NULL) + goto error; + + demod = kmalloc(sizeof(struct drx_demod_instance), GFP_KERNEL); + if (demod == NULL) + goto error; + + demod_addr = kmalloc(sizeof(struct i2c_device_addr), GFP_KERNEL); + if (demod_addr == NULL) + goto error; + memcpy(demod_addr, &drxj_default_addr_g, + sizeof(struct i2c_device_addr)); + + demod_comm_attr = kmalloc(sizeof(struct drx_common_attr), GFP_KERNEL); + if (demod_comm_attr == NULL) + goto error; + memcpy(demod_comm_attr, &drxj_default_comm_attr_g, + sizeof(struct drx_common_attr)); + + demod_ext_attr = kmalloc(sizeof(struct drxj_data), GFP_KERNEL); + if (demod_ext_attr == NULL) + goto error; + memcpy(demod_ext_attr, &drxj_data_g, sizeof(struct drxj_data)); + + /* setup the state */ + state->i2c = i2c; + state->demod = demod; + + /* setup the demod data */ + memcpy(demod, &drxj_default_demod_g, sizeof(struct drx_demod_instance)); + + demod->my_i2c_dev_addr = demod_addr; + demod->my_common_attr = demod_comm_attr; + demod->my_i2c_dev_addr->user_data = state; + demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE; + demod->my_common_attr->verify_microcode = true; + demod->my_common_attr->intermediate_freq = 5000; + demod->my_common_attr->current_power_mode = DRX_POWER_DOWN; + demod->my_ext_attr = demod_ext_attr; + ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; + demod->i2c = i2c; + + result = drxj_open(demod); + if (result != 0) { + pr_err("DRX open failed! Aborting\n"); + goto error; + } + + /* Turn off the LNA */ + uio_cfg.uio = DRX_UIO1; + uio_cfg.mode = DRX_UIO_MODE_READWRITE; + /* Configure user-I/O #3: enable read/write */ + result = ctrl_set_uio_cfg(demod, &uio_cfg); + if (result) { + pr_err("Failed to setup LNA GPIO!\n"); + goto error; + } + + uio_data.uio = DRX_UIO1; + uio_data.value = false; + result = ctrl_uio_write(demod, &uio_data); + if (result != 0) { + pr_err("Failed to disable LNA!\n"); + goto error; + } + + /* create dvb_frontend */ + memcpy(&state->frontend.ops, &drx39xxj_ops, + sizeof(struct dvb_frontend_ops)); + + state->frontend.demodulator_priv = state; + + /* Initialize stats - needed for DVBv5 stats to work */ + p = &state->frontend.dtv_property_cache; + p->strength.len = 1; + p->pre_bit_count.len = 1; + p->pre_bit_error.len = 1; + p->post_bit_count.len = 1; + p->post_bit_error.len = 1; + p->block_count.len = 1; + p->block_error.len = 1; + p->cnr.len = 1; + + p->strength.stat[0].scale = FE_SCALE_RELATIVE; + p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + + return &state->frontend; + +error: + kfree(demod_ext_attr); + kfree(demod_comm_attr); + kfree(demod_addr); + kfree(demod); + kfree(state); + + return NULL; +} +EXPORT_SYMBOL(drx39xxj_attach); + +static struct dvb_frontend_ops drx39xxj_ops = { + .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, + .info = { + .name = "Micronas DRX39xxj family Frontend", + .frequency_stepsize = 62500, + .frequency_min = 51000000, + .frequency_max = 858000000, + .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB + }, + + .init = drx39xxj_init, + .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl, + .sleep = drx39xxj_sleep, + .set_frontend = drx39xxj_set_frontend, + .get_tune_settings = drx39xxj_get_tune_settings, + .read_status = drx39xxj_read_status, + .read_ber = drx39xxj_read_ber, + .read_signal_strength = drx39xxj_read_signal_strength, + .read_snr = drx39xxj_read_snr, + .read_ucblocks = drx39xxj_read_ucblocks, + .release = drx39xxj_release, + .set_lna = drx39xxj_set_lna, +}; + +MODULE_DESCRIPTION("Micronas DRX39xxj Frontend"); +MODULE_AUTHOR("Devin Heitmueller"); +MODULE_LICENSE("GPL"); +MODULE_FIRMWARE(DRX39XX_MAIN_FIRMWARE); diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h new file mode 100644 index 0000000..55ad535 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -0,0 +1,650 @@ + +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + + DRXJ specific header file + + Authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen +*/ + +#ifndef __DRXJ_H__ +#define __DRXJ_H__ +/*------------------------------------------------------------------------- +INCLUDES +-------------------------------------------------------------------------*/ + +#include "drx_driver.h" +#include "drx_dap_fasi.h" + +/* Check DRX-J specific dap condition */ +/* Multi master mode and short addr format only will not work. + RMW, CRC reset, broadcast and switching back to single master mode + cannot be done with short addr only in multi master mode. */ +#if ((DRXDAP_SINGLE_MASTER == 0) && (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)) +#error "Multi master mode and short addressing only is an illegal combination" + *; /* Generate a fatal compiler error to make sure it stops here, + this is necesarry because not all compilers stop after a #error. */ +#endif + +/*------------------------------------------------------------------------- +TYPEDEFS +-------------------------------------------------------------------------*/ +/*============================================================================*/ +/*============================================================================*/ +/*== code support ============================================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== SCU cmd if =============================================================*/ +/*============================================================================*/ +/*============================================================================*/ + + struct drxjscu_cmd { + u16 command; + /**< Command number */ + u16 parameter_len; + /**< Data length in byte */ + u16 result_len; + /**< result length in byte */ + u16 *parameter; + /**< General purpous param */ + u16 *result; + /**< General purpous param */}; + +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL CFG related data structures ========================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* extra intermediate lock state for VSB,QAM,NTSC */ +#define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1) + +/* OOB lock states */ +#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */ +#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */ + +/* Intermediate powermodes for DRXJ */ +#define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8 +#define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9 +#define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10 + +/* supstition for GPIO FNC mux */ +#define APP_O (0x0000) + +/*#define DRX_CTRL_BASE (0x0000)*/ + +#define DRXJ_CTRL_CFG_BASE (0x1000) + enum drxj_cfg_type { + DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE, + DRXJ_CFG_AGC_IF, + DRXJ_CFG_AGC_INTERNAL, + DRXJ_CFG_PRE_SAW, + DRXJ_CFG_AFE_GAIN, + DRXJ_CFG_SYMBOL_CLK_OFFSET, + DRXJ_CFG_ACCUM_CR_RS_CW_ERR, + DRXJ_CFG_FEC_MERS_SEQ_COUNT, + DRXJ_CFG_OOB_MISC, + DRXJ_CFG_SMART_ANT, + DRXJ_CFG_OOB_PRE_SAW, + DRXJ_CFG_VSB_MISC, + DRXJ_CFG_RESET_PACKET_ERR, + + /* ATV (FM) */ + DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */ + DRXJ_CFG_ATV_MISC, + DRXJ_CFG_ATV_EQU_COEF, + DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */ + + DRXJ_CFG_MPEG_OUTPUT_MISC, + DRXJ_CFG_HW_CFG, + DRXJ_CFG_OOB_LO_POW, + + DRXJ_CFG_MAX /* dummy, never to be used */}; + +/** +* /struct enum drxj_cfg_smart_ant_io * smart antenna i/o. +*/ +enum drxj_cfg_smart_ant_io { + DRXJ_SMT_ANT_OUTPUT = 0, + DRXJ_SMT_ANT_INPUT +}; + +/** +* /struct struct drxj_cfg_smart_ant * Set smart antenna. +*/ + struct drxj_cfg_smart_ant { + enum drxj_cfg_smart_ant_io io; + u16 ctrl_data; + }; + +/** +* /struct DRXJAGCSTATUS_t +* AGC status information from the DRXJ-IQM-AF. +*/ +struct drxj_agc_status { + u16 IFAGC; + u16 RFAGC; + u16 digital_agc; +}; + +/* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ + +/** +* /struct enum drxj_agc_ctrl_mode * Available AGCs modes in the DRXJ. +*/ + enum drxj_agc_ctrl_mode { + DRX_AGC_CTRL_AUTO = 0, + DRX_AGC_CTRL_USER, + DRX_AGC_CTRL_OFF}; + +/** +* /struct struct drxj_cfg_agc * Generic interface for all AGCs present on the DRXJ. +*/ + struct drxj_cfg_agc { + enum drx_standard standard; /* standard for which these settings apply */ + enum drxj_agc_ctrl_mode ctrl_mode; /* off, user, auto */ + u16 output_level; /* range dependent on AGC */ + u16 min_output_level; /* range dependent on AGC */ + u16 max_output_level; /* range dependent on AGC */ + u16 speed; /* range dependent on AGC */ + u16 top; /* rf-agc take over point */ + u16 cut_off_current; /* rf-agc is accelerated if output current + is below cut-off current */}; + +/* DRXJ_CFG_PRE_SAW */ + +/** +* /struct struct drxj_cfg_pre_saw * Interface to configure pre SAW sense. +*/ + struct drxj_cfg_pre_saw { + enum drx_standard standard; /* standard to which these settings apply */ + u16 reference; /* pre SAW reference value, range 0 .. 31 */ + bool use_pre_saw; /* true algorithms must use pre SAW sense */}; + +/* DRXJ_CFG_AFE_GAIN */ + +/** +* /struct struct drxj_cfg_afe_gain * Interface to configure gain of AFE (LNA + PGA). +*/ + struct drxj_cfg_afe_gain { + enum drx_standard standard; /* standard to which these settings apply */ + u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */}; + +/** +* /struct drxjrs_errors +* Available failure information in DRXJ_FEC_RS. +* +* Container for errors that are received in the most recently finished measurment period +* +*/ + struct drxjrs_errors { + u16 nr_bit_errors; + /**< no of pre RS bit errors */ + u16 nr_symbol_errors; + /**< no of pre RS symbol errors */ + u16 nr_packet_errors; + /**< no of pre RS packet errors */ + u16 nr_failures; + /**< no of post RS failures to decode */ + u16 nr_snc_par_fail_count; + /**< no of post RS bit erros */ + }; + +/** +* /struct struct drxj_cfg_vsb_misc * symbol error rate +*/ + struct drxj_cfg_vsb_misc { + u32 symb_error; + /**< symbol error rate sps */}; + +/** +* /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. +* +*/ + enum drxj_mpeg_start_width { + DRXJ_MPEG_START_WIDTH_1CLKCYC, + DRXJ_MPEG_START_WIDTH_8CLKCYC}; + +/** +* /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. +* +*/ + enum drxj_mpeg_output_clock_rate { + DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, + DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K}; + +/** +* /struct DRXJCfgMisc_t +* Change TEI bit of MPEG output +* reverse MPEG output bit order +* set MPEG output clock rate +*/ + struct drxj_cfg_mpeg_output_misc { + bool disable_tei_handling; /**< if true pass (not change) TEI bit */ + bool bit_reverse_mpeg_outout; /**< if true, parallel: msb on MD0; serial: lsb out first */ + enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; + /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ + enum drxj_mpeg_start_width mpeg_start_width; /**< set MPEG output start width */}; + +/** +* /enum enum drxj_xtal_freq * Supported external crystal reference frequency. +*/ + enum drxj_xtal_freq { + DRXJ_XTAL_FREQ_RSVD, + DRXJ_XTAL_FREQ_27MHZ, + DRXJ_XTAL_FREQ_20P25MHZ, + DRXJ_XTAL_FREQ_4MHZ}; + +/** +* /enum enum drxj_xtal_freq * Supported external crystal reference frequency. +*/ + enum drxji2c_speed { + DRXJ_I2C_SPEED_400KBPS, + DRXJ_I2C_SPEED_100KBPS}; + +/** +* /struct struct drxj_cfg_hw_cfg * Get hw configuration, such as crystal reference frequency, I2C speed, etc... +*/ + struct drxj_cfg_hw_cfg { + enum drxj_xtal_freq xtal_freq; + /**< crystal reference frequency */ + enum drxji2c_speed i2c_speed; + /**< 100 or 400 kbps */}; + +/* + * DRXJ_CFG_ATV_MISC + */ + struct drxj_cfg_atv_misc { + s16 peak_filter; /* -8 .. 15 */ + u16 noise_filter; /* 0 .. 15 */}; + +/* + * struct drxj_cfg_oob_misc */ +#define DRXJ_OOB_STATE_RESET 0x0 +#define DRXJ_OOB_STATE_AGN_HUNT 0x1 +#define DRXJ_OOB_STATE_DGN_HUNT 0x2 +#define DRXJ_OOB_STATE_AGC_HUNT 0x3 +#define DRXJ_OOB_STATE_FRQ_HUNT 0x4 +#define DRXJ_OOB_STATE_PHA_HUNT 0x8 +#define DRXJ_OOB_STATE_TIM_HUNT 0x10 +#define DRXJ_OOB_STATE_EQU_HUNT 0x20 +#define DRXJ_OOB_STATE_EQT_HUNT 0x30 +#define DRXJ_OOB_STATE_SYNC 0x40 + +struct drxj_cfg_oob_misc { + struct drxj_agc_status agc; + bool eq_lock; + bool sym_timing_lock; + bool phase_lock; + bool freq_lock; + bool dig_gain_lock; + bool ana_gain_lock; + u8 state; +}; + +/* + * Index of in array of coef + */ + enum drxj_cfg_oob_lo_power { + DRXJ_OOB_LO_POW_MINUS0DB = 0, + DRXJ_OOB_LO_POW_MINUS5DB, + DRXJ_OOB_LO_POW_MINUS10DB, + DRXJ_OOB_LO_POW_MINUS15DB, + DRXJ_OOB_LO_POW_MAX}; + +/* + * DRXJ_CFG_ATV_EQU_COEF + */ + struct drxj_cfg_atv_equ_coef { + s16 coef0; /* -256 .. 255 */ + s16 coef1; /* -256 .. 255 */ + s16 coef2; /* -256 .. 255 */ + s16 coef3; /* -256 .. 255 */}; + +/* + * Index of in array of coef + */ + enum drxj_coef_array_index { + DRXJ_COEF_IDX_MN = 0, + DRXJ_COEF_IDX_FM, + DRXJ_COEF_IDX_L, + DRXJ_COEF_IDX_LP, + DRXJ_COEF_IDX_BG, + DRXJ_COEF_IDX_DK, + DRXJ_COEF_IDX_I, + DRXJ_COEF_IDX_MAX}; + +/* + * DRXJ_CFG_ATV_OUTPUT + */ + +/** +* /enum DRXJAttenuation_t +* Attenuation setting for SIF AGC. +* +*/ + enum drxjsif_attenuation { + DRXJ_SIF_ATTENUATION_0DB, + DRXJ_SIF_ATTENUATION_3DB, + DRXJ_SIF_ATTENUATION_6DB, + DRXJ_SIF_ATTENUATION_9DB}; + +/** +* /struct struct drxj_cfg_atv_output * SIF attenuation setting. +* +*/ +struct drxj_cfg_atv_output { + bool enable_cvbs_output; /* true= enabled */ + bool enable_sif_output; /* true= enabled */ + enum drxjsif_attenuation sif_attenuation; +}; + +/* + DRXJ_CFG_ATV_AGC_STATUS (get only) +*/ +/* TODO : AFE interface not yet finished, subject to change */ + struct drxj_cfg_atv_agc_status { + u16 rf_agc_gain; /* 0 .. 877 uA */ + u16 if_agc_gain; /* 0 .. 877 uA */ + s16 video_agc_gain; /* -75 .. 1972 in 0.1 dB steps */ + s16 audio_agc_gain; /* -4 .. 1020 in 0.1 dB steps */ + u16 rf_agc_loop_gain; /* 0 .. 7 */ + u16 if_agc_loop_gain; /* 0 .. 7 */ + u16 video_agc_loop_gain; /* 0 .. 7 */}; + +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL related data structures ============================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* NONE */ + +/*============================================================================*/ +/*============================================================================*/ + +/*========================================*/ +/** +* /struct struct drxj_data * DRXJ specific attributes. +* +* Global data container for DRXJ specific data. +* +*/ + struct drxj_data { + /* device capabilties (determined during drx_open()) */ + bool has_lna; /**< true if LNA (aka PGA) present */ + bool has_oob; /**< true if OOB supported */ + bool has_ntsc; /**< true if NTSC supported */ + bool has_btsc; /**< true if BTSC supported */ + bool has_smatx; /**< true if mat_tx is available */ + bool has_smarx; /**< true if mat_rx is available */ + bool has_gpio; /**< true if GPIO is available */ + bool has_irqn; /**< true if IRQN is available */ + /* A1/A2/A... */ + u8 mfx; /**< metal fix */ + + /* tuner settings */ + bool mirror_freq_spect_oob;/**< tuner inversion (true = tuner mirrors the signal */ + + /* standard/channel settings */ + enum drx_standard standard; /**< current standard information */ + enum drx_modulation constellation; + /**< current constellation */ + s32 frequency; /**< center signal frequency in KHz */ + enum drx_bandwidth curr_bandwidth; + /**< current channel bandwidth */ + enum drx_mirror mirror; /**< current channel mirror */ + + /* signal quality information */ + u32 fec_bits_desired; /**< BER accounting period */ + u16 fec_vd_plen; /**< no of trellis symbols: VD SER measurement period */ + u16 qam_vd_prescale; /**< Viterbi Measurement Prescale */ + u16 qam_vd_period; /**< Viterbi Measurement period */ + u16 fec_rs_plen; /**< defines RS BER measurement period */ + u16 fec_rs_prescale; /**< ReedSolomon Measurement Prescale */ + u16 fec_rs_period; /**< ReedSolomon Measurement period */ + bool reset_pkt_err_acc; /**< Set a flag to reset accumulated packet error */ + u16 pkt_err_acc_start; /**< Set a flag to reset accumulated packet error */ + + /* HI configuration */ + u16 hi_cfg_timing_div; /**< HI Configure() parameter 2 */ + u16 hi_cfg_bridge_delay; /**< HI Configure() parameter 3 */ + u16 hi_cfg_wake_up_key; /**< HI Configure() parameter 4 */ + u16 hi_cfg_ctrl; /**< HI Configure() parameter 5 */ + u16 hi_cfg_transmit; /**< HI Configure() parameter 6 */ + + /* UIO configuartion */ + enum drxuio_mode uio_sma_rx_mode;/**< current mode of SmaRx pin */ + enum drxuio_mode uio_sma_tx_mode;/**< current mode of SmaTx pin */ + enum drxuio_mode uio_gpio_mode; /**< current mode of ASEL pin */ + enum drxuio_mode uio_irqn_mode; /**< current mode of IRQN pin */ + + /* IQM fs frequecy shift and inversion */ + u32 iqm_fs_rate_ofs; /**< frequency shifter setting after setchannel */ + bool pos_image; /**< Ture: positive image */ + /* IQM RC frequecy shift */ + u32 iqm_rc_rate_ofs; /**< frequency shifter setting after setchannel */ + + /* ATV configuartion */ + u32 atv_cfg_changed_flags; /**< flag: flags cfg changes */ + s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ + s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ + s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ + s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ + bool phase_correction_bypass;/**< flag: true=bypass */ + s16 atv_top_vid_peak; /**< shadow of ATV_TOP_VID_PEAK__A */ + u16 atv_top_noise_th; /**< shadow of ATV_TOP_NOISE_TH__A */ + bool enable_cvbs_output; /**< flag CVBS ouput enable */ + bool enable_sif_output; /**< flag SIF ouput enable */ + enum drxjsif_attenuation sif_attenuation; + /**< current SIF att setting */ + /* Agc configuration for QAM and VSB */ + struct drxj_cfg_agc qam_rf_agc_cfg; /**< qam RF AGC config */ + struct drxj_cfg_agc qam_if_agc_cfg; /**< qam IF AGC config */ + struct drxj_cfg_agc vsb_rf_agc_cfg; /**< vsb RF AGC config */ + struct drxj_cfg_agc vsb_if_agc_cfg; /**< vsb IF AGC config */ + + /* PGA gain configuration for QAM and VSB */ + u16 qam_pga_cfg; /**< qam PGA config */ + u16 vsb_pga_cfg; /**< vsb PGA config */ + + /* Pre SAW configuration for QAM and VSB */ + struct drxj_cfg_pre_saw qam_pre_saw_cfg; + /**< qam pre SAW config */ + struct drxj_cfg_pre_saw vsb_pre_saw_cfg; + /**< qam pre SAW config */ + + /* Version information */ + char v_text[2][12]; /**< allocated text versions */ + struct drx_version v_version[2]; /**< allocated versions structs */ + struct drx_version_list v_list_elements[2]; + /**< allocated version list */ + + /* smart antenna configuration */ + bool smart_ant_inverted; + + /* Tracking filter setting for OOB */ + u16 oob_trk_filter_cfg[8]; + bool oob_power_on; + + /* MPEG static bitrate setting */ + u32 mpeg_ts_static_bitrate; /**< bitrate static MPEG output */ + bool disable_te_ihandling; /**< MPEG TS TEI handling */ + bool bit_reverse_mpeg_outout;/**< MPEG output bit order */ + enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; + /**< MPEG output clock rate */ + enum drxj_mpeg_start_width mpeg_start_width; + /**< MPEG Start width */ + + /* Pre SAW & Agc configuration for ATV */ + struct drxj_cfg_pre_saw atv_pre_saw_cfg; + /**< atv pre SAW config */ + struct drxj_cfg_agc atv_rf_agc_cfg; /**< atv RF AGC config */ + struct drxj_cfg_agc atv_if_agc_cfg; /**< atv IF AGC config */ + u16 atv_pga_cfg; /**< atv pga config */ + + u32 curr_symbol_rate; + + /* pin-safe mode */ + bool pdr_safe_mode; /**< PDR safe mode activated */ + u16 pdr_safe_restore_val_gpio; + u16 pdr_safe_restore_val_v_sync; + u16 pdr_safe_restore_val_sma_rx; + u16 pdr_safe_restore_val_sma_tx; + + /* OOB pre-saw value */ + u16 oob_pre_saw; + enum drxj_cfg_oob_lo_power oob_lo_pow; + + struct drx_aud_data aud_data; + /**< audio storage */}; + +/*------------------------------------------------------------------------- +Access MACROS +-------------------------------------------------------------------------*/ +/** +* \brief Compilable references to attributes +* \param d pointer to demod instance +* +* Used as main reference to an attribute field. +* Can be used by both macro implementation and function implementation. +* These macros are defined to avoid duplication of code in macro and function +* definitions that handle access of demod common or extended attributes. +* +*/ + +#define DRXJ_ATTR_BTSC_DETECT(d) \ + (((struct drxj_data *)(d)->my_ext_attr)->aud_data.btsc_detect) + +/*------------------------------------------------------------------------- +DEFINES +-------------------------------------------------------------------------*/ + +/** +* \def DRXJ_NTSC_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For NTSC standard. +* NTSC channels are listed by their picture carrier frequency (Fpc). +* The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input. +* In case the tuner module is not used the DRX-J requires that the tuner is +* tuned to the centre frequency of the channel: +* +* Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET +* +*/ +#define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750)) + +/** +* \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For PAL/SECAM - BG standard. This define is needed in case the tuner module +* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). +* The DRX-J requires that the tuner is tuned to: +* Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET +* +* In case the tuner module is used the drxdriver takes care of this. +* In case the tuner module is NOT used the application programmer must take +* care of this. +* +*/ +#define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375)) + +/** +* \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module +* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). +* The DRX-J requires that the tuner is tuned to: +* Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET +* +* In case the tuner module is used the drxdriver takes care of this. +* In case the tuner module is NOT used the application programmer must take +* care of this. +* +*/ +#define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775)) + +/** +* \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For PAL/SECAM - LP standard. This define is needed in case the tuner module +* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). +* The DRX-J requires that the tuner is tuned to: +* Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET +* +* In case the tuner module is used the drxdriver takes care of this. +* In case the tuner module is NOT used the application programmer must take +* care of this. +*/ +#define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255)) + +/** +* \def DRXJ_FM_CARRIER_FREQ_OFFSET +* \brief Offset from sound carrier to centre frequency in kHz, in RF domain +* +* For FM standard. +* FM channels are listed by their sound carrier frequency (Fsc). +* The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as +* input. +* In case the tuner module is not used the DRX-J requires that the tuner is +* tuned to the Ffm frequency of the channel. +* +* Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET +* +*/ +#define DRXJ_FM_CARRIER_FREQ_OFFSET ((s32)(-3000)) + +/* Revision types -------------------------------------------------------*/ + +#define DRXJ_TYPE_ID (0x3946000DUL) + +/* Macros ---------------------------------------------------------------*/ + +/* Convert OOB lock status to string */ +#define DRXJ_STR_OOB_LOCKSTATUS(x) ( \ + (x == DRX_NEVER_LOCK) ? "Never" : \ + (x == DRX_NOT_LOCKED) ? "No" : \ + (x == DRX_LOCKED) ? "Locked" : \ + (x == DRX_LOCK_STATE_1) ? "AGC lock" : \ + (x == DRX_LOCK_STATE_2) ? "sync lock" : \ + "(Invalid)") + +#endif /* __DRXJ_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h new file mode 100644 index 0000000..0bbd4ae --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h @@ -0,0 +1,15055 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/* + *********************************************************************************************************************** + * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE + * + * Filename: drxj_map.h + * Generated on: Mon Jan 18 12:09:24 2010 + * Generated by: IDF:x 1.3.0 + * Generated from: reg_map + * Output start: [entry point] + * + * filename last modified re-use + * ----------------------------------------------------- + * reg_map.1.tmp Mon Jan 18 12:09:24 2010 - + * + */ + +#ifndef __DRXJ_MAP__H__ +#define __DRXJ_MAP__H__ INCLUDED + +#ifdef _REGISTERTABLE_ +#include <registertable.h> + extern register_table_t drxj_map[]; + extern register_table_info_t drxj_map_info[]; +#endif + +#define ATV_COMM_EXEC__A 0xC00000 +#define ATV_COMM_EXEC__W 2 +#define ATV_COMM_EXEC__M 0x3 +#define ATV_COMM_EXEC__PRE 0x0 +#define ATV_COMM_EXEC_STOP 0x0 +#define ATV_COMM_EXEC_ACTIVE 0x1 +#define ATV_COMM_EXEC_HOLD 0x2 + +#define ATV_COMM_STATE__A 0xC00001 +#define ATV_COMM_STATE__W 16 +#define ATV_COMM_STATE__M 0xFFFF +#define ATV_COMM_STATE__PRE 0x0 +#define ATV_COMM_MB__A 0xC00002 +#define ATV_COMM_MB__W 16 +#define ATV_COMM_MB__M 0xFFFF +#define ATV_COMM_MB__PRE 0x0 +#define ATV_COMM_INT_REQ__A 0xC00003 +#define ATV_COMM_INT_REQ__W 16 +#define ATV_COMM_INT_REQ__M 0xFFFF +#define ATV_COMM_INT_REQ__PRE 0x0 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__B 0 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__W 1 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__M 0x1 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__PRE 0x0 + +#define ATV_COMM_INT_STA__A 0xC00005 +#define ATV_COMM_INT_STA__W 16 +#define ATV_COMM_INT_STA__M 0xFFFF +#define ATV_COMM_INT_STA__PRE 0x0 +#define ATV_COMM_INT_MSK__A 0xC00006 +#define ATV_COMM_INT_MSK__W 16 +#define ATV_COMM_INT_MSK__M 0xFFFF +#define ATV_COMM_INT_MSK__PRE 0x0 +#define ATV_COMM_INT_STM__A 0xC00007 +#define ATV_COMM_INT_STM__W 16 +#define ATV_COMM_INT_STM__M 0xFFFF +#define ATV_COMM_INT_STM__PRE 0x0 + +#define ATV_COMM_KEY__A 0xC0000F +#define ATV_COMM_KEY__W 16 +#define ATV_COMM_KEY__M 0xFFFF +#define ATV_COMM_KEY__PRE 0x0 +#define ATV_COMM_KEY_KEY 0xFABA +#define ATV_COMM_KEY_MIN 0x0 +#define ATV_COMM_KEY_MAX 0xFFFF + +#define ATV_TOP_COMM_EXEC__A 0xC10000 +#define ATV_TOP_COMM_EXEC__W 2 +#define ATV_TOP_COMM_EXEC__M 0x3 +#define ATV_TOP_COMM_EXEC__PRE 0x0 +#define ATV_TOP_COMM_EXEC_STOP 0x0 +#define ATV_TOP_COMM_EXEC_ACTIVE 0x1 +#define ATV_TOP_COMM_EXEC_HOLD 0x2 + +#define ATV_TOP_COMM_STATE__A 0xC10001 +#define ATV_TOP_COMM_STATE__W 16 +#define ATV_TOP_COMM_STATE__M 0xFFFF +#define ATV_TOP_COMM_STATE__PRE 0x0 +#define ATV_TOP_COMM_STATE_STATE__B 0 +#define ATV_TOP_COMM_STATE_STATE__W 16 +#define ATV_TOP_COMM_STATE_STATE__M 0xFFFF +#define ATV_TOP_COMM_STATE_STATE__PRE 0x0 + +#define ATV_TOP_COMM_MB__A 0xC10002 +#define ATV_TOP_COMM_MB__W 16 +#define ATV_TOP_COMM_MB__M 0xFFFF +#define ATV_TOP_COMM_MB__PRE 0x0 +#define ATV_TOP_COMM_MB_CTL__B 0 +#define ATV_TOP_COMM_MB_CTL__W 1 +#define ATV_TOP_COMM_MB_CTL__M 0x1 +#define ATV_TOP_COMM_MB_CTL__PRE 0x0 +#define ATV_TOP_COMM_MB_OBS__B 1 +#define ATV_TOP_COMM_MB_OBS__W 1 +#define ATV_TOP_COMM_MB_OBS__M 0x2 +#define ATV_TOP_COMM_MB_OBS__PRE 0x0 + +#define ATV_TOP_COMM_MB_MUX_CTRL__B 2 +#define ATV_TOP_COMM_MB_MUX_CTRL__W 4 +#define ATV_TOP_COMM_MB_MUX_CTRL__M 0x3C +#define ATV_TOP_COMM_MB_MUX_CTRL__PRE 0x0 +#define ATV_TOP_COMM_MB_MUX_CTRL_PEAK_S 0x0 +#define ATV_TOP_COMM_MB_MUX_CTRL_VID_GAIN 0x4 +#define ATV_TOP_COMM_MB_MUX_CTRL_CORR_O 0x8 +#define ATV_TOP_COMM_MB_MUX_CTRL_CR_ROT_O 0xC +#define ATV_TOP_COMM_MB_MUX_CTRL_CR_IIR_IQ 0x10 +#define ATV_TOP_COMM_MB_MUX_CTRL_VIDEO_O 0x14 +#define ATV_TOP_COMM_MB_MUX_CTRL_SIF_O 0x18 +#define ATV_TOP_COMM_MB_MUX_CTRL_SIF2025_O 0x1C +#define ATV_TOP_COMM_MB_MUX_CTRL_POST_S 0x20 + +#define ATV_TOP_COMM_MB_MUX_OBS__B 6 +#define ATV_TOP_COMM_MB_MUX_OBS__W 4 +#define ATV_TOP_COMM_MB_MUX_OBS__M 0x3C0 +#define ATV_TOP_COMM_MB_MUX_OBS__PRE 0x0 +#define ATV_TOP_COMM_MB_MUX_OBS_PEAK_S 0x0 +#define ATV_TOP_COMM_MB_MUX_OBS_VID_GAIN 0x40 +#define ATV_TOP_COMM_MB_MUX_OBS_CORR_O 0x80 +#define ATV_TOP_COMM_MB_MUX_OBS_CR_ROT_O 0xC0 +#define ATV_TOP_COMM_MB_MUX_OBS_CR_IIR_IQ 0x100 +#define ATV_TOP_COMM_MB_MUX_OBS_VIDEO_O 0x140 +#define ATV_TOP_COMM_MB_MUX_OBS_SIF_O 0x180 +#define ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O 0x1C0 +#define ATV_TOP_COMM_MB_MUX_OBS_POST_S 0x200 + +#define ATV_TOP_COMM_INT_REQ__A 0xC10003 +#define ATV_TOP_COMM_INT_REQ__W 16 +#define ATV_TOP_COMM_INT_REQ__M 0xFFFF +#define ATV_TOP_COMM_INT_REQ__PRE 0x0 +#define ATV_TOP_COMM_INT_STA__A 0xC10005 +#define ATV_TOP_COMM_INT_STA__W 16 +#define ATV_TOP_COMM_INT_STA__M 0xFFFF +#define ATV_TOP_COMM_INT_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_STA_FAGC_STA__B 0 +#define ATV_TOP_COMM_INT_STA_FAGC_STA__W 1 +#define ATV_TOP_COMM_INT_STA_FAGC_STA__M 0x1 +#define ATV_TOP_COMM_INT_STA_FAGC_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_STA_OVM_STA__B 1 +#define ATV_TOP_COMM_INT_STA_OVM_STA__W 1 +#define ATV_TOP_COMM_INT_STA_OVM_STA__M 0x2 +#define ATV_TOP_COMM_INT_STA_OVM_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__B 2 +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__W 1 +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__M 0x4 +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK__A 0xC10006 +#define ATV_TOP_COMM_INT_MSK__W 16 +#define ATV_TOP_COMM_INT_MSK__M 0xFFFF +#define ATV_TOP_COMM_INT_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__B 0 +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__W 1 +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__M 0x1 +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__B 1 +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__W 1 +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__M 0x2 +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__B 2 +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__W 1 +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__M 0x4 +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM__A 0xC10007 +#define ATV_TOP_COMM_INT_STM__W 16 +#define ATV_TOP_COMM_INT_STM__M 0xFFFF +#define ATV_TOP_COMM_INT_STM__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM_FAGC_STM__B 0 +#define ATV_TOP_COMM_INT_STM_FAGC_STM__W 1 +#define ATV_TOP_COMM_INT_STM_FAGC_STM__M 0x1 +#define ATV_TOP_COMM_INT_STM_FAGC_STM__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM_OVM_STM__B 1 +#define ATV_TOP_COMM_INT_STM_OVM_STM__W 1 +#define ATV_TOP_COMM_INT_STM_OVM_STM__M 0x2 +#define ATV_TOP_COMM_INT_STM_OVM_STM__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__B 2 +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__W 1 +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__M 0x4 +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__PRE 0x0 + +#define ATV_TOP_COMM_KEY__A 0xC1000F +#define ATV_TOP_COMM_KEY__W 16 +#define ATV_TOP_COMM_KEY__M 0xFFFF +#define ATV_TOP_COMM_KEY__PRE 0x0 + +#define ATV_TOP_COMM_KEY_KEY__B 0 +#define ATV_TOP_COMM_KEY_KEY__W 16 +#define ATV_TOP_COMM_KEY_KEY__M 0xFFFF +#define ATV_TOP_COMM_KEY_KEY__PRE 0x0 +#define ATV_TOP_COMM_KEY_KEY_KEY 0xFABA +#define ATV_TOP_COMM_KEY_KEY_MIN 0x0 +#define ATV_TOP_COMM_KEY_KEY_MAX 0xFFFF + +#define ATV_TOP_CR_AMP_TH__A 0xC10010 +#define ATV_TOP_CR_AMP_TH__W 8 +#define ATV_TOP_CR_AMP_TH__M 0xFF +#define ATV_TOP_CR_AMP_TH__PRE 0x8 +#define ATV_TOP_CR_AMP_TH_MN 0x8 + +#define ATV_TOP_CR_CONT__A 0xC10011 +#define ATV_TOP_CR_CONT__W 9 +#define ATV_TOP_CR_CONT__M 0x1FF +#define ATV_TOP_CR_CONT__PRE 0x9C + +#define ATV_TOP_CR_CONT_CR_P__B 0 +#define ATV_TOP_CR_CONT_CR_P__W 3 +#define ATV_TOP_CR_CONT_CR_P__M 0x7 +#define ATV_TOP_CR_CONT_CR_P__PRE 0x4 +#define ATV_TOP_CR_CONT_CR_P_MN 0x4 +#define ATV_TOP_CR_CONT_CR_P_FM 0x0 + +#define ATV_TOP_CR_CONT_CR_D__B 3 +#define ATV_TOP_CR_CONT_CR_D__W 3 +#define ATV_TOP_CR_CONT_CR_D__M 0x38 +#define ATV_TOP_CR_CONT_CR_D__PRE 0x18 +#define ATV_TOP_CR_CONT_CR_D_MN 0x18 +#define ATV_TOP_CR_CONT_CR_D_FM 0x0 + +#define ATV_TOP_CR_CONT_CR_I__B 6 +#define ATV_TOP_CR_CONT_CR_I__W 3 +#define ATV_TOP_CR_CONT_CR_I__M 0x1C0 +#define ATV_TOP_CR_CONT_CR_I__PRE 0x80 +#define ATV_TOP_CR_CONT_CR_I_MN 0x80 +#define ATV_TOP_CR_CONT_CR_I_FM 0x0 + +#define ATV_TOP_CR_OVM_TH__A 0xC10012 +#define ATV_TOP_CR_OVM_TH__W 8 +#define ATV_TOP_CR_OVM_TH__M 0xFF +#define ATV_TOP_CR_OVM_TH__PRE 0xA0 +#define ATV_TOP_CR_OVM_TH_MN 0xA0 +#define ATV_TOP_CR_OVM_TH_FM 0x0 + +#define ATV_TOP_NOISE_TH__A 0xC10013 +#define ATV_TOP_NOISE_TH__W 4 +#define ATV_TOP_NOISE_TH__M 0xF +#define ATV_TOP_NOISE_TH__PRE 0x8 +#define ATV_TOP_NOISE_TH_MN 0x8 + +#define ATV_TOP_EQU0__A 0xC10014 +#define ATV_TOP_EQU0__W 9 +#define ATV_TOP_EQU0__M 0x1FF +#define ATV_TOP_EQU0__PRE 0x1FB + +#define ATV_TOP_EQU0_EQU_C0__B 0 +#define ATV_TOP_EQU0_EQU_C0__W 9 +#define ATV_TOP_EQU0_EQU_C0__M 0x1FF +#define ATV_TOP_EQU0_EQU_C0__PRE 0x1FB +#define ATV_TOP_EQU0_EQU_C0_MN 0xFB + +#define ATV_TOP_EQU1__A 0xC10015 +#define ATV_TOP_EQU1__W 9 +#define ATV_TOP_EQU1__M 0x1FF +#define ATV_TOP_EQU1__PRE 0x1CE + +#define ATV_TOP_EQU1_EQU_C1__B 0 +#define ATV_TOP_EQU1_EQU_C1__W 9 +#define ATV_TOP_EQU1_EQU_C1__M 0x1FF +#define ATV_TOP_EQU1_EQU_C1__PRE 0x1CE +#define ATV_TOP_EQU1_EQU_C1_MN 0xCE + +#define ATV_TOP_EQU2__A 0xC10016 +#define ATV_TOP_EQU2__W 9 +#define ATV_TOP_EQU2__M 0x1FF +#define ATV_TOP_EQU2__PRE 0xD2 + +#define ATV_TOP_EQU2_EQU_C2__B 0 +#define ATV_TOP_EQU2_EQU_C2__W 9 +#define ATV_TOP_EQU2_EQU_C2__M 0x1FF +#define ATV_TOP_EQU2_EQU_C2__PRE 0xD2 +#define ATV_TOP_EQU2_EQU_C2_MN 0xD2 + +#define ATV_TOP_EQU3__A 0xC10017 +#define ATV_TOP_EQU3__W 9 +#define ATV_TOP_EQU3__M 0x1FF +#define ATV_TOP_EQU3__PRE 0x160 + +#define ATV_TOP_EQU3_EQU_C3__B 0 +#define ATV_TOP_EQU3_EQU_C3__W 9 +#define ATV_TOP_EQU3_EQU_C3__M 0x1FF +#define ATV_TOP_EQU3_EQU_C3__PRE 0x160 +#define ATV_TOP_EQU3_EQU_C3_MN 0x60 + +#define ATV_TOP_ROT_MODE__A 0xC10018 +#define ATV_TOP_ROT_MODE__W 1 +#define ATV_TOP_ROT_MODE__M 0x1 +#define ATV_TOP_ROT_MODE__PRE 0x0 +#define ATV_TOP_ROT_MODE_AMPTH_DEPEND 0x0 +#define ATV_TOP_ROT_MODE_ALWAYS 0x1 + +#define ATV_TOP_MOD_CONTROL__A 0xC10019 +#define ATV_TOP_MOD_CONTROL__W 12 +#define ATV_TOP_MOD_CONTROL__M 0xFFF +#define ATV_TOP_MOD_CONTROL__PRE 0x5B1 + +#define ATV_TOP_MOD_CONTROL_MOD_IR__B 0 +#define ATV_TOP_MOD_CONTROL_MOD_IR__W 3 +#define ATV_TOP_MOD_CONTROL_MOD_IR__M 0x7 +#define ATV_TOP_MOD_CONTROL_MOD_IR__PRE 0x1 +#define ATV_TOP_MOD_CONTROL_MOD_IR_MN 0x1 +#define ATV_TOP_MOD_CONTROL_MOD_IR_FM 0x0 + +#define ATV_TOP_MOD_CONTROL_MOD_IF__B 3 +#define ATV_TOP_MOD_CONTROL_MOD_IF__W 4 +#define ATV_TOP_MOD_CONTROL_MOD_IF__M 0x78 +#define ATV_TOP_MOD_CONTROL_MOD_IF__PRE 0x30 +#define ATV_TOP_MOD_CONTROL_MOD_IF_MN 0x30 +#define ATV_TOP_MOD_CONTROL_MOD_IF_FM 0x0 + +#define ATV_TOP_MOD_CONTROL_MOD_MODE__B 7 +#define ATV_TOP_MOD_CONTROL_MOD_MODE__W 1 +#define ATV_TOP_MOD_CONTROL_MOD_MODE__M 0x80 +#define ATV_TOP_MOD_CONTROL_MOD_MODE__PRE 0x80 +#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE 0x0 +#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE_FALL 0x80 + +#define ATV_TOP_MOD_CONTROL_MOD_TH__B 8 +#define ATV_TOP_MOD_CONTROL_MOD_TH__W 4 +#define ATV_TOP_MOD_CONTROL_MOD_TH__M 0xF00 +#define ATV_TOP_MOD_CONTROL_MOD_TH__PRE 0x500 +#define ATV_TOP_MOD_CONTROL_MOD_TH_MN 0x500 +#define ATV_TOP_MOD_CONTROL_MOD_TH_FM 0x0 + +#define ATV_TOP_STD__A 0xC1001A +#define ATV_TOP_STD__W 2 +#define ATV_TOP_STD__M 0x3 +#define ATV_TOP_STD__PRE 0x0 + +#define ATV_TOP_STD_MODE__B 0 +#define ATV_TOP_STD_MODE__W 1 +#define ATV_TOP_STD_MODE__M 0x1 +#define ATV_TOP_STD_MODE__PRE 0x0 +#define ATV_TOP_STD_MODE_MN 0x0 +#define ATV_TOP_STD_MODE_FM 0x1 + +#define ATV_TOP_STD_VID_POL__B 1 +#define ATV_TOP_STD_VID_POL__W 1 +#define ATV_TOP_STD_VID_POL__M 0x2 +#define ATV_TOP_STD_VID_POL__PRE 0x0 +#define ATV_TOP_STD_VID_POL_NEG 0x0 +#define ATV_TOP_STD_VID_POL_POS 0x2 + +#define ATV_TOP_VID_AMP__A 0xC1001B +#define ATV_TOP_VID_AMP__W 12 +#define ATV_TOP_VID_AMP__M 0xFFF +#define ATV_TOP_VID_AMP__PRE 0x380 +#define ATV_TOP_VID_AMP_MN 0x380 +#define ATV_TOP_VID_AMP_FM 0x0 + +#define ATV_TOP_VID_PEAK__A 0xC1001C +#define ATV_TOP_VID_PEAK__W 5 +#define ATV_TOP_VID_PEAK__M 0x1F +#define ATV_TOP_VID_PEAK__PRE 0x1 + +#define ATV_TOP_FAGC_TH__A 0xC1001D +#define ATV_TOP_FAGC_TH__W 11 +#define ATV_TOP_FAGC_TH__M 0x7FF +#define ATV_TOP_FAGC_TH__PRE 0x2B2 +#define ATV_TOP_FAGC_TH_MN 0x2B2 + +#define ATV_TOP_SYNC_SLICE__A 0xC1001E +#define ATV_TOP_SYNC_SLICE__W 11 +#define ATV_TOP_SYNC_SLICE__M 0x7FF +#define ATV_TOP_SYNC_SLICE__PRE 0x243 +#define ATV_TOP_SYNC_SLICE_MN 0x243 + +#define ATV_TOP_SIF_GAIN__A 0xC1001F +#define ATV_TOP_SIF_GAIN__W 11 +#define ATV_TOP_SIF_GAIN__M 0x7FF +#define ATV_TOP_SIF_GAIN__PRE 0x0 + +#define ATV_TOP_SIF_TP__A 0xC10020 +#define ATV_TOP_SIF_TP__W 6 +#define ATV_TOP_SIF_TP__M 0x3F +#define ATV_TOP_SIF_TP__PRE 0x0 + +#define ATV_TOP_MOD_ACCU__A 0xC10021 +#define ATV_TOP_MOD_ACCU__W 10 +#define ATV_TOP_MOD_ACCU__M 0x3FF +#define ATV_TOP_MOD_ACCU__PRE 0x0 + +#define ATV_TOP_CR_FREQ__A 0xC10022 +#define ATV_TOP_CR_FREQ__W 8 +#define ATV_TOP_CR_FREQ__M 0xFF +#define ATV_TOP_CR_FREQ__PRE 0x0 + +#define ATV_TOP_CR_PHAD__A 0xC10023 +#define ATV_TOP_CR_PHAD__W 12 +#define ATV_TOP_CR_PHAD__M 0xFFF +#define ATV_TOP_CR_PHAD__PRE 0x0 + +#define ATV_TOP_AF_SIF_ATT__A 0xC10024 +#define ATV_TOP_AF_SIF_ATT__W 2 +#define ATV_TOP_AF_SIF_ATT__M 0x3 +#define ATV_TOP_AF_SIF_ATT__PRE 0x0 +#define ATV_TOP_AF_SIF_ATT_0DB 0x0 +#define ATV_TOP_AF_SIF_ATT_M3DB 0x1 +#define ATV_TOP_AF_SIF_ATT_M6DB 0x2 +#define ATV_TOP_AF_SIF_ATT_M9DB 0x3 + +#define ATV_TOP_STDBY__A 0xC10025 +#define ATV_TOP_STDBY__W 2 +#define ATV_TOP_STDBY__M 0x3 +#define ATV_TOP_STDBY__PRE 0x1 + +#define ATV_TOP_STDBY_SIF_STDBY__B 0 +#define ATV_TOP_STDBY_SIF_STDBY__W 1 +#define ATV_TOP_STDBY_SIF_STDBY__M 0x1 +#define ATV_TOP_STDBY_SIF_STDBY__PRE 0x1 +#define ATV_TOP_STDBY_SIF_STDBY_ACTIVE 0x0 +#define ATV_TOP_STDBY_SIF_STDBY_STANDBY 0x1 + +#define ATV_TOP_STDBY_CVBS_STDBY__B 1 +#define ATV_TOP_STDBY_CVBS_STDBY__W 1 +#define ATV_TOP_STDBY_CVBS_STDBY__M 0x2 +#define ATV_TOP_STDBY_CVBS_STDBY__PRE 0x0 +#define ATV_TOP_STDBY_CVBS_STDBY_A1_ACTIVE 0x0 +#define ATV_TOP_STDBY_CVBS_STDBY_A1_STANDBY 0x2 +#define ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE 0x2 +#define ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY 0x0 + +#define ATV_TOP_OVERRIDE_SFR__A 0xC10026 +#define ATV_TOP_OVERRIDE_SFR__W 1 +#define ATV_TOP_OVERRIDE_SFR__M 0x1 +#define ATV_TOP_OVERRIDE_SFR__PRE 0x0 +#define ATV_TOP_OVERRIDE_SFR_ACTIVE 0x0 +#define ATV_TOP_OVERRIDE_SFR_OVERRIDE 0x1 + +#define ATV_TOP_SFR_VID_GAIN__A 0xC10027 +#define ATV_TOP_SFR_VID_GAIN__W 16 +#define ATV_TOP_SFR_VID_GAIN__M 0xFFFF +#define ATV_TOP_SFR_VID_GAIN__PRE 0x0 + +#define ATV_TOP_SFR_AGC_RES__A 0xC10028 +#define ATV_TOP_SFR_AGC_RES__W 5 +#define ATV_TOP_SFR_AGC_RES__M 0x1F +#define ATV_TOP_SFR_AGC_RES__PRE 0x0 + +#define ATV_TOP_OVM_COMP__A 0xC10029 +#define ATV_TOP_OVM_COMP__W 12 +#define ATV_TOP_OVM_COMP__M 0xFFF +#define ATV_TOP_OVM_COMP__PRE 0x0 +#define ATV_TOP_OUT_CONF__A 0xC1002A +#define ATV_TOP_OUT_CONF__W 5 +#define ATV_TOP_OUT_CONF__M 0x1F +#define ATV_TOP_OUT_CONF__PRE 0x0 + +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__B 0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__W 1 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__M 0x1 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__PRE 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_UNSIGNED 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_SIGNED 0x1 + +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__B 1 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__W 1 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__M 0x2 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__PRE 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_UNSIGNED 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_SIGNED 0x2 + +#define ATV_TOP_OUT_CONF_SIF20_SIGN__B 2 +#define ATV_TOP_OUT_CONF_SIF20_SIGN__W 1 +#define ATV_TOP_OUT_CONF_SIF20_SIGN__M 0x4 +#define ATV_TOP_OUT_CONF_SIF20_SIGN__PRE 0x0 +#define ATV_TOP_OUT_CONF_SIF20_SIGN_UNSIGNED 0x0 +#define ATV_TOP_OUT_CONF_SIF20_SIGN_SIGNED 0x4 + +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__B 3 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__W 1 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__M 0x8 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__PRE 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_NORMAL 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_BITREVERSED 0x8 + +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__B 4 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__W 1 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__M 0x10 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__PRE 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED 0x10 + +#define ATV_AFT_COMM_EXEC__A 0xFF0000 +#define ATV_AFT_COMM_EXEC__W 2 +#define ATV_AFT_COMM_EXEC__M 0x3 +#define ATV_AFT_COMM_EXEC__PRE 0x0 +#define ATV_AFT_COMM_EXEC_STOP 0x0 +#define ATV_AFT_COMM_EXEC_ACTIVE 0x1 +#define ATV_AFT_COMM_EXEC_HOLD 0x2 + +#define ATV_AFT_TST__A 0xFF0010 +#define ATV_AFT_TST__W 4 +#define ATV_AFT_TST__M 0xF +#define ATV_AFT_TST__PRE 0x0 + +#define AUD_COMM_EXEC__A 0x1000000 +#define AUD_COMM_EXEC__W 2 +#define AUD_COMM_EXEC__M 0x3 +#define AUD_COMM_EXEC__PRE 0x0 +#define AUD_COMM_EXEC_STOP 0x0 +#define AUD_COMM_EXEC_ACTIVE 0x1 + +#define AUD_COMM_MB__A 0x1000002 +#define AUD_COMM_MB__W 16 +#define AUD_COMM_MB__M 0xFFFF +#define AUD_COMM_MB__PRE 0x0 + +#define AUD_TOP_COMM_EXEC__A 0x1010000 +#define AUD_TOP_COMM_EXEC__W 2 +#define AUD_TOP_COMM_EXEC__M 0x3 +#define AUD_TOP_COMM_EXEC__PRE 0x0 +#define AUD_TOP_COMM_EXEC_STOP 0x0 +#define AUD_TOP_COMM_EXEC_ACTIVE 0x1 + +#define AUD_TOP_COMM_MB__A 0x1010002 +#define AUD_TOP_COMM_MB__W 16 +#define AUD_TOP_COMM_MB__M 0xFFFF +#define AUD_TOP_COMM_MB__PRE 0x0 + +#define AUD_TOP_COMM_MB_CTL__B 0 +#define AUD_TOP_COMM_MB_CTL__W 1 +#define AUD_TOP_COMM_MB_CTL__M 0x1 +#define AUD_TOP_COMM_MB_CTL__PRE 0x0 +#define AUD_TOP_COMM_MB_CTL_CTR_OFF 0x0 +#define AUD_TOP_COMM_MB_CTL_CTR_ON 0x1 + +#define AUD_TOP_COMM_MB_OBS__B 1 +#define AUD_TOP_COMM_MB_OBS__W 1 +#define AUD_TOP_COMM_MB_OBS__M 0x2 +#define AUD_TOP_COMM_MB_OBS__PRE 0x0 +#define AUD_TOP_COMM_MB_OBS_OBS_OFF 0x0 +#define AUD_TOP_COMM_MB_OBS_OBS_ON 0x2 + +#define AUD_TOP_COMM_MB_MUX_CTRL__B 2 +#define AUD_TOP_COMM_MB_MUX_CTRL__W 4 +#define AUD_TOP_COMM_MB_MUX_CTRL__M 0x3C +#define AUD_TOP_COMM_MB_MUX_CTRL__PRE 0x0 +#define AUD_TOP_COMM_MB_MUX_CTRL_DEMOD_TBO 0x0 +#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_IRQS 0x4 +#define AUD_TOP_COMM_MB_MUX_CTRL_OBSERVEPC 0x8 +#define AUD_TOP_COMM_MB_MUX_CTRL_SAOUT 0xC +#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_SCHEQ 0x10 + +#define AUD_TOP_COMM_MB_MUX_OBS__B 6 +#define AUD_TOP_COMM_MB_MUX_OBS__W 4 +#define AUD_TOP_COMM_MB_MUX_OBS__M 0x3C0 +#define AUD_TOP_COMM_MB_MUX_OBS__PRE 0x0 +#define AUD_TOP_COMM_MB_MUX_OBS_DEMOD_TBO 0x0 +#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_IRQS 0x40 +#define AUD_TOP_COMM_MB_MUX_OBS_OBSERVEPC 0x80 +#define AUD_TOP_COMM_MB_MUX_OBS_SAOUT 0xC0 +#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_SCHEQ 0x100 + +#define AUD_TOP_TR_MDE__A 0x1010010 +#define AUD_TOP_TR_MDE__W 5 +#define AUD_TOP_TR_MDE__M 0x1F +#define AUD_TOP_TR_MDE__PRE 0x18 + +#define AUD_TOP_TR_MDE_FIFO_SIZE__B 0 +#define AUD_TOP_TR_MDE_FIFO_SIZE__W 4 +#define AUD_TOP_TR_MDE_FIFO_SIZE__M 0xF +#define AUD_TOP_TR_MDE_FIFO_SIZE__PRE 0x8 + +#define AUD_TOP_TR_MDE_RD_LOCK__B 4 +#define AUD_TOP_TR_MDE_RD_LOCK__W 1 +#define AUD_TOP_TR_MDE_RD_LOCK__M 0x10 +#define AUD_TOP_TR_MDE_RD_LOCK__PRE 0x10 +#define AUD_TOP_TR_MDE_RD_LOCK_NORMAL 0x0 +#define AUD_TOP_TR_MDE_RD_LOCK_LOCK 0x10 + +#define AUD_TOP_TR_CTR__A 0x1010011 +#define AUD_TOP_TR_CTR__W 4 +#define AUD_TOP_TR_CTR__M 0xF +#define AUD_TOP_TR_CTR__PRE 0x0 + +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__B 0 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__W 1 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__M 0x1 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY_NOT_READY 0x0 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY_READY 0x1 + +#define AUD_TOP_TR_CTR_FIFO_EMPTY__B 1 +#define AUD_TOP_TR_CTR_FIFO_EMPTY__W 1 +#define AUD_TOP_TR_CTR_FIFO_EMPTY__M 0x2 +#define AUD_TOP_TR_CTR_FIFO_EMPTY__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_EMPTY_NOT_EMPTY 0x0 +#define AUD_TOP_TR_CTR_FIFO_EMPTY_EMPTY 0x2 + +#define AUD_TOP_TR_CTR_FIFO_LOCK__B 2 +#define AUD_TOP_TR_CTR_FIFO_LOCK__W 1 +#define AUD_TOP_TR_CTR_FIFO_LOCK__M 0x4 +#define AUD_TOP_TR_CTR_FIFO_LOCK__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_LOCK_UNLOCKED 0x0 +#define AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED 0x4 + +#define AUD_TOP_TR_CTR_FIFO_FULL__B 3 +#define AUD_TOP_TR_CTR_FIFO_FULL__W 1 +#define AUD_TOP_TR_CTR_FIFO_FULL__M 0x8 +#define AUD_TOP_TR_CTR_FIFO_FULL__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_FULL_EMPTY 0x0 +#define AUD_TOP_TR_CTR_FIFO_FULL_FULL 0x8 + +#define AUD_TOP_TR_RD_REG__A 0x1010012 +#define AUD_TOP_TR_RD_REG__W 16 +#define AUD_TOP_TR_RD_REG__M 0xFFFF +#define AUD_TOP_TR_RD_REG__PRE 0x0 + +#define AUD_TOP_TR_RD_REG_RESULT__B 0 +#define AUD_TOP_TR_RD_REG_RESULT__W 16 +#define AUD_TOP_TR_RD_REG_RESULT__M 0xFFFF +#define AUD_TOP_TR_RD_REG_RESULT__PRE 0x0 + +#define AUD_TOP_TR_TIMER__A 0x1010013 +#define AUD_TOP_TR_TIMER__W 16 +#define AUD_TOP_TR_TIMER__M 0xFFFF +#define AUD_TOP_TR_TIMER__PRE 0x0 + +#define AUD_TOP_TR_TIMER_CYCLES__B 0 +#define AUD_TOP_TR_TIMER_CYCLES__W 16 +#define AUD_TOP_TR_TIMER_CYCLES__M 0xFFFF +#define AUD_TOP_TR_TIMER_CYCLES__PRE 0x0 + +#define AUD_TOP_DEMOD_TBO_SEL__A 0x1010014 +#define AUD_TOP_DEMOD_TBO_SEL__W 5 +#define AUD_TOP_DEMOD_TBO_SEL__M 0x1F +#define AUD_TOP_DEMOD_TBO_SEL__PRE 0x0 + +#define AUD_DEM_WR_MODUS__A 0x1030030 +#define AUD_DEM_WR_MODUS__W 16 +#define AUD_DEM_WR_MODUS__M 0xFFFF +#define AUD_DEM_WR_MODUS__PRE 0x0 + +#define AUD_DEM_WR_MODUS_MOD_ASS__B 0 +#define AUD_DEM_WR_MODUS_MOD_ASS__W 1 +#define AUD_DEM_WR_MODUS_MOD_ASS__M 0x1 +#define AUD_DEM_WR_MODUS_MOD_ASS__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_ASS_OFF 0x0 +#define AUD_DEM_WR_MODUS_MOD_ASS_ON 0x1 + +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__B 1 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__W 1 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__M 0x2 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR_DISABLE 0x0 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR_ENABLE 0x2 + +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__B 2 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__W 1 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M 0x4 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED 0x0 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED 0x4 + +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__B 8 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__W 1 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__M 0x100 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL 0x0 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION 0x100 + +#define AUD_DEM_WR_MODUS_MOD_CM_A__B 9 +#define AUD_DEM_WR_MODUS_MOD_CM_A__W 1 +#define AUD_DEM_WR_MODUS_MOD_CM_A__M 0x200 +#define AUD_DEM_WR_MODUS_MOD_CM_A__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_A_MUTE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_A_NOISE 0x200 + +#define AUD_DEM_WR_MODUS_MOD_CM_B__B 10 +#define AUD_DEM_WR_MODUS_MOD_CM_B__W 1 +#define AUD_DEM_WR_MODUS_MOD_CM_B__M 0x400 +#define AUD_DEM_WR_MODUS_MOD_CM_B__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_B_MUTE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_B_NOISE 0x400 + +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__B 11 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__W 1 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__M 0x800 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U 0x0 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U 0x800 + +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__B 12 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__W 1 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__M 0x1000 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM 0x0 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K 0x1000 + +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__B 13 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__W 2 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__M 0x6000 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_KOREA 0x0 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC 0x2000 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_EIAJ 0x4000 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA 0x6000 + +#define AUD_DEM_WR_MODUS_MOD_BTSC__B 15 +#define AUD_DEM_WR_MODUS_MOD_BTSC__W 1 +#define AUD_DEM_WR_MODUS_MOD_BTSC__M 0x8000 +#define AUD_DEM_WR_MODUS_MOD_BTSC__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO 0x0 +#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP 0x8000 + +#define AUD_DEM_WR_STANDARD_SEL__A 0x1030020 +#define AUD_DEM_WR_STANDARD_SEL__W 16 +#define AUD_DEM_WR_STANDARD_SEL__M 0xFFFF +#define AUD_DEM_WR_STANDARD_SEL__PRE 0x0 + +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__B 0 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__W 12 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__M 0xFFF +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__PRE 0x0 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO 0x1 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA 0x2 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM 0x3 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1 0x4 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2 0x5 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3 0x7 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM 0x8 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM 0x9 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM 0xA +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM 0xB +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO 0x20 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP 0x21 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J 0x30 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO 0x40 + +#define AUD_DEM_RD_STANDARD_RES__A 0x102007E +#define AUD_DEM_RD_STANDARD_RES__W 16 +#define AUD_DEM_RD_STANDARD_RES__M 0xFFFF +#define AUD_DEM_RD_STANDARD_RES__PRE 0x0 + +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__B 0 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__W 16 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__M 0xFFFF +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__PRE 0x0 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD 0x0 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM 0x2 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM 0x3 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM 0x4 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM 0x5 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM 0x7 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM 0x8 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM 0x9 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM 0xA +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM 0xB +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO 0x20 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP 0x21 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J 0x30 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO 0x40 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE 0x7FF + +#define AUD_DEM_RD_STATUS__A 0x1020200 +#define AUD_DEM_RD_STATUS__W 16 +#define AUD_DEM_RD_STATUS__M 0xFFFF +#define AUD_DEM_RD_STATUS__PRE 0x0 + +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__B 0 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__W 1 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__M 0x1 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NO_RDS_DATA 0x0 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NEW_RDS_DATA 0x1 + +#define AUD_DEM_RD_STATUS_STAT_CARR_A__B 1 +#define AUD_DEM_RD_STATUS_STAT_CARR_A__W 1 +#define AUD_DEM_RD_STATUS_STAT_CARR_A__M 0x2 +#define AUD_DEM_RD_STATUS_STAT_CARR_A__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_A_NOT_DETECTED 0x2 + +#define AUD_DEM_RD_STATUS_STAT_CARR_B__B 2 +#define AUD_DEM_RD_STATUS_STAT_CARR_B__W 1 +#define AUD_DEM_RD_STATUS_STAT_CARR_B__M 0x4 +#define AUD_DEM_RD_STATUS_STAT_CARR_B__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_B_NOT_DETECTED 0x4 + +#define AUD_DEM_RD_STATUS_STAT_NICAM__B 5 +#define AUD_DEM_RD_STATUS_STAT_NICAM__W 1 +#define AUD_DEM_RD_STATUS_STAT_NICAM__M 0x20 +#define AUD_DEM_RD_STATUS_STAT_NICAM__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_NICAM_NO_NICAM 0x0 +#define AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED 0x20 + +#define AUD_DEM_RD_STATUS_STAT_STEREO__B 6 +#define AUD_DEM_RD_STATUS_STAT_STEREO__W 1 +#define AUD_DEM_RD_STATUS_STAT_STEREO__M 0x40 +#define AUD_DEM_RD_STATUS_STAT_STEREO__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_STEREO_NO_STEREO 0x0 +#define AUD_DEM_RD_STATUS_STAT_STEREO_STEREO 0x40 + +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__B 7 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__W 1 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__M 0x80 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_DEPENDENT_FM_MONO_PROGRAM 0x0 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_INDEPENDENT_FM_MONO_PROGRAM 0x80 + +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__B 8 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__W 1 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M 0x100 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_NO_SAP 0x0 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP 0x100 + +#define AUD_DEM_RD_STATUS_BAD_NICAM__B 9 +#define AUD_DEM_RD_STATUS_BAD_NICAM__W 1 +#define AUD_DEM_RD_STATUS_BAD_NICAM__M 0x200 +#define AUD_DEM_RD_STATUS_BAD_NICAM__PRE 0x0 +#define AUD_DEM_RD_STATUS_BAD_NICAM_OK 0x0 +#define AUD_DEM_RD_STATUS_BAD_NICAM_BAD 0x200 + +#define AUD_DEM_RD_RDS_ARRAY_CNT__A 0x102020F +#define AUD_DEM_RD_RDS_ARRAY_CNT__W 12 +#define AUD_DEM_RD_RDS_ARRAY_CNT__M 0xFFF +#define AUD_DEM_RD_RDS_ARRAY_CNT__PRE 0x0 + +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__B 0 +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__W 12 +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__M 0xFFF +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE 0x0 +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID 0xFFF + +#define AUD_DEM_RD_RDS_DATA__A 0x1020210 +#define AUD_DEM_RD_RDS_DATA__W 12 +#define AUD_DEM_RD_RDS_DATA__M 0xFFF +#define AUD_DEM_RD_RDS_DATA__PRE 0x0 + +#define AUD_DSP_WR_FM_PRESC__A 0x105000E +#define AUD_DSP_WR_FM_PRESC__W 16 +#define AUD_DSP_WR_FM_PRESC__M 0xFFFF +#define AUD_DSP_WR_FM_PRESC__PRE 0x0 + +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B 8 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__W 8 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__M 0xFF00 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__PRE 0x0 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION 0x7F00 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_50_KHZ_FM_DEVIATION 0x4800 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_75_KHZ_FM_DEVIATION 0x3000 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_100_KHZ_FM_DEVIATION 0x2400 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_150_KHZ_FM_DEVIATION 0x1800 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION 0x1300 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION 0x900 + +#define AUD_DSP_WR_NICAM_PRESC__A 0x1050010 +#define AUD_DSP_WR_NICAM_PRESC__W 16 +#define AUD_DSP_WR_NICAM_PRESC__M 0xFFFF +#define AUD_DSP_WR_NICAM_PRESC__PRE 0x0 +#define AUD_DSP_WR_VOLUME__A 0x1050000 +#define AUD_DSP_WR_VOLUME__W 16 +#define AUD_DSP_WR_VOLUME__M 0xFFFF +#define AUD_DSP_WR_VOLUME__PRE 0x0 + +#define AUD_DSP_WR_VOLUME_VOL_MAIN__B 8 +#define AUD_DSP_WR_VOLUME_VOL_MAIN__W 8 +#define AUD_DSP_WR_VOLUME_VOL_MAIN__M 0xFF00 +#define AUD_DSP_WR_VOLUME_VOL_MAIN__PRE 0x0 + +#define AUD_DSP_WR_SRC_I2S_MATR__A 0x1050038 +#define AUD_DSP_WR_SRC_I2S_MATR__W 16 +#define AUD_DSP_WR_SRC_I2S_MATR__M 0xFFFF +#define AUD_DSP_WR_SRC_I2S_MATR__PRE 0x0 + +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__B 8 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__W 8 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M 0xFF00 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__PRE 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB 0x100 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A 0x300 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B 0x400 + +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__B 0 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__W 8 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M 0xFF +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__PRE 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B 0x10 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO 0x20 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO 0x30 + +#define AUD_DSP_WR_AVC__A 0x1050029 +#define AUD_DSP_WR_AVC__W 16 +#define AUD_DSP_WR_AVC__M 0xFFFF +#define AUD_DSP_WR_AVC__PRE 0x0 + +#define AUD_DSP_WR_AVC_AVC_ON__B 14 +#define AUD_DSP_WR_AVC_AVC_ON__W 2 +#define AUD_DSP_WR_AVC_AVC_ON__M 0xC000 +#define AUD_DSP_WR_AVC_AVC_ON__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_ON_OFF 0x0 +#define AUD_DSP_WR_AVC_AVC_ON_ON 0xC000 + +#define AUD_DSP_WR_AVC_AVC_DECAY__B 8 +#define AUD_DSP_WR_AVC_AVC_DECAY__W 4 +#define AUD_DSP_WR_AVC_AVC_DECAY__M 0xF00 +#define AUD_DSP_WR_AVC_AVC_DECAY__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_DECAY_8_SEC 0x800 +#define AUD_DSP_WR_AVC_AVC_DECAY_4_SEC 0x400 +#define AUD_DSP_WR_AVC_AVC_DECAY_2_SEC 0x200 +#define AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC 0x100 + +#define AUD_DSP_WR_AVC_AVC_REF_LEV__B 4 +#define AUD_DSP_WR_AVC_AVC_REF_LEV__W 4 +#define AUD_DSP_WR_AVC_AVC_REF_LEV__M 0xF0 +#define AUD_DSP_WR_AVC_AVC_REF_LEV__PRE 0x0 + +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__B 2 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__W 2 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__M 0xC +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB 0x4 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB 0x8 + +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__B 0 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__W 2 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__M 0x3 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB 0x1 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB 0x3 + +#define AUD_DSP_WR_QPEAK__A 0x105000C +#define AUD_DSP_WR_QPEAK__W 16 +#define AUD_DSP_WR_QPEAK__M 0xFFFF +#define AUD_DSP_WR_QPEAK__PRE 0x0 + +#define AUD_DSP_WR_QPEAK_SRC_QP__B 8 +#define AUD_DSP_WR_QPEAK_SRC_QP__W 8 +#define AUD_DSP_WR_QPEAK_SRC_QP__M 0xFF00 +#define AUD_DSP_WR_QPEAK_SRC_QP__PRE 0x0 +#define AUD_DSP_WR_QPEAK_SRC_QP_MONO 0x0 +#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_AB 0x100 +#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_A 0x300 +#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_B 0x400 + +#define AUD_DSP_WR_QPEAK_MAT_QP__B 0 +#define AUD_DSP_WR_QPEAK_MAT_QP__W 8 +#define AUD_DSP_WR_QPEAK_MAT_QP__M 0xFF +#define AUD_DSP_WR_QPEAK_MAT_QP__PRE 0x0 +#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_A 0x0 +#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_B 0x10 +#define AUD_DSP_WR_QPEAK_MAT_QP_STEREO 0x20 +#define AUD_DSP_WR_QPEAK_MAT_QP_MONO 0x30 + +#define AUD_DSP_RD_QPEAK_L__A 0x1040019 +#define AUD_DSP_RD_QPEAK_L__W 16 +#define AUD_DSP_RD_QPEAK_L__M 0xFFFF +#define AUD_DSP_RD_QPEAK_L__PRE 0x0 + +#define AUD_DSP_RD_QPEAK_R__A 0x104001A +#define AUD_DSP_RD_QPEAK_R__W 16 +#define AUD_DSP_RD_QPEAK_R__M 0xFFFF +#define AUD_DSP_RD_QPEAK_R__PRE 0x0 + +#define AUD_DSP_WR_BEEPER__A 0x1050014 +#define AUD_DSP_WR_BEEPER__W 16 +#define AUD_DSP_WR_BEEPER__M 0xFFFF +#define AUD_DSP_WR_BEEPER__PRE 0x0 + +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__B 8 +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__W 7 +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__M 0x7F00 +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__PRE 0x0 + +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__B 0 +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__W 7 +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M 0x7F +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__PRE 0x0 + +#define AUD_DEM_WR_I2S_CONFIG2__A 0x1030050 +#define AUD_DEM_WR_I2S_CONFIG2__W 16 +#define AUD_DEM_WR_I2S_CONFIG2__M 0xFFFF +#define AUD_DEM_WR_I2S_CONFIG2__PRE 0x0 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__B 6 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__M 0x40 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_NORMAL 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_INVERTED 0x40 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__B 4 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M 0x10 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE 0x10 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__B 3 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M 0x8 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE 0x8 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__B 2 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M 0x4 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH 0x4 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__B 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M 0x2 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY 0x2 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__B 0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M 0x1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16 0x1 + +#define AUD_DSP_WR_I2S_OUT_FS__A 0x105002A +#define AUD_DSP_WR_I2S_OUT_FS__W 16 +#define AUD_DSP_WR_I2S_OUT_FS__M 0xFFFF +#define AUD_DSP_WR_I2S_OUT_FS__PRE 0x0 + +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__B 0 +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__W 16 +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__M 0xFFFF +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__PRE 0x0 + +#define AUD_DSP_WR_AV_SYNC__A 0x105002B +#define AUD_DSP_WR_AV_SYNC__W 16 +#define AUD_DSP_WR_AV_SYNC__M 0xFFFF +#define AUD_DSP_WR_AV_SYNC__PRE 0x0 + +#define AUD_DSP_WR_AV_SYNC_AV_ON__B 15 +#define AUD_DSP_WR_AV_SYNC_AV_ON__W 1 +#define AUD_DSP_WR_AV_SYNC_AV_ON__M 0x8000 +#define AUD_DSP_WR_AV_SYNC_AV_ON__PRE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE 0x8000 + +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__B 14 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__W 1 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__M 0x4000 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__PRE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_MONOCHROME 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_NTSC 0x4000 + +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__B 0 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__W 2 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M 0x3 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__PRE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_AUTO 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM 0x1 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC 0x2 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME 0x3 + +#define AUD_DSP_RD_STATUS2__A 0x104007B +#define AUD_DSP_RD_STATUS2__W 16 +#define AUD_DSP_RD_STATUS2__M 0xFFFF +#define AUD_DSP_RD_STATUS2__PRE 0x0 + +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__B 15 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__W 1 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__M 0x8000 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__PRE 0x0 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE_NO_SYNC 0x0 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE_SYNC_ACTIVE 0x8000 + +#define AUD_DSP_RD_XDFP_FW__A 0x104001D +#define AUD_DSP_RD_XDFP_FW__W 16 +#define AUD_DSP_RD_XDFP_FW__M 0xFFFF +#define AUD_DSP_RD_XDFP_FW__PRE 0x344 + +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__B 0 +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__W 16 +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__M 0xFFFF +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__PRE 0x344 + +#define AUD_DSP_RD_XFP_FW__A 0x10404B8 +#define AUD_DSP_RD_XFP_FW__W 16 +#define AUD_DSP_RD_XFP_FW__M 0xFFFF +#define AUD_DSP_RD_XFP_FW__PRE 0x42 + +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__B 0 +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__W 16 +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__M 0xFFFF +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__PRE 0x42 + +#define AUD_DEM_WR_DCO_B_HI__A 0x103009B +#define AUD_DEM_WR_DCO_B_HI__W 16 +#define AUD_DEM_WR_DCO_B_HI__M 0xFFFF +#define AUD_DEM_WR_DCO_B_HI__PRE 0x0 + +#define AUD_DEM_WR_DCO_B_LO__A 0x1030093 +#define AUD_DEM_WR_DCO_B_LO__W 16 +#define AUD_DEM_WR_DCO_B_LO__M 0xFFFF +#define AUD_DEM_WR_DCO_B_LO__PRE 0x0 + +#define AUD_DEM_WR_DCO_A_HI__A 0x10300AB +#define AUD_DEM_WR_DCO_A_HI__W 16 +#define AUD_DEM_WR_DCO_A_HI__M 0xFFFF +#define AUD_DEM_WR_DCO_A_HI__PRE 0x0 + +#define AUD_DEM_WR_DCO_A_LO__A 0x10300A3 +#define AUD_DEM_WR_DCO_A_LO__W 16 +#define AUD_DEM_WR_DCO_A_LO__M 0xFFFF +#define AUD_DEM_WR_DCO_A_LO__PRE 0x0 +#define AUD_DEM_WR_NICAM_THRSHLD__A 0x1030021 +#define AUD_DEM_WR_NICAM_THRSHLD__W 16 +#define AUD_DEM_WR_NICAM_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_NICAM_THRSHLD__PRE 0x2BC + +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__B 0 +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__W 12 +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__M 0xFFF +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__PRE 0x2BC + +#define AUD_DEM_WR_A2_THRSHLD__A 0x1030022 +#define AUD_DEM_WR_A2_THRSHLD__W 16 +#define AUD_DEM_WR_A2_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_A2_THRSHLD__PRE 0x190 + +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__B 0 +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__W 12 +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__M 0xFFF +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__PRE 0x190 + +#define AUD_DEM_WR_BTSC_THRSHLD__A 0x1030023 +#define AUD_DEM_WR_BTSC_THRSHLD__W 16 +#define AUD_DEM_WR_BTSC_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_BTSC_THRSHLD__PRE 0xC + +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__B 0 +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__W 12 +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__M 0xFFF +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__PRE 0xC + +#define AUD_DEM_WR_CM_A_THRSHLD__A 0x1030024 +#define AUD_DEM_WR_CM_A_THRSHLD__W 16 +#define AUD_DEM_WR_CM_A_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_CM_A_THRSHLD__PRE 0x2A + +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__B 0 +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__W 12 +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__M 0xFFF +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__PRE 0x2A + +#define AUD_DEM_WR_CM_B_THRSHLD__A 0x1030025 +#define AUD_DEM_WR_CM_B_THRSHLD__W 16 +#define AUD_DEM_WR_CM_B_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_CM_B_THRSHLD__PRE 0x2A + +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__B 0 +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__W 12 +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__M 0xFFF +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__PRE 0x2A + +#define AUD_DEM_RD_NIC_C_AD_BITS__A 0x1020023 +#define AUD_DEM_RD_NIC_C_AD_BITS__W 16 +#define AUD_DEM_RD_NIC_C_AD_BITS__M 0xFFFF +#define AUD_DEM_RD_NIC_C_AD_BITS__PRE 0x0 + +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__B 0 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__W 1 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__M 0x1 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__PRE 0x0 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_NOT_SYNCED 0x0 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_SYNCED 0x1 + +#define AUD_DEM_RD_NIC_C_AD_BITS_C__B 1 +#define AUD_DEM_RD_NIC_C_AD_BITS_C__W 4 +#define AUD_DEM_RD_NIC_C_AD_BITS_C__M 0x1E +#define AUD_DEM_RD_NIC_C_AD_BITS_C__PRE 0x0 + +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__B 5 +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__W 3 +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__M 0xE0 +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__PRE 0x0 + +#define AUD_DEM_RD_NIC_ADD_BITS_HI__A 0x1020038 +#define AUD_DEM_RD_NIC_ADD_BITS_HI__W 16 +#define AUD_DEM_RD_NIC_ADD_BITS_HI__M 0xFFFF +#define AUD_DEM_RD_NIC_ADD_BITS_HI__PRE 0x0 + +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__B 0 +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__W 8 +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__M 0xFF +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__PRE 0x0 + +#define AUD_DEM_RD_NIC_CIB__A 0x1020038 +#define AUD_DEM_RD_NIC_CIB__W 16 +#define AUD_DEM_RD_NIC_CIB__M 0xFFFF +#define AUD_DEM_RD_NIC_CIB__PRE 0x0 + +#define AUD_DEM_RD_NIC_CIB_CIB2__B 0 +#define AUD_DEM_RD_NIC_CIB_CIB2__W 1 +#define AUD_DEM_RD_NIC_CIB_CIB2__M 0x1 +#define AUD_DEM_RD_NIC_CIB_CIB2__PRE 0x0 + +#define AUD_DEM_RD_NIC_CIB_CIB1__B 1 +#define AUD_DEM_RD_NIC_CIB_CIB1__W 1 +#define AUD_DEM_RD_NIC_CIB_CIB1__M 0x2 +#define AUD_DEM_RD_NIC_CIB_CIB1__PRE 0x0 + +#define AUD_DEM_RD_NIC_ERROR_RATE__A 0x1020057 +#define AUD_DEM_RD_NIC_ERROR_RATE__W 16 +#define AUD_DEM_RD_NIC_ERROR_RATE__M 0xFFFF +#define AUD_DEM_RD_NIC_ERROR_RATE__PRE 0x0 + +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__B 0 +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__W 12 +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__M 0xFFF +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__PRE 0x0 + +#define AUD_DEM_WR_FM_DEEMPH__A 0x103000F +#define AUD_DEM_WR_FM_DEEMPH__W 16 +#define AUD_DEM_WR_FM_DEEMPH__M 0xFFFF +#define AUD_DEM_WR_FM_DEEMPH__PRE 0x0 +#define AUD_DEM_WR_FM_DEEMPH_50US 0x0 +#define AUD_DEM_WR_FM_DEEMPH_75US 0x1 +#define AUD_DEM_WR_FM_DEEMPH_OFF 0x3F + +#define AUD_DEM_WR_FM_MATRIX__A 0x103006F +#define AUD_DEM_WR_FM_MATRIX__W 16 +#define AUD_DEM_WR_FM_MATRIX__M 0xFFFF +#define AUD_DEM_WR_FM_MATRIX__PRE 0x0 +#define AUD_DEM_WR_FM_MATRIX_NO_MATRIX 0x0 +#define AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX 0x1 +#define AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX 0x2 +#define AUD_DEM_WR_FM_MATRIX_SOUND_A 0x3 +#define AUD_DEM_WR_FM_MATRIX_SOUND_B 0x4 + +#define AUD_DSP_RD_FM_IDENT_VALUE__A 0x1040018 +#define AUD_DSP_RD_FM_IDENT_VALUE__W 16 +#define AUD_DSP_RD_FM_IDENT_VALUE__M 0xFFFF +#define AUD_DSP_RD_FM_IDENT_VALUE__PRE 0x0 + +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B 8 +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__W 8 +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__M 0xFF00 +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_A__A 0x104001B +#define AUD_DSP_RD_FM_DC_LEVEL_A__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_A__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_A__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__B 0 +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_B__A 0x104001C +#define AUD_DSP_RD_FM_DC_LEVEL_B__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_B__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_B__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__B 0 +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__PRE 0x0 + +#define AUD_DEM_WR_FM_DC_NOTCH_SW__A 0x1030017 +#define AUD_DEM_WR_FM_DC_NOTCH_SW__W 16 +#define AUD_DEM_WR_FM_DC_NOTCH_SW__M 0xFFFF +#define AUD_DEM_WR_FM_DC_NOTCH_SW__PRE 0x0 + +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__B 0 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__W 16 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__M 0xFFFF +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__PRE 0x0 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_ON 0x0 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_OFF 0x3F + +#define AUD_DSP_WR_SYNC_OUT__A 0x1050026 +#define AUD_DSP_WR_SYNC_OUT__W 16 +#define AUD_DSP_WR_SYNC_OUT__M 0xFFFF +#define AUD_DSP_WR_SYNC_OUT__PRE 0x0 +#define AUD_DSP_WR_SYNC_OUT_OFF 0x0 +#define AUD_DSP_WR_SYNC_OUT_SYNCHRONOUS 0x1 + +#define AUD_XFP_DRAM_1K__A 0x1060000 +#define AUD_XFP_DRAM_1K__W 16 +#define AUD_XFP_DRAM_1K__M 0xFFFF +#define AUD_XFP_DRAM_1K__PRE 0x0 +#define AUD_XFP_DRAM_1K_D__B 0 +#define AUD_XFP_DRAM_1K_D__W 16 +#define AUD_XFP_DRAM_1K_D__M 0xFFFF +#define AUD_XFP_DRAM_1K_D__PRE 0x0 + +#define AUD_XFP_PRAM_4K__A 0x1070000 +#define AUD_XFP_PRAM_4K__W 16 +#define AUD_XFP_PRAM_4K__M 0xFFFF +#define AUD_XFP_PRAM_4K__PRE 0x0 +#define AUD_XFP_PRAM_4K_D__B 0 +#define AUD_XFP_PRAM_4K_D__W 16 +#define AUD_XFP_PRAM_4K_D__M 0xFFFF +#define AUD_XFP_PRAM_4K_D__PRE 0x0 + +#define AUD_XDFP_DRAM_1K__A 0x1080000 +#define AUD_XDFP_DRAM_1K__W 16 +#define AUD_XDFP_DRAM_1K__M 0xFFFF +#define AUD_XDFP_DRAM_1K__PRE 0x0 +#define AUD_XDFP_DRAM_1K_D__B 0 +#define AUD_XDFP_DRAM_1K_D__W 16 +#define AUD_XDFP_DRAM_1K_D__M 0xFFFF +#define AUD_XDFP_DRAM_1K_D__PRE 0x0 + +#define AUD_XDFP_PRAM_4K__A 0x1090000 +#define AUD_XDFP_PRAM_4K__W 16 +#define AUD_XDFP_PRAM_4K__M 0xFFFF +#define AUD_XDFP_PRAM_4K__PRE 0x0 +#define AUD_XDFP_PRAM_4K_D__B 0 +#define AUD_XDFP_PRAM_4K_D__W 16 +#define AUD_XDFP_PRAM_4K_D__M 0xFFFF +#define AUD_XDFP_PRAM_4K_D__PRE 0x0 + +#define FEC_COMM_EXEC__A 0x2400000 +#define FEC_COMM_EXEC__W 2 +#define FEC_COMM_EXEC__M 0x3 +#define FEC_COMM_EXEC__PRE 0x0 +#define FEC_COMM_EXEC_STOP 0x0 +#define FEC_COMM_EXEC_ACTIVE 0x1 +#define FEC_COMM_EXEC_HOLD 0x2 + +#define FEC_COMM_MB__A 0x2400002 +#define FEC_COMM_MB__W 16 +#define FEC_COMM_MB__M 0xFFFF +#define FEC_COMM_MB__PRE 0x0 +#define FEC_COMM_INT_REQ__A 0x2400003 +#define FEC_COMM_INT_REQ__W 16 +#define FEC_COMM_INT_REQ__M 0xFFFF +#define FEC_COMM_INT_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_OC_REQ__B 0 +#define FEC_COMM_INT_REQ_OC_REQ__W 1 +#define FEC_COMM_INT_REQ_OC_REQ__M 0x1 +#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_RS_REQ__B 1 +#define FEC_COMM_INT_REQ_RS_REQ__W 1 +#define FEC_COMM_INT_REQ_RS_REQ__M 0x2 +#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_DI_REQ__B 2 +#define FEC_COMM_INT_REQ_DI_REQ__W 1 +#define FEC_COMM_INT_REQ_DI_REQ__M 0x4 +#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x0 + +#define FEC_COMM_INT_STA__A 0x2400005 +#define FEC_COMM_INT_STA__W 16 +#define FEC_COMM_INT_STA__M 0xFFFF +#define FEC_COMM_INT_STA__PRE 0x0 +#define FEC_COMM_INT_MSK__A 0x2400006 +#define FEC_COMM_INT_MSK__W 16 +#define FEC_COMM_INT_MSK__M 0xFFFF +#define FEC_COMM_INT_MSK__PRE 0x0 +#define FEC_COMM_INT_STM__A 0x2400007 +#define FEC_COMM_INT_STM__W 16 +#define FEC_COMM_INT_STM__M 0xFFFF +#define FEC_COMM_INT_STM__PRE 0x0 + +#define FEC_TOP_COMM_EXEC__A 0x2410000 +#define FEC_TOP_COMM_EXEC__W 2 +#define FEC_TOP_COMM_EXEC__M 0x3 +#define FEC_TOP_COMM_EXEC__PRE 0x0 +#define FEC_TOP_COMM_EXEC_STOP 0x0 +#define FEC_TOP_COMM_EXEC_ACTIVE 0x1 +#define FEC_TOP_COMM_EXEC_HOLD 0x2 + +#define FEC_TOP_ANNEX__A 0x2410010 +#define FEC_TOP_ANNEX__W 2 +#define FEC_TOP_ANNEX__M 0x3 +#define FEC_TOP_ANNEX__PRE 0x0 +#define FEC_TOP_ANNEX_A 0x0 +#define FEC_TOP_ANNEX_B 0x1 +#define FEC_TOP_ANNEX_C 0x2 +#define FEC_TOP_ANNEX_D 0x3 + +#define FEC_DI_COMM_EXEC__A 0x2420000 +#define FEC_DI_COMM_EXEC__W 2 +#define FEC_DI_COMM_EXEC__M 0x3 +#define FEC_DI_COMM_EXEC__PRE 0x0 +#define FEC_DI_COMM_EXEC_STOP 0x0 +#define FEC_DI_COMM_EXEC_ACTIVE 0x1 +#define FEC_DI_COMM_EXEC_HOLD 0x2 + +#define FEC_DI_COMM_MB__A 0x2420002 +#define FEC_DI_COMM_MB__W 2 +#define FEC_DI_COMM_MB__M 0x3 +#define FEC_DI_COMM_MB__PRE 0x0 +#define FEC_DI_COMM_MB_CTL__B 0 +#define FEC_DI_COMM_MB_CTL__W 1 +#define FEC_DI_COMM_MB_CTL__M 0x1 +#define FEC_DI_COMM_MB_CTL__PRE 0x0 +#define FEC_DI_COMM_MB_CTL_OFF 0x0 +#define FEC_DI_COMM_MB_CTL_ON 0x1 +#define FEC_DI_COMM_MB_OBS__B 1 +#define FEC_DI_COMM_MB_OBS__W 1 +#define FEC_DI_COMM_MB_OBS__M 0x2 +#define FEC_DI_COMM_MB_OBS__PRE 0x0 +#define FEC_DI_COMM_MB_OBS_OFF 0x0 +#define FEC_DI_COMM_MB_OBS_ON 0x2 + +#define FEC_DI_COMM_INT_REQ__A 0x2420003 +#define FEC_DI_COMM_INT_REQ__W 1 +#define FEC_DI_COMM_INT_REQ__M 0x1 +#define FEC_DI_COMM_INT_REQ__PRE 0x0 +#define FEC_DI_COMM_INT_STA__A 0x2420005 +#define FEC_DI_COMM_INT_STA__W 2 +#define FEC_DI_COMM_INT_STA__M 0x3 +#define FEC_DI_COMM_INT_STA__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STA_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_MSK__A 0x2420006 +#define FEC_DI_COMM_INT_MSK__W 2 +#define FEC_DI_COMM_INT_MSK__M 0x3 +#define FEC_DI_COMM_INT_MSK__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STM__A 0x2420007 +#define FEC_DI_COMM_INT_STM__W 2 +#define FEC_DI_COMM_INT_STM__M 0x3 +#define FEC_DI_COMM_INT_STM__PRE 0x0 +#define FEC_DI_COMM_INT_STM_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STM_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_STATUS__A 0x2420010 +#define FEC_DI_STATUS__W 1 +#define FEC_DI_STATUS__M 0x1 +#define FEC_DI_STATUS__PRE 0x0 +#define FEC_DI_MODE__A 0x2420011 +#define FEC_DI_MODE__W 3 +#define FEC_DI_MODE__M 0x7 +#define FEC_DI_MODE__PRE 0x0 + +#define FEC_DI_MODE_NO_SYNC__B 0 +#define FEC_DI_MODE_NO_SYNC__W 1 +#define FEC_DI_MODE_NO_SYNC__M 0x1 +#define FEC_DI_MODE_NO_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2 +#define FEC_DI_MODE_IGNORE_TIMEOUT__W 1 +#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4 +#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0 + +#define FEC_DI_CONTROL_WORD__A 0x2420012 +#define FEC_DI_CONTROL_WORD__W 4 +#define FEC_DI_CONTROL_WORD__M 0xF +#define FEC_DI_CONTROL_WORD__PRE 0x0 + +#define FEC_DI_RESTART__A 0x2420013 +#define FEC_DI_RESTART__W 1 +#define FEC_DI_RESTART__M 0x1 +#define FEC_DI_RESTART__PRE 0x0 + +#define FEC_DI_TIMEOUT_LO__A 0x2420014 +#define FEC_DI_TIMEOUT_LO__W 16 +#define FEC_DI_TIMEOUT_LO__M 0xFFFF +#define FEC_DI_TIMEOUT_LO__PRE 0x0 + +#define FEC_DI_TIMEOUT_HI__A 0x2420015 +#define FEC_DI_TIMEOUT_HI__W 8 +#define FEC_DI_TIMEOUT_HI__M 0xFF +#define FEC_DI_TIMEOUT_HI__PRE 0xA + +#define FEC_RS_COMM_EXEC__A 0x2430000 +#define FEC_RS_COMM_EXEC__W 2 +#define FEC_RS_COMM_EXEC__M 0x3 +#define FEC_RS_COMM_EXEC__PRE 0x0 +#define FEC_RS_COMM_EXEC_STOP 0x0 +#define FEC_RS_COMM_EXEC_ACTIVE 0x1 +#define FEC_RS_COMM_EXEC_HOLD 0x2 + +#define FEC_RS_COMM_MB__A 0x2430002 +#define FEC_RS_COMM_MB__W 2 +#define FEC_RS_COMM_MB__M 0x3 +#define FEC_RS_COMM_MB__PRE 0x0 +#define FEC_RS_COMM_MB_CTL__B 0 +#define FEC_RS_COMM_MB_CTL__W 1 +#define FEC_RS_COMM_MB_CTL__M 0x1 +#define FEC_RS_COMM_MB_CTL__PRE 0x0 +#define FEC_RS_COMM_MB_CTL_OFF 0x0 +#define FEC_RS_COMM_MB_CTL_ON 0x1 +#define FEC_RS_COMM_MB_OBS__B 1 +#define FEC_RS_COMM_MB_OBS__W 1 +#define FEC_RS_COMM_MB_OBS__M 0x2 +#define FEC_RS_COMM_MB_OBS__PRE 0x0 +#define FEC_RS_COMM_MB_OBS_OFF 0x0 +#define FEC_RS_COMM_MB_OBS_ON 0x2 + +#define FEC_RS_COMM_INT_REQ__A 0x2430003 +#define FEC_RS_COMM_INT_REQ__W 1 +#define FEC_RS_COMM_INT_REQ__M 0x1 +#define FEC_RS_COMM_INT_REQ__PRE 0x0 +#define FEC_RS_COMM_INT_STA__A 0x2430005 +#define FEC_RS_COMM_INT_STA__W 2 +#define FEC_RS_COMM_INT_STA__M 0x3 +#define FEC_RS_COMM_INT_STA__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_MSK__A 0x2430006 +#define FEC_RS_COMM_INT_MSK__W 2 +#define FEC_RS_COMM_INT_MSK__M 0x3 +#define FEC_RS_COMM_INT_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_COMM_INT_STM__A 0x2430007 +#define FEC_RS_COMM_INT_STM__W 2 +#define FEC_RS_COMM_INT_STM__M 0x3 +#define FEC_RS_COMM_INT_STM__PRE 0x0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_STATUS__A 0x2430010 +#define FEC_RS_STATUS__W 1 +#define FEC_RS_STATUS__M 0x1 +#define FEC_RS_STATUS__PRE 0x0 +#define FEC_RS_MODE__A 0x2430011 +#define FEC_RS_MODE__W 1 +#define FEC_RS_MODE__M 0x1 +#define FEC_RS_MODE__PRE 0x0 + +#define FEC_RS_MODE_BYPASS__B 0 +#define FEC_RS_MODE_BYPASS__W 1 +#define FEC_RS_MODE_BYPASS__M 0x1 +#define FEC_RS_MODE_BYPASS__PRE 0x0 + +#define FEC_RS_MEASUREMENT_PERIOD__A 0x2430012 +#define FEC_RS_MEASUREMENT_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x1171 + +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x1171 + +#define FEC_RS_MEASUREMENT_PRESCALE__A 0x2430013 +#define FEC_RS_MEASUREMENT_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x1 + +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x1 + +#define FEC_RS_NR_BIT_ERRORS__A 0x2430014 +#define FEC_RS_NR_BIT_ERRORS__W 16 +#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF +#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_BIT_ERRORS_EXP__B 12 +#define FEC_RS_NR_BIT_ERRORS_EXP__W 4 +#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_SYMBOL_ERRORS__A 0x2430015 +#define FEC_RS_NR_SYMBOL_ERRORS__W 16 +#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF +#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_PACKET_ERRORS__A 0x2430016 +#define FEC_RS_NR_PACKET_ERRORS__W 16 +#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF +#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12 +#define FEC_RS_NR_PACKET_ERRORS_EXP__W 4 +#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_FAILURES__A 0x2430017 +#define FEC_RS_NR_FAILURES__W 16 +#define FEC_RS_NR_FAILURES__M 0xFFFF +#define FEC_RS_NR_FAILURES__PRE 0x0 + +#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0 +#define FEC_RS_NR_FAILURES_FIXED_MANT__W 12 +#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x0 + +#define FEC_RS_NR_FAILURES_EXP__B 12 +#define FEC_RS_NR_FAILURES_EXP__W 4 +#define FEC_RS_NR_FAILURES_EXP__M 0xF000 +#define FEC_RS_NR_FAILURES_EXP__PRE 0x0 + +#define FEC_OC_COMM_EXEC__A 0x2440000 +#define FEC_OC_COMM_EXEC__W 2 +#define FEC_OC_COMM_EXEC__M 0x3 +#define FEC_OC_COMM_EXEC__PRE 0x0 +#define FEC_OC_COMM_EXEC_STOP 0x0 +#define FEC_OC_COMM_EXEC_ACTIVE 0x1 +#define FEC_OC_COMM_EXEC_HOLD 0x2 + +#define FEC_OC_COMM_MB__A 0x2440002 +#define FEC_OC_COMM_MB__W 2 +#define FEC_OC_COMM_MB__M 0x3 +#define FEC_OC_COMM_MB__PRE 0x0 +#define FEC_OC_COMM_MB_CTL__B 0 +#define FEC_OC_COMM_MB_CTL__W 1 +#define FEC_OC_COMM_MB_CTL__M 0x1 +#define FEC_OC_COMM_MB_CTL__PRE 0x0 +#define FEC_OC_COMM_MB_CTL_OFF 0x0 +#define FEC_OC_COMM_MB_CTL_ON 0x1 +#define FEC_OC_COMM_MB_OBS__B 1 +#define FEC_OC_COMM_MB_OBS__W 1 +#define FEC_OC_COMM_MB_OBS__M 0x2 +#define FEC_OC_COMM_MB_OBS__PRE 0x0 +#define FEC_OC_COMM_MB_OBS_OFF 0x0 +#define FEC_OC_COMM_MB_OBS_ON 0x2 + +#define FEC_OC_COMM_INT_REQ__A 0x2440003 +#define FEC_OC_COMM_INT_REQ__W 1 +#define FEC_OC_COMM_INT_REQ__M 0x1 +#define FEC_OC_COMM_INT_REQ__PRE 0x0 +#define FEC_OC_COMM_INT_STA__A 0x2440005 +#define FEC_OC_COMM_INT_STA__W 8 +#define FEC_OC_COMM_INT_STA__M 0xFF +#define FEC_OC_COMM_INT_STA__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x4 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x8 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x10 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x20 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x40 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x80 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_MSK__A 0x2440006 +#define FEC_OC_COMM_INT_MSK__W 8 +#define FEC_OC_COMM_INT_MSK__M 0xFF +#define FEC_OC_COMM_INT_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_COMM_INT_STM__A 0x2440007 +#define FEC_OC_COMM_INT_STM__W 8 +#define FEC_OC_COMM_INT_STM__M 0xFF +#define FEC_OC_COMM_INT_STM__PRE 0x0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_STATUS__A 0x2440010 +#define FEC_OC_STATUS__W 5 +#define FEC_OC_STATUS__M 0x1F +#define FEC_OC_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_DPR_STATUS__B 0 +#define FEC_OC_STATUS_DPR_STATUS__W 1 +#define FEC_OC_STATUS_DPR_STATUS__M 0x1 +#define FEC_OC_STATUS_DPR_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_SNC_STATUS__B 1 +#define FEC_OC_STATUS_SNC_STATUS__W 2 +#define FEC_OC_STATUS_SNC_STATUS__M 0x6 +#define FEC_OC_STATUS_SNC_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_FIFO_FULL__B 3 +#define FEC_OC_STATUS_FIFO_FULL__W 1 +#define FEC_OC_STATUS_FIFO_FULL__M 0x8 +#define FEC_OC_STATUS_FIFO_FULL__PRE 0x0 + +#define FEC_OC_STATUS_FIFO_EMPTY__B 4 +#define FEC_OC_STATUS_FIFO_EMPTY__W 1 +#define FEC_OC_STATUS_FIFO_EMPTY__M 0x10 +#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x0 + +#define FEC_OC_MODE__A 0x2440011 +#define FEC_OC_MODE__W 4 +#define FEC_OC_MODE__M 0xF +#define FEC_OC_MODE__PRE 0x0 + +#define FEC_OC_MODE_PARITY__B 0 +#define FEC_OC_MODE_PARITY__W 1 +#define FEC_OC_MODE_PARITY__M 0x1 +#define FEC_OC_MODE_PARITY__PRE 0x0 + +#define FEC_OC_MODE_TRANSPARENT__B 1 +#define FEC_OC_MODE_TRANSPARENT__W 1 +#define FEC_OC_MODE_TRANSPARENT__M 0x2 +#define FEC_OC_MODE_TRANSPARENT__PRE 0x0 + +#define FEC_OC_MODE_CLEAR__B 2 +#define FEC_OC_MODE_CLEAR__W 1 +#define FEC_OC_MODE_CLEAR__M 0x4 +#define FEC_OC_MODE_CLEAR__PRE 0x0 + +#define FEC_OC_MODE_RETAIN_FRAMING__B 3 +#define FEC_OC_MODE_RETAIN_FRAMING__W 1 +#define FEC_OC_MODE_RETAIN_FRAMING__M 0x8 +#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x0 + +#define FEC_OC_DPR_MODE__A 0x2440012 +#define FEC_OC_DPR_MODE__W 2 +#define FEC_OC_DPR_MODE__M 0x3 +#define FEC_OC_DPR_MODE__PRE 0x0 + +#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0 +#define FEC_OC_DPR_MODE_ERR_DISABLE__W 1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x0 + +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0 + +#define FEC_OC_DPR_UNLOCK__A 0x2440013 +#define FEC_OC_DPR_UNLOCK__W 1 +#define FEC_OC_DPR_UNLOCK__M 0x1 +#define FEC_OC_DPR_UNLOCK__PRE 0x0 +#define FEC_OC_DTO_MODE__A 0x2440014 +#define FEC_OC_DTO_MODE__W 3 +#define FEC_OC_DTO_MODE__M 0x7 +#define FEC_OC_DTO_MODE__PRE 0x0 + +#define FEC_OC_DTO_MODE_DYNAMIC__B 0 +#define FEC_OC_DTO_MODE_DYNAMIC__W 1 +#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 +#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x0 + +#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x0 + +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0 + +#define FEC_OC_DTO_PERIOD__A 0x2440015 +#define FEC_OC_DTO_PERIOD__W 8 +#define FEC_OC_DTO_PERIOD__M 0xFF +#define FEC_OC_DTO_PERIOD__PRE 0x0 +#define FEC_OC_DTO_RATE_LO__A 0x2440016 +#define FEC_OC_DTO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0 +#define FEC_OC_DTO_RATE_LO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_HI__A 0x2440017 +#define FEC_OC_DTO_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0 +#define FEC_OC_DTO_RATE_HI_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_BURST_LEN__A 0x2440018 +#define FEC_OC_DTO_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN__PRE 0xBC + +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC + +#define FEC_OC_FCT_MODE__A 0x244001A +#define FEC_OC_FCT_MODE__W 2 +#define FEC_OC_FCT_MODE__M 0x3 +#define FEC_OC_FCT_MODE__PRE 0x0 + +#define FEC_OC_FCT_MODE_RAT_ENA__B 0 +#define FEC_OC_FCT_MODE_RAT_ENA__W 1 +#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 +#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x0 + +#define FEC_OC_FCT_MODE_VIRT_ENA__B 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__W 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 +#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x0 + +#define FEC_OC_FCT_USAGE__A 0x244001B +#define FEC_OC_FCT_USAGE__W 3 +#define FEC_OC_FCT_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE__PRE 0x2 + +#define FEC_OC_FCT_USAGE_USAGE__B 0 +#define FEC_OC_FCT_USAGE_USAGE__W 3 +#define FEC_OC_FCT_USAGE_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE_USAGE__PRE 0x2 + +#define FEC_OC_FCT_OCCUPATION__A 0x244001C +#define FEC_OC_FCT_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION__PRE 0x0 + +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x0 + +#define FEC_OC_TMD_MODE__A 0x244001E +#define FEC_OC_TMD_MODE__W 3 +#define FEC_OC_TMD_MODE__M 0x7 +#define FEC_OC_TMD_MODE__PRE 0x4 + +#define FEC_OC_TMD_MODE_MODE__B 0 +#define FEC_OC_TMD_MODE_MODE__W 3 +#define FEC_OC_TMD_MODE_MODE__M 0x7 +#define FEC_OC_TMD_MODE_MODE__PRE 0x4 + +#define FEC_OC_TMD_COUNT__A 0x244001F +#define FEC_OC_TMD_COUNT__W 10 +#define FEC_OC_TMD_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_COUNT_COUNT__B 0 +#define FEC_OC_TMD_COUNT_COUNT__W 10 +#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_HI_MARGIN__A 0x2440020 +#define FEC_OC_TMD_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN__PRE 0x200 + +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x200 + +#define FEC_OC_TMD_LO_MARGIN__A 0x2440021 +#define FEC_OC_TMD_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN__PRE 0x100 + +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x100 + +#define FEC_OC_TMD_CTL_UPD_RATE__A 0x2440022 +#define FEC_OC_TMD_CTL_UPD_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x1 + +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x1 + +#define FEC_OC_TMD_INT_UPD_RATE__A 0x2440023 +#define FEC_OC_TMD_INT_UPD_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x4 + +#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x4 + +#define FEC_OC_AVR_PARM_A__A 0x2440026 +#define FEC_OC_AVR_PARM_A__W 4 +#define FEC_OC_AVR_PARM_A__M 0xF +#define FEC_OC_AVR_PARM_A__PRE 0x6 + +#define FEC_OC_AVR_PARM_A_PARM__B 0 +#define FEC_OC_AVR_PARM_A_PARM__W 4 +#define FEC_OC_AVR_PARM_A_PARM__M 0xF +#define FEC_OC_AVR_PARM_A_PARM__PRE 0x6 + +#define FEC_OC_AVR_PARM_B__A 0x2440027 +#define FEC_OC_AVR_PARM_B__W 4 +#define FEC_OC_AVR_PARM_B__M 0xF +#define FEC_OC_AVR_PARM_B__PRE 0x4 + +#define FEC_OC_AVR_PARM_B_PARM__B 0 +#define FEC_OC_AVR_PARM_B_PARM__W 4 +#define FEC_OC_AVR_PARM_B_PARM__M 0xF +#define FEC_OC_AVR_PARM_B_PARM__PRE 0x4 + +#define FEC_OC_AVR_AVG_LO__A 0x2440028 +#define FEC_OC_AVR_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0 +#define FEC_OC_AVR_AVG_LO_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI__A 0x2440029 +#define FEC_OC_AVR_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0 +#define FEC_OC_AVR_AVG_HI_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x0 + +#define FEC_OC_RCN_MODE__A 0x244002C +#define FEC_OC_RCN_MODE__W 5 +#define FEC_OC_RCN_MODE__M 0x1F +#define FEC_OC_RCN_MODE__PRE 0x1F + +#define FEC_OC_RCN_MODE_MODE__B 0 +#define FEC_OC_RCN_MODE_MODE__W 5 +#define FEC_OC_RCN_MODE_MODE__M 0x1F +#define FEC_OC_RCN_MODE_MODE__PRE 0x1F + +#define FEC_OC_RCN_OCC_SETTLE__A 0x244002D +#define FEC_OC_RCN_OCC_SETTLE__W 11 +#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE__PRE 0x180 + +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x180 + +#define FEC_OC_RCN_GAIN__A 0x244002E +#define FEC_OC_RCN_GAIN__W 4 +#define FEC_OC_RCN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN__PRE 0xC + +#define FEC_OC_RCN_GAIN_GAIN__B 0 +#define FEC_OC_RCN_GAIN_GAIN__W 4 +#define FEC_OC_RCN_GAIN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC + +#define FEC_OC_RCN_CTL_RATE_LO__A 0x2440030 +#define FEC_OC_RCN_CTL_RATE_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_HI__A 0x2440031 +#define FEC_OC_RCN_CTL_RATE_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_STEP_LO__A 0x2440032 +#define FEC_OC_RCN_CTL_STEP_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_HI__A 0x2440033 +#define FEC_OC_RCN_CTL_STEP_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x8 + +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x8 + +#define FEC_OC_RCN_DTO_OFS_LO__A 0x2440034 +#define FEC_OC_RCN_DTO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI__A 0x2440035 +#define FEC_OC_RCN_DTO_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO__A 0x2440036 +#define FEC_OC_RCN_DTO_RATE_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI__A 0x2440037 +#define FEC_OC_RCN_DTO_RATE_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO__A 0x2440038 +#define FEC_OC_RCN_RATE_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_HI__A 0x2440039 +#define FEC_OC_RCN_RATE_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_DYN_RATE_LO__A 0x244003A +#define FEC_OC_RCN_DYN_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI__A 0x244003B +#define FEC_OC_RCN_DYN_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x0 + +#define FEC_OC_SNC_MODE__A 0x2440040 +#define FEC_OC_SNC_MODE__W 4 +#define FEC_OC_SNC_MODE__M 0xF +#define FEC_OC_SNC_MODE__PRE 0x0 + +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x0 + +#define FEC_OC_SNC_MODE_ERROR_CTL__B 1 +#define FEC_OC_SNC_MODE_ERROR_CTL__W 2 +#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x6 +#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x0 + +#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3 +#define FEC_OC_SNC_MODE_CORR_DISABLE__W 1 +#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x8 +#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x0 + +#define FEC_OC_SNC_LWM__A 0x2440041 +#define FEC_OC_SNC_LWM__W 4 +#define FEC_OC_SNC_LWM__M 0xF +#define FEC_OC_SNC_LWM__PRE 0x3 + +#define FEC_OC_SNC_LWM_MARK__B 0 +#define FEC_OC_SNC_LWM_MARK__W 4 +#define FEC_OC_SNC_LWM_MARK__M 0xF +#define FEC_OC_SNC_LWM_MARK__PRE 0x3 + +#define FEC_OC_SNC_HWM__A 0x2440042 +#define FEC_OC_SNC_HWM__W 4 +#define FEC_OC_SNC_HWM__M 0xF +#define FEC_OC_SNC_HWM__PRE 0x5 + +#define FEC_OC_SNC_HWM_MARK__B 0 +#define FEC_OC_SNC_HWM_MARK__W 4 +#define FEC_OC_SNC_HWM_MARK__M 0xF +#define FEC_OC_SNC_HWM_MARK__PRE 0x5 + +#define FEC_OC_SNC_UNLOCK__A 0x2440043 +#define FEC_OC_SNC_UNLOCK__W 1 +#define FEC_OC_SNC_UNLOCK__M 0x1 +#define FEC_OC_SNC_UNLOCK__PRE 0x0 + +#define FEC_OC_SNC_UNLOCK_RESTART__B 0 +#define FEC_OC_SNC_UNLOCK_RESTART__W 1 +#define FEC_OC_SNC_UNLOCK_RESTART__M 0x1 +#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT__A 0x2440044 +#define FEC_OC_SNC_LOCK_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT__A 0x2440045 +#define FEC_OC_SNC_FAIL_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_PERIOD__A 0x2440046 +#define FEC_OC_SNC_FAIL_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x1171 + +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x1171 + +#define FEC_OC_EMS_MODE__A 0x2440047 +#define FEC_OC_EMS_MODE__W 2 +#define FEC_OC_EMS_MODE__M 0x3 +#define FEC_OC_EMS_MODE__PRE 0x0 + +#define FEC_OC_EMS_MODE_MODE__B 0 +#define FEC_OC_EMS_MODE_MODE__W 2 +#define FEC_OC_EMS_MODE_MODE__M 0x3 +#define FEC_OC_EMS_MODE_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE__A 0x2440048 +#define FEC_OC_IPR_MODE__W 12 +#define FEC_OC_IPR_MODE__M 0xFFF +#define FEC_OC_IPR_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE_SERIAL__B 0 +#define FEC_OC_IPR_MODE_SERIAL__W 1 +#define FEC_OC_IPR_MODE_SERIAL__M 0x1 +#define FEC_OC_IPR_MODE_SERIAL__PRE 0x0 + +#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x8 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x20 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x40 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x80 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x100 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x200 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x400 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x800 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT__A 0x2440049 +#define FEC_OC_IPR_INVERT__W 12 +#define FEC_OC_IPR_INVERT__M 0xFFF +#define FEC_OC_IPR_INVERT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD0__B 0 +#define FEC_OC_IPR_INVERT_MD0__W 1 +#define FEC_OC_IPR_INVERT_MD0__M 0x1 +#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD1__B 1 +#define FEC_OC_IPR_INVERT_MD1__W 1 +#define FEC_OC_IPR_INVERT_MD1__M 0x2 +#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD2__B 2 +#define FEC_OC_IPR_INVERT_MD2__W 1 +#define FEC_OC_IPR_INVERT_MD2__M 0x4 +#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD3__B 3 +#define FEC_OC_IPR_INVERT_MD3__W 1 +#define FEC_OC_IPR_INVERT_MD3__M 0x8 +#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD4__B 4 +#define FEC_OC_IPR_INVERT_MD4__W 1 +#define FEC_OC_IPR_INVERT_MD4__M 0x10 +#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD5__B 5 +#define FEC_OC_IPR_INVERT_MD5__W 1 +#define FEC_OC_IPR_INVERT_MD5__M 0x20 +#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD6__B 6 +#define FEC_OC_IPR_INVERT_MD6__W 1 +#define FEC_OC_IPR_INVERT_MD6__M 0x40 +#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD7__B 7 +#define FEC_OC_IPR_INVERT_MD7__W 1 +#define FEC_OC_IPR_INVERT_MD7__M 0x80 +#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MERR__B 8 +#define FEC_OC_IPR_INVERT_MERR__W 1 +#define FEC_OC_IPR_INVERT_MERR__M 0x100 +#define FEC_OC_IPR_INVERT_MERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MSTRT__B 9 +#define FEC_OC_IPR_INVERT_MSTRT__W 1 +#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 +#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MVAL__B 10 +#define FEC_OC_IPR_INVERT_MVAL__W 1 +#define FEC_OC_IPR_INVERT_MVAL__M 0x400 +#define FEC_OC_IPR_INVERT_MVAL__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MCLK__B 11 +#define FEC_OC_IPR_INVERT_MCLK__W 1 +#define FEC_OC_IPR_INVERT_MCLK__M 0x800 +#define FEC_OC_IPR_INVERT_MCLK__PRE 0x0 + +#define FEC_OC_OCR_MODE__A 0x2440050 +#define FEC_OC_OCR_MODE__W 4 +#define FEC_OC_OCR_MODE__M 0xF +#define FEC_OC_OCR_MODE__PRE 0x0 + +#define FEC_OC_OCR_MODE_MB_SELECT__B 0 +#define FEC_OC_OCR_MODE_MB_SELECT__W 1 +#define FEC_OC_OCR_MODE_MB_SELECT__M 0x1 +#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2 +#define FEC_OC_OCR_MODE_GRAB_SELECT__W 1 +#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x4 +#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x8 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x0 + +#define FEC_OC_OCR_RATE__A 0x2440051 +#define FEC_OC_OCR_RATE__W 4 +#define FEC_OC_OCR_RATE__M 0xF +#define FEC_OC_OCR_RATE__PRE 0x0 + +#define FEC_OC_OCR_RATE_RATE__B 0 +#define FEC_OC_OCR_RATE_RATE__W 4 +#define FEC_OC_OCR_RATE_RATE__M 0xF +#define FEC_OC_OCR_RATE_RATE__PRE 0x0 + +#define FEC_OC_OCR_INVERT__A 0x2440052 +#define FEC_OC_OCR_INVERT__W 12 +#define FEC_OC_OCR_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT__PRE 0x800 + +#define FEC_OC_OCR_INVERT_INVERT__B 0 +#define FEC_OC_OCR_INVERT_INVERT__W 12 +#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT_INVERT__PRE 0x800 + +#define FEC_OC_OCR_GRAB_COUNT__A 0x2440053 +#define FEC_OC_OCR_GRAB_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC__A 0x2440054 +#define FEC_OC_OCR_GRAB_SYNC__W 8 +#define FEC_OC_OCR_GRAB_SYNC__M 0xFF +#define FEC_OC_OCR_GRAB_SYNC__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x7 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x78 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x80 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0__A 0x2440055 +#define FEC_OC_OCR_GRAB_RD0__W 10 +#define FEC_OC_OCR_GRAB_RD0__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD0_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1__A 0x2440056 +#define FEC_OC_OCR_GRAB_RD1__W 10 +#define FEC_OC_OCR_GRAB_RD1__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD1_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2__A 0x2440057 +#define FEC_OC_OCR_GRAB_RD2__W 10 +#define FEC_OC_OCR_GRAB_RD2__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD2_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3__A 0x2440058 +#define FEC_OC_OCR_GRAB_RD3__W 10 +#define FEC_OC_OCR_GRAB_RD3__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD3_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4__A 0x2440059 +#define FEC_OC_OCR_GRAB_RD4__W 10 +#define FEC_OC_OCR_GRAB_RD4__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD4_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5__A 0x244005A +#define FEC_OC_OCR_GRAB_RD5__W 10 +#define FEC_OC_OCR_GRAB_RD5__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD5_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0 + +#define FEC_DI_RAM__A 0x2450000 + +#define FEC_RS_RAM__A 0x2460000 + +#define FEC_OC_RAM__A 0x2470000 + +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_COMM_EXEC__W 2 +#define IQM_COMM_EXEC__M 0x3 +#define IQM_COMM_EXEC__PRE 0x0 +#define IQM_COMM_EXEC_STOP 0x0 +#define IQM_COMM_EXEC_ACTIVE 0x1 +#define IQM_COMM_EXEC_HOLD 0x2 + +#define IQM_COMM_MB__A 0x1800002 +#define IQM_COMM_MB__W 16 +#define IQM_COMM_MB__M 0xFFFF +#define IQM_COMM_MB__PRE 0x0 +#define IQM_COMM_INT_REQ__A 0x1800003 +#define IQM_COMM_INT_REQ__W 2 +#define IQM_COMM_INT_REQ__M 0x3 +#define IQM_COMM_INT_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_AF_REQ__B 0 +#define IQM_COMM_INT_REQ_AF_REQ__W 1 +#define IQM_COMM_INT_REQ_AF_REQ__M 0x1 +#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_CF_REQ__B 1 +#define IQM_COMM_INT_REQ_CF_REQ__W 1 +#define IQM_COMM_INT_REQ_CF_REQ__M 0x2 +#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x0 + +#define IQM_COMM_INT_STA__A 0x1800005 +#define IQM_COMM_INT_STA__W 16 +#define IQM_COMM_INT_STA__M 0xFFFF +#define IQM_COMM_INT_STA__PRE 0x0 +#define IQM_COMM_INT_MSK__A 0x1800006 +#define IQM_COMM_INT_MSK__W 16 +#define IQM_COMM_INT_MSK__M 0xFFFF +#define IQM_COMM_INT_MSK__PRE 0x0 +#define IQM_COMM_INT_STM__A 0x1800007 +#define IQM_COMM_INT_STM__W 16 +#define IQM_COMM_INT_STM__M 0xFFFF +#define IQM_COMM_INT_STM__PRE 0x0 + +#define IQM_FS_COMM_EXEC__A 0x1820000 +#define IQM_FS_COMM_EXEC__W 2 +#define IQM_FS_COMM_EXEC__M 0x3 +#define IQM_FS_COMM_EXEC__PRE 0x0 +#define IQM_FS_COMM_EXEC_STOP 0x0 +#define IQM_FS_COMM_EXEC_ACTIVE 0x1 +#define IQM_FS_COMM_EXEC_HOLD 0x2 + +#define IQM_FS_COMM_MB__A 0x1820002 +#define IQM_FS_COMM_MB__W 2 +#define IQM_FS_COMM_MB__M 0x3 +#define IQM_FS_COMM_MB__PRE 0x0 +#define IQM_FS_COMM_MB_CTL__B 0 +#define IQM_FS_COMM_MB_CTL__W 1 +#define IQM_FS_COMM_MB_CTL__M 0x1 +#define IQM_FS_COMM_MB_CTL__PRE 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FS_COMM_MB_OBS__B 1 +#define IQM_FS_COMM_MB_OBS__W 1 +#define IQM_FS_COMM_MB_OBS__M 0x2 +#define IQM_FS_COMM_MB_OBS__PRE 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_FS_RATE_OFS_LO__A 0x1820010 +#define IQM_FS_RATE_OFS_LO__W 16 +#define IQM_FS_RATE_OFS_LO__M 0xFFFF +#define IQM_FS_RATE_OFS_LO__PRE 0x0 +#define IQM_FS_RATE_OFS_HI__A 0x1820011 +#define IQM_FS_RATE_OFS_HI__W 12 +#define IQM_FS_RATE_OFS_HI__M 0xFFF +#define IQM_FS_RATE_OFS_HI__PRE 0x0 +#define IQM_FS_RATE_LO__A 0x1820012 +#define IQM_FS_RATE_LO__W 16 +#define IQM_FS_RATE_LO__M 0xFFFF +#define IQM_FS_RATE_LO__PRE 0x0 +#define IQM_FS_RATE_HI__A 0x1820013 +#define IQM_FS_RATE_HI__W 12 +#define IQM_FS_RATE_HI__M 0xFFF +#define IQM_FS_RATE_HI__PRE 0x0 + +#define IQM_FS_ADJ_SEL__A 0x1820014 +#define IQM_FS_ADJ_SEL__W 2 +#define IQM_FS_ADJ_SEL__M 0x3 +#define IQM_FS_ADJ_SEL__PRE 0x0 +#define IQM_FS_ADJ_SEL_OFF 0x0 +#define IQM_FS_ADJ_SEL_QAM 0x1 +#define IQM_FS_ADJ_SEL_VSB 0x2 + +#define IQM_FD_COMM_EXEC__A 0x1830000 +#define IQM_FD_COMM_EXEC__W 2 +#define IQM_FD_COMM_EXEC__M 0x3 +#define IQM_FD_COMM_EXEC__PRE 0x0 +#define IQM_FD_COMM_EXEC_STOP 0x0 +#define IQM_FD_COMM_EXEC_ACTIVE 0x1 +#define IQM_FD_COMM_EXEC_HOLD 0x2 + +#define IQM_FD_COMM_MB__A 0x1830002 +#define IQM_FD_COMM_MB__W 2 +#define IQM_FD_COMM_MB__M 0x3 +#define IQM_FD_COMM_MB__PRE 0x0 +#define IQM_FD_COMM_MB_CTL__B 0 +#define IQM_FD_COMM_MB_CTL__W 1 +#define IQM_FD_COMM_MB_CTL__M 0x1 +#define IQM_FD_COMM_MB_CTL__PRE 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FD_COMM_MB_OBS__B 1 +#define IQM_FD_COMM_MB_OBS__W 1 +#define IQM_FD_COMM_MB_OBS__M 0x2 +#define IQM_FD_COMM_MB_OBS__PRE 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RC_COMM_EXEC__A 0x1840000 +#define IQM_RC_COMM_EXEC__W 2 +#define IQM_RC_COMM_EXEC__M 0x3 +#define IQM_RC_COMM_EXEC__PRE 0x0 +#define IQM_RC_COMM_EXEC_STOP 0x0 +#define IQM_RC_COMM_EXEC_ACTIVE 0x1 +#define IQM_RC_COMM_EXEC_HOLD 0x2 + +#define IQM_RC_COMM_MB__A 0x1840002 +#define IQM_RC_COMM_MB__W 2 +#define IQM_RC_COMM_MB__M 0x3 +#define IQM_RC_COMM_MB__PRE 0x0 +#define IQM_RC_COMM_MB_CTL__B 0 +#define IQM_RC_COMM_MB_CTL__W 1 +#define IQM_RC_COMM_MB_CTL__M 0x1 +#define IQM_RC_COMM_MB_CTL__PRE 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RC_COMM_MB_OBS__B 1 +#define IQM_RC_COMM_MB_OBS__W 1 +#define IQM_RC_COMM_MB_OBS__M 0x2 +#define IQM_RC_COMM_MB_OBS__PRE 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RC_RATE_OFS_LO__A 0x1840010 +#define IQM_RC_RATE_OFS_LO__W 16 +#define IQM_RC_RATE_OFS_LO__M 0xFFFF +#define IQM_RC_RATE_OFS_LO__PRE 0x0 +#define IQM_RC_RATE_OFS_HI__A 0x1840011 +#define IQM_RC_RATE_OFS_HI__W 8 +#define IQM_RC_RATE_OFS_HI__M 0xFF +#define IQM_RC_RATE_OFS_HI__PRE 0x0 +#define IQM_RC_RATE_LO__A 0x1840012 +#define IQM_RC_RATE_LO__W 16 +#define IQM_RC_RATE_LO__M 0xFFFF +#define IQM_RC_RATE_LO__PRE 0x0 +#define IQM_RC_RATE_HI__A 0x1840013 +#define IQM_RC_RATE_HI__W 8 +#define IQM_RC_RATE_HI__M 0xFF +#define IQM_RC_RATE_HI__PRE 0x0 + +#define IQM_RC_ADJ_SEL__A 0x1840014 +#define IQM_RC_ADJ_SEL__W 2 +#define IQM_RC_ADJ_SEL__M 0x3 +#define IQM_RC_ADJ_SEL__PRE 0x0 +#define IQM_RC_ADJ_SEL_OFF 0x0 +#define IQM_RC_ADJ_SEL_QAM 0x1 +#define IQM_RC_ADJ_SEL_VSB 0x2 + +#define IQM_RC_CROUT_ENA__A 0x1840015 +#define IQM_RC_CROUT_ENA__W 1 +#define IQM_RC_CROUT_ENA__M 0x1 +#define IQM_RC_CROUT_ENA__PRE 0x0 + +#define IQM_RC_CROUT_ENA_ENA__B 0 +#define IQM_RC_CROUT_ENA_ENA__W 1 +#define IQM_RC_CROUT_ENA_ENA__M 0x1 +#define IQM_RC_CROUT_ENA_ENA__PRE 0x0 + +#define IQM_RC_STRETCH__A 0x1840016 +#define IQM_RC_STRETCH__W 5 +#define IQM_RC_STRETCH__M 0x1F +#define IQM_RC_STRETCH__PRE 0x0 +#define IQM_RC_STRETCH_QAM_B_64 0x1E +#define IQM_RC_STRETCH_QAM_B_256 0x1C +#define IQM_RC_STRETCH_ATV 0xF + +#define IQM_RT_COMM_EXEC__A 0x1850000 +#define IQM_RT_COMM_EXEC__W 2 +#define IQM_RT_COMM_EXEC__M 0x3 +#define IQM_RT_COMM_EXEC__PRE 0x0 +#define IQM_RT_COMM_EXEC_STOP 0x0 +#define IQM_RT_COMM_EXEC_ACTIVE 0x1 +#define IQM_RT_COMM_EXEC_HOLD 0x2 + +#define IQM_RT_COMM_MB__A 0x1850002 +#define IQM_RT_COMM_MB__W 2 +#define IQM_RT_COMM_MB__M 0x3 +#define IQM_RT_COMM_MB__PRE 0x0 +#define IQM_RT_COMM_MB_CTL__B 0 +#define IQM_RT_COMM_MB_CTL__W 1 +#define IQM_RT_COMM_MB_CTL__M 0x1 +#define IQM_RT_COMM_MB_CTL__PRE 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RT_COMM_MB_OBS__B 1 +#define IQM_RT_COMM_MB_OBS__W 1 +#define IQM_RT_COMM_MB_OBS__M 0x2 +#define IQM_RT_COMM_MB_OBS__PRE 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RT_ACTIVE__A 0x1850010 +#define IQM_RT_ACTIVE__W 2 +#define IQM_RT_ACTIVE__M 0x3 +#define IQM_RT_ACTIVE__PRE 0x0 + +#define IQM_RT_ACTIVE_ACTIVE_RT__B 0 +#define IQM_RT_ACTIVE_ACTIVE_RT__W 1 +#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x1 +#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x1 + +#define IQM_RT_ACTIVE_ACTIVE_CR__B 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__W 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2 +#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2 + +#define IQM_RT_LO_INCR__A 0x1850011 +#define IQM_RT_LO_INCR__W 12 +#define IQM_RT_LO_INCR__M 0xFFF +#define IQM_RT_LO_INCR__PRE 0x588 +#define IQM_RT_LO_INCR_FM 0x0 +#define IQM_RT_LO_INCR_MN 0x588 + +#define IQM_RT_ROT_BP__A 0x1850012 +#define IQM_RT_ROT_BP__W 2 +#define IQM_RT_ROT_BP__M 0x3 +#define IQM_RT_ROT_BP__PRE 0x0 + +#define IQM_RT_ROT_BP_ROT_OFF__B 0 +#define IQM_RT_ROT_BP_ROT_OFF__W 1 +#define IQM_RT_ROT_BP_ROT_OFF__M 0x1 +#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x1 + +#define IQM_RT_ROT_BP_ROT_BPF__B 1 +#define IQM_RT_ROT_BP_ROT_BPF__W 1 +#define IQM_RT_ROT_BP_ROT_BPF__M 0x2 +#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0 + +#define IQM_RT_LP_BP__A 0x1850013 +#define IQM_RT_LP_BP__W 1 +#define IQM_RT_LP_BP__M 0x1 +#define IQM_RT_LP_BP__PRE 0x0 + +#define IQM_RT_DELAY__A 0x1850014 +#define IQM_RT_DELAY__W 7 +#define IQM_RT_DELAY__M 0x7F +#define IQM_RT_DELAY__PRE 0x45 + +#define IQM_CF_COMM_EXEC__A 0x1860000 +#define IQM_CF_COMM_EXEC__W 2 +#define IQM_CF_COMM_EXEC__M 0x3 +#define IQM_CF_COMM_EXEC__PRE 0x0 +#define IQM_CF_COMM_EXEC_STOP 0x0 +#define IQM_CF_COMM_EXEC_ACTIVE 0x1 +#define IQM_CF_COMM_EXEC_HOLD 0x2 + +#define IQM_CF_COMM_MB__A 0x1860002 +#define IQM_CF_COMM_MB__W 2 +#define IQM_CF_COMM_MB__M 0x3 +#define IQM_CF_COMM_MB__PRE 0x0 +#define IQM_CF_COMM_MB_CTL__B 0 +#define IQM_CF_COMM_MB_CTL__W 1 +#define IQM_CF_COMM_MB_CTL__M 0x1 +#define IQM_CF_COMM_MB_CTL__PRE 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_CF_COMM_MB_OBS__B 1 +#define IQM_CF_COMM_MB_OBS__W 1 +#define IQM_CF_COMM_MB_OBS__M 0x2 +#define IQM_CF_COMM_MB_OBS__PRE 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_CF_COMM_INT_REQ__A 0x1860003 +#define IQM_CF_COMM_INT_REQ__W 1 +#define IQM_CF_COMM_INT_REQ__M 0x1 +#define IQM_CF_COMM_INT_REQ__PRE 0x0 +#define IQM_CF_COMM_INT_STA__A 0x1860005 +#define IQM_CF_COMM_INT_STA__W 1 +#define IQM_CF_COMM_INT_STA__M 0x1 +#define IQM_CF_COMM_INT_STA__PRE 0x0 +#define IQM_CF_COMM_INT_STA_PM__B 0 +#define IQM_CF_COMM_INT_STA_PM__W 1 +#define IQM_CF_COMM_INT_STA_PM__M 0x1 +#define IQM_CF_COMM_INT_STA_PM__PRE 0x0 + +#define IQM_CF_COMM_INT_MSK__A 0x1860006 +#define IQM_CF_COMM_INT_MSK__W 1 +#define IQM_CF_COMM_INT_MSK__M 0x1 +#define IQM_CF_COMM_INT_MSK__PRE 0x0 +#define IQM_CF_COMM_INT_MSK_PM__B 0 +#define IQM_CF_COMM_INT_MSK_PM__W 1 +#define IQM_CF_COMM_INT_MSK_PM__M 0x1 +#define IQM_CF_COMM_INT_MSK_PM__PRE 0x0 + +#define IQM_CF_COMM_INT_STM__A 0x1860007 +#define IQM_CF_COMM_INT_STM__W 1 +#define IQM_CF_COMM_INT_STM__M 0x1 +#define IQM_CF_COMM_INT_STM__PRE 0x0 +#define IQM_CF_COMM_INT_STM_PM__B 0 +#define IQM_CF_COMM_INT_STM_PM__W 1 +#define IQM_CF_COMM_INT_STM_PM__M 0x1 +#define IQM_CF_COMM_INT_STM_PM__PRE 0x0 + +#define IQM_CF_SYMMETRIC__A 0x1860010 +#define IQM_CF_SYMMETRIC__W 2 +#define IQM_CF_SYMMETRIC__M 0x3 +#define IQM_CF_SYMMETRIC__PRE 0x0 + +#define IQM_CF_SYMMETRIC_RE__B 0 +#define IQM_CF_SYMMETRIC_RE__W 1 +#define IQM_CF_SYMMETRIC_RE__M 0x1 +#define IQM_CF_SYMMETRIC_RE__PRE 0x0 + +#define IQM_CF_SYMMETRIC_IM__B 1 +#define IQM_CF_SYMMETRIC_IM__W 1 +#define IQM_CF_SYMMETRIC_IM__M 0x2 +#define IQM_CF_SYMMETRIC_IM__PRE 0x0 + +#define IQM_CF_MIDTAP__A 0x1860011 +#define IQM_CF_MIDTAP__W 2 +#define IQM_CF_MIDTAP__M 0x3 +#define IQM_CF_MIDTAP__PRE 0x3 + +#define IQM_CF_MIDTAP_RE__B 0 +#define IQM_CF_MIDTAP_RE__W 1 +#define IQM_CF_MIDTAP_RE__M 0x1 +#define IQM_CF_MIDTAP_RE__PRE 0x1 + +#define IQM_CF_MIDTAP_IM__B 1 +#define IQM_CF_MIDTAP_IM__W 1 +#define IQM_CF_MIDTAP_IM__M 0x2 +#define IQM_CF_MIDTAP_IM__PRE 0x2 + +#define IQM_CF_OUT_ENA__A 0x1860012 +#define IQM_CF_OUT_ENA__W 3 +#define IQM_CF_OUT_ENA__M 0x7 +#define IQM_CF_OUT_ENA__PRE 0x0 + +#define IQM_CF_OUT_ENA_ATV__B 0 +#define IQM_CF_OUT_ENA_ATV__W 1 +#define IQM_CF_OUT_ENA_ATV__M 0x1 +#define IQM_CF_OUT_ENA_ATV__PRE 0x0 + +#define IQM_CF_OUT_ENA_QAM__B 1 +#define IQM_CF_OUT_ENA_QAM__W 1 +#define IQM_CF_OUT_ENA_QAM__M 0x2 +#define IQM_CF_OUT_ENA_QAM__PRE 0x0 + +#define IQM_CF_OUT_ENA_VSB__B 2 +#define IQM_CF_OUT_ENA_VSB__W 1 +#define IQM_CF_OUT_ENA_VSB__M 0x4 +#define IQM_CF_OUT_ENA_VSB__PRE 0x0 + +#define IQM_CF_ADJ_SEL__A 0x1860013 +#define IQM_CF_ADJ_SEL__W 2 +#define IQM_CF_ADJ_SEL__M 0x3 +#define IQM_CF_ADJ_SEL__PRE 0x0 +#define IQM_CF_SCALE__A 0x1860014 +#define IQM_CF_SCALE__W 14 +#define IQM_CF_SCALE__M 0x3FFF +#define IQM_CF_SCALE__PRE 0x400 + +#define IQM_CF_SCALE_SH__A 0x1860015 +#define IQM_CF_SCALE_SH__W 2 +#define IQM_CF_SCALE_SH__M 0x3 +#define IQM_CF_SCALE_SH__PRE 0x0 + +#define IQM_CF_AMP__A 0x1860016 +#define IQM_CF_AMP__W 14 +#define IQM_CF_AMP__M 0x3FFF +#define IQM_CF_AMP__PRE 0x0 + +#define IQM_CF_POW_MEAS_LEN__A 0x1860017 +#define IQM_CF_POW_MEAS_LEN__W 3 +#define IQM_CF_POW_MEAS_LEN__M 0x7 +#define IQM_CF_POW_MEAS_LEN__PRE 0x2 +#define IQM_CF_POW_MEAS_LEN_QAM_B_64 0x1 +#define IQM_CF_POW_MEAS_LEN_QAM_B_256 0x1 + +#define IQM_CF_POW__A 0x1860018 +#define IQM_CF_POW__W 16 +#define IQM_CF_POW__M 0xFFFF +#define IQM_CF_POW__PRE 0x2 +#define IQM_CF_TAP_RE0__A 0x1860020 +#define IQM_CF_TAP_RE0__W 7 +#define IQM_CF_TAP_RE0__M 0x7F +#define IQM_CF_TAP_RE0__PRE 0x2 +#define IQM_CF_TAP_RE1__A 0x1860021 +#define IQM_CF_TAP_RE1__W 7 +#define IQM_CF_TAP_RE1__M 0x7F +#define IQM_CF_TAP_RE1__PRE 0x2 +#define IQM_CF_TAP_RE2__A 0x1860022 +#define IQM_CF_TAP_RE2__W 7 +#define IQM_CF_TAP_RE2__M 0x7F +#define IQM_CF_TAP_RE2__PRE 0x2 +#define IQM_CF_TAP_RE3__A 0x1860023 +#define IQM_CF_TAP_RE3__W 7 +#define IQM_CF_TAP_RE3__M 0x7F +#define IQM_CF_TAP_RE3__PRE 0x2 +#define IQM_CF_TAP_RE4__A 0x1860024 +#define IQM_CF_TAP_RE4__W 7 +#define IQM_CF_TAP_RE4__M 0x7F +#define IQM_CF_TAP_RE4__PRE 0x2 +#define IQM_CF_TAP_RE5__A 0x1860025 +#define IQM_CF_TAP_RE5__W 7 +#define IQM_CF_TAP_RE5__M 0x7F +#define IQM_CF_TAP_RE5__PRE 0x2 +#define IQM_CF_TAP_RE6__A 0x1860026 +#define IQM_CF_TAP_RE6__W 7 +#define IQM_CF_TAP_RE6__M 0x7F +#define IQM_CF_TAP_RE6__PRE 0x2 +#define IQM_CF_TAP_RE7__A 0x1860027 +#define IQM_CF_TAP_RE7__W 9 +#define IQM_CF_TAP_RE7__M 0x1FF +#define IQM_CF_TAP_RE7__PRE 0x2 +#define IQM_CF_TAP_RE8__A 0x1860028 +#define IQM_CF_TAP_RE8__W 9 +#define IQM_CF_TAP_RE8__M 0x1FF +#define IQM_CF_TAP_RE8__PRE 0x2 +#define IQM_CF_TAP_RE9__A 0x1860029 +#define IQM_CF_TAP_RE9__W 9 +#define IQM_CF_TAP_RE9__M 0x1FF +#define IQM_CF_TAP_RE9__PRE 0x2 +#define IQM_CF_TAP_RE10__A 0x186002A +#define IQM_CF_TAP_RE10__W 9 +#define IQM_CF_TAP_RE10__M 0x1FF +#define IQM_CF_TAP_RE10__PRE 0x2 +#define IQM_CF_TAP_RE11__A 0x186002B +#define IQM_CF_TAP_RE11__W 9 +#define IQM_CF_TAP_RE11__M 0x1FF +#define IQM_CF_TAP_RE11__PRE 0x2 +#define IQM_CF_TAP_RE12__A 0x186002C +#define IQM_CF_TAP_RE12__W 9 +#define IQM_CF_TAP_RE12__M 0x1FF +#define IQM_CF_TAP_RE12__PRE 0x2 +#define IQM_CF_TAP_RE13__A 0x186002D +#define IQM_CF_TAP_RE13__W 9 +#define IQM_CF_TAP_RE13__M 0x1FF +#define IQM_CF_TAP_RE13__PRE 0x2 +#define IQM_CF_TAP_RE14__A 0x186002E +#define IQM_CF_TAP_RE14__W 9 +#define IQM_CF_TAP_RE14__M 0x1FF +#define IQM_CF_TAP_RE14__PRE 0x2 +#define IQM_CF_TAP_RE15__A 0x186002F +#define IQM_CF_TAP_RE15__W 9 +#define IQM_CF_TAP_RE15__M 0x1FF +#define IQM_CF_TAP_RE15__PRE 0x2 +#define IQM_CF_TAP_RE16__A 0x1860030 +#define IQM_CF_TAP_RE16__W 9 +#define IQM_CF_TAP_RE16__M 0x1FF +#define IQM_CF_TAP_RE16__PRE 0x2 +#define IQM_CF_TAP_RE17__A 0x1860031 +#define IQM_CF_TAP_RE17__W 9 +#define IQM_CF_TAP_RE17__M 0x1FF +#define IQM_CF_TAP_RE17__PRE 0x2 +#define IQM_CF_TAP_RE18__A 0x1860032 +#define IQM_CF_TAP_RE18__W 9 +#define IQM_CF_TAP_RE18__M 0x1FF +#define IQM_CF_TAP_RE18__PRE 0x2 +#define IQM_CF_TAP_RE19__A 0x1860033 +#define IQM_CF_TAP_RE19__W 9 +#define IQM_CF_TAP_RE19__M 0x1FF +#define IQM_CF_TAP_RE19__PRE 0x2 +#define IQM_CF_TAP_RE20__A 0x1860034 +#define IQM_CF_TAP_RE20__W 9 +#define IQM_CF_TAP_RE20__M 0x1FF +#define IQM_CF_TAP_RE20__PRE 0x2 +#define IQM_CF_TAP_RE21__A 0x1860035 +#define IQM_CF_TAP_RE21__W 11 +#define IQM_CF_TAP_RE21__M 0x7FF +#define IQM_CF_TAP_RE21__PRE 0x2 +#define IQM_CF_TAP_RE22__A 0x1860036 +#define IQM_CF_TAP_RE22__W 11 +#define IQM_CF_TAP_RE22__M 0x7FF +#define IQM_CF_TAP_RE22__PRE 0x2 +#define IQM_CF_TAP_RE23__A 0x1860037 +#define IQM_CF_TAP_RE23__W 11 +#define IQM_CF_TAP_RE23__M 0x7FF +#define IQM_CF_TAP_RE23__PRE 0x2 +#define IQM_CF_TAP_RE24__A 0x1860038 +#define IQM_CF_TAP_RE24__W 11 +#define IQM_CF_TAP_RE24__M 0x7FF +#define IQM_CF_TAP_RE24__PRE 0x2 +#define IQM_CF_TAP_RE25__A 0x1860039 +#define IQM_CF_TAP_RE25__W 11 +#define IQM_CF_TAP_RE25__M 0x7FF +#define IQM_CF_TAP_RE25__PRE 0x2 +#define IQM_CF_TAP_RE26__A 0x186003A +#define IQM_CF_TAP_RE26__W 11 +#define IQM_CF_TAP_RE26__M 0x7FF +#define IQM_CF_TAP_RE26__PRE 0x2 +#define IQM_CF_TAP_RE27__A 0x186003B +#define IQM_CF_TAP_RE27__W 11 +#define IQM_CF_TAP_RE27__M 0x7FF +#define IQM_CF_TAP_RE27__PRE 0x2 +#define IQM_CF_TAP_IM0__A 0x1860040 +#define IQM_CF_TAP_IM0__W 7 +#define IQM_CF_TAP_IM0__M 0x7F +#define IQM_CF_TAP_IM0__PRE 0x2 +#define IQM_CF_TAP_IM1__A 0x1860041 +#define IQM_CF_TAP_IM1__W 7 +#define IQM_CF_TAP_IM1__M 0x7F +#define IQM_CF_TAP_IM1__PRE 0x2 +#define IQM_CF_TAP_IM2__A 0x1860042 +#define IQM_CF_TAP_IM2__W 7 +#define IQM_CF_TAP_IM2__M 0x7F +#define IQM_CF_TAP_IM2__PRE 0x2 +#define IQM_CF_TAP_IM3__A 0x1860043 +#define IQM_CF_TAP_IM3__W 7 +#define IQM_CF_TAP_IM3__M 0x7F +#define IQM_CF_TAP_IM3__PRE 0x2 +#define IQM_CF_TAP_IM4__A 0x1860044 +#define IQM_CF_TAP_IM4__W 7 +#define IQM_CF_TAP_IM4__M 0x7F +#define IQM_CF_TAP_IM4__PRE 0x2 +#define IQM_CF_TAP_IM5__A 0x1860045 +#define IQM_CF_TAP_IM5__W 7 +#define IQM_CF_TAP_IM5__M 0x7F +#define IQM_CF_TAP_IM5__PRE 0x2 +#define IQM_CF_TAP_IM6__A 0x1860046 +#define IQM_CF_TAP_IM6__W 7 +#define IQM_CF_TAP_IM6__M 0x7F +#define IQM_CF_TAP_IM6__PRE 0x2 +#define IQM_CF_TAP_IM7__A 0x1860047 +#define IQM_CF_TAP_IM7__W 9 +#define IQM_CF_TAP_IM7__M 0x1FF +#define IQM_CF_TAP_IM7__PRE 0x2 +#define IQM_CF_TAP_IM8__A 0x1860048 +#define IQM_CF_TAP_IM8__W 9 +#define IQM_CF_TAP_IM8__M 0x1FF +#define IQM_CF_TAP_IM8__PRE 0x2 +#define IQM_CF_TAP_IM9__A 0x1860049 +#define IQM_CF_TAP_IM9__W 9 +#define IQM_CF_TAP_IM9__M 0x1FF +#define IQM_CF_TAP_IM9__PRE 0x2 +#define IQM_CF_TAP_IM10__A 0x186004A +#define IQM_CF_TAP_IM10__W 9 +#define IQM_CF_TAP_IM10__M 0x1FF +#define IQM_CF_TAP_IM10__PRE 0x2 +#define IQM_CF_TAP_IM11__A 0x186004B +#define IQM_CF_TAP_IM11__W 9 +#define IQM_CF_TAP_IM11__M 0x1FF +#define IQM_CF_TAP_IM11__PRE 0x2 +#define IQM_CF_TAP_IM12__A 0x186004C +#define IQM_CF_TAP_IM12__W 9 +#define IQM_CF_TAP_IM12__M 0x1FF +#define IQM_CF_TAP_IM12__PRE 0x2 +#define IQM_CF_TAP_IM13__A 0x186004D +#define IQM_CF_TAP_IM13__W 9 +#define IQM_CF_TAP_IM13__M 0x1FF +#define IQM_CF_TAP_IM13__PRE 0x2 +#define IQM_CF_TAP_IM14__A 0x186004E +#define IQM_CF_TAP_IM14__W 9 +#define IQM_CF_TAP_IM14__M 0x1FF +#define IQM_CF_TAP_IM14__PRE 0x2 +#define IQM_CF_TAP_IM15__A 0x186004F +#define IQM_CF_TAP_IM15__W 9 +#define IQM_CF_TAP_IM15__M 0x1FF +#define IQM_CF_TAP_IM15__PRE 0x2 +#define IQM_CF_TAP_IM16__A 0x1860050 +#define IQM_CF_TAP_IM16__W 9 +#define IQM_CF_TAP_IM16__M 0x1FF +#define IQM_CF_TAP_IM16__PRE 0x2 +#define IQM_CF_TAP_IM17__A 0x1860051 +#define IQM_CF_TAP_IM17__W 9 +#define IQM_CF_TAP_IM17__M 0x1FF +#define IQM_CF_TAP_IM17__PRE 0x2 +#define IQM_CF_TAP_IM18__A 0x1860052 +#define IQM_CF_TAP_IM18__W 9 +#define IQM_CF_TAP_IM18__M 0x1FF +#define IQM_CF_TAP_IM18__PRE 0x2 +#define IQM_CF_TAP_IM19__A 0x1860053 +#define IQM_CF_TAP_IM19__W 9 +#define IQM_CF_TAP_IM19__M 0x1FF +#define IQM_CF_TAP_IM19__PRE 0x2 +#define IQM_CF_TAP_IM20__A 0x1860054 +#define IQM_CF_TAP_IM20__W 9 +#define IQM_CF_TAP_IM20__M 0x1FF +#define IQM_CF_TAP_IM20__PRE 0x2 +#define IQM_CF_TAP_IM21__A 0x1860055 +#define IQM_CF_TAP_IM21__W 11 +#define IQM_CF_TAP_IM21__M 0x7FF +#define IQM_CF_TAP_IM21__PRE 0x2 +#define IQM_CF_TAP_IM22__A 0x1860056 +#define IQM_CF_TAP_IM22__W 11 +#define IQM_CF_TAP_IM22__M 0x7FF +#define IQM_CF_TAP_IM22__PRE 0x2 +#define IQM_CF_TAP_IM23__A 0x1860057 +#define IQM_CF_TAP_IM23__W 11 +#define IQM_CF_TAP_IM23__M 0x7FF +#define IQM_CF_TAP_IM23__PRE 0x2 +#define IQM_CF_TAP_IM24__A 0x1860058 +#define IQM_CF_TAP_IM24__W 11 +#define IQM_CF_TAP_IM24__M 0x7FF +#define IQM_CF_TAP_IM24__PRE 0x2 +#define IQM_CF_TAP_IM25__A 0x1860059 +#define IQM_CF_TAP_IM25__W 11 +#define IQM_CF_TAP_IM25__M 0x7FF +#define IQM_CF_TAP_IM25__PRE 0x2 +#define IQM_CF_TAP_IM26__A 0x186005A +#define IQM_CF_TAP_IM26__W 11 +#define IQM_CF_TAP_IM26__M 0x7FF +#define IQM_CF_TAP_IM26__PRE 0x2 +#define IQM_CF_TAP_IM27__A 0x186005B +#define IQM_CF_TAP_IM27__W 11 +#define IQM_CF_TAP_IM27__M 0x7FF +#define IQM_CF_TAP_IM27__PRE 0x2 + +#define IQM_AF_COMM_EXEC__A 0x1870000 +#define IQM_AF_COMM_EXEC__W 2 +#define IQM_AF_COMM_EXEC__M 0x3 +#define IQM_AF_COMM_EXEC__PRE 0x0 +#define IQM_AF_COMM_EXEC_STOP 0x0 +#define IQM_AF_COMM_EXEC_ACTIVE 0x1 +#define IQM_AF_COMM_EXEC_HOLD 0x2 + +#define IQM_AF_COMM_MB__A 0x1870002 +#define IQM_AF_COMM_MB__W 8 +#define IQM_AF_COMM_MB__M 0xFF +#define IQM_AF_COMM_MB__PRE 0x0 +#define IQM_AF_COMM_MB_CTL__B 0 +#define IQM_AF_COMM_MB_CTL__W 1 +#define IQM_AF_COMM_MB_CTL__M 0x1 +#define IQM_AF_COMM_MB_CTL__PRE 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_AF_COMM_MB_OBS__B 1 +#define IQM_AF_COMM_MB_OBS__W 1 +#define IQM_AF_COMM_MB_OBS__M 0x2 +#define IQM_AF_COMM_MB_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_ON 0x2 +#define IQM_AF_COMM_MB_MUX_CTRL__B 2 +#define IQM_AF_COMM_MB_MUX_CTRL__W 3 +#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C +#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x4 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x8 +#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0xC +#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0x10 +#define IQM_AF_COMM_MB_MUX_OBS__B 5 +#define IQM_AF_COMM_MB_MUX_OBS__W 3 +#define IQM_AF_COMM_MB_MUX_OBS__M 0xE0 +#define IQM_AF_COMM_MB_MUX_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0x20 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0x40 +#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0x60 +#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0x80 + +#define IQM_AF_COMM_INT_REQ__A 0x1870003 +#define IQM_AF_COMM_INT_REQ__W 1 +#define IQM_AF_COMM_INT_REQ__M 0x1 +#define IQM_AF_COMM_INT_REQ__PRE 0x0 +#define IQM_AF_COMM_INT_STA__A 0x1870005 +#define IQM_AF_COMM_INT_STA__W 2 +#define IQM_AF_COMM_INT_STA__M 0x3 +#define IQM_AF_COMM_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0x0 + +#define IQM_AF_COMM_INT_MSK__A 0x1870006 +#define IQM_AF_COMM_INT_MSK__W 2 +#define IQM_AF_COMM_INT_MSK__M 0x3 +#define IQM_AF_COMM_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0x1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x2 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0x0 + +#define IQM_AF_COMM_INT_STM__A 0x1870007 +#define IQM_AF_COMM_INT_STM__W 2 +#define IQM_AF_COMM_INT_STM__M 0x3 +#define IQM_AF_COMM_INT_STM__PRE 0x0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0 + +#define IQM_AF_FDB_SEL__A 0x1870010 +#define IQM_AF_FDB_SEL__W 1 +#define IQM_AF_FDB_SEL__M 0x1 +#define IQM_AF_FDB_SEL__PRE 0x0 + +#define IQM_AF_INVEXT__A 0x1870011 +#define IQM_AF_INVEXT__W 1 +#define IQM_AF_INVEXT__M 0x1 +#define IQM_AF_INVEXT__PRE 0x0 +#define IQM_AF_CLKNEG__A 0x1870012 +#define IQM_AF_CLKNEG__W 2 +#define IQM_AF_CLKNEG__M 0x3 +#define IQM_AF_CLKNEG__PRE 0x0 + +#define IQM_AF_CLKNEG_CLKNEGPEAK__B 0 +#define IQM_AF_CLKNEG_CLKNEGPEAK__W 1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__M 0x1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0x1 + +#define IQM_AF_CLKNEG_CLKNEGDATA__B 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__W 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 +#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 + +#define IQM_AF_MON_IN_MUX__A 0x1870013 +#define IQM_AF_MON_IN_MUX__W 2 +#define IQM_AF_MON_IN_MUX__M 0x3 +#define IQM_AF_MON_IN_MUX__PRE 0x0 + +#define IQM_AF_MON_IN5__A 0x1870014 +#define IQM_AF_MON_IN5__W 10 +#define IQM_AF_MON_IN5__M 0x3FF +#define IQM_AF_MON_IN5__PRE 0x0 + +#define IQM_AF_MON_IN4__A 0x1870015 +#define IQM_AF_MON_IN4__W 10 +#define IQM_AF_MON_IN4__M 0x3FF +#define IQM_AF_MON_IN4__PRE 0x0 + +#define IQM_AF_MON_IN3__A 0x1870016 +#define IQM_AF_MON_IN3__W 10 +#define IQM_AF_MON_IN3__M 0x3FF +#define IQM_AF_MON_IN3__PRE 0x0 + +#define IQM_AF_MON_IN2__A 0x1870017 +#define IQM_AF_MON_IN2__W 10 +#define IQM_AF_MON_IN2__M 0x3FF +#define IQM_AF_MON_IN2__PRE 0x0 + +#define IQM_AF_MON_IN1__A 0x1870018 +#define IQM_AF_MON_IN1__W 10 +#define IQM_AF_MON_IN1__M 0x3FF +#define IQM_AF_MON_IN1__PRE 0x0 + +#define IQM_AF_MON_IN0__A 0x1870019 +#define IQM_AF_MON_IN0__W 10 +#define IQM_AF_MON_IN0__M 0x3FF +#define IQM_AF_MON_IN0__PRE 0x0 + +#define IQM_AF_MON_IN_VAL__A 0x187001A +#define IQM_AF_MON_IN_VAL__W 1 +#define IQM_AF_MON_IN_VAL__M 0x1 +#define IQM_AF_MON_IN_VAL__PRE 0x0 + +#define IQM_AF_START_LOCK__A 0x187001B +#define IQM_AF_START_LOCK__W 1 +#define IQM_AF_START_LOCK__M 0x1 +#define IQM_AF_START_LOCK__PRE 0x0 + +#define IQM_AF_PHASE0__A 0x187001C +#define IQM_AF_PHASE0__W 7 +#define IQM_AF_PHASE0__M 0x7F +#define IQM_AF_PHASE0__PRE 0x0 + +#define IQM_AF_PHASE1__A 0x187001D +#define IQM_AF_PHASE1__W 7 +#define IQM_AF_PHASE1__M 0x7F +#define IQM_AF_PHASE1__PRE 0x0 + +#define IQM_AF_PHASE2__A 0x187001E +#define IQM_AF_PHASE2__W 7 +#define IQM_AF_PHASE2__M 0x7F +#define IQM_AF_PHASE2__PRE 0x0 + +#define IQM_AF_SCU_PHASE__A 0x187001F +#define IQM_AF_SCU_PHASE__W 2 +#define IQM_AF_SCU_PHASE__M 0x3 +#define IQM_AF_SCU_PHASE__PRE 0x0 + +#define IQM_AF_SYNC_SEL__A 0x1870020 +#define IQM_AF_SYNC_SEL__W 2 +#define IQM_AF_SYNC_SEL__M 0x3 +#define IQM_AF_SYNC_SEL__PRE 0x0 +#define IQM_AF_ADC_CONF__A 0x1870021 +#define IQM_AF_ADC_CONF__W 4 +#define IQM_AF_ADC_CONF__M 0xF +#define IQM_AF_ADC_CONF__PRE 0x0 + +#define IQM_AF_ADC_CONF_ADC_SIGN__B 0 +#define IQM_AF_ADC_CONF_ADC_SIGN__W 1 +#define IQM_AF_ADC_CONF_ADC_SIGN__M 0x1 +#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0x1 + +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x2 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x2 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 2 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0x4 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0x4 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 3 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0x8 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8 + +#define IQM_AF_CLP_CLIP__A 0x1870022 +#define IQM_AF_CLP_CLIP__W 16 +#define IQM_AF_CLP_CLIP__M 0xFFFF +#define IQM_AF_CLP_CLIP__PRE 0x0 + +#define IQM_AF_CLP_LEN__A 0x1870023 +#define IQM_AF_CLP_LEN__W 16 +#define IQM_AF_CLP_LEN__M 0xFFFF +#define IQM_AF_CLP_LEN__PRE 0x0 +#define IQM_AF_CLP_LEN_QAM_B_64 0x400 +#define IQM_AF_CLP_LEN_QAM_B_256 0x400 +#define IQM_AF_CLP_LEN_ATV 0x0 + +#define IQM_AF_CLP_TH__A 0x1870024 +#define IQM_AF_CLP_TH__W 9 +#define IQM_AF_CLP_TH__M 0x1FF +#define IQM_AF_CLP_TH__PRE 0x0 +#define IQM_AF_CLP_TH_QAM_B_64 0x80 +#define IQM_AF_CLP_TH_QAM_B_256 0x80 +#define IQM_AF_CLP_TH_ATV 0x1C0 + +#define IQM_AF_DCF_BYPASS__A 0x1870025 +#define IQM_AF_DCF_BYPASS__W 1 +#define IQM_AF_DCF_BYPASS__M 0x1 +#define IQM_AF_DCF_BYPASS__PRE 0x0 +#define IQM_AF_DCF_BYPASS_ACTIVE 0x0 +#define IQM_AF_DCF_BYPASS_BYPASS 0x1 + +#define IQM_AF_SNS_LEN__A 0x1870026 +#define IQM_AF_SNS_LEN__W 16 +#define IQM_AF_SNS_LEN__M 0xFFFF +#define IQM_AF_SNS_LEN__PRE 0x0 +#define IQM_AF_SNS_LEN_QAM_B_64 0x400 +#define IQM_AF_SNS_LEN_QAM_B_256 0x400 +#define IQM_AF_SNS_LEN_ATV 0x0 + +#define IQM_AF_SNS_SENSE__A 0x1870027 +#define IQM_AF_SNS_SENSE__W 16 +#define IQM_AF_SNS_SENSE__M 0xFFFF +#define IQM_AF_SNS_SENSE__PRE 0x0 + +#define IQM_AF_AGC_IF__A 0x1870028 +#define IQM_AF_AGC_IF__W 15 +#define IQM_AF_AGC_IF__M 0x7FFF +#define IQM_AF_AGC_IF__PRE 0x0 + +#define IQM_AF_AGC_RF__A 0x1870029 +#define IQM_AF_AGC_RF__W 15 +#define IQM_AF_AGC_RF__M 0x7FFF +#define IQM_AF_AGC_RF__PRE 0x0 + +#define IQM_AF_PGA_GAIN__A 0x187002A +#define IQM_AF_PGA_GAIN__W 4 +#define IQM_AF_PGA_GAIN__M 0xF +#define IQM_AF_PGA_GAIN__PRE 0x0 + +#define IQM_AF_PDREF__A 0x187002B +#define IQM_AF_PDREF__W 5 +#define IQM_AF_PDREF__M 0x1F +#define IQM_AF_PDREF__PRE 0x0 +#define IQM_AF_PDREF_QAM_B_64 0xF +#define IQM_AF_PDREF_QAM_B_256 0xF +#define IQM_AF_PDREF_ATV 0xF + +#define IQM_AF_STDBY__A 0x187002C +#define IQM_AF_STDBY__W 6 +#define IQM_AF_STDBY__M 0x3F +#define IQM_AF_STDBY__PRE 0x0 + +#define IQM_AF_STDBY_STDBY_BIAS__B 0 +#define IQM_AF_STDBY_STDBY_BIAS__W 1 +#define IQM_AF_STDBY_STDBY_BIAS__M 0x1 +#define IQM_AF_STDBY_STDBY_BIAS__PRE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0x1 + +#define IQM_AF_STDBY_STDBY_ADC__B 1 +#define IQM_AF_STDBY_STDBY_ADC__W 1 +#define IQM_AF_STDBY_STDBY_ADC__M 0x2 +#define IQM_AF_STDBY_STDBY_ADC__PRE 0x0 +#define IQM_AF_STDBY_STDBY_ADC_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_ADC_A1_STANDBY 0x2 +#define IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE 0x2 +#define IQM_AF_STDBY_STDBY_ADC_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_AMP__B 2 +#define IQM_AF_STDBY_STDBY_AMP__W 1 +#define IQM_AF_STDBY_STDBY_AMP__M 0x4 +#define IQM_AF_STDBY_STDBY_AMP__PRE 0x0 +#define IQM_AF_STDBY_STDBY_AMP_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_AMP_A1_STANDBY 0x4 +#define IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE 0x4 +#define IQM_AF_STDBY_STDBY_AMP_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_PD__B 3 +#define IQM_AF_STDBY_STDBY_PD__W 1 +#define IQM_AF_STDBY_STDBY_PD__M 0x8 +#define IQM_AF_STDBY_STDBY_PD__PRE 0x0 +#define IQM_AF_STDBY_STDBY_PD_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_PD_A1_STANDBY 0x8 +#define IQM_AF_STDBY_STDBY_PD_A2_ACTIVE 0x8 +#define IQM_AF_STDBY_STDBY_PD_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_TAGC_IF__B 4 +#define IQM_AF_STDBY_STDBY_TAGC_IF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_IF__M 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A1_STANDBY 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_TAGC_RF__B 5 +#define IQM_AF_STDBY_STDBY_TAGC_RF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_RF__M 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A1_STANDBY 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_STANDBY 0x0 + +#define IQM_AF_AMUX__A 0x187002D +#define IQM_AF_AMUX__W 2 +#define IQM_AF_AMUX__M 0x3 +#define IQM_AF_AMUX__PRE 0x0 + +#define IQM_AF_TST_AFEMAIN__A 0x187002E +#define IQM_AF_TST_AFEMAIN__W 8 +#define IQM_AF_TST_AFEMAIN__M 0xFF +#define IQM_AF_TST_AFEMAIN__PRE 0x0 + +#define IQM_RT_RAM__A 0x1880000 + +#define IQM_RT_RAM_DLY__B 0 +#define IQM_RT_RAM_DLY__W 13 +#define IQM_RT_RAM_DLY__M 0x1FFF +#define IQM_RT_RAM_DLY__PRE 0x0 + +#define ORX_COMM_EXEC__A 0x2000000 +#define ORX_COMM_EXEC__W 2 +#define ORX_COMM_EXEC__M 0x3 +#define ORX_COMM_EXEC__PRE 0x0 +#define ORX_COMM_EXEC_STOP 0x0 +#define ORX_COMM_EXEC_ACTIVE 0x1 +#define ORX_COMM_EXEC_HOLD 0x2 + +#define ORX_COMM_STATE__A 0x2000001 +#define ORX_COMM_STATE__W 16 +#define ORX_COMM_STATE__M 0xFFFF +#define ORX_COMM_STATE__PRE 0x0 +#define ORX_COMM_MB__A 0x2000002 +#define ORX_COMM_MB__W 16 +#define ORX_COMM_MB__M 0xFFFF +#define ORX_COMM_MB__PRE 0x0 +#define ORX_COMM_INT_REQ__A 0x2000003 +#define ORX_COMM_INT_REQ__W 16 +#define ORX_COMM_INT_REQ__M 0xFFFF +#define ORX_COMM_INT_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_EQU_REQ__B 0 +#define ORX_COMM_INT_REQ_EQU_REQ__W 1 +#define ORX_COMM_INT_REQ_EQU_REQ__M 0x1 +#define ORX_COMM_INT_REQ_EQU_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_DDC_REQ__B 1 +#define ORX_COMM_INT_REQ_DDC_REQ__W 1 +#define ORX_COMM_INT_REQ_DDC_REQ__M 0x2 +#define ORX_COMM_INT_REQ_DDC_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_FWP_REQ__B 2 +#define ORX_COMM_INT_REQ_FWP_REQ__W 1 +#define ORX_COMM_INT_REQ_FWP_REQ__M 0x4 +#define ORX_COMM_INT_REQ_FWP_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_CON_REQ__B 3 +#define ORX_COMM_INT_REQ_CON_REQ__W 1 +#define ORX_COMM_INT_REQ_CON_REQ__M 0x8 +#define ORX_COMM_INT_REQ_CON_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_NSU_REQ__B 4 +#define ORX_COMM_INT_REQ_NSU_REQ__W 1 +#define ORX_COMM_INT_REQ_NSU_REQ__M 0x10 +#define ORX_COMM_INT_REQ_NSU_REQ__PRE 0x0 + +#define ORX_COMM_INT_STA__A 0x2000005 +#define ORX_COMM_INT_STA__W 16 +#define ORX_COMM_INT_STA__M 0xFFFF +#define ORX_COMM_INT_STA__PRE 0x0 +#define ORX_COMM_INT_MSK__A 0x2000006 +#define ORX_COMM_INT_MSK__W 16 +#define ORX_COMM_INT_MSK__M 0xFFFF +#define ORX_COMM_INT_MSK__PRE 0x0 +#define ORX_COMM_INT_STM__A 0x2000007 +#define ORX_COMM_INT_STM__W 16 +#define ORX_COMM_INT_STM__M 0xFFFF +#define ORX_COMM_INT_STM__PRE 0x0 + +#define ORX_TOP_COMM_EXEC__A 0x2010000 +#define ORX_TOP_COMM_EXEC__W 2 +#define ORX_TOP_COMM_EXEC__M 0x3 +#define ORX_TOP_COMM_EXEC__PRE 0x0 +#define ORX_TOP_COMM_EXEC_STOP 0x0 +#define ORX_TOP_COMM_EXEC_ACTIVE 0x1 +#define ORX_TOP_COMM_EXEC_HOLD 0x2 + +#define ORX_TOP_COMM_KEY__A 0x201000F +#define ORX_TOP_COMM_KEY__W 16 +#define ORX_TOP_COMM_KEY__M 0xFFFF +#define ORX_TOP_COMM_KEY__PRE 0x0 +#define ORX_TOP_COMM_KEY_KEY 0xFABA + +#define ORX_TOP_MDE_W__A 0x2010010 +#define ORX_TOP_MDE_W__W 2 +#define ORX_TOP_MDE_W__M 0x3 +#define ORX_TOP_MDE_W__PRE 0x2 +#define ORX_TOP_MDE_W_RATE_1544KBPS 0x0 +#define ORX_TOP_MDE_W_RATE_3088KBPS 0x1 +#define ORX_TOP_MDE_W_RATE_2048KBPS_SQRT 0x2 +#define ORX_TOP_MDE_W_RATE_2048KBPS_RO 0x3 + +#define ORX_TOP_AIF_CTRL_W__A 0x2010011 +#define ORX_TOP_AIF_CTRL_W__W 3 +#define ORX_TOP_AIF_CTRL_W__M 0x7 +#define ORX_TOP_AIF_CTRL_W__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__B 0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__W 1 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__M 0x1 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_POS_CLK_EDGE 0x0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_NEG_CLK_EDGE 0x1 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__B 1 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__W 1 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__M 0x2 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REGULAR_BIT_ORDER_ADC 0x0 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REVERSAL_BIT_ORDER_ADC 0x2 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__B 2 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__W 1 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__M 0x4 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_INV_MSB_NO_MSB_INVERSION_ADC 0x0 +#define ORX_TOP_AIF_CTRL_W_INV_MSB_MSB_INVERSION_ADC 0x4 + +#define ORX_FWP_COMM_EXEC__A 0x2020000 +#define ORX_FWP_COMM_EXEC__W 2 +#define ORX_FWP_COMM_EXEC__M 0x3 +#define ORX_FWP_COMM_EXEC__PRE 0x0 +#define ORX_FWP_COMM_EXEC_STOP 0x0 +#define ORX_FWP_COMM_EXEC_ACTIVE 0x1 +#define ORX_FWP_COMM_EXEC_HOLD 0x2 + +#define ORX_FWP_COMM_MB__A 0x2020002 +#define ORX_FWP_COMM_MB__W 8 +#define ORX_FWP_COMM_MB__M 0xFF +#define ORX_FWP_COMM_MB__PRE 0x0 +#define ORX_FWP_COMM_MB_CTL__B 0 +#define ORX_FWP_COMM_MB_CTL__W 1 +#define ORX_FWP_COMM_MB_CTL__M 0x1 +#define ORX_FWP_COMM_MB_CTL__PRE 0x0 +#define ORX_FWP_COMM_MB_CTL_OFF 0x0 +#define ORX_FWP_COMM_MB_CTL_ON 0x1 +#define ORX_FWP_COMM_MB_OBS__B 1 +#define ORX_FWP_COMM_MB_OBS__W 1 +#define ORX_FWP_COMM_MB_OBS__M 0x2 +#define ORX_FWP_COMM_MB_OBS__PRE 0x0 +#define ORX_FWP_COMM_MB_OBS_OFF 0x0 +#define ORX_FWP_COMM_MB_OBS_ON 0x2 + +#define ORX_FWP_COMM_MB_CTL_MUX__B 2 +#define ORX_FWP_COMM_MB_CTL_MUX__W 3 +#define ORX_FWP_COMM_MB_CTL_MUX__M 0x1C +#define ORX_FWP_COMM_MB_CTL_MUX__PRE 0x0 + +#define ORX_FWP_COMM_MB_OBS_MUX__B 5 +#define ORX_FWP_COMM_MB_OBS_MUX__W 3 +#define ORX_FWP_COMM_MB_OBS_MUX__M 0xE0 +#define ORX_FWP_COMM_MB_OBS_MUX__PRE 0x0 + +#define ORX_FWP_AAG_LEN_W__A 0x2020010 +#define ORX_FWP_AAG_LEN_W__W 16 +#define ORX_FWP_AAG_LEN_W__M 0xFFFF +#define ORX_FWP_AAG_LEN_W__PRE 0x800 + +#define ORX_FWP_AAG_THR_W__A 0x2020011 +#define ORX_FWP_AAG_THR_W__W 8 +#define ORX_FWP_AAG_THR_W__M 0xFF +#define ORX_FWP_AAG_THR_W__PRE 0x50 + +#define ORX_FWP_AAG_THR_CNT_R__A 0x2020012 +#define ORX_FWP_AAG_THR_CNT_R__W 16 +#define ORX_FWP_AAG_THR_CNT_R__M 0xFFFF +#define ORX_FWP_AAG_THR_CNT_R__PRE 0x0 + +#define ORX_FWP_AAG_SNS_CNT_R__A 0x2020013 +#define ORX_FWP_AAG_SNS_CNT_R__W 16 +#define ORX_FWP_AAG_SNS_CNT_R__M 0xFFFF +#define ORX_FWP_AAG_SNS_CNT_R__PRE 0x0 + +#define ORX_FWP_PFI_A_W__A 0x2020014 +#define ORX_FWP_PFI_A_W__W 8 +#define ORX_FWP_PFI_A_W__M 0xFF +#define ORX_FWP_PFI_A_W__PRE 0xB0 +#define ORX_FWP_PFI_A_W_RATE_2048KBPS 0xB0 +#define ORX_FWP_PFI_A_W_RATE_1544KBPS 0xA4 +#define ORX_FWP_PFI_A_W_RATE_3088KBPS 0xC0 + +#define ORX_FWP_PFI_B_W__A 0x2020015 +#define ORX_FWP_PFI_B_W__W 8 +#define ORX_FWP_PFI_B_W__M 0xFF +#define ORX_FWP_PFI_B_W__PRE 0x9E +#define ORX_FWP_PFI_B_W_RATE_2048KBPS 0x9E +#define ORX_FWP_PFI_B_W_RATE_1544KBPS 0x94 +#define ORX_FWP_PFI_B_W_RATE_3088KBPS 0xB0 + +#define ORX_FWP_PFI_C_W__A 0x2020016 +#define ORX_FWP_PFI_C_W__W 8 +#define ORX_FWP_PFI_C_W__M 0xFF +#define ORX_FWP_PFI_C_W__PRE 0x5C +#define ORX_FWP_PFI_C_W_RATE_2048KBPS 0x5C +#define ORX_FWP_PFI_C_W_RATE_1544KBPS 0x64 +#define ORX_FWP_PFI_C_W_RATE_3088KBPS 0x50 + +#define ORX_FWP_KR1_AMP_R__A 0x2020017 +#define ORX_FWP_KR1_AMP_R__W 9 +#define ORX_FWP_KR1_AMP_R__M 0x1FF +#define ORX_FWP_KR1_AMP_R__PRE 0x0 + +#define ORX_FWP_KR1_LDT_W__A 0x2020018 +#define ORX_FWP_KR1_LDT_W__W 3 +#define ORX_FWP_KR1_LDT_W__M 0x7 +#define ORX_FWP_KR1_LDT_W__PRE 0x2 +#define ORX_FWP_SRC_DGN_W__A 0x2020019 +#define ORX_FWP_SRC_DGN_W__W 16 +#define ORX_FWP_SRC_DGN_W__M 0xFFFF +#define ORX_FWP_SRC_DGN_W__PRE 0x1FF + +#define ORX_FWP_SRC_DGN_W_MANT__B 0 +#define ORX_FWP_SRC_DGN_W_MANT__W 9 +#define ORX_FWP_SRC_DGN_W_MANT__M 0x1FF +#define ORX_FWP_SRC_DGN_W_MANT__PRE 0x1FF + +#define ORX_FWP_SRC_DGN_W_EXP__B 12 +#define ORX_FWP_SRC_DGN_W_EXP__W 4 +#define ORX_FWP_SRC_DGN_W_EXP__M 0xF000 +#define ORX_FWP_SRC_DGN_W_EXP__PRE 0x0 + +#define ORX_FWP_NYQ_ADR_W__A 0x202001A +#define ORX_FWP_NYQ_ADR_W__W 5 +#define ORX_FWP_NYQ_ADR_W__M 0x1F +#define ORX_FWP_NYQ_ADR_W__PRE 0x1F + +#define ORX_FWP_NYQ_COF_RW__A 0x202001B +#define ORX_FWP_NYQ_COF_RW__W 10 +#define ORX_FWP_NYQ_COF_RW__M 0x3FF +#define ORX_FWP_NYQ_COF_RW__PRE 0x0 + +#define ORX_FWP_IQM_FRQ_W__A 0x202001C +#define ORX_FWP_IQM_FRQ_W__W 16 +#define ORX_FWP_IQM_FRQ_W__M 0xFFFF +#define ORX_FWP_IQM_FRQ_W__PRE 0x4301 + +#define ORX_EQU_COMM_EXEC__A 0x2030000 +#define ORX_EQU_COMM_EXEC__W 2 +#define ORX_EQU_COMM_EXEC__M 0x3 +#define ORX_EQU_COMM_EXEC__PRE 0x0 +#define ORX_EQU_COMM_EXEC_STOP 0x0 +#define ORX_EQU_COMM_EXEC_ACTIVE 0x1 +#define ORX_EQU_COMM_EXEC_HOLD 0x2 + +#define ORX_EQU_COMM_MB__A 0x2030002 +#define ORX_EQU_COMM_MB__W 8 +#define ORX_EQU_COMM_MB__M 0xFF +#define ORX_EQU_COMM_MB__PRE 0x0 +#define ORX_EQU_COMM_MB_CTL__B 0 +#define ORX_EQU_COMM_MB_CTL__W 1 +#define ORX_EQU_COMM_MB_CTL__M 0x1 +#define ORX_EQU_COMM_MB_CTL__PRE 0x0 +#define ORX_EQU_COMM_MB_CTL_OFF 0x0 +#define ORX_EQU_COMM_MB_CTL_ON 0x1 +#define ORX_EQU_COMM_MB_OBS__B 1 +#define ORX_EQU_COMM_MB_OBS__W 1 +#define ORX_EQU_COMM_MB_OBS__M 0x2 +#define ORX_EQU_COMM_MB_OBS__PRE 0x0 +#define ORX_EQU_COMM_MB_OBS_OFF 0x0 +#define ORX_EQU_COMM_MB_OBS_ON 0x2 + +#define ORX_EQU_COMM_MB_CTL_MUX__B 2 +#define ORX_EQU_COMM_MB_CTL_MUX__W 3 +#define ORX_EQU_COMM_MB_CTL_MUX__M 0x1C +#define ORX_EQU_COMM_MB_CTL_MUX__PRE 0x0 + +#define ORX_EQU_COMM_MB_OBS_MUX__B 5 +#define ORX_EQU_COMM_MB_OBS_MUX__W 3 +#define ORX_EQU_COMM_MB_OBS_MUX__M 0xE0 +#define ORX_EQU_COMM_MB_OBS_MUX__PRE 0x0 + +#define ORX_EQU_COMM_INT_REQ__A 0x2030003 +#define ORX_EQU_COMM_INT_REQ__W 1 +#define ORX_EQU_COMM_INT_REQ__M 0x1 +#define ORX_EQU_COMM_INT_REQ__PRE 0x0 +#define ORX_EQU_COMM_INT_STA__A 0x2030005 +#define ORX_EQU_COMM_INT_STA__W 2 +#define ORX_EQU_COMM_INT_STA__M 0x3 +#define ORX_EQU_COMM_INT_STA__PRE 0x0 + +#define ORX_EQU_COMM_INT_STA_FFF_READ__B 0 +#define ORX_EQU_COMM_INT_STA_FFF_READ__W 1 +#define ORX_EQU_COMM_INT_STA_FFF_READ__M 0x1 +#define ORX_EQU_COMM_INT_STA_FFF_READ__PRE 0x0 + +#define ORX_EQU_COMM_INT_STA_FBF_READ__B 1 +#define ORX_EQU_COMM_INT_STA_FBF_READ__W 1 +#define ORX_EQU_COMM_INT_STA_FBF_READ__M 0x2 +#define ORX_EQU_COMM_INT_STA_FBF_READ__PRE 0x0 + +#define ORX_EQU_COMM_INT_MSK__A 0x2030006 +#define ORX_EQU_COMM_INT_MSK__W 2 +#define ORX_EQU_COMM_INT_MSK__M 0x3 +#define ORX_EQU_COMM_INT_MSK__PRE 0x0 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__B 0 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__W 1 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__M 0x1 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__PRE 0x0 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__B 1 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__W 1 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__M 0x2 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__PRE 0x0 + +#define ORX_EQU_COMM_INT_STM__A 0x2030007 +#define ORX_EQU_COMM_INT_STM__W 2 +#define ORX_EQU_COMM_INT_STM__M 0x3 +#define ORX_EQU_COMM_INT_STM__PRE 0x0 +#define ORX_EQU_COMM_INT_STM_FFF_READ__B 0 +#define ORX_EQU_COMM_INT_STM_FFF_READ__W 1 +#define ORX_EQU_COMM_INT_STM_FFF_READ__M 0x1 +#define ORX_EQU_COMM_INT_STM_FFF_READ__PRE 0x0 +#define ORX_EQU_COMM_INT_STM_FBF_READ__B 1 +#define ORX_EQU_COMM_INT_STM_FBF_READ__W 1 +#define ORX_EQU_COMM_INT_STM_FBF_READ__M 0x2 +#define ORX_EQU_COMM_INT_STM_FBF_READ__PRE 0x0 + +#define ORX_EQU_FFF_SCL_W__A 0x2030010 +#define ORX_EQU_FFF_SCL_W__W 1 +#define ORX_EQU_FFF_SCL_W__M 0x1 +#define ORX_EQU_FFF_SCL_W__PRE 0x0 +#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_1 0x0 +#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_2 0x1 + +#define ORX_EQU_FFF_UPD_W__A 0x2030011 +#define ORX_EQU_FFF_UPD_W__W 1 +#define ORX_EQU_FFF_UPD_W__M 0x1 +#define ORX_EQU_FFF_UPD_W__PRE 0x0 +#define ORX_EQU_FFF_UPD_W_NO_UPDATE 0x0 +#define ORX_EQU_FFF_UPD_W_LMS_UPDATE 0x1 + +#define ORX_EQU_FFF_STP_W__A 0x2030012 +#define ORX_EQU_FFF_STP_W__W 3 +#define ORX_EQU_FFF_STP_W__M 0x7 +#define ORX_EQU_FFF_STP_W__PRE 0x2 + +#define ORX_EQU_FFF_LEA_W__A 0x2030013 +#define ORX_EQU_FFF_LEA_W__W 4 +#define ORX_EQU_FFF_LEA_W__M 0xF +#define ORX_EQU_FFF_LEA_W__PRE 0x4 + +#define ORX_EQU_FFF_RWT_W__A 0x2030014 +#define ORX_EQU_FFF_RWT_W__W 2 +#define ORX_EQU_FFF_RWT_W__M 0x3 +#define ORX_EQU_FFF_RWT_W__PRE 0x0 + +#define ORX_EQU_FFF_C0RE_RW__A 0x2030015 +#define ORX_EQU_FFF_C0RE_RW__W 12 +#define ORX_EQU_FFF_C0RE_RW__M 0xFFF +#define ORX_EQU_FFF_C0RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C0IM_RW__A 0x2030016 +#define ORX_EQU_FFF_C0IM_RW__W 12 +#define ORX_EQU_FFF_C0IM_RW__M 0xFFF +#define ORX_EQU_FFF_C0IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C1RE_RW__A 0x2030017 +#define ORX_EQU_FFF_C1RE_RW__W 12 +#define ORX_EQU_FFF_C1RE_RW__M 0xFFF +#define ORX_EQU_FFF_C1RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C1IM_RW__A 0x2030018 +#define ORX_EQU_FFF_C1IM_RW__W 12 +#define ORX_EQU_FFF_C1IM_RW__M 0xFFF +#define ORX_EQU_FFF_C1IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C2RE_RW__A 0x2030019 +#define ORX_EQU_FFF_C2RE_RW__W 12 +#define ORX_EQU_FFF_C2RE_RW__M 0xFFF +#define ORX_EQU_FFF_C2RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C2IM_RW__A 0x203001A +#define ORX_EQU_FFF_C2IM_RW__W 12 +#define ORX_EQU_FFF_C2IM_RW__M 0xFFF +#define ORX_EQU_FFF_C2IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C3RE_RW__A 0x203001B +#define ORX_EQU_FFF_C3RE_RW__W 12 +#define ORX_EQU_FFF_C3RE_RW__M 0xFFF +#define ORX_EQU_FFF_C3RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C3IM_RW__A 0x203001C +#define ORX_EQU_FFF_C3IM_RW__W 12 +#define ORX_EQU_FFF_C3IM_RW__M 0xFFF +#define ORX_EQU_FFF_C3IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C4RE_RW__A 0x203001D +#define ORX_EQU_FFF_C4RE_RW__W 12 +#define ORX_EQU_FFF_C4RE_RW__M 0xFFF +#define ORX_EQU_FFF_C4RE_RW__PRE 0x400 + +#define ORX_EQU_FFF_C4IM_RW__A 0x203001E +#define ORX_EQU_FFF_C4IM_RW__W 12 +#define ORX_EQU_FFF_C4IM_RW__M 0xFFF +#define ORX_EQU_FFF_C4IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C5RE_RW__A 0x203001F +#define ORX_EQU_FFF_C5RE_RW__W 12 +#define ORX_EQU_FFF_C5RE_RW__M 0xFFF +#define ORX_EQU_FFF_C5RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C5IM_RW__A 0x2030020 +#define ORX_EQU_FFF_C5IM_RW__W 12 +#define ORX_EQU_FFF_C5IM_RW__M 0xFFF +#define ORX_EQU_FFF_C5IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C6RE_RW__A 0x2030021 +#define ORX_EQU_FFF_C6RE_RW__W 12 +#define ORX_EQU_FFF_C6RE_RW__M 0xFFF +#define ORX_EQU_FFF_C6RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C6IM_RW__A 0x2030022 +#define ORX_EQU_FFF_C6IM_RW__W 12 +#define ORX_EQU_FFF_C6IM_RW__M 0xFFF +#define ORX_EQU_FFF_C6IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C7RE_RW__A 0x2030023 +#define ORX_EQU_FFF_C7RE_RW__W 12 +#define ORX_EQU_FFF_C7RE_RW__M 0xFFF +#define ORX_EQU_FFF_C7RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C7IM_RW__A 0x2030024 +#define ORX_EQU_FFF_C7IM_RW__W 12 +#define ORX_EQU_FFF_C7IM_RW__M 0xFFF +#define ORX_EQU_FFF_C7IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C8RE_RW__A 0x2030025 +#define ORX_EQU_FFF_C8RE_RW__W 12 +#define ORX_EQU_FFF_C8RE_RW__M 0xFFF +#define ORX_EQU_FFF_C8RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C8IM_RW__A 0x2030026 +#define ORX_EQU_FFF_C8IM_RW__W 12 +#define ORX_EQU_FFF_C8IM_RW__M 0xFFF +#define ORX_EQU_FFF_C8IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C9RE_RW__A 0x2030027 +#define ORX_EQU_FFF_C9RE_RW__W 12 +#define ORX_EQU_FFF_C9RE_RW__M 0xFFF +#define ORX_EQU_FFF_C9RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C9IM_RW__A 0x2030028 +#define ORX_EQU_FFF_C9IM_RW__W 12 +#define ORX_EQU_FFF_C9IM_RW__M 0xFFF +#define ORX_EQU_FFF_C9IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C10RE_RW__A 0x2030029 +#define ORX_EQU_FFF_C10RE_RW__W 12 +#define ORX_EQU_FFF_C10RE_RW__M 0xFFF +#define ORX_EQU_FFF_C10RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C10IM_RW__A 0x203002A +#define ORX_EQU_FFF_C10IM_RW__W 12 +#define ORX_EQU_FFF_C10IM_RW__M 0xFFF +#define ORX_EQU_FFF_C10IM_RW__PRE 0x0 + +#define ORX_EQU_MXB_SEL_W__A 0x203002B +#define ORX_EQU_MXB_SEL_W__W 1 +#define ORX_EQU_MXB_SEL_W__M 0x1 +#define ORX_EQU_MXB_SEL_W__PRE 0x0 +#define ORX_EQU_MXB_SEL_W_UNDECIDED_SYMBOLS 0x0 +#define ORX_EQU_MXB_SEL_W_DECIDED_SYMBOLS 0x1 + +#define ORX_EQU_FBF_UPD_W__A 0x203002C +#define ORX_EQU_FBF_UPD_W__W 1 +#define ORX_EQU_FBF_UPD_W__M 0x1 +#define ORX_EQU_FBF_UPD_W__PRE 0x0 +#define ORX_EQU_FBF_UPD_W_NO_UPDATE 0x0 +#define ORX_EQU_FBF_UPD_W_LMS_UPDATE 0x1 + +#define ORX_EQU_FBF_STP_W__A 0x203002D +#define ORX_EQU_FBF_STP_W__W 3 +#define ORX_EQU_FBF_STP_W__M 0x7 +#define ORX_EQU_FBF_STP_W__PRE 0x2 + +#define ORX_EQU_FBF_LEA_W__A 0x203002E +#define ORX_EQU_FBF_LEA_W__W 4 +#define ORX_EQU_FBF_LEA_W__M 0xF +#define ORX_EQU_FBF_LEA_W__PRE 0x4 + +#define ORX_EQU_FBF_RWT_W__A 0x203002F +#define ORX_EQU_FBF_RWT_W__W 2 +#define ORX_EQU_FBF_RWT_W__M 0x3 +#define ORX_EQU_FBF_RWT_W__PRE 0x0 + +#define ORX_EQU_FBF_C0RE_RW__A 0x2030030 +#define ORX_EQU_FBF_C0RE_RW__W 12 +#define ORX_EQU_FBF_C0RE_RW__M 0xFFF +#define ORX_EQU_FBF_C0RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C0IM_RW__A 0x2030031 +#define ORX_EQU_FBF_C0IM_RW__W 12 +#define ORX_EQU_FBF_C0IM_RW__M 0xFFF +#define ORX_EQU_FBF_C0IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C1RE_RW__A 0x2030032 +#define ORX_EQU_FBF_C1RE_RW__W 12 +#define ORX_EQU_FBF_C1RE_RW__M 0xFFF +#define ORX_EQU_FBF_C1RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C1IM_RW__A 0x2030033 +#define ORX_EQU_FBF_C1IM_RW__W 12 +#define ORX_EQU_FBF_C1IM_RW__M 0xFFF +#define ORX_EQU_FBF_C1IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C2RE_RW__A 0x2030034 +#define ORX_EQU_FBF_C2RE_RW__W 12 +#define ORX_EQU_FBF_C2RE_RW__M 0xFFF +#define ORX_EQU_FBF_C2RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C2IM_RW__A 0x2030035 +#define ORX_EQU_FBF_C2IM_RW__W 12 +#define ORX_EQU_FBF_C2IM_RW__M 0xFFF +#define ORX_EQU_FBF_C2IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C3RE_RW__A 0x2030036 +#define ORX_EQU_FBF_C3RE_RW__W 12 +#define ORX_EQU_FBF_C3RE_RW__M 0xFFF +#define ORX_EQU_FBF_C3RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C3IM_RW__A 0x2030037 +#define ORX_EQU_FBF_C3IM_RW__W 12 +#define ORX_EQU_FBF_C3IM_RW__M 0xFFF +#define ORX_EQU_FBF_C3IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C4RE_RW__A 0x2030038 +#define ORX_EQU_FBF_C4RE_RW__W 12 +#define ORX_EQU_FBF_C4RE_RW__M 0xFFF +#define ORX_EQU_FBF_C4RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C4IM_RW__A 0x2030039 +#define ORX_EQU_FBF_C4IM_RW__W 12 +#define ORX_EQU_FBF_C4IM_RW__M 0xFFF +#define ORX_EQU_FBF_C4IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C5RE_RW__A 0x203003A +#define ORX_EQU_FBF_C5RE_RW__W 12 +#define ORX_EQU_FBF_C5RE_RW__M 0xFFF +#define ORX_EQU_FBF_C5RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C5IM_RW__A 0x203003B +#define ORX_EQU_FBF_C5IM_RW__W 12 +#define ORX_EQU_FBF_C5IM_RW__M 0xFFF +#define ORX_EQU_FBF_C5IM_RW__PRE 0x0 + +#define ORX_EQU_ERR_SEL_W__A 0x203003C +#define ORX_EQU_ERR_SEL_W__W 1 +#define ORX_EQU_ERR_SEL_W__M 0x1 +#define ORX_EQU_ERR_SEL_W__PRE 0x0 +#define ORX_EQU_ERR_SEL_W_CMA_ERROR 0x0 +#define ORX_EQU_ERR_SEL_W_DDA_ERROR 0x1 + +#define ORX_EQU_ERR_TIS_W__A 0x203003D +#define ORX_EQU_ERR_TIS_W__W 1 +#define ORX_EQU_ERR_TIS_W__M 0x1 +#define ORX_EQU_ERR_TIS_W__PRE 0x0 +#define ORX_EQU_ERR_TIS_W_CMA_SIGNALS 0x0 +#define ORX_EQU_ERR_TIS_W_DDA_SIGNALS 0x1 + +#define ORX_EQU_ERR_EDI_R__A 0x203003E +#define ORX_EQU_ERR_EDI_R__W 5 +#define ORX_EQU_ERR_EDI_R__M 0x1F +#define ORX_EQU_ERR_EDI_R__PRE 0xF + +#define ORX_EQU_ERR_EDQ_R__A 0x203003F +#define ORX_EQU_ERR_EDQ_R__W 5 +#define ORX_EQU_ERR_EDQ_R__M 0x1F +#define ORX_EQU_ERR_EDQ_R__PRE 0xF + +#define ORX_EQU_ERR_ECI_R__A 0x2030040 +#define ORX_EQU_ERR_ECI_R__W 5 +#define ORX_EQU_ERR_ECI_R__M 0x1F +#define ORX_EQU_ERR_ECI_R__PRE 0xF + +#define ORX_EQU_ERR_ECQ_R__A 0x2030041 +#define ORX_EQU_ERR_ECQ_R__W 5 +#define ORX_EQU_ERR_ECQ_R__M 0x1F +#define ORX_EQU_ERR_ECQ_R__PRE 0xF + +#define ORX_EQU_MER_MER_R__A 0x2030042 +#define ORX_EQU_MER_MER_R__W 6 +#define ORX_EQU_MER_MER_R__M 0x3F +#define ORX_EQU_MER_MER_R__PRE 0x3F + +#define ORX_EQU_MER_LDT_W__A 0x2030043 +#define ORX_EQU_MER_LDT_W__W 3 +#define ORX_EQU_MER_LDT_W__M 0x7 +#define ORX_EQU_MER_LDT_W__PRE 0x4 + +#define ORX_EQU_SYN_LEN_W__A 0x2030044 +#define ORX_EQU_SYN_LEN_W__W 16 +#define ORX_EQU_SYN_LEN_W__M 0xFFFF +#define ORX_EQU_SYN_LEN_W__PRE 0x0 + +#define ORX_DDC_COMM_EXEC__A 0x2040000 +#define ORX_DDC_COMM_EXEC__W 2 +#define ORX_DDC_COMM_EXEC__M 0x3 +#define ORX_DDC_COMM_EXEC__PRE 0x0 +#define ORX_DDC_COMM_EXEC_STOP 0x0 +#define ORX_DDC_COMM_EXEC_ACTIVE 0x1 +#define ORX_DDC_COMM_EXEC_HOLD 0x2 + +#define ORX_DDC_COMM_MB__A 0x2040002 +#define ORX_DDC_COMM_MB__W 6 +#define ORX_DDC_COMM_MB__M 0x3F +#define ORX_DDC_COMM_MB__PRE 0x0 +#define ORX_DDC_COMM_MB_CTL__B 0 +#define ORX_DDC_COMM_MB_CTL__W 1 +#define ORX_DDC_COMM_MB_CTL__M 0x1 +#define ORX_DDC_COMM_MB_CTL__PRE 0x0 +#define ORX_DDC_COMM_MB_CTL_OFF 0x0 +#define ORX_DDC_COMM_MB_CTL_ON 0x1 +#define ORX_DDC_COMM_MB_OBS__B 1 +#define ORX_DDC_COMM_MB_OBS__W 1 +#define ORX_DDC_COMM_MB_OBS__M 0x2 +#define ORX_DDC_COMM_MB_OBS__PRE 0x0 +#define ORX_DDC_COMM_MB_OBS_OFF 0x0 +#define ORX_DDC_COMM_MB_OBS_ON 0x2 + +#define ORX_DDC_COMM_MB_CTL_MUX__B 2 +#define ORX_DDC_COMM_MB_CTL_MUX__W 2 +#define ORX_DDC_COMM_MB_CTL_MUX__M 0xC +#define ORX_DDC_COMM_MB_CTL_MUX__PRE 0x0 + +#define ORX_DDC_COMM_MB_OBS_MUX__B 4 +#define ORX_DDC_COMM_MB_OBS_MUX__W 2 +#define ORX_DDC_COMM_MB_OBS_MUX__M 0x30 +#define ORX_DDC_COMM_MB_OBS_MUX__PRE 0x0 + +#define ORX_DDC_COMM_INT_REQ__A 0x2040003 +#define ORX_DDC_COMM_INT_REQ__W 1 +#define ORX_DDC_COMM_INT_REQ__M 0x1 +#define ORX_DDC_COMM_INT_REQ__PRE 0x0 +#define ORX_DDC_COMM_INT_STA__A 0x2040005 +#define ORX_DDC_COMM_INT_STA__W 1 +#define ORX_DDC_COMM_INT_STA__M 0x1 +#define ORX_DDC_COMM_INT_STA__PRE 0x0 +#define ORX_DDC_COMM_INT_MSK__A 0x2040006 +#define ORX_DDC_COMM_INT_MSK__W 1 +#define ORX_DDC_COMM_INT_MSK__M 0x1 +#define ORX_DDC_COMM_INT_MSK__PRE 0x0 +#define ORX_DDC_COMM_INT_STM__A 0x2040007 +#define ORX_DDC_COMM_INT_STM__W 1 +#define ORX_DDC_COMM_INT_STM__M 0x1 +#define ORX_DDC_COMM_INT_STM__PRE 0x0 +#define ORX_DDC_DEC_MAP_W__A 0x2040010 +#define ORX_DDC_DEC_MAP_W__W 9 +#define ORX_DDC_DEC_MAP_W__M 0x1FF +#define ORX_DDC_DEC_MAP_W__PRE 0x178 + +#define ORX_DDC_DEC_MAP_W_QUADR0__B 0 +#define ORX_DDC_DEC_MAP_W_QUADR0__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR0__M 0x3 +#define ORX_DDC_DEC_MAP_W_QUADR0__PRE 0x0 +#define ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_DEFAULT 0x0 +#define ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_ALTERNATE 0x0 + +#define ORX_DDC_DEC_MAP_W_QUADR1__B 2 +#define ORX_DDC_DEC_MAP_W_QUADR1__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR1__M 0xC +#define ORX_DDC_DEC_MAP_W_QUADR1__PRE 0x8 +#define ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_DEFAULT 0x8 +#define ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_ALTERNATE 0x4 + +#define ORX_DDC_DEC_MAP_W_QUADR2__B 4 +#define ORX_DDC_DEC_MAP_W_QUADR2__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR2__M 0x30 +#define ORX_DDC_DEC_MAP_W_QUADR2__PRE 0x30 +#define ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_DEFAULT 0x30 +#define ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_ALTERNATE 0x30 + +#define ORX_DDC_DEC_MAP_W_QUADR3__B 6 +#define ORX_DDC_DEC_MAP_W_QUADR3__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR3__M 0xC0 +#define ORX_DDC_DEC_MAP_W_QUADR3__PRE 0x40 +#define ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_DEFAULT 0x40 +#define ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_ALTERNATE 0x80 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__B 8 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__W 1 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__M 0x100 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__PRE 0x100 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD_COHERENT_DECODING 0x0 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD_DIFF_DECODING 0x100 + +#define ORX_DDC_OFO_SET_W__A 0x2040011 +#define ORX_DDC_OFO_SET_W__W 16 +#define ORX_DDC_OFO_SET_W__M 0xFFFF +#define ORX_DDC_OFO_SET_W__PRE 0x1402 + +#define ORX_DDC_OFO_SET_W_PHASE__B 0 +#define ORX_DDC_OFO_SET_W_PHASE__W 7 +#define ORX_DDC_OFO_SET_W_PHASE__M 0x7F +#define ORX_DDC_OFO_SET_W_PHASE__PRE 0x2 + +#define ORX_DDC_OFO_SET_W_CRXHITIME__B 7 +#define ORX_DDC_OFO_SET_W_CRXHITIME__W 7 +#define ORX_DDC_OFO_SET_W_CRXHITIME__M 0x3F80 +#define ORX_DDC_OFO_SET_W_CRXHITIME__PRE 0x1400 + +#define ORX_DDC_OFO_SET_W_CRXINV__B 14 +#define ORX_DDC_OFO_SET_W_CRXINV__W 1 +#define ORX_DDC_OFO_SET_W_CRXINV__M 0x4000 +#define ORX_DDC_OFO_SET_W_CRXINV__PRE 0x0 + +#define ORX_DDC_OFO_SET_W_DISABLE__B 15 +#define ORX_DDC_OFO_SET_W_DISABLE__W 1 +#define ORX_DDC_OFO_SET_W_DISABLE__M 0x8000 +#define ORX_DDC_OFO_SET_W_DISABLE__PRE 0x0 + +#define ORX_CON_COMM_EXEC__A 0x2050000 +#define ORX_CON_COMM_EXEC__W 2 +#define ORX_CON_COMM_EXEC__M 0x3 +#define ORX_CON_COMM_EXEC__PRE 0x0 +#define ORX_CON_COMM_EXEC_STOP 0x0 +#define ORX_CON_COMM_EXEC_ACTIVE 0x1 +#define ORX_CON_COMM_EXEC_HOLD 0x2 + +#define ORX_CON_LDT_W__A 0x2050010 +#define ORX_CON_LDT_W__W 3 +#define ORX_CON_LDT_W__M 0x7 +#define ORX_CON_LDT_W__PRE 0x3 + +#define ORX_CON_LDT_W_CON_LDT_W__B 0 +#define ORX_CON_LDT_W_CON_LDT_W__W 3 +#define ORX_CON_LDT_W_CON_LDT_W__M 0x7 +#define ORX_CON_LDT_W_CON_LDT_W__PRE 0x3 + +#define ORX_CON_RST_W__A 0x2050011 +#define ORX_CON_RST_W__W 4 +#define ORX_CON_RST_W__M 0xF +#define ORX_CON_RST_W__PRE 0x0 + +#define ORX_CON_RST_W_CPH__B 0 +#define ORX_CON_RST_W_CPH__W 1 +#define ORX_CON_RST_W_CPH__M 0x1 +#define ORX_CON_RST_W_CPH__PRE 0x0 + +#define ORX_CON_RST_W_CTI__B 1 +#define ORX_CON_RST_W_CTI__W 1 +#define ORX_CON_RST_W_CTI__M 0x2 +#define ORX_CON_RST_W_CTI__PRE 0x0 + +#define ORX_CON_RST_W_KRN__B 2 +#define ORX_CON_RST_W_KRN__W 1 +#define ORX_CON_RST_W_KRN__M 0x4 +#define ORX_CON_RST_W_KRN__PRE 0x0 + +#define ORX_CON_RST_W_KRP__B 3 +#define ORX_CON_RST_W_KRP__W 1 +#define ORX_CON_RST_W_KRP__M 0x8 +#define ORX_CON_RST_W_KRP__PRE 0x0 + +#define ORX_CON_CPH_PHI_R__A 0x2050012 +#define ORX_CON_CPH_PHI_R__W 16 +#define ORX_CON_CPH_PHI_R__M 0xFFFF +#define ORX_CON_CPH_PHI_R__PRE 0x0 + +#define ORX_CON_CPH_FRQ_R__A 0x2050013 +#define ORX_CON_CPH_FRQ_R__W 16 +#define ORX_CON_CPH_FRQ_R__M 0xFFFF +#define ORX_CON_CPH_FRQ_R__PRE 0x0 + +#define ORX_CON_CPH_AMP_R__A 0x2050014 +#define ORX_CON_CPH_AMP_R__W 16 +#define ORX_CON_CPH_AMP_R__M 0xFFFF +#define ORX_CON_CPH_AMP_R__PRE 0x0 + +#define ORX_CON_CPH_KDF_W__A 0x2050015 +#define ORX_CON_CPH_KDF_W__W 4 +#define ORX_CON_CPH_KDF_W__M 0xF +#define ORX_CON_CPH_KDF_W__PRE 0x0 + +#define ORX_CON_CPH_KPF_W__A 0x2050016 +#define ORX_CON_CPH_KPF_W__W 4 +#define ORX_CON_CPH_KPF_W__M 0xF +#define ORX_CON_CPH_KPF_W__PRE 0x0 + +#define ORX_CON_CPH_KIF_W__A 0x2050017 +#define ORX_CON_CPH_KIF_W__W 4 +#define ORX_CON_CPH_KIF_W__M 0xF +#define ORX_CON_CPH_KIF_W__PRE 0x0 +#define ORX_CON_CPH_APT_W__A 0x2050018 +#define ORX_CON_CPH_APT_W__W 16 +#define ORX_CON_CPH_APT_W__M 0xFFFF +#define ORX_CON_CPH_APT_W__PRE 0x804 + +#define ORX_CON_CPH_APT_W_PTH__B 0 +#define ORX_CON_CPH_APT_W_PTH__W 8 +#define ORX_CON_CPH_APT_W_PTH__M 0xFF +#define ORX_CON_CPH_APT_W_PTH__PRE 0x4 + +#define ORX_CON_CPH_APT_W_ATH__B 8 +#define ORX_CON_CPH_APT_W_ATH__W 8 +#define ORX_CON_CPH_APT_W_ATH__M 0xFF00 +#define ORX_CON_CPH_APT_W_ATH__PRE 0x800 + +#define ORX_CON_CPH_WLC_W__A 0x2050019 +#define ORX_CON_CPH_WLC_W__W 8 +#define ORX_CON_CPH_WLC_W__M 0xFF +#define ORX_CON_CPH_WLC_W__PRE 0x81 + +#define ORX_CON_CPH_WLC_W_LATC__B 0 +#define ORX_CON_CPH_WLC_W_LATC__W 4 +#define ORX_CON_CPH_WLC_W_LATC__M 0xF +#define ORX_CON_CPH_WLC_W_LATC__PRE 0x1 + +#define ORX_CON_CPH_WLC_W_WLIM__B 4 +#define ORX_CON_CPH_WLC_W_WLIM__W 4 +#define ORX_CON_CPH_WLC_W_WLIM__M 0xF0 +#define ORX_CON_CPH_WLC_W_WLIM__PRE 0x80 + +#define ORX_CON_CPH_DLY_W__A 0x205001A +#define ORX_CON_CPH_DLY_W__W 3 +#define ORX_CON_CPH_DLY_W__M 0x7 +#define ORX_CON_CPH_DLY_W__PRE 0x4 + +#define ORX_CON_CPH_TCL_W__A 0x205001B +#define ORX_CON_CPH_TCL_W__W 3 +#define ORX_CON_CPH_TCL_W__M 0x7 +#define ORX_CON_CPH_TCL_W__PRE 0x3 + +#define ORX_CON_KRP_AMP_R__A 0x205001C +#define ORX_CON_KRP_AMP_R__W 9 +#define ORX_CON_KRP_AMP_R__M 0x1FF +#define ORX_CON_KRP_AMP_R__PRE 0x0 + +#define ORX_CON_KRN_AMP_R__A 0x205001D +#define ORX_CON_KRN_AMP_R__W 9 +#define ORX_CON_KRN_AMP_R__M 0x1FF +#define ORX_CON_KRN_AMP_R__PRE 0x0 + +#define ORX_CON_CTI_DTI_R__A 0x205001E +#define ORX_CON_CTI_DTI_R__W 16 +#define ORX_CON_CTI_DTI_R__M 0xFFFF +#define ORX_CON_CTI_DTI_R__PRE 0x0 + +#define ORX_CON_CTI_KDT_W__A 0x205001F +#define ORX_CON_CTI_KDT_W__W 4 +#define ORX_CON_CTI_KDT_W__M 0xF +#define ORX_CON_CTI_KDT_W__PRE 0x4 + +#define ORX_CON_CTI_KPT_W__A 0x2050020 +#define ORX_CON_CTI_KPT_W__W 4 +#define ORX_CON_CTI_KPT_W__M 0xF +#define ORX_CON_CTI_KPT_W__PRE 0x3 + +#define ORX_CON_CTI_KIT_W__A 0x2050021 +#define ORX_CON_CTI_KIT_W__W 4 +#define ORX_CON_CTI_KIT_W__M 0xF +#define ORX_CON_CTI_KIT_W__PRE 0xB + +#define ORX_CON_CTI_TAT_W__A 0x2050022 +#define ORX_CON_CTI_TAT_W__W 4 +#define ORX_CON_CTI_TAT_W__M 0xF +#define ORX_CON_CTI_TAT_W__PRE 0x3 + +#define ORX_NSU_COMM_EXEC__A 0x2060000 +#define ORX_NSU_COMM_EXEC__W 2 +#define ORX_NSU_COMM_EXEC__M 0x3 +#define ORX_NSU_COMM_EXEC__PRE 0x0 +#define ORX_NSU_COMM_EXEC_STOP 0x0 +#define ORX_NSU_COMM_EXEC_ACTIVE 0x1 +#define ORX_NSU_COMM_EXEC_HOLD 0x2 + +#define ORX_NSU_AOX_STDBY_W__A 0x2060010 +#define ORX_NSU_AOX_STDBY_W__W 8 +#define ORX_NSU_AOX_STDBY_W__M 0xFF +#define ORX_NSU_AOX_STDBY_W__PRE 0x0 + +#define ORX_NSU_AOX_STDBY_W_STDBYADC__B 0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYADC__M 0x1 +#define ORX_NSU_AOX_STDBY_W_STDBYADC__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A1_OFF 0x1 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON 0x1 + +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__B 1 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__M 0x2 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_OFF 0x2 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON 0x2 + +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__B 2 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__M 0x4 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_OFF 0x4 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON 0x4 + +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__B 3 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__M 0x8 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_OFF 0x8 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON 0x8 + +#define ORX_NSU_AOX_STDBY_W_STDBYPD__B 4 +#define ORX_NSU_AOX_STDBY_W_STDBYPD__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYPD__M 0x10 +#define ORX_NSU_AOX_STDBY_W_STDBYPD__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A1_OFF 0x10 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON 0x10 + +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__B 5 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__M 0x20 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_OFF 0x20 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON 0x20 + +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__B 6 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__M 0x40 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_OFF 0x40 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON 0x40 + +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__B 7 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__M 0x80 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_OFF 0x80 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON 0x80 + +#define ORX_NSU_AOX_LOFRQ_W__A 0x2060011 +#define ORX_NSU_AOX_LOFRQ_W__W 16 +#define ORX_NSU_AOX_LOFRQ_W__M 0xFFFF +#define ORX_NSU_AOX_LOFRQ_W__PRE 0x0 +#define ORX_NSU_AOX_LOMDE_W__A 0x2060012 +#define ORX_NSU_AOX_LOMDE_W__W 16 +#define ORX_NSU_AOX_LOMDE_W__M 0xFFFF +#define ORX_NSU_AOX_LOMDE_W__PRE 0x0 + +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__B 0 +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__W 8 +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__M 0xFF +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__PRE 0x0 + +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__B 13 +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__W 1 +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__M 0x2000 +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__PRE 0x0 + +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__B 14 +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__W 2 +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__M 0xC000 +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__PRE 0x0 + +#define ORX_NSU_AOX_LOPOW_W__A 0x2060013 +#define ORX_NSU_AOX_LOPOW_W__W 2 +#define ORX_NSU_AOX_LOPOW_W__M 0x3 +#define ORX_NSU_AOX_LOPOW_W__PRE 0x0 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS0DB 0x0 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS5DB 0x1 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS10DB 0x2 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS15DB 0x3 + +#define ORX_NSU_AOX_STHR_W__A 0x2060014 +#define ORX_NSU_AOX_STHR_W__W 5 +#define ORX_NSU_AOX_STHR_W__M 0x1F +#define ORX_NSU_AOX_STHR_W__PRE 0x0 + +#define ORX_NSU_TUN_RFGAIN_W__A 0x2060015 +#define ORX_NSU_TUN_RFGAIN_W__W 15 +#define ORX_NSU_TUN_RFGAIN_W__M 0x7FFF +#define ORX_NSU_TUN_RFGAIN_W__PRE 0x0 + +#define ORX_NSU_TUN_IFGAIN_W__A 0x2060016 +#define ORX_NSU_TUN_IFGAIN_W__W 15 +#define ORX_NSU_TUN_IFGAIN_W__M 0x7FFF +#define ORX_NSU_TUN_IFGAIN_W__PRE 0x0 + +#define ORX_NSU_TUN_BPF_W__A 0x2060017 +#define ORX_NSU_TUN_BPF_W__W 15 +#define ORX_NSU_TUN_BPF_W__M 0x7FFF +#define ORX_NSU_TUN_BPF_W__PRE 0x1F9 +#define ORX_NSU_NSS_BITSWAP_W__A 0x2060018 +#define ORX_NSU_NSS_BITSWAP_W__W 3 +#define ORX_NSU_NSS_BITSWAP_W__M 0x7 +#define ORX_NSU_NSS_BITSWAP_W__PRE 0x0 + +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__B 0 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__W 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__M 0x1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__PRE 0x0 + +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__B 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__W 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__M 0x2 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__PRE 0x0 + +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__B 2 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__W 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__M 0x4 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__PRE 0x0 + +#define ORX_TST_COMM_EXEC__A 0x23F0000 +#define ORX_TST_COMM_EXEC__W 2 +#define ORX_TST_COMM_EXEC__M 0x3 +#define ORX_TST_COMM_EXEC__PRE 0x0 +#define ORX_TST_COMM_EXEC_STOP 0x0 +#define ORX_TST_COMM_EXEC_ACTIVE 0x1 +#define ORX_TST_COMM_EXEC_HOLD 0x2 + +#define ORX_TST_AOX_TST_W__A 0x23F0010 +#define ORX_TST_AOX_TST_W__W 8 +#define ORX_TST_AOX_TST_W__M 0xFF +#define ORX_TST_AOX_TST_W__PRE 0x0 + +#define QAM_COMM_EXEC__A 0x1400000 +#define QAM_COMM_EXEC__W 2 +#define QAM_COMM_EXEC__M 0x3 +#define QAM_COMM_EXEC__PRE 0x0 +#define QAM_COMM_EXEC_STOP 0x0 +#define QAM_COMM_EXEC_ACTIVE 0x1 +#define QAM_COMM_EXEC_HOLD 0x2 + +#define QAM_COMM_MB__A 0x1400002 +#define QAM_COMM_MB__W 16 +#define QAM_COMM_MB__M 0xFFFF +#define QAM_COMM_MB__PRE 0x0 +#define QAM_COMM_INT_REQ__A 0x1400003 +#define QAM_COMM_INT_REQ__W 16 +#define QAM_COMM_INT_REQ__M 0xFFFF +#define QAM_COMM_INT_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SL_REQ__B 0 +#define QAM_COMM_INT_REQ_SL_REQ__W 1 +#define QAM_COMM_INT_REQ_SL_REQ__M 0x1 +#define QAM_COMM_INT_REQ_SL_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_LC_REQ__B 1 +#define QAM_COMM_INT_REQ_LC_REQ__W 1 +#define QAM_COMM_INT_REQ_LC_REQ__M 0x2 +#define QAM_COMM_INT_REQ_LC_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_VD_REQ__B 2 +#define QAM_COMM_INT_REQ_VD_REQ__W 1 +#define QAM_COMM_INT_REQ_VD_REQ__M 0x4 +#define QAM_COMM_INT_REQ_VD_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SY_REQ__B 3 +#define QAM_COMM_INT_REQ_SY_REQ__W 1 +#define QAM_COMM_INT_REQ_SY_REQ__M 0x8 +#define QAM_COMM_INT_REQ_SY_REQ__PRE 0x0 + +#define QAM_COMM_INT_STA__A 0x1400005 +#define QAM_COMM_INT_STA__W 16 +#define QAM_COMM_INT_STA__M 0xFFFF +#define QAM_COMM_INT_STA__PRE 0x0 +#define QAM_COMM_INT_MSK__A 0x1400006 +#define QAM_COMM_INT_MSK__W 16 +#define QAM_COMM_INT_MSK__M 0xFFFF +#define QAM_COMM_INT_MSK__PRE 0x0 +#define QAM_COMM_INT_STM__A 0x1400007 +#define QAM_COMM_INT_STM__W 16 +#define QAM_COMM_INT_STM__M 0xFFFF +#define QAM_COMM_INT_STM__PRE 0x0 + +#define QAM_TOP_COMM_EXEC__A 0x1410000 +#define QAM_TOP_COMM_EXEC__W 2 +#define QAM_TOP_COMM_EXEC__M 0x3 +#define QAM_TOP_COMM_EXEC__PRE 0x0 +#define QAM_TOP_COMM_EXEC_STOP 0x0 +#define QAM_TOP_COMM_EXEC_ACTIVE 0x1 +#define QAM_TOP_COMM_EXEC_HOLD 0x2 + +#define QAM_TOP_ANNEX__A 0x1410010 +#define QAM_TOP_ANNEX__W 2 +#define QAM_TOP_ANNEX__M 0x3 +#define QAM_TOP_ANNEX__PRE 0x1 +#define QAM_TOP_ANNEX_A 0x0 +#define QAM_TOP_ANNEX_B 0x1 +#define QAM_TOP_ANNEX_C 0x2 +#define QAM_TOP_ANNEX_D 0x3 + +#define QAM_TOP_CONSTELLATION__A 0x1410011 +#define QAM_TOP_CONSTELLATION__W 3 +#define QAM_TOP_CONSTELLATION__M 0x7 +#define QAM_TOP_CONSTELLATION__PRE 0x5 +#define QAM_TOP_CONSTELLATION_NONE 0x0 +#define QAM_TOP_CONSTELLATION_QPSK 0x1 +#define QAM_TOP_CONSTELLATION_QAM8 0x2 +#define QAM_TOP_CONSTELLATION_QAM16 0x3 +#define QAM_TOP_CONSTELLATION_QAM32 0x4 +#define QAM_TOP_CONSTELLATION_QAM64 0x5 +#define QAM_TOP_CONSTELLATION_QAM128 0x6 +#define QAM_TOP_CONSTELLATION_QAM256 0x7 + +#define QAM_FQ_COMM_EXEC__A 0x1420000 +#define QAM_FQ_COMM_EXEC__W 2 +#define QAM_FQ_COMM_EXEC__M 0x3 +#define QAM_FQ_COMM_EXEC__PRE 0x0 +#define QAM_FQ_COMM_EXEC_STOP 0x0 +#define QAM_FQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_FQ_COMM_EXEC_HOLD 0x2 + +#define QAM_FQ_MODE__A 0x1420010 +#define QAM_FQ_MODE__W 3 +#define QAM_FQ_MODE__M 0x7 +#define QAM_FQ_MODE__PRE 0x0 + +#define QAM_FQ_MODE_TAPRESET__B 0 +#define QAM_FQ_MODE_TAPRESET__W 1 +#define QAM_FQ_MODE_TAPRESET__M 0x1 +#define QAM_FQ_MODE_TAPRESET__PRE 0x0 +#define QAM_FQ_MODE_TAPRESET_RST 0x1 + +#define QAM_FQ_MODE_TAPLMS__B 1 +#define QAM_FQ_MODE_TAPLMS__W 1 +#define QAM_FQ_MODE_TAPLMS__M 0x2 +#define QAM_FQ_MODE_TAPLMS__PRE 0x0 +#define QAM_FQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_FQ_MODE_TAPDRAIN__B 2 +#define QAM_FQ_MODE_TAPDRAIN__W 1 +#define QAM_FQ_MODE_TAPDRAIN__M 0x4 +#define QAM_FQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4 + +#define QAM_FQ_MU_FACTOR__A 0x1420011 +#define QAM_FQ_MU_FACTOR__W 3 +#define QAM_FQ_MU_FACTOR__M 0x7 +#define QAM_FQ_MU_FACTOR__PRE 0x0 + +#define QAM_FQ_LA_FACTOR__A 0x1420012 +#define QAM_FQ_LA_FACTOR__W 4 +#define QAM_FQ_LA_FACTOR__M 0xF +#define QAM_FQ_LA_FACTOR__PRE 0xC +#define QAM_FQ_CENTTAP_IDX__A 0x1420016 +#define QAM_FQ_CENTTAP_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_IDX_IDX__B 0 +#define QAM_FQ_CENTTAP_IDX_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_VALUE__A 0x1420017 +#define QAM_FQ_CENTTAP_VALUE__W 12 +#define QAM_FQ_CENTTAP_VALUE__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE__PRE 0x600 + +#define QAM_FQ_CENTTAP_VALUE_TAP__B 0 +#define QAM_FQ_CENTTAP_VALUE_TAP__W 12 +#define QAM_FQ_CENTTAP_VALUE_TAP__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL0__A 0x1420020 +#define QAM_FQ_TAP_RE_EL0__W 12 +#define QAM_FQ_TAP_RE_EL0__M 0xFFF +#define QAM_FQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL0_TAP__B 0 +#define QAM_FQ_TAP_RE_EL0_TAP__W 12 +#define QAM_FQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0__A 0x1420021 +#define QAM_FQ_TAP_IM_EL0__W 12 +#define QAM_FQ_TAP_IM_EL0__M 0xFFF +#define QAM_FQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0_TAP__B 0 +#define QAM_FQ_TAP_IM_EL0_TAP__W 12 +#define QAM_FQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1__A 0x1420022 +#define QAM_FQ_TAP_RE_EL1__W 12 +#define QAM_FQ_TAP_RE_EL1__M 0xFFF +#define QAM_FQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1_TAP__B 0 +#define QAM_FQ_TAP_RE_EL1_TAP__W 12 +#define QAM_FQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1__A 0x1420023 +#define QAM_FQ_TAP_IM_EL1__W 12 +#define QAM_FQ_TAP_IM_EL1__M 0xFFF +#define QAM_FQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1_TAP__B 0 +#define QAM_FQ_TAP_IM_EL1_TAP__W 12 +#define QAM_FQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2__A 0x1420024 +#define QAM_FQ_TAP_RE_EL2__W 12 +#define QAM_FQ_TAP_RE_EL2__M 0xFFF +#define QAM_FQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2_TAP__B 0 +#define QAM_FQ_TAP_RE_EL2_TAP__W 12 +#define QAM_FQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2__A 0x1420025 +#define QAM_FQ_TAP_IM_EL2__W 12 +#define QAM_FQ_TAP_IM_EL2__M 0xFFF +#define QAM_FQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2_TAP__B 0 +#define QAM_FQ_TAP_IM_EL2_TAP__W 12 +#define QAM_FQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3__A 0x1420026 +#define QAM_FQ_TAP_RE_EL3__W 12 +#define QAM_FQ_TAP_RE_EL3__M 0xFFF +#define QAM_FQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3_TAP__B 0 +#define QAM_FQ_TAP_RE_EL3_TAP__W 12 +#define QAM_FQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3__A 0x1420027 +#define QAM_FQ_TAP_IM_EL3__W 12 +#define QAM_FQ_TAP_IM_EL3__M 0xFFF +#define QAM_FQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3_TAP__B 0 +#define QAM_FQ_TAP_IM_EL3_TAP__W 12 +#define QAM_FQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4__A 0x1420028 +#define QAM_FQ_TAP_RE_EL4__W 12 +#define QAM_FQ_TAP_RE_EL4__M 0xFFF +#define QAM_FQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4_TAP__B 0 +#define QAM_FQ_TAP_RE_EL4_TAP__W 12 +#define QAM_FQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4__A 0x1420029 +#define QAM_FQ_TAP_IM_EL4__W 12 +#define QAM_FQ_TAP_IM_EL4__M 0xFFF +#define QAM_FQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4_TAP__B 0 +#define QAM_FQ_TAP_IM_EL4_TAP__W 12 +#define QAM_FQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5__A 0x142002A +#define QAM_FQ_TAP_RE_EL5__W 12 +#define QAM_FQ_TAP_RE_EL5__M 0xFFF +#define QAM_FQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5_TAP__B 0 +#define QAM_FQ_TAP_RE_EL5_TAP__W 12 +#define QAM_FQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5__A 0x142002B +#define QAM_FQ_TAP_IM_EL5__W 12 +#define QAM_FQ_TAP_IM_EL5__M 0xFFF +#define QAM_FQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5_TAP__B 0 +#define QAM_FQ_TAP_IM_EL5_TAP__W 12 +#define QAM_FQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6__A 0x142002C +#define QAM_FQ_TAP_RE_EL6__W 12 +#define QAM_FQ_TAP_RE_EL6__M 0xFFF +#define QAM_FQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6_TAP__B 0 +#define QAM_FQ_TAP_RE_EL6_TAP__W 12 +#define QAM_FQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6__A 0x142002D +#define QAM_FQ_TAP_IM_EL6__W 12 +#define QAM_FQ_TAP_IM_EL6__M 0xFFF +#define QAM_FQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6_TAP__B 0 +#define QAM_FQ_TAP_IM_EL6_TAP__W 12 +#define QAM_FQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7__A 0x142002E +#define QAM_FQ_TAP_RE_EL7__W 12 +#define QAM_FQ_TAP_RE_EL7__M 0xFFF +#define QAM_FQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7_TAP__B 0 +#define QAM_FQ_TAP_RE_EL7_TAP__W 12 +#define QAM_FQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7__A 0x142002F +#define QAM_FQ_TAP_IM_EL7__W 12 +#define QAM_FQ_TAP_IM_EL7__M 0xFFF +#define QAM_FQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7_TAP__B 0 +#define QAM_FQ_TAP_IM_EL7_TAP__W 12 +#define QAM_FQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8__A 0x1420030 +#define QAM_FQ_TAP_RE_EL8__W 12 +#define QAM_FQ_TAP_RE_EL8__M 0xFFF +#define QAM_FQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8_TAP__B 0 +#define QAM_FQ_TAP_RE_EL8_TAP__W 12 +#define QAM_FQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8__A 0x1420031 +#define QAM_FQ_TAP_IM_EL8__W 12 +#define QAM_FQ_TAP_IM_EL8__M 0xFFF +#define QAM_FQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8_TAP__B 0 +#define QAM_FQ_TAP_IM_EL8_TAP__W 12 +#define QAM_FQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9__A 0x1420032 +#define QAM_FQ_TAP_RE_EL9__W 12 +#define QAM_FQ_TAP_RE_EL9__M 0xFFF +#define QAM_FQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9_TAP__B 0 +#define QAM_FQ_TAP_RE_EL9_TAP__W 12 +#define QAM_FQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9__A 0x1420033 +#define QAM_FQ_TAP_IM_EL9__W 12 +#define QAM_FQ_TAP_IM_EL9__M 0xFFF +#define QAM_FQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9_TAP__B 0 +#define QAM_FQ_TAP_IM_EL9_TAP__W 12 +#define QAM_FQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10__A 0x1420034 +#define QAM_FQ_TAP_RE_EL10__W 12 +#define QAM_FQ_TAP_RE_EL10__M 0xFFF +#define QAM_FQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10_TAP__B 0 +#define QAM_FQ_TAP_RE_EL10_TAP__W 12 +#define QAM_FQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10__A 0x1420035 +#define QAM_FQ_TAP_IM_EL10__W 12 +#define QAM_FQ_TAP_IM_EL10__M 0xFFF +#define QAM_FQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10_TAP__B 0 +#define QAM_FQ_TAP_IM_EL10_TAP__W 12 +#define QAM_FQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11__A 0x1420036 +#define QAM_FQ_TAP_RE_EL11__W 12 +#define QAM_FQ_TAP_RE_EL11__M 0xFFF +#define QAM_FQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11_TAP__B 0 +#define QAM_FQ_TAP_RE_EL11_TAP__W 12 +#define QAM_FQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11__A 0x1420037 +#define QAM_FQ_TAP_IM_EL11__W 12 +#define QAM_FQ_TAP_IM_EL11__M 0xFFF +#define QAM_FQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11_TAP__B 0 +#define QAM_FQ_TAP_IM_EL11_TAP__W 12 +#define QAM_FQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12__A 0x1420038 +#define QAM_FQ_TAP_RE_EL12__W 12 +#define QAM_FQ_TAP_RE_EL12__M 0xFFF +#define QAM_FQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12_TAP__B 0 +#define QAM_FQ_TAP_RE_EL12_TAP__W 12 +#define QAM_FQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12__A 0x1420039 +#define QAM_FQ_TAP_IM_EL12__W 12 +#define QAM_FQ_TAP_IM_EL12__M 0xFFF +#define QAM_FQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12_TAP__B 0 +#define QAM_FQ_TAP_IM_EL12_TAP__W 12 +#define QAM_FQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13__A 0x142003A +#define QAM_FQ_TAP_RE_EL13__W 12 +#define QAM_FQ_TAP_RE_EL13__M 0xFFF +#define QAM_FQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13_TAP__B 0 +#define QAM_FQ_TAP_RE_EL13_TAP__W 12 +#define QAM_FQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13__A 0x142003B +#define QAM_FQ_TAP_IM_EL13__W 12 +#define QAM_FQ_TAP_IM_EL13__M 0xFFF +#define QAM_FQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13_TAP__B 0 +#define QAM_FQ_TAP_IM_EL13_TAP__W 12 +#define QAM_FQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14__A 0x142003C +#define QAM_FQ_TAP_RE_EL14__W 12 +#define QAM_FQ_TAP_RE_EL14__M 0xFFF +#define QAM_FQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14_TAP__B 0 +#define QAM_FQ_TAP_RE_EL14_TAP__W 12 +#define QAM_FQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14__A 0x142003D +#define QAM_FQ_TAP_IM_EL14__W 12 +#define QAM_FQ_TAP_IM_EL14__M 0xFFF +#define QAM_FQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14_TAP__B 0 +#define QAM_FQ_TAP_IM_EL14_TAP__W 12 +#define QAM_FQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15__A 0x142003E +#define QAM_FQ_TAP_RE_EL15__W 12 +#define QAM_FQ_TAP_RE_EL15__M 0xFFF +#define QAM_FQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15_TAP__B 0 +#define QAM_FQ_TAP_RE_EL15_TAP__W 12 +#define QAM_FQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15__A 0x142003F +#define QAM_FQ_TAP_IM_EL15__W 12 +#define QAM_FQ_TAP_IM_EL15__M 0xFFF +#define QAM_FQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15_TAP__B 0 +#define QAM_FQ_TAP_IM_EL15_TAP__W 12 +#define QAM_FQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16__A 0x1420040 +#define QAM_FQ_TAP_RE_EL16__W 12 +#define QAM_FQ_TAP_RE_EL16__M 0xFFF +#define QAM_FQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16_TAP__B 0 +#define QAM_FQ_TAP_RE_EL16_TAP__W 12 +#define QAM_FQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16__A 0x1420041 +#define QAM_FQ_TAP_IM_EL16__W 12 +#define QAM_FQ_TAP_IM_EL16__M 0xFFF +#define QAM_FQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16_TAP__B 0 +#define QAM_FQ_TAP_IM_EL16_TAP__W 12 +#define QAM_FQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17__A 0x1420042 +#define QAM_FQ_TAP_RE_EL17__W 12 +#define QAM_FQ_TAP_RE_EL17__M 0xFFF +#define QAM_FQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17_TAP__B 0 +#define QAM_FQ_TAP_RE_EL17_TAP__W 12 +#define QAM_FQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17__A 0x1420043 +#define QAM_FQ_TAP_IM_EL17__W 12 +#define QAM_FQ_TAP_IM_EL17__M 0xFFF +#define QAM_FQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17_TAP__B 0 +#define QAM_FQ_TAP_IM_EL17_TAP__W 12 +#define QAM_FQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18__A 0x1420044 +#define QAM_FQ_TAP_RE_EL18__W 12 +#define QAM_FQ_TAP_RE_EL18__M 0xFFF +#define QAM_FQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18_TAP__B 0 +#define QAM_FQ_TAP_RE_EL18_TAP__W 12 +#define QAM_FQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18__A 0x1420045 +#define QAM_FQ_TAP_IM_EL18__W 12 +#define QAM_FQ_TAP_IM_EL18__M 0xFFF +#define QAM_FQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18_TAP__B 0 +#define QAM_FQ_TAP_IM_EL18_TAP__W 12 +#define QAM_FQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL19__A 0x1420046 +#define QAM_FQ_TAP_RE_EL19__W 12 +#define QAM_FQ_TAP_RE_EL19__M 0xFFF +#define QAM_FQ_TAP_RE_EL19__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL19_TAP__B 0 +#define QAM_FQ_TAP_RE_EL19_TAP__W 12 +#define QAM_FQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0x600 + +#define QAM_FQ_TAP_IM_EL19__A 0x1420047 +#define QAM_FQ_TAP_IM_EL19__W 12 +#define QAM_FQ_TAP_IM_EL19__M 0xFFF +#define QAM_FQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL19_TAP__B 0 +#define QAM_FQ_TAP_IM_EL19_TAP__W 12 +#define QAM_FQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20__A 0x1420048 +#define QAM_FQ_TAP_RE_EL20__W 12 +#define QAM_FQ_TAP_RE_EL20__M 0xFFF +#define QAM_FQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20_TAP__B 0 +#define QAM_FQ_TAP_RE_EL20_TAP__W 12 +#define QAM_FQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20__A 0x1420049 +#define QAM_FQ_TAP_IM_EL20__W 12 +#define QAM_FQ_TAP_IM_EL20__M 0xFFF +#define QAM_FQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20_TAP__B 0 +#define QAM_FQ_TAP_IM_EL20_TAP__W 12 +#define QAM_FQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21__A 0x142004A +#define QAM_FQ_TAP_RE_EL21__W 12 +#define QAM_FQ_TAP_RE_EL21__M 0xFFF +#define QAM_FQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21_TAP__B 0 +#define QAM_FQ_TAP_RE_EL21_TAP__W 12 +#define QAM_FQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21__A 0x142004B +#define QAM_FQ_TAP_IM_EL21__W 12 +#define QAM_FQ_TAP_IM_EL21__M 0xFFF +#define QAM_FQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21_TAP__B 0 +#define QAM_FQ_TAP_IM_EL21_TAP__W 12 +#define QAM_FQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22__A 0x142004C +#define QAM_FQ_TAP_RE_EL22__W 12 +#define QAM_FQ_TAP_RE_EL22__M 0xFFF +#define QAM_FQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22_TAP__B 0 +#define QAM_FQ_TAP_RE_EL22_TAP__W 12 +#define QAM_FQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22__A 0x142004D +#define QAM_FQ_TAP_IM_EL22__W 12 +#define QAM_FQ_TAP_IM_EL22__M 0xFFF +#define QAM_FQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22_TAP__B 0 +#define QAM_FQ_TAP_IM_EL22_TAP__W 12 +#define QAM_FQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23__A 0x142004E +#define QAM_FQ_TAP_RE_EL23__W 12 +#define QAM_FQ_TAP_RE_EL23__M 0xFFF +#define QAM_FQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23_TAP__B 0 +#define QAM_FQ_TAP_RE_EL23_TAP__W 12 +#define QAM_FQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23__A 0x142004F +#define QAM_FQ_TAP_IM_EL23__W 12 +#define QAM_FQ_TAP_IM_EL23__M 0xFFF +#define QAM_FQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23_TAP__B 0 +#define QAM_FQ_TAP_IM_EL23_TAP__W 12 +#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2 + +#define QAM_SL_COMM_EXEC__A 0x1430000 +#define QAM_SL_COMM_EXEC__W 2 +#define QAM_SL_COMM_EXEC__M 0x3 +#define QAM_SL_COMM_EXEC__PRE 0x0 +#define QAM_SL_COMM_EXEC_STOP 0x0 +#define QAM_SL_COMM_EXEC_ACTIVE 0x1 +#define QAM_SL_COMM_EXEC_HOLD 0x2 + +#define QAM_SL_COMM_MB__A 0x1430002 +#define QAM_SL_COMM_MB__W 4 +#define QAM_SL_COMM_MB__M 0xF +#define QAM_SL_COMM_MB__PRE 0x0 +#define QAM_SL_COMM_MB_CTL__B 0 +#define QAM_SL_COMM_MB_CTL__W 1 +#define QAM_SL_COMM_MB_CTL__M 0x1 +#define QAM_SL_COMM_MB_CTL__PRE 0x0 +#define QAM_SL_COMM_MB_CTL_OFF 0x0 +#define QAM_SL_COMM_MB_CTL_ON 0x1 +#define QAM_SL_COMM_MB_OBS__B 1 +#define QAM_SL_COMM_MB_OBS__W 1 +#define QAM_SL_COMM_MB_OBS__M 0x2 +#define QAM_SL_COMM_MB_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_OBS_OFF 0x0 +#define QAM_SL_COMM_MB_OBS_ON 0x2 +#define QAM_SL_COMM_MB_MUX_OBS__B 2 +#define QAM_SL_COMM_MB_MUX_OBS__W 2 +#define QAM_SL_COMM_MB_MUX_OBS__M 0xC +#define QAM_SL_COMM_MB_MUX_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0x4 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0x8 +#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0xC + +#define QAM_SL_COMM_INT_REQ__A 0x1430003 +#define QAM_SL_COMM_INT_REQ__W 1 +#define QAM_SL_COMM_INT_REQ__M 0x1 +#define QAM_SL_COMM_INT_REQ__PRE 0x0 +#define QAM_SL_COMM_INT_STA__A 0x1430005 +#define QAM_SL_COMM_INT_STA__W 2 +#define QAM_SL_COMM_INT_STA__M 0x3 +#define QAM_SL_COMM_INT_STA__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 0 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0x1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MER_INT__B 1 +#define QAM_SL_COMM_INT_STA_MER_INT__W 1 +#define QAM_SL_COMM_INT_STA_MER_INT__M 0x2 +#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_MSK__A 0x1430006 +#define QAM_SL_COMM_INT_MSK__W 2 +#define QAM_SL_COMM_INT_MSK__M 0x3 +#define QAM_SL_COMM_INT_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0x1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MER_MSK__B 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x2 +#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0x0 + +#define QAM_SL_COMM_INT_STM__A 0x1430007 +#define QAM_SL_COMM_INT_STM__W 2 +#define QAM_SL_COMM_INT_STM__M 0x3 +#define QAM_SL_COMM_INT_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0x1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MER_STM__B 1 +#define QAM_SL_COMM_INT_STM_MER_STM__W 1 +#define QAM_SL_COMM_INT_STM_MER_STM__M 0x2 +#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0x0 + +#define QAM_SL_MODE__A 0x1430010 +#define QAM_SL_MODE__W 11 +#define QAM_SL_MODE__M 0x7FF +#define QAM_SL_MODE__PRE 0x0 + +#define QAM_SL_MODE_SLICER4LC__B 0 +#define QAM_SL_MODE_SLICER4LC__W 2 +#define QAM_SL_MODE_SLICER4LC__M 0x3 +#define QAM_SL_MODE_SLICER4LC__PRE 0x0 +#define QAM_SL_MODE_SLICER4LC_RECT 0x0 +#define QAM_SL_MODE_SLICER4LC_ONET 0x1 +#define QAM_SL_MODE_SLICER4LC_RAD 0x2 + +#define QAM_SL_MODE_SLICER4DQ__B 2 +#define QAM_SL_MODE_SLICER4DQ__W 2 +#define QAM_SL_MODE_SLICER4DQ__M 0xC +#define QAM_SL_MODE_SLICER4DQ__PRE 0x0 +#define QAM_SL_MODE_SLICER4DQ_RECT 0x0 +#define QAM_SL_MODE_SLICER4DQ_ONET 0x4 +#define QAM_SL_MODE_SLICER4DQ_RAD 0x8 + +#define QAM_SL_MODE_SLICER4VD__B 4 +#define QAM_SL_MODE_SLICER4VD__W 2 +#define QAM_SL_MODE_SLICER4VD__M 0x30 +#define QAM_SL_MODE_SLICER4VD__PRE 0x0 +#define QAM_SL_MODE_SLICER4VD_RECT 0x0 +#define QAM_SL_MODE_SLICER4VD_ONET 0x10 +#define QAM_SL_MODE_SLICER4VD_RAD 0x20 + +#define QAM_SL_MODE_ROT_DIS__B 6 +#define QAM_SL_MODE_ROT_DIS__W 1 +#define QAM_SL_MODE_ROT_DIS__M 0x40 +#define QAM_SL_MODE_ROT_DIS__PRE 0x0 + +#define QAM_SL_MODE_DQROT_DIS__B 7 +#define QAM_SL_MODE_DQROT_DIS__W 1 +#define QAM_SL_MODE_DQROT_DIS__M 0x80 +#define QAM_SL_MODE_DQROT_DIS__PRE 0x0 + +#define QAM_SL_MODE_DFE_DIS__B 8 +#define QAM_SL_MODE_DFE_DIS__W 1 +#define QAM_SL_MODE_DFE_DIS__M 0x100 +#define QAM_SL_MODE_DFE_DIS__PRE 0x0 + +#define QAM_SL_MODE_RADIUS_MIX__B 9 +#define QAM_SL_MODE_RADIUS_MIX__W 1 +#define QAM_SL_MODE_RADIUS_MIX__M 0x200 +#define QAM_SL_MODE_RADIUS_MIX__PRE 0x0 + +#define QAM_SL_MODE_TILT_COMP__B 10 +#define QAM_SL_MODE_TILT_COMP__W 1 +#define QAM_SL_MODE_TILT_COMP__M 0x400 +#define QAM_SL_MODE_TILT_COMP__PRE 0x0 + +#define QAM_SL_K_FACTOR__A 0x1430011 +#define QAM_SL_K_FACTOR__W 4 +#define QAM_SL_K_FACTOR__M 0xF +#define QAM_SL_K_FACTOR__PRE 0x0 +#define QAM_SL_MEDIAN__A 0x1430012 +#define QAM_SL_MEDIAN__W 14 +#define QAM_SL_MEDIAN__M 0x3FFF +#define QAM_SL_MEDIAN__PRE 0x0 + +#define QAM_SL_MEDIAN_LENGTH__B 0 +#define QAM_SL_MEDIAN_LENGTH__W 2 +#define QAM_SL_MEDIAN_LENGTH__M 0x3 +#define QAM_SL_MEDIAN_LENGTH__PRE 0x0 + +#define QAM_SL_MEDIAN_CORRECT__B 2 +#define QAM_SL_MEDIAN_CORRECT__W 4 +#define QAM_SL_MEDIAN_CORRECT__M 0x3C +#define QAM_SL_MEDIAN_CORRECT__PRE 0x0 + +#define QAM_SL_MEDIAN_TOLERANCE__B 6 +#define QAM_SL_MEDIAN_TOLERANCE__W 7 +#define QAM_SL_MEDIAN_TOLERANCE__M 0x1FC0 +#define QAM_SL_MEDIAN_TOLERANCE__PRE 0x0 + +#define QAM_SL_MEDIAN_FAST__B 13 +#define QAM_SL_MEDIAN_FAST__W 1 +#define QAM_SL_MEDIAN_FAST__M 0x2000 +#define QAM_SL_MEDIAN_FAST__PRE 0x0 + +#define QAM_SL_ALPHA__A 0x1430013 +#define QAM_SL_ALPHA__W 3 +#define QAM_SL_ALPHA__M 0x7 +#define QAM_SL_ALPHA__PRE 0x0 + +#define QAM_SL_PHASELIMIT__A 0x1430014 +#define QAM_SL_PHASELIMIT__W 9 +#define QAM_SL_PHASELIMIT__M 0x1FF +#define QAM_SL_PHASELIMIT__PRE 0x0 +#define QAM_SL_MTA_LENGTH__A 0x1430015 +#define QAM_SL_MTA_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH__PRE 0x1 + +#define QAM_SL_MTA_LENGTH_LENGTH__B 0 +#define QAM_SL_MTA_LENGTH_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0x1 + +#define QAM_SL_MEDIAN_ERROR__A 0x1430016 +#define QAM_SL_MEDIAN_ERROR__W 10 +#define QAM_SL_MEDIAN_ERROR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR__PRE 0x0 + +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 0 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 10 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0 + +#define QAM_SL_ERR_POWER__A 0x1430017 +#define QAM_SL_ERR_POWER__W 16 +#define QAM_SL_ERR_POWER__M 0xFFFF +#define QAM_SL_ERR_POWER__PRE 0x0 + +#define QAM_DQ_COMM_EXEC__A 0x1440000 +#define QAM_DQ_COMM_EXEC__W 2 +#define QAM_DQ_COMM_EXEC__M 0x3 +#define QAM_DQ_COMM_EXEC__PRE 0x0 +#define QAM_DQ_COMM_EXEC_STOP 0x0 +#define QAM_DQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_DQ_COMM_EXEC_HOLD 0x2 + +#define QAM_DQ_MODE__A 0x1440010 +#define QAM_DQ_MODE__W 5 +#define QAM_DQ_MODE__M 0x1F +#define QAM_DQ_MODE__PRE 0x0 + +#define QAM_DQ_MODE_TAPRESET__B 0 +#define QAM_DQ_MODE_TAPRESET__W 1 +#define QAM_DQ_MODE_TAPRESET__M 0x1 +#define QAM_DQ_MODE_TAPRESET__PRE 0x0 +#define QAM_DQ_MODE_TAPRESET_RST 0x1 + +#define QAM_DQ_MODE_TAPLMS__B 1 +#define QAM_DQ_MODE_TAPLMS__W 1 +#define QAM_DQ_MODE_TAPLMS__M 0x2 +#define QAM_DQ_MODE_TAPLMS__PRE 0x0 +#define QAM_DQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_DQ_MODE_TAPDRAIN__B 2 +#define QAM_DQ_MODE_TAPDRAIN__W 1 +#define QAM_DQ_MODE_TAPDRAIN__M 0x4 +#define QAM_DQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0x4 + +#define QAM_DQ_MODE_FB__B 3 +#define QAM_DQ_MODE_FB__W 2 +#define QAM_DQ_MODE_FB__M 0x18 +#define QAM_DQ_MODE_FB__PRE 0x0 +#define QAM_DQ_MODE_FB_CMA 0x0 +#define QAM_DQ_MODE_FB_RADIUS 0x8 +#define QAM_DQ_MODE_FB_DFB 0x10 +#define QAM_DQ_MODE_FB_TRELLIS 0x18 + +#define QAM_DQ_MU_FACTOR__A 0x1440011 +#define QAM_DQ_MU_FACTOR__W 3 +#define QAM_DQ_MU_FACTOR__M 0x7 +#define QAM_DQ_MU_FACTOR__PRE 0x0 + +#define QAM_DQ_LA_FACTOR__A 0x1440012 +#define QAM_DQ_LA_FACTOR__W 4 +#define QAM_DQ_LA_FACTOR__M 0xF +#define QAM_DQ_LA_FACTOR__PRE 0xC + +#define QAM_DQ_CMA_RATIO__A 0x1440013 +#define QAM_DQ_CMA_RATIO__W 14 +#define QAM_DQ_CMA_RATIO__M 0x3FFF +#define QAM_DQ_CMA_RATIO__PRE 0x3CF9 +#define QAM_DQ_CMA_RATIO_QPSK 0x2000 +#define QAM_DQ_CMA_RATIO_QAM16 0x34CD +#define QAM_DQ_CMA_RATIO_QAM64 0x3A00 +#define QAM_DQ_CMA_RATIO_QAM256 0x3B4D +#define QAM_DQ_CMA_RATIO_QAM1024 0x3BA0 + +#define QAM_DQ_QUAL_RADSEL__A 0x1440014 +#define QAM_DQ_QUAL_RADSEL__W 3 +#define QAM_DQ_QUAL_RADSEL__M 0x7 +#define QAM_DQ_QUAL_RADSEL__PRE 0x0 + +#define QAM_DQ_QUAL_RADSEL_BIT__B 0 +#define QAM_DQ_QUAL_RADSEL_BIT__W 3 +#define QAM_DQ_QUAL_RADSEL_BIT__M 0x7 +#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0x6 + +#define QAM_DQ_QUAL_ENA__A 0x1440015 +#define QAM_DQ_QUAL_ENA__W 1 +#define QAM_DQ_QUAL_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA__PRE 0x0 + +#define QAM_DQ_QUAL_ENA_ENA__B 0 +#define QAM_DQ_QUAL_ENA_ENA__W 1 +#define QAM_DQ_QUAL_ENA_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA_ENA__PRE 0x0 +#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0x1 + +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__PRE 0x4 + +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__PRE 0x6 + +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 + +#define QAM_DQ_RAW_LIM__A 0x144001E +#define QAM_DQ_RAW_LIM__W 5 +#define QAM_DQ_RAW_LIM__M 0x1F +#define QAM_DQ_RAW_LIM__PRE 0x1F + +#define QAM_DQ_RAW_LIM_BIT__B 0 +#define QAM_DQ_RAW_LIM_BIT__W 5 +#define QAM_DQ_RAW_LIM_BIT__M 0x1F +#define QAM_DQ_RAW_LIM_BIT__PRE 0x1F + +#define QAM_DQ_TAP_RE_EL0__A 0x1440020 +#define QAM_DQ_TAP_RE_EL0__W 12 +#define QAM_DQ_TAP_RE_EL0__M 0xFFF +#define QAM_DQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL0_TAP__B 0 +#define QAM_DQ_TAP_RE_EL0_TAP__W 12 +#define QAM_DQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0__A 0x1440021 +#define QAM_DQ_TAP_IM_EL0__W 12 +#define QAM_DQ_TAP_IM_EL0__M 0xFFF +#define QAM_DQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0_TAP__B 0 +#define QAM_DQ_TAP_IM_EL0_TAP__W 12 +#define QAM_DQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1__A 0x1440022 +#define QAM_DQ_TAP_RE_EL1__W 12 +#define QAM_DQ_TAP_RE_EL1__M 0xFFF +#define QAM_DQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1_TAP__B 0 +#define QAM_DQ_TAP_RE_EL1_TAP__W 12 +#define QAM_DQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1__A 0x1440023 +#define QAM_DQ_TAP_IM_EL1__W 12 +#define QAM_DQ_TAP_IM_EL1__M 0xFFF +#define QAM_DQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1_TAP__B 0 +#define QAM_DQ_TAP_IM_EL1_TAP__W 12 +#define QAM_DQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2__A 0x1440024 +#define QAM_DQ_TAP_RE_EL2__W 12 +#define QAM_DQ_TAP_RE_EL2__M 0xFFF +#define QAM_DQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2_TAP__B 0 +#define QAM_DQ_TAP_RE_EL2_TAP__W 12 +#define QAM_DQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2__A 0x1440025 +#define QAM_DQ_TAP_IM_EL2__W 12 +#define QAM_DQ_TAP_IM_EL2__M 0xFFF +#define QAM_DQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2_TAP__B 0 +#define QAM_DQ_TAP_IM_EL2_TAP__W 12 +#define QAM_DQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3__A 0x1440026 +#define QAM_DQ_TAP_RE_EL3__W 12 +#define QAM_DQ_TAP_RE_EL3__M 0xFFF +#define QAM_DQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3_TAP__B 0 +#define QAM_DQ_TAP_RE_EL3_TAP__W 12 +#define QAM_DQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3__A 0x1440027 +#define QAM_DQ_TAP_IM_EL3__W 12 +#define QAM_DQ_TAP_IM_EL3__M 0xFFF +#define QAM_DQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3_TAP__B 0 +#define QAM_DQ_TAP_IM_EL3_TAP__W 12 +#define QAM_DQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4__A 0x1440028 +#define QAM_DQ_TAP_RE_EL4__W 12 +#define QAM_DQ_TAP_RE_EL4__M 0xFFF +#define QAM_DQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4_TAP__B 0 +#define QAM_DQ_TAP_RE_EL4_TAP__W 12 +#define QAM_DQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4__A 0x1440029 +#define QAM_DQ_TAP_IM_EL4__W 12 +#define QAM_DQ_TAP_IM_EL4__M 0xFFF +#define QAM_DQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4_TAP__B 0 +#define QAM_DQ_TAP_IM_EL4_TAP__W 12 +#define QAM_DQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5__A 0x144002A +#define QAM_DQ_TAP_RE_EL5__W 12 +#define QAM_DQ_TAP_RE_EL5__M 0xFFF +#define QAM_DQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5_TAP__B 0 +#define QAM_DQ_TAP_RE_EL5_TAP__W 12 +#define QAM_DQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5__A 0x144002B +#define QAM_DQ_TAP_IM_EL5__W 12 +#define QAM_DQ_TAP_IM_EL5__M 0xFFF +#define QAM_DQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5_TAP__B 0 +#define QAM_DQ_TAP_IM_EL5_TAP__W 12 +#define QAM_DQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6__A 0x144002C +#define QAM_DQ_TAP_RE_EL6__W 12 +#define QAM_DQ_TAP_RE_EL6__M 0xFFF +#define QAM_DQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6_TAP__B 0 +#define QAM_DQ_TAP_RE_EL6_TAP__W 12 +#define QAM_DQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6__A 0x144002D +#define QAM_DQ_TAP_IM_EL6__W 12 +#define QAM_DQ_TAP_IM_EL6__M 0xFFF +#define QAM_DQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6_TAP__B 0 +#define QAM_DQ_TAP_IM_EL6_TAP__W 12 +#define QAM_DQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7__A 0x144002E +#define QAM_DQ_TAP_RE_EL7__W 12 +#define QAM_DQ_TAP_RE_EL7__M 0xFFF +#define QAM_DQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7_TAP__B 0 +#define QAM_DQ_TAP_RE_EL7_TAP__W 12 +#define QAM_DQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7__A 0x144002F +#define QAM_DQ_TAP_IM_EL7__W 12 +#define QAM_DQ_TAP_IM_EL7__M 0xFFF +#define QAM_DQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7_TAP__B 0 +#define QAM_DQ_TAP_IM_EL7_TAP__W 12 +#define QAM_DQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8__A 0x1440030 +#define QAM_DQ_TAP_RE_EL8__W 12 +#define QAM_DQ_TAP_RE_EL8__M 0xFFF +#define QAM_DQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8_TAP__B 0 +#define QAM_DQ_TAP_RE_EL8_TAP__W 12 +#define QAM_DQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8__A 0x1440031 +#define QAM_DQ_TAP_IM_EL8__W 12 +#define QAM_DQ_TAP_IM_EL8__M 0xFFF +#define QAM_DQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8_TAP__B 0 +#define QAM_DQ_TAP_IM_EL8_TAP__W 12 +#define QAM_DQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9__A 0x1440032 +#define QAM_DQ_TAP_RE_EL9__W 12 +#define QAM_DQ_TAP_RE_EL9__M 0xFFF +#define QAM_DQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9_TAP__B 0 +#define QAM_DQ_TAP_RE_EL9_TAP__W 12 +#define QAM_DQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9__A 0x1440033 +#define QAM_DQ_TAP_IM_EL9__W 12 +#define QAM_DQ_TAP_IM_EL9__M 0xFFF +#define QAM_DQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9_TAP__B 0 +#define QAM_DQ_TAP_IM_EL9_TAP__W 12 +#define QAM_DQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10__A 0x1440034 +#define QAM_DQ_TAP_RE_EL10__W 12 +#define QAM_DQ_TAP_RE_EL10__M 0xFFF +#define QAM_DQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10_TAP__B 0 +#define QAM_DQ_TAP_RE_EL10_TAP__W 12 +#define QAM_DQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10__A 0x1440035 +#define QAM_DQ_TAP_IM_EL10__W 12 +#define QAM_DQ_TAP_IM_EL10__M 0xFFF +#define QAM_DQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10_TAP__B 0 +#define QAM_DQ_TAP_IM_EL10_TAP__W 12 +#define QAM_DQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11__A 0x1440036 +#define QAM_DQ_TAP_RE_EL11__W 12 +#define QAM_DQ_TAP_RE_EL11__M 0xFFF +#define QAM_DQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11_TAP__B 0 +#define QAM_DQ_TAP_RE_EL11_TAP__W 12 +#define QAM_DQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11__A 0x1440037 +#define QAM_DQ_TAP_IM_EL11__W 12 +#define QAM_DQ_TAP_IM_EL11__M 0xFFF +#define QAM_DQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11_TAP__B 0 +#define QAM_DQ_TAP_IM_EL11_TAP__W 12 +#define QAM_DQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12__A 0x1440038 +#define QAM_DQ_TAP_RE_EL12__W 12 +#define QAM_DQ_TAP_RE_EL12__M 0xFFF +#define QAM_DQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12_TAP__B 0 +#define QAM_DQ_TAP_RE_EL12_TAP__W 12 +#define QAM_DQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12__A 0x1440039 +#define QAM_DQ_TAP_IM_EL12__W 12 +#define QAM_DQ_TAP_IM_EL12__M 0xFFF +#define QAM_DQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12_TAP__B 0 +#define QAM_DQ_TAP_IM_EL12_TAP__W 12 +#define QAM_DQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13__A 0x144003A +#define QAM_DQ_TAP_RE_EL13__W 12 +#define QAM_DQ_TAP_RE_EL13__M 0xFFF +#define QAM_DQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13_TAP__B 0 +#define QAM_DQ_TAP_RE_EL13_TAP__W 12 +#define QAM_DQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13__A 0x144003B +#define QAM_DQ_TAP_IM_EL13__W 12 +#define QAM_DQ_TAP_IM_EL13__M 0xFFF +#define QAM_DQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13_TAP__B 0 +#define QAM_DQ_TAP_IM_EL13_TAP__W 12 +#define QAM_DQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14__A 0x144003C +#define QAM_DQ_TAP_RE_EL14__W 12 +#define QAM_DQ_TAP_RE_EL14__M 0xFFF +#define QAM_DQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14_TAP__B 0 +#define QAM_DQ_TAP_RE_EL14_TAP__W 12 +#define QAM_DQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14__A 0x144003D +#define QAM_DQ_TAP_IM_EL14__W 12 +#define QAM_DQ_TAP_IM_EL14__M 0xFFF +#define QAM_DQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14_TAP__B 0 +#define QAM_DQ_TAP_IM_EL14_TAP__W 12 +#define QAM_DQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15__A 0x144003E +#define QAM_DQ_TAP_RE_EL15__W 12 +#define QAM_DQ_TAP_RE_EL15__M 0xFFF +#define QAM_DQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15_TAP__B 0 +#define QAM_DQ_TAP_RE_EL15_TAP__W 12 +#define QAM_DQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15__A 0x144003F +#define QAM_DQ_TAP_IM_EL15__W 12 +#define QAM_DQ_TAP_IM_EL15__M 0xFFF +#define QAM_DQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15_TAP__B 0 +#define QAM_DQ_TAP_IM_EL15_TAP__W 12 +#define QAM_DQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16__A 0x1440040 +#define QAM_DQ_TAP_RE_EL16__W 12 +#define QAM_DQ_TAP_RE_EL16__M 0xFFF +#define QAM_DQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16_TAP__B 0 +#define QAM_DQ_TAP_RE_EL16_TAP__W 12 +#define QAM_DQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16__A 0x1440041 +#define QAM_DQ_TAP_IM_EL16__W 12 +#define QAM_DQ_TAP_IM_EL16__M 0xFFF +#define QAM_DQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16_TAP__B 0 +#define QAM_DQ_TAP_IM_EL16_TAP__W 12 +#define QAM_DQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17__A 0x1440042 +#define QAM_DQ_TAP_RE_EL17__W 12 +#define QAM_DQ_TAP_RE_EL17__M 0xFFF +#define QAM_DQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17_TAP__B 0 +#define QAM_DQ_TAP_RE_EL17_TAP__W 12 +#define QAM_DQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17__A 0x1440043 +#define QAM_DQ_TAP_IM_EL17__W 12 +#define QAM_DQ_TAP_IM_EL17__M 0xFFF +#define QAM_DQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17_TAP__B 0 +#define QAM_DQ_TAP_IM_EL17_TAP__W 12 +#define QAM_DQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18__A 0x1440044 +#define QAM_DQ_TAP_RE_EL18__W 12 +#define QAM_DQ_TAP_RE_EL18__M 0xFFF +#define QAM_DQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18_TAP__B 0 +#define QAM_DQ_TAP_RE_EL18_TAP__W 12 +#define QAM_DQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18__A 0x1440045 +#define QAM_DQ_TAP_IM_EL18__W 12 +#define QAM_DQ_TAP_IM_EL18__M 0xFFF +#define QAM_DQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18_TAP__B 0 +#define QAM_DQ_TAP_IM_EL18_TAP__W 12 +#define QAM_DQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19__A 0x1440046 +#define QAM_DQ_TAP_RE_EL19__W 12 +#define QAM_DQ_TAP_RE_EL19__M 0xFFF +#define QAM_DQ_TAP_RE_EL19__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19_TAP__B 0 +#define QAM_DQ_TAP_RE_EL19_TAP__W 12 +#define QAM_DQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19__A 0x1440047 +#define QAM_DQ_TAP_IM_EL19__W 12 +#define QAM_DQ_TAP_IM_EL19__M 0xFFF +#define QAM_DQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19_TAP__B 0 +#define QAM_DQ_TAP_IM_EL19_TAP__W 12 +#define QAM_DQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20__A 0x1440048 +#define QAM_DQ_TAP_RE_EL20__W 12 +#define QAM_DQ_TAP_RE_EL20__M 0xFFF +#define QAM_DQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20_TAP__B 0 +#define QAM_DQ_TAP_RE_EL20_TAP__W 12 +#define QAM_DQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20__A 0x1440049 +#define QAM_DQ_TAP_IM_EL20__W 12 +#define QAM_DQ_TAP_IM_EL20__M 0xFFF +#define QAM_DQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20_TAP__B 0 +#define QAM_DQ_TAP_IM_EL20_TAP__W 12 +#define QAM_DQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21__A 0x144004A +#define QAM_DQ_TAP_RE_EL21__W 12 +#define QAM_DQ_TAP_RE_EL21__M 0xFFF +#define QAM_DQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21_TAP__B 0 +#define QAM_DQ_TAP_RE_EL21_TAP__W 12 +#define QAM_DQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21__A 0x144004B +#define QAM_DQ_TAP_IM_EL21__W 12 +#define QAM_DQ_TAP_IM_EL21__M 0xFFF +#define QAM_DQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21_TAP__B 0 +#define QAM_DQ_TAP_IM_EL21_TAP__W 12 +#define QAM_DQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22__A 0x144004C +#define QAM_DQ_TAP_RE_EL22__W 12 +#define QAM_DQ_TAP_RE_EL22__M 0xFFF +#define QAM_DQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22_TAP__B 0 +#define QAM_DQ_TAP_RE_EL22_TAP__W 12 +#define QAM_DQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22__A 0x144004D +#define QAM_DQ_TAP_IM_EL22__W 12 +#define QAM_DQ_TAP_IM_EL22__M 0xFFF +#define QAM_DQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22_TAP__B 0 +#define QAM_DQ_TAP_IM_EL22_TAP__W 12 +#define QAM_DQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23__A 0x144004E +#define QAM_DQ_TAP_RE_EL23__W 12 +#define QAM_DQ_TAP_RE_EL23__M 0xFFF +#define QAM_DQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23_TAP__B 0 +#define QAM_DQ_TAP_RE_EL23_TAP__W 12 +#define QAM_DQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23__A 0x144004F +#define QAM_DQ_TAP_IM_EL23__W 12 +#define QAM_DQ_TAP_IM_EL23__M 0xFFF +#define QAM_DQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23_TAP__B 0 +#define QAM_DQ_TAP_IM_EL23_TAP__W 12 +#define QAM_DQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24__A 0x1440050 +#define QAM_DQ_TAP_RE_EL24__W 12 +#define QAM_DQ_TAP_RE_EL24__M 0xFFF +#define QAM_DQ_TAP_RE_EL24__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24_TAP__B 0 +#define QAM_DQ_TAP_RE_EL24_TAP__W 12 +#define QAM_DQ_TAP_RE_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24__A 0x1440051 +#define QAM_DQ_TAP_IM_EL24__W 12 +#define QAM_DQ_TAP_IM_EL24__M 0xFFF +#define QAM_DQ_TAP_IM_EL24__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24_TAP__B 0 +#define QAM_DQ_TAP_IM_EL24_TAP__W 12 +#define QAM_DQ_TAP_IM_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25__A 0x1440052 +#define QAM_DQ_TAP_RE_EL25__W 12 +#define QAM_DQ_TAP_RE_EL25__M 0xFFF +#define QAM_DQ_TAP_RE_EL25__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25_TAP__B 0 +#define QAM_DQ_TAP_RE_EL25_TAP__W 12 +#define QAM_DQ_TAP_RE_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25__A 0x1440053 +#define QAM_DQ_TAP_IM_EL25__W 12 +#define QAM_DQ_TAP_IM_EL25__M 0xFFF +#define QAM_DQ_TAP_IM_EL25__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25_TAP__B 0 +#define QAM_DQ_TAP_IM_EL25_TAP__W 12 +#define QAM_DQ_TAP_IM_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26__A 0x1440054 +#define QAM_DQ_TAP_RE_EL26__W 12 +#define QAM_DQ_TAP_RE_EL26__M 0xFFF +#define QAM_DQ_TAP_RE_EL26__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26_TAP__B 0 +#define QAM_DQ_TAP_RE_EL26_TAP__W 12 +#define QAM_DQ_TAP_RE_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26__A 0x1440055 +#define QAM_DQ_TAP_IM_EL26__W 12 +#define QAM_DQ_TAP_IM_EL26__M 0xFFF +#define QAM_DQ_TAP_IM_EL26__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26_TAP__B 0 +#define QAM_DQ_TAP_IM_EL26_TAP__W 12 +#define QAM_DQ_TAP_IM_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27__A 0x1440056 +#define QAM_DQ_TAP_RE_EL27__W 12 +#define QAM_DQ_TAP_RE_EL27__M 0xFFF +#define QAM_DQ_TAP_RE_EL27__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27_TAP__B 0 +#define QAM_DQ_TAP_RE_EL27_TAP__W 12 +#define QAM_DQ_TAP_RE_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27__A 0x1440057 +#define QAM_DQ_TAP_IM_EL27__W 12 +#define QAM_DQ_TAP_IM_EL27__M 0xFFF +#define QAM_DQ_TAP_IM_EL27__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27_TAP__B 0 +#define QAM_DQ_TAP_IM_EL27_TAP__W 12 +#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2 + +#define QAM_LC_COMM_EXEC__A 0x1450000 +#define QAM_LC_COMM_EXEC__W 2 +#define QAM_LC_COMM_EXEC__M 0x3 +#define QAM_LC_COMM_EXEC__PRE 0x0 +#define QAM_LC_COMM_EXEC_STOP 0x0 +#define QAM_LC_COMM_EXEC_ACTIVE 0x1 +#define QAM_LC_COMM_EXEC_HOLD 0x2 + +#define QAM_LC_COMM_MB__A 0x1450002 +#define QAM_LC_COMM_MB__W 2 +#define QAM_LC_COMM_MB__M 0x3 +#define QAM_LC_COMM_MB__PRE 0x0 +#define QAM_LC_COMM_MB_CTL__B 0 +#define QAM_LC_COMM_MB_CTL__W 1 +#define QAM_LC_COMM_MB_CTL__M 0x1 +#define QAM_LC_COMM_MB_CTL__PRE 0x0 +#define QAM_LC_COMM_MB_CTL_OFF 0x0 +#define QAM_LC_COMM_MB_CTL_ON 0x1 +#define QAM_LC_COMM_MB_OBS__B 1 +#define QAM_LC_COMM_MB_OBS__W 1 +#define QAM_LC_COMM_MB_OBS__M 0x2 +#define QAM_LC_COMM_MB_OBS__PRE 0x0 +#define QAM_LC_COMM_MB_OBS_OFF 0x0 +#define QAM_LC_COMM_MB_OBS_ON 0x2 + +#define QAM_LC_COMM_INT_REQ__A 0x1450003 +#define QAM_LC_COMM_INT_REQ__W 1 +#define QAM_LC_COMM_INT_REQ__M 0x1 +#define QAM_LC_COMM_INT_REQ__PRE 0x0 +#define QAM_LC_COMM_INT_STA__A 0x1450005 +#define QAM_LC_COMM_INT_STA__W 3 +#define QAM_LC_COMM_INT_STA__M 0x7 +#define QAM_LC_COMM_INT_STA__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_READY__B 0 +#define QAM_LC_COMM_INT_STA_READY__W 1 +#define QAM_LC_COMM_INT_STA_READY__M 0x1 +#define QAM_LC_COMM_INT_STA_READY__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_MSK__A 0x1450006 +#define QAM_LC_COMM_INT_MSK__W 3 +#define QAM_LC_COMM_INT_MSK__M 0x7 +#define QAM_LC_COMM_INT_MSK__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_READY__B 0 +#define QAM_LC_COMM_INT_MSK_READY__W 1 +#define QAM_LC_COMM_INT_MSK_READY__M 0x1 +#define QAM_LC_COMM_INT_MSK_READY__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_STM__A 0x1450007 +#define QAM_LC_COMM_INT_STM__W 3 +#define QAM_LC_COMM_INT_STM__M 0x7 +#define QAM_LC_COMM_INT_STM__PRE 0x0 +#define QAM_LC_COMM_INT_STM_READY__B 0 +#define QAM_LC_COMM_INT_STM_READY__W 1 +#define QAM_LC_COMM_INT_STM_READY__M 0x1 +#define QAM_LC_COMM_INT_STM_READY__PRE 0x0 +#define QAM_LC_COMM_INT_STM_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_MODE__A 0x1450010 +#define QAM_LC_MODE__W 3 +#define QAM_LC_MODE__M 0x7 +#define QAM_LC_MODE__PRE 0x7 + +#define QAM_LC_MODE_ENABLE_A__B 0 +#define QAM_LC_MODE_ENABLE_A__W 1 +#define QAM_LC_MODE_ENABLE_A__M 0x1 +#define QAM_LC_MODE_ENABLE_A__PRE 0x1 + +#define QAM_LC_MODE_ENABLE_F__B 1 +#define QAM_LC_MODE_ENABLE_F__W 1 +#define QAM_LC_MODE_ENABLE_F__M 0x2 +#define QAM_LC_MODE_ENABLE_F__PRE 0x2 + +#define QAM_LC_MODE_ENABLE_R__B 2 +#define QAM_LC_MODE_ENABLE_R__W 1 +#define QAM_LC_MODE_ENABLE_R__M 0x4 +#define QAM_LC_MODE_ENABLE_R__PRE 0x4 + +#define QAM_LC_CA__A 0x1450011 +#define QAM_LC_CA__W 6 +#define QAM_LC_CA__M 0x3F +#define QAM_LC_CA__PRE 0x28 + +#define QAM_LC_CA_COEF__B 0 +#define QAM_LC_CA_COEF__W 6 +#define QAM_LC_CA_COEF__M 0x3F +#define QAM_LC_CA_COEF__PRE 0x28 + +#define QAM_LC_CF__A 0x1450012 +#define QAM_LC_CF__W 8 +#define QAM_LC_CF__M 0xFF +#define QAM_LC_CF__PRE 0x8C + +#define QAM_LC_CF_COEF__B 0 +#define QAM_LC_CF_COEF__W 8 +#define QAM_LC_CF_COEF__M 0xFF +#define QAM_LC_CF_COEF__PRE 0x8C + +#define QAM_LC_CF1__A 0x1450013 +#define QAM_LC_CF1__W 8 +#define QAM_LC_CF1__M 0xFF +#define QAM_LC_CF1__PRE 0x1E + +#define QAM_LC_CF1_COEF__B 0 +#define QAM_LC_CF1_COEF__W 8 +#define QAM_LC_CF1_COEF__M 0xFF +#define QAM_LC_CF1_COEF__PRE 0x1E + +#define QAM_LC_CP__A 0x1450014 +#define QAM_LC_CP__W 8 +#define QAM_LC_CP__M 0xFF +#define QAM_LC_CP__PRE 0x78 + +#define QAM_LC_CP_COEF__B 0 +#define QAM_LC_CP_COEF__W 8 +#define QAM_LC_CP_COEF__M 0xFF +#define QAM_LC_CP_COEF__PRE 0x78 + +#define QAM_LC_CI__A 0x1450015 +#define QAM_LC_CI__W 8 +#define QAM_LC_CI__M 0xFF +#define QAM_LC_CI__PRE 0x46 + +#define QAM_LC_CI_COEF__B 0 +#define QAM_LC_CI_COEF__W 8 +#define QAM_LC_CI_COEF__M 0xFF +#define QAM_LC_CI_COEF__PRE 0x46 + +#define QAM_LC_EP__A 0x1450016 +#define QAM_LC_EP__W 6 +#define QAM_LC_EP__M 0x3F +#define QAM_LC_EP__PRE 0x0 + +#define QAM_LC_EP_COEF__B 0 +#define QAM_LC_EP_COEF__W 6 +#define QAM_LC_EP_COEF__M 0x3F +#define QAM_LC_EP_COEF__PRE 0x0 + +#define QAM_LC_EI__A 0x1450017 +#define QAM_LC_EI__W 6 +#define QAM_LC_EI__M 0x3F +#define QAM_LC_EI__PRE 0x0 + +#define QAM_LC_EI_COEF__B 0 +#define QAM_LC_EI_COEF__W 6 +#define QAM_LC_EI_COEF__M 0x3F +#define QAM_LC_EI_COEF__PRE 0x0 + +#define QAM_LC_QUAL_TAB0__A 0x1450018 +#define QAM_LC_QUAL_TAB0__W 5 +#define QAM_LC_QUAL_TAB0__M 0x1F +#define QAM_LC_QUAL_TAB0__PRE 0x1 + +#define QAM_LC_QUAL_TAB0_VALUE__B 0 +#define QAM_LC_QUAL_TAB0_VALUE__W 5 +#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB1__A 0x1450019 +#define QAM_LC_QUAL_TAB1__W 5 +#define QAM_LC_QUAL_TAB1__M 0x1F +#define QAM_LC_QUAL_TAB1__PRE 0x1 + +#define QAM_LC_QUAL_TAB1_VALUE__B 0 +#define QAM_LC_QUAL_TAB1_VALUE__W 5 +#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB2__A 0x145001A +#define QAM_LC_QUAL_TAB2__W 5 +#define QAM_LC_QUAL_TAB2__M 0x1F +#define QAM_LC_QUAL_TAB2__PRE 0x1 + +#define QAM_LC_QUAL_TAB2_VALUE__B 0 +#define QAM_LC_QUAL_TAB2_VALUE__W 5 +#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB3__A 0x145001B +#define QAM_LC_QUAL_TAB3__W 5 +#define QAM_LC_QUAL_TAB3__M 0x1F +#define QAM_LC_QUAL_TAB3__PRE 0x1 + +#define QAM_LC_QUAL_TAB3_VALUE__B 0 +#define QAM_LC_QUAL_TAB3_VALUE__W 5 +#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB4__A 0x145001C +#define QAM_LC_QUAL_TAB4__W 5 +#define QAM_LC_QUAL_TAB4__M 0x1F +#define QAM_LC_QUAL_TAB4__PRE 0x1 + +#define QAM_LC_QUAL_TAB4_VALUE__B 0 +#define QAM_LC_QUAL_TAB4_VALUE__W 5 +#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB5__A 0x145001D +#define QAM_LC_QUAL_TAB5__W 5 +#define QAM_LC_QUAL_TAB5__M 0x1F +#define QAM_LC_QUAL_TAB5__PRE 0x1 + +#define QAM_LC_QUAL_TAB5_VALUE__B 0 +#define QAM_LC_QUAL_TAB5_VALUE__W 5 +#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB6__A 0x145001E +#define QAM_LC_QUAL_TAB6__W 5 +#define QAM_LC_QUAL_TAB6__M 0x1F +#define QAM_LC_QUAL_TAB6__PRE 0x1 + +#define QAM_LC_QUAL_TAB6_VALUE__B 0 +#define QAM_LC_QUAL_TAB6_VALUE__W 5 +#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB8__A 0x145001F +#define QAM_LC_QUAL_TAB8__W 5 +#define QAM_LC_QUAL_TAB8__M 0x1F +#define QAM_LC_QUAL_TAB8__PRE 0x1 + +#define QAM_LC_QUAL_TAB8_VALUE__B 0 +#define QAM_LC_QUAL_TAB8_VALUE__W 5 +#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB9__A 0x1450020 +#define QAM_LC_QUAL_TAB9__W 5 +#define QAM_LC_QUAL_TAB9__M 0x1F +#define QAM_LC_QUAL_TAB9__PRE 0x1 + +#define QAM_LC_QUAL_TAB9_VALUE__B 0 +#define QAM_LC_QUAL_TAB9_VALUE__W 5 +#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB10__A 0x1450021 +#define QAM_LC_QUAL_TAB10__W 5 +#define QAM_LC_QUAL_TAB10__M 0x1F +#define QAM_LC_QUAL_TAB10__PRE 0x1 + +#define QAM_LC_QUAL_TAB10_VALUE__B 0 +#define QAM_LC_QUAL_TAB10_VALUE__W 5 +#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB10_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB12__A 0x1450022 +#define QAM_LC_QUAL_TAB12__W 5 +#define QAM_LC_QUAL_TAB12__M 0x1F +#define QAM_LC_QUAL_TAB12__PRE 0x1 + +#define QAM_LC_QUAL_TAB12_VALUE__B 0 +#define QAM_LC_QUAL_TAB12_VALUE__W 5 +#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB12_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB15__A 0x1450023 +#define QAM_LC_QUAL_TAB15__W 5 +#define QAM_LC_QUAL_TAB15__M 0x1F +#define QAM_LC_QUAL_TAB15__PRE 0x1 + +#define QAM_LC_QUAL_TAB15_VALUE__B 0 +#define QAM_LC_QUAL_TAB15_VALUE__W 5 +#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB15_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB16__A 0x1450024 +#define QAM_LC_QUAL_TAB16__W 5 +#define QAM_LC_QUAL_TAB16__M 0x1F +#define QAM_LC_QUAL_TAB16__PRE 0x1 + +#define QAM_LC_QUAL_TAB16_VALUE__B 0 +#define QAM_LC_QUAL_TAB16_VALUE__W 5 +#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB20__A 0x1450025 +#define QAM_LC_QUAL_TAB20__W 5 +#define QAM_LC_QUAL_TAB20__M 0x1F +#define QAM_LC_QUAL_TAB20__PRE 0x1 + +#define QAM_LC_QUAL_TAB20_VALUE__B 0 +#define QAM_LC_QUAL_TAB20_VALUE__W 5 +#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB25__A 0x1450026 +#define QAM_LC_QUAL_TAB25__W 5 +#define QAM_LC_QUAL_TAB25__M 0x1F +#define QAM_LC_QUAL_TAB25__PRE 0x1 + +#define QAM_LC_QUAL_TAB25_VALUE__B 0 +#define QAM_LC_QUAL_TAB25_VALUE__W 5 +#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x1 + +#define QAM_LC_EQ_TIMING__A 0x1450027 +#define QAM_LC_EQ_TIMING__W 10 +#define QAM_LC_EQ_TIMING__M 0x3FF +#define QAM_LC_EQ_TIMING__PRE 0x0 + +#define QAM_LC_EQ_TIMING_OFFS__B 0 +#define QAM_LC_EQ_TIMING_OFFS__W 10 +#define QAM_LC_EQ_TIMING_OFFS__M 0x3FF +#define QAM_LC_EQ_TIMING_OFFS__PRE 0x0 + +#define QAM_LC_LPF_FACTORP__A 0x1450028 +#define QAM_LC_LPF_FACTORP__W 3 +#define QAM_LC_LPF_FACTORP__M 0x7 +#define QAM_LC_LPF_FACTORP__PRE 0x3 + +#define QAM_LC_LPF_FACTORP_FACTOR__B 0 +#define QAM_LC_LPF_FACTORP_FACTOR__W 3 +#define QAM_LC_LPF_FACTORP_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0x3 + +#define QAM_LC_LPF_FACTORI__A 0x1450029 +#define QAM_LC_LPF_FACTORI__W 3 +#define QAM_LC_LPF_FACTORI__M 0x7 +#define QAM_LC_LPF_FACTORI__PRE 0x3 + +#define QAM_LC_LPF_FACTORI_FACTOR__B 0 +#define QAM_LC_LPF_FACTORI_FACTOR__W 3 +#define QAM_LC_LPF_FACTORI_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0x3 + +#define QAM_LC_RATE_LIMIT__A 0x145002A +#define QAM_LC_RATE_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT__PRE 0x3 + +#define QAM_LC_RATE_LIMIT_LIMIT__B 0 +#define QAM_LC_RATE_LIMIT_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0x3 + +#define QAM_LC_SYMBOL_FREQ__A 0x145002B +#define QAM_LC_SYMBOL_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ__PRE 0x199 + +#define QAM_LC_SYMBOL_FREQ_FREQ__B 0 +#define QAM_LC_SYMBOL_FREQ_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0x199 +#define QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_64 0x197 +#define QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256 0x1B2 + +#define QAM_LC_MTA_LENGTH__A 0x145002C +#define QAM_LC_MTA_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH__PRE 0x2 + +#define QAM_LC_MTA_LENGTH_LENGTH__B 0 +#define QAM_LC_MTA_LENGTH_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x2 + +#define QAM_LC_AMP_ACCU__A 0x145002D +#define QAM_LC_AMP_ACCU__W 14 +#define QAM_LC_AMP_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU__PRE 0x600 + +#define QAM_LC_AMP_ACCU_ACCU__B 0 +#define QAM_LC_AMP_ACCU_ACCU__W 14 +#define QAM_LC_AMP_ACCU_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU_ACCU__PRE 0x600 + +#define QAM_LC_FREQ_ACCU__A 0x145002E +#define QAM_LC_FREQ_ACCU__W 10 +#define QAM_LC_FREQ_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU__PRE 0x0 + +#define QAM_LC_FREQ_ACCU_ACCU__B 0 +#define QAM_LC_FREQ_ACCU_ACCU__W 10 +#define QAM_LC_FREQ_ACCU_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU__A 0x145002F +#define QAM_LC_RATE_ACCU__W 10 +#define QAM_LC_RATE_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU_ACCU__B 0 +#define QAM_LC_RATE_ACCU_ACCU__W 10 +#define QAM_LC_RATE_ACCU_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_AMPLITUDE__A 0x1450030 +#define QAM_LC_AMPLITUDE__W 10 +#define QAM_LC_AMPLITUDE__M 0x3FF +#define QAM_LC_AMPLITUDE__PRE 0x0 + +#define QAM_LC_AMPLITUDE_SIZE__B 0 +#define QAM_LC_AMPLITUDE_SIZE__W 10 +#define QAM_LC_AMPLITUDE_SIZE__M 0x3FF +#define QAM_LC_AMPLITUDE_SIZE__PRE 0x0 + +#define QAM_LC_RAD_ERROR__A 0x1450031 +#define QAM_LC_RAD_ERROR__W 10 +#define QAM_LC_RAD_ERROR__M 0x3FF +#define QAM_LC_RAD_ERROR__PRE 0x0 + +#define QAM_LC_RAD_ERROR_SIZE__B 0 +#define QAM_LC_RAD_ERROR_SIZE__W 10 +#define QAM_LC_RAD_ERROR_SIZE__M 0x3FF +#define QAM_LC_RAD_ERROR_SIZE__PRE 0x0 + +#define QAM_LC_FREQ_OFFS__A 0x1450032 +#define QAM_LC_FREQ_OFFS__W 10 +#define QAM_LC_FREQ_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS__PRE 0x0 + +#define QAM_LC_FREQ_OFFS_OFFS__B 0 +#define QAM_LC_FREQ_OFFS_OFFS__W 10 +#define QAM_LC_FREQ_OFFS_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS_OFFS__PRE 0x0 + +#define QAM_LC_PHASE_ERROR__A 0x1450033 +#define QAM_LC_PHASE_ERROR__W 10 +#define QAM_LC_PHASE_ERROR__M 0x3FF +#define QAM_LC_PHASE_ERROR__PRE 0x0 + +#define QAM_LC_PHASE_ERROR_SIZE__B 0 +#define QAM_LC_PHASE_ERROR_SIZE__W 10 +#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF +#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0 + +#define QAM_VD_COMM_EXEC__A 0x1460000 +#define QAM_VD_COMM_EXEC__W 2 +#define QAM_VD_COMM_EXEC__M 0x3 +#define QAM_VD_COMM_EXEC__PRE 0x0 +#define QAM_VD_COMM_EXEC_STOP 0x0 +#define QAM_VD_COMM_EXEC_ACTIVE 0x1 +#define QAM_VD_COMM_EXEC_HOLD 0x2 + +#define QAM_VD_COMM_MB__A 0x1460002 +#define QAM_VD_COMM_MB__W 2 +#define QAM_VD_COMM_MB__M 0x3 +#define QAM_VD_COMM_MB__PRE 0x0 +#define QAM_VD_COMM_MB_CTL__B 0 +#define QAM_VD_COMM_MB_CTL__W 1 +#define QAM_VD_COMM_MB_CTL__M 0x1 +#define QAM_VD_COMM_MB_CTL__PRE 0x0 +#define QAM_VD_COMM_MB_CTL_OFF 0x0 +#define QAM_VD_COMM_MB_CTL_ON 0x1 +#define QAM_VD_COMM_MB_OBS__B 1 +#define QAM_VD_COMM_MB_OBS__W 1 +#define QAM_VD_COMM_MB_OBS__M 0x2 +#define QAM_VD_COMM_MB_OBS__PRE 0x0 +#define QAM_VD_COMM_MB_OBS_OFF 0x0 +#define QAM_VD_COMM_MB_OBS_ON 0x2 + +#define QAM_VD_COMM_INT_REQ__A 0x1460003 +#define QAM_VD_COMM_INT_REQ__W 1 +#define QAM_VD_COMM_INT_REQ__M 0x1 +#define QAM_VD_COMM_INT_REQ__PRE 0x0 +#define QAM_VD_COMM_INT_STA__A 0x1460005 +#define QAM_VD_COMM_INT_STA__W 2 +#define QAM_VD_COMM_INT_STA__M 0x3 +#define QAM_VD_COMM_INT_STA__PRE 0x0 + +#define QAM_VD_COMM_INT_STA_LOCK_INT__B 0 +#define QAM_VD_COMM_INT_STA_LOCK_INT__W 1 +#define QAM_VD_COMM_INT_STA_LOCK_INT__M 0x1 +#define QAM_VD_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define QAM_VD_COMM_INT_STA_PERIOD_INT__B 1 +#define QAM_VD_COMM_INT_STA_PERIOD_INT__W 1 +#define QAM_VD_COMM_INT_STA_PERIOD_INT__M 0x2 +#define QAM_VD_COMM_INT_STA_PERIOD_INT__PRE 0x0 + +#define QAM_VD_COMM_INT_MSK__A 0x1460006 +#define QAM_VD_COMM_INT_MSK__W 2 +#define QAM_VD_COMM_INT_MSK__M 0x3 +#define QAM_VD_COMM_INT_MSK__PRE 0x0 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__B 0 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__W 1 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__M 0x1 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__PRE 0x0 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__B 1 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__W 1 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__M 0x2 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__PRE 0x0 + +#define QAM_VD_COMM_INT_STM__A 0x1460007 +#define QAM_VD_COMM_INT_STM__W 2 +#define QAM_VD_COMM_INT_STM__M 0x3 +#define QAM_VD_COMM_INT_STM__PRE 0x0 +#define QAM_VD_COMM_INT_STM_LOCK_INT__B 0 +#define QAM_VD_COMM_INT_STM_LOCK_INT__W 1 +#define QAM_VD_COMM_INT_STM_LOCK_INT__M 0x1 +#define QAM_VD_COMM_INT_STM_LOCK_INT__PRE 0x0 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__B 1 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__W 1 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__M 0x2 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__PRE 0x0 + +#define QAM_VD_STATUS__A 0x1460010 +#define QAM_VD_STATUS__W 1 +#define QAM_VD_STATUS__M 0x1 +#define QAM_VD_STATUS__PRE 0x0 + +#define QAM_VD_STATUS_LOCK__B 0 +#define QAM_VD_STATUS_LOCK__W 1 +#define QAM_VD_STATUS_LOCK__M 0x1 +#define QAM_VD_STATUS_LOCK__PRE 0x0 + +#define QAM_VD_UNLOCK_CONTROL__A 0x1460011 +#define QAM_VD_UNLOCK_CONTROL__W 1 +#define QAM_VD_UNLOCK_CONTROL__M 0x1 +#define QAM_VD_UNLOCK_CONTROL__PRE 0x0 + +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__B 0 +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__W 1 +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__M 0x1 +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__PRE 0x0 + +#define QAM_VD_MIN_VOTING_ROUNDS__A 0x1460012 +#define QAM_VD_MIN_VOTING_ROUNDS__W 6 +#define QAM_VD_MIN_VOTING_ROUNDS__M 0x3F +#define QAM_VD_MIN_VOTING_ROUNDS__PRE 0x10 + +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__B 0 +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__W 6 +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__M 0x3F +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__PRE 0x10 + +#define QAM_VD_MAX_VOTING_ROUNDS__A 0x1460013 +#define QAM_VD_MAX_VOTING_ROUNDS__W 6 +#define QAM_VD_MAX_VOTING_ROUNDS__M 0x3F +#define QAM_VD_MAX_VOTING_ROUNDS__PRE 0x10 + +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__B 0 +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__W 6 +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__M 0x3F +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__PRE 0x10 + +#define QAM_VD_TRACEBACK_DEPTH__A 0x1460014 +#define QAM_VD_TRACEBACK_DEPTH__W 5 +#define QAM_VD_TRACEBACK_DEPTH__M 0x1F +#define QAM_VD_TRACEBACK_DEPTH__PRE 0x10 + +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__B 0 +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__W 5 +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__M 0x1F +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__PRE 0x10 + +#define QAM_VD_UNLOCK__A 0x1460015 +#define QAM_VD_UNLOCK__W 1 +#define QAM_VD_UNLOCK__M 0x1 +#define QAM_VD_UNLOCK__PRE 0x0 +#define QAM_VD_MEASUREMENT_PERIOD__A 0x1460016 +#define QAM_VD_MEASUREMENT_PERIOD__W 16 +#define QAM_VD_MEASUREMENT_PERIOD__M 0xFFFF +#define QAM_VD_MEASUREMENT_PERIOD__PRE 0x8236 + +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__B 0 +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__W 16 +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__PRE 0x8236 + +#define QAM_VD_MEASUREMENT_PRESCALE__A 0x1460017 +#define QAM_VD_MEASUREMENT_PRESCALE__W 16 +#define QAM_VD_MEASUREMENT_PRESCALE__M 0xFFFF +#define QAM_VD_MEASUREMENT_PRESCALE__PRE 0x4 + +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__B 0 +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__W 16 +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x4 + +#define QAM_VD_DELTA_PATH_METRIC__A 0x1460018 +#define QAM_VD_DELTA_PATH_METRIC__W 16 +#define QAM_VD_DELTA_PATH_METRIC__M 0xFFFF +#define QAM_VD_DELTA_PATH_METRIC__PRE 0xFFFF + +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__B 0 +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__W 12 +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__M 0xFFF +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__PRE 0xFFF + +#define QAM_VD_DELTA_PATH_METRIC_EXP__B 12 +#define QAM_VD_DELTA_PATH_METRIC_EXP__W 4 +#define QAM_VD_DELTA_PATH_METRIC_EXP__M 0xF000 +#define QAM_VD_DELTA_PATH_METRIC_EXP__PRE 0xF000 + +#define QAM_VD_NR_QSYM_ERRORS__A 0x1460019 +#define QAM_VD_NR_QSYM_ERRORS__W 16 +#define QAM_VD_NR_QSYM_ERRORS__M 0xFFFF +#define QAM_VD_NR_QSYM_ERRORS__PRE 0xFFFF + +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__B 0 +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__W 12 +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__M 0xFFF +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__PRE 0xFFF + +#define QAM_VD_NR_QSYM_ERRORS_EXP__B 12 +#define QAM_VD_NR_QSYM_ERRORS_EXP__W 4 +#define QAM_VD_NR_QSYM_ERRORS_EXP__M 0xF000 +#define QAM_VD_NR_QSYM_ERRORS_EXP__PRE 0xF000 + +#define QAM_VD_NR_SYMBOL_ERRORS__A 0x146001A +#define QAM_VD_NR_SYMBOL_ERRORS__W 16 +#define QAM_VD_NR_SYMBOL_ERRORS__M 0xFFFF +#define QAM_VD_NR_SYMBOL_ERRORS__PRE 0xFFFF + +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF + +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__B 12 +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__W 4 +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__M 0xF000 +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 + +#define QAM_VD_RELOCK_COUNT__A 0x146001B +#define QAM_VD_RELOCK_COUNT__W 16 +#define QAM_VD_RELOCK_COUNT__M 0xFFFF +#define QAM_VD_RELOCK_COUNT__PRE 0x0 + +#define QAM_VD_RELOCK_COUNT_COUNT__B 0 +#define QAM_VD_RELOCK_COUNT_COUNT__W 8 +#define QAM_VD_RELOCK_COUNT_COUNT__M 0xFF +#define QAM_VD_RELOCK_COUNT_COUNT__PRE 0x0 + +#define QAM_SY_COMM_EXEC__A 0x1470000 +#define QAM_SY_COMM_EXEC__W 2 +#define QAM_SY_COMM_EXEC__M 0x3 +#define QAM_SY_COMM_EXEC__PRE 0x0 +#define QAM_SY_COMM_EXEC_STOP 0x0 +#define QAM_SY_COMM_EXEC_ACTIVE 0x1 +#define QAM_SY_COMM_EXEC_HOLD 0x2 + +#define QAM_SY_COMM_MB__A 0x1470002 +#define QAM_SY_COMM_MB__W 2 +#define QAM_SY_COMM_MB__M 0x3 +#define QAM_SY_COMM_MB__PRE 0x0 +#define QAM_SY_COMM_MB_CTL__B 0 +#define QAM_SY_COMM_MB_CTL__W 1 +#define QAM_SY_COMM_MB_CTL__M 0x1 +#define QAM_SY_COMM_MB_CTL__PRE 0x0 +#define QAM_SY_COMM_MB_CTL_OFF 0x0 +#define QAM_SY_COMM_MB_CTL_ON 0x1 +#define QAM_SY_COMM_MB_OBS__B 1 +#define QAM_SY_COMM_MB_OBS__W 1 +#define QAM_SY_COMM_MB_OBS__M 0x2 +#define QAM_SY_COMM_MB_OBS__PRE 0x0 +#define QAM_SY_COMM_MB_OBS_OFF 0x0 +#define QAM_SY_COMM_MB_OBS_ON 0x2 + +#define QAM_SY_COMM_INT_REQ__A 0x1470003 +#define QAM_SY_COMM_INT_REQ__W 1 +#define QAM_SY_COMM_INT_REQ__M 0x1 +#define QAM_SY_COMM_INT_REQ__PRE 0x0 +#define QAM_SY_COMM_INT_STA__A 0x1470005 +#define QAM_SY_COMM_INT_STA__W 4 +#define QAM_SY_COMM_INT_STA__M 0xF +#define QAM_SY_COMM_INT_STA__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_LOCK_INT__B 0 +#define QAM_SY_COMM_INT_STA_LOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__M 0x1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 2 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 1 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 3 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 1 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0x8 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_MSK__A 0x1470006 +#define QAM_SY_COMM_INT_MSK__W 4 +#define QAM_SY_COMM_INT_MSK__M 0xF +#define QAM_SY_COMM_INT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_COMM_INT_STM__A 0x1470007 +#define QAM_SY_COMM_INT_STM__W 4 +#define QAM_SY_COMM_INT_STM__M 0xF +#define QAM_SY_COMM_INT_STM__PRE 0x0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_STATUS__A 0x1470010 +#define QAM_SY_STATUS__W 2 +#define QAM_SY_STATUS__M 0x3 +#define QAM_SY_STATUS__PRE 0x0 + +#define QAM_SY_STATUS_SYNC_STATE__B 0 +#define QAM_SY_STATUS_SYNC_STATE__W 2 +#define QAM_SY_STATUS_SYNC_STATE__M 0x3 +#define QAM_SY_STATUS_SYNC_STATE__PRE 0x0 + +#define QAM_SY_TIMEOUT__A 0x1470011 +#define QAM_SY_TIMEOUT__W 16 +#define QAM_SY_TIMEOUT__M 0xFFFF +#define QAM_SY_TIMEOUT__PRE 0x3A98 + +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__W 4 +#define QAM_SY_SYNC_LWM__M 0xF +#define QAM_SY_SYNC_LWM__PRE 0x2 + +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__W 4 +#define QAM_SY_SYNC_AWM__M 0xF +#define QAM_SY_SYNC_AWM__PRE 0x3 + +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__W 4 +#define QAM_SY_SYNC_HWM__M 0xF +#define QAM_SY_SYNC_HWM__PRE 0x5 + +#define QAM_SY_UNLOCK__A 0x1470015 +#define QAM_SY_UNLOCK__W 1 +#define QAM_SY_UNLOCK__M 0x1 +#define QAM_SY_UNLOCK__PRE 0x0 +#define QAM_SY_CONTROL_WORD__A 0x1470016 +#define QAM_SY_CONTROL_WORD__W 4 +#define QAM_SY_CONTROL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD__PRE 0x0 + +#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 0 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__W 4 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0 + +#define QAM_VD_ISS_RAM__A 0x1480000 + +#define QAM_VD_QSS_RAM__A 0x1490000 + +#define QAM_VD_SYM_RAM__A 0x14A0000 + +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__W 2 +#define SCU_COMM_EXEC__M 0x3 +#define SCU_COMM_EXEC__PRE 0x0 +#define SCU_COMM_EXEC_STOP 0x0 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_HOLD 0x2 + +#define SCU_COMM_STATE__A 0x800001 +#define SCU_COMM_STATE__W 16 +#define SCU_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE__PRE 0x0 + +#define SCU_COMM_STATE_COMM_STATE__B 0 +#define SCU_COMM_STATE_COMM_STATE__W 16 +#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE_COMM_STATE__PRE 0x0 + +#define SCU_TOP_COMM_EXEC__A 0x810000 +#define SCU_TOP_COMM_EXEC__W 2 +#define SCU_TOP_COMM_EXEC__M 0x3 +#define SCU_TOP_COMM_EXEC__PRE 0x0 +#define SCU_TOP_COMM_EXEC_STOP 0x0 +#define SCU_TOP_COMM_EXEC_ACTIVE 0x1 +#define SCU_TOP_COMM_EXEC_HOLD 0x2 + +#define SCU_TOP_COMM_STATE__A 0x810001 +#define SCU_TOP_COMM_STATE__W 16 +#define SCU_TOP_COMM_STATE__M 0xFFFF +#define SCU_TOP_COMM_STATE__PRE 0x0 +#define SCU_TOP_MWAIT_CTR__A 0x810010 +#define SCU_TOP_MWAIT_CTR__W 2 +#define SCU_TOP_MWAIT_CTR__M 0x3 +#define SCU_TOP_MWAIT_CTR__PRE 0x0 + +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0x1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0x1 + +#define SCU_TOP_MWAIT_CTR_READY_DIS__B 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__W 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x2 +#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2 + +#define SCU_LOW_RAM__A 0x820000 + +#define SCU_LOW_RAM_LOW__B 0 +#define SCU_LOW_RAM_LOW__W 16 +#define SCU_LOW_RAM_LOW__M 0xFFFF +#define SCU_LOW_RAM_LOW__PRE 0x0 + +#define SCU_HIGH_RAM__A 0x830000 + +#define SCU_HIGH_RAM_HIGH__B 0 +#define SCU_HIGH_RAM_HIGH__W 16 +#define SCU_HIGH_RAM_HIGH__M 0xFFFF +#define SCU_HIGH_RAM_HIGH__PRE 0x0 + +#define SCU_RAM_AGC_RF_MAX__A 0x831E96 +#define SCU_RAM_AGC_RF_MAX__W 15 +#define SCU_RAM_AGC_RF_MAX__M 0x7FFF +#define SCU_RAM_AGC_RF_MAX__PRE 0x0 + +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831E97 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0x0 + +#define SCU_RAM_AGC_KI_CYCCNT__A 0x831E98 +#define SCU_RAM_AGC_KI_CYCCNT__W 16 +#define SCU_RAM_AGC_KI_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_KI_CYCLEN__A 0x831E99 +#define SCU_RAM_AGC_KI_CYCLEN__W 16 +#define SCU_RAM_AGC_KI_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCLEN__PRE 0x0 + +#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831E9A +#define SCU_RAM_AGC_SNS_CYCLEN__W 16 +#define SCU_RAM_AGC_SNS_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0x0 + +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831E9B +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0x0 + +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831E9C +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0x0 +#define SCU_RAM_AGC_KI__A 0x831E9D +#define SCU_RAM_AGC_KI__W 15 +#define SCU_RAM_AGC_KI__M 0x7FFF +#define SCU_RAM_AGC_KI__PRE 0x0 + +#define SCU_RAM_AGC_KI_DGAIN__B 0 +#define SCU_RAM_AGC_KI_DGAIN__W 4 +#define SCU_RAM_AGC_KI_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_DGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_RF__B 4 +#define SCU_RAM_AGC_KI_RF__W 4 +#define SCU_RAM_AGC_KI_RF__M 0xF0 +#define SCU_RAM_AGC_KI_RF__PRE 0x0 + +#define SCU_RAM_AGC_KI_IF__B 8 +#define SCU_RAM_AGC_KI_IF__W 4 +#define SCU_RAM_AGC_KI_IF__M 0xF00 +#define SCU_RAM_AGC_KI_IF__PRE 0x0 + +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__B 12 +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__W 1 +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__M 0x1000 +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__PRE 0x0 + +#define SCU_RAM_AGC_KI_INV_IF_POL__B 13 +#define SCU_RAM_AGC_KI_INV_IF_POL__W 1 +#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 +#define SCU_RAM_AGC_KI_INV_IF_POL__PRE 0x0 + +#define SCU_RAM_AGC_KI_INV_RF_POL__B 14 +#define SCU_RAM_AGC_KI_INV_RF_POL__W 1 +#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 +#define SCU_RAM_AGC_KI_INV_RF_POL__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED__A 0x831E9E +#define SCU_RAM_AGC_KI_RED__W 6 +#define SCU_RAM_AGC_KI_RED__M 0x3F +#define SCU_RAM_AGC_KI_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_INNER_RED__B 0 +#define SCU_RAM_AGC_KI_RED_INNER_RED__W 2 +#define SCU_RAM_AGC_KI_RED_INNER_RED__M 0x3 +#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC +#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831E9F +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16 +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MINGAIN__A 0x831EA0 +#define SCU_RAM_AGC_KI_MINGAIN__W 16 +#define SCU_RAM_AGC_KI_MINGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MINGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831EA1 +#define SCU_RAM_AGC_KI_MAXGAIN__W 16 +#define SCU_RAM_AGC_KI_MAXGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831EA2 +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 16 +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0x0 +#define SCU_RAM_AGC_KI_MIN__A 0x831EA3 +#define SCU_RAM_AGC_KI_MIN__W 12 +#define SCU_RAM_AGC_KI_MIN__M 0xFFF +#define SCU_RAM_AGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MIN_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MIN_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_RF__B 4 +#define SCU_RAM_AGC_KI_MIN_RF__W 4 +#define SCU_RAM_AGC_KI_MIN_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MIN_RF__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_IF__B 8 +#define SCU_RAM_AGC_KI_MIN_IF__W 4 +#define SCU_RAM_AGC_KI_MIN_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MIN_IF__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX__A 0x831EA4 +#define SCU_RAM_AGC_KI_MAX__W 12 +#define SCU_RAM_AGC_KI_MAX__M 0xFFF +#define SCU_RAM_AGC_KI_MAX__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MAX_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MAX_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_RF__B 4 +#define SCU_RAM_AGC_KI_MAX_RF__W 4 +#define SCU_RAM_AGC_KI_MAX_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MAX_RF__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_IF__B 8 +#define SCU_RAM_AGC_KI_MAX_IF__W 4 +#define SCU_RAM_AGC_KI_MAX_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MAX_IF__PRE 0x0 + +#define SCU_RAM_AGC_CLP_SUM__A 0x831EA5 +#define SCU_RAM_AGC_CLP_SUM__W 16 +#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM__PRE 0x0 + +#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831EA6 +#define SCU_RAM_AGC_CLP_SUM_MIN__W 16 +#define SCU_RAM_AGC_CLP_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0x0 + +#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831EA7 +#define SCU_RAM_AGC_CLP_SUM_MAX__W 16 +#define SCU_RAM_AGC_CLP_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831EA8 +#define SCU_RAM_AGC_CLP_CYCLEN__W 16 +#define SCU_RAM_AGC_CLP_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831EA9 +#define SCU_RAM_AGC_CLP_CYCCNT__W 16 +#define SCU_RAM_AGC_CLP_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831EAA +#define SCU_RAM_AGC_CLP_DIR_TO__W 8 +#define SCU_RAM_AGC_CLP_DIR_TO__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831EAB +#define SCU_RAM_AGC_CLP_DIR_WD__W 8 +#define SCU_RAM_AGC_CLP_DIR_WD__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831EAC +#define SCU_RAM_AGC_CLP_DIR_STP__W 16 +#define SCU_RAM_AGC_CLP_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM__A 0x831EAD +#define SCU_RAM_AGC_SNS_SUM__W 16 +#define SCU_RAM_AGC_SNS_SUM__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831EAE +#define SCU_RAM_AGC_SNS_SUM_MIN__W 16 +#define SCU_RAM_AGC_SNS_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831EAF +#define SCU_RAM_AGC_SNS_SUM_MAX__W 16 +#define SCU_RAM_AGC_SNS_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0x0 + +#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831EB0 +#define SCU_RAM_AGC_SNS_CYCCNT__W 16 +#define SCU_RAM_AGC_SNS_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831EB1 +#define SCU_RAM_AGC_SNS_DIR_TO__W 8 +#define SCU_RAM_AGC_SNS_DIR_TO__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831EB2 +#define SCU_RAM_AGC_SNS_DIR_WD__W 8 +#define SCU_RAM_AGC_SNS_DIR_WD__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831EB3 +#define SCU_RAM_AGC_SNS_DIR_STP__W 16 +#define SCU_RAM_AGC_SNS_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN__A 0x831EB4 +#define SCU_RAM_AGC_INGAIN__W 16 +#define SCU_RAM_AGC_INGAIN__M 0xFFFF +#define SCU_RAM_AGC_INGAIN__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN_TGT__A 0x831EB5 +#define SCU_RAM_AGC_INGAIN_TGT__W 15 +#define SCU_RAM_AGC_INGAIN_TGT__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831EB6 +#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831EB7 +#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831EB8 +#define SCU_RAM_AGC_IF_IACCU_HI__W 16 +#define SCU_RAM_AGC_IF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831EB9 +#define SCU_RAM_AGC_IF_IACCU_LO__W 8 +#define SCU_RAM_AGC_IF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831EBA +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831EBB +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831EBC +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831EBD +#define SCU_RAM_AGC_RF_IACCU_HI__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831EBE +#define SCU_RAM_AGC_RF_IACCU_LO__W 8 +#define SCU_RAM_AGC_RF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831EBF +#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0x0 + +#define SCU_RAM_SP__A 0x831EC0 +#define SCU_RAM_SP__W 16 +#define SCU_RAM_SP__M 0xFFFF +#define SCU_RAM_SP__PRE 0x0 + +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831EC1 +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0x831EC2 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0x831EC3 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0x0 + +#define SCU_RAM_FEC_MEAS_COUNT__A 0x831EC4 +#define SCU_RAM_FEC_MEAS_COUNT__W 16 +#define SCU_RAM_FEC_MEAS_COUNT__M 0xFFFF +#define SCU_RAM_FEC_MEAS_COUNT__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A 0x831EC5 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__W 16 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__A 0x831EC6 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__W 16 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__PRE 0x0 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__W 1 +#define SCU_RAM_GPIO__M 0x1 +#define SCU_RAM_GPIO__PRE 0x0 + +#define SCU_RAM_GPIO_HW_LOCK_IND__B 0 +#define SCU_RAM_GPIO_HW_LOCK_IND__W 1 +#define SCU_RAM_GPIO_HW_LOCK_IND__M 0x1 +#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0x1 + +#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__W 8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__M 0xFF +#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_false 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_true 0x1 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x2 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0x4 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4 + +#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0x831ECA +#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 16 +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0x0 + +#define SCU_RAM_INHIBIT_1__A 0x831ECC +#define SCU_RAM_INHIBIT_1__W 16 +#define SCU_RAM_INHIBIT_1__M 0xFFFF +#define SCU_RAM_INHIBIT_1__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_0__A 0x831ECD +#define SCU_RAM_HTOL_BUF_0__W 16 +#define SCU_RAM_HTOL_BUF_0__M 0xFFFF +#define SCU_RAM_HTOL_BUF_0__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_1__A 0x831ECE +#define SCU_RAM_HTOL_BUF_1__W 16 +#define SCU_RAM_HTOL_BUF_1__M 0xFFFF +#define SCU_RAM_HTOL_BUF_1__PRE 0x0 + +#define SCU_RAM_INHIBIT_2__A 0x831ECF +#define SCU_RAM_INHIBIT_2__W 16 +#define SCU_RAM_INHIBIT_2__M 0xFFFF +#define SCU_RAM_INHIBIT_2__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_0__A 0x831ED0 +#define SCU_RAM_TR_SHORT_BUF_0__W 16 +#define SCU_RAM_TR_SHORT_BUF_0__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_1__A 0x831ED1 +#define SCU_RAM_TR_SHORT_BUF_1__W 16 +#define SCU_RAM_TR_SHORT_BUF_1__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_0__A 0x831ED2 +#define SCU_RAM_TR_LONG_BUF_0__W 16 +#define SCU_RAM_TR_LONG_BUF_0__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_1__A 0x831ED3 +#define SCU_RAM_TR_LONG_BUF_1__W 16 +#define SCU_RAM_TR_LONG_BUF_1__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_2__A 0x831ED4 +#define SCU_RAM_TR_LONG_BUF_2__W 16 +#define SCU_RAM_TR_LONG_BUF_2__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_2__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_3__A 0x831ED5 +#define SCU_RAM_TR_LONG_BUF_3__W 16 +#define SCU_RAM_TR_LONG_BUF_3__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_3__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_4__A 0x831ED6 +#define SCU_RAM_TR_LONG_BUF_4__W 16 +#define SCU_RAM_TR_LONG_BUF_4__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_4__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_5__A 0x831ED7 +#define SCU_RAM_TR_LONG_BUF_5__W 16 +#define SCU_RAM_TR_LONG_BUF_5__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_5__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_6__A 0x831ED8 +#define SCU_RAM_TR_LONG_BUF_6__W 16 +#define SCU_RAM_TR_LONG_BUF_6__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_6__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_7__A 0x831ED9 +#define SCU_RAM_TR_LONG_BUF_7__W 16 +#define SCU_RAM_TR_LONG_BUF_7__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_7__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_8__A 0x831EDA +#define SCU_RAM_TR_LONG_BUF_8__W 16 +#define SCU_RAM_TR_LONG_BUF_8__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_8__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_9__A 0x831EDB +#define SCU_RAM_TR_LONG_BUF_9__W 16 +#define SCU_RAM_TR_LONG_BUF_9__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_9__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_10__A 0x831EDC +#define SCU_RAM_TR_LONG_BUF_10__W 16 +#define SCU_RAM_TR_LONG_BUF_10__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_10__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_11__A 0x831EDD +#define SCU_RAM_TR_LONG_BUF_11__W 16 +#define SCU_RAM_TR_LONG_BUF_11__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_11__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_12__A 0x831EDE +#define SCU_RAM_TR_LONG_BUF_12__W 16 +#define SCU_RAM_TR_LONG_BUF_12__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_12__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_13__A 0x831EDF +#define SCU_RAM_TR_LONG_BUF_13__W 16 +#define SCU_RAM_TR_LONG_BUF_13__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_13__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_14__A 0x831EE0 +#define SCU_RAM_TR_LONG_BUF_14__W 16 +#define SCU_RAM_TR_LONG_BUF_14__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_14__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_15__A 0x831EE1 +#define SCU_RAM_TR_LONG_BUF_15__W 16 +#define SCU_RAM_TR_LONG_BUF_15__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_15__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_16__A 0x831EE2 +#define SCU_RAM_TR_LONG_BUF_16__W 16 +#define SCU_RAM_TR_LONG_BUF_16__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_16__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_17__A 0x831EE3 +#define SCU_RAM_TR_LONG_BUF_17__W 16 +#define SCU_RAM_TR_LONG_BUF_17__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_17__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_18__A 0x831EE4 +#define SCU_RAM_TR_LONG_BUF_18__W 16 +#define SCU_RAM_TR_LONG_BUF_18__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_18__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_19__A 0x831EE5 +#define SCU_RAM_TR_LONG_BUF_19__W 16 +#define SCU_RAM_TR_LONG_BUF_19__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_19__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_20__A 0x831EE6 +#define SCU_RAM_TR_LONG_BUF_20__W 16 +#define SCU_RAM_TR_LONG_BUF_20__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_20__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_21__A 0x831EE7 +#define SCU_RAM_TR_LONG_BUF_21__W 16 +#define SCU_RAM_TR_LONG_BUF_21__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_21__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_22__A 0x831EE8 +#define SCU_RAM_TR_LONG_BUF_22__W 16 +#define SCU_RAM_TR_LONG_BUF_22__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_22__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_23__A 0x831EE9 +#define SCU_RAM_TR_LONG_BUF_23__W 16 +#define SCU_RAM_TR_LONG_BUF_23__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_23__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_24__A 0x831EEA +#define SCU_RAM_TR_LONG_BUF_24__W 16 +#define SCU_RAM_TR_LONG_BUF_24__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_24__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_25__A 0x831EEB +#define SCU_RAM_TR_LONG_BUF_25__W 16 +#define SCU_RAM_TR_LONG_BUF_25__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_25__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_26__A 0x831EEC +#define SCU_RAM_TR_LONG_BUF_26__W 16 +#define SCU_RAM_TR_LONG_BUF_26__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_26__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_27__A 0x831EED +#define SCU_RAM_TR_LONG_BUF_27__W 16 +#define SCU_RAM_TR_LONG_BUF_27__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_27__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_28__A 0x831EEE +#define SCU_RAM_TR_LONG_BUF_28__W 16 +#define SCU_RAM_TR_LONG_BUF_28__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_28__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_29__A 0x831EEF +#define SCU_RAM_TR_LONG_BUF_29__W 16 +#define SCU_RAM_TR_LONG_BUF_29__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_29__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_30__A 0x831EF0 +#define SCU_RAM_TR_LONG_BUF_30__W 16 +#define SCU_RAM_TR_LONG_BUF_30__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_30__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_31__A 0x831EF1 +#define SCU_RAM_TR_LONG_BUF_31__W 16 +#define SCU_RAM_TR_LONG_BUF_31__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_31__PRE 0x0 +#define SCU_RAM_ATV_AMS_MAX__A 0x831EF2 +#define SCU_RAM_ATV_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 0 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MIN__A 0x831EF3 +#define SCU_RAM_ATV_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 0 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0x0 + +#define SCU_RAM_ATV_FIELD_CNT__A 0x831EF4 +#define SCU_RAM_ATV_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 0 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST__A 0x831EF5 +#define SCU_RAM_ATV_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0x1 + +#define SCU_RAM_ATV_AAGC_LP2__A 0x831EF6 +#define SCU_RAM_ATV_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 0 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL__A 0x831EF7 +#define SCU_RAM_ATV_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 0 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY__A 0x831EF8 +#define SCU_RAM_ATV_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 0 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA__A 0x831EF9 +#define SCU_RAM_ATV_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 0 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF__A 0x831EFA +#define SCU_RAM_ATV_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_BP_REF__B 0 +#define SCU_RAM_ATV_BP_REF_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MIN__A 0x831EFB +#define SCU_RAM_ATV_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 0 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MAX__A 0x831EFC +#define SCU_RAM_ATV_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 0 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0x0 + +#define SCU_RAM_ATV_BP_CNT__A 0x831EFD +#define SCU_RAM_ATV_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 0 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT__A 0x831EFE +#define SCU_RAM_ATV_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 0 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MIN__A 0x831EFF +#define SCU_RAM_ATV_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BPC_KI_MIN__A 0x831F00 +#define SCU_RAM_ATV_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 0 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A 0x831F01 +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__W 16 +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__M 0xFFFF +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__PRE 0x0 + +#define SCU_RAM_ORX_RF_RX_DATA_RATE__A 0x831F02 +#define SCU_RAM_ORX_RF_RX_DATA_RATE__W 8 +#define SCU_RAM_ORX_RF_RX_DATA_RATE__M 0xFF +#define SCU_RAM_ORX_RF_RX_DATA_RATE__PRE 0x0 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC 0x0 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC 0x1 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT 0x40 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT 0x41 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC 0x80 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC 0x81 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC 0xC0 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC 0xC1 + +#define SCU_RAM_ORX_SCU_STATE__A 0x831F03 +#define SCU_RAM_ORX_SCU_STATE__W 8 +#define SCU_RAM_ORX_SCU_STATE__M 0xFF +#define SCU_RAM_ORX_SCU_STATE__PRE 0x0 +#define SCU_RAM_ORX_SCU_STATE_RESET 0x0 +#define SCU_RAM_ORX_SCU_STATE_AGN_HUNT 0x1 +#define SCU_RAM_ORX_SCU_STATE_DGN_HUNT 0x2 +#define SCU_RAM_ORX_SCU_STATE_AGC_HUNT 0x3 +#define SCU_RAM_ORX_SCU_STATE_FRQ_HUNT 0x4 +#define SCU_RAM_ORX_SCU_STATE_PHA_HUNT 0x8 +#define SCU_RAM_ORX_SCU_STATE_TIM_HUNT 0x10 +#define SCU_RAM_ORX_SCU_STATE_EQU_HUNT 0x20 +#define SCU_RAM_ORX_SCU_STATE_EQT_HUNT 0x30 +#define SCU_RAM_ORX_SCU_STATE_SYNC 0x40 + +#define SCU_RAM_ORX_SCU_LOCK__A 0x831F04 +#define SCU_RAM_ORX_SCU_LOCK__W 16 +#define SCU_RAM_ORX_SCU_LOCK__M 0xFFFF +#define SCU_RAM_ORX_SCU_LOCK__PRE 0x0 + +#define SCU_RAM_ORX_TARGET_MODE__A 0x831F05 +#define SCU_RAM_ORX_TARGET_MODE__W 2 +#define SCU_RAM_ORX_TARGET_MODE__M 0x3 +#define SCU_RAM_ORX_TARGET_MODE__PRE 0x0 +#define SCU_RAM_ORX_TARGET_MODE_1544KBPS 0x0 +#define SCU_RAM_ORX_TARGET_MODE_3088KBPS 0x1 +#define SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT 0x2 +#define SCU_RAM_ORX_TARGET_MODE_2048KBPS_RO 0x3 + +#define SCU_RAM_ORX_MER_MIN_DB__A 0x831F06 +#define SCU_RAM_ORX_MER_MIN_DB__W 8 +#define SCU_RAM_ORX_MER_MIN_DB__M 0xFF +#define SCU_RAM_ORX_MER_MIN_DB__PRE 0x0 + +#define SCU_RAM_ORX_RF_GAIN__A 0x831F07 +#define SCU_RAM_ORX_RF_GAIN__W 16 +#define SCU_RAM_ORX_RF_GAIN__M 0xFFFF +#define SCU_RAM_ORX_RF_GAIN__PRE 0x0 + +#define SCU_RAM_ORX_RF_GAIN_MIN__A 0x831F08 +#define SCU_RAM_ORX_RF_GAIN_MIN__W 16 +#define SCU_RAM_ORX_RF_GAIN_MIN__M 0xFFFF +#define SCU_RAM_ORX_RF_GAIN_MIN__PRE 0x0 + +#define SCU_RAM_ORX_RF_GAIN_MAX__A 0x831F09 +#define SCU_RAM_ORX_RF_GAIN_MAX__W 16 +#define SCU_RAM_ORX_RF_GAIN_MAX__M 0xFFFF +#define SCU_RAM_ORX_RF_GAIN_MAX__PRE 0x0 + +#define SCU_RAM_ORX_IF_GAIN__A 0x831F0A +#define SCU_RAM_ORX_IF_GAIN__W 16 +#define SCU_RAM_ORX_IF_GAIN__M 0xFFFF +#define SCU_RAM_ORX_IF_GAIN__PRE 0x0 + +#define SCU_RAM_ORX_IF_GAIN_MIN__A 0x831F0B +#define SCU_RAM_ORX_IF_GAIN_MIN__W 16 +#define SCU_RAM_ORX_IF_GAIN_MIN__M 0xFFFF +#define SCU_RAM_ORX_IF_GAIN_MIN__PRE 0x0 + +#define SCU_RAM_ORX_IF_GAIN_MAX__A 0x831F0C +#define SCU_RAM_ORX_IF_GAIN_MAX__W 16 +#define SCU_RAM_ORX_IF_GAIN_MAX__M 0xFFFF +#define SCU_RAM_ORX_IF_GAIN_MAX__PRE 0x0 + +#define SCU_RAM_ORX_AGN_HEADR__A 0x831F0D +#define SCU_RAM_ORX_AGN_HEADR__W 16 +#define SCU_RAM_ORX_AGN_HEADR__M 0xFFFF +#define SCU_RAM_ORX_AGN_HEADR__PRE 0x0 + +#define SCU_RAM_ORX_AGN_HEADR_STP__A 0x831F0E +#define SCU_RAM_ORX_AGN_HEADR_STP__W 8 +#define SCU_RAM_ORX_AGN_HEADR_STP__M 0xFF +#define SCU_RAM_ORX_AGN_HEADR_STP__PRE 0x0 + +#define SCU_RAM_ORX_AGN_KI__A 0x831F0F +#define SCU_RAM_ORX_AGN_KI__W 8 +#define SCU_RAM_ORX_AGN_KI__M 0xFF +#define SCU_RAM_ORX_AGN_KI__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_TH__A 0x831F10 +#define SCU_RAM_ORX_AGN_LOCK_TH__W 16 +#define SCU_RAM_ORX_AGN_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_AGN_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_WD__A 0x831F11 +#define SCU_RAM_ORX_AGN_LOCK_WD__W 16 +#define SCU_RAM_ORX_AGN_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_AGN_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__A 0x831F12 +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__A 0x831F13 +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_TOTH__A 0x831F14 +#define SCU_RAM_ORX_AGN_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_AGN_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_AGN_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_MASK__A 0x831F15 +#define SCU_RAM_ORX_AGN_LOCK_MASK__W 8 +#define SCU_RAM_ORX_AGN_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_AGN_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_DGN__A 0x831F16 +#define SCU_RAM_ORX_DGN__W 16 +#define SCU_RAM_ORX_DGN__M 0xFFFF +#define SCU_RAM_ORX_DGN__PRE 0x0 + +#define SCU_RAM_ORX_DGN_MIN__A 0x831F17 +#define SCU_RAM_ORX_DGN_MIN__W 16 +#define SCU_RAM_ORX_DGN_MIN__M 0xFFFF +#define SCU_RAM_ORX_DGN_MIN__PRE 0x0 + +#define SCU_RAM_ORX_DGN_MAX__A 0x831F18 +#define SCU_RAM_ORX_DGN_MAX__W 16 +#define SCU_RAM_ORX_DGN_MAX__M 0xFFFF +#define SCU_RAM_ORX_DGN_MAX__PRE 0x0 + +#define SCU_RAM_ORX_DGN_AMP__A 0x831F19 +#define SCU_RAM_ORX_DGN_AMP__W 16 +#define SCU_RAM_ORX_DGN_AMP__M 0xFFFF +#define SCU_RAM_ORX_DGN_AMP__PRE 0x0 + +#define SCU_RAM_ORX_DGN_AMPTARGET__A 0x831F1A +#define SCU_RAM_ORX_DGN_AMPTARGET__W 16 +#define SCU_RAM_ORX_DGN_AMPTARGET__M 0xFFFF +#define SCU_RAM_ORX_DGN_AMPTARGET__PRE 0x0 + +#define SCU_RAM_ORX_DGN_KI__A 0x831F1B +#define SCU_RAM_ORX_DGN_KI__W 8 +#define SCU_RAM_ORX_DGN_KI__M 0xFF +#define SCU_RAM_ORX_DGN_KI__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_TH__A 0x831F1C +#define SCU_RAM_ORX_DGN_LOCK_TH__W 16 +#define SCU_RAM_ORX_DGN_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_DGN_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_WD__A 0x831F1D +#define SCU_RAM_ORX_DGN_LOCK_WD__W 16 +#define SCU_RAM_ORX_DGN_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_DGN_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__A 0x831F1E +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__A 0x831F1F +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_TOTH__A 0x831F20 +#define SCU_RAM_ORX_DGN_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_DGN_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_DGN_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_MASK__A 0x831F21 +#define SCU_RAM_ORX_DGN_LOCK_MASK__W 8 +#define SCU_RAM_ORX_DGN_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_DGN_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_FREQ_GAIN_CORR__A 0x831F22 +#define SCU_RAM_ORX_FREQ_GAIN_CORR__W 8 +#define SCU_RAM_ORX_FREQ_GAIN_CORR__M 0xFF +#define SCU_RAM_ORX_FREQ_GAIN_CORR__PRE 0x0 +#define SCU_RAM_ORX_FREQ_GAIN_CORR_1544KBPS 0x60 +#define SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS 0x80 +#define SCU_RAM_ORX_FREQ_GAIN_CORR_3088KBPS 0xC0 + +#define SCU_RAM_ORX_FRQ_OFFSET__A 0x831F23 +#define SCU_RAM_ORX_FRQ_OFFSET__W 16 +#define SCU_RAM_ORX_FRQ_OFFSET__M 0xFFFF +#define SCU_RAM_ORX_FRQ_OFFSET__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__A 0x831F24 +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__W 15 +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__M 0x7FFF +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_KI__A 0x831F25 +#define SCU_RAM_ORX_FRQ_KI__W 8 +#define SCU_RAM_ORX_FRQ_KI__M 0xFF +#define SCU_RAM_ORX_FRQ_KI__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_DIFF__A 0x831F26 +#define SCU_RAM_ORX_FRQ_DIFF__W 16 +#define SCU_RAM_ORX_FRQ_DIFF__M 0xFFFF +#define SCU_RAM_ORX_FRQ_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_TH__A 0x831F27 +#define SCU_RAM_ORX_FRQ_LOCK_TH__W 16 +#define SCU_RAM_ORX_FRQ_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_WD__A 0x831F28 +#define SCU_RAM_ORX_FRQ_LOCK_WD__W 16 +#define SCU_RAM_ORX_FRQ_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_FRQ_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__A 0x831F29 +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__A 0x831F2A +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__A 0x831F2B +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_MASK__A 0x831F2C +#define SCU_RAM_ORX_FRQ_LOCK_MASK__W 8 +#define SCU_RAM_ORX_FRQ_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_FRQ_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_PHA_DIFF__A 0x831F2D +#define SCU_RAM_ORX_PHA_DIFF__W 16 +#define SCU_RAM_ORX_PHA_DIFF__M 0xFFFF +#define SCU_RAM_ORX_PHA_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_TH__A 0x831F2E +#define SCU_RAM_ORX_PHA_LOCK_TH__W 16 +#define SCU_RAM_ORX_PHA_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_PHA_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_WD__A 0x831F2F +#define SCU_RAM_ORX_PHA_LOCK_WD__W 16 +#define SCU_RAM_ORX_PHA_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_PHA_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__A 0x831F30 +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__A 0x831F31 +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_TOTH__A 0x831F32 +#define SCU_RAM_ORX_PHA_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_PHA_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_PHA_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_MASK__A 0x831F33 +#define SCU_RAM_ORX_PHA_LOCK_MASK__W 8 +#define SCU_RAM_ORX_PHA_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_PHA_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_TIM_OFFSET__A 0x831F34 +#define SCU_RAM_ORX_TIM_OFFSET__W 16 +#define SCU_RAM_ORX_TIM_OFFSET__M 0xFFFF +#define SCU_RAM_ORX_TIM_OFFSET__PRE 0x0 + +#define SCU_RAM_ORX_TIM_DIFF__A 0x831F35 +#define SCU_RAM_ORX_TIM_DIFF__W 16 +#define SCU_RAM_ORX_TIM_DIFF__M 0xFFFF +#define SCU_RAM_ORX_TIM_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_TH__A 0x831F36 +#define SCU_RAM_ORX_TIM_LOCK_TH__W 16 +#define SCU_RAM_ORX_TIM_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_TIM_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_WD__A 0x831F37 +#define SCU_RAM_ORX_TIM_LOCK_WD__W 16 +#define SCU_RAM_ORX_TIM_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_TIM_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__A 0x831F38 +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__A 0x831F39 +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_TOTH__A 0x831F3A +#define SCU_RAM_ORX_TIM_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_TIM_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_TIM_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_MASK__A 0x831F3B +#define SCU_RAM_ORX_TIM_LOCK_MASK__W 8 +#define SCU_RAM_ORX_TIM_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_TIM_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_EQU_DIFF__A 0x831F3C +#define SCU_RAM_ORX_EQU_DIFF__W 16 +#define SCU_RAM_ORX_EQU_DIFF__M 0xFFFF +#define SCU_RAM_ORX_EQU_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_TH__A 0x831F3D +#define SCU_RAM_ORX_EQU_LOCK_TH__W 16 +#define SCU_RAM_ORX_EQU_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_EQU_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_WD__A 0x831F3E +#define SCU_RAM_ORX_EQU_LOCK_WD__W 16 +#define SCU_RAM_ORX_EQU_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_EQU_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__A 0x831F3F +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__A 0x831F40 +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_TOTH__A 0x831F41 +#define SCU_RAM_ORX_EQU_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_EQU_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_EQU_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_MASK__A 0x831F42 +#define SCU_RAM_ORX_EQU_LOCK_MASK__W 8 +#define SCU_RAM_ORX_EQU_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_EQU_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_FLT_FRQ__A 0x831F43 +#define SCU_RAM_ORX_FLT_FRQ__W 16 +#define SCU_RAM_ORX_FLT_FRQ__M 0xFFFF +#define SCU_RAM_ORX_FLT_FRQ__PRE 0x0 +#define SCU_RAM_ORX_RST_CPH__A 0x831F44 +#define SCU_RAM_ORX_RST_CPH__W 4 +#define SCU_RAM_ORX_RST_CPH__M 0xF +#define SCU_RAM_ORX_RST_CPH__PRE 0x0 + +#define SCU_RAM_ORX_RST_CPH_RST_CPH__B 0 +#define SCU_RAM_ORX_RST_CPH_RST_CPH__W 4 +#define SCU_RAM_ORX_RST_CPH_RST_CPH__M 0xF +#define SCU_RAM_ORX_RST_CPH_RST_CPH__PRE 0x0 + +#define SCU_RAM_ORX_RST_CTI__A 0x831F45 +#define SCU_RAM_ORX_RST_CTI__W 4 +#define SCU_RAM_ORX_RST_CTI__M 0xF +#define SCU_RAM_ORX_RST_CTI__PRE 0x0 + +#define SCU_RAM_ORX_RST_CTI_RST_CTI__B 0 +#define SCU_RAM_ORX_RST_CTI_RST_CTI__W 4 +#define SCU_RAM_ORX_RST_CTI_RST_CTI__M 0xF +#define SCU_RAM_ORX_RST_CTI_RST_CTI__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRN__A 0x831F46 +#define SCU_RAM_ORX_RST_KRN__W 4 +#define SCU_RAM_ORX_RST_KRN__M 0xF +#define SCU_RAM_ORX_RST_KRN__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRN_RST_KRN__B 0 +#define SCU_RAM_ORX_RST_KRN_RST_KRN__W 4 +#define SCU_RAM_ORX_RST_KRN_RST_KRN__M 0xF +#define SCU_RAM_ORX_RST_KRN_RST_KRN__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRP__A 0x831F47 +#define SCU_RAM_ORX_RST_KRP__W 4 +#define SCU_RAM_ORX_RST_KRP__M 0xF +#define SCU_RAM_ORX_RST_KRP__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRP_RST_KRP__B 0 +#define SCU_RAM_ORX_RST_KRP_RST_KRP__W 4 +#define SCU_RAM_ORX_RST_KRP_RST_KRP__M 0xF +#define SCU_RAM_ORX_RST_KRP_RST_KRP__PRE 0x0 + +#define SCU_RAM_ATV_STANDARD__A 0x831F48 +#define SCU_RAM_ATV_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD__PRE 0x0 + +#define SCU_RAM_ATV_STANDARD_STANDARD__B 0 +#define SCU_RAM_ATV_STANDARD_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD_STANDARD__PRE 0x0 +#define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x2 +#define SCU_RAM_ATV_STANDARD_STANDARD_B 0x103 +#define SCU_RAM_ATV_STANDARD_STANDARD_G 0x3 +#define SCU_RAM_ATV_STANDARD_STANDARD_DK 0x4 +#define SCU_RAM_ATV_STANDARD_STANDARD_L 0x9 +#define SCU_RAM_ATV_STANDARD_STANDARD_LP 0x109 +#define SCU_RAM_ATV_STANDARD_STANDARD_I 0xA +#define SCU_RAM_ATV_STANDARD_STANDARD_FM 0x40 + +#define SCU_RAM_ATV_DETECT__A 0x831F49 +#define SCU_RAM_ATV_DETECT__W 1 +#define SCU_RAM_ATV_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT__PRE 0x0 + +#define SCU_RAM_ATV_DETECT_DETECT__B 0 +#define SCU_RAM_ATV_DETECT_DETECT__W 1 +#define SCU_RAM_ATV_DETECT_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT_DETECT__PRE 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_false 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_true 0x1 + +#define SCU_RAM_ATV_DETECT_TH__A 0x831F4A +#define SCU_RAM_ATV_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH__PRE 0x0 + +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__B 0 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE 0x0 + +#define SCU_RAM_ATV_LOCK__A 0x831F4B +#define SCU_RAM_ATV_LOCK__W 2 +#define SCU_RAM_ATV_LOCK__M 0x3 +#define SCU_RAM_ATV_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B 0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W 1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M 0x1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK 0x1 + +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__B 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__W 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x2 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x2 + +#define SCU_RAM_ATV_CR_LOCK__A 0x831F4C +#define SCU_RAM_ATV_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__B 0 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_AGC_MODE__A 0x831F4D +#define SCU_RAM_ATV_AGC_MODE__W 8 +#define SCU_RAM_ATV_AGC_MODE__M 0xFF +#define SCU_RAM_ATV_AGC_MODE__PRE 0x0 + +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B 2 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W 1 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M 0x4 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW 0x4 + +#define SCU_RAM_ATV_AGC_MODE_BP_EN__B 3 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__M 0x8 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE 0x8 + +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__B 4 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__W 2 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__M 0x30 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF 0x0 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM 0x10 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM 0x20 + +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B 6 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M 0x40 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE 0x40 + +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B 7 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W 1 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M 0x80 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80 + +#define SCU_RAM_ATV_RSV_01__A 0x831F4E +#define SCU_RAM_ATV_RSV_01__W 16 +#define SCU_RAM_ATV_RSV_01__M 0xFFFF +#define SCU_RAM_ATV_RSV_01__PRE 0x0 + +#define SCU_RAM_ATV_RSV_02__A 0x831F4F +#define SCU_RAM_ATV_RSV_02__W 16 +#define SCU_RAM_ATV_RSV_02__M 0xFFFF +#define SCU_RAM_ATV_RSV_02__PRE 0x0 + +#define SCU_RAM_ATV_RSV_03__A 0x831F50 +#define SCU_RAM_ATV_RSV_03__W 16 +#define SCU_RAM_ATV_RSV_03__M 0xFFFF +#define SCU_RAM_ATV_RSV_03__PRE 0x0 + +#define SCU_RAM_ATV_RSV_04__A 0x831F51 +#define SCU_RAM_ATV_RSV_04__W 16 +#define SCU_RAM_ATV_RSV_04__M 0xFFFF +#define SCU_RAM_ATV_RSV_04__PRE 0x0 +#define SCU_RAM_ATV_FAGC_TH_RED__A 0x831F52 +#define SCU_RAM_ATV_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED__PRE 0x0 + +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B 0 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_REF__A 0x831F53 +#define SCU_RAM_ATV_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B 0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE 0x0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN 0x2BC +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK 0x2D0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I 0x314 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP 0x28A + +#define SCU_RAM_ATV_ACT_AMX__A 0x831F54 +#define SCU_RAM_ATV_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__B 0 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI__A 0x831F55 +#define SCU_RAM_ATV_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__B 0 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0 + +#define SCU_RAM_ATV_RSV_05__A 0x831F56 +#define SCU_RAM_ATV_RSV_05__W 16 +#define SCU_RAM_ATV_RSV_05__M 0xFFFF +#define SCU_RAM_ATV_RSV_05__PRE 0x0 + +#define SCU_RAM_ATV_RSV_06__A 0x831F57 +#define SCU_RAM_ATV_RSV_06__W 16 +#define SCU_RAM_ATV_RSV_06__M 0xFFFF +#define SCU_RAM_ATV_RSV_06__PRE 0x0 + +#define SCU_RAM_ATV_RSV_07__A 0x831F58 +#define SCU_RAM_ATV_RSV_07__W 16 +#define SCU_RAM_ATV_RSV_07__M 0xFFFF +#define SCU_RAM_ATV_RSV_07__PRE 0x0 + +#define SCU_RAM_ATV_RSV_08__A 0x831F59 +#define SCU_RAM_ATV_RSV_08__W 16 +#define SCU_RAM_ATV_RSV_08__M 0xFFFF +#define SCU_RAM_ATV_RSV_08__PRE 0x0 + +#define SCU_RAM_ATV_RSV_09__A 0x831F5A +#define SCU_RAM_ATV_RSV_09__W 16 +#define SCU_RAM_ATV_RSV_09__M 0xFFFF +#define SCU_RAM_ATV_RSV_09__PRE 0x0 + +#define SCU_RAM_ATV_RSV_10__A 0x831F5B +#define SCU_RAM_ATV_RSV_10__W 16 +#define SCU_RAM_ATV_RSV_10__M 0xFFFF +#define SCU_RAM_ATV_RSV_10__PRE 0x0 + +#define SCU_RAM_ATV_RSV_11__A 0x831F5C +#define SCU_RAM_ATV_RSV_11__W 16 +#define SCU_RAM_ATV_RSV_11__M 0xFFFF +#define SCU_RAM_ATV_RSV_11__PRE 0x0 + +#define SCU_RAM_ATV_RSV_12__A 0x831F5D +#define SCU_RAM_ATV_RSV_12__W 16 +#define SCU_RAM_ATV_RSV_12__M 0xFFFF +#define SCU_RAM_ATV_RSV_12__PRE 0x0 +#define SCU_RAM_ATV_VID_GAIN_HI__A 0x831F5E +#define SCU_RAM_ATV_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B 0 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_LO__A 0x831F5F +#define SCU_RAM_ATV_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B 0 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0 + +#define SCU_RAM_ATV_RSV_13__A 0x831F60 +#define SCU_RAM_ATV_RSV_13__W 16 +#define SCU_RAM_ATV_RSV_13__M 0xFFFF +#define SCU_RAM_ATV_RSV_13__PRE 0x0 + +#define SCU_RAM_ATV_RSV_14__A 0x831F61 +#define SCU_RAM_ATV_RSV_14__W 16 +#define SCU_RAM_ATV_RSV_14__M 0xFFFF +#define SCU_RAM_ATV_RSV_14__PRE 0x0 + +#define SCU_RAM_ATV_RSV_15__A 0x831F62 +#define SCU_RAM_ATV_RSV_15__W 16 +#define SCU_RAM_ATV_RSV_15__M 0xFFFF +#define SCU_RAM_ATV_RSV_15__PRE 0x0 + +#define SCU_RAM_ATV_RSV_16__A 0x831F63 +#define SCU_RAM_ATV_RSV_16__W 16 +#define SCU_RAM_ATV_RSV_16__M 0xFFFF +#define SCU_RAM_ATV_RSV_16__PRE 0x0 +#define SCU_RAM_ATV_AAGC_CNT__A 0x831F64 +#define SCU_RAM_ATV_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B 0 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE 0x0 + +#define SCU_RAM_ATV_SIF_GAIN__A 0x831F65 +#define SCU_RAM_ATV_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN__PRE 0x0 + +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B 0 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x0 + +#define SCU_RAM_ATV_RSV_17__A 0x831F66 +#define SCU_RAM_ATV_RSV_17__W 16 +#define SCU_RAM_ATV_RSV_17__M 0xFFFF +#define SCU_RAM_ATV_RSV_17__PRE 0x0 + +#define SCU_RAM_ATV_RSV_18__A 0x831F67 +#define SCU_RAM_ATV_RSV_18__W 16 +#define SCU_RAM_ATV_RSV_18__M 0xFFFF +#define SCU_RAM_ATV_RSV_18__PRE 0x0 + +#define SCU_RAM_ATV_RATE_OFS__A 0x831F68 +#define SCU_RAM_ATV_RATE_OFS__W 12 +#define SCU_RAM_ATV_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_LO_INCR__A 0x831F69 +#define SCU_RAM_ATV_LO_INCR__W 12 +#define SCU_RAM_ATV_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_IIR_CRIT__A 0x831F6A +#define SCU_RAM_ATV_IIR_CRIT__W 12 +#define SCU_RAM_ATV_IIR_CRIT__M 0xFFF +#define SCU_RAM_ATV_IIR_CRIT__PRE 0x0 + +#define SCU_RAM_ATV_DEF_RATE_OFS__A 0x831F6B +#define SCU_RAM_ATV_DEF_RATE_OFS__W 12 +#define SCU_RAM_ATV_DEF_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_DEF_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_DEF_LO_INCR__A 0x831F6C +#define SCU_RAM_ATV_DEF_LO_INCR__W 12 +#define SCU_RAM_ATV_DEF_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_DEF_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D +#define SCU_RAM_ATV_ENABLE_IIR_WA__W 1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__M 0x1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE 0x0 + +#define SCU_RAM_ATV_MOD_CONTROL__A 0x831F6E +#define SCU_RAM_ATV_MOD_CONTROL__W 12 +#define SCU_RAM_ATV_MOD_CONTROL__M 0xFFF +#define SCU_RAM_ATV_MOD_CONTROL__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MAX__A 0x831F6F +#define SCU_RAM_ATV_PAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_PAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MAX__PRE 0x0 + +#define SCU_RAM_ATV_BPC_KI_MAX__A 0x831F70 +#define SCU_RAM_ATV_BPC_KI_MAX__W 12 +#define SCU_RAM_ATV_BPC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MAX__PRE 0x0 + +#define SCU_RAM_ATV_NAGC_KI_MAX__A 0x831F71 +#define SCU_RAM_ATV_NAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_NAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MAX__PRE 0x0 +#define SCU_RAM_ATV_NAGC_KI_MIN__A 0x831F72 +#define SCU_RAM_ATV_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_KI_CHANGE_TH__A 0x831F73 +#define SCU_RAM_ATV_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH__PRE 0x0 + +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B 0 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE 0x0 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD 0x14 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD 0x28 + +#define SCU_RAM_QAM_PARAM_ANNEX__A 0x831F74 +#define SCU_RAM_QAM_PARAM_ANNEX__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE 0x0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A 0x0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B 0x1 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D 0x3 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION__A 0x831F75 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE 0x0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE__A 0x831F76 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE 0x0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN 0xFE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO 0xFF + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A 0x831F77 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A 0x831F78 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CENTERTAP__A 0x831F79 +#define SCU_RAM_QAM_EQ_CENTERTAP__W 16 +#define SCU_RAM_QAM_EQ_CENTERTAP__M 0xFFFF +#define SCU_RAM_QAM_EQ_CENTERTAP__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__B 0 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__W 8 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__M 0xFF +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_0__A 0x831F7A +#define SCU_RAM_QAM_WR_RSV_0__W 16 +#define SCU_RAM_QAM_WR_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A 0x831F7B +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A 0x831F7C +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5__A 0x831F7D +#define SCU_RAM_QAM_WR_RSV_5__W 16 +#define SCU_RAM_QAM_WR_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6__A 0x831F7E +#define SCU_RAM_QAM_WR_RSV_6__W 16 +#define SCU_RAM_QAM_WR_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7__A 0x831F7F +#define SCU_RAM_QAM_WR_RSV_7__W 16 +#define SCU_RAM_QAM_WR_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8__A 0x831F80 +#define SCU_RAM_QAM_WR_RSV_8__W 16 +#define SCU_RAM_QAM_WR_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9__A 0x831F81 +#define SCU_RAM_QAM_WR_RSV_9__W 16 +#define SCU_RAM_QAM_WR_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10__A 0x831F82 +#define SCU_RAM_QAM_WR_RSV_10__W 16 +#define SCU_RAM_QAM_WR_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FMHUM_TO__A 0x831F83 +#define SCU_RAM_QAM_FSM_FMHUM_TO__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B 0 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B 0 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B 0 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT__A 0x831F8B +#define SCU_RAM_QAM_FSM_STATE_TGT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A 0x831F8C +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W 9 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M 0x1FF +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH__A 0x831F8D +#define SCU_RAM_QAM_FSM_ATH__W 16 +#define SCU_RAM_QAM_FSM_ATH__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH_BIT__B 0 +#define SCU_RAM_QAM_FSM_ATH_BIT__W 16 +#define SCU_RAM_QAM_FSM_ATH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__W 16 +#define SCU_RAM_QAM_FSM_RTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_RTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_RTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_16 0x8C +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_64 0x4E +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_128 0x32 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_256 0x2D + +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__W 16 +#define SCU_RAM_QAM_FSM_FTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_FTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_FTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_16 0x32 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_32 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_64 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_128 0x14 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_256 0x14 + +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__W 16 +#define SCU_RAM_QAM_FSM_PTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_PTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_PTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_PTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_16 0xC8 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_32 0x96 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_128 0x64 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_256 0x64 + +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__W 16 +#define SCU_RAM_QAM_FSM_MTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_MTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_MTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_MTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_16 0x5A +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_128 0x3C +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_256 0x50 + +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__W 16 +#define SCU_RAM_QAM_FSM_CTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_CTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_CTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_CTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_16 0xA0 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_32 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_256 0x8C + +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__W 16 +#define SCU_RAM_QAM_FSM_QTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_QTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_QTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_QTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_16 0xE6 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_32 0xAA +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_64 0xC3 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_256 0x96 + +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256 0x46 + +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16 0x1E +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32 0x14 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64 0x28 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128 0x8 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256 0x28 + +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE 0x0 + +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16 0x4 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128 0x7 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256 0x6 + +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__W 16 +#define SCU_RAM_QAM_LC_CA_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_MEDIUM__A 0x831F98 +#define SCU_RAM_QAM_LC_CA_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CA_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__W 16 +#define SCU_RAM_QAM_LC_CA_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__W 16 +#define SCU_RAM_QAM_LC_CP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__W 16 +#define SCU_RAM_QAM_LC_CP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__W 16 +#define SCU_RAM_QAM_LC_CI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__W 16 +#define SCU_RAM_QAM_LC_CI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__W 16 +#define SCU_RAM_QAM_LC_EP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__W 16 +#define SCU_RAM_QAM_LC_EP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__W 16 +#define SCU_RAM_QAM_LC_EI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__W 16 +#define SCU_RAM_QAM_LC_EI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER__PRE 0x0 + +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__B 0 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE + +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 + +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF + +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 + +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D + +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 + +#define SCU_RAM_QAM_CTL_ENA__A 0x831FB3 +#define SCU_RAM_QAM_CTL_ENA__W 16 +#define SCU_RAM_QAM_CTL_ENA__M 0xFFFF +#define SCU_RAM_QAM_CTL_ENA__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_AMP__B 0 +#define SCU_RAM_QAM_CTL_ENA_AMP__W 1 +#define SCU_RAM_QAM_CTL_ENA_AMP__M 0x1 +#define SCU_RAM_QAM_CTL_ENA_AMP__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_ACQ__B 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__W 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x2 +#define SCU_RAM_QAM_CTL_ENA_ACQ__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_EQU__B 2 +#define SCU_RAM_QAM_CTL_ENA_EQU__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQU__M 0x4 +#define SCU_RAM_QAM_CTL_ENA_EQU__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_SLC__B 3 +#define SCU_RAM_QAM_CTL_ENA_SLC__W 1 +#define SCU_RAM_QAM_CTL_ENA_SLC__M 0x8 +#define SCU_RAM_QAM_CTL_ENA_SLC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_LC__B 4 +#define SCU_RAM_QAM_CTL_ENA_LC__W 1 +#define SCU_RAM_QAM_CTL_ENA_LC__M 0x10 +#define SCU_RAM_QAM_CTL_ENA_LC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_AGC__B 5 +#define SCU_RAM_QAM_CTL_ENA_AGC__W 1 +#define SCU_RAM_QAM_CTL_ENA_AGC__M 0x20 +#define SCU_RAM_QAM_CTL_ENA_AGC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_FEC__B 6 +#define SCU_RAM_QAM_CTL_ENA_FEC__W 1 +#define SCU_RAM_QAM_CTL_ENA_FEC__M 0x40 +#define SCU_RAM_QAM_CTL_ENA_FEC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_AXIS__B 7 +#define SCU_RAM_QAM_CTL_ENA_AXIS__W 1 +#define SCU_RAM_QAM_CTL_ENA_AXIS__M 0x80 +#define SCU_RAM_QAM_CTL_ENA_AXIS__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_FMHUM__B 8 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__W 1 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__M 0x100 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_EQTIME__B 9 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__M 0x200 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__B 10 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__W 1 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__M 0x400 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_1__A 0x831FB4 +#define SCU_RAM_QAM_WR_RSV_1__W 16 +#define SCU_RAM_QAM_WR_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2__A 0x831FB5 +#define SCU_RAM_QAM_WR_RSV_2__W 16 +#define SCU_RAM_QAM_WR_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3__A 0x831FB6 +#define SCU_RAM_QAM_WR_RSV_3__W 16 +#define SCU_RAM_QAM_WR_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A 0x831FB7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A 0x831FB8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE 0x0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN 0xFE + +#define SCU_RAM_QAM_RD_RSV_4__A 0x831FB9 +#define SCU_RAM_QAM_RD_RSV_4__W 16 +#define SCU_RAM_QAM_RD_RSV_4__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_4_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_4_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_4_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED__A 0x831FBA +#define SCU_RAM_QAM_LOCKED__W 16 +#define SCU_RAM_QAM_LOCKED__M 0xFFFF +#define SCU_RAM_QAM_LOCKED__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED_INTLEVEL__B 0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__W 8 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__M 0xFF +#define SCU_RAM_QAM_LOCKED_INTLEVEL__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK 0x1 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x2 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK 0x3 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK 0x4 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK 0x5 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK 0x6 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK 0x7 + +#define SCU_RAM_QAM_LOCKED_LOCKED__B 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__W 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__M 0xFF00 +#define SCU_RAM_QAM_LOCKED_LOCKED__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 +#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 +#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 + +#define SCU_RAM_QAM_EVENTS_OCC_HI__A 0x831FBB +#define SCU_RAM_QAM_EVENTS_OCC_HI__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M 0xF000 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO__A 0x831FBC +#define SCU_RAM_QAM_EVENTS_OCC_LO__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M 0x1000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B 13 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M 0x2000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B 14 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M 0x4000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B 15 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M 0x8000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI__A 0x831FBD +#define SCU_RAM_QAM_EVENTS_SCHED_HI__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO__A 0x831FBE +#define SCU_RAM_QAM_EVENTS_SCHED_LO__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED__A 0x831FBF +#define SCU_RAM_QAM_TASKLETS_SCHED__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN__A 0x831FC0 +#define SCU_RAM_QAM_TASKLETS_RUN__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A 0x831FC1 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A 0x831FC2 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5__A 0x831FC3 +#define SCU_RAM_QAM_RD_RSV_5__W 16 +#define SCU_RAM_QAM_RD_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6__A 0x831FC4 +#define SCU_RAM_QAM_RD_RSV_6__W 16 +#define SCU_RAM_QAM_RD_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7__A 0x831FC5 +#define SCU_RAM_QAM_RD_RSV_7__W 16 +#define SCU_RAM_QAM_RD_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8__A 0x831FC6 +#define SCU_RAM_QAM_RD_RSV_8__W 16 +#define SCU_RAM_QAM_RD_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9__A 0x831FC7 +#define SCU_RAM_QAM_RD_RSV_9__W 16 +#define SCU_RAM_QAM_RD_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10__A 0x831FC8 +#define SCU_RAM_QAM_RD_RSV_10__W 16 +#define SCU_RAM_QAM_RD_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS__A 0x831FC9 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B 0 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE__A 0x831FCA +#define SCU_RAM_QAM_FSM_STATE__W 4 +#define SCU_RAM_QAM_FSM_STATE__M 0xF +#define SCU_RAM_QAM_FSM_STATE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_STATE_NEW__A 0x831FCB +#define SCU_RAM_QAM_FSM_STATE_NEW__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A 0x831FCC +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W 9 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M 0x1FF +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B 2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M 0x4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B 3 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M 0x8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B 4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M 0x10 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B 5 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M 0x20 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B 6 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M 0x40 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B 7 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M 0x80 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B 8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M 0x100 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION__A 0x831FCD +#define SCU_RAM_QAM_FSM_RATE_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A 0x831FCE +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ERR_STATE__A 0x831FCF +#define SCU_RAM_QAM_ERR_STATE__W 4 +#define SCU_RAM_QAM_ERR_STATE__M 0xF +#define SCU_RAM_QAM_ERR_STATE__PRE 0x0 + +#define SCU_RAM_QAM_ERR_STATE_BIT__B 0 +#define SCU_RAM_QAM_ERR_STATE_BIT__W 4 +#define SCU_RAM_QAM_ERR_STATE_BIT__M 0xF +#define SCU_RAM_QAM_ERR_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A 0x831FD0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W 9 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M 0x1FF +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK__A 0x831FD1 +#define SCU_RAM_QAM_EQ_LOCK__W 1 +#define SCU_RAM_QAM_EQ_LOCK__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK_BIT__B 0 +#define SCU_RAM_QAM_EQ_LOCK_BIT__W 1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE__A 0x831FD2 +#define SCU_RAM_QAM_EQ_STATE__W 16 +#define SCU_RAM_QAM_EQ_STATE__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE_BIT__B 0 +#define SCU_RAM_QAM_EQ_STATE_BIT__W 16 +#define SCU_RAM_QAM_EQ_STATE_BIT__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0__A 0x831FD3 +#define SCU_RAM_QAM_RD_RSV_0__W 16 +#define SCU_RAM_QAM_RD_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1__A 0x831FD4 +#define SCU_RAM_QAM_RD_RSV_1__W 16 +#define SCU_RAM_QAM_RD_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2__A 0x831FD5 +#define SCU_RAM_QAM_RD_RSV_2__W 16 +#define SCU_RAM_QAM_RD_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3__A 0x831FD6 +#define SCU_RAM_QAM_RD_RSV_3__W 16 +#define SCU_RAM_QAM_RD_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3_BIT__PRE 0x0 + +#define SCU_RAM_VSB_CTL_MODE__A 0x831FD7 +#define SCU_RAM_VSB_CTL_MODE__W 2 +#define SCU_RAM_VSB_CTL_MODE__M 0x3 +#define SCU_RAM_VSB_CTL_MODE__PRE 0x0 + +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__B 0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__W 1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__M 0x1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__PRE 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_OFF 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_ON 0x1 + +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__B 1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__W 1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__M 0x2 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__PRE 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_OFF 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_ON 0x2 + +#define SCU_RAM_VSB_NOTCH_THRESHOLD__A 0x831FD8 +#define SCU_RAM_VSB_NOTCH_THRESHOLD__W 16 +#define SCU_RAM_VSB_NOTCH_THRESHOLD__M 0xFFFF +#define SCU_RAM_VSB_NOTCH_THRESHOLD__PRE 0x0 + +#define SCU_RAM_VSB_RSV_0__A 0x831FD9 +#define SCU_RAM_VSB_RSV_0__W 16 +#define SCU_RAM_VSB_RSV_0__M 0xFFFF +#define SCU_RAM_VSB_RSV_0__PRE 0x0 + +#define SCU_RAM_VSB_RSV_1__A 0x831FDA +#define SCU_RAM_VSB_RSV_1__W 16 +#define SCU_RAM_VSB_RSV_1__M 0xFFFF +#define SCU_RAM_VSB_RSV_1__PRE 0x0 + +#define SCU_RAM_VSB_RSV_2__A 0x831FDB +#define SCU_RAM_VSB_RSV_2__W 16 +#define SCU_RAM_VSB_RSV_2__M 0xFFFF +#define SCU_RAM_VSB_RSV_2__PRE 0x0 + +#define SCU_RAM_VSB_RSV_3__A 0x831FDC +#define SCU_RAM_VSB_RSV_3__W 16 +#define SCU_RAM_VSB_RSV_3__M 0xFFFF +#define SCU_RAM_VSB_RSV_3__PRE 0x0 + +#define SCU_RAM_VSB_RSV_4__A 0x831FDD +#define SCU_RAM_VSB_RSV_4__W 16 +#define SCU_RAM_VSB_RSV_4__M 0xFFFF +#define SCU_RAM_VSB_RSV_4__PRE 0x0 + +#define SCU_RAM_VSB_RSV_5__A 0x831FDE +#define SCU_RAM_VSB_RSV_5__W 16 +#define SCU_RAM_VSB_RSV_5__M 0xFFFF +#define SCU_RAM_VSB_RSV_5__PRE 0x0 + +#define SCU_RAM_VSB_RSV_6__A 0x831FDF +#define SCU_RAM_VSB_RSV_6__W 16 +#define SCU_RAM_VSB_RSV_6__M 0xFFFF +#define SCU_RAM_VSB_RSV_6__PRE 0x0 + +#define SCU_RAM_VSB_RSV_7__A 0x831FE0 +#define SCU_RAM_VSB_RSV_7__W 16 +#define SCU_RAM_VSB_RSV_7__M 0xFFFF +#define SCU_RAM_VSB_RSV_7__PRE 0x0 + +#define SCU_RAM_VSB_RSV_8__A 0x831FE1 +#define SCU_RAM_VSB_RSV_8__W 16 +#define SCU_RAM_VSB_RSV_8__M 0xFFFF +#define SCU_RAM_VSB_RSV_8__PRE 0x0 + +#define SCU_RAM_VSB_RSV_9__A 0x831FE2 +#define SCU_RAM_VSB_RSV_9__W 16 +#define SCU_RAM_VSB_RSV_9__M 0xFFFF +#define SCU_RAM_VSB_RSV_9__PRE 0x0 + +#define SCU_RAM_VSB_RSV_10__A 0x831FE3 +#define SCU_RAM_VSB_RSV_10__W 16 +#define SCU_RAM_VSB_RSV_10__M 0xFFFF +#define SCU_RAM_VSB_RSV_10__PRE 0x0 + +#define SCU_RAM_VSB_RSV_11__A 0x831FE4 +#define SCU_RAM_VSB_RSV_11__W 16 +#define SCU_RAM_VSB_RSV_11__M 0xFFFF +#define SCU_RAM_VSB_RSV_11__PRE 0x0 + +#define SCU_RAM_VSB_RSV_12__A 0x831FE5 +#define SCU_RAM_VSB_RSV_12__W 16 +#define SCU_RAM_VSB_RSV_12__M 0xFFFF +#define SCU_RAM_VSB_RSV_12__PRE 0x0 + +#define SCU_RAM_VSB_RSV_13__A 0x831FE6 +#define SCU_RAM_VSB_RSV_13__W 16 +#define SCU_RAM_VSB_RSV_13__M 0xFFFF +#define SCU_RAM_VSB_RSV_13__PRE 0x0 + +#define SCU_RAM_VSB_AGC_POW_TGT__A 0x831FE7 +#define SCU_RAM_VSB_AGC_POW_TGT__W 15 +#define SCU_RAM_VSB_AGC_POW_TGT__M 0x7FFF +#define SCU_RAM_VSB_AGC_POW_TGT__PRE 0x0 + +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__A 0x831FE8 +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__W 8 +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__M 0xFF +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__PRE 0x0 + +#define SCU_RAM_VSB_FIELD_NUMBER__A 0x831FE9 +#define SCU_RAM_VSB_FIELD_NUMBER__W 9 +#define SCU_RAM_VSB_FIELD_NUMBER__M 0x1FF +#define SCU_RAM_VSB_FIELD_NUMBER__PRE 0x0 + +#define SCU_RAM_VSB_SEGMENT_NUMBER__A 0x831FEA +#define SCU_RAM_VSB_SEGMENT_NUMBER__W 10 +#define SCU_RAM_VSB_SEGMENT_NUMBER__M 0x3FF +#define SCU_RAM_VSB_SEGMENT_NUMBER__PRE 0x0 + +#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB +#define SCU_RAM_DRIVER_VER_HI__W 16 +#define SCU_RAM_DRIVER_VER_HI__M 0xFFFF +#define SCU_RAM_DRIVER_VER_HI__PRE 0x0 + +#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC +#define SCU_RAM_DRIVER_VER_LO__W 16 +#define SCU_RAM_DRIVER_VER_LO__M 0xFFFF +#define SCU_RAM_DRIVER_VER_LO__PRE 0x0 + +#define SCU_RAM_PARAM_15__A 0x831FED +#define SCU_RAM_PARAM_15__W 16 +#define SCU_RAM_PARAM_15__M 0xFFFF +#define SCU_RAM_PARAM_15__PRE 0x0 + +#define SCU_RAM_PARAM_14__A 0x831FEE +#define SCU_RAM_PARAM_14__W 16 +#define SCU_RAM_PARAM_14__M 0xFFFF +#define SCU_RAM_PARAM_14__PRE 0x0 + +#define SCU_RAM_PARAM_13__A 0x831FEF +#define SCU_RAM_PARAM_13__W 16 +#define SCU_RAM_PARAM_13__M 0xFFFF +#define SCU_RAM_PARAM_13__PRE 0x0 + +#define SCU_RAM_PARAM_12__A 0x831FF0 +#define SCU_RAM_PARAM_12__W 16 +#define SCU_RAM_PARAM_12__M 0xFFFF +#define SCU_RAM_PARAM_12__PRE 0x0 + +#define SCU_RAM_PARAM_11__A 0x831FF1 +#define SCU_RAM_PARAM_11__W 16 +#define SCU_RAM_PARAM_11__M 0xFFFF +#define SCU_RAM_PARAM_11__PRE 0x0 + +#define SCU_RAM_PARAM_10__A 0x831FF2 +#define SCU_RAM_PARAM_10__W 16 +#define SCU_RAM_PARAM_10__M 0xFFFF +#define SCU_RAM_PARAM_10__PRE 0x0 + +#define SCU_RAM_PARAM_9__A 0x831FF3 +#define SCU_RAM_PARAM_9__W 16 +#define SCU_RAM_PARAM_9__M 0xFFFF +#define SCU_RAM_PARAM_9__PRE 0x0 + +#define SCU_RAM_PARAM_8__A 0x831FF4 +#define SCU_RAM_PARAM_8__W 16 +#define SCU_RAM_PARAM_8__M 0xFFFF +#define SCU_RAM_PARAM_8__PRE 0x0 + +#define SCU_RAM_PARAM_7__A 0x831FF5 +#define SCU_RAM_PARAM_7__W 16 +#define SCU_RAM_PARAM_7__M 0xFFFF +#define SCU_RAM_PARAM_7__PRE 0x0 + +#define SCU_RAM_PARAM_6__A 0x831FF6 +#define SCU_RAM_PARAM_6__W 16 +#define SCU_RAM_PARAM_6__M 0xFFFF +#define SCU_RAM_PARAM_6__PRE 0x0 + +#define SCU_RAM_PARAM_5__A 0x831FF7 +#define SCU_RAM_PARAM_5__W 16 +#define SCU_RAM_PARAM_5__M 0xFFFF +#define SCU_RAM_PARAM_5__PRE 0x0 + +#define SCU_RAM_PARAM_4__A 0x831FF8 +#define SCU_RAM_PARAM_4__W 16 +#define SCU_RAM_PARAM_4__M 0xFFFF +#define SCU_RAM_PARAM_4__PRE 0x0 + +#define SCU_RAM_PARAM_3__A 0x831FF9 +#define SCU_RAM_PARAM_3__W 16 +#define SCU_RAM_PARAM_3__M 0xFFFF +#define SCU_RAM_PARAM_3__PRE 0x0 + +#define SCU_RAM_PARAM_2__A 0x831FFA +#define SCU_RAM_PARAM_2__W 16 +#define SCU_RAM_PARAM_2__M 0xFFFF +#define SCU_RAM_PARAM_2__PRE 0x0 + +#define SCU_RAM_PARAM_1__A 0x831FFB +#define SCU_RAM_PARAM_1__W 16 +#define SCU_RAM_PARAM_1__M 0xFFFF +#define SCU_RAM_PARAM_1__PRE 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 + +#define SCU_RAM_PARAM_0__A 0x831FFC +#define SCU_RAM_PARAM_0__W 16 +#define SCU_RAM_PARAM_0__M 0xFFFF +#define SCU_RAM_PARAM_0__PRE 0x0 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 +#define SCU_RAM_PARAM_0_RESULT_OK 0x0 +#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF +#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE +#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD +#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC + +#define SCU_RAM_COMMAND__A 0x831FFD +#define SCU_RAM_COMMAND__W 16 +#define SCU_RAM_COMMAND__M 0xFFFF +#define SCU_RAM_COMMAND__PRE 0x0 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 +#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM 0x6 +#define SCU_RAM_COMMAND_CMD_DEMOD_HOLD 0x7 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESUME 0x8 +#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE 0x80 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE 0x81 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL 0x82 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR 0x83 +#define SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE 0x84 +#define SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE 0x85 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS 0x80 +#define SCU_RAM_COMMAND_CMD_DEBUG_HTOL 0x81 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER 0x82 +#define SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK 0x83 +#define SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK 0x84 +#define SCU_RAM_COMMAND_CMD_ADMIN_NOP 0xFF +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION 0xFE +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION 0xFD +#define SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS 0xC0 + +#define SCU_RAM_COMMAND_STANDARD__B 8 +#define SCU_RAM_COMMAND_STANDARD__W 8 +#define SCU_RAM_COMMAND_STANDARD__M 0xFF00 +#define SCU_RAM_COMMAND_STANDARD__PRE 0x0 +#define SCU_RAM_COMMAND_STANDARD_ATV 0x100 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND_STANDARD_VSB 0x300 +#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +#define SCU_RAM_COMMAND_STANDARD_OOB 0x8000 +#define SCU_RAM_COMMAND_STANDARD_TOP 0xFF00 + +#define SCU_RAM_VERSION_HI__A 0x831FFE +#define SCU_RAM_VERSION_HI__W 16 +#define SCU_RAM_VERSION_HI__M 0xFFFF +#define SCU_RAM_VERSION_HI__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__B 12 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__M 0xF000 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__B 8 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__M 0xF00 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__B 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__M 0xF0 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__B 0 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__M 0xF +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_LO__A 0x831FFF +#define SCU_RAM_VERSION_LO__W 16 +#define SCU_RAM_VERSION_LO__M 0xFFFF +#define SCU_RAM_VERSION_LO__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__B 12 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__M 0xF000 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__B 8 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__M 0xF00 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__B 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__M 0xF0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__B 0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0 + +#define SIO_COMM_EXEC__A 0x400000 +#define SIO_COMM_EXEC__W 2 +#define SIO_COMM_EXEC__M 0x3 +#define SIO_COMM_EXEC__PRE 0x0 +#define SIO_COMM_EXEC_STOP 0x0 +#define SIO_COMM_EXEC_ACTIVE 0x1 +#define SIO_COMM_EXEC_HOLD 0x2 + +#define SIO_COMM_STATE__A 0x400001 +#define SIO_COMM_STATE__W 16 +#define SIO_COMM_STATE__M 0xFFFF +#define SIO_COMM_STATE__PRE 0x0 +#define SIO_COMM_MB__A 0x400002 +#define SIO_COMM_MB__W 16 +#define SIO_COMM_MB__M 0xFFFF +#define SIO_COMM_MB__PRE 0x0 +#define SIO_COMM_INT_REQ__A 0x400003 +#define SIO_COMM_INT_REQ__W 16 +#define SIO_COMM_INT_REQ__M 0xFFFF +#define SIO_COMM_INT_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_HI_REQ__B 0 +#define SIO_COMM_INT_REQ_HI_REQ__W 1 +#define SIO_COMM_INT_REQ_HI_REQ__M 0x1 +#define SIO_COMM_INT_REQ_HI_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_SA_REQ__B 1 +#define SIO_COMM_INT_REQ_SA_REQ__W 1 +#define SIO_COMM_INT_REQ_SA_REQ__M 0x2 +#define SIO_COMM_INT_REQ_SA_REQ__PRE 0x0 + +#define SIO_COMM_INT_STA__A 0x400005 +#define SIO_COMM_INT_STA__W 16 +#define SIO_COMM_INT_STA__M 0xFFFF +#define SIO_COMM_INT_STA__PRE 0x0 +#define SIO_COMM_INT_MSK__A 0x400006 +#define SIO_COMM_INT_MSK__W 16 +#define SIO_COMM_INT_MSK__M 0xFFFF +#define SIO_COMM_INT_MSK__PRE 0x0 +#define SIO_COMM_INT_STM__A 0x400007 +#define SIO_COMM_INT_STM__W 16 +#define SIO_COMM_INT_STM__M 0xFFFF +#define SIO_COMM_INT_STM__PRE 0x0 + +#define SIO_TOP_COMM_EXEC__A 0x410000 +#define SIO_TOP_COMM_EXEC__W 2 +#define SIO_TOP_COMM_EXEC__M 0x3 +#define SIO_TOP_COMM_EXEC__PRE 0x0 +#define SIO_TOP_COMM_EXEC_STOP 0x0 +#define SIO_TOP_COMM_EXEC_ACTIVE 0x1 +#define SIO_TOP_COMM_EXEC_HOLD 0x2 + +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_COMM_KEY__W 16 +#define SIO_TOP_COMM_KEY__M 0xFFFF +#define SIO_TOP_COMM_KEY__PRE 0x0 +#define SIO_TOP_COMM_KEY_KEY 0xFABA + +#define SIO_TOP_JTAGID_LO__A 0x410012 +#define SIO_TOP_JTAGID_LO__W 16 +#define SIO_TOP_JTAGID_LO__M 0xFFFF +#define SIO_TOP_JTAGID_LO__PRE 0x0 + +#define SIO_TOP_JTAGID_HI__A 0x410013 +#define SIO_TOP_JTAGID_HI__W 16 +#define SIO_TOP_JTAGID_HI__M 0xFFFF +#define SIO_TOP_JTAGID_HI__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010 +#define SIO_HI_RA_RAM_S0_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_DEV_ID__A 0x420011 +#define SIO_HI_RA_RAM_S0_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S0_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S0_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S0_FLG_CRC__A 0x420012 +#define SIO_HI_RA_RAM_S0_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S0_FLG_ACC__A 0x420013 +#define SIO_HI_RA_RAM_S0_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S0_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B 0 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M 0x3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE__A 0x420014 +#define SIO_HI_RA_RAM_S0_STATE__W 1 +#define SIO_HI_RA_RAM_S0_STATE__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BLK_BNK__A 0x420015 +#define SIO_HI_RA_RAM_S0_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S0_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S0_ADDR__A 0x420016 +#define SIO_HI_RA_RAM_S0_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_CRC__A 0x420017 +#define SIO_HI_RA_RAM_S0_CRC__W 16 +#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S0_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BUFFER__A 0x420018 +#define SIO_HI_RA_RAM_S0_BUFFER__W 16 +#define SIO_HI_RA_RAM_S0_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S0_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_RMWBUF__A 0x420019 +#define SIO_HI_RA_RAM_S0_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S0_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S0_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_VB__A 0x42001A +#define SIO_HI_RA_RAM_S0_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S0_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP0__A 0x42001B +#define SIO_HI_RA_RAM_S0_TEMP0__W 16 +#define SIO_HI_RA_RAM_S0_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP1__A 0x42001C +#define SIO_HI_RA_RAM_S0_TEMP1__W 16 +#define SIO_HI_RA_RAM_S0_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_OFFSET__A 0x42001D +#define SIO_HI_RA_RAM_S0_OFFSET__W 16 +#define SIO_HI_RA_RAM_S0_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S0_OFFSET__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_SMM__A 0x420020 +#define SIO_HI_RA_RAM_S1_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_DEV_ID__A 0x420021 +#define SIO_HI_RA_RAM_S1_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S1_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S1_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S1_FLG_CRC__A 0x420022 +#define SIO_HI_RA_RAM_S1_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S1_FLG_ACC__A 0x420023 +#define SIO_HI_RA_RAM_S1_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S1_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B 0 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M 0x3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE__A 0x420024 +#define SIO_HI_RA_RAM_S1_STATE__W 1 +#define SIO_HI_RA_RAM_S1_STATE__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BLK_BNK__A 0x420025 +#define SIO_HI_RA_RAM_S1_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S1_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S1_ADDR__A 0x420026 +#define SIO_HI_RA_RAM_S1_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_CRC__A 0x420027 +#define SIO_HI_RA_RAM_S1_CRC__W 16 +#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S1_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BUFFER__A 0x420028 +#define SIO_HI_RA_RAM_S1_BUFFER__W 16 +#define SIO_HI_RA_RAM_S1_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S1_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_RMWBUF__A 0x420029 +#define SIO_HI_RA_RAM_S1_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S1_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S1_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_VB__A 0x42002A +#define SIO_HI_RA_RAM_S1_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S1_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP0__A 0x42002B +#define SIO_HI_RA_RAM_S1_TEMP0__W 16 +#define SIO_HI_RA_RAM_S1_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP1__A 0x42002C +#define SIO_HI_RA_RAM_S1_TEMP1__W 16 +#define SIO_HI_RA_RAM_S1_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_OFFSET__A 0x42002D +#define SIO_HI_RA_RAM_S1_OFFSET__W 16 +#define SIO_HI_RA_RAM_S1_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S1_OFFSET__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA__A 0x420030 +#define SIO_HI_RA_RAM_SEMA__W 1 +#define SIO_HI_RA_RAM_SEMA__M 0x1 +#define SIO_HI_RA_RAM_SEMA__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA_FREE 0x0 +#define SIO_HI_RA_RAM_SEMA_BUSY 0x1 + +#define SIO_HI_RA_RAM_RES__A 0x420031 +#define SIO_HI_RA_RAM_RES__W 3 +#define SIO_HI_RA_RAM_RES__M 0x7 +#define SIO_HI_RA_RAM_RES__PRE 0x0 +#define SIO_HI_RA_RAM_RES_OK 0x0 +#define SIO_HI_RA_RAM_RES_ERROR 0x1 +#define SIO_HI_RA_RAM_RES_I2C_START_FOUND 0x1 +#define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x2 +#define SIO_HI_RA_RAM_RES_I2C_ARB_LOST 0x3 +#define SIO_HI_RA_RAM_RES_I2C_ERROR 0x4 + +#define SIO_HI_RA_RAM_CMD__A 0x420032 +#define SIO_HI_RA_RAM_CMD__W 4 +#define SIO_HI_RA_RAM_CMD__M 0xF +#define SIO_HI_RA_RAM_CMD__PRE 0x0 +#define SIO_HI_RA_RAM_CMD_NULL 0x0 +#define SIO_HI_RA_RAM_CMD_UIO 0x1 +#define SIO_HI_RA_RAM_CMD_RESET 0x2 +#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 +#define SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER 0x4 +#define SIO_HI_RA_RAM_CMD_I2C_TRANSMIT 0x5 +#define SIO_HI_RA_RAM_CMD_EXEC 0x6 +#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 +#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 + +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 + +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 + +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 + +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 + +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 + +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 + +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 + +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF + +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 + +#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E +#define SIO_HI_RA_RAM_AB_TEMP__W 16 +#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF +#define SIO_HI_RA_RAM_AB_TEMP__PRE 0x0 + +#define SIO_HI_RA_RAM_I2C_CTL__A 0x42006F +#define SIO_HI_RA_RAM_I2C_CTL__W 16 +#define SIO_HI_RA_RAM_I2C_CTL__M 0xFFFF +#define SIO_HI_RA_RAM_I2C_CTL__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0__A 0x420070 +#define SIO_HI_RA_RAM_VB_ENTRY0__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B 0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M 0xF +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M 0xF0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B 8 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M 0xF00 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B 12 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M 0xF000 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0__A 0x420071 +#define SIO_HI_RA_RAM_VB_OFFSET0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072 +#define SIO_HI_RA_RAM_VB_ENTRY1__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY1__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET1__A 0x420073 +#define SIO_HI_RA_RAM_VB_OFFSET1__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074 +#define SIO_HI_RA_RAM_VB_ENTRY2__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY2__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET2__A 0x420075 +#define SIO_HI_RA_RAM_VB_OFFSET2__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076 +#define SIO_HI_RA_RAM_VB_ENTRY3__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY3__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET3__A 0x420077 +#define SIO_HI_RA_RAM_VB_OFFSET3__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078 +#define SIO_HI_RA_RAM_VB_ENTRY4__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY4__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET4__A 0x420079 +#define SIO_HI_RA_RAM_VB_OFFSET4__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A +#define SIO_HI_RA_RAM_VB_ENTRY5__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY5__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET5__A 0x42007B +#define SIO_HI_RA_RAM_VB_OFFSET5__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C +#define SIO_HI_RA_RAM_VB_ENTRY6__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY6__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET6__A 0x42007D +#define SIO_HI_RA_RAM_VB_OFFSET6__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E +#define SIO_HI_RA_RAM_VB_ENTRY7__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY7__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET7__A 0x42007F +#define SIO_HI_RA_RAM_VB_OFFSET7__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000 +#define SIO_HI_IF_RAM_TRP_BPT_0__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_BPT_1__A 0x430001 +#define SIO_HI_IF_RAM_TRP_BPT_1__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_1__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_0__A 0x430002 +#define SIO_HI_IF_RAM_TRP_STK_0__W 12 +#define SIO_HI_IF_RAM_TRP_STK_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_1__A 0x430003 +#define SIO_HI_IF_RAM_TRP_STK_1__W 12 +#define SIO_HI_IF_RAM_TRP_STK_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_1__PRE 0x0 +#define SIO_HI_IF_RAM_FUN_BASE__A 0x430300 +#define SIO_HI_IF_RAM_FUN_BASE__W 12 +#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF +#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0 + +#define SIO_HI_IF_COMM_EXEC__A 0x440000 +#define SIO_HI_IF_COMM_EXEC__W 2 +#define SIO_HI_IF_COMM_EXEC__M 0x3 +#define SIO_HI_IF_COMM_EXEC__PRE 0x0 +#define SIO_HI_IF_COMM_EXEC_STOP 0x0 +#define SIO_HI_IF_COMM_EXEC_ACTIVE 0x1 +#define SIO_HI_IF_COMM_EXEC_HOLD 0x2 +#define SIO_HI_IF_COMM_EXEC_STEP 0x3 + +#define SIO_HI_IF_COMM_STATE__A 0x440001 +#define SIO_HI_IF_COMM_STATE__W 10 +#define SIO_HI_IF_COMM_STATE__M 0x3FF +#define SIO_HI_IF_COMM_STATE__PRE 0x0 +#define SIO_HI_IF_COMM_INT_REQ__A 0x440003 +#define SIO_HI_IF_COMM_INT_REQ__W 1 +#define SIO_HI_IF_COMM_INT_REQ__M 0x1 +#define SIO_HI_IF_COMM_INT_REQ__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA__A 0x440005 +#define SIO_HI_IF_COMM_INT_STA__W 1 +#define SIO_HI_IF_COMM_INT_STA__M 0x1 +#define SIO_HI_IF_COMM_INT_STA__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STA_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STA_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STA_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_MSK__A 0x440006 +#define SIO_HI_IF_COMM_INT_MSK__W 1 +#define SIO_HI_IF_COMM_INT_MSK__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK__PRE 0x0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__B 0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__W 1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_STM__A 0x440007 +#define SIO_HI_IF_COMM_INT_STM__W 1 +#define SIO_HI_IF_COMM_INT_STM__M 0x1 +#define SIO_HI_IF_COMM_INT_STM__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STM_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STM_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STM_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STM_STAT__PRE 0x0 + +#define SIO_HI_IF_STK_0__A 0x440010 +#define SIO_HI_IF_STK_0__W 10 +#define SIO_HI_IF_STK_0__M 0x3FF +#define SIO_HI_IF_STK_0__PRE 0x2 + +#define SIO_HI_IF_STK_0_ADDR__B 0 +#define SIO_HI_IF_STK_0_ADDR__W 10 +#define SIO_HI_IF_STK_0_ADDR__M 0x3FF +#define SIO_HI_IF_STK_0_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_1__A 0x440011 +#define SIO_HI_IF_STK_1__W 10 +#define SIO_HI_IF_STK_1__M 0x3FF +#define SIO_HI_IF_STK_1__PRE 0x2 +#define SIO_HI_IF_STK_1_ADDR__B 0 +#define SIO_HI_IF_STK_1_ADDR__W 10 +#define SIO_HI_IF_STK_1_ADDR__M 0x3FF +#define SIO_HI_IF_STK_1_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_2__A 0x440012 +#define SIO_HI_IF_STK_2__W 10 +#define SIO_HI_IF_STK_2__M 0x3FF +#define SIO_HI_IF_STK_2__PRE 0x2 +#define SIO_HI_IF_STK_2_ADDR__B 0 +#define SIO_HI_IF_STK_2_ADDR__W 10 +#define SIO_HI_IF_STK_2_ADDR__M 0x3FF +#define SIO_HI_IF_STK_2_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_3__A 0x440013 +#define SIO_HI_IF_STK_3__W 10 +#define SIO_HI_IF_STK_3__M 0x3FF +#define SIO_HI_IF_STK_3__PRE 0x2 + +#define SIO_HI_IF_STK_3_ADDR__B 0 +#define SIO_HI_IF_STK_3_ADDR__W 10 +#define SIO_HI_IF_STK_3_ADDR__M 0x3FF +#define SIO_HI_IF_STK_3_ADDR__PRE 0x2 + +#define SIO_HI_IF_BPT_IDX__A 0x44001F +#define SIO_HI_IF_BPT_IDX__W 1 +#define SIO_HI_IF_BPT_IDX__M 0x1 +#define SIO_HI_IF_BPT_IDX__PRE 0x0 + +#define SIO_HI_IF_BPT_IDX_ADDR__B 0 +#define SIO_HI_IF_BPT_IDX_ADDR__W 1 +#define SIO_HI_IF_BPT_IDX_ADDR__M 0x1 +#define SIO_HI_IF_BPT_IDX_ADDR__PRE 0x0 + +#define SIO_HI_IF_BPT__A 0x440020 +#define SIO_HI_IF_BPT__W 10 +#define SIO_HI_IF_BPT__M 0x3FF +#define SIO_HI_IF_BPT__PRE 0x2 + +#define SIO_HI_IF_BPT_ADDR__B 0 +#define SIO_HI_IF_BPT_ADDR__W 10 +#define SIO_HI_IF_BPT_ADDR__M 0x3FF +#define SIO_HI_IF_BPT_ADDR__PRE 0x2 + +#define SIO_CC_COMM_EXEC__A 0x450000 +#define SIO_CC_COMM_EXEC__W 2 +#define SIO_CC_COMM_EXEC__M 0x3 +#define SIO_CC_COMM_EXEC__PRE 0x0 +#define SIO_CC_COMM_EXEC_STOP 0x0 +#define SIO_CC_COMM_EXEC_ACTIVE 0x1 +#define SIO_CC_COMM_EXEC_HOLD 0x2 + +#define SIO_CC_PLL_MODE__A 0x450010 +#define SIO_CC_PLL_MODE__W 6 +#define SIO_CC_PLL_MODE__M 0x3F +#define SIO_CC_PLL_MODE__PRE 0x0 + +#define SIO_CC_PLL_MODE_FREF_SEL__B 0 +#define SIO_CC_PLL_MODE_FREF_SEL__W 2 +#define SIO_CC_PLL_MODE_FREF_SEL__M 0x3 +#define SIO_CC_PLL_MODE_FREF_SEL__PRE 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_OHW 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_27_00 0x1 +#define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x2 +#define SIO_CC_PLL_MODE_FREF_SEL_4_00 0x3 + +#define SIO_CC_PLL_MODE_LOCKSEL__B 2 +#define SIO_CC_PLL_MODE_LOCKSEL__W 2 +#define SIO_CC_PLL_MODE_LOCKSEL__M 0xC +#define SIO_CC_PLL_MODE_LOCKSEL__PRE 0x0 + +#define SIO_CC_PLL_MODE_BYPASS__B 4 +#define SIO_CC_PLL_MODE_BYPASS__W 2 +#define SIO_CC_PLL_MODE_BYPASS__M 0x30 +#define SIO_CC_PLL_MODE_BYPASS__PRE 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OHW 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OFF 0x10 +#define SIO_CC_PLL_MODE_BYPASS_ON 0x20 + +#define SIO_CC_PLL_TEST__A 0x450011 +#define SIO_CC_PLL_TEST__W 8 +#define SIO_CC_PLL_TEST__M 0xFF +#define SIO_CC_PLL_TEST__PRE 0x0 + +#define SIO_CC_PLL_LOCK__A 0x450012 +#define SIO_CC_PLL_LOCK__W 1 +#define SIO_CC_PLL_LOCK__M 0x1 +#define SIO_CC_PLL_LOCK__PRE 0x0 +#define SIO_CC_CLK_MODE__A 0x450014 +#define SIO_CC_CLK_MODE__W 5 +#define SIO_CC_CLK_MODE__M 0x1F +#define SIO_CC_CLK_MODE__PRE 0x0 + +#define SIO_CC_CLK_MODE_DELAY__B 0 +#define SIO_CC_CLK_MODE_DELAY__W 4 +#define SIO_CC_CLK_MODE_DELAY__M 0xF +#define SIO_CC_CLK_MODE_DELAY__PRE 0x0 + +#define SIO_CC_CLK_MODE_INVERT__B 4 +#define SIO_CC_CLK_MODE_INVERT__W 1 +#define SIO_CC_CLK_MODE_INVERT__M 0x10 +#define SIO_CC_CLK_MODE_INVERT__PRE 0x0 + +#define SIO_CC_PWD_MODE__A 0x450015 +#define SIO_CC_PWD_MODE__W 3 +#define SIO_CC_PWD_MODE__M 0x7 +#define SIO_CC_PWD_MODE__PRE 0x0 + +#define SIO_CC_PWD_MODE_LEVEL__B 0 +#define SIO_CC_PWD_MODE_LEVEL__W 2 +#define SIO_CC_PWD_MODE_LEVEL__M 0x3 +#define SIO_CC_PWD_MODE_LEVEL__PRE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x1 +#define SIO_CC_PWD_MODE_LEVEL_PLL 0x2 +#define SIO_CC_PWD_MODE_LEVEL_OSC 0x3 + +#define SIO_CC_PWD_MODE_USE_LOCK__B 2 +#define SIO_CC_PWD_MODE_USE_LOCK__W 1 +#define SIO_CC_PWD_MODE_USE_LOCK__M 0x4 +#define SIO_CC_PWD_MODE_USE_LOCK__PRE 0x0 + +#define SIO_CC_SOFT_RST__A 0x450016 +#define SIO_CC_SOFT_RST__W 2 +#define SIO_CC_SOFT_RST__M 0x3 +#define SIO_CC_SOFT_RST__PRE 0x0 + +#define SIO_CC_SOFT_RST_SYS__B 0 +#define SIO_CC_SOFT_RST_SYS__W 1 +#define SIO_CC_SOFT_RST_SYS__M 0x1 +#define SIO_CC_SOFT_RST_SYS__PRE 0x0 + +#define SIO_CC_SOFT_RST_OSC__B 1 +#define SIO_CC_SOFT_RST_OSC__W 1 +#define SIO_CC_SOFT_RST_OSC__M 0x2 +#define SIO_CC_SOFT_RST_OSC__PRE 0x0 + +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_CC_UPDATE__W 16 +#define SIO_CC_UPDATE__M 0xFFFF +#define SIO_CC_UPDATE__PRE 0x0 +#define SIO_CC_UPDATE_KEY 0xFABA + +#define SIO_SA_COMM_EXEC__A 0x460000 +#define SIO_SA_COMM_EXEC__W 2 +#define SIO_SA_COMM_EXEC__M 0x3 +#define SIO_SA_COMM_EXEC__PRE 0x0 +#define SIO_SA_COMM_EXEC_STOP 0x0 +#define SIO_SA_COMM_EXEC_ACTIVE 0x1 +#define SIO_SA_COMM_EXEC_HOLD 0x2 + +#define SIO_SA_COMM_INT_REQ__A 0x460003 +#define SIO_SA_COMM_INT_REQ__W 1 +#define SIO_SA_COMM_INT_REQ__M 0x1 +#define SIO_SA_COMM_INT_REQ__PRE 0x0 +#define SIO_SA_COMM_INT_STA__A 0x460005 +#define SIO_SA_COMM_INT_STA__W 4 +#define SIO_SA_COMM_INT_STA__M 0xF +#define SIO_SA_COMM_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__B 0 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__M 0x1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x2 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__B 2 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__M 0x4 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B 3 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W 1 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M 0x8 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK__A 0x460006 +#define SIO_SA_COMM_INT_MSK__W 4 +#define SIO_SA_COMM_INT_MSK__M 0xF +#define SIO_SA_COMM_INT_MSK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM__A 0x460007 +#define SIO_SA_COMM_INT_STM__W 4 +#define SIO_SA_COMM_INT_STM__M 0xF +#define SIO_SA_COMM_INT_STM__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_PRESCALER__A 0x460010 +#define SIO_SA_PRESCALER__W 13 +#define SIO_SA_PRESCALER__M 0x1FFF +#define SIO_SA_PRESCALER__PRE 0x18B7 +#define SIO_SA_TX_DATA0__A 0x460011 +#define SIO_SA_TX_DATA0__W 16 +#define SIO_SA_TX_DATA0__M 0xFFFF +#define SIO_SA_TX_DATA0__PRE 0x0 +#define SIO_SA_TX_DATA1__A 0x460012 +#define SIO_SA_TX_DATA1__W 16 +#define SIO_SA_TX_DATA1__M 0xFFFF +#define SIO_SA_TX_DATA1__PRE 0x0 +#define SIO_SA_TX_DATA2__A 0x460013 +#define SIO_SA_TX_DATA2__W 16 +#define SIO_SA_TX_DATA2__M 0xFFFF +#define SIO_SA_TX_DATA2__PRE 0x0 +#define SIO_SA_TX_DATA3__A 0x460014 +#define SIO_SA_TX_DATA3__W 16 +#define SIO_SA_TX_DATA3__M 0xFFFF +#define SIO_SA_TX_DATA3__PRE 0x0 +#define SIO_SA_TX_LENGTH__A 0x460015 +#define SIO_SA_TX_LENGTH__W 6 +#define SIO_SA_TX_LENGTH__M 0x3F +#define SIO_SA_TX_LENGTH__PRE 0x0 +#define SIO_SA_TX_COMMAND__A 0x460016 +#define SIO_SA_TX_COMMAND__W 2 +#define SIO_SA_TX_COMMAND__M 0x3 +#define SIO_SA_TX_COMMAND__PRE 0x3 + +#define SIO_SA_TX_COMMAND_TX_INVERT__B 0 +#define SIO_SA_TX_COMMAND_TX_INVERT__W 1 +#define SIO_SA_TX_COMMAND_TX_INVERT__M 0x1 +#define SIO_SA_TX_COMMAND_TX_INVERT__PRE 0x1 + +#define SIO_SA_TX_COMMAND_TX_ENABLE__B 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__W 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x2 +#define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x2 + +#define SIO_SA_TX_STATUS__A 0x460017 +#define SIO_SA_TX_STATUS__W 2 +#define SIO_SA_TX_STATUS__M 0x3 +#define SIO_SA_TX_STATUS__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUSY__B 0 +#define SIO_SA_TX_STATUS_BUSY__W 1 +#define SIO_SA_TX_STATUS_BUSY__M 0x1 +#define SIO_SA_TX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_TX_STATUS_BUFF_FULL__PRE 0x0 + +#define SIO_SA_RX_DATA0__A 0x460018 +#define SIO_SA_RX_DATA0__W 16 +#define SIO_SA_RX_DATA0__M 0xFFFF +#define SIO_SA_RX_DATA0__PRE 0x0 +#define SIO_SA_RX_DATA1__A 0x460019 +#define SIO_SA_RX_DATA1__W 16 +#define SIO_SA_RX_DATA1__M 0xFFFF +#define SIO_SA_RX_DATA1__PRE 0x0 +#define SIO_SA_RX_LENGTH__A 0x46001A +#define SIO_SA_RX_LENGTH__W 6 +#define SIO_SA_RX_LENGTH__M 0x3F +#define SIO_SA_RX_LENGTH__PRE 0x0 +#define SIO_SA_RX_COMMAND__A 0x46001B +#define SIO_SA_RX_COMMAND__W 1 +#define SIO_SA_RX_COMMAND__M 0x1 +#define SIO_SA_RX_COMMAND__PRE 0x1 + +#define SIO_SA_RX_COMMAND_RX_INVERT__B 0 +#define SIO_SA_RX_COMMAND_RX_INVERT__W 1 +#define SIO_SA_RX_COMMAND_RX_INVERT__M 0x1 +#define SIO_SA_RX_COMMAND_RX_INVERT__PRE 0x1 + +#define SIO_SA_RX_STATUS__A 0x46001C +#define SIO_SA_RX_STATUS__W 2 +#define SIO_SA_RX_STATUS__M 0x3 +#define SIO_SA_RX_STATUS__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUSY__B 0 +#define SIO_SA_RX_STATUS_BUSY__W 1 +#define SIO_SA_RX_STATUS_BUSY__M 0x1 +#define SIO_SA_RX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0 + +#define SIO_PDR_COMM_EXEC__A 0x7F0000 +#define SIO_PDR_COMM_EXEC__W 2 +#define SIO_PDR_COMM_EXEC__M 0x3 +#define SIO_PDR_COMM_EXEC__PRE 0x0 +#define SIO_PDR_COMM_EXEC_STOP 0x0 +#define SIO_PDR_COMM_EXEC_ACTIVE 0x1 +#define SIO_PDR_COMM_EXEC_HOLD 0x2 + +#define SIO_PDR_MON_CFG__A 0x7F0010 +#define SIO_PDR_MON_CFG__W 2 +#define SIO_PDR_MON_CFG__M 0x3 +#define SIO_PDR_MON_CFG__PRE 0x0 + +#define SIO_PDR_MON_CFG_OSEL__B 0 +#define SIO_PDR_MON_CFG_OSEL__W 1 +#define SIO_PDR_MON_CFG_OSEL__M 0x1 +#define SIO_PDR_MON_CFG_OSEL__PRE 0x0 + +#define SIO_PDR_MON_CFG_IACT__B 1 +#define SIO_PDR_MON_CFG_IACT__W 1 +#define SIO_PDR_MON_CFG_IACT__M 0x2 +#define SIO_PDR_MON_CFG_IACT__PRE 0x0 + +#define SIO_PDR_FDB_CFG__A 0x7F0011 +#define SIO_PDR_FDB_CFG__W 2 +#define SIO_PDR_FDB_CFG__M 0x3 +#define SIO_PDR_FDB_CFG__PRE 0x0 +#define SIO_PDR_FDB_CFG_SEL__B 0 +#define SIO_PDR_FDB_CFG_SEL__W 2 +#define SIO_PDR_FDB_CFG_SEL__M 0x3 +#define SIO_PDR_FDB_CFG_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_SEL__A 0x7F0012 +#define SIO_PDR_SMA_RX_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL__PRE 0x0 +#define SIO_PDR_SMA_RX_SEL_SEL__B 0 +#define SIO_PDR_SMA_RX_SEL_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL_SEL__PRE 0x0 + +#define SIO_PDR_SMA_TX_SILENT__A 0x7F0013 +#define SIO_PDR_SMA_TX_SILENT__W 1 +#define SIO_PDR_SMA_TX_SILENT__M 0x1 +#define SIO_PDR_SMA_TX_SILENT__PRE 0x0 +#define SIO_PDR_UIO_IN_LO__A 0x7F0014 +#define SIO_PDR_UIO_IN_LO__W 16 +#define SIO_PDR_UIO_IN_LO__M 0xFFFF +#define SIO_PDR_UIO_IN_LO__PRE 0x0 +#define SIO_PDR_UIO_IN_LO_DATA__B 0 +#define SIO_PDR_UIO_IN_LO_DATA__W 16 +#define SIO_PDR_UIO_IN_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_IN_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_IN_HI__A 0x7F0015 +#define SIO_PDR_UIO_IN_HI__W 14 +#define SIO_PDR_UIO_IN_HI__M 0x3FFF +#define SIO_PDR_UIO_IN_HI__PRE 0x0 +#define SIO_PDR_UIO_IN_HI_DATA__B 0 +#define SIO_PDR_UIO_IN_HI_DATA__W 14 +#define SIO_PDR_UIO_IN_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_IN_HI_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 +#define SIO_PDR_UIO_OUT_LO__W 16 +#define SIO_PDR_UIO_OUT_LO__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO__PRE 0x0 +#define SIO_PDR_UIO_OUT_LO_DATA__B 0 +#define SIO_PDR_UIO_OUT_LO_DATA__W 16 +#define SIO_PDR_UIO_OUT_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_HI__A 0x7F0017 +#define SIO_PDR_UIO_OUT_HI__W 14 +#define SIO_PDR_UIO_OUT_HI__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI__PRE 0x0 +#define SIO_PDR_UIO_OUT_HI_DATA__B 0 +#define SIO_PDR_UIO_OUT_HI_DATA__W 14 +#define SIO_PDR_UIO_OUT_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI_DATA__PRE 0x0 + +#define SIO_PDR_PWM1_MODE__A 0x7F0018 +#define SIO_PDR_PWM1_MODE__W 2 +#define SIO_PDR_PWM1_MODE__M 0x3 +#define SIO_PDR_PWM1_MODE__PRE 0x0 +#define SIO_PDR_PWM1_PRESCALE__A 0x7F0019 +#define SIO_PDR_PWM1_PRESCALE__W 6 +#define SIO_PDR_PWM1_PRESCALE__M 0x3F +#define SIO_PDR_PWM1_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM1_VALUE__A 0x7F001A +#define SIO_PDR_PWM1_VALUE__W 11 +#define SIO_PDR_PWM1_VALUE__M 0x7FF +#define SIO_PDR_PWM1_VALUE__PRE 0x0 +#define SIO_PDR_PWM2_MODE__A 0x7F001C +#define SIO_PDR_PWM2_MODE__W 2 +#define SIO_PDR_PWM2_MODE__M 0x3 +#define SIO_PDR_PWM2_MODE__PRE 0x0 +#define SIO_PDR_PWM2_PRESCALE__A 0x7F001D +#define SIO_PDR_PWM2_PRESCALE__W 6 +#define SIO_PDR_PWM2_PRESCALE__M 0x3F +#define SIO_PDR_PWM2_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM2_VALUE__A 0x7F001E +#define SIO_PDR_PWM2_VALUE__W 11 +#define SIO_PDR_PWM2_VALUE__M 0x7FF +#define SIO_PDR_PWM2_VALUE__PRE 0x0 +#define SIO_PDR_OHW_CFG__A 0x7F001F +#define SIO_PDR_OHW_CFG__W 7 +#define SIO_PDR_OHW_CFG__M 0x7F +#define SIO_PDR_OHW_CFG__PRE 0x0 + +#define SIO_PDR_OHW_CFG_FREF_SEL__B 0 +#define SIO_PDR_OHW_CFG_FREF_SEL__W 2 +#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 +#define SIO_PDR_OHW_CFG_FREF_SEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_BYPASS__B 2 +#define SIO_PDR_OHW_CFG_BYPASS__W 1 +#define SIO_PDR_OHW_CFG_BYPASS__M 0x4 +#define SIO_PDR_OHW_CFG_BYPASS__PRE 0x0 + +#define SIO_PDR_OHW_CFG_ASEL__B 3 +#define SIO_PDR_OHW_CFG_ASEL__W 3 +#define SIO_PDR_OHW_CFG_ASEL__M 0x38 +#define SIO_PDR_OHW_CFG_ASEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_SPEED__B 6 +#define SIO_PDR_OHW_CFG_SPEED__W 1 +#define SIO_PDR_OHW_CFG_SPEED__M 0x40 +#define SIO_PDR_OHW_CFG_SPEED__PRE 0x0 + +#define SIO_PDR_I2S_WS_CFG__A 0x7F0020 +#define SIO_PDR_I2S_WS_CFG__W 9 +#define SIO_PDR_I2S_WS_CFG__M 0x1FF +#define SIO_PDR_I2S_WS_CFG__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_MODE__B 0 +#define SIO_PDR_I2S_WS_CFG_MODE__W 3 +#define SIO_PDR_I2S_WS_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_WS_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_WS_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_KEEP__B 6 +#define SIO_PDR_I2S_WS_CFG_KEEP__W 2 +#define SIO_PDR_I2S_WS_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_WS_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_UIO__B 8 +#define SIO_PDR_I2S_WS_CFG_UIO__W 1 +#define SIO_PDR_I2S_WS_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_WS_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_CFG__A 0x7F0021 +#define SIO_PDR_GPIO_CFG__W 9 +#define SIO_PDR_GPIO_CFG__M 0x1FF +#define SIO_PDR_GPIO_CFG__PRE 0x10 +#define SIO_PDR_GPIO_CFG_MODE__B 0 +#define SIO_PDR_GPIO_CFG_MODE__W 3 +#define SIO_PDR_GPIO_CFG_MODE__M 0x7 +#define SIO_PDR_GPIO_CFG_MODE__PRE 0x0 +#define SIO_PDR_GPIO_CFG_DRIVE__B 3 +#define SIO_PDR_GPIO_CFG_DRIVE__W 3 +#define SIO_PDR_GPIO_CFG_DRIVE__M 0x38 +#define SIO_PDR_GPIO_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_GPIO_CFG_KEEP__B 6 +#define SIO_PDR_GPIO_CFG_KEEP__W 2 +#define SIO_PDR_GPIO_CFG_KEEP__M 0xC0 +#define SIO_PDR_GPIO_CFG_KEEP__PRE 0x0 +#define SIO_PDR_GPIO_CFG_UIO__B 8 +#define SIO_PDR_GPIO_CFG_UIO__W 1 +#define SIO_PDR_GPIO_CFG_UIO__M 0x100 +#define SIO_PDR_GPIO_CFG_UIO__PRE 0x0 + +#define SIO_PDR_IRQN_CFG__A 0x7F0022 +#define SIO_PDR_IRQN_CFG__W 9 +#define SIO_PDR_IRQN_CFG__M 0x1FF +#define SIO_PDR_IRQN_CFG__PRE 0x10 +#define SIO_PDR_IRQN_CFG_MODE__B 0 +#define SIO_PDR_IRQN_CFG_MODE__W 3 +#define SIO_PDR_IRQN_CFG_MODE__M 0x7 +#define SIO_PDR_IRQN_CFG_MODE__PRE 0x0 +#define SIO_PDR_IRQN_CFG_DRIVE__B 3 +#define SIO_PDR_IRQN_CFG_DRIVE__W 3 +#define SIO_PDR_IRQN_CFG_DRIVE__M 0x38 +#define SIO_PDR_IRQN_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_IRQN_CFG_KEEP__B 6 +#define SIO_PDR_IRQN_CFG_KEEP__W 2 +#define SIO_PDR_IRQN_CFG_KEEP__M 0xC0 +#define SIO_PDR_IRQN_CFG_KEEP__PRE 0x0 +#define SIO_PDR_IRQN_CFG_UIO__B 8 +#define SIO_PDR_IRQN_CFG_UIO__W 1 +#define SIO_PDR_IRQN_CFG_UIO__M 0x100 +#define SIO_PDR_IRQN_CFG_UIO__PRE 0x0 + +#define SIO_PDR_OOB_CRX_CFG__A 0x7F0023 +#define SIO_PDR_OOB_CRX_CFG__W 9 +#define SIO_PDR_OOB_CRX_CFG__M 0x1FF +#define SIO_PDR_OOB_CRX_CFG__PRE 0x10 +#define SIO_PDR_OOB_CRX_CFG_MODE__B 0 +#define SIO_PDR_OOB_CRX_CFG_MODE__W 3 +#define SIO_PDR_OOB_CRX_CFG_MODE__M 0x7 +#define SIO_PDR_OOB_CRX_CFG_MODE__PRE 0x0 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__B 3 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__W 3 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__M 0x38 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_OOB_CRX_CFG_KEEP__B 6 +#define SIO_PDR_OOB_CRX_CFG_KEEP__W 2 +#define SIO_PDR_OOB_CRX_CFG_KEEP__M 0xC0 +#define SIO_PDR_OOB_CRX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_OOB_CRX_CFG_UIO__B 8 +#define SIO_PDR_OOB_CRX_CFG_UIO__W 1 +#define SIO_PDR_OOB_CRX_CFG_UIO__M 0x100 +#define SIO_PDR_OOB_CRX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_OOB_DRX_CFG__A 0x7F0024 +#define SIO_PDR_OOB_DRX_CFG__W 9 +#define SIO_PDR_OOB_DRX_CFG__M 0x1FF +#define SIO_PDR_OOB_DRX_CFG__PRE 0x10 +#define SIO_PDR_OOB_DRX_CFG_MODE__B 0 +#define SIO_PDR_OOB_DRX_CFG_MODE__W 3 +#define SIO_PDR_OOB_DRX_CFG_MODE__M 0x7 +#define SIO_PDR_OOB_DRX_CFG_MODE__PRE 0x0 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__B 3 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__W 3 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__M 0x38 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_OOB_DRX_CFG_KEEP__B 6 +#define SIO_PDR_OOB_DRX_CFG_KEEP__W 2 +#define SIO_PDR_OOB_DRX_CFG_KEEP__M 0xC0 +#define SIO_PDR_OOB_DRX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_OOB_DRX_CFG_UIO__B 8 +#define SIO_PDR_OOB_DRX_CFG_UIO__W 1 +#define SIO_PDR_OOB_DRX_CFG_UIO__M 0x100 +#define SIO_PDR_OOB_DRX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MSTRT_CFG__A 0x7F0025 +#define SIO_PDR_MSTRT_CFG__W 9 +#define SIO_PDR_MSTRT_CFG__M 0x1FF +#define SIO_PDR_MSTRT_CFG__PRE 0x50 +#define SIO_PDR_MSTRT_CFG_MODE__B 0 +#define SIO_PDR_MSTRT_CFG_MODE__W 3 +#define SIO_PDR_MSTRT_CFG_MODE__M 0x7 +#define SIO_PDR_MSTRT_CFG_MODE__PRE 0x0 +#define SIO_PDR_MSTRT_CFG_DRIVE__B 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__W 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__M 0x38 +#define SIO_PDR_MSTRT_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MSTRT_CFG_KEEP__B 6 +#define SIO_PDR_MSTRT_CFG_KEEP__W 2 +#define SIO_PDR_MSTRT_CFG_KEEP__M 0xC0 +#define SIO_PDR_MSTRT_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MSTRT_CFG_UIO__B 8 +#define SIO_PDR_MSTRT_CFG_UIO__W 1 +#define SIO_PDR_MSTRT_CFG_UIO__M 0x100 +#define SIO_PDR_MSTRT_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MERR_CFG__A 0x7F0026 +#define SIO_PDR_MERR_CFG__W 9 +#define SIO_PDR_MERR_CFG__M 0x1FF +#define SIO_PDR_MERR_CFG__PRE 0x50 +#define SIO_PDR_MERR_CFG_MODE__B 0 +#define SIO_PDR_MERR_CFG_MODE__W 3 +#define SIO_PDR_MERR_CFG_MODE__M 0x7 +#define SIO_PDR_MERR_CFG_MODE__PRE 0x0 +#define SIO_PDR_MERR_CFG_DRIVE__B 3 +#define SIO_PDR_MERR_CFG_DRIVE__W 3 +#define SIO_PDR_MERR_CFG_DRIVE__M 0x38 +#define SIO_PDR_MERR_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MERR_CFG_KEEP__B 6 +#define SIO_PDR_MERR_CFG_KEEP__W 2 +#define SIO_PDR_MERR_CFG_KEEP__M 0xC0 +#define SIO_PDR_MERR_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MERR_CFG_UIO__B 8 +#define SIO_PDR_MERR_CFG_UIO__W 1 +#define SIO_PDR_MERR_CFG_UIO__M 0x100 +#define SIO_PDR_MERR_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MCLK_CFG__A 0x7F0028 +#define SIO_PDR_MCLK_CFG__W 9 +#define SIO_PDR_MCLK_CFG__M 0x1FF +#define SIO_PDR_MCLK_CFG__PRE 0x50 +#define SIO_PDR_MCLK_CFG_MODE__B 0 +#define SIO_PDR_MCLK_CFG_MODE__W 3 +#define SIO_PDR_MCLK_CFG_MODE__M 0x7 +#define SIO_PDR_MCLK_CFG_MODE__PRE 0x0 +#define SIO_PDR_MCLK_CFG_DRIVE__B 3 +#define SIO_PDR_MCLK_CFG_DRIVE__W 3 +#define SIO_PDR_MCLK_CFG_DRIVE__M 0x38 +#define SIO_PDR_MCLK_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MCLK_CFG_KEEP__B 6 +#define SIO_PDR_MCLK_CFG_KEEP__W 2 +#define SIO_PDR_MCLK_CFG_KEEP__M 0xC0 +#define SIO_PDR_MCLK_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MCLK_CFG_UIO__B 8 +#define SIO_PDR_MCLK_CFG_UIO__W 1 +#define SIO_PDR_MCLK_CFG_UIO__M 0x100 +#define SIO_PDR_MCLK_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MVAL_CFG__A 0x7F0029 +#define SIO_PDR_MVAL_CFG__W 9 +#define SIO_PDR_MVAL_CFG__M 0x1FF +#define SIO_PDR_MVAL_CFG__PRE 0x50 +#define SIO_PDR_MVAL_CFG_MODE__B 0 +#define SIO_PDR_MVAL_CFG_MODE__W 3 +#define SIO_PDR_MVAL_CFG_MODE__M 0x7 +#define SIO_PDR_MVAL_CFG_MODE__PRE 0x0 +#define SIO_PDR_MVAL_CFG_DRIVE__B 3 +#define SIO_PDR_MVAL_CFG_DRIVE__W 3 +#define SIO_PDR_MVAL_CFG_DRIVE__M 0x38 +#define SIO_PDR_MVAL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MVAL_CFG_KEEP__B 6 +#define SIO_PDR_MVAL_CFG_KEEP__W 2 +#define SIO_PDR_MVAL_CFG_KEEP__M 0xC0 +#define SIO_PDR_MVAL_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MVAL_CFG_UIO__B 8 +#define SIO_PDR_MVAL_CFG_UIO__W 1 +#define SIO_PDR_MVAL_CFG_UIO__M 0x100 +#define SIO_PDR_MVAL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD0_CFG__A 0x7F002A +#define SIO_PDR_MD0_CFG__W 9 +#define SIO_PDR_MD0_CFG__M 0x1FF +#define SIO_PDR_MD0_CFG__PRE 0x50 +#define SIO_PDR_MD0_CFG_MODE__B 0 +#define SIO_PDR_MD0_CFG_MODE__W 3 +#define SIO_PDR_MD0_CFG_MODE__M 0x7 +#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD0_CFG_DRIVE__B 3 +#define SIO_PDR_MD0_CFG_DRIVE__W 3 +#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD0_CFG_KEEP__B 6 +#define SIO_PDR_MD0_CFG_KEEP__W 2 +#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD0_CFG_UIO__B 8 +#define SIO_PDR_MD0_CFG_UIO__W 1 +#define SIO_PDR_MD0_CFG_UIO__M 0x100 +#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD1_CFG__A 0x7F002B +#define SIO_PDR_MD1_CFG__W 9 +#define SIO_PDR_MD1_CFG__M 0x1FF +#define SIO_PDR_MD1_CFG__PRE 0x50 +#define SIO_PDR_MD1_CFG_MODE__B 0 +#define SIO_PDR_MD1_CFG_MODE__W 3 +#define SIO_PDR_MD1_CFG_MODE__M 0x7 +#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD1_CFG_DRIVE__B 3 +#define SIO_PDR_MD1_CFG_DRIVE__W 3 +#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD1_CFG_KEEP__B 6 +#define SIO_PDR_MD1_CFG_KEEP__W 2 +#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD1_CFG_UIO__B 8 +#define SIO_PDR_MD1_CFG_UIO__W 1 +#define SIO_PDR_MD1_CFG_UIO__M 0x100 +#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD2_CFG__A 0x7F002C +#define SIO_PDR_MD2_CFG__W 9 +#define SIO_PDR_MD2_CFG__M 0x1FF +#define SIO_PDR_MD2_CFG__PRE 0x50 +#define SIO_PDR_MD2_CFG_MODE__B 0 +#define SIO_PDR_MD2_CFG_MODE__W 3 +#define SIO_PDR_MD2_CFG_MODE__M 0x7 +#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD2_CFG_DRIVE__B 3 +#define SIO_PDR_MD2_CFG_DRIVE__W 3 +#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD2_CFG_KEEP__B 6 +#define SIO_PDR_MD2_CFG_KEEP__W 2 +#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD2_CFG_UIO__B 8 +#define SIO_PDR_MD2_CFG_UIO__W 1 +#define SIO_PDR_MD2_CFG_UIO__M 0x100 +#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD3_CFG__A 0x7F002D +#define SIO_PDR_MD3_CFG__W 9 +#define SIO_PDR_MD3_CFG__M 0x1FF +#define SIO_PDR_MD3_CFG__PRE 0x50 +#define SIO_PDR_MD3_CFG_MODE__B 0 +#define SIO_PDR_MD3_CFG_MODE__W 3 +#define SIO_PDR_MD3_CFG_MODE__M 0x7 +#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD3_CFG_DRIVE__B 3 +#define SIO_PDR_MD3_CFG_DRIVE__W 3 +#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD3_CFG_KEEP__B 6 +#define SIO_PDR_MD3_CFG_KEEP__W 2 +#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD3_CFG_UIO__B 8 +#define SIO_PDR_MD3_CFG_UIO__W 1 +#define SIO_PDR_MD3_CFG_UIO__M 0x100 +#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD4_CFG__A 0x7F002F +#define SIO_PDR_MD4_CFG__W 9 +#define SIO_PDR_MD4_CFG__M 0x1FF +#define SIO_PDR_MD4_CFG__PRE 0x50 +#define SIO_PDR_MD4_CFG_MODE__B 0 +#define SIO_PDR_MD4_CFG_MODE__W 3 +#define SIO_PDR_MD4_CFG_MODE__M 0x7 +#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD4_CFG_DRIVE__B 3 +#define SIO_PDR_MD4_CFG_DRIVE__W 3 +#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD4_CFG_KEEP__B 6 +#define SIO_PDR_MD4_CFG_KEEP__W 2 +#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD4_CFG_UIO__B 8 +#define SIO_PDR_MD4_CFG_UIO__W 1 +#define SIO_PDR_MD4_CFG_UIO__M 0x100 +#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD5_CFG__A 0x7F0030 +#define SIO_PDR_MD5_CFG__W 9 +#define SIO_PDR_MD5_CFG__M 0x1FF +#define SIO_PDR_MD5_CFG__PRE 0x50 +#define SIO_PDR_MD5_CFG_MODE__B 0 +#define SIO_PDR_MD5_CFG_MODE__W 3 +#define SIO_PDR_MD5_CFG_MODE__M 0x7 +#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD5_CFG_DRIVE__B 3 +#define SIO_PDR_MD5_CFG_DRIVE__W 3 +#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD5_CFG_KEEP__B 6 +#define SIO_PDR_MD5_CFG_KEEP__W 2 +#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD5_CFG_UIO__B 8 +#define SIO_PDR_MD5_CFG_UIO__W 1 +#define SIO_PDR_MD5_CFG_UIO__M 0x100 +#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD6_CFG__A 0x7F0031 +#define SIO_PDR_MD6_CFG__W 9 +#define SIO_PDR_MD6_CFG__M 0x1FF +#define SIO_PDR_MD6_CFG__PRE 0x50 +#define SIO_PDR_MD6_CFG_MODE__B 0 +#define SIO_PDR_MD6_CFG_MODE__W 3 +#define SIO_PDR_MD6_CFG_MODE__M 0x7 +#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD6_CFG_DRIVE__B 3 +#define SIO_PDR_MD6_CFG_DRIVE__W 3 +#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD6_CFG_KEEP__B 6 +#define SIO_PDR_MD6_CFG_KEEP__W 2 +#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD6_CFG_UIO__B 8 +#define SIO_PDR_MD6_CFG_UIO__W 1 +#define SIO_PDR_MD6_CFG_UIO__M 0x100 +#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD7_CFG__A 0x7F0032 +#define SIO_PDR_MD7_CFG__W 9 +#define SIO_PDR_MD7_CFG__M 0x1FF +#define SIO_PDR_MD7_CFG__PRE 0x50 +#define SIO_PDR_MD7_CFG_MODE__B 0 +#define SIO_PDR_MD7_CFG_MODE__W 3 +#define SIO_PDR_MD7_CFG_MODE__M 0x7 +#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD7_CFG_DRIVE__B 3 +#define SIO_PDR_MD7_CFG_DRIVE__W 3 +#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD7_CFG_KEEP__B 6 +#define SIO_PDR_MD7_CFG_KEEP__W 2 +#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD7_CFG_UIO__B 8 +#define SIO_PDR_MD7_CFG_UIO__W 1 +#define SIO_PDR_MD7_CFG_UIO__M 0x100 +#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL1_CFG__A 0x7F0033 +#define SIO_PDR_I2C_SCL1_CFG__W 9 +#define SIO_PDR_I2C_SCL1_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA1_CFG__A 0x7F0034 +#define SIO_PDR_I2C_SDA1_CFG__W 9 +#define SIO_PDR_I2C_SDA1_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_VSYNC_CFG__A 0x7F0036 +#define SIO_PDR_VSYNC_CFG__W 9 +#define SIO_PDR_VSYNC_CFG__M 0x1FF +#define SIO_PDR_VSYNC_CFG__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_MODE__B 0 +#define SIO_PDR_VSYNC_CFG_MODE__W 3 +#define SIO_PDR_VSYNC_CFG_MODE__M 0x7 +#define SIO_PDR_VSYNC_CFG_MODE__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_DRIVE__B 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__W 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__M 0x38 +#define SIO_PDR_VSYNC_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_KEEP__B 6 +#define SIO_PDR_VSYNC_CFG_KEEP__W 2 +#define SIO_PDR_VSYNC_CFG_KEEP__M 0xC0 +#define SIO_PDR_VSYNC_CFG_KEEP__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_UIO__B 8 +#define SIO_PDR_VSYNC_CFG_UIO__W 1 +#define SIO_PDR_VSYNC_CFG_UIO__M 0x100 +#define SIO_PDR_VSYNC_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_RX_CFG__A 0x7F0037 +#define SIO_PDR_SMA_RX_CFG__W 9 +#define SIO_PDR_SMA_RX_CFG__M 0x1FF +#define SIO_PDR_SMA_RX_CFG__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_MODE__B 0 +#define SIO_PDR_SMA_RX_CFG_MODE__W 3 +#define SIO_PDR_SMA_RX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_RX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_RX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_RX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_RX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_RX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_UIO__B 8 +#define SIO_PDR_SMA_RX_CFG_UIO__W 1 +#define SIO_PDR_SMA_RX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_RX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 +#define SIO_PDR_SMA_TX_CFG__W 9 +#define SIO_PDR_SMA_TX_CFG__M 0x1FF +#define SIO_PDR_SMA_TX_CFG__PRE 0x90 +#define SIO_PDR_SMA_TX_CFG_MODE__B 0 +#define SIO_PDR_SMA_TX_CFG_MODE__W 3 +#define SIO_PDR_SMA_TX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_TX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_TX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_TX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_TX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_TX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_TX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_TX_CFG_KEEP__PRE 0x80 +#define SIO_PDR_SMA_TX_CFG_UIO__B 8 +#define SIO_PDR_SMA_TX_CFG_UIO__W 1 +#define SIO_PDR_SMA_TX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_TX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA2_CFG__A 0x7F003F +#define SIO_PDR_I2C_SDA2_CFG__W 9 +#define SIO_PDR_I2C_SDA2_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL2_CFG__A 0x7F0040 +#define SIO_PDR_I2C_SCL2_CFG__W 9 +#define SIO_PDR_I2C_SCL2_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_CL_CFG__A 0x7F0041 +#define SIO_PDR_I2S_CL_CFG__W 9 +#define SIO_PDR_I2S_CL_CFG__M 0x1FF +#define SIO_PDR_I2S_CL_CFG__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_MODE__B 0 +#define SIO_PDR_I2S_CL_CFG_MODE__W 3 +#define SIO_PDR_I2S_CL_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_CL_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_CL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_KEEP__B 6 +#define SIO_PDR_I2S_CL_CFG_KEEP__W 2 +#define SIO_PDR_I2S_CL_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_CL_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_UIO__B 8 +#define SIO_PDR_I2S_CL_CFG_UIO__W 1 +#define SIO_PDR_I2S_CL_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_CL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_DA_CFG__A 0x7F0042 +#define SIO_PDR_I2S_DA_CFG__W 9 +#define SIO_PDR_I2S_DA_CFG__M 0x1FF +#define SIO_PDR_I2S_DA_CFG__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_MODE__B 0 +#define SIO_PDR_I2S_DA_CFG_MODE__W 3 +#define SIO_PDR_I2S_DA_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_DA_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_DA_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_KEEP__B 6 +#define SIO_PDR_I2S_DA_CFG_KEEP__W 2 +#define SIO_PDR_I2S_DA_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_DA_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_UIO__B 8 +#define SIO_PDR_I2S_DA_CFG_UIO__W 1 +#define SIO_PDR_I2S_DA_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_DA_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_GPIO_FNC__A 0x7F0050 +#define SIO_PDR_GPIO_GPIO_FNC__W 2 +#define SIO_PDR_GPIO_GPIO_FNC__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC__PRE 0x0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__B 0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__W 2 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_IRQN_GPIO_FNC__A 0x7F0051 +#define SIO_PDR_IRQN_GPIO_FNC__W 2 +#define SIO_PDR_IRQN_GPIO_FNC__M 0x3 +#define SIO_PDR_IRQN_GPIO_FNC__PRE 0x0 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__B 0 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__W 2 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MSTRT_GPIO_FNC__A 0x7F0052 +#define SIO_PDR_MSTRT_GPIO_FNC__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MERR_GPIO_FNC__A 0x7F0053 +#define SIO_PDR_MERR_GPIO_FNC__W 2 +#define SIO_PDR_MERR_GPIO_FNC__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MERR_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MCLK_GPIO_FNC__A 0x7F0054 +#define SIO_PDR_MCLK_GPIO_FNC__W 2 +#define SIO_PDR_MCLK_GPIO_FNC__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MVAL_GPIO_FNC__A 0x7F0055 +#define SIO_PDR_MVAL_GPIO_FNC__W 2 +#define SIO_PDR_MVAL_GPIO_FNC__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 +#define SIO_PDR_MD0_GPIO_FNC__W 2 +#define SIO_PDR_MD0_GPIO_FNC__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 +#define SIO_PDR_MD1_GPIO_FNC__W 2 +#define SIO_PDR_MD1_GPIO_FNC__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 +#define SIO_PDR_MD2_GPIO_FNC__W 2 +#define SIO_PDR_MD2_GPIO_FNC__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 +#define SIO_PDR_MD3_GPIO_FNC__W 2 +#define SIO_PDR_MD3_GPIO_FNC__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A +#define SIO_PDR_MD4_GPIO_FNC__W 2 +#define SIO_PDR_MD4_GPIO_FNC__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B +#define SIO_PDR_MD5_GPIO_FNC__W 2 +#define SIO_PDR_MD5_GPIO_FNC__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C +#define SIO_PDR_MD6_GPIO_FNC__W 2 +#define SIO_PDR_MD6_GPIO_FNC__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D +#define SIO_PDR_MD7_GPIO_FNC__W 2 +#define SIO_PDR_MD7_GPIO_FNC__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_GPIO_FNC__A 0x7F005E +#define SIO_PDR_SMA_RX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_TX_GPIO_FNC__A 0x7F005F +#define SIO_PDR_SMA_TX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0 + +#define VSB_COMM_EXEC__A 0x1C00000 +#define VSB_COMM_EXEC__W 2 +#define VSB_COMM_EXEC__M 0x3 +#define VSB_COMM_EXEC__PRE 0x0 +#define VSB_COMM_EXEC_STOP 0x0 +#define VSB_COMM_EXEC_ACTIVE 0x1 +#define VSB_COMM_EXEC_HOLD 0x2 + +#define VSB_COMM_MB__A 0x1C00002 +#define VSB_COMM_MB__W 16 +#define VSB_COMM_MB__M 0xFFFF +#define VSB_COMM_MB__PRE 0x0 +#define VSB_COMM_INT_REQ__A 0x1C00003 +#define VSB_COMM_INT_REQ__W 1 +#define VSB_COMM_INT_REQ__M 0x1 +#define VSB_COMM_INT_REQ__PRE 0x0 + +#define VSB_COMM_INT_REQ_TOP_INT_REQ__B 0 +#define VSB_COMM_INT_REQ_TOP_INT_REQ__W 1 +#define VSB_COMM_INT_REQ_TOP_INT_REQ__M 0x1 +#define VSB_COMM_INT_REQ_TOP_INT_REQ__PRE 0x0 + +#define VSB_COMM_INT_STA__A 0x1C00005 +#define VSB_COMM_INT_STA__W 16 +#define VSB_COMM_INT_STA__M 0xFFFF +#define VSB_COMM_INT_STA__PRE 0x0 + +#define VSB_COMM_INT_MSK__A 0x1C00006 +#define VSB_COMM_INT_MSK__W 16 +#define VSB_COMM_INT_MSK__M 0xFFFF +#define VSB_COMM_INT_MSK__PRE 0x0 + +#define VSB_COMM_INT_STM__A 0x1C00007 +#define VSB_COMM_INT_STM__W 16 +#define VSB_COMM_INT_STM__M 0xFFFF +#define VSB_COMM_INT_STM__PRE 0x0 + +#define VSB_TOP_COMM_EXEC__A 0x1C10000 +#define VSB_TOP_COMM_EXEC__W 2 +#define VSB_TOP_COMM_EXEC__M 0x3 +#define VSB_TOP_COMM_EXEC__PRE 0x0 +#define VSB_TOP_COMM_EXEC_STOP 0x0 +#define VSB_TOP_COMM_EXEC_ACTIVE 0x1 +#define VSB_TOP_COMM_EXEC_HOLD 0x2 + +#define VSB_TOP_COMM_MB__A 0x1C10002 +#define VSB_TOP_COMM_MB__W 10 +#define VSB_TOP_COMM_MB__M 0x3FF +#define VSB_TOP_COMM_MB__PRE 0x0 + +#define VSB_TOP_COMM_MB_CTL__B 0 +#define VSB_TOP_COMM_MB_CTL__W 1 +#define VSB_TOP_COMM_MB_CTL__M 0x1 +#define VSB_TOP_COMM_MB_CTL__PRE 0x0 +#define VSB_TOP_COMM_MB_CTL_CTL_OFF 0x0 +#define VSB_TOP_COMM_MB_CTL_CTL_ON 0x1 + +#define VSB_TOP_COMM_MB_OBS__B 1 +#define VSB_TOP_COMM_MB_OBS__W 1 +#define VSB_TOP_COMM_MB_OBS__M 0x2 +#define VSB_TOP_COMM_MB_OBS__PRE 0x0 +#define VSB_TOP_COMM_MB_OBS_OBS_OFF 0x0 +#define VSB_TOP_COMM_MB_OBS_OBS_ON 0x2 + +#define VSB_TOP_COMM_MB_MUX_CTL__B 2 +#define VSB_TOP_COMM_MB_MUX_CTL__W 4 +#define VSB_TOP_COMM_MB_MUX_CTL__M 0x3C +#define VSB_TOP_COMM_MB_MUX_CTL__PRE 0x0 + +#define VSB_TOP_COMM_MB_MUX_OBS__B 6 +#define VSB_TOP_COMM_MB_MUX_OBS__W 4 +#define VSB_TOP_COMM_MB_MUX_OBS__M 0x3C0 +#define VSB_TOP_COMM_MB_MUX_OBS__PRE 0x0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FEC 0x0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM 0x40 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM_AMPLITUDE 0x80 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_1 0xC0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2 0x100 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_1 0x140 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_2 0x180 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_1 0x1C0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_2 0x200 + +#define VSB_TOP_COMM_INT_REQ__A 0x1C10003 +#define VSB_TOP_COMM_INT_REQ__W 1 +#define VSB_TOP_COMM_INT_REQ__M 0x1 +#define VSB_TOP_COMM_INT_REQ__PRE 0x0 +#define VSB_TOP_COMM_INT_STA__A 0x1C10005 +#define VSB_TOP_COMM_INT_STA__W 6 +#define VSB_TOP_COMM_INT_STA__M 0x3F +#define VSB_TOP_COMM_INT_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__B 0 +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__W 1 +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__M 0x1 +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_LOCK_STA__B 1 +#define VSB_TOP_COMM_INT_STA_LOCK_STA__W 1 +#define VSB_TOP_COMM_INT_STA_LOCK_STA__M 0x2 +#define VSB_TOP_COMM_INT_STA_LOCK_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__B 2 +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__W 1 +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__M 0x4 +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__B 3 +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__W 1 +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__M 0x8 +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__B 4 +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__W 1 +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__M 0x10 +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_MERSER_STA__B 5 +#define VSB_TOP_COMM_INT_STA_MERSER_STA__W 1 +#define VSB_TOP_COMM_INT_STA_MERSER_STA__M 0x20 +#define VSB_TOP_COMM_INT_STA_MERSER_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK__A 0x1C10006 +#define VSB_TOP_COMM_INT_MSK__W 6 +#define VSB_TOP_COMM_INT_MSK__M 0x3F +#define VSB_TOP_COMM_INT_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__B 0 +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__M 0x1 +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__B 1 +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__M 0x2 +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__B 2 +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__M 0x4 +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__B 3 +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__M 0x8 +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__B 4 +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__M 0x10 +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__B 5 +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__M 0x20 +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM__A 0x1C10007 +#define VSB_TOP_COMM_INT_STM__W 6 +#define VSB_TOP_COMM_INT_STM__M 0x3F +#define VSB_TOP_COMM_INT_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__B 0 +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__W 1 +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__M 0x1 +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_LOCK_STM__B 1 +#define VSB_TOP_COMM_INT_STM_LOCK_STM__W 1 +#define VSB_TOP_COMM_INT_STM_LOCK_STM__M 0x2 +#define VSB_TOP_COMM_INT_STM_LOCK_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__B 2 +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__W 1 +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__M 0x4 +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__B 3 +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__W 1 +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__M 0x8 +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__B 4 +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__W 1 +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__M 0x10 +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_MERSER_STM__B 5 +#define VSB_TOP_COMM_INT_STM_MERSER_STM__W 1 +#define VSB_TOP_COMM_INT_STM_MERSER_STM__M 0x20 +#define VSB_TOP_COMM_INT_STM_MERSER_STM__PRE 0x0 + +#define VSB_TOP_CKGN1ACQ__A 0x1C10010 +#define VSB_TOP_CKGN1ACQ__W 8 +#define VSB_TOP_CKGN1ACQ__M 0xFF +#define VSB_TOP_CKGN1ACQ__PRE 0x4 + +#define VSB_TOP_CKGN1TRK__A 0x1C10011 +#define VSB_TOP_CKGN1TRK__W 8 +#define VSB_TOP_CKGN1TRK__M 0xFF +#define VSB_TOP_CKGN1TRK__PRE 0x0 + +#define VSB_TOP_CKGN2ACQ__A 0x1C10012 +#define VSB_TOP_CKGN2ACQ__W 8 +#define VSB_TOP_CKGN2ACQ__M 0xFF +#define VSB_TOP_CKGN2ACQ__PRE 0x2 + +#define VSB_TOP_CKGN2TRK__A 0x1C10013 +#define VSB_TOP_CKGN2TRK__W 8 +#define VSB_TOP_CKGN2TRK__M 0xFF +#define VSB_TOP_CKGN2TRK__PRE 0x1 + +#define VSB_TOP_CKGN3__A 0x1C10014 +#define VSB_TOP_CKGN3__W 8 +#define VSB_TOP_CKGN3__M 0xFF +#define VSB_TOP_CKGN3__PRE 0x5 + +#define VSB_TOP_CYGN1ACQ__A 0x1C10015 +#define VSB_TOP_CYGN1ACQ__W 8 +#define VSB_TOP_CYGN1ACQ__M 0xFF +#define VSB_TOP_CYGN1ACQ__PRE 0x3 + +#define VSB_TOP_CYGN1TRK__A 0x1C10016 +#define VSB_TOP_CYGN1TRK__W 8 +#define VSB_TOP_CYGN1TRK__M 0xFF +#define VSB_TOP_CYGN1TRK__PRE 0x0 + +#define VSB_TOP_CYGN2ACQ__A 0x1C10017 +#define VSB_TOP_CYGN2ACQ__W 8 +#define VSB_TOP_CYGN2ACQ__M 0xFF +#define VSB_TOP_CYGN2ACQ__PRE 0x3 + +#define VSB_TOP_CYGN2TRK__A 0x1C10018 +#define VSB_TOP_CYGN2TRK__W 8 +#define VSB_TOP_CYGN2TRK__M 0xFF +#define VSB_TOP_CYGN2TRK__PRE 0x2 + +#define VSB_TOP_CYGN3__A 0x1C10019 +#define VSB_TOP_CYGN3__W 8 +#define VSB_TOP_CYGN3__M 0xFF +#define VSB_TOP_CYGN3__PRE 0x6 +#define VSB_TOP_SYNCCTRLWORD__A 0x1C1001A +#define VSB_TOP_SYNCCTRLWORD__W 5 +#define VSB_TOP_SYNCCTRLWORD__M 0x1F +#define VSB_TOP_SYNCCTRLWORD__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_PRST__B 0 +#define VSB_TOP_SYNCCTRLWORD_PRST__W 1 +#define VSB_TOP_SYNCCTRLWORD_PRST__M 0x1 +#define VSB_TOP_SYNCCTRLWORD_PRST__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__B 1 +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__W 1 +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__M 0x2 +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_INVCNST__B 2 +#define VSB_TOP_SYNCCTRLWORD_INVCNST__W 1 +#define VSB_TOP_SYNCCTRLWORD_INVCNST__M 0x4 +#define VSB_TOP_SYNCCTRLWORD_INVCNST__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__B 3 +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__W 1 +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__M 0x8 +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__B 4 +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__W 1 +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__M 0x10 +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__PRE 0x0 + +#define VSB_TOP_MAINSMUP__A 0x1C1001B +#define VSB_TOP_MAINSMUP__W 8 +#define VSB_TOP_MAINSMUP__M 0xFF +#define VSB_TOP_MAINSMUP__PRE 0xFF + +#define VSB_TOP_EQSMUP__A 0x1C1001C +#define VSB_TOP_EQSMUP__W 8 +#define VSB_TOP_EQSMUP__M 0xFF +#define VSB_TOP_EQSMUP__PRE 0xFF +#define VSB_TOP_SYSMUXCTRL__A 0x1C1001D +#define VSB_TOP_SYSMUXCTRL__W 13 +#define VSB_TOP_SYSMUXCTRL__M 0x1FFF +#define VSB_TOP_SYSMUXCTRL__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__B 0 +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__M 0x1 +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__B 1 +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__M 0x2 +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__B 2 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__M 0x4 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__B 3 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__M 0x8 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__B 4 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__M 0x10 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__B 5 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__M 0x20 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__B 6 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__M 0x40 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__B 7 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__M 0x80 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__B 8 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__W 4 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__M 0xF00 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__B 12 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__M 0x1000 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SNRTH_RCA1__A 0x1C1001E +#define VSB_TOP_SNRTH_RCA1__W 8 +#define VSB_TOP_SNRTH_RCA1__M 0xFF +#define VSB_TOP_SNRTH_RCA1__PRE 0x53 + +#define VSB_TOP_SNRTH_RCA1_DN__B 0 +#define VSB_TOP_SNRTH_RCA1_DN__W 4 +#define VSB_TOP_SNRTH_RCA1_DN__M 0xF +#define VSB_TOP_SNRTH_RCA1_DN__PRE 0x3 + +#define VSB_TOP_SNRTH_RCA1_UP__B 4 +#define VSB_TOP_SNRTH_RCA1_UP__W 4 +#define VSB_TOP_SNRTH_RCA1_UP__M 0xF0 +#define VSB_TOP_SNRTH_RCA1_UP__PRE 0x50 + +#define VSB_TOP_SNRTH_RCA2__A 0x1C1001F +#define VSB_TOP_SNRTH_RCA2__W 8 +#define VSB_TOP_SNRTH_RCA2__M 0xFF +#define VSB_TOP_SNRTH_RCA2__PRE 0x75 + +#define VSB_TOP_SNRTH_RCA2_DN__B 0 +#define VSB_TOP_SNRTH_RCA2_DN__W 4 +#define VSB_TOP_SNRTH_RCA2_DN__M 0xF +#define VSB_TOP_SNRTH_RCA2_DN__PRE 0x5 + +#define VSB_TOP_SNRTH_RCA2_UP__B 4 +#define VSB_TOP_SNRTH_RCA2_UP__W 4 +#define VSB_TOP_SNRTH_RCA2_UP__M 0xF0 +#define VSB_TOP_SNRTH_RCA2_UP__PRE 0x70 + +#define VSB_TOP_SNRTH_DDM1__A 0x1C10020 +#define VSB_TOP_SNRTH_DDM1__W 8 +#define VSB_TOP_SNRTH_DDM1__M 0xFF +#define VSB_TOP_SNRTH_DDM1__PRE 0xCA + +#define VSB_TOP_SNRTH_DDM1_DN__B 0 +#define VSB_TOP_SNRTH_DDM1_DN__W 4 +#define VSB_TOP_SNRTH_DDM1_DN__M 0xF +#define VSB_TOP_SNRTH_DDM1_DN__PRE 0xA + +#define VSB_TOP_SNRTH_DDM1_UP__B 4 +#define VSB_TOP_SNRTH_DDM1_UP__W 4 +#define VSB_TOP_SNRTH_DDM1_UP__M 0xF0 +#define VSB_TOP_SNRTH_DDM1_UP__PRE 0xC0 + +#define VSB_TOP_SNRTH_DDM2__A 0x1C10021 +#define VSB_TOP_SNRTH_DDM2__W 8 +#define VSB_TOP_SNRTH_DDM2__M 0xFF +#define VSB_TOP_SNRTH_DDM2__PRE 0xCA + +#define VSB_TOP_SNRTH_DDM2_DN__B 0 +#define VSB_TOP_SNRTH_DDM2_DN__W 4 +#define VSB_TOP_SNRTH_DDM2_DN__M 0xF +#define VSB_TOP_SNRTH_DDM2_DN__PRE 0xA + +#define VSB_TOP_SNRTH_DDM2_UP__B 4 +#define VSB_TOP_SNRTH_DDM2_UP__W 4 +#define VSB_TOP_SNRTH_DDM2_UP__M 0xF0 +#define VSB_TOP_SNRTH_DDM2_UP__PRE 0xC0 + +#define VSB_TOP_SNRTH_PT__A 0x1C10022 +#define VSB_TOP_SNRTH_PT__W 8 +#define VSB_TOP_SNRTH_PT__M 0xFF +#define VSB_TOP_SNRTH_PT__PRE 0xD8 + +#define VSB_TOP_SNRTH_PT_DN__B 0 +#define VSB_TOP_SNRTH_PT_DN__W 4 +#define VSB_TOP_SNRTH_PT_DN__M 0xF +#define VSB_TOP_SNRTH_PT_DN__PRE 0x8 + +#define VSB_TOP_SNRTH_PT_UP__B 4 +#define VSB_TOP_SNRTH_PT_UP__W 4 +#define VSB_TOP_SNRTH_PT_UP__M 0xF0 +#define VSB_TOP_SNRTH_PT_UP__PRE 0xD0 + +#define VSB_TOP_CYSMSTATES__A 0x1C10023 +#define VSB_TOP_CYSMSTATES__W 8 +#define VSB_TOP_CYSMSTATES__M 0xFF +#define VSB_TOP_CYSMSTATES__PRE 0x0 + +#define VSB_TOP_CYSMSTATES_SYSST__B 0 +#define VSB_TOP_CYSMSTATES_SYSST__W 4 +#define VSB_TOP_CYSMSTATES_SYSST__M 0xF +#define VSB_TOP_CYSMSTATES_SYSST__PRE 0x0 + +#define VSB_TOP_CYSMSTATES_EQST__B 4 +#define VSB_TOP_CYSMSTATES_EQST__W 4 +#define VSB_TOP_CYSMSTATES_EQST__M 0xF0 +#define VSB_TOP_CYSMSTATES_EQST__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL__A 0x1C10024 +#define VSB_TOP_SMALL_NOTCH_CONTROL__W 8 +#define VSB_TOP_SMALL_NOTCH_CONTROL__M 0xFF +#define VSB_TOP_SMALL_NOTCH_CONTROL__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__B 0 +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__M 0x1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__B 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__M 0x2 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__B 2 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__M 0x4 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__B 3 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__W 4 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__M 0x78 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__B 7 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__M 0x80 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__PRE 0x0 + +#define VSB_TOP_TAPREADCYC__A 0x1C10025 +#define VSB_TOP_TAPREADCYC__W 9 +#define VSB_TOP_TAPREADCYC__M 0x1FF +#define VSB_TOP_TAPREADCYC__PRE 0x1 + +#define VSB_TOP_VALIDPKLVL__A 0x1C10026 +#define VSB_TOP_VALIDPKLVL__W 13 +#define VSB_TOP_VALIDPKLVL__M 0x1FFF +#define VSB_TOP_VALIDPKLVL__PRE 0x100 + +#define VSB_TOP_CENTROID_FINE_DELAY__A 0x1C10027 +#define VSB_TOP_CENTROID_FINE_DELAY__W 10 +#define VSB_TOP_CENTROID_FINE_DELAY__M 0x3FF +#define VSB_TOP_CENTROID_FINE_DELAY__PRE 0xFF + +#define VSB_TOP_CENTROID_SMACH_DELAY__A 0x1C10028 +#define VSB_TOP_CENTROID_SMACH_DELAY__W 10 +#define VSB_TOP_CENTROID_SMACH_DELAY__M 0x3FF +#define VSB_TOP_CENTROID_SMACH_DELAY__PRE 0x1FF + +#define VSB_TOP_SNR__A 0x1C10029 +#define VSB_TOP_SNR__W 14 +#define VSB_TOP_SNR__M 0x3FFF +#define VSB_TOP_SNR__PRE 0x0 +#define VSB_TOP_LOCKSTATUS__A 0x1C1002A +#define VSB_TOP_LOCKSTATUS__W 7 +#define VSB_TOP_LOCKSTATUS__M 0x7F +#define VSB_TOP_LOCKSTATUS__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_VSBMODE__B 0 +#define VSB_TOP_LOCKSTATUS_VSBMODE__W 4 +#define VSB_TOP_LOCKSTATUS_VSBMODE__M 0xF +#define VSB_TOP_LOCKSTATUS_VSBMODE__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_FRMLOCK__B 4 +#define VSB_TOP_LOCKSTATUS_FRMLOCK__W 1 +#define VSB_TOP_LOCKSTATUS_FRMLOCK__M 0x10 +#define VSB_TOP_LOCKSTATUS_FRMLOCK__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_CYLOCK__B 5 +#define VSB_TOP_LOCKSTATUS_CYLOCK__W 1 +#define VSB_TOP_LOCKSTATUS_CYLOCK__M 0x20 +#define VSB_TOP_LOCKSTATUS_CYLOCK__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_DDMON__B 6 +#define VSB_TOP_LOCKSTATUS_DDMON__W 1 +#define VSB_TOP_LOCKSTATUS_DDMON__M 0x40 +#define VSB_TOP_LOCKSTATUS_DDMON__PRE 0x0 + +#define VSB_TOP_CTST__A 0x1C1002B +#define VSB_TOP_CTST__W 4 +#define VSB_TOP_CTST__M 0xF +#define VSB_TOP_CTST__PRE 0x0 +#define VSB_TOP_EQSMRSTCTRL__A 0x1C1002C +#define VSB_TOP_EQSMRSTCTRL__W 7 +#define VSB_TOP_EQSMRSTCTRL__M 0x7F +#define VSB_TOP_EQSMRSTCTRL__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_RCAON__B 0 +#define VSB_TOP_EQSMRSTCTRL_RCAON__W 1 +#define VSB_TOP_EQSMRSTCTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMRSTCTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DFEON__B 1 +#define VSB_TOP_EQSMRSTCTRL_DFEON__W 1 +#define VSB_TOP_EQSMRSTCTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMRSTCTRL_DFEON__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL__A 0x1C1002D +#define VSB_TOP_EQSMTRNCTRL__W 7 +#define VSB_TOP_EQSMTRNCTRL__M 0x7F +#define VSB_TOP_EQSMTRNCTRL__PRE 0x40 + +#define VSB_TOP_EQSMTRNCTRL_RCAON__B 0 +#define VSB_TOP_EQSMTRNCTRL_RCAON__W 1 +#define VSB_TOP_EQSMTRNCTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMTRNCTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DFEON__B 1 +#define VSB_TOP_EQSMTRNCTRL_DFEON__W 1 +#define VSB_TOP_EQSMTRNCTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMTRNCTRL_DFEON__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__PRE 0x40 + +#define VSB_TOP_EQSMRCA1CTRL__A 0x1C1002E +#define VSB_TOP_EQSMRCA1CTRL__W 7 +#define VSB_TOP_EQSMRCA1CTRL__M 0x7F +#define VSB_TOP_EQSMRCA1CTRL__PRE 0x1 + +#define VSB_TOP_EQSMRCA1CTRL_RCAON__B 0 +#define VSB_TOP_EQSMRCA1CTRL_RCAON__W 1 +#define VSB_TOP_EQSMRCA1CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMRCA1CTRL_RCAON__PRE 0x1 + +#define VSB_TOP_EQSMRCA1CTRL_DFEON__B 1 +#define VSB_TOP_EQSMRCA1CTRL_DFEON__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMRCA1CTRL_DFEON__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL__A 0x1C1002F +#define VSB_TOP_EQSMRCA2CTRL__W 7 +#define VSB_TOP_EQSMRCA2CTRL__M 0x7F +#define VSB_TOP_EQSMRCA2CTRL__PRE 0x3 + +#define VSB_TOP_EQSMRCA2CTRL_RCAON__B 0 +#define VSB_TOP_EQSMRCA2CTRL_RCAON__W 1 +#define VSB_TOP_EQSMRCA2CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMRCA2CTRL_RCAON__PRE 0x1 + +#define VSB_TOP_EQSMRCA2CTRL_DFEON__B 1 +#define VSB_TOP_EQSMRCA2CTRL_DFEON__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMRCA2CTRL_DFEON__PRE 0x2 + +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL__A 0x1C10030 +#define VSB_TOP_EQSMDDM1CTRL__W 7 +#define VSB_TOP_EQSMDDM1CTRL__M 0x7F +#define VSB_TOP_EQSMDDM1CTRL__PRE 0x6 + +#define VSB_TOP_EQSMDDM1CTRL_RCAON__B 0 +#define VSB_TOP_EQSMDDM1CTRL_RCAON__W 1 +#define VSB_TOP_EQSMDDM1CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMDDM1CTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_DFEON__B 1 +#define VSB_TOP_EQSMDDM1CTRL_DFEON__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMDDM1CTRL_DFEON__PRE 0x2 + +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__PRE 0x4 + +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM2CTRL__A 0x1C10031 +#define VSB_TOP_EQSMDDM2CTRL__W 7 +#define VSB_TOP_EQSMDDM2CTRL__M 0x7F +#define VSB_TOP_EQSMDDM2CTRL__PRE 0x1E + +#define VSB_TOP_EQSMDDM2CTRL_RCAON__B 0 +#define VSB_TOP_EQSMDDM2CTRL_RCAON__W 1 +#define VSB_TOP_EQSMDDM2CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMDDM2CTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMDDM2CTRL_DFEON__B 1 +#define VSB_TOP_EQSMDDM2CTRL_DFEON__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMDDM2CTRL_DFEON__PRE 0x2 + +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__PRE 0x4 + +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__PRE 0x8 + +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__PRE 0x10 + +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMRSTCTRL__A 0x1C10032 +#define VSB_TOP_SYSSMRSTCTRL__W 11 +#define VSB_TOP_SYSSMRSTCTRL__M 0x7FF +#define VSB_TOP_SYSSMRSTCTRL__PRE 0x7F9 + +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__PRE 0x1 + +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__PRE 0x10 + +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__PRE 0x20 + +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__PRE 0x80 + +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__PRE 0x100 + +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__PRE 0x200 + +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__PRE 0x400 + +#define VSB_TOP_SYSSMCYCTRL__A 0x1C10033 +#define VSB_TOP_SYSSMCYCTRL__W 11 +#define VSB_TOP_SYSSMCYCTRL__M 0x7FF +#define VSB_TOP_SYSSMCYCTRL__PRE 0x4E9 + +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__PRE 0x1 + +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__PRE 0x20 + +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__PRE 0x80 + +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__PRE 0x400 + +#define VSB_TOP_SYSSMTRNCTRL__A 0x1C10034 +#define VSB_TOP_SYSSMTRNCTRL__W 11 +#define VSB_TOP_SYSSMTRNCTRL__M 0x7FF +#define VSB_TOP_SYSSMTRNCTRL__PRE 0x204 + +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__PRE 0x4 + +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__PRE 0x200 + +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL__A 0x1C10035 +#define VSB_TOP_SYSSMEQCTRL__W 11 +#define VSB_TOP_SYSSMEQCTRL__M 0x7FF +#define VSB_TOP_SYSSMEQCTRL__PRE 0x304 + +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__PRE 0x4 + +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__PRE 0x100 + +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__PRE 0x200 + +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL__A 0x1C10036 +#define VSB_TOP_SYSSMAGCCTRL__W 11 +#define VSB_TOP_SYSSMAGCCTRL__M 0x7FF +#define VSB_TOP_SYSSMAGCCTRL__PRE 0xF9 + +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__PRE 0x1 + +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__PRE 0x10 + +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__PRE 0x20 + +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__PRE 0x80 + +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL__A 0x1C10037 +#define VSB_TOP_SYSSMCTCTRL__W 11 +#define VSB_TOP_SYSSMCTCTRL__M 0x7FF +#define VSB_TOP_SYSSMCTCTRL__PRE 0x4A + +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__PRE 0x2 + +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_EQCTRL__A 0x1C10038 +#define VSB_TOP_EQCTRL__W 10 +#define VSB_TOP_EQCTRL__M 0x3FF +#define VSB_TOP_EQCTRL__PRE 0x6 + +#define VSB_TOP_EQCTRL_STASSIGNEN__B 0 +#define VSB_TOP_EQCTRL_STASSIGNEN__W 1 +#define VSB_TOP_EQCTRL_STASSIGNEN__M 0x1 +#define VSB_TOP_EQCTRL_STASSIGNEN__PRE 0x0 + +#define VSB_TOP_EQCTRL_ORCANCMAEN__B 1 +#define VSB_TOP_EQCTRL_ORCANCMAEN__W 1 +#define VSB_TOP_EQCTRL_ORCANCMAEN__M 0x2 +#define VSB_TOP_EQCTRL_ORCANCMAEN__PRE 0x2 + +#define VSB_TOP_EQCTRL_ODAGCGO__B 2 +#define VSB_TOP_EQCTRL_ODAGCGO__W 1 +#define VSB_TOP_EQCTRL_ODAGCGO__M 0x4 +#define VSB_TOP_EQCTRL_ODAGCGO__PRE 0x4 + +#define VSB_TOP_EQCTRL_OPTGAIN__B 3 +#define VSB_TOP_EQCTRL_OPTGAIN__W 3 +#define VSB_TOP_EQCTRL_OPTGAIN__M 0x38 +#define VSB_TOP_EQCTRL_OPTGAIN__PRE 0x0 + +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__B 6 +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__W 1 +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__M 0x40 +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__PRE 0x0 + +#define VSB_TOP_EQCTRL_CMAGAIN__B 7 +#define VSB_TOP_EQCTRL_CMAGAIN__W 3 +#define VSB_TOP_EQCTRL_CMAGAIN__M 0x380 +#define VSB_TOP_EQCTRL_CMAGAIN__PRE 0x0 + +#define VSB_TOP_PREEQAGCCTRL__A 0x1C10039 +#define VSB_TOP_PREEQAGCCTRL__W 5 +#define VSB_TOP_PREEQAGCCTRL__M 0x1F +#define VSB_TOP_PREEQAGCCTRL__PRE 0x10 + +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__B 0 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__W 4 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__M 0xF +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__PRE 0x0 + +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__B 4 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__W 1 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__M 0x10 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__PRE 0x10 + +#define VSB_TOP_PREEQAGCPWRREFLVLHI__A 0x1C1003A +#define VSB_TOP_PREEQAGCPWRREFLVLHI__W 8 +#define VSB_TOP_PREEQAGCPWRREFLVLHI__M 0xFF +#define VSB_TOP_PREEQAGCPWRREFLVLHI__PRE 0x0 + +#define VSB_TOP_PREEQAGCPWRREFLVLLO__A 0x1C1003B +#define VSB_TOP_PREEQAGCPWRREFLVLLO__W 16 +#define VSB_TOP_PREEQAGCPWRREFLVLLO__M 0xFFFF +#define VSB_TOP_PREEQAGCPWRREFLVLLO__PRE 0x1D66 + +#define VSB_TOP_CORINGSEL__A 0x1C1003C +#define VSB_TOP_CORINGSEL__W 8 +#define VSB_TOP_CORINGSEL__M 0xFF +#define VSB_TOP_CORINGSEL__PRE 0x3 +#define VSB_TOP_BEDETCTRL__A 0x1C1003D +#define VSB_TOP_BEDETCTRL__W 9 +#define VSB_TOP_BEDETCTRL__M 0x1FF +#define VSB_TOP_BEDETCTRL__PRE 0x145 + +#define VSB_TOP_BEDETCTRL_MIXRATIO__B 0 +#define VSB_TOP_BEDETCTRL_MIXRATIO__W 3 +#define VSB_TOP_BEDETCTRL_MIXRATIO__M 0x7 +#define VSB_TOP_BEDETCTRL_MIXRATIO__PRE 0x5 + +#define VSB_TOP_BEDETCTRL_CYOFFSEL__B 3 +#define VSB_TOP_BEDETCTRL_CYOFFSEL__W 1 +#define VSB_TOP_BEDETCTRL_CYOFFSEL__M 0x8 +#define VSB_TOP_BEDETCTRL_CYOFFSEL__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__B 4 +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__W 1 +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__M 0x10 +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__B 5 +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__M 0x20 +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__B 6 +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__M 0x40 +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__PRE 0x40 + +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__B 7 +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__M 0x80 +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__B 8 +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__M 0x100 +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__PRE 0x100 + +#define VSB_TOP_LBAGCREFLVL__A 0x1C1003E +#define VSB_TOP_LBAGCREFLVL__W 12 +#define VSB_TOP_LBAGCREFLVL__M 0xFFF +#define VSB_TOP_LBAGCREFLVL__PRE 0x200 + +#define VSB_TOP_UBAGCREFLVL__A 0x1C1003F +#define VSB_TOP_UBAGCREFLVL__W 12 +#define VSB_TOP_UBAGCREFLVL__M 0xFFF +#define VSB_TOP_UBAGCREFLVL__PRE 0x400 + +#define VSB_TOP_NOTCH1_BIN_NUM__A 0x1C10040 +#define VSB_TOP_NOTCH1_BIN_NUM__W 11 +#define VSB_TOP_NOTCH1_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH1_BIN_NUM__PRE 0xB2 + +#define VSB_TOP_NOTCH2_BIN_NUM__A 0x1C10041 +#define VSB_TOP_NOTCH2_BIN_NUM__W 11 +#define VSB_TOP_NOTCH2_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH2_BIN_NUM__PRE 0x40B + +#define VSB_TOP_NOTCH_START_BIN_NUM__A 0x1C10042 +#define VSB_TOP_NOTCH_START_BIN_NUM__W 11 +#define VSB_TOP_NOTCH_START_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH_START_BIN_NUM__PRE 0x7C0 + +#define VSB_TOP_NOTCH_STOP_BIN_NUM__A 0x1C10043 +#define VSB_TOP_NOTCH_STOP_BIN_NUM__W 11 +#define VSB_TOP_NOTCH_STOP_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH_STOP_BIN_NUM__PRE 0x43F + +#define VSB_TOP_NOTCH_TEST_DURATION__A 0x1C10044 +#define VSB_TOP_NOTCH_TEST_DURATION__W 11 +#define VSB_TOP_NOTCH_TEST_DURATION__M 0x7FF +#define VSB_TOP_NOTCH_TEST_DURATION__PRE 0x7FF + +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__A 0x1C10045 +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__W 11 +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__M 0x7FF +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__PRE 0x0 + +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__A 0x1C10046 +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__W 16 +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__M 0xFFFF +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__PRE 0x0 + +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__A 0x1C10047 +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__W 11 +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__M 0x7FF +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__PRE 0x0 + +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__A 0x1C10048 +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__W 16 +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__M 0xFFFF +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__PRE 0x0 + +#define VSB_TOP_NOTCH_SWEEP_RUNNING__A 0x1C10049 +#define VSB_TOP_NOTCH_SWEEP_RUNNING__W 1 +#define VSB_TOP_NOTCH_SWEEP_RUNNING__M 0x1 +#define VSB_TOP_NOTCH_SWEEP_RUNNING__PRE 0x0 + +#define VSB_TOP_PREEQDAGCRATIO__A 0x1C1004A +#define VSB_TOP_PREEQDAGCRATIO__W 13 +#define VSB_TOP_PREEQDAGCRATIO__M 0x1FFF +#define VSB_TOP_PREEQDAGCRATIO__PRE 0x0 +#define VSB_TOP_AGC_TRUNCCTRL__A 0x1C1004B +#define VSB_TOP_AGC_TRUNCCTRL__W 4 +#define VSB_TOP_AGC_TRUNCCTRL__M 0xF +#define VSB_TOP_AGC_TRUNCCTRL__PRE 0xF + +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__B 0 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__W 2 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__M 0x3 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__PRE 0x3 + +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__B 2 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__W 1 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__M 0x4 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__PRE 0x4 + +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__B 3 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__W 1 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__M 0x8 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__PRE 0x8 + +#define VSB_TOP_BEAGC_DEADZONEINIT__A 0x1C1004C +#define VSB_TOP_BEAGC_DEADZONEINIT__W 8 +#define VSB_TOP_BEAGC_DEADZONEINIT__M 0xFF +#define VSB_TOP_BEAGC_DEADZONEINIT__PRE 0x50 + +#define VSB_TOP_BEAGC_REFLEVEL__A 0x1C1004D +#define VSB_TOP_BEAGC_REFLEVEL__W 9 +#define VSB_TOP_BEAGC_REFLEVEL__M 0x1FF +#define VSB_TOP_BEAGC_REFLEVEL__PRE 0xAE + +#define VSB_TOP_BEAGC_GAINSHIFT__A 0x1C1004E +#define VSB_TOP_BEAGC_GAINSHIFT__W 3 +#define VSB_TOP_BEAGC_GAINSHIFT__M 0x7 +#define VSB_TOP_BEAGC_GAINSHIFT__PRE 0x3 + +#define VSB_TOP_BEAGC_REGINIT__A 0x1C1004F +#define VSB_TOP_BEAGC_REGINIT__W 15 +#define VSB_TOP_BEAGC_REGINIT__M 0x7FFF +#define VSB_TOP_BEAGC_REGINIT__PRE 0x40 + +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__B 14 +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__W 1 +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__M 0x4000 +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__PRE 0x0 + +#define VSB_TOP_BEAGC_SCALE__A 0x1C10050 +#define VSB_TOP_BEAGC_SCALE__W 14 +#define VSB_TOP_BEAGC_SCALE__M 0x3FFF +#define VSB_TOP_BEAGC_SCALE__PRE 0x0 + +#define VSB_TOP_CFAGC_DEADZONEINIT__A 0x1C10051 +#define VSB_TOP_CFAGC_DEADZONEINIT__W 8 +#define VSB_TOP_CFAGC_DEADZONEINIT__M 0xFF +#define VSB_TOP_CFAGC_DEADZONEINIT__PRE 0x50 + +#define VSB_TOP_CFAGC_REFLEVEL__A 0x1C10052 +#define VSB_TOP_CFAGC_REFLEVEL__W 9 +#define VSB_TOP_CFAGC_REFLEVEL__M 0x1FF +#define VSB_TOP_CFAGC_REFLEVEL__PRE 0xAE + +#define VSB_TOP_CFAGC_GAINSHIFT__A 0x1C10053 +#define VSB_TOP_CFAGC_GAINSHIFT__W 3 +#define VSB_TOP_CFAGC_GAINSHIFT__M 0x7 +#define VSB_TOP_CFAGC_GAINSHIFT__PRE 0x3 + +#define VSB_TOP_CFAGC_REGINIT__A 0x1C10054 +#define VSB_TOP_CFAGC_REGINIT__W 15 +#define VSB_TOP_CFAGC_REGINIT__M 0x7FFF +#define VSB_TOP_CFAGC_REGINIT__PRE 0x80 + +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__B 14 +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__W 1 +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__M 0x4000 +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__PRE 0x0 + +#define VSB_TOP_CFAGC_SCALE__A 0x1C10055 +#define VSB_TOP_CFAGC_SCALE__W 14 +#define VSB_TOP_CFAGC_SCALE__M 0x3FFF +#define VSB_TOP_CFAGC_SCALE__PRE 0x0 + +#define VSB_TOP_CKTRKONCTL__A 0x1C10056 +#define VSB_TOP_CKTRKONCTL__W 2 +#define VSB_TOP_CKTRKONCTL__M 0x3 +#define VSB_TOP_CKTRKONCTL__PRE 0x0 + +#define VSB_TOP_CYTRKONCTL__A 0x1C10057 +#define VSB_TOP_CYTRKONCTL__W 2 +#define VSB_TOP_CYTRKONCTL__M 0x3 +#define VSB_TOP_CYTRKONCTL__PRE 0x0 + +#define VSB_TOP_PTONCTL__A 0x1C10058 +#define VSB_TOP_PTONCTL__W 2 +#define VSB_TOP_PTONCTL__M 0x3 +#define VSB_TOP_PTONCTL__PRE 0x0 + +#define VSB_TOP_NOTCH_SCALE_1__A 0x1C10059 +#define VSB_TOP_NOTCH_SCALE_1__W 8 +#define VSB_TOP_NOTCH_SCALE_1__M 0xFF +#define VSB_TOP_NOTCH_SCALE_1__PRE 0xA + +#define VSB_TOP_NOTCH_SCALE_2__A 0x1C1005A +#define VSB_TOP_NOTCH_SCALE_2__W 8 +#define VSB_TOP_NOTCH_SCALE_2__M 0xFF +#define VSB_TOP_NOTCH_SCALE_2__PRE 0xA + +#define VSB_TOP_FIRSTLARGFFETAP__A 0x1C1005B +#define VSB_TOP_FIRSTLARGFFETAP__W 12 +#define VSB_TOP_FIRSTLARGFFETAP__M 0xFFF +#define VSB_TOP_FIRSTLARGFFETAP__PRE 0x0 + +#define VSB_TOP_FIRSTLARGFFETAPADDR__A 0x1C1005C +#define VSB_TOP_FIRSTLARGFFETAPADDR__W 11 +#define VSB_TOP_FIRSTLARGFFETAPADDR__M 0x7FF +#define VSB_TOP_FIRSTLARGFFETAPADDR__PRE 0x0 + +#define VSB_TOP_SECONDLARGFFETAP__A 0x1C1005D +#define VSB_TOP_SECONDLARGFFETAP__W 12 +#define VSB_TOP_SECONDLARGFFETAP__M 0xFFF +#define VSB_TOP_SECONDLARGFFETAP__PRE 0x0 + +#define VSB_TOP_SECONDLARGFFETAPADDR__A 0x1C1005E +#define VSB_TOP_SECONDLARGFFETAPADDR__W 11 +#define VSB_TOP_SECONDLARGFFETAPADDR__M 0x7FF +#define VSB_TOP_SECONDLARGFFETAPADDR__PRE 0x0 + +#define VSB_TOP_FIRSTLARGDFETAP__A 0x1C1005F +#define VSB_TOP_FIRSTLARGDFETAP__W 12 +#define VSB_TOP_FIRSTLARGDFETAP__M 0xFFF +#define VSB_TOP_FIRSTLARGDFETAP__PRE 0x0 + +#define VSB_TOP_FIRSTLARGDFETAPADDR__A 0x1C10060 +#define VSB_TOP_FIRSTLARGDFETAPADDR__W 11 +#define VSB_TOP_FIRSTLARGDFETAPADDR__M 0x7FF +#define VSB_TOP_FIRSTLARGDFETAPADDR__PRE 0x0 + +#define VSB_TOP_SECONDLARGDFETAP__A 0x1C10061 +#define VSB_TOP_SECONDLARGDFETAP__W 12 +#define VSB_TOP_SECONDLARGDFETAP__M 0xFFF +#define VSB_TOP_SECONDLARGDFETAP__PRE 0x0 + +#define VSB_TOP_SECONDLARGDFETAPADDR__A 0x1C10062 +#define VSB_TOP_SECONDLARGDFETAPADDR__W 11 +#define VSB_TOP_SECONDLARGDFETAPADDR__M 0x7FF +#define VSB_TOP_SECONDLARGDFETAPADDR__PRE 0x0 + +#define VSB_TOP_PARAOWDBUS__A 0x1C10063 +#define VSB_TOP_PARAOWDBUS__W 12 +#define VSB_TOP_PARAOWDBUS__M 0xFFF +#define VSB_TOP_PARAOWDBUS__PRE 0x0 +#define VSB_TOP_PARAOWCTRL__A 0x1C10064 +#define VSB_TOP_PARAOWCTRL__W 7 +#define VSB_TOP_PARAOWCTRL__M 0x7F +#define VSB_TOP_PARAOWCTRL__PRE 0x0 + +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__B 0 +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__W 6 +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__M 0x3F +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__PRE 0x0 + +#define VSB_TOP_PARAOWCTRL_PARAOWEN__B 6 +#define VSB_TOP_PARAOWCTRL_PARAOWEN__W 1 +#define VSB_TOP_PARAOWCTRL_PARAOWEN__M 0x40 +#define VSB_TOP_PARAOWCTRL_PARAOWEN__PRE 0x0 + +#define VSB_TOP_CURRENTSEGLOCAT__A 0x1C10065 +#define VSB_TOP_CURRENTSEGLOCAT__W 10 +#define VSB_TOP_CURRENTSEGLOCAT__M 0x3FF +#define VSB_TOP_CURRENTSEGLOCAT__PRE 0x0 + +#define VSB_TOP_MEASUREMENT_PERIOD__A 0x1C10066 +#define VSB_TOP_MEASUREMENT_PERIOD__W 16 +#define VSB_TOP_MEASUREMENT_PERIOD__M 0xFFFF +#define VSB_TOP_MEASUREMENT_PERIOD__PRE 0x0 + +#define VSB_TOP_NR_SYM_ERRS__A 0x1C10067 +#define VSB_TOP_NR_SYM_ERRS__W 16 +#define VSB_TOP_NR_SYM_ERRS__M 0xFFFF +#define VSB_TOP_NR_SYM_ERRS__PRE 0xFFFF + +#define VSB_TOP_ERR_ENERGY_L__A 0x1C10068 +#define VSB_TOP_ERR_ENERGY_L__W 16 +#define VSB_TOP_ERR_ENERGY_L__M 0xFFFF +#define VSB_TOP_ERR_ENERGY_L__PRE 0xFFFF + +#define VSB_TOP_ERR_ENERGY_H__A 0x1C10069 +#define VSB_TOP_ERR_ENERGY_H__W 16 +#define VSB_TOP_ERR_ENERGY_H__M 0xFFFF +#define VSB_TOP_ERR_ENERGY_H__PRE 0xFFFF + +#define VSB_TOP_SLICER_SEL_8LEV__A 0x1C1006A +#define VSB_TOP_SLICER_SEL_8LEV__W 1 +#define VSB_TOP_SLICER_SEL_8LEV__M 0x1 +#define VSB_TOP_SLICER_SEL_8LEV__PRE 0x1 + +#define VSB_TOP_BNFIELD__A 0x1C1006B +#define VSB_TOP_BNFIELD__W 3 +#define VSB_TOP_BNFIELD__M 0x7 +#define VSB_TOP_BNFIELD__PRE 0x3 + +#define VSB_TOP_CLPLASTNUM__A 0x1C1006C +#define VSB_TOP_CLPLASTNUM__W 8 +#define VSB_TOP_CLPLASTNUM__M 0xFF +#define VSB_TOP_CLPLASTNUM__PRE 0x0 + +#define VSB_TOP_BNSQERR__A 0x1C1006D +#define VSB_TOP_BNSQERR__W 16 +#define VSB_TOP_BNSQERR__M 0xFFFF +#define VSB_TOP_BNSQERR__PRE 0x1AD + +#define VSB_TOP_BNTHRESH__A 0x1C1006E +#define VSB_TOP_BNTHRESH__W 9 +#define VSB_TOP_BNTHRESH__M 0x1FF +#define VSB_TOP_BNTHRESH__PRE 0x120 + +#define VSB_TOP_BNCLPNUM__A 0x1C1006F +#define VSB_TOP_BNCLPNUM__W 16 +#define VSB_TOP_BNCLPNUM__M 0xFFFF +#define VSB_TOP_BNCLPNUM__PRE 0x0 +#define VSB_TOP_PHASELOCKCTRL__A 0x1C10070 +#define VSB_TOP_PHASELOCKCTRL__W 7 +#define VSB_TOP_PHASELOCKCTRL__M 0x7F +#define VSB_TOP_PHASELOCKCTRL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__B 0 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__W 1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__M 0x1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__B 1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__W 1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__M 0x2 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__B 2 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__W 1 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__M 0x4 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__B 3 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__W 1 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__M 0x8 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__B 4 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__W 1 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__M 0x10 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__B 5 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__W 1 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__M 0x20 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__B 6 +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__W 1 +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__M 0x40 +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__PRE 0x0 + +#define VSB_TOP_DLOCKACCUM__A 0x1C10071 +#define VSB_TOP_DLOCKACCUM__W 16 +#define VSB_TOP_DLOCKACCUM__M 0xFFFF +#define VSB_TOP_DLOCKACCUM__PRE 0x0 + +#define VSB_TOP_PLOCKACCUM__A 0x1C10072 +#define VSB_TOP_PLOCKACCUM__W 16 +#define VSB_TOP_PLOCKACCUM__M 0xFFFF +#define VSB_TOP_PLOCKACCUM__PRE 0x0 + +#define VSB_TOP_CLOCKACCUM__A 0x1C10073 +#define VSB_TOP_CLOCKACCUM__W 16 +#define VSB_TOP_CLOCKACCUM__M 0xFFFF +#define VSB_TOP_CLOCKACCUM__PRE 0x0 + +#define VSB_TOP_DCRMVACUMI__A 0x1C10074 +#define VSB_TOP_DCRMVACUMI__W 10 +#define VSB_TOP_DCRMVACUMI__M 0x3FF +#define VSB_TOP_DCRMVACUMI__PRE 0x0 + +#define VSB_TOP_DCRMVACUMQ__A 0x1C10075 +#define VSB_TOP_DCRMVACUMQ__W 10 +#define VSB_TOP_DCRMVACUMQ__M 0x3FF +#define VSB_TOP_DCRMVACUMQ__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A 0x1C20000 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__A 0x1C20001 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__A 0x1C20002 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__A 0x1C20003 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__A 0x1C20004 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__A 0x1C20005 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__A 0x1C20006 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__A 0x1C20007 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__A 0x1C20008 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__A 0x1C20009 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__A 0x1C2000A +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__A 0x1C2000B +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__A 0x1C2000C +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__A 0x1C2000D +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__A 0x1C2000E +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__A 0x1C2000F +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__A 0x1C20010 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__A 0x1C20011 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__A 0x1C20012 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__A 0x1C20013 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__A 0x1C20014 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__A 0x1C20015 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__A 0x1C20016 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__A 0x1C20017 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__A 0x1C20018 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__A 0x1C20019 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__A 0x1C2001A +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__A 0x1C2001B +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__A 0x1C2001C +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__A 0x1C2001D +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__A 0x1C2001E +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__A 0x1C2001F +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__A 0x1C20020 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__A 0x1C20021 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__A 0x1C20022 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__A 0x1C20023 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__A 0x1C20024 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__A 0x1C20025 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__A 0x1C20026 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__A 0x1C20027 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__A 0x1C20028 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__A 0x1C20029 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__A 0x1C2002A +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__A 0x1C2002B +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__A 0x1C2002C +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__A 0x1C2002D +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__A 0x1C2002E +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__A 0x1C2002F +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__A 0x1C20030 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__A 0x1C20031 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__A 0x1C20032 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__A 0x1C20033 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__A 0x1C20034 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__A 0x1C20035 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__A 0x1C20036 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__A 0x1C20037 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__A 0x1C20038 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__A 0x1C20039 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__A 0x1C2003A +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__A 0x1C2003B +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__A 0x1C2003C +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__A 0x1C2003D +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__A 0x1C2003E +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__A 0x1C2003F +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__A 0x1C20040 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__A 0x1C20041 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__A 0x1C20042 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__A 0x1C20043 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__A 0x1C20044 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__A 0x1C20045 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__A 0x1C20046 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__A 0x1C20047 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__A 0x1C20048 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__A 0x1C20049 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__A 0x1C2004A +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__A 0x1C2004B +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__A 0x1C2004C +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__A 0x1C2004D +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__A 0x1C2004E +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__A 0x1C2004F +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__A 0x1C20050 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__A 0x1C20051 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__A 0x1C20052 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__A 0x1C20053 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__A 0x1C20054 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__A 0x1C20055 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__A 0x1C20056 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__A 0x1C20057 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__A 0x1C20058 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__A 0x1C20059 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__A 0x1C2005A +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__A 0x1C2005B +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__A 0x1C2005C +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__A 0x1C2005D +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__A 0x1C2005E +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__A 0x1C2005F +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__A 0x1C20060 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__A 0x1C20061 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__A 0x1C20062 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__A 0x1C20063 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__A 0x1C20064 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__A 0x1C20065 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__A 0x1C20066 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__A 0x1C20067 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__A 0x1C20068 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__A 0x1C20069 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__A 0x1C2006A +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__A 0x1C2006B +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__A 0x1C2006C +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__A 0x1C2006D +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__A 0x1C2006E +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__A 0x1C2006F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__A 0x1C20070 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__A 0x1C20071 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__A 0x1C20072 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__A 0x1C20073 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__A 0x1C20074 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__A 0x1C20075 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__A 0x1C20076 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__A 0x1C20077 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__PRE 0x0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__A 0x1C20078 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__A 0x1C20079 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__A 0x1C2007A +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__A 0x1C2007B +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__A 0x1C2007C +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__A 0x1C2007D +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__A 0x1C2007E +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__A 0x1C2007F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A 0x1C30000 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__A 0x1C30001 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__A 0x1C30002 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__A 0x1C30003 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__A 0x1C30004 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__A 0x1C30005 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__A 0x1C30006 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__A 0x1C30007 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__A 0x1C30008 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__A 0x1C30009 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__A 0x1C3000A +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__A 0x1C3000B +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__A 0x1C3000C +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__A 0x1C3000D +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__A 0x1C3000E +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__A 0x1C3000F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__A 0x1C30010 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__A 0x1C30011 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__A 0x1C30012 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__A 0x1C30013 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__A 0x1C30014 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__A 0x1C30015 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__A 0x1C30016 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__A 0x1C30017 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__A 0x1C30018 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__A 0x1C30019 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__A 0x1C3001A +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__A 0x1C3001B +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__A 0x1C3001C +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__A 0x1C3001D +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__A 0x1C3001E +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__A 0x1C3001F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__A 0x1C30020 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__A 0x1C30021 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__A 0x1C30022 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__A 0x1C30023 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__A 0x1C30024 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__A 0x1C30025 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__A 0x1C30026 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__A 0x1C30027 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__A 0x1C30028 +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__A 0x1C30029 +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__A 0x1C3002A +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__A 0x1C3002B +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__A 0x1C3002C +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__A 0x1C3002D +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__A 0x1C3002E +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__A 0x1C3002F +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__A 0x1C30030 +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__A 0x1C30031 +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__PRE 0x0 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__A 0x1C30032 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__A 0x1C30033 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__A 0x1C30034 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__A 0x1C30035 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__PRE 0x0 + +#define VSB_TCMEQ_RAM__A 0x1C40000 + +#define VSB_TCMEQ_RAM_TCMEQ_RAM__B 0 +#define VSB_TCMEQ_RAM_TCMEQ_RAM__W 16 +#define VSB_TCMEQ_RAM_TCMEQ_RAM__M 0xFFFF +#define VSB_TCMEQ_RAM_TCMEQ_RAM__PRE 0x0 + +#define VSB_FCPRE_RAM__A 0x1C50000 + +#define VSB_FCPRE_RAM_FCPRE_RAM__B 0 +#define VSB_FCPRE_RAM_FCPRE_RAM__W 16 +#define VSB_FCPRE_RAM_FCPRE_RAM__M 0xFFFF +#define VSB_FCPRE_RAM_FCPRE_RAM__PRE 0x0 + +#define VSB_EQTAP_RAM__A 0x1C60000 + +#define VSB_EQTAP_RAM_EQTAP_RAM__B 0 +#define VSB_EQTAP_RAM_EQTAP_RAM__W 12 +#define VSB_EQTAP_RAM_EQTAP_RAM__M 0xFFF +#define VSB_EQTAP_RAM_EQTAP_RAM__PRE 0x0 + +#endif diff --git a/drivers/media/dvb-frontends/drxd_hard.c b/drivers/media/dvb-frontends/drxd_hard.c index 959ae36..5b87ece 100644 --- a/drivers/media/dvb-frontends/drxd_hard.c +++ b/drivers/media/dvb-frontends/drxd_hard.c @@ -2688,11 +2688,11 @@ static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) status = EnableAndResetMB(state); if (status < 0) break; - if (state->type_A) + if (state->type_A) { status = ResetCEFR(state); if (status < 0) break; - + } if (fw) { status = DownloadMicrocode(state, fw, fw_size); if (status < 0) diff --git a/drivers/media/dvb-frontends/ds3000.c b/drivers/media/dvb-frontends/ds3000.c index 1e344b0..335daef 100644 --- a/drivers/media/dvb-frontends/ds3000.c +++ b/drivers/media/dvb-frontends/ds3000.c @@ -616,7 +616,7 @@ static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr) snr_reading = dvbs2_noise_reading / tmp; if (snr_reading > 80) snr_reading = 80; - *snr = -(dvbs2_snr_tab[snr_reading] / 1000); + *snr = -(dvbs2_snr_tab[snr_reading - 1] / 1000); } dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, snr_reading, *snr); diff --git a/drivers/media/dvb-frontends/it913x-fe-priv.h b/drivers/media/dvb-frontends/it913x-fe-priv.h deleted file mode 100644 index eb6fd8a..0000000 --- a/drivers/media/dvb-frontends/it913x-fe-priv.h +++ /dev/null @@ -1,1051 +0,0 @@ - -struct it913xset { u32 pro; - u32 address; - u8 reg[15]; - u8 count; -}; - -struct adctable { u32 adcFrequency; - u32 bandwidth; - u32 coeff_1_2048; - u32 coeff_1_4096; - u32 coeff_1_8191; - u32 coeff_1_8192; - u32 coeff_1_8193; - u32 coeff_2_2k; - u32 coeff_2_4k; - u32 coeff_2_8k; - u16 bfsfcw_fftinx_ratio; - u16 fftinx_bfsfcw_ratio; -}; - -/* clock and coeff tables only table 3 is used with IT9137*/ -/* TODO other tables relate AF9035 may be removed */ -static struct adctable tab1[] = { - { 20156250, 6000000, - 0x02b8ba6e, 0x015c5d37, 0x00ae340d, 0x00ae2e9b, 0x00ae292a, - 0x015c5d37, 0x00ae2e9b, 0x0057174e, 0x02f1, 0x015c }, - { 20156250, 7000000, - 0x032cd980, 0x01966cc0, 0x00cb3cba, 0x00cb3660, 0x00cb3007, - 0x01966cc0, 0x00cb3660, 0x00659b30, 0x0285, 0x0196 }, - { 20156250, 8000000, - 0x03a0f893, 0x01d07c49, 0x00e84567, 0x00e83e25, 0x00e836e3, - 0x01d07c49, 0x00e83e25, 0x00741f12, 0x0234, 0x01d0 }, - { 20156250, 5000000, - 0x02449b5c, 0x01224dae, 0x00912b60, 0x009126d7, 0x0091224e, - 0x01224dae, 0x009126d7, 0x0048936b, 0x0387, 0x0122 } -}; - -static struct adctable tab2[] = { - { 20187500, 6000000, - 0x02b7a654, 0x015bd32a, 0x00adef04, 0x00ade995, 0x00ade426, - 0x015bd32a, 0x00ade995, 0x0056f4ca, 0x02f2, 0x015c }, - { 20187500, 7000000, - 0x032b9761, 0x0195cbb1, 0x00caec30, 0x00cae5d8, 0x00cadf81, - 0x0195cbb1, 0x00cae5d8, 0x006572ec, 0x0286, 0x0196 }, - { 20187500, 8000000, - 0x039f886f, 0x01cfc438, 0x00e7e95b, 0x00e7e21c, 0x00e7dadd, - 0x01cfc438, 0x00e7e21c, 0x0073f10e, 0x0235, 0x01d0 }, - { 20187500, 5000000, - 0x0243b546, 0x0121daa3, 0x0090f1d9, 0x0090ed51, 0x0090e8ca, - 0x0121daa3, 0x0090ed51, 0x004876a9, 0x0388, 0x0122 } - -}; - -static struct adctable tab3[] = { - { 20250000, 6000000, - 0x02b580ad, 0x015ac057, 0x00ad6597, 0x00ad602b, 0x00ad5ac1, - 0x015ac057, 0x00ad602b, 0x0056b016, 0x02f4, 0x015b }, - { 20250000, 7000000, - 0x03291620, 0x01948b10, 0x00ca4bda, 0x00ca4588, 0x00ca3f36, - 0x01948b10, 0x00ca4588, 0x006522c4, 0x0288, 0x0195 }, - { 20250000, 8000000, - 0x039cab92, 0x01ce55c9, 0x00e7321e, 0x00e72ae4, 0x00e723ab, - 0x01ce55c9, 0x00e72ae4, 0x00739572, 0x0237, 0x01ce }, - { 20250000, 5000000, - 0x0241eb3b, 0x0120f59e, 0x00907f53, 0x00907acf, 0x0090764b, - 0x0120f59e, 0x00907acf, 0x00483d67, 0x038b, 0x0121 } - -}; - -static struct adctable tab4[] = { - { 20583333, 6000000, - 0x02aa4598, 0x015522cc, 0x00aa96bb, 0x00aa9166, 0x00aa8c12, - 0x015522cc, 0x00aa9166, 0x005548b3, 0x0300, 0x0155 }, - { 20583333, 7000000, - 0x031bfbdc, 0x018dfdee, 0x00c7052f, 0x00c6fef7, 0x00c6f8bf, - 0x018dfdee, 0x00c6fef7, 0x00637f7b, 0x0293, 0x018e }, - { 20583333, 8000000, - 0x038db21f, 0x01c6d910, 0x00e373a3, 0x00e36c88, 0x00e3656d, - 0x01c6d910, 0x00e36c88, 0x0071b644, 0x0240, 0x01c7 }, - { 20583333, 5000000, - 0x02388f54, 0x011c47aa, 0x008e2846, 0x008e23d5, 0x008e1f64, - 0x011c47aa, 0x008e23d5, 0x004711ea, 0x039a, 0x011c } - -}; - -static struct adctable tab5[] = { - { 20416667, 6000000, - 0x02afd765, 0x0157ebb3, 0x00abfb39, 0x00abf5d9, 0x00abf07a, - 0x0157ebb3, 0x00abf5d9, 0x0055faed, 0x02fa, 0x0158 }, - { 20416667, 7000000, - 0x03227b4b, 0x01913da6, 0x00c8a518, 0x00c89ed3, 0x00c8988e, - 0x01913da6, 0x00c89ed3, 0x00644f69, 0x028d, 0x0191 }, - { 20416667, 8000000, - 0x03951f32, 0x01ca8f99, 0x00e54ef7, 0x00e547cc, 0x00e540a2, - 0x01ca8f99, 0x00e547cc, 0x0072a3e6, 0x023c, 0x01cb }, - { 20416667, 5000000, - 0x023d337f, 0x011e99c0, 0x008f515a, 0x008f4ce0, 0x008f4865, - 0x011e99c0, 0x008f4ce0, 0x0047a670, 0x0393, 0x011f } - -}; - -static struct adctable tab6[] = { - { 20480000, 6000000, - 0x02adb6db, 0x0156db6e, 0x00ab7312, 0x00ab6db7, 0x00ab685c, - 0x0156db6e, 0x00ab6db7, 0x0055b6db, 0x02fd, 0x0157 }, - { 20480000, 7000000, - 0x03200000, 0x01900000, 0x00c80640, 0x00c80000, 0x00c7f9c0, - 0x01900000, 0x00c80000, 0x00640000, 0x028f, 0x0190 }, - { 20480000, 8000000, - 0x03924925, 0x01c92492, 0x00e4996e, 0x00e49249, 0x00e48b25, - 0x01c92492, 0x00e49249, 0x00724925, 0x023d, 0x01c9 }, - { 20480000, 5000000, - 0x023b6db7, 0x011db6db, 0x008edfe5, 0x008edb6e, 0x008ed6f7, - 0x011db6db, 0x008edb6e, 0x00476db7, 0x0396, 0x011e } -}; - -static struct adctable tab7[] = { - { 20500000, 6000000, - 0x02ad0b99, 0x015685cc, 0x00ab4840, 0x00ab42e6, 0x00ab3d8c, - 0x015685cc, 0x00ab42e6, 0x0055a173, 0x02fd, 0x0157 }, - { 20500000, 7000000, - 0x031f3832, 0x018f9c19, 0x00c7d44b, 0x00c7ce0c, 0x00c7c7ce, - 0x018f9c19, 0x00c7ce0c, 0x0063e706, 0x0290, 0x0190 }, - { 20500000, 8000000, - 0x039164cb, 0x01c8b266, 0x00e46056, 0x00e45933, 0x00e45210, - 0x01c8b266, 0x00e45933, 0x00722c99, 0x023e, 0x01c9 }, - { 20500000, 5000000, - 0x023adeff, 0x011d6f80, 0x008ebc36, 0x008eb7c0, 0x008eb34a, - 0x011d6f80, 0x008eb7c0, 0x00475be0, 0x0396, 0x011d } - -}; - -static struct adctable tab8[] = { - { 20625000, 6000000, - 0x02a8e4bd, 0x0154725e, 0x00aa3e81, 0x00aa392f, 0x00aa33de, - 0x0154725e, 0x00aa392f, 0x00551c98, 0x0302, 0x0154 }, - { 20625000, 7000000, - 0x031a6032, 0x018d3019, 0x00c69e41, 0x00c6980c, 0x00c691d8, - 0x018d3019, 0x00c6980c, 0x00634c06, 0x0294, 0x018d }, - { 20625000, 8000000, - 0x038bdba6, 0x01c5edd3, 0x00e2fe02, 0x00e2f6ea, 0x00e2efd2, - 0x01c5edd3, 0x00e2f6ea, 0x00717b75, 0x0242, 0x01c6 }, - { 20625000, 5000000, - 0x02376948, 0x011bb4a4, 0x008ddec1, 0x008dda52, 0x008dd5e3, - 0x011bb4a4, 0x008dda52, 0x0046ed29, 0x039c, 0x011c } - -}; - -struct table { - u32 xtal; - struct adctable *table; -}; - -static struct table fe_clockTable[] = { - {12000000, tab3}, /* 12.00MHz */ - {20480000, tab6}, /* 20.48MHz */ - {36000000, tab3}, /* 36.00MHz */ - {30000000, tab1}, /* 30.00MHz */ - {26000000, tab4}, /* 26.00MHz */ - {28000000, tab5}, /* 28.00MHz */ - {32000000, tab7}, /* 32.00MHz */ - {34000000, tab2}, /* 34.00MHz */ - {24000000, tab1}, /* 24.00MHz */ - {22000000, tab8}, /* 22.00MHz */ -}; - -/* fe get */ -fe_code_rate_t fe_code[] = { - FEC_1_2, - FEC_2_3, - FEC_3_4, - FEC_5_6, - FEC_7_8, - FEC_NONE, -}; - -fe_guard_interval_t fe_gi[] = { - GUARD_INTERVAL_1_32, - GUARD_INTERVAL_1_16, - GUARD_INTERVAL_1_8, - GUARD_INTERVAL_1_4, -}; - -fe_hierarchy_t fe_hi[] = { - HIERARCHY_NONE, - HIERARCHY_1, - HIERARCHY_2, - HIERARCHY_4, -}; - -fe_transmit_mode_t fe_mode[] = { - TRANSMISSION_MODE_2K, - TRANSMISSION_MODE_8K, - TRANSMISSION_MODE_4K, -}; - -fe_modulation_t fe_con[] = { - QPSK, - QAM_16, - QAM_64, -}; - -enum { - PRIORITY_HIGH = 0, /* High-priority stream */ - PRIORITY_LOW, /* Low-priority stream */ -}; - -/* Standard demodulator functions */ -static struct it913xset set_solo_fe[] = { - {PRO_LINK, GPIOH5_EN, {0x01}, 0x01}, - {PRO_LINK, GPIOH5_ON, {0x01}, 0x01}, - {PRO_LINK, GPIOH5_O, {0x00}, 0x01}, - {PRO_LINK, GPIOH5_O, {0x01}, 0x01}, - {PRO_LINK, DVBT_INTEN, {0x04}, 0x01}, - {PRO_LINK, DVBT_ENABLE, {0x05}, 0x01}, - {PRO_DMOD, MP2IF_MPEG_PAR_MODE, {0x00}, 0x01}, - {PRO_LINK, HOSTB_MPEG_SER_MODE, {0x00}, 0x01}, - {PRO_LINK, HOSTB_MPEG_PAR_MODE, {0x00}, 0x01}, - {PRO_DMOD, DCA_UPPER_CHIP, {0x00}, 0x01}, - {PRO_LINK, HOSTB_DCA_UPPER, {0x00}, 0x01}, - {PRO_DMOD, DCA_LOWER_CHIP, {0x00}, 0x01}, - {PRO_LINK, HOSTB_DCA_LOWER, {0x00}, 0x01}, - {PRO_DMOD, DCA_PLATCH, {0x00}, 0x01}, - {PRO_DMOD, DCA_FPGA_LATCH, {0x00}, 0x01}, - {PRO_DMOD, DCA_STAND_ALONE, {0x01}, 0x01}, - {PRO_DMOD, DCA_ENABLE, {0x00}, 0x01}, - {PRO_DMOD, MP2IF_MPEG_PAR_MODE, {0x00}, 0x01}, - {PRO_DMOD, BFS_FCW, {0x00, 0x00, 0x00}, 0x03}, - {0xff, 0x0000, {0x00}, 0x00}, /* Terminating Entry */ -}; - - -static struct it913xset init_1[] = { - {PRO_LINK, LOCK3_OUT, {0x01}, 0x01}, - {PRO_LINK, PADMISCDRSR, {0x01}, 0x01}, - {PRO_LINK, PADMISCDR2, {0x00}, 0x01}, - {PRO_DMOD, 0xec57, {0x00, 0x00}, 0x02}, - {PRO_LINK, PADMISCDR4, {0x00}, 0x01}, /* Power up */ - {PRO_LINK, PADMISCDR8, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - - -/* Version 1 types */ -static struct it913xset it9135_v1[] = { - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a}, 0x01}, - {PRO_DMOD, 0x007e, {0x04}, 0x01}, - {PRO_DMOD, 0x0081, {0x0a}, 0x01}, - {PRO_DMOD, 0x008a, {0x01}, 0x01}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06}, 0x01}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009f, {0xe1}, 0x01}, - {PRO_DMOD, 0x00a0, {0xcf}, 0x01}, - {PRO_DMOD, 0x00a3, {0x01}, 0x01}, - {PRO_DMOD, 0x00a5, {0x01}, 0x01}, - {PRO_DMOD, 0x00a6, {0x01}, 0x01}, - {PRO_DMOD, 0x00a9, {0x00}, 0x01}, - {PRO_DMOD, 0x00aa, {0x01}, 0x01}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00c2, {0x05}, 0x01}, - {PRO_DMOD, 0x00c6, {0x19}, 0x01}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf016, {0x10}, 0x01}, - {PRO_DMOD, 0xf017, {0x04}, 0x01}, - {PRO_DMOD, 0xf018, {0x05}, 0x01}, - {PRO_DMOD, 0xf019, {0x04}, 0x01}, - {PRO_DMOD, 0xf01a, {0x05}, 0x01}, - {PRO_DMOD, 0xf021, {0x03}, 0x01}, - {PRO_DMOD, 0xf022, {0x0a}, 0x01}, - {PRO_DMOD, 0xf023, {0x0a}, 0x01}, - {PRO_DMOD, 0xf02b, {0x00}, 0x01}, - {PRO_DMOD, 0xf02c, {0x01}, 0x01}, - {PRO_DMOD, 0xf064, {0x03}, 0x01}, - {PRO_DMOD, 0xf065, {0xf9}, 0x01}, - {PRO_DMOD, 0xf066, {0x03}, 0x01}, - {PRO_DMOD, 0xf067, {0x01}, 0x01}, - {PRO_DMOD, 0xf06f, {0xe0}, 0x01}, - {PRO_DMOD, 0xf070, {0x03}, 0x01}, - {PRO_DMOD, 0xf072, {0x0f}, 0x01}, - {PRO_DMOD, 0xf073, {0x03}, 0x01}, - {PRO_DMOD, 0xf078, {0x00}, 0x01}, - {PRO_DMOD, 0xf087, {0x00}, 0x01}, - {PRO_DMOD, 0xf09b, {0x3f}, 0x01}, - {PRO_DMOD, 0xf09c, {0x00}, 0x01}, - {PRO_DMOD, 0xf09d, {0x20}, 0x01}, - {PRO_DMOD, 0xf09e, {0x00}, 0x01}, - {PRO_DMOD, 0xf09f, {0x0c}, 0x01}, - {PRO_DMOD, 0xf0a0, {0x00}, 0x01}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00}, 0x01}, - {PRO_DMOD, 0xf14d, {0x00}, 0x01}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00}, 0x01}, - {PRO_DMOD, 0xf15b, {0x08}, 0x01}, - {PRO_DMOD, 0xf15d, {0x03}, 0x01}, - {PRO_DMOD, 0xf15e, {0x05}, 0x01}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01}, 0x01}, - {PRO_DMOD, 0xf167, {0x40}, 0x01}, - {PRO_DMOD, 0xf168, {0x0f}, 0x01}, - {PRO_DMOD, 0xf17a, {0x00}, 0x01}, - {PRO_DMOD, 0xf17b, {0x00}, 0x01}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36}, 0x01}, - {PRO_DMOD, 0xf1bd, {0x00}, 0x01}, - {PRO_DMOD, 0xf1cb, {0xa0}, 0x01}, - {PRO_DMOD, 0xf1cc, {0x01}, 0x01}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf40e, {0x0a}, 0x01}, - {PRO_DMOD, 0xf40f, {0x40}, 0x01}, - {PRO_DMOD, 0xf410, {0x08}, 0x01}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15}, 0x01}, - {PRO_DMOD, 0xf562, {0x20}, 0x01}, - {PRO_DMOD, 0xf5df, {0xfb}, 0x01}, - {PRO_DMOD, 0xf5e0, {0x00}, 0x01}, - {PRO_DMOD, 0xf5e3, {0x09}, 0x01}, - {PRO_DMOD, 0xf5e4, {0x01}, 0x01}, - {PRO_DMOD, 0xf5e5, {0x01}, 0x01}, - {PRO_DMOD, 0xf5f8, {0x01}, 0x01}, - {PRO_DMOD, 0xf5fd, {0x01}, 0x01}, - {PRO_DMOD, 0xf600, {0x05}, 0x01}, - {PRO_DMOD, 0xf601, {0x08}, 0x01}, - {PRO_DMOD, 0xf602, {0x0b}, 0x01}, - {PRO_DMOD, 0xf603, {0x0e}, 0x01}, - {PRO_DMOD, 0xf604, {0x11}, 0x01}, - {PRO_DMOD, 0xf605, {0x14}, 0x01}, - {PRO_DMOD, 0xf606, {0x17}, 0x01}, - {PRO_DMOD, 0xf607, {0x1f}, 0x01}, - {PRO_DMOD, 0xf60e, {0x00}, 0x01}, - {PRO_DMOD, 0xf60f, {0x04}, 0x01}, - {PRO_DMOD, 0xf610, {0x32}, 0x01}, - {PRO_DMOD, 0xf611, {0x10}, 0x01}, - {PRO_DMOD, 0xf707, {0xfc}, 0x01}, - {PRO_DMOD, 0xf708, {0x00}, 0x01}, - {PRO_DMOD, 0xf709, {0x37}, 0x01}, - {PRO_DMOD, 0xf70a, {0x00}, 0x01}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40}, 0x01}, - {PRO_DMOD, 0xf810, {0x54}, 0x01}, - {PRO_DMOD, 0xf811, {0x5a}, 0x01}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -static struct it913xset it9135_38[] = { - {PRO_DMOD, 0x0043, {0x00}, 0x01}, - {PRO_DMOD, 0x0046, {0x38}, 0x01}, - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0x0068, {0x0a}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03}, - {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0xc8, 0x01}, 0x05}, - {PRO_DMOD, 0x007e, {0x04, 0x00}, 0x02}, - {PRO_DMOD, 0x0081, { 0x0a, 0x12, 0x02, 0x0a, 0x03, 0xc8, 0xb8, - 0xd0, 0xc3, 0x01}, 0x0a}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02}, - {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02}, - {PRO_DMOD, 0x00a3, {0x01, 0x5a, 0x01, 0x01}, 0x04}, - {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00b3, {0x02, 0x32}, 0x02}, - {PRO_DMOD, 0x00b6, {0x14}, 0x01}, - {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05}, 0x03}, - {PRO_DMOD, 0x00c4, {0x00}, 0x01}, - {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02}, - {PRO_DMOD, 0x00cc, {0x2e, 0x51, 0x33}, 0x03}, - {PRO_DMOD, 0x00f3, {0x05, 0x8c, 0x8c}, 0x03}, - {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03}, - {PRO_DMOD, 0x00fc, { 0x02, 0x02, 0x02, 0x09, 0x50, 0x7b, 0x77, - 0x00, 0x02, 0xc8, 0x05, 0x7b}, 0x0c}, - {PRO_DMOD, 0x0109, {0x02}, 0x01}, - {PRO_DMOD, 0x0115, {0x0a, 0x03, 0x02, 0x80}, 0x04}, - {PRO_DMOD, 0x011a, {0xc8, 0x7b, 0x8a, 0xa0}, 0x04}, - {PRO_DMOD, 0x0122, {0x02, 0x18, 0xc3}, 0x03}, - {PRO_DMOD, 0x0127, {0x00, 0x07}, 0x02}, - {PRO_DMOD, 0x012a, {0x53, 0x51, 0x4e, 0x43}, 0x04}, - {PRO_DMOD, 0x0137, {0x01, 0x00, 0x07, 0x00, 0x06}, 0x05}, - {PRO_DMOD, 0x013d, {0x00, 0x01, 0x5b, 0xc8, 0x59}, 0x05}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf016, {0x10, 0x04, 0x05, 0x04, 0x05}, 0x05}, - {PRO_DMOD, 0xf01f, {0x8c, 0x00, 0x03, 0x0a, 0x0a}, 0x05}, - {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00, 0x01}, 0x04}, - {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04}, - {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02}, - {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02}, - {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02}, - {PRO_DMOD, 0xf085, {0x00, 0x02, 0x00}, 0x03}, - {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02}, - {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03}, - {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02}, - {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04}, - {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05}, - {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04}, - {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02}, - {PRO_DMOD, 0xf5df, {0xfb, 0x00}, 0x02}, - {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03}, - {PRO_DMOD, 0xf5f8, {0x01}, 0x01}, - {PRO_DMOD, 0xf5fd, {0x01}, 0x01}, - {PRO_DMOD, 0xf600, { 0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17, - 0x1f}, 0x08}, - {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04}, - {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -static struct it913xset it9135_51[] = { - {PRO_DMOD, 0x0043, {0x00}, 0x01}, - {PRO_DMOD, 0x0046, {0x51}, 0x01}, - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0x0068, {0x0a}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a, 0x06, 0x02}, 0x03}, - {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0xc8, 0x01}, 0x05}, - {PRO_DMOD, 0x007e, {0x04, 0x00}, 0x02}, - {PRO_DMOD, 0x0081, { 0x0a, 0x12, 0x02, 0x0a, 0x03, 0xc0, 0x96, - 0xcf, 0xc3, 0x01}, 0x0a}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02}, - {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02}, - {PRO_DMOD, 0x00a3, {0x01, 0x5a, 0x01, 0x01}, 0x04}, - {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00b3, {0x02, 0x3c}, 0x02}, - {PRO_DMOD, 0x00b6, {0x14}, 0x01}, - {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05}, 0x03}, - {PRO_DMOD, 0x00c4, {0x00}, 0x01}, - {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02}, - {PRO_DMOD, 0x00cc, {0x2e, 0x51, 0x33}, 0x03}, - {PRO_DMOD, 0x00f3, {0x05, 0x8c, 0x8c}, 0x03}, - {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03}, - {PRO_DMOD, 0x00fc, { 0x03, 0x02, 0x02, 0x09, 0x50, 0x7a, 0x77, - 0x01, 0x02, 0xb0, 0x02, 0x7a}, 0x0c}, - {PRO_DMOD, 0x0109, {0x02}, 0x01}, - {PRO_DMOD, 0x0115, {0x0a, 0x03, 0x02, 0x80}, 0x04}, - {PRO_DMOD, 0x011a, {0xc0, 0x7a, 0xac, 0x8c}, 0x04}, - {PRO_DMOD, 0x0122, {0x02, 0x70, 0xa4}, 0x03}, - {PRO_DMOD, 0x0127, {0x00, 0x07}, 0x02}, - {PRO_DMOD, 0x012a, {0x53, 0x51, 0x4e, 0x43}, 0x04}, - {PRO_DMOD, 0x0137, {0x01, 0x00, 0x07, 0x00, 0x06}, 0x05}, - {PRO_DMOD, 0x013d, {0x00, 0x01, 0x5b, 0xc0, 0x59}, 0x05}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf016, {0x10, 0x04, 0x05, 0x04, 0x05}, 0x05}, - {PRO_DMOD, 0xf01f, {0x8c, 0x00, 0x03, 0x0a, 0x0a}, 0x05}, - {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00, 0x01}, 0x04}, - {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04}, - {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02}, - {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02}, - {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02}, - {PRO_DMOD, 0xf085, {0xc0, 0x01, 0x00}, 0x03}, - {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02}, - {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03}, - {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02}, - {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04}, - {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05}, - {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04}, - {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02}, - {PRO_DMOD, 0xf5df, {0xfb, 0x00}, 0x02}, - {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03}, - {PRO_DMOD, 0xf5f8, {0x01}, 0x01}, - {PRO_DMOD, 0xf5fd, {0x01}, 0x01}, - {PRO_DMOD, 0xf600, { 0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17, - 0x1f}, 0x08}, - {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04}, - {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -static struct it913xset it9135_52[] = { - {PRO_DMOD, 0x0043, {0x00}, 0x01}, - {PRO_DMOD, 0x0046, {0x52}, 0x01}, - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0x0068, {0x10}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03}, - {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0xa0, 0x01}, 0x05}, - {PRO_DMOD, 0x007e, {0x04, 0x00}, 0x02}, - {PRO_DMOD, 0x0081, { 0x0a, 0x12, 0x03, 0x0a, 0x03, 0xb3, 0x97, - 0xc0, 0x9e, 0x01}, 0x0a}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02}, - {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02}, - {PRO_DMOD, 0x00a3, {0x01, 0x5c, 0x01, 0x01}, 0x04}, - {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00b3, {0x02, 0x3c}, 0x02}, - {PRO_DMOD, 0x00b6, {0x14}, 0x01}, - {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05}, 0x03}, - {PRO_DMOD, 0x00c4, {0x00}, 0x01}, - {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02}, - {PRO_DMOD, 0x00cc, {0x2e, 0x51, 0x33}, 0x03}, - {PRO_DMOD, 0x00f3, {0x05, 0x91, 0x8c}, 0x03}, - {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03}, - {PRO_DMOD, 0x00fc, { 0x03, 0x02, 0x02, 0x09, 0x50, 0x74, 0x77, - 0x02, 0x02, 0xae, 0x02, 0x6e}, 0x0c}, - {PRO_DMOD, 0x0109, {0x02}, 0x01}, - {PRO_DMOD, 0x0115, {0x0a, 0x03, 0x02, 0x80}, 0x04}, - {PRO_DMOD, 0x011a, {0xcd, 0x62, 0xa4, 0x8c}, 0x04}, - {PRO_DMOD, 0x0122, {0x03, 0x18, 0x9e}, 0x03}, - {PRO_DMOD, 0x0127, {0x00, 0x07}, 0x02}, - {PRO_DMOD, 0x012a, {0x53, 0x51, 0x4e, 0x43}, 0x04}, - {PRO_DMOD, 0x0137, {0x00, 0x00, 0x07, 0x00, 0x06}, 0x05}, - {PRO_DMOD, 0x013d, {0x00, 0x01, 0x5b, 0xb6, 0x59}, 0x05}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf016, {0x10, 0x04, 0x05, 0x04, 0x05}, 0x05}, - {PRO_DMOD, 0xf01f, {0x8c, 0x00, 0x03, 0x0a, 0x0a}, 0x05}, - {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00, 0x01}, 0x04}, - {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04}, - {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02}, - {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02}, - {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02}, - {PRO_DMOD, 0xf085, {0xc0, 0x01, 0x00}, 0x03}, - {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02}, - {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03}, - {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02}, - {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04}, - {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05}, - {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04}, - {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02}, - {PRO_DMOD, 0xf5df, {0xfb, 0x00}, 0x02}, - {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03}, - {PRO_DMOD, 0xf5f8, {0x01}, 0x01}, - {PRO_DMOD, 0xf5fd, {0x01}, 0x01}, - {PRO_DMOD, 0xf600, {0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17, - 0x1f}, 0x08}, - {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04}, - {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -/* Version 2 types */ -static struct it913xset it9135_v2[] = { - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a}, 0x01}, - {PRO_DMOD, 0x007e, {0x04}, 0x01}, - {PRO_DMOD, 0x0081, {0x0a}, 0x01}, - {PRO_DMOD, 0x008a, {0x01}, 0x01}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06}, 0x01}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009f, {0xe1}, 0x01}, - {PRO_DMOD, 0x00a0, {0xcf}, 0x01}, - {PRO_DMOD, 0x00a3, {0x01}, 0x01}, - {PRO_DMOD, 0x00a5, {0x01}, 0x01}, - {PRO_DMOD, 0x00a6, {0x01}, 0x01}, - {PRO_DMOD, 0x00a9, {0x00}, 0x01}, - {PRO_DMOD, 0x00aa, {0x01}, 0x01}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00c2, {0x05}, 0x01}, - {PRO_DMOD, 0x00c6, {0x19}, 0x01}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf02b, {0x00}, 0x01}, - {PRO_DMOD, 0xf064, {0x03}, 0x01}, - {PRO_DMOD, 0xf065, {0xf9}, 0x01}, - {PRO_DMOD, 0xf066, {0x03}, 0x01}, - {PRO_DMOD, 0xf067, {0x01}, 0x01}, - {PRO_DMOD, 0xf06f, {0xe0}, 0x01}, - {PRO_DMOD, 0xf070, {0x03}, 0x01}, - {PRO_DMOD, 0xf072, {0x0f}, 0x01}, - {PRO_DMOD, 0xf073, {0x03}, 0x01}, - {PRO_DMOD, 0xf078, {0x00}, 0x01}, - {PRO_DMOD, 0xf087, {0x00}, 0x01}, - {PRO_DMOD, 0xf09b, {0x3f}, 0x01}, - {PRO_DMOD, 0xf09c, {0x00}, 0x01}, - {PRO_DMOD, 0xf09d, {0x20}, 0x01}, - {PRO_DMOD, 0xf09e, {0x00}, 0x01}, - {PRO_DMOD, 0xf09f, {0x0c}, 0x01}, - {PRO_DMOD, 0xf0a0, {0x00}, 0x01}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00}, 0x01}, - {PRO_DMOD, 0xf14d, {0x00}, 0x01}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00}, 0x01}, - {PRO_DMOD, 0xf15b, {0x08}, 0x01}, - {PRO_DMOD, 0xf15d, {0x03}, 0x01}, - {PRO_DMOD, 0xf15e, {0x05}, 0x01}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01}, 0x01}, - {PRO_DMOD, 0xf167, {0x40}, 0x01}, - {PRO_DMOD, 0xf168, {0x0f}, 0x01}, - {PRO_DMOD, 0xf17a, {0x00}, 0x01}, - {PRO_DMOD, 0xf17b, {0x00}, 0x01}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36}, 0x01}, - {PRO_DMOD, 0xf1bd, {0x00}, 0x01}, - {PRO_DMOD, 0xf1cb, {0xa0}, 0x01}, - {PRO_DMOD, 0xf1cc, {0x01}, 0x01}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf40e, {0x0a}, 0x01}, - {PRO_DMOD, 0xf40f, {0x40}, 0x01}, - {PRO_DMOD, 0xf410, {0x08}, 0x01}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15}, 0x01}, - {PRO_DMOD, 0xf562, {0x20}, 0x01}, - {PRO_DMOD, 0xf5e3, {0x09}, 0x01}, - {PRO_DMOD, 0xf5e4, {0x01}, 0x01}, - {PRO_DMOD, 0xf5e5, {0x01}, 0x01}, - {PRO_DMOD, 0xf600, {0x05}, 0x01}, - {PRO_DMOD, 0xf601, {0x08}, 0x01}, - {PRO_DMOD, 0xf602, {0x0b}, 0x01}, - {PRO_DMOD, 0xf603, {0x0e}, 0x01}, - {PRO_DMOD, 0xf604, {0x11}, 0x01}, - {PRO_DMOD, 0xf605, {0x14}, 0x01}, - {PRO_DMOD, 0xf606, {0x17}, 0x01}, - {PRO_DMOD, 0xf607, {0x1f}, 0x01}, - {PRO_DMOD, 0xf60e, {0x00}, 0x01}, - {PRO_DMOD, 0xf60f, {0x04}, 0x01}, - {PRO_DMOD, 0xf610, {0x32}, 0x01}, - {PRO_DMOD, 0xf611, {0x10}, 0x01}, - {PRO_DMOD, 0xf707, {0xfc}, 0x01}, - {PRO_DMOD, 0xf708, {0x00}, 0x01}, - {PRO_DMOD, 0xf709, {0x37}, 0x01}, - {PRO_DMOD, 0xf70a, {0x00}, 0x01}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40}, 0x01}, - {PRO_DMOD, 0xf810, {0x54}, 0x01}, - {PRO_DMOD, 0xf811, {0x5a}, 0x01}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -static struct it913xset it9135_60[] = { - {PRO_DMOD, 0x0043, {0x00}, 0x01}, - {PRO_DMOD, 0x0046, {0x60}, 0x01}, - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0x0068, {0x0a}, 0x01}, - {PRO_DMOD, 0x006a, {0x03}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03}, - {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0x8c, 0x01}, 0x05}, - {PRO_DMOD, 0x007e, {0x04}, 0x01}, - {PRO_DMOD, 0x0081, {0x0a, 0x12}, 0x02}, - {PRO_DMOD, 0x0084, {0x0a, 0x33, 0xbe, 0xa0, 0xc6, 0xb6, 0x01}, 0x07}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02}, - {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02}, - {PRO_DMOD, 0x00a3, {0x01, 0x5a, 0x01, 0x01}, 0x04}, - {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00b3, {0x02, 0x3a}, 0x02}, - {PRO_DMOD, 0x00b6, {0x14}, 0x01}, - {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05, 0x01, 0x00}, 0x05}, - {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02}, - {PRO_DMOD, 0x00cb, {0x32, 0x2c, 0x4f, 0x30}, 0x04}, - {PRO_DMOD, 0x00f3, {0x05, 0xa0, 0x8c}, 0x03}, - {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03}, - {PRO_DMOD, 0x00fc, { 0x03, 0x03, 0x02, 0x0a, 0x50, 0x7b, 0x8c, - 0x00, 0x02, 0xbe, 0x00}, 0x0b}, - {PRO_DMOD, 0x0109, {0x02}, 0x01}, - {PRO_DMOD, 0x0115, {0x0a, 0x03}, 0x02}, - {PRO_DMOD, 0x011a, {0xbe}, 0x01}, - {PRO_DMOD, 0x0124, {0xae}, 0x01}, - {PRO_DMOD, 0x0127, {0x00}, 0x01}, - {PRO_DMOD, 0x012a, {0x56, 0x50, 0x47, 0x42}, 0x04}, - {PRO_DMOD, 0x0137, {0x00}, 0x01}, - {PRO_DMOD, 0x013b, {0x08}, 0x01}, - {PRO_DMOD, 0x013f, {0x5b}, 0x01}, - {PRO_DMOD, 0x0141, { 0x59, 0xf9, 0x19, 0x19, 0x8c, 0x8c, 0x8c, - 0x6e, 0x8c, 0x50, 0x8c, 0x8c, 0xac, 0xc6, - 0x33}, 0x0f}, - {PRO_DMOD, 0x0151, {0x28}, 0x01}, - {PRO_DMOD, 0x0153, {0xbc}, 0x01}, - {PRO_DMOD, 0x0178, {0x09}, 0x01}, - {PRO_DMOD, 0x0181, {0x94, 0x6e}, 0x02}, - {PRO_DMOD, 0x0185, {0x24}, 0x01}, - {PRO_DMOD, 0x0187, {0x00, 0x00, 0xbe, 0x02, 0x80}, 0x05}, - {PRO_DMOD, 0xed02, {0xff}, 0x01}, - {PRO_DMOD, 0xee42, {0xff}, 0x01}, - {PRO_DMOD, 0xee82, {0xff}, 0x01}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf01f, {0x8c, 0x00}, 0x02}, - {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00}, 0x03}, - {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04}, - {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02}, - {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02}, - {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02}, - {PRO_DMOD, 0xf087, {0x00}, 0x01}, - {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02}, - {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03}, - {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02}, - {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04}, - {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05}, - {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04}, - {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02}, - {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03}, - {PRO_DMOD, 0xf600, {0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17 - , 0x1f}, 0x08}, - {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04}, - {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -static struct it913xset it9135_61[] = { - {PRO_DMOD, 0x0043, {0x00}, 0x01}, - {PRO_DMOD, 0x0046, {0x61}, 0x01}, - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0x0068, {0x06}, 0x01}, - {PRO_DMOD, 0x006a, {0x03}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03}, - {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0x90, 0x01}, 0x05}, - {PRO_DMOD, 0x007e, {0x04}, 0x01}, - {PRO_DMOD, 0x0081, {0x0a, 0x12}, 0x02}, - {PRO_DMOD, 0x0084, {0x0a, 0x33, 0xbc, 0x9c, 0xcc, 0xa8, 0x01}, 0x07}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02}, - {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02}, - {PRO_DMOD, 0x00a3, {0x01, 0x5c, 0x01, 0x01}, 0x04}, - {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00b3, {0x02, 0x3a}, 0x02}, - {PRO_DMOD, 0x00b6, {0x14}, 0x01}, - {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05, 0x01, 0x00}, 0x05}, - {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02}, - {PRO_DMOD, 0x00cb, {0x32, 0x2c, 0x4f, 0x30}, 0x04}, - {PRO_DMOD, 0x00f3, {0x05, 0xa0, 0x8c}, 0x03}, - {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03}, - {PRO_DMOD, 0x00fc, { 0x03, 0x03, 0x02, 0x08, 0x50, 0x7b, 0x8c, - 0x01, 0x02, 0xc8, 0x00}, 0x0b}, - {PRO_DMOD, 0x0109, {0x02}, 0x01}, - {PRO_DMOD, 0x0115, {0x0a, 0x03}, 0x02}, - {PRO_DMOD, 0x011a, {0xc6}, 0x01}, - {PRO_DMOD, 0x0124, {0xa8}, 0x01}, - {PRO_DMOD, 0x0127, {0x00}, 0x01}, - {PRO_DMOD, 0x012a, {0x59, 0x50, 0x47, 0x42}, 0x04}, - {PRO_DMOD, 0x0137, {0x00}, 0x01}, - {PRO_DMOD, 0x013b, {0x05}, 0x01}, - {PRO_DMOD, 0x013f, {0x5b}, 0x01}, - {PRO_DMOD, 0x0141, { 0x59, 0xf9, 0x59, 0x59, 0x8c, 0x8c, 0x8c, - 0x7b, 0x8c, 0x50, 0x8c, 0x8c, 0xa8, 0xc6, - 0x33}, 0x0f}, - {PRO_DMOD, 0x0151, {0x28}, 0x01}, - {PRO_DMOD, 0x0153, {0xcc}, 0x01}, - {PRO_DMOD, 0x0178, {0x09}, 0x01}, - {PRO_DMOD, 0x0181, {0x9c, 0x76}, 0x02}, - {PRO_DMOD, 0x0185, {0x28}, 0x01}, - {PRO_DMOD, 0x0187, {0x01, 0x00, 0xaa, 0x02, 0x80}, 0x05}, - {PRO_DMOD, 0xed02, {0xff}, 0x01}, - {PRO_DMOD, 0xee42, {0xff}, 0x01}, - {PRO_DMOD, 0xee82, {0xff}, 0x01}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf01f, {0x8c, 0x00}, 0x02}, - {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00}, 0x03}, - {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04}, - {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02}, - {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02}, - {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02}, - {PRO_DMOD, 0xf087, {0x00}, 0x01}, - {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02}, - {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03}, - {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02}, - {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04}, - {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05}, - {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04}, - {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02}, - {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03}, - {PRO_DMOD, 0xf600, { 0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17, - 0x1f}, 0x08}, - {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04}, - {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -static struct it913xset it9135_62[] = { - {PRO_DMOD, 0x0043, {0x00}, 0x01}, - {PRO_DMOD, 0x0046, {0x62}, 0x01}, - {PRO_DMOD, 0x0051, {0x01}, 0x01}, - {PRO_DMOD, 0x005f, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0x0068, {0x0a}, 0x01}, - {PRO_DMOD, 0x006a, {0x03}, 0x01}, - {PRO_DMOD, 0x0070, {0x0a, 0x05, 0x02}, 0x03}, - {PRO_DMOD, 0x0075, {0x8c, 0x8c, 0x8c, 0x8c, 0x01}, 0x05}, - {PRO_DMOD, 0x007e, {0x04}, 0x01}, - {PRO_DMOD, 0x0081, {0x0a, 0x12}, 0x02}, - {PRO_DMOD, 0x0084, { 0x0a, 0x33, 0xb8, 0x9c, 0xb2, 0xa6, 0x01}, - 0x07}, - {PRO_DMOD, 0x008e, {0x01}, 0x01}, - {PRO_DMOD, 0x0092, {0x06, 0x00, 0x00, 0x00, 0x00}, 0x05}, - {PRO_DMOD, 0x0099, {0x01}, 0x01}, - {PRO_DMOD, 0x009b, {0x3c, 0x28}, 0x02}, - {PRO_DMOD, 0x009f, {0xe1, 0xcf}, 0x02}, - {PRO_DMOD, 0x00a3, {0x01, 0x5a, 0x01, 0x01}, 0x04}, - {PRO_DMOD, 0x00a9, {0x00, 0x01}, 0x02}, - {PRO_DMOD, 0x00b0, {0x01}, 0x01}, - {PRO_DMOD, 0x00b3, {0x02, 0x3a}, 0x02}, - {PRO_DMOD, 0x00b6, {0x14}, 0x01}, - {PRO_DMOD, 0x00c0, {0x11, 0x00, 0x05, 0x01, 0x00}, 0x05}, - {PRO_DMOD, 0x00c6, {0x19, 0x00}, 0x02}, - {PRO_DMOD, 0x00cb, {0x32, 0x2c, 0x4f, 0x30}, 0x04}, - {PRO_DMOD, 0x00f3, {0x05, 0x8c, 0x8c}, 0x03}, - {PRO_DMOD, 0x00f8, {0x03, 0x06, 0x06}, 0x03}, - {PRO_DMOD, 0x00fc, { 0x02, 0x03, 0x02, 0x09, 0x50, 0x6e, 0x8c, - 0x02, 0x02, 0xc2, 0x00}, 0x0b}, - {PRO_DMOD, 0x0109, {0x02}, 0x01}, - {PRO_DMOD, 0x0115, {0x0a, 0x03}, 0x02}, - {PRO_DMOD, 0x011a, {0xb8}, 0x01}, - {PRO_DMOD, 0x0124, {0xa8}, 0x01}, - {PRO_DMOD, 0x0127, {0x00}, 0x01}, - {PRO_DMOD, 0x012a, {0x53, 0x51, 0x4e, 0x43}, 0x04}, - {PRO_DMOD, 0x0137, {0x00}, 0x01}, - {PRO_DMOD, 0x013b, {0x05}, 0x01}, - {PRO_DMOD, 0x013f, {0x5b}, 0x01}, - {PRO_DMOD, 0x0141, { 0x59, 0xf9, 0x59, 0x19, 0x8c, 0x8c, 0x8c, - 0x7b, 0x8c, 0x50, 0x70, 0x8c, 0x96, 0xd0, - 0x33}, 0x0f}, - {PRO_DMOD, 0x0151, {0x28}, 0x01}, - {PRO_DMOD, 0x0153, {0xb2}, 0x01}, - {PRO_DMOD, 0x0178, {0x09}, 0x01}, - {PRO_DMOD, 0x0181, {0x9c, 0x6e}, 0x02}, - {PRO_DMOD, 0x0185, {0x24}, 0x01}, - {PRO_DMOD, 0x0187, {0x00, 0x00, 0xb8, 0x02, 0x80}, 0x05}, - {PRO_DMOD, 0xed02, {0xff}, 0x01}, - {PRO_DMOD, 0xee42, {0xff}, 0x01}, - {PRO_DMOD, 0xee82, {0xff}, 0x01}, - {PRO_DMOD, 0xf000, {0x0f}, 0x01}, - {PRO_DMOD, 0xf01f, {0x8c, 0x00}, 0x02}, - {PRO_DMOD, 0xf029, {0x8c, 0x00, 0x00}, 0x03}, - {PRO_DMOD, 0xf064, {0x03, 0xf9, 0x03, 0x01}, 0x04}, - {PRO_DMOD, 0xf06f, {0xe0, 0x03}, 0x02}, - {PRO_DMOD, 0xf072, {0x0f, 0x03}, 0x02}, - {PRO_DMOD, 0xf077, {0x01, 0x00}, 0x02}, - {PRO_DMOD, 0xf087, {0x00}, 0x01}, - {PRO_DMOD, 0xf09b, {0x3f, 0x00, 0x20, 0x00, 0x0c, 0x00}, 0x06}, - {PRO_DMOD, 0xf130, {0x04}, 0x01}, - {PRO_DMOD, 0xf132, {0x04}, 0x01}, - {PRO_DMOD, 0xf144, {0x1a}, 0x01}, - {PRO_DMOD, 0xf146, {0x00}, 0x01}, - {PRO_DMOD, 0xf14a, {0x01}, 0x01}, - {PRO_DMOD, 0xf14c, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf14f, {0x04}, 0x01}, - {PRO_DMOD, 0xf158, {0x7f}, 0x01}, - {PRO_DMOD, 0xf15a, {0x00, 0x08}, 0x02}, - {PRO_DMOD, 0xf15d, {0x03, 0x05}, 0x02}, - {PRO_DMOD, 0xf163, {0x05}, 0x01}, - {PRO_DMOD, 0xf166, {0x01, 0x40, 0x0f}, 0x03}, - {PRO_DMOD, 0xf17a, {0x00, 0x00}, 0x02}, - {PRO_DMOD, 0xf183, {0x01}, 0x01}, - {PRO_DMOD, 0xf19d, {0x40}, 0x01}, - {PRO_DMOD, 0xf1bc, {0x36, 0x00}, 0x02}, - {PRO_DMOD, 0xf1cb, {0xa0, 0x01}, 0x02}, - {PRO_DMOD, 0xf204, {0x10}, 0x01}, - {PRO_DMOD, 0xf214, {0x00}, 0x01}, - {PRO_DMOD, 0xf24c, {0x88, 0x95, 0x9a, 0x90}, 0x04}, - {PRO_DMOD, 0xf25a, {0x07, 0xe8, 0x03, 0xb0, 0x04}, 0x05}, - {PRO_DMOD, 0xf270, {0x01, 0x02, 0x01, 0x02}, 0x04}, - {PRO_DMOD, 0xf40e, {0x0a, 0x40, 0x08}, 0x03}, - {PRO_DMOD, 0xf55f, {0x0a}, 0x01}, - {PRO_DMOD, 0xf561, {0x15, 0x20}, 0x02}, - {PRO_DMOD, 0xf5e3, {0x09, 0x01, 0x01}, 0x03}, - {PRO_DMOD, 0xf600, { 0x05, 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17, - 0x1f}, 0x08}, - {PRO_DMOD, 0xf60e, {0x00, 0x04, 0x32, 0x10}, 0x04}, - {PRO_DMOD, 0xf707, {0xfc, 0x00, 0x37, 0x00}, 0x04}, - {PRO_DMOD, 0xf78b, {0x01}, 0x01}, - {PRO_DMOD, 0xf80f, {0x40, 0x54, 0x5a}, 0x03}, - {PRO_DMOD, 0xf905, {0x01}, 0x01}, - {PRO_DMOD, 0xfb06, {0x03}, 0x01}, - {PRO_DMOD, 0xfd8b, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00} /* Terminating Entry */ -}; - -/* Tuner setting scripts (still keeping it9137) */ -static struct it913xset it9137_tuner_off[] = { - {PRO_DMOD, 0xfba8, {0x01}, 0x01}, /* Tuner Clock Off */ - {PRO_DMOD, 0xec40, {0x00}, 0x01}, /* Power Down Tuner */ - {PRO_DMOD, 0xec02, {0x3f, 0x1f, 0x3f, 0x3f}, 0x04}, - {PRO_DMOD, 0xec06, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00}, 0x0c}, - {PRO_DMOD, 0xec12, {0x00, 0x00, 0x00, 0x00}, 0x04}, - {PRO_DMOD, 0xec17, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00}, 0x09}, - {PRO_DMOD, 0xec22, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00}, 0x0a}, - {PRO_DMOD, 0xec20, {0x00}, 0x01}, - {PRO_DMOD, 0xec3f, {0x01}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00}, /* Terminating Entry */ -}; - -static struct it913xset set_it9135_template[] = { - {PRO_DMOD, 0xee06, {0x00}, 0x01}, - {PRO_DMOD, 0xec56, {0x00}, 0x01}, - {PRO_DMOD, 0xec4c, {0x00}, 0x01}, - {PRO_DMOD, 0xec4d, {0x00}, 0x01}, - {PRO_DMOD, 0xec4e, {0x00}, 0x01}, - {PRO_DMOD, 0x011e, {0x00}, 0x01}, /* Older Devices */ - {PRO_DMOD, 0x011f, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00}, /* Terminating Entry */ -}; - -static struct it913xset set_it9137_template[] = { - {PRO_DMOD, 0xee06, {0x00}, 0x01}, - {PRO_DMOD, 0xec56, {0x00}, 0x01}, - {PRO_DMOD, 0xec4c, {0x00}, 0x01}, - {PRO_DMOD, 0xec4d, {0x00}, 0x01}, - {PRO_DMOD, 0xec4e, {0x00}, 0x01}, - {PRO_DMOD, 0xec4f, {0x00}, 0x01}, - {PRO_DMOD, 0xec50, {0x00}, 0x01}, - {0xff, 0x0000, {0x00}, 0x00}, /* Terminating Entry */ -}; diff --git a/drivers/media/dvb-frontends/it913x-fe.c b/drivers/media/dvb-frontends/it913x-fe.c deleted file mode 100644 index 6e1c6eb..0000000 --- a/drivers/media/dvb-frontends/it913x-fe.c +++ /dev/null @@ -1,1045 +0,0 @@ -/* - * Driver for it913x-fe Frontend - * - * with support for on chip it9137 integral tuner - * - * Copyright (C) 2011 Malcolm Priestley (tvboxspy@gmail.com) - * IT9137 Copyright (C) ITE Tech Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= - */ - -#include <linux/module.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/types.h> - -#include "dvb_frontend.h" -#include "it913x-fe.h" -#include "it913x-fe-priv.h" - -static int it913x_debug; - -module_param_named(debug, it913x_debug, int, 0644); -MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able))."); - -#define dprintk(level, args...) do { \ - if (level & it913x_debug) \ - printk(KERN_DEBUG "it913x-fe: " args); \ -} while (0) - -#define deb_info(args...) dprintk(0x01, args) -#define debug_data_snipet(level, name, p) \ - dprintk(level, name" (%02x%02x%02x%02x%02x%02x%02x%02x)", \ - *p, *(p+1), *(p+2), *(p+3), *(p+4), \ - *(p+5), *(p+6), *(p+7)); -#define info(format, arg...) \ - printk(KERN_INFO "it913x-fe: " format "\n" , ## arg) - -struct it913x_fe_state { - struct dvb_frontend frontend; - struct i2c_adapter *i2c_adap; - struct ite_config *config; - u8 i2c_addr; - u32 frequency; - fe_modulation_t constellation; - fe_transmit_mode_t transmission_mode; - u8 priority; - u32 crystalFrequency; - u32 adcFrequency; - u8 tuner_type; - struct adctable *table; - fe_status_t it913x_status; - u16 tun_xtal; - u8 tun_fdiv; - u8 tun_clk_mode; - u32 tun_fn_min; - u32 ucblocks; -}; - -static int it913x_read_reg(struct it913x_fe_state *state, - u32 reg, u8 *data, u8 count) -{ - int ret; - u8 pro = PRO_DMOD; /* All reads from demodulator */ - u8 b[4]; - struct i2c_msg msg[2] = { - { .addr = state->i2c_addr + (pro << 1), .flags = 0, - .buf = b, .len = sizeof(b) }, - { .addr = state->i2c_addr + (pro << 1), .flags = I2C_M_RD, - .buf = data, .len = count } - }; - b[0] = (u8) reg >> 24; - b[1] = (u8)(reg >> 16) & 0xff; - b[2] = (u8)(reg >> 8) & 0xff; - b[3] = (u8) reg & 0xff; - - ret = i2c_transfer(state->i2c_adap, msg, 2); - - return ret; -} - -static int it913x_read_reg_u8(struct it913x_fe_state *state, u32 reg) -{ - int ret; - u8 b[1]; - ret = it913x_read_reg(state, reg, &b[0], sizeof(b)); - return (ret < 0) ? -ENODEV : b[0]; -} - -static int it913x_write(struct it913x_fe_state *state, - u8 pro, u32 reg, u8 buf[], u8 count) -{ - u8 b[256]; - struct i2c_msg msg[1] = { - { .addr = state->i2c_addr + (pro << 1), .flags = 0, - .buf = b, .len = count + 4 } - }; - int ret; - - b[0] = (u8) reg >> 24; - b[1] = (u8)(reg >> 16) & 0xff; - b[2] = (u8)(reg >> 8) & 0xff; - b[3] = (u8) reg & 0xff; - memcpy(&b[4], buf, count); - - ret = i2c_transfer(state->i2c_adap, msg, 1); - - if (ret < 0) - return -EIO; - - return 0; -} - -static int it913x_write_reg(struct it913x_fe_state *state, - u8 pro, u32 reg, u32 data) -{ - int ret; - u8 b[4]; - u8 s; - - b[0] = data >> 24; - b[1] = (data >> 16) & 0xff; - b[2] = (data >> 8) & 0xff; - b[3] = data & 0xff; - /* expand write as needed */ - if (data < 0x100) - s = 3; - else if (data < 0x1000) - s = 2; - else if (data < 0x100000) - s = 1; - else - s = 0; - - ret = it913x_write(state, pro, reg, &b[s], sizeof(b) - s); - - return ret; -} - -static int it913x_fe_script_loader(struct it913x_fe_state *state, - struct it913xset *loadscript) -{ - int ret, i; - if (loadscript == NULL) - return -EINVAL; - - for (i = 0; i < 1000; ++i) { - if (loadscript[i].pro == 0xff) - break; - ret = it913x_write(state, loadscript[i].pro, - loadscript[i].address, - loadscript[i].reg, loadscript[i].count); - if (ret < 0) - return -ENODEV; - } - return 0; -} - -static int it913x_init_tuner(struct it913x_fe_state *state) -{ - int ret, i, reg; - u8 val, nv_val; - u8 nv[] = {48, 32, 24, 16, 12, 8, 6, 4, 2}; - u8 b[2]; - - reg = it913x_read_reg_u8(state, 0xec86); - switch (reg) { - case 0: - state->tun_clk_mode = reg; - state->tun_xtal = 2000; - state->tun_fdiv = 3; - val = 16; - break; - case -ENODEV: - return -ENODEV; - case 1: - default: - state->tun_clk_mode = reg; - state->tun_xtal = 640; - state->tun_fdiv = 1; - val = 6; - break; - } - - reg = it913x_read_reg_u8(state, 0xed03); - - if (reg < 0) - return -ENODEV; - else if (reg < ARRAY_SIZE(nv)) - nv_val = nv[reg]; - else - nv_val = 2; - - for (i = 0; i < 50; i++) { - ret = it913x_read_reg(state, 0xed23, &b[0], sizeof(b)); - reg = (b[1] << 8) + b[0]; - if (reg > 0) - break; - if (ret < 0) - return -ENODEV; - udelay(2000); - } - state->tun_fn_min = state->tun_xtal * reg; - state->tun_fn_min /= (state->tun_fdiv * nv_val); - deb_info("Tuner fn_min %d", state->tun_fn_min); - - if (state->config->chip_ver > 1) - msleep(50); - else { - for (i = 0; i < 50; i++) { - reg = it913x_read_reg_u8(state, 0xec82); - if (reg > 0) - break; - if (reg < 0) - return -ENODEV; - udelay(2000); - } - } - - return it913x_write_reg(state, PRO_DMOD, 0xed81, val); -} - -static int it9137_set_tuner(struct it913x_fe_state *state, - u32 bandwidth, u32 frequency_m) -{ - struct it913xset *set_tuner = set_it9137_template; - int ret, reg; - u32 frequency = frequency_m / 1000; - u32 freq, temp_f, tmp; - u16 iqik_m_cal; - u16 n_div; - u8 n; - u8 l_band; - u8 lna_band; - u8 bw; - - if (state->config->firmware_ver == 1) - set_tuner = set_it9135_template; - else - set_tuner = set_it9137_template; - - deb_info("Tuner Frequency %d Bandwidth %d", frequency, bandwidth); - - if (frequency >= 51000 && frequency <= 440000) { - l_band = 0; - lna_band = 0; - } else if (frequency > 440000 && frequency <= 484000) { - l_band = 1; - lna_band = 1; - } else if (frequency > 484000 && frequency <= 533000) { - l_band = 1; - lna_band = 2; - } else if (frequency > 533000 && frequency <= 587000) { - l_band = 1; - lna_band = 3; - } else if (frequency > 587000 && frequency <= 645000) { - l_band = 1; - lna_band = 4; - } else if (frequency > 645000 && frequency <= 710000) { - l_band = 1; - lna_band = 5; - } else if (frequency > 710000 && frequency <= 782000) { - l_band = 1; - lna_band = 6; - } else if (frequency > 782000 && frequency <= 860000) { - l_band = 1; - lna_band = 7; - } else if (frequency > 1450000 && frequency <= 1492000) { - l_band = 1; - lna_band = 0; - } else if (frequency > 1660000 && frequency <= 1685000) { - l_band = 1; - lna_band = 1; - } else - return -EINVAL; - set_tuner[0].reg[0] = lna_band; - - switch (bandwidth) { - case 5000000: - bw = 0; - break; - case 6000000: - bw = 2; - break; - case 7000000: - bw = 4; - break; - default: - case 8000000: - bw = 6; - break; - } - - set_tuner[1].reg[0] = bw; - set_tuner[2].reg[0] = 0xa0 | (l_band << 3); - - if (frequency > 53000 && frequency <= 74000) { - n_div = 48; - n = 0; - } else if (frequency > 74000 && frequency <= 111000) { - n_div = 32; - n = 1; - } else if (frequency > 111000 && frequency <= 148000) { - n_div = 24; - n = 2; - } else if (frequency > 148000 && frequency <= 222000) { - n_div = 16; - n = 3; - } else if (frequency > 222000 && frequency <= 296000) { - n_div = 12; - n = 4; - } else if (frequency > 296000 && frequency <= 445000) { - n_div = 8; - n = 5; - } else if (frequency > 445000 && frequency <= state->tun_fn_min) { - n_div = 6; - n = 6; - } else if (frequency > state->tun_fn_min && frequency <= 950000) { - n_div = 4; - n = 7; - } else if (frequency > 1450000 && frequency <= 1680000) { - n_div = 2; - n = 0; - } else - return -EINVAL; - - reg = it913x_read_reg_u8(state, 0xed81); - iqik_m_cal = (u16)reg * n_div; - - if (reg < 0x20) { - if (state->tun_clk_mode == 0) - iqik_m_cal = (iqik_m_cal * 9) >> 5; - else - iqik_m_cal >>= 1; - } else { - iqik_m_cal = 0x40 - iqik_m_cal; - if (state->tun_clk_mode == 0) - iqik_m_cal = ~((iqik_m_cal * 9) >> 5); - else - iqik_m_cal = ~(iqik_m_cal >> 1); - } - - temp_f = frequency * (u32)n_div * (u32)state->tun_fdiv; - freq = temp_f / state->tun_xtal; - tmp = freq * state->tun_xtal; - - if ((temp_f - tmp) >= (state->tun_xtal >> 1)) - freq++; - - freq += (u32) n << 13; - /* Frequency OMEGA_IQIK_M_CAL_MID*/ - temp_f = freq + (u32)iqik_m_cal; - - set_tuner[3].reg[0] = temp_f & 0xff; - set_tuner[4].reg[0] = (temp_f >> 8) & 0xff; - - deb_info("High Frequency = %04x", temp_f); - - /* Lower frequency */ - set_tuner[5].reg[0] = freq & 0xff; - set_tuner[6].reg[0] = (freq >> 8) & 0xff; - - deb_info("low Frequency = %04x", freq); - - ret = it913x_fe_script_loader(state, set_tuner); - - return (ret < 0) ? -ENODEV : 0; -} - -static int it913x_fe_select_bw(struct it913x_fe_state *state, - u32 bandwidth, u32 adcFrequency) -{ - int ret, i; - u8 buffer[256]; - u32 coeff[8]; - u16 bfsfcw_fftinx_ratio; - u16 fftinx_bfsfcw_ratio; - u8 count; - u8 bw; - u8 adcmultiplier; - - deb_info("Bandwidth %d Adc %d", bandwidth, adcFrequency); - - switch (bandwidth) { - case 5000000: - bw = 3; - break; - case 6000000: - bw = 0; - break; - case 7000000: - bw = 1; - break; - default: - case 8000000: - bw = 2; - break; - } - ret = it913x_write_reg(state, PRO_DMOD, REG_BW, bw); - - if (state->table == NULL) - return -EINVAL; - - /* In write order */ - coeff[0] = state->table[bw].coeff_1_2048; - coeff[1] = state->table[bw].coeff_2_2k; - coeff[2] = state->table[bw].coeff_1_8191; - coeff[3] = state->table[bw].coeff_1_8192; - coeff[4] = state->table[bw].coeff_1_8193; - coeff[5] = state->table[bw].coeff_2_8k; - coeff[6] = state->table[bw].coeff_1_4096; - coeff[7] = state->table[bw].coeff_2_4k; - bfsfcw_fftinx_ratio = state->table[bw].bfsfcw_fftinx_ratio; - fftinx_bfsfcw_ratio = state->table[bw].fftinx_bfsfcw_ratio; - - /* ADC multiplier */ - ret = it913x_read_reg_u8(state, ADC_X_2); - if (ret < 0) - return -EINVAL; - - adcmultiplier = ret; - - count = 0; - - /* Build Buffer for COEFF Registers */ - for (i = 0; i < 8; i++) { - if (adcmultiplier == 1) - coeff[i] /= 2; - buffer[count++] = (coeff[i] >> 24) & 0x3; - buffer[count++] = (coeff[i] >> 16) & 0xff; - buffer[count++] = (coeff[i] >> 8) & 0xff; - buffer[count++] = coeff[i] & 0xff; - } - - /* bfsfcw_fftinx_ratio register 0x21-0x22 */ - buffer[count++] = bfsfcw_fftinx_ratio & 0xff; - buffer[count++] = (bfsfcw_fftinx_ratio >> 8) & 0xff; - /* fftinx_bfsfcw_ratio register 0x23-0x24 */ - buffer[count++] = fftinx_bfsfcw_ratio & 0xff; - buffer[count++] = (fftinx_bfsfcw_ratio >> 8) & 0xff; - /* start at COEFF_1_2048 and write through to fftinx_bfsfcw_ratio*/ - ret = it913x_write(state, PRO_DMOD, COEFF_1_2048, buffer, count); - - for (i = 0; i < 42; i += 8) - debug_data_snipet(0x1, "Buffer", &buffer[i]); - - return ret; -} - - - -static int it913x_fe_read_status(struct dvb_frontend *fe, fe_status_t *status) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - int ret, i; - fe_status_t old_status = state->it913x_status; - *status = 0; - - if (state->it913x_status == 0) { - ret = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS); - if (ret == 0x1) { - *status |= FE_HAS_SIGNAL; - for (i = 0; i < 40; i++) { - ret = it913x_read_reg_u8(state, MP2IF_SYNC_LK); - if (ret == 0x1) - break; - msleep(25); - } - if (ret == 0x1) - *status |= FE_HAS_CARRIER - | FE_HAS_VITERBI - | FE_HAS_SYNC; - state->it913x_status = *status; - } - } - - if (state->it913x_status & FE_HAS_SYNC) { - ret = it913x_read_reg_u8(state, TPSD_LOCK); - if (ret == 0x1) - *status |= FE_HAS_LOCK - | state->it913x_status; - else - state->it913x_status = 0; - if (old_status != state->it913x_status) - ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, ret); - } - - return 0; -} - -/* FEC values based on fe_code_rate_t non supported values 0*/ -int it913x_qpsk_pval[] = {0, -93, -91, -90, 0, -89, -88}; -int it913x_16qam_pval[] = {0, -87, -85, -84, 0, -83, -82}; -int it913x_64qam_pval[] = {0, -82, -80, -78, 0, -77, -76}; - -static int it913x_get_signal_strength(struct dvb_frontend *fe) -{ - struct dtv_frontend_properties *p = &fe->dtv_property_cache; - struct it913x_fe_state *state = fe->demodulator_priv; - u8 code_rate; - int ret, temp; - u8 lna_gain_os; - - ret = it913x_read_reg_u8(state, VAR_P_INBAND); - if (ret < 0) - return ret; - - /* VHF/UHF gain offset */ - if (state->frequency < 300000000) - lna_gain_os = 7; - else - lna_gain_os = 14; - - temp = (ret - 100) - lna_gain_os; - - if (state->priority == PRIORITY_HIGH) - code_rate = p->code_rate_HP; - else - code_rate = p->code_rate_LP; - - if (code_rate >= ARRAY_SIZE(it913x_qpsk_pval)) - return -EINVAL; - - deb_info("Reg VAR_P_INBAND:%d Calc Offset Value:%d", ret, temp); - - /* Apply FEC offset values*/ - switch (p->modulation) { - case QPSK: - temp -= it913x_qpsk_pval[code_rate]; - break; - case QAM_16: - temp -= it913x_16qam_pval[code_rate]; - break; - case QAM_64: - temp -= it913x_64qam_pval[code_rate]; - break; - default: - return -EINVAL; - } - - if (temp < -15) - ret = 0; - else if ((-15 <= temp) && (temp < 0)) - ret = (2 * (temp + 15)) / 3; - else if ((0 <= temp) && (temp < 20)) - ret = 4 * temp + 10; - else if ((20 <= temp) && (temp < 35)) - ret = (2 * (temp - 20)) / 3 + 90; - else if (temp >= 35) - ret = 100; - - deb_info("Signal Strength :%d", ret); - - return ret; -} - -static int it913x_fe_read_signal_strength(struct dvb_frontend *fe, - u16 *strength) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - int ret = 0; - if (state->config->read_slevel) { - if (state->it913x_status & FE_HAS_SIGNAL) - ret = it913x_read_reg_u8(state, SIGNAL_LEVEL); - } else - ret = it913x_get_signal_strength(fe); - - if (ret >= 0) - *strength = (u16)((u32)ret * 0xffff / 0x64); - - return (ret < 0) ? -ENODEV : 0; -} - -static int it913x_fe_read_snr(struct dvb_frontend *fe, u16 *snr) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - int ret; - u8 reg[3]; - u32 snr_val, snr_min, snr_max; - u32 temp; - - ret = it913x_read_reg(state, 0x2c, reg, sizeof(reg)); - - snr_val = (u32)(reg[2] << 16) | (reg[1] << 8) | reg[0]; - - ret |= it913x_read_reg(state, 0xf78b, reg, 1); - if (reg[0]) - snr_val /= reg[0]; - - if (state->transmission_mode == TRANSMISSION_MODE_2K) - snr_val *= 4; - else if (state->transmission_mode == TRANSMISSION_MODE_4K) - snr_val *= 2; - - if (state->constellation == QPSK) { - snr_min = 0xb4711; - snr_max = 0x191451; - } else if (state->constellation == QAM_16) { - snr_min = 0x4f0d5; - snr_max = 0xc7925; - } else if (state->constellation == QAM_64) { - snr_min = 0x256d0; - snr_max = 0x626be; - } else - return -EINVAL; - - if (snr_val < snr_min) - *snr = 0; - else if (snr_val < snr_max) { - temp = (snr_val - snr_min) >> 5; - temp *= 0xffff; - temp /= (snr_max - snr_min) >> 5; - *snr = (u16)temp; - } else - *snr = 0xffff; - - return (ret < 0) ? -ENODEV : 0; -} - -static int it913x_fe_read_ber(struct dvb_frontend *fe, u32 *ber) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - u8 reg[5]; - /* Read Aborted Packets and Pre-Viterbi error rate 5 bytes */ - it913x_read_reg(state, RSD_ABORT_PKT_LSB, reg, sizeof(reg)); - state->ucblocks += (u32)(reg[1] << 8) | reg[0]; - *ber = (u32)(reg[4] << 16) | (reg[3] << 8) | reg[2]; - return 0; -} - -static int it913x_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - int ret; - u8 reg[2]; - /* Aborted Packets */ - ret = it913x_read_reg(state, RSD_ABORT_PKT_LSB, reg, sizeof(reg)); - state->ucblocks += (u32)(reg[1] << 8) | reg[0]; - *ucblocks = state->ucblocks; - return ret; -} - -static int it913x_fe_get_frontend(struct dvb_frontend *fe) -{ - struct dtv_frontend_properties *p = &fe->dtv_property_cache; - struct it913x_fe_state *state = fe->demodulator_priv; - u8 reg[8]; - - it913x_read_reg(state, REG_TPSD_TX_MODE, reg, sizeof(reg)); - - if (reg[3] < 3) - p->modulation = fe_con[reg[3]]; - - if (reg[0] < 3) - p->transmission_mode = fe_mode[reg[0]]; - - if (reg[1] < 4) - p->guard_interval = fe_gi[reg[1]]; - - if (reg[2] < 4) - p->hierarchy = fe_hi[reg[2]]; - - state->priority = reg[5]; - - p->code_rate_HP = (reg[6] < 6) ? fe_code[reg[6]] : FEC_NONE; - p->code_rate_LP = (reg[7] < 6) ? fe_code[reg[7]] : FEC_NONE; - - /* Update internal state to reflect the autodetected props */ - state->constellation = p->modulation; - state->transmission_mode = p->transmission_mode; - - return 0; -} - -static int it913x_fe_set_frontend(struct dvb_frontend *fe) -{ - struct dtv_frontend_properties *p = &fe->dtv_property_cache; - struct it913x_fe_state *state = fe->demodulator_priv; - int i; - u8 empty_ch, last_ch; - - state->it913x_status = 0; - - /* Set bw*/ - it913x_fe_select_bw(state, p->bandwidth_hz, - state->adcFrequency); - - /* Training Mode Off */ - it913x_write_reg(state, PRO_LINK, TRAINING_MODE, 0x0); - - /* Clear Empty Channel */ - it913x_write_reg(state, PRO_DMOD, EMPTY_CHANNEL_STATUS, 0x0); - - /* Clear bits */ - it913x_write_reg(state, PRO_DMOD, MP2IF_SYNC_LK, 0x0); - /* LED on */ - it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1); - /* Select Band*/ - if ((p->frequency >= 51000000) && (p->frequency <= 230000000)) - i = 0; - else if ((p->frequency >= 350000000) && (p->frequency <= 900000000)) - i = 1; - else if ((p->frequency >= 1450000000) && (p->frequency <= 1680000000)) - i = 2; - else - return -EOPNOTSUPP; - - it913x_write_reg(state, PRO_DMOD, FREE_BAND, i); - - deb_info("Frontend Set Tuner Type %02x", state->tuner_type); - switch (state->tuner_type) { - case IT9135_38: - case IT9135_51: - case IT9135_52: - case IT9135_60: - case IT9135_61: - case IT9135_62: - it9137_set_tuner(state, - p->bandwidth_hz, p->frequency); - break; - default: - if (fe->ops.tuner_ops.set_params) { - fe->ops.tuner_ops.set_params(fe); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - } - break; - } - /* LED off */ - it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0); - /* Trigger ofsm */ - it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0); - last_ch = 2; - for (i = 0; i < 40; ++i) { - empty_ch = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS); - if (last_ch == 1 && empty_ch == 1) - break; - if (last_ch == 2 && empty_ch == 2) - return 0; - last_ch = empty_ch; - msleep(25); - } - for (i = 0; i < 40; ++i) { - if (it913x_read_reg_u8(state, D_TPSD_LOCK) == 1) - break; - msleep(25); - } - - state->frequency = p->frequency; - return 0; -} - -static int it913x_fe_suspend(struct it913x_fe_state *state) -{ - int ret, i; - u8 b; - - ret = it913x_write_reg(state, PRO_DMOD, SUSPEND_FLAG, 0x1); - - ret |= it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0); - - for (i = 0; i < 128; i++) { - ret = it913x_read_reg(state, SUSPEND_FLAG, &b, 1); - if (ret < 0) - return -ENODEV; - if (b == 0) - break; - - } - - ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x8); - /* Turn LED off */ - ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0); - - ret |= it913x_fe_script_loader(state, it9137_tuner_off); - - return (ret < 0) ? -ENODEV : 0; -} - -/* Power sequence */ -/* Power Up Tuner on -> Frontend suspend off -> Tuner clk on */ -/* Power Down Frontend suspend on -> Tuner clk off -> Tuner off */ - -static int it913x_fe_sleep(struct dvb_frontend *fe) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - return it913x_fe_suspend(state); -} - -static u32 compute_div(u32 a, u32 b, u32 x) -{ - u32 res = 0; - u32 c = 0; - u32 i = 0; - - if (a > b) { - c = a / b; - a = a - c * b; - } - - for (i = 0; i < x; i++) { - if (a >= b) { - res += 1; - a -= b; - } - a <<= 1; - res <<= 1; - } - - res = (c << x) + res; - - return res; -} - -static int it913x_fe_start(struct it913x_fe_state *state) -{ - struct it913xset *set_lna; - struct it913xset *set_mode; - int ret; - u8 adf = (state->config->adf & 0xf); - u32 adc, xtal; - u8 b[4]; - - if (state->config->chip_ver == 1) - ret = it913x_init_tuner(state); - - info("ADF table value :%02x", adf); - - if (adf < 10) { - state->crystalFrequency = fe_clockTable[adf].xtal ; - state->table = fe_clockTable[adf].table; - state->adcFrequency = state->table->adcFrequency; - - adc = compute_div(state->adcFrequency, 1000000ul, 19ul); - xtal = compute_div(state->crystalFrequency, 1000000ul, 19ul); - - } else - return -EINVAL; - - /* Set LED indicator on GPIOH3 */ - ret = it913x_write_reg(state, PRO_LINK, GPIOH3_EN, 0x1); - ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_ON, 0x1); - ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1); - - ret |= it913x_write_reg(state, PRO_LINK, 0xf641, state->tuner_type); - ret |= it913x_write_reg(state, PRO_DMOD, 0xf5ca, 0x01); - ret |= it913x_write_reg(state, PRO_DMOD, 0xf715, 0x01); - - b[0] = xtal & 0xff; - b[1] = (xtal >> 8) & 0xff; - b[2] = (xtal >> 16) & 0xff; - b[3] = (xtal >> 24); - ret |= it913x_write(state, PRO_DMOD, XTAL_CLK, b , 4); - - b[0] = adc & 0xff; - b[1] = (adc >> 8) & 0xff; - b[2] = (adc >> 16) & 0xff; - ret |= it913x_write(state, PRO_DMOD, ADC_FREQ, b, 3); - - if (state->config->adc_x2) - ret |= it913x_write_reg(state, PRO_DMOD, ADC_X_2, 0x01); - b[0] = 0; - b[1] = 0; - b[2] = 0; - ret |= it913x_write(state, PRO_DMOD, 0x0029, b, 3); - - info("Crystal Frequency :%d Adc Frequency :%d ADC X2: %02x", - state->crystalFrequency, state->adcFrequency, - state->config->adc_x2); - deb_info("Xtal value :%04x Adc value :%04x", xtal, adc); - - if (ret < 0) - return -ENODEV; - - /* v1 or v2 tuner script */ - if (state->config->chip_ver > 1) - ret = it913x_fe_script_loader(state, it9135_v2); - else - ret = it913x_fe_script_loader(state, it9135_v1); - if (ret < 0) - return ret; - - /* LNA Scripts */ - switch (state->tuner_type) { - case IT9135_51: - set_lna = it9135_51; - break; - case IT9135_52: - set_lna = it9135_52; - break; - case IT9135_60: - set_lna = it9135_60; - break; - case IT9135_61: - set_lna = it9135_61; - break; - case IT9135_62: - set_lna = it9135_62; - break; - case IT9135_38: - default: - set_lna = it9135_38; - } - info("Tuner LNA type :%02x", state->tuner_type); - - ret = it913x_fe_script_loader(state, set_lna); - if (ret < 0) - return ret; - - if (state->config->chip_ver == 2) { - ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x1); - ret |= it913x_write_reg(state, PRO_LINK, PADODPU, 0x0); - ret |= it913x_write_reg(state, PRO_LINK, AGC_O_D, 0x0); - ret |= it913x_init_tuner(state); - } - if (ret < 0) - return -ENODEV; - - /* Always solo frontend */ - set_mode = set_solo_fe; - ret |= it913x_fe_script_loader(state, set_mode); - - ret |= it913x_fe_suspend(state); - return (ret < 0) ? -ENODEV : 0; -} - -static int it913x_fe_init(struct dvb_frontend *fe) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - int ret = 0; - /* Power Up Tuner - common all versions */ - ret = it913x_write_reg(state, PRO_DMOD, 0xec40, 0x1); - - ret |= it913x_fe_script_loader(state, init_1); - - ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x0); - - ret |= it913x_write_reg(state, PRO_DMOD, 0xfba8, 0x0); - - return (ret < 0) ? -ENODEV : 0; -} - -static void it913x_fe_release(struct dvb_frontend *fe) -{ - struct it913x_fe_state *state = fe->demodulator_priv; - kfree(state); -} - -static struct dvb_frontend_ops it913x_fe_ofdm_ops; - -struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap, - u8 i2c_addr, struct ite_config *config) -{ - struct it913x_fe_state *state = NULL; - int ret; - - /* allocate memory for the internal state */ - state = kzalloc(sizeof(struct it913x_fe_state), GFP_KERNEL); - if (state == NULL) - return NULL; - if (config == NULL) - goto error; - - state->i2c_adap = i2c_adap; - state->i2c_addr = i2c_addr; - state->config = config; - - switch (state->config->tuner_id_0) { - case IT9135_51: - case IT9135_52: - case IT9135_60: - case IT9135_61: - case IT9135_62: - state->tuner_type = state->config->tuner_id_0; - break; - default: - case IT9135_38: - state->tuner_type = IT9135_38; - } - - ret = it913x_fe_start(state); - if (ret < 0) - goto error; - - - /* create dvb_frontend */ - memcpy(&state->frontend.ops, &it913x_fe_ofdm_ops, - sizeof(struct dvb_frontend_ops)); - state->frontend.demodulator_priv = state; - - return &state->frontend; -error: - kfree(state); - return NULL; -} -EXPORT_SYMBOL(it913x_fe_attach); - -static struct dvb_frontend_ops it913x_fe_ofdm_ops = { - .delsys = { SYS_DVBT }, - .info = { - .name = "it913x-fe DVB-T", - .frequency_min = 51000000, - .frequency_max = 1680000000, - .frequency_stepsize = 62500, - .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | - FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | - FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO | - FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | - FE_CAN_GUARD_INTERVAL_AUTO | - FE_CAN_HIERARCHY_AUTO, - }, - - .release = it913x_fe_release, - - .init = it913x_fe_init, - .sleep = it913x_fe_sleep, - - .set_frontend = it913x_fe_set_frontend, - .get_frontend = it913x_fe_get_frontend, - - .read_status = it913x_fe_read_status, - .read_signal_strength = it913x_fe_read_signal_strength, - .read_snr = it913x_fe_read_snr, - .read_ber = it913x_fe_read_ber, - .read_ucblocks = it913x_fe_read_ucblocks, -}; - -MODULE_DESCRIPTION("it913x Frontend and it9137 tuner"); -MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com"); -MODULE_VERSION("1.15"); -MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb-frontends/it913x-fe.h b/drivers/media/dvb-frontends/it913x-fe.h deleted file mode 100644 index df0ad42..0000000 --- a/drivers/media/dvb-frontends/it913x-fe.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Driver for it913x Frontend - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= - */ - -#ifndef IT913X_FE_H -#define IT913X_FE_H - -#include <linux/kconfig.h> -#include <linux/dvb/frontend.h> -#include "dvb_frontend.h" - -struct ite_config { - u8 chip_ver; - u16 chip_type; - u32 firmware; - u8 firmware_ver; - u8 adc_x2; - u8 tuner_id_0; - u8 tuner_id_1; - u8 dual_mode; - u8 adf; - /* option to read SIGNAL_LEVEL */ - u8 read_slevel; -}; - -#if IS_ENABLED(CONFIG_DVB_IT913X_FE) -extern struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap, - u8 i2c_addr, struct ite_config *config); -#else -static inline struct dvb_frontend *it913x_fe_attach( - struct i2c_adapter *i2c_adap, - u8 i2c_addr, struct ite_config *config) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} -#endif /* CONFIG_IT913X_FE */ -#define I2C_BASE_ADDR 0x10 -#define DEV_0 0x0 -#define DEV_1 0x10 -#define PRO_LINK 0x0 -#define PRO_DMOD 0x1 -#define DEV_0_DMOD (PRO_DMOD << 0x7) -#define DEV_1_DMOD (DEV_0_DMOD | DEV_1) -#define CHIP2_I2C_ADDR 0x3a - -#define AFE_MEM0 0xfb24 - -#define MP2_SW_RST 0xf99d -#define MP2IF2_SW_RST 0xf9a4 - -#define PADODPU 0xd827 -#define THIRDODPU 0xd828 -#define AGC_O_D 0xd829 - -#define EP0_TX_EN 0xdd11 -#define EP0_TX_NAK 0xdd13 -#define EP4_TX_LEN_LSB 0xdd88 -#define EP4_TX_LEN_MSB 0xdd89 -#define EP4_MAX_PKT 0xdd0c -#define EP5_TX_LEN_LSB 0xdd8a -#define EP5_TX_LEN_MSB 0xdd8b -#define EP5_MAX_PKT 0xdd0d - -#define IO_MUX_POWER_CLK 0xd800 -#define CLK_O_EN 0xd81a -#define I2C_CLK 0xf103 -#define I2C_CLK_100 0x7 -#define I2C_CLK_400 0x1a - -#define D_TPSD_LOCK 0xf5a9 -#define MP2IF2_EN 0xf9a3 -#define MP2IF_SERIAL 0xf985 -#define TSIS_ENABLE 0xf9cd -#define MP2IF2_HALF_PSB 0xf9a5 -#define MP2IF_STOP_EN 0xf9b5 -#define MPEG_FULL_SPEED 0xf990 -#define TOP_HOSTB_SER_MODE 0xd91c - -#define PID_RST 0xf992 -#define PID_EN 0xf993 -#define PID_INX_EN 0xf994 -#define PID_INX 0xf995 -#define PID_LSB 0xf996 -#define PID_MSB 0xf997 - -#define MP2IF_MPEG_PAR_MODE 0xf986 -#define DCA_UPPER_CHIP 0xf731 -#define DCA_LOWER_CHIP 0xf732 -#define DCA_PLATCH 0xf730 -#define DCA_FPGA_LATCH 0xf778 -#define DCA_STAND_ALONE 0xf73c -#define DCA_ENABLE 0xf776 - -#define DVBT_INTEN 0xf41f -#define DVBT_ENABLE 0xf41a -#define HOSTB_DCA_LOWER 0xd91f -#define HOSTB_MPEG_PAR_MODE 0xd91b -#define HOSTB_MPEG_SER_MODE 0xd91c -#define HOSTB_MPEG_SER_DO7 0xd91d -#define HOSTB_DCA_UPPER 0xd91e -#define PADMISCDR2 0xd830 -#define PADMISCDR4 0xd831 -#define PADMISCDR8 0xd832 -#define PADMISCDRSR 0xd833 -#define LOCK3_OUT 0xd8fd - -#define GPIOH1_O 0xd8af -#define GPIOH1_EN 0xd8b0 -#define GPIOH1_ON 0xd8b1 -#define GPIOH3_O 0xd8b3 -#define GPIOH3_EN 0xd8b4 -#define GPIOH3_ON 0xd8b5 -#define GPIOH5_O 0xd8bb -#define GPIOH5_EN 0xd8bc -#define GPIOH5_ON 0xd8bd - -#define AFE_MEM0 0xfb24 - -#define REG_TPSD_TX_MODE 0xf900 -#define REG_TPSD_GI 0xf901 -#define REG_TPSD_HIER 0xf902 -#define REG_TPSD_CONST 0xf903 -#define REG_BW 0xf904 -#define REG_PRIV 0xf905 -#define REG_TPSD_HP_CODE 0xf906 -#define REG_TPSD_LP_CODE 0xf907 - -#define MP2IF_SYNC_LK 0xf999 -#define ADC_FREQ 0xf1cd - -#define TRIGGER_OFSM 0x0000 -/* COEFF Registers start at 0x0001 to 0x0020 */ -#define COEFF_1_2048 0x0001 -#define XTAL_CLK 0x0025 -#define BFS_FCW 0x0029 - -/* Error Regs */ -#define RSD_ABORT_PKT_LSB 0x0032 -#define RSD_ABORT_PKT_MSB 0x0033 -#define RSD_BIT_ERR_0_7 0x0034 -#define RSD_BIT_ERR_8_15 0x0035 -#define RSD_BIT_ERR_23_16 0x0036 -#define RSD_BIT_COUNT_LSB 0x0037 -#define RSD_BIT_COUNT_MSB 0x0038 - -#define TPSD_LOCK 0x003c -#define TRAINING_MODE 0x0040 -#define ADC_X_2 0x0045 -#define TUNER_ID 0x0046 -#define EMPTY_CHANNEL_STATUS 0x0047 -#define SIGNAL_LEVEL 0x0048 -#define SIGNAL_QUALITY 0x0049 -#define EST_SIGNAL_LEVEL 0x004a -#define FREE_BAND 0x004b -#define SUSPEND_FLAG 0x004c -#define VAR_P_INBAND 0x00f7 - -/* Build in tuner types */ -#define IT9137 0x38 -#define IT9135_38 0x38 -#define IT9135_51 0x51 -#define IT9135_52 0x52 -#define IT9135_60 0x60 -#define IT9135_61 0x61 -#define IT9135_62 0x62 - -enum { - CMD_DEMOD_READ = 0, - CMD_DEMOD_WRITE, - CMD_TUNER_READ, - CMD_TUNER_WRITE, - CMD_REG_EEPROM_READ, - CMD_REG_EEPROM_WRITE, - CMD_DATA_READ, - CMD_VAR_READ = 8, - CMD_VAR_WRITE, - CMD_PLATFORM_GET, - CMD_PLATFORM_SET, - CMD_IP_CACHE, - CMD_IP_ADD, - CMD_IP_REMOVE, - CMD_PID_ADD, - CMD_PID_REMOVE, - CMD_SIPSI_GET, - CMD_SIPSI_MPE_RESET, - CMD_H_PID_ADD = 0x15, - CMD_H_PID_REMOVE, - CMD_ABORT, - CMD_IR_GET, - CMD_IR_SET, - CMD_FW_DOWNLOAD = 0x21, - CMD_QUERYINFO, - CMD_BOOT, - CMD_FW_DOWNLOAD_BEGIN, - CMD_FW_DOWNLOAD_END, - CMD_RUN_CODE, - CMD_SCATTER_READ = 0x28, - CMD_SCATTER_WRITE, - CMD_GENERIC_READ, - CMD_GENERIC_WRITE -}; - -enum { - READ_LONG, - WRITE_LONG, - READ_SHORT, - WRITE_SHORT, - READ_DATA, - WRITE_DATA, - WRITE_CMD, -}; - -enum { - IT9135_AUTO = 0, - IT9137_FW, - IT9135_V1_FW, - IT9135_V2_FW, -}; - -#endif /* IT913X_FE_H */ diff --git a/drivers/media/dvb-frontends/m88ds3103.c b/drivers/media/dvb-frontends/m88ds3103.c index b8a7897..2ef8ce1 100644 --- a/drivers/media/dvb-frontends/m88ds3103.c +++ b/drivers/media/dvb-frontends/m88ds3103.c @@ -271,6 +271,13 @@ static int m88ds3103_set_frontend(struct dvb_frontend *fe) ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency); if (ret) goto err; + } else { + /* + * Use nominal target frequency as tuner driver does not provide + * actual frequency used. Carrier offset calculation is not + * valid. + */ + tuner_frequency = c->frequency; } /* reset */ @@ -428,18 +435,10 @@ static int m88ds3103_set_frontend(struct dvb_frontend *fe) goto err; switch (target_mclk) { - case 72000: - u8tmp1 = 0x00; /* 0b00 */ - u8tmp2 = 0x03; /* 0b11 */ - break; case 96000: u8tmp1 = 0x02; /* 0b10 */ u8tmp2 = 0x01; /* 0b01 */ break; - case 115200: - u8tmp1 = 0x01; /* 0b01 */ - u8tmp2 = 0x01; /* 0b01 */ - break; case 144000: u8tmp1 = 0x00; /* 0b00 */ u8tmp2 = 0x01; /* 0b01 */ @@ -448,10 +447,6 @@ static int m88ds3103_set_frontend(struct dvb_frontend *fe) u8tmp1 = 0x03; /* 0b11 */ u8tmp2 = 0x00; /* 0b00 */ break; - default: - dev_dbg(&priv->i2c->dev, "%s: invalid target_mclk\n", __func__); - ret = -EINVAL; - goto err; } ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0); @@ -711,9 +706,6 @@ static int m88ds3103_get_frontend(struct dvb_frontend *fe) case 1: c->inversion = INVERSION_ON; break; - default: - dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n", - __func__); } switch ((buf[1] >> 5) & 0x07) { @@ -793,9 +785,6 @@ static int m88ds3103_get_frontend(struct dvb_frontend *fe) case 1: c->pilot = PILOT_ON; break; - default: - dev_dbg(&priv->i2c->dev, "%s: invalid pilot\n", - __func__); } switch ((buf[0] >> 6) & 0x07) { @@ -823,9 +812,6 @@ static int m88ds3103_get_frontend(struct dvb_frontend *fe) case 1: c->inversion = INVERSION_ON; break; - default: - dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n", - __func__); } switch ((buf[2] >> 0) & 0x03) { @@ -958,7 +944,7 @@ static int m88ds3103_set_tone(struct dvb_frontend *fe, switch (fe_sec_tone_mode) { case SEC_TONE_ON: tone = 0; - reg_a1_mask = 0x87; + reg_a1_mask = 0x47; break; case SEC_TONE_OFF: tone = 1; diff --git a/drivers/media/dvb-frontends/m88rs2000.c b/drivers/media/dvb-frontends/m88rs2000.c index b235146..32cffca 100644 --- a/drivers/media/dvb-frontends/m88rs2000.c +++ b/drivers/media/dvb-frontends/m88rs2000.c @@ -715,6 +715,22 @@ static int m88rs2000_get_frontend(struct dvb_frontend *fe) return 0; } +static int m88rs2000_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *tune) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + + if (c->symbol_rate > 3000000) + tune->min_delay_ms = 2000; + else + tune->min_delay_ms = 3000; + + tune->step_size = c->symbol_rate / 16000; + tune->max_drift = c->symbol_rate / 2000; + + return 0; +} + static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) { struct m88rs2000_state *state = fe->demodulator_priv; @@ -746,7 +762,7 @@ static struct dvb_frontend_ops m88rs2000_ops = { .symbol_rate_tolerance = 500, /* ppm */ .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | - FE_CAN_QPSK | + FE_CAN_QPSK | FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO }, @@ -766,6 +782,7 @@ static struct dvb_frontend_ops m88rs2000_ops = { .set_frontend = m88rs2000_set_frontend, .get_frontend = m88rs2000_get_frontend, + .get_tune_settings = m88rs2000_get_tune_settings, }; struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config, diff --git a/drivers/media/dvb-frontends/mb86a20s.c b/drivers/media/dvb-frontends/mb86a20s.c index 2c7217f..2f458bb 100644 --- a/drivers/media/dvb-frontends/mb86a20s.c +++ b/drivers/media/dvb-frontends/mb86a20s.c @@ -1,7 +1,7 @@ /* * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver * - * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2010-2013 Mauro Carvalho Chehab * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com> * * This program is free software; you can redistribute it and/or @@ -2156,5 +2156,5 @@ static struct dvb_frontend_ops mb86a20s_ops = { }; MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb-frontends/mb86a20s.h b/drivers/media/dvb-frontends/mb86a20s.h index 6627a39..cbeb941 100644 --- a/drivers/media/dvb-frontends/mb86a20s.h +++ b/drivers/media/dvb-frontends/mb86a20s.h @@ -1,7 +1,7 @@ /* * Fujitsu mb86a20s driver * - * Copyright (C) 2010 Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2010 Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/drivers/media/dvb-frontends/rtl2832.c b/drivers/media/dvb-frontends/rtl2832.c index ff73da9..fdbed35 100644 --- a/drivers/media/dvb-frontends/rtl2832.c +++ b/drivers/media/dvb-frontends/rtl2832.c @@ -24,11 +24,6 @@ /* Max transfer size done by I2C transfer functions */ #define MAX_XFER_SIZE 64 - -int rtl2832_debug; -module_param_named(debug, rtl2832_debug, int, 0644); -MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); - #define REG_MASK(b) (BIT(b + 1) - 1) static const struct rtl2832_reg_entry registers[] = { @@ -185,12 +180,13 @@ static int rtl2832_wr(struct rtl2832_priv *priv, u8 reg, u8 *val, int len) buf[0] = reg; memcpy(&buf[1], val, len); - ret = i2c_transfer(priv->i2c, msg, 1); + ret = i2c_transfer(priv->i2c_adapter, msg, 1); if (ret == 1) { ret = 0; } else { - dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \ - "len=%d\n", KBUILD_MODNAME, ret, reg, len); + dev_warn(&priv->i2c->dev, + "%s: i2c wr failed=%d reg=%02x len=%d\n", + KBUILD_MODNAME, ret, reg, len); ret = -EREMOTEIO; } return ret; @@ -214,12 +210,13 @@ static int rtl2832_rd(struct rtl2832_priv *priv, u8 reg, u8 *val, int len) } }; - ret = i2c_transfer(priv->i2c, msg, 2); + ret = i2c_transfer(priv->i2c_adapter, msg, 2); if (ret == 2) { ret = 0; } else { - dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \ - "len=%d\n", KBUILD_MODNAME, ret, reg, len); + dev_warn(&priv->i2c->dev, + "%s: i2c rd failed=%d reg=%02x len=%d\n", + KBUILD_MODNAME, ret, reg, len); ret = -EREMOTEIO; } return ret; @@ -417,7 +414,7 @@ static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq) ret = rtl2832_wr_demod_reg(priv, DVBT_PSET_IFFREQ, pset_iffreq); - return (ret); + return ret; } static int rtl2832_init(struct dvb_frontend *fe) @@ -514,15 +511,10 @@ static int rtl2832_init(struct dvb_frontend *fe) goto err; } - if (!fe->ops.tuner_ops.get_if_frequency) { - ret = rtl2832_set_if(fe, priv->cfg.if_dvbt); - if (ret) - goto err; - } - /* * r820t NIM code does a software reset here at the demod - - * may not be needed, as there's already a software reset at set_params() + * may not be needed, as there's already a software reset at + * set_params() */ #if 1 /* soft reset */ @@ -599,9 +591,9 @@ static int rtl2832_set_frontend(struct dvb_frontend *fe) }; - dev_dbg(&priv->i2c->dev, "%s: frequency=%d bandwidth_hz=%d " \ - "inversion=%d\n", __func__, c->frequency, - c->bandwidth_hz, c->inversion); + dev_dbg(&priv->i2c->dev, + "%s: frequency=%d bandwidth_hz=%d inversion=%d\n", + __func__, c->frequency, c->bandwidth_hz, c->inversion); /* program tuner */ if (fe->ops.tuner_ops.set_params) @@ -899,9 +891,149 @@ static void rtl2832_release(struct dvb_frontend *fe) struct rtl2832_priv *priv = fe->demodulator_priv; dev_dbg(&priv->i2c->dev, "%s:\n", __func__); + cancel_delayed_work_sync(&priv->i2c_gate_work); + i2c_del_mux_adapter(priv->i2c_adapter_tuner); + i2c_del_mux_adapter(priv->i2c_adapter); kfree(priv); } +/* + * Delay mechanism to avoid unneeded I2C gate open / close. Gate close is + * delayed here a little bit in order to see if there is sequence of I2C + * messages sent to same I2C bus. + * We must use unlocked version of __i2c_transfer() in order to avoid deadlock + * as lock is already taken by calling muxed i2c_transfer(). + */ +static void rtl2832_i2c_gate_work(struct work_struct *work) +{ + struct rtl2832_priv *priv = container_of(work, + struct rtl2832_priv, i2c_gate_work.work); + struct i2c_adapter *adap = priv->i2c; + int ret; + u8 buf[2]; + struct i2c_msg msg[1] = { + { + .addr = priv->cfg.i2c_addr, + .flags = 0, + .len = sizeof(buf), + .buf = buf, + } + }; + + /* select reg bank 1 */ + buf[0] = 0x00; + buf[1] = 0x01; + ret = __i2c_transfer(adap, msg, 1); + if (ret != 1) + goto err; + + priv->page = 1; + + /* close I2C repeater gate */ + buf[0] = 0x01; + buf[1] = 0x10; + ret = __i2c_transfer(adap, msg, 1); + if (ret != 1) + goto err; + + priv->i2c_gate_state = 0; + + return; +err: + dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); + + return; +} + +static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id) +{ + struct rtl2832_priv *priv = mux_priv; + int ret; + u8 buf[2], val; + struct i2c_msg msg[1] = { + { + .addr = priv->cfg.i2c_addr, + .flags = 0, + .len = sizeof(buf), + .buf = buf, + } + }; + struct i2c_msg msg_rd[2] = { + { + .addr = priv->cfg.i2c_addr, + .flags = 0, + .len = 1, + .buf = "\x01", + }, { + .addr = priv->cfg.i2c_addr, + .flags = I2C_M_RD, + .len = 1, + .buf = &val, + } + }; + + /* terminate possible gate closing */ + cancel_delayed_work_sync(&priv->i2c_gate_work); + + if (priv->i2c_gate_state == chan_id) + return 0; + + /* select reg bank 1 */ + buf[0] = 0x00; + buf[1] = 0x01; + ret = __i2c_transfer(adap, msg, 1); + if (ret != 1) + goto err; + + priv->page = 1; + + /* we must read that register, otherwise there will be errors */ + ret = __i2c_transfer(adap, msg_rd, 2); + if (ret != 2) + goto err; + + /* open or close I2C repeater gate */ + buf[0] = 0x01; + if (chan_id == 1) + buf[1] = 0x18; /* open */ + else + buf[1] = 0x10; /* close */ + + ret = __i2c_transfer(adap, msg, 1); + if (ret != 1) + goto err; + + priv->i2c_gate_state = chan_id; + + return 0; +err: + dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); + + return -EREMOTEIO; +} + +static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv, + u32 chan_id) +{ + struct rtl2832_priv *priv = mux_priv; + schedule_delayed_work(&priv->i2c_gate_work, usecs_to_jiffies(100)); + return 0; +} + +struct i2c_adapter *rtl2832_get_i2c_adapter(struct dvb_frontend *fe) +{ + struct rtl2832_priv *priv = fe->demodulator_priv; + return priv->i2c_adapter_tuner; +} +EXPORT_SYMBOL(rtl2832_get_i2c_adapter); + +struct i2c_adapter *rtl2832_get_private_i2c_adapter(struct dvb_frontend *fe) +{ + struct rtl2832_priv *priv = fe->demodulator_priv; + return priv->i2c_adapter; +} +EXPORT_SYMBOL(rtl2832_get_private_i2c_adapter); + struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg, struct i2c_adapter *i2c) { @@ -920,12 +1052,25 @@ struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg, priv->i2c = i2c; priv->tuner = cfg->tuner; memcpy(&priv->cfg, cfg, sizeof(struct rtl2832_config)); + INIT_DELAYED_WORK(&priv->i2c_gate_work, rtl2832_i2c_gate_work); + + /* create muxed i2c adapter for demod itself */ + priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0, + rtl2832_select, NULL); + if (priv->i2c_adapter == NULL) + goto err; /* check if the demod is there */ ret = rtl2832_rd_reg(priv, 0x00, 0x0, &tmp); if (ret) goto err; + /* create muxed i2c adapter for demod tuner bus */ + priv->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, priv, + 0, 1, 0, rtl2832_select, rtl2832_deselect); + if (priv->i2c_adapter_tuner == NULL) + goto err; + /* create dvb_frontend */ memcpy(&priv->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops)); priv->fe.demodulator_priv = priv; @@ -936,6 +1081,8 @@ struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg, return &priv->fe; err: dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret); + if (priv && priv->i2c_adapter) + i2c_del_mux_adapter(priv->i2c_adapter); kfree(priv); return NULL; } diff --git a/drivers/media/dvb-frontends/rtl2832.h b/drivers/media/dvb-frontends/rtl2832.h index 2cfbb6a..cb3b6b0 100644 --- a/drivers/media/dvb-frontends/rtl2832.h +++ b/drivers/media/dvb-frontends/rtl2832.h @@ -38,13 +38,6 @@ struct rtl2832_config { u32 xtal; /* - * IFs for all used modes. - * Hz - * 4570000, 4571429, 36000000, 36125000, 36166667, 44000000 - */ - u32 if_dvbt; - - /* * tuner * XXX: This must be keep sync with dvb_usb_rtl28xxu demod driver. */ @@ -58,11 +51,21 @@ struct rtl2832_config { }; #if IS_ENABLED(CONFIG_DVB_RTL2832) -extern struct dvb_frontend *rtl2832_attach( +struct dvb_frontend *rtl2832_attach( const struct rtl2832_config *cfg, struct i2c_adapter *i2c ); + +extern struct i2c_adapter *rtl2832_get_i2c_adapter( + struct dvb_frontend *fe +); + +extern struct i2c_adapter *rtl2832_get_private_i2c_adapter( + struct dvb_frontend *fe +); + #else + static inline struct dvb_frontend *rtl2832_attach( const struct rtl2832_config *config, struct i2c_adapter *i2c @@ -71,6 +74,21 @@ static inline struct dvb_frontend *rtl2832_attach( pr_warn("%s: driver disabled by Kconfig\n", __func__); return NULL; } + +static inline struct i2c_adapter *rtl2832_get_i2c_adapter( + struct dvb_frontend *fe +) +{ + return NULL; +} + +static inline struct i2c_adapter *rtl2832_get_private_i2c_adapter( + struct dvb_frontend *fe +) +{ + return NULL; +} + #endif diff --git a/drivers/media/dvb-frontends/rtl2832_priv.h b/drivers/media/dvb-frontends/rtl2832_priv.h index b5f2b80..ae469f0 100644 --- a/drivers/media/dvb-frontends/rtl2832_priv.h +++ b/drivers/media/dvb-frontends/rtl2832_priv.h @@ -23,9 +23,12 @@ #include "dvb_frontend.h" #include "rtl2832.h" +#include <linux/i2c-mux.h> struct rtl2832_priv { struct i2c_adapter *i2c; + struct i2c_adapter *i2c_adapter; + struct i2c_adapter *i2c_adapter_tuner; struct dvb_frontend fe; struct rtl2832_config cfg; @@ -34,6 +37,7 @@ struct rtl2832_priv { u8 tuner; u8 page; /* active register page */ + struct delayed_work i2c_gate_work; }; struct rtl2832_reg_entry { @@ -267,7 +271,7 @@ static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = { {DVBT_OPT_ADC_IQ, 0x1}, {DVBT_AD_AVI, 0x0}, {DVBT_AD_AVQ, 0x0}, - {DVBT_SPEC_INV, 0x0}, + {DVBT_SPEC_INV, 0x0}, }; static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = { @@ -301,7 +305,7 @@ static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = { {DVBT_GI_PGA_STATE, 0x0}, {DVBT_EN_AGC_PGA, 0x1}, {DVBT_IF_AGC_MAN, 0x0}, - {DVBT_SPEC_INV, 0x0}, + {DVBT_SPEC_INV, 0x0}, }; static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = { @@ -339,32 +343,32 @@ static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = { {DVBT_REG_MONSEL, 0x1}, {DVBT_REG_MON, 0x1}, {DVBT_REG_4MSEL, 0x0}, - {DVBT_SPEC_INV, 0x0}, + {DVBT_SPEC_INV, 0x0}, }; static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = { - {DVBT_DAGC_TRG_VAL, 0x39}, - {DVBT_AGC_TARG_VAL_0, 0x0}, - {DVBT_AGC_TARG_VAL_8_1, 0x40}, - {DVBT_AAGC_LOOP_GAIN, 0x16}, - {DVBT_LOOP_GAIN2_3_0, 0x8}, - {DVBT_LOOP_GAIN2_4, 0x1}, - {DVBT_LOOP_GAIN3, 0x18}, - {DVBT_VTOP1, 0x35}, - {DVBT_VTOP2, 0x21}, - {DVBT_VTOP3, 0x21}, - {DVBT_KRF1, 0x0}, - {DVBT_KRF2, 0x40}, - {DVBT_KRF3, 0x10}, - {DVBT_KRF4, 0x10}, - {DVBT_IF_AGC_MIN, 0x80}, - {DVBT_IF_AGC_MAX, 0x7f}, - {DVBT_RF_AGC_MIN, 0x80}, - {DVBT_RF_AGC_MAX, 0x7f}, - {DVBT_POLAR_RF_AGC, 0x0}, - {DVBT_POLAR_IF_AGC, 0x0}, - {DVBT_AD7_SETTING, 0xe9f4}, - {DVBT_SPEC_INV, 0x1}, + {DVBT_DAGC_TRG_VAL, 0x39}, + {DVBT_AGC_TARG_VAL_0, 0x0}, + {DVBT_AGC_TARG_VAL_8_1, 0x40}, + {DVBT_AAGC_LOOP_GAIN, 0x16}, + {DVBT_LOOP_GAIN2_3_0, 0x8}, + {DVBT_LOOP_GAIN2_4, 0x1}, + {DVBT_LOOP_GAIN3, 0x18}, + {DVBT_VTOP1, 0x35}, + {DVBT_VTOP2, 0x21}, + {DVBT_VTOP3, 0x21}, + {DVBT_KRF1, 0x0}, + {DVBT_KRF2, 0x40}, + {DVBT_KRF3, 0x10}, + {DVBT_KRF4, 0x10}, + {DVBT_IF_AGC_MIN, 0x80}, + {DVBT_IF_AGC_MAX, 0x7f}, + {DVBT_RF_AGC_MIN, 0x80}, + {DVBT_RF_AGC_MAX, 0x7f}, + {DVBT_POLAR_RF_AGC, 0x0}, + {DVBT_POLAR_IF_AGC, 0x0}, + {DVBT_AD7_SETTING, 0xe9f4}, + {DVBT_SPEC_INV, 0x1}, }; #endif /* RTL2832_PRIV_H */ diff --git a/drivers/media/dvb-frontends/s921.c b/drivers/media/dvb-frontends/s921.c index a271ac3..69862e1 100644 --- a/drivers/media/dvb-frontends/s921.c +++ b/drivers/media/dvb-frontends/s921.c @@ -2,7 +2,7 @@ * Sharp VA3A5JZ921 One Seg Broadcast Module driver * This device is labeled as just S. 921 at the top of the frontend can * - * Copyright (C) 2009-2010 Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2009-2010 Mauro Carvalho Chehab * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com> * * Developed for Leadership SBTVD 1seg device sold in Brazil @@ -539,6 +539,6 @@ static struct dvb_frontend_ops s921_ops = { }; MODULE_DESCRIPTION("DVB Frontend module for Sharp S921 hardware"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_AUTHOR("Douglas Landgraf <dougsland@redhat.com>"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb-frontends/s921.h b/drivers/media/dvb-frontends/s921.h index 8d5e2a6..9b20c9e 100644 --- a/drivers/media/dvb-frontends/s921.h +++ b/drivers/media/dvb-frontends/s921.h @@ -1,7 +1,7 @@ /* * Sharp s921 driver * - * Copyright (C) 2009 Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2009 Mauro Carvalho Chehab * Copyright (C) 2009 Douglas Landgraf <dougsland@redhat.com> * * This program is free software; you can redistribute it and/or diff --git a/drivers/media/dvb-frontends/stb6100.c b/drivers/media/dvb-frontends/stb6100.c index cea175d..4ef8a5c 100644 --- a/drivers/media/dvb-frontends/stb6100.c +++ b/drivers/media/dvb-frontends/stb6100.c @@ -193,7 +193,7 @@ static int stb6100_write_reg_range(struct stb6100_state *state, u8 buf[], int st .len = len + 1 }; - if (1 + len > sizeof(buf)) { + if (1 + len > sizeof(cmdbuf)) { printk(KERN_WARNING "%s: i2c wr: len=%d is too big!\n", KBUILD_MODNAME, len); diff --git a/drivers/media/dvb-frontends/stv0900_sw.c b/drivers/media/dvb-frontends/stv0900_sw.c index 0a40edf..4ce1d26 100644 --- a/drivers/media/dvb-frontends/stv0900_sw.c +++ b/drivers/media/dvb-frontends/stv0900_sw.c @@ -1081,7 +1081,7 @@ static int stv0900_wait_for_lock(struct stv0900_internal *intp, lock = stv0900_get_demod_lock(intp, demod, dmd_timeout); if (lock) - lock = lock && stv0900_get_fec_lock(intp, demod, fec_timeout); + lock = stv0900_get_fec_lock(intp, demod, fec_timeout); if (lock) { lock = 0; diff --git a/drivers/media/dvb-frontends/tda10071.c b/drivers/media/dvb-frontends/tda10071.c index 8ad3a57..522fe00 100644 --- a/drivers/media/dvb-frontends/tda10071.c +++ b/drivers/media/dvb-frontends/tda10071.c @@ -42,8 +42,8 @@ static int tda10071_wr_regs(struct tda10071_priv *priv, u8 reg, u8 *val, if (1 + len > sizeof(buf)) { dev_warn(&priv->i2c->dev, - "%s: i2c wr reg=%04x: len=%d is too big!\n", - KBUILD_MODNAME, reg, len); + "%s: i2c wr reg=%04x: len=%d is too big!\n", + KBUILD_MODNAME, reg, len); return -EINVAL; } @@ -54,8 +54,9 @@ static int tda10071_wr_regs(struct tda10071_priv *priv, u8 reg, u8 *val, if (ret == 1) { ret = 0; } else { - dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \ - "len=%d\n", KBUILD_MODNAME, ret, reg, len); + dev_warn(&priv->i2c->dev, + "%s: i2c wr failed=%d reg=%02x len=%d\n", + KBUILD_MODNAME, ret, reg, len); ret = -EREMOTEIO; } return ret; @@ -83,8 +84,8 @@ static int tda10071_rd_regs(struct tda10071_priv *priv, u8 reg, u8 *val, if (len > sizeof(buf)) { dev_warn(&priv->i2c->dev, - "%s: i2c wr reg=%04x: len=%d is too big!\n", - KBUILD_MODNAME, reg, len); + "%s: i2c wr reg=%04x: len=%d is too big!\n", + KBUILD_MODNAME, reg, len); return -EINVAL; } @@ -93,8 +94,9 @@ static int tda10071_rd_regs(struct tda10071_priv *priv, u8 reg, u8 *val, memcpy(val, buf, len); ret = 0; } else { - dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \ - "len=%d\n", KBUILD_MODNAME, ret, reg, len); + dev_warn(&priv->i2c->dev, + "%s: i2c rd failed=%d reg=%02x len=%d\n", + KBUILD_MODNAME, ret, reg, len); ret = -EREMOTEIO; } return ret; @@ -491,10 +493,9 @@ static int tda10071_read_status(struct dvb_frontend *fe, fe_status_t *status) if (ret) goto error; - if (tmp & 0x01) /* tuner PLL */ - *status |= FE_HAS_SIGNAL; + /* 0x39[0] tuner PLL */ if (tmp & 0x02) /* demod PLL */ - *status |= FE_HAS_CARRIER; + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; if (tmp & 0x04) /* viterbi or LDPC*/ *status |= FE_HAS_VITERBI; if (tmp & 0x08) /* RS or BCH */ @@ -668,11 +669,11 @@ static int tda10071_set_frontend(struct dvb_frontend *fe) int ret, i; u8 mode, rolloff, pilot, inversion, div; - dev_dbg(&priv->i2c->dev, "%s: delivery_system=%d modulation=%d " \ - "frequency=%d symbol_rate=%d inversion=%d pilot=%d " \ - "rolloff=%d\n", __func__, c->delivery_system, c->modulation, - c->frequency, c->symbol_rate, c->inversion, c->pilot, - c->rolloff); + dev_dbg(&priv->i2c->dev, + "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n", + __func__, c->delivery_system, c->modulation, + c->frequency, c->symbol_rate, c->inversion, c->pilot, + c->rolloff); priv->delivery_system = SYS_UNDEFINED; @@ -952,10 +953,8 @@ static int tda10071_init(struct dvb_frontend *fe) /* request the firmware, this will block and timeout */ ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent); if (ret) { - dev_err(&priv->i2c->dev, "%s: did not find the " \ - "firmware file. (%s) Please see " \ - "linux/Documentation/dvb/ for more " \ - "details on firmware-problems. (%d)\n", + dev_err(&priv->i2c->dev, + "%s: did not find the firmware file. (%s) Please see linux/Documentation/dvb/ for more details on firmware-problems. (%d)\n", KBUILD_MODNAME, fw_file, ret); goto error; } @@ -985,11 +984,12 @@ static int tda10071_init(struct dvb_frontend *fe) if (ret) goto error_release_firmware; - dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state, " \ - "will try to load a firmware\n", KBUILD_MODNAME, - tda10071_ops.info.name); - dev_info(&priv->i2c->dev, "%s: downloading firmware from " \ - "file '%s'\n", KBUILD_MODNAME, fw_file); + dev_info(&priv->i2c->dev, + "%s: found a '%s' in cold state, will try to load a firmware\n", + KBUILD_MODNAME, tda10071_ops.info.name); + dev_info(&priv->i2c->dev, + "%s: downloading firmware from file '%s'\n", + KBUILD_MODNAME, fw_file); /* do not download last byte */ fw_size = fw->size - 1; @@ -1003,11 +1003,10 @@ static int tda10071_init(struct dvb_frontend *fe) ret = tda10071_wr_regs(priv, 0xfa, (u8 *) &fw->data[fw_size - remaining], len); if (ret) { - dev_err(&priv->i2c->dev, "%s: firmware " \ - "download failed=%d\n", + dev_err(&priv->i2c->dev, + "%s: firmware download failed=%d\n", KBUILD_MODNAME, ret); - if (ret) - goto error_release_firmware; + goto error_release_firmware; } } release_firmware(fw); @@ -1069,12 +1068,17 @@ static int tda10071_init(struct dvb_frontend *fe) if (ret) goto error; + if (priv->cfg.tuner_i2c_addr) + tmp = priv->cfg.tuner_i2c_addr; + else + tmp = 0x14; + cmd.args[0] = CMD_TUNER_INIT; cmd.args[1] = 0x00; cmd.args[2] = 0x00; cmd.args[3] = 0x00; cmd.args[4] = 0x00; - cmd.args[5] = (priv->cfg.tuner_i2c_addr) ? priv->cfg.tuner_i2c_addr : 0x14; + cmd.args[5] = tmp; cmd.args[6] = 0x00; cmd.args[7] = 0x03; cmd.args[8] = 0x02; @@ -1214,14 +1218,14 @@ struct dvb_frontend *tda10071_attach(const struct tda10071_config *config, /* make sure demod i2c address is specified */ if (!config->demod_i2c_addr) { - dev_dbg(&i2c->dev, "%s: invalid demod i2c address!\n", __func__); + dev_dbg(&i2c->dev, "%s: invalid demod i2c address\n", __func__); ret = -EINVAL; goto error; } /* make sure tuner i2c address is specified */ if (!config->tuner_i2c_addr) { - dev_dbg(&i2c->dev, "%s: invalid tuner i2c address!\n", __func__); + dev_dbg(&i2c->dev, "%s: invalid tuner i2c address\n", __func__); ret = -EINVAL; goto error; } diff --git a/drivers/media/dvb-frontends/tda10071.h b/drivers/media/dvb-frontends/tda10071.h index f9542f6..331b5a8 100644 --- a/drivers/media/dvb-frontends/tda10071.h +++ b/drivers/media/dvb-frontends/tda10071.h @@ -79,7 +79,7 @@ extern struct dvb_frontend *tda10071_attach( static inline struct dvb_frontend *tda10071_attach( const struct tda10071_config *config, struct i2c_adapter *i2c) { - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + dev_warn(&i2c->dev, "%s: driver disabled by Kconfig\n", __func__); return NULL; } #endif diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 4aa9c53..c930be3 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -196,7 +196,7 @@ config VIDEO_ADV7183 config VIDEO_ADV7604 tristate "Analog Devices ADV7604 decoder" - depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API + depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API && MEDIA_CONTROLLER ---help--- Support for the Analog Devices ADV7604 video decoder. @@ -208,7 +208,7 @@ config VIDEO_ADV7604 config VIDEO_ADV7842 tristate "Analog Devices ADV7842 decoder" - depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API + depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API && MEDIA_CONTROLLER ---help--- Support for the Analog Devices ADV7842 video decoder. @@ -431,7 +431,7 @@ config VIDEO_ADV7393 config VIDEO_ADV7511 tristate "Analog Devices ADV7511 encoder" - depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API + depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API && MEDIA_CONTROLLER ---help--- Support for the Analog Devices ADV7511 video encoder. @@ -629,6 +629,15 @@ config VIDEO_LM3560 This is a driver for the lm3560 dual flash controllers. It controls flash, torch LEDs. +config VIDEO_LM3646 + tristate "LM3646 dual flash driver support" + depends on I2C && VIDEO_V4L2 && MEDIA_CONTROLLER + depends on MEDIA_CAMERA_SUPPORT + select REGMAP_I2C + ---help--- + This is a driver for the lm3646 dual flash controllers. It controls + flash, torch LEDs. + comment "Video improvement chips" config VIDEO_UPD64031A @@ -659,6 +668,7 @@ comment "Audio/Video compression chips" config VIDEO_SAA6752HS tristate "Philips SAA6752HS MPEG-2 Audio/Video Encoder" depends on VIDEO_V4L2 && I2C + select CRC32 ---help--- Support for the Philips SAA6752HS MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer. diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index 48888ae..01b6bfc 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -72,6 +72,7 @@ obj-$(CONFIG_VIDEO_S5C73M3) += s5c73m3/ obj-$(CONFIG_VIDEO_ADP1653) += adp1653.o obj-$(CONFIG_VIDEO_AS3645A) += as3645a.o obj-$(CONFIG_VIDEO_LM3560) += lm3560.o +obj-$(CONFIG_VIDEO_LM3646) += lm3646.o obj-$(CONFIG_VIDEO_SMIAPP_PLL) += smiapp-pll.o obj-$(CONFIG_VIDEO_AK881X) += ak881x.o obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o diff --git a/drivers/media/i2c/ad9389b.c b/drivers/media/i2c/ad9389b.c index 83225d6..1b7ecfd 100644 --- a/drivers/media/i2c/ad9389b.c +++ b/drivers/media/i2c/ad9389b.c @@ -573,7 +573,7 @@ static const struct v4l2_subdev_core_ops ad9389b_core_ops = { /* ------------------------------ PAD OPS ------------------------------ */ -static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) +static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) { struct ad9389b_state *state = get_ad9389b_state(sd); diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c index d7d99f1..5e638b1 100644 --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c @@ -123,11 +123,11 @@ struct adv7180_state { struct v4l2_ctrl_handler ctrl_hdl; struct v4l2_subdev sd; - struct work_struct work; struct mutex mutex; /* mutual excl. when accessing chip */ int irq; v4l2_std_id curr_norm; bool autodetect; + bool powered; u8 input; }; #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \ @@ -312,6 +312,37 @@ out: return ret; } +static int adv7180_set_power(struct adv7180_state *state, + struct i2c_client *client, bool on) +{ + u8 val; + + if (on) + val = ADV7180_PWR_MAN_ON; + else + val = ADV7180_PWR_MAN_OFF; + + return i2c_smbus_write_byte_data(client, ADV7180_PWR_MAN_REG, val); +} + +static int adv7180_s_power(struct v4l2_subdev *sd, int on) +{ + struct adv7180_state *state = to_state(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + ret = mutex_lock_interruptible(&state->mutex); + if (ret) + return ret; + + ret = adv7180_set_power(state, client, on); + if (ret == 0) + state->powered = on; + + mutex_unlock(&state->mutex); + return ret; +} + static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl) { struct v4l2_subdev *sd = to_adv7180_sd(ctrl); @@ -442,6 +473,7 @@ static const struct v4l2_subdev_video_ops adv7180_video_ops = { static const struct v4l2_subdev_core_ops adv7180_core_ops = { .s_std = adv7180_s_std, + .s_power = adv7180_s_power, }; static const struct v4l2_subdev_ops adv7180_ops = { @@ -449,10 +481,9 @@ static const struct v4l2_subdev_ops adv7180_ops = { .video = &adv7180_video_ops, }; -static void adv7180_work(struct work_struct *work) +static irqreturn_t adv7180_irq(int irq, void *devid) { - struct adv7180_state *state = container_of(work, struct adv7180_state, - work); + struct adv7180_state *state = devid; struct i2c_client *client = v4l2_get_subdevdata(&state->sd); u8 isr3; @@ -468,17 +499,6 @@ static void adv7180_work(struct work_struct *work) __adv7180_status(client, NULL, &state->curr_norm); mutex_unlock(&state->mutex); - enable_irq(state->irq); -} - -static irqreturn_t adv7180_irq(int irq, void *devid) -{ - struct adv7180_state *state = devid; - - schedule_work(&state->work); - - disable_irq_nosync(state->irq); - return IRQ_HANDLED; } @@ -533,48 +553,52 @@ static int init_device(struct i2c_client *client, struct adv7180_state *state) /* register for interrupts */ if (state->irq > 0) { - ret = request_irq(state->irq, adv7180_irq, 0, KBUILD_MODNAME, - state); + ret = request_threaded_irq(state->irq, NULL, adv7180_irq, + IRQF_ONESHOT, KBUILD_MODNAME, state); if (ret) return ret; ret = i2c_smbus_write_byte_data(client, ADV7180_ADI_CTRL_REG, ADV7180_ADI_CTRL_IRQ_SPACE); if (ret < 0) - return ret; + goto err; /* config the Interrupt pin to be active low */ ret = i2c_smbus_write_byte_data(client, ADV7180_ICONF1_ADI, ADV7180_ICONF1_ACTIVE_LOW | ADV7180_ICONF1_PSYNC_ONLY); if (ret < 0) - return ret; + goto err; ret = i2c_smbus_write_byte_data(client, ADV7180_IMR1_ADI, 0); if (ret < 0) - return ret; + goto err; ret = i2c_smbus_write_byte_data(client, ADV7180_IMR2_ADI, 0); if (ret < 0) - return ret; + goto err; /* enable AD change interrupts interrupts */ ret = i2c_smbus_write_byte_data(client, ADV7180_IMR3_ADI, ADV7180_IRQ3_AD_CHANGE); if (ret < 0) - return ret; + goto err; ret = i2c_smbus_write_byte_data(client, ADV7180_IMR4_ADI, 0); if (ret < 0) - return ret; + goto err; ret = i2c_smbus_write_byte_data(client, ADV7180_ADI_CTRL_REG, 0); if (ret < 0) - return ret; + goto err; } return 0; + +err: + free_irq(state->irq, state); + return ret; } static int adv7180_probe(struct i2c_client *client, @@ -598,9 +622,9 @@ static int adv7180_probe(struct i2c_client *client, } state->irq = client->irq; - INIT_WORK(&state->work, adv7180_work); mutex_init(&state->mutex); state->autodetect = true; + state->powered = true; state->input = 0; sd = &state->sd; v4l2_i2c_subdev_init(sd, client, &adv7180_ops); @@ -611,15 +635,21 @@ static int adv7180_probe(struct i2c_client *client, ret = init_device(client, state); if (ret) goto err_free_ctrl; + + ret = v4l2_async_register_subdev(sd); + if (ret) + goto err_free_irq; + return 0; +err_free_irq: + if (state->irq > 0) + free_irq(client->irq, state); err_free_ctrl: adv7180_exit_controls(state); err_unreg_subdev: mutex_destroy(&state->mutex); - v4l2_device_unregister_subdev(sd); err: - printk(KERN_ERR KBUILD_MODNAME ": Failed to probe: %d\n", ret); return ret; } @@ -628,20 +658,14 @@ static int adv7180_remove(struct i2c_client *client) struct v4l2_subdev *sd = i2c_get_clientdata(client); struct adv7180_state *state = to_state(sd); - if (state->irq > 0) { + v4l2_async_unregister_subdev(sd); + + if (state->irq > 0) free_irq(client->irq, state); - if (cancel_work_sync(&state->work)) { - /* - * Work was pending, therefore we need to enable - * IRQ here to balance the disable_irq() done in the - * interrupt handler. - */ - enable_irq(state->irq); - } - } - mutex_destroy(&state->mutex); v4l2_device_unregister_subdev(sd); + adv7180_exit_controls(state); + mutex_destroy(&state->mutex); return 0; } @@ -654,13 +678,10 @@ static const struct i2c_device_id adv7180_id[] = { static int adv7180_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); - int ret; + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct adv7180_state *state = to_state(sd); - ret = i2c_smbus_write_byte_data(client, ADV7180_PWR_MAN_REG, - ADV7180_PWR_MAN_OFF); - if (ret < 0) - return ret; - return 0; + return adv7180_set_power(state, client, false); } static int adv7180_resume(struct device *dev) @@ -670,10 +691,11 @@ static int adv7180_resume(struct device *dev) struct adv7180_state *state = to_state(sd); int ret; - ret = i2c_smbus_write_byte_data(client, ADV7180_PWR_MAN_REG, - ADV7180_PWR_MAN_ON); - if (ret < 0) - return ret; + if (state->powered) { + ret = adv7180_set_power(state, client, true); + if (ret) + return ret; + } ret = init_device(client, state); if (ret < 0) return ret; diff --git a/drivers/media/i2c/adv7511.c b/drivers/media/i2c/adv7511.c index ee61894..942ca4b 100644 --- a/drivers/media/i2c/adv7511.c +++ b/drivers/media/i2c/adv7511.c @@ -597,7 +597,7 @@ static int adv7511_isr(struct v4l2_subdev *sd, u32 status, bool *handled) return 0; } -static int adv7511_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) +static int adv7511_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) { struct adv7511_state *state = get_adv7511_state(sd); diff --git a/drivers/media/i2c/adv7604.c b/drivers/media/i2c/adv7604.c index 71c8570..98cc540 100644 --- a/drivers/media/i2c/adv7604.c +++ b/drivers/media/i2c/adv7604.c @@ -1658,7 +1658,7 @@ static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled) return 0; } -static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) +static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) { struct adv7604_state *state = to_state(sd); u8 *data = NULL; @@ -1728,7 +1728,7 @@ static int get_edid_spa_location(const u8 *edid) return -1; } -static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) +static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) { struct adv7604_state *state = to_state(sd); int spa_loc; diff --git a/drivers/media/i2c/adv7842.c b/drivers/media/i2c/adv7842.c index 9bbd665..636ac08 100644 --- a/drivers/media/i2c/adv7842.c +++ b/drivers/media/i2c/adv7842.c @@ -546,6 +546,14 @@ static void main_reset(struct v4l2_subdev *sd) /* ----------------------------------------------------------------------- */ +static inline bool is_analog_input(struct v4l2_subdev *sd) +{ + struct adv7842_state *state = to_state(sd); + + return ((state->mode == ADV7842_MODE_RGB) || + (state->mode == ADV7842_MODE_COMP)); +} + static inline bool is_digital_input(struct v4l2_subdev *sd) { struct adv7842_state *state = to_state(sd); @@ -1027,12 +1035,72 @@ static void configure_custom_video_timings(struct v4l2_subdev *sd, cp_write(sd, 0xac, (height & 0x0f) << 4); } +static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) +{ + struct adv7842_state *state = to_state(sd); + u8 offset_buf[4]; + + if (auto_offset) { + offset_a = 0x3ff; + offset_b = 0x3ff; + offset_c = 0x3ff; + } + + v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", + __func__, auto_offset ? "Auto" : "Manual", + offset_a, offset_b, offset_c); + + offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); + offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); + offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); + offset_buf[3] = offset_c & 0x0ff; + + /* Registers must be written in this order with no i2c access in between */ + if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf)) + v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); +} + +static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) +{ + struct adv7842_state *state = to_state(sd); + u8 gain_buf[4]; + u8 gain_man = 1; + u8 agc_mode_man = 1; + + if (auto_gain) { + gain_man = 0; + agc_mode_man = 0; + gain_a = 0x100; + gain_b = 0x100; + gain_c = 0x100; + } + + v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", + __func__, auto_gain ? "Auto" : "Manual", + gain_a, gain_b, gain_c); + + gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); + gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); + gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); + gain_buf[3] = ((gain_c & 0x0ff)); + + /* Registers must be written in this order with no i2c access in between */ + if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf)) + v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); +} + static void set_rgb_quantization_range(struct v4l2_subdev *sd) { struct adv7842_state *state = to_state(sd); + bool rgb_output = io_read(sd, 0x02) & 0x02; + bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; + + v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", + __func__, state->rgb_quantization_range, + rgb_output, hdmi_signal); - v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n", - __func__, state->rgb_quantization_range); + adv7842_set_gain(sd, true, 0x0, 0x0, 0x0); + adv7842_set_offset(sd, true, 0x0, 0x0, 0x0); switch (state->rgb_quantization_range) { case V4L2_DV_RGB_RANGE_AUTO: @@ -1050,7 +1118,7 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd) break; } - if (hdmi_read(sd, 0x05) & 0x80) { + if (hdmi_signal) { /* Receiving HDMI signal * Set automode */ io_write_and_or(sd, 0x02, 0x0f, 0xf0); @@ -1066,24 +1134,45 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd) } else { /* RGB full range (0-255) */ io_write_and_or(sd, 0x02, 0x0f, 0x10); + + if (is_digital_input(sd) && rgb_output) { + adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); + } else { + adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); + adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); + } } break; case V4L2_DV_RGB_RANGE_LIMITED: if (state->mode == ADV7842_MODE_COMP) { /* YCrCb limited range (16-235) */ io_write_and_or(sd, 0x02, 0x0f, 0x20); - } else { - /* RGB limited range (16-235) */ - io_write_and_or(sd, 0x02, 0x0f, 0x00); + break; } + + /* RGB limited range (16-235) */ + io_write_and_or(sd, 0x02, 0x0f, 0x00); + break; case V4L2_DV_RGB_RANGE_FULL: if (state->mode == ADV7842_MODE_COMP) { /* YCrCb full range (0-255) */ io_write_and_or(sd, 0x02, 0x0f, 0x60); + break; + } + + /* RGB full range (0-255) */ + io_write_and_or(sd, 0x02, 0x0f, 0x10); + + if (is_analog_input(sd) || hdmi_signal) + break; + + /* Adjust gain/offset for DVI-D signals only */ + if (rgb_output) { + adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); } else { - /* RGB full range (0-255) */ - io_write_and_or(sd, 0x02, 0x0f, 0x10); + adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); + adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); } break; } @@ -1360,12 +1449,11 @@ static int adv7842_query_dv_timings(struct v4l2_subdev *sd, bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); - freq = (hdmi_read(sd, 0x06) * 1000000) + - ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000; - + freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000; + freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813); if (is_hdmi(sd)) { /* adjust for deep color mode */ - freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 5) + 8); + freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8); } bt->pixelclock = freq; bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + @@ -1717,8 +1805,8 @@ static void select_input(struct v4l2_subdev *sd, * (rev. 2.5, June 2010)" p. 17. */ afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ - cp_write(sd, 0x3e, 0x80); /* CP core pre-gain control, - enable color control */ + cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ + /* CP coast control */ cp_write(sd, 0xc3, 0x33); /* Component mode */ @@ -1926,7 +2014,7 @@ static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) return 0; } -static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) +static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) { struct adv7842_state *state = to_state(sd); u8 *data = NULL; @@ -1966,7 +2054,7 @@ static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edi return 0; } -static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e) +static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e) { struct adv7842_state *state = to_state(sd); int err = 0; @@ -2103,7 +2191,8 @@ static void print_avi_infoframe(struct v4l2_subdev *sd) { int i; uint8_t buf[14]; - uint8_t avi_inf_len; + u8 avi_len; + u8 avi_ver; struct avi_info_frame avi; if (!(hdmi_read(sd, 0x05) & 0x80)) { @@ -2116,18 +2205,20 @@ static void print_avi_infoframe(struct v4l2_subdev *sd) } if (io_read(sd, 0x88) & 0x10) { - /* Note: the ADV7842 calculated incorrect checksums for InfoFrames - with a length of 14 or 15. See the ADV7842 Register Settings - Recommendations document for more details. */ - v4l2_info(sd, "AVI infoframe checksum error\n"); - return; + v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n"); + io_write(sd, 0x8a, 0x10); /* clear AVI_INF_CKS_ERR_RAW */ + if (io_read(sd, 0x88) & 0x10) { + v4l2_info(sd, "AVI infoframe checksum error still present\n"); + io_write(sd, 0x8a, 0x10); /* clear AVI_INF_CKS_ERR_RAW */ + } } - avi_inf_len = infoframe_read(sd, 0xe2); + avi_len = infoframe_read(sd, 0xe2); + avi_ver = infoframe_read(sd, 0xe1); v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", - infoframe_read(sd, 0xe1), avi_inf_len); + avi_ver, avi_len); - if (infoframe_read(sd, 0xe1) != 0x02) + if (avi_ver != 0x02) return; for (i = 0; i < 14; i++) @@ -2602,9 +2693,15 @@ static int adv7842_core_init(struct v4l2_subdev *sd) /* disable I2C access to internal EDID ram from HDMI DDC ports */ rep_write_and_or(sd, 0x77, 0xf3, 0x00); - hdmi_write(sd, 0x69, 0xa3); /* HPA manual */ - /* HPA disable on port A and B */ - io_write_and_or(sd, 0x20, 0xcf, 0x00); + if (pdata->hpa_auto) { + /* HPA auto, HPA 0.5s after Edid set and Cable detect */ + hdmi_write(sd, 0x69, 0x5c); + } else { + /* HPA manual */ + hdmi_write(sd, 0x69, 0xa3); + /* HPA disable on port A and B */ + io_write_and_or(sd, 0x20, 0xcf, 0x00); + } /* LLC */ io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase); diff --git a/drivers/media/i2c/ir-kbd-i2c.c b/drivers/media/i2c/ir-kbd-i2c.c index 99ee456..c8fe135 100644 --- a/drivers/media/i2c/ir-kbd-i2c.c +++ b/drivers/media/i2c/ir-kbd-i2c.c @@ -431,8 +431,8 @@ static int ir_probe(struct i2c_client *client, const struct i2c_device_id *id) * Initialize the other fields of rc_dev */ rc->map_name = ir->ir_codes; - rc->allowed_protos = rc_type; - rc->enabled_protocols = rc_type; + rc_set_allowed_protocols(rc, rc_type); + rc_set_enabled_protocols(rc, rc_type); if (!rc->driver_name) rc->driver_name = MODULE_NAME; diff --git a/drivers/media/i2c/lm3560.c b/drivers/media/i2c/lm3560.c index d98ca3a..c23de59 100644 --- a/drivers/media/i2c/lm3560.c +++ b/drivers/media/i2c/lm3560.c @@ -15,12 +15,6 @@ * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * */ #include <linux/delay.h> @@ -42,7 +36,7 @@ #define REG_FLAG 0xd0 #define REG_CONFIG1 0xe0 -/* Fault Mask */ +/* fault mask */ #define FAULT_TIMEOUT (1<<0) #define FAULT_OVERTEMP (1<<1) #define FAULT_SHORT_CIRCUIT (1<<2) @@ -53,7 +47,8 @@ enum led_enable { MODE_FLASH = 0x3, }; -/* struct lm3560_flash +/** + * struct lm3560_flash * * @pdata: platform data * @regmap: reg. map for i2c @@ -98,7 +93,7 @@ static int lm3560_mode_ctrl(struct lm3560_flash *flash) return rval; } -/* led1/2 enable/disable */ +/* led1/2 enable/disable */ static int lm3560_enable_ctrl(struct lm3560_flash *flash, enum lm3560_led_id led_no, bool on) { @@ -168,7 +163,7 @@ static int lm3560_flash_brt_ctrl(struct lm3560_flash *flash, return rval; } -/* V4L2 controls */ +/* v4l2 controls */ static int lm3560_get_ctrl(struct v4l2_ctrl *ctrl, enum lm3560_led_id led_no) { struct lm3560_flash *flash = to_lm3560_flash(ctrl, led_no); @@ -297,6 +292,7 @@ static int lm3560_init_controls(struct lm3560_flash *flash, const struct v4l2_ctrl_ops *ops = &lm3560_led_ctrl_ops[led_no]; v4l2_ctrl_handler_init(hdl, 8); + /* flash mode */ v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_FLASH_LED_MODE, V4L2_FLASH_LED_MODE_TORCH, ~0x7, @@ -309,6 +305,7 @@ static int lm3560_init_controls(struct lm3560_flash *flash, /* flash strobe */ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_STROBE, 0, 0, 0, 0); + /* flash strobe stop */ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_STROBE_STOP, 0, 0, 0, 0); @@ -395,7 +392,7 @@ static int lm3560_init_device(struct lm3560_flash *flash) rval = lm3560_mode_ctrl(flash); if (rval < 0) return rval; - /* Reset faults */ + /* reset faults */ rval = regmap_read(flash->regmap, REG_FLAG, ®_val); return rval; } @@ -419,8 +416,7 @@ static int lm3560_probe(struct i2c_client *client, /* if there is no platform data, use chip default value */ if (pdata == NULL) { - pdata = - kzalloc(sizeof(struct lm3560_platform_data), GFP_KERNEL); + pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); if (pdata == NULL) return -ENODEV; pdata->peak = LM3560_PEAK_3600mA; diff --git a/drivers/media/i2c/lm3646.c b/drivers/media/i2c/lm3646.c new file mode 100644 index 0000000..626fb46 --- /dev/null +++ b/drivers/media/i2c/lm3646.c @@ -0,0 +1,414 @@ +/* + * drivers/media/i2c/lm3646.c + * General device driver for TI lm3646, Dual FLASH LED Driver + * + * Copyright (C) 2014 Texas Instruments + * + * Contact: Daniel Jeong <gshark.jeong@gmail.com> + * Ldd-Mlp <ldd-mlp@list.ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + */ + +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/regmap.h> +#include <linux/videodev2.h> +#include <media/lm3646.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> + +/* registers definitions */ +#define REG_ENABLE 0x01 +#define REG_TORCH_BR 0x05 +#define REG_FLASH_BR 0x05 +#define REG_FLASH_TOUT 0x04 +#define REG_FLAG 0x08 +#define REG_STROBE_SRC 0x06 +#define REG_LED1_FLASH_BR 0x06 +#define REG_LED1_TORCH_BR 0x07 + +#define MASK_ENABLE 0x03 +#define MASK_TORCH_BR 0x70 +#define MASK_FLASH_BR 0x0F +#define MASK_FLASH_TOUT 0x07 +#define MASK_FLAG 0xFF +#define MASK_STROBE_SRC 0x80 + +/* Fault Mask */ +#define FAULT_TIMEOUT (1<<0) +#define FAULT_SHORT_CIRCUIT (1<<1) +#define FAULT_UVLO (1<<2) +#define FAULT_IVFM (1<<3) +#define FAULT_OCP (1<<4) +#define FAULT_OVERTEMP (1<<5) +#define FAULT_NTC_TRIP (1<<6) +#define FAULT_OVP (1<<7) + +enum led_mode { + MODE_SHDN = 0x0, + MODE_TORCH = 0x2, + MODE_FLASH = 0x3, +}; + +/* + * struct lm3646_flash + * + * @pdata: platform data + * @regmap: reg. map for i2c + * @lock: muxtex for serial access. + * @led_mode: V4L2 LED mode + * @ctrls_led: V4L2 contols + * @subdev_led: V4L2 subdev + * @mode_reg : mode register value + */ +struct lm3646_flash { + struct device *dev; + struct lm3646_platform_data *pdata; + struct regmap *regmap; + + struct v4l2_ctrl_handler ctrls_led; + struct v4l2_subdev subdev_led; + + u8 mode_reg; +}; + +#define to_lm3646_flash(_ctrl) \ + container_of(_ctrl->handler, struct lm3646_flash, ctrls_led) + +/* enable mode control */ +static int lm3646_mode_ctrl(struct lm3646_flash *flash, + enum v4l2_flash_led_mode led_mode) +{ + switch (led_mode) { + case V4L2_FLASH_LED_MODE_NONE: + return regmap_write(flash->regmap, + REG_ENABLE, flash->mode_reg | MODE_SHDN); + case V4L2_FLASH_LED_MODE_TORCH: + return regmap_write(flash->regmap, + REG_ENABLE, flash->mode_reg | MODE_TORCH); + case V4L2_FLASH_LED_MODE_FLASH: + return regmap_write(flash->regmap, + REG_ENABLE, flash->mode_reg | MODE_FLASH); + } + return -EINVAL; +} + +/* V4L2 controls */ +static int lm3646_get_ctrl(struct v4l2_ctrl *ctrl) +{ + struct lm3646_flash *flash = to_lm3646_flash(ctrl); + unsigned int reg_val; + int rval; + + if (ctrl->id != V4L2_CID_FLASH_FAULT) + return -EINVAL; + + rval = regmap_read(flash->regmap, REG_FLAG, ®_val); + if (rval < 0) + return rval; + + ctrl->val = 0; + if (reg_val & FAULT_TIMEOUT) + ctrl->val |= V4L2_FLASH_FAULT_TIMEOUT; + if (reg_val & FAULT_SHORT_CIRCUIT) + ctrl->val |= V4L2_FLASH_FAULT_SHORT_CIRCUIT; + if (reg_val & FAULT_UVLO) + ctrl->val |= V4L2_FLASH_FAULT_UNDER_VOLTAGE; + if (reg_val & FAULT_IVFM) + ctrl->val |= V4L2_FLASH_FAULT_INPUT_VOLTAGE; + if (reg_val & FAULT_OCP) + ctrl->val |= V4L2_FLASH_FAULT_OVER_CURRENT; + if (reg_val & FAULT_OVERTEMP) + ctrl->val |= V4L2_FLASH_FAULT_OVER_TEMPERATURE; + if (reg_val & FAULT_NTC_TRIP) + ctrl->val |= V4L2_FLASH_FAULT_LED_OVER_TEMPERATURE; + if (reg_val & FAULT_OVP) + ctrl->val |= V4L2_FLASH_FAULT_OVER_VOLTAGE; + + return 0; +} + +static int lm3646_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct lm3646_flash *flash = to_lm3646_flash(ctrl); + unsigned int reg_val; + int rval = -EINVAL; + + switch (ctrl->id) { + case V4L2_CID_FLASH_LED_MODE: + + if (ctrl->val != V4L2_FLASH_LED_MODE_FLASH) + return lm3646_mode_ctrl(flash, ctrl->val); + /* switch to SHDN mode before flash strobe on */ + return lm3646_mode_ctrl(flash, V4L2_FLASH_LED_MODE_NONE); + + case V4L2_CID_FLASH_STROBE_SOURCE: + return regmap_update_bits(flash->regmap, + REG_STROBE_SRC, MASK_STROBE_SRC, + (ctrl->val) << 7); + + case V4L2_CID_FLASH_STROBE: + + /* read and check current mode of chip to start flash */ + rval = regmap_read(flash->regmap, REG_ENABLE, ®_val); + if (rval < 0 || ((reg_val & MASK_ENABLE) != MODE_SHDN)) + return rval; + /* flash on */ + return lm3646_mode_ctrl(flash, V4L2_FLASH_LED_MODE_FLASH); + + case V4L2_CID_FLASH_STROBE_STOP: + + /* + * flash mode will be turned automatically + * from FLASH mode to SHDN mode after flash duration timeout + * read and check current mode of chip to stop flash + */ + rval = regmap_read(flash->regmap, REG_ENABLE, ®_val); + if (rval < 0) + return rval; + if ((reg_val & MASK_ENABLE) == MODE_FLASH) + return lm3646_mode_ctrl(flash, + V4L2_FLASH_LED_MODE_NONE); + return rval; + + case V4L2_CID_FLASH_TIMEOUT: + return regmap_update_bits(flash->regmap, + REG_FLASH_TOUT, MASK_FLASH_TOUT, + LM3646_FLASH_TOUT_ms_TO_REG + (ctrl->val)); + + case V4L2_CID_FLASH_INTENSITY: + return regmap_update_bits(flash->regmap, + REG_FLASH_BR, MASK_FLASH_BR, + LM3646_TOTAL_FLASH_BRT_uA_TO_REG + (ctrl->val)); + + case V4L2_CID_FLASH_TORCH_INTENSITY: + return regmap_update_bits(flash->regmap, + REG_TORCH_BR, MASK_TORCH_BR, + LM3646_TOTAL_TORCH_BRT_uA_TO_REG + (ctrl->val) << 4); + } + + return -EINVAL; +} + +static const struct v4l2_ctrl_ops lm3646_led_ctrl_ops = { + .g_volatile_ctrl = lm3646_get_ctrl, + .s_ctrl = lm3646_set_ctrl, +}; + +static int lm3646_init_controls(struct lm3646_flash *flash) +{ + struct v4l2_ctrl *fault; + struct v4l2_ctrl_handler *hdl = &flash->ctrls_led; + const struct v4l2_ctrl_ops *ops = &lm3646_led_ctrl_ops; + + v4l2_ctrl_handler_init(hdl, 8); + /* flash mode */ + v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_FLASH_LED_MODE, + V4L2_FLASH_LED_MODE_TORCH, ~0x7, + V4L2_FLASH_LED_MODE_NONE); + + /* flash source */ + v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_FLASH_STROBE_SOURCE, + 0x1, ~0x3, V4L2_FLASH_STROBE_SOURCE_SOFTWARE); + + /* flash strobe */ + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_STROBE, 0, 0, 0, 0); + /* flash strobe stop */ + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_STROBE_STOP, 0, 0, 0, 0); + + /* flash strobe timeout */ + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_TIMEOUT, + LM3646_FLASH_TOUT_MIN, + LM3646_FLASH_TOUT_MAX, + LM3646_FLASH_TOUT_STEP, flash->pdata->flash_timeout); + + /* max flash current */ + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_INTENSITY, + LM3646_TOTAL_FLASH_BRT_MIN, + LM3646_TOTAL_FLASH_BRT_MAX, + LM3646_TOTAL_FLASH_BRT_STEP, + LM3646_TOTAL_FLASH_BRT_MAX); + + /* max torch current */ + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_TORCH_INTENSITY, + LM3646_TOTAL_TORCH_BRT_MIN, + LM3646_TOTAL_TORCH_BRT_MAX, + LM3646_TOTAL_TORCH_BRT_STEP, + LM3646_TOTAL_TORCH_BRT_MAX); + + /* fault */ + fault = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FLASH_FAULT, 0, + V4L2_FLASH_FAULT_OVER_VOLTAGE + | V4L2_FLASH_FAULT_OVER_TEMPERATURE + | V4L2_FLASH_FAULT_SHORT_CIRCUIT + | V4L2_FLASH_FAULT_TIMEOUT, 0, 0); + if (fault != NULL) + fault->flags |= V4L2_CTRL_FLAG_VOLATILE; + + if (hdl->error) + return hdl->error; + + flash->subdev_led.ctrl_handler = hdl; + return 0; +} + +/* initialize device */ +static const struct v4l2_subdev_ops lm3646_ops = { + .core = NULL, +}; + +static const struct regmap_config lm3646_regmap = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xFF, +}; + +static int lm3646_subdev_init(struct lm3646_flash *flash) +{ + struct i2c_client *client = to_i2c_client(flash->dev); + int rval; + + v4l2_i2c_subdev_init(&flash->subdev_led, client, &lm3646_ops); + flash->subdev_led.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + strcpy(flash->subdev_led.name, LM3646_NAME); + rval = lm3646_init_controls(flash); + if (rval) + goto err_out; + rval = media_entity_init(&flash->subdev_led.entity, 0, NULL, 0); + if (rval < 0) + goto err_out; + flash->subdev_led.entity.type = MEDIA_ENT_T_V4L2_SUBDEV_FLASH; + return rval; + +err_out: + v4l2_ctrl_handler_free(&flash->ctrls_led); + return rval; +} + +static int lm3646_init_device(struct lm3646_flash *flash) +{ + unsigned int reg_val; + int rval; + + /* read the value of mode register to reduce redundant i2c accesses */ + rval = regmap_read(flash->regmap, REG_ENABLE, ®_val); + if (rval < 0) + return rval; + flash->mode_reg = reg_val & 0xfc; + + /* output disable */ + rval = lm3646_mode_ctrl(flash, V4L2_FLASH_LED_MODE_NONE); + if (rval < 0) + return rval; + + /* + * LED1 flash current setting + * LED2 flash current = Total(Max) flash current - LED1 flash current + */ + rval = regmap_update_bits(flash->regmap, + REG_LED1_FLASH_BR, 0x7F, + LM3646_LED1_FLASH_BRT_uA_TO_REG + (flash->pdata->led1_flash_brt)); + + if (rval < 0) + return rval; + + /* + * LED1 torch current setting + * LED2 torch current = Total(Max) torch current - LED1 torch current + */ + rval = regmap_update_bits(flash->regmap, + REG_LED1_TORCH_BR, 0x7F, + LM3646_LED1_TORCH_BRT_uA_TO_REG + (flash->pdata->led1_torch_brt)); + if (rval < 0) + return rval; + + /* Reset flag register */ + return regmap_read(flash->regmap, REG_FLAG, ®_val); +} + +static int lm3646_probe(struct i2c_client *client, + const struct i2c_device_id *devid) +{ + struct lm3646_flash *flash; + struct lm3646_platform_data *pdata = dev_get_platdata(&client->dev); + int rval; + + flash = devm_kzalloc(&client->dev, sizeof(*flash), GFP_KERNEL); + if (flash == NULL) + return -ENOMEM; + + flash->regmap = devm_regmap_init_i2c(client, &lm3646_regmap); + if (IS_ERR(flash->regmap)) + return PTR_ERR(flash->regmap); + + /* check device tree if there is no platform data */ + if (pdata == NULL) { + pdata = devm_kzalloc(&client->dev, + sizeof(struct lm3646_platform_data), + GFP_KERNEL); + if (pdata == NULL) + return -ENOMEM; + /* use default data in case of no platform data */ + pdata->flash_timeout = LM3646_FLASH_TOUT_MAX; + pdata->led1_torch_brt = LM3646_LED1_TORCH_BRT_MAX; + pdata->led1_flash_brt = LM3646_LED1_FLASH_BRT_MAX; + } + flash->pdata = pdata; + flash->dev = &client->dev; + + rval = lm3646_subdev_init(flash); + if (rval < 0) + return rval; + + rval = lm3646_init_device(flash); + if (rval < 0) + return rval; + + i2c_set_clientdata(client, flash); + + return 0; +} + +static int lm3646_remove(struct i2c_client *client) +{ + struct lm3646_flash *flash = i2c_get_clientdata(client); + + v4l2_device_unregister_subdev(&flash->subdev_led); + v4l2_ctrl_handler_free(&flash->ctrls_led); + media_entity_cleanup(&flash->subdev_led.entity); + + return 0; +} + +static const struct i2c_device_id lm3646_id_table[] = { + {LM3646_NAME, 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, lm3646_id_table); + +static struct i2c_driver lm3646_i2c_driver = { + .driver = { + .name = LM3646_NAME, + }, + .probe = lm3646_probe, + .remove = lm3646_remove, + .id_table = lm3646_id_table, +}; + +module_i2c_driver(lm3646_i2c_driver); + +MODULE_AUTHOR("Daniel Jeong <gshark.jeong@gmail.com>"); +MODULE_AUTHOR("Ldd Mlp <ldd-mlp@list.ti.com>"); +MODULE_DESCRIPTION("Texas Instruments LM3646 Dual Flash LED driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index 192c4aa..33daace 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -78,6 +78,9 @@ #define MT9P031_PLL_CONFIG_1 0x11 #define MT9P031_PLL_CONFIG_2 0x12 #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a +#define MT9P031_PIXEL_CLOCK_INVERT (1 << 15) +#define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8) +#define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0) #define MT9P031_FRAME_RESTART 0x0b #define MT9P031_SHUTTER_DELAY 0x0c #define MT9P031_RST 0x0d @@ -130,6 +133,8 @@ struct mt9p031 { enum mt9p031_model model; struct aptina_pll pll; + unsigned int clk_div; + bool use_pll; int reset; struct v4l2_ctrl_handler ctrls; @@ -198,6 +203,11 @@ static int mt9p031_reset(struct mt9p031 *mt9p031) if (ret < 0) return ret; + ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL, + MT9P031_PIXEL_CLOCK_DIVIDE(mt9p031->clk_div)); + if (ret < 0) + return ret; + return mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN, 0); } @@ -222,15 +232,34 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); struct mt9p031_platform_data *pdata = mt9p031->pdata; + int ret; mt9p031->clk = devm_clk_get(&client->dev, NULL); if (IS_ERR(mt9p031->clk)) return PTR_ERR(mt9p031->clk); - clk_set_rate(mt9p031->clk, pdata->ext_freq); + ret = clk_set_rate(mt9p031->clk, pdata->ext_freq); + if (ret < 0) + return ret; + + /* If the external clock frequency is out of bounds for the PLL use the + * pixel clock divider only and disable the PLL. + */ + if (pdata->ext_freq > limits.ext_clock_max) { + unsigned int div; + + div = DIV_ROUND_UP(pdata->ext_freq, pdata->target_freq); + div = roundup_pow_of_two(div) / 2; + + mt9p031->clk_div = max_t(unsigned int, div, 64); + mt9p031->use_pll = false; + + return 0; + } mt9p031->pll.ext_clock = pdata->ext_freq; mt9p031->pll.pix_clock = pdata->target_freq; + mt9p031->use_pll = true; return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll); } @@ -240,6 +269,9 @@ static int mt9p031_pll_enable(struct mt9p031 *mt9p031) struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); int ret; + if (!mt9p031->use_pll) + return 0; + ret = mt9p031_write(client, MT9P031_PLL_CONTROL, MT9P031_PLL_CONTROL_PWRON); if (ret < 0) @@ -265,6 +297,9 @@ static inline int mt9p031_pll_disable(struct mt9p031 *mt9p031) { struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); + if (!mt9p031->use_pll) + return 0; + return mt9p031_write(client, MT9P031_PLL_CONTROL, MT9P031_PLL_CONTROL_PWROFF); } @@ -285,9 +320,15 @@ static int mt9p031_power_on(struct mt9p031 *mt9p031) if (ret < 0) return ret; - /* Emable clock */ - if (mt9p031->clk) - clk_prepare_enable(mt9p031->clk); + /* Enable clock */ + if (mt9p031->clk) { + ret = clk_prepare_enable(mt9p031->clk); + if (ret) { + regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators), + mt9p031->regulators); + return ret; + } + } /* Now RESET_BAR must be high */ if (gpio_is_valid(mt9p031->reset)) { diff --git a/drivers/media/i2c/mt9t001.c b/drivers/media/i2c/mt9t001.c index d41c70e..422e068 100644 --- a/drivers/media/i2c/mt9t001.c +++ b/drivers/media/i2c/mt9t001.c @@ -12,9 +12,11 @@ * published by the Free Software Foundation. */ +#include <linux/clk.h> #include <linux/i2c.h> -#include <linux/module.h> #include <linux/log2.h> +#include <linux/module.h> +#include <linux/regulator/consumer.h> #include <linux/slab.h> #include <linux/videodev2.h> #include <linux/v4l2-mediabus.h> @@ -55,6 +57,7 @@ #define MT9T001_OUTPUT_CONTROL_SYNC (1 << 0) #define MT9T001_OUTPUT_CONTROL_CHIP_ENABLE (1 << 1) #define MT9T001_OUTPUT_CONTROL_TEST_DATA (1 << 6) +#define MT9T001_OUTPUT_CONTROL_DEF 0x0002 #define MT9T001_SHUTTER_WIDTH_HIGH 0x08 #define MT9T001_SHUTTER_WIDTH_LOW 0x09 #define MT9T001_SHUTTER_WIDTH_MIN 1 @@ -116,6 +119,12 @@ struct mt9t001 { struct v4l2_subdev subdev; struct media_pad pad; + struct clk *clk; + struct regulator_bulk_data regulators[2]; + + struct mutex power_lock; /* lock to protect power_count */ + int power_count; + struct v4l2_mbus_framefmt format; struct v4l2_rect crop; @@ -159,6 +168,77 @@ static int mt9t001_set_output_control(struct mt9t001 *mt9t001, u16 clear, return 0; } +static int mt9t001_reset(struct mt9t001 *mt9t001) +{ + struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev); + int ret; + + /* Reset the chip and stop data read out */ + ret = mt9t001_write(client, MT9T001_RESET, 1); + if (ret < 0) + return ret; + + ret = mt9t001_write(client, MT9T001_RESET, 0); + if (ret < 0) + return ret; + + mt9t001->output_control = MT9T001_OUTPUT_CONTROL_DEF; + + return mt9t001_set_output_control(mt9t001, + MT9T001_OUTPUT_CONTROL_CHIP_ENABLE, + 0); +} + +static int mt9t001_power_on(struct mt9t001 *mt9t001) +{ + int ret; + + /* Bring up the supplies */ + ret = regulator_bulk_enable(ARRAY_SIZE(mt9t001->regulators), + mt9t001->regulators); + if (ret < 0) + return ret; + + /* Enable clock */ + ret = clk_prepare_enable(mt9t001->clk); + if (ret < 0) + regulator_bulk_disable(ARRAY_SIZE(mt9t001->regulators), + mt9t001->regulators); + + return ret; +} + +static void mt9t001_power_off(struct mt9t001 *mt9t001) +{ + regulator_bulk_disable(ARRAY_SIZE(mt9t001->regulators), + mt9t001->regulators); + + clk_disable_unprepare(mt9t001->clk); +} + +static int __mt9t001_set_power(struct mt9t001 *mt9t001, bool on) +{ + struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev); + int ret; + + if (!on) { + mt9t001_power_off(mt9t001); + return 0; + } + + ret = mt9t001_power_on(mt9t001); + if (ret < 0) + return ret; + + ret = mt9t001_reset(mt9t001); + if (ret < 0) { + dev_err(&client->dev, "Failed to reset the camera\n"); + return ret; + } + + return v4l2_ctrl_handler_setup(&mt9t001->ctrls); +} + /* ----------------------------------------------------------------------------- * V4L2 subdev video operations */ @@ -195,6 +275,7 @@ static int mt9t001_s_stream(struct v4l2_subdev *subdev, int enable) { const u16 mode = MT9T001_OUTPUT_CONTROL_CHIP_ENABLE; struct i2c_client *client = v4l2_get_subdevdata(subdev); + struct mt9t001_platform_data *pdata = client->dev.platform_data; struct mt9t001 *mt9t001 = to_mt9t001(subdev); struct v4l2_mbus_framefmt *format = &mt9t001->format; struct v4l2_rect *crop = &mt9t001->crop; @@ -205,6 +286,14 @@ static int mt9t001_s_stream(struct v4l2_subdev *subdev, int enable) if (!enable) return mt9t001_set_output_control(mt9t001, mode, 0); + /* Configure the pixel clock polarity */ + if (pdata->clk_pol) { + ret = mt9t001_write(client, MT9T001_PIXEL_CLOCK, + MT9T001_PIXEL_CLOCK_INVERT); + if (ret < 0) + return ret; + } + /* Configure the window size and row/column bin */ hratio = DIV_ROUND_CLOSEST(crop->width, format->width); vratio = DIV_ROUND_CLOSEST(crop->height, format->height); @@ -630,9 +719,67 @@ static const struct v4l2_ctrl_config mt9t001_gains[] = { }; /* ----------------------------------------------------------------------------- + * V4L2 subdev core operations + */ + +static int mt9t001_set_power(struct v4l2_subdev *subdev, int on) +{ + struct mt9t001 *mt9t001 = to_mt9t001(subdev); + int ret = 0; + + mutex_lock(&mt9t001->power_lock); + + /* If the power count is modified from 0 to != 0 or from != 0 to 0, + * update the power state. + */ + if (mt9t001->power_count == !on) { + ret = __mt9t001_set_power(mt9t001, !!on); + if (ret < 0) + goto out; + } + + /* Update the power count. */ + mt9t001->power_count += on ? 1 : -1; + WARN_ON(mt9t001->power_count < 0); + +out: + mutex_unlock(&mt9t001->power_lock); + return ret; +} + +/* ----------------------------------------------------------------------------- * V4L2 subdev internal operations */ +static int mt9t001_registered(struct v4l2_subdev *subdev) +{ + struct i2c_client *client = v4l2_get_subdevdata(subdev); + struct mt9t001 *mt9t001 = to_mt9t001(subdev); + s32 data; + int ret; + + ret = mt9t001_power_on(mt9t001); + if (ret < 0) { + dev_err(&client->dev, "MT9T001 power up failed\n"); + return ret; + } + + /* Read out the chip version register */ + data = mt9t001_read(client, MT9T001_CHIP_VERSION); + mt9t001_power_off(mt9t001); + + if (data != MT9T001_CHIP_ID) { + dev_err(&client->dev, + "MT9T001 not detected, wrong version 0x%04x\n", data); + return -ENODEV; + } + + dev_info(&client->dev, "MT9T001 detected at address 0x%02x\n", + client->addr); + + return 0; +} + static int mt9t001_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) { struct v4l2_mbus_framefmt *format; @@ -651,9 +798,18 @@ static int mt9t001_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) format->field = V4L2_FIELD_NONE; format->colorspace = V4L2_COLORSPACE_SRGB; - return 0; + return mt9t001_set_power(subdev, 1); +} + +static int mt9t001_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) +{ + return mt9t001_set_power(subdev, 0); } +static struct v4l2_subdev_core_ops mt9t001_subdev_core_ops = { + .s_power = mt9t001_set_power, +}; + static struct v4l2_subdev_video_ops mt9t001_subdev_video_ops = { .s_stream = mt9t001_s_stream, }; @@ -668,58 +824,17 @@ static struct v4l2_subdev_pad_ops mt9t001_subdev_pad_ops = { }; static struct v4l2_subdev_ops mt9t001_subdev_ops = { + .core = &mt9t001_subdev_core_ops, .video = &mt9t001_subdev_video_ops, .pad = &mt9t001_subdev_pad_ops, }; static struct v4l2_subdev_internal_ops mt9t001_subdev_internal_ops = { + .registered = mt9t001_registered, .open = mt9t001_open, + .close = mt9t001_close, }; -static int mt9t001_video_probe(struct i2c_client *client) -{ - struct mt9t001_platform_data *pdata = client->dev.platform_data; - s32 data; - int ret; - - dev_info(&client->dev, "Probing MT9T001 at address 0x%02x\n", - client->addr); - - /* Reset the chip and stop data read out */ - ret = mt9t001_write(client, MT9T001_RESET, 1); - if (ret < 0) - return ret; - - ret = mt9t001_write(client, MT9T001_RESET, 0); - if (ret < 0) - return ret; - - ret = mt9t001_write(client, MT9T001_OUTPUT_CONTROL, 0); - if (ret < 0) - return ret; - - /* Configure the pixel clock polarity */ - if (pdata->clk_pol) { - ret = mt9t001_write(client, MT9T001_PIXEL_CLOCK, - MT9T001_PIXEL_CLOCK_INVERT); - if (ret < 0) - return ret; - } - - /* Read and check the sensor version */ - data = mt9t001_read(client, MT9T001_CHIP_VERSION); - if (data != MT9T001_CHIP_ID) { - dev_err(&client->dev, "MT9T001 not detected, wrong version " - "0x%04x\n", data); - return -ENODEV; - } - - dev_info(&client->dev, "MT9T001 detected at address 0x%02x\n", - client->addr); - - return ret; -} - static int mt9t001_probe(struct i2c_client *client, const struct i2c_device_id *did) { @@ -740,14 +855,28 @@ static int mt9t001_probe(struct i2c_client *client, return -EIO; } - ret = mt9t001_video_probe(client); - if (ret < 0) - return ret; - mt9t001 = devm_kzalloc(&client->dev, sizeof(*mt9t001), GFP_KERNEL); if (!mt9t001) return -ENOMEM; + mutex_init(&mt9t001->power_lock); + mt9t001->output_control = MT9T001_OUTPUT_CONTROL_DEF; + + mt9t001->regulators[0].supply = "vdd"; + mt9t001->regulators[1].supply = "vaa"; + + ret = devm_regulator_bulk_get(&client->dev, 2, mt9t001->regulators); + if (ret < 0) { + dev_err(&client->dev, "Unable to get regulators\n"); + return ret; + } + + mt9t001->clk = devm_clk_get(&client->dev, NULL); + if (IS_ERR(mt9t001->clk)) { + dev_err(&client->dev, "Unable to get clock\n"); + return PTR_ERR(mt9t001->clk); + } + v4l2_ctrl_handler_init(&mt9t001->ctrls, ARRAY_SIZE(mt9t001_ctrls) + ARRAY_SIZE(mt9t001_gains) + 4); diff --git a/drivers/media/i2c/mt9v011.c b/drivers/media/i2c/mt9v011.c index f74698c..47e4753 100644 --- a/drivers/media/i2c/mt9v011.c +++ b/drivers/media/i2c/mt9v011.c @@ -1,7 +1,7 @@ /* * mt9v011 -Micron 1/4-Inch VGA Digital Image Sensor * - * Copyright (c) 2009 Mauro Carvalho Chehab (mchehab@redhat.com) + * Copyright (c) 2009 Mauro Carvalho Chehab * This code is placed under the terms of the GNU General Public License v2 */ @@ -16,7 +16,7 @@ #include <media/mt9v011.h> MODULE_DESCRIPTION("Micron mt9v011 sensor driver"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_LICENSE("GPL"); static int debug; diff --git a/drivers/media/i2c/mt9v032.c b/drivers/media/i2c/mt9v032.c index 36c504b..40172b8 100644 --- a/drivers/media/i2c/mt9v032.c +++ b/drivers/media/i2c/mt9v032.c @@ -317,8 +317,14 @@ static int mt9v032_power_on(struct mt9v032 *mt9v032) struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); int ret; - clk_set_rate(mt9v032->clk, mt9v032->sysclk); - clk_prepare_enable(mt9v032->clk); + ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk); + if (ret < 0) + return ret; + + ret = clk_prepare_enable(mt9v032->clk); + if (ret) + return ret; + udelay(1); /* Reset the chip and stop data read out */ diff --git a/drivers/media/i2c/sr030pc30.c b/drivers/media/i2c/sr030pc30.c index ae94326..118f8ee 100644 --- a/drivers/media/i2c/sr030pc30.c +++ b/drivers/media/i2c/sr030pc30.c @@ -8,7 +8,7 @@ * and HeungJun Kim <riverful.kim@samsung.com>. * * Based on mt9v011 Micron Digital Image Sensor driver - * Copyright (c) 2009 Mauro Carvalho Chehab (mchehab@redhat.com) + * Copyright (c) 2009 Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/media/i2c/ths8200.c b/drivers/media/i2c/ths8200.c index 04139ee..f72561e 100644 --- a/drivers/media/i2c/ths8200.c +++ b/drivers/media/i2c/ths8200.c @@ -217,8 +217,8 @@ static void ths8200_core_init(struct v4l2_subdev *sd) /* Disable embedded syncs on the output by setting * the amplitude to zero for all channels. */ - ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x2a); - ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x2a); + ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x00); + ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x00); } static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) @@ -318,15 +318,15 @@ static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) (htotal(bt) >> 8) & 0x1f); ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt)); - /* v sync width transmitted */ - ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync) & 0xff); + /* v sync width transmitted (must add 1 to get correct output) */ + ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync + 1) & 0xff); ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f, - ((bt->vsync) >> 2) & 0xc0); + ((bt->vsync + 1) >> 2) & 0xc0); - /* The pixel value v sync is asserted on */ + /* The pixel value v sync is asserted on (must add 1 to get correct output) */ ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8, - (vtotal(bt)>>8) & 0x7); - ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt)); + ((vtotal(bt) + 1) >> 8) & 0x7); + ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt) + 1); /* For progressive video vlength2 must be set to all 0 and vdly2 must * be set to all 1. @@ -336,11 +336,11 @@ static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff); /* Internal delay factors to synchronize the sync pulses and the data */ - /* Experimental values delays (hor 4, ver 1) */ - ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, (htotal(bt)>>8) & 0x1f); - ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, (htotal(bt) - 4) & 0xff); + /* Experimental values delays (hor 0, ver 0) */ + ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, 0); + ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, 0); ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0); - ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 1); + ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 0); /* Polarity of received and transmitted sync signals */ if (bt->polarities & V4L2_DV_HSYNC_POS_POL) { @@ -356,7 +356,7 @@ static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) /* Timing of video input bus is derived from HS, VS, and FID dedicated * inputs */ - ths8200_write(sd, THS8200_DTG2_CNTL, 0x47 | polarity); + ths8200_write(sd, THS8200_DTG2_CNTL, 0x44 | polarity); /* leave reset */ ths8200_s_stream(sd, true); diff --git a/drivers/media/i2c/tvp5150.c b/drivers/media/i2c/tvp5150.c index 542d252..4fd3688 100644 --- a/drivers/media/i2c/tvp5150.c +++ b/drivers/media/i2c/tvp5150.c @@ -16,9 +16,9 @@ #include "tvp5150_reg.h" -#define TVP5150_H_MAX 720 -#define TVP5150_V_MAX_525_60 480 -#define TVP5150_V_MAX_OTHERS 576 +#define TVP5150_H_MAX 720U +#define TVP5150_V_MAX_525_60 480U +#define TVP5150_V_MAX_OTHERS 576U #define TVP5150_MAX_CROP_LEFT 511 #define TVP5150_MAX_CROP_TOP 127 #define TVP5150_CROP_SHIFT 2 @@ -29,7 +29,7 @@ MODULE_LICENSE("GPL"); static int debug; -module_param(debug, int, 0); +module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Debug level (0-2)"); struct tvp5150 { diff --git a/drivers/media/parport/bw-qcam.c b/drivers/media/parport/bw-qcam.c index d12bd33..8a0e84c 100644 --- a/drivers/media/parport/bw-qcam.c +++ b/drivers/media/parport/bw-qcam.c @@ -667,13 +667,16 @@ static void buffer_queue(struct vb2_buffer *vb) vb2_buffer_done(vb, VB2_BUF_STATE_DONE); } -static int buffer_finish(struct vb2_buffer *vb) +static void buffer_finish(struct vb2_buffer *vb) { struct qcam *qcam = vb2_get_drv_priv(vb->vb2_queue); void *vbuf = vb2_plane_vaddr(vb, 0); int size = vb->vb2_queue->plane_sizes[0]; int len; + if (!vb2_is_streaming(vb->vb2_queue)) + return; + mutex_lock(&qcam->lock); parport_claim_or_block(qcam->pdev); @@ -691,7 +694,6 @@ static int buffer_finish(struct vb2_buffer *vb) if (len != size) vb->state = VB2_BUF_STATE_ERROR; vb2_set_plane_payload(vb, 0, len); - return 0; } static struct vb2_ops qcam_video_qops = { @@ -965,7 +967,7 @@ static struct qcam *qcam_init(struct parport *port) q->drv_priv = qcam; q->ops = &qcam_video_qops; q->mem_ops = &vb2_vmalloc_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; err = vb2_queue_init(q); if (err < 0) { v4l2_err(v4l2_dev, "couldn't init vb2_queue for %s.\n", port->name); diff --git a/drivers/media/pci/bt8xx/bttv-cards.c b/drivers/media/pci/bt8xx/bttv-cards.c index 6662b49..d06963b 100644 --- a/drivers/media/pci/bt8xx/bttv-cards.c +++ b/drivers/media/pci/bt8xx/bttv-cards.c @@ -2855,7 +2855,22 @@ struct tvcard bttv_tvcards[] = { .tuner_type = TUNER_ABSENT, .tuner_addr = ADDR_UNSET, }, - + [BTTV_BOARD_KWORLD_VSTREAM_XPERT] = { + /* Pojar George <geoubuntu@gmail.com> */ + .name = "Kworld V-Stream Xpert TV PVR878", + .video_inputs = 3, + /* .audio_inputs= 1, */ + .svhs = 2, + .gpiomask = 0x001c0007, + .muxsel = MUXSEL(2, 3, 1, 1), + .gpiomux = { 0, 1, 2, 2 }, + .gpiomute = 3, + .pll = PLL_28, + .tuner_type = TUNER_TENA_9533_DI, + .tuner_addr = ADDR_UNSET, + .has_remote = 1, + .has_radio = 1, + }, }; static const unsigned int bttv_num_tvcards = ARRAY_SIZE(bttv_tvcards); diff --git a/drivers/media/pci/bt8xx/bttv-input.c b/drivers/media/pci/bt8xx/bttv-input.c index f368213..5930bce 100644 --- a/drivers/media/pci/bt8xx/bttv-input.c +++ b/drivers/media/pci/bt8xx/bttv-input.c @@ -483,6 +483,7 @@ int bttv_input_init(struct bttv *btv) case BTTV_BOARD_ASKEY_CPH03X: case BTTV_BOARD_CONCEPTRONIC_CTVFMI2: case BTTV_BOARD_CONTVFMI: + case BTTV_BOARD_KWORLD_VSTREAM_XPERT: ir_codes = RC_MAP_PIXELVIEW; ir->mask_keycode = 0x001F00; ir->mask_keyup = 0x006000; diff --git a/drivers/media/pci/bt8xx/bttv.h b/drivers/media/pci/bt8xx/bttv.h index df578ef..bb5da34 100644 --- a/drivers/media/pci/bt8xx/bttv.h +++ b/drivers/media/pci/bt8xx/bttv.h @@ -188,6 +188,7 @@ #define BTTV_BOARD_ADLINK_MPG24 0xa2 #define BTTV_BOARD_BT848_CAP_14 0xa3 #define BTTV_BOARD_CYBERVISION_CV06 0xa4 +#define BTTV_BOARD_KWORLD_VSTREAM_XPERT 0xa5 /* more card-specific defines */ #define PT2254_L_CHANNEL 0x10 diff --git a/drivers/media/pci/cx23885/cx23885-dvb.c b/drivers/media/pci/cx23885/cx23885-dvb.c index 0549205..4be01b3 100644 --- a/drivers/media/pci/cx23885/cx23885-dvb.c +++ b/drivers/media/pci/cx23885/cx23885-dvb.c @@ -473,6 +473,7 @@ static struct ds3000_config tevii_ds3000_config = { static struct ts2020_config tevii_ts2020_config = { .tuner_address = 0x60, .clk_out_div = 1, + .frequency_div = 1146000, }; static struct cx24116_config dvbworld_cx24116_config = { diff --git a/drivers/media/pci/cx23885/cx23885-input.c b/drivers/media/pci/cx23885/cx23885-input.c index 8a49e7c..097d0a0 100644 --- a/drivers/media/pci/cx23885/cx23885-input.c +++ b/drivers/media/pci/cx23885/cx23885-input.c @@ -346,7 +346,7 @@ int cx23885_input_init(struct cx23885_dev *dev) } rc->dev.parent = &dev->pci->dev; rc->driver_type = driver_type; - rc->allowed_protos = allowed_protos; + rc_set_allowed_protocols(rc, allowed_protos); rc->priv = kernel_ir; rc->open = cx23885_input_ir_open; rc->close = cx23885_input_ir_close; diff --git a/drivers/media/pci/cx88/cx88-input.c b/drivers/media/pci/cx88/cx88-input.c index f29e18c..f991696 100644 --- a/drivers/media/pci/cx88/cx88-input.c +++ b/drivers/media/pci/cx88/cx88-input.c @@ -469,7 +469,7 @@ int cx88_ir_init(struct cx88_core *core, struct pci_dev *pci) dev->timeout = 10 * 1000 * 1000; /* 10 ms */ } else { dev->driver_type = RC_DRIVER_SCANCODE; - dev->allowed_protos = rc_type; + rc_set_allowed_protocols(dev, rc_type); } ir->core = core; diff --git a/drivers/media/pci/ddbridge/ddbridge-core.c b/drivers/media/pci/ddbridge/ddbridge-core.c index 9375f30..fb52bda8 100644 --- a/drivers/media/pci/ddbridge/ddbridge-core.c +++ b/drivers/media/pci/ddbridge/ddbridge-core.c @@ -876,10 +876,8 @@ static int dvb_input_attach(struct ddb_input *input) return -ENODEV; if (tuner_attach_tda18271(input) < 0) return -ENODEV; - if (input->fe) { - if (dvb_register_frontend(adap, input->fe) < 0) - return -ENODEV; - } + if (dvb_register_frontend(adap, input->fe) < 0) + return -ENODEV; if (input->fe2) { if (dvb_register_frontend(adap, input->fe2) < 0) return -ENODEV; diff --git a/drivers/media/pci/saa7134/saa7134-cards.c b/drivers/media/pci/saa7134/saa7134-cards.c index c9b2350..6e4bdb9 100644 --- a/drivers/media/pci/saa7134/saa7134-cards.c +++ b/drivers/media/pci/saa7134/saa7134-cards.c @@ -8045,8 +8045,8 @@ int saa7134_board_init2(struct saa7134_dev *dev) break; } /* switch() */ - /* initialize tuner */ - if (TUNER_ABSENT != dev->tuner_type) { + /* initialize tuner (don't do this when resuming) */ + if (!dev->insuspend && TUNER_ABSENT != dev->tuner_type) { int has_demod = (dev->tda9887_conf & TDA9887_PRESENT); /* Note: radio tuner address is always filled in, diff --git a/drivers/media/pci/sta2x11/sta2x11_vip.c b/drivers/media/pci/sta2x11/sta2x11_vip.c index e5cfb6c..bb11443 100644 --- a/drivers/media/pci/sta2x11/sta2x11_vip.c +++ b/drivers/media/pci/sta2x11/sta2x11_vip.c @@ -327,7 +327,7 @@ static void buffer_queue(struct vb2_buffer *vb) } spin_unlock(&vip->lock); } -static int buffer_finish(struct vb2_buffer *vb) +static void buffer_finish(struct vb2_buffer *vb) { struct sta2x11_vip *vip = vb2_get_drv_priv(vb->vb2_queue); struct vip_buffer *vip_buf = to_vip_buffer(vb); @@ -337,9 +337,8 @@ static int buffer_finish(struct vb2_buffer *vb) list_del_init(&vip_buf->list); spin_unlock(&vip->lock); - vip_active_buf_next(vip); - - return 0; + if (vb2_is_streaming(vb->vb2_queue)) + vip_active_buf_next(vip); } static int start_streaming(struct vb2_queue *vq, unsigned int count) diff --git a/drivers/media/pci/ttpci/av7110_hw.c b/drivers/media/pci/ttpci/av7110_hw.c index 6299d5d..300bd3c 100644 --- a/drivers/media/pci/ttpci/av7110_hw.c +++ b/drivers/media/pci/ttpci/av7110_hw.c @@ -501,7 +501,7 @@ int av7110_fw_cmd(struct av7110 *av7110, int type, int com, int num, ...) // dprintk(4, "%p\n", av7110); - if (2 + num > sizeof(buf)) { + if (2 + num > ARRAY_SIZE(buf)) { printk(KERN_WARNING "%s: %s len=%d is too big!\n", KBUILD_MODNAME, __func__, num); diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index b2a4403..c137abf 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -36,7 +36,7 @@ source "drivers/media/platform/blackfin/Kconfig" config VIDEO_SH_VOU tristate "SuperH VOU video output driver" depends on MEDIA_CAMERA_SUPPORT - depends on VIDEO_DEV && I2C + depends on VIDEO_DEV && I2C && HAS_DMA depends on ARCH_SHMOBILE || COMPILE_TEST select VIDEOBUF_DMA_CONTIG help diff --git a/drivers/media/platform/arv.c b/drivers/media/platform/arv.c index e346d32d..e9410e4 100644 --- a/drivers/media/platform/arv.c +++ b/drivers/media/platform/arv.c @@ -109,7 +109,7 @@ extern struct cpuinfo_m32r boot_cpu_data; struct ar { struct v4l2_device v4l2_dev; struct video_device vdev; - unsigned int start_capture; /* duaring capture in INT. mode. */ + int start_capture; /* duaring capture in INT. mode. */ #if USE_INT unsigned char *line_buff; /* DMA line buffer */ #endif @@ -307,11 +307,11 @@ static ssize_t ar_read(struct file *file, char *buf, size_t count, loff_t *ppos) /* * Okay, kick AR LSI to invoke an interrupt */ - ar->start_capture = 0; + ar->start_capture = -1; ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1); local_irq_restore(flags); /* .... AR interrupts .... */ - interruptible_sleep_on(&ar->wait); + wait_event_interruptible(ar->wait, ar->start_capture == 0); if (signal_pending(current)) { printk(KERN_ERR "arv: interrupted while get frame data.\n"); ret = -EINTR; diff --git a/drivers/media/platform/blackfin/bfin_capture.c b/drivers/media/platform/blackfin/bfin_capture.c index 2819165..200bec9 100644 --- a/drivers/media/platform/blackfin/bfin_capture.c +++ b/drivers/media/platform/blackfin/bfin_capture.c @@ -997,7 +997,7 @@ static int bcap_probe(struct platform_device *pdev) q->buf_struct_size = sizeof(struct bcap_buffer); q->ops = &bcap_video_qops; q->mem_ops = &vb2_dma_contig_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(q); if (ret) diff --git a/drivers/media/platform/coda.c b/drivers/media/platform/coda.c index 61f3dbc..3e5199e 100644 --- a/drivers/media/platform/coda.c +++ b/drivers/media/platform/coda.c @@ -2428,7 +2428,7 @@ static int coda_queue_init(void *priv, struct vb2_queue *src_vq, src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->ops = &coda_qops; src_vq->mem_ops = &vb2_dma_contig_memops; - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(src_vq); if (ret) @@ -2440,7 +2440,7 @@ static int coda_queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); dst_vq->ops = &coda_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; return vb2_queue_init(dst_vq); } @@ -2829,6 +2829,9 @@ static void coda_finish_encode(struct coda_ctx *ctx) } dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp; + dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_buf->v4l2_buf.flags |= + src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode; v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); diff --git a/drivers/media/platform/davinci/vpbe_display.c b/drivers/media/platform/davinci/vpbe_display.c index b02aba4..b4f12d0 100644 --- a/drivers/media/platform/davinci/vpbe_display.c +++ b/drivers/media/platform/davinci/vpbe_display.c @@ -341,14 +341,8 @@ static int vpbe_start_streaming(struct vb2_queue *vq, unsigned int count) { struct vpbe_fh *fh = vb2_get_drv_priv(vq); struct vpbe_layer *layer = fh->layer; - struct vpbe_device *vpbe_dev = fh->disp_dev->vpbe_dev; int ret; - /* If buffer queue is empty, return error */ - if (list_empty(&layer->dma_queue)) { - v4l2_err(&vpbe_dev->v4l2_dev, "buffer queue is empty\n"); - return -ENOBUFS; - } /* Get the next frame from the buffer queue */ layer->next_frm = layer->cur_frm = list_entry(layer->dma_queue.next, struct vpbe_disp_buffer, list); @@ -1415,7 +1409,8 @@ static int vpbe_display_reqbufs(struct file *file, void *priv, q->ops = &video_qops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct vpbe_disp_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->min_buffers_needed = 1; ret = vb2_queue_init(q); if (ret) { diff --git a/drivers/media/platform/davinci/vpif_capture.c b/drivers/media/platform/davinci/vpif_capture.c index 735ec47..756da78 100644 --- a/drivers/media/platform/davinci/vpif_capture.c +++ b/drivers/media/platform/davinci/vpif_capture.c @@ -272,13 +272,7 @@ static int vpif_start_streaming(struct vb2_queue *vq, unsigned int count) unsigned long flags; int ret; - /* If buffer queue is empty, return error */ spin_lock_irqsave(&common->irqlock, flags); - if (list_empty(&common->dma_queue)) { - spin_unlock_irqrestore(&common->irqlock, flags); - vpif_dbg(1, debug, "buffer queue is empty\n"); - return -ENOBUFS; - } /* Get the next frame from the buffer queue */ common->cur_frm = common->next_frm = list_entry(common->dma_queue.next, @@ -1023,7 +1017,8 @@ static int vpif_reqbufs(struct file *file, void *priv, q->ops = &video_qops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct vpif_cap_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->min_buffers_needed = 1; ret = vb2_queue_init(q); if (ret) { diff --git a/drivers/media/platform/davinci/vpif_display.c b/drivers/media/platform/davinci/vpif_display.c index 9d115cd..0ac841e 100644 --- a/drivers/media/platform/davinci/vpif_display.c +++ b/drivers/media/platform/davinci/vpif_display.c @@ -234,13 +234,7 @@ static int vpif_start_streaming(struct vb2_queue *vq, unsigned int count) unsigned long flags; int ret; - /* If buffer queue is empty, return error */ spin_lock_irqsave(&common->irqlock, flags); - if (list_empty(&common->dma_queue)) { - spin_unlock_irqrestore(&common->irqlock, flags); - vpif_err("buffer queue is empty\n"); - return -ENOBUFS; - } /* Get the next frame from the buffer queue */ common->next_frm = common->cur_frm = @@ -983,7 +977,8 @@ static int vpif_reqbufs(struct file *file, void *priv, q->ops = &video_qops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct vpif_disp_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->min_buffers_needed = 1; ret = vb2_queue_init(q); if (ret) { diff --git a/drivers/media/platform/exynos-gsc/gsc-m2m.c b/drivers/media/platform/exynos-gsc/gsc-m2m.c index 810c3e1..d0ea94f 100644 --- a/drivers/media/platform/exynos-gsc/gsc-m2m.c +++ b/drivers/media/platform/exynos-gsc/gsc-m2m.c @@ -88,8 +88,12 @@ void gsc_m2m_job_finish(struct gsc_ctx *ctx, int vb_state) dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx); if (src_vb && dst_vb) { - src_vb->v4l2_buf.timestamp = dst_vb->v4l2_buf.timestamp; - src_vb->v4l2_buf.timecode = dst_vb->v4l2_buf.timecode; + dst_vb->v4l2_buf.timestamp = src_vb->v4l2_buf.timestamp; + dst_vb->v4l2_buf.timecode = src_vb->v4l2_buf.timecode; + dst_vb->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_vb->v4l2_buf.flags |= + src_vb->v4l2_buf.flags + & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; v4l2_m2m_buf_done(src_vb, vb_state); v4l2_m2m_buf_done(dst_vb, vb_state); @@ -590,7 +594,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->ops = &gsc_m2m_qops; src_vq->mem_ops = &vb2_dma_contig_memops; src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(src_vq); if (ret) @@ -603,7 +607,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->ops = &gsc_m2m_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; return vb2_queue_init(dst_vq); } diff --git a/drivers/media/platform/exynos4-is/fimc-capture.c b/drivers/media/platform/exynos4-is/fimc-capture.c index 8a712ca..92ae812 100644 --- a/drivers/media/platform/exynos4-is/fimc-capture.c +++ b/drivers/media/platform/exynos4-is/fimc-capture.c @@ -1782,7 +1782,7 @@ static int fimc_register_capture_device(struct fimc_dev *fimc, q->ops = &fimc_capture_qops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct fimc_vid_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; q->lock = &fimc->lock; ret = vb2_queue_init(q); diff --git a/drivers/media/platform/exynos4-is/fimc-lite.c b/drivers/media/platform/exynos4-is/fimc-lite.c index 779ec3c..3ad660b 100644 --- a/drivers/media/platform/exynos4-is/fimc-lite.c +++ b/drivers/media/platform/exynos4-is/fimc-lite.c @@ -1313,7 +1313,7 @@ static int fimc_lite_subdev_registered(struct v4l2_subdev *sd) q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct flite_buffer); q->drv_priv = fimc; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; q->lock = &fimc->lock; ret = vb2_queue_init(q); diff --git a/drivers/media/platform/exynos4-is/fimc-m2m.c b/drivers/media/platform/exynos4-is/fimc-m2m.c index 9da95bd..36971d9 100644 --- a/drivers/media/platform/exynos4-is/fimc-m2m.c +++ b/drivers/media/platform/exynos4-is/fimc-m2m.c @@ -134,6 +134,9 @@ static void fimc_device_run(void *priv) goto dma_unlock; dst_vb->v4l2_buf.timestamp = src_vb->v4l2_buf.timestamp; + dst_vb->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_vb->v4l2_buf.flags |= + src_vb->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; /* Reconfigure hardware if the context has changed. */ if (fimc->m2m.ctx != ctx) { @@ -557,7 +560,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->ops = &fimc_qops; src_vq->mem_ops = &vb2_dma_contig_memops; src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; src_vq->lock = &ctx->fimc_dev->lock; ret = vb2_queue_init(src_vq); @@ -570,7 +573,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->ops = &fimc_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; dst_vq->lock = &ctx->fimc_dev->lock; return vb2_queue_init(dst_vq); diff --git a/drivers/media/platform/m2m-deinterlace.c b/drivers/media/platform/m2m-deinterlace.c index 6bb86b5..c21d14f 100644 --- a/drivers/media/platform/m2m-deinterlace.c +++ b/drivers/media/platform/m2m-deinterlace.c @@ -207,8 +207,11 @@ static void dma_callback(void *data) src_vb = v4l2_m2m_src_buf_remove(curr_ctx->m2m_ctx); dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->m2m_ctx); - src_vb->v4l2_buf.timestamp = dst_vb->v4l2_buf.timestamp; - src_vb->v4l2_buf.timecode = dst_vb->v4l2_buf.timecode; + dst_vb->v4l2_buf.timestamp = src_vb->v4l2_buf.timestamp; + dst_vb->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_vb->v4l2_buf.flags |= + src_vb->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_vb->v4l2_buf.timecode = src_vb->v4l2_buf.timecode; v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE); v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE); @@ -868,7 +871,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->ops = &deinterlace_qops; src_vq->mem_ops = &vb2_dma_contig_memops; - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; q_data[V4L2_M2M_SRC].fmt = &formats[0]; q_data[V4L2_M2M_SRC].width = 640; q_data[V4L2_M2M_SRC].height = 480; @@ -885,7 +888,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); dst_vq->ops = &deinterlace_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; q_data[V4L2_M2M_DST].fmt = &formats[0]; q_data[V4L2_M2M_DST].width = 640; q_data[V4L2_M2M_DST].height = 480; diff --git a/drivers/media/platform/marvell-ccic/mcam-core.c b/drivers/media/platform/marvell-ccic/mcam-core.c index 32fab30..8b34c48 100644 --- a/drivers/media/platform/marvell-ccic/mcam-core.c +++ b/drivers/media/platform/marvell-ccic/mcam-core.c @@ -1238,7 +1238,7 @@ static int mcam_vb_sg_buf_prepare(struct vb2_buffer *vb) return 0; } -static int mcam_vb_sg_buf_finish(struct vb2_buffer *vb) +static void mcam_vb_sg_buf_finish(struct vb2_buffer *vb) { struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue); struct sg_table *sg_table = vb2_dma_sg_plane_desc(vb, 0); @@ -1246,7 +1246,6 @@ static int mcam_vb_sg_buf_finish(struct vb2_buffer *vb) if (sg_table) dma_unmap_sg(cam->dev, sg_table->sgl, sg_table->nents, DMA_FROM_DEVICE); - return 0; } static void mcam_vb_sg_buf_cleanup(struct vb2_buffer *vb) diff --git a/drivers/media/platform/mem2mem_testdev.c b/drivers/media/platform/mem2mem_testdev.c index 08e2437..4f3096b 100644 --- a/drivers/media/platform/mem2mem_testdev.c +++ b/drivers/media/platform/mem2mem_testdev.c @@ -60,9 +60,7 @@ MODULE_PARM_DESC(debug, "activates debug info"); #define MEM2MEM_VID_MEM_LIMIT (16 * 1024 * 1024) /* Default transaction time in msec */ -#define MEM2MEM_DEF_TRANSTIME 1000 -/* Default number of buffers per transaction */ -#define MEM2MEM_DEF_TRANSLEN 1 +#define MEM2MEM_DEF_TRANSTIME 40 #define MEM2MEM_COLOR_STEP (0xff >> 4) #define MEM2MEM_NUM_TILES 8 @@ -114,6 +112,7 @@ struct m2mtest_q_data { unsigned int width; unsigned int height; unsigned int sizeimage; + unsigned int sequence; struct m2mtest_fmt *fmt; }; @@ -236,9 +235,21 @@ static int device_process(struct m2mtest_ctx *ctx, bytes_left = bytesperline - tile_w * MEM2MEM_NUM_TILES; w = 0; + out_vb->v4l2_buf.sequence = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE)->sequence++; + in_vb->v4l2_buf.sequence = q_data->sequence++; memcpy(&out_vb->v4l2_buf.timestamp, &in_vb->v4l2_buf.timestamp, sizeof(struct timeval)); + if (in_vb->v4l2_buf.flags & V4L2_BUF_FLAG_TIMECODE) + memcpy(&out_vb->v4l2_buf.timecode, &in_vb->v4l2_buf.timecode, + sizeof(struct v4l2_timecode)); + out_vb->v4l2_buf.field = in_vb->v4l2_buf.field; + out_vb->v4l2_buf.flags = in_vb->v4l2_buf.flags & + (V4L2_BUF_FLAG_TIMECODE | + V4L2_BUF_FLAG_KEYFRAME | + V4L2_BUF_FLAG_PFRAME | + V4L2_BUF_FLAG_BFRAME | + V4L2_BUF_FLAG_TSTAMP_SRC_MASK); switch (ctx->mode) { case MEM2MEM_HFLIP | MEM2MEM_VFLIP: @@ -505,19 +516,8 @@ static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, static int vidioc_try_fmt(struct v4l2_format *f, struct m2mtest_fmt *fmt) { - enum v4l2_field field; - - field = f->fmt.pix.field; - - if (field == V4L2_FIELD_ANY) - field = V4L2_FIELD_NONE; - else if (V4L2_FIELD_NONE != field) - return -EINVAL; - /* V4L2 specification suggests the driver corrects the format struct * if any of the dimensions is unsupported */ - f->fmt.pix.field = field; - if (f->fmt.pix.height < MIN_H) f->fmt.pix.height = MIN_H; else if (f->fmt.pix.height > MAX_H) @@ -531,6 +531,8 @@ static int vidioc_try_fmt(struct v4l2_format *f, struct m2mtest_fmt *fmt) f->fmt.pix.width &= ~DIM_ALIGN_MASK; f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3; f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; + f->fmt.pix.field = V4L2_FIELD_NONE; + f->fmt.pix.priv = 0; return 0; } @@ -542,7 +544,11 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, struct m2mtest_ctx *ctx = file2ctx(file); fmt = find_format(f); - if (!fmt || !(fmt->types & MEM2MEM_CAPTURE)) { + if (!fmt) { + f->fmt.pix.pixelformat = formats[0].fourcc; + fmt = find_format(f); + } + if (!(fmt->types & MEM2MEM_CAPTURE)) { v4l2_err(&ctx->dev->v4l2_dev, "Fourcc format (0x%08x) invalid.\n", f->fmt.pix.pixelformat); @@ -560,7 +566,11 @@ static int vidioc_try_fmt_vid_out(struct file *file, void *priv, struct m2mtest_ctx *ctx = file2ctx(file); fmt = find_format(f); - if (!fmt || !(fmt->types & MEM2MEM_OUTPUT)) { + if (!fmt) { + f->fmt.pix.pixelformat = formats[0].fourcc; + fmt = find_format(f); + } + if (!(fmt->types & MEM2MEM_OUTPUT)) { v4l2_err(&ctx->dev->v4l2_dev, "Fourcc format (0x%08x) invalid.\n", f->fmt.pix.pixelformat); @@ -740,6 +750,15 @@ static int m2mtest_buf_prepare(struct vb2_buffer *vb) dprintk(ctx->dev, "type: %d\n", vb->vb2_queue->type); q_data = get_q_data(ctx, vb->vb2_queue->type); + if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) { + if (vb->v4l2_buf.field == V4L2_FIELD_ANY) + vb->v4l2_buf.field = V4L2_FIELD_NONE; + if (vb->v4l2_buf.field != V4L2_FIELD_NONE) { + dprintk(ctx->dev, "%s field isn't supported\n", + __func__); + return -EINVAL; + } + } if (vb2_plane_size(vb, 0) < q_data->sizeimage) { dprintk(ctx->dev, "%s data will not fit into plane (%lu < %lu)\n", @@ -755,13 +774,45 @@ static int m2mtest_buf_prepare(struct vb2_buffer *vb) static void m2mtest_buf_queue(struct vb2_buffer *vb) { struct m2mtest_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); + v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vb); } +static int m2mtest_start_streaming(struct vb2_queue *q, unsigned count) +{ + struct m2mtest_ctx *ctx = vb2_get_drv_priv(q); + struct m2mtest_q_data *q_data = get_q_data(ctx, q->type); + + q_data->sequence = 0; + return 0; +} + +static int m2mtest_stop_streaming(struct vb2_queue *q) +{ + struct m2mtest_ctx *ctx = vb2_get_drv_priv(q); + struct vb2_buffer *vb; + unsigned long flags; + + for (;;) { + if (V4L2_TYPE_IS_OUTPUT(q->type)) + vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + else + vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + if (vb == NULL) + return 0; + spin_lock_irqsave(&ctx->dev->irqlock, flags); + v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR); + spin_unlock_irqrestore(&ctx->dev->irqlock, flags); + } + return 0; +} + static struct vb2_ops m2mtest_qops = { .queue_setup = m2mtest_queue_setup, .buf_prepare = m2mtest_buf_prepare, .buf_queue = m2mtest_buf_queue, + .start_streaming = m2mtest_start_streaming, + .stop_streaming = m2mtest_stop_streaming, .wait_prepare = vb2_ops_wait_prepare, .wait_finish = vb2_ops_wait_finish, }; @@ -772,12 +823,12 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *ds int ret; src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; - src_vq->io_modes = VB2_MMAP | VB2_DMABUF; + src_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; src_vq->drv_priv = ctx; src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->ops = &m2mtest_qops; src_vq->mem_ops = &vb2_vmalloc_memops; - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; src_vq->lock = &ctx->dev->dev_mutex; ret = vb2_queue_init(src_vq); @@ -785,12 +836,12 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *ds return ret; dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; + dst_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; dst_vq->drv_priv = ctx; dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); dst_vq->ops = &m2mtest_qops; dst_vq->mem_ops = &vb2_vmalloc_memops; - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; dst_vq->lock = &ctx->dev->dev_mutex; return vb2_queue_init(dst_vq); @@ -801,10 +852,10 @@ static const struct v4l2_ctrl_config m2mtest_ctrl_trans_time_msec = { .id = V4L2_CID_TRANS_TIME_MSEC, .name = "Transaction Time (msec)", .type = V4L2_CTRL_TYPE_INTEGER, - .def = 1001, + .def = MEM2MEM_DEF_TRANSTIME, .min = 1, .max = 10001, - .step = 100, + .step = 1, }; static const struct v4l2_ctrl_config m2mtest_ctrl_trans_num_bufs = { diff --git a/drivers/media/platform/mx2_emmaprp.c b/drivers/media/platform/mx2_emmaprp.c index c690435..0b7480e 100644 --- a/drivers/media/platform/mx2_emmaprp.c +++ b/drivers/media/platform/mx2_emmaprp.c @@ -377,8 +377,13 @@ static irqreturn_t emmaprp_irq(int irq_emma, void *data) src_vb = v4l2_m2m_src_buf_remove(curr_ctx->m2m_ctx); dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->m2m_ctx); - src_vb->v4l2_buf.timestamp = dst_vb->v4l2_buf.timestamp; - src_vb->v4l2_buf.timecode = dst_vb->v4l2_buf.timecode; + dst_vb->v4l2_buf.timestamp = src_vb->v4l2_buf.timestamp; + dst_vb->v4l2_buf.flags &= + ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_vb->v4l2_buf.flags |= + src_vb->v4l2_buf.flags + & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_vb->v4l2_buf.timecode = src_vb->v4l2_buf.timecode; spin_lock_irqsave(&pcdev->irqlock, flags); v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE); @@ -766,7 +771,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->ops = &emmaprp_qops; src_vq->mem_ops = &vb2_dma_contig_memops; - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(src_vq); if (ret) @@ -778,7 +783,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); dst_vq->ops = &emmaprp_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; return vb2_queue_init(dst_vq); } diff --git a/drivers/media/platform/omap/omap_vout.c b/drivers/media/platform/omap/omap_vout.c index dfd0a21..9a726ea 100644 --- a/drivers/media/platform/omap/omap_vout.c +++ b/drivers/media/platform/omap/omap_vout.c @@ -601,6 +601,7 @@ static void omap_vout_isr(void *arg, unsigned int irqstatus) switch (cur_display->type) { case OMAP_DISPLAY_TYPE_DSI: case OMAP_DISPLAY_TYPE_DPI: + case OMAP_DISPLAY_TYPE_DVI: if (mgr_id == OMAP_DSS_CHANNEL_LCD) irq = DISPC_IRQ_VSYNC; else if (mgr_id == OMAP_DSS_CHANNEL_LCD2) diff --git a/drivers/media/platform/omap/omap_vout_vrfb.c b/drivers/media/platform/omap/omap_vout_vrfb.c index cf1c437..62e7e57 100644 --- a/drivers/media/platform/omap/omap_vout_vrfb.c +++ b/drivers/media/platform/omap/omap_vout_vrfb.c @@ -270,7 +270,8 @@ int omap_vout_prepare_vrfb(struct omap_vout_device *vout, omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, 0x20, 0); omap_start_dma(tx->dma_ch); - interruptible_sleep_on_timeout(&tx->wait, VRFB_TX_TIMEOUT); + wait_event_interruptible_timeout(tx->wait, tx->tx_status == 1, + VRFB_TX_TIMEOUT); if (tx->tx_status == 0) { omap_stop_dma(tx->dma_ch); diff --git a/drivers/media/platform/omap3isp/isp.c b/drivers/media/platform/omap3isp/isp.c index 5807185..06a0df4 100644 --- a/drivers/media/platform/omap3isp/isp.c +++ b/drivers/media/platform/omap3isp/isp.c @@ -391,7 +391,7 @@ static void isp_disable_interrupts(struct isp_device *isp) * @isp: OMAP3 ISP device * @idle: Consider idle state. * - * Set the power settings for the ISP and SBL bus and cConfigure the HS/VS + * Set the power settings for the ISP and SBL bus and configure the HS/VS * interrupt source. * * We need to configure the HS/VS interrupt source before interrupts get @@ -588,9 +588,6 @@ static void isp_isr_sbl(struct isp_device *isp) * @_isp: Pointer to the OMAP3 ISP device * * Handles the corresponding callback if plugged in. - * - * Returns IRQ_HANDLED when IRQ was correctly handled, or IRQ_NONE when the - * IRQ wasn't handled. */ static irqreturn_t isp_isr(int irq, void *_isp) { @@ -1420,7 +1417,7 @@ int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait, } /* - * omap3isp_module_sync_is_stopped - Helper to verify if module was stopping + * omap3isp_module_sync_is_stopping - Helper to verify if module was stopping * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization * @stopping: flag which tells module wants to stop * diff --git a/drivers/media/platform/omap3isp/isp.h b/drivers/media/platform/omap3isp/isp.h index 081f5ec..6d5e697 100644 --- a/drivers/media/platform/omap3isp/isp.h +++ b/drivers/media/platform/omap3isp/isp.h @@ -265,7 +265,7 @@ void omap3isp_unregister_entities(struct platform_device *pdev); /* * isp_reg_readl - Read value of an OMAP3 ISP register - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * @isp_mmio_range: Range to which the register offset refers to. * @reg_offset: Register offset to read from. * @@ -280,7 +280,7 @@ u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range, /* * isp_reg_writel - Write value to an OMAP3 ISP register - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * @reg_value: 32 bit value to write to the register. * @isp_mmio_range: Range to which the register offset refers to. * @reg_offset: Register offset to write into. @@ -293,8 +293,8 @@ void isp_reg_writel(struct isp_device *isp, u32 reg_value, } /* - * isp_reg_and - Clear individual bits in an OMAP3 ISP register - * @dev: Device pointer specific to the OMAP3 ISP. + * isp_reg_clr - Clear individual bits in an OMAP3 ISP register + * @isp: Device pointer specific to the OMAP3 ISP. * @mmio_range: Range to which the register offset refers to. * @reg: Register offset to work on. * @clr_bits: 32 bit value which would be cleared in the register. @@ -310,7 +310,7 @@ void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range, /* * isp_reg_set - Set individual bits in an OMAP3 ISP register - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * @mmio_range: Range to which the register offset refers to. * @reg: Register offset to work on. * @set_bits: 32 bit value which would be set in the register. @@ -326,7 +326,7 @@ void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range, /* * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * @mmio_range: Range to which the register offset refers to. * @reg: Register offset to work on. * @clr_bits: 32 bit value which would be cleared in the register. diff --git a/drivers/media/platform/omap3isp/ispccdc.c b/drivers/media/platform/omap3isp/ispccdc.c index 5db2c88..4d920c8 100644 --- a/drivers/media/platform/omap3isp/ispccdc.c +++ b/drivers/media/platform/omap3isp/ispccdc.c @@ -293,7 +293,7 @@ static int __ccdc_lsc_enable(struct isp_ccdc_device *ccdc, int enable) isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG, ISPCCDC_LSC_ENABLE); ccdc->lsc.state = LSC_STATE_STOPPED; - dev_warn(to_device(ccdc), "LSC prefecth timeout\n"); + dev_warn(to_device(ccdc), "LSC prefetch timeout\n"); return -ETIMEDOUT; } ccdc->lsc.state = LSC_STATE_RUNNING; @@ -674,7 +674,7 @@ static void ccdc_config_imgattr(struct isp_ccdc_device *ccdc, u32 colptn) /* * ccdc_config - Set CCDC configuration from userspace * @ccdc: Pointer to ISP CCDC device. - * @userspace_add: Structure containing CCDC configuration sent from userspace. + * @ccdc_struct: Structure containing CCDC configuration sent from userspace. * * Returns 0 if successful, -EINVAL if the pointer to the configuration * structure is null, or the copy_from_user function fails to copy user space @@ -793,7 +793,7 @@ static void ccdc_apply_controls(struct isp_ccdc_device *ccdc) /* * omap3isp_ccdc_restore_context - Restore values of the CCDC module registers - * @dev: Pointer to ISP device + * @isp: Pointer to ISP device */ void omap3isp_ccdc_restore_context(struct isp_device *isp) { @@ -2525,7 +2525,7 @@ error_video: /* * omap3isp_ccdc_init - CCDC module initialization. - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * * TODO: Get the initialisation values from platform data. * @@ -2564,7 +2564,7 @@ int omap3isp_ccdc_init(struct isp_device *isp) /* * omap3isp_ccdc_cleanup - CCDC module cleanup. - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. */ void omap3isp_ccdc_cleanup(struct isp_device *isp) { diff --git a/drivers/media/platform/omap3isp/ispccdc.h b/drivers/media/platform/omap3isp/ispccdc.h index a5da9e1..9d24e41 100644 --- a/drivers/media/platform/omap3isp/ispccdc.h +++ b/drivers/media/platform/omap3isp/ispccdc.h @@ -63,12 +63,6 @@ struct ispccdc_lsc_config_req { /* * ispccdc_lsc - CCDC LSC parameters - * @update_config: Set when user changes config - * @request_enable: Whether LSC is requested to be enabled - * @config: LSC config set by user - * @update_table: Set when user provides a new LSC table to table_new - * @table_new: LSC table set by user, ISP address - * @table_inuse: LSC table currently in use, ISP address */ struct ispccdc_lsc { enum ispccdc_lsc_state state; diff --git a/drivers/media/platform/omap3isp/ispccp2.c b/drivers/media/platform/omap3isp/ispccp2.c index e84fe05..b30b67d 100644 --- a/drivers/media/platform/omap3isp/ispccp2.c +++ b/drivers/media/platform/omap3isp/ispccp2.c @@ -211,7 +211,7 @@ static void ccp2_mem_enable(struct isp_ccp2_device *ccp2, u8 enable) /* * ccp2_phyif_config - Initialize CCP2 phy interface config * @ccp2: Pointer to ISP CCP2 device - * @config: CCP2 platform data + * @pdata: CCP2 platform data * * Configure the CCP2 physical interface module from platform data. * @@ -518,7 +518,7 @@ static void ccp2_mem_configure(struct isp_ccp2_device *ccp2, ISPCCP2_LCM_IRQSTATUS_EOF_IRQ, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQSTATUS); - /* Enable LCM interupts */ + /* Enable LCM interrupts */ isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQENABLE, ISPCCP2_LCM_IRQSTATUS_EOF_IRQ | ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ); @@ -1096,7 +1096,7 @@ static int ccp2_init_entities(struct isp_ccp2_device *ccp2) * implementation we use a fixed 32 bytes alignment regardless of the * input format and width. If strict 128 bits alignment support is * required ispvideo will need to be made aware of this special dual - * alignement requirements. + * alignment requirements. */ ccp2->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT; ccp2->video_in.bpl_alignment = 32; diff --git a/drivers/media/platform/omap3isp/isphist.c b/drivers/media/platform/omap3isp/isphist.c index e070c24..06a5f81 100644 --- a/drivers/media/platform/omap3isp/isphist.c +++ b/drivers/media/platform/omap3isp/isphist.c @@ -299,7 +299,7 @@ static u32 hist_get_buf_size(struct omap3isp_hist_config *conf) /* * hist_validate_params - Helper function to check user given params. - * @user_cfg: Pointer to user configuration structure. + * @new_conf: Pointer to user configuration structure. * * Returns 0 on success configuration. */ @@ -351,7 +351,7 @@ static int hist_validate_params(struct ispstat *hist, void *new_conf) buf_size = hist_get_buf_size(user_cfg); if (buf_size > user_cfg->buf_size) - /* User's buf_size request wasn't enoght */ + /* User's buf_size request wasn't enough */ user_cfg->buf_size = buf_size; else if (user_cfg->buf_size > OMAP3ISP_HIST_MAX_BUF_SIZE) user_cfg->buf_size = OMAP3ISP_HIST_MAX_BUF_SIZE; diff --git a/drivers/media/platform/omap3isp/isppreview.c b/drivers/media/platform/omap3isp/isppreview.c index 1c776c1..395b2b0 100644 --- a/drivers/media/platform/omap3isp/isppreview.c +++ b/drivers/media/platform/omap3isp/isppreview.c @@ -122,7 +122,7 @@ static struct omap3isp_prev_csc flr_prev_csc = { #define PREV_MAX_OUT_WIDTH_REV_15 4096 /* - * Coeficient Tables for the submodules in Preview. + * Coefficient Tables for the submodules in Preview. * Array is initialised with the values from.the tables text file. */ @@ -971,7 +971,8 @@ static void preview_setup_hw(struct isp_prev_device *prev, u32 update, /* * preview_config_ycpos - Configure byte layout of YUV image. - * @mode: Indicates the required byte layout. + * @prev: pointer to previewer private structure + * @pixelcode: pixel code */ static void preview_config_ycpos(struct isp_prev_device *prev, @@ -1079,6 +1080,7 @@ static void preview_config_input_format(struct isp_prev_device *prev, */ static void preview_config_input_size(struct isp_prev_device *prev, u32 active) { + const struct v4l2_mbus_framefmt *format = &prev->formats[PREV_PAD_SINK]; struct isp_device *isp = to_isp_device(prev); unsigned int sph = prev->crop.left; unsigned int eph = prev->crop.left + prev->crop.width - 1; @@ -1086,6 +1088,14 @@ static void preview_config_input_size(struct isp_prev_device *prev, u32 active) unsigned int elv = prev->crop.top + prev->crop.height - 1; u32 features; + if (format->code != V4L2_MBUS_FMT_Y8_1X8 && + format->code != V4L2_MBUS_FMT_Y10_1X10) { + sph -= 2; + eph += 2; + slv -= 2; + elv += 2; + } + features = (prev->params.params[0].features & active) | (prev->params.params[1].features & ~active); @@ -1363,8 +1373,8 @@ static void preview_init_params(struct isp_prev_device *prev) } /* - * preview_max_out_width - Handle previewer hardware ouput limitations - * @isp_revision : ISP revision + * preview_max_out_width - Handle previewer hardware output limitations + * @prev: pointer to previewer private structure * returns maximum width output for current isp revision */ static unsigned int preview_max_out_width(struct isp_prev_device *prev) @@ -1610,7 +1620,7 @@ static const struct v4l2_ctrl_ops preview_ctrl_ops = { /* * preview_ioctl - Handle preview module private ioctl's - * @prev: pointer to preview context structure + * @sd: pointer to v4l2 subdev structure * @cmd: configuration command * @arg: configuration argument * return -EINVAL or zero on success @@ -2341,7 +2351,7 @@ error_video_in: /* * omap3isp_preview_init - Previewer initialization. - * @dev : Pointer to ISP device + * @isp : Pointer to ISP device * return -ENOMEM or zero on success */ int omap3isp_preview_init(struct isp_device *isp) diff --git a/drivers/media/platform/omap3isp/ispqueue.c b/drivers/media/platform/omap3isp/ispqueue.c index 5f0f8fa..a5e6585 100644 --- a/drivers/media/platform/omap3isp/ispqueue.c +++ b/drivers/media/platform/omap3isp/ispqueue.c @@ -597,7 +597,7 @@ static int isp_video_buffer_wait(struct isp_video_buffer *buf, int nonblocking) * isp_video_queue_free - Free video buffers memory * * Buffers can only be freed if the queue isn't streaming and if no buffer is - * mapped to userspace. Return -EBUSY if those conditions aren't statisfied. + * mapped to userspace. Return -EBUSY if those conditions aren't satisfied. * * This function must be called with the queue lock held. */ diff --git a/drivers/media/platform/omap3isp/ispresizer.c b/drivers/media/platform/omap3isp/ispresizer.c index 0d36b8b..86369df 100644 --- a/drivers/media/platform/omap3isp/ispresizer.c +++ b/drivers/media/platform/omap3isp/ispresizer.c @@ -206,7 +206,7 @@ static void resizer_set_bilinear(struct isp_res_device *res, /* * resizer_set_ycpos - Luminance and chrominance order * @res: Device context. - * @order: order type. + * @pixelcode: pixel code. */ static void resizer_set_ycpos(struct isp_res_device *res, enum v4l2_mbus_pixelcode pixelcode) @@ -918,8 +918,8 @@ static void resizer_calc_ratios(struct isp_res_device *res, /* * resizer_set_crop_params - Setup hardware with cropping parameters * @res : resizer private structure - * @crop_rect : current crop rectangle - * @ratio : resizer ratios + * @input : format on sink pad + * @output : format on source pad * return none */ static void resizer_set_crop_params(struct isp_res_device *res, diff --git a/drivers/media/platform/omap3isp/ispresizer.h b/drivers/media/platform/omap3isp/ispresizer.h index 70c1c0e..9b01e90 100644 --- a/drivers/media/platform/omap3isp/ispresizer.h +++ b/drivers/media/platform/omap3isp/ispresizer.h @@ -30,12 +30,12 @@ #include <linux/types.h> /* - * Constants for filter coefficents count + * Constants for filter coefficients count */ #define COEFF_CNT 32 /* - * struct isprsz_coef - Structure for resizer filter coeffcients. + * struct isprsz_coef - Structure for resizer filter coefficients. * @h_filter_coef_4tap: Horizontal filter coefficients for 8-phase/4-tap * mode (.5x-4x) * @v_filter_coef_4tap: Vertical filter coefficients for 8-phase/4-tap diff --git a/drivers/media/platform/omap3isp/ispstat.c b/drivers/media/platform/omap3isp/ispstat.c index a75407c..5707f85 100644 --- a/drivers/media/platform/omap3isp/ispstat.c +++ b/drivers/media/platform/omap3isp/ispstat.c @@ -144,7 +144,7 @@ static int isp_stat_buf_check_magic(struct ispstat *stat, for (w = buf->virt_addr + buf_size, end = w + MAGIC_SIZE; w < end; w++) { if (unlikely(*w != MAGIC_NUM)) { - dev_dbg(stat->isp->dev, "%s: endding magic check does " + dev_dbg(stat->isp->dev, "%s: ending magic check does " "not match.\n", stat->subdev.name); return -EINVAL; } @@ -841,7 +841,7 @@ int omap3isp_stat_s_stream(struct v4l2_subdev *subdev, int enable) if (enable) { /* * Only set enable PCR bit if the module was previously - * enabled through ioct. + * enabled through ioctl. */ isp_stat_try_enable(stat); } else { diff --git a/drivers/media/platform/omap3isp/ispvideo.c b/drivers/media/platform/omap3isp/ispvideo.c index 856fdf5..85b4036 100644 --- a/drivers/media/platform/omap3isp/ispvideo.c +++ b/drivers/media/platform/omap3isp/ispvideo.c @@ -333,7 +333,7 @@ isp_video_check_format(struct isp_video *video, struct isp_video_fh *vfh) /* * ispmmu_vmap - Wrapper for Virtual memory mapping of a scatter gather list - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * @sglist: Pointer to source Scatter gather list to allocate. * @sglen: Number of elements of the scatter-gatter list. * @@ -363,7 +363,7 @@ ispmmu_vmap(struct isp_device *isp, const struct scatterlist *sglist, int sglen) /* * ispmmu_vunmap - Unmap a device address from the ISP MMU - * @dev: Device pointer specific to the OMAP3 ISP. + * @isp: Device pointer specific to the OMAP3 ISP. * @da: Device address generated from a ispmmu_vmap call. */ static void ispmmu_vunmap(struct isp_device *isp, dma_addr_t da) @@ -886,7 +886,11 @@ static int isp_video_check_external_subdevs(struct isp_video *video, struct v4l2_ext_controls ctrls; struct v4l2_ext_control ctrl; unsigned int i; - int ret = 0; + int ret; + + /* Memory-to-memory pipelines have no external subdev. */ + if (pipe->input != NULL) + return 0; for (i = 0; i < ARRAY_SIZE(ents); i++) { /* Is the entity part of the pipeline? */ @@ -905,7 +909,7 @@ static int isp_video_check_external_subdevs(struct isp_video *video, if (!source) { dev_warn(isp->dev, "can't find source, failing now\n"); - return ret; + return -EINVAL; } if (media_entity_type(source) != MEDIA_ENT_T_V4L2_SUBDEV) diff --git a/drivers/media/platform/s3c-camif/camif-capture.c b/drivers/media/platform/s3c-camif/camif-capture.c index 40b298a..4e4d163 100644 --- a/drivers/media/platform/s3c-camif/camif-capture.c +++ b/drivers/media/platform/s3c-camif/camif-capture.c @@ -1160,7 +1160,7 @@ int s3c_camif_register_video_node(struct camif_dev *camif, int idx) q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct camif_buffer); q->drv_priv = vp; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(q); if (ret) @@ -1592,26 +1592,27 @@ int s3c_camif_create_subdev(struct camif_dev *camif) ARRAY_SIZE(s3c_camif_test_pattern_menu) - 1, 0, 0, s3c_camif_test_pattern_menu); - camif->ctrl_colorfx = v4l2_ctrl_new_std_menu(handler, + if (camif->variant->has_img_effect) { + camif->ctrl_colorfx = v4l2_ctrl_new_std_menu(handler, &s3c_camif_subdev_ctrl_ops, V4L2_CID_COLORFX, V4L2_COLORFX_SET_CBCR, ~0x981f, V4L2_COLORFX_NONE); - camif->ctrl_colorfx_cbcr = v4l2_ctrl_new_std(handler, + camif->ctrl_colorfx_cbcr = v4l2_ctrl_new_std(handler, &s3c_camif_subdev_ctrl_ops, V4L2_CID_COLORFX_CBCR, 0, 0xffff, 1, 0); + } + if (handler->error) { v4l2_ctrl_handler_free(handler); media_entity_cleanup(&sd->entity); return handler->error; } - v4l2_ctrl_auto_cluster(2, &camif->ctrl_colorfx, + if (camif->variant->has_img_effect) + v4l2_ctrl_auto_cluster(2, &camif->ctrl_colorfx, V4L2_COLORFX_SET_CBCR, false); - if (!camif->variant->has_img_effect) { - camif->ctrl_colorfx->flags |= V4L2_CTRL_FLAG_DISABLED; - camif->ctrl_colorfx_cbcr->flags |= V4L2_CTRL_FLAG_DISABLED; - } + sd->ctrl_handler = handler; v4l2_set_subdevdata(sd, camif); diff --git a/drivers/media/platform/s5p-g2d/g2d.c b/drivers/media/platform/s5p-g2d/g2d.c index 0fcf7d7..357af1e 100644 --- a/drivers/media/platform/s5p-g2d/g2d.c +++ b/drivers/media/platform/s5p-g2d/g2d.c @@ -157,7 +157,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->ops = &g2d_qops; src_vq->mem_ops = &vb2_dma_contig_memops; src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; src_vq->lock = &ctx->dev->mutex; ret = vb2_queue_init(src_vq); @@ -170,7 +170,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->ops = &g2d_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; dst_vq->lock = &ctx->dev->mutex; return vb2_queue_init(dst_vq); @@ -560,6 +560,9 @@ static irqreturn_t g2d_isr(int irq, void *prv) dst->v4l2_buf.timecode = src->v4l2_buf.timecode; dst->v4l2_buf.timestamp = src->v4l2_buf.timestamp; + dst->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst->v4l2_buf.flags |= + src->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE); v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE); diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c b/drivers/media/platform/s5p-jpeg/jpeg-core.c index 7d68d0b..8a18972 100644 --- a/drivers/media/platform/s5p-jpeg/jpeg-core.c +++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c @@ -1701,7 +1701,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->ops = &s5p_jpeg_qops; src_vq->mem_ops = &vb2_dma_contig_memops; - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; src_vq->lock = &ctx->jpeg->lock; ret = vb2_queue_init(src_vq); @@ -1714,7 +1714,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); dst_vq->ops = &s5p_jpeg_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; dst_vq->lock = &ctx->jpeg->lock; return vb2_queue_init(dst_vq); @@ -1766,6 +1766,9 @@ static irqreturn_t s5p_jpeg_irq(int irq, void *dev_id) dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode; dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp; + dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_buf->v4l2_buf.flags |= + src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; v4l2_m2m_buf_done(src_buf, state); if (curr_ctx->mode == S5P_JPEG_ENCODE) diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v6.h b/drivers/media/platform/s5p-mfc/regs-mfc-v6.h index 2398cdf..8d0b686 100644 --- a/drivers/media/platform/s5p-mfc/regs-mfc-v6.h +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v6.h @@ -229,6 +229,7 @@ #define S5P_FIMV_E_PADDING_CTRL_V6 0xf7a4 #define S5P_FIMV_E_MV_HOR_RANGE_V6 0xf7ac #define S5P_FIMV_E_MV_VER_RANGE_V6 0xf7b0 +#define S5P_FIMV_E_MV_RANGE_V6_MASK 0x3fff #define S5P_FIMV_E_VBV_BUFFER_SIZE_V6 0xf84c #define S5P_FIMV_E_VBV_INIT_DELAY_V6 0xf850 diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index e2aac59..89356ae 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -232,6 +232,11 @@ static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) src_buf->b->v4l2_buf.timecode; dst_buf->b->v4l2_buf.timestamp = src_buf->b->v4l2_buf.timestamp; + dst_buf->b->v4l2_buf.flags &= + ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + dst_buf->b->v4l2_buf.flags |= + src_buf->b->v4l2_buf.flags + & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; switch (frame_type) { case S5P_FIMV_DECODE_FRAME_I_FRAME: dst_buf->b->v4l2_buf.flags |= @@ -794,7 +799,7 @@ static int s5p_mfc_open(struct file *file) goto err_queue_init; } q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(q); if (ret) { mfc_err("Failed to initialize videobuf2 queue(capture)\n"); @@ -816,7 +821,7 @@ static int s5p_mfc_open(struct file *file) goto err_queue_init; } q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(q); if (ret) { mfc_err("Failed to initialize videobuf2 queue(output)\n"); @@ -1147,9 +1152,9 @@ static int s5p_mfc_probe(struct platform_device *pdev) ret = -ENOMEM; goto err_dec_alloc; } - vfd->fops = &s5p_mfc_fops, + vfd->fops = &s5p_mfc_fops; vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); - vfd->release = video_device_release, + vfd->release = video_device_release; vfd->lock = &dev->mfc_mutex; vfd->v4l2_dev = &dev->v4l2_dev; vfd->vfl_dir = VFL_DIR_M2M; @@ -1172,9 +1177,9 @@ static int s5p_mfc_probe(struct platform_device *pdev) ret = -ENOMEM; goto err_enc_alloc; } - vfd->fops = &s5p_mfc_fops, + vfd->fops = &s5p_mfc_fops; vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); - vfd->release = video_device_release, + vfd->release = video_device_release; vfd->lock = &dev->mfc_mutex; vfd->v4l2_dev = &dev->v4l2_dev; vfd->vfl_dir = VFL_DIR_M2M; diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h index f723f1f..5c28cc3 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h @@ -426,6 +426,8 @@ struct s5p_mfc_vp8_enc_params { struct s5p_mfc_enc_params { u16 width; u16 height; + u32 mv_h_range; + u32 mv_v_range; u16 gop_size; enum v4l2_mpeg_video_multi_slice_mode slice_mode; diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c index 2475a3c..ee05f2d 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c @@ -44,8 +44,6 @@ int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev) return -ENOMEM; } - dev->bank1 = dev->bank1; - if (HAS_PORTNUM(dev) && IS_TWOPORT(dev)) { bank2_virt = dma_alloc_coherent(dev->mem_dev_r, 1 << MFC_BASE_ALIGN_ORDER, &bank2_dma_addr, GFP_KERNEL); diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c index 91b6e02..df83cd1 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c @@ -208,6 +208,24 @@ static struct mfc_control controls[] = { .default_value = 0, }, { + .id = V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Horizontal MV Search Range", + .minimum = 16, + .maximum = 128, + .step = 16, + .default_value = 32, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Vertical MV Search Range", + .minimum = 16, + .maximum = 128, + .step = 16, + .default_value = 32, + }, + { .id = V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE, .type = V4L2_CTRL_TYPE_INTEGER, .minimum = 0, @@ -1417,6 +1435,12 @@ static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_MPEG_VIDEO_VBV_SIZE: p->vbv_size = ctrl->val; break; + case V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE: + p->mv_h_range = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE: + p->mv_v_range = ctrl->val; + break; case V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE: p->codec.h264.cpb_size = ctrl->val; break; diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c index f6ff2db..f64621a 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c @@ -727,14 +727,10 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); /* setting for MV range [16, 256] */ - reg = 0; - reg &= ~(0x3FFF); - reg = 256; + reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK); WRITEL(reg, S5P_FIMV_E_MV_HOR_RANGE_V6); - reg = 0; - reg &= ~(0x3FFF); - reg = 256; + reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK); WRITEL(reg, S5P_FIMV_E_MV_VER_RANGE_V6); WRITEL(0x0, S5P_FIMV_E_FRAME_INSERTION_V6); diff --git a/drivers/media/platform/s5p-tv/mixer_video.c b/drivers/media/platform/s5p-tv/mixer_video.c index c5059ba..a1ce55f 100644 --- a/drivers/media/platform/s5p-tv/mixer_video.c +++ b/drivers/media/platform/s5p-tv/mixer_video.c @@ -946,11 +946,6 @@ static int start_streaming(struct vb2_queue *vq, unsigned int count) mxr_dbg(mdev, "%s\n", __func__); - if (count == 0) { - mxr_dbg(mdev, "no output buffers queued\n"); - return -ENOBUFS; - } - /* block any changes in output configuration */ mxr_output_get(mdev); @@ -1124,6 +1119,7 @@ struct mxr_layer *mxr_base_layer_create(struct mxr_device *mdev, .drv_priv = layer, .buf_struct_size = sizeof(struct mxr_buffer), .ops = &mxr_video_qops, + .min_buffers_needed = 1, .mem_ops = &vb2_dma_contig_memops, }; diff --git a/drivers/media/platform/soc_camera/atmel-isi.c b/drivers/media/platform/soc_camera/atmel-isi.c index 4835173..f0b6c90 100644 --- a/drivers/media/platform/soc_camera/atmel-isi.c +++ b/drivers/media/platform/soc_camera/atmel-isi.c @@ -472,7 +472,7 @@ static int isi_camera_init_videobuf(struct vb2_queue *q, q->buf_struct_size = sizeof(struct frame_buffer); q->ops = &isi_video_qops; q->mem_ops = &vb2_dma_contig_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; return vb2_queue_init(q); } diff --git a/drivers/media/platform/soc_camera/mx2_camera.c b/drivers/media/platform/soc_camera/mx2_camera.c index d73abca..3e84480 100644 --- a/drivers/media/platform/soc_camera/mx2_camera.c +++ b/drivers/media/platform/soc_camera/mx2_camera.c @@ -794,7 +794,7 @@ static int mx2_camera_init_videobuf(struct vb2_queue *q, q->ops = &mx2_videobuf_ops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct mx2_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; return vb2_queue_init(q); } diff --git a/drivers/media/platform/soc_camera/mx3_camera.c b/drivers/media/platform/soc_camera/mx3_camera.c index f975b70..9ed81ac 100644 --- a/drivers/media/platform/soc_camera/mx3_camera.c +++ b/drivers/media/platform/soc_camera/mx3_camera.c @@ -453,7 +453,7 @@ static int mx3_camera_init_videobuf(struct vb2_queue *q, q->ops = &mx3_videobuf_ops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct mx3_camera_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; return vb2_queue_init(q); } diff --git a/drivers/media/platform/soc_camera/rcar_vin.c b/drivers/media/platform/soc_camera/rcar_vin.c index 3b1c05a..704eee7 100644 --- a/drivers/media/platform/soc_camera/rcar_vin.c +++ b/drivers/media/platform/soc_camera/rcar_vin.c @@ -68,6 +68,8 @@ #define VNMC_YCAL (1 << 19) #define VNMC_INF_YUV8_BT656 (0 << 16) #define VNMC_INF_YUV8_BT601 (1 << 16) +#define VNMC_INF_YUV10_BT656 (2 << 16) +#define VNMC_INF_YUV10_BT601 (3 << 16) #define VNMC_INF_YUV16 (5 << 16) #define VNMC_VUP (1 << 10) #define VNMC_IM_ODD (0 << 3) @@ -275,6 +277,12 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) /* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */ vnmc |= priv->pdata->flags & RCAR_VIN_BT656 ? VNMC_INF_YUV8_BT656 : VNMC_INF_YUV8_BT601; + break; + case V4L2_MBUS_FMT_YUYV10_2X10: + /* BT.656 10bit YCbCr422 or BT.601 10bit YCbCr422 */ + vnmc |= priv->pdata->flags & RCAR_VIN_BT656 ? + VNMC_INF_YUV10_BT656 : VNMC_INF_YUV10_BT601; + break; default: break; } @@ -1003,6 +1011,7 @@ static int rcar_vin_get_formats(struct soc_camera_device *icd, unsigned int idx, switch (code) { case V4L2_MBUS_FMT_YUYV8_1X16: case V4L2_MBUS_FMT_YUYV8_2X8: + case V4L2_MBUS_FMT_YUYV10_2X10: if (cam->extra_fmt) break; @@ -1360,7 +1369,7 @@ static int rcar_vin_init_videobuf2(struct vb2_queue *vq, vq->ops = &rcar_vin_vb2_ops; vq->mem_ops = &vb2_dma_contig_memops; vq->buf_struct_size = sizeof(struct rcar_vin_buffer); - vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; return vb2_queue_init(vq); } diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c index 150bd4d..3e75a46 100644 --- a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +++ b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c @@ -1665,7 +1665,7 @@ static int sh_mobile_ceu_init_videobuf(struct vb2_queue *q, q->ops = &sh_mobile_ceu_videobuf_ops; q->mem_ops = &vb2_dma_contig_memops; q->buf_struct_size = sizeof(struct sh_mobile_ceu_buffer); - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; return vb2_queue_init(q); } diff --git a/drivers/media/platform/ti-vpe/vpe.c b/drivers/media/platform/ti-vpe/vpe.c index 1296c53..7a77a5b 100644 --- a/drivers/media/platform/ti-vpe/vpe.c +++ b/drivers/media/platform/ti-vpe/vpe.c @@ -1278,6 +1278,8 @@ static irqreturn_t vpe_irq(int irq_vpe, void *data) d_buf = &d_vb->v4l2_buf; d_buf->timestamp = s_buf->timestamp; + d_buf->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + d_buf->flags |= s_buf->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; if (s_buf->flags & V4L2_BUF_FLAG_TIMECODE) { d_buf->flags |= V4L2_BUF_FLAG_TIMECODE; d_buf->timecode = s_buf->timecode; @@ -1770,7 +1772,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->ops = &vpe_qops; src_vq->mem_ops = &vb2_dma_contig_memops; - src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(src_vq); if (ret) @@ -1783,7 +1785,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); dst_vq->ops = &vpe_qops; dst_vq->mem_ops = &vb2_dma_contig_memops; - dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; return vb2_queue_init(dst_vq); } diff --git a/drivers/media/platform/vivi.c b/drivers/media/platform/vivi.c index 2d4e73b..3890f4f 100644 --- a/drivers/media/platform/vivi.c +++ b/drivers/media/platform/vivi.c @@ -70,10 +70,6 @@ static unsigned debug; module_param(debug, uint, 0644); MODULE_PARM_DESC(debug, "activates debug info"); -static unsigned int vid_limit = 16; -module_param(vid_limit, uint, 0644); -MODULE_PARM_DESC(vid_limit, "capture memory limit in megabytes"); - /* Global font descriptor */ static const u8 *font8x16; @@ -191,7 +187,6 @@ struct vivi_buffer { /* common v4l buffer stuff -- must be first */ struct vb2_buffer vb; struct list_head list; - const struct vivi_fmt *fmt; }; struct vivi_dmaqueue { @@ -254,7 +249,7 @@ struct vivi_dev { struct v4l2_fract timeperframe; unsigned int width, height; struct vb2_queue vb_vidq; - unsigned int field_count; + unsigned int seq_count; u8 bars[9][3]; u8 line[MAX_WIDTH * 8] __attribute__((__aligned__(4))); @@ -675,8 +670,7 @@ static void vivi_fillbuff(struct vivi_dev *dev, struct vivi_buffer *buf) dev->mv_count += 2; buf->vb.v4l2_buf.field = V4L2_FIELD_INTERLACED; - dev->field_count++; - buf->vb.v4l2_buf.sequence = dev->field_count >> 1; + buf->vb.v4l2_buf.sequence = dev->seq_count++; v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); } @@ -818,19 +812,15 @@ static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, struct vivi_dev *dev = vb2_get_drv_priv(vq); unsigned long size; - if (fmt) + size = dev->width * dev->height * dev->pixelsize; + if (fmt) { + if (fmt->fmt.pix.sizeimage < size) + return -EINVAL; size = fmt->fmt.pix.sizeimage; - else - size = dev->width * dev->height * dev->pixelsize; - - if (size == 0) - return -EINVAL; - - if (0 == *nbuffers) - *nbuffers = 32; - - while (size * *nbuffers > vid_limit * 1024 * 1024) - (*nbuffers)--; + /* check against insane over 8K resolution buffers */ + if (size > 7680 * 4320 * dev->pixelsize) + return -EINVAL; + } *nplanes = 1; @@ -876,8 +866,6 @@ static int buffer_prepare(struct vb2_buffer *vb) vb2_set_plane_payload(&buf->vb, 0, size); - buf->fmt = dev->fmt; - precalculate_bars(dev); precalculate_line(dev); @@ -901,8 +889,20 @@ static void buffer_queue(struct vb2_buffer *vb) static int start_streaming(struct vb2_queue *vq, unsigned int count) { struct vivi_dev *dev = vb2_get_drv_priv(vq); + int err; + dprintk(dev, 1, "%s\n", __func__); - return vivi_start_generating(dev); + dev->seq_count = 0; + err = vivi_start_generating(dev); + if (err) { + struct vivi_buffer *buf, *tmp; + + list_for_each_entry_safe(buf, tmp, &dev->vidq.active, list) { + list_del(&buf->list); + vb2_buffer_done(&buf->vb, VB2_BUF_STATE_QUEUED); + } + } + return err; } /* abort streaming and wait for last buffer */ @@ -1121,7 +1121,11 @@ static int vidioc_enum_frameintervals(struct file *file, void *priv, if (!fmt) return -EINVAL; - /* regarding width & height - we support any */ + /* check for valid width/height */ + if (fival->width < 48 || fival->width > MAX_WIDTH || (fival->width & 3)) + return -EINVAL; + if (fival->height < 32 || fival->height > MAX_HEIGHT) + return -EINVAL; fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS; @@ -1439,7 +1443,7 @@ static int __init vivi_create_instance(int inst) q->buf_struct_size = sizeof(struct vivi_buffer); q->ops = &vivi_video_qops; q->mem_ops = &vb2_vmalloc_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ret = vb2_queue_init(q); if (ret) diff --git a/drivers/media/platform/vsp1/vsp1.h b/drivers/media/platform/vsp1/vsp1.h index 94d1b02..0313210 100644 --- a/drivers/media/platform/vsp1/vsp1.h +++ b/drivers/media/platform/vsp1/vsp1.h @@ -1,7 +1,7 @@ /* * vsp1.h -- R-Car VSP1 Driver * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c index 0df0a99..2f74f0e 100644 --- a/drivers/media/platform/vsp1/vsp1_drv.c +++ b/drivers/media/platform/vsp1/vsp1_drv.c @@ -1,7 +1,7 @@ /* * vsp1_drv.c -- R-Car VSP1 Driver * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_entity.c b/drivers/media/platform/vsp1/vsp1_entity.c index 0226e47..3fc9e42 100644 --- a/drivers/media/platform/vsp1/vsp1_entity.c +++ b/drivers/media/platform/vsp1/vsp1_entity.c @@ -1,7 +1,7 @@ /* * vsp1_entity.c -- R-Car VSP1 Base Entity * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_entity.h b/drivers/media/platform/vsp1/vsp1_entity.h index e152798..f6fd698 100644 --- a/drivers/media/platform/vsp1/vsp1_entity.h +++ b/drivers/media/platform/vsp1/vsp1_entity.h @@ -1,7 +1,7 @@ /* * vsp1_entity.h -- R-Car VSP1 Base Entity * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_lif.c b/drivers/media/platform/vsp1/vsp1_lif.c index 74a32e6..135a789 100644 --- a/drivers/media/platform/vsp1/vsp1_lif.c +++ b/drivers/media/platform/vsp1/vsp1_lif.c @@ -1,7 +1,7 @@ /* * vsp1_lif.c -- R-Car VSP1 LCD Controller Interface * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_lif.h b/drivers/media/platform/vsp1/vsp1_lif.h index 89b93af..7b35879 100644 --- a/drivers/media/platform/vsp1/vsp1_lif.h +++ b/drivers/media/platform/vsp1/vsp1_lif.h @@ -1,7 +1,7 @@ /* * vsp1_lif.h -- R-Car VSP1 LCD Controller Interface * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_rpf.c b/drivers/media/platform/vsp1/vsp1_rpf.c index bce2be5..2b04d0f 100644 --- a/drivers/media/platform/vsp1/vsp1_rpf.c +++ b/drivers/media/platform/vsp1/vsp1_rpf.c @@ -1,7 +1,7 @@ /* * vsp1_rpf.c -- R-Car VSP1 Read Pixel Formatter * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_rwpf.c b/drivers/media/platform/vsp1/vsp1_rwpf.c index 782f770..ec3dab6 100644 --- a/drivers/media/platform/vsp1/vsp1_rwpf.c +++ b/drivers/media/platform/vsp1/vsp1_rwpf.c @@ -1,7 +1,7 @@ /* * vsp1_rwpf.c -- R-Car VSP1 Read and Write Pixel Formatters * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_rwpf.h b/drivers/media/platform/vsp1/vsp1_rwpf.h index 6cbdb54..5c5ee81 100644 --- a/drivers/media/platform/vsp1/vsp1_rwpf.h +++ b/drivers/media/platform/vsp1/vsp1_rwpf.h @@ -1,7 +1,7 @@ /* * vsp1_rwpf.h -- R-Car VSP1 Read and Write Pixel Formatters * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_uds.c b/drivers/media/platform/vsp1/vsp1_uds.c index 0e50b37..622342a 100644 --- a/drivers/media/platform/vsp1/vsp1_uds.c +++ b/drivers/media/platform/vsp1/vsp1_uds.c @@ -1,7 +1,7 @@ /* * vsp1_uds.c -- R-Car VSP1 Up and Down Scaler * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_uds.h b/drivers/media/platform/vsp1/vsp1_uds.h index 972a285..479d12d 100644 --- a/drivers/media/platform/vsp1/vsp1_uds.h +++ b/drivers/media/platform/vsp1/vsp1_uds.h @@ -1,7 +1,7 @@ /* * vsp1_uds.h -- R-Car VSP1 Up and Down Scaler * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c index b4687a8..b48f135 100644 --- a/drivers/media/platform/vsp1/vsp1_video.c +++ b/drivers/media/platform/vsp1/vsp1_video.c @@ -1,7 +1,7 @@ /* * vsp1_video.c -- R-Car VSP1 Video Node * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * @@ -1051,7 +1051,7 @@ int vsp1_video_init(struct vsp1_video *video, struct vsp1_entity *rwpf) video->queue.buf_struct_size = sizeof(struct vsp1_video_buffer); video->queue.ops = &vsp1_video_queue_qops; video->queue.mem_ops = &vb2_dma_contig_memops; - video->queue.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY; + video->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(&video->queue); if (ret < 0) { dev_err(video->vsp1->dev, "failed to initialize vb2 queue\n"); diff --git a/drivers/media/platform/vsp1/vsp1_video.h b/drivers/media/platform/vsp1/vsp1_video.h index d8612a3..53e4b37 100644 --- a/drivers/media/platform/vsp1/vsp1_video.h +++ b/drivers/media/platform/vsp1/vsp1_video.h @@ -1,7 +1,7 @@ /* * vsp1_video.h -- R-Car VSP1 Video Node * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/platform/vsp1/vsp1_wpf.c b/drivers/media/platform/vsp1/vsp1_wpf.c index 7baed81..11a61c6 100644 --- a/drivers/media/platform/vsp1/vsp1_wpf.c +++ b/drivers/media/platform/vsp1/vsp1_wpf.c @@ -1,7 +1,7 @@ /* * vsp1_wpf.c -- R-Car VSP1 Write Pixel Formatter * - * Copyright (C) 2013 Renesas Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * diff --git a/drivers/media/radio/radio-cadet.c b/drivers/media/radio/radio-cadet.c index 545c04c..d719e59 100644 --- a/drivers/media/radio/radio-cadet.c +++ b/drivers/media/radio/radio-cadet.c @@ -270,6 +270,16 @@ reset_rds: outb(inb(dev->io + 1) & 0x7f, dev->io + 1); } +static bool cadet_has_rds_data(struct cadet *dev) +{ + bool result; + + mutex_lock(&dev->lock); + result = dev->rdsin != dev->rdsout; + mutex_unlock(&dev->lock); + return result; +} + static void cadet_handler(unsigned long data) { @@ -279,13 +289,12 @@ static void cadet_handler(unsigned long data) if (mutex_trylock(&dev->lock)) { outb(0x3, dev->io); /* Select RDS Decoder Control */ if ((inb(dev->io + 1) & 0x20) != 0) - printk(KERN_CRIT "cadet: RDS fifo overflow\n"); + pr_err("cadet: RDS fifo overflow\n"); outb(0x80, dev->io); /* Select RDS fifo */ + while ((inb(dev->io) & 0x80) != 0) { dev->rdsbuf[dev->rdsin] = inb(dev->io + 1); - if (dev->rdsin + 1 == dev->rdsout) - printk(KERN_WARNING "cadet: RDS buffer overflow\n"); - else + if (dev->rdsin + 1 != dev->rdsout) dev->rdsin++; } mutex_unlock(&dev->lock); @@ -294,7 +303,7 @@ static void cadet_handler(unsigned long data) /* * Service pending read */ - if (dev->rdsin != dev->rdsout) + if (cadet_has_rds_data(dev)) wake_up_interruptible(&dev->read_queue); /* @@ -327,22 +336,21 @@ static ssize_t cadet_read(struct file *file, char __user *data, size_t count, lo mutex_lock(&dev->lock); if (dev->rdsstat == 0) cadet_start_rds(dev); - if (dev->rdsin == dev->rdsout) { - if (file->f_flags & O_NONBLOCK) { - i = -EWOULDBLOCK; - goto unlock; - } - mutex_unlock(&dev->lock); - interruptible_sleep_on(&dev->read_queue); - mutex_lock(&dev->lock); - } + mutex_unlock(&dev->lock); + + if (!cadet_has_rds_data(dev) && (file->f_flags & O_NONBLOCK)) + return -EWOULDBLOCK; + i = wait_event_interruptible(dev->read_queue, cadet_has_rds_data(dev)); + if (i) + return i; + + mutex_lock(&dev->lock); while (i < count && dev->rdsin != dev->rdsout) readbuf[i++] = dev->rdsbuf[dev->rdsout++]; + mutex_unlock(&dev->lock); if (i && copy_to_user(data, readbuf, i)) - i = -EFAULT; -unlock: - mutex_unlock(&dev->lock); + return -EFAULT; return i; } @@ -352,7 +360,7 @@ static int vidioc_querycap(struct file *file, void *priv, { strlcpy(v->driver, "ADS Cadet", sizeof(v->driver)); strlcpy(v->card, "ADS Cadet", sizeof(v->card)); - strlcpy(v->bus_info, "ISA", sizeof(v->bus_info)); + strlcpy(v->bus_info, "ISA:radio-cadet", sizeof(v->bus_info)); v->device_caps = V4L2_CAP_TUNER | V4L2_CAP_RADIO | V4L2_CAP_READWRITE | V4L2_CAP_RDS_CAPTURE; v->capabilities = v->device_caps | V4L2_CAP_DEVICE_CAPS; @@ -491,7 +499,7 @@ static unsigned int cadet_poll(struct file *file, struct poll_table_struct *wait cadet_start_rds(dev); mutex_unlock(&dev->lock); } - if (dev->rdsin != dev->rdsout) + if (cadet_has_rds_data(dev)) res |= POLLIN | POLLRDNORM; return res; } diff --git a/drivers/media/radio/radio-keene.c b/drivers/media/radio/radio-keene.c index fa39640..3d12782 100644 --- a/drivers/media/radio/radio-keene.c +++ b/drivers/media/radio/radio-keene.c @@ -416,22 +416,5 @@ static struct usb_driver usb_keene_driver = { .reset_resume = usb_keene_resume, }; -static int __init keene_init(void) -{ - int retval = usb_register(&usb_keene_driver); - - if (retval) - pr_err(KBUILD_MODNAME - ": usb_register failed. Error number %d\n", retval); - - return retval; -} - -static void __exit keene_exit(void) -{ - usb_deregister(&usb_keene_driver); -} - -module_init(keene_init); -module_exit(keene_exit); +module_usb_driver(usb_keene_driver); diff --git a/drivers/media/radio/si4713/Kconfig b/drivers/media/radio/si4713/Kconfig index a7c3ba8..9c8b887 100644 --- a/drivers/media/radio/si4713/Kconfig +++ b/drivers/media/radio/si4713/Kconfig @@ -1,7 +1,7 @@ config USB_SI4713 tristate "Silicon Labs Si4713 FM Radio Transmitter support with USB" - depends on USB && RADIO_SI4713 - select SI4713 + depends on USB && I2C && RADIO_SI4713 + select I2C_SI4713 ---help--- This is a driver for USB devices with the Silicon Labs SI4713 chip. Currently these devices are known to work. @@ -16,7 +16,7 @@ config USB_SI4713 config PLATFORM_SI4713 tristate "Silicon Labs Si4713 FM Radio Transmitter support with I2C" depends on I2C && RADIO_SI4713 - select SI4713 + select I2C_SI4713 ---help--- This is a driver for I2C devices with the Silicon Labs SI4713 chip. diff --git a/drivers/media/radio/si4713/radio-usb-si4713.c b/drivers/media/radio/si4713/radio-usb-si4713.c index 779855b..86502b2 100644 --- a/drivers/media/radio/si4713/radio-usb-si4713.c +++ b/drivers/media/radio/si4713/radio-usb-si4713.c @@ -223,7 +223,7 @@ struct si4713_start_seq_table { * (0x03): Get serial number of the board (Response : CB000-00-00) * (0x06, 0x03, 0x03, 0x08, 0x01, 0x0f) : Get Component revision */ -static struct si4713_start_seq_table start_seq[] = { +static const struct si4713_start_seq_table start_seq[] = { { 1, { 0x03 } }, { 2, { 0x32, 0x7f } }, @@ -261,7 +261,7 @@ static int si4713_start_seq(struct si4713_usb_device *radio) for (i = 0; i < ARRAY_SIZE(start_seq); i++) { int len = start_seq[i].len; - u8 *payload = start_seq[i].payload; + const u8 *payload = start_seq[i].payload; memcpy(radio->buffer + 1, payload, len); memset(radio->buffer + len + 1, 0, BUFFER_LENGTH - 1 - len); diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig index 904f113..8fbd377 100644 --- a/drivers/media/rc/Kconfig +++ b/drivers/media/rc/Kconfig @@ -106,6 +106,15 @@ config IR_SANYO_DECODER uses the Sanyo protocol (Sanyo, Aiwa, Chinon remotes), and you need software decoding support. +config IR_SHARP_DECODER + tristate "Enable IR raw decoder for the Sharp protocol" + depends on RC_CORE + default y + + ---help--- + Enable this option if you have an infrared remote control which + uses the Sharp protocol, and you need software decoding support. + config IR_MCE_KBD_DECODER tristate "Enable IR raw decoder for the MCE keyboard/mouse protocol" depends on RC_CORE @@ -300,6 +309,8 @@ config IR_RX51 The driver uses omap DM timers for generating the carrier wave and pulses. +source "drivers/media/rc/img-ir/Kconfig" + config RC_LOOPBACK tristate "Remote Control Loopback Driver" depends on RC_CORE diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile index f4eb32c..f8b54ff 100644 --- a/drivers/media/rc/Makefile +++ b/drivers/media/rc/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_IR_JVC_DECODER) += ir-jvc-decoder.o obj-$(CONFIG_IR_SONY_DECODER) += ir-sony-decoder.o obj-$(CONFIG_IR_RC5_SZ_DECODER) += ir-rc5-sz-decoder.o obj-$(CONFIG_IR_SANYO_DECODER) += ir-sanyo-decoder.o +obj-$(CONFIG_IR_SHARP_DECODER) += ir-sharp-decoder.o obj-$(CONFIG_IR_MCE_KBD_DECODER) += ir-mce_kbd-decoder.o obj-$(CONFIG_IR_LIRC_CODEC) += ir-lirc-codec.o @@ -31,3 +32,4 @@ obj-$(CONFIG_IR_GPIO_CIR) += gpio-ir-recv.o obj-$(CONFIG_IR_IGUANA) += iguanair.o obj-$(CONFIG_IR_TTUSBIR) += ttusbir.o obj-$(CONFIG_RC_ST) += st_rc.o +obj-$(CONFIG_IR_IMG) += img-ir/ diff --git a/drivers/media/rc/ati_remote.c b/drivers/media/rc/ati_remote.c index 4d6a63f..2df7c55 100644 --- a/drivers/media/rc/ati_remote.c +++ b/drivers/media/rc/ati_remote.c @@ -784,7 +784,7 @@ static void ati_remote_rc_init(struct ati_remote *ati_remote) rdev->priv = ati_remote; rdev->driver_type = RC_DRIVER_SCANCODE; - rdev->allowed_protos = RC_BIT_OTHER; + rc_set_allowed_protocols(rdev, RC_BIT_OTHER); rdev->driver_name = "ati_remote"; rdev->open = ati_remote_rc_open; diff --git a/drivers/media/rc/ene_ir.c b/drivers/media/rc/ene_ir.c index c1444f8..fc9d23f 100644 --- a/drivers/media/rc/ene_ir.c +++ b/drivers/media/rc/ene_ir.c @@ -1059,7 +1059,7 @@ static int ene_probe(struct pnp_dev *pnp_dev, const struct pnp_device_id *id) learning_mode_force = false; rdev->driver_type = RC_DRIVER_IR_RAW; - rdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rdev, RC_BIT_ALL); rdev->priv = dev; rdev->open = ene_open; rdev->close = ene_close; diff --git a/drivers/media/rc/fintek-cir.c b/drivers/media/rc/fintek-cir.c index d6fa441..46b66e5 100644 --- a/drivers/media/rc/fintek-cir.c +++ b/drivers/media/rc/fintek-cir.c @@ -541,7 +541,7 @@ static int fintek_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id /* Set up the rc device */ rdev->priv = fintek; rdev->driver_type = RC_DRIVER_IR_RAW; - rdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rdev, RC_BIT_ALL); rdev->open = fintek_open; rdev->close = fintek_close; rdev->input_name = FINTEK_DESCRIPTION; diff --git a/drivers/media/rc/gpio-ir-recv.c b/drivers/media/rc/gpio-ir-recv.c index 80c611c..29b5f89 100644 --- a/drivers/media/rc/gpio-ir-recv.c +++ b/drivers/media/rc/gpio-ir-recv.c @@ -145,9 +145,9 @@ static int gpio_ir_recv_probe(struct platform_device *pdev) rcdev->dev.parent = &pdev->dev; rcdev->driver_name = GPIO_IR_DRIVER_NAME; if (pdata->allowed_protos) - rcdev->allowed_protos = pdata->allowed_protos; + rc_set_allowed_protocols(rcdev, pdata->allowed_protos); else - rcdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rcdev, RC_BIT_ALL); rcdev->map_name = pdata->map_name ?: RC_MAP_EMPTY; gpio_dev->rcdev = rcdev; diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c index fdae05c..627ddfd 100644 --- a/drivers/media/rc/iguanair.c +++ b/drivers/media/rc/iguanair.c @@ -286,10 +286,10 @@ static int iguanair_receiver(struct iguanair *ir, bool enable) } /* - * The iguana ir creates the carrier by busy spinning after each pulse or - * space. This is counted in CPU cycles, with the CPU running at 24MHz. It is + * The iguanair creates the carrier by busy spinning after each half period. + * This is counted in CPU cycles, with the CPU running at 24MHz. It is * broken down into 7-cycles and 4-cyles delays, with a preference for - * 4-cycle delays. + * 4-cycle delays, minus the overhead of the loop itself (cycle_overhead). */ static int iguanair_set_tx_carrier(struct rc_dev *dev, uint32_t carrier) { @@ -316,7 +316,14 @@ static int iguanair_set_tx_carrier(struct rc_dev *dev, uint32_t carrier) sevens = (4 - cycles) & 3; fours = (cycles - sevens * 7) / 4; - /* magic happens here */ + /* + * The firmware interprets these values as a relative offset + * for a branch. Immediately following the branches, there + * 4 instructions of 7 cycles (2 bytes each) and 110 + * instructions of 4 cycles (1 byte each). A relative branch + * of 0 will execute all of them, branch further for less + * cycle burning. + */ ir->packet->busy7 = (4 - sevens) * 2; ir->packet->busy4 = 110 - fours; } @@ -357,20 +364,14 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) rc = -EINVAL; goto out; } - while (periods > 127) { - ir->packet->payload[size++] = 127 | space; - periods -= 127; + while (periods) { + unsigned p = min(periods, 127u); + ir->packet->payload[size++] = p | space; + periods -= p; } - - ir->packet->payload[size++] = periods | space; space ^= 0x80; } - if (count == 0) { - rc = -EINVAL; - goto out; - } - ir->packet->header.start = 0; ir->packet->header.direction = DIR_OUT; ir->packet->header.cmd = CMD_SEND; @@ -494,7 +495,7 @@ static int iguanair_probe(struct usb_interface *intf, usb_to_input_id(ir->udev, &rc->input_id); rc->dev.parent = &intf->dev; rc->driver_type = RC_DRIVER_IR_RAW; - rc->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rc, RC_BIT_ALL); rc->priv = ir; rc->open = iguanair_open; rc->close = iguanair_close; diff --git a/drivers/media/rc/img-ir/Kconfig b/drivers/media/rc/img-ir/Kconfig new file mode 100644 index 0000000..03ba9fc --- /dev/null +++ b/drivers/media/rc/img-ir/Kconfig @@ -0,0 +1,61 @@ +config IR_IMG + tristate "ImgTec IR Decoder" + depends on RC_CORE + select IR_IMG_HW if !IR_IMG_RAW + help + Say Y or M here if you want to use the ImgTec infrared decoder + functionality found in SoCs such as TZ1090. + +config IR_IMG_RAW + bool "Raw decoder" + depends on IR_IMG + help + Say Y here to enable the raw mode driver which passes raw IR signal + changes to the IR raw decoders for software decoding. This is much + less reliable (due to lack of timestamps) and consumes more + processing power than using hardware decode, but can be useful for + testing, debug, and to make more protocols available. + +config IR_IMG_HW + bool "Hardware decoder" + depends on IR_IMG + help + Say Y here to enable the hardware decode driver which decodes the IR + signals in hardware. This is more reliable, consumes less processing + power since only a single interrupt is received for each scancode, + and allows an IR scancode to be used as a wake event. + +config IR_IMG_NEC + bool "NEC protocol support" + depends on IR_IMG_HW + help + Say Y here to enable support for the NEC, extended NEC, and 32-bit + NEC protocols in the ImgTec infrared decoder block. + +config IR_IMG_JVC + bool "JVC protocol support" + depends on IR_IMG_HW + help + Say Y here to enable support for the JVC protocol in the ImgTec + infrared decoder block. + +config IR_IMG_SONY + bool "Sony protocol support" + depends on IR_IMG_HW + help + Say Y here to enable support for the Sony protocol in the ImgTec + infrared decoder block. + +config IR_IMG_SHARP + bool "Sharp protocol support" + depends on IR_IMG_HW + help + Say Y here to enable support for the Sharp protocol in the ImgTec + infrared decoder block. + +config IR_IMG_SANYO + bool "Sanyo protocol support" + depends on IR_IMG_HW + help + Say Y here to enable support for the Sanyo protocol (used by Sanyo, + Aiwa, Chinon remotes) in the ImgTec infrared decoder block. diff --git a/drivers/media/rc/img-ir/Makefile b/drivers/media/rc/img-ir/Makefile new file mode 100644 index 0000000..92a459d --- /dev/null +++ b/drivers/media/rc/img-ir/Makefile @@ -0,0 +1,11 @@ +img-ir-y := img-ir-core.o +img-ir-$(CONFIG_IR_IMG_RAW) += img-ir-raw.o +img-ir-$(CONFIG_IR_IMG_HW) += img-ir-hw.o +img-ir-$(CONFIG_IR_IMG_NEC) += img-ir-nec.o +img-ir-$(CONFIG_IR_IMG_JVC) += img-ir-jvc.o +img-ir-$(CONFIG_IR_IMG_SONY) += img-ir-sony.o +img-ir-$(CONFIG_IR_IMG_SHARP) += img-ir-sharp.o +img-ir-$(CONFIG_IR_IMG_SANYO) += img-ir-sanyo.o +img-ir-objs := $(img-ir-y) + +obj-$(CONFIG_IR_IMG) += img-ir.o diff --git a/drivers/media/rc/img-ir/img-ir-core.c b/drivers/media/rc/img-ir/img-ir-core.c new file mode 100644 index 0000000..6b78348 --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-core.c @@ -0,0 +1,176 @@ +/* + * ImgTec IR Decoder found in PowerDown Controller. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + * + * This contains core img-ir code for setting up the driver. The two interfaces + * (raw and hardware decode) are handled separately. + */ + +#include <linux/clk.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include "img-ir.h" + +static irqreturn_t img_ir_isr(int irq, void *dev_id) +{ + struct img_ir_priv *priv = dev_id; + u32 irq_status; + + spin_lock(&priv->lock); + /* we have to clear irqs before reading */ + irq_status = img_ir_read(priv, IMG_IR_IRQ_STATUS); + img_ir_write(priv, IMG_IR_IRQ_CLEAR, irq_status); + + /* don't handle valid data irqs if we're only interested in matches */ + irq_status &= img_ir_read(priv, IMG_IR_IRQ_ENABLE); + + /* hand off edge interrupts to raw decode handler */ + if (irq_status & IMG_IR_IRQ_EDGE && img_ir_raw_enabled(&priv->raw)) + img_ir_isr_raw(priv, irq_status); + + /* hand off hardware match interrupts to hardware decode handler */ + if (irq_status & (IMG_IR_IRQ_DATA_MATCH | + IMG_IR_IRQ_DATA_VALID | + IMG_IR_IRQ_DATA2_VALID) && + img_ir_hw_enabled(&priv->hw)) + img_ir_isr_hw(priv, irq_status); + + spin_unlock(&priv->lock); + return IRQ_HANDLED; +} + +static void img_ir_setup(struct img_ir_priv *priv) +{ + /* start off with interrupts disabled */ + img_ir_write(priv, IMG_IR_IRQ_ENABLE, 0); + + img_ir_setup_raw(priv); + img_ir_setup_hw(priv); + + if (!IS_ERR(priv->clk)) + clk_prepare_enable(priv->clk); +} + +static void img_ir_ident(struct img_ir_priv *priv) +{ + u32 core_rev = img_ir_read(priv, IMG_IR_CORE_REV); + + dev_info(priv->dev, + "IMG IR Decoder (%d.%d.%d.%d) probed successfully\n", + (core_rev & IMG_IR_DESIGNER) >> IMG_IR_DESIGNER_SHIFT, + (core_rev & IMG_IR_MAJOR_REV) >> IMG_IR_MAJOR_REV_SHIFT, + (core_rev & IMG_IR_MINOR_REV) >> IMG_IR_MINOR_REV_SHIFT, + (core_rev & IMG_IR_MAINT_REV) >> IMG_IR_MAINT_REV_SHIFT); + dev_info(priv->dev, "Modes:%s%s\n", + img_ir_hw_enabled(&priv->hw) ? " hardware" : "", + img_ir_raw_enabled(&priv->raw) ? " raw" : ""); +} + +static int img_ir_probe(struct platform_device *pdev) +{ + struct img_ir_priv *priv; + struct resource *res_regs; + int irq, error, error2; + + /* Get resources from platform device */ + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "cannot find IRQ resource\n"); + return irq; + } + + /* Private driver data */ + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + dev_err(&pdev->dev, "cannot allocate device data\n"); + return -ENOMEM; + } + platform_set_drvdata(pdev, priv); + priv->dev = &pdev->dev; + spin_lock_init(&priv->lock); + + /* Ioremap the registers */ + res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->reg_base = devm_ioremap_resource(&pdev->dev, res_regs); + if (IS_ERR(priv->reg_base)) + return PTR_ERR(priv->reg_base); + + /* Get core clock */ + priv->clk = devm_clk_get(&pdev->dev, "core"); + if (IS_ERR(priv->clk)) + dev_warn(&pdev->dev, "cannot get core clock resource\n"); + /* + * The driver doesn't need to know about the system ("sys") or power + * modulation ("mod") clocks yet + */ + + /* Set up raw & hw decoder */ + error = img_ir_probe_raw(priv); + error2 = img_ir_probe_hw(priv); + if (error && error2) + return (error == -ENODEV) ? error2 : error; + + /* Get the IRQ */ + priv->irq = irq; + error = request_irq(priv->irq, img_ir_isr, 0, "img-ir", priv); + if (error) { + dev_err(&pdev->dev, "cannot register IRQ %u\n", + priv->irq); + error = -EIO; + goto err_irq; + } + + img_ir_ident(priv); + img_ir_setup(priv); + + return 0; + +err_irq: + img_ir_remove_hw(priv); + img_ir_remove_raw(priv); + return error; +} + +static int img_ir_remove(struct platform_device *pdev) +{ + struct img_ir_priv *priv = platform_get_drvdata(pdev); + + free_irq(priv->irq, img_ir_isr); + img_ir_remove_hw(priv); + img_ir_remove_raw(priv); + + if (!IS_ERR(priv->clk)) + clk_disable_unprepare(priv->clk); + return 0; +} + +static SIMPLE_DEV_PM_OPS(img_ir_pmops, img_ir_suspend, img_ir_resume); + +static const struct of_device_id img_ir_match[] = { + { .compatible = "img,ir-rev1" }, + {} +}; +MODULE_DEVICE_TABLE(of, img_ir_match); + +static struct platform_driver img_ir_driver = { + .driver = { + .name = "img-ir", + .owner = THIS_MODULE, + .of_match_table = img_ir_match, + .pm = &img_ir_pmops, + }, + .probe = img_ir_probe, + .remove = img_ir_remove, +}; + +module_platform_driver(img_ir_driver); + +MODULE_AUTHOR("Imagination Technologies Ltd."); +MODULE_DESCRIPTION("ImgTec IR"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/rc/img-ir/img-ir-hw.c b/drivers/media/rc/img-ir/img-ir-hw.c new file mode 100644 index 0000000..579a52b --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-hw.c @@ -0,0 +1,1053 @@ +/* + * ImgTec IR Hardware Decoder found in PowerDown Controller. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + * + * This ties into the input subsystem using the RC-core. Protocol support is + * provided in separate modules which provide the parameters and scancode + * translation functions to set up the hardware decoder and interpret the + * resulting input. + */ + +#include <linux/bitops.h> +#include <linux/clk.h> +#include <linux/interrupt.h> +#include <linux/spinlock.h> +#include <linux/timer.h> +#include <media/rc-core.h> +#include "img-ir.h" + +/* Decoders lock (only modified to preprocess them) */ +static DEFINE_SPINLOCK(img_ir_decoders_lock); + +extern struct img_ir_decoder img_ir_nec; +extern struct img_ir_decoder img_ir_jvc; +extern struct img_ir_decoder img_ir_sony; +extern struct img_ir_decoder img_ir_sharp; +extern struct img_ir_decoder img_ir_sanyo; + +static bool img_ir_decoders_preprocessed; +static struct img_ir_decoder *img_ir_decoders[] = { +#ifdef CONFIG_IR_IMG_NEC + &img_ir_nec, +#endif +#ifdef CONFIG_IR_IMG_JVC + &img_ir_jvc, +#endif +#ifdef CONFIG_IR_IMG_SONY + &img_ir_sony, +#endif +#ifdef CONFIG_IR_IMG_SHARP + &img_ir_sharp, +#endif +#ifdef CONFIG_IR_IMG_SANYO + &img_ir_sanyo, +#endif + NULL +}; + +#define IMG_IR_F_FILTER BIT(RC_FILTER_NORMAL) /* enable filtering */ +#define IMG_IR_F_WAKE BIT(RC_FILTER_WAKEUP) /* enable waking */ + +/* code type quirks */ + +#define IMG_IR_QUIRK_CODE_BROKEN 0x1 /* Decode is broken */ +#define IMG_IR_QUIRK_CODE_LEN_INCR 0x2 /* Bit length needs increment */ + +/* functions for preprocessing timings, ensuring max is set */ + +static void img_ir_timing_preprocess(struct img_ir_timing_range *range, + unsigned int unit) +{ + if (range->max < range->min) + range->max = range->min; + if (unit) { + /* multiply by unit and convert to microseconds */ + range->min = (range->min*unit)/1000; + range->max = (range->max*unit + 999)/1000; /* round up */ + } +} + +static void img_ir_symbol_timing_preprocess(struct img_ir_symbol_timing *timing, + unsigned int unit) +{ + img_ir_timing_preprocess(&timing->pulse, unit); + img_ir_timing_preprocess(&timing->space, unit); +} + +static void img_ir_timings_preprocess(struct img_ir_timings *timings, + unsigned int unit) +{ + img_ir_symbol_timing_preprocess(&timings->ldr, unit); + img_ir_symbol_timing_preprocess(&timings->s00, unit); + img_ir_symbol_timing_preprocess(&timings->s01, unit); + img_ir_symbol_timing_preprocess(&timings->s10, unit); + img_ir_symbol_timing_preprocess(&timings->s11, unit); + /* default s10 and s11 to s00 and s01 if no leader */ + if (unit) + /* multiply by unit and convert to microseconds (round up) */ + timings->ft.ft_min = (timings->ft.ft_min*unit + 999)/1000; +} + +/* functions for filling empty fields with defaults */ + +static void img_ir_timing_defaults(struct img_ir_timing_range *range, + struct img_ir_timing_range *defaults) +{ + if (!range->min) + range->min = defaults->min; + if (!range->max) + range->max = defaults->max; +} + +static void img_ir_symbol_timing_defaults(struct img_ir_symbol_timing *timing, + struct img_ir_symbol_timing *defaults) +{ + img_ir_timing_defaults(&timing->pulse, &defaults->pulse); + img_ir_timing_defaults(&timing->space, &defaults->space); +} + +static void img_ir_timings_defaults(struct img_ir_timings *timings, + struct img_ir_timings *defaults) +{ + img_ir_symbol_timing_defaults(&timings->ldr, &defaults->ldr); + img_ir_symbol_timing_defaults(&timings->s00, &defaults->s00); + img_ir_symbol_timing_defaults(&timings->s01, &defaults->s01); + img_ir_symbol_timing_defaults(&timings->s10, &defaults->s10); + img_ir_symbol_timing_defaults(&timings->s11, &defaults->s11); + if (!timings->ft.ft_min) + timings->ft.ft_min = defaults->ft.ft_min; +} + +/* functions for converting timings to register values */ + +/** + * img_ir_control() - Convert control struct to control register value. + * @control: Control data + * + * Returns: The control register value equivalent of @control. + */ +static u32 img_ir_control(const struct img_ir_control *control) +{ + u32 ctrl = control->code_type << IMG_IR_CODETYPE_SHIFT; + if (control->decoden) + ctrl |= IMG_IR_DECODEN; + if (control->hdrtog) + ctrl |= IMG_IR_HDRTOG; + if (control->ldrdec) + ctrl |= IMG_IR_LDRDEC; + if (control->decodinpol) + ctrl |= IMG_IR_DECODINPOL; + if (control->bitorien) + ctrl |= IMG_IR_BITORIEN; + if (control->d1validsel) + ctrl |= IMG_IR_D1VALIDSEL; + if (control->bitinv) + ctrl |= IMG_IR_BITINV; + if (control->decodend2) + ctrl |= IMG_IR_DECODEND2; + if (control->bitoriend2) + ctrl |= IMG_IR_BITORIEND2; + if (control->bitinvd2) + ctrl |= IMG_IR_BITINVD2; + return ctrl; +} + +/** + * img_ir_timing_range_convert() - Convert microsecond range. + * @out: Output timing range in clock cycles with a shift. + * @in: Input timing range in microseconds. + * @tolerance: Tolerance as a fraction of 128 (roughly percent). + * @clock_hz: IR clock rate in Hz. + * @shift: Shift of output units. + * + * Converts min and max from microseconds to IR clock cycles, applies a + * tolerance, and shifts for the register, rounding in the right direction. + * Note that in and out can safely be the same object. + */ +static void img_ir_timing_range_convert(struct img_ir_timing_range *out, + const struct img_ir_timing_range *in, + unsigned int tolerance, + unsigned long clock_hz, + unsigned int shift) +{ + unsigned int min = in->min; + unsigned int max = in->max; + /* add a tolerance */ + min = min - (min*tolerance >> 7); + max = max + (max*tolerance >> 7); + /* convert from microseconds into clock cycles */ + min = min*clock_hz / 1000000; + max = (max*clock_hz + 999999) / 1000000; /* round up */ + /* apply shift and copy to output */ + out->min = min >> shift; + out->max = (max + ((1 << shift) - 1)) >> shift; /* round up */ +} + +/** + * img_ir_symbol_timing() - Convert symbol timing struct to register value. + * @timing: Symbol timing data + * @tolerance: Timing tolerance where 0-128 represents 0-100% + * @clock_hz: Frequency of source clock in Hz + * @pd_shift: Shift to apply to symbol period + * @w_shift: Shift to apply to symbol width + * + * Returns: Symbol timing register value based on arguments. + */ +static u32 img_ir_symbol_timing(const struct img_ir_symbol_timing *timing, + unsigned int tolerance, + unsigned long clock_hz, + unsigned int pd_shift, + unsigned int w_shift) +{ + struct img_ir_timing_range hw_pulse, hw_period; + /* we calculate period in hw_period, then convert in place */ + hw_period.min = timing->pulse.min + timing->space.min; + hw_period.max = timing->pulse.max + timing->space.max; + img_ir_timing_range_convert(&hw_period, &hw_period, + tolerance, clock_hz, pd_shift); + img_ir_timing_range_convert(&hw_pulse, &timing->pulse, + tolerance, clock_hz, w_shift); + /* construct register value */ + return (hw_period.max << IMG_IR_PD_MAX_SHIFT) | + (hw_period.min << IMG_IR_PD_MIN_SHIFT) | + (hw_pulse.max << IMG_IR_W_MAX_SHIFT) | + (hw_pulse.min << IMG_IR_W_MIN_SHIFT); +} + +/** + * img_ir_free_timing() - Convert free time timing struct to register value. + * @timing: Free symbol timing data + * @clock_hz: Source clock frequency in Hz + * + * Returns: Free symbol timing register value. + */ +static u32 img_ir_free_timing(const struct img_ir_free_timing *timing, + unsigned long clock_hz) +{ + unsigned int minlen, maxlen, ft_min; + /* minlen is only 5 bits, and round minlen to multiple of 2 */ + if (timing->minlen < 30) + minlen = timing->minlen & -2; + else + minlen = 30; + /* maxlen has maximum value of 48, and round maxlen to multiple of 2 */ + if (timing->maxlen < 48) + maxlen = (timing->maxlen + 1) & -2; + else + maxlen = 48; + /* convert and shift ft_min, rounding upwards */ + ft_min = (timing->ft_min*clock_hz + 999999) / 1000000; + ft_min = (ft_min + 7) >> 3; + /* construct register value */ + return (maxlen << IMG_IR_MAXLEN_SHIFT) | + (minlen << IMG_IR_MINLEN_SHIFT) | + (ft_min << IMG_IR_FT_MIN_SHIFT); +} + +/** + * img_ir_free_timing_dynamic() - Update free time register value. + * @st_ft: Static free time register value from img_ir_free_timing. + * @filter: Current filter which may additionally restrict min/max len. + * + * Returns: Updated free time register value based on the current filter. + */ +static u32 img_ir_free_timing_dynamic(u32 st_ft, struct img_ir_filter *filter) +{ + unsigned int minlen, maxlen, newminlen, newmaxlen; + + /* round minlen, maxlen to multiple of 2 */ + newminlen = filter->minlen & -2; + newmaxlen = (filter->maxlen + 1) & -2; + /* extract min/max len from register */ + minlen = (st_ft & IMG_IR_MINLEN) >> IMG_IR_MINLEN_SHIFT; + maxlen = (st_ft & IMG_IR_MAXLEN) >> IMG_IR_MAXLEN_SHIFT; + /* if the new values are more restrictive, update the register value */ + if (newminlen > minlen) { + st_ft &= ~IMG_IR_MINLEN; + st_ft |= newminlen << IMG_IR_MINLEN_SHIFT; + } + if (newmaxlen < maxlen) { + st_ft &= ~IMG_IR_MAXLEN; + st_ft |= newmaxlen << IMG_IR_MAXLEN_SHIFT; + } + return st_ft; +} + +/** + * img_ir_timings_convert() - Convert timings to register values + * @regs: Output timing register values + * @timings: Input timing data + * @tolerance: Timing tolerance where 0-128 represents 0-100% + * @clock_hz: Source clock frequency in Hz + */ +static void img_ir_timings_convert(struct img_ir_timing_regvals *regs, + const struct img_ir_timings *timings, + unsigned int tolerance, + unsigned int clock_hz) +{ + /* leader symbol timings are divided by 16 */ + regs->ldr = img_ir_symbol_timing(&timings->ldr, tolerance, clock_hz, + 4, 4); + /* other symbol timings, pd fields only are divided by 2 */ + regs->s00 = img_ir_symbol_timing(&timings->s00, tolerance, clock_hz, + 1, 0); + regs->s01 = img_ir_symbol_timing(&timings->s01, tolerance, clock_hz, + 1, 0); + regs->s10 = img_ir_symbol_timing(&timings->s10, tolerance, clock_hz, + 1, 0); + regs->s11 = img_ir_symbol_timing(&timings->s11, tolerance, clock_hz, + 1, 0); + regs->ft = img_ir_free_timing(&timings->ft, clock_hz); +} + +/** + * img_ir_decoder_preprocess() - Preprocess timings in decoder. + * @decoder: Decoder to be preprocessed. + * + * Ensures that the symbol timing ranges are valid with respect to ordering, and + * does some fixed conversion on them. + */ +static void img_ir_decoder_preprocess(struct img_ir_decoder *decoder) +{ + /* default tolerance */ + if (!decoder->tolerance) + decoder->tolerance = 10; /* percent */ + /* and convert tolerance to fraction out of 128 */ + decoder->tolerance = decoder->tolerance * 128 / 100; + + /* fill in implicit fields */ + img_ir_timings_preprocess(&decoder->timings, decoder->unit); + + /* do the same for repeat timings if applicable */ + if (decoder->repeat) { + img_ir_timings_preprocess(&decoder->rtimings, decoder->unit); + img_ir_timings_defaults(&decoder->rtimings, &decoder->timings); + } +} + +/** + * img_ir_decoder_convert() - Generate internal timings in decoder. + * @decoder: Decoder to be converted to internal timings. + * @timings: Timing register values. + * @clock_hz: IR clock rate in Hz. + * + * Fills out the repeat timings and timing register values for a specific clock + * rate. + */ +static void img_ir_decoder_convert(const struct img_ir_decoder *decoder, + struct img_ir_reg_timings *reg_timings, + unsigned int clock_hz) +{ + /* calculate control value */ + reg_timings->ctrl = img_ir_control(&decoder->control); + + /* fill in implicit fields and calculate register values */ + img_ir_timings_convert(®_timings->timings, &decoder->timings, + decoder->tolerance, clock_hz); + + /* do the same for repeat timings if applicable */ + if (decoder->repeat) + img_ir_timings_convert(®_timings->rtimings, + &decoder->rtimings, decoder->tolerance, + clock_hz); +} + +/** + * img_ir_write_timings() - Write timings to the hardware now + * @priv: IR private data + * @regs: Timing register values to write + * @type: RC filter type (RC_FILTER_*) + * + * Write timing register values @regs to the hardware, taking into account the + * current filter which may impose restrictions on the length of the expected + * data. + */ +static void img_ir_write_timings(struct img_ir_priv *priv, + struct img_ir_timing_regvals *regs, + enum rc_filter_type type) +{ + struct img_ir_priv_hw *hw = &priv->hw; + + /* filter may be more restrictive to minlen, maxlen */ + u32 ft = regs->ft; + if (hw->flags & BIT(type)) + ft = img_ir_free_timing_dynamic(regs->ft, &hw->filters[type]); + /* write to registers */ + img_ir_write(priv, IMG_IR_LEAD_SYMB_TIMING, regs->ldr); + img_ir_write(priv, IMG_IR_S00_SYMB_TIMING, regs->s00); + img_ir_write(priv, IMG_IR_S01_SYMB_TIMING, regs->s01); + img_ir_write(priv, IMG_IR_S10_SYMB_TIMING, regs->s10); + img_ir_write(priv, IMG_IR_S11_SYMB_TIMING, regs->s11); + img_ir_write(priv, IMG_IR_FREE_SYMB_TIMING, ft); + dev_dbg(priv->dev, "timings: ldr=%#x, s=[%#x, %#x, %#x, %#x], ft=%#x\n", + regs->ldr, regs->s00, regs->s01, regs->s10, regs->s11, ft); +} + +static void img_ir_write_filter(struct img_ir_priv *priv, + struct img_ir_filter *filter) +{ + if (filter) { + dev_dbg(priv->dev, "IR filter=%016llx & %016llx\n", + (unsigned long long)filter->data, + (unsigned long long)filter->mask); + img_ir_write(priv, IMG_IR_IRQ_MSG_DATA_LW, (u32)filter->data); + img_ir_write(priv, IMG_IR_IRQ_MSG_DATA_UP, (u32)(filter->data + >> 32)); + img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_LW, (u32)filter->mask); + img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_UP, (u32)(filter->mask + >> 32)); + } else { + dev_dbg(priv->dev, "IR clearing filter\n"); + img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_LW, 0); + img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_UP, 0); + } +} + +/* caller must have lock */ +static void _img_ir_set_filter(struct img_ir_priv *priv, + struct img_ir_filter *filter) +{ + struct img_ir_priv_hw *hw = &priv->hw; + u32 irq_en, irq_on; + + irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE); + if (filter) { + /* Only use the match interrupt */ + hw->filters[RC_FILTER_NORMAL] = *filter; + hw->flags |= IMG_IR_F_FILTER; + irq_on = IMG_IR_IRQ_DATA_MATCH; + irq_en &= ~(IMG_IR_IRQ_DATA_VALID | IMG_IR_IRQ_DATA2_VALID); + } else { + /* Only use the valid interrupt */ + hw->flags &= ~IMG_IR_F_FILTER; + irq_en &= ~IMG_IR_IRQ_DATA_MATCH; + irq_on = IMG_IR_IRQ_DATA_VALID | IMG_IR_IRQ_DATA2_VALID; + } + irq_en |= irq_on; + + img_ir_write_filter(priv, filter); + /* clear any interrupts we're enabling so we don't handle old ones */ + img_ir_write(priv, IMG_IR_IRQ_CLEAR, irq_on); + img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en); +} + +/* caller must have lock */ +static void _img_ir_set_wake_filter(struct img_ir_priv *priv, + struct img_ir_filter *filter) +{ + struct img_ir_priv_hw *hw = &priv->hw; + if (filter) { + /* Enable wake, and copy filter for later */ + hw->filters[RC_FILTER_WAKEUP] = *filter; + hw->flags |= IMG_IR_F_WAKE; + } else { + /* Disable wake */ + hw->flags &= ~IMG_IR_F_WAKE; + } +} + +/* Callback for setting scancode filter */ +static int img_ir_set_filter(struct rc_dev *dev, enum rc_filter_type type, + struct rc_scancode_filter *sc_filter) +{ + struct img_ir_priv *priv = dev->priv; + struct img_ir_priv_hw *hw = &priv->hw; + struct img_ir_filter filter, *filter_ptr = &filter; + int ret = 0; + + dev_dbg(priv->dev, "IR scancode %sfilter=%08x & %08x\n", + type == RC_FILTER_WAKEUP ? "wake " : "", + sc_filter->data, + sc_filter->mask); + + spin_lock_irq(&priv->lock); + + /* filtering can always be disabled */ + if (!sc_filter->mask) { + filter_ptr = NULL; + goto set_unlock; + } + + /* current decoder must support scancode filtering */ + if (!hw->decoder || !hw->decoder->filter) { + ret = -EINVAL; + goto unlock; + } + + /* convert scancode filter to raw filter */ + filter.minlen = 0; + filter.maxlen = ~0; + ret = hw->decoder->filter(sc_filter, &filter, hw->enabled_protocols); + if (ret) + goto unlock; + dev_dbg(priv->dev, "IR raw %sfilter=%016llx & %016llx\n", + type == RC_FILTER_WAKEUP ? "wake " : "", + (unsigned long long)filter.data, + (unsigned long long)filter.mask); + +set_unlock: + /* apply raw filters */ + switch (type) { + case RC_FILTER_NORMAL: + _img_ir_set_filter(priv, filter_ptr); + break; + case RC_FILTER_WAKEUP: + _img_ir_set_wake_filter(priv, filter_ptr); + break; + default: + ret = -EINVAL; + } + +unlock: + spin_unlock_irq(&priv->lock); + return ret; +} + +/** + * img_ir_set_decoder() - Set the current decoder. + * @priv: IR private data. + * @decoder: Decoder to use with immediate effect. + * @proto: Protocol bitmap (or 0 to use decoder->type). + */ +static void img_ir_set_decoder(struct img_ir_priv *priv, + const struct img_ir_decoder *decoder, + u64 proto) +{ + struct img_ir_priv_hw *hw = &priv->hw; + struct rc_dev *rdev = hw->rdev; + u32 ir_status, irq_en; + spin_lock_irq(&priv->lock); + + /* switch off and disable interrupts */ + img_ir_write(priv, IMG_IR_CONTROL, 0); + irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE); + img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en & IMG_IR_IRQ_EDGE); + img_ir_write(priv, IMG_IR_IRQ_CLEAR, IMG_IR_IRQ_ALL & ~IMG_IR_IRQ_EDGE); + + /* ack any data already detected */ + ir_status = img_ir_read(priv, IMG_IR_STATUS); + if (ir_status & (IMG_IR_RXDVAL | IMG_IR_RXDVALD2)) { + ir_status &= ~(IMG_IR_RXDVAL | IMG_IR_RXDVALD2); + img_ir_write(priv, IMG_IR_STATUS, ir_status); + img_ir_read(priv, IMG_IR_DATA_LW); + img_ir_read(priv, IMG_IR_DATA_UP); + } + + /* stop the end timer and switch back to normal mode */ + del_timer_sync(&hw->end_timer); + hw->mode = IMG_IR_M_NORMAL; + + /* clear the wakeup scancode filter */ + rdev->scancode_filters[RC_FILTER_WAKEUP].data = 0; + rdev->scancode_filters[RC_FILTER_WAKEUP].mask = 0; + + /* clear raw filters */ + _img_ir_set_filter(priv, NULL); + _img_ir_set_wake_filter(priv, NULL); + + /* clear the enabled protocols */ + hw->enabled_protocols = 0; + + /* switch decoder */ + hw->decoder = decoder; + if (!decoder) + goto unlock; + + /* set the enabled protocols */ + if (!proto) + proto = decoder->type; + hw->enabled_protocols = proto; + + /* write the new timings */ + img_ir_decoder_convert(decoder, &hw->reg_timings, hw->clk_hz); + img_ir_write_timings(priv, &hw->reg_timings.timings, RC_FILTER_NORMAL); + + /* set up and enable */ + img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl); + + +unlock: + spin_unlock_irq(&priv->lock); +} + +/** + * img_ir_decoder_compatable() - Find whether a decoder will work with a device. + * @priv: IR private data. + * @dec: Decoder to check. + * + * Returns: true if @dec is compatible with the device @priv refers to. + */ +static bool img_ir_decoder_compatible(struct img_ir_priv *priv, + const struct img_ir_decoder *dec) +{ + unsigned int ct; + + /* don't accept decoders using code types which aren't supported */ + ct = dec->control.code_type; + if (priv->hw.ct_quirks[ct] & IMG_IR_QUIRK_CODE_BROKEN) + return false; + + return true; +} + +/** + * img_ir_allowed_protos() - Get allowed protocols from global decoder list. + * @priv: IR private data. + * + * Returns: Mask of protocols supported by the device @priv refers to. + */ +static u64 img_ir_allowed_protos(struct img_ir_priv *priv) +{ + u64 protos = 0; + struct img_ir_decoder **decp; + + for (decp = img_ir_decoders; *decp; ++decp) { + const struct img_ir_decoder *dec = *decp; + if (img_ir_decoder_compatible(priv, dec)) + protos |= dec->type; + } + return protos; +} + +/* Callback for changing protocol using sysfs */ +static int img_ir_change_protocol(struct rc_dev *dev, u64 *ir_type) +{ + struct img_ir_priv *priv = dev->priv; + struct img_ir_priv_hw *hw = &priv->hw; + struct rc_dev *rdev = hw->rdev; + struct img_ir_decoder **decp; + u64 wakeup_protocols; + + if (!*ir_type) { + /* disable all protocols */ + img_ir_set_decoder(priv, NULL, 0); + goto success; + } + for (decp = img_ir_decoders; *decp; ++decp) { + const struct img_ir_decoder *dec = *decp; + if (!img_ir_decoder_compatible(priv, dec)) + continue; + if (*ir_type & dec->type) { + *ir_type &= dec->type; + img_ir_set_decoder(priv, dec, *ir_type); + goto success; + } + } + return -EINVAL; + +success: + /* + * Only allow matching wakeup protocols for now, and only if filtering + * is supported. + */ + wakeup_protocols = *ir_type; + if (!hw->decoder || !hw->decoder->filter) + wakeup_protocols = 0; + rc_set_allowed_wakeup_protocols(rdev, wakeup_protocols); + rc_set_enabled_wakeup_protocols(rdev, wakeup_protocols); + return 0; +} + +/* Changes ir-core protocol device attribute */ +static void img_ir_set_protocol(struct img_ir_priv *priv, u64 proto) +{ + struct rc_dev *rdev = priv->hw.rdev; + + spin_lock_irq(&rdev->rc_map.lock); + rdev->rc_map.rc_type = __ffs64(proto); + spin_unlock_irq(&rdev->rc_map.lock); + + mutex_lock(&rdev->lock); + rc_set_enabled_protocols(rdev, proto); + rc_set_allowed_wakeup_protocols(rdev, proto); + rc_set_enabled_wakeup_protocols(rdev, proto); + mutex_unlock(&rdev->lock); +} + +/* Set up IR decoders */ +static void img_ir_init_decoders(void) +{ + struct img_ir_decoder **decp; + + spin_lock(&img_ir_decoders_lock); + if (!img_ir_decoders_preprocessed) { + for (decp = img_ir_decoders; *decp; ++decp) + img_ir_decoder_preprocess(*decp); + img_ir_decoders_preprocessed = true; + } + spin_unlock(&img_ir_decoders_lock); +} + +#ifdef CONFIG_PM_SLEEP +/** + * img_ir_enable_wake() - Switch to wake mode. + * @priv: IR private data. + * + * Returns: non-zero if the IR can wake the system. + */ +static int img_ir_enable_wake(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + int ret = 0; + + spin_lock_irq(&priv->lock); + if (hw->flags & IMG_IR_F_WAKE) { + /* interrupt only on a match */ + hw->suspend_irqen = img_ir_read(priv, IMG_IR_IRQ_ENABLE); + img_ir_write(priv, IMG_IR_IRQ_ENABLE, IMG_IR_IRQ_DATA_MATCH); + img_ir_write_filter(priv, &hw->filters[RC_FILTER_WAKEUP]); + img_ir_write_timings(priv, &hw->reg_timings.timings, + RC_FILTER_WAKEUP); + hw->mode = IMG_IR_M_WAKE; + ret = 1; + } + spin_unlock_irq(&priv->lock); + return ret; +} + +/** + * img_ir_disable_wake() - Switch out of wake mode. + * @priv: IR private data + * + * Returns: 1 if the hardware should be allowed to wake from a sleep state. + * 0 otherwise. + */ +static int img_ir_disable_wake(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + int ret = 0; + + spin_lock_irq(&priv->lock); + if (hw->flags & IMG_IR_F_WAKE) { + /* restore normal filtering */ + if (hw->flags & IMG_IR_F_FILTER) { + img_ir_write(priv, IMG_IR_IRQ_ENABLE, + (hw->suspend_irqen & IMG_IR_IRQ_EDGE) | + IMG_IR_IRQ_DATA_MATCH); + img_ir_write_filter(priv, + &hw->filters[RC_FILTER_NORMAL]); + } else { + img_ir_write(priv, IMG_IR_IRQ_ENABLE, + (hw->suspend_irqen & IMG_IR_IRQ_EDGE) | + IMG_IR_IRQ_DATA_VALID | + IMG_IR_IRQ_DATA2_VALID); + img_ir_write_filter(priv, NULL); + } + img_ir_write_timings(priv, &hw->reg_timings.timings, + RC_FILTER_NORMAL); + hw->mode = IMG_IR_M_NORMAL; + ret = 1; + } + spin_unlock_irq(&priv->lock); + return ret; +} +#endif /* CONFIG_PM_SLEEP */ + +/* lock must be held */ +static void img_ir_begin_repeat(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + if (hw->mode == IMG_IR_M_NORMAL) { + /* switch to repeat timings */ + img_ir_write(priv, IMG_IR_CONTROL, 0); + hw->mode = IMG_IR_M_REPEATING; + img_ir_write_timings(priv, &hw->reg_timings.rtimings, + RC_FILTER_NORMAL); + img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl); + } +} + +/* lock must be held */ +static void img_ir_end_repeat(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + if (hw->mode == IMG_IR_M_REPEATING) { + /* switch to normal timings */ + img_ir_write(priv, IMG_IR_CONTROL, 0); + hw->mode = IMG_IR_M_NORMAL; + img_ir_write_timings(priv, &hw->reg_timings.timings, + RC_FILTER_NORMAL); + img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl); + } +} + +/* lock must be held */ +static void img_ir_handle_data(struct img_ir_priv *priv, u32 len, u64 raw) +{ + struct img_ir_priv_hw *hw = &priv->hw; + const struct img_ir_decoder *dec = hw->decoder; + int ret = IMG_IR_SCANCODE; + int scancode; + if (dec->scancode) + ret = dec->scancode(len, raw, &scancode, hw->enabled_protocols); + else if (len >= 32) + scancode = (u32)raw; + else if (len < 32) + scancode = (u32)raw & ((1 << len)-1); + dev_dbg(priv->dev, "data (%u bits) = %#llx\n", + len, (unsigned long long)raw); + if (ret == IMG_IR_SCANCODE) { + dev_dbg(priv->dev, "decoded scan code %#x\n", scancode); + rc_keydown(hw->rdev, scancode, 0); + img_ir_end_repeat(priv); + } else if (ret == IMG_IR_REPEATCODE) { + if (hw->mode == IMG_IR_M_REPEATING) { + dev_dbg(priv->dev, "decoded repeat code\n"); + rc_repeat(hw->rdev); + } else { + dev_dbg(priv->dev, "decoded unexpected repeat code, ignoring\n"); + } + } else { + dev_dbg(priv->dev, "decode failed (%d)\n", ret); + return; + } + + + if (dec->repeat) { + unsigned long interval; + + img_ir_begin_repeat(priv); + + /* update timer, but allowing for 1/8th tolerance */ + interval = dec->repeat + (dec->repeat >> 3); + mod_timer(&hw->end_timer, + jiffies + msecs_to_jiffies(interval)); + } +} + +/* timer function to end waiting for repeat. */ +static void img_ir_end_timer(unsigned long arg) +{ + struct img_ir_priv *priv = (struct img_ir_priv *)arg; + + spin_lock_irq(&priv->lock); + img_ir_end_repeat(priv); + spin_unlock_irq(&priv->lock); +} + +#ifdef CONFIG_COMMON_CLK +static void img_ir_change_frequency(struct img_ir_priv *priv, + struct clk_notifier_data *change) +{ + struct img_ir_priv_hw *hw = &priv->hw; + + dev_dbg(priv->dev, "clk changed %lu HZ -> %lu HZ\n", + change->old_rate, change->new_rate); + + spin_lock_irq(&priv->lock); + if (hw->clk_hz == change->new_rate) + goto unlock; + hw->clk_hz = change->new_rate; + /* refresh current timings */ + if (hw->decoder) { + img_ir_decoder_convert(hw->decoder, &hw->reg_timings, + hw->clk_hz); + switch (hw->mode) { + case IMG_IR_M_NORMAL: + img_ir_write_timings(priv, &hw->reg_timings.timings, + RC_FILTER_NORMAL); + break; + case IMG_IR_M_REPEATING: + img_ir_write_timings(priv, &hw->reg_timings.rtimings, + RC_FILTER_NORMAL); + break; +#ifdef CONFIG_PM_SLEEP + case IMG_IR_M_WAKE: + img_ir_write_timings(priv, &hw->reg_timings.timings, + RC_FILTER_WAKEUP); + break; +#endif + } + } +unlock: + spin_unlock_irq(&priv->lock); +} + +static int img_ir_clk_notify(struct notifier_block *self, unsigned long action, + void *data) +{ + struct img_ir_priv *priv = container_of(self, struct img_ir_priv, + hw.clk_nb); + switch (action) { + case POST_RATE_CHANGE: + img_ir_change_frequency(priv, data); + break; + default: + break; + } + return NOTIFY_OK; +} +#endif /* CONFIG_COMMON_CLK */ + +/* called with priv->lock held */ +void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status) +{ + struct img_ir_priv_hw *hw = &priv->hw; + u32 ir_status, len, lw, up; + unsigned int ct; + + /* use the current decoder */ + if (!hw->decoder) + return; + + ir_status = img_ir_read(priv, IMG_IR_STATUS); + if (!(ir_status & (IMG_IR_RXDVAL | IMG_IR_RXDVALD2))) + return; + ir_status &= ~(IMG_IR_RXDVAL | IMG_IR_RXDVALD2); + img_ir_write(priv, IMG_IR_STATUS, ir_status); + + len = (ir_status & IMG_IR_RXDLEN) >> IMG_IR_RXDLEN_SHIFT; + /* some versions report wrong length for certain code types */ + ct = hw->decoder->control.code_type; + if (hw->ct_quirks[ct] & IMG_IR_QUIRK_CODE_LEN_INCR) + ++len; + + lw = img_ir_read(priv, IMG_IR_DATA_LW); + up = img_ir_read(priv, IMG_IR_DATA_UP); + img_ir_handle_data(priv, len, (u64)up << 32 | lw); +} + +void img_ir_setup_hw(struct img_ir_priv *priv) +{ + struct img_ir_decoder **decp; + + if (!priv->hw.rdev) + return; + + /* Use the first available decoder (or disable stuff if NULL) */ + for (decp = img_ir_decoders; *decp; ++decp) { + const struct img_ir_decoder *dec = *decp; + if (img_ir_decoder_compatible(priv, dec)) { + img_ir_set_protocol(priv, dec->type); + img_ir_set_decoder(priv, dec, 0); + return; + } + } + img_ir_set_decoder(priv, NULL, 0); +} + +/** + * img_ir_probe_hw_caps() - Probe capabilities of the hardware. + * @priv: IR private data. + */ +static void img_ir_probe_hw_caps(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + /* + * When a version of the block becomes available without these quirks, + * they'll have to depend on the core revision. + */ + hw->ct_quirks[IMG_IR_CODETYPE_PULSELEN] + |= IMG_IR_QUIRK_CODE_LEN_INCR; + hw->ct_quirks[IMG_IR_CODETYPE_BIPHASE] + |= IMG_IR_QUIRK_CODE_BROKEN; + hw->ct_quirks[IMG_IR_CODETYPE_2BITPULSEPOS] + |= IMG_IR_QUIRK_CODE_BROKEN; +} + +int img_ir_probe_hw(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + struct rc_dev *rdev; + int error; + + /* Ensure hardware decoders have been preprocessed */ + img_ir_init_decoders(); + + /* Probe hardware capabilities */ + img_ir_probe_hw_caps(priv); + + /* Set up the end timer */ + setup_timer(&hw->end_timer, img_ir_end_timer, (unsigned long)priv); + + /* Register a clock notifier */ + if (!IS_ERR(priv->clk)) { + hw->clk_hz = clk_get_rate(priv->clk); +#ifdef CONFIG_COMMON_CLK + hw->clk_nb.notifier_call = img_ir_clk_notify; + error = clk_notifier_register(priv->clk, &hw->clk_nb); + if (error) + dev_warn(priv->dev, + "failed to register clock notifier\n"); +#endif + } else { + hw->clk_hz = 32768; + } + + /* Allocate hardware decoder */ + hw->rdev = rdev = rc_allocate_device(); + if (!rdev) { + dev_err(priv->dev, "cannot allocate input device\n"); + error = -ENOMEM; + goto err_alloc_rc; + } + rdev->priv = priv; + rdev->map_name = RC_MAP_EMPTY; + rc_set_allowed_protocols(rdev, img_ir_allowed_protos(priv)); + rdev->input_name = "IMG Infrared Decoder"; + rdev->s_filter = img_ir_set_filter; + + /* Register hardware decoder */ + error = rc_register_device(rdev); + if (error) { + dev_err(priv->dev, "failed to register IR input device\n"); + goto err_register_rc; + } + + /* + * Set this after rc_register_device as no protocols have been + * registered yet. + */ + rdev->change_protocol = img_ir_change_protocol; + + device_init_wakeup(priv->dev, 1); + + return 0; + +err_register_rc: + img_ir_set_decoder(priv, NULL, 0); + hw->rdev = NULL; + rc_free_device(rdev); +err_alloc_rc: +#ifdef CONFIG_COMMON_CLK + if (!IS_ERR(priv->clk)) + clk_notifier_unregister(priv->clk, &hw->clk_nb); +#endif + return error; +} + +void img_ir_remove_hw(struct img_ir_priv *priv) +{ + struct img_ir_priv_hw *hw = &priv->hw; + struct rc_dev *rdev = hw->rdev; + if (!rdev) + return; + img_ir_set_decoder(priv, NULL, 0); + hw->rdev = NULL; + rc_unregister_device(rdev); +#ifdef CONFIG_COMMON_CLK + if (!IS_ERR(priv->clk)) + clk_notifier_unregister(priv->clk, &hw->clk_nb); +#endif +} + +#ifdef CONFIG_PM_SLEEP +int img_ir_suspend(struct device *dev) +{ + struct img_ir_priv *priv = dev_get_drvdata(dev); + + if (device_may_wakeup(dev) && img_ir_enable_wake(priv)) + enable_irq_wake(priv->irq); + return 0; +} + +int img_ir_resume(struct device *dev) +{ + struct img_ir_priv *priv = dev_get_drvdata(dev); + + if (device_may_wakeup(dev) && img_ir_disable_wake(priv)) + disable_irq_wake(priv->irq); + return 0; +} +#endif /* CONFIG_PM_SLEEP */ diff --git a/drivers/media/rc/img-ir/img-ir-hw.h b/drivers/media/rc/img-ir/img-ir-hw.h new file mode 100644 index 0000000..6c9a94a --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-hw.h @@ -0,0 +1,269 @@ +/* + * ImgTec IR Hardware Decoder found in PowerDown Controller. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + */ + +#ifndef _IMG_IR_HW_H_ +#define _IMG_IR_HW_H_ + +#include <linux/kernel.h> +#include <media/rc-core.h> + +/* constants */ + +#define IMG_IR_CODETYPE_PULSELEN 0x0 /* Sony */ +#define IMG_IR_CODETYPE_PULSEDIST 0x1 /* NEC, Toshiba, Micom, Sharp */ +#define IMG_IR_CODETYPE_BIPHASE 0x2 /* RC-5/6 */ +#define IMG_IR_CODETYPE_2BITPULSEPOS 0x3 /* RC-MM */ + + +/* Timing information */ + +/** + * struct img_ir_control - Decoder control settings + * @decoden: Primary decoder enable + * @code_type: Decode type (see IMG_IR_CODETYPE_*) + * @hdrtog: Detect header toggle symbol after leader symbol + * @ldrdec: Don't discard leader if maximum width reached + * @decodinpol: Decoder input polarity (1=active high) + * @bitorien: Bit orientation (1=MSB first) + * @d1validsel: Decoder 2 takes over if it detects valid data + * @bitinv: Bit inversion switch (1=don't invert) + * @decodend2: Secondary decoder enable (no leader symbol) + * @bitoriend2: Bit orientation (1=MSB first) + * @bitinvd2: Secondary decoder bit inversion switch (1=don't invert) + */ +struct img_ir_control { + unsigned decoden:1; + unsigned code_type:2; + unsigned hdrtog:1; + unsigned ldrdec:1; + unsigned decodinpol:1; + unsigned bitorien:1; + unsigned d1validsel:1; + unsigned bitinv:1; + unsigned decodend2:1; + unsigned bitoriend2:1; + unsigned bitinvd2:1; +}; + +/** + * struct img_ir_timing_range - range of timing values + * @min: Minimum timing value + * @max: Maximum timing value (if < @min, this will be set to @min during + * preprocessing step, so it is normally not explicitly initialised + * and is taken care of by the tolerance) + */ +struct img_ir_timing_range { + u16 min; + u16 max; +}; + +/** + * struct img_ir_symbol_timing - timing data for a symbol + * @pulse: Timing range for the length of the pulse in this symbol + * @space: Timing range for the length of the space in this symbol + */ +struct img_ir_symbol_timing { + struct img_ir_timing_range pulse; + struct img_ir_timing_range space; +}; + +/** + * struct img_ir_free_timing - timing data for free time symbol + * @minlen: Minimum number of bits of data + * @maxlen: Maximum number of bits of data + * @ft_min: Minimum free time after message + */ +struct img_ir_free_timing { + /* measured in bits */ + u8 minlen; + u8 maxlen; + u16 ft_min; +}; + +/** + * struct img_ir_timings - Timing values. + * @ldr: Leader symbol timing data + * @s00: Zero symbol timing data for primary decoder + * @s01: One symbol timing data for primary decoder + * @s10: Zero symbol timing data for secondary (no leader symbol) decoder + * @s11: One symbol timing data for secondary (no leader symbol) decoder + * @ft: Free time symbol timing data + */ +struct img_ir_timings { + struct img_ir_symbol_timing ldr, s00, s01, s10, s11; + struct img_ir_free_timing ft; +}; + +/** + * struct img_ir_filter - Filter IR events. + * @data: Data to match. + * @mask: Mask of bits to compare. + * @minlen: Additional minimum number of bits. + * @maxlen: Additional maximum number of bits. + */ +struct img_ir_filter { + u64 data; + u64 mask; + u8 minlen; + u8 maxlen; +}; + +/** + * struct img_ir_timing_regvals - Calculated timing register values. + * @ldr: Leader symbol timing register value + * @s00: Zero symbol timing register value for primary decoder + * @s01: One symbol timing register value for primary decoder + * @s10: Zero symbol timing register value for secondary decoder + * @s11: One symbol timing register value for secondary decoder + * @ft: Free time symbol timing register value + */ +struct img_ir_timing_regvals { + u32 ldr, s00, s01, s10, s11, ft; +}; + +#define IMG_IR_SCANCODE 0 /* new scancode */ +#define IMG_IR_REPEATCODE 1 /* repeat the previous code */ + +/** + * struct img_ir_decoder - Decoder settings for an IR protocol. + * @type: Protocol types bitmap. + * @tolerance: Timing tolerance as a percentage (default 10%). + * @unit: Unit of timings in nanoseconds (default 1 us). + * @timings: Primary timings + * @rtimings: Additional override timings while waiting for repeats. + * @repeat: Maximum repeat interval (always in milliseconds). + * @control: Control flags. + * + * @scancode: Pointer to function to convert the IR data into a scancode (it + * must be safe to execute in interrupt context). + * Returns IMG_IR_SCANCODE to emit new scancode. + * Returns IMG_IR_REPEATCODE to repeat previous code. + * Returns -errno (e.g. -EINVAL) on error. + * @filter: Pointer to function to convert scancode filter to raw hardware + * filter. The minlen and maxlen fields will have been initialised + * to the maximum range. + */ +struct img_ir_decoder { + /* core description */ + u64 type; + unsigned int tolerance; + unsigned int unit; + struct img_ir_timings timings; + struct img_ir_timings rtimings; + unsigned int repeat; + struct img_ir_control control; + + /* scancode logic */ + int (*scancode)(int len, u64 raw, int *scancode, u64 protocols); + int (*filter)(const struct rc_scancode_filter *in, + struct img_ir_filter *out, u64 protocols); +}; + +/** + * struct img_ir_reg_timings - Reg values for decoder timings at clock rate. + * @ctrl: Processed control register value. + * @timings: Processed primary timings. + * @rtimings: Processed repeat timings. + */ +struct img_ir_reg_timings { + u32 ctrl; + struct img_ir_timing_regvals timings; + struct img_ir_timing_regvals rtimings; +}; + +int img_ir_register_decoder(struct img_ir_decoder *dec); +void img_ir_unregister_decoder(struct img_ir_decoder *dec); + +struct img_ir_priv; + +#ifdef CONFIG_IR_IMG_HW + +enum img_ir_mode { + IMG_IR_M_NORMAL, + IMG_IR_M_REPEATING, +#ifdef CONFIG_PM_SLEEP + IMG_IR_M_WAKE, +#endif +}; + +/** + * struct img_ir_priv_hw - Private driver data for hardware decoder. + * @ct_quirks: Quirk bits for each code type. + * @rdev: Remote control device + * @clk_nb: Notifier block for clock notify events. + * @end_timer: Timer until repeat timeout. + * @decoder: Current decoder settings. + * @enabled_protocols: Currently enabled protocols. + * @clk_hz: Current core clock rate in Hz. + * @reg_timings: Timing reg values for decoder at clock rate. + * @flags: IMG_IR_F_*. + * @filters: HW filters (derived from scancode filters). + * @mode: Current decode mode. + * @suspend_irqen: Saved IRQ enable mask over suspend. + */ +struct img_ir_priv_hw { + unsigned int ct_quirks[4]; + struct rc_dev *rdev; + struct notifier_block clk_nb; + struct timer_list end_timer; + const struct img_ir_decoder *decoder; + u64 enabled_protocols; + unsigned long clk_hz; + struct img_ir_reg_timings reg_timings; + unsigned int flags; + struct img_ir_filter filters[RC_FILTER_MAX]; + + enum img_ir_mode mode; + u32 suspend_irqen; +}; + +static inline bool img_ir_hw_enabled(struct img_ir_priv_hw *hw) +{ + return hw->rdev; +}; + +void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status); +void img_ir_setup_hw(struct img_ir_priv *priv); +int img_ir_probe_hw(struct img_ir_priv *priv); +void img_ir_remove_hw(struct img_ir_priv *priv); + +#ifdef CONFIG_PM_SLEEP +int img_ir_suspend(struct device *dev); +int img_ir_resume(struct device *dev); +#else +#define img_ir_suspend NULL +#define img_ir_resume NULL +#endif + +#else + +struct img_ir_priv_hw { +}; + +static inline bool img_ir_hw_enabled(struct img_ir_priv_hw *hw) +{ + return false; +}; +static inline void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status) +{ +} +static inline void img_ir_setup_hw(struct img_ir_priv *priv) +{ +} +static inline int img_ir_probe_hw(struct img_ir_priv *priv) +{ + return -ENODEV; +} +static inline void img_ir_remove_hw(struct img_ir_priv *priv) +{ +} + +#define img_ir_suspend NULL +#define img_ir_resume NULL + +#endif /* CONFIG_IR_IMG_HW */ + +#endif /* _IMG_IR_HW_H_ */ diff --git a/drivers/media/rc/img-ir/img-ir-jvc.c b/drivers/media/rc/img-ir/img-ir-jvc.c new file mode 100644 index 0000000..10209d2 --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-jvc.c @@ -0,0 +1,81 @@ +/* + * ImgTec IR Decoder setup for JVC protocol. + * + * Copyright 2012-2014 Imagination Technologies Ltd. + */ + +#include "img-ir-hw.h" + +/* Convert JVC data to a scancode */ +static int img_ir_jvc_scancode(int len, u64 raw, int *scancode, u64 protocols) +{ + unsigned int cust, data; + + if (len != 16) + return -EINVAL; + + cust = (raw >> 0) & 0xff; + data = (raw >> 8) & 0xff; + + *scancode = cust << 8 | data; + return IMG_IR_SCANCODE; +} + +/* Convert JVC scancode to JVC data filter */ +static int img_ir_jvc_filter(const struct rc_scancode_filter *in, + struct img_ir_filter *out, u64 protocols) +{ + unsigned int cust, data; + unsigned int cust_m, data_m; + + cust = (in->data >> 8) & 0xff; + cust_m = (in->mask >> 8) & 0xff; + data = (in->data >> 0) & 0xff; + data_m = (in->mask >> 0) & 0xff; + + out->data = cust | data << 8; + out->mask = cust_m | data_m << 8; + + return 0; +} + +/* + * JVC decoder + * See also http://www.sbprojects.com/knowledge/ir/jvc.php + * http://support.jvc.com/consumer/support/documents/RemoteCodes.pdf + */ +struct img_ir_decoder img_ir_jvc = { + .type = RC_BIT_JVC, + .control = { + .decoden = 1, + .code_type = IMG_IR_CODETYPE_PULSEDIST, + }, + /* main timings */ + .unit = 527500, /* 527.5 us */ + .timings = { + /* leader symbol */ + .ldr = { + .pulse = { 16 /* 8.44 ms */ }, + .space = { 8 /* 4.22 ms */ }, + }, + /* 0 symbol */ + .s00 = { + .pulse = { 1 /* 527.5 us +-60 us */ }, + .space = { 1 /* 527.5 us */ }, + }, + /* 1 symbol */ + .s01 = { + .pulse = { 1 /* 527.5 us +-60 us */ }, + .space = { 3 /* 1.5825 ms +-40 us */ }, + }, + /* free time */ + .ft = { + .minlen = 16, + .maxlen = 16, + .ft_min = 10, /* 5.275 ms */ + }, + }, + /* scancode logic */ + .scancode = img_ir_jvc_scancode, + .filter = img_ir_jvc_filter, +}; diff --git a/drivers/media/rc/img-ir/img-ir-nec.c b/drivers/media/rc/img-ir/img-ir-nec.c new file mode 100644 index 0000000..e7a731bc --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-nec.c @@ -0,0 +1,148 @@ +/* + * ImgTec IR Decoder setup for NEC protocol. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + */ + +#include "img-ir-hw.h" + +/* Convert NEC data to a scancode */ +static int img_ir_nec_scancode(int len, u64 raw, int *scancode, u64 protocols) +{ + unsigned int addr, addr_inv, data, data_inv; + /* a repeat code has no data */ + if (!len) + return IMG_IR_REPEATCODE; + if (len != 32) + return -EINVAL; + /* raw encoding: ddDDaaAA */ + addr = (raw >> 0) & 0xff; + addr_inv = (raw >> 8) & 0xff; + data = (raw >> 16) & 0xff; + data_inv = (raw >> 24) & 0xff; + if ((data_inv ^ data) != 0xff) { + /* 32-bit NEC (used by Apple and TiVo remotes) */ + /* scan encoding: aaAAddDD */ + *scancode = addr_inv << 24 | + addr << 16 | + data_inv << 8 | + data; + } else if ((addr_inv ^ addr) != 0xff) { + /* Extended NEC */ + /* scan encoding: AAaaDD */ + *scancode = addr << 16 | + addr_inv << 8 | + data; + } else { + /* Normal NEC */ + /* scan encoding: AADD */ + *scancode = addr << 8 | + data; + } + return IMG_IR_SCANCODE; +} + +/* Convert NEC scancode to NEC data filter */ +static int img_ir_nec_filter(const struct rc_scancode_filter *in, + struct img_ir_filter *out, u64 protocols) +{ + unsigned int addr, addr_inv, data, data_inv; + unsigned int addr_m, addr_inv_m, data_m, data_inv_m; + + data = in->data & 0xff; + data_m = in->mask & 0xff; + + if ((in->data | in->mask) & 0xff000000) { + /* 32-bit NEC (used by Apple and TiVo remotes) */ + /* scan encoding: aaAAddDD */ + addr_inv = (in->data >> 24) & 0xff; + addr_inv_m = (in->mask >> 24) & 0xff; + addr = (in->data >> 16) & 0xff; + addr_m = (in->mask >> 16) & 0xff; + data_inv = (in->data >> 8) & 0xff; + data_inv_m = (in->mask >> 8) & 0xff; + } else if ((in->data | in->mask) & 0x00ff0000) { + /* Extended NEC */ + /* scan encoding AAaaDD */ + addr = (in->data >> 16) & 0xff; + addr_m = (in->mask >> 16) & 0xff; + addr_inv = (in->data >> 8) & 0xff; + addr_inv_m = (in->mask >> 8) & 0xff; + data_inv = data ^ 0xff; + data_inv_m = data_m; + } else { + /* Normal NEC */ + /* scan encoding: AADD */ + addr = (in->data >> 8) & 0xff; + addr_m = (in->mask >> 8) & 0xff; + addr_inv = addr ^ 0xff; + addr_inv_m = addr_m; + data_inv = data ^ 0xff; + data_inv_m = data_m; + } + + /* raw encoding: ddDDaaAA */ + out->data = data_inv << 24 | + data << 16 | + addr_inv << 8 | + addr; + out->mask = data_inv_m << 24 | + data_m << 16 | + addr_inv_m << 8 | + addr_m; + return 0; +} + +/* + * NEC decoder + * See also http://www.sbprojects.com/knowledge/ir/nec.php + * http://wiki.altium.com/display/ADOH/NEC+Infrared+Transmission+Protocol + */ +struct img_ir_decoder img_ir_nec = { + .type = RC_BIT_NEC, + .control = { + .decoden = 1, + .code_type = IMG_IR_CODETYPE_PULSEDIST, + }, + /* main timings */ + .unit = 562500, /* 562.5 us */ + .timings = { + /* leader symbol */ + .ldr = { + .pulse = { 16 /* 9ms */ }, + .space = { 8 /* 4.5ms */ }, + }, + /* 0 symbol */ + .s00 = { + .pulse = { 1 /* 562.5 us */ }, + .space = { 1 /* 562.5 us */ }, + }, + /* 1 symbol */ + .s01 = { + .pulse = { 1 /* 562.5 us */ }, + .space = { 3 /* 1687.5 us */ }, + }, + /* free time */ + .ft = { + .minlen = 32, + .maxlen = 32, + .ft_min = 10, /* 5.625 ms */ + }, + }, + /* repeat codes */ + .repeat = 108, /* 108 ms */ + .rtimings = { + /* leader symbol */ + .ldr = { + .space = { 4 /* 2.25 ms */ }, + }, + /* free time */ + .ft = { + .minlen = 0, /* repeat code has no data */ + .maxlen = 0, + }, + }, + /* scancode logic */ + .scancode = img_ir_nec_scancode, + .filter = img_ir_nec_filter, +}; diff --git a/drivers/media/rc/img-ir/img-ir-raw.c b/drivers/media/rc/img-ir/img-ir-raw.c new file mode 100644 index 0000000..cfb01d9 --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-raw.c @@ -0,0 +1,151 @@ +/* + * ImgTec IR Raw Decoder found in PowerDown Controller. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + * + * This ties into the input subsystem using the RC-core in raw mode. Raw IR + * signal edges are reported and decoded by generic software decoders. + */ + +#include <linux/spinlock.h> +#include <media/rc-core.h> +#include "img-ir.h" + +#define ECHO_TIMEOUT_MS 150 /* ms between echos */ + +/* must be called with priv->lock held */ +static void img_ir_refresh_raw(struct img_ir_priv *priv, u32 irq_status) +{ + struct img_ir_priv_raw *raw = &priv->raw; + struct rc_dev *rc_dev = priv->raw.rdev; + int multiple; + u32 ir_status; + + /* find whether both rise and fall was detected */ + multiple = ((irq_status & IMG_IR_IRQ_EDGE) == IMG_IR_IRQ_EDGE); + /* + * If so, we need to see if the level has actually changed. + * If it's just noise that we didn't have time to process, + * there's no point reporting it. + */ + ir_status = img_ir_read(priv, IMG_IR_STATUS) & IMG_IR_IRRXD; + if (multiple && ir_status == raw->last_status) + return; + raw->last_status = ir_status; + + /* report the edge to the IR raw decoders */ + if (ir_status) /* low */ + ir_raw_event_store_edge(rc_dev, IR_SPACE); + else /* high */ + ir_raw_event_store_edge(rc_dev, IR_PULSE); + ir_raw_event_handle(rc_dev); +} + +/* called with priv->lock held */ +void img_ir_isr_raw(struct img_ir_priv *priv, u32 irq_status) +{ + struct img_ir_priv_raw *raw = &priv->raw; + + /* check not removing */ + if (!raw->rdev) + return; + + img_ir_refresh_raw(priv, irq_status); + + /* start / push back the echo timer */ + mod_timer(&raw->timer, jiffies + msecs_to_jiffies(ECHO_TIMEOUT_MS)); +} + +/* + * Echo timer callback function. + * The raw decoders expect to get a final sample even if there are no edges, in + * order to be assured of the final space. If there are no edges for a certain + * time we use this timer to emit a final sample to satisfy them. + */ +static void img_ir_echo_timer(unsigned long arg) +{ + struct img_ir_priv *priv = (struct img_ir_priv *)arg; + + spin_lock_irq(&priv->lock); + + /* check not removing */ + if (priv->raw.rdev) + /* + * It's safe to pass irq_status=0 since it's only used to check + * for double edges. + */ + img_ir_refresh_raw(priv, 0); + + spin_unlock_irq(&priv->lock); +} + +void img_ir_setup_raw(struct img_ir_priv *priv) +{ + u32 irq_en; + + if (!priv->raw.rdev) + return; + + /* clear and enable edge interrupts */ + spin_lock_irq(&priv->lock); + irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE); + irq_en |= IMG_IR_IRQ_EDGE; + img_ir_write(priv, IMG_IR_IRQ_CLEAR, IMG_IR_IRQ_EDGE); + img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en); + spin_unlock_irq(&priv->lock); +} + +int img_ir_probe_raw(struct img_ir_priv *priv) +{ + struct img_ir_priv_raw *raw = &priv->raw; + struct rc_dev *rdev; + int error; + + /* Set up the echo timer */ + setup_timer(&raw->timer, img_ir_echo_timer, (unsigned long)priv); + + /* Allocate raw decoder */ + raw->rdev = rdev = rc_allocate_device(); + if (!rdev) { + dev_err(priv->dev, "cannot allocate raw input device\n"); + return -ENOMEM; + } + rdev->priv = priv; + rdev->map_name = RC_MAP_EMPTY; + rdev->input_name = "IMG Infrared Decoder Raw"; + rdev->driver_type = RC_DRIVER_IR_RAW; + + /* Register raw decoder */ + error = rc_register_device(rdev); + if (error) { + dev_err(priv->dev, "failed to register raw IR input device\n"); + rc_free_device(rdev); + raw->rdev = NULL; + return error; + } + + return 0; +} + +void img_ir_remove_raw(struct img_ir_priv *priv) +{ + struct img_ir_priv_raw *raw = &priv->raw; + struct rc_dev *rdev = raw->rdev; + u32 irq_en; + + if (!rdev) + return; + + /* switch off and disable raw (edge) interrupts */ + spin_lock_irq(&priv->lock); + raw->rdev = NULL; + irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE); + irq_en &= ~IMG_IR_IRQ_EDGE; + img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en); + img_ir_write(priv, IMG_IR_IRQ_CLEAR, IMG_IR_IRQ_EDGE); + spin_unlock_irq(&priv->lock); + + rc_unregister_device(rdev); + + del_timer_sync(&raw->timer); +} diff --git a/drivers/media/rc/img-ir/img-ir-raw.h b/drivers/media/rc/img-ir/img-ir-raw.h new file mode 100644 index 0000000..9802ffd --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-raw.h @@ -0,0 +1,60 @@ +/* + * ImgTec IR Raw Decoder found in PowerDown Controller. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + */ + +#ifndef _IMG_IR_RAW_H_ +#define _IMG_IR_RAW_H_ + +struct img_ir_priv; + +#ifdef CONFIG_IR_IMG_RAW + +/** + * struct img_ir_priv_raw - Private driver data for raw decoder. + * @rdev: Raw remote control device + * @timer: Timer to echo samples to keep soft decoders happy. + * @last_status: Last raw status bits. + */ +struct img_ir_priv_raw { + struct rc_dev *rdev; + struct timer_list timer; + u32 last_status; +}; + +static inline bool img_ir_raw_enabled(struct img_ir_priv_raw *raw) +{ + return raw->rdev; +}; + +void img_ir_isr_raw(struct img_ir_priv *priv, u32 irq_status); +void img_ir_setup_raw(struct img_ir_priv *priv); +int img_ir_probe_raw(struct img_ir_priv *priv); +void img_ir_remove_raw(struct img_ir_priv *priv); + +#else + +struct img_ir_priv_raw { +}; +static inline bool img_ir_raw_enabled(struct img_ir_priv_raw *raw) +{ + return false; +}; +static inline void img_ir_isr_raw(struct img_ir_priv *priv, u32 irq_status) +{ +} +static inline void img_ir_setup_raw(struct img_ir_priv *priv) +{ +} +static inline int img_ir_probe_raw(struct img_ir_priv *priv) +{ + return -ENODEV; +} +static inline void img_ir_remove_raw(struct img_ir_priv *priv) +{ +} + +#endif /* CONFIG_IR_IMG_RAW */ + +#endif /* _IMG_IR_RAW_H_ */ diff --git a/drivers/media/rc/img-ir/img-ir-sanyo.c b/drivers/media/rc/img-ir/img-ir-sanyo.c new file mode 100644 index 0000000..c2c763e --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-sanyo.c @@ -0,0 +1,122 @@ +/* + * ImgTec IR Decoder setup for Sanyo protocol. + * + * Copyright 2012-2014 Imagination Technologies Ltd. + * + * From ir-sanyo-decoder.c: + * + * This protocol uses the NEC protocol timings. However, data is formatted as: + * 13 bits Custom Code + * 13 bits NOT(Custom Code) + * 8 bits Key data + * 8 bits NOT(Key data) + * + * According with LIRC, this protocol is used on Sanyo, Aiwa and Chinon + * Information for this protocol is available at the Sanyo LC7461 datasheet. + */ + +#include "img-ir-hw.h" + +/* Convert Sanyo data to a scancode */ +static int img_ir_sanyo_scancode(int len, u64 raw, int *scancode, u64 protocols) +{ + unsigned int addr, addr_inv, data, data_inv; + /* a repeat code has no data */ + if (!len) + return IMG_IR_REPEATCODE; + if (len != 42) + return -EINVAL; + addr = (raw >> 0) & 0x1fff; + addr_inv = (raw >> 13) & 0x1fff; + data = (raw >> 26) & 0xff; + data_inv = (raw >> 34) & 0xff; + /* Validate data */ + if ((data_inv ^ data) != 0xff) + return -EINVAL; + /* Validate address */ + if ((addr_inv ^ addr) != 0x1fff) + return -EINVAL; + + /* Normal Sanyo */ + *scancode = addr << 8 | data; + return IMG_IR_SCANCODE; +} + +/* Convert Sanyo scancode to Sanyo data filter */ +static int img_ir_sanyo_filter(const struct rc_scancode_filter *in, + struct img_ir_filter *out, u64 protocols) +{ + unsigned int addr, addr_inv, data, data_inv; + unsigned int addr_m, data_m; + + data = in->data & 0xff; + data_m = in->mask & 0xff; + data_inv = data ^ 0xff; + + if (in->data & 0xff700000) + return -EINVAL; + + addr = (in->data >> 8) & 0x1fff; + addr_m = (in->mask >> 8) & 0x1fff; + addr_inv = addr ^ 0x1fff; + + out->data = (u64)data_inv << 34 | + (u64)data << 26 | + addr_inv << 13 | + addr; + out->mask = (u64)data_m << 34 | + (u64)data_m << 26 | + addr_m << 13 | + addr_m; + return 0; +} + +/* Sanyo decoder */ +struct img_ir_decoder img_ir_sanyo = { + .type = RC_BIT_SANYO, + .control = { + .decoden = 1, + .code_type = IMG_IR_CODETYPE_PULSEDIST, + }, + /* main timings */ + .unit = 562500, /* 562.5 us */ + .timings = { + /* leader symbol */ + .ldr = { + .pulse = { 16 /* 9ms */ }, + .space = { 8 /* 4.5ms */ }, + }, + /* 0 symbol */ + .s00 = { + .pulse = { 1 /* 562.5 us */ }, + .space = { 1 /* 562.5 us */ }, + }, + /* 1 symbol */ + .s01 = { + .pulse = { 1 /* 562.5 us */ }, + .space = { 3 /* 1687.5 us */ }, + }, + /* free time */ + .ft = { + .minlen = 42, + .maxlen = 42, + .ft_min = 10, /* 5.625 ms */ + }, + }, + /* repeat codes */ + .repeat = 108, /* 108 ms */ + .rtimings = { + /* leader symbol */ + .ldr = { + .space = { 4 /* 2.25 ms */ }, + }, + /* free time */ + .ft = { + .minlen = 0, /* repeat code has no data */ + .maxlen = 0, + }, + }, + /* scancode logic */ + .scancode = img_ir_sanyo_scancode, + .filter = img_ir_sanyo_filter, +}; diff --git a/drivers/media/rc/img-ir/img-ir-sharp.c b/drivers/media/rc/img-ir/img-ir-sharp.c new file mode 100644 index 0000000..3397cc5 --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-sharp.c @@ -0,0 +1,99 @@ +/* + * ImgTec IR Decoder setup for Sharp protocol. + * + * Copyright 2012-2014 Imagination Technologies Ltd. + */ + +#include "img-ir-hw.h" + +/* Convert Sharp data to a scancode */ +static int img_ir_sharp_scancode(int len, u64 raw, int *scancode, u64 protocols) +{ + unsigned int addr, cmd, exp, chk; + + if (len != 15) + return -EINVAL; + + addr = (raw >> 0) & 0x1f; + cmd = (raw >> 5) & 0xff; + exp = (raw >> 13) & 0x1; + chk = (raw >> 14) & 0x1; + + /* validate data */ + if (!exp) + return -EINVAL; + if (chk) + /* probably the second half of the message */ + return -EINVAL; + + *scancode = addr << 8 | cmd; + return IMG_IR_SCANCODE; +} + +/* Convert Sharp scancode to Sharp data filter */ +static int img_ir_sharp_filter(const struct rc_scancode_filter *in, + struct img_ir_filter *out, u64 protocols) +{ + unsigned int addr, cmd, exp = 0, chk = 0; + unsigned int addr_m, cmd_m, exp_m = 0, chk_m = 0; + + addr = (in->data >> 8) & 0x1f; + addr_m = (in->mask >> 8) & 0x1f; + cmd = (in->data >> 0) & 0xff; + cmd_m = (in->mask >> 0) & 0xff; + if (cmd_m) { + /* if filtering commands, we can only match the first part */ + exp = 1; + exp_m = 1; + chk = 0; + chk_m = 1; + } + + out->data = addr | + cmd << 5 | + exp << 13 | + chk << 14; + out->mask = addr_m | + cmd_m << 5 | + exp_m << 13 | + chk_m << 14; + + return 0; +} + +/* + * Sharp decoder + * See also http://www.sbprojects.com/knowledge/ir/sharp.php + */ +struct img_ir_decoder img_ir_sharp = { + .type = RC_BIT_SHARP, + .control = { + .decoden = 0, + .decodend2 = 1, + .code_type = IMG_IR_CODETYPE_PULSEDIST, + .d1validsel = 1, + }, + /* main timings */ + .tolerance = 20, /* 20% */ + .timings = { + /* 0 symbol */ + .s10 = { + .pulse = { 320 /* 320 us */ }, + .space = { 680 /* 1 ms period */ }, + }, + /* 1 symbol */ + .s11 = { + .pulse = { 320 /* 320 us */ }, + .space = { 1680 /* 2 ms period */ }, + }, + /* free time */ + .ft = { + .minlen = 15, + .maxlen = 15, + .ft_min = 5000, /* 5 ms */ + }, + }, + /* scancode logic */ + .scancode = img_ir_sharp_scancode, + .filter = img_ir_sharp_filter, +}; diff --git a/drivers/media/rc/img-ir/img-ir-sony.c b/drivers/media/rc/img-ir/img-ir-sony.c new file mode 100644 index 0000000..993409a --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir-sony.c @@ -0,0 +1,145 @@ +/* + * ImgTec IR Decoder setup for Sony (SIRC) protocol. + * + * Copyright 2012-2014 Imagination Technologies Ltd. + */ + +#include "img-ir-hw.h" + +/* Convert Sony data to a scancode */ +static int img_ir_sony_scancode(int len, u64 raw, int *scancode, u64 protocols) +{ + unsigned int dev, subdev, func; + + switch (len) { + case 12: + if (!(protocols & RC_BIT_SONY12)) + return -EINVAL; + func = raw & 0x7f; /* first 7 bits */ + raw >>= 7; + dev = raw & 0x1f; /* next 5 bits */ + subdev = 0; + break; + case 15: + if (!(protocols & RC_BIT_SONY15)) + return -EINVAL; + func = raw & 0x7f; /* first 7 bits */ + raw >>= 7; + dev = raw & 0xff; /* next 8 bits */ + subdev = 0; + break; + case 20: + if (!(protocols & RC_BIT_SONY20)) + return -EINVAL; + func = raw & 0x7f; /* first 7 bits */ + raw >>= 7; + dev = raw & 0x1f; /* next 5 bits */ + raw >>= 5; + subdev = raw & 0xff; /* next 8 bits */ + break; + default: + return -EINVAL; + } + *scancode = dev << 16 | subdev << 8 | func; + return IMG_IR_SCANCODE; +} + +/* Convert NEC scancode to NEC data filter */ +static int img_ir_sony_filter(const struct rc_scancode_filter *in, + struct img_ir_filter *out, u64 protocols) +{ + unsigned int dev, subdev, func; + unsigned int dev_m, subdev_m, func_m; + unsigned int len = 0; + + dev = (in->data >> 16) & 0xff; + dev_m = (in->mask >> 16) & 0xff; + subdev = (in->data >> 8) & 0xff; + subdev_m = (in->mask >> 8) & 0xff; + func = (in->data >> 0) & 0x7f; + func_m = (in->mask >> 0) & 0x7f; + + if (subdev & subdev_m) { + /* can't encode subdev and higher device bits */ + if (dev & dev_m & 0xe0) + return -EINVAL; + /* subdevice (extended) bits only in 20 bit encoding */ + if (!(protocols & RC_BIT_SONY20)) + return -EINVAL; + len = 20; + dev_m &= 0x1f; + } else if (dev & dev_m & 0xe0) { + /* upper device bits only in 15 bit encoding */ + if (!(protocols & RC_BIT_SONY15)) + return -EINVAL; + len = 15; + subdev_m = 0; + } else { + /* + * The hardware mask cannot distinguish high device bits and low + * extended bits, so logically AND those bits of the masks + * together. + */ + subdev_m &= (dev_m >> 5) | 0xf8; + dev_m &= 0x1f; + } + + /* ensure there aren't any bits straying between fields */ + dev &= dev_m; + subdev &= subdev_m; + + /* write the hardware filter */ + out->data = func | + dev << 7 | + subdev << 15; + out->mask = func_m | + dev_m << 7 | + subdev_m << 15; + + if (len) { + out->minlen = len; + out->maxlen = len; + } + return 0; +} + +/* + * Sony SIRC decoder + * See also http://www.sbprojects.com/knowledge/ir/sirc.php + * http://picprojects.org.uk/projects/sirc/sonysirc.pdf + */ +struct img_ir_decoder img_ir_sony = { + .type = RC_BIT_SONY12 | RC_BIT_SONY15 | RC_BIT_SONY20, + .control = { + .decoden = 1, + .code_type = IMG_IR_CODETYPE_PULSELEN, + }, + /* main timings */ + .unit = 600000, /* 600 us */ + .timings = { + /* leader symbol */ + .ldr = { + .pulse = { 4 /* 2.4 ms */ }, + .space = { 1 /* 600 us */ }, + }, + /* 0 symbol */ + .s00 = { + .pulse = { 1 /* 600 us */ }, + .space = { 1 /* 600 us */ }, + }, + /* 1 symbol */ + .s01 = { + .pulse = { 2 /* 1.2 ms */ }, + .space = { 1 /* 600 us */ }, + }, + /* free time */ + .ft = { + .minlen = 12, + .maxlen = 20, + .ft_min = 10, /* 6 ms */ + }, + }, + /* scancode logic */ + .scancode = img_ir_sony_scancode, + .filter = img_ir_sony_filter, +}; diff --git a/drivers/media/rc/img-ir/img-ir.h b/drivers/media/rc/img-ir/img-ir.h new file mode 100644 index 0000000..afb1893 --- /dev/null +++ b/drivers/media/rc/img-ir/img-ir.h @@ -0,0 +1,166 @@ +/* + * ImgTec IR Decoder found in PowerDown Controller. + * + * Copyright 2010-2014 Imagination Technologies Ltd. + */ + +#ifndef _IMG_IR_H_ +#define _IMG_IR_H_ + +#include <linux/io.h> +#include <linux/spinlock.h> + +#include "img-ir-raw.h" +#include "img-ir-hw.h" + +/* registers */ + +/* relative to the start of the IR block of registers */ +#define IMG_IR_CONTROL 0x00 +#define IMG_IR_STATUS 0x04 +#define IMG_IR_DATA_LW 0x08 +#define IMG_IR_DATA_UP 0x0c +#define IMG_IR_LEAD_SYMB_TIMING 0x10 +#define IMG_IR_S00_SYMB_TIMING 0x14 +#define IMG_IR_S01_SYMB_TIMING 0x18 +#define IMG_IR_S10_SYMB_TIMING 0x1c +#define IMG_IR_S11_SYMB_TIMING 0x20 +#define IMG_IR_FREE_SYMB_TIMING 0x24 +#define IMG_IR_POW_MOD_PARAMS 0x28 +#define IMG_IR_POW_MOD_ENABLE 0x2c +#define IMG_IR_IRQ_MSG_DATA_LW 0x30 +#define IMG_IR_IRQ_MSG_DATA_UP 0x34 +#define IMG_IR_IRQ_MSG_MASK_LW 0x38 +#define IMG_IR_IRQ_MSG_MASK_UP 0x3c +#define IMG_IR_IRQ_ENABLE 0x40 +#define IMG_IR_IRQ_STATUS 0x44 +#define IMG_IR_IRQ_CLEAR 0x48 +#define IMG_IR_IRCORE_ID 0xf0 +#define IMG_IR_CORE_REV 0xf4 +#define IMG_IR_CORE_DES1 0xf8 +#define IMG_IR_CORE_DES2 0xfc + + +/* field masks */ + +/* IMG_IR_CONTROL */ +#define IMG_IR_DECODEN 0x40000000 +#define IMG_IR_CODETYPE 0x30000000 +#define IMG_IR_CODETYPE_SHIFT 28 +#define IMG_IR_HDRTOG 0x08000000 +#define IMG_IR_LDRDEC 0x04000000 +#define IMG_IR_DECODINPOL 0x02000000 /* active high */ +#define IMG_IR_BITORIEN 0x01000000 /* MSB first */ +#define IMG_IR_D1VALIDSEL 0x00008000 +#define IMG_IR_BITINV 0x00000040 /* don't invert */ +#define IMG_IR_DECODEND2 0x00000010 +#define IMG_IR_BITORIEND2 0x00000002 /* MSB first */ +#define IMG_IR_BITINVD2 0x00000001 /* don't invert */ + +/* IMG_IR_STATUS */ +#define IMG_IR_RXDVALD2 0x00001000 +#define IMG_IR_IRRXD 0x00000400 +#define IMG_IR_TOGSTATE 0x00000200 +#define IMG_IR_RXDVAL 0x00000040 +#define IMG_IR_RXDLEN 0x0000003f +#define IMG_IR_RXDLEN_SHIFT 0 + +/* IMG_IR_LEAD_SYMB_TIMING, IMG_IR_Sxx_SYMB_TIMING */ +#define IMG_IR_PD_MAX 0xff000000 +#define IMG_IR_PD_MAX_SHIFT 24 +#define IMG_IR_PD_MIN 0x00ff0000 +#define IMG_IR_PD_MIN_SHIFT 16 +#define IMG_IR_W_MAX 0x0000ff00 +#define IMG_IR_W_MAX_SHIFT 8 +#define IMG_IR_W_MIN 0x000000ff +#define IMG_IR_W_MIN_SHIFT 0 + +/* IMG_IR_FREE_SYMB_TIMING */ +#define IMG_IR_MAXLEN 0x0007e000 +#define IMG_IR_MAXLEN_SHIFT 13 +#define IMG_IR_MINLEN 0x00001f00 +#define IMG_IR_MINLEN_SHIFT 8 +#define IMG_IR_FT_MIN 0x000000ff +#define IMG_IR_FT_MIN_SHIFT 0 + +/* IMG_IR_POW_MOD_PARAMS */ +#define IMG_IR_PERIOD_LEN 0x3f000000 +#define IMG_IR_PERIOD_LEN_SHIFT 24 +#define IMG_IR_PERIOD_DUTY 0x003f0000 +#define IMG_IR_PERIOD_DUTY_SHIFT 16 +#define IMG_IR_STABLE_STOP 0x00003f00 +#define IMG_IR_STABLE_STOP_SHIFT 8 +#define IMG_IR_STABLE_START 0x0000003f +#define IMG_IR_STABLE_START_SHIFT 0 + +/* IMG_IR_POW_MOD_ENABLE */ +#define IMG_IR_POWER_OUT_EN 0x00000002 +#define IMG_IR_POWER_MOD_EN 0x00000001 + +/* IMG_IR_IRQ_ENABLE, IMG_IR_IRQ_STATUS, IMG_IR_IRQ_CLEAR */ +#define IMG_IR_IRQ_DEC2_ERR 0x00000080 +#define IMG_IR_IRQ_DEC_ERR 0x00000040 +#define IMG_IR_IRQ_ACT_LEVEL 0x00000020 +#define IMG_IR_IRQ_FALL_EDGE 0x00000010 +#define IMG_IR_IRQ_RISE_EDGE 0x00000008 +#define IMG_IR_IRQ_DATA_MATCH 0x00000004 +#define IMG_IR_IRQ_DATA2_VALID 0x00000002 +#define IMG_IR_IRQ_DATA_VALID 0x00000001 +#define IMG_IR_IRQ_ALL 0x000000ff +#define IMG_IR_IRQ_EDGE (IMG_IR_IRQ_FALL_EDGE | IMG_IR_IRQ_RISE_EDGE) + +/* IMG_IR_CORE_ID */ +#define IMG_IR_CORE_ID 0x00ff0000 +#define IMG_IR_CORE_ID_SHIFT 16 +#define IMG_IR_CORE_CONFIG 0x0000ffff +#define IMG_IR_CORE_CONFIG_SHIFT 0 + +/* IMG_IR_CORE_REV */ +#define IMG_IR_DESIGNER 0xff000000 +#define IMG_IR_DESIGNER_SHIFT 24 +#define IMG_IR_MAJOR_REV 0x00ff0000 +#define IMG_IR_MAJOR_REV_SHIFT 16 +#define IMG_IR_MINOR_REV 0x0000ff00 +#define IMG_IR_MINOR_REV_SHIFT 8 +#define IMG_IR_MAINT_REV 0x000000ff +#define IMG_IR_MAINT_REV_SHIFT 0 + +struct device; +struct clk; + +/** + * struct img_ir_priv - Private driver data. + * @dev: Platform device. + * @irq: IRQ number. + * @clk: Input clock. + * @reg_base: Iomem base address of IR register block. + * @lock: Protects IR registers and variables in this struct. + * @raw: Driver data for raw decoder. + * @hw: Driver data for hardware decoder. + */ +struct img_ir_priv { + struct device *dev; + int irq; + struct clk *clk; + void __iomem *reg_base; + spinlock_t lock; + + struct img_ir_priv_raw raw; + struct img_ir_priv_hw hw; +}; + +/* Hardware access */ + +static inline void img_ir_write(struct img_ir_priv *priv, + unsigned int reg_offs, unsigned int data) +{ + iowrite32(data, priv->reg_base + reg_offs); +} + +static inline unsigned int img_ir_read(struct img_ir_priv *priv, + unsigned int reg_offs) +{ + return ioread32(priv->reg_base + reg_offs); +} + +#endif /* _IMG_IR_H_ */ diff --git a/drivers/media/rc/imon.c b/drivers/media/rc/imon.c index 822b9f4..6f24e77 100644 --- a/drivers/media/rc/imon.c +++ b/drivers/media/rc/imon.c @@ -1017,7 +1017,7 @@ static int imon_ir_change_protocol(struct rc_dev *rc, u64 *rc_type) unsigned char ir_proto_packet[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86 }; - if (*rc_type && !(*rc_type & rc->allowed_protos)) + if (*rc_type && !rc_protocols_allowed(rc, *rc_type)) dev_warn(dev, "Looks like you're trying to use an IR protocol " "this device does not support\n"); @@ -1867,7 +1867,8 @@ static struct rc_dev *imon_init_rdev(struct imon_context *ictx) rdev->priv = ictx; rdev->driver_type = RC_DRIVER_SCANCODE; - rdev->allowed_protos = RC_BIT_OTHER | RC_BIT_RC6_MCE; /* iMON PAD or MCE */ + /* iMON PAD or MCE */ + rc_set_allowed_protocols(rdev, RC_BIT_OTHER | RC_BIT_RC6_MCE); rdev->change_protocol = imon_ir_change_protocol; rdev->driver_name = MOD_NAME; @@ -1880,7 +1881,7 @@ static struct rc_dev *imon_init_rdev(struct imon_context *ictx) if (ictx->product == 0xffdc) { imon_get_ffdc_type(ictx); - rdev->allowed_protos = ictx->rc_type; + rc_set_allowed_protocols(rdev, ictx->rc_type); } imon_set_display_type(ictx); diff --git a/drivers/media/rc/ir-jvc-decoder.c b/drivers/media/rc/ir-jvc-decoder.c index 3948138..4ea62a1 100644 --- a/drivers/media/rc/ir-jvc-decoder.c +++ b/drivers/media/rc/ir-jvc-decoder.c @@ -47,7 +47,7 @@ static int ir_jvc_decode(struct rc_dev *dev, struct ir_raw_event ev) { struct jvc_dec *data = &dev->raw->jvc; - if (!(dev->enabled_protocols & RC_BIT_JVC)) + if (!rc_protocols_enabled(dev, RC_BIT_JVC)) return 0; if (!is_timing_event(ev)) { diff --git a/drivers/media/rc/ir-lirc-codec.c b/drivers/media/rc/ir-lirc-codec.c index ed2c8a1..d731da6 100644 --- a/drivers/media/rc/ir-lirc-codec.c +++ b/drivers/media/rc/ir-lirc-codec.c @@ -35,7 +35,7 @@ static int ir_lirc_decode(struct rc_dev *dev, struct ir_raw_event ev) struct lirc_codec *lirc = &dev->raw->lirc; int sample; - if (!(dev->enabled_protocols & RC_BIT_LIRC)) + if (!rc_protocols_enabled(dev, RC_BIT_LIRC)) return 0; if (!dev->raw->lirc.drv || !dev->raw->lirc.drv->rbuf) diff --git a/drivers/media/rc/ir-mce_kbd-decoder.c b/drivers/media/rc/ir-mce_kbd-decoder.c index 9f3c9b5..0c55f79 100644 --- a/drivers/media/rc/ir-mce_kbd-decoder.c +++ b/drivers/media/rc/ir-mce_kbd-decoder.c @@ -216,7 +216,7 @@ static int ir_mce_kbd_decode(struct rc_dev *dev, struct ir_raw_event ev) u32 scancode; unsigned long delay; - if (!(dev->enabled_protocols & RC_BIT_MCE_KBD)) + if (!rc_protocols_enabled(dev, RC_BIT_MCE_KBD)) return 0; if (!is_timing_event(ev)) { diff --git a/drivers/media/rc/ir-nec-decoder.c b/drivers/media/rc/ir-nec-decoder.c index 9a90094..9de1791 100644 --- a/drivers/media/rc/ir-nec-decoder.c +++ b/drivers/media/rc/ir-nec-decoder.c @@ -1,6 +1,6 @@ /* ir-nec-decoder.c - handle NEC IR Pulse/Space protocol * - * Copyright (C) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -52,7 +52,7 @@ static int ir_nec_decode(struct rc_dev *dev, struct ir_raw_event ev) u8 address, not_address, command, not_command; bool send_32bits = false; - if (!(dev->enabled_protocols & RC_BIT_NEC)) + if (!rc_protocols_enabled(dev, RC_BIT_NEC)) return 0; if (!is_timing_event(ev)) { @@ -172,7 +172,10 @@ static int ir_nec_decode(struct rc_dev *dev, struct ir_raw_event ev) if (send_32bits) { /* NEC transport, but modified protocol, used by at * least Apple and TiVo remotes */ - scancode = data->bits; + scancode = not_address << 24 | + address << 16 | + not_command << 8 | + command; IR_dprintk(1, "NEC (modified) scancode 0x%08x\n", scancode); } else if ((address ^ not_address) != 0xff) { /* Extended NEC */ @@ -222,6 +225,6 @@ module_init(ir_nec_decode_init); module_exit(ir_nec_decode_exit); MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("NEC IR protocol decoder"); diff --git a/drivers/media/rc/ir-raw.c b/drivers/media/rc/ir-raw.c index 5c42750..763c9d1 100644 --- a/drivers/media/rc/ir-raw.c +++ b/drivers/media/rc/ir-raw.c @@ -1,6 +1,6 @@ /* ir-raw.c - handle IR pulse/space events * - * Copyright (C) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -256,7 +256,7 @@ int ir_raw_event_register(struct rc_dev *dev) return -ENOMEM; dev->raw->dev = dev; - dev->enabled_protocols = ~0; + rc_set_enabled_protocols(dev, ~0); rc = kfifo_alloc(&dev->raw->kfifo, sizeof(struct ir_raw_event) * MAX_IR_EVENT_SIZE, GFP_KERNEL); @@ -352,6 +352,7 @@ void ir_raw_init(void) load_jvc_decode(); load_sony_decode(); load_sanyo_decode(); + load_sharp_decode(); load_mce_kbd_decode(); load_lirc_codec(); diff --git a/drivers/media/rc/ir-rc5-decoder.c b/drivers/media/rc/ir-rc5-decoder.c index 4e53a31..4295d9b 100644 --- a/drivers/media/rc/ir-rc5-decoder.c +++ b/drivers/media/rc/ir-rc5-decoder.c @@ -1,6 +1,6 @@ /* ir-rc5-decoder.c - handle RC5(x) IR Pulse/Space protocol * - * Copyright (C) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -52,7 +52,7 @@ static int ir_rc5_decode(struct rc_dev *dev, struct ir_raw_event ev) u8 toggle; u32 scancode; - if (!(dev->enabled_protocols & (RC_BIT_RC5 | RC_BIT_RC5X))) + if (!rc_protocols_enabled(dev, RC_BIT_RC5 | RC_BIT_RC5X)) return 0; if (!is_timing_event(ev)) { @@ -128,7 +128,7 @@ again: if (data->wanted_bits == RC5X_NBITS) { /* RC5X */ u8 xdata, command, system; - if (!(dev->enabled_protocols & RC_BIT_RC5X)) { + if (!rc_protocols_enabled(dev, RC_BIT_RC5X)) { data->state = STATE_INACTIVE; return 0; } @@ -145,7 +145,7 @@ again: } else { /* RC5 */ u8 command, system; - if (!(dev->enabled_protocols & RC_BIT_RC5)) { + if (!rc_protocols_enabled(dev, RC_BIT_RC5)) { data->state = STATE_INACTIVE; return 0; } @@ -193,6 +193,6 @@ module_init(ir_rc5_decode_init); module_exit(ir_rc5_decode_exit); MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("RC5(x) IR protocol decoder"); diff --git a/drivers/media/rc/ir-rc5-sz-decoder.c b/drivers/media/rc/ir-rc5-sz-decoder.c index 865fe84..dc18b74 100644 --- a/drivers/media/rc/ir-rc5-sz-decoder.c +++ b/drivers/media/rc/ir-rc5-sz-decoder.c @@ -1,6 +1,6 @@ /* ir-rc5-sz-decoder.c - handle RC5 Streamzap IR Pulse/Space protocol * - * Copyright (C) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2010 by Mauro Carvalho Chehab * Copyright (C) 2010 by Jarod Wilson <jarod@redhat.com> * * This program is free software; you can redistribute it and/or modify @@ -48,7 +48,7 @@ static int ir_rc5_sz_decode(struct rc_dev *dev, struct ir_raw_event ev) u8 toggle, command, system; u32 scancode; - if (!(dev->enabled_protocols & RC_BIT_RC5_SZ)) + if (!rc_protocols_enabled(dev, RC_BIT_RC5_SZ)) return 0; if (!is_timing_event(ev)) { diff --git a/drivers/media/rc/ir-rc6-decoder.c b/drivers/media/rc/ir-rc6-decoder.c index 7cba7d3..cfbd64e 100644 --- a/drivers/media/rc/ir-rc6-decoder.c +++ b/drivers/media/rc/ir-rc6-decoder.c @@ -89,9 +89,9 @@ static int ir_rc6_decode(struct rc_dev *dev, struct ir_raw_event ev) u32 scancode; u8 toggle; - if (!(dev->enabled_protocols & - (RC_BIT_RC6_0 | RC_BIT_RC6_6A_20 | RC_BIT_RC6_6A_24 | - RC_BIT_RC6_6A_32 | RC_BIT_RC6_MCE))) + if (!rc_protocols_enabled(dev, RC_BIT_RC6_0 | RC_BIT_RC6_6A_20 | + RC_BIT_RC6_6A_24 | RC_BIT_RC6_6A_32 | + RC_BIT_RC6_MCE)) return 0; if (!is_timing_event(ev)) { diff --git a/drivers/media/rc/ir-sanyo-decoder.c b/drivers/media/rc/ir-sanyo-decoder.c index 0a06205..eb715f0 100644 --- a/drivers/media/rc/ir-sanyo-decoder.c +++ b/drivers/media/rc/ir-sanyo-decoder.c @@ -1,6 +1,6 @@ /* ir-sanyo-decoder.c - handle SANYO IR Pulse/Space protocol * - * Copyright (C) 2011 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2011 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -58,7 +58,7 @@ static int ir_sanyo_decode(struct rc_dev *dev, struct ir_raw_event ev) u32 scancode; u8 address, command, not_command; - if (!(dev->enabled_protocols & RC_BIT_SANYO)) + if (!rc_protocols_enabled(dev, RC_BIT_SANYO)) return 0; if (!is_timing_event(ev)) { @@ -200,6 +200,6 @@ module_init(ir_sanyo_decode_init); module_exit(ir_sanyo_decode_exit); MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("SANYO IR protocol decoder"); diff --git a/drivers/media/rc/ir-sharp-decoder.c b/drivers/media/rc/ir-sharp-decoder.c new file mode 100644 index 0000000..66d2039 --- /dev/null +++ b/drivers/media/rc/ir-sharp-decoder.c @@ -0,0 +1,200 @@ +/* ir-sharp-decoder.c - handle Sharp IR Pulse/Space protocol + * + * Copyright (C) 2013-2014 Imagination Technologies Ltd. + * + * Based on NEC decoder: + * Copyright (C) 2010 by Mauro Carvalho Chehab + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/bitrev.h> +#include <linux/module.h> +#include "rc-core-priv.h" + +#define SHARP_NBITS 15 +#define SHARP_UNIT 40000 /* ns */ +#define SHARP_BIT_PULSE (8 * SHARP_UNIT) /* 320us */ +#define SHARP_BIT_0_PERIOD (25 * SHARP_UNIT) /* 1ms (680us space) */ +#define SHARP_BIT_1_PERIOD (50 * SHARP_UNIT) /* 2ms (1680ms space) */ +#define SHARP_ECHO_SPACE (1000 * SHARP_UNIT) /* 40 ms */ +#define SHARP_TRAILER_SPACE (125 * SHARP_UNIT) /* 5 ms (even longer) */ + +enum sharp_state { + STATE_INACTIVE, + STATE_BIT_PULSE, + STATE_BIT_SPACE, + STATE_TRAILER_PULSE, + STATE_ECHO_SPACE, + STATE_TRAILER_SPACE, +}; + +/** + * ir_sharp_decode() - Decode one Sharp pulse or space + * @dev: the struct rc_dev descriptor of the device + * @duration: the struct ir_raw_event descriptor of the pulse/space + * + * This function returns -EINVAL if the pulse violates the state machine + */ +static int ir_sharp_decode(struct rc_dev *dev, struct ir_raw_event ev) +{ + struct sharp_dec *data = &dev->raw->sharp; + u32 msg, echo, address, command, scancode; + + if (!rc_protocols_enabled(dev, RC_BIT_SHARP)) + return 0; + + if (!is_timing_event(ev)) { + if (ev.reset) + data->state = STATE_INACTIVE; + return 0; + } + + IR_dprintk(2, "Sharp decode started at state %d (%uus %s)\n", + data->state, TO_US(ev.duration), TO_STR(ev.pulse)); + + switch (data->state) { + + case STATE_INACTIVE: + if (!ev.pulse) + break; + + if (!eq_margin(ev.duration, SHARP_BIT_PULSE, + SHARP_BIT_PULSE / 2)) + break; + + data->count = 0; + data->pulse_len = ev.duration; + data->state = STATE_BIT_SPACE; + return 0; + + case STATE_BIT_PULSE: + if (!ev.pulse) + break; + + if (!eq_margin(ev.duration, SHARP_BIT_PULSE, + SHARP_BIT_PULSE / 2)) + break; + + data->pulse_len = ev.duration; + data->state = STATE_BIT_SPACE; + return 0; + + case STATE_BIT_SPACE: + if (ev.pulse) + break; + + data->bits <<= 1; + if (eq_margin(data->pulse_len + ev.duration, SHARP_BIT_1_PERIOD, + SHARP_BIT_PULSE * 2)) + data->bits |= 1; + else if (!eq_margin(data->pulse_len + ev.duration, + SHARP_BIT_0_PERIOD, SHARP_BIT_PULSE * 2)) + break; + data->count++; + + if (data->count == SHARP_NBITS || + data->count == SHARP_NBITS * 2) + data->state = STATE_TRAILER_PULSE; + else + data->state = STATE_BIT_PULSE; + + return 0; + + case STATE_TRAILER_PULSE: + if (!ev.pulse) + break; + + if (!eq_margin(ev.duration, SHARP_BIT_PULSE, + SHARP_BIT_PULSE / 2)) + break; + + if (data->count == SHARP_NBITS) { + /* exp,chk bits should be 1,0 */ + if ((data->bits & 0x3) != 0x2) + break; + data->state = STATE_ECHO_SPACE; + } else { + data->state = STATE_TRAILER_SPACE; + } + return 0; + + case STATE_ECHO_SPACE: + if (ev.pulse) + break; + + if (!eq_margin(ev.duration, SHARP_ECHO_SPACE, + SHARP_ECHO_SPACE / 4)) + break; + + data->state = STATE_BIT_PULSE; + + return 0; + + case STATE_TRAILER_SPACE: + if (ev.pulse) + break; + + if (!geq_margin(ev.duration, SHARP_TRAILER_SPACE, + SHARP_BIT_PULSE / 2)) + break; + + /* Validate - command, ext, chk should be inverted in 2nd */ + msg = (data->bits >> 15) & 0x7fff; + echo = data->bits & 0x7fff; + if ((msg ^ echo) != 0x3ff) { + IR_dprintk(1, + "Sharp checksum error: received 0x%04x, 0x%04x\n", + msg, echo); + break; + } + + address = bitrev8((msg >> 7) & 0xf8); + command = bitrev8((msg >> 2) & 0xff); + + scancode = address << 8 | command; + IR_dprintk(1, "Sharp scancode 0x%04x\n", scancode); + + rc_keydown(dev, scancode, 0); + data->state = STATE_INACTIVE; + return 0; + } + + IR_dprintk(1, "Sharp decode failed at count %d state %d (%uus %s)\n", + data->count, data->state, TO_US(ev.duration), + TO_STR(ev.pulse)); + data->state = STATE_INACTIVE; + return -EINVAL; +} + +static struct ir_raw_handler sharp_handler = { + .protocols = RC_BIT_SHARP, + .decode = ir_sharp_decode, +}; + +static int __init ir_sharp_decode_init(void) +{ + ir_raw_handler_register(&sharp_handler); + + pr_info("IR Sharp protocol handler initialized\n"); + return 0; +} + +static void __exit ir_sharp_decode_exit(void) +{ + ir_raw_handler_unregister(&sharp_handler); +} + +module_init(ir_sharp_decode_init); +module_exit(ir_sharp_decode_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("James Hogan <james.hogan@imgtec.com>"); +MODULE_DESCRIPTION("Sharp IR protocol decoder"); diff --git a/drivers/media/rc/ir-sony-decoder.c b/drivers/media/rc/ir-sony-decoder.c index 29ab9c2..599c19a 100644 --- a/drivers/media/rc/ir-sony-decoder.c +++ b/drivers/media/rc/ir-sony-decoder.c @@ -45,8 +45,8 @@ static int ir_sony_decode(struct rc_dev *dev, struct ir_raw_event ev) u32 scancode; u8 device, subdevice, function; - if (!(dev->enabled_protocols & - (RC_BIT_SONY12 | RC_BIT_SONY15 | RC_BIT_SONY20))) + if (!rc_protocols_enabled(dev, RC_BIT_SONY12 | RC_BIT_SONY15 | + RC_BIT_SONY20)) return 0; if (!is_timing_event(ev)) { @@ -124,7 +124,7 @@ static int ir_sony_decode(struct rc_dev *dev, struct ir_raw_event ev) switch (data->count) { case 12: - if (!(dev->enabled_protocols & RC_BIT_SONY12)) { + if (!rc_protocols_enabled(dev, RC_BIT_SONY12)) { data->state = STATE_INACTIVE; return 0; } @@ -133,7 +133,7 @@ static int ir_sony_decode(struct rc_dev *dev, struct ir_raw_event ev) function = bitrev8((data->bits >> 4) & 0xFE); break; case 15: - if (!(dev->enabled_protocols & RC_BIT_SONY15)) { + if (!rc_protocols_enabled(dev, RC_BIT_SONY15)) { data->state = STATE_INACTIVE; return 0; } @@ -142,7 +142,7 @@ static int ir_sony_decode(struct rc_dev *dev, struct ir_raw_event ev) function = bitrev8((data->bits >> 7) & 0xFE); break; case 20: - if (!(dev->enabled_protocols & RC_BIT_SONY20)) { + if (!rc_protocols_enabled(dev, RC_BIT_SONY20)) { data->state = STATE_INACTIVE; return 0; } diff --git a/drivers/media/rc/ite-cir.c b/drivers/media/rc/ite-cir.c index 63b4225..ab24cc6 100644 --- a/drivers/media/rc/ite-cir.c +++ b/drivers/media/rc/ite-cir.c @@ -1563,7 +1563,7 @@ static int ite_probe(struct pnp_dev *pdev, const struct pnp_device_id /* set up ir-core props */ rdev->priv = itdev; rdev->driver_type = RC_DRIVER_IR_RAW; - rdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rdev, RC_BIT_ALL); rdev->open = ite_open; rdev->close = ite_close; rdev->s_idle = ite_s_idle; diff --git a/drivers/media/rc/keymaps/rc-adstech-dvb-t-pci.c b/drivers/media/rc/keymaps/rc-adstech-dvb-t-pci.c index b0e42df..01d901f 100644 --- a/drivers/media/rc/keymaps/rc-adstech-dvb-t-pci.c +++ b/drivers/media/rc/keymaps/rc-adstech-dvb-t-pci.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -87,4 +87,4 @@ module_init(init_rc_map_adstech_dvb_t_pci) module_exit(exit_rc_map_adstech_dvb_t_pci) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-apac-viewcomp.c b/drivers/media/rc/keymaps/rc-apac-viewcomp.c index 8c92ff9..bf9efa0 100644 --- a/drivers/media/rc/keymaps/rc-apac-viewcomp.c +++ b/drivers/media/rc/keymaps/rc-apac-viewcomp.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -78,4 +78,4 @@ module_init(init_rc_map_apac_viewcomp) module_exit(exit_rc_map_apac_viewcomp) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-asus-pc39.c b/drivers/media/rc/keymaps/rc-asus-pc39.c index 2caf211..9e674ba 100644 --- a/drivers/media/rc/keymaps/rc-asus-pc39.c +++ b/drivers/media/rc/keymaps/rc-asus-pc39.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -89,4 +89,4 @@ module_init(init_rc_map_asus_pc39) module_exit(exit_rc_map_asus_pc39) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-asus-ps3-100.c b/drivers/media/rc/keymaps/rc-asus-ps3-100.c index ba76609..e45de35 100644 --- a/drivers/media/rc/keymaps/rc-asus-ps3-100.c +++ b/drivers/media/rc/keymaps/rc-asus-ps3-100.c @@ -1,6 +1,6 @@ /* asus-ps3-100.h - Keytable for asus_ps3_100 Remote Controller * - * Copyright (c) 2012 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2012 by Mauro Carvalho Chehab * * Based on a previous patch from Remi Schwartz <remi.schwartz@gmail.com> * @@ -88,4 +88,4 @@ module_init(init_rc_map_asus_ps3_100) module_exit(exit_rc_map_asus_ps3_100) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-ati-tv-wonder-hd-600.c b/drivers/media/rc/keymaps/rc-ati-tv-wonder-hd-600.c index 2031224..91392d4 100644 --- a/drivers/media/rc/keymaps/rc-ati-tv-wonder-hd-600.c +++ b/drivers/media/rc/keymaps/rc-ati-tv-wonder-hd-600.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -67,4 +67,4 @@ module_init(init_rc_map_ati_tv_wonder_hd_600) module_exit(exit_rc_map_ati_tv_wonder_hd_600) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avermedia-a16d.c b/drivers/media/rc/keymaps/rc-avermedia-a16d.c index 894939a..ff30a71 100644 --- a/drivers/media/rc/keymaps/rc-avermedia-a16d.c +++ b/drivers/media/rc/keymaps/rc-avermedia-a16d.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -73,4 +73,4 @@ module_init(init_rc_map_avermedia_a16d) module_exit(exit_rc_map_avermedia_a16d) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avermedia-cardbus.c b/drivers/media/rc/keymaps/rc-avermedia-cardbus.c index d2aaf5b..d7471a6 100644 --- a/drivers/media/rc/keymaps/rc-avermedia-cardbus.c +++ b/drivers/media/rc/keymaps/rc-avermedia-cardbus.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -95,4 +95,4 @@ module_init(init_rc_map_avermedia_cardbus) module_exit(exit_rc_map_avermedia_cardbus) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avermedia-dvbt.c b/drivers/media/rc/keymaps/rc-avermedia-dvbt.c index dc2baf0..e2417d6 100644 --- a/drivers/media/rc/keymaps/rc-avermedia-dvbt.c +++ b/drivers/media/rc/keymaps/rc-avermedia-dvbt.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,4 +76,4 @@ module_init(init_rc_map_avermedia_dvbt) module_exit(exit_rc_map_avermedia_dvbt) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avermedia-m135a.c b/drivers/media/rc/keymaps/rc-avermedia-m135a.c index 04269d3..843598a 100644 --- a/drivers/media/rc/keymaps/rc-avermedia-m135a.c +++ b/drivers/media/rc/keymaps/rc-avermedia-m135a.c @@ -1,6 +1,6 @@ /* avermedia-m135a.c - Keytable for Avermedia M135A Remote Controllers * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * Copyright (c) 2010 by Herton Ronaldo Krzesinski <herton@mandriva.com.br> * * This program is free software; you can redistribute it and/or modify @@ -145,4 +145,4 @@ module_init(init_rc_map_avermedia_m135a) module_exit(exit_rc_map_avermedia_m135a) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avermedia-m733a-rm-k6.c b/drivers/media/rc/keymaps/rc-avermedia-m733a-rm-k6.c index e83b1a1..b24e748 100644 --- a/drivers/media/rc/keymaps/rc-avermedia-m733a-rm-k6.c +++ b/drivers/media/rc/keymaps/rc-avermedia-m733a-rm-k6.c @@ -93,4 +93,4 @@ module_init(init_rc_map_avermedia_m733a_rm_k6) module_exit(exit_rc_map_avermedia_m733a_rm_k6) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avermedia.c b/drivers/media/rc/keymaps/rc-avermedia.c index c6063df..3f68fbe 100644 --- a/drivers/media/rc/keymaps/rc-avermedia.c +++ b/drivers/media/rc/keymaps/rc-avermedia.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -84,4 +84,4 @@ module_init(init_rc_map_avermedia) module_exit(exit_rc_map_avermedia) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-avertv-303.c b/drivers/media/rc/keymaps/rc-avertv-303.c index 14f7845..c35bc5b 100644 --- a/drivers/media/rc/keymaps/rc-avertv-303.c +++ b/drivers/media/rc/keymaps/rc-avertv-303.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -83,4 +83,4 @@ module_init(init_rc_map_avertv_303) module_exit(exit_rc_map_avertv_303) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-behold-columbus.c b/drivers/media/rc/keymaps/rc-behold-columbus.c index 086b4b1..1fc344e 100644 --- a/drivers/media/rc/keymaps/rc-behold-columbus.c +++ b/drivers/media/rc/keymaps/rc-behold-columbus.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -106,4 +106,4 @@ module_init(init_rc_map_behold_columbus) module_exit(exit_rc_map_behold_columbus) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-behold.c b/drivers/media/rc/keymaps/rc-behold.c index 0877e34..d6519f8 100644 --- a/drivers/media/rc/keymaps/rc-behold.c +++ b/drivers/media/rc/keymaps/rc-behold.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -139,4 +139,4 @@ module_init(init_rc_map_behold) module_exit(exit_rc_map_behold) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-budget-ci-old.c b/drivers/media/rc/keymaps/rc-budget-ci-old.c index 8311e09..b196a5f 100644 --- a/drivers/media/rc/keymaps/rc-budget-ci-old.c +++ b/drivers/media/rc/keymaps/rc-budget-ci-old.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -91,4 +91,4 @@ module_init(init_rc_map_budget_ci_old) module_exit(exit_rc_map_budget_ci_old) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-cinergy-1400.c b/drivers/media/rc/keymaps/rc-cinergy-1400.c index 0c87fba..a099c08 100644 --- a/drivers/media/rc/keymaps/rc-cinergy-1400.c +++ b/drivers/media/rc/keymaps/rc-cinergy-1400.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -82,4 +82,4 @@ module_init(init_rc_map_cinergy_1400) module_exit(exit_rc_map_cinergy_1400) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-cinergy.c b/drivers/media/rc/keymaps/rc-cinergy.c index 309e9e3..b0f4328 100644 --- a/drivers/media/rc/keymaps/rc-cinergy.c +++ b/drivers/media/rc/keymaps/rc-cinergy.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,4 +76,4 @@ module_init(init_rc_map_cinergy) module_exit(exit_rc_map_cinergy) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-dib0700-nec.c b/drivers/media/rc/keymaps/rc-dib0700-nec.c index 492a05a..a0fa543 100644 --- a/drivers/media/rc/keymaps/rc-dib0700-nec.c +++ b/drivers/media/rc/keymaps/rc-dib0700-nec.c @@ -1,6 +1,6 @@ /* rc-dvb0700-big.c - Keytable for devices in dvb0700 * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * TODO: This table is a real mess, as it merges RC codes from several * devices into a big table. It also has both RC-5 and NEC codes inside. @@ -122,4 +122,4 @@ module_init(init_rc_map) module_exit(exit_rc_map) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-dib0700-rc5.c b/drivers/media/rc/keymaps/rc-dib0700-rc5.c index 454ea59..9079411 100644 --- a/drivers/media/rc/keymaps/rc-dib0700-rc5.c +++ b/drivers/media/rc/keymaps/rc-dib0700-rc5.c @@ -1,6 +1,6 @@ /* rc-dvb0700-big.c - Keytable for devices in dvb0700 * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * TODO: This table is a real mess, as it merges RC codes from several * devices into a big table. It also has both RC-5 and NEC codes inside. @@ -233,4 +233,4 @@ module_init(init_rc_map) module_exit(exit_rc_map) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-dm1105-nec.c b/drivers/media/rc/keymaps/rc-dm1105-nec.c index 67fc9fb..46e7ae4 100644 --- a/drivers/media/rc/keymaps/rc-dm1105-nec.c +++ b/drivers/media/rc/keymaps/rc-dm1105-nec.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -74,4 +74,4 @@ module_init(init_rc_map_dm1105_nec) module_exit(exit_rc_map_dm1105_nec) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-dntv-live-dvb-t.c b/drivers/media/rc/keymaps/rc-dntv-live-dvb-t.c index 91ea91d..d2826b4 100644 --- a/drivers/media/rc/keymaps/rc-dntv-live-dvb-t.c +++ b/drivers/media/rc/keymaps/rc-dntv-live-dvb-t.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,4 +76,4 @@ module_init(init_rc_map_dntv_live_dvb_t) module_exit(exit_rc_map_dntv_live_dvb_t) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-dntv-live-dvbt-pro.c b/drivers/media/rc/keymaps/rc-dntv-live-dvbt-pro.c index fd680d4..0d74769 100644 --- a/drivers/media/rc/keymaps/rc-dntv-live-dvbt-pro.c +++ b/drivers/media/rc/keymaps/rc-dntv-live-dvbt-pro.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -95,4 +95,4 @@ module_init(init_rc_map_dntv_live_dvbt_pro) module_exit(exit_rc_map_dntv_live_dvbt_pro) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-em-terratec.c b/drivers/media/rc/keymaps/rc-em-terratec.c index d1fcd64..7f1e06b 100644 --- a/drivers/media/rc/keymaps/rc-em-terratec.c +++ b/drivers/media/rc/keymaps/rc-em-terratec.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -67,4 +67,4 @@ module_init(init_rc_map_em_terratec) module_exit(exit_rc_map_em_terratec) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-encore-enltv-fm53.c b/drivers/media/rc/keymaps/rc-encore-enltv-fm53.c index 2fe45e4..4fc3904 100644 --- a/drivers/media/rc/keymaps/rc-encore-enltv-fm53.c +++ b/drivers/media/rc/keymaps/rc-encore-enltv-fm53.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -79,4 +79,4 @@ module_init(init_rc_map_encore_enltv_fm53) module_exit(exit_rc_map_encore_enltv_fm53) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-encore-enltv.c b/drivers/media/rc/keymaps/rc-encore-enltv.c index 223de75..f1914e2 100644 --- a/drivers/media/rc/keymaps/rc-encore-enltv.c +++ b/drivers/media/rc/keymaps/rc-encore-enltv.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -110,4 +110,4 @@ module_init(init_rc_map_encore_enltv) module_exit(exit_rc_map_encore_enltv) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-encore-enltv2.c b/drivers/media/rc/keymaps/rc-encore-enltv2.c index 669cbff..9c6c552 100644 --- a/drivers/media/rc/keymaps/rc-encore-enltv2.c +++ b/drivers/media/rc/keymaps/rc-encore-enltv2.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -88,4 +88,4 @@ module_init(init_rc_map_encore_enltv2) module_exit(exit_rc_map_encore_enltv2) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-evga-indtube.c b/drivers/media/rc/keymaps/rc-evga-indtube.c index 2c647fc..2370d2a 100644 --- a/drivers/media/rc/keymaps/rc-evga-indtube.c +++ b/drivers/media/rc/keymaps/rc-evga-indtube.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -59,4 +59,4 @@ module_init(init_rc_map_evga_indtube) module_exit(exit_rc_map_evga_indtube) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-eztv.c b/drivers/media/rc/keymaps/rc-eztv.c index 7692144..b5c96ed 100644 --- a/drivers/media/rc/keymaps/rc-eztv.c +++ b/drivers/media/rc/keymaps/rc-eztv.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -94,4 +94,4 @@ module_init(init_rc_map_eztv) module_exit(exit_rc_map_eztv) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-flydvb.c b/drivers/media/rc/keymaps/rc-flydvb.c index 3a6bba3..25cb89f 100644 --- a/drivers/media/rc/keymaps/rc-flydvb.c +++ b/drivers/media/rc/keymaps/rc-flydvb.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -75,4 +75,4 @@ module_init(init_rc_map_flydvb) module_exit(exit_rc_map_flydvb) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-flyvideo.c b/drivers/media/rc/keymaps/rc-flyvideo.c index bf9da58..e71377d 100644 --- a/drivers/media/rc/keymaps/rc-flyvideo.c +++ b/drivers/media/rc/keymaps/rc-flyvideo.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -68,4 +68,4 @@ module_init(init_rc_map_flyvideo) module_exit(exit_rc_map_flyvideo) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-fusionhdtv-mce.c b/drivers/media/rc/keymaps/rc-fusionhdtv-mce.c index 2f0970f..cf0608d 100644 --- a/drivers/media/rc/keymaps/rc-fusionhdtv-mce.c +++ b/drivers/media/rc/keymaps/rc-fusionhdtv-mce.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -96,4 +96,4 @@ module_init(init_rc_map_fusionhdtv_mce) module_exit(exit_rc_map_fusionhdtv_mce) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-gadmei-rm008z.c b/drivers/media/rc/keymaps/rc-gadmei-rm008z.c index 0e98ec4..03575bd 100644 --- a/drivers/media/rc/keymaps/rc-gadmei-rm008z.c +++ b/drivers/media/rc/keymaps/rc-gadmei-rm008z.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -79,4 +79,4 @@ module_init(init_rc_map_gadmei_rm008z) module_exit(exit_rc_map_gadmei_rm008z) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-genius-tvgo-a11mce.c b/drivers/media/rc/keymaps/rc-genius-tvgo-a11mce.c index a2e2faa..b2ab13b 100644 --- a/drivers/media/rc/keymaps/rc-genius-tvgo-a11mce.c +++ b/drivers/media/rc/keymaps/rc-genius-tvgo-a11mce.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -82,4 +82,4 @@ module_init(init_rc_map_genius_tvgo_a11mce) module_exit(exit_rc_map_genius_tvgo_a11mce) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-gotview7135.c b/drivers/media/rc/keymaps/rc-gotview7135.c index 864614e..229a36a 100644 --- a/drivers/media/rc/keymaps/rc-gotview7135.c +++ b/drivers/media/rc/keymaps/rc-gotview7135.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -77,4 +77,4 @@ module_init(init_rc_map_gotview7135) module_exit(exit_rc_map_gotview7135) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-hauppauge.c b/drivers/media/rc/keymaps/rc-hauppauge.c index 929bbbc1..36d57f7c 100644 --- a/drivers/media/rc/keymaps/rc-hauppauge.c +++ b/drivers/media/rc/keymaps/rc-hauppauge.c @@ -8,7 +8,7 @@ * - Hauppauge Black; * - DSR-0112 remote bundled with Haupauge MiniStick. * - * Copyright (c) 2010-2011 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010-2011 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -290,4 +290,4 @@ module_init(init_rc_map_rc5_hauppauge_new) module_exit(exit_rc_map_rc5_hauppauge_new) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-iodata-bctv7e.c b/drivers/media/rc/keymaps/rc-iodata-bctv7e.c index 34540df..9ee154c 100644 --- a/drivers/media/rc/keymaps/rc-iodata-bctv7e.c +++ b/drivers/media/rc/keymaps/rc-iodata-bctv7e.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -86,4 +86,4 @@ module_init(init_rc_map_iodata_bctv7e) module_exit(exit_rc_map_iodata_bctv7e) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-kaiomy.c b/drivers/media/rc/keymaps/rc-kaiomy.c index 4264a78..60803a7 100644 --- a/drivers/media/rc/keymaps/rc-kaiomy.c +++ b/drivers/media/rc/keymaps/rc-kaiomy.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -85,4 +85,4 @@ module_init(init_rc_map_kaiomy) module_exit(exit_rc_map_kaiomy) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-kworld-315u.c b/drivers/media/rc/keymaps/rc-kworld-315u.c index e48cd26..ba087ee 100644 --- a/drivers/media/rc/keymaps/rc-kworld-315u.c +++ b/drivers/media/rc/keymaps/rc-kworld-315u.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -81,4 +81,4 @@ module_init(init_rc_map_kworld_315u) module_exit(exit_rc_map_kworld_315u) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-kworld-pc150u.c b/drivers/media/rc/keymaps/rc-kworld-pc150u.c index 233bb5e..b92e571 100644 --- a/drivers/media/rc/keymaps/rc-kworld-pc150u.c +++ b/drivers/media/rc/keymaps/rc-kworld-pc150u.c @@ -4,7 +4,7 @@ * * Copyright (c) 2010 by Kyle Strickland * (based on kworld-plus-tv-analog.c by - * Mauro Carvalho Chehab <mchehab@redhat.com>) + * Mauro Carvalho Chehab) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c b/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c index 32998d6..edc8685 100644 --- a/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c +++ b/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -97,4 +97,4 @@ module_init(init_rc_map_kworld_plus_tv_analog) module_exit(exit_rc_map_kworld_plus_tv_analog) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-manli.c b/drivers/media/rc/keymaps/rc-manli.c index e7038bb..92424ef 100644 --- a/drivers/media/rc/keymaps/rc-manli.c +++ b/drivers/media/rc/keymaps/rc-manli.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -132,4 +132,4 @@ module_init(init_rc_map_manli) module_exit(exit_rc_map_manli) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-msi-tvanywhere-plus.c b/drivers/media/rc/keymaps/rc-msi-tvanywhere-plus.c index c393d8a..fd7a55c 100644 --- a/drivers/media/rc/keymaps/rc-msi-tvanywhere-plus.c +++ b/drivers/media/rc/keymaps/rc-msi-tvanywhere-plus.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -121,4 +121,4 @@ module_init(init_rc_map_msi_tvanywhere_plus) module_exit(exit_rc_map_msi_tvanywhere_plus) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-msi-tvanywhere.c b/drivers/media/rc/keymaps/rc-msi-tvanywhere.c index a7003d3..4233a8d 100644 --- a/drivers/media/rc/keymaps/rc-msi-tvanywhere.c +++ b/drivers/media/rc/keymaps/rc-msi-tvanywhere.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -67,4 +67,4 @@ module_init(init_rc_map_msi_tvanywhere) module_exit(exit_rc_map_msi_tvanywhere) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-nebula.c b/drivers/media/rc/keymaps/rc-nebula.c index 3f0ddd7..8ec881a 100644 --- a/drivers/media/rc/keymaps/rc-nebula.c +++ b/drivers/media/rc/keymaps/rc-nebula.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -94,4 +94,4 @@ module_init(init_rc_map_nebula) module_exit(exit_rc_map_nebula) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-nec-terratec-cinergy-xs.c b/drivers/media/rc/keymaps/rc-nec-terratec-cinergy-xs.c index 8d4dae2..292bbad3 100644 --- a/drivers/media/rc/keymaps/rc-nec-terratec-cinergy-xs.c +++ b/drivers/media/rc/keymaps/rc-nec-terratec-cinergy-xs.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,7 +14,7 @@ #include <linux/module.h> /* Terratec Cinergy Hybrid T USB XS FM - Mauro Carvalho Chehab <mchehab@redhat.com> + Mauro Carvalho Chehab */ static struct rc_map_table nec_terratec_cinergy_xs[] = { @@ -155,4 +155,4 @@ module_init(init_rc_map_nec_terratec_cinergy_xs) module_exit(exit_rc_map_nec_terratec_cinergy_xs) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-norwood.c b/drivers/media/rc/keymaps/rc-norwood.c index 9e65f07..ca1b82a 100644 --- a/drivers/media/rc/keymaps/rc-norwood.c +++ b/drivers/media/rc/keymaps/rc-norwood.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -83,4 +83,4 @@ module_init(init_rc_map_norwood) module_exit(exit_rc_map_norwood) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-npgtech.c b/drivers/media/rc/keymaps/rc-npgtech.c index 65d0cfc..1fb9460 100644 --- a/drivers/media/rc/keymaps/rc-npgtech.c +++ b/drivers/media/rc/keymaps/rc-npgtech.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -78,4 +78,4 @@ module_init(init_rc_map_npgtech) module_exit(exit_rc_map_npgtech) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pctv-sedna.c b/drivers/media/rc/keymaps/rc-pctv-sedna.c index bf2cbdf..5ef01ab 100644 --- a/drivers/media/rc/keymaps/rc-pctv-sedna.c +++ b/drivers/media/rc/keymaps/rc-pctv-sedna.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -78,4 +78,4 @@ module_init(init_rc_map_pctv_sedna) module_exit(exit_rc_map_pctv_sedna) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pinnacle-color.c b/drivers/media/rc/keymaps/rc-pinnacle-color.c index b46cd8f..a218b47 100644 --- a/drivers/media/rc/keymaps/rc-pinnacle-color.c +++ b/drivers/media/rc/keymaps/rc-pinnacle-color.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -92,4 +92,4 @@ module_init(init_rc_map_pinnacle_color) module_exit(exit_rc_map_pinnacle_color) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pinnacle-grey.c b/drivers/media/rc/keymaps/rc-pinnacle-grey.c index d525df9..4a3f467 100644 --- a/drivers/media/rc/keymaps/rc-pinnacle-grey.c +++ b/drivers/media/rc/keymaps/rc-pinnacle-grey.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -87,4 +87,4 @@ module_init(init_rc_map_pinnacle_grey) module_exit(exit_rc_map_pinnacle_grey) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pinnacle-pctv-hd.c b/drivers/media/rc/keymaps/rc-pinnacle-pctv-hd.c index a4603d0..e89cc10 100644 --- a/drivers/media/rc/keymaps/rc-pinnacle-pctv-hd.c +++ b/drivers/media/rc/keymaps/rc-pinnacle-pctv-hd.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -68,4 +68,4 @@ module_init(init_rc_map_pinnacle_pctv_hd) module_exit(exit_rc_map_pinnacle_pctv_hd) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pixelview-002t.c b/drivers/media/rc/keymaps/rc-pixelview-002t.c index 33eb643..d967c38 100644 --- a/drivers/media/rc/keymaps/rc-pixelview-002t.c +++ b/drivers/media/rc/keymaps/rc-pixelview-002t.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -75,4 +75,4 @@ module_init(init_rc_map_pixelview) module_exit(exit_rc_map_pixelview) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pixelview-mk12.c b/drivers/media/rc/keymaps/rc-pixelview-mk12.c index 21f4dd2..224d0ef 100644 --- a/drivers/media/rc/keymaps/rc-pixelview-mk12.c +++ b/drivers/media/rc/keymaps/rc-pixelview-mk12.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -81,4 +81,4 @@ module_init(init_rc_map_pixelview) module_exit(exit_rc_map_pixelview) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pixelview-new.c b/drivers/media/rc/keymaps/rc-pixelview-new.c index f944ad2..781d788 100644 --- a/drivers/media/rc/keymaps/rc-pixelview-new.c +++ b/drivers/media/rc/keymaps/rc-pixelview-new.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -81,4 +81,4 @@ module_init(init_rc_map_pixelview_new) module_exit(exit_rc_map_pixelview_new) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pixelview.c b/drivers/media/rc/keymaps/rc-pixelview.c index a6020ee..39e6fea 100644 --- a/drivers/media/rc/keymaps/rc-pixelview.c +++ b/drivers/media/rc/keymaps/rc-pixelview.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -80,4 +80,4 @@ module_init(init_rc_map_pixelview) module_exit(exit_rc_map_pixelview) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-powercolor-real-angel.c b/drivers/media/rc/keymaps/rc-powercolor-real-angel.c index e74c571..e96fa3a 100644 --- a/drivers/media/rc/keymaps/rc-powercolor-real-angel.c +++ b/drivers/media/rc/keymaps/rc-powercolor-real-angel.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -79,4 +79,4 @@ module_init(init_rc_map_powercolor_real_angel) module_exit(exit_rc_map_powercolor_real_angel) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-proteus-2309.c b/drivers/media/rc/keymaps/rc-proteus-2309.c index adee803..eef626e 100644 --- a/drivers/media/rc/keymaps/rc-proteus-2309.c +++ b/drivers/media/rc/keymaps/rc-proteus-2309.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -67,4 +67,4 @@ module_init(init_rc_map_proteus_2309) module_exit(exit_rc_map_proteus_2309) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-purpletv.c b/drivers/media/rc/keymaps/rc-purpletv.c index 722597a..cec6fe4 100644 --- a/drivers/media/rc/keymaps/rc-purpletv.c +++ b/drivers/media/rc/keymaps/rc-purpletv.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -79,4 +79,4 @@ module_init(init_rc_map_purpletv) module_exit(exit_rc_map_purpletv) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-pv951.c b/drivers/media/rc/keymaps/rc-pv951.c index 0105d63..5ac89ce 100644 --- a/drivers/media/rc/keymaps/rc-pv951.c +++ b/drivers/media/rc/keymaps/rc-pv951.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,4 +76,4 @@ module_init(init_rc_map_pv951) module_exit(exit_rc_map_pv951) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-real-audio-220-32-keys.c b/drivers/media/rc/keymaps/rc-real-audio-220-32-keys.c index 073694d..9f778bd 100644 --- a/drivers/media/rc/keymaps/rc-real-audio-220-32-keys.c +++ b/drivers/media/rc/keymaps/rc-real-audio-220-32-keys.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,4 +76,4 @@ module_init(init_rc_map_real_audio_220_32_keys) module_exit(exit_rc_map_real_audio_220_32_keys) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-tbs-nec.c b/drivers/media/rc/keymaps/rc-tbs-nec.c index 5039be7..24ce2a2 100644 --- a/drivers/media/rc/keymaps/rc-tbs-nec.c +++ b/drivers/media/rc/keymaps/rc-tbs-nec.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -73,4 +73,4 @@ module_init(init_rc_map_tbs_nec) module_exit(exit_rc_map_tbs_nec) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-terratec-cinergy-xs.c b/drivers/media/rc/keymaps/rc-terratec-cinergy-xs.c index 53629fb..97eb83a 100644 --- a/drivers/media/rc/keymaps/rc-terratec-cinergy-xs.c +++ b/drivers/media/rc/keymaps/rc-terratec-cinergy-xs.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -90,4 +90,4 @@ module_init(init_rc_map_terratec_cinergy_xs) module_exit(exit_rc_map_terratec_cinergy_xs) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-tevii-nec.c b/drivers/media/rc/keymaps/rc-tevii-nec.c index f2c3b75..38e0c08 100644 --- a/drivers/media/rc/keymaps/rc-tevii-nec.c +++ b/drivers/media/rc/keymaps/rc-tevii-nec.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -86,4 +86,4 @@ module_init(init_rc_map_tevii_nec) module_exit(exit_rc_map_tevii_nec) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-tivo.c b/drivers/media/rc/keymaps/rc-tivo.c index 454e062..5cc1b45 100644 --- a/drivers/media/rc/keymaps/rc-tivo.c +++ b/drivers/media/rc/keymaps/rc-tivo.c @@ -15,62 +15,62 @@ * Initial mapping is for the TiVo remote included in the Nero LiquidTV bundle, * which also ships with a TiVo-branded IR transceiver, supported by the mceusb * driver. Note that the remote uses an NEC-ish protocol, but instead of having - * a command/not_command pair, it has a vendor ID of 0xa10c, but some keys, the + * a command/not_command pair, it has a vendor ID of 0x3085, but some keys, the * NEC extended checksums do pass, so the table presently has the intended * values and the checksum-passed versions for those keys. */ static struct rc_map_table tivo[] = { - { 0xa10c900f, KEY_MEDIA }, /* TiVo Button */ - { 0xa10c0807, KEY_POWER2 }, /* TV Power */ - { 0xa10c8807, KEY_TV }, /* Live TV/Swap */ - { 0xa10c2c03, KEY_VIDEO_NEXT }, /* TV Input */ - { 0xa10cc807, KEY_INFO }, - { 0xa10cfa05, KEY_CYCLEWINDOWS }, /* Window */ + { 0x3085f009, KEY_MEDIA }, /* TiVo Button */ + { 0x3085e010, KEY_POWER2 }, /* TV Power */ + { 0x3085e011, KEY_TV }, /* Live TV/Swap */ + { 0x3085c034, KEY_VIDEO_NEXT }, /* TV Input */ + { 0x3085e013, KEY_INFO }, + { 0x3085a05f, KEY_CYCLEWINDOWS }, /* Window */ { 0x0085305f, KEY_CYCLEWINDOWS }, - { 0xa10c6c03, KEY_EPG }, /* Guide */ + { 0x3085c036, KEY_EPG }, /* Guide */ - { 0xa10c2807, KEY_UP }, - { 0xa10c6807, KEY_DOWN }, - { 0xa10ce807, KEY_LEFT }, - { 0xa10ca807, KEY_RIGHT }, + { 0x3085e014, KEY_UP }, + { 0x3085e016, KEY_DOWN }, + { 0x3085e017, KEY_LEFT }, + { 0x3085e015, KEY_RIGHT }, - { 0xa10c1807, KEY_SCROLLDOWN }, /* Red Thumbs Down */ - { 0xa10c9807, KEY_SELECT }, - { 0xa10c5807, KEY_SCROLLUP }, /* Green Thumbs Up */ + { 0x3085e018, KEY_SCROLLDOWN }, /* Red Thumbs Down */ + { 0x3085e019, KEY_SELECT }, + { 0x3085e01a, KEY_SCROLLUP }, /* Green Thumbs Up */ - { 0xa10c3807, KEY_VOLUMEUP }, - { 0xa10cb807, KEY_VOLUMEDOWN }, - { 0xa10cd807, KEY_MUTE }, - { 0xa10c040b, KEY_RECORD }, - { 0xa10c7807, KEY_CHANNELUP }, - { 0xa10cf807, KEY_CHANNELDOWN }, + { 0x3085e01c, KEY_VOLUMEUP }, + { 0x3085e01d, KEY_VOLUMEDOWN }, + { 0x3085e01b, KEY_MUTE }, + { 0x3085d020, KEY_RECORD }, + { 0x3085e01e, KEY_CHANNELUP }, + { 0x3085e01f, KEY_CHANNELDOWN }, { 0x0085301f, KEY_CHANNELDOWN }, - { 0xa10c840b, KEY_PLAY }, - { 0xa10cc40b, KEY_PAUSE }, - { 0xa10ca40b, KEY_SLOW }, - { 0xa10c440b, KEY_REWIND }, - { 0xa10c240b, KEY_FASTFORWARD }, - { 0xa10c640b, KEY_PREVIOUS }, - { 0xa10ce40b, KEY_NEXT }, /* ->| */ + { 0x3085d021, KEY_PLAY }, + { 0x3085d023, KEY_PAUSE }, + { 0x3085d025, KEY_SLOW }, + { 0x3085d022, KEY_REWIND }, + { 0x3085d024, KEY_FASTFORWARD }, + { 0x3085d026, KEY_PREVIOUS }, + { 0x3085d027, KEY_NEXT }, /* ->| */ - { 0xa10c220d, KEY_ZOOM }, /* Aspect */ - { 0xa10c120d, KEY_STOP }, - { 0xa10c520d, KEY_DVD }, /* DVD Menu */ + { 0x3085b044, KEY_ZOOM }, /* Aspect */ + { 0x3085b048, KEY_STOP }, + { 0x3085b04a, KEY_DVD }, /* DVD Menu */ - { 0xa10c140b, KEY_NUMERIC_1 }, - { 0xa10c940b, KEY_NUMERIC_2 }, - { 0xa10c540b, KEY_NUMERIC_3 }, - { 0xa10cd40b, KEY_NUMERIC_4 }, - { 0xa10c340b, KEY_NUMERIC_5 }, - { 0xa10cb40b, KEY_NUMERIC_6 }, - { 0xa10c740b, KEY_NUMERIC_7 }, - { 0xa10cf40b, KEY_NUMERIC_8 }, + { 0x3085d028, KEY_NUMERIC_1 }, + { 0x3085d029, KEY_NUMERIC_2 }, + { 0x3085d02a, KEY_NUMERIC_3 }, + { 0x3085d02b, KEY_NUMERIC_4 }, + { 0x3085d02c, KEY_NUMERIC_5 }, + { 0x3085d02d, KEY_NUMERIC_6 }, + { 0x3085d02e, KEY_NUMERIC_7 }, + { 0x3085d02f, KEY_NUMERIC_8 }, { 0x0085302f, KEY_NUMERIC_8 }, - { 0xa10c0c03, KEY_NUMERIC_9 }, - { 0xa10c8c03, KEY_NUMERIC_0 }, - { 0xa10ccc03, KEY_ENTER }, - { 0xa10c4c03, KEY_CLEAR }, + { 0x3085c030, KEY_NUMERIC_9 }, + { 0x3085c031, KEY_NUMERIC_0 }, + { 0x3085c033, KEY_ENTER }, + { 0x3085c032, KEY_CLEAR }, }; static struct rc_map_list tivo_map = { diff --git a/drivers/media/rc/keymaps/rc-tt-1500.c b/drivers/media/rc/keymaps/rc-tt-1500.c index 80217ff..c766d3b 100644 --- a/drivers/media/rc/keymaps/rc-tt-1500.c +++ b/drivers/media/rc/keymaps/rc-tt-1500.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -80,4 +80,4 @@ module_init(init_rc_map_tt_1500) module_exit(exit_rc_map_tt_1500) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-videomate-s350.c b/drivers/media/rc/keymaps/rc-videomate-s350.c index 8bfc3e8..8a35477 100644 --- a/drivers/media/rc/keymaps/rc-videomate-s350.c +++ b/drivers/media/rc/keymaps/rc-videomate-s350.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -83,4 +83,4 @@ module_init(init_rc_map_videomate_s350) module_exit(exit_rc_map_videomate_s350) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-videomate-tv-pvr.c b/drivers/media/rc/keymaps/rc-videomate-tv-pvr.c index 390ce94..eb0cda7 100644 --- a/drivers/media/rc/keymaps/rc-videomate-tv-pvr.c +++ b/drivers/media/rc/keymaps/rc-videomate-tv-pvr.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -85,4 +85,4 @@ module_init(init_rc_map_videomate_tv_pvr) module_exit(exit_rc_map_videomate_tv_pvr) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-winfast-usbii-deluxe.c b/drivers/media/rc/keymaps/rc-winfast-usbii-deluxe.c index 2852bf7..c1dd598 100644 --- a/drivers/media/rc/keymaps/rc-winfast-usbii-deluxe.c +++ b/drivers/media/rc/keymaps/rc-winfast-usbii-deluxe.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -80,4 +80,4 @@ module_init(init_rc_map_winfast_usbii_deluxe) module_exit(exit_rc_map_winfast_usbii_deluxe) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/keymaps/rc-winfast.c b/drivers/media/rc/keymaps/rc-winfast.c index 2df1cba..8a779da 100644 --- a/drivers/media/rc/keymaps/rc-winfast.c +++ b/drivers/media/rc/keymaps/rc-winfast.c @@ -2,7 +2,7 @@ * * keymap imported from ir-keymaps.c * - * Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -100,4 +100,4 @@ module_init(init_rc_map_winfast) module_exit(exit_rc_map_winfast) MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); diff --git a/drivers/media/rc/mceusb.c b/drivers/media/rc/mceusb.c index a25bb15..5d8f3d4 100644 --- a/drivers/media/rc/mceusb.c +++ b/drivers/media/rc/mceusb.c @@ -84,7 +84,7 @@ #define MCE_PORT_IR 0x4 /* (0x4 << 5) | MCE_CMD = 0x9f */ #define MCE_PORT_SYS 0x7 /* (0x7 << 5) | MCE_CMD = 0xff */ #define MCE_PORT_SER 0x6 /* 0xc0 thru 0xdf flush & 0x1f bytes */ -#define MCE_PORT_MASK 0xe0 /* Mask out command bits */ +#define MCE_PORT_MASK 0xe0 /* Mask out command bits */ /* Command port headers */ #define MCE_CMD_PORT_IR 0x9f /* IR-related cmd/rsp */ @@ -153,19 +153,6 @@ #define MCE_COMMAND_IRDATA 0x80 #define MCE_PACKET_LENGTH_MASK 0x1f /* Packet length mask */ -/* module parameters */ -#ifdef CONFIG_USB_DEBUG -static bool debug = 1; -#else -static bool debug; -#endif - -#define mce_dbg(dev, fmt, ...) \ - do { \ - if (debug) \ - dev_info(dev, fmt, ## __VA_ARGS__); \ - } while (0) - /* general constants */ #define SEND_FLAG_IN_PROGRESS 1 #define SEND_FLAG_COMPLETE 2 @@ -541,16 +528,13 @@ static int mceusb_cmd_datasize(u8 cmd, u8 subcmd) static void mceusb_dev_printdata(struct mceusb_dev *ir, char *buf, int offset, int len, bool out) { - char codes[USB_BUFLEN * 3 + 1]; - char inout[9]; +#if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) + char *inout; u8 cmd, subcmd, data1, data2, data3, data4; struct device *dev = ir->dev; - int i, start, skip = 0; + int start, skip = 0; u32 carrier, period; - if (!debug) - return; - /* skip meaningless 0xb1 0x60 header bytes on orig receiver */ if (ir->flags.microsoft_gen1 && !out && !offset) skip = 2; @@ -558,16 +542,10 @@ static void mceusb_dev_printdata(struct mceusb_dev *ir, char *buf, if (len <= skip) return; - for (i = 0; i < len && i < USB_BUFLEN; i++) - snprintf(codes + i * 3, 4, "%02x ", buf[i + offset] & 0xff); - - dev_info(dev, "%sx data: %s(length=%d)\n", - (out ? "t" : "r"), codes, len); + dev_dbg(dev, "%cx data: %*ph (length=%d)", + (out ? 't' : 'r'), min(len, USB_BUFLEN), buf, len); - if (out) - strcpy(inout, "Request\0"); - else - strcpy(inout, "Got\0"); + inout = out ? "Request" : "Got"; start = offset + skip; cmd = buf[start] & 0xff; @@ -583,50 +561,50 @@ static void mceusb_dev_printdata(struct mceusb_dev *ir, char *buf, break; if ((subcmd == MCE_CMD_PORT_SYS) && (data1 == MCE_CMD_RESUME)) - dev_info(dev, "Device resume requested\n"); + dev_dbg(dev, "Device resume requested"); else - dev_info(dev, "Unknown command 0x%02x 0x%02x\n", + dev_dbg(dev, "Unknown command 0x%02x 0x%02x", cmd, subcmd); break; case MCE_CMD_PORT_SYS: switch (subcmd) { case MCE_RSP_EQEMVER: if (!out) - dev_info(dev, "Emulator interface version %x\n", + dev_dbg(dev, "Emulator interface version %x", data1); break; case MCE_CMD_G_REVISION: if (len == 2) - dev_info(dev, "Get hw/sw rev?\n"); + dev_dbg(dev, "Get hw/sw rev?"); else - dev_info(dev, "hw/sw rev 0x%02x 0x%02x " - "0x%02x 0x%02x\n", data1, data2, + dev_dbg(dev, "hw/sw rev 0x%02x 0x%02x 0x%02x 0x%02x", + data1, data2, buf[start + 4], buf[start + 5]); break; case MCE_CMD_RESUME: - dev_info(dev, "Device resume requested\n"); + dev_dbg(dev, "Device resume requested"); break; case MCE_RSP_CMD_ILLEGAL: - dev_info(dev, "Illegal PORT_SYS command\n"); + dev_dbg(dev, "Illegal PORT_SYS command"); break; case MCE_RSP_EQWAKEVERSION: if (!out) - dev_info(dev, "Wake version, proto: 0x%02x, " + dev_dbg(dev, "Wake version, proto: 0x%02x, " "payload: 0x%02x, address: 0x%02x, " - "version: 0x%02x\n", + "version: 0x%02x", data1, data2, data3, data4); break; case MCE_RSP_GETPORTSTATUS: if (!out) /* We use data1 + 1 here, to match hw labels */ - dev_info(dev, "TX port %d: blaster is%s connected\n", + dev_dbg(dev, "TX port %d: blaster is%s connected", data1 + 1, data4 ? " not" : ""); break; case MCE_CMD_FLASHLED: - dev_info(dev, "Attempting to flash LED\n"); + dev_dbg(dev, "Attempting to flash LED"); break; default: - dev_info(dev, "Unknown command 0x%02x 0x%02x\n", + dev_dbg(dev, "Unknown command 0x%02x 0x%02x", cmd, subcmd); break; } @@ -634,13 +612,13 @@ static void mceusb_dev_printdata(struct mceusb_dev *ir, char *buf, case MCE_CMD_PORT_IR: switch (subcmd) { case MCE_CMD_SIG_END: - dev_info(dev, "End of signal\n"); + dev_dbg(dev, "End of signal"); break; case MCE_CMD_PING: - dev_info(dev, "Ping\n"); + dev_dbg(dev, "Ping"); break; case MCE_CMD_UNKNOWN: - dev_info(dev, "Resp to 9f 05 of 0x%02x 0x%02x\n", + dev_dbg(dev, "Resp to 9f 05 of 0x%02x 0x%02x", data1, data2); break; case MCE_RSP_EQIRCFS: @@ -649,51 +627,51 @@ static void mceusb_dev_printdata(struct mceusb_dev *ir, char *buf, if (!period) break; carrier = (1000 * 1000) / period; - dev_info(dev, "%s carrier of %u Hz (period %uus)\n", + dev_dbg(dev, "%s carrier of %u Hz (period %uus)", inout, carrier, period); break; case MCE_CMD_GETIRCFS: - dev_info(dev, "Get carrier mode and freq\n"); + dev_dbg(dev, "Get carrier mode and freq"); break; case MCE_RSP_EQIRTXPORTS: - dev_info(dev, "%s transmit blaster mask of 0x%02x\n", + dev_dbg(dev, "%s transmit blaster mask of 0x%02x", inout, data1); break; case MCE_RSP_EQIRTIMEOUT: /* value is in units of 50us, so x*50/1000 ms */ period = ((data1 << 8) | data2) * MCE_TIME_UNIT / 1000; - dev_info(dev, "%s receive timeout of %d ms\n", + dev_dbg(dev, "%s receive timeout of %d ms", inout, period); break; case MCE_CMD_GETIRTIMEOUT: - dev_info(dev, "Get receive timeout\n"); + dev_dbg(dev, "Get receive timeout"); break; case MCE_CMD_GETIRTXPORTS: - dev_info(dev, "Get transmit blaster mask\n"); + dev_dbg(dev, "Get transmit blaster mask"); break; case MCE_RSP_EQIRRXPORTEN: - dev_info(dev, "%s %s-range receive sensor in use\n", + dev_dbg(dev, "%s %s-range receive sensor in use", inout, data1 == 0x02 ? "short" : "long"); break; case MCE_CMD_GETIRRXPORTEN: /* aka MCE_RSP_EQIRRXCFCNT */ if (out) - dev_info(dev, "Get receive sensor\n"); + dev_dbg(dev, "Get receive sensor"); else if (ir->learning_enabled) - dev_info(dev, "RX pulse count: %d\n", + dev_dbg(dev, "RX pulse count: %d", ((data1 << 8) | data2)); break; case MCE_RSP_EQIRNUMPORTS: if (out) break; - dev_info(dev, "Num TX ports: %x, num RX ports: %x\n", + dev_dbg(dev, "Num TX ports: %x, num RX ports: %x", data1, data2); break; case MCE_RSP_CMD_ILLEGAL: - dev_info(dev, "Illegal PORT_IR command\n"); + dev_dbg(dev, "Illegal PORT_IR command"); break; default: - dev_info(dev, "Unknown command 0x%02x 0x%02x\n", + dev_dbg(dev, "Unknown command 0x%02x 0x%02x", cmd, subcmd); break; } @@ -703,10 +681,11 @@ static void mceusb_dev_printdata(struct mceusb_dev *ir, char *buf, } if (cmd == MCE_IRDATA_TRAILER) - dev_info(dev, "End of raw IR data\n"); + dev_dbg(dev, "End of raw IR data"); else if ((cmd != MCE_CMD_PORT_IR) && ((cmd & MCE_PORT_MASK) == MCE_COMMAND_IRDATA)) - dev_info(dev, "Raw IR data, %d pulse/space samples\n", ir->rem); + dev_dbg(dev, "Raw IR data, %d pulse/space samples", ir->rem); +#endif } static void mce_async_callback(struct urb *urb) @@ -718,10 +697,25 @@ static void mce_async_callback(struct urb *urb) return; ir = urb->context; - if (ir) { + + switch (urb->status) { + /* success */ + case 0: len = urb->actual_length; mceusb_dev_printdata(ir, urb->transfer_buffer, 0, len, true); + break; + + case -ECONNRESET: + case -ENOENT: + case -EILSEQ: + case -ESHUTDOWN: + break; + + case -EPIPE: + default: + dev_err(ir->dev, "Error: request urb status = %d", urb->status); + break; } /* the transfer buffer and urb were allocated in mce_request_packet */ @@ -770,17 +764,17 @@ static void mce_request_packet(struct mceusb_dev *ir, unsigned char *data, return; } - mce_dbg(dev, "receive request called (size=%#x)\n", size); + dev_dbg(dev, "receive request called (size=%#x)", size); async_urb->transfer_buffer_length = size; async_urb->dev = ir->usbdev; res = usb_submit_urb(async_urb, GFP_ATOMIC); if (res) { - mce_dbg(dev, "receive request FAILED! (res=%d)\n", res); + dev_err(dev, "receive request FAILED! (res=%d)", res); return; } - mce_dbg(dev, "receive request complete (res=%d)\n", res); + dev_dbg(dev, "receive request complete (res=%d)", res); } static void mce_async_out(struct mceusb_dev *ir, unsigned char *data, int size) @@ -895,8 +889,7 @@ static int mceusb_set_tx_carrier(struct rc_dev *dev, u32 carrier) ir->carrier = carrier; cmdbuf[2] = MCE_CMD_SIG_END; cmdbuf[3] = MCE_IRDATA_TRAILER; - mce_dbg(ir->dev, "%s: disabling carrier " - "modulation\n", __func__); + dev_dbg(ir->dev, "disabling carrier modulation"); mce_async_out(ir, cmdbuf, sizeof(cmdbuf)); return carrier; } @@ -907,8 +900,8 @@ static int mceusb_set_tx_carrier(struct rc_dev *dev, u32 carrier) ir->carrier = carrier; cmdbuf[2] = prescaler; cmdbuf[3] = divisor; - mce_dbg(ir->dev, "%s: requesting %u HZ " - "carrier\n", __func__, carrier); + dev_dbg(ir->dev, "requesting %u HZ carrier", + carrier); /* Transmit new carrier to mce device */ mce_async_out(ir, cmdbuf, sizeof(cmdbuf)); @@ -998,7 +991,7 @@ static void mceusb_process_ir_data(struct mceusb_dev *ir, int buf_len) rawir.duration = (ir->buf_in[i] & MCE_PULSE_MASK) * US_TO_NS(MCE_TIME_UNIT); - mce_dbg(ir->dev, "Storing %s with duration %d\n", + dev_dbg(ir->dev, "Storing %s with duration %d", rawir.pulse ? "pulse" : "space", rawir.duration); @@ -1032,7 +1025,7 @@ static void mceusb_process_ir_data(struct mceusb_dev *ir, int buf_len) ir->parser_state = CMD_HEADER; } if (event) { - mce_dbg(ir->dev, "processed IR data, calling ir_raw_event_handle\n"); + dev_dbg(ir->dev, "processed IR data"); ir_raw_event_handle(ir->rc); } } @@ -1055,7 +1048,7 @@ static void mceusb_dev_recv(struct urb *urb) if (ir->send_flags == RECV_FLAG_IN_PROGRESS) { ir->send_flags = SEND_FLAG_COMPLETE; - mce_dbg(ir->dev, "setup answer received %d bytes\n", + dev_dbg(ir->dev, "setup answer received %d bytes\n", buf_len); } @@ -1067,13 +1060,14 @@ static void mceusb_dev_recv(struct urb *urb) case -ECONNRESET: case -ENOENT: + case -EILSEQ: case -ESHUTDOWN: usb_unlink_urb(urb); return; case -EPIPE: default: - mce_dbg(ir->dev, "Error: urb status = %d\n", urb->status); + dev_err(ir->dev, "Error: urb status = %d", urb->status); break; } @@ -1095,7 +1089,7 @@ static void mceusb_gen1_init(struct mceusb_dev *ir) data = kzalloc(USB_CTRL_MSG_SZ, GFP_KERNEL); if (!data) { - dev_err(dev, "%s: memory allocation failed!\n", __func__); + dev_err(dev, "%s: memory allocation failed!", __func__); return; } @@ -1106,28 +1100,28 @@ static void mceusb_gen1_init(struct mceusb_dev *ir) ret = usb_control_msg(ir->usbdev, usb_rcvctrlpipe(ir->usbdev, 0), USB_REQ_SET_ADDRESS, USB_TYPE_VENDOR, 0, 0, data, USB_CTRL_MSG_SZ, HZ * 3); - mce_dbg(dev, "%s - ret = %d\n", __func__, ret); - mce_dbg(dev, "%s - data[0] = %d, data[1] = %d\n", - __func__, data[0], data[1]); + dev_dbg(dev, "set address - ret = %d", ret); + dev_dbg(dev, "set address - data[0] = %d, data[1] = %d", + data[0], data[1]); /* set feature: bit rate 38400 bps */ ret = usb_control_msg(ir->usbdev, usb_sndctrlpipe(ir->usbdev, 0), USB_REQ_SET_FEATURE, USB_TYPE_VENDOR, 0xc04e, 0x0000, NULL, 0, HZ * 3); - mce_dbg(dev, "%s - ret = %d\n", __func__, ret); + dev_dbg(dev, "set feature - ret = %d", ret); /* bRequest 4: set char length to 8 bits */ ret = usb_control_msg(ir->usbdev, usb_sndctrlpipe(ir->usbdev, 0), 4, USB_TYPE_VENDOR, 0x0808, 0x0000, NULL, 0, HZ * 3); - mce_dbg(dev, "%s - retB = %d\n", __func__, ret); + dev_dbg(dev, "set char length - retB = %d", ret); /* bRequest 2: set handshaking to use DTR/DSR */ ret = usb_control_msg(ir->usbdev, usb_sndctrlpipe(ir->usbdev, 0), 2, USB_TYPE_VENDOR, 0x0000, 0x0100, NULL, 0, HZ * 3); - mce_dbg(dev, "%s - retC = %d\n", __func__, ret); + dev_dbg(dev, "set handshake - retC = %d", ret); /* device resume */ mce_async_out(ir, DEVICE_RESUME, sizeof(DEVICE_RESUME)); @@ -1198,7 +1192,7 @@ static struct rc_dev *mceusb_init_rc_dev(struct mceusb_dev *ir) rc = rc_allocate_device(); if (!rc) { - dev_err(dev, "remote dev allocation failed\n"); + dev_err(dev, "remote dev allocation failed"); goto out; } @@ -1217,7 +1211,7 @@ static struct rc_dev *mceusb_init_rc_dev(struct mceusb_dev *ir) rc->dev.parent = dev; rc->priv = ir; rc->driver_type = RC_DRIVER_IR_RAW; - rc->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rc, RC_BIT_ALL); rc->timeout = MS_TO_NS(100); if (!ir->flags.no_tx) { rc->s_tx_mask = mceusb_set_tx_mask; @@ -1230,7 +1224,7 @@ static struct rc_dev *mceusb_init_rc_dev(struct mceusb_dev *ir) ret = rc_register_device(rc); if (ret < 0) { - dev_err(dev, "remote dev registration failed\n"); + dev_err(dev, "remote dev registration failed"); goto out; } @@ -1258,7 +1252,7 @@ static int mceusb_dev_probe(struct usb_interface *intf, bool tx_mask_normal; int ir_intfnum; - mce_dbg(&intf->dev, "%s called\n", __func__); + dev_dbg(&intf->dev, "%s called", __func__); idesc = intf->cur_altsetting; @@ -1286,8 +1280,7 @@ static int mceusb_dev_probe(struct usb_interface *intf, ep_in = ep; ep_in->bmAttributes = USB_ENDPOINT_XFER_INT; ep_in->bInterval = 1; - mce_dbg(&intf->dev, "acceptable inbound endpoint " - "found\n"); + dev_dbg(&intf->dev, "acceptable inbound endpoint found"); } if ((ep_out == NULL) @@ -1301,12 +1294,11 @@ static int mceusb_dev_probe(struct usb_interface *intf, ep_out = ep; ep_out->bmAttributes = USB_ENDPOINT_XFER_INT; ep_out->bInterval = 1; - mce_dbg(&intf->dev, "acceptable outbound endpoint " - "found\n"); + dev_dbg(&intf->dev, "acceptable outbound endpoint found"); } } if (ep_in == NULL) { - mce_dbg(&intf->dev, "inbound and/or endpoint not found\n"); + dev_dbg(&intf->dev, "inbound and/or endpoint not found"); return -ENODEV; } @@ -1357,7 +1349,7 @@ static int mceusb_dev_probe(struct usb_interface *intf, ir->urb_in->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; /* flush buffers on the device */ - mce_dbg(&intf->dev, "Flushing receive buffers\n"); + dev_dbg(&intf->dev, "Flushing receive buffers\n"); mce_flush_rx_buffer(ir, maxp); /* figure out which firmware/emulator version this hardware has */ @@ -1382,10 +1374,9 @@ static int mceusb_dev_probe(struct usb_interface *intf, device_set_wakeup_capable(ir->dev, true); device_set_wakeup_enable(ir->dev, true); - dev_info(&intf->dev, "Registered %s with mce emulator interface " - "version %x\n", name, ir->emver); - dev_info(&intf->dev, "%x tx ports (0x%x cabled) and " - "%x rx sensors (0x%x active)\n", + dev_info(&intf->dev, "Registered %s with mce emulator interface version %x", + name, ir->emver); + dev_info(&intf->dev, "%x tx ports (0x%x cabled) and %x rx sensors (0x%x active)", ir->num_txports, ir->txports_cabled, ir->num_rxports, ir->rxports_active); @@ -1399,7 +1390,7 @@ urb_in_alloc_fail: buf_in_alloc_fail: kfree(ir); mem_alloc_fail: - dev_err(&intf->dev, "%s: device setup failed!\n", __func__); + dev_err(&intf->dev, "%s: device setup failed!", __func__); return -ENOMEM; } @@ -1427,7 +1418,7 @@ static void mceusb_dev_disconnect(struct usb_interface *intf) static int mceusb_dev_suspend(struct usb_interface *intf, pm_message_t message) { struct mceusb_dev *ir = usb_get_intfdata(intf); - dev_info(ir->dev, "suspend\n"); + dev_info(ir->dev, "suspend"); usb_kill_urb(ir->urb_in); return 0; } @@ -1435,7 +1426,7 @@ static int mceusb_dev_suspend(struct usb_interface *intf, pm_message_t message) static int mceusb_dev_resume(struct usb_interface *intf) { struct mceusb_dev *ir = usb_get_intfdata(intf); - dev_info(ir->dev, "resume\n"); + dev_info(ir->dev, "resume"); if (usb_submit_urb(ir->urb_in, GFP_ATOMIC)) return -EIO; return 0; @@ -1457,6 +1448,3 @@ MODULE_DESCRIPTION(DRIVER_DESC); MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(usb, mceusb_dev_table); - -module_param(debug, bool, S_IRUGO | S_IWUSR); -MODULE_PARM_DESC(debug, "Debug enabled or not"); diff --git a/drivers/media/rc/nuvoton-cir.c b/drivers/media/rc/nuvoton-cir.c index 21ee0dc..d244e1a 100644 --- a/drivers/media/rc/nuvoton-cir.c +++ b/drivers/media/rc/nuvoton-cir.c @@ -330,9 +330,6 @@ static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt) /* Enable CIR Wake via PSOUT# (Pin60) */ nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); - /* enable cir interrupt of mouse/keyboard IRQ event */ - nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS); - /* enable pme interrupt of cir wakeup event */ nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); @@ -456,7 +453,6 @@ static void nvt_enable_wake(struct nvt_dev *nvt) nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); - nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS); nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); @@ -989,6 +985,12 @@ static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) goto exit_free_dev_rdev; ret = -ENODEV; + /* activate pnp device */ + if (pnp_activate_dev(pdev) < 0) { + dev_err(&pdev->dev, "Could not activate PNP device!\n"); + goto exit_free_dev_rdev; + } + /* validate pnp resources */ if (!pnp_port_valid(pdev, 0) || pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) { @@ -1042,7 +1044,7 @@ static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) /* Set up the rc device */ rdev->priv = nvt; rdev->driver_type = RC_DRIVER_IR_RAW; - rdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rdev, RC_BIT_ALL); rdev->open = nvt_open; rdev->close = nvt_close; rdev->tx_ir = nvt_tx_ir; diff --git a/drivers/media/rc/nuvoton-cir.h b/drivers/media/rc/nuvoton-cir.h index 07e8310..e1cf23c 100644 --- a/drivers/media/rc/nuvoton-cir.h +++ b/drivers/media/rc/nuvoton-cir.h @@ -363,7 +363,6 @@ struct nvt_dev { #define LOGICAL_DEV_ENABLE 0x01 #define CIR_WAKE_ENABLE_BIT 0x08 -#define CIR_INTR_MOUSE_IRQ_BIT 0x80 #define PME_INTR_CIR_PASS_BIT 0x08 /* w83677hg CIR pin config */ diff --git a/drivers/media/rc/rc-core-priv.h b/drivers/media/rc/rc-core-priv.h index 70a180b..da536c9 100644 --- a/drivers/media/rc/rc-core-priv.h +++ b/drivers/media/rc/rc-core-priv.h @@ -1,7 +1,7 @@ /* * Remote Controller core raw events header * - * Copyright (C) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -88,6 +88,12 @@ struct ir_raw_event_ctrl { unsigned count; u64 bits; } sanyo; + struct sharp_dec { + int state; + unsigned count; + u32 bits; + unsigned int pulse_len; + } sharp; struct mce_kbd_dec { struct input_dev *idev; struct timer_list rx_timeout; @@ -204,6 +210,13 @@ static inline void load_sony_decode(void) { } static inline void load_sanyo_decode(void) { } #endif +/* from ir-sharp-decoder.c */ +#ifdef CONFIG_IR_SHARP_DECODER_MODULE +#define load_sharp_decode() request_module_nowait("ir-sharp-decoder") +#else +static inline void load_sharp_decode(void) { } +#endif + /* from ir-mce_kbd-decoder.c */ #ifdef CONFIG_IR_MCE_KBD_DECODER_MODULE #define load_mce_kbd_decode() request_module_nowait("ir-mce_kbd-decoder") diff --git a/drivers/media/rc/rc-loopback.c b/drivers/media/rc/rc-loopback.c index 53d0282..0a88e0c 100644 --- a/drivers/media/rc/rc-loopback.c +++ b/drivers/media/rc/rc-loopback.c @@ -195,7 +195,7 @@ static int __init loop_init(void) rc->map_name = RC_MAP_EMPTY; rc->priv = &loopdev; rc->driver_type = RC_DRIVER_IR_RAW; - rc->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rc, RC_BIT_ALL); rc->timeout = 100 * 1000 * 1000; /* 100 ms */ rc->min_timeout = 1; rc->max_timeout = UINT_MAX; diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index 02e2f38..99697aa 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -1,6 +1,6 @@ /* rc-main.c - Remote Controller core module * - * Copyright (C) 2009-2010 by Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2009-2010 by Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,7 +24,7 @@ /* Bitmap to store allocated device numbers from 0 to IRRCV_NUM_DEVICES - 1 */ #define IRRCV_NUM_DEVICES 256 -DECLARE_BITMAP(ir_core_dev_number, IRRCV_NUM_DEVICES); +static DECLARE_BITMAP(ir_core_dev_number, IRRCV_NUM_DEVICES); /* Sizes are in bytes, 256 bytes allows for 32 entries on x64 */ #define IR_TAB_MIN_SIZE 256 @@ -62,7 +62,7 @@ struct rc_map *rc_map_get(const char *name) map = seek_rc_map(name); #ifdef MODULE if (!map) { - int rc = request_module(name); + int rc = request_module("%s", name); if (rc < 0) { printk(KERN_ERR "Couldn't load IR keymap %s\n", name); return NULL; @@ -633,6 +633,7 @@ EXPORT_SYMBOL_GPL(rc_repeat); static void ir_do_keydown(struct rc_dev *dev, int scancode, u32 keycode, u8 toggle) { + struct rc_scancode_filter *filter; bool new_event = !dev->keypressed || dev->last_scancode != scancode || dev->last_toggle != toggle; @@ -640,6 +641,11 @@ static void ir_do_keydown(struct rc_dev *dev, int scancode, if (new_event && dev->keypressed) ir_do_keyup(dev, false); + /* Generic scancode filtering */ + filter = &dev->scancode_filters[RC_FILTER_NORMAL]; + if (filter->mask && ((scancode ^ filter->data) & filter->mask)) + return; + input_event(dev->input_dev, EV_MSC, MSC_SCAN, scancode); if (new_event && keycode != KEY_RESERVED) { @@ -653,9 +659,10 @@ static void ir_do_keydown(struct rc_dev *dev, int scancode, "key 0x%04x, scancode 0x%04x\n", dev->input_name, keycode, scancode); input_report_key(dev->input_dev, keycode, 1); + + led_trigger_event(led_feedback, LED_FULL); } - led_trigger_event(led_feedback, LED_FULL); input_sync(dev->input_dev); } @@ -790,18 +797,44 @@ static struct { RC_BIT_SONY20, "sony" }, { RC_BIT_RC5_SZ, "rc-5-sz" }, { RC_BIT_SANYO, "sanyo" }, + { RC_BIT_SHARP, "sharp" }, { RC_BIT_MCE_KBD, "mce_kbd" }, { RC_BIT_LIRC, "lirc" }, }; /** - * show_protocols() - shows the current IR protocol(s) + * struct rc_filter_attribute - Device attribute relating to a filter type. + * @attr: Device attribute. + * @type: Filter type. + * @mask: false for filter value, true for filter mask. + */ +struct rc_filter_attribute { + struct device_attribute attr; + enum rc_filter_type type; + bool mask; +}; +#define to_rc_filter_attr(a) container_of(a, struct rc_filter_attribute, attr) + +#define RC_PROTO_ATTR(_name, _mode, _show, _store, _type) \ + struct rc_filter_attribute dev_attr_##_name = { \ + .attr = __ATTR(_name, _mode, _show, _store), \ + .type = (_type), \ + } +#define RC_FILTER_ATTR(_name, _mode, _show, _store, _type, _mask) \ + struct rc_filter_attribute dev_attr_##_name = { \ + .attr = __ATTR(_name, _mode, _show, _store), \ + .type = (_type), \ + .mask = (_mask), \ + } + +/** + * show_protocols() - shows the current/wakeup IR protocol(s) * @device: the device descriptor * @mattr: the device attribute struct (unused) * @buf: a pointer to the output buffer * * This routine is a callback routine for input read the IR protocol type(s). - * it is trigged by reading /sys/class/rc/rc?/protocols. + * it is trigged by reading /sys/class/rc/rc?/[wakeup_]protocols. * It returns the protocol names of supported protocols. * Enabled protocols are printed in brackets. * @@ -812,6 +845,7 @@ static ssize_t show_protocols(struct device *device, struct device_attribute *mattr, char *buf) { struct rc_dev *dev = to_rc_dev(device); + struct rc_filter_attribute *fattr = to_rc_filter_attr(mattr); u64 allowed, enabled; char *tmp = buf; int i; @@ -822,9 +856,10 @@ static ssize_t show_protocols(struct device *device, mutex_lock(&dev->lock); - enabled = dev->enabled_protocols; - if (dev->driver_type == RC_DRIVER_SCANCODE) - allowed = dev->allowed_protos; + enabled = dev->enabled_protocols[fattr->type]; + if (dev->driver_type == RC_DRIVER_SCANCODE || + fattr->type == RC_FILTER_WAKEUP) + allowed = dev->allowed_protocols[fattr->type]; else if (dev->raw) allowed = ir_raw_get_allowed_protocols(); else { @@ -856,14 +891,14 @@ static ssize_t show_protocols(struct device *device, } /** - * store_protocols() - changes the current IR protocol(s) + * store_protocols() - changes the current/wakeup IR protocol(s) * @device: the device descriptor * @mattr: the device attribute struct (unused) * @buf: a pointer to the input buffer * @len: length of the input buffer * * This routine is for changing the IR protocol type. - * It is trigged by writing to /sys/class/rc/rc?/protocols. + * It is trigged by writing to /sys/class/rc/rc?/[wakeup_]protocols. * Writing "+proto" will add a protocol to the list of enabled protocols. * Writing "-proto" will remove a protocol from the list of enabled protocols. * Writing "proto" will enable only "proto". @@ -880,12 +915,15 @@ static ssize_t store_protocols(struct device *device, size_t len) { struct rc_dev *dev = to_rc_dev(device); + struct rc_filter_attribute *fattr = to_rc_filter_attr(mattr); bool enable, disable; const char *tmp; - u64 type; + u64 old_type, type; u64 mask; int rc, i, count = 0; ssize_t ret; + int (*change_protocol)(struct rc_dev *dev, u64 *rc_type); + struct rc_scancode_filter local_filter, *filter; /* Device is being removed */ if (!dev) @@ -898,7 +936,8 @@ static ssize_t store_protocols(struct device *device, ret = -EINVAL; goto out; } - type = dev->enabled_protocols; + old_type = dev->enabled_protocols[fattr->type]; + type = old_type; while ((tmp = strsep((char **) &data, " \n")) != NULL) { if (!*tmp) @@ -946,8 +985,10 @@ static ssize_t store_protocols(struct device *device, goto out; } - if (dev->change_protocol) { - rc = dev->change_protocol(dev, &type); + change_protocol = (fattr->type == RC_FILTER_NORMAL) + ? dev->change_protocol : dev->change_wakeup_protocol; + if (change_protocol) { + rc = change_protocol(dev, &type); if (rc < 0) { IR_dprintk(1, "Error setting protocols to 0x%llx\n", (long long)type); @@ -956,10 +997,40 @@ static ssize_t store_protocols(struct device *device, } } - dev->enabled_protocols = type; + dev->enabled_protocols[fattr->type] = type; IR_dprintk(1, "Current protocol(s): 0x%llx\n", (long long)type); + /* + * If the protocol is changed the filter needs updating. + * Try setting the same filter with the new protocol (if any). + * Fall back to clearing the filter. + */ + filter = &dev->scancode_filters[fattr->type]; + if (old_type != type && filter->mask) { + local_filter = *filter; + if (!type) { + /* no protocol => clear filter */ + ret = -1; + } else if (!dev->s_filter) { + /* generic filtering => accept any filter */ + ret = 0; + } else { + /* hardware filtering => try setting, otherwise clear */ + ret = dev->s_filter(dev, fattr->type, &local_filter); + } + if (ret < 0) { + /* clear the filter */ + local_filter.data = 0; + local_filter.mask = 0; + if (dev->s_filter) + dev->s_filter(dev, fattr->type, &local_filter); + } + + /* commit the new filter */ + *filter = local_filter; + } + ret = len; out: @@ -967,6 +1038,115 @@ out: return ret; } +/** + * show_filter() - shows the current scancode filter value or mask + * @device: the device descriptor + * @attr: the device attribute struct + * @buf: a pointer to the output buffer + * + * This routine is a callback routine to read a scancode filter value or mask. + * It is trigged by reading /sys/class/rc/rc?/[wakeup_]filter[_mask]. + * It prints the current scancode filter value or mask of the appropriate filter + * type in hexadecimal into @buf and returns the size of the buffer. + * + * Bits of the filter value corresponding to set bits in the filter mask are + * compared against input scancodes and non-matching scancodes are discarded. + * + * dev->lock is taken to guard against races between device registration, + * store_filter and show_filter. + */ +static ssize_t show_filter(struct device *device, + struct device_attribute *attr, + char *buf) +{ + struct rc_dev *dev = to_rc_dev(device); + struct rc_filter_attribute *fattr = to_rc_filter_attr(attr); + u32 val; + + /* Device is being removed */ + if (!dev) + return -EINVAL; + + mutex_lock(&dev->lock); + if (fattr->mask) + val = dev->scancode_filters[fattr->type].mask; + else + val = dev->scancode_filters[fattr->type].data; + mutex_unlock(&dev->lock); + + return sprintf(buf, "%#x\n", val); +} + +/** + * store_filter() - changes the scancode filter value + * @device: the device descriptor + * @attr: the device attribute struct + * @buf: a pointer to the input buffer + * @len: length of the input buffer + * + * This routine is for changing a scancode filter value or mask. + * It is trigged by writing to /sys/class/rc/rc?/[wakeup_]filter[_mask]. + * Returns -EINVAL if an invalid filter value for the current protocol was + * specified or if scancode filtering is not supported by the driver, otherwise + * returns @len. + * + * Bits of the filter value corresponding to set bits in the filter mask are + * compared against input scancodes and non-matching scancodes are discarded. + * + * dev->lock is taken to guard against races between device registration, + * store_filter and show_filter. + */ +static ssize_t store_filter(struct device *device, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct rc_dev *dev = to_rc_dev(device); + struct rc_filter_attribute *fattr = to_rc_filter_attr(attr); + struct rc_scancode_filter local_filter, *filter; + int ret; + unsigned long val; + + /* Device is being removed */ + if (!dev) + return -EINVAL; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + /* Scancode filter not supported (but still accept 0) */ + if (!dev->s_filter && fattr->type != RC_FILTER_NORMAL) + return val ? -EINVAL : count; + + mutex_lock(&dev->lock); + + /* Tell the driver about the new filter */ + filter = &dev->scancode_filters[fattr->type]; + local_filter = *filter; + if (fattr->mask) + local_filter.mask = val; + else + local_filter.data = val; + if (!dev->enabled_protocols[fattr->type] && local_filter.mask) { + /* refuse to set a filter unless a protocol is enabled */ + ret = -EINVAL; + goto unlock; + } + if (dev->s_filter) { + ret = dev->s_filter(dev, fattr->type, &local_filter); + if (ret < 0) + goto unlock; + } + + /* Success, commit the new filter */ + *filter = local_filter; + +unlock: + mutex_unlock(&dev->lock); + return (ret < 0) ? ret : count; +} + static void rc_dev_release(struct device *device) { } @@ -996,11 +1176,26 @@ static int rc_dev_uevent(struct device *device, struct kobj_uevent_env *env) /* * Static device attribute struct with the sysfs attributes for IR's */ -static DEVICE_ATTR(protocols, S_IRUGO | S_IWUSR, - show_protocols, store_protocols); +static RC_PROTO_ATTR(protocols, S_IRUGO | S_IWUSR, + show_protocols, store_protocols, RC_FILTER_NORMAL); +static RC_PROTO_ATTR(wakeup_protocols, S_IRUGO | S_IWUSR, + show_protocols, store_protocols, RC_FILTER_WAKEUP); +static RC_FILTER_ATTR(filter, S_IRUGO|S_IWUSR, + show_filter, store_filter, RC_FILTER_NORMAL, false); +static RC_FILTER_ATTR(filter_mask, S_IRUGO|S_IWUSR, + show_filter, store_filter, RC_FILTER_NORMAL, true); +static RC_FILTER_ATTR(wakeup_filter, S_IRUGO|S_IWUSR, + show_filter, store_filter, RC_FILTER_WAKEUP, false); +static RC_FILTER_ATTR(wakeup_filter_mask, S_IRUGO|S_IWUSR, + show_filter, store_filter, RC_FILTER_WAKEUP, true); static struct attribute *rc_dev_attrs[] = { - &dev_attr_protocols.attr, + &dev_attr_protocols.attr.attr, + &dev_attr_wakeup_protocols.attr.attr, + &dev_attr_filter.attr.attr, + &dev_attr_filter_mask.attr.attr, + &dev_attr_wakeup_filter.attr.attr, + &dev_attr_wakeup_filter_mask.attr.attr, NULL, }; @@ -1091,14 +1286,6 @@ int rc_register_device(struct rc_dev *dev) if (dev->close) dev->input_dev->close = ir_close; - /* - * Take the lock here, as the device sysfs node will appear - * when device_add() is called, which may trigger an ir-keytable udev - * rule, which will in turn call show_protocols and access - * dev->enabled_protocols before it has been initialized. - */ - mutex_lock(&dev->lock); - do { devno = find_first_zero_bit(ir_core_dev_number, IRRCV_NUM_DEVICES); @@ -1107,6 +1294,14 @@ int rc_register_device(struct rc_dev *dev) return -ENOMEM; } while (test_and_set_bit(devno, ir_core_dev_number)); + /* + * Take the lock here, as the device sysfs node will appear + * when device_add() is called, which may trigger an ir-keytable udev + * rule, which will in turn call show_protocols and access + * dev->enabled_protocols before it has been initialized. + */ + mutex_lock(&dev->lock); + dev->devno = devno; dev_set_name(&dev->dev, "rc%ld", dev->devno); dev_set_drvdata(&dev->dev, dev); @@ -1172,7 +1367,7 @@ int rc_register_device(struct rc_dev *dev) rc = dev->change_protocol(dev, &rc_type); if (rc < 0) goto out_raw; - dev->enabled_protocols = rc_type; + dev->enabled_protocols[RC_FILTER_NORMAL] = rc_type; } mutex_unlock(&dev->lock); @@ -1260,5 +1455,5 @@ int rc_core_debug; /* ir_debug level (0,1,2) */ EXPORT_SYMBOL_GPL(rc_core_debug); module_param_named(debug, rc_core_debug, int, 0644); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/rc/redrat3.c b/drivers/media/rc/redrat3.c index a5d4f88..47cd373 100644 --- a/drivers/media/rc/redrat3.c +++ b/drivers/media/rc/redrat3.c @@ -922,7 +922,7 @@ static struct rc_dev *redrat3_init_rc_dev(struct redrat3_dev *rr3) rc->dev.parent = dev; rc->priv = rr3; rc->driver_type = RC_DRIVER_IR_RAW; - rc->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rc, RC_BIT_ALL); rc->timeout = US_TO_NS(2750); rc->tx_ir = redrat3_transmit_ir; rc->s_tx_carrier = redrat3_set_tx_carrier; diff --git a/drivers/media/rc/st_rc.c b/drivers/media/rc/st_rc.c index 8f0cddb..22e4c1f 100644 --- a/drivers/media/rc/st_rc.c +++ b/drivers/media/rc/st_rc.c @@ -287,7 +287,7 @@ static int st_rc_probe(struct platform_device *pdev) st_rc_hardware_init(rc_dev); rdev->driver_type = RC_DRIVER_IR_RAW; - rdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rdev, RC_BIT_ALL); /* rx sampling rate is 10Mhz */ rdev->rx_resolution = 100; rdev->timeout = US_TO_NS(MAX_SYMB_TIME); diff --git a/drivers/media/rc/streamzap.c b/drivers/media/rc/streamzap.c index d7b11e6..f4e0bc3 100644 --- a/drivers/media/rc/streamzap.c +++ b/drivers/media/rc/streamzap.c @@ -322,7 +322,7 @@ static struct rc_dev *streamzap_init_rc_dev(struct streamzap_ir *sz) rdev->dev.parent = dev; rdev->priv = sz; rdev->driver_type = RC_DRIVER_IR_RAW; - rdev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rdev, RC_BIT_ALL); rdev->driver_name = DRIVER_NAME; rdev->map_name = RC_MAP_STREAMZAP; diff --git a/drivers/media/rc/ttusbir.c b/drivers/media/rc/ttusbir.c index d8de205..c5be38e 100644 --- a/drivers/media/rc/ttusbir.c +++ b/drivers/media/rc/ttusbir.c @@ -318,7 +318,7 @@ static int ttusbir_probe(struct usb_interface *intf, usb_to_input_id(tt->udev, &rc->input_id); rc->dev.parent = &intf->dev; rc->driver_type = RC_DRIVER_IR_RAW; - rc->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(rc, RC_BIT_ALL); rc->priv = tt; rc->driver_name = DRIVER_NAME; rc->map_name = RC_MAP_TT_1500; diff --git a/drivers/media/rc/winbond-cir.c b/drivers/media/rc/winbond-cir.c index 904baf4..a8b981f 100644 --- a/drivers/media/rc/winbond-cir.c +++ b/drivers/media/rc/winbond-cir.c @@ -1082,7 +1082,7 @@ wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id) data->dev->dev.parent = &device->dev; data->dev->timeout = MS_TO_NS(100); data->dev->rx_resolution = US_TO_NS(2); - data->dev->allowed_protos = RC_BIT_ALL; + rc_set_allowed_protocols(data->dev, RC_BIT_ALL); err = rc_register_device(data->dev); if (err) diff --git a/drivers/media/tuners/Kconfig b/drivers/media/tuners/Kconfig index ba2e365..a128488 100644 --- a/drivers/media/tuners/Kconfig +++ b/drivers/media/tuners/Kconfig @@ -204,6 +204,7 @@ config MEDIA_TUNER_TDA18212 config MEDIA_TUNER_E4000 tristate "Elonics E4000 silicon tuner" depends on MEDIA_SUPPORT && I2C + select REGMAP_I2C default m if !MEDIA_SUBDRV_AUTOSELECT help Elonics E4000 silicon tuner driver. diff --git a/drivers/media/tuners/e4000.c b/drivers/media/tuners/e4000.c index 40c1da7..90d9334 100644 --- a/drivers/media/tuners/e4000.c +++ b/drivers/media/tuners/e4000.c @@ -21,220 +21,113 @@ #include "e4000_priv.h" #include <linux/math64.h> -/* Max transfer size done by I2C transfer functions */ -#define MAX_XFER_SIZE 64 - -/* write multiple registers */ -static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len) -{ - int ret; - u8 buf[MAX_XFER_SIZE]; - struct i2c_msg msg[1] = { - { - .addr = priv->cfg->i2c_addr, - .flags = 0, - .len = 1 + len, - .buf = buf, - } - }; - - if (1 + len > sizeof(buf)) { - dev_warn(&priv->i2c->dev, - "%s: i2c wr reg=%04x: len=%d is too big!\n", - KBUILD_MODNAME, reg, len); - return -EINVAL; - } - - buf[0] = reg; - memcpy(&buf[1], val, len); - - ret = i2c_transfer(priv->i2c, msg, 1); - if (ret == 1) { - ret = 0; - } else { - dev_warn(&priv->i2c->dev, - "%s: i2c wr failed=%d reg=%02x len=%d\n", - KBUILD_MODNAME, ret, reg, len); - ret = -EREMOTEIO; - } - return ret; -} - -/* read multiple registers */ -static int e4000_rd_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len) -{ - int ret; - u8 buf[MAX_XFER_SIZE]; - struct i2c_msg msg[2] = { - { - .addr = priv->cfg->i2c_addr, - .flags = 0, - .len = 1, - .buf = ®, - }, { - .addr = priv->cfg->i2c_addr, - .flags = I2C_M_RD, - .len = len, - .buf = buf, - } - }; - - if (len > sizeof(buf)) { - dev_warn(&priv->i2c->dev, - "%s: i2c rd reg=%04x: len=%d is too big!\n", - KBUILD_MODNAME, reg, len); - return -EINVAL; - } - - ret = i2c_transfer(priv->i2c, msg, 2); - if (ret == 2) { - memcpy(val, buf, len); - ret = 0; - } else { - dev_warn(&priv->i2c->dev, - "%s: i2c rd failed=%d reg=%02x len=%d\n", - KBUILD_MODNAME, ret, reg, len); - ret = -EREMOTEIO; - } - - return ret; -} - -/* write single register */ -static int e4000_wr_reg(struct e4000_priv *priv, u8 reg, u8 val) -{ - return e4000_wr_regs(priv, reg, &val, 1); -} - -/* read single register */ -static int e4000_rd_reg(struct e4000_priv *priv, u8 reg, u8 *val) -{ - return e4000_rd_regs(priv, reg, val, 1); -} - static int e4000_init(struct dvb_frontend *fe) { - struct e4000_priv *priv = fe->tuner_priv; + struct e4000 *s = fe->tuner_priv; int ret; - dev_dbg(&priv->i2c->dev, "%s:\n", __func__); - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); + dev_dbg(&s->client->dev, "%s:\n", __func__); /* dummy I2C to ensure I2C wakes up */ - ret = e4000_wr_reg(priv, 0x02, 0x40); + ret = regmap_write(s->regmap, 0x02, 0x40); /* reset */ - ret = e4000_wr_reg(priv, 0x00, 0x01); - if (ret < 0) + ret = regmap_write(s->regmap, 0x00, 0x01); + if (ret) goto err; /* disable output clock */ - ret = e4000_wr_reg(priv, 0x06, 0x00); - if (ret < 0) + ret = regmap_write(s->regmap, 0x06, 0x00); + if (ret) goto err; - ret = e4000_wr_reg(priv, 0x7a, 0x96); - if (ret < 0) + ret = regmap_write(s->regmap, 0x7a, 0x96); + if (ret) goto err; /* configure gains */ - ret = e4000_wr_regs(priv, 0x7e, "\x01\xfe", 2); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x7e, "\x01\xfe", 2); + if (ret) goto err; - ret = e4000_wr_reg(priv, 0x82, 0x00); - if (ret < 0) + ret = regmap_write(s->regmap, 0x82, 0x00); + if (ret) goto err; - ret = e4000_wr_reg(priv, 0x24, 0x05); - if (ret < 0) + ret = regmap_write(s->regmap, 0x24, 0x05); + if (ret) goto err; - ret = e4000_wr_regs(priv, 0x87, "\x20\x01", 2); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x87, "\x20\x01", 2); + if (ret) goto err; - ret = e4000_wr_regs(priv, 0x9f, "\x7f\x07", 2); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x9f, "\x7f\x07", 2); + if (ret) goto err; /* DC offset control */ - ret = e4000_wr_reg(priv, 0x2d, 0x1f); - if (ret < 0) + ret = regmap_write(s->regmap, 0x2d, 0x1f); + if (ret) goto err; - ret = e4000_wr_regs(priv, 0x70, "\x01\x01", 2); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x70, "\x01\x01", 2); + if (ret) goto err; /* gain control */ - ret = e4000_wr_reg(priv, 0x1a, 0x17); - if (ret < 0) + ret = regmap_write(s->regmap, 0x1a, 0x17); + if (ret) goto err; - ret = e4000_wr_reg(priv, 0x1f, 0x1a); - if (ret < 0) + ret = regmap_write(s->regmap, 0x1f, 0x1a); + if (ret) goto err; - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return 0; + s->active = true; err: - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + if (ret) + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); - dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); return ret; } static int e4000_sleep(struct dvb_frontend *fe) { - struct e4000_priv *priv = fe->tuner_priv; + struct e4000 *s = fe->tuner_priv; int ret; - dev_dbg(&priv->i2c->dev, "%s:\n", __func__); + dev_dbg(&s->client->dev, "%s:\n", __func__); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); + s->active = false; - ret = e4000_wr_reg(priv, 0x00, 0x00); - if (ret < 0) + ret = regmap_write(s->regmap, 0x00, 0x00); + if (ret) goto err; - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return 0; err: - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + if (ret) + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); - dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); return ret; } static int e4000_set_params(struct dvb_frontend *fe) { - struct e4000_priv *priv = fe->tuner_priv; + struct e4000 *s = fe->tuner_priv; struct dtv_frontend_properties *c = &fe->dtv_property_cache; int ret, i, sigma_delta; - unsigned int f_vco; + unsigned int pll_n, pll_f; + u64 f_vco; u8 buf[5], i_data[4], q_data[4]; - dev_dbg(&priv->i2c->dev, - "%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n", + dev_dbg(&s->client->dev, + "%s: delivery_system=%d frequency=%u bandwidth_hz=%u\n", __func__, c->delivery_system, c->frequency, c->bandwidth_hz); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - /* gain control manual */ - ret = e4000_wr_reg(priv, 0x1a, 0x00); - if (ret < 0) + ret = regmap_write(s->regmap, 0x1a, 0x00); + if (ret) goto err; /* PLL */ @@ -248,23 +141,21 @@ static int e4000_set_params(struct dvb_frontend *fe) goto err; } - /* - * Note: Currently f_vco overflows when c->frequency is 1 073 741 824 Hz - * or more. - */ - f_vco = c->frequency * e4000_pll_lut[i].mul; - sigma_delta = div_u64(0x10000ULL * (f_vco % priv->cfg->clock), priv->cfg->clock); - buf[0] = f_vco / priv->cfg->clock; + f_vco = 1ull * c->frequency * e4000_pll_lut[i].mul; + pll_n = div_u64_rem(f_vco, s->clock, &pll_f); + sigma_delta = div_u64(0x10000ULL * pll_f, s->clock); + buf[0] = pll_n; buf[1] = (sigma_delta >> 0) & 0xff; buf[2] = (sigma_delta >> 8) & 0xff; buf[3] = 0x00; buf[4] = e4000_pll_lut[i].div; - dev_dbg(&priv->i2c->dev, "%s: f_vco=%u pll div=%d sigma_delta=%04x\n", + dev_dbg(&s->client->dev, + "%s: f_vco=%llu pll div=%d sigma_delta=%04x\n", __func__, f_vco, buf[0], sigma_delta); - ret = e4000_wr_regs(priv, 0x09, buf, 5); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x09, buf, 5); + if (ret) goto err; /* LNA filter (RF filter) */ @@ -278,8 +169,8 @@ static int e4000_set_params(struct dvb_frontend *fe) goto err; } - ret = e4000_wr_reg(priv, 0x10, e400_lna_filter_lut[i].val); - if (ret < 0) + ret = regmap_write(s->regmap, 0x10, e400_lna_filter_lut[i].val); + if (ret) goto err; /* IF filters */ @@ -296,8 +187,8 @@ static int e4000_set_params(struct dvb_frontend *fe) buf[0] = e4000_if_filter_lut[i].reg11_val; buf[1] = e4000_if_filter_lut[i].reg12_val; - ret = e4000_wr_regs(priv, 0x11, buf, 2); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x11, buf, 2); + if (ret) goto err; /* frequency band */ @@ -311,34 +202,34 @@ static int e4000_set_params(struct dvb_frontend *fe) goto err; } - ret = e4000_wr_reg(priv, 0x07, e4000_band_lut[i].reg07_val); - if (ret < 0) + ret = regmap_write(s->regmap, 0x07, e4000_band_lut[i].reg07_val); + if (ret) goto err; - ret = e4000_wr_reg(priv, 0x78, e4000_band_lut[i].reg78_val); - if (ret < 0) + ret = regmap_write(s->regmap, 0x78, e4000_band_lut[i].reg78_val); + if (ret) goto err; /* DC offset */ for (i = 0; i < 4; i++) { if (i == 0) - ret = e4000_wr_regs(priv, 0x15, "\x00\x7e\x24", 3); + ret = regmap_bulk_write(s->regmap, 0x15, "\x00\x7e\x24", 3); else if (i == 1) - ret = e4000_wr_regs(priv, 0x15, "\x00\x7f", 2); + ret = regmap_bulk_write(s->regmap, 0x15, "\x00\x7f", 2); else if (i == 2) - ret = e4000_wr_regs(priv, 0x15, "\x01", 1); + ret = regmap_bulk_write(s->regmap, 0x15, "\x01", 1); else - ret = e4000_wr_regs(priv, 0x16, "\x7e", 1); + ret = regmap_bulk_write(s->regmap, 0x16, "\x7e", 1); - if (ret < 0) + if (ret) goto err; - ret = e4000_wr_reg(priv, 0x29, 0x01); - if (ret < 0) + ret = regmap_write(s->regmap, 0x29, 0x01); + if (ret) goto err; - ret = e4000_rd_regs(priv, 0x2a, buf, 3); - if (ret < 0) + ret = regmap_bulk_read(s->regmap, 0x2a, buf, 3); + if (ret) goto err; i_data[i] = (((buf[2] >> 0) & 0x3) << 6) | (buf[0] & 0x3f); @@ -348,53 +239,226 @@ static int e4000_set_params(struct dvb_frontend *fe) swap(q_data[2], q_data[3]); swap(i_data[2], i_data[3]); - ret = e4000_wr_regs(priv, 0x50, q_data, 4); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x50, q_data, 4); + if (ret) goto err; - ret = e4000_wr_regs(priv, 0x60, i_data, 4); - if (ret < 0) + ret = regmap_bulk_write(s->regmap, 0x60, i_data, 4); + if (ret) goto err; /* gain control auto */ - ret = e4000_wr_reg(priv, 0x1a, 0x17); - if (ret < 0) + ret = regmap_write(s->regmap, 0x1a, 0x17); + if (ret) goto err; - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return 0; err: - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + if (ret) + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); - dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); return ret; } static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) { - struct e4000_priv *priv = fe->tuner_priv; + struct e4000 *s = fe->tuner_priv; - dev_dbg(&priv->i2c->dev, "%s:\n", __func__); + dev_dbg(&s->client->dev, "%s:\n", __func__); *frequency = 0; /* Zero-IF */ return 0; } -static int e4000_release(struct dvb_frontend *fe) +#if IS_ENABLED(CONFIG_VIDEO_V4L2) +static int e4000_set_lna_gain(struct dvb_frontend *fe) { - struct e4000_priv *priv = fe->tuner_priv; + struct e4000 *s = fe->tuner_priv; + int ret; + u8 u8tmp; + + dev_dbg(&s->client->dev, "%s: lna auto=%d->%d val=%d->%d\n", + __func__, s->lna_gain_auto->cur.val, + s->lna_gain_auto->val, s->lna_gain->cur.val, + s->lna_gain->val); + + if (s->lna_gain_auto->val && s->if_gain_auto->cur.val) + u8tmp = 0x17; + else if (s->lna_gain_auto->val) + u8tmp = 0x19; + else if (s->if_gain_auto->cur.val) + u8tmp = 0x16; + else + u8tmp = 0x10; + + ret = regmap_write(s->regmap, 0x1a, u8tmp); + if (ret) + goto err; + + if (s->lna_gain_auto->val == false) { + ret = regmap_write(s->regmap, 0x14, s->lna_gain->val); + if (ret) + goto err; + } +err: + if (ret) + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); - dev_dbg(&priv->i2c->dev, "%s:\n", __func__); + return ret; +} - kfree(fe->tuner_priv); +static int e4000_set_mixer_gain(struct dvb_frontend *fe) +{ + struct e4000 *s = fe->tuner_priv; + int ret; + u8 u8tmp; - return 0; + dev_dbg(&s->client->dev, "%s: mixer auto=%d->%d val=%d->%d\n", + __func__, s->mixer_gain_auto->cur.val, + s->mixer_gain_auto->val, s->mixer_gain->cur.val, + s->mixer_gain->val); + + if (s->mixer_gain_auto->val) + u8tmp = 0x15; + else + u8tmp = 0x14; + + ret = regmap_write(s->regmap, 0x20, u8tmp); + if (ret) + goto err; + + if (s->mixer_gain_auto->val == false) { + ret = regmap_write(s->regmap, 0x15, s->mixer_gain->val); + if (ret) + goto err; + } +err: + if (ret) + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); + + return ret; } +static int e4000_set_if_gain(struct dvb_frontend *fe) +{ + struct e4000 *s = fe->tuner_priv; + int ret; + u8 buf[2]; + u8 u8tmp; + + dev_dbg(&s->client->dev, "%s: if auto=%d->%d val=%d->%d\n", + __func__, s->if_gain_auto->cur.val, + s->if_gain_auto->val, s->if_gain->cur.val, + s->if_gain->val); + + if (s->if_gain_auto->val && s->lna_gain_auto->cur.val) + u8tmp = 0x17; + else if (s->lna_gain_auto->cur.val) + u8tmp = 0x19; + else if (s->if_gain_auto->val) + u8tmp = 0x16; + else + u8tmp = 0x10; + + ret = regmap_write(s->regmap, 0x1a, u8tmp); + if (ret) + goto err; + + if (s->if_gain_auto->val == false) { + buf[0] = e4000_if_gain_lut[s->if_gain->val].reg16_val; + buf[1] = e4000_if_gain_lut[s->if_gain->val].reg17_val; + ret = regmap_bulk_write(s->regmap, 0x16, buf, 2); + if (ret) + goto err; + } +err: + if (ret) + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); + + return ret; +} + +static int e4000_pll_lock(struct dvb_frontend *fe) +{ + struct e4000 *s = fe->tuner_priv; + int ret; + unsigned int utmp; + + ret = regmap_read(s->regmap, 0x07, &utmp); + if (ret) + goto err; + + s->pll_lock->val = (utmp & 0x01); +err: + if (ret) + dev_dbg(&s->client->dev, "%s: failed=%d\n", __func__, ret); + + return ret; +} + +static int e4000_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct e4000 *s = container_of(ctrl->handler, struct e4000, hdl); + int ret; + + if (s->active == false) + return 0; + + switch (ctrl->id) { + case V4L2_CID_RF_TUNER_PLL_LOCK: + ret = e4000_pll_lock(s->fe); + break; + default: + dev_dbg(&s->client->dev, "%s: unknown ctrl: id=%d name=%s\n", + __func__, ctrl->id, ctrl->name); + ret = -EINVAL; + } + + return ret; +} + +static int e4000_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct e4000 *s = container_of(ctrl->handler, struct e4000, hdl); + struct dvb_frontend *fe = s->fe; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int ret; + + if (s->active == false) + return 0; + + switch (ctrl->id) { + case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: + case V4L2_CID_RF_TUNER_BANDWIDTH: + c->bandwidth_hz = s->bandwidth->val; + ret = e4000_set_params(s->fe); + break; + case V4L2_CID_RF_TUNER_LNA_GAIN_AUTO: + case V4L2_CID_RF_TUNER_LNA_GAIN: + ret = e4000_set_lna_gain(s->fe); + break; + case V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO: + case V4L2_CID_RF_TUNER_MIXER_GAIN: + ret = e4000_set_mixer_gain(s->fe); + break; + case V4L2_CID_RF_TUNER_IF_GAIN_AUTO: + case V4L2_CID_RF_TUNER_IF_GAIN: + ret = e4000_set_if_gain(s->fe); + break; + default: + dev_dbg(&s->client->dev, "%s: unknown ctrl: id=%d name=%s\n", + __func__, ctrl->id, ctrl->name); + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops e4000_ctrl_ops = { + .g_volatile_ctrl = e4000_g_volatile_ctrl, + .s_ctrl = e4000_s_ctrl, +}; +#endif + static const struct dvb_tuner_ops e4000_tuner_ops = { .info = { .name = "Elonics E4000", @@ -402,8 +466,6 @@ static const struct dvb_tuner_ops e4000_tuner_ops = { .frequency_max = 862000000, }, - .release = e4000_release, - .init = e4000_init, .sleep = e4000_sleep, .set_params = e4000_set_params, @@ -411,62 +473,148 @@ static const struct dvb_tuner_ops e4000_tuner_ops = { .get_if_frequency = e4000_get_if_frequency, }; -struct dvb_frontend *e4000_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, const struct e4000_config *cfg) +/* + * Use V4L2 subdev to carry V4L2 control handler, even we don't implement + * subdev itself, just to avoid reinventing the wheel. + */ +static int e4000_probe(struct i2c_client *client, + const struct i2c_device_id *id) { - struct e4000_priv *priv; + struct e4000_config *cfg = client->dev.platform_data; + struct dvb_frontend *fe = cfg->fe; + struct e4000 *s; int ret; - u8 chip_id; - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); + unsigned int utmp; + static const struct regmap_config regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xff, + }; - priv = kzalloc(sizeof(struct e4000_priv), GFP_KERNEL); - if (!priv) { + s = kzalloc(sizeof(struct e4000), GFP_KERNEL); + if (!s) { ret = -ENOMEM; - dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME); + dev_err(&client->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME); goto err; } - priv->cfg = cfg; - priv->i2c = i2c; + s->clock = cfg->clock; + s->client = client; + s->fe = cfg->fe; + s->regmap = devm_regmap_init_i2c(client, ®map_config); + if (IS_ERR(s->regmap)) { + ret = PTR_ERR(s->regmap); + goto err; + } /* check if the tuner is there */ - ret = e4000_rd_reg(priv, 0x02, &chip_id); - if (ret < 0) + ret = regmap_read(s->regmap, 0x02, &utmp); + if (ret) goto err; - dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id); + dev_dbg(&s->client->dev, "%s: chip id=%02x\n", __func__, utmp); - if (chip_id != 0x40) + if (utmp != 0x40) { + ret = -ENODEV; goto err; + } /* put sleep as chip seems to be in normal mode by default */ - ret = e4000_wr_reg(priv, 0x00, 0x00); - if (ret < 0) + ret = regmap_write(s->regmap, 0x00, 0x00); + if (ret) goto err; - dev_info(&priv->i2c->dev, +#if IS_ENABLED(CONFIG_VIDEO_V4L2) + /* Register controls */ + v4l2_ctrl_handler_init(&s->hdl, 9); + s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1); + s->bandwidth = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_BANDWIDTH, 4300000, 11000000, 100000, 4300000); + v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false); + s->lna_gain_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_LNA_GAIN_AUTO, 0, 1, 1, 1); + s->lna_gain = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_LNA_GAIN, 0, 15, 1, 10); + v4l2_ctrl_auto_cluster(2, &s->lna_gain_auto, 0, false); + s->mixer_gain_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO, 0, 1, 1, 1); + s->mixer_gain = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1); + v4l2_ctrl_auto_cluster(2, &s->mixer_gain_auto, 0, false); + s->if_gain_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_IF_GAIN_AUTO, 0, 1, 1, 1); + s->if_gain = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_IF_GAIN, 0, 54, 1, 0); + v4l2_ctrl_auto_cluster(2, &s->if_gain_auto, 0, false); + s->pll_lock = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, + V4L2_CID_RF_TUNER_PLL_LOCK, 0, 1, 1, 0); + if (s->hdl.error) { + ret = s->hdl.error; + dev_err(&s->client->dev, "Could not initialize controls\n"); + v4l2_ctrl_handler_free(&s->hdl); + goto err; + } + + s->sd.ctrl_handler = &s->hdl; +#endif + + dev_info(&s->client->dev, "%s: Elonics E4000 successfully identified\n", KBUILD_MODNAME); - fe->tuner_priv = priv; + fe->tuner_priv = s; memcpy(&fe->ops.tuner_ops, &e4000_tuner_ops, sizeof(struct dvb_tuner_ops)); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + v4l2_set_subdevdata(&s->sd, client); + i2c_set_clientdata(client, &s->sd); - return fe; + return 0; err: - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + if (ret) { + dev_dbg(&client->dev, "%s: failed=%d\n", __func__, ret); + kfree(s); + } + + return ret; +} + +static int e4000_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct e4000 *s = container_of(sd, struct e4000, sd); + struct dvb_frontend *fe = s->fe; + + dev_dbg(&client->dev, "%s:\n", __func__); - dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret); - kfree(priv); - return NULL; +#if IS_ENABLED(CONFIG_VIDEO_V4L2) + v4l2_ctrl_handler_free(&s->hdl); +#endif + memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops)); + fe->tuner_priv = NULL; + kfree(s); + + return 0; } -EXPORT_SYMBOL(e4000_attach); + +static const struct i2c_device_id e4000_id[] = { + {"e4000", 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, e4000_id); + +static struct i2c_driver e4000_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "e4000", + }, + .probe = e4000_probe, + .remove = e4000_remove, + .id_table = e4000_id, +}; + +module_i2c_driver(e4000_driver); MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver"); MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); diff --git a/drivers/media/tuners/e4000.h b/drivers/media/tuners/e4000.h index 25ee7c0..e74b8b2 100644 --- a/drivers/media/tuners/e4000.h +++ b/drivers/media/tuners/e4000.h @@ -24,12 +24,15 @@ #include <linux/kconfig.h> #include "dvb_frontend.h" +/* + * I2C address + * 0x64, 0x65, 0x66, 0x67 + */ struct e4000_config { /* - * I2C address - * 0x64, 0x65, 0x66, 0x67 + * frontend */ - u8 i2c_addr; + struct dvb_frontend *fe; /* * clock @@ -37,16 +40,4 @@ struct e4000_config { u32 clock; }; -#if IS_ENABLED(CONFIG_MEDIA_TUNER_E4000) -extern struct dvb_frontend *e4000_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, const struct e4000_config *cfg); -#else -static inline struct dvb_frontend *e4000_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, const struct e4000_config *cfg) -{ - dev_warn(&i2c->dev, "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} -#endif - #endif diff --git a/drivers/media/tuners/e4000_priv.h b/drivers/media/tuners/e4000_priv.h index a385505..cb00704 100644 --- a/drivers/media/tuners/e4000_priv.h +++ b/drivers/media/tuners/e4000_priv.h @@ -22,10 +22,29 @@ #define E4000_PRIV_H #include "e4000.h" +#include <media/v4l2-ctrls.h> +#include <media/v4l2-subdev.h> +#include <linux/regmap.h> -struct e4000_priv { - const struct e4000_config *cfg; - struct i2c_adapter *i2c; +struct e4000 { + struct i2c_client *client; + struct regmap *regmap; + u32 clock; + struct dvb_frontend *fe; + struct v4l2_subdev sd; + bool active; + + /* Controls */ + struct v4l2_ctrl_handler hdl; + struct v4l2_ctrl *bandwidth_auto; + struct v4l2_ctrl *bandwidth; + struct v4l2_ctrl *lna_gain_auto; + struct v4l2_ctrl *lna_gain; + struct v4l2_ctrl *mixer_gain_auto; + struct v4l2_ctrl *mixer_gain; + struct v4l2_ctrl *if_gain_auto; + struct v4l2_ctrl *if_gain; + struct v4l2_ctrl *pll_lock; }; struct e4000_pll { @@ -144,4 +163,67 @@ static const struct e4000_if_filter e4000_if_filter_lut[] = { { 0xffffffff, 0x00, 0x20 }, }; +struct e4000_if_gain { + u8 reg16_val; + u8 reg17_val; +}; + +static const struct e4000_if_gain e4000_if_gain_lut[] = { + {0x00, 0x00}, + {0x20, 0x00}, + {0x40, 0x00}, + {0x02, 0x00}, + {0x22, 0x00}, + {0x42, 0x00}, + {0x04, 0x00}, + {0x24, 0x00}, + {0x44, 0x00}, + {0x01, 0x00}, + {0x21, 0x00}, + {0x41, 0x00}, + {0x03, 0x00}, + {0x23, 0x00}, + {0x43, 0x00}, + {0x05, 0x00}, + {0x25, 0x00}, + {0x45, 0x00}, + {0x07, 0x00}, + {0x27, 0x00}, + {0x47, 0x00}, + {0x0f, 0x00}, + {0x2f, 0x00}, + {0x4f, 0x00}, + {0x17, 0x00}, + {0x37, 0x00}, + {0x57, 0x00}, + {0x1f, 0x00}, + {0x3f, 0x00}, + {0x5f, 0x00}, + {0x1f, 0x01}, + {0x3f, 0x01}, + {0x5f, 0x01}, + {0x1f, 0x02}, + {0x3f, 0x02}, + {0x5f, 0x02}, + {0x1f, 0x03}, + {0x3f, 0x03}, + {0x5f, 0x03}, + {0x1f, 0x04}, + {0x3f, 0x04}, + {0x5f, 0x04}, + {0x1f, 0x0c}, + {0x3f, 0x0c}, + {0x5f, 0x0c}, + {0x1f, 0x14}, + {0x3f, 0x14}, + {0x5f, 0x14}, + {0x1f, 0x1c}, + {0x3f, 0x1c}, + {0x5f, 0x1c}, + {0x1f, 0x24}, + {0x3f, 0x24}, + {0x5f, 0x24}, + {0x7f, 0x24}, +}; + #endif diff --git a/drivers/media/tuners/mt2063.c b/drivers/media/tuners/mt2063.c index 20cca40..f640dcf 100644 --- a/drivers/media/tuners/mt2063.c +++ b/drivers/media/tuners/mt2063.c @@ -1,7 +1,7 @@ /* * Driver for mt2063 Micronas tuner * - * Copyright (c) 2011 Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2011 Mauro Carvalho Chehab * * This driver came from a driver originally written by: * Henry Wang <Henry.wang@AzureWave.com> @@ -2298,6 +2298,6 @@ static int tuner_MT2063_ClearPowerMaskBits(struct dvb_frontend *fe) } #endif -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_DESCRIPTION("MT2063 Silicon tuner"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/tuners/r820t.c b/drivers/media/tuners/r820t.c index d9ee43f..319adc4 100644 --- a/drivers/media/tuners/r820t.c +++ b/drivers/media/tuners/r820t.c @@ -1,7 +1,7 @@ /* * Rafael Micro R820T driver * - * Copyright (C) 2013 Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2013 Mauro Carvalho Chehab * * This driver was written from scratch, based on an existing driver * that it is part of rtl-sdr git tree, released under GPLv2: @@ -2351,5 +2351,5 @@ err_no_gate: EXPORT_SYMBOL_GPL(r820t_attach); MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/tuners/tda18212.c b/drivers/media/tuners/tda18212.c index abe256e..05a4ac9 100644 --- a/drivers/media/tuners/tda18212.c +++ b/drivers/media/tuners/tda18212.c @@ -150,6 +150,8 @@ static int tda18212_set_params(struct dvb_frontend *fe) #define DVBT2_8 5 #define DVBC_6 6 #define DVBC_8 7 + #define ATSC_VSB 8 + #define ATSC_QAM 9 static const u8 bw_params[][3] = { /* reg: 0f 13 23 */ [DVBT_6] = { 0xb3, 0x20, 0x03 }, @@ -160,6 +162,8 @@ static int tda18212_set_params(struct dvb_frontend *fe) [DVBT2_8] = { 0xbc, 0x22, 0x01 }, [DVBC_6] = { 0x92, 0x50, 0x03 }, [DVBC_8] = { 0x92, 0x53, 0x03 }, + [ATSC_VSB] = { 0x7d, 0x20, 0x63 }, + [ATSC_QAM] = { 0x7d, 0x20, 0x63 }, }; dev_dbg(&priv->i2c->dev, @@ -171,6 +175,14 @@ static int tda18212_set_params(struct dvb_frontend *fe) fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ switch (c->delivery_system) { + case SYS_ATSC: + if_khz = priv->cfg->if_atsc_vsb; + i = ATSC_VSB; + break; + case SYS_DVBC_ANNEX_B: + if_khz = priv->cfg->if_atsc_qam; + i = ATSC_QAM; + break; case SYS_DVBT: switch (c->bandwidth_hz) { case 6000000: diff --git a/drivers/media/tuners/tda18212.h b/drivers/media/tuners/tda18212.h index 7e0d503..c36b49e 100644 --- a/drivers/media/tuners/tda18212.h +++ b/drivers/media/tuners/tda18212.h @@ -35,6 +35,8 @@ struct tda18212_config { u16 if_dvbt2_7; u16 if_dvbt2_8; u16 if_dvbc; + u16 if_atsc_vsb; + u16 if_atsc_qam; }; #if IS_ENABLED(CONFIG_MEDIA_TUNER_TDA18212) diff --git a/drivers/media/tuners/tuner-xc2028.c b/drivers/media/tuners/tuner-xc2028.c index cca508d..76a8165 100644 --- a/drivers/media/tuners/tuner-xc2028.c +++ b/drivers/media/tuners/tuner-xc2028.c @@ -1107,6 +1107,9 @@ static int generic_set_freq(struct dvb_frontend *fe, u32 freq /* in HZ */, offset += 200000; } #endif + default: + tuner_err("Unsupported tuner type %d.\n", new_type); + break; } div = (freq - offset + DIV / 2) / DIV; diff --git a/drivers/media/usb/au0828/au0828-cards.c b/drivers/media/usb/au0828/au0828-cards.c index dd32dec..7fdadf9 100644 --- a/drivers/media/usb/au0828/au0828-cards.c +++ b/drivers/media/usb/au0828/au0828-cards.c @@ -108,7 +108,7 @@ struct au0828_board au0828_boards[] = { .name = "DViCO FusionHDTV USB", .tuner_type = UNSET, .tuner_addr = ADDR_UNSET, - .i2c_clk_divider = AU0828_I2C_CLK_250KHZ, + .i2c_clk_divider = AU0828_I2C_CLK_20KHZ, }, [AU0828_BOARD_HAUPPAUGE_WOODBURY] = { .name = "Hauppauge Woodbury", @@ -270,18 +270,25 @@ void au0828_gpio_setup(struct au0828_dev *dev) * 9 - XC5000 Tuner */ - /* Into reset */ + /* Set relevant GPIOs as outputs (leave the EEPROM W/P + as an input since we will never touch it and it has + a pullup) */ au0828_write(dev, REG_003, 0x02); au0828_write(dev, REG_002, 0x80 | 0x20 | 0x10); + + /* Into reset */ au0828_write(dev, REG_001, 0x0); au0828_write(dev, REG_000, 0x0); - msleep(100); + msleep(50); - /* Out of reset (leave the cs5340 in reset until needed) */ - au0828_write(dev, REG_003, 0x02); - au0828_write(dev, REG_001, 0x02); - au0828_write(dev, REG_002, 0x80 | 0x20 | 0x10); - au0828_write(dev, REG_000, 0x80 | 0x40 | 0x20); + /* Bring power supply out of reset */ + au0828_write(dev, REG_000, 0x80); + msleep(50); + + /* Bring xc5000 and au8522 out of reset (leave the + cs5340 in reset until needed) */ + au0828_write(dev, REG_001, 0x02); /* xc5000 */ + au0828_write(dev, REG_000, 0x80 | 0x20); /* PS + au8522 */ msleep(250); break; diff --git a/drivers/media/usb/cx231xx/cx231xx-input.c b/drivers/media/usb/cx231xx/cx231xx-input.c index 0f7b424..46d52fa 100644 --- a/drivers/media/usb/cx231xx/cx231xx-input.c +++ b/drivers/media/usb/cx231xx/cx231xx-input.c @@ -1,7 +1,7 @@ /* * cx231xx IR glue driver * - * Copyright (C) 2010 Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2010 Mauro Carvalho Chehab * * Polaris (cx231xx) has its support for IR's with a design close to MCE. * however, a few designs are using an external I2C chip for IR, instead diff --git a/drivers/media/usb/dvb-usb-v2/Kconfig b/drivers/media/usb/dvb-usb-v2/Kconfig index 2059d0c8..037e519 100644 --- a/drivers/media/usb/dvb-usb-v2/Kconfig +++ b/drivers/media/usb/dvb-usb-v2/Kconfig @@ -100,13 +100,6 @@ config DVB_USB_GL861 Say Y here to support the MSI Megasky 580 (55801) DVB-T USB2.0 receiver with USB ID 0db0:5581. -config DVB_USB_IT913X - tristate "ITE IT913X DVB-T USB2.0 support" - depends on DVB_USB_V2 - select DVB_IT913X_FE - help - Say Y here to support the ITE IT913X DVB-T USB2.0 - config DVB_USB_LME2510 tristate "LME DM04/QQBOX DVB-S USB2.0 support" depends on DVB_USB_V2 @@ -133,7 +126,7 @@ config DVB_USB_MXL111SF config DVB_USB_RTL28XXU tristate "Realtek RTL28xxU DVB USB support" - depends on DVB_USB_V2 + depends on DVB_USB_V2 && I2C_MUX select DVB_RTL2830 select DVB_RTL2832 select MEDIA_TUNER_QT1010 if MEDIA_SUBDRV_AUTOSELECT diff --git a/drivers/media/usb/dvb-usb-v2/Makefile b/drivers/media/usb/dvb-usb-v2/Makefile index 2c06714..7407b83 100644 --- a/drivers/media/usb/dvb-usb-v2/Makefile +++ b/drivers/media/usb/dvb-usb-v2/Makefile @@ -22,9 +22,6 @@ obj-$(CONFIG_DVB_USB_CE6230) += dvb-usb-ce6230.o dvb-usb-ec168-objs := ec168.o obj-$(CONFIG_DVB_USB_EC168) += dvb-usb-ec168.o -dvb-usb-it913x-objs := it913x.o -obj-$(CONFIG_DVB_USB_IT913X) += dvb-usb-it913x.o - dvb-usb-lmedm04-objs := lmedm04.o obj-$(CONFIG_DVB_USB_LME2510) += dvb-usb-lmedm04.o @@ -44,3 +41,4 @@ ccflags-y += -I$(srctree)/drivers/media/dvb-core ccflags-y += -I$(srctree)/drivers/media/dvb-frontends ccflags-y += -I$(srctree)/drivers/media/tuners ccflags-y += -I$(srctree)/drivers/media/common +ccflags-y += -I$(srctree)/drivers/staging/media/rtl2832u_sdr diff --git a/drivers/media/usb/dvb-usb-v2/af9035.c b/drivers/media/usb/dvb-usb-v2/af9035.c index 8ede8ea..021e4d3 100644 --- a/drivers/media/usb/dvb-usb-v2/af9035.c +++ b/drivers/media/usb/dvb-usb-v2/af9035.c @@ -575,6 +575,10 @@ static int af9035_download_firmware(struct dvb_usb_device *d, if (ret < 0) goto err; + /* use default I2C address if eeprom has no address set */ + if (!tmp) + tmp = 0x3a; + if (state->chip_type == 0x9135) { ret = af9035_wr_reg(d, 0x004bfb, tmp); if (ret < 0) @@ -637,6 +641,7 @@ static int af9035_read_config(struct dvb_usb_device *d) /* demod I2C "address" */ state->af9033_config[0].i2c_addr = 0x38; + state->af9033_config[1].i2c_addr = 0x3a; state->af9033_config[0].adc_multiplier = AF9033_ADC_MULTIPLIER_2X; state->af9033_config[1].adc_multiplier = AF9033_ADC_MULTIPLIER_2X; state->af9033_config[0].ts_mode = AF9033_TS_MODE_USB; @@ -684,7 +689,9 @@ static int af9035_read_config(struct dvb_usb_device *d) if (ret < 0) goto err; - state->af9033_config[1].i2c_addr = tmp; + if (tmp) + state->af9033_config[1].i2c_addr = tmp; + dev_dbg(&d->udev->dev, "%s: 2nd demod I2C addr=%02x\n", __func__, tmp); } @@ -938,12 +945,7 @@ static int af9035_frontend_callback(void *adapter_priv, int component, static int af9035_get_adapter_count(struct dvb_usb_device *d) { struct state *state = d_to_priv(d); - - /* disable 2nd adapter as we don't have PID filters implemented */ - if (d->udev->speed == USB_SPEED_FULL) - return 1; - else - return state->dual_mode + 1; + return state->dual_mode + 1; } static int af9035_frontend_attach(struct dvb_usb_adapter *adap) @@ -961,7 +963,7 @@ static int af9035_frontend_attach(struct dvb_usb_adapter *adap) /* attach demodulator */ adap->fe[0] = dvb_attach(af9033_attach, &state->af9033_config[adap->id], - &d->i2c_adap); + &d->i2c_adap, &state->ops); if (adap->fe[0] == NULL) { ret = -ENODEV; goto err; @@ -1369,58 +1371,19 @@ static int af9035_get_stream_config(struct dvb_frontend *fe, u8 *ts_type, return 0; } -/* - * FIXME: PID filter is property of demodulator and should be moved to the - * correct driver. Also we support only adapter #0 PID filter and will - * disable adapter #1 if USB1.1 is used. - */ static int af9035_pid_filter_ctrl(struct dvb_usb_adapter *adap, int onoff) { - struct dvb_usb_device *d = adap_to_d(adap); - int ret; - - dev_dbg(&d->udev->dev, "%s: onoff=%d\n", __func__, onoff); - - ret = af9035_wr_reg_mask(d, 0x80f993, onoff, 0x01); - if (ret < 0) - goto err; - - return 0; - -err: - dev_dbg(&d->udev->dev, "%s: failed=%d\n", __func__, ret); + struct state *state = adap_to_priv(adap); - return ret; + return state->ops.pid_filter_ctrl(adap->fe[0], onoff); } static int af9035_pid_filter(struct dvb_usb_adapter *adap, int index, u16 pid, int onoff) { - struct dvb_usb_device *d = adap_to_d(adap); - int ret; - u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff}; - - dev_dbg(&d->udev->dev, "%s: index=%d pid=%04x onoff=%d\n", - __func__, index, pid, onoff); - - ret = af9035_wr_regs(d, 0x80f996, wbuf, 2); - if (ret < 0) - goto err; - - ret = af9035_wr_reg(d, 0x80f994, onoff); - if (ret < 0) - goto err; - - ret = af9035_wr_reg(d, 0x80f995, index); - if (ret < 0) - goto err; - - return 0; - -err: - dev_dbg(&d->udev->dev, "%s: failed=%d\n", __func__, ret); + struct state *state = adap_to_priv(adap); - return ret; + return state->ops.pid_filter(adap->fe[0], index, pid, onoff); } static int af9035_probe(struct usb_interface *intf, @@ -1494,6 +1457,13 @@ static const struct dvb_usb_device_properties af9035_props = { .stream = DVB_USB_STREAM_BULK(0x84, 6, 87 * 188), }, { + .caps = DVB_USB_ADAP_HAS_PID_FILTER | + DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF, + + .pid_filter_count = 32, + .pid_filter_ctrl = af9035_pid_filter_ctrl, + .pid_filter = af9035_pid_filter, + .stream = DVB_USB_STREAM_BULK(0x85, 6, 87 * 188), }, }, @@ -1528,12 +1498,30 @@ static const struct usb_device_id af9035_id_table[] = { { DVB_USB_DEVICE(USB_VID_TERRATEC, 0x00aa, &af9035_props, "TerraTec Cinergy T Stick (rev. 2)", NULL) }, /* IT9135 devices */ -#if 0 - { DVB_USB_DEVICE(0x048d, 0x9135, - &af9035_props, "IT9135 reference design", NULL) }, - { DVB_USB_DEVICE(0x048d, 0x9006, - &af9035_props, "IT9135 reference design", NULL) }, -#endif + { DVB_USB_DEVICE(USB_VID_ITETECH, USB_PID_ITETECH_IT9135, + &af9035_props, "ITE 9135 Generic", RC_MAP_IT913X_V1) }, + { DVB_USB_DEVICE(USB_VID_ITETECH, USB_PID_ITETECH_IT9135_9005, + &af9035_props, "ITE 9135(9005) Generic", RC_MAP_IT913X_V2) }, + { DVB_USB_DEVICE(USB_VID_ITETECH, USB_PID_ITETECH_IT9135_9006, + &af9035_props, "ITE 9135(9006) Generic", RC_MAP_IT913X_V1) }, + { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_1835, + &af9035_props, "Avermedia A835B(1835)", RC_MAP_IT913X_V2) }, + { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_2835, + &af9035_props, "Avermedia A835B(2835)", RC_MAP_IT913X_V2) }, + { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_3835, + &af9035_props, "Avermedia A835B(3835)", RC_MAP_IT913X_V2) }, + { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_4835, + &af9035_props, "Avermedia A835B(4835)", RC_MAP_IT913X_V2) }, + { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_H335, + &af9035_props, "Avermedia H335", RC_MAP_IT913X_V2) }, + { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_KWORLD_UB499_2T_T09, + &af9035_props, "Kworld UB499-2T T09", RC_MAP_IT913X_V1) }, + { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_SVEON_STV22_IT9137, + &af9035_props, "Sveon STV22 Dual DVB-T HDTV", + RC_MAP_IT913X_V1) }, + { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_CTVDIGDUAL_V2, + &af9035_props, "Digital Dual TV Receiver CTVDIGDUAL_V2", + RC_MAP_IT913X_V1) }, /* XXX: that same ID [0ccd:0099] is used by af9015 driver too */ { DVB_USB_DEVICE(USB_VID_TERRATEC, 0x0099, &af9035_props, "TerraTec Cinergy T Stick Dual RC (rev. 2)", NULL) }, diff --git a/drivers/media/usb/dvb-usb-v2/af9035.h b/drivers/media/usb/dvb-usb-v2/af9035.h index a1c68d8..c21902f 100644 --- a/drivers/media/usb/dvb-usb-v2/af9035.h +++ b/drivers/media/usb/dvb-usb-v2/af9035.h @@ -62,6 +62,8 @@ struct state { u8 dual_mode:1; u16 eeprom_addr; struct af9033_config af9033_config[2]; + + struct af9033_ops ops; }; static const u32 clock_lut_af9035[] = { diff --git a/drivers/media/usb/dvb-usb-v2/az6007.c b/drivers/media/usb/dvb-usb-v2/az6007.c index c1051c3..c3c4b98 100644 --- a/drivers/media/usb/dvb-usb-v2/az6007.c +++ b/drivers/media/usb/dvb-usb-v2/az6007.c @@ -7,7 +7,7 @@ * http://linux.terratec.de/files/TERRATEC_H7/20110323_TERRATEC_H7_Linux.tar.gz * The original driver's license is GPL, as declared with MODULE_LICENSE() * - * Copyright (c) 2010-2012 Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (c) 2010-2012 Mauro Carvalho Chehab * Driver modified by in order to work with upstream drxk driver, and * tons of bugs got fixed, and converted to use dvb-usb-v2. * @@ -975,7 +975,7 @@ static struct usb_driver az6007_usb_driver = { module_usb_driver(az6007_usb_driver); MODULE_AUTHOR("Henry Wang <Henry.wang@AzureWave.com>"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_DESCRIPTION("Driver for AzureWave 6007 DVB-C/T USB2.0 and clones"); MODULE_VERSION("2.0"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c b/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c index 8a054d6..de02db8 100644 --- a/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c +++ b/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c @@ -164,7 +164,7 @@ static int dvb_usbv2_remote_init(struct dvb_usb_device *d) dev->driver_name = (char *) d->props->driver_name; dev->map_name = d->rc.map_name; dev->driver_type = d->rc.driver_type; - dev->allowed_protos = d->rc.allowed_protos; + rc_set_allowed_protocols(dev, d->rc.allowed_protos); dev->change_protocol = d->rc.change_protocol; dev->priv = d; diff --git a/drivers/media/usb/dvb-usb-v2/it913x.c b/drivers/media/usb/dvb-usb-v2/it913x.c deleted file mode 100644 index fe95a58..0000000 --- a/drivers/media/usb/dvb-usb-v2/it913x.c +++ /dev/null @@ -1,828 +0,0 @@ -/* - * DVB USB compliant linux driver for ITE IT9135 and IT9137 - * - * Copyright (C) 2011 Malcolm Priestley (tvboxspy@gmail.com) - * IT9135 (C) ITE Tech Inc. - * IT9137 (C) ITE Tech Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License Version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * - * see Documentation/dvb/README.dvb-usb for more information - * see Documentation/dvb/it9137.txt for firmware information - * - */ -#define DVB_USB_LOG_PREFIX "it913x" - -#include <linux/usb.h> -#include <linux/usb/input.h> -#include <media/rc-core.h> - -#include "dvb_usb.h" -#include "it913x-fe.h" - -/* debug */ -static int dvb_usb_it913x_debug; -#define it_debug(var, level, args...) \ - do { if ((var & level)) pr_debug(DVB_USB_LOG_PREFIX": " args); \ -} while (0) -#define deb_info(level, args...) it_debug(dvb_usb_it913x_debug, level, args) -#define info(args...) pr_info(DVB_USB_LOG_PREFIX": " args) - -module_param_named(debug, dvb_usb_it913x_debug, int, 0644); -MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able))."); - -static int dvb_usb_it913x_firmware; -module_param_named(firmware, dvb_usb_it913x_firmware, int, 0644); -MODULE_PARM_DESC(firmware, "set firmware 0=auto "\ - "1=IT9137 2=IT9135 V1 3=IT9135 V2"); -#define FW_IT9137 "dvb-usb-it9137-01.fw" -#define FW_IT9135_V1 "dvb-usb-it9135-01.fw" -#define FW_IT9135_V2 "dvb-usb-it9135-02.fw" - -DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); - -struct it913x_state { - struct ite_config it913x_config; - u8 pid_filter_onoff; - bool proprietary_ir; - int cmd_counter; -}; - -static u16 check_sum(u8 *p, u8 len) -{ - u16 sum = 0; - u8 i = 1; - while (i < len) - sum += (i++ & 1) ? (*p++) << 8 : *p++; - return ~sum; -} - -static int it913x_io(struct dvb_usb_device *d, u8 mode, u8 pro, - u8 cmd, u32 reg, u8 addr, u8 *data, u8 len) -{ - struct it913x_state *st = d->priv; - int ret = 0, i, buf_size = 1; - u8 *buff; - u8 rlen; - u16 chk_sum; - - buff = kzalloc(256, GFP_KERNEL); - if (!buff) { - info("USB Buffer Failed"); - return -ENOMEM; - } - - buff[buf_size++] = pro; - buff[buf_size++] = cmd; - buff[buf_size++] = st->cmd_counter; - - switch (mode) { - case READ_LONG: - case WRITE_LONG: - buff[buf_size++] = len; - buff[buf_size++] = 2; - buff[buf_size++] = (reg >> 24); - buff[buf_size++] = (reg >> 16) & 0xff; - buff[buf_size++] = (reg >> 8) & 0xff; - buff[buf_size++] = reg & 0xff; - break; - case READ_SHORT: - buff[buf_size++] = addr; - break; - case WRITE_SHORT: - buff[buf_size++] = len; - buff[buf_size++] = addr; - buff[buf_size++] = (reg >> 8) & 0xff; - buff[buf_size++] = reg & 0xff; - break; - case READ_DATA: - case WRITE_DATA: - break; - case WRITE_CMD: - mode = 7; - break; - default: - kfree(buff); - return -EINVAL; - } - - if (mode & 1) { - for (i = 0; i < len ; i++) - buff[buf_size++] = data[i]; - } - chk_sum = check_sum(&buff[1], buf_size); - - buff[buf_size++] = chk_sum >> 8; - buff[0] = buf_size; - buff[buf_size++] = (chk_sum & 0xff); - - ret = dvb_usbv2_generic_rw(d, buff, buf_size, buff, (mode & 1) ? - 5 : len + 5); - if (ret < 0) - goto error; - - rlen = (mode & 0x1) ? 0x1 : len; - - if (mode & 1) - ret = buff[2]; - else - memcpy(data, &buff[3], rlen); - - st->cmd_counter++; - -error: kfree(buff); - - return ret; -} - -static int it913x_wr_reg(struct dvb_usb_device *d, u8 pro, u32 reg , u8 data) -{ - int ret; - u8 b[1]; - b[0] = data; - ret = it913x_io(d, WRITE_LONG, pro, - CMD_DEMOD_WRITE, reg, 0, b, sizeof(b)); - - return ret; -} - -static int it913x_read_reg(struct dvb_usb_device *d, u32 reg) -{ - int ret; - u8 data[1]; - - ret = it913x_io(d, READ_LONG, DEV_0, - CMD_DEMOD_READ, reg, 0, &data[0], sizeof(data)); - - return (ret < 0) ? ret : data[0]; -} - -static int it913x_query(struct dvb_usb_device *d, u8 pro) -{ - struct it913x_state *st = d->priv; - int ret, i; - u8 data[4]; - u8 ver; - - for (i = 0; i < 5; i++) { - ret = it913x_io(d, READ_LONG, pro, CMD_DEMOD_READ, - 0x1222, 0, &data[0], 3); - ver = data[0]; - if (ver > 0 && ver < 3) - break; - msleep(100); - } - - if (ver < 1 || ver > 2) { - info("Failed to identify chip version applying 1"); - st->it913x_config.chip_ver = 0x1; - st->it913x_config.chip_type = 0x9135; - return 0; - } - - st->it913x_config.chip_ver = ver; - st->it913x_config.chip_type = (u16)(data[2] << 8) + data[1]; - - info("Chip Version=%02x Chip Type=%04x", st->it913x_config.chip_ver, - st->it913x_config.chip_type); - - ret = it913x_io(d, READ_SHORT, pro, - CMD_QUERYINFO, 0, 0x1, &data[0], 4); - - st->it913x_config.firmware = (data[0] << 24) | (data[1] << 16) | - (data[2] << 8) | data[3]; - - return ret; -} - -static int it913x_pid_filter_ctrl(struct dvb_usb_adapter *adap, int onoff) -{ - struct dvb_usb_device *d = adap_to_d(adap); - struct it913x_state *st = adap_to_priv(adap); - int ret; - u8 pro = (adap->id == 0) ? DEV_0_DMOD : DEV_1_DMOD; - - mutex_lock(&d->i2c_mutex); - - deb_info(1, "PID_C (%02x)", onoff); - - st->pid_filter_onoff = adap->pid_filtering; - ret = it913x_wr_reg(d, pro, PID_EN, st->pid_filter_onoff); - - mutex_unlock(&d->i2c_mutex); - return ret; -} - -static int it913x_pid_filter(struct dvb_usb_adapter *adap, - int index, u16 pid, int onoff) -{ - struct dvb_usb_device *d = adap_to_d(adap); - struct it913x_state *st = adap_to_priv(adap); - int ret; - u8 pro = (adap->id == 0) ? DEV_0_DMOD : DEV_1_DMOD; - - mutex_lock(&d->i2c_mutex); - - deb_info(1, "PID_F (%02x)", onoff); - - ret = it913x_wr_reg(d, pro, PID_LSB, (u8)(pid & 0xff)); - - ret |= it913x_wr_reg(d, pro, PID_MSB, (u8)(pid >> 8)); - - ret |= it913x_wr_reg(d, pro, PID_INX_EN, (u8)onoff); - - ret |= it913x_wr_reg(d, pro, PID_INX, (u8)(index & 0x1f)); - - if (d->udev->speed == USB_SPEED_HIGH && pid == 0x2000) { - ret |= it913x_wr_reg(d , pro, PID_EN, !onoff); - st->pid_filter_onoff = !onoff; - } else - st->pid_filter_onoff = - adap->pid_filtering; - - mutex_unlock(&d->i2c_mutex); - return 0; -} - - -static int it913x_return_status(struct dvb_usb_device *d) -{ - struct it913x_state *st = d->priv; - int ret = it913x_query(d, DEV_0); - if (st->it913x_config.firmware > 0) - info("Firmware Version %d", st->it913x_config.firmware); - - return ret; -} - -static int it913x_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], - int num) -{ - struct dvb_usb_device *d = i2c_get_adapdata(adap); - static u8 data[256]; - int ret; - u32 reg; - u8 pro; - - mutex_lock(&d->i2c_mutex); - - deb_info(2, "num of messages %d address %02x", num, msg[0].addr); - - pro = (msg[0].addr & 0x2) ? DEV_0_DMOD : 0x0; - pro |= (msg[0].addr & 0x20) ? DEV_1 : DEV_0; - memcpy(data, msg[0].buf, msg[0].len); - reg = (data[0] << 24) + (data[1] << 16) + - (data[2] << 8) + data[3]; - if (num == 2) { - ret = it913x_io(d, READ_LONG, pro, - CMD_DEMOD_READ, reg, 0, data, msg[1].len); - memcpy(msg[1].buf, data, msg[1].len); - } else - ret = it913x_io(d, WRITE_LONG, pro, CMD_DEMOD_WRITE, - reg, 0, &data[4], msg[0].len - 4); - - mutex_unlock(&d->i2c_mutex); - - return ret; -} - -static u32 it913x_i2c_func(struct i2c_adapter *adapter) -{ - return I2C_FUNC_I2C; -} - -static struct i2c_algorithm it913x_i2c_algo = { - .master_xfer = it913x_i2c_xfer, - .functionality = it913x_i2c_func, -}; - -/* Callbacks for DVB USB */ -#if IS_ENABLED(CONFIG_RC_CORE) -static int it913x_rc_query(struct dvb_usb_device *d) -{ - u8 ibuf[4]; - int ret; - u32 key; - /* Avoid conflict with frontends*/ - mutex_lock(&d->i2c_mutex); - - ret = it913x_io(d, READ_LONG, PRO_LINK, CMD_IR_GET, - 0, 0, &ibuf[0], sizeof(ibuf)); - - if ((ibuf[2] + ibuf[3]) == 0xff) { - key = ibuf[2]; - key += ibuf[0] << 16; - key += ibuf[1] << 8; - deb_info(1, "NEC Extended Key =%08x", key); - if (d->rc_dev != NULL) - rc_keydown(d->rc_dev, key, 0); - } - - mutex_unlock(&d->i2c_mutex); - - return ret; -} - -static int it913x_get_rc_config(struct dvb_usb_device *d, struct dvb_usb_rc *rc) -{ - struct it913x_state *st = d->priv; - - if (st->proprietary_ir == false) { - rc->map_name = NULL; - return 0; - } - - rc->allowed_protos = RC_BIT_NEC; - rc->query = it913x_rc_query; - rc->interval = 250; - - return 0; -} -#else - #define it913x_get_rc_config NULL -#endif - -/* Firmware sets raw */ -static const char fw_it9135_v1[] = FW_IT9135_V1; -static const char fw_it9135_v2[] = FW_IT9135_V2; -static const char fw_it9137[] = FW_IT9137; - -static void ite_get_firmware_name(struct dvb_usb_device *d, - const char **name) -{ - struct it913x_state *st = d->priv; - int sw; - /* auto switch */ - if (le16_to_cpu(d->udev->descriptor.idVendor) == USB_VID_KWORLD_2) - sw = IT9137_FW; - else if (st->it913x_config.chip_ver == 1) - sw = IT9135_V1_FW; - else - sw = IT9135_V2_FW; - - /* force switch */ - if (dvb_usb_it913x_firmware != IT9135_AUTO) - sw = dvb_usb_it913x_firmware; - - switch (sw) { - case IT9135_V1_FW: - st->it913x_config.firmware_ver = 1; - st->it913x_config.adc_x2 = 1; - st->it913x_config.read_slevel = false; - *name = fw_it9135_v1; - break; - case IT9135_V2_FW: - st->it913x_config.firmware_ver = 1; - st->it913x_config.adc_x2 = 1; - st->it913x_config.read_slevel = false; - *name = fw_it9135_v2; - switch (st->it913x_config.tuner_id_0) { - case IT9135_61: - case IT9135_62: - break; - default: - info("Unknown tuner ID applying default 0x60"); - case IT9135_60: - st->it913x_config.tuner_id_0 = IT9135_60; - } - break; - case IT9137_FW: - default: - st->it913x_config.firmware_ver = 0; - st->it913x_config.adc_x2 = 0; - st->it913x_config.read_slevel = true; - *name = fw_it9137; - } - - return; -} - -#define TS_MPEG_PKT_SIZE 188 -#define EP_LOW 21 -#define TS_BUFFER_SIZE_PID (EP_LOW*TS_MPEG_PKT_SIZE) -#define EP_HIGH 348 -#define TS_BUFFER_SIZE_MAX (EP_HIGH*TS_MPEG_PKT_SIZE) - -static int it913x_get_stream_config(struct dvb_frontend *fe, u8 *ts_type, - struct usb_data_stream_properties *stream) -{ - struct dvb_usb_adapter *adap = fe_to_adap(fe); - if (adap->pid_filtering) - stream->u.bulk.buffersize = TS_BUFFER_SIZE_PID; - else - stream->u.bulk.buffersize = TS_BUFFER_SIZE_MAX; - - return 0; -} - -static int it913x_select_config(struct dvb_usb_device *d) -{ - struct it913x_state *st = d->priv; - int ret, reg; - - ret = it913x_return_status(d); - if (ret < 0) - return ret; - - if (st->it913x_config.chip_ver == 0x02 - && st->it913x_config.chip_type == 0x9135) - reg = it913x_read_reg(d, 0x461d); - else - reg = it913x_read_reg(d, 0x461b); - - if (reg < 0) - return reg; - - if (reg == 0) { - st->it913x_config.dual_mode = 0; - st->it913x_config.tuner_id_0 = IT9135_38; - st->proprietary_ir = true; - } else { - /* TS mode */ - reg = it913x_read_reg(d, 0x49c5); - if (reg < 0) - return reg; - st->it913x_config.dual_mode = reg; - - /* IR mode type */ - reg = it913x_read_reg(d, 0x49ac); - if (reg < 0) - return reg; - if (reg == 5) { - info("Remote propriety (raw) mode"); - st->proprietary_ir = true; - } else if (reg == 1) { - info("Remote HID mode NOT SUPPORTED"); - st->proprietary_ir = false; - } - - /* Tuner_id */ - reg = it913x_read_reg(d, 0x49d0); - if (reg < 0) - return reg; - st->it913x_config.tuner_id_0 = reg; - } - - info("Dual mode=%x Tuner Type=%x", st->it913x_config.dual_mode, - st->it913x_config.tuner_id_0); - - return ret; -} - -static int it913x_streaming_ctrl(struct dvb_frontend *fe, int onoff) -{ - struct dvb_usb_adapter *adap = fe_to_adap(fe); - struct dvb_usb_device *d = adap_to_d(adap); - struct it913x_state *st = fe_to_priv(fe); - int ret = 0; - u8 pro = (adap->id == 0) ? DEV_0_DMOD : DEV_1_DMOD; - - deb_info(1, "STM (%02x)", onoff); - - if (!onoff) { - mutex_lock(&d->i2c_mutex); - - ret = it913x_wr_reg(d, pro, PID_RST, 0x1); - - mutex_unlock(&d->i2c_mutex); - st->pid_filter_onoff = - adap->pid_filtering; - - } - - return ret; -} - -static int it913x_identify_state(struct dvb_usb_device *d, const char **name) -{ - struct it913x_state *st = d->priv; - int ret; - u8 reg; - - /* Read and select config */ - ret = it913x_select_config(d); - if (ret < 0) - return ret; - - ite_get_firmware_name(d, name); - - if (st->it913x_config.firmware > 0) - return WARM; - - if (st->it913x_config.dual_mode) { - st->it913x_config.tuner_id_1 = it913x_read_reg(d, 0x49e0); - ret = it913x_wr_reg(d, DEV_0, GPIOH1_EN, 0x1); - ret |= it913x_wr_reg(d, DEV_0, GPIOH1_ON, 0x1); - ret |= it913x_wr_reg(d, DEV_0, GPIOH1_O, 0x1); - msleep(50); - ret |= it913x_wr_reg(d, DEV_0, GPIOH1_O, 0x0); - msleep(50); - reg = it913x_read_reg(d, GPIOH1_O); - if (reg == 0) { - ret |= it913x_wr_reg(d, DEV_0, GPIOH1_O, 0x1); - ret |= it913x_return_status(d); - if (ret != 0) - ret = it913x_wr_reg(d, DEV_0, - GPIOH1_O, 0x0); - } - } - - reg = it913x_read_reg(d, IO_MUX_POWER_CLK); - - if (st->it913x_config.dual_mode) { - ret |= it913x_wr_reg(d, DEV_0, 0x4bfb, CHIP2_I2C_ADDR); - if (st->it913x_config.firmware_ver == 1) - ret |= it913x_wr_reg(d, DEV_0, 0xcfff, 0x1); - else - ret |= it913x_wr_reg(d, DEV_0, CLK_O_EN, 0x1); - } else { - ret |= it913x_wr_reg(d, DEV_0, 0x4bfb, 0x0); - if (st->it913x_config.firmware_ver == 1) - ret |= it913x_wr_reg(d, DEV_0, 0xcfff, 0x0); - else - ret |= it913x_wr_reg(d, DEV_0, CLK_O_EN, 0x0); - } - - ret |= it913x_wr_reg(d, DEV_0, I2C_CLK, I2C_CLK_100); - - return (ret < 0) ? ret : COLD; -} - -static int it913x_download_firmware(struct dvb_usb_device *d, - const struct firmware *fw) -{ - struct it913x_state *st = d->priv; - int ret = 0, i = 0, pos = 0; - u8 packet_size, min_pkt; - u8 *fw_data; - - ret = it913x_wr_reg(d, DEV_0, I2C_CLK, I2C_CLK_100); - - info("FRM Starting Firmware Download"); - - /* Multi firmware loader */ - /* This uses scatter write firmware headers */ - /* The firmware must start with 03 XX 00 */ - /* and be the extact firmware length */ - - if (st->it913x_config.chip_ver == 2) - min_pkt = 0x11; - else - min_pkt = 0x19; - - while (i <= fw->size) { - if (((fw->data[i] == 0x3) && (fw->data[i + 2] == 0x0)) - || (i == fw->size)) { - packet_size = i - pos; - if ((packet_size > min_pkt) || (i == fw->size)) { - fw_data = (u8 *)(fw->data + pos); - pos += packet_size; - if (packet_size > 0) { - ret = it913x_io(d, WRITE_DATA, - DEV_0, CMD_SCATTER_WRITE, 0, - 0, fw_data, packet_size); - if (ret < 0) - break; - } - udelay(1000); - } - } - i++; - } - - if (ret < 0) - info("FRM Firmware Download Failed (%d)" , ret); - else - info("FRM Firmware Download Completed - Resetting Device"); - - msleep(30); - - ret = it913x_io(d, WRITE_CMD, DEV_0, CMD_BOOT, 0, 0, NULL, 0); - if (ret < 0) - info("FRM Device not responding to reboot"); - - ret = it913x_return_status(d); - if (st->it913x_config.firmware == 0) { - info("FRM Failed to reboot device"); - return -ENODEV; - } - - msleep(30); - - ret = it913x_wr_reg(d, DEV_0, I2C_CLK, I2C_CLK_400); - - msleep(30); - - /* Tuner function */ - if (st->it913x_config.dual_mode) - ret |= it913x_wr_reg(d, DEV_0_DMOD , 0xec4c, 0xa0); - else - ret |= it913x_wr_reg(d, DEV_0_DMOD , 0xec4c, 0x68); - - if ((st->it913x_config.chip_ver == 1) && - (st->it913x_config.chip_type == 0x9135)) { - ret |= it913x_wr_reg(d, DEV_0, PADODPU, 0x0); - ret |= it913x_wr_reg(d, DEV_0, AGC_O_D, 0x0); - if (st->it913x_config.dual_mode) { - ret |= it913x_wr_reg(d, DEV_1, PADODPU, 0x0); - ret |= it913x_wr_reg(d, DEV_1, AGC_O_D, 0x0); - } - } - - return (ret < 0) ? -ENODEV : 0; -} - -static int it913x_name(struct dvb_usb_adapter *adap) -{ - struct dvb_usb_device *d = adap_to_d(adap); - const char *desc = d->name; - char *fe_name[] = {"_1", "_2", "_3", "_4"}; - char *name = adap->fe[0]->ops.info.name; - - strlcpy(name, desc, 128); - strlcat(name, fe_name[adap->id], 128); - - return 0; -} - -static int it913x_frontend_attach(struct dvb_usb_adapter *adap) -{ - struct dvb_usb_device *d = adap_to_d(adap); - struct it913x_state *st = d->priv; - int ret = 0; - u8 adap_addr = I2C_BASE_ADDR + (adap->id << 5); - u16 ep_size = (adap->pid_filtering) ? TS_BUFFER_SIZE_PID / 4 : - TS_BUFFER_SIZE_MAX / 4; - u8 pkt_size = 0x80; - - if (d->udev->speed != USB_SPEED_HIGH) - pkt_size = 0x10; - - st->it913x_config.adf = it913x_read_reg(d, IO_MUX_POWER_CLK); - - adap->fe[0] = dvb_attach(it913x_fe_attach, - &d->i2c_adap, adap_addr, &st->it913x_config); - - if (adap->id == 0 && adap->fe[0]) { - it913x_wr_reg(d, DEV_0_DMOD, MP2_SW_RST, 0x1); - it913x_wr_reg(d, DEV_0_DMOD, MP2IF2_SW_RST, 0x1); - it913x_wr_reg(d, DEV_0, EP0_TX_EN, 0x0f); - it913x_wr_reg(d, DEV_0, EP0_TX_NAK, 0x1b); - if (st->proprietary_ir == false) /* Enable endpoint 3 */ - it913x_wr_reg(d, DEV_0, EP0_TX_EN, 0x3f); - else - it913x_wr_reg(d, DEV_0, EP0_TX_EN, 0x2f); - it913x_wr_reg(d, DEV_0, EP4_TX_LEN_LSB, - ep_size & 0xff); - it913x_wr_reg(d, DEV_0, EP4_TX_LEN_MSB, ep_size >> 8); - ret = it913x_wr_reg(d, DEV_0, EP4_MAX_PKT, pkt_size); - } else if (adap->id == 1 && adap->fe[0]) { - if (st->proprietary_ir == false) - it913x_wr_reg(d, DEV_0, EP0_TX_EN, 0x7f); - else - it913x_wr_reg(d, DEV_0, EP0_TX_EN, 0x6f); - it913x_wr_reg(d, DEV_0, EP5_TX_LEN_LSB, - ep_size & 0xff); - it913x_wr_reg(d, DEV_0, EP5_TX_LEN_MSB, ep_size >> 8); - it913x_wr_reg(d, DEV_0, EP5_MAX_PKT, pkt_size); - it913x_wr_reg(d, DEV_0_DMOD, MP2IF2_EN, 0x1); - it913x_wr_reg(d, DEV_1_DMOD, MP2IF_SERIAL, 0x1); - it913x_wr_reg(d, DEV_1, TOP_HOSTB_SER_MODE, 0x1); - it913x_wr_reg(d, DEV_0_DMOD, TSIS_ENABLE, 0x1); - it913x_wr_reg(d, DEV_0_DMOD, MP2_SW_RST, 0x0); - it913x_wr_reg(d, DEV_0_DMOD, MP2IF2_SW_RST, 0x0); - it913x_wr_reg(d, DEV_0_DMOD, MP2IF2_HALF_PSB, 0x0); - it913x_wr_reg(d, DEV_0_DMOD, MP2IF_STOP_EN, 0x1); - it913x_wr_reg(d, DEV_1_DMOD, MPEG_FULL_SPEED, 0x0); - ret = it913x_wr_reg(d, DEV_1_DMOD, MP2IF_STOP_EN, 0x0); - } else - return -ENODEV; - - ret |= it913x_name(adap); - - return ret; -} - -/* DVB USB Driver */ -static int it913x_get_adapter_count(struct dvb_usb_device *d) -{ - struct it913x_state *st = d->priv; - if (st->it913x_config.dual_mode) - return 2; - return 1; -} - -static struct dvb_usb_device_properties it913x_properties = { - .driver_name = KBUILD_MODNAME, - .owner = THIS_MODULE, - .bInterfaceNumber = 0, - .generic_bulk_ctrl_endpoint = 0x02, - .generic_bulk_ctrl_endpoint_response = 0x81, - - .adapter_nr = adapter_nr, - .size_of_priv = sizeof(struct it913x_state), - - .identify_state = it913x_identify_state, - .i2c_algo = &it913x_i2c_algo, - - .download_firmware = it913x_download_firmware, - - .frontend_attach = it913x_frontend_attach, - .get_rc_config = it913x_get_rc_config, - .get_stream_config = it913x_get_stream_config, - .get_adapter_count = it913x_get_adapter_count, - .streaming_ctrl = it913x_streaming_ctrl, - - - .adapter = { - { - .caps = DVB_USB_ADAP_HAS_PID_FILTER| - DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF, - .pid_filter_count = 32, - .pid_filter = it913x_pid_filter, - .pid_filter_ctrl = it913x_pid_filter_ctrl, - .stream = - DVB_USB_STREAM_BULK(0x84, 10, TS_BUFFER_SIZE_MAX), - }, - { - .caps = DVB_USB_ADAP_HAS_PID_FILTER| - DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF, - .pid_filter_count = 32, - .pid_filter = it913x_pid_filter, - .pid_filter_ctrl = it913x_pid_filter_ctrl, - .stream = - DVB_USB_STREAM_BULK(0x85, 10, TS_BUFFER_SIZE_MAX), - } - } -}; - -static const struct usb_device_id it913x_id_table[] = { - { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_KWORLD_UB499_2T_T09, - &it913x_properties, "Kworld UB499-2T T09(IT9137)", - RC_MAP_IT913X_V1) }, - { DVB_USB_DEVICE(USB_VID_ITETECH, USB_PID_ITETECH_IT9135, - &it913x_properties, "ITE 9135 Generic", - RC_MAP_IT913X_V1) }, - { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_SVEON_STV22_IT9137, - &it913x_properties, "Sveon STV22 Dual DVB-T HDTV(IT9137)", - RC_MAP_IT913X_V1) }, - { DVB_USB_DEVICE(USB_VID_ITETECH, USB_PID_ITETECH_IT9135_9005, - &it913x_properties, "ITE 9135(9005) Generic", - RC_MAP_IT913X_V2) }, - { DVB_USB_DEVICE(USB_VID_ITETECH, USB_PID_ITETECH_IT9135_9006, - &it913x_properties, "ITE 9135(9006) Generic", - RC_MAP_IT913X_V1) }, - { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_1835, - &it913x_properties, "Avermedia A835B(1835)", - RC_MAP_IT913X_V2) }, - { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_2835, - &it913x_properties, "Avermedia A835B(2835)", - RC_MAP_IT913X_V2) }, - { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_3835, - &it913x_properties, "Avermedia A835B(3835)", - RC_MAP_IT913X_V2) }, - { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A835B_4835, - &it913x_properties, "Avermedia A835B(4835)", - RC_MAP_IT913X_V2) }, - { DVB_USB_DEVICE(USB_VID_KWORLD_2, USB_PID_CTVDIGDUAL_V2, - &it913x_properties, "Digital Dual TV Receiver CTVDIGDUAL_V2", - RC_MAP_IT913X_V1) }, - { DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_H335, - &it913x_properties, "Avermedia H335", - RC_MAP_IT913X_V2) }, - {} /* Terminating entry */ -}; - -MODULE_DEVICE_TABLE(usb, it913x_id_table); - -static struct usb_driver it913x_driver = { - .name = KBUILD_MODNAME, - .probe = dvb_usbv2_probe, - .disconnect = dvb_usbv2_disconnect, - .suspend = dvb_usbv2_suspend, - .resume = dvb_usbv2_resume, - .id_table = it913x_id_table, -}; - -module_usb_driver(it913x_driver); - -MODULE_AUTHOR("Malcolm Priestley <tvboxspy@gmail.com>"); -MODULE_DESCRIPTION("it913x USB 2 Driver"); -MODULE_VERSION("1.33"); -MODULE_LICENSE("GPL"); -MODULE_FIRMWARE(FW_IT9135_V1); -MODULE_FIRMWARE(FW_IT9135_V2); -MODULE_FIRMWARE(FW_IT9137); - diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index fda5c64..c83c16c 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -24,6 +24,7 @@ #include "rtl2830.h" #include "rtl2832.h" +#include "rtl2832_sdr.h" #include "qt1010.h" #include "mt2060.h" @@ -35,6 +36,9 @@ #include "tua9001.h" #include "r820t.h" +static int rtl28xxu_disable_rc; +module_param_named(disable_rc, rtl28xxu_disable_rc, int, 0644); +MODULE_PARM_DESC(disable_rc, "disable RTL2832U remote controller"); DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); static int rtl28xxu_ctrl_msg(struct dvb_usb_device *d, struct rtl28xxu_req *req) @@ -513,7 +517,7 @@ err: return ret; } -static struct rtl2830_config rtl28xxu_rtl2830_mt2060_config = { +static const struct rtl2830_config rtl28xxu_rtl2830_mt2060_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, .ts_mode = 0, @@ -524,7 +528,7 @@ static struct rtl2830_config rtl28xxu_rtl2830_mt2060_config = { }; -static struct rtl2830_config rtl28xxu_rtl2830_qt1010_config = { +static const struct rtl2830_config rtl28xxu_rtl2830_qt1010_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, .ts_mode = 0, @@ -534,7 +538,7 @@ static struct rtl2830_config rtl28xxu_rtl2830_qt1010_config = { .agc_targ_val = 0x2d, }; -static struct rtl2830_config rtl28xxu_rtl2830_mxl5005s_config = { +static const struct rtl2830_config rtl28xxu_rtl2830_mxl5005s_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, .ts_mode = 0, @@ -548,7 +552,7 @@ static int rtl2831u_frontend_attach(struct dvb_usb_adapter *adap) { struct dvb_usb_device *d = adap_to_d(adap); struct rtl28xxu_priv *priv = d_to_priv(d); - struct rtl2830_config *rtl2830_config; + const struct rtl2830_config *rtl2830_config; int ret; dev_dbg(&d->udev->dev, "%s:\n", __func__); @@ -583,33 +587,31 @@ err: return ret; } -static struct rtl2832_config rtl28xxu_rtl2832_fc0012_config = { +static const struct rtl2832_config rtl28xxu_rtl2832_fc0012_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, - .if_dvbt = 0, .tuner = TUNER_RTL2832_FC0012 }; -static struct rtl2832_config rtl28xxu_rtl2832_fc0013_config = { +static const struct rtl2832_config rtl28xxu_rtl2832_fc0013_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, - .if_dvbt = 0, .tuner = TUNER_RTL2832_FC0013 }; -static struct rtl2832_config rtl28xxu_rtl2832_tua9001_config = { +static const struct rtl2832_config rtl28xxu_rtl2832_tua9001_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, .tuner = TUNER_RTL2832_TUA9001, }; -static struct rtl2832_config rtl28xxu_rtl2832_e4000_config = { +static const struct rtl2832_config rtl28xxu_rtl2832_e4000_config = { .i2c_addr = 0x10, /* 0x20 */ .xtal = 28800000, .tuner = TUNER_RTL2832_E4000, }; -static struct rtl2832_config rtl28xxu_rtl2832_r820t_config = { +static const struct rtl2832_config rtl28xxu_rtl2832_r820t_config = { .i2c_addr = 0x10, .xtal = 28800000, .tuner = TUNER_RTL2832_R820T, @@ -733,7 +735,7 @@ static int rtl2832u_frontend_attach(struct dvb_usb_adapter *adap) int ret; struct dvb_usb_device *d = adap_to_d(adap); struct rtl28xxu_priv *priv = d_to_priv(d); - struct rtl2832_config *rtl2832_config; + const struct rtl2832_config *rtl2832_config; dev_dbg(&d->udev->dev, "%s:\n", __func__); @@ -772,6 +774,9 @@ static int rtl2832u_frontend_attach(struct dvb_usb_adapter *adap) goto err; } + /* RTL2832 I2C repeater */ + priv->demod_i2c_adapter = rtl2832_get_i2c_adapter(adap->fe[0]); + /* set fe callback */ adap->fe[0]->callback = rtl2832u_frontend_callback; @@ -851,11 +856,6 @@ err: return ret; } -static const struct e4000_config rtl2832u_e4000_config = { - .i2c_addr = 0x64, - .clock = 28800000, -}; - static const struct fc2580_config rtl2832u_fc2580_config = { .i2c_addr = 0x56, .clock = 16384000, @@ -889,10 +889,14 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) int ret; struct dvb_usb_device *d = adap_to_d(adap); struct rtl28xxu_priv *priv = d_to_priv(d); - struct dvb_frontend *fe; + struct dvb_frontend *fe = NULL; + struct i2c_board_info info; + struct i2c_client *client; dev_dbg(&d->udev->dev, "%s:\n", __func__); + memset(&info, 0, sizeof(struct i2c_board_info)); + switch (priv->tuner) { case TUNER_RTL2832_FC0012: fe = dvb_attach(fc0012_attach, adap->fe[0], @@ -902,7 +906,10 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) * that to the tuner driver */ adap->fe[0]->ops.read_signal_strength = adap->fe[0]->ops.tuner_ops.get_rf_strength; - return 0; + + /* attach SDR */ + dvb_attach(rtl2832_sdr_attach, adap->fe[0], &d->i2c_adap, + &rtl28xxu_rtl2832_fc0012_config, NULL); break; case TUNER_RTL2832_FC0013: fe = dvb_attach(fc0013_attach, adap->fe[0], @@ -911,10 +918,43 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) /* fc0013 also supports signal strength reading */ adap->fe[0]->ops.read_signal_strength = adap->fe[0]->ops.tuner_ops.get_rf_strength; - return 0; - case TUNER_RTL2832_E4000: - fe = dvb_attach(e4000_attach, adap->fe[0], &d->i2c_adap, - &rtl2832u_e4000_config); + + /* attach SDR */ + dvb_attach(rtl2832_sdr_attach, adap->fe[0], &d->i2c_adap, + &rtl28xxu_rtl2832_fc0013_config, NULL); + break; + case TUNER_RTL2832_E4000: { + struct v4l2_subdev *sd; + struct i2c_adapter *i2c_adap_internal = + rtl2832_get_private_i2c_adapter(adap->fe[0]); + struct e4000_config e4000_config = { + .fe = adap->fe[0], + .clock = 28800000, + }; + + strlcpy(info.type, "e4000", I2C_NAME_SIZE); + info.addr = 0x64; + info.platform_data = &e4000_config; + + request_module(info.type); + client = i2c_new_device(priv->demod_i2c_adapter, &info); + if (client == NULL || client->dev.driver == NULL) + break; + + if (!try_module_get(client->dev.driver->owner)) { + i2c_unregister_device(client); + break; + } + + priv->client = client; + sd = i2c_get_clientdata(client); + i2c_set_adapdata(i2c_adap_internal, d); + + /* attach SDR */ + dvb_attach(rtl2832_sdr_attach, adap->fe[0], + i2c_adap_internal, + &rtl28xxu_rtl2832_e4000_config, sd); + } break; case TUNER_RTL2832_FC2580: fe = dvb_attach(fc2580_attach, adap->fe[0], &d->i2c_adap, @@ -940,6 +980,10 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) /* Use tuner to get the signal strength */ adap->fe[0]->ops.read_signal_strength = adap->fe[0]->ops.tuner_ops.get_rf_strength; + + /* attach SDR */ + dvb_attach(rtl2832_sdr_attach, adap->fe[0], &d->i2c_adap, + &rtl28xxu_rtl2832_r820t_config, NULL); break; case TUNER_RTL2832_R828D: /* power off mn88472 demod on GPIO0 */ @@ -963,12 +1007,11 @@ static int rtl2832u_tuner_attach(struct dvb_usb_adapter *adap) adap->fe[0]->ops.tuner_ops.get_rf_strength; break; default: - fe = NULL; dev_err(&d->udev->dev, "%s: unknown tuner=%d\n", KBUILD_MODNAME, priv->tuner); } - if (fe == NULL) { + if (fe == NULL && priv->client == NULL) { ret = -ENODEV; goto err; } @@ -1013,6 +1056,22 @@ err: return ret; } +static void rtl28xxu_exit(struct dvb_usb_device *d) +{ + struct rtl28xxu_priv *priv = d->priv; + struct i2c_client *client = priv->client; + + dev_dbg(&d->udev->dev, "%s:\n", __func__); + + /* remove I2C tuner */ + if (client) { + module_put(client->dev.driver->owner); + i2c_unregister_device(client); + } + + return; +} + static int rtl2831u_power_ctrl(struct dvb_usb_device *d, int onoff) { int ret; @@ -1322,6 +1381,10 @@ err: static int rtl2832u_get_rc_config(struct dvb_usb_device *d, struct dvb_usb_rc *rc) { + /* disable IR interrupts in order to avoid SDR sample loss */ + if (rtl28xxu_disable_rc) + return rtl28xx_wr_reg(d, IR_RX_IE, 0x00); + /* load empty to enable rc */ if (!rc->map_name) rc->map_name = RC_MAP_EMPTY; @@ -1371,6 +1434,7 @@ static const struct dvb_usb_device_properties rtl2832u_props = { .frontend_attach = rtl2832u_frontend_attach, .tuner_attach = rtl2832u_tuner_attach, .init = rtl28xxu_init, + .exit = rtl28xxu_exit, .get_rc_config = rtl2832u_get_rc_config, .num_adapters = 1, @@ -1382,6 +1446,7 @@ static const struct dvb_usb_device_properties rtl2832u_props = { }; static const struct usb_device_id rtl28xxu_id_table[] = { + /* RTL2831U devices: */ { DVB_USB_DEVICE(USB_VID_REALTEK, USB_PID_REALTEK_RTL2831U, &rtl2831u_props, "Realtek RTL2831U reference design", NULL) }, { DVB_USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_FREECOM_DVBT, @@ -1389,6 +1454,7 @@ static const struct usb_device_id rtl28xxu_id_table[] = { { DVB_USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_FREECOM_DVBT_2, &rtl2831u_props, "Freecom USB2.0 DVB-T", NULL) }, + /* RTL2832U devices: */ { DVB_USB_DEVICE(USB_VID_REALTEK, 0x2832, &rtl2832u_props, "Realtek RTL2832U reference design", NULL) }, { DVB_USB_DEVICE(USB_VID_REALTEK, 0x2838, @@ -1401,6 +1467,8 @@ static const struct usb_device_id rtl28xxu_id_table[] = { &rtl2832u_props, "TerraTec NOXON DAB Stick", NULL) }, { DVB_USB_DEVICE(USB_VID_TERRATEC, USB_PID_NOXON_DAB_STICK_REV2, &rtl2832u_props, "TerraTec NOXON DAB Stick (rev 2)", NULL) }, + { DVB_USB_DEVICE(USB_VID_TERRATEC, USB_PID_NOXON_DAB_STICK_REV3, + &rtl2832u_props, "TerraTec NOXON DAB Stick (rev 3)", NULL) }, { DVB_USB_DEVICE(USB_VID_GTEK, USB_PID_TREKSTOR_TERRES_2_0, &rtl2832u_props, "Trekstor DVB-T Stick Terres 2.0", NULL) }, { DVB_USB_DEVICE(USB_VID_DEXATEK, 0x1101, @@ -1429,9 +1497,14 @@ static const struct usb_device_id rtl28xxu_id_table[] = { &rtl2832u_props, "Leadtek WinFast DTV Dongle mini", NULL) }, { DVB_USB_DEVICE(USB_VID_GTEK, USB_PID_CPYTO_REDI_PC50A, &rtl2832u_props, "Crypto ReDi PC 50 A", NULL) }, + { DVB_USB_DEVICE(USB_VID_KYE, 0x707f, + &rtl2832u_props, "Genius TVGo DVB-T03", NULL) }, + /* RTL2832P devices: */ { DVB_USB_DEVICE(USB_VID_HANFTEK, 0x0131, &rtl2832u_props, "Astrometa DVB-T2", NULL) }, + { DVB_USB_DEVICE(USB_VID_KYE, 0x707f, + &rtl2832u_props, "Genius TVGo DVB-T03", NULL) }, { } }; MODULE_DEVICE_TABLE(usb, rtl28xxu_id_table); diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.h b/drivers/media/usb/dvb-usb-v2/rtl28xxu.h index 2142bcb..a26cab1 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.h +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.h @@ -55,7 +55,9 @@ struct rtl28xxu_priv { u8 tuner; char *tuner_name; u8 page; /* integrated demod active register page */ + struct i2c_adapter *demod_i2c_adapter; bool rc_active; + struct i2c_client *client; }; enum rtl28xxu_chip_id { diff --git a/drivers/media/usb/dvb-usb/dvb-usb-remote.c b/drivers/media/usb/dvb-usb/dvb-usb-remote.c index 41bacff..4058aea 100644 --- a/drivers/media/usb/dvb-usb/dvb-usb-remote.c +++ b/drivers/media/usb/dvb-usb/dvb-usb-remote.c @@ -272,7 +272,7 @@ static int rc_core_dvb_usb_remote_init(struct dvb_usb_device *d) dev->driver_name = d->props.rc.core.module_name; dev->map_name = d->props.rc.core.rc_codes; dev->change_protocol = d->props.rc.core.change_protocol; - dev->allowed_protos = d->props.rc.core.allowed_protos; + rc_set_allowed_protocols(dev, d->props.rc.core.allowed_protos); dev->driver_type = d->props.rc.core.driver_type; usb_to_input_id(d->udev, &dev->input_id); dev->input_name = "IR-receiver inside an USB DVB receiver"; diff --git a/drivers/media/usb/em28xx/Kconfig b/drivers/media/usb/em28xx/Kconfig index a1fccf3..d23a912 100644 --- a/drivers/media/usb/em28xx/Kconfig +++ b/drivers/media/usb/em28xx/Kconfig @@ -53,8 +53,10 @@ config VIDEO_EM28XX_DVB select DVB_MB86A20S if MEDIA_SUBDRV_AUTOSELECT select MEDIA_TUNER_QT1010 if MEDIA_SUBDRV_AUTOSELECT select MEDIA_TUNER_TDA18271 if MEDIA_SUBDRV_AUTOSELECT + select MEDIA_TUNER_TDA18212 if MEDIA_SUBDRV_AUTOSELECT select DVB_M88DS3103 if MEDIA_SUBDRV_AUTOSELECT select MEDIA_TUNER_M88TS2022 if MEDIA_SUBDRV_AUTOSELECT + select DVB_DRX39XYJ if MEDIA_SUBDRV_AUTOSELECT ---help--- This adds support for DVB cards based on the Empiatech em28xx chips. diff --git a/drivers/media/usb/em28xx/em28xx-audio.c b/drivers/media/usb/em28xx/em28xx-audio.c index 1a28897..342490f 100644 --- a/drivers/media/usb/em28xx/em28xx-audio.c +++ b/drivers/media/usb/em28xx/em28xx-audio.c @@ -252,7 +252,7 @@ static int snd_em28xx_capture_open(struct snd_pcm_substream *substream) { struct em28xx *dev = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; - int ret = 0; + int nonblock, ret = 0; if (!dev) { em28xx_err("BUG: em28xx can't find device struct." @@ -265,45 +265,48 @@ static int snd_em28xx_capture_open(struct snd_pcm_substream *substream) dprintk("opening device and trying to acquire exclusive lock\n"); + nonblock = !!(substream->f_flags & O_NONBLOCK); + if (nonblock) { + if (!mutex_trylock(&dev->lock)) + return -EAGAIN; + } else + mutex_lock(&dev->lock); + runtime->hw = snd_em28xx_hw_capture; - if ((dev->alt == 0 || dev->is_audio_only) && dev->adev.users == 0) { - int nonblock = !!(substream->f_flags & O_NONBLOCK); - - if (nonblock) { - if (!mutex_trylock(&dev->lock)) - return -EAGAIN; - } else - mutex_lock(&dev->lock); - if (dev->is_audio_only) - /* vendor audio is on a separate interface */ - dev->alt = 1; - else - /* vendor audio is on the same interface as video */ - dev->alt = 7; - /* - * FIXME: The intention seems to be to select the alt - * setting with the largest wMaxPacketSize for the video - * endpoint. - * At least dev->alt should be used instead, but we - * should probably not touch it at all if it is - * already >0, because wMaxPacketSize of the audio - * endpoints seems to be the same for all. - */ - - dprintk("changing alternate number on interface %d to %d\n", - dev->ifnum, dev->alt); - usb_set_interface(dev->udev, dev->ifnum, dev->alt); + + if (dev->adev.users == 0) { + if (dev->alt == 0 || dev->is_audio_only) { + if (dev->is_audio_only) + /* audio is on a separate interface */ + dev->alt = 1; + else + /* audio is on the same interface as video */ + dev->alt = 7; + /* + * FIXME: The intention seems to be to select + * the alt setting with the largest + * wMaxPacketSize for the video endpoint. + * At least dev->alt should be used instead, but + * we should probably not touch it at all if it + * is already >0, because wMaxPacketSize of the + * audio endpoints seems to be the same for all. + */ + dprintk("changing alternate number on interface %d to %d\n", + dev->ifnum, dev->alt); + usb_set_interface(dev->udev, dev->ifnum, dev->alt); + } /* Sets volume, mute, etc */ dev->mute = 0; ret = em28xx_audio_analog_set(dev); if (ret < 0) goto err; - - dev->adev.users++; - mutex_unlock(&dev->lock); } + kref_get(&dev->ref); + dev->adev.users++; + mutex_unlock(&dev->lock); + /* Dynamically adjust the period size */ snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, @@ -341,6 +344,7 @@ static int snd_em28xx_pcm_close(struct snd_pcm_substream *substream) substream->runtime->dma_area = NULL; } mutex_unlock(&dev->lock); + kref_put(&dev->ref, em28xx_free_device); return 0; } @@ -895,6 +899,8 @@ static int em28xx_audio_init(struct em28xx *dev) em28xx_info("Binding audio extension\n"); + kref_get(&dev->ref); + printk(KERN_INFO "em28xx-audio.c: Copyright (C) 2006 Markus " "Rechberger\n"); printk(KERN_INFO @@ -966,7 +972,7 @@ static int em28xx_audio_fini(struct em28xx *dev) if (dev == NULL) return 0; - if (dev->has_alsa_audio != 1) { + if (!dev->has_alsa_audio) { /* This device does not support the extension (in this case the device is expecting the snd-usb-audio module or doesn't have analog audio support at all) */ @@ -985,6 +991,35 @@ static int em28xx_audio_fini(struct em28xx *dev) dev->adev.sndcard = NULL; } + kref_put(&dev->ref, em28xx_free_device); + return 0; +} + +static int em28xx_audio_suspend(struct em28xx *dev) +{ + if (dev == NULL) + return 0; + + if (!dev->has_alsa_audio) + return 0; + + em28xx_info("Suspending audio extension"); + em28xx_deinit_isoc_audio(dev); + atomic_set(&dev->stream_started, 0); + return 0; +} + +static int em28xx_audio_resume(struct em28xx *dev) +{ + if (dev == NULL) + return 0; + + if (!dev->has_alsa_audio) + return 0; + + em28xx_info("Resuming audio extension"); + /* Nothing to do other than schedule_work() ?? */ + schedule_work(&dev->wq_trigger); return 0; } @@ -993,6 +1028,8 @@ static struct em28xx_ops audio_ops = { .name = "Em28xx Audio Extension", .init = em28xx_audio_init, .fini = em28xx_audio_fini, + .suspend = em28xx_audio_suspend, + .resume = em28xx_audio_resume, }; static int __init em28xx_alsa_register(void) @@ -1007,7 +1044,7 @@ static void __exit em28xx_alsa_unregister(void) MODULE_LICENSE("GPL"); MODULE_AUTHOR("Markus Rechberger <mrechberger@gmail.com>"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_DESCRIPTION(DRIVER_DESC " - audio interface"); MODULE_VERSION(EM28XX_VERSION); diff --git a/drivers/media/usb/em28xx/em28xx-camera.c b/drivers/media/usb/em28xx/em28xx-camera.c index c29f5c4..505e050 100644 --- a/drivers/media/usb/em28xx/em28xx-camera.c +++ b/drivers/media/usb/em28xx/em28xx-camera.c @@ -120,7 +120,7 @@ static int em28xx_probe_sensor_micron(struct em28xx *dev) reg = 0x00; ret = i2c_master_send(&client, ®, 1); if (ret < 0) { - if (ret != -ENODEV) + if (ret != -ENXIO) em28xx_errdev("couldn't read from i2c device 0x%02x: error %i\n", client.addr << 1, ret); continue; @@ -218,7 +218,7 @@ static int em28xx_probe_sensor_omnivision(struct em28xx *dev) reg = 0x1c; ret = i2c_smbus_read_byte_data(&client, reg); if (ret < 0) { - if (ret != -ENODEV) + if (ret != -ENXIO) em28xx_errdev("couldn't read from i2c device 0x%02x: error %i\n", client.addr << 1, ret); continue; diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index 4d97a76..50aa5a5 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -66,7 +66,7 @@ MODULE_PARM_DESC(usb_xfer_mode, /* Bitmask marking allocated devices from 0 to EM28XX_MAXBOARDS - 1 */ -DECLARE_BITMAP(em28xx_devused, EM28XX_MAXBOARDS); +static DECLARE_BITMAP(em28xx_devused, EM28XX_MAXBOARDS); struct em28xx_hash_table { unsigned long hash; @@ -189,6 +189,14 @@ static struct em28xx_reg_seq kworld_a340_digital[] = { { -1, -1, -1, -1}, }; +static struct em28xx_reg_seq kworld_ub435q_v3_digital[] = { + {EM2874_R80_GPIO_P0_CTRL, 0xff, 0xff, 100}, + {EM2874_R80_GPIO_P0_CTRL, 0xfe, 0xff, 100}, + {EM2874_R80_GPIO_P0_CTRL, 0xbe, 0xff, 100}, + {EM2874_R80_GPIO_P0_CTRL, 0xfe, 0xff, 100}, + { -1, -1, -1, -1}, +}; + /* Pinnacle Hybrid Pro eb1a:2881 */ static struct em28xx_reg_seq pinnacle_hybrid_pro_analog[] = { {EM2820_R08_GPIO_CTRL, 0xfd, ~EM_GPIO_4, 10}, @@ -214,6 +222,17 @@ static struct em28xx_reg_seq terratec_cinergy_USB_XS_FR_digital[] = { { -1, -1, -1, -1}, }; +/* PCTV HD Mini (80e) GPIOs + 0-5: not used + 6: demod reset, active low + 7: LED on, active high */ +static struct em28xx_reg_seq em2874_pctv_80e_digital[] = { + {EM28XX_R06_I2C_CLK, 0x45, 0xff, 10}, /*400 KHz*/ + {EM2874_R80_GPIO_P0_CTRL, 0x00, 0xff, 100},/*Demod reset*/ + {EM2874_R80_GPIO_P0_CTRL, 0x40, 0xff, 10}, + { -1, -1, -1, -1}, +}; + /* eb1a:2868 Reddo DVB-C USB TV Box GPIO4 - CU1216L NIM Other GPIOs seems to be don't care. */ @@ -497,6 +516,27 @@ static struct em28xx_led speedlink_vad_laplace_leds[] = { {-1, 0, 0, 0}, }; +static struct em28xx_led kworld_ub435q_v3_leds[] = { + { + .role = EM28XX_LED_DIGITAL_CAPTURING, + .gpio_reg = EM2874_R80_GPIO_P0_CTRL, + .gpio_mask = 0x80, + .inverted = 1, + }, + {-1, 0, 0, 0}, +}; + +static struct em28xx_led pctv_80e_leds[] = { + { + .role = EM28XX_LED_DIGITAL_CAPTURING, + .gpio_reg = EM2874_R80_GPIO_P0_CTRL, + .gpio_mask = 0x80, + .inverted = 0, + }, + {-1, 0, 0, 0}, +}; + + /* * Board definitions */ @@ -2128,6 +2168,29 @@ struct em28xx_board em28xx_boards[] = { .tuner_gpio = default_tuner_gpio, .def_i2c_bus = 1, }, + /* + * 1b80:e34c KWorld USB ATSC TV Stick UB435-Q V3 + * Empia EM2874B + LG DT3305 + NXP TDA18271HDC2 + */ + [EM2874_BOARD_KWORLD_UB435Q_V3] = { + .name = "KWorld USB ATSC TV Stick UB435-Q V3", + .tuner_type = TUNER_ABSENT, + .has_dvb = 1, + .tuner_gpio = kworld_ub435q_v3_digital, + .def_i2c_bus = 1, + .i2c_speed = EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ, + .leds = kworld_ub435q_v3_leds, + }, + [EM2874_BOARD_PCTV_HD_MINI_80E] = { + .name = "Pinnacle PCTV HD Mini", + .tuner_type = TUNER_ABSENT, + .has_dvb = 1, + .dvb_gpio = em2874_pctv_80e_digital, + .decoder = EM28XX_NODECODER, + .ir_codes = RC_MAP_PINNACLE_PCTV_HD, + .leds = pctv_80e_leds, + }, /* 1ae7:9003/9004 SpeedLink Vicious And Devine Laplace webcam * Empia EM2765 + OmniVision OV2640 */ [EM2765_BOARD_SPEEDLINK_VAD_LAPLACE] = { @@ -2290,6 +2353,8 @@ struct usb_device_id em28xx_id_table[] = { .driver_info = EM2882_BOARD_PINNACLE_HYBRID_PRO_330E }, { USB_DEVICE(0x2304, 0x0227), .driver_info = EM2880_BOARD_PINNACLE_PCTV_HD_PRO }, + { USB_DEVICE(0x2304, 0x023f), + .driver_info = EM2874_BOARD_PCTV_HD_MINI_80E }, { USB_DEVICE(0x0413, 0x6023), .driver_info = EM2800_BOARD_LEADTEK_WINFAST_USBII }, { USB_DEVICE(0x093b, 0xa003), @@ -2304,6 +2369,8 @@ struct usb_device_id em28xx_id_table[] = { .driver_info = EM2870_BOARD_KWORLD_A340 }, { USB_DEVICE(0x1b80, 0xe346), .driver_info = EM2874_BOARD_KWORLD_UB435Q_V2 }, + { USB_DEVICE(0x1b80, 0xe34c), + .driver_info = EM2874_BOARD_KWORLD_UB435Q_V3 }, { USB_DEVICE(0x2013, 0x024f), .driver_info = EM28174_BOARD_PCTV_290E }, { USB_DEVICE(0x2013, 0x024c), @@ -2872,7 +2939,7 @@ static void flush_request_modules(struct em28xx *dev) * unregisters the v4l2,i2c and usb devices * called when the device gets disconnected or at module unload */ -void em28xx_release_resources(struct em28xx *dev) +static void em28xx_release_resources(struct em28xx *dev) { /*FIXME: I2C IR should be disconnected */ @@ -2889,7 +2956,27 @@ void em28xx_release_resources(struct em28xx *dev) mutex_unlock(&dev->lock); }; -EXPORT_SYMBOL_GPL(em28xx_release_resources); + +/** + * em28xx_free_device() - Free em28xx device + * + * @ref: struct kref for em28xx device + * + * This is called when all extensions and em28xx core unregisters a device + */ +void em28xx_free_device(struct kref *ref) +{ + struct em28xx *dev = kref_to_dev(ref); + + em28xx_info("Freeing device\n"); + + if (!dev->disconnected) + em28xx_release_resources(dev); + + kfree(dev->alt_max_pkt_size_isoc); + kfree(dev); +} +EXPORT_SYMBOL_GPL(em28xx_free_device); /* * em28xx_init_dev() @@ -3331,8 +3418,8 @@ static int em28xx_usb_probe(struct usb_interface *interface, if (has_video) { if (!dev->analog_ep_isoc || (try_bulk && dev->analog_ep_bulk)) dev->analog_xfer_bulk = 1; - em28xx_info("analog set to %s mode.\n", - dev->analog_xfer_bulk ? "bulk" : "isoc"); + em28xx_info("analog set to %s mode.\n", + dev->analog_xfer_bulk ? "bulk" : "isoc"); } if (has_dvb) { if (!dev->dvb_ep_isoc || (try_bulk && dev->dvb_ep_bulk)) @@ -3342,6 +3429,8 @@ static int em28xx_usb_probe(struct usb_interface *interface, dev->dvb_xfer_bulk ? "bulk" : "isoc"); } + kref_init(&dev->ref); + request_modules(dev); /* Should be the last thing to do, to avoid newer udev's to @@ -3386,17 +3475,39 @@ static void em28xx_usb_disconnect(struct usb_interface *interface) em28xx_close_extension(dev); em28xx_release_resources(dev); + kref_put(&dev->ref, em28xx_free_device); +} - if (!dev->users) { - kfree(dev->alt_max_pkt_size_isoc); - kfree(dev); - } +static int em28xx_usb_suspend(struct usb_interface *interface, + pm_message_t message) +{ + struct em28xx *dev; + + dev = usb_get_intfdata(interface); + if (!dev) + return 0; + em28xx_suspend_extension(dev); + return 0; +} + +static int em28xx_usb_resume(struct usb_interface *interface) +{ + struct em28xx *dev; + + dev = usb_get_intfdata(interface); + if (!dev) + return 0; + em28xx_resume_extension(dev); + return 0; } static struct usb_driver em28xx_usb_driver = { .name = "em28xx", .probe = em28xx_usb_probe, .disconnect = em28xx_usb_disconnect, + .suspend = em28xx_usb_suspend, + .resume = em28xx_usb_resume, + .reset_resume = em28xx_usb_resume, .id_table = em28xx_id_table, }; diff --git a/drivers/media/usb/em28xx/em28xx-core.c b/drivers/media/usb/em28xx/em28xx-core.c index 898fb9b..523d7e9 100644 --- a/drivers/media/usb/em28xx/em28xx-core.c +++ b/drivers/media/usb/em28xx/em28xx-core.c @@ -619,6 +619,7 @@ EXPORT_SYMBOL_GPL(em28xx_find_led); int em28xx_capture_start(struct em28xx *dev, int start) { int rc; + const struct em28xx_led *led = NULL; if (dev->chip_id == CHIP_ID_EM2874 || dev->chip_id == CHIP_ID_EM2884 || @@ -643,6 +644,8 @@ int em28xx_capture_start(struct em28xx *dev, int start) /* Enable video capture */ rc = em28xx_write_reg(dev, 0x48, 0x00); + if (rc < 0) + return rc; if (dev->mode == EM28XX_ANALOG_MODE) rc = em28xx_write_reg(dev, @@ -650,6 +653,8 @@ int em28xx_capture_start(struct em28xx *dev, int start) else rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37); + if (rc < 0) + return rc; msleep(6); } else { @@ -658,19 +663,16 @@ int em28xx_capture_start(struct em28xx *dev, int start) } } - if (rc < 0) - return rc; - - /* Switch (explicitly controlled) analog capturing LED on/off */ - if (dev->mode == EM28XX_ANALOG_MODE) { - const struct em28xx_led *led; + if (dev->mode == EM28XX_ANALOG_MODE) led = em28xx_find_led(dev, EM28XX_LED_ANALOG_CAPTURING); - if (led) - em28xx_write_reg_bits(dev, led->gpio_reg, - (!start ^ led->inverted) ? - ~led->gpio_mask : led->gpio_mask, - led->gpio_mask); - } + else + led = em28xx_find_led(dev, EM28XX_LED_DIGITAL_CAPTURING); + + if (led) + em28xx_write_reg_bits(dev, led->gpio_reg, + (!start ^ led->inverted) ? + ~led->gpio_mask : led->gpio_mask, + led->gpio_mask); return rc; } @@ -1106,3 +1108,31 @@ void em28xx_close_extension(struct em28xx *dev) list_del(&dev->devlist); mutex_unlock(&em28xx_devlist_mutex); } + +int em28xx_suspend_extension(struct em28xx *dev) +{ + const struct em28xx_ops *ops = NULL; + + em28xx_info("Suspending extensions"); + mutex_lock(&em28xx_devlist_mutex); + list_for_each_entry(ops, &em28xx_extension_devlist, next) { + if (ops->suspend) + ops->suspend(dev); + } + mutex_unlock(&em28xx_devlist_mutex); + return 0; +} + +int em28xx_resume_extension(struct em28xx *dev) +{ + const struct em28xx_ops *ops = NULL; + + em28xx_info("Resuming extensions"); + mutex_lock(&em28xx_devlist_mutex); + list_for_each_entry(ops, &em28xx_extension_devlist, next) { + if (ops->resume) + ops->resume(dev); + } + mutex_unlock(&em28xx_devlist_mutex); + return 0; +} diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index a0a669e..f599b18 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -41,6 +41,7 @@ #include "mt352.h" #include "mt352_priv.h" /* FIXME */ #include "tda1002x.h" +#include "drx39xyj/drx39xxj.h" #include "tda18271.h" #include "s921.h" #include "drxd.h" @@ -48,6 +49,7 @@ #include "tda18271c2dd.h" #include "drxk.h" #include "tda10071.h" +#include "tda18212.h" #include "a8293.h" #include "qt1010.h" #include "mb86a20s.h" @@ -161,6 +163,8 @@ static inline int em28xx_dvb_urb_data_copy(struct em28xx *dev, struct urb *urb) if (urb->status != -EPROTO) continue; } + if (!urb->actual_length) + continue; dvb_dmx_swfilter(&dev->dvb->demux, urb->transfer_buffer, urb->actual_length); } else { @@ -170,6 +174,8 @@ static inline int em28xx_dvb_urb_data_copy(struct em28xx *dev, struct urb *urb) if (urb->iso_frame_desc[i].status != -EPROTO) continue; } + if (!urb->iso_frame_desc[i].actual_length) + continue; dvb_dmx_swfilter(&dev->dvb->demux, urb->transfer_buffer + urb->iso_frame_desc[i].offset, @@ -208,10 +214,10 @@ static int em28xx_start_streaming(struct em28xx_dvb *dvb) if (rc < 0) return rc; - dprintk(1, "Using %d buffers each with %d x %d bytes\n", + dprintk(1, "Using %d buffers each with %d x %d bytes, alternate %d\n", EM28XX_DVB_NUM_BUFS, packet_multiplier, - dvb_max_packet_size); + dvb_max_packet_size, dvb_alt); return em28xx_init_usb_xfer(dev, EM28XX_DIGITAL_MODE, dev->dvb_xfer_bulk, @@ -315,6 +321,18 @@ static struct lgdt3305_config em2874_lgdt3305_dev = { .qam_if_khz = 4000, }; +static struct lgdt3305_config em2874_lgdt3305_nogate_dev = { + .i2c_addr = 0x0e, + .demod_chip = LGDT3305, + .spectral_inversion = 1, + .deny_i2c_rptr = 1, + .mpeg_mode = LGDT3305_MPEG_SERIAL, + .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE, + .tpvalid_polarity = LGDT3305_TP_VALID_HIGH, + .vsb_if_khz = 3600, + .qam_if_khz = 3600, +}; + static struct s921_config sharp_isdbt = { .demod_address = 0x30 >> 1 }; @@ -351,6 +369,12 @@ static struct tda18271_config kworld_ub435q_v2_config = { .gate = TDA18271_GATE_DIGITAL, }; +static struct tda18212_config kworld_ub435q_v3_config = { + .i2c_address = 0x60, + .if_atsc_vsb = 3600, + .if_atsc_qam = 3600, +}; + static struct zl10353_config em28xx_zl10353_xc3028_no_i2c_gate = { .demod_address = (0x1e >> 1), .no_tuner = 1, @@ -693,7 +717,8 @@ static void pctv_520e_init(struct em28xx *dev) static int em28xx_pctv_290e_set_lna(struct dvb_frontend *fe) { struct dtv_frontend_properties *c = &fe->dtv_property_cache; - struct em28xx *dev = fe->dvb->priv; + struct em28xx_i2c_bus *i2c_bus = fe->dvb->priv; + struct em28xx *dev = i2c_bus->dev; #ifdef CONFIG_GPIOLIB struct em28xx_dvb *dvb = dev->dvb; int ret; @@ -817,6 +842,20 @@ static const struct m88ds3103_config pctv_461e_m88ds3103_config = { .agc = 0x99, }; + +static struct tda18271_std_map drx_j_std_map = { + .atsc_6 = { .if_freq = 5000, .agc_mode = 3, .std = 0, .if_lvl = 1, + .rfagc_top = 0x37, }, + .qam_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3, .if_lvl = 1, + .rfagc_top = 0x37, }, +}; + +static struct tda18271_config pinnacle_80e_dvb_config = { + .std_map = &drx_j_std_map, + .gate = TDA18271_GATE_DIGITAL, + .role = TDA18271_MASTER, +}; + /* ------------------------------------------------------------------ */ static int em28xx_attach_xc3028(u8 addr, struct em28xx *dev) @@ -1005,7 +1044,6 @@ static int em28xx_dvb_init(struct em28xx *dev) em28xx_info("Binding DVB extension\n"); dvb = kzalloc(sizeof(struct em28xx_dvb), GFP_KERNEL); - if (dvb == NULL) { em28xx_info("em28xx_dvb: memory allocation failed\n"); return -ENOMEM; @@ -1370,10 +1408,40 @@ static int em28xx_dvb_init(struct em28xx *dev) goto out_free; } break; + case EM2874_BOARD_KWORLD_UB435Q_V3: + dvb->fe[0] = dvb_attach(lgdt3305_attach, + &em2874_lgdt3305_nogate_dev, + &dev->i2c_adap[dev->def_i2c_bus]); + if (!dvb->fe[0]) { + result = -EINVAL; + goto out_free; + } + + /* Attach the demodulator. */ + if (!dvb_attach(tda18212_attach, dvb->fe[0], + &dev->i2c_adap[dev->def_i2c_bus], + &kworld_ub435q_v3_config)) { + result = -EINVAL; + goto out_free; + } + break; + case EM2874_BOARD_PCTV_HD_MINI_80E: + dvb->fe[0] = dvb_attach(drx39xxj_attach, &dev->i2c_adap[dev->def_i2c_bus]); + if (dvb->fe[0] != NULL) { + dvb->fe[0] = dvb_attach(tda18271_attach, dvb->fe[0], 0x60, + &dev->i2c_adap[dev->def_i2c_bus], + &pinnacle_80e_dvb_config); + if (!dvb->fe[0]) { + result = -EINVAL; + goto out_free; + } + } + break; case EM28178_BOARD_PCTV_461E: { /* demod I2C adapter */ struct i2c_adapter *i2c_adapter; + struct i2c_client *client; struct i2c_board_info info; struct m88ts2022_config m88ts2022_config = { .clock = 27000000, @@ -1396,7 +1464,19 @@ static int em28xx_dvb_init(struct em28xx *dev) info.addr = 0x60; info.platform_data = &m88ts2022_config; request_module("m88ts2022"); - dvb->i2c_client_tuner = i2c_new_device(i2c_adapter, &info); + client = i2c_new_device(i2c_adapter, &info); + if (client == NULL || client->dev.driver == NULL) { + dvb_frontend_detach(dvb->fe[0]); + result = -ENODEV; + goto out_free; + } + + if (!try_module_get(client->dev.driver->owner)) { + i2c_unregister_device(client); + dvb_frontend_detach(dvb->fe[0]); + result = -ENODEV; + goto out_free; + } /* delegate signal strength measurement to tuner */ dvb->fe[0]->ops.read_signal_strength = @@ -1406,10 +1486,14 @@ static int em28xx_dvb_init(struct em28xx *dev) if (!dvb_attach(a8293_attach, dvb->fe[0], &dev->i2c_adap[dev->def_i2c_bus], &em28xx_a8293_config)) { + module_put(client->dev.driver->owner); + i2c_unregister_device(client); dvb_frontend_detach(dvb->fe[0]); result = -ENODEV; goto out_free; } + + dvb->i2c_client_tuner = client; } break; default: @@ -1437,6 +1521,9 @@ static int em28xx_dvb_init(struct em28xx *dev) dvb->adapter.mfe_shared = mfe_shared; em28xx_info("DVB extension successfully initialized\n"); + + kref_get(&dev->ref); + ret: em28xx_set_mode(dev, EM28XX_SUSPEND); mutex_unlock(&dev->lock); @@ -1457,6 +1544,9 @@ static inline void prevent_sleep(struct dvb_frontend_ops *ops) static int em28xx_dvb_fini(struct em28xx *dev) { + struct em28xx_dvb *dvb; + struct i2c_client *client; + if (dev->is_audio_only) { /* Shouldn't initialize IR for this interface */ return 0; @@ -1467,23 +1557,96 @@ static int em28xx_dvb_fini(struct em28xx *dev) return 0; } + if (!dev->dvb) + return 0; + em28xx_info("Closing DVB extension"); + dvb = dev->dvb; + client = dvb->i2c_client_tuner; + + em28xx_uninit_usb_xfer(dev, EM28XX_DIGITAL_MODE); + + if (dev->disconnected) { + /* We cannot tell the device to sleep + * once it has been unplugged. */ + if (dvb->fe[0]) + prevent_sleep(&dvb->fe[0]->ops); + if (dvb->fe[1]) + prevent_sleep(&dvb->fe[1]->ops); + } + + /* remove I2C tuner */ + if (client) { + module_put(client->dev.driver->owner); + i2c_unregister_device(client); + } + + em28xx_unregister_dvb(dvb); + kfree(dvb); + dev->dvb = NULL; + kref_put(&dev->ref, em28xx_free_device); + + return 0; +} + +static int em28xx_dvb_suspend(struct em28xx *dev) +{ + int ret = 0; + + if (dev->is_audio_only) + return 0; + + if (!dev->board.has_dvb) + return 0; + + em28xx_info("Suspending DVB extension"); if (dev->dvb) { struct em28xx_dvb *dvb = dev->dvb; - em28xx_uninit_usb_xfer(dev, EM28XX_DIGITAL_MODE); + if (dvb->fe[0]) { + ret = dvb_frontend_suspend(dvb->fe[0]); + em28xx_info("fe0 suspend %d", ret); + } + if (dvb->fe[1]) { + dvb_frontend_suspend(dvb->fe[1]); + em28xx_info("fe1 suspend %d", ret); + } + } + + return 0; +} + +static int em28xx_dvb_resume(struct em28xx *dev) +{ + int ret = 0; - if (dev->disconnected) { - /* We cannot tell the device to sleep - * once it has been unplugged. */ - if (dvb->fe[0]) - prevent_sleep(&dvb->fe[0]->ops); - if (dvb->fe[1]) - prevent_sleep(&dvb->fe[1]->ops); + if (dev->is_audio_only) + return 0; + + if (!dev->board.has_dvb) + return 0; + + em28xx_info("Resuming DVB extension"); + if (dev->dvb) { + struct em28xx_dvb *dvb = dev->dvb; + struct i2c_client *client = dvb->i2c_client_tuner; + + if (dvb->fe[0]) { + ret = dvb_frontend_resume(dvb->fe[0]); + em28xx_info("fe0 resume %d", ret); + } + + if (dvb->fe[1]) { + ret = dvb_frontend_resume(dvb->fe[1]); + em28xx_info("fe1 resume %d", ret); + } + /* remove I2C tuner */ + if (client) { + module_put(client->dev.driver->owner); + i2c_unregister_device(client); } - i2c_release_client(dvb->i2c_client_tuner); em28xx_unregister_dvb(dvb); kfree(dvb); dev->dvb = NULL; @@ -1497,6 +1660,8 @@ static struct em28xx_ops dvb_ops = { .name = "Em28xx dvb Extension", .init = em28xx_dvb_init, .fini = em28xx_dvb_fini, + .suspend = em28xx_dvb_suspend, + .resume = em28xx_dvb_resume, }; static int __init em28xx_dvb_register(void) diff --git a/drivers/media/usb/em28xx/em28xx-i2c.c b/drivers/media/usb/em28xx/em28xx-i2c.c index 7e17240..ba6433c 100644 --- a/drivers/media/usb/em28xx/em28xx-i2c.c +++ b/drivers/media/usb/em28xx/em28xx-i2c.c @@ -81,7 +81,7 @@ static int em2800_i2c_send_bytes(struct em28xx *dev, u8 addr, u8 *buf, u16 len) return len; if (ret == 0x94 + len - 1) { if (i2c_debug == 1) - em28xx_warn("R05 returned 0x%02x: I2C timeout", + em28xx_warn("R05 returned 0x%02x: I2C ACK error\n", ret); return -ENXIO; } @@ -128,7 +128,7 @@ static int em2800_i2c_recv_bytes(struct em28xx *dev, u8 addr, u8 *buf, u16 len) break; if (ret == 0x94 + len - 1) { if (i2c_debug == 1) - em28xx_warn("R05 returned 0x%02x: I2C timeout", + em28xx_warn("R05 returned 0x%02x: I2C ACK error\n", ret); return -ENXIO; } @@ -210,7 +210,7 @@ static int em28xx_i2c_send_bytes(struct em28xx *dev, u16 addr, u8 *buf, return len; if (ret == 0x10) { if (i2c_debug == 1) - em28xx_warn("I2C transfer timeout on writing to addr 0x%02x", + em28xx_warn("I2C ACK error on writing to addr 0x%02x\n", addr); return -ENXIO; } @@ -226,10 +226,18 @@ static int em28xx_i2c_send_bytes(struct em28xx *dev, u16 addr, u8 *buf, * (even with high payload) ... */ } - if (i2c_debug) - em28xx_warn("write to i2c device at 0x%x timed out (status=%i)\n", - addr, ret); - return -ETIMEDOUT; + + if (ret == 0x02 || ret == 0x04) { + /* NOTE: these errors seem to be related to clock stretching */ + if (i2c_debug) + em28xx_warn("write to i2c device at 0x%x timed out (status=%i)\n", + addr, ret); + return -ETIMEDOUT; + } + + em28xx_warn("write to i2c device at 0x%x failed with unknown error (status=%i)\n", + addr, ret); + return -EIO; } /* @@ -274,13 +282,22 @@ static int em28xx_i2c_recv_bytes(struct em28xx *dev, u16 addr, u8 *buf, u16 len) } if (ret == 0x10) { if (i2c_debug == 1) - em28xx_warn("I2C transfer timeout on writing to addr 0x%02x", + em28xx_warn("I2C ACK error on writing to addr 0x%02x\n", addr); return -ENXIO; } - em28xx_warn("unknown i2c error (status=%i)\n", ret); - return -ETIMEDOUT; + if (ret == 0x02 || ret == 0x04) { + /* NOTE: these errors seem to be related to clock stretching */ + if (i2c_debug) + em28xx_warn("write to i2c device at 0x%x timed out (status=%i)\n", + addr, ret); + return -ETIMEDOUT; + } + + em28xx_warn("write to i2c device at 0x%x failed with unknown error (status=%i)\n", + addr, ret); + return -EIO; } /* @@ -337,7 +354,7 @@ static int em25xx_bus_B_send_bytes(struct em28xx *dev, u16 addr, u8 *buf, return len; else if (ret > 0) { if (i2c_debug == 1) - em28xx_warn("Bus B R08 returned 0x%02x: I2C timeout", + em28xx_warn("Bus B R08 returned 0x%02x: I2C ACK error\n", ret); return -ENXIO; } @@ -392,7 +409,7 @@ static int em25xx_bus_B_recv_bytes(struct em28xx *dev, u16 addr, u8 *buf, return len; else if (ret > 0) { if (i2c_debug == 1) - em28xx_warn("Bus B R08 returned 0x%02x: I2C timeout", + em28xx_warn("Bus B R08 returned 0x%02x: I2C ACK error\n", ret); return -ENXIO; } diff --git a/drivers/media/usb/em28xx/em28xx-input.c b/drivers/media/usb/em28xx/em28xx-input.c index 18f65d8..56ef49d 100644 --- a/drivers/media/usb/em28xx/em28xx-input.c +++ b/drivers/media/usb/em28xx/em28xx-input.c @@ -676,6 +676,8 @@ static int em28xx_ir_init(struct em28xx *dev) return 0; } + kref_get(&dev->ref); + if (dev->board.buttons) em28xx_init_buttons(dev); @@ -725,7 +727,7 @@ static int em28xx_ir_init(struct em28xx *dev) case EM2820_BOARD_HAUPPAUGE_WINTV_USB_2: rc->map_name = RC_MAP_HAUPPAUGE; ir->get_key_i2c = em28xx_get_key_em_haup; - rc->allowed_protos = RC_BIT_RC5; + rc_set_allowed_protocols(rc, RC_BIT_RC5); break; case EM2820_BOARD_LEADTEK_WINFAST_USBII_DELUXE: rc->map_name = RC_MAP_WINFAST_USBII_DELUXE; @@ -741,7 +743,7 @@ static int em28xx_ir_init(struct em28xx *dev) switch (dev->chip_id) { case CHIP_ID_EM2860: case CHIP_ID_EM2883: - rc->allowed_protos = RC_BIT_RC5 | RC_BIT_NEC; + rc_set_allowed_protocols(rc, RC_BIT_RC5 | RC_BIT_NEC); ir->get_key = default_polling_getkey; break; case CHIP_ID_EM2884: @@ -749,8 +751,8 @@ static int em28xx_ir_init(struct em28xx *dev) case CHIP_ID_EM28174: case CHIP_ID_EM28178: ir->get_key = em2874_polling_getkey; - rc->allowed_protos = RC_BIT_RC5 | RC_BIT_NEC | - RC_BIT_RC6_0; + rc_set_allowed_protocols(rc, RC_BIT_RC5 | RC_BIT_NEC | + RC_BIT_RC6_0); break; default: err = -ENODEV; @@ -816,7 +818,7 @@ static int em28xx_ir_fini(struct em28xx *dev) /* skip detach on non attached boards */ if (!ir) - return 0; + goto ref_put; if (ir->rc) rc_unregister_device(ir->rc); @@ -824,6 +826,45 @@ static int em28xx_ir_fini(struct em28xx *dev) /* done */ kfree(ir); dev->ir = NULL; + +ref_put: + kref_put(&dev->ref, em28xx_free_device); + + return 0; +} + +static int em28xx_ir_suspend(struct em28xx *dev) +{ + struct em28xx_IR *ir = dev->ir; + + if (dev->is_audio_only) + return 0; + + em28xx_info("Suspending input extension"); + if (ir) + cancel_delayed_work_sync(&ir->work); + cancel_delayed_work_sync(&dev->buttons_query_work); + /* is canceling delayed work sufficient or does the rc event + kthread needs stopping? kthread is stopped in + ir_raw_event_unregister() */ + return 0; +} + +static int em28xx_ir_resume(struct em28xx *dev) +{ + struct em28xx_IR *ir = dev->ir; + + if (dev->is_audio_only) + return 0; + + em28xx_info("Resuming input extension"); + /* if suspend calls ir_raw_event_unregister(), the should call + ir_raw_event_register() */ + if (ir) + schedule_delayed_work(&ir->work, msecs_to_jiffies(ir->polling)); + if (dev->num_button_polling_addresses) + schedule_delayed_work(&dev->buttons_query_work, + msecs_to_jiffies(dev->button_polling_interval)); return 0; } @@ -832,6 +873,8 @@ static struct em28xx_ops rc_ops = { .name = "Em28xx Input Extension", .init = em28xx_ir_init, .fini = em28xx_ir_fini, + .suspend = em28xx_ir_suspend, + .resume = em28xx_ir_resume, }; static int __init em28xx_rc_register(void) @@ -845,7 +888,7 @@ static void __exit em28xx_rc_unregister(void) } MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_DESCRIPTION(DRIVER_DESC " - input interface"); MODULE_VERSION(EM28XX_VERSION); diff --git a/drivers/media/usb/em28xx/em28xx-video.c b/drivers/media/usb/em28xx/em28xx-video.c index c3c9289..0856e5d 100644 --- a/drivers/media/usb/em28xx/em28xx-video.c +++ b/drivers/media/usb/em28xx/em28xx-video.c @@ -1029,7 +1029,7 @@ static int em28xx_vb2_setup(struct em28xx *dev) q = &dev->vb_vidq; q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; q->io_modes = VB2_READ | VB2_MMAP | VB2_USERPTR | VB2_DMABUF; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; q->drv_priv = dev; q->buf_struct_size = sizeof(struct em28xx_buffer); q->ops = &em28xx_video_qops; @@ -1043,7 +1043,7 @@ static int em28xx_vb2_setup(struct em28xx *dev) q = &dev->vb_vbiq; q->type = V4L2_BUF_TYPE_VBI_CAPTURE; q->io_modes = VB2_READ | VB2_MMAP | VB2_USERPTR; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; q->drv_priv = dev; q->buf_struct_size = sizeof(struct em28xx_buffer); q->ops = &em28xx_vbi_qops; @@ -1837,7 +1837,6 @@ static int em28xx_v4l2_open(struct file *filp) video_device_node_name(vdev), v4l2_type_names[fh_type], dev->users); - if (mutex_lock_interruptible(&dev->lock)) return -ERESTARTSYS; fh = kzalloc(sizeof(struct em28xx_fh), GFP_KERNEL); @@ -1869,6 +1868,7 @@ static int em28xx_v4l2_open(struct file *filp) v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_radio); } + kref_get(&dev->ref); dev->users++; mutex_unlock(&dev->lock); @@ -1918,18 +1918,43 @@ static int em28xx_v4l2_fini(struct em28xx *dev) video_unregister_device(dev->vdev); } + v4l2_ctrl_handler_free(&dev->ctrl_handler); + v4l2_device_unregister(&dev->v4l2_dev); + if (dev->clk) { v4l2_clk_unregister_fixed(dev->clk); dev->clk = NULL; } - v4l2_ctrl_handler_free(&dev->ctrl_handler); - v4l2_device_unregister(&dev->v4l2_dev); - - if (dev->users) - em28xx_warn("Device is open ! Memory deallocation is deferred on last close.\n"); mutex_unlock(&dev->lock); + kref_put(&dev->ref, em28xx_free_device); + + return 0; +} + +static int em28xx_v4l2_suspend(struct em28xx *dev) +{ + if (dev->is_audio_only) + return 0; + if (!dev->has_video) + return 0; + + em28xx_info("Suspending video extension"); + em28xx_stop_urbs(dev); + return 0; +} + +static int em28xx_v4l2_resume(struct em28xx *dev) +{ + if (dev->is_audio_only) + return 0; + + if (!dev->has_video) + return 0; + + em28xx_info("Resuming video extension"); + /* what do we do here */ return 0; } @@ -1950,11 +1975,9 @@ static int em28xx_v4l2_close(struct file *filp) mutex_lock(&dev->lock); if (dev->users == 1) { - /* free the remaining resources if device is disconnected */ - if (dev->disconnected) { - kfree(dev->alt_max_pkt_size_isoc); + /* No sense to try to write to the device */ + if (dev->disconnected) goto exit; - } /* Save some power by putting tuner to sleep */ v4l2_device_call_all(&dev->v4l2_dev, 0, core, s_power, 0); @@ -1975,6 +1998,8 @@ static int em28xx_v4l2_close(struct file *filp) exit: dev->users--; mutex_unlock(&dev->lock); + kref_put(&dev->ref, em28xx_free_device); + return 0; } @@ -2273,7 +2298,8 @@ static int em28xx_v4l2_init(struct em28xx *dev) } em28xx_tuner_setup(dev); - em28xx_init_camera(dev); + if (dev->em28xx_sensor != EM28XX_NOSENSOR) + em28xx_init_camera(dev); /* Configure audio */ ret = em28xx_audio_setup(dev); @@ -2488,6 +2514,8 @@ static int em28xx_v4l2_init(struct em28xx *dev) em28xx_info("V4L2 extension successfully initialized\n"); + kref_get(&dev->ref); + mutex_unlock(&dev->lock); return 0; @@ -2504,6 +2532,8 @@ static struct em28xx_ops v4l2_ops = { .name = "Em28xx v4l2 Extension", .init = em28xx_v4l2_init, .fini = em28xx_v4l2_fini, + .suspend = em28xx_v4l2_suspend, + .resume = em28xx_v4l2_resume, }; static int __init em28xx_video_register(void) diff --git a/drivers/media/usb/em28xx/em28xx.h b/drivers/media/usb/em28xx/em28xx.h index 32d8a4b..2051fc9 100644 --- a/drivers/media/usb/em28xx/em28xx.h +++ b/drivers/media/usb/em28xx/em28xx.h @@ -32,6 +32,7 @@ #include <linux/workqueue.h> #include <linux/i2c.h> #include <linux/mutex.h> +#include <linux/kref.h> #include <linux/videodev2.h> #include <media/videobuf2-vmalloc.h> @@ -104,6 +105,7 @@ #define EM2882_BOARD_PINNACLE_HYBRID_PRO_330E 56 #define EM2883_BOARD_KWORLD_HYBRID_330U 57 #define EM2820_BOARD_COMPRO_VIDEOMATE_FORYOU 58 +#define EM2874_BOARD_PCTV_HD_MINI_80E 59 #define EM2883_BOARD_HAUPPAUGE_WINTV_HVR_850 60 #define EM2820_BOARD_PROLINK_PLAYTV_BOX4_USB2 61 #define EM2820_BOARD_GADMEI_TVR200 62 @@ -137,6 +139,7 @@ #define EM2874_BOARD_KWORLD_UB435Q_V2 90 #define EM2765_BOARD_SPEEDLINK_VAD_LAPLACE 91 #define EM28178_BOARD_PCTV_461E 92 +#define EM2874_BOARD_KWORLD_UB435Q_V3 93 /* Limits minimum and default number of buffers */ #define EM28XX_MIN_BUF 4 @@ -399,6 +402,7 @@ enum em28xx_adecoder { enum em28xx_led_role { EM28XX_LED_ANALOG_CAPTURING = 0, + EM28XX_LED_DIGITAL_CAPTURING, EM28XX_LED_ILLUMINATION, EM28XX_NUM_LED_ROLES, /* must be the last */ }; @@ -533,9 +537,10 @@ struct em28xx_i2c_bus { enum em28xx_i2c_algo_type algo_type; }; - /* main device struct */ struct em28xx { + struct kref ref; + /* generic device properties */ char name[30]; /* name (including minor) of the device */ int model; /* index in the device_data struct */ @@ -707,12 +712,16 @@ struct em28xx { struct em28xx_dvb *dvb; }; +#define kref_to_dev(d) container_of(d, struct em28xx, ref) + struct em28xx_ops { struct list_head next; char *name; int id; int (*init)(struct em28xx *); int (*fini)(struct em28xx *); + int (*suspend)(struct em28xx *); + int (*resume)(struct em28xx *); }; /* Provided by em28xx-i2c.c */ @@ -758,13 +767,15 @@ int em28xx_register_extension(struct em28xx_ops *dev); void em28xx_unregister_extension(struct em28xx_ops *dev); void em28xx_init_extension(struct em28xx *dev); void em28xx_close_extension(struct em28xx *dev); +int em28xx_suspend_extension(struct em28xx *dev); +int em28xx_resume_extension(struct em28xx *dev); /* Provided by em28xx-cards.c */ extern struct em28xx_board em28xx_boards[]; extern struct usb_device_id em28xx_id_table[]; int em28xx_tuner_callback(void *ptr, int component, int command, int arg); void em28xx_setup_xc3028(struct em28xx *dev, struct xc2028_ctrl *ctl); -void em28xx_release_resources(struct em28xx *dev); +void em28xx_free_device(struct kref *ref); /* Provided by em28xx-camera.c */ int em28xx_detect_sensor(struct em28xx *dev); diff --git a/drivers/media/usb/gspca/kinect.c b/drivers/media/usb/gspca/kinect.c index 3773a8a..081f051 100644 --- a/drivers/media/usb/gspca/kinect.c +++ b/drivers/media/usb/gspca/kinect.c @@ -155,10 +155,11 @@ static int send_cmd(struct gspca_dev *gspca_dev, uint16_t cmd, void *cmdbuf, do { actual_len = kinect_read(udev, ibuf, 0x200); } while (actual_len == 0); - PDEBUG(D_USBO, "Control reply: %d", res); + PDEBUG(D_USBO, "Control reply: %d", actual_len); if (actual_len < sizeof(*rhdr)) { - pr_err("send_cmd: Input control transfer failed (%d)\n", res); - return res; + pr_err("send_cmd: Input control transfer failed (%d)\n", + actual_len); + return actual_len < 0 ? actual_len : -EREMOTEIO; } actual_len -= sizeof(*rhdr); diff --git a/drivers/media/usb/gspca/sn9c20x.c b/drivers/media/usb/gspca/sn9c20x.c index 2a38621..41a9a89 100644 --- a/drivers/media/usb/gspca/sn9c20x.c +++ b/drivers/media/usb/gspca/sn9c20x.c @@ -2359,6 +2359,7 @@ static const struct usb_device_id device_table[] = { {USB_DEVICE(0x045e, 0x00f4), SN9C20X(OV9650, 0x30, 0)}, {USB_DEVICE(0x145f, 0x013d), SN9C20X(OV7660, 0x21, 0)}, {USB_DEVICE(0x0458, 0x7029), SN9C20X(HV7131R, 0x11, 0)}, + {USB_DEVICE(0x0458, 0x7045), SN9C20X(MT9M112, 0x5d, LED_REVERSE)}, {USB_DEVICE(0x0458, 0x704a), SN9C20X(MT9M112, 0x5d, 0)}, {USB_DEVICE(0x0458, 0x704c), SN9C20X(MT9M112, 0x5d, 0)}, {USB_DEVICE(0xa168, 0x0610), SN9C20X(HV7131R, 0x11, 0)}, diff --git a/drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c b/drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c index bf3e5c3..e60cbb3 100644 --- a/drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c +++ b/drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.c @@ -178,7 +178,7 @@ static int vv6410_stop(struct sd *sd) PDEBUG(D_STREAM, "Halting stream"); - return (err < 0) ? err : 0; + return 0; } static int vv6410_dump(struct sd *sd) diff --git a/drivers/media/usb/gspca/topro.c b/drivers/media/usb/gspca/topro.c index 640c2fe..5fcd1ee 100644 --- a/drivers/media/usb/gspca/topro.c +++ b/drivers/media/usb/gspca/topro.c @@ -4631,8 +4631,16 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, } data++; len--; + if (len < 2) { + gspca_dev->last_packet_type = DISCARD_PACKET; + return; + } if (*data == 0xff && data[1] == 0xd8) { /*fixme: there may be information in the 4 high bits*/ + if (len < 7) { + gspca_dev->last_packet_type = DISCARD_PACKET; + return; + } if ((data[6] & 0x0f) != sd->quality) set_dqt(gspca_dev, data[6] & 0x0f); gspca_frame_add(gspca_dev, FIRST_PACKET, @@ -4672,7 +4680,7 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, gspca_dev->last_packet_type = DISCARD_PACKET; break; case 0xcc: - if (data[1] != 0xff || data[2] != 0xd8) + if (len >= 3 && (data[1] != 0xff || data[2] != 0xd8)) gspca_frame_add(gspca_dev, INTER_PACKET, data + 1, len - 1); else diff --git a/drivers/media/usb/pwc/pwc-if.c b/drivers/media/usb/pwc/pwc-if.c index abf365a..84a6720 100644 --- a/drivers/media/usb/pwc/pwc-if.c +++ b/drivers/media/usb/pwc/pwc-if.c @@ -614,17 +614,20 @@ static int buffer_prepare(struct vb2_buffer *vb) return 0; } -static int buffer_finish(struct vb2_buffer *vb) +static void buffer_finish(struct vb2_buffer *vb) { struct pwc_device *pdev = vb2_get_drv_priv(vb->vb2_queue); struct pwc_frame_buf *buf = container_of(vb, struct pwc_frame_buf, vb); - /* - * Application has called dqbuf and is getting back a buffer we've - * filled, take the pwc data we've stored in buf->data and decompress - * it into a usable format, storing the result in the vb2_buffer - */ - return pwc_decompress(pdev, buf); + if (vb->state == VB2_BUF_STATE_DONE) { + /* + * Application has called dqbuf and is getting back a buffer + * we've filled, take the pwc data we've stored in buf->data + * and decompress it into a usable format, storing the result + * in the vb2_buffer. + */ + pwc_decompress(pdev, buf); + } } static void buffer_cleanup(struct vb2_buffer *vb) @@ -1001,7 +1004,7 @@ static int usb_pwc_probe(struct usb_interface *intf, const struct usb_device_id pdev->vb_queue.buf_struct_size = sizeof(struct pwc_frame_buf); pdev->vb_queue.ops = &pwc_vb_queue_ops; pdev->vb_queue.mem_ops = &vb2_vmalloc_memops; - pdev->vb_queue.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + pdev->vb_queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; rc = vb2_queue_init(&pdev->vb_queue); if (rc < 0) { PWC_ERROR("Oops, could not initialize vb2 queue.\n"); diff --git a/drivers/media/usb/s2255/Kconfig b/drivers/media/usb/s2255/Kconfig index 7e8ee1f..8c3fcee 100644 --- a/drivers/media/usb/s2255/Kconfig +++ b/drivers/media/usb/s2255/Kconfig @@ -1,7 +1,7 @@ config USB_S2255 tristate "USB Sensoray 2255 video capture device" depends on VIDEO_V4L2 - select VIDEOBUF_VMALLOC + select VIDEOBUF2_VMALLOC default n help Say Y here if you want support for the Sensoray 2255 USB device. diff --git a/drivers/media/usb/s2255/s2255drv.c b/drivers/media/usb/s2255/s2255drv.c index 6bc9b8e..1d4ba2b 100644 --- a/drivers/media/usb/s2255/s2255drv.c +++ b/drivers/media/usb/s2255/s2255drv.c @@ -1,7 +1,7 @@ /* * s2255drv.c - a driver for the Sensoray 2255 USB video capture device * - * Copyright (C) 2007-2013 by Sensoray Company Inc. + * Copyright (C) 2007-2014 by Sensoray Company Inc. * Dean Anderson * * Some video buffer code based on vivi driver: @@ -45,14 +45,14 @@ #include <linux/mm.h> #include <linux/vmalloc.h> #include <linux/usb.h> -#include <media/videobuf-vmalloc.h> +#include <media/videobuf2-vmalloc.h> #include <media/v4l2-common.h> #include <media/v4l2-device.h> #include <media/v4l2-ioctl.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-event.h> -#define S2255_VERSION "1.23.1" +#define S2255_VERSION "1.25.1" #define FIRMWARE_FILE_NAME "f2255usb.bin" /* default JPEG quality */ @@ -69,7 +69,7 @@ #define S2255_DSP_BOOTTIME 800 /* maximum time to wait for firmware to load (ms) */ #define S2255_LOAD_TIMEOUT (5000 + S2255_DSP_BOOTTIME) -#define S2255_DEF_BUFS 16 +#define S2255_MIN_BUFS 2 #define S2255_SETMODE_TIMEOUT 500 #define S2255_VIDSTATUS_TIMEOUT 350 #define S2255_MARKER_FRAME cpu_to_le32(0x2255DA4AL) @@ -178,11 +178,6 @@ struct s2255_bufferi { DEF_FDEC, DEF_BRIGHT, DEF_CONTRAST, DEF_SATURATION, \ DEF_HUE, 0, DEF_USB_BLOCK, 0} -struct s2255_dmaqueue { - struct list_head active; - struct s2255_dev *dev; -}; - /* for firmware loading, fw_state */ #define S2255_FW_NOTLOADED 0 #define S2255_FW_LOADED_DSPWAIT 1 @@ -217,12 +212,14 @@ struct s2255_pipeinfo { struct s2255_fmt; /*forward declaration */ struct s2255_dev; -struct s2255_channel { +/* 2255 video channel */ +struct s2255_vc { + struct s2255_dev *dev; struct video_device vdev; struct v4l2_ctrl_handler hdl; struct v4l2_ctrl *jpegqual_ctrl; int resources; - struct s2255_dmaqueue vidq; + struct list_head buf_list; struct s2255_bufferi buffer; struct s2255_mode mode; v4l2_std_id std; @@ -232,8 +229,6 @@ struct s2255_channel { struct v4l2_captureparm cap_parm; int cur_frame; int last_frame; - - int b_acquire; /* allocated image size */ unsigned long req_image_size; /* received packet size */ @@ -252,17 +247,22 @@ struct s2255_channel { int vidstatus_ready; unsigned int width; unsigned int height; + enum v4l2_field field; const struct s2255_fmt *fmt; int idx; /* channel number on device, 0-3 */ + struct vb2_queue vb_vidq; + struct mutex vb_lock; /* streaming lock */ + spinlock_t qlock; }; struct s2255_dev { - struct s2255_channel channel[MAX_CHANNELS]; - struct v4l2_device v4l2_dev; + struct s2255_vc vc[MAX_CHANNELS]; + struct v4l2_device v4l2_dev; atomic_t num_channels; int frames; struct mutex lock; /* channels[].vdev.lock */ + struct mutex cmdlock; /* protects cmdbuf */ struct usb_device *udev; struct usb_interface *interface; u8 read_endpoint; @@ -272,10 +272,11 @@ struct s2255_dev { u32 cc; /* current channel */ int frame_ready; int chn_ready; - spinlock_t slock; /* dsp firmware version (f2255usb.bin) */ int dsp_fw_ver; u16 pid; /* product id */ +#define S2255_CMDBUF_SIZE 512 + __le32 *cmdbuf; }; static inline struct s2255_dev *to_s2255_dev(struct v4l2_device *v4l2_dev) @@ -292,19 +293,10 @@ struct s2255_fmt { /* buffer for one video frame */ struct s2255_buffer { /* common v4l buffer stuff -- must be first */ - struct videobuf_buffer vb; - const struct s2255_fmt *fmt; + struct vb2_buffer vb; + struct list_head list; }; -struct s2255_fh { - /* this must be the first field in this struct */ - struct v4l2_fh fh; - struct s2255_dev *dev; - struct videobuf_queue vb_vidq; - enum v4l2_buf_type type; - struct s2255_channel *channel; - int resources; -}; /* current cypress EEPROM firmware version */ #define S2255_CUR_USB_FWVER ((3 << 8) | 12) @@ -352,15 +344,14 @@ struct s2255_fh { static unsigned long G_chnmap[MAX_CHANNELS] = {3, 2, 1, 0}; static int debug; -static int *s2255_debug = &debug; static int s2255_start_readpipe(struct s2255_dev *dev); static void s2255_stop_readpipe(struct s2255_dev *dev); -static int s2255_start_acquire(struct s2255_channel *channel); -static int s2255_stop_acquire(struct s2255_channel *channel); -static void s2255_fillbuff(struct s2255_channel *chn, struct s2255_buffer *buf, +static int s2255_start_acquire(struct s2255_vc *vc); +static int s2255_stop_acquire(struct s2255_vc *vc); +static void s2255_fillbuff(struct s2255_vc *vc, struct s2255_buffer *buf, int jpgsize); -static int s2255_set_mode(struct s2255_channel *chan, struct s2255_mode *mode); +static int s2255_set_mode(struct s2255_vc *vc, struct s2255_mode *mode); static int s2255_board_shutdown(struct s2255_dev *dev); static void s2255_fwload_start(struct s2255_dev *dev, int reset); static void s2255_destroy(struct s2255_dev *dev); @@ -373,19 +364,11 @@ static long s2255_vendor_req(struct s2255_dev *dev, unsigned char req, #define s2255_dev_err(dev, fmt, arg...) \ dev_err(dev, S2255_DRIVER_NAME " - " fmt, ##arg) -#define dprintk(level, fmt, arg...) \ - do { \ - if (*s2255_debug >= (level)) { \ - printk(KERN_DEBUG S2255_DRIVER_NAME \ - ": " fmt, ##arg); \ - } \ - } while (0) +#define dprintk(dev, level, fmt, arg...) \ + v4l2_dbg(level, debug, &dev->v4l2_dev, fmt, ## arg) static struct usb_driver s2255_driver; -/* Declare static vars that will be used as parameters */ -static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ - /* start video number */ static int video_nr = -1; /* /dev/videoN, -1 for autodetect */ @@ -394,8 +377,6 @@ static int jpeg_enable = 1; module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Debug level(0-100) default 0"); -module_param(vid_limit, int, 0644); -MODULE_PARM_DESC(vid_limit, "video memory limit(Mb)"); module_param(video_nr, int, 0644); MODULE_PARM_DESC(video_nr, "start video minor(-1 default autodetect)"); module_param(jpeg_enable, int, 0644); @@ -444,27 +425,27 @@ static const struct s2255_fmt formats[] = { } }; -static int norm_maxw(struct s2255_channel *channel) +static int norm_maxw(struct s2255_vc *vc) { - return (channel->std & V4L2_STD_525_60) ? + return (vc->std & V4L2_STD_525_60) ? LINE_SZ_4CIFS_NTSC : LINE_SZ_4CIFS_PAL; } -static int norm_maxh(struct s2255_channel *channel) +static int norm_maxh(struct s2255_vc *vc) { - return (channel->std & V4L2_STD_525_60) ? + return (vc->std & V4L2_STD_525_60) ? (NUM_LINES_1CIFS_NTSC * 2) : (NUM_LINES_1CIFS_PAL * 2); } -static int norm_minw(struct s2255_channel *channel) +static int norm_minw(struct s2255_vc *vc) { - return (channel->std & V4L2_STD_525_60) ? + return (vc->std & V4L2_STD_525_60) ? LINE_SZ_1CIFS_NTSC : LINE_SZ_1CIFS_PAL; } -static int norm_minh(struct s2255_channel *channel) +static int norm_minh(struct s2255_vc *vc) { - return (channel->std & V4L2_STD_525_60) ? + return (vc->std & V4L2_STD_525_60) ? (NUM_LINES_1CIFS_NTSC) : (NUM_LINES_1CIFS_PAL); } @@ -498,7 +479,7 @@ static void planar422p_to_yuv_packed(const unsigned char *in, static void s2255_reset_dsppower(struct s2255_dev *dev) { s2255_vendor_req(dev, 0x40, 0x0000, 0x0001, NULL, 0, 1); - msleep(10); + msleep(20); s2255_vendor_req(dev, 0x50, 0x0000, 0x0000, NULL, 0, 1); msleep(600); s2255_vendor_req(dev, 0x10, 0x0000, 0x0000, NULL, 0, 1); @@ -510,9 +491,8 @@ static void s2255_reset_dsppower(struct s2255_dev *dev) static void s2255_timer(unsigned long user_data) { struct s2255_fw *data = (struct s2255_fw *)user_data; - dprintk(100, "%s\n", __func__); if (usb_submit_urb(data->fw_urb, GFP_ATOMIC) < 0) { - printk(KERN_ERR "s2255: can't submit urb\n"); + pr_err("s2255: can't submit urb\n"); atomic_set(&data->fw_state, S2255_FW_FAILED); /* wake up anything waiting for the firmware */ wake_up(&data->wait_fw); @@ -532,7 +512,6 @@ static void s2255_fwchunk_complete(struct urb *urb) struct s2255_fw *data = urb->context; struct usb_device *udev = urb->dev; int len; - dprintk(100, "%s: udev %p urb %p", __func__, udev, urb); if (urb->status) { dev_err(&udev->dev, "URB failed with status %d\n", urb->status); atomic_set(&data->fw_state, S2255_FW_FAILED); @@ -559,9 +538,6 @@ static void s2255_fwchunk_complete(struct urb *urb) if (len < CHUNK_SIZE) memset(data->pfw_data, 0, CHUNK_SIZE); - dprintk(100, "completed len %d, loaded %d \n", len, - data->fw_loaded); - memcpy(data->pfw_data, (char *) data->fw->data + data->fw_loaded, len); @@ -576,36 +552,32 @@ static void s2255_fwchunk_complete(struct urb *urb) return; } data->fw_loaded += len; - } else { + } else atomic_set(&data->fw_state, S2255_FW_LOADED_DSPWAIT); - dprintk(100, "%s: firmware upload complete\n", __func__); - } return; } -static int s2255_got_frame(struct s2255_channel *channel, int jpgsize) +static int s2255_got_frame(struct s2255_vc *vc, int jpgsize) { - struct s2255_dmaqueue *dma_q = &channel->vidq; struct s2255_buffer *buf; - struct s2255_dev *dev = to_s2255_dev(channel->vdev.v4l2_dev); + struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); unsigned long flags = 0; int rc = 0; - spin_lock_irqsave(&dev->slock, flags); - if (list_empty(&dma_q->active)) { - dprintk(1, "No active queue to serve\n"); + spin_lock_irqsave(&vc->qlock, flags); + if (list_empty(&vc->buf_list)) { + dprintk(dev, 1, "No active queue to serve\n"); rc = -1; goto unlock; } - buf = list_entry(dma_q->active.next, - struct s2255_buffer, vb.queue); - list_del(&buf->vb.queue); - v4l2_get_timestamp(&buf->vb.ts); - s2255_fillbuff(channel, buf, jpgsize); - wake_up(&buf->vb.done); - dprintk(2, "%s: [buf/i] [%p/%d]\n", __func__, buf, buf->vb.i); + buf = list_entry(vc->buf_list.next, + struct s2255_buffer, list); + list_del(&buf->list); + v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); + s2255_fillbuff(vc, buf, jpgsize); + dprintk(dev, 2, "%s: [buf] [%p]\n", __func__, buf); unlock: - spin_unlock_irqrestore(&dev->slock, flags); + spin_unlock_irqrestore(&vc->qlock, flags); return rc; } @@ -615,9 +587,9 @@ static const struct s2255_fmt *format_by_fourcc(int fourcc) for (i = 0; i < ARRAY_SIZE(formats); i++) { if (-1 == formats[i].fourcc) continue; - if (!jpeg_enable && ((formats[i].fourcc == V4L2_PIX_FMT_JPEG) || - (formats[i].fourcc == V4L2_PIX_FMT_MJPEG))) - continue; + if (!jpeg_enable && ((formats[i].fourcc == V4L2_PIX_FMT_JPEG) || + (formats[i].fourcc == V4L2_PIX_FMT_MJPEG))) + continue; if (formats[i].fourcc == fourcc) return formats + i; } @@ -632,56 +604,56 @@ static const struct s2255_fmt *format_by_fourcc(int fourcc) * http://v4l.videotechnology.com/ * */ -static void s2255_fillbuff(struct s2255_channel *channel, +static void s2255_fillbuff(struct s2255_vc *vc, struct s2255_buffer *buf, int jpgsize) { int pos = 0; const char *tmpbuf; - char *vbuf = videobuf_to_vmalloc(&buf->vb); + char *vbuf = vb2_plane_vaddr(&buf->vb, 0); unsigned long last_frame; + struct s2255_dev *dev = vc->dev; if (!vbuf) return; - last_frame = channel->last_frame; + last_frame = vc->last_frame; if (last_frame != -1) { tmpbuf = - (const char *)channel->buffer.frame[last_frame].lpvbits; - switch (buf->fmt->fourcc) { + (const char *)vc->buffer.frame[last_frame].lpvbits; + switch (vc->fmt->fourcc) { case V4L2_PIX_FMT_YUYV: case V4L2_PIX_FMT_UYVY: planar422p_to_yuv_packed((const unsigned char *)tmpbuf, - vbuf, buf->vb.width, - buf->vb.height, - buf->fmt->fourcc); + vbuf, vc->width, + vc->height, + vc->fmt->fourcc); break; case V4L2_PIX_FMT_GREY: - memcpy(vbuf, tmpbuf, buf->vb.width * buf->vb.height); + memcpy(vbuf, tmpbuf, vc->width * vc->height); break; case V4L2_PIX_FMT_JPEG: case V4L2_PIX_FMT_MJPEG: - buf->vb.size = jpgsize; - memcpy(vbuf, tmpbuf, buf->vb.size); + buf->vb.v4l2_buf.length = jpgsize; + memcpy(vbuf, tmpbuf, jpgsize); break; case V4L2_PIX_FMT_YUV422P: memcpy(vbuf, tmpbuf, - buf->vb.width * buf->vb.height * 2); + vc->width * vc->height * 2); break; default: - printk(KERN_DEBUG "s2255: unknown format?\n"); + pr_info("s2255: unknown format?\n"); } - channel->last_frame = -1; + vc->last_frame = -1; } else { - printk(KERN_ERR "s2255: =======no frame\n"); + pr_err("s2255: =======no frame\n"); return; - } - dprintk(2, "s2255fill at : Buffer 0x%08lx size= %d\n", + dprintk(dev, 2, "s2255fill at : Buffer 0x%08lx size= %d\n", (unsigned long)vbuf, pos); /* tell v4l buffer was filled */ - - buf->vb.field_count = channel->frame_count * 2; - v4l2_get_timestamp(&buf->vb.ts); - buf->vb.state = VIDEOBUF_DONE; + buf->vb.v4l2_buf.field = vc->field; + buf->vb.v4l2_buf.sequence = vc->frame_count; + v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); + vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE); } @@ -689,144 +661,82 @@ static void s2255_fillbuff(struct s2255_channel *channel, Videobuf operations ------------------------------------------------------------------*/ -static int buffer_setup(struct videobuf_queue *vq, unsigned int *count, - unsigned int *size) +static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, + unsigned int *nbuffers, unsigned int *nplanes, + unsigned int sizes[], void *alloc_ctxs[]) { - struct s2255_fh *fh = vq->priv_data; - struct s2255_channel *channel = fh->channel; - *size = channel->width * channel->height * (channel->fmt->depth >> 3); - - if (0 == *count) - *count = S2255_DEF_BUFS; - - if (*size * *count > vid_limit * 1024 * 1024) - *count = (vid_limit * 1024 * 1024) / *size; - + struct s2255_vc *vc = vb2_get_drv_priv(vq); + if (*nbuffers < S2255_MIN_BUFS) + *nbuffers = S2255_MIN_BUFS; + *nplanes = 1; + sizes[0] = vc->width * vc->height * (vc->fmt->depth >> 3); return 0; } -static void free_buffer(struct videobuf_queue *vq, struct s2255_buffer *buf) -{ - dprintk(4, "%s\n", __func__); - - videobuf_vmalloc_free(&buf->vb); - buf->vb.state = VIDEOBUF_NEEDS_INIT; -} - -static int buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, - enum v4l2_field field) +static int buffer_prepare(struct vb2_buffer *vb) { - struct s2255_fh *fh = vq->priv_data; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = vb2_get_drv_priv(vb->vb2_queue); struct s2255_buffer *buf = container_of(vb, struct s2255_buffer, vb); - int rc; - int w = channel->width; - int h = channel->height; - dprintk(4, "%s, field=%d\n", __func__, field); - if (channel->fmt == NULL) + int w = vc->width; + int h = vc->height; + unsigned long size; + + dprintk(vc->dev, 4, "%s\n", __func__); + if (vc->fmt == NULL) return -EINVAL; - if ((w < norm_minw(channel)) || - (w > norm_maxw(channel)) || - (h < norm_minh(channel)) || - (h > norm_maxh(channel))) { - dprintk(4, "invalid buffer prepare\n"); + if ((w < norm_minw(vc)) || + (w > norm_maxw(vc)) || + (h < norm_minh(vc)) || + (h > norm_maxh(vc))) { + dprintk(vc->dev, 4, "invalid buffer prepare\n"); return -EINVAL; } - buf->vb.size = w * h * (channel->fmt->depth >> 3); - if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size) { - dprintk(4, "invalid buffer prepare\n"); + size = w * h * (vc->fmt->depth >> 3); + if (vb2_plane_size(vb, 0) < size) { + dprintk(vc->dev, 4, "invalid buffer prepare\n"); return -EINVAL; } - buf->fmt = channel->fmt; - buf->vb.width = w; - buf->vb.height = h; - buf->vb.field = field; - - if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { - rc = videobuf_iolock(vq, &buf->vb, NULL); - if (rc < 0) - goto fail; - } - - buf->vb.state = VIDEOBUF_PREPARED; + vb2_set_plane_payload(&buf->vb, 0, size); return 0; -fail: - free_buffer(vq, buf); - return rc; } -static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +static void buffer_queue(struct vb2_buffer *vb) { struct s2255_buffer *buf = container_of(vb, struct s2255_buffer, vb); - struct s2255_fh *fh = vq->priv_data; - struct s2255_channel *channel = fh->channel; - struct s2255_dmaqueue *vidq = &channel->vidq; - dprintk(1, "%s\n", __func__); - buf->vb.state = VIDEOBUF_QUEUED; - list_add_tail(&buf->vb.queue, &vidq->active); + struct s2255_vc *vc = vb2_get_drv_priv(vb->vb2_queue); + unsigned long flags = 0; + dprintk(vc->dev, 1, "%s\n", __func__); + spin_lock_irqsave(&vc->qlock, flags); + list_add_tail(&buf->list, &vc->buf_list); + spin_unlock_irqrestore(&vc->qlock, flags); } -static void buffer_release(struct videobuf_queue *vq, - struct videobuf_buffer *vb) -{ - struct s2255_buffer *buf = container_of(vb, struct s2255_buffer, vb); - struct s2255_fh *fh = vq->priv_data; - dprintk(4, "%s %d\n", __func__, fh->channel->idx); - free_buffer(vq, buf); -} +static int start_streaming(struct vb2_queue *vq, unsigned int count); +static int stop_streaming(struct vb2_queue *vq); -static struct videobuf_queue_ops s2255_video_qops = { - .buf_setup = buffer_setup, +static struct vb2_ops s2255_video_qops = { + .queue_setup = queue_setup, .buf_prepare = buffer_prepare, .buf_queue = buffer_queue, - .buf_release = buffer_release, + .start_streaming = start_streaming, + .stop_streaming = stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, }; - -static int res_get(struct s2255_fh *fh) -{ - struct s2255_channel *channel = fh->channel; - /* is it free? */ - if (channel->resources) - return 0; /* no, someone else uses it */ - /* it's free, grab it */ - channel->resources = 1; - fh->resources = 1; - dprintk(1, "s2255: res: get\n"); - return 1; -} - -static int res_locked(struct s2255_fh *fh) -{ - return fh->channel->resources; -} - -static int res_check(struct s2255_fh *fh) -{ - return fh->resources; -} - - -static void res_free(struct s2255_fh *fh) -{ - struct s2255_channel *channel = fh->channel; - channel->resources = 0; - fh->resources = 0; - dprintk(1, "res: put\n"); -} - static int vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap) { - struct s2255_fh *fh = file->private_data; - struct s2255_dev *dev = fh->dev; + struct s2255_vc *vc = video_drvdata(file); + struct s2255_dev *dev = vc->dev; strlcpy(cap->driver, "s2255", sizeof(cap->driver)); strlcpy(cap->card, "s2255", sizeof(cap->card)); usb_make_path(dev->udev, cap->bus_info, sizeof(cap->bus_info)); - cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | + V4L2_CAP_READWRITE; cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; return 0; } @@ -841,7 +751,6 @@ static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, if (!jpeg_enable && ((formats[index].fourcc == V4L2_PIX_FMT_JPEG) || (formats[index].fourcc == V4L2_PIX_FMT_MJPEG))) return -EINVAL; - dprintk(4, "name %s\n", formats[index].name); strlcpy(f->description, formats[index].name, sizeof(f->description)); f->pixelformat = formats[index].fourcc; return 0; @@ -850,19 +759,18 @@ static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) { - struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; - int is_ntsc = channel->std & V4L2_STD_525_60; + struct s2255_vc *vc = video_drvdata(file); + int is_ntsc = vc->std & V4L2_STD_525_60; - f->fmt.pix.width = channel->width; - f->fmt.pix.height = channel->height; + f->fmt.pix.width = vc->width; + f->fmt.pix.height = vc->height; if (f->fmt.pix.height >= (is_ntsc ? NUM_LINES_1CIFS_NTSC : NUM_LINES_1CIFS_PAL) * 2) f->fmt.pix.field = V4L2_FIELD_INTERLACED; else f->fmt.pix.field = V4L2_FIELD_TOP; - f->fmt.pix.pixelformat = channel->fmt->fourcc; - f->fmt.pix.bytesperline = f->fmt.pix.width * (channel->fmt->depth >> 3); + f->fmt.pix.pixelformat = vc->fmt->fourcc; + f->fmt.pix.bytesperline = f->fmt.pix.width * (vc->fmt->depth >> 3); f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; f->fmt.pix.priv = 0; @@ -874,9 +782,8 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, { const struct s2255_fmt *fmt; enum v4l2_field field; - struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; - int is_ntsc = channel->std & V4L2_STD_525_60; + struct s2255_vc *vc = video_drvdata(file); + int is_ntsc = vc->std & V4L2_STD_525_60; fmt = format_by_fourcc(f->fmt.pix.pixelformat); @@ -885,7 +792,7 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, field = f->fmt.pix.field; - dprintk(50, "%s NTSC: %d suggested width: %d, height: %d\n", + dprintk(vc->dev, 50, "%s NTSC: %d suggested width: %d, height: %d\n", __func__, is_ntsc, f->fmt.pix.width, f->fmt.pix.height); if (is_ntsc) { /* NTSC */ @@ -927,7 +834,7 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; f->fmt.pix.priv = 0; - dprintk(50, "%s: set width %d height %d field %d\n", __func__, + dprintk(vc->dev, 50, "%s: set width %d height %d field %d\n", __func__, f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field); return 0; } @@ -935,14 +842,13 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) { - struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = video_drvdata(file); const struct s2255_fmt *fmt; - struct videobuf_queue *q = &fh->vb_vidq; + struct vb2_queue *q = &vc->vb_vidq; struct s2255_mode mode; int ret; - ret = vidioc_try_fmt_vid_cap(file, fh, f); + ret = vidioc_try_fmt_vid_cap(file, vc, f); if (ret < 0) return ret; @@ -952,28 +858,19 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, if (fmt == NULL) return -EINVAL; - mutex_lock(&q->vb_lock); - - if (videobuf_queue_is_busy(&fh->vb_vidq)) { - dprintk(1, "queue busy\n"); - ret = -EBUSY; - goto out_s_fmt; + if (vb2_is_busy(q)) { + dprintk(vc->dev, 1, "queue busy\n"); + return -EBUSY; } - if (res_locked(fh)) { - dprintk(1, "%s: channel busy\n", __func__); - ret = -EBUSY; - goto out_s_fmt; - } - mode = channel->mode; - channel->fmt = fmt; - channel->width = f->fmt.pix.width; - channel->height = f->fmt.pix.height; - fh->vb_vidq.field = f->fmt.pix.field; - fh->type = f->type; - if (channel->width > norm_minw(channel)) { - if (channel->height > norm_minh(channel)) { - if (channel->cap_parm.capturemode & + mode = vc->mode; + vc->fmt = fmt; + vc->width = f->fmt.pix.width; + vc->height = f->fmt.pix.height; + vc->field = f->fmt.pix.field; + if (vc->width > norm_minw(vc)) { + if (vc->height > norm_minh(vc)) { + if (vc->cap_parm.capturemode & V4L2_MODE_HIGHQUALITY) mode.scale = SCALE_4CIFSI; else @@ -985,7 +882,7 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, mode.scale = SCALE_1CIFS; } /* color mode */ - switch (channel->fmt->fourcc) { + switch (vc->fmt->fourcc) { case V4L2_PIX_FMT_GREY: mode.color &= ~MASK_COLOR; mode.color |= COLOR_Y8; @@ -994,7 +891,7 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, case V4L2_PIX_FMT_MJPEG: mode.color &= ~MASK_COLOR; mode.color |= COLOR_JPG; - mode.color |= (channel->jpegqual << 8); + mode.color |= (vc->jpegqual << 8); break; case V4L2_PIX_FMT_YUV422P: mode.color &= ~MASK_COLOR; @@ -1007,52 +904,17 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, mode.color |= COLOR_YUVPK; break; } - if ((mode.color & MASK_COLOR) != (channel->mode.color & MASK_COLOR)) + if ((mode.color & MASK_COLOR) != (vc->mode.color & MASK_COLOR)) mode.restart = 1; - else if (mode.scale != channel->mode.scale) + else if (mode.scale != vc->mode.scale) mode.restart = 1; - else if (mode.format != channel->mode.format) + else if (mode.format != vc->mode.format) mode.restart = 1; - channel->mode = mode; - (void) s2255_set_mode(channel, &mode); - ret = 0; -out_s_fmt: - mutex_unlock(&q->vb_lock); - return ret; -} - -static int vidioc_reqbufs(struct file *file, void *priv, - struct v4l2_requestbuffers *p) -{ - int rc; - struct s2255_fh *fh = priv; - rc = videobuf_reqbufs(&fh->vb_vidq, p); - return rc; -} - -static int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *p) -{ - int rc; - struct s2255_fh *fh = priv; - rc = videobuf_querybuf(&fh->vb_vidq, p); - return rc; -} - -static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p) -{ - int rc; - struct s2255_fh *fh = priv; - rc = videobuf_qbuf(&fh->vb_vidq, p); - return rc; + vc->mode = mode; + (void) s2255_set_mode(vc, &mode); + return 0; } -static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) -{ - int rc; - struct s2255_fh *fh = priv; - rc = videobuf_dqbuf(&fh->vb_vidq, p, file->f_flags & O_NONBLOCK); - return rc; -} /* write to the configuration pipe, synchronously */ static int s2255_write_config(struct usb_device *udev, unsigned char *pbuf, @@ -1150,201 +1012,166 @@ static void s2255_print_cfg(struct s2255_dev *sdev, struct s2255_mode *mode) * When the restart parameter is set, we sleep for ONE frame to allow the * DSP time to get the new frame */ -static int s2255_set_mode(struct s2255_channel *channel, +static int s2255_set_mode(struct s2255_vc *vc, struct s2255_mode *mode) { int res; - __le32 *buffer; unsigned long chn_rev; - struct s2255_dev *dev = to_s2255_dev(channel->vdev.v4l2_dev); + struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); int i; + __le32 *buffer = dev->cmdbuf; - chn_rev = G_chnmap[channel->idx]; - dprintk(3, "%s channel: %d\n", __func__, channel->idx); + mutex_lock(&dev->cmdlock); + chn_rev = G_chnmap[vc->idx]; + dprintk(dev, 3, "%s channel: %d\n", __func__, vc->idx); /* if JPEG, set the quality */ if ((mode->color & MASK_COLOR) == COLOR_JPG) { mode->color &= ~MASK_COLOR; mode->color |= COLOR_JPG; mode->color &= ~MASK_JPG_QUALITY; - mode->color |= (channel->jpegqual << 8); + mode->color |= (vc->jpegqual << 8); } /* save the mode */ - channel->mode = *mode; - channel->req_image_size = get_transfer_size(mode); - dprintk(1, "%s: reqsize %ld\n", __func__, channel->req_image_size); - buffer = kzalloc(512, GFP_KERNEL); - if (buffer == NULL) { - dev_err(&dev->udev->dev, "out of mem\n"); - return -ENOMEM; - } + vc->mode = *mode; + vc->req_image_size = get_transfer_size(mode); + dprintk(dev, 1, "%s: reqsize %ld\n", __func__, vc->req_image_size); /* set the mode */ buffer[0] = IN_DATA_TOKEN; buffer[1] = (__le32) cpu_to_le32(chn_rev); buffer[2] = CMD_SET_MODE; for (i = 0; i < sizeof(struct s2255_mode) / sizeof(u32); i++) - buffer[3 + i] = cpu_to_le32(((u32 *)&channel->mode)[i]); - channel->setmode_ready = 0; + buffer[3 + i] = cpu_to_le32(((u32 *)&vc->mode)[i]); + vc->setmode_ready = 0; res = s2255_write_config(dev->udev, (unsigned char *)buffer, 512); if (debug) s2255_print_cfg(dev, mode); - kfree(buffer); /* wait at least 3 frames before continuing */ if (mode->restart) { - wait_event_timeout(channel->wait_setmode, - (channel->setmode_ready != 0), + wait_event_timeout(vc->wait_setmode, + (vc->setmode_ready != 0), msecs_to_jiffies(S2255_SETMODE_TIMEOUT)); - if (channel->setmode_ready != 1) { - printk(KERN_DEBUG "s2255: no set mode response\n"); + if (vc->setmode_ready != 1) { + dprintk(dev, 0, "s2255: no set mode response\n"); res = -EFAULT; } } /* clear the restart flag */ - channel->mode.restart = 0; - dprintk(1, "%s chn %d, result: %d\n", __func__, channel->idx, res); + vc->mode.restart = 0; + dprintk(dev, 1, "%s chn %d, result: %d\n", __func__, vc->idx, res); + mutex_unlock(&dev->cmdlock); return res; } -static int s2255_cmd_status(struct s2255_channel *channel, u32 *pstatus) +static int s2255_cmd_status(struct s2255_vc *vc, u32 *pstatus) { int res; - __le32 *buffer; u32 chn_rev; - struct s2255_dev *dev = to_s2255_dev(channel->vdev.v4l2_dev); - chn_rev = G_chnmap[channel->idx]; - dprintk(4, "%s chan %d\n", __func__, channel->idx); - buffer = kzalloc(512, GFP_KERNEL); - if (buffer == NULL) { - dev_err(&dev->udev->dev, "out of mem\n"); - return -ENOMEM; - } + struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); + __le32 *buffer = dev->cmdbuf; + + mutex_lock(&dev->cmdlock); + chn_rev = G_chnmap[vc->idx]; + dprintk(dev, 4, "%s chan %d\n", __func__, vc->idx); /* form the get vid status command */ buffer[0] = IN_DATA_TOKEN; buffer[1] = (__le32) cpu_to_le32(chn_rev); buffer[2] = CMD_STATUS; *pstatus = 0; - channel->vidstatus_ready = 0; + vc->vidstatus_ready = 0; res = s2255_write_config(dev->udev, (unsigned char *)buffer, 512); - kfree(buffer); - wait_event_timeout(channel->wait_vidstatus, - (channel->vidstatus_ready != 0), + wait_event_timeout(vc->wait_vidstatus, + (vc->vidstatus_ready != 0), msecs_to_jiffies(S2255_VIDSTATUS_TIMEOUT)); - if (channel->vidstatus_ready != 1) { - printk(KERN_DEBUG "s2255: no vidstatus response\n"); + if (vc->vidstatus_ready != 1) { + dprintk(dev, 0, "s2255: no vidstatus response\n"); res = -EFAULT; } - *pstatus = channel->vidstatus; - dprintk(4, "%s, vid status %d\n", __func__, *pstatus); + *pstatus = vc->vidstatus; + dprintk(dev, 4, "%s, vid status %d\n", __func__, *pstatus); + mutex_unlock(&dev->cmdlock); return res; } -static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +static int start_streaming(struct vb2_queue *vq, unsigned int count) { - int res; - struct s2255_fh *fh = priv; - struct s2255_dev *dev = fh->dev; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = vb2_get_drv_priv(vq); int j; - dprintk(4, "%s\n", __func__); - if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { - dev_err(&dev->udev->dev, "invalid fh type0\n"); - return -EINVAL; - } - if (i != fh->type) { - dev_err(&dev->udev->dev, "invalid fh type1\n"); - return -EINVAL; - } - if (!res_get(fh)) { - s2255_dev_err(&dev->udev->dev, "stream busy\n"); - return -EBUSY; - } - channel->last_frame = -1; - channel->bad_payload = 0; - channel->cur_frame = 0; - channel->frame_count = 0; + vc->last_frame = -1; + vc->bad_payload = 0; + vc->cur_frame = 0; + vc->frame_count = 0; for (j = 0; j < SYS_FRAMES; j++) { - channel->buffer.frame[j].ulState = S2255_READ_IDLE; - channel->buffer.frame[j].cur_size = 0; + vc->buffer.frame[j].ulState = S2255_READ_IDLE; + vc->buffer.frame[j].cur_size = 0; } - res = videobuf_streamon(&fh->vb_vidq); - if (res == 0) { - s2255_start_acquire(channel); - channel->b_acquire = 1; - } else - res_free(fh); - - return res; + return s2255_start_acquire(vc); } -static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +/* abort streaming and wait for last buffer */ +static int stop_streaming(struct vb2_queue *vq) { - struct s2255_fh *fh = priv; - dprintk(4, "%s\n, channel: %d", __func__, fh->channel->idx); - if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { - printk(KERN_ERR "invalid fh type0\n"); - return -EINVAL; + struct s2255_vc *vc = vb2_get_drv_priv(vq); + struct s2255_buffer *buf, *node; + unsigned long flags; + (void) s2255_stop_acquire(vc); + spin_lock_irqsave(&vc->qlock, flags); + list_for_each_entry_safe(buf, node, &vc->buf_list, list) { + list_del(&buf->list); + vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); + dprintk(vc->dev, 2, "[%p/%d] done\n", + buf, buf->vb.v4l2_buf.index); } - if (i != fh->type) { - printk(KERN_ERR "invalid type i\n"); - return -EINVAL; - } - s2255_stop_acquire(fh->channel); - videobuf_streamoff(&fh->vb_vidq); - res_free(fh); + spin_unlock_irqrestore(&vc->qlock, flags); return 0; } static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id i) { - struct s2255_fh *fh = priv; + struct s2255_vc *vc = video_drvdata(file); struct s2255_mode mode; - struct videobuf_queue *q = &fh->vb_vidq; - struct s2255_channel *channel = fh->channel; - int ret = 0; + struct vb2_queue *q = &vc->vb_vidq; - mutex_lock(&q->vb_lock); - if (res_locked(fh)) { - dprintk(1, "can't change standard after started\n"); - ret = -EBUSY; - goto out_s_std; - } - mode = fh->channel->mode; + /* + * Changing the standard implies a format change, which is not allowed + * while buffers for use with streaming have already been allocated. + */ + if (vb2_is_busy(q)) + return -EBUSY; + + mode = vc->mode; if (i & V4L2_STD_525_60) { - dprintk(4, "%s 60 Hz\n", __func__); + dprintk(vc->dev, 4, "%s 60 Hz\n", __func__); /* if changing format, reset frame decimation/intervals */ if (mode.format != FORMAT_NTSC) { mode.restart = 1; mode.format = FORMAT_NTSC; mode.fdec = FDEC_1; - channel->width = LINE_SZ_4CIFS_NTSC; - channel->height = NUM_LINES_4CIFS_NTSC * 2; + vc->width = LINE_SZ_4CIFS_NTSC; + vc->height = NUM_LINES_4CIFS_NTSC * 2; } } else if (i & V4L2_STD_625_50) { - dprintk(4, "%s 50 Hz\n", __func__); + dprintk(vc->dev, 4, "%s 50 Hz\n", __func__); if (mode.format != FORMAT_PAL) { mode.restart = 1; mode.format = FORMAT_PAL; mode.fdec = FDEC_1; - channel->width = LINE_SZ_4CIFS_PAL; - channel->height = NUM_LINES_4CIFS_PAL * 2; + vc->width = LINE_SZ_4CIFS_PAL; + vc->height = NUM_LINES_4CIFS_PAL * 2; } - } else { - ret = -EINVAL; - goto out_s_std; - } - fh->channel->std = i; + } else + return -EINVAL; + vc->std = i; if (mode.restart) - s2255_set_mode(fh->channel, &mode); -out_s_std: - mutex_unlock(&q->vb_lock); - return ret; + s2255_set_mode(vc, &mode); + return 0; } static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *i) { - struct s2255_fh *fh = priv; + struct s2255_vc *vc = video_drvdata(file); - *i = fh->channel->std; + *i = vc->std; return 0; } @@ -1358,10 +1185,10 @@ static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *i) static int vidioc_enum_input(struct file *file, void *priv, struct v4l2_input *inp) { - struct s2255_fh *fh = priv; - struct s2255_dev *dev = fh->dev; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = video_drvdata(file); + struct s2255_dev *dev = vc->dev; u32 status = 0; + if (inp->index != 0) return -EINVAL; inp->type = V4L2_INPUT_TYPE_CAMERA; @@ -1369,8 +1196,9 @@ static int vidioc_enum_input(struct file *file, void *priv, inp->status = 0; if (dev->dsp_fw_ver >= S2255_MIN_DSP_STATUS) { int rc; - rc = s2255_cmd_status(fh->channel, &status); - dprintk(4, "s2255_cmd_status rc: %d status %x\n", rc, status); + rc = s2255_cmd_status(vc, &status); + dprintk(dev, 4, "s2255_cmd_status rc: %d status %x\n", + rc, status); if (rc == 0) inp->status = (status & 0x01) ? 0 : V4L2_IN_ST_NO_SIGNAL; @@ -1381,7 +1209,7 @@ static int vidioc_enum_input(struct file *file, void *priv, strlcpy(inp->name, "Composite", sizeof(inp->name)); break; case 0x2257: - strlcpy(inp->name, (channel->idx < 2) ? "Composite" : "S-Video", + strlcpy(inp->name, (vc->idx < 2) ? "Composite" : "S-Video", sizeof(inp->name)); break; } @@ -1402,13 +1230,10 @@ static int vidioc_s_input(struct file *file, void *priv, unsigned int i) static int s2255_s_ctrl(struct v4l2_ctrl *ctrl) { - struct s2255_channel *channel = - container_of(ctrl->handler, struct s2255_channel, hdl); + struct s2255_vc *vc = + container_of(ctrl->handler, struct s2255_vc, hdl); struct s2255_mode mode; - - mode = channel->mode; - dprintk(4, "%s\n", __func__); - + mode = vc->mode; /* update the mode to the corresponding value */ switch (ctrl->id) { case V4L2_CID_BRIGHTNESS: @@ -1428,7 +1253,7 @@ static int s2255_s_ctrl(struct v4l2_ctrl *ctrl) mode.color |= !ctrl->val << 16; break; case V4L2_CID_JPEG_COMPRESSION_QUALITY: - channel->jpegqual = ctrl->val; + vc->jpegqual = ctrl->val; return 0; default: return -EINVAL; @@ -1438,48 +1263,48 @@ static int s2255_s_ctrl(struct v4l2_ctrl *ctrl) some V4L programs restart stream unnecessarily after a s_crtl. */ - s2255_set_mode(channel, &mode); + s2255_set_mode(vc, &mode); return 0; } static int vidioc_g_jpegcomp(struct file *file, void *priv, struct v4l2_jpegcompression *jc) { - struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = video_drvdata(file); memset(jc, 0, sizeof(*jc)); - jc->quality = channel->jpegqual; - dprintk(2, "%s: quality %d\n", __func__, jc->quality); + jc->quality = vc->jpegqual; + dprintk(vc->dev, 2, "%s: quality %d\n", __func__, jc->quality); return 0; } static int vidioc_s_jpegcomp(struct file *file, void *priv, const struct v4l2_jpegcompression *jc) { - struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = video_drvdata(file); + if (jc->quality < 0 || jc->quality > 100) return -EINVAL; - v4l2_ctrl_s_ctrl(channel->jpegqual_ctrl, jc->quality); - dprintk(2, "%s: quality %d\n", __func__, jc->quality); + v4l2_ctrl_s_ctrl(vc->jpegqual_ctrl, jc->quality); + dprintk(vc->dev, 2, "%s: quality %d\n", __func__, jc->quality); return 0; } static int vidioc_g_parm(struct file *file, void *priv, struct v4l2_streamparm *sp) { - struct s2255_fh *fh = priv; __u32 def_num, def_dem; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = video_drvdata(file); + if (sp->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; sp->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; - sp->parm.capture.capturemode = channel->cap_parm.capturemode; - def_num = (channel->mode.format == FORMAT_NTSC) ? 1001 : 1000; - def_dem = (channel->mode.format == FORMAT_NTSC) ? 30000 : 25000; + sp->parm.capture.capturemode = vc->cap_parm.capturemode; + sp->parm.capture.readbuffers = S2255_MIN_BUFS; + def_num = (vc->mode.format == FORMAT_NTSC) ? 1001 : 1000; + def_dem = (vc->mode.format == FORMAT_NTSC) ? 30000 : 25000; sp->parm.capture.timeperframe.denominator = def_dem; - switch (channel->mode.fdec) { + switch (vc->mode.fdec) { default: case FDEC_1: sp->parm.capture.timeperframe.numerator = def_num; @@ -1494,7 +1319,8 @@ static int vidioc_g_parm(struct file *file, void *priv, sp->parm.capture.timeperframe.numerator = def_num * 5; break; } - dprintk(4, "%s capture mode, %d timeperframe %d/%d\n", __func__, + dprintk(vc->dev, 4, "%s capture mode, %d timeperframe %d/%d\n", + __func__, sp->parm.capture.capturemode, sp->parm.capture.timeperframe.numerator, sp->parm.capture.timeperframe.denominator); @@ -1504,17 +1330,16 @@ static int vidioc_g_parm(struct file *file, void *priv, static int vidioc_s_parm(struct file *file, void *priv, struct v4l2_streamparm *sp) { - struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = video_drvdata(file); struct s2255_mode mode; int fdec = FDEC_1; __u32 def_num, def_dem; if (sp->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; - mode = channel->mode; + mode = vc->mode; /* high quality capture mode requires a stream restart */ - if (channel->cap_parm.capturemode - != sp->parm.capture.capturemode && res_locked(fh)) + if ((vc->cap_parm.capturemode != sp->parm.capture.capturemode) + && vb2_is_streaming(&vc->vb_vidq)) return -EBUSY; def_num = (mode.format == FORMAT_NTSC) ? 1001 : 1000; def_dem = (mode.format == FORMAT_NTSC) ? 30000 : 25000; @@ -1534,8 +1359,9 @@ static int vidioc_s_parm(struct file *file, void *priv, } mode.fdec = fdec; sp->parm.capture.timeperframe.denominator = def_dem; - s2255_set_mode(channel, &mode); - dprintk(4, "%s capture mode, %d timeperframe %d/%d, fdec %d\n", + sp->parm.capture.readbuffers = S2255_MIN_BUFS; + s2255_set_mode(vc, &mode); + dprintk(vc->dev, 4, "%s capture mode, %d timeperframe %d/%d, fdec %d\n", __func__, sp->parm.capture.capturemode, sp->parm.capture.timeperframe.numerator, @@ -1558,9 +1384,8 @@ static const struct v4l2_frmsize_discrete pal_sizes[] = { static int vidioc_enum_framesizes(struct file *file, void *priv, struct v4l2_frmsizeenum *fe) { - struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; - int is_ntsc = channel->std & V4L2_STD_525_60; + struct s2255_vc *vc = video_drvdata(file); + int is_ntsc = vc->std & V4L2_STD_525_60; const struct s2255_fmt *fmt; if (fe->index >= NUM_SIZE_ENUMS) @@ -1577,11 +1402,10 @@ static int vidioc_enum_framesizes(struct file *file, void *priv, static int vidioc_enum_frameintervals(struct file *file, void *priv, struct v4l2_frmivalenum *fe) { - struct s2255_fh *fh = priv; - struct s2255_channel *channel = fh->channel; + struct s2255_vc *vc = video_drvdata(file); const struct s2255_fmt *fmt; const struct v4l2_frmsize_discrete *sizes; - int is_ntsc = channel->std & V4L2_STD_525_60; + int is_ntsc = vc->std & V4L2_STD_525_60; #define NUM_FRAME_ENUMS 4 int frm_dec[NUM_FRAME_ENUMS] = {1, 2, 3, 5}; int i; @@ -1604,21 +1428,24 @@ static int vidioc_enum_frameintervals(struct file *file, void *priv, fe->type = V4L2_FRMIVAL_TYPE_DISCRETE; fe->discrete.denominator = is_ntsc ? 30000 : 25000; fe->discrete.numerator = (is_ntsc ? 1001 : 1000) * frm_dec[fe->index]; - dprintk(4, "%s discrete %d/%d\n", __func__, fe->discrete.numerator, + dprintk(vc->dev, 4, "%s discrete %d/%d\n", __func__, + fe->discrete.numerator, fe->discrete.denominator); return 0; } -static int __s2255_open(struct file *file) +static int s2255_open(struct file *file) { - struct video_device *vdev = video_devdata(file); - struct s2255_channel *channel = video_drvdata(file); - struct s2255_dev *dev = to_s2255_dev(vdev->v4l2_dev); - struct s2255_fh *fh; - enum v4l2_buf_type type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + struct s2255_vc *vc = video_drvdata(file); + struct s2255_dev *dev = vc->dev; int state; - dprintk(1, "s2255: open called (dev=%s)\n", - video_device_node_name(vdev)); + int rc = 0; + + rc = v4l2_fh_open(file); + if (rc != 0) + return rc; + + dprintk(dev, 1, "s2255: %s\n", __func__); state = atomic_read(&dev->fw_data->fw_state); switch (state) { case S2255_FW_DISCONNECTING: @@ -1640,7 +1467,7 @@ static int __s2255_open(struct file *file) case S2255_FW_LOADED_DSPWAIT: /* give S2255_LOAD_TIMEOUT time for firmware to load in case driver loaded and then device immediately opened */ - printk(KERN_INFO "%s waiting for firmware load\n", __func__); + pr_info("%s waiting for firmware load\n", __func__); wait_event_timeout(dev->fw_data->wait_fw, ((atomic_read(&dev->fw_data->fw_state) == S2255_FW_SUCCESS) || @@ -1659,16 +1486,15 @@ static int __s2255_open(struct file *file) case S2255_FW_SUCCESS: break; case S2255_FW_FAILED: - printk(KERN_INFO "2255 firmware load failed.\n"); + pr_info("2255 firmware load failed.\n"); return -ENODEV; case S2255_FW_DISCONNECTING: - printk(KERN_INFO "%s: disconnecting\n", __func__); + pr_info("%s: disconnecting\n", __func__); return -ENODEV; case S2255_FW_LOADED_DSPWAIT: case S2255_FW_NOTLOADED: - printk(KERN_INFO "%s: firmware not loaded yet" - "please try again later\n", - __func__); + pr_info("%s: firmware not loaded, please retry\n", + __func__); /* * Timeout on firmware load means device unusable. * Set firmware failure state. @@ -1678,71 +1504,21 @@ static int __s2255_open(struct file *file) S2255_FW_FAILED); return -EAGAIN; default: - printk(KERN_INFO "%s: unknown state\n", __func__); + pr_info("%s: unknown state\n", __func__); return -EFAULT; } - /* allocate + initialize per filehandle data */ - fh = kzalloc(sizeof(*fh), GFP_KERNEL); - if (NULL == fh) - return -ENOMEM; - v4l2_fh_init(&fh->fh, vdev); - v4l2_fh_add(&fh->fh); - file->private_data = &fh->fh; - fh->dev = dev; - fh->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - fh->channel = channel; - if (!channel->configured) { + if (!vc->configured) { /* configure channel to default state */ - channel->fmt = &formats[0]; - s2255_set_mode(channel, &channel->mode); - channel->configured = 1; - } - dprintk(1, "%s: dev=%s type=%s\n", __func__, - video_device_node_name(vdev), v4l2_type_names[type]); - dprintk(2, "%s: fh=0x%08lx, dev=0x%08lx, vidq=0x%08lx\n", __func__, - (unsigned long)fh, (unsigned long)dev, - (unsigned long)&channel->vidq); - dprintk(4, "%s: list_empty active=%d\n", __func__, - list_empty(&channel->vidq.active)); - videobuf_queue_vmalloc_init(&fh->vb_vidq, &s2255_video_qops, - NULL, &dev->slock, - fh->type, - V4L2_FIELD_INTERLACED, - sizeof(struct s2255_buffer), - fh, vdev->lock); + vc->fmt = &formats[0]; + s2255_set_mode(vc, &vc->mode); + vc->configured = 1; + } return 0; } -static int s2255_open(struct file *file) -{ - struct video_device *vdev = video_devdata(file); - int ret; - - if (mutex_lock_interruptible(vdev->lock)) - return -ERESTARTSYS; - ret = __s2255_open(file); - mutex_unlock(vdev->lock); - return ret; -} - -static unsigned int s2255_poll(struct file *file, - struct poll_table_struct *wait) -{ - struct s2255_fh *fh = file->private_data; - struct s2255_dev *dev = fh->dev; - int rc = v4l2_ctrl_poll(file, wait); - - dprintk(100, "%s\n", __func__); - if (V4L2_BUF_TYPE_VIDEO_CAPTURE != fh->type) - return POLLERR; - mutex_lock(&dev->lock); - rc |= videobuf_poll_stream(file, &fh->vb_vidq, wait); - mutex_unlock(&dev->lock); - return rc; -} - static void s2255_destroy(struct s2255_dev *dev) { + dprintk(dev, 1, "%s", __func__); /* board shutdown stops the read pipe if it is running */ s2255_board_shutdown(dev); /* make sure firmware still not trying to load */ @@ -1760,62 +1536,18 @@ static void s2255_destroy(struct s2255_dev *dev) mutex_destroy(&dev->lock); usb_put_dev(dev->udev); v4l2_device_unregister(&dev->v4l2_dev); - dprintk(1, "%s", __func__); + kfree(dev->cmdbuf); kfree(dev); } -static int s2255_release(struct file *file) -{ - struct s2255_fh *fh = file->private_data; - struct s2255_dev *dev = fh->dev; - struct video_device *vdev = video_devdata(file); - struct s2255_channel *channel = fh->channel; - if (!dev) - return -ENODEV; - mutex_lock(&dev->lock); - /* turn off stream */ - if (res_check(fh)) { - if (channel->b_acquire) - s2255_stop_acquire(fh->channel); - videobuf_streamoff(&fh->vb_vidq); - res_free(fh); - } - videobuf_mmap_free(&fh->vb_vidq); - mutex_unlock(&dev->lock); - dprintk(1, "%s (dev=%s)\n", __func__, video_device_node_name(vdev)); - v4l2_fh_del(&fh->fh); - v4l2_fh_exit(&fh->fh); - kfree(fh); - return 0; -} - -static int s2255_mmap_v4l(struct file *file, struct vm_area_struct *vma) -{ - struct s2255_fh *fh = file->private_data; - struct s2255_dev *dev; - int ret; - - if (!fh) - return -ENODEV; - dev = fh->dev; - dprintk(4, "%s, vma=0x%08lx\n", __func__, (unsigned long)vma); - if (mutex_lock_interruptible(&dev->lock)) - return -ERESTARTSYS; - ret = videobuf_mmap_mapper(&fh->vb_vidq, vma); - mutex_unlock(&dev->lock); - dprintk(4, "%s vma start=0x%08lx, size=%ld, ret=%d\n", __func__, - (unsigned long)vma->vm_start, - (unsigned long)vma->vm_end - (unsigned long)vma->vm_start, ret); - return ret; -} - static const struct v4l2_file_operations s2255_fops_v4l = { .owner = THIS_MODULE, .open = s2255_open, - .release = s2255_release, - .poll = s2255_poll, + .release = vb2_fop_release, + .poll = vb2_fop_poll, .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */ - .mmap = s2255_mmap_v4l, + .mmap = vb2_fop_mmap, + .read = vb2_fop_read, }; static const struct v4l2_ioctl_ops s2255_ioctl_ops = { @@ -1824,17 +1556,17 @@ static const struct v4l2_ioctl_ops s2255_ioctl_ops = { .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, - .vidioc_reqbufs = vidioc_reqbufs, - .vidioc_querybuf = vidioc_querybuf, - .vidioc_qbuf = vidioc_qbuf, - .vidioc_dqbuf = vidioc_dqbuf, + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, .vidioc_s_std = vidioc_s_std, .vidioc_g_std = vidioc_g_std, .vidioc_enum_input = vidioc_enum_input, .vidioc_g_input = vidioc_g_input, .vidioc_s_input = vidioc_s_input, - .vidioc_streamon = vidioc_streamon, - .vidioc_streamoff = vidioc_streamoff, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, .vidioc_s_jpegcomp = vidioc_s_jpegcomp, .vidioc_g_jpegcomp = vidioc_g_jpegcomp, .vidioc_s_parm = vidioc_s_parm, @@ -1849,13 +1581,14 @@ static const struct v4l2_ioctl_ops s2255_ioctl_ops = { static void s2255_video_device_release(struct video_device *vdev) { struct s2255_dev *dev = to_s2255_dev(vdev->v4l2_dev); - struct s2255_channel *channel = - container_of(vdev, struct s2255_channel, vdev); + struct s2255_vc *vc = + container_of(vdev, struct s2255_vc, vdev); - v4l2_ctrl_handler_free(&channel->hdl); - dprintk(4, "%s, chnls: %d\n", __func__, + dprintk(dev, 4, "%s, chnls: %d\n", __func__, atomic_read(&dev->num_channels)); + v4l2_ctrl_handler_free(&vc->hdl); + if (atomic_dec_and_test(&dev->num_channels)) s2255_destroy(dev); return; @@ -1888,52 +1621,70 @@ static int s2255_probe_v4l(struct s2255_dev *dev) int ret; int i; int cur_nr = video_nr; - struct s2255_channel *channel; + struct s2255_vc *vc; + struct vb2_queue *q; + ret = v4l2_device_register(&dev->interface->dev, &dev->v4l2_dev); if (ret) return ret; /* initialize all video 4 linux */ /* register 4 video devices */ for (i = 0; i < MAX_CHANNELS; i++) { - channel = &dev->channel[i]; - INIT_LIST_HEAD(&channel->vidq.active); + vc = &dev->vc[i]; + INIT_LIST_HEAD(&vc->buf_list); - v4l2_ctrl_handler_init(&channel->hdl, 6); - v4l2_ctrl_new_std(&channel->hdl, &s2255_ctrl_ops, + v4l2_ctrl_handler_init(&vc->hdl, 6); + v4l2_ctrl_new_std(&vc->hdl, &s2255_ctrl_ops, V4L2_CID_BRIGHTNESS, -127, 127, 1, DEF_BRIGHT); - v4l2_ctrl_new_std(&channel->hdl, &s2255_ctrl_ops, + v4l2_ctrl_new_std(&vc->hdl, &s2255_ctrl_ops, V4L2_CID_CONTRAST, 0, 255, 1, DEF_CONTRAST); - v4l2_ctrl_new_std(&channel->hdl, &s2255_ctrl_ops, + v4l2_ctrl_new_std(&vc->hdl, &s2255_ctrl_ops, V4L2_CID_SATURATION, 0, 255, 1, DEF_SATURATION); - v4l2_ctrl_new_std(&channel->hdl, &s2255_ctrl_ops, + v4l2_ctrl_new_std(&vc->hdl, &s2255_ctrl_ops, V4L2_CID_HUE, 0, 255, 1, DEF_HUE); - channel->jpegqual_ctrl = v4l2_ctrl_new_std(&channel->hdl, + vc->jpegqual_ctrl = v4l2_ctrl_new_std(&vc->hdl, &s2255_ctrl_ops, V4L2_CID_JPEG_COMPRESSION_QUALITY, 0, 100, 1, S2255_DEF_JPEG_QUAL); if (dev->dsp_fw_ver >= S2255_MIN_DSP_COLORFILTER && - (dev->pid != 0x2257 || channel->idx <= 1)) - v4l2_ctrl_new_custom(&channel->hdl, &color_filter_ctrl, NULL); - if (channel->hdl.error) { - ret = channel->hdl.error; - v4l2_ctrl_handler_free(&channel->hdl); + (dev->pid != 0x2257 || vc->idx <= 1)) + v4l2_ctrl_new_custom(&vc->hdl, &color_filter_ctrl, + NULL); + if (vc->hdl.error) { + ret = vc->hdl.error; + v4l2_ctrl_handler_free(&vc->hdl); dev_err(&dev->udev->dev, "couldn't register control\n"); break; } - channel->vidq.dev = dev; - /* register 4 video devices */ - channel->vdev = template; - channel->vdev.ctrl_handler = &channel->hdl; - channel->vdev.lock = &dev->lock; - channel->vdev.v4l2_dev = &dev->v4l2_dev; - set_bit(V4L2_FL_USE_FH_PRIO, &channel->vdev.flags); - video_set_drvdata(&channel->vdev, channel); + q = &vc->vb_vidq; + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + q->io_modes = VB2_MMAP | VB2_READ | VB2_USERPTR; + q->drv_priv = vc; + q->lock = &vc->vb_lock; + q->buf_struct_size = sizeof(struct s2255_buffer); + q->mem_ops = &vb2_vmalloc_memops; + q->ops = &s2255_video_qops; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + ret = vb2_queue_init(q); + if (ret != 0) { + dev_err(&dev->udev->dev, + "%s vb2_queue_init 0x%x\n", __func__, ret); + break; + } + /* register video devices */ + vc->vdev = template; + vc->vdev.queue = q; + vc->vdev.ctrl_handler = &vc->hdl; + vc->vdev.lock = &dev->lock; + vc->vdev.v4l2_dev = &dev->v4l2_dev; + set_bit(V4L2_FL_USE_FH_PRIO, &vc->vdev.flags); + video_set_drvdata(&vc->vdev, vc); if (video_nr == -1) - ret = video_register_device(&channel->vdev, + ret = video_register_device(&vc->vdev, VFL_TYPE_GRABBER, video_nr); else - ret = video_register_device(&channel->vdev, + ret = video_register_device(&vc->vdev, VFL_TYPE_GRABBER, cur_nr + i); @@ -1944,18 +1695,18 @@ static int s2255_probe_v4l(struct s2255_dev *dev) } atomic_inc(&dev->num_channels); v4l2_info(&dev->v4l2_dev, "V4L2 device registered as %s\n", - video_device_node_name(&channel->vdev)); + video_device_node_name(&vc->vdev)); } - printk(KERN_INFO "Sensoray 2255 V4L driver Revision: %s\n", - S2255_VERSION); + pr_info("Sensoray 2255 V4L driver Revision: %s\n", + S2255_VERSION); /* if no channels registered, return error and probe will fail*/ if (atomic_read(&dev->num_channels) == 0) { v4l2_device_unregister(&dev->v4l2_dev); return ret; } if (atomic_read(&dev->num_channels) != MAX_CHANNELS) - printk(KERN_WARNING "s2255: Not all channels available.\n"); + pr_warn("s2255: Not all channels available.\n"); return 0; } @@ -1981,11 +1732,11 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) s32 idx = -1; struct s2255_framei *frm; unsigned char *pdata; - struct s2255_channel *channel; - dprintk(100, "buffer to user\n"); - channel = &dev->channel[dev->cc]; - idx = channel->cur_frame; - frm = &channel->buffer.frame[idx]; + struct s2255_vc *vc; + dprintk(dev, 100, "buffer to user\n"); + vc = &dev->vc[dev->cc]; + idx = vc->cur_frame; + frm = &vc->buffer.frame[idx]; if (frm->ulState == S2255_READ_IDLE) { int jj; unsigned int cc; @@ -1997,28 +1748,27 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) for (jj = 0; jj < (pipe_info->cur_transfer_size - 12); jj++) { switch (*pdword) { case S2255_MARKER_FRAME: - dprintk(4, "found frame marker at offset:" - " %d [%x %x]\n", jj, pdata[0], - pdata[1]); + dprintk(dev, 4, "marker @ offset: %d [%x %x]\n", + jj, pdata[0], pdata[1]); offset = jj + PREFIX_SIZE; bframe = 1; cc = le32_to_cpu(pdword[1]); if (cc >= MAX_CHANNELS) { - printk(KERN_ERR - "bad channel\n"); + dprintk(dev, 0, + "bad channel\n"); return -EINVAL; } /* reverse it */ dev->cc = G_chnmap[cc]; - channel = &dev->channel[dev->cc]; + vc = &dev->vc[dev->cc]; payload = le32_to_cpu(pdword[3]); - if (payload > channel->req_image_size) { - channel->bad_payload++; + if (payload > vc->req_image_size) { + vc->bad_payload++; /* discard the bad frame */ return -EINVAL; } - channel->pkt_size = payload; - channel->jpg_size = le32_to_cpu(pdword[4]); + vc->pkt_size = payload; + vc->jpg_size = le32_to_cpu(pdword[4]); break; case S2255_MARKER_RESPONSE: @@ -2029,34 +1779,34 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) cc = G_chnmap[le32_to_cpu(pdword[1])]; if (cc >= MAX_CHANNELS) break; - channel = &dev->channel[cc]; + vc = &dev->vc[cc]; switch (pdword[2]) { case S2255_RESPONSE_SETMODE: /* check if channel valid */ /* set mode ready */ - channel->setmode_ready = 1; - wake_up(&channel->wait_setmode); - dprintk(5, "setmode ready %d\n", cc); + vc->setmode_ready = 1; + wake_up(&vc->wait_setmode); + dprintk(dev, 5, "setmode rdy %d\n", cc); break; case S2255_RESPONSE_FW: dev->chn_ready |= (1 << cc); if ((dev->chn_ready & 0x0f) != 0x0f) break; /* all channels ready */ - printk(KERN_INFO "s2255: fw loaded\n"); + pr_info("s2255: fw loaded\n"); atomic_set(&dev->fw_data->fw_state, S2255_FW_SUCCESS); wake_up(&dev->fw_data->wait_fw); break; case S2255_RESPONSE_STATUS: - channel->vidstatus = le32_to_cpu(pdword[3]); - channel->vidstatus_ready = 1; - wake_up(&channel->wait_vidstatus); - dprintk(5, "got vidstatus %x chan %d\n", + vc->vidstatus = le32_to_cpu(pdword[3]); + vc->vidstatus_ready = 1; + wake_up(&vc->wait_vidstatus); + dprintk(dev, 5, "vstat %x chan %d\n", le32_to_cpu(pdword[3]), cc); break; default: - printk(KERN_INFO "s2255 unknown resp\n"); + pr_info("s2255 unknown resp\n"); } default: pdata++; @@ -2068,11 +1818,11 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) if (!bframe) return -EINVAL; } - channel = &dev->channel[dev->cc]; - idx = channel->cur_frame; - frm = &channel->buffer.frame[idx]; + vc = &dev->vc[dev->cc]; + idx = vc->cur_frame; + frm = &vc->buffer.frame[idx]; /* search done. now find out if should be acquiring on this channel */ - if (!channel->b_acquire) { + if (!vb2_is_streaming(&vc->vb_vidq)) { /* we found a frame, but this channel is turned off */ frm->ulState = S2255_READ_IDLE; return -EINVAL; @@ -2088,7 +1838,7 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) if (frm->lpvbits == NULL) { - dprintk(1, "s2255 frame buffer == NULL.%p %p %d %d", + dprintk(dev, 1, "s2255 frame buffer == NULL.%p %p %d %d", frm, dev, dev->cc, idx); return -ENOMEM; } @@ -2097,28 +1847,28 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) copy_size = (pipe_info->cur_transfer_size - offset); - size = channel->pkt_size - PREFIX_SIZE; + size = vc->pkt_size - PREFIX_SIZE; /* sanity check on pdest */ - if ((copy_size + frm->cur_size) < channel->req_image_size) + if ((copy_size + frm->cur_size) < vc->req_image_size) memcpy(pdest, psrc, copy_size); frm->cur_size += copy_size; - dprintk(4, "cur_size size %lu size %lu \n", frm->cur_size, size); + dprintk(dev, 4, "cur_size: %lu, size: %lu\n", frm->cur_size, size); if (frm->cur_size >= size) { - dprintk(2, "****************[%d]Buffer[%d]full*************\n", + dprintk(dev, 2, "******[%d]Buffer[%d]full*******\n", dev->cc, idx); - channel->last_frame = channel->cur_frame; - channel->cur_frame++; + vc->last_frame = vc->cur_frame; + vc->cur_frame++; /* end of system frame ring buffer, start at zero */ - if ((channel->cur_frame == SYS_FRAMES) || - (channel->cur_frame == channel->buffer.dwFrames)) - channel->cur_frame = 0; + if ((vc->cur_frame == SYS_FRAMES) || + (vc->cur_frame == vc->buffer.dwFrames)) + vc->cur_frame = 0; /* frame ready */ - if (channel->b_acquire) - s2255_got_frame(channel, channel->jpg_size); - channel->frame_count++; + if (vb2_is_streaming(&vc->vb_vidq)) + s2255_got_frame(vc, vc->jpg_size); + vc->frame_count++; frm->ulState = S2255_READ_IDLE; frm->cur_size = 0; @@ -2131,7 +1881,7 @@ static void s2255_read_video_callback(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info) { int res; - dprintk(50, "callback read video \n"); + dprintk(dev, 50, "callback read video\n"); if (dev->cc >= MAX_CHANNELS) { dev->cc = 0; @@ -2141,9 +1891,9 @@ static void s2255_read_video_callback(struct s2255_dev *dev, /* otherwise copy to the system buffers */ res = save_frame(dev, pipe_info); if (res != 0) - dprintk(4, "s2255: read callback failed\n"); + dprintk(dev, 4, "s2255: read callback failed\n"); - dprintk(50, "callback read video done\n"); + dprintk(dev, 50, "callback read video done\n"); return; } @@ -2181,9 +1931,9 @@ static int s2255_get_fx2fw(struct s2255_dev *dev) ret = s2255_vendor_req(dev, S2255_VR_FW, 0, 0, transBuffer, 2, S2255_VR_IN); if (ret < 0) - dprintk(2, "get fw error: %x\n", ret); + dprintk(dev, 2, "get fw error: %x\n", ret); fw = transBuffer[0] + (transBuffer[1] << 8); - dprintk(2, "Get FW %x %x\n", transBuffer[0], transBuffer[1]); + dprintk(dev, 2, "Get FW %x %x\n", transBuffer[0], transBuffer[1]); return fw; } @@ -2191,12 +1941,11 @@ static int s2255_get_fx2fw(struct s2255_dev *dev) * Create the system ring buffer to copy frames into from the * usb read pipe. */ -static int s2255_create_sys_buffers(struct s2255_channel *channel) +static int s2255_create_sys_buffers(struct s2255_vc *vc) { unsigned long i; unsigned long reqsize; - dprintk(1, "create sys buffers\n"); - channel->buffer.dwFrames = SYS_FRAMES; + vc->buffer.dwFrames = SYS_FRAMES; /* always allocate maximum size(PAL) for system buffers */ reqsize = SYS_FRAMES_MAXSIZE; @@ -2205,40 +1954,33 @@ static int s2255_create_sys_buffers(struct s2255_channel *channel) for (i = 0; i < SYS_FRAMES; i++) { /* allocate the frames */ - channel->buffer.frame[i].lpvbits = vmalloc(reqsize); - dprintk(1, "valloc %p chan %d, idx %lu, pdata %p\n", - &channel->buffer.frame[i], channel->idx, i, - channel->buffer.frame[i].lpvbits); - channel->buffer.frame[i].size = reqsize; - if (channel->buffer.frame[i].lpvbits == NULL) { - printk(KERN_INFO "out of memory. using less frames\n"); - channel->buffer.dwFrames = i; + vc->buffer.frame[i].lpvbits = vmalloc(reqsize); + vc->buffer.frame[i].size = reqsize; + if (vc->buffer.frame[i].lpvbits == NULL) { + pr_info("out of memory. using less frames\n"); + vc->buffer.dwFrames = i; break; } } /* make sure internal states are set */ for (i = 0; i < SYS_FRAMES; i++) { - channel->buffer.frame[i].ulState = 0; - channel->buffer.frame[i].cur_size = 0; + vc->buffer.frame[i].ulState = 0; + vc->buffer.frame[i].cur_size = 0; } - channel->cur_frame = 0; - channel->last_frame = -1; + vc->cur_frame = 0; + vc->last_frame = -1; return 0; } -static int s2255_release_sys_buffers(struct s2255_channel *channel) +static int s2255_release_sys_buffers(struct s2255_vc *vc) { unsigned long i; - dprintk(1, "release sys buffers\n"); for (i = 0; i < SYS_FRAMES; i++) { - if (channel->buffer.frame[i].lpvbits) { - dprintk(1, "vfree %p\n", - channel->buffer.frame[i].lpvbits); - vfree(channel->buffer.frame[i].lpvbits); - } - channel->buffer.frame[i].lpvbits = NULL; + if (vc->buffer.frame[i].lpvbits) + vfree(vc->buffer.frame[i].lpvbits); + vc->buffer.frame[i].lpvbits = NULL; } return 0; } @@ -2249,7 +1991,7 @@ static int s2255_board_init(struct s2255_dev *dev) int fw_ver; int j; struct s2255_pipeinfo *pipe = &dev->pipe; - dprintk(4, "board init: %p", dev); + dprintk(dev, 4, "board init: %p", dev); memset(pipe, 0, sizeof(*pipe)); pipe->dev = dev; pipe->cur_transfer_size = S2255_USB_XFER_SIZE; @@ -2258,54 +2000,53 @@ static int s2255_board_init(struct s2255_dev *dev) pipe->transfer_buffer = kzalloc(pipe->max_transfer_size, GFP_KERNEL); if (pipe->transfer_buffer == NULL) { - dprintk(1, "out of memory!\n"); + dprintk(dev, 1, "out of memory!\n"); return -ENOMEM; } /* query the firmware */ fw_ver = s2255_get_fx2fw(dev); - printk(KERN_INFO "s2255: usb firmware version %d.%d\n", - (fw_ver >> 8) & 0xff, - fw_ver & 0xff); + pr_info("s2255: usb firmware version %d.%d\n", + (fw_ver >> 8) & 0xff, + fw_ver & 0xff); if (fw_ver < S2255_CUR_USB_FWVER) - printk(KERN_INFO "s2255: newer USB firmware available\n"); + pr_info("s2255: newer USB firmware available\n"); for (j = 0; j < MAX_CHANNELS; j++) { - struct s2255_channel *channel = &dev->channel[j]; - channel->b_acquire = 0; - channel->mode = mode_def; + struct s2255_vc *vc = &dev->vc[j]; + vc->mode = mode_def; if (dev->pid == 0x2257 && j > 1) - channel->mode.color |= (1 << 16); - channel->jpegqual = S2255_DEF_JPEG_QUAL; - channel->width = LINE_SZ_4CIFS_NTSC; - channel->height = NUM_LINES_4CIFS_NTSC * 2; - channel->std = V4L2_STD_NTSC_M; - channel->fmt = &formats[0]; - channel->mode.restart = 1; - channel->req_image_size = get_transfer_size(&mode_def); - channel->frame_count = 0; + vc->mode.color |= (1 << 16); + vc->jpegqual = S2255_DEF_JPEG_QUAL; + vc->width = LINE_SZ_4CIFS_NTSC; + vc->height = NUM_LINES_4CIFS_NTSC * 2; + vc->std = V4L2_STD_NTSC_M; + vc->fmt = &formats[0]; + vc->mode.restart = 1; + vc->req_image_size = get_transfer_size(&mode_def); + vc->frame_count = 0; /* create the system buffers */ - s2255_create_sys_buffers(channel); + s2255_create_sys_buffers(vc); } /* start read pipe */ s2255_start_readpipe(dev); - dprintk(1, "%s: success\n", __func__); + dprintk(dev, 1, "%s: success\n", __func__); return 0; } static int s2255_board_shutdown(struct s2255_dev *dev) { u32 i; - dprintk(1, "%s: dev: %p", __func__, dev); + dprintk(dev, 1, "%s: dev: %p", __func__, dev); for (i = 0; i < MAX_CHANNELS; i++) { - if (dev->channel[i].b_acquire) - s2255_stop_acquire(&dev->channel[i]); + if (vb2_is_streaming(&dev->vc[i].vb_vidq)) + s2255_stop_acquire(&dev->vc[i]); } s2255_stop_readpipe(dev); for (i = 0; i < MAX_CHANNELS; i++) - s2255_release_sys_buffers(&dev->channel[i]); + s2255_release_sys_buffers(&dev->vc[i]); /* release transfer buffer */ kfree(dev->pipe.transfer_buffer); return 0; @@ -2318,13 +2059,10 @@ static void read_pipe_completion(struct urb *purb) int status; int pipe; pipe_info = purb->context; - dprintk(100, "%s: urb:%p, status %d\n", __func__, purb, - purb->status); if (pipe_info == NULL) { dev_err(&purb->dev->dev, "no context!\n"); return; } - dev = pipe_info->dev; if (dev == NULL) { dev_err(&purb->dev->dev, "no context!\n"); @@ -2333,13 +2071,13 @@ static void read_pipe_completion(struct urb *purb) status = purb->status; /* if shutting down, do not resubmit, exit immediately */ if (status == -ESHUTDOWN) { - dprintk(2, "%s: err shutdown\n", __func__); + dprintk(dev, 2, "%s: err shutdown\n", __func__); pipe_info->err_count++; return; } if (pipe_info->state == 0) { - dprintk(2, "%s: exiting USB pipe", __func__); + dprintk(dev, 2, "%s: exiting USB pipe", __func__); return; } @@ -2347,7 +2085,7 @@ static void read_pipe_completion(struct urb *purb) s2255_read_video_callback(dev, pipe_info); else { pipe_info->err_count++; - dprintk(1, "%s: failed URB %d\n", __func__, status); + dprintk(dev, 1, "%s: failed URB %d\n", __func__, status); } pipe = usb_rcvbulkpipe(dev->udev, dev->read_endpoint); @@ -2359,11 +2097,10 @@ static void read_pipe_completion(struct urb *purb) read_pipe_completion, pipe_info); if (pipe_info->state != 0) { - if (usb_submit_urb(pipe_info->stream_urb, GFP_ATOMIC)) { + if (usb_submit_urb(pipe_info->stream_urb, GFP_ATOMIC)) dev_err(&dev->udev->dev, "error submitting urb\n"); - } } else { - dprintk(2, "%s :complete state 0\n", __func__); + dprintk(dev, 2, "%s :complete state 0\n", __func__); } return; } @@ -2374,7 +2111,7 @@ static int s2255_start_readpipe(struct s2255_dev *dev) int retval; struct s2255_pipeinfo *pipe_info = &dev->pipe; pipe = usb_rcvbulkpipe(dev->udev, dev->read_endpoint); - dprintk(2, "%s: IN %d\n", __func__, dev->read_endpoint); + dprintk(dev, 2, "%s: IN %d\n", __func__, dev->read_endpoint); pipe_info->state = 1; pipe_info->err_count = 0; pipe_info->stream_urb = usb_alloc_urb(0, GFP_KERNEL); @@ -2391,70 +2128,64 @@ static int s2255_start_readpipe(struct s2255_dev *dev) read_pipe_completion, pipe_info); retval = usb_submit_urb(pipe_info->stream_urb, GFP_KERNEL); if (retval) { - printk(KERN_ERR "s2255: start read pipe failed\n"); + pr_err("s2255: start read pipe failed\n"); return retval; } return 0; } /* starts acquisition process */ -static int s2255_start_acquire(struct s2255_channel *channel) +static int s2255_start_acquire(struct s2255_vc *vc) { - unsigned char *buffer; int res; unsigned long chn_rev; int j; - struct s2255_dev *dev = to_s2255_dev(channel->vdev.v4l2_dev); - chn_rev = G_chnmap[channel->idx]; - buffer = kzalloc(512, GFP_KERNEL); - if (buffer == NULL) { - dev_err(&dev->udev->dev, "out of mem\n"); - return -ENOMEM; - } - - channel->last_frame = -1; - channel->bad_payload = 0; - channel->cur_frame = 0; + struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); + __le32 *buffer = dev->cmdbuf; + + mutex_lock(&dev->cmdlock); + chn_rev = G_chnmap[vc->idx]; + vc->last_frame = -1; + vc->bad_payload = 0; + vc->cur_frame = 0; for (j = 0; j < SYS_FRAMES; j++) { - channel->buffer.frame[j].ulState = 0; - channel->buffer.frame[j].cur_size = 0; + vc->buffer.frame[j].ulState = 0; + vc->buffer.frame[j].cur_size = 0; } /* send the start command */ - *(__le32 *) buffer = IN_DATA_TOKEN; - *((__le32 *) buffer + 1) = (__le32) cpu_to_le32(chn_rev); - *((__le32 *) buffer + 2) = CMD_START; + buffer[0] = IN_DATA_TOKEN; + buffer[1] = (__le32) cpu_to_le32(chn_rev); + buffer[2] = CMD_START; res = s2255_write_config(dev->udev, (unsigned char *)buffer, 512); if (res != 0) dev_err(&dev->udev->dev, "CMD_START error\n"); - dprintk(2, "start acquire exit[%d] %d \n", channel->idx, res); - kfree(buffer); - return 0; + dprintk(dev, 2, "start acquire exit[%d] %d\n", vc->idx, res); + mutex_unlock(&dev->cmdlock); + return res; } -static int s2255_stop_acquire(struct s2255_channel *channel) +static int s2255_stop_acquire(struct s2255_vc *vc) { - unsigned char *buffer; int res; unsigned long chn_rev; - struct s2255_dev *dev = to_s2255_dev(channel->vdev.v4l2_dev); - chn_rev = G_chnmap[channel->idx]; - buffer = kzalloc(512, GFP_KERNEL); - if (buffer == NULL) { - dev_err(&dev->udev->dev, "out of mem\n"); - return -ENOMEM; - } + struct s2255_dev *dev = to_s2255_dev(vc->vdev.v4l2_dev); + __le32 *buffer = dev->cmdbuf; + + mutex_lock(&dev->cmdlock); + chn_rev = G_chnmap[vc->idx]; /* send the stop command */ - *(__le32 *) buffer = IN_DATA_TOKEN; - *((__le32 *) buffer + 1) = (__le32) cpu_to_le32(chn_rev); - *((__le32 *) buffer + 2) = CMD_STOP; + buffer[0] = IN_DATA_TOKEN; + buffer[1] = (__le32) cpu_to_le32(chn_rev); + buffer[2] = CMD_STOP; + res = s2255_write_config(dev->udev, (unsigned char *)buffer, 512); if (res != 0) dev_err(&dev->udev->dev, "CMD_STOP error\n"); - kfree(buffer); - channel->b_acquire = 0; - dprintk(4, "%s: chn %d, res %d\n", __func__, channel->idx, res); + + dprintk(dev, 4, "%s: chn %d, res %d\n", __func__, vc->idx, res); + mutex_unlock(&dev->cmdlock); return res; } @@ -2469,7 +2200,7 @@ static void s2255_stop_readpipe(struct s2255_dev *dev) usb_free_urb(pipe->stream_urb); pipe->stream_urb = NULL; } - dprintk(4, "%s", __func__); + dprintk(dev, 4, "%s", __func__); return; } @@ -2501,19 +2232,27 @@ static int s2255_probe(struct usb_interface *interface, int retval = -ENOMEM; __le32 *pdata; int fw_size; - dprintk(2, "%s\n", __func__); + /* allocate memory for our device state and initialize it to zero */ dev = kzalloc(sizeof(struct s2255_dev), GFP_KERNEL); if (dev == NULL) { s2255_dev_err(&interface->dev, "out of memory\n"); return -ENOMEM; } + + dev->cmdbuf = kzalloc(S2255_CMDBUF_SIZE, GFP_KERNEL); + if (dev->cmdbuf == NULL) { + s2255_dev_err(&interface->dev, "out of memory\n"); + return -ENOMEM; + } + atomic_set(&dev->num_channels, 0); dev->pid = le16_to_cpu(id->idProduct); dev->fw_data = kzalloc(sizeof(struct s2255_fw), GFP_KERNEL); if (!dev->fw_data) goto errorFWDATA1; mutex_init(&dev->lock); + mutex_init(&dev->cmdlock); /* grab usb_device and save it */ dev->udev = usb_get_dev(interface_to_usbdev(interface)); if (dev->udev == NULL) { @@ -2521,12 +2260,13 @@ static int s2255_probe(struct usb_interface *interface, retval = -ENODEV; goto errorUDEV; } - dprintk(1, "dev: %p, udev %p interface %p\n", dev, - dev->udev, interface); + dev_dbg(&interface->dev, "dev: %p, udev %p interface %p\n", + dev, dev->udev, interface); dev->interface = interface; /* set up the endpoint information */ iface_desc = interface->cur_altsetting; - dprintk(1, "num endpoints %d\n", iface_desc->desc.bNumEndpoints); + dev_dbg(&interface->dev, "num EP: %d\n", + iface_desc->desc.bNumEndpoints); for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) { endpoint = &iface_desc->endpoint[i].desc; if (!dev->read_endpoint && usb_endpoint_is_bulk_in(endpoint)) { @@ -2544,10 +2284,13 @@ static int s2255_probe(struct usb_interface *interface, dev->timer.data = (unsigned long)dev->fw_data; init_waitqueue_head(&dev->fw_data->wait_fw); for (i = 0; i < MAX_CHANNELS; i++) { - struct s2255_channel *channel = &dev->channel[i]; - dev->channel[i].idx = i; - init_waitqueue_head(&channel->wait_setmode); - init_waitqueue_head(&channel->wait_vidstatus); + struct s2255_vc *vc = &dev->vc[i]; + vc->idx = i; + vc->dev = dev; + init_waitqueue_head(&vc->wait_setmode); + init_waitqueue_head(&vc->wait_vidstatus); + spin_lock_init(&vc->qlock); + mutex_init(&vc->vb_lock); } dev->fw_data->fw_urb = usb_alloc_urb(0, GFP_KERNEL); @@ -2564,7 +2307,7 @@ static int s2255_probe(struct usb_interface *interface, /* load the first chunk */ if (request_firmware(&dev->fw_data->fw, FIRMWARE_FILE_NAME, &dev->udev->dev)) { - printk(KERN_ERR "sensoray 2255 failed to get firmware\n"); + dev_err(&interface->dev, "sensoray 2255 failed to get firmware\n"); goto errorREQFW; } /* check the firmware is valid */ @@ -2572,28 +2315,27 @@ static int s2255_probe(struct usb_interface *interface, pdata = (__le32 *) &dev->fw_data->fw->data[fw_size - 8]; if (*pdata != S2255_FW_MARKER) { - printk(KERN_INFO "Firmware invalid.\n"); + dev_err(&interface->dev, "Firmware invalid.\n"); retval = -ENODEV; goto errorFWMARKER; } else { /* make sure firmware is the latest */ __le32 *pRel; pRel = (__le32 *) &dev->fw_data->fw->data[fw_size - 4]; - printk(KERN_INFO "s2255 dsp fw version %x\n", le32_to_cpu(*pRel)); + pr_info("s2255 dsp fw version %x\n", le32_to_cpu(*pRel)); dev->dsp_fw_ver = le32_to_cpu(*pRel); if (dev->dsp_fw_ver < S2255_CUR_DSP_FWVER) - printk(KERN_INFO "s2255: f2255usb.bin out of date.\n"); + pr_info("s2255: f2255usb.bin out of date.\n"); if (dev->pid == 0x2257 && dev->dsp_fw_ver < S2255_MIN_DSP_COLORFILTER) - printk(KERN_WARNING "s2255: 2257 requires firmware %d" - " or above.\n", S2255_MIN_DSP_COLORFILTER); + pr_warn("2257 needs firmware %d or above.\n", + S2255_MIN_DSP_COLORFILTER); } usb_reset_device(dev->udev); /* load 2255 board specific */ retval = s2255_board_init(dev); if (retval) goto errorBOARDINIT; - spin_lock_init(&dev->slock); s2255_fwload_start(dev, 0); /* loads v4l specific */ retval = s2255_probe_v4l(dev); @@ -2617,8 +2359,9 @@ errorUDEV: kfree(dev->fw_data); mutex_destroy(&dev->lock); errorFWDATA1: + kfree(dev->cmdbuf); kfree(dev); - printk(KERN_WARNING "Sensoray 2255 driver load failed: 0x%x\n", retval); + pr_warn("Sensoray 2255 driver load failed: 0x%x\n", retval); return retval; } @@ -2635,15 +2378,15 @@ static void s2255_disconnect(struct usb_interface *interface) atomic_inc(&dev->num_channels); /* unregister each video device. */ for (i = 0; i < channels; i++) - video_unregister_device(&dev->channel[i].vdev); + video_unregister_device(&dev->vc[i].vdev); /* wake up any of our timers */ atomic_set(&dev->fw_data->fw_state, S2255_FW_DISCONNECTING); wake_up(&dev->fw_data->wait_fw); for (i = 0; i < MAX_CHANNELS; i++) { - dev->channel[i].setmode_ready = 1; - wake_up(&dev->channel[i].wait_setmode); - dev->channel[i].vidstatus_ready = 1; - wake_up(&dev->channel[i].wait_vidstatus); + dev->vc[i].setmode_ready = 1; + wake_up(&dev->vc[i].wait_setmode); + dev->vc[i].vidstatus_ready = 1; + wake_up(&dev->vc[i].wait_vidstatus); } if (atomic_dec_and_test(&dev->num_channels)) s2255_destroy(dev); diff --git a/drivers/media/usb/siano/smsusb.c b/drivers/media/usb/siano/smsusb.c index 05bd91a..1836a41 100644 --- a/drivers/media/usb/siano/smsusb.c +++ b/drivers/media/usb/siano/smsusb.c @@ -653,6 +653,8 @@ static const struct usb_device_id smsusb_id_table[] = { .driver_info = SMS1XXX_BOARD_ZTE_DVB_DATA_CARD }, { USB_DEVICE(0x19D2, 0x0078), .driver_info = SMS1XXX_BOARD_ONDA_MDTV_DATA_CARD }, + { USB_DEVICE(0x3275, 0x0080), + .driver_info = SMS1XXX_BOARD_SIANO_RIO }, { } /* Terminating entry */ }; diff --git a/drivers/media/usb/stk1160/stk1160-v4l.c b/drivers/media/usb/stk1160/stk1160-v4l.c index c45c988..37bc00f 100644 --- a/drivers/media/usb/stk1160/stk1160-v4l.c +++ b/drivers/media/usb/stk1160/stk1160-v4l.c @@ -641,7 +641,7 @@ int stk1160_vb2_setup(struct stk1160 *dev) q->buf_struct_size = sizeof(struct stk1160_buffer); q->ops = &stk1160_video_qops; q->mem_ops = &vb2_vmalloc_memops; - q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; rc = vb2_queue_init(q); if (rc < 0) diff --git a/drivers/media/usb/tm6000/tm6000-alsa.c b/drivers/media/usb/tm6000/tm6000-alsa.c index 3239cd6..74e5697 100644 --- a/drivers/media/usb/tm6000/tm6000-alsa.c +++ b/drivers/media/usb/tm6000/tm6000-alsa.c @@ -1,7 +1,7 @@ /* * * Support for audio capture for tm5600/6000/6010 - * (c) 2007-2008 Mauro Carvalho Chehab <mchehab@redhat.com> + * (c) 2007-2008 Mauro Carvalho Chehab * * Based on cx88-alsa.c * @@ -56,7 +56,7 @@ MODULE_PARM_DESC(index, "Index value for tm6000x capture interface(s)."); ****************************************************************************/ MODULE_DESCRIPTION("ALSA driver module for tm5600/tm6000/tm6010 based TV cards"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_LICENSE("GPL"); MODULE_SUPPORTED_DEVICE("{{Trident,tm5600}," "{{Trident,tm6000}," diff --git a/drivers/media/usb/tm6000/tm6000-dvb.c b/drivers/media/usb/tm6000/tm6000-dvb.c index 9fc1e94..095f5db 100644 --- a/drivers/media/usb/tm6000/tm6000-dvb.c +++ b/drivers/media/usb/tm6000/tm6000-dvb.c @@ -32,7 +32,7 @@ #include "xc5000.h" MODULE_DESCRIPTION("DVB driver extension module for tm5600/6000/6010 based TV cards"); -MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); MODULE_LICENSE("GPL"); MODULE_SUPPORTED_DEVICE("{{Trident, tm5600}," diff --git a/drivers/media/usb/tm6000/tm6000-input.c b/drivers/media/usb/tm6000/tm6000-input.c index 8a6bbf1..d1af543 100644 --- a/drivers/media/usb/tm6000/tm6000-input.c +++ b/drivers/media/usb/tm6000/tm6000-input.c @@ -422,7 +422,7 @@ int tm6000_ir_init(struct tm6000_core *dev) ir->rc = rc; /* input setup */ - rc->allowed_protos = RC_BIT_RC5 | RC_BIT_NEC; + rc_set_allowed_protocols(rc, RC_BIT_RC5 | RC_BIT_NEC); /* Neded, in order to support NEC remotes with 24 or 32 bits */ rc->scanmask = 0xffff; rc->priv = ir; diff --git a/drivers/media/usb/tm6000/tm6000-stds.c b/drivers/media/usb/tm6000/tm6000-stds.c index 5e28d6a..93a4b24 100644 --- a/drivers/media/usb/tm6000/tm6000-stds.c +++ b/drivers/media/usb/tm6000/tm6000-stds.c @@ -1,7 +1,7 @@ /* * tm6000-stds.c - driver for TM5600/TM6000/TM6010 USB video capture devices * - * Copyright (C) 2007 Mauro Carvalho Chehab <mchehab@redhat.com> + * Copyright (C) 2007 Mauro Carvalho Chehab * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/media/usb/usbtv/Makefile b/drivers/media/usb/usbtv/Makefile index 28b872f..775316a 100644 --- a/drivers/media/usb/usbtv/Makefile +++ b/drivers/media/usb/usbtv/Makefile @@ -1 +1,4 @@ +usbtv-y := usbtv-core.o \ + usbtv-video.o + obj-$(CONFIG_VIDEO_USBTV) += usbtv.o diff --git a/drivers/media/usb/usbtv/usbtv-core.c b/drivers/media/usb/usbtv/usbtv-core.c new file mode 100644 index 0000000..2f87ddf --- /dev/null +++ b/drivers/media/usb/usbtv/usbtv-core.c @@ -0,0 +1,134 @@ +/* + * Fushicai USBTV007 Video Grabber Driver + * + * Product web site: + * http://www.fushicai.com/products_detail/&productId=d05449ee-b690-42f9-a661-aa7353894bed.html + * + * Following LWN articles were very useful in construction of this driver: + * Video4Linux2 API series: http://lwn.net/Articles/203924/ + * videobuf2 API explanation: http://lwn.net/Articles/447435/ + * Thanks go to Jonathan Corbet for providing this quality documentation. + * He is awesome. + * + * Copyright (c) 2013 Lubomir Rintel + * All rights reserved. + * No physical hardware was harmed running Windows during the + * reverse-engineering activity + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL"). + */ + +#include "usbtv.h" + +int usbtv_set_regs(struct usbtv *usbtv, const u16 regs[][2], int size) +{ + int ret; + int pipe = usb_rcvctrlpipe(usbtv->udev, 0); + int i; + + for (i = 0; i < size; i++) { + u16 index = regs[i][0]; + u16 value = regs[i][1]; + + ret = usb_control_msg(usbtv->udev, pipe, USBTV_REQUEST_REG, + USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + value, index, NULL, 0, 0); + if (ret < 0) + return ret; + } + + return 0; +} + +static int usbtv_probe(struct usb_interface *intf, + const struct usb_device_id *id) +{ + int ret; + int size; + struct device *dev = &intf->dev; + struct usbtv *usbtv; + + /* Checks that the device is what we think it is. */ + if (intf->num_altsetting != 2) + return -ENODEV; + if (intf->altsetting[1].desc.bNumEndpoints != 4) + return -ENODEV; + + /* Packet size is split into 11 bits of base size and count of + * extra multiplies of it.*/ + size = usb_endpoint_maxp(&intf->altsetting[1].endpoint[0].desc); + size = (size & 0x07ff) * (((size & 0x1800) >> 11) + 1); + + /* Device structure */ + usbtv = kzalloc(sizeof(struct usbtv), GFP_KERNEL); + if (usbtv == NULL) + return -ENOMEM; + usbtv->dev = dev; + usbtv->udev = usb_get_dev(interface_to_usbdev(intf)); + + usbtv->iso_size = size; + + usb_set_intfdata(intf, usbtv); + + ret = usbtv_video_init(usbtv); + if (ret < 0) + goto usbtv_video_fail; + + /* for simplicity we exploit the v4l2_device reference counting */ + v4l2_device_get(&usbtv->v4l2_dev); + + dev_info(dev, "Fushicai USBTV007 Video Grabber\n"); + return 0; + +usbtv_video_fail: + kfree(usbtv); + + return ret; +} + +static void usbtv_disconnect(struct usb_interface *intf) +{ + struct usbtv *usbtv = usb_get_intfdata(intf); + usb_set_intfdata(intf, NULL); + + if (!usbtv) + return; + + usbtv_video_free(usbtv); + + usb_put_dev(usbtv->udev); + usbtv->udev = NULL; + + /* the usbtv structure will be deallocated when v4l2 will be + done using it */ + v4l2_device_put(&usbtv->v4l2_dev); +} + +static struct usb_device_id usbtv_id_table[] = { + { USB_DEVICE(0x1b71, 0x3002) }, + {} +}; +MODULE_DEVICE_TABLE(usb, usbtv_id_table); + +MODULE_AUTHOR("Lubomir Rintel"); +MODULE_DESCRIPTION("Fushicai USBTV007 Video Grabber Driver"); +MODULE_LICENSE("Dual BSD/GPL"); + +static struct usb_driver usbtv_usb_driver = { + .name = "usbtv", + .id_table = usbtv_id_table, + .probe = usbtv_probe, + .disconnect = usbtv_disconnect, +}; + +module_usb_driver(usbtv_usb_driver); diff --git a/drivers/media/usb/usbtv/usbtv.c b/drivers/media/usb/usbtv/usbtv-video.c index 6222a4a..20365bd 100644 --- a/drivers/media/usb/usbtv/usbtv.c +++ b/drivers/media/usb/usbtv/usbtv-video.c @@ -28,45 +28,10 @@ * GNU General Public License ("GPL"). */ -#include <linux/init.h> -#include <linux/list.h> -#include <linux/module.h> -#include <linux/slab.h> -#include <linux/usb.h> -#include <linux/videodev2.h> - -#include <media/v4l2-device.h> #include <media/v4l2-ioctl.h> #include <media/videobuf2-core.h> -#include <media/videobuf2-vmalloc.h> - -/* Hardware. */ -#define USBTV_VIDEO_ENDP 0x81 -#define USBTV_BASE 0xc000 -#define USBTV_REQUEST_REG 12 - -/* Number of concurrent isochronous urbs submitted. - * Higher numbers was seen to overly saturate the USB bus. */ -#define USBTV_ISOC_TRANSFERS 16 -#define USBTV_ISOC_PACKETS 8 - -#define USBTV_CHUNK_SIZE 256 -#define USBTV_CHUNK 240 - -/* Chunk header. */ -#define USBTV_MAGIC_OK(chunk) ((be32_to_cpu(chunk[0]) & 0xff000000) \ - == 0x88000000) -#define USBTV_FRAME_ID(chunk) ((be32_to_cpu(chunk[0]) & 0x00ff0000) >> 16) -#define USBTV_ODD(chunk) ((be32_to_cpu(chunk[0]) & 0x0000f000) >> 15) -#define USBTV_CHUNK_NO(chunk) (be32_to_cpu(chunk[0]) & 0x00000fff) - -#define USBTV_TV_STD (V4L2_STD_525_60 | V4L2_STD_PAL) - -/* parameters for supported TV norms */ -struct usbtv_norm_params { - v4l2_std_id norm; - int cap_width, cap_height; -}; + +#include "usbtv.h" static struct usbtv_norm_params norm_params[] = { { @@ -81,43 +46,6 @@ static struct usbtv_norm_params norm_params[] = { } }; -/* A single videobuf2 frame buffer. */ -struct usbtv_buf { - struct vb2_buffer vb; - struct list_head list; -}; - -/* Per-device structure. */ -struct usbtv { - struct device *dev; - struct usb_device *udev; - struct v4l2_device v4l2_dev; - struct video_device vdev; - struct vb2_queue vb2q; - struct mutex v4l2_lock; - struct mutex vb2q_lock; - - /* List of videobuf2 buffers protected by a lock. */ - spinlock_t buflock; - struct list_head bufs; - - /* Number of currently processed frame, useful find - * out when a new one begins. */ - u32 frame_id; - int chunks_done; - - enum { - USBTV_COMPOSITE_INPUT, - USBTV_SVIDEO_INPUT, - } input; - v4l2_std_id norm; - int width, height; - int n_chunks; - int iso_size; - unsigned int sequence; - struct urb *isoc_urbs[USBTV_ISOC_TRANSFERS]; -}; - static int usbtv_configure_for_norm(struct usbtv *usbtv, v4l2_std_id norm) { int i, ret = 0; @@ -142,26 +70,6 @@ static int usbtv_configure_for_norm(struct usbtv *usbtv, v4l2_std_id norm) return ret; } -static int usbtv_set_regs(struct usbtv *usbtv, const u16 regs[][2], int size) -{ - int ret; - int pipe = usb_rcvctrlpipe(usbtv->udev, 0); - int i; - - for (i = 0; i < size; i++) { - u16 index = regs[i][0]; - u16 value = regs[i][1]; - - ret = usb_control_msg(usbtv->udev, pipe, USBTV_REQUEST_REG, - USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, - value, index, NULL, 0, 0); - if (ret < 0) - return ret; - } - - return 0; -} - static int usbtv_select_input(struct usbtv *usbtv, int input) { int ret; @@ -560,12 +468,6 @@ start_fail: return ret; } -struct usb_device_id usbtv_id_table[] = { - { USB_DEVICE(0x1b71, 0x3002) }, - {} -}; -MODULE_DEVICE_TABLE(usb, usbtv_id_table); - static int usbtv_querycap(struct file *file, void *priv, struct v4l2_capability *cap) { @@ -660,7 +562,7 @@ static int usbtv_s_input(struct file *file, void *priv, unsigned int i) return usbtv_select_input(usbtv, i); } -struct v4l2_ioctl_ops usbtv_ioctl_ops = { +static struct v4l2_ioctl_ops usbtv_ioctl_ops = { .vidioc_querycap = usbtv_querycap, .vidioc_enum_input = usbtv_enum_input, .vidioc_enum_fmt_vid_cap = usbtv_enum_fmt_vid_cap, @@ -682,7 +584,7 @@ struct v4l2_ioctl_ops usbtv_ioctl_ops = { .vidioc_streamoff = vb2_ioctl_streamoff, }; -struct v4l2_file_operations usbtv_fops = { +static struct v4l2_file_operations usbtv_fops = { .owner = THIS_MODULE, .unlocked_ioctl = video_ioctl2, .mmap = vb2_fop_mmap, @@ -743,7 +645,7 @@ static int usbtv_stop_streaming(struct vb2_queue *vq) return 0; } -struct vb2_ops usbtv_vb2_ops = { +static struct vb2_ops usbtv_vb2_ops = { .queue_setup = usbtv_queue_setup, .buf_queue = usbtv_buf_queue, .start_streaming = usbtv_start_streaming, @@ -759,33 +661,9 @@ static void usbtv_release(struct v4l2_device *v4l2_dev) kfree(usbtv); } -static int usbtv_probe(struct usb_interface *intf, - const struct usb_device_id *id) +int usbtv_video_init(struct usbtv *usbtv) { int ret; - int size; - struct device *dev = &intf->dev; - struct usbtv *usbtv; - - /* Checks that the device is what we think it is. */ - if (intf->num_altsetting != 2) - return -ENODEV; - if (intf->altsetting[1].desc.bNumEndpoints != 4) - return -ENODEV; - - /* Packet size is split into 11 bits of base size and count of - * extra multiplies of it.*/ - size = usb_endpoint_maxp(&intf->altsetting[1].endpoint[0].desc); - size = (size & 0x07ff) * (((size & 0x1800) >> 11) + 1); - - /* Device structure */ - usbtv = kzalloc(sizeof(struct usbtv), GFP_KERNEL); - if (usbtv == NULL) - return -ENOMEM; - usbtv->dev = dev; - usbtv->udev = usb_get_dev(interface_to_usbdev(intf)); - - usbtv->iso_size = size; (void)usbtv_configure_for_norm(usbtv, V4L2_STD_525_60); @@ -801,24 +679,22 @@ static int usbtv_probe(struct usb_interface *intf, usbtv->vb2q.buf_struct_size = sizeof(struct usbtv_buf); usbtv->vb2q.ops = &usbtv_vb2_ops; usbtv->vb2q.mem_ops = &vb2_vmalloc_memops; - usbtv->vb2q.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + usbtv->vb2q.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; usbtv->vb2q.lock = &usbtv->vb2q_lock; ret = vb2_queue_init(&usbtv->vb2q); if (ret < 0) { - dev_warn(dev, "Could not initialize videobuf2 queue\n"); - goto usbtv_fail; + dev_warn(usbtv->dev, "Could not initialize videobuf2 queue\n"); + return ret; } /* v4l2 structure */ usbtv->v4l2_dev.release = usbtv_release; - ret = v4l2_device_register(dev, &usbtv->v4l2_dev); + ret = v4l2_device_register(usbtv->dev, &usbtv->v4l2_dev); if (ret < 0) { - dev_warn(dev, "Could not register v4l2 device\n"); + dev_warn(usbtv->dev, "Could not register v4l2 device\n"); goto v4l2_fail; } - usb_set_intfdata(intf, usbtv); - /* Video structure */ strlcpy(usbtv->vdev.name, "usbtv", sizeof(usbtv->vdev.name)); usbtv->vdev.v4l2_dev = &usbtv->v4l2_dev; @@ -832,52 +708,31 @@ static int usbtv_probe(struct usb_interface *intf, video_set_drvdata(&usbtv->vdev, usbtv); ret = video_register_device(&usbtv->vdev, VFL_TYPE_GRABBER, -1); if (ret < 0) { - dev_warn(dev, "Could not register video device\n"); + dev_warn(usbtv->dev, "Could not register video device\n"); goto vdev_fail; } - dev_info(dev, "Fushicai USBTV007 Video Grabber\n"); return 0; vdev_fail: v4l2_device_unregister(&usbtv->v4l2_dev); v4l2_fail: vb2_queue_release(&usbtv->vb2q); -usbtv_fail: - kfree(usbtv); return ret; } -static void usbtv_disconnect(struct usb_interface *intf) +void usbtv_video_free(struct usbtv *usbtv) { - struct usbtv *usbtv = usb_get_intfdata(intf); - mutex_lock(&usbtv->vb2q_lock); mutex_lock(&usbtv->v4l2_lock); usbtv_stop(usbtv); - usb_set_intfdata(intf, NULL); video_unregister_device(&usbtv->vdev); v4l2_device_disconnect(&usbtv->v4l2_dev); - usb_put_dev(usbtv->udev); - usbtv->udev = NULL; mutex_unlock(&usbtv->v4l2_lock); mutex_unlock(&usbtv->vb2q_lock); v4l2_device_put(&usbtv->v4l2_dev); } - -MODULE_AUTHOR("Lubomir Rintel"); -MODULE_DESCRIPTION("Fushicai USBTV007 Video Grabber Driver"); -MODULE_LICENSE("Dual BSD/GPL"); - -struct usb_driver usbtv_usb_driver = { - .name = "usbtv", - .id_table = usbtv_id_table, - .probe = usbtv_probe, - .disconnect = usbtv_disconnect, -}; - -module_usb_driver(usbtv_usb_driver); diff --git a/drivers/media/usb/usbtv/usbtv.h b/drivers/media/usb/usbtv/usbtv.h new file mode 100644 index 0000000..cb1d388 --- /dev/null +++ b/drivers/media/usb/usbtv/usbtv.h @@ -0,0 +1,99 @@ +/* + * Fushicai USBTV007 Video Grabber Driver + * + * Copyright (c) 2013 Lubomir Rintel + * All rights reserved. + * No physical hardware was harmed running Windows during the + * reverse-engineering activity + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL"). + */ + +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/usb.h> + +#include <media/v4l2-device.h> +#include <media/videobuf2-vmalloc.h> + +/* Hardware. */ +#define USBTV_VIDEO_ENDP 0x81 +#define USBTV_BASE 0xc000 +#define USBTV_REQUEST_REG 12 + +/* Number of concurrent isochronous urbs submitted. + * Higher numbers was seen to overly saturate the USB bus. */ +#define USBTV_ISOC_TRANSFERS 16 +#define USBTV_ISOC_PACKETS 8 + +#define USBTV_CHUNK_SIZE 256 +#define USBTV_CHUNK 240 + +/* Chunk header. */ +#define USBTV_MAGIC_OK(chunk) ((be32_to_cpu(chunk[0]) & 0xff000000) \ + == 0x88000000) +#define USBTV_FRAME_ID(chunk) ((be32_to_cpu(chunk[0]) & 0x00ff0000) >> 16) +#define USBTV_ODD(chunk) ((be32_to_cpu(chunk[0]) & 0x0000f000) >> 15) +#define USBTV_CHUNK_NO(chunk) (be32_to_cpu(chunk[0]) & 0x00000fff) + +#define USBTV_TV_STD (V4L2_STD_525_60 | V4L2_STD_PAL) + +/* parameters for supported TV norms */ +struct usbtv_norm_params { + v4l2_std_id norm; + int cap_width, cap_height; +}; + +/* A single videobuf2 frame buffer. */ +struct usbtv_buf { + struct vb2_buffer vb; + struct list_head list; +}; + +/* Per-device structure. */ +struct usbtv { + struct device *dev; + struct usb_device *udev; + + /* video */ + struct v4l2_device v4l2_dev; + struct video_device vdev; + struct vb2_queue vb2q; + struct mutex v4l2_lock; + struct mutex vb2q_lock; + + /* List of videobuf2 buffers protected by a lock. */ + spinlock_t buflock; + struct list_head bufs; + + /* Number of currently processed frame, useful find + * out when a new one begins. */ + u32 frame_id; + int chunks_done; + + enum { + USBTV_COMPOSITE_INPUT, + USBTV_SVIDEO_INPUT, + } input; + v4l2_std_id norm; + int width, height; + int n_chunks; + int iso_size; + unsigned int sequence; + struct urb *isoc_urbs[USBTV_ISOC_TRANSFERS]; +}; + +int usbtv_set_regs(struct usbtv *usbtv, const u16 regs[][2], int size); + +int usbtv_video_init(struct usbtv *usbtv); +void usbtv_video_free(struct usbtv *usbtv); diff --git a/drivers/media/usb/usbvision/usbvision.h b/drivers/media/usb/usbvision/usbvision.h index 8a25876..a0c73cf 100644 --- a/drivers/media/usb/usbvision/usbvision.h +++ b/drivers/media/usb/usbvision/usbvision.h @@ -203,14 +203,6 @@ enum { mr = LIMIT_RGB(mm_r); \ } -/* Debugging aid */ -#define USBVISION_SAY_AND_WAIT(what) { \ - wait_queue_head_t wq; \ - init_waitqueue_head(&wq); \ - printk(KERN_INFO "Say: %s\n", what); \ - interruptible_sleep_on_timeout(&wq, HZ * 3); \ -} - /* * This macro checks if usbvision is still operational. The 'usbvision' * pointer must be valid, usbvision->dev must be valid, we are not diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c index c3bb250..ad47c5c 100644 --- a/drivers/media/usb/uvc/uvc_driver.c +++ b/drivers/media/usb/uvc/uvc_driver.c @@ -108,11 +108,31 @@ static struct uvc_format_desc uvc_fmts[] = { .fcc = V4L2_PIX_FMT_Y16, }, { - .name = "RGB Bayer", + .name = "BGGR Bayer (BY8 )", .guid = UVC_GUID_FORMAT_BY8, .fcc = V4L2_PIX_FMT_SBGGR8, }, { + .name = "BGGR Bayer (BA81)", + .guid = UVC_GUID_FORMAT_BA81, + .fcc = V4L2_PIX_FMT_SBGGR8, + }, + { + .name = "GBRG Bayer (GBRG)", + .guid = UVC_GUID_FORMAT_GBRG, + .fcc = V4L2_PIX_FMT_SGBRG8, + }, + { + .name = "GRBG Bayer (GRBG)", + .guid = UVC_GUID_FORMAT_GRBG, + .fcc = V4L2_PIX_FMT_SGRBG8, + }, + { + .name = "RGGB Bayer (RGGB)", + .guid = UVC_GUID_FORMAT_RGGB, + .fcc = V4L2_PIX_FMT_SRGGB8, + }, + { .name = "RGB565", .guid = UVC_GUID_FORMAT_RGBP, .fcc = V4L2_PIX_FMT_RGB565, @@ -925,7 +945,7 @@ static int uvc_parse_standard_control(struct uvc_device *dev, case UVC_VC_HEADER: n = buflen >= 12 ? buffer[11] : 0; - if (buflen < 12 || buflen < 12 + n) { + if (buflen < 12 + n) { uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " "interface %d HEADER error\n", udev->devnum, alts->desc.bInterfaceNumber); diff --git a/drivers/media/usb/uvc/uvc_queue.c b/drivers/media/usb/uvc/uvc_queue.c index cd962be..6e92d20 100644 --- a/drivers/media/usb/uvc/uvc_queue.c +++ b/drivers/media/usb/uvc/uvc_queue.c @@ -48,12 +48,14 @@ static int uvc_queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, struct uvc_streaming *stream = container_of(queue, struct uvc_streaming, queue); - if (*nbuffers > UVC_MAX_VIDEO_BUFFERS) - *nbuffers = UVC_MAX_VIDEO_BUFFERS; + /* Make sure the image size is large enough. */ + if (fmt && fmt->fmt.pix.sizeimage < stream->ctrl.dwMaxVideoFrameSize) + return -EINVAL; *nplanes = 1; - sizes[0] = stream->ctrl.dwMaxVideoFrameSize; + sizes[0] = fmt ? fmt->fmt.pix.sizeimage + : stream->ctrl.dwMaxVideoFrameSize; return 0; } @@ -104,15 +106,15 @@ static void uvc_buffer_queue(struct vb2_buffer *vb) spin_unlock_irqrestore(&queue->irqlock, flags); } -static int uvc_buffer_finish(struct vb2_buffer *vb) +static void uvc_buffer_finish(struct vb2_buffer *vb) { struct uvc_video_queue *queue = vb2_get_drv_priv(vb->vb2_queue); struct uvc_streaming *stream = container_of(queue, struct uvc_streaming, queue); struct uvc_buffer *buf = container_of(vb, struct uvc_buffer, buf); - uvc_video_clock_update(stream, &vb->v4l2_buf, buf); - return 0; + if (vb->state == VB2_BUF_STATE_DONE) + uvc_video_clock_update(stream, &vb->v4l2_buf, buf); } static void uvc_wait_prepare(struct vb2_queue *vq) @@ -149,7 +151,8 @@ int uvc_queue_init(struct uvc_video_queue *queue, enum v4l2_buf_type type, queue->queue.buf_struct_size = sizeof(struct uvc_buffer); queue->queue.ops = &uvc_queue_qops; queue->queue.mem_ops = &vb2_vmalloc_memops; - queue->queue.timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + queue->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC + | V4L2_BUF_FLAG_TSTAMP_SRC_SOE; ret = vb2_queue_init(&queue->queue); if (ret) return ret; @@ -196,6 +199,18 @@ int uvc_query_buffer(struct uvc_video_queue *queue, struct v4l2_buffer *buf) return ret; } +int uvc_create_buffers(struct uvc_video_queue *queue, + struct v4l2_create_buffers *cb) +{ + int ret; + + mutex_lock(&queue->mutex); + ret = vb2_create_bufs(&queue->queue, cb); + mutex_unlock(&queue->mutex); + + return ret; +} + int uvc_queue_buffer(struct uvc_video_queue *queue, struct v4l2_buffer *buf) { int ret; diff --git a/drivers/media/usb/uvc/uvc_v4l2.c b/drivers/media/usb/uvc/uvc_v4l2.c index 3afff92..378ae02 100644 --- a/drivers/media/usb/uvc/uvc_v4l2.c +++ b/drivers/media/usb/uvc/uvc_v4l2.c @@ -1000,6 +1000,17 @@ static long uvc_v4l2_do_ioctl(struct file *file, unsigned int cmd, void *arg) return uvc_query_buffer(&stream->queue, buf); } + case VIDIOC_CREATE_BUFS: + { + struct v4l2_create_buffers *cb = arg; + + ret = uvc_acquire_privileges(handle); + if (ret < 0) + return ret; + + return uvc_create_buffers(&stream->queue, cb); + } + case VIDIOC_QBUF: if (!uvc_has_privileges(handle)) return -EBUSY; diff --git a/drivers/media/usb/uvc/uvc_video.c b/drivers/media/usb/uvc/uvc_video.c index 898c208..8d52baf 100644 --- a/drivers/media/usb/uvc/uvc_video.c +++ b/drivers/media/usb/uvc/uvc_video.c @@ -1453,6 +1453,9 @@ static unsigned int uvc_endpoint_max_bpi(struct usb_device *dev, case USB_SPEED_HIGH: psize = usb_endpoint_maxp(&ep->desc); return (psize & 0x07ff) * (1 + ((psize >> 11) & 3)); + case USB_SPEED_WIRELESS: + psize = usb_endpoint_maxp(&ep->desc); + return psize; default: psize = usb_endpoint_maxp(&ep->desc); return psize & 0x07ff; @@ -1847,7 +1850,25 @@ int uvc_video_enable(struct uvc_streaming *stream, int enable) if (!enable) { uvc_uninit_video(stream, 1); - usb_set_interface(stream->dev->udev, stream->intfnum, 0); + if (stream->intf->num_altsetting > 1) { + usb_set_interface(stream->dev->udev, + stream->intfnum, 0); + } else { + /* UVC doesn't specify how to inform a bulk-based device + * when the video stream is stopped. Windows sends a + * CLEAR_FEATURE(HALT) request to the video streaming + * bulk endpoint, mimic the same behaviour. + */ + unsigned int epnum = stream->header.bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK; + unsigned int dir = stream->header.bEndpointAddress + & USB_ENDPOINT_DIR_MASK; + unsigned int pipe; + + pipe = usb_sndbulkpipe(stream->dev->udev, epnum) | dir; + usb_clear_halt(stream->dev->udev, pipe); + } + uvc_queue_enable(&stream->queue, 0); uvc_video_clock_cleanup(stream); return 0; diff --git a/drivers/media/usb/uvc/uvcvideo.h b/drivers/media/usb/uvc/uvcvideo.h index 9e35982..b1f69a6 100644 --- a/drivers/media/usb/uvc/uvcvideo.h +++ b/drivers/media/usb/uvc/uvcvideo.h @@ -94,6 +94,18 @@ #define UVC_GUID_FORMAT_BY8 \ { 'B', 'Y', '8', ' ', 0x00, 0x00, 0x10, 0x00, \ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} +#define UVC_GUID_FORMAT_BA81 \ + { 'B', 'A', '8', '1', 0x00, 0x00, 0x10, 0x00, \ + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} +#define UVC_GUID_FORMAT_GBRG \ + { 'G', 'B', 'R', 'G', 0x00, 0x00, 0x10, 0x00, \ + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} +#define UVC_GUID_FORMAT_GRBG \ + { 'G', 'R', 'B', 'G', 0x00, 0x00, 0x10, 0x00, \ + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} +#define UVC_GUID_FORMAT_RGGB \ + { 'R', 'G', 'G', 'B', 0x00, 0x00, 0x10, 0x00, \ + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} #define UVC_GUID_FORMAT_RGBP \ { 'R', 'G', 'B', 'P', 0x00, 0x00, 0x10, 0x00, \ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} @@ -115,8 +127,6 @@ #define UVC_URBS 5 /* Maximum number of packets per URB. */ #define UVC_MAX_PACKETS 32 -/* Maximum number of video buffers. */ -#define UVC_MAX_VIDEO_BUFFERS 32 /* Maximum status buffer size in bytes of interrupt URB. */ #define UVC_MAX_STATUS_SIZE 16 @@ -616,6 +626,8 @@ extern int uvc_alloc_buffers(struct uvc_video_queue *queue, extern void uvc_free_buffers(struct uvc_video_queue *queue); extern int uvc_query_buffer(struct uvc_video_queue *queue, struct v4l2_buffer *v4l2_buf); +extern int uvc_create_buffers(struct uvc_video_queue *queue, + struct v4l2_create_buffers *v4l2_cb); extern int uvc_queue_buffer(struct uvc_video_queue *queue, struct v4l2_buffer *v4l2_buf); extern int uvc_dequeue_buffer(struct uvc_video_queue *queue, diff --git a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c index 6191968..04b2daf 100644 --- a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c +++ b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c @@ -740,7 +740,7 @@ static int put_v4l2_event32(struct v4l2_event *kp, struct v4l2_event32 __user *u return 0; } -struct v4l2_subdev_edid32 { +struct v4l2_edid32 { __u32 pad; __u32 start_block; __u32 blocks; @@ -748,11 +748,11 @@ struct v4l2_subdev_edid32 { compat_caddr_t edid; }; -static int get_v4l2_subdev_edid32(struct v4l2_subdev_edid *kp, struct v4l2_subdev_edid32 __user *up) +static int get_v4l2_edid32(struct v4l2_edid *kp, struct v4l2_edid32 __user *up) { u32 tmp; - if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_subdev_edid32)) || + if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_edid32)) || get_user(kp->pad, &up->pad) || get_user(kp->start_block, &up->start_block) || get_user(kp->blocks, &up->blocks) || @@ -763,11 +763,11 @@ static int get_v4l2_subdev_edid32(struct v4l2_subdev_edid *kp, struct v4l2_subde return 0; } -static int put_v4l2_subdev_edid32(struct v4l2_subdev_edid *kp, struct v4l2_subdev_edid32 __user *up) +static int put_v4l2_edid32(struct v4l2_edid *kp, struct v4l2_edid32 __user *up) { u32 tmp = (u32)((unsigned long)kp->edid); - if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_subdev_edid32)) || + if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_edid32)) || put_user(kp->pad, &up->pad) || put_user(kp->start_block, &up->start_block) || put_user(kp->blocks, &up->blocks) || @@ -787,8 +787,8 @@ static int put_v4l2_subdev_edid32(struct v4l2_subdev_edid *kp, struct v4l2_subde #define VIDIOC_DQBUF32 _IOWR('V', 17, struct v4l2_buffer32) #define VIDIOC_ENUMSTD32 _IOWR('V', 25, struct v4l2_standard32) #define VIDIOC_ENUMINPUT32 _IOWR('V', 26, struct v4l2_input32) -#define VIDIOC_SUBDEV_G_EDID32 _IOWR('V', 63, struct v4l2_subdev_edid32) -#define VIDIOC_SUBDEV_S_EDID32 _IOWR('V', 64, struct v4l2_subdev_edid32) +#define VIDIOC_G_EDID32 _IOWR('V', 40, struct v4l2_edid32) +#define VIDIOC_S_EDID32 _IOWR('V', 41, struct v4l2_edid32) #define VIDIOC_TRY_FMT32 _IOWR('V', 64, struct v4l2_format32) #define VIDIOC_G_EXT_CTRLS32 _IOWR('V', 71, struct v4l2_ext_controls32) #define VIDIOC_S_EXT_CTRLS32 _IOWR('V', 72, struct v4l2_ext_controls32) @@ -816,7 +816,7 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar struct v4l2_ext_controls v2ecs; struct v4l2_event v2ev; struct v4l2_create_buffers v2crt; - struct v4l2_subdev_edid v2edid; + struct v4l2_edid v2edid; unsigned long vx; int vi; } karg; @@ -849,8 +849,8 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar case VIDIOC_S_OUTPUT32: cmd = VIDIOC_S_OUTPUT; break; case VIDIOC_CREATE_BUFS32: cmd = VIDIOC_CREATE_BUFS; break; case VIDIOC_PREPARE_BUF32: cmd = VIDIOC_PREPARE_BUF; break; - case VIDIOC_SUBDEV_G_EDID32: cmd = VIDIOC_SUBDEV_G_EDID; break; - case VIDIOC_SUBDEV_S_EDID32: cmd = VIDIOC_SUBDEV_S_EDID; break; + case VIDIOC_G_EDID32: cmd = VIDIOC_G_EDID; break; + case VIDIOC_S_EDID32: cmd = VIDIOC_S_EDID; break; } switch (cmd) { @@ -868,9 +868,9 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar compatible_arg = 0; break; - case VIDIOC_SUBDEV_G_EDID: - case VIDIOC_SUBDEV_S_EDID: - err = get_v4l2_subdev_edid32(&karg.v2edid, up); + case VIDIOC_G_EDID: + case VIDIOC_S_EDID: + err = get_v4l2_edid32(&karg.v2edid, up); compatible_arg = 0; break; @@ -966,9 +966,9 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar err = put_v4l2_event32(&karg.v2ev, up); break; - case VIDIOC_SUBDEV_G_EDID: - case VIDIOC_SUBDEV_S_EDID: - err = put_v4l2_subdev_edid32(&karg.v2edid, up); + case VIDIOC_G_EDID: + case VIDIOC_S_EDID: + err = put_v4l2_edid32(&karg.v2edid, up); break; case VIDIOC_G_FMT: @@ -1006,103 +1006,14 @@ long v4l2_compat_ioctl32(struct file *file, unsigned int cmd, unsigned long arg) if (!file->f_op->unlocked_ioctl) return ret; - switch (cmd) { - case VIDIOC_QUERYCAP: - case VIDIOC_RESERVED: - case VIDIOC_ENUM_FMT: - case VIDIOC_G_FMT32: - case VIDIOC_S_FMT32: - case VIDIOC_REQBUFS: - case VIDIOC_QUERYBUF32: - case VIDIOC_G_FBUF32: - case VIDIOC_S_FBUF32: - case VIDIOC_OVERLAY32: - case VIDIOC_QBUF32: - case VIDIOC_EXPBUF: - case VIDIOC_DQBUF32: - case VIDIOC_STREAMON32: - case VIDIOC_STREAMOFF32: - case VIDIOC_G_PARM: - case VIDIOC_S_PARM: - case VIDIOC_G_STD: - case VIDIOC_S_STD: - case VIDIOC_ENUMSTD32: - case VIDIOC_ENUMINPUT32: - case VIDIOC_G_CTRL: - case VIDIOC_S_CTRL: - case VIDIOC_G_TUNER: - case VIDIOC_S_TUNER: - case VIDIOC_G_AUDIO: - case VIDIOC_S_AUDIO: - case VIDIOC_QUERYCTRL: - case VIDIOC_QUERYMENU: - case VIDIOC_G_INPUT32: - case VIDIOC_S_INPUT32: - case VIDIOC_G_OUTPUT32: - case VIDIOC_S_OUTPUT32: - case VIDIOC_ENUMOUTPUT: - case VIDIOC_G_AUDOUT: - case VIDIOC_S_AUDOUT: - case VIDIOC_G_MODULATOR: - case VIDIOC_S_MODULATOR: - case VIDIOC_S_FREQUENCY: - case VIDIOC_G_FREQUENCY: - case VIDIOC_CROPCAP: - case VIDIOC_G_CROP: - case VIDIOC_S_CROP: - case VIDIOC_G_SELECTION: - case VIDIOC_S_SELECTION: - case VIDIOC_G_JPEGCOMP: - case VIDIOC_S_JPEGCOMP: - case VIDIOC_QUERYSTD: - case VIDIOC_TRY_FMT32: - case VIDIOC_ENUMAUDIO: - case VIDIOC_ENUMAUDOUT: - case VIDIOC_G_PRIORITY: - case VIDIOC_S_PRIORITY: - case VIDIOC_G_SLICED_VBI_CAP: - case VIDIOC_LOG_STATUS: - case VIDIOC_G_EXT_CTRLS32: - case VIDIOC_S_EXT_CTRLS32: - case VIDIOC_TRY_EXT_CTRLS32: - case VIDIOC_ENUM_FRAMESIZES: - case VIDIOC_ENUM_FRAMEINTERVALS: - case VIDIOC_G_ENC_INDEX: - case VIDIOC_ENCODER_CMD: - case VIDIOC_TRY_ENCODER_CMD: - case VIDIOC_DECODER_CMD: - case VIDIOC_TRY_DECODER_CMD: - case VIDIOC_DBG_S_REGISTER: - case VIDIOC_DBG_G_REGISTER: - case VIDIOC_S_HW_FREQ_SEEK: - case VIDIOC_S_DV_TIMINGS: - case VIDIOC_G_DV_TIMINGS: - case VIDIOC_DQEVENT: - case VIDIOC_DQEVENT32: - case VIDIOC_SUBSCRIBE_EVENT: - case VIDIOC_UNSUBSCRIBE_EVENT: - case VIDIOC_CREATE_BUFS32: - case VIDIOC_PREPARE_BUF32: - case VIDIOC_ENUM_DV_TIMINGS: - case VIDIOC_QUERY_DV_TIMINGS: - case VIDIOC_DV_TIMINGS_CAP: - case VIDIOC_ENUM_FREQ_BANDS: - case VIDIOC_SUBDEV_G_EDID32: - case VIDIOC_SUBDEV_S_EDID32: + if (_IOC_TYPE(cmd) == 'V' && _IOC_NR(cmd) < BASE_VIDIOC_PRIVATE) ret = do_video_ioctl(file, cmd, arg); - break; + else if (vdev->fops->compat_ioctl32) + ret = vdev->fops->compat_ioctl32(file, cmd, arg); - default: - if (vdev->fops->compat_ioctl32) - ret = vdev->fops->compat_ioctl32(file, cmd, arg); - - if (ret == -ENOIOCTLCMD) - printk(KERN_WARNING "compat_ioctl32: " - "unknown ioctl '%c', dir=%d, #%d (0x%08x)\n", - _IOC_TYPE(cmd), _IOC_DIR(cmd), _IOC_NR(cmd), - cmd); - break; - } + if (ret == -ENOIOCTLCMD) + pr_warn("compat_ioctl32: unknown ioctl '%c', dir=%d, #%d (0x%08x)\n", + _IOC_TYPE(cmd), _IOC_DIR(cmd), _IOC_NR(cmd), cmd); return ret; } EXPORT_SYMBOL_GPL(v4l2_compat_ioctl32); diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c index 6ff002b..55c6832 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c @@ -735,6 +735,8 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_MPEG_VIDEO_DEC_PTS: return "Video Decoder PTS"; case V4L2_CID_MPEG_VIDEO_DEC_FRAME: return "Video Decoder Frame Count"; case V4L2_CID_MPEG_VIDEO_VBV_DELAY: return "Initial Delay for VBV Control"; + case V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE: return "Horizontal MV Search Range"; + case V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE: return "Vertical MV Search Range"; case V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER: return "Repeat Sequence Header"; /* VPX controls */ @@ -857,6 +859,17 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_FM_RX_CLASS: return "FM Radio Receiver Controls"; case V4L2_CID_TUNE_DEEMPHASIS: return "De-Emphasis"; case V4L2_CID_RDS_RECEPTION: return "RDS Reception"; + + case V4L2_CID_RF_TUNER_CLASS: return "RF Tuner Controls"; + case V4L2_CID_RF_TUNER_LNA_GAIN_AUTO: return "LNA Gain, Auto"; + case V4L2_CID_RF_TUNER_LNA_GAIN: return "LNA Gain"; + case V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO: return "Mixer Gain, Auto"; + case V4L2_CID_RF_TUNER_MIXER_GAIN: return "Mixer Gain"; + case V4L2_CID_RF_TUNER_IF_GAIN_AUTO: return "IF Gain, Auto"; + case V4L2_CID_RF_TUNER_IF_GAIN: return "IF Gain"; + case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: return "Bandwidth, Auto"; + case V4L2_CID_RF_TUNER_BANDWIDTH: return "Bandwidth"; + case V4L2_CID_RF_TUNER_PLL_LOCK: return "PLL Lock"; default: return NULL; } @@ -906,10 +919,19 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_WIDE_DYNAMIC_RANGE: case V4L2_CID_IMAGE_STABILIZATION: case V4L2_CID_RDS_RECEPTION: + case V4L2_CID_RF_TUNER_LNA_GAIN_AUTO: + case V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO: + case V4L2_CID_RF_TUNER_IF_GAIN_AUTO: + case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: + case V4L2_CID_RF_TUNER_PLL_LOCK: *type = V4L2_CTRL_TYPE_BOOLEAN; *min = 0; *max = *step = 1; break; + case V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE: + case V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE: + *type = V4L2_CTRL_TYPE_INTEGER; + break; case V4L2_CID_PAN_RESET: case V4L2_CID_TILT_RESET: case V4L2_CID_FLASH_STROBE: @@ -991,6 +1013,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_IMAGE_PROC_CLASS: case V4L2_CID_DV_CLASS: case V4L2_CID_FM_RX_CLASS: + case V4L2_CID_RF_TUNER_CLASS: *type = V4L2_CTRL_TYPE_CTRL_CLASS; /* You can neither read not write these */ *flags |= V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_WRITE_ONLY; @@ -1063,6 +1086,10 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_PILOT_TONE_FREQUENCY: case V4L2_CID_TUNE_POWER_LEVEL: case V4L2_CID_TUNE_ANTENNA_CAPACITOR: + case V4L2_CID_RF_TUNER_LNA_GAIN: + case V4L2_CID_RF_TUNER_MIXER_GAIN: + case V4L2_CID_RF_TUNER_IF_GAIN: + case V4L2_CID_RF_TUNER_BANDWIDTH: *flags |= V4L2_CTRL_FLAG_SLIDER; break; case V4L2_CID_PAN_RELATIVE: @@ -1081,6 +1108,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_DV_RX_POWER_PRESENT: *flags |= V4L2_CTRL_FLAG_READ_ONLY; break; + case V4L2_CID_RF_TUNER_PLL_LOCK: + *flags |= V4L2_CTRL_FLAG_VOLATILE; + break; } } EXPORT_SYMBOL(v4l2_ctrl_fill); @@ -1921,7 +1951,8 @@ void v4l2_ctrl_cluster(unsigned ncontrols, struct v4l2_ctrl **controls) int i; /* The first control is the master control and it must not be NULL */ - BUG_ON(ncontrols == 0 || controls[0] == NULL); + if (WARN_ON(ncontrols == 0 || controls[0] == NULL)) + return; for (i = 0; i < ncontrols; i++) { if (controls[i]) { diff --git a/drivers/media/v4l2-core/v4l2-dev.c b/drivers/media/v4l2-core/v4l2-dev.c index 0a30dbf..634d863 100644 --- a/drivers/media/v4l2-core/v4l2-dev.c +++ b/drivers/media/v4l2-core/v4l2-dev.c @@ -554,6 +554,7 @@ static void determine_valid_ioctls(struct video_device *vdev) bool is_vid = vdev->vfl_type == VFL_TYPE_GRABBER; bool is_vbi = vdev->vfl_type == VFL_TYPE_VBI; bool is_radio = vdev->vfl_type == VFL_TYPE_RADIO; + bool is_sdr = vdev->vfl_type == VFL_TYPE_SDR; bool is_rx = vdev->vfl_dir != VFL_DIR_TX; bool is_tx = vdev->vfl_dir != VFL_DIR_RX; @@ -662,9 +663,20 @@ static void determine_valid_ioctls(struct video_device *vdev) ops->vidioc_try_fmt_sliced_vbi_out))) set_bit(_IOC_NR(VIDIOC_TRY_FMT), valid_ioctls); SET_VALID_IOCTL(ops, VIDIOC_G_SLICED_VBI_CAP, vidioc_g_sliced_vbi_cap); + } else if (is_sdr) { + /* SDR specific ioctls */ + if (ops->vidioc_enum_fmt_sdr_cap) + set_bit(_IOC_NR(VIDIOC_ENUM_FMT), valid_ioctls); + if (ops->vidioc_g_fmt_sdr_cap) + set_bit(_IOC_NR(VIDIOC_G_FMT), valid_ioctls); + if (ops->vidioc_s_fmt_sdr_cap) + set_bit(_IOC_NR(VIDIOC_S_FMT), valid_ioctls); + if (ops->vidioc_try_fmt_sdr_cap) + set_bit(_IOC_NR(VIDIOC_TRY_FMT), valid_ioctls); } - if (!is_radio) { - /* ioctls valid for video or vbi */ + + if (is_vid || is_vbi || is_sdr) { + /* ioctls valid for video, vbi or sdr */ SET_VALID_IOCTL(ops, VIDIOC_REQBUFS, vidioc_reqbufs); SET_VALID_IOCTL(ops, VIDIOC_QUERYBUF, vidioc_querybuf); SET_VALID_IOCTL(ops, VIDIOC_QBUF, vidioc_qbuf); @@ -672,6 +684,10 @@ static void determine_valid_ioctls(struct video_device *vdev) SET_VALID_IOCTL(ops, VIDIOC_DQBUF, vidioc_dqbuf); SET_VALID_IOCTL(ops, VIDIOC_CREATE_BUFS, vidioc_create_bufs); SET_VALID_IOCTL(ops, VIDIOC_PREPARE_BUF, vidioc_prepare_buf); + } + + if (is_vid || is_vbi) { + /* ioctls valid for video or vbi */ if (ops->vidioc_s_std) set_bit(_IOC_NR(VIDIOC_ENUMSTD), valid_ioctls); SET_VALID_IOCTL(ops, VIDIOC_S_STD, vidioc_s_std); @@ -685,6 +701,7 @@ static void determine_valid_ioctls(struct video_device *vdev) SET_VALID_IOCTL(ops, VIDIOC_G_AUDIO, vidioc_g_audio); SET_VALID_IOCTL(ops, VIDIOC_S_AUDIO, vidioc_s_audio); SET_VALID_IOCTL(ops, VIDIOC_QUERY_DV_TIMINGS, vidioc_query_dv_timings); + SET_VALID_IOCTL(ops, VIDIOC_S_EDID, vidioc_s_edid); } if (is_tx) { SET_VALID_IOCTL(ops, VIDIOC_ENUMOUTPUT, vidioc_enum_output); @@ -710,9 +727,10 @@ static void determine_valid_ioctls(struct video_device *vdev) SET_VALID_IOCTL(ops, VIDIOC_G_DV_TIMINGS, vidioc_g_dv_timings); SET_VALID_IOCTL(ops, VIDIOC_ENUM_DV_TIMINGS, vidioc_enum_dv_timings); SET_VALID_IOCTL(ops, VIDIOC_DV_TIMINGS_CAP, vidioc_dv_timings_cap); + SET_VALID_IOCTL(ops, VIDIOC_G_EDID, vidioc_g_edid); } - if (is_tx) { - /* transmitter only ioctls */ + if (is_tx && (is_radio || is_sdr)) { + /* radio transmitter only ioctls */ SET_VALID_IOCTL(ops, VIDIOC_G_MODULATOR, vidioc_g_modulator); SET_VALID_IOCTL(ops, VIDIOC_S_MODULATOR, vidioc_s_modulator); } @@ -758,6 +776,8 @@ static void determine_valid_ioctls(struct video_device *vdev) * %VFL_TYPE_RADIO - A radio card * * %VFL_TYPE_SUBDEV - A subdevice + * + * %VFL_TYPE_SDR - Software Defined Radio */ int __video_register_device(struct video_device *vdev, int type, int nr, int warn_if_nr_in_use, struct module *owner) @@ -797,6 +817,10 @@ int __video_register_device(struct video_device *vdev, int type, int nr, case VFL_TYPE_SUBDEV: name_base = "v4l-subdev"; break; + case VFL_TYPE_SDR: + /* Use device name 'swradio' because 'sdr' was already taken. */ + name_base = "swradio"; + break; default: printk(KERN_ERR "%s called with unknown type: %d\n", __func__, type); diff --git a/drivers/media/v4l2-core/v4l2-dv-timings.c b/drivers/media/v4l2-core/v4l2-dv-timings.c index f7902fe..48b20df 100644 --- a/drivers/media/v4l2-core/v4l2-dv-timings.c +++ b/drivers/media/v4l2-core/v4l2-dv-timings.c @@ -26,6 +26,10 @@ #include <linux/v4l2-dv-timings.h> #include <media/v4l2-dv-timings.h> +MODULE_AUTHOR("Hans Verkuil"); +MODULE_DESCRIPTION("V4L2 DV Timings Helper Functions"); +MODULE_LICENSE("GPL"); + const struct v4l2_dv_timings v4l2_dv_timings_presets[] = { V4L2_DV_BT_CEA_640X480P59_94, V4L2_DV_BT_CEA_720X480I59_94, @@ -324,6 +328,10 @@ EXPORT_SYMBOL_GPL(v4l2_print_dv_timings); * This function will attempt to detect if the given values correspond to a * valid CVT format. If so, then it will return true, and fmt will be filled * in with the found CVT timings. + * + * TODO: VESA defined a new version 2 of their reduced blanking + * formula. Support for that is currently missing in this CVT + * detection function. */ bool v4l2_detect_cvt(unsigned frame_height, unsigned hfreq, unsigned vsync, u32 polarities, struct v4l2_dv_timings *fmt) diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index 707aef7..d9113cc 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -152,6 +152,7 @@ const char *v4l2_type_names[] = { [V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY] = "vid-out-overlay", [V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE] = "vid-cap-mplane", [V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE] = "vid-out-mplane", + [V4L2_BUF_TYPE_SDR_CAPTURE] = "sdr-cap", }; EXPORT_SYMBOL(v4l2_type_names); @@ -245,6 +246,7 @@ static void v4l_print_format(const void *arg, bool write_only) const struct v4l2_vbi_format *vbi; const struct v4l2_sliced_vbi_format *sliced; const struct v4l2_window *win; + const struct v4l2_sdr_format *sdr; unsigned i; pr_cont("type=%s", prt_names(p->type, v4l2_type_names)); @@ -318,6 +320,14 @@ static void v4l_print_format(const void *arg, bool write_only) sliced->service_lines[0][i], sliced->service_lines[1][i]); break; + case V4L2_BUF_TYPE_SDR_CAPTURE: + sdr = &p->fmt.sdr; + pr_cont(", pixelformat=%c%c%c%c\n", + (sdr->pixelformat >> 0) & 0xff, + (sdr->pixelformat >> 8) & 0xff, + (sdr->pixelformat >> 16) & 0xff, + (sdr->pixelformat >> 24) & 0xff); + break; } } @@ -834,6 +844,14 @@ static void v4l_print_freq_band(const void *arg, bool write_only) p->rangehigh, p->modulation); } +static void v4l_print_edid(const void *arg, bool write_only) +{ + const struct v4l2_edid *p = arg; + + pr_cont("pad=%u, start_block=%u, blocks=%u\n", + p->pad, p->start_block, p->blocks); +} + static void v4l_print_u32(const void *arg, bool write_only) { pr_cont("value=%u\n", *(const u32 *)arg); @@ -881,6 +899,7 @@ static int check_fmt(struct file *file, enum v4l2_buf_type type) const struct v4l2_ioctl_ops *ops = vfd->ioctl_ops; bool is_vid = vfd->vfl_type == VFL_TYPE_GRABBER; bool is_vbi = vfd->vfl_type == VFL_TYPE_VBI; + bool is_sdr = vfd->vfl_type == VFL_TYPE_SDR; bool is_rx = vfd->vfl_dir != VFL_DIR_TX; bool is_tx = vfd->vfl_dir != VFL_DIR_RX; @@ -930,6 +949,10 @@ static int check_fmt(struct file *file, enum v4l2_buf_type type) if (is_vbi && is_tx && ops->vidioc_g_fmt_sliced_vbi_out) return 0; break; + case V4L2_BUF_TYPE_SDR_CAPTURE: + if (is_sdr && is_rx && ops->vidioc_g_fmt_sdr_cap) + return 0; + break; default: break; } @@ -1049,6 +1072,10 @@ static int v4l_enum_fmt(const struct v4l2_ioctl_ops *ops, if (unlikely(!is_tx || !ops->vidioc_enum_fmt_vid_out_mplane)) break; return ops->vidioc_enum_fmt_vid_out_mplane(file, fh, arg); + case V4L2_BUF_TYPE_SDR_CAPTURE: + if (unlikely(!is_rx || !ops->vidioc_enum_fmt_sdr_cap)) + break; + return ops->vidioc_enum_fmt_sdr_cap(file, fh, arg); } return -EINVAL; } @@ -1059,6 +1086,7 @@ static int v4l_g_fmt(const struct v4l2_ioctl_ops *ops, struct v4l2_format *p = arg; struct video_device *vfd = video_devdata(file); bool is_vid = vfd->vfl_type == VFL_TYPE_GRABBER; + bool is_sdr = vfd->vfl_type == VFL_TYPE_SDR; bool is_rx = vfd->vfl_dir != VFL_DIR_TX; bool is_tx = vfd->vfl_dir != VFL_DIR_RX; @@ -1103,6 +1131,10 @@ static int v4l_g_fmt(const struct v4l2_ioctl_ops *ops, if (unlikely(!is_tx || is_vid || !ops->vidioc_g_fmt_sliced_vbi_out)) break; return ops->vidioc_g_fmt_sliced_vbi_out(file, fh, arg); + case V4L2_BUF_TYPE_SDR_CAPTURE: + if (unlikely(!is_rx || !is_sdr || !ops->vidioc_g_fmt_sdr_cap)) + break; + return ops->vidioc_g_fmt_sdr_cap(file, fh, arg); } return -EINVAL; } @@ -1113,6 +1145,7 @@ static int v4l_s_fmt(const struct v4l2_ioctl_ops *ops, struct v4l2_format *p = arg; struct video_device *vfd = video_devdata(file); bool is_vid = vfd->vfl_type == VFL_TYPE_GRABBER; + bool is_sdr = vfd->vfl_type == VFL_TYPE_SDR; bool is_rx = vfd->vfl_dir != VFL_DIR_TX; bool is_tx = vfd->vfl_dir != VFL_DIR_RX; @@ -1167,6 +1200,11 @@ static int v4l_s_fmt(const struct v4l2_ioctl_ops *ops, break; CLEAR_AFTER_FIELD(p, fmt.sliced); return ops->vidioc_s_fmt_sliced_vbi_out(file, fh, arg); + case V4L2_BUF_TYPE_SDR_CAPTURE: + if (unlikely(!is_rx || !is_sdr || !ops->vidioc_s_fmt_sdr_cap)) + break; + CLEAR_AFTER_FIELD(p, fmt.sdr); + return ops->vidioc_s_fmt_sdr_cap(file, fh, arg); } return -EINVAL; } @@ -1177,6 +1215,7 @@ static int v4l_try_fmt(const struct v4l2_ioctl_ops *ops, struct v4l2_format *p = arg; struct video_device *vfd = video_devdata(file); bool is_vid = vfd->vfl_type == VFL_TYPE_GRABBER; + bool is_sdr = vfd->vfl_type == VFL_TYPE_SDR; bool is_rx = vfd->vfl_dir != VFL_DIR_TX; bool is_tx = vfd->vfl_dir != VFL_DIR_RX; @@ -1231,6 +1270,11 @@ static int v4l_try_fmt(const struct v4l2_ioctl_ops *ops, break; CLEAR_AFTER_FIELD(p, fmt.sliced); return ops->vidioc_try_fmt_sliced_vbi_out(file, fh, arg); + case V4L2_BUF_TYPE_SDR_CAPTURE: + if (unlikely(!is_rx || !is_sdr || !ops->vidioc_try_fmt_sdr_cap)) + break; + CLEAR_AFTER_FIELD(p, fmt.sdr); + return ops->vidioc_try_fmt_sdr_cap(file, fh, arg); } return -EINVAL; } @@ -1291,8 +1335,11 @@ static int v4l_g_frequency(const struct v4l2_ioctl_ops *ops, struct video_device *vfd = video_devdata(file); struct v4l2_frequency *p = arg; - p->type = (vfd->vfl_type == VFL_TYPE_RADIO) ? - V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; + if (vfd->vfl_type == VFL_TYPE_SDR) + p->type = V4L2_TUNER_ADC; + else + p->type = (vfd->vfl_type == VFL_TYPE_RADIO) ? + V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; return ops->vidioc_g_frequency(file, fh, p); } @@ -1303,10 +1350,15 @@ static int v4l_s_frequency(const struct v4l2_ioctl_ops *ops, const struct v4l2_frequency *p = arg; enum v4l2_tuner_type type; - type = (vfd->vfl_type == VFL_TYPE_RADIO) ? - V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; - if (p->type != type) - return -EINVAL; + if (vfd->vfl_type == VFL_TYPE_SDR) { + if (p->type != V4L2_TUNER_ADC && p->type != V4L2_TUNER_RF) + return -EINVAL; + } else { + type = (vfd->vfl_type == VFL_TYPE_RADIO) ? + V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; + if (type != p->type) + return -EINVAL; + } return ops->vidioc_s_frequency(file, fh, p); } @@ -1386,6 +1438,10 @@ static int v4l_s_hw_freq_seek(const struct v4l2_ioctl_ops *ops, struct v4l2_hw_freq_seek *p = arg; enum v4l2_tuner_type type; + /* s_hw_freq_seek is not supported for SDR for now */ + if (vfd->vfl_type == VFL_TYPE_SDR) + return -EINVAL; + type = (vfd->vfl_type == VFL_TYPE_RADIO) ? V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; if (p->type != type) @@ -1885,11 +1941,16 @@ static int v4l_enum_freq_bands(const struct v4l2_ioctl_ops *ops, enum v4l2_tuner_type type; int err; - type = (vfd->vfl_type == VFL_TYPE_RADIO) ? - V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; - - if (type != p->type) - return -EINVAL; + if (vfd->vfl_type == VFL_TYPE_SDR) { + if (p->type != V4L2_TUNER_ADC && p->type != V4L2_TUNER_RF) + return -EINVAL; + type = p->type; + } else { + type = (vfd->vfl_type == VFL_TYPE_RADIO) ? + V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; + if (type != p->type) + return -EINVAL; + } if (ops->vidioc_enum_freq_bands) return ops->vidioc_enum_freq_bands(file, fh, p); if (is_valid_ioctl(vfd, VIDIOC_G_TUNER)) { @@ -2009,6 +2070,8 @@ static struct v4l2_ioctl_info v4l2_ioctls[] = { IOCTL_INFO_FNC(VIDIOC_QUERYMENU, v4l_querymenu, v4l_print_querymenu, INFO_FL_CTRL | INFO_FL_CLEAR(v4l2_querymenu, index)), IOCTL_INFO_STD(VIDIOC_G_INPUT, vidioc_g_input, v4l_print_u32, 0), IOCTL_INFO_FNC(VIDIOC_S_INPUT, v4l_s_input, v4l_print_u32, INFO_FL_PRIO), + IOCTL_INFO_STD(VIDIOC_G_EDID, vidioc_g_edid, v4l_print_edid, INFO_FL_CLEAR(v4l2_edid, edid)), + IOCTL_INFO_STD(VIDIOC_S_EDID, vidioc_s_edid, v4l_print_edid, INFO_FL_PRIO | INFO_FL_CLEAR(v4l2_edid, edid)), IOCTL_INFO_STD(VIDIOC_G_OUTPUT, vidioc_g_output, v4l_print_u32, 0), IOCTL_INFO_FNC(VIDIOC_S_OUTPUT, v4l_s_output, v4l_print_u32, INFO_FL_PRIO), IOCTL_INFO_FNC(VIDIOC_ENUMOUTPUT, v4l_enumoutput, v4l_print_enumoutput, INFO_FL_CLEAR(v4l2_output, index)), @@ -2221,9 +2284,9 @@ static int check_array_args(unsigned int cmd, void *parg, size_t *array_size, break; } - case VIDIOC_SUBDEV_G_EDID: - case VIDIOC_SUBDEV_S_EDID: { - struct v4l2_subdev_edid *edid = parg; + case VIDIOC_G_EDID: + case VIDIOC_S_EDID: { + struct v4l2_edid *edid = parg; if (edid->blocks) { if (edid->blocks > 256) { diff --git a/drivers/media/v4l2-core/v4l2-subdev.c b/drivers/media/v4l2-core/v4l2-subdev.c index 996c248..aea84ac 100644 --- a/drivers/media/v4l2-core/v4l2-subdev.c +++ b/drivers/media/v4l2-core/v4l2-subdev.c @@ -349,10 +349,10 @@ static long subdev_do_ioctl(struct file *file, unsigned int cmd, void *arg) sd, pad, set_selection, subdev_fh, sel); } - case VIDIOC_SUBDEV_G_EDID: + case VIDIOC_G_EDID: return v4l2_subdev_call(sd, pad, get_edid, arg); - case VIDIOC_SUBDEV_S_EDID: + case VIDIOC_S_EDID: return v4l2_subdev_call(sd, pad, set_edid, arg); #endif default: @@ -368,6 +368,17 @@ static long subdev_ioctl(struct file *file, unsigned int cmd, return video_usercopy(file, cmd, arg, subdev_do_ioctl); } +#ifdef CONFIG_COMPAT +static long subdev_compat_ioctl32(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct video_device *vdev = video_devdata(file); + struct v4l2_subdev *sd = vdev_to_v4l2_subdev(vdev); + + return v4l2_subdev_call(sd, core, compat_ioctl32, cmd, arg); +} +#endif + static unsigned int subdev_poll(struct file *file, poll_table *wait) { struct video_device *vdev = video_devdata(file); @@ -389,6 +400,9 @@ const struct v4l2_file_operations v4l2_subdev_fops = { .owner = THIS_MODULE, .open = subdev_open, .unlocked_ioctl = subdev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = subdev_compat_ioctl32, +#endif .release = subdev_close, .poll = subdev_poll, }; diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index a127925..f9059bb 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -33,17 +33,74 @@ module_param(debug, int, 0644); printk(KERN_DEBUG "vb2: " fmt, ## arg); \ } while (0) -#define call_memop(q, op, args...) \ - (((q)->mem_ops->op) ? \ - ((q)->mem_ops->op(args)) : 0) +#ifdef CONFIG_VIDEO_ADV_DEBUG + +/* + * If advanced debugging is on, then count how often each op is called, + * which can either be per-buffer or per-queue. + * + * If the op failed then the 'fail_' variant is called to decrease the + * counter. That makes it easy to check that the 'init' and 'cleanup' + * (and variations thereof) stay balanced. + */ + +#define call_memop(vb, op, args...) \ +({ \ + struct vb2_queue *_q = (vb)->vb2_queue; \ + dprintk(2, "call_memop(%p, %d, %s)%s\n", \ + _q, (vb)->v4l2_buf.index, #op, \ + _q->mem_ops->op ? "" : " (nop)"); \ + (vb)->cnt_mem_ ## op++; \ + _q->mem_ops->op ? _q->mem_ops->op(args) : 0; \ +}) +#define fail_memop(vb, op) ((vb)->cnt_mem_ ## op--) + +#define call_qop(q, op, args...) \ +({ \ + dprintk(2, "call_qop(%p, %s)%s\n", q, #op, \ + (q)->ops->op ? "" : " (nop)"); \ + (q)->cnt_ ## op++; \ + (q)->ops->op ? (q)->ops->op(args) : 0; \ +}) +#define fail_qop(q, op) ((q)->cnt_ ## op--) + +#define call_vb_qop(vb, op, args...) \ +({ \ + struct vb2_queue *_q = (vb)->vb2_queue; \ + dprintk(2, "call_vb_qop(%p, %d, %s)%s\n", \ + _q, (vb)->v4l2_buf.index, #op, \ + _q->ops->op ? "" : " (nop)"); \ + (vb)->cnt_ ## op++; \ + _q->ops->op ? _q->ops->op(args) : 0; \ +}) +#define fail_vb_qop(vb, op) ((vb)->cnt_ ## op--) + +#else + +#define call_memop(vb, op, args...) \ + ((vb)->vb2_queue->mem_ops->op ? (vb)->vb2_queue->mem_ops->op(args) : 0) +#define fail_memop(vb, op) #define call_qop(q, op, args...) \ - (((q)->ops->op) ? ((q)->ops->op(args)) : 0) + ((q)->ops->op ? (q)->ops->op(args) : 0) +#define fail_qop(q, op) +#define call_vb_qop(vb, op, args...) \ + ((vb)->vb2_queue->ops->op ? (vb)->vb2_queue->ops->op(args) : 0) +#define fail_vb_qop(vb, op) + +#endif + +/* Flags that are set by the vb2 core */ #define V4L2_BUFFER_MASK_FLAGS (V4L2_BUF_FLAG_MAPPED | V4L2_BUF_FLAG_QUEUED | \ V4L2_BUF_FLAG_DONE | V4L2_BUF_FLAG_ERROR | \ V4L2_BUF_FLAG_PREPARED | \ V4L2_BUF_FLAG_TIMESTAMP_MASK) +/* Output buffer flags that should be passed on to the driver */ +#define V4L2_BUFFER_OUT_FLAGS (V4L2_BUF_FLAG_PFRAME | V4L2_BUF_FLAG_BFRAME | \ + V4L2_BUF_FLAG_KEYFRAME | V4L2_BUF_FLAG_TIMECODE) + +static void __vb2_queue_cancel(struct vb2_queue *q); /** * __vb2_buf_mem_alloc() - allocate video memory for the given buffer @@ -61,7 +118,7 @@ static int __vb2_buf_mem_alloc(struct vb2_buffer *vb) for (plane = 0; plane < vb->num_planes; ++plane) { unsigned long size = PAGE_ALIGN(q->plane_sizes[plane]); - mem_priv = call_memop(q, alloc, q->alloc_ctx[plane], + mem_priv = call_memop(vb, alloc, q->alloc_ctx[plane], size, q->gfp_flags); if (IS_ERR_OR_NULL(mem_priv)) goto free; @@ -73,9 +130,10 @@ static int __vb2_buf_mem_alloc(struct vb2_buffer *vb) return 0; free: + fail_memop(vb, alloc); /* Free already allocated memory if one of the allocations failed */ for (; plane > 0; --plane) { - call_memop(q, put, vb->planes[plane - 1].mem_priv); + call_memop(vb, put, vb->planes[plane - 1].mem_priv); vb->planes[plane - 1].mem_priv = NULL; } @@ -87,11 +145,10 @@ free: */ static void __vb2_buf_mem_free(struct vb2_buffer *vb) { - struct vb2_queue *q = vb->vb2_queue; unsigned int plane; for (plane = 0; plane < vb->num_planes; ++plane) { - call_memop(q, put, vb->planes[plane].mem_priv); + call_memop(vb, put, vb->planes[plane].mem_priv); vb->planes[plane].mem_priv = NULL; dprintk(3, "Freed plane %d of buffer %d\n", plane, vb->v4l2_buf.index); @@ -104,12 +161,11 @@ static void __vb2_buf_mem_free(struct vb2_buffer *vb) */ static void __vb2_buf_userptr_put(struct vb2_buffer *vb) { - struct vb2_queue *q = vb->vb2_queue; unsigned int plane; for (plane = 0; plane < vb->num_planes; ++plane) { if (vb->planes[plane].mem_priv) - call_memop(q, put_userptr, vb->planes[plane].mem_priv); + call_memop(vb, put_userptr, vb->planes[plane].mem_priv); vb->planes[plane].mem_priv = NULL; } } @@ -118,15 +174,15 @@ static void __vb2_buf_userptr_put(struct vb2_buffer *vb) * __vb2_plane_dmabuf_put() - release memory associated with * a DMABUF shared plane */ -static void __vb2_plane_dmabuf_put(struct vb2_queue *q, struct vb2_plane *p) +static void __vb2_plane_dmabuf_put(struct vb2_buffer *vb, struct vb2_plane *p) { if (!p->mem_priv) return; if (p->dbuf_mapped) - call_memop(q, unmap_dmabuf, p->mem_priv); + call_memop(vb, unmap_dmabuf, p->mem_priv); - call_memop(q, detach_dmabuf, p->mem_priv); + call_memop(vb, detach_dmabuf, p->mem_priv); dma_buf_put(p->dbuf); memset(p, 0, sizeof(*p)); } @@ -137,11 +193,10 @@ static void __vb2_plane_dmabuf_put(struct vb2_queue *q, struct vb2_plane *p) */ static void __vb2_buf_dmabuf_put(struct vb2_buffer *vb) { - struct vb2_queue *q = vb->vb2_queue; unsigned int plane; for (plane = 0; plane < vb->num_planes; ++plane) - __vb2_plane_dmabuf_put(q, &vb->planes[plane]); + __vb2_plane_dmabuf_put(vb, &vb->planes[plane]); } /** @@ -246,10 +301,11 @@ static int __vb2_queue_alloc(struct vb2_queue *q, enum v4l2_memory memory, * callback, if given. An error in initialization * results in queue setup failure. */ - ret = call_qop(q, buf_init, vb); + ret = call_vb_qop(vb, buf_init, vb); if (ret) { dprintk(1, "Buffer %d %p initialization" " failed\n", buffer, vb); + fail_vb_qop(vb, buf_init); __vb2_buf_mem_free(vb); kfree(vb); break; @@ -321,18 +377,79 @@ static int __vb2_queue_free(struct vb2_queue *q, unsigned int buffers) } /* Call driver-provided cleanup function for each buffer, if provided */ - if (q->ops->buf_cleanup) { - for (buffer = q->num_buffers - buffers; buffer < q->num_buffers; - ++buffer) { - if (NULL == q->bufs[buffer]) - continue; - q->ops->buf_cleanup(q->bufs[buffer]); - } + for (buffer = q->num_buffers - buffers; buffer < q->num_buffers; + ++buffer) { + struct vb2_buffer *vb = q->bufs[buffer]; + + if (vb && vb->planes[0].mem_priv) + call_vb_qop(vb, buf_cleanup, vb); } /* Release video buffer memory */ __vb2_free_mem(q, buffers); +#ifdef CONFIG_VIDEO_ADV_DEBUG + /* + * Check that all the calls were balances during the life-time of this + * queue. If not (or if the debug level is 1 or up), then dump the + * counters to the kernel log. + */ + if (q->num_buffers) { + bool unbalanced = q->cnt_start_streaming != q->cnt_stop_streaming || + q->cnt_wait_prepare != q->cnt_wait_finish; + + if (unbalanced || debug) { + pr_info("vb2: counters for queue %p:%s\n", q, + unbalanced ? " UNBALANCED!" : ""); + pr_info("vb2: setup: %u start_streaming: %u stop_streaming: %u\n", + q->cnt_queue_setup, q->cnt_start_streaming, + q->cnt_stop_streaming); + pr_info("vb2: wait_prepare: %u wait_finish: %u\n", + q->cnt_wait_prepare, q->cnt_wait_finish); + } + q->cnt_queue_setup = 0; + q->cnt_wait_prepare = 0; + q->cnt_wait_finish = 0; + q->cnt_start_streaming = 0; + q->cnt_stop_streaming = 0; + } + for (buffer = 0; buffer < q->num_buffers; ++buffer) { + struct vb2_buffer *vb = q->bufs[buffer]; + bool unbalanced = vb->cnt_mem_alloc != vb->cnt_mem_put || + vb->cnt_mem_prepare != vb->cnt_mem_finish || + vb->cnt_mem_get_userptr != vb->cnt_mem_put_userptr || + vb->cnt_mem_attach_dmabuf != vb->cnt_mem_detach_dmabuf || + vb->cnt_mem_map_dmabuf != vb->cnt_mem_unmap_dmabuf || + vb->cnt_buf_queue != vb->cnt_buf_done || + vb->cnt_buf_prepare != vb->cnt_buf_finish || + vb->cnt_buf_init != vb->cnt_buf_cleanup; + + if (unbalanced || debug) { + pr_info("vb2: counters for queue %p, buffer %d:%s\n", + q, buffer, unbalanced ? " UNBALANCED!" : ""); + pr_info("vb2: buf_init: %u buf_cleanup: %u buf_prepare: %u buf_finish: %u\n", + vb->cnt_buf_init, vb->cnt_buf_cleanup, + vb->cnt_buf_prepare, vb->cnt_buf_finish); + pr_info("vb2: buf_queue: %u buf_done: %u\n", + vb->cnt_buf_queue, vb->cnt_buf_done); + pr_info("vb2: alloc: %u put: %u prepare: %u finish: %u mmap: %u\n", + vb->cnt_mem_alloc, vb->cnt_mem_put, + vb->cnt_mem_prepare, vb->cnt_mem_finish, + vb->cnt_mem_mmap); + pr_info("vb2: get_userptr: %u put_userptr: %u\n", + vb->cnt_mem_get_userptr, vb->cnt_mem_put_userptr); + pr_info("vb2: attach_dmabuf: %u detach_dmabuf: %u map_dmabuf: %u unmap_dmabuf: %u\n", + vb->cnt_mem_attach_dmabuf, vb->cnt_mem_detach_dmabuf, + vb->cnt_mem_map_dmabuf, vb->cnt_mem_unmap_dmabuf); + pr_info("vb2: get_dmabuf: %u num_users: %u vaddr: %u cookie: %u\n", + vb->cnt_mem_get_dmabuf, + vb->cnt_mem_num_users, + vb->cnt_mem_vaddr, + vb->cnt_mem_cookie); + } + } +#endif + /* Free videobuf buffers */ for (buffer = q->num_buffers - buffers; buffer < q->num_buffers; ++buffer) { @@ -341,9 +458,10 @@ static int __vb2_queue_free(struct vb2_queue *q, unsigned int buffers) } q->num_buffers -= buffers; - if (!q->num_buffers) + if (!q->num_buffers) { q->memory = 0; - INIT_LIST_HEAD(&q->queued_list); + INIT_LIST_HEAD(&q->queued_list); + } return 0; } @@ -424,7 +542,7 @@ static bool __buffer_in_use(struct vb2_queue *q, struct vb2_buffer *vb) * case anyway. If num_users() returns more than 1, * we are not the only user of the plane's memory. */ - if (mem_priv && call_memop(q, num_users, mem_priv) > 1) + if (mem_priv && call_memop(vb, num_users, mem_priv) > 1) return true; } return false; @@ -484,7 +602,16 @@ static void __fill_v4l2_buffer(struct vb2_buffer *vb, struct v4l2_buffer *b) * Clear any buffer state related flags. */ b->flags &= ~V4L2_BUFFER_MASK_FLAGS; - b->flags |= q->timestamp_type; + b->flags |= q->timestamp_flags & V4L2_BUF_FLAG_TIMESTAMP_MASK; + if ((q->timestamp_flags & V4L2_BUF_FLAG_TIMESTAMP_MASK) != + V4L2_BUF_FLAG_TIMESTAMP_COPY) { + /* + * For non-COPY timestamps, drop timestamp source bits + * and obtain the timestamp source from the queue. + */ + b->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + b->flags |= q->timestamp_flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + } switch (vb->state) { case VB2_BUF_STATE_QUEUED: @@ -677,6 +804,12 @@ static int __reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req) return -EBUSY; } + /* + * Call queue_cancel to clean up any buffers in the PREPARED or + * QUEUED state which is possible if buffers were prepared or + * queued without ever calling STREAMON. + */ + __vb2_queue_cancel(q); ret = __vb2_queue_free(q, q->num_buffers); if (ret) return ret; @@ -693,6 +826,7 @@ static int __reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req) * Make sure the requested values and current defaults are sane. */ num_buffers = min_t(unsigned int, req->count, VIDEO_MAX_FRAME); + num_buffers = max_t(unsigned int, req->count, q->min_buffers_needed); memset(q->plane_sizes, 0, sizeof(q->plane_sizes)); memset(q->alloc_ctx, 0, sizeof(q->alloc_ctx)); q->memory = req->memory; @@ -703,26 +837,35 @@ static int __reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req) */ ret = call_qop(q, queue_setup, q, NULL, &num_buffers, &num_planes, q->plane_sizes, q->alloc_ctx); - if (ret) + if (ret) { + fail_qop(q, queue_setup); return ret; + } /* Finally, allocate buffers and video memory */ - ret = __vb2_queue_alloc(q, req->memory, num_buffers, num_planes); - if (ret == 0) { + allocated_buffers = __vb2_queue_alloc(q, req->memory, num_buffers, num_planes); + if (allocated_buffers == 0) { dprintk(1, "Memory allocation failed\n"); return -ENOMEM; } - allocated_buffers = ret; + /* + * There is no point in continuing if we can't allocate the minimum + * number of buffers needed by this vb2_queue. + */ + if (allocated_buffers < q->min_buffers_needed) + ret = -ENOMEM; /* * Check if driver can handle the allocated number of buffers. */ - if (allocated_buffers < num_buffers) { + if (!ret && allocated_buffers < num_buffers) { num_buffers = allocated_buffers; ret = call_qop(q, queue_setup, q, NULL, &num_buffers, &num_planes, q->plane_sizes, q->alloc_ctx); + if (ret) + fail_qop(q, queue_setup); if (!ret && allocated_buffers < num_buffers) ret = -ENOMEM; @@ -736,6 +879,10 @@ static int __reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req) q->num_buffers = allocated_buffers; if (ret < 0) { + /* + * Note: __vb2_queue_free() will subtract 'allocated_buffers' + * from q->num_buffers. + */ __vb2_queue_free(q, allocated_buffers); return ret; } @@ -803,24 +950,24 @@ static int __create_bufs(struct vb2_queue *q, struct v4l2_create_buffers *create */ ret = call_qop(q, queue_setup, q, &create->format, &num_buffers, &num_planes, q->plane_sizes, q->alloc_ctx); - if (ret) + if (ret) { + fail_qop(q, queue_setup); return ret; + } /* Finally, allocate buffers and video memory */ - ret = __vb2_queue_alloc(q, create->memory, num_buffers, + allocated_buffers = __vb2_queue_alloc(q, create->memory, num_buffers, num_planes); - if (ret == 0) { + if (allocated_buffers == 0) { dprintk(1, "Memory allocation failed\n"); return -ENOMEM; } - allocated_buffers = ret; - /* * Check if driver can handle the so far allocated number of buffers. */ - if (ret < num_buffers) { - num_buffers = ret; + if (allocated_buffers < num_buffers) { + num_buffers = allocated_buffers; /* * q->num_buffers contains the total number of buffers, that the @@ -828,6 +975,8 @@ static int __create_bufs(struct vb2_queue *q, struct v4l2_create_buffers *create */ ret = call_qop(q, queue_setup, q, &create->format, &num_buffers, &num_planes, q->plane_sizes, q->alloc_ctx); + if (ret) + fail_qop(q, queue_setup); if (!ret && allocated_buffers < num_buffers) ret = -ENOMEM; @@ -841,6 +990,10 @@ static int __create_bufs(struct vb2_queue *q, struct v4l2_create_buffers *create q->num_buffers += allocated_buffers; if (ret < 0) { + /* + * Note: __vb2_queue_free() will subtract 'allocated_buffers' + * from q->num_buffers. + */ __vb2_queue_free(q, allocated_buffers); return -ENOMEM; } @@ -882,12 +1035,10 @@ EXPORT_SYMBOL_GPL(vb2_create_bufs); */ void *vb2_plane_vaddr(struct vb2_buffer *vb, unsigned int plane_no) { - struct vb2_queue *q = vb->vb2_queue; - if (plane_no > vb->num_planes || !vb->planes[plane_no].mem_priv) return NULL; - return call_memop(q, vaddr, vb->planes[plane_no].mem_priv); + return call_memop(vb, vaddr, vb->planes[plane_no].mem_priv); } EXPORT_SYMBOL_GPL(vb2_plane_vaddr); @@ -905,12 +1056,10 @@ EXPORT_SYMBOL_GPL(vb2_plane_vaddr); */ void *vb2_plane_cookie(struct vb2_buffer *vb, unsigned int plane_no) { - struct vb2_queue *q = vb->vb2_queue; - if (plane_no > vb->num_planes || !vb->planes[plane_no].mem_priv) return NULL; - return call_memop(q, cookie, vb->planes[plane_no].mem_priv); + return call_memop(vb, cookie, vb->planes[plane_no].mem_priv); } EXPORT_SYMBOL_GPL(vb2_plane_cookie); @@ -918,13 +1067,20 @@ EXPORT_SYMBOL_GPL(vb2_plane_cookie); * vb2_buffer_done() - inform videobuf that an operation on a buffer is finished * @vb: vb2_buffer returned from the driver * @state: either VB2_BUF_STATE_DONE if the operation finished successfully - * or VB2_BUF_STATE_ERROR if the operation finished with an error + * or VB2_BUF_STATE_ERROR if the operation finished with an error. + * If start_streaming fails then it should return buffers with state + * VB2_BUF_STATE_QUEUED to put them back into the queue. * * This function should be called by the driver after a hardware operation on * a buffer is finished and the buffer may be returned to userspace. The driver * cannot use this buffer anymore until it is queued back to it by videobuf * by the means of buf_queue callback. Only buffers previously queued to the * driver by buf_queue can be passed to this function. + * + * While streaming a buffer can only be returned in state DONE or ERROR. + * The start_streaming op can also return them in case the DMA engine cannot + * be started for some reason. In that case the buffers should be returned with + * state QUEUED. */ void vb2_buffer_done(struct vb2_buffer *vb, enum vb2_buffer_state state) { @@ -932,26 +1088,43 @@ void vb2_buffer_done(struct vb2_buffer *vb, enum vb2_buffer_state state) unsigned long flags; unsigned int plane; - if (vb->state != VB2_BUF_STATE_ACTIVE) + if (WARN_ON(vb->state != VB2_BUF_STATE_ACTIVE)) return; - if (state != VB2_BUF_STATE_DONE && state != VB2_BUF_STATE_ERROR) - return; + if (!q->start_streaming_called) { + if (WARN_ON(state != VB2_BUF_STATE_QUEUED)) + state = VB2_BUF_STATE_QUEUED; + } else if (!WARN_ON(!q->start_streaming_called)) { + if (WARN_ON(state != VB2_BUF_STATE_DONE && + state != VB2_BUF_STATE_ERROR)) + state = VB2_BUF_STATE_ERROR; + } +#ifdef CONFIG_VIDEO_ADV_DEBUG + /* + * Although this is not a callback, it still does have to balance + * with the buf_queue op. So update this counter manually. + */ + vb->cnt_buf_done++; +#endif dprintk(4, "Done processing on buffer %d, state: %d\n", vb->v4l2_buf.index, state); /* sync buffers */ for (plane = 0; plane < vb->num_planes; ++plane) - call_memop(q, finish, vb->planes[plane].mem_priv); + call_memop(vb, finish, vb->planes[plane].mem_priv); /* Add the buffer to the done buffers list */ spin_lock_irqsave(&q->done_lock, flags); vb->state = state; - list_add_tail(&vb->done_entry, &q->done_list); - atomic_dec(&q->queued_count); + if (state != VB2_BUF_STATE_QUEUED) + list_add_tail(&vb->done_entry, &q->done_list); + atomic_dec(&q->owned_by_drv_count); spin_unlock_irqrestore(&q->done_lock, flags); + if (state == VB2_BUF_STATE_QUEUED) + return; + /* Inform any processes that may be waiting for buffers */ wake_up(&q->done_wq); } @@ -1025,9 +1198,31 @@ static void __fill_vb2_buffer(struct vb2_buffer *vb, const struct v4l2_buffer *b } - vb->v4l2_buf.field = b->field; - vb->v4l2_buf.timestamp = b->timestamp; + /* Zero flags that the vb2 core handles */ vb->v4l2_buf.flags = b->flags & ~V4L2_BUFFER_MASK_FLAGS; + if ((vb->vb2_queue->timestamp_flags & V4L2_BUF_FLAG_TIMESTAMP_MASK) != + V4L2_BUF_FLAG_TIMESTAMP_COPY || !V4L2_TYPE_IS_OUTPUT(b->type)) { + /* + * Non-COPY timestamps and non-OUTPUT queues will get + * their timestamp and timestamp source flags from the + * queue. + */ + vb->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + } + + if (V4L2_TYPE_IS_OUTPUT(b->type)) { + /* + * For output buffers mask out the timecode flag: + * this will be handled later in vb2_internal_qbuf(). + * The 'field' is valid metadata for this output buffer + * and so that needs to be copied here. + */ + vb->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TIMECODE; + vb->v4l2_buf.field = b->field; + } else { + /* Zero any output buffer flags as this is a capture buffer */ + vb->v4l2_buf.flags &= ~V4L2_BUFFER_OUT_FLAGS; + } } /** @@ -1041,6 +1236,7 @@ static int __qbuf_userptr(struct vb2_buffer *vb, const struct v4l2_buffer *b) unsigned int plane; int ret; int write = !V4L2_TYPE_IS_OUTPUT(q->type); + bool reacquired = vb->planes[0].mem_priv == NULL; /* Copy relevant information provided by the userspace */ __fill_vb2_buffer(vb, b, planes); @@ -1066,20 +1262,25 @@ static int __qbuf_userptr(struct vb2_buffer *vb, const struct v4l2_buffer *b) } /* Release previously acquired memory if present */ - if (vb->planes[plane].mem_priv) - call_memop(q, put_userptr, vb->planes[plane].mem_priv); + if (vb->planes[plane].mem_priv) { + if (!reacquired) { + reacquired = true; + call_vb_qop(vb, buf_cleanup, vb); + } + call_memop(vb, put_userptr, vb->planes[plane].mem_priv); + } vb->planes[plane].mem_priv = NULL; - vb->v4l2_planes[plane].m.userptr = 0; - vb->v4l2_planes[plane].length = 0; + memset(&vb->v4l2_planes[plane], 0, sizeof(struct v4l2_plane)); /* Acquire each plane's memory */ - mem_priv = call_memop(q, get_userptr, q->alloc_ctx[plane], + mem_priv = call_memop(vb, get_userptr, q->alloc_ctx[plane], planes[plane].m.userptr, planes[plane].length, write); if (IS_ERR_OR_NULL(mem_priv)) { dprintk(1, "qbuf: failed acquiring userspace " "memory for plane %d\n", plane); + fail_memop(vb, get_userptr); ret = mem_priv ? PTR_ERR(mem_priv) : -EINVAL; goto err; } @@ -1087,28 +1288,40 @@ static int __qbuf_userptr(struct vb2_buffer *vb, const struct v4l2_buffer *b) } /* - * Call driver-specific initialization on the newly acquired buffer, - * if provided. - */ - ret = call_qop(q, buf_init, vb); - if (ret) { - dprintk(1, "qbuf: buffer initialization failed\n"); - goto err; - } - - /* * Now that everything is in order, copy relevant information * provided by userspace. */ for (plane = 0; plane < vb->num_planes; ++plane) vb->v4l2_planes[plane] = planes[plane]; + if (reacquired) { + /* + * One or more planes changed, so we must call buf_init to do + * the driver-specific initialization on the newly acquired + * buffer, if provided. + */ + ret = call_vb_qop(vb, buf_init, vb); + if (ret) { + dprintk(1, "qbuf: buffer initialization failed\n"); + fail_vb_qop(vb, buf_init); + goto err; + } + } + + ret = call_vb_qop(vb, buf_prepare, vb); + if (ret) { + dprintk(1, "qbuf: buffer preparation failed\n"); + fail_vb_qop(vb, buf_prepare); + call_vb_qop(vb, buf_cleanup, vb); + goto err; + } + return 0; err: /* In case of errors, release planes that were already acquired */ for (plane = 0; plane < vb->num_planes; ++plane) { if (vb->planes[plane].mem_priv) - call_memop(q, put_userptr, vb->planes[plane].mem_priv); + call_memop(vb, put_userptr, vb->planes[plane].mem_priv); vb->planes[plane].mem_priv = NULL; vb->v4l2_planes[plane].m.userptr = 0; vb->v4l2_planes[plane].length = 0; @@ -1122,8 +1335,13 @@ err: */ static int __qbuf_mmap(struct vb2_buffer *vb, const struct v4l2_buffer *b) { + int ret; + __fill_vb2_buffer(vb, b, vb->v4l2_planes); - return 0; + ret = call_vb_qop(vb, buf_prepare, vb); + if (ret) + fail_vb_qop(vb, buf_prepare); + return ret; } /** @@ -1137,6 +1355,7 @@ static int __qbuf_dmabuf(struct vb2_buffer *vb, const struct v4l2_buffer *b) unsigned int plane; int ret; int write = !V4L2_TYPE_IS_OUTPUT(q->type); + bool reacquired = vb->planes[0].mem_priv == NULL; /* Copy relevant information provided by the userspace */ __fill_vb2_buffer(vb, b, planes); @@ -1172,15 +1391,21 @@ static int __qbuf_dmabuf(struct vb2_buffer *vb, const struct v4l2_buffer *b) dprintk(1, "qbuf: buffer for plane %d changed\n", plane); + if (!reacquired) { + reacquired = true; + call_vb_qop(vb, buf_cleanup, vb); + } + /* Release previously acquired memory if present */ - __vb2_plane_dmabuf_put(q, &vb->planes[plane]); + __vb2_plane_dmabuf_put(vb, &vb->planes[plane]); memset(&vb->v4l2_planes[plane], 0, sizeof(struct v4l2_plane)); /* Acquire each plane's memory */ - mem_priv = call_memop(q, attach_dmabuf, q->alloc_ctx[plane], + mem_priv = call_memop(vb, attach_dmabuf, q->alloc_ctx[plane], dbuf, planes[plane].length, write); if (IS_ERR(mem_priv)) { dprintk(1, "qbuf: failed to attach dmabuf\n"); + fail_memop(vb, attach_dmabuf); ret = PTR_ERR(mem_priv); dma_buf_put(dbuf); goto err; @@ -1195,32 +1420,44 @@ static int __qbuf_dmabuf(struct vb2_buffer *vb, const struct v4l2_buffer *b) * the buffer(s).. */ for (plane = 0; plane < vb->num_planes; ++plane) { - ret = call_memop(q, map_dmabuf, vb->planes[plane].mem_priv); + ret = call_memop(vb, map_dmabuf, vb->planes[plane].mem_priv); if (ret) { dprintk(1, "qbuf: failed to map dmabuf for plane %d\n", plane); + fail_memop(vb, map_dmabuf); goto err; } vb->planes[plane].dbuf_mapped = 1; } /* - * Call driver-specific initialization on the newly acquired buffer, - * if provided. - */ - ret = call_qop(q, buf_init, vb); - if (ret) { - dprintk(1, "qbuf: buffer initialization failed\n"); - goto err; - } - - /* * Now that everything is in order, copy relevant information * provided by userspace. */ for (plane = 0; plane < vb->num_planes; ++plane) vb->v4l2_planes[plane] = planes[plane]; + if (reacquired) { + /* + * Call driver-specific initialization on the newly acquired buffer, + * if provided. + */ + ret = call_vb_qop(vb, buf_init, vb); + if (ret) { + dprintk(1, "qbuf: buffer initialization failed\n"); + fail_vb_qop(vb, buf_init); + goto err; + } + } + + ret = call_vb_qop(vb, buf_prepare, vb); + if (ret) { + dprintk(1, "qbuf: buffer preparation failed\n"); + fail_vb_qop(vb, buf_prepare); + call_vb_qop(vb, buf_cleanup, vb); + goto err; + } + return 0; err: /* In case of errors, release planes that were already acquired */ @@ -1238,13 +1475,13 @@ static void __enqueue_in_driver(struct vb2_buffer *vb) unsigned int plane; vb->state = VB2_BUF_STATE_ACTIVE; - atomic_inc(&q->queued_count); + atomic_inc(&q->owned_by_drv_count); /* sync buffers */ for (plane = 0; plane < vb->num_planes; ++plane) - call_memop(q, prepare, vb->planes[plane].mem_priv); + call_memop(vb, prepare, vb->planes[plane].mem_priv); - q->ops->buf_queue(vb); + call_vb_qop(vb, buf_queue, vb); } static int __buf_prepare(struct vb2_buffer *vb, const struct v4l2_buffer *b) @@ -1261,6 +1498,10 @@ static int __buf_prepare(struct vb2_buffer *vb, const struct v4l2_buffer *b) } vb->state = VB2_BUF_STATE_PREPARING; + vb->v4l2_buf.timestamp.tv_sec = 0; + vb->v4l2_buf.timestamp.tv_usec = 0; + vb->v4l2_buf.sequence = 0; + switch (q->memory) { case V4L2_MEMORY_MMAP: ret = __qbuf_mmap(vb, b); @@ -1295,8 +1536,6 @@ static int __buf_prepare(struct vb2_buffer *vb, const struct v4l2_buffer *b) ret = -EINVAL; } - if (!ret) - ret = call_qop(q, buf_prepare, vb); if (ret) dprintk(1, "qbuf: buffer preparation failed: %d\n", ret); vb->state = ret ? VB2_BUF_STATE_DEQUEUED : VB2_BUF_STATE_PREPARED; @@ -1382,32 +1621,49 @@ EXPORT_SYMBOL_GPL(vb2_prepare_buf); * vb2_start_streaming() - Attempt to start streaming. * @q: videobuf2 queue * - * If there are not enough buffers, then retry_start_streaming is set to - * 1 and 0 is returned. The next time a buffer is queued and - * retry_start_streaming is 1, this function will be called again to - * retry starting the DMA engine. + * Attempt to start streaming. When this function is called there must be + * at least q->min_buffers_needed buffers queued up (i.e. the minimum + * number of buffers required for the DMA engine to function). If the + * @start_streaming op fails it is supposed to return all the driver-owned + * buffers back to vb2 in state QUEUED. Check if that happened and if + * not warn and reclaim them forcefully. */ static int vb2_start_streaming(struct vb2_queue *q) { + struct vb2_buffer *vb; int ret; - /* Tell the driver to start streaming */ - ret = call_qop(q, start_streaming, q, atomic_read(&q->queued_count)); - /* - * If there are not enough buffers queued to start streaming, then - * the start_streaming operation will return -ENOBUFS and you have to - * retry when the next buffer is queued. + * If any buffers were queued before streamon, + * we can now pass them to driver for processing. */ - if (ret == -ENOBUFS) { - dprintk(1, "qbuf: not enough buffers, retry when more buffers are queued.\n"); - q->retry_start_streaming = 1; + list_for_each_entry(vb, &q->queued_list, queued_entry) + __enqueue_in_driver(vb); + + /* Tell the driver to start streaming */ + ret = call_qop(q, start_streaming, q, + atomic_read(&q->owned_by_drv_count)); + q->start_streaming_called = ret == 0; + if (!ret) return 0; + + fail_qop(q, start_streaming); + dprintk(1, "qbuf: driver refused to start streaming\n"); + if (WARN_ON(atomic_read(&q->owned_by_drv_count))) { + unsigned i; + + /* + * Forcefully reclaim buffers if the driver did not + * correctly return them to vb2. + */ + for (i = 0; i < q->num_buffers; ++i) { + vb = q->bufs[i]; + if (vb->state == VB2_BUF_STATE_ACTIVE) + vb2_buffer_done(vb, VB2_BUF_STATE_QUEUED); + } + /* Must be zero now */ + WARN_ON(atomic_read(&q->owned_by_drv_count)); } - if (ret) - dprintk(1, "qbuf: driver refused to start streaming\n"); - else - q->retry_start_streaming = 0; return ret; } @@ -1420,11 +1676,6 @@ static int vb2_internal_qbuf(struct vb2_queue *q, struct v4l2_buffer *b) return ret; vb = q->bufs[b->index]; - if (vb->state != VB2_BUF_STATE_DEQUEUED) { - dprintk(1, "%s(): invalid buffer state %d\n", __func__, - vb->state); - return -EINVAL; - } switch (vb->state) { case VB2_BUF_STATE_DEQUEUED: @@ -1438,7 +1689,8 @@ static int vb2_internal_qbuf(struct vb2_queue *q, struct v4l2_buffer *b) dprintk(1, "qbuf: buffer still being prepared\n"); return -EINVAL; default: - dprintk(1, "qbuf: buffer already in use\n"); + dprintk(1, "%s(): invalid buffer state %d\n", __func__, + vb->state); return -EINVAL; } @@ -1447,19 +1699,39 @@ static int vb2_internal_qbuf(struct vb2_queue *q, struct v4l2_buffer *b) * dequeued in dqbuf. */ list_add_tail(&vb->queued_entry, &q->queued_list); + q->queued_count++; vb->state = VB2_BUF_STATE_QUEUED; + if (V4L2_TYPE_IS_OUTPUT(q->type)) { + /* + * For output buffers copy the timestamp if needed, + * and the timecode field and flag if needed. + */ + if ((q->timestamp_flags & V4L2_BUF_FLAG_TIMESTAMP_MASK) == + V4L2_BUF_FLAG_TIMESTAMP_COPY) + vb->v4l2_buf.timestamp = b->timestamp; + vb->v4l2_buf.flags |= b->flags & V4L2_BUF_FLAG_TIMECODE; + if (b->flags & V4L2_BUF_FLAG_TIMECODE) + vb->v4l2_buf.timecode = b->timecode; + } /* * If already streaming, give the buffer to driver for processing. * If not, the buffer will be given to driver on next streamon. */ - if (q->streaming) + if (q->start_streaming_called) __enqueue_in_driver(vb); /* Fill buffer information for the userspace */ __fill_v4l2_buffer(vb, b); - if (q->retry_start_streaming) { + /* + * If streamon has been called, and we haven't yet called + * start_streaming() since not enough buffers were queued, and + * we now have reached the minimum number of queued buffers, + * then we can finally call start_streaming(). + */ + if (q->streaming && !q->start_streaming_called && + q->queued_count >= q->min_buffers_needed) { ret = vb2_start_streaming(q); if (ret) return ret; @@ -1614,8 +1886,8 @@ int vb2_wait_for_all_buffers(struct vb2_queue *q) return -EINVAL; } - if (!q->retry_start_streaming) - wait_event(q->done_wq, !atomic_read(&q->queued_count)); + if (q->start_streaming_called) + wait_event(q->done_wq, !atomic_read(&q->owned_by_drv_count)); return 0; } EXPORT_SYMBOL_GPL(vb2_wait_for_all_buffers); @@ -1639,7 +1911,7 @@ static void __vb2_dqbuf(struct vb2_buffer *vb) for (i = 0; i < vb->num_planes; ++i) { if (!vb->planes[i].dbuf_mapped) continue; - call_memop(q, unmap_dmabuf, vb->planes[i].mem_priv); + call_memop(vb, unmap_dmabuf, vb->planes[i].mem_priv); vb->planes[i].dbuf_mapped = 0; } } @@ -1657,12 +1929,6 @@ static int vb2_internal_dqbuf(struct vb2_queue *q, struct v4l2_buffer *b, bool n if (ret < 0) return ret; - ret = call_qop(q, buf_finish, vb); - if (ret) { - dprintk(1, "dqbuf: buffer finish failed\n"); - return ret; - } - switch (vb->state) { case VB2_BUF_STATE_DONE: dprintk(3, "dqbuf: Returning done buffer\n"); @@ -1675,10 +1941,13 @@ static int vb2_internal_dqbuf(struct vb2_queue *q, struct v4l2_buffer *b, bool n return -EINVAL; } + call_vb_qop(vb, buf_finish, vb); + /* Fill buffer information for the userspace */ __fill_v4l2_buffer(vb, b); /* Remove from videobuf queue */ list_del(&vb->queued_entry); + q->queued_count--; /* go back to dequeued state */ __vb2_dqbuf(vb); @@ -1729,18 +1998,23 @@ static void __vb2_queue_cancel(struct vb2_queue *q) { unsigned int i; - if (q->retry_start_streaming) { - q->retry_start_streaming = 0; - q->streaming = 0; - } - /* * Tell driver to stop all transactions and release all queued * buffers. */ - if (q->streaming) + if (q->start_streaming_called) call_qop(q, stop_streaming, q); q->streaming = 0; + q->start_streaming_called = 0; + q->queued_count = 0; + + if (WARN_ON(atomic_read(&q->owned_by_drv_count))) { + for (i = 0; i < q->num_buffers; ++i) + if (q->bufs[i]->state == VB2_BUF_STATE_ACTIVE) + vb2_buffer_done(q->bufs[i], VB2_BUF_STATE_ERROR); + /* Must be zero now */ + WARN_ON(atomic_read(&q->owned_by_drv_count)); + } /* * Remove all buffers from videobuf's list... @@ -1751,19 +2025,31 @@ static void __vb2_queue_cancel(struct vb2_queue *q) * has not already dequeued before initiating cancel. */ INIT_LIST_HEAD(&q->done_list); - atomic_set(&q->queued_count, 0); + atomic_set(&q->owned_by_drv_count, 0); wake_up_all(&q->done_wq); /* * Reinitialize all buffers for next use. + * Make sure to call buf_finish for any queued buffers. Normally + * that's done in dqbuf, but that's not going to happen when we + * cancel the whole queue. Note: this code belongs here, not in + * __vb2_dqbuf() since in vb2_internal_dqbuf() there is a critical + * call to __fill_v4l2_buffer() after buf_finish(). That order can't + * be changed, so we can't move the buf_finish() to __vb2_dqbuf(). */ - for (i = 0; i < q->num_buffers; ++i) - __vb2_dqbuf(q->bufs[i]); + for (i = 0; i < q->num_buffers; ++i) { + struct vb2_buffer *vb = q->bufs[i]; + + if (vb->state != VB2_BUF_STATE_DEQUEUED) { + vb->state = VB2_BUF_STATE_PREPARED; + call_vb_qop(vb, buf_finish, vb); + } + __vb2_dqbuf(vb); + } } static int vb2_internal_streamon(struct vb2_queue *q, enum v4l2_buf_type type) { - struct vb2_buffer *vb; int ret; if (type != q->type) { @@ -1781,18 +2067,26 @@ static int vb2_internal_streamon(struct vb2_queue *q, enum v4l2_buf_type type) return -EINVAL; } + if (!q->num_buffers) { + dprintk(1, "streamon: no buffers have been allocated\n"); + return -EINVAL; + } + if (q->num_buffers < q->min_buffers_needed) { + dprintk(1, "streamon: need at least %u allocated buffers\n", + q->min_buffers_needed); + return -EINVAL; + } + /* - * If any buffers were queued before streamon, - * we can now pass them to driver for processing. + * Tell driver to start streaming provided sufficient buffers + * are available. */ - list_for_each_entry(vb, &q->queued_list, queued_entry) - __enqueue_in_driver(vb); - - /* Tell driver to start streaming. */ - ret = vb2_start_streaming(q); - if (ret) { - __vb2_queue_cancel(q); - return ret; + if (q->queued_count >= q->min_buffers_needed) { + ret = vb2_start_streaming(q); + if (ret) { + __vb2_queue_cancel(q); + return ret; + } } q->streaming = 1; @@ -1831,14 +2125,14 @@ static int vb2_internal_streamoff(struct vb2_queue *q, enum v4l2_buf_type type) return -EINVAL; } - if (!q->streaming) { - dprintk(3, "streamoff successful: not streaming\n"); - return 0; - } - /* * Cancel will pause streaming and remove all buffers from the driver * and videobuf, effectively returning control over them to userspace. + * + * Note that we do this even if q->streaming == 0: if you prepare or + * queue buffers, and then call streamoff without ever having called + * streamon, you would still expect those buffers to be returned to + * their normal dequeued state. */ __vb2_queue_cancel(q); @@ -1950,10 +2244,11 @@ int vb2_expbuf(struct vb2_queue *q, struct v4l2_exportbuffer *eb) vb_plane = &vb->planes[eb->plane]; - dbuf = call_memop(q, get_dmabuf, vb_plane->mem_priv, eb->flags & O_ACCMODE); + dbuf = call_memop(vb, get_dmabuf, vb_plane->mem_priv, eb->flags & O_ACCMODE); if (IS_ERR_OR_NULL(dbuf)) { dprintk(1, "Failed to export buffer %d, plane %d\n", eb->index, eb->plane); + fail_memop(vb, get_dmabuf); return -EINVAL; } @@ -2045,9 +2340,11 @@ int vb2_mmap(struct vb2_queue *q, struct vm_area_struct *vma) return -EINVAL; } - ret = call_memop(q, mmap, vb->planes[plane].mem_priv, vma); - if (ret) + ret = call_memop(vb, mmap, vb->planes[plane].mem_priv, vma); + if (ret) { + fail_memop(vb, mmap); return ret; + } dprintk(3, "Buffer %d, plane %d successfully mapped\n", buffer, plane); return 0; @@ -2200,11 +2497,14 @@ int vb2_queue_init(struct vb2_queue *q) WARN_ON(!q->io_modes) || WARN_ON(!q->ops->queue_setup) || WARN_ON(!q->ops->buf_queue) || - WARN_ON(q->timestamp_type & ~V4L2_BUF_FLAG_TIMESTAMP_MASK)) + WARN_ON(q->timestamp_flags & + ~(V4L2_BUF_FLAG_TIMESTAMP_MASK | + V4L2_BUF_FLAG_TSTAMP_SRC_MASK))) return -EINVAL; /* Warn that the driver should choose an appropriate timestamp type */ - WARN_ON(q->timestamp_type == V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN); + WARN_ON((q->timestamp_flags & V4L2_BUF_FLAG_TIMESTAMP_MASK) == + V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN); INIT_LIST_HEAD(&q->queued_list); INIT_LIST_HEAD(&q->done_list); @@ -2251,6 +2551,22 @@ struct vb2_fileio_buf { /** * struct vb2_fileio_data - queue context used by file io emulator * + * @cur_index: the index of the buffer currently being read from or + * written to. If equal to q->num_buffers then a new buffer + * must be dequeued. + * @initial_index: in the read() case all buffers are queued up immediately + * in __vb2_init_fileio() and __vb2_perform_fileio() just cycles + * buffers. However, in the write() case no buffers are initially + * queued, instead whenever a buffer is full it is queued up by + * __vb2_perform_fileio(). Only once all available buffers have + * been queued up will __vb2_perform_fileio() start to dequeue + * buffers. This means that initially __vb2_perform_fileio() + * needs to know what buffer index to use when it is queuing up + * the buffers for the first time. That initial index is stored + * in this field. Once it is equal to q->num_buffers all + * available buffers have been queued and __vb2_perform_fileio() + * should start the normal dequeue/queue cycle. + * * vb2 provides a compatibility layer and emulator of file io (read and * write) calls on top of streaming API. For proper operation it required * this structure to save the driver state between each call of the read @@ -2260,7 +2576,8 @@ struct vb2_fileio_data { struct v4l2_requestbuffers req; struct v4l2_buffer b; struct vb2_fileio_buf bufs[VIDEO_MAX_FRAME]; - unsigned int index; + unsigned int cur_index; + unsigned int initial_index; unsigned int q_count; unsigned int dq_count; unsigned int flags; @@ -2280,9 +2597,9 @@ static int __vb2_init_fileio(struct vb2_queue *q, int read) /* * Sanity check */ - if ((read && !(q->io_modes & VB2_READ)) || - (!read && !(q->io_modes & VB2_WRITE))) - BUG(); + if (WARN_ON((read && !(q->io_modes & VB2_READ)) || + (!read && !(q->io_modes & VB2_WRITE)))) + return -EINVAL; /* * Check if device supports mapping buffers to kernel virtual space. @@ -2360,7 +2677,12 @@ static int __vb2_init_fileio(struct vb2_queue *q, int read) goto err_reqbufs; fileio->bufs[i].queued = 1; } - fileio->index = q->num_buffers; + /* + * All buffers have been queued, so mark that by setting + * initial_index to q->num_buffers + */ + fileio->initial_index = q->num_buffers; + fileio->cur_index = q->num_buffers; } /* @@ -2439,7 +2761,7 @@ static size_t __vb2_perform_fileio(struct vb2_queue *q, char __user *data, size_ /* * Check if we need to dequeue the buffer. */ - index = fileio->index; + index = fileio->cur_index; if (index >= q->num_buffers) { /* * Call vb2_dqbuf to get buffer back. @@ -2453,7 +2775,7 @@ static size_t __vb2_perform_fileio(struct vb2_queue *q, char __user *data, size_ return ret; fileio->dq_count += 1; - index = fileio->b.index; + fileio->cur_index = index = fileio->b.index; buf = &fileio->bufs[index]; /* @@ -2529,8 +2851,20 @@ static size_t __vb2_perform_fileio(struct vb2_queue *q, char __user *data, size_ buf->queued = 1; buf->size = vb2_plane_size(q->bufs[index], 0); fileio->q_count += 1; - if (fileio->index < q->num_buffers) - fileio->index++; + /* + * If we are queuing up buffers for the first time, then + * increase initial_index by one. + */ + if (fileio->initial_index < q->num_buffers) + fileio->initial_index++; + /* + * The next buffer to use is either a buffer that's going to be + * queued for the first time (initial_index < q->num_buffers) + * or it is equal to q->num_buffers, meaning that the next + * time we need to dequeue a buffer since we've now queued up + * all the 'first time' buffers. + */ + fileio->cur_index = fileio->initial_index; } /* |
