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-rw-r--r--drivers/gpu/drm/radeon/Kconfig1
-rw-r--r--drivers/gpu/drm/radeon/Makefile43
-rw-r--r--drivers/gpu/drm/radeon/atombios.h11
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c105
-rw-r--r--drivers/gpu/drm/radeon/avivod.h69
-rw-r--r--drivers/gpu/drm/radeon/mkregtable.c720
-rw-r--r--drivers/gpu/drm/radeon/r100.c1232
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h124
-rw-r--r--drivers/gpu/drm/radeon/r100d.h607
-rw-r--r--drivers/gpu/drm/radeon/r200.c456
-rw-r--r--drivers/gpu/drm/radeon/r300.c556
-rw-r--r--drivers/gpu/drm/radeon/r300.h36
-rw-r--r--drivers/gpu/drm/radeon/r300d.h101
-rw-r--r--drivers/gpu/drm/radeon/r420.c301
-rw-r--r--drivers/gpu/drm/radeon/r420d.h249
-rw-r--r--drivers/gpu/drm/radeon/r520.c6
-rw-r--r--drivers/gpu/drm/radeon/r600.c1802
-rw-r--r--drivers/gpu/drm/radeon/r600_blit.c850
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c805
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_shaders.c1072
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_shaders.h14
-rw-r--r--drivers/gpu/drm/radeon/r600_cp.c541
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c657
-rw-r--r--drivers/gpu/drm/radeon/r600_microcode.h23297
-rw-r--r--drivers/gpu/drm/radeon/r600d.h662
-rw-r--r--drivers/gpu/drm/radeon/radeon.h269
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h240
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c171
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c58
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c480
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c151
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c423
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c101
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c23
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h151
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c137
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c674
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c49
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_ioc32.c15
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq.c18
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq_kms.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c25
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c85
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c368
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_tv.c904
-rw-r--r--drivers/gpu/drm/radeon/radeon_microcode.h1844
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h74
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_reg.h79
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c143
-rw-r--r--drivers/gpu/drm/radeon/radeon_share.h39
-rw-r--r--drivers/gpu/drm/radeon/radeon_state.c23
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c96
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r100105
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r200184
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r300729
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rn5030
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rs600729
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rv515486
-rw-r--r--drivers/gpu/drm/radeon/rs400.c56
-rw-r--r--drivers/gpu/drm/radeon/rs600.c106
-rw-r--r--drivers/gpu/drm/radeon/rs690.c4
-rw-r--r--drivers/gpu/drm/radeon/rs780.c102
-rw-r--r--drivers/gpu/drm/radeon/rv515.c524
-rw-r--r--drivers/gpu/drm/radeon/rv515d.h (renamed from drivers/gpu/drm/radeon/rv515r.h)56
-rw-r--r--drivers/gpu/drm/radeon/rv770.c1050
-rw-r--r--drivers/gpu/drm/radeon/rv770d.h341
71 files changed, 17508 insertions, 27985 deletions
diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index 2168d67..5982321 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -1,7 +1,6 @@
config DRM_RADEON_KMS
bool "Enable modesetting on radeon by default"
depends on DRM_RADEON
- select DRM_TTM
help
Choose this option if you want kernel modesetting enabled by default,
and you have a new enough userspace to support this. Running old
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 013d380..09a28923 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -3,18 +3,53 @@
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
ccflags-y := -Iinclude/drm
+
+hostprogs-y := mkregtable
+
+quiet_cmd_mkregtable = MKREGTABLE $@
+ cmd_mkregtable = $(obj)/mkregtable $< > $@
+
+$(obj)/rn50_reg_safe.h: $(src)/reg_srcs/rn50 $(obj)/mkregtable
+ $(call if_changed,mkregtable)
+
+$(obj)/r100_reg_safe.h: $(src)/reg_srcs/r100 $(obj)/mkregtable
+ $(call if_changed,mkregtable)
+
+$(obj)/r200_reg_safe.h: $(src)/reg_srcs/r200 $(obj)/mkregtable
+ $(call if_changed,mkregtable)
+
+$(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable
+ $(call if_changed,mkregtable)
+
+$(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable
+ $(call if_changed,mkregtable)
+
+$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable
+ $(call if_changed,mkregtable)
+
+$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h
+
+$(obj)/r200.o: $(obj)/r200_reg_safe.h
+
+$(obj)/rv515.o: $(obj)/rv515_reg_safe.h
+
+$(obj)/r300.o: $(obj)/r300_reg_safe.h
+
+$(obj)/rs600.o: $(obj)/rs600_reg_safe.h
+
radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
radeon_irq.o r300_cmdbuf.o r600_cp.o
-
-radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \
+# add KMS driver
+radeon-y += radeon_device.o radeon_kms.o \
radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \
atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \
radeon_legacy_crtc.o radeon_legacy_encoders.o radeon_connectors.o \
radeon_encoders.o radeon_display.o radeon_cursor.o radeon_i2c.o \
radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \
radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
- rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \
- radeon_test.o
+ rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \
+ r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
+ r600_blit_kms.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index cf67928..5d40208 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -2374,6 +2374,17 @@ typedef struct _ATOM_ANALOG_TV_INFO {
ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];
} ATOM_ANALOG_TV_INFO;
+#define MAX_SUPPORTED_TV_TIMING_V1_2 3
+
+typedef struct _ATOM_ANALOG_TV_INFO_V1_2 {
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ UCHAR ucTV_SupportedStandard;
+ UCHAR ucTV_BootUpDefaultStandard;
+ UCHAR ucExt_TV_ASIC_ID;
+ UCHAR ucExt_TV_ASIC_SlaveAddr;
+ ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];
+} ATOM_ANALOG_TV_INFO_V1_2;
+
/**************************************************************************/
/* VRAM usage and their defintions */
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 74d034f..6a01592 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -31,6 +31,10 @@
#include "atom.h"
#include "atom-bits.h"
+/* evil but including atombios.h is much worse */
+bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
+ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
+ int32_t *pixel_clock);
static void atombios_overscan_setup(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
@@ -89,17 +93,32 @@ static void atombios_scaler_setup(struct drm_crtc *crtc)
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
ENABLE_SCALER_PS_ALLOCATION args;
int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
+
/* fixme - fill in enc_priv for atom dac */
enum radeon_tv_std tv_std = TV_STD_NTSC;
+ bool is_tv = false, is_cv = false;
+ struct drm_encoder *encoder;
if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
return;
+ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ /* find tv std */
+ if (encoder->crtc == crtc) {
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
+ struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
+ tv_std = tv_dac->tv_std;
+ is_tv = true;
+ }
+ }
+ }
+
memset(&args, 0, sizeof(args));
args.ucScaler = radeon_crtc->crtc_id;
- if (radeon_crtc->devices & (ATOM_DEVICE_TV_SUPPORT)) {
+ if (is_tv) {
switch (tv_std) {
case TV_STD_NTSC:
default:
@@ -128,7 +147,7 @@ static void atombios_scaler_setup(struct drm_crtc *crtc)
break;
}
args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
- } else if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT)) {
+ } else if (is_cv) {
args.ucTVStandard = ATOM_TV_CV;
args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
} else {
@@ -151,9 +170,9 @@ static void atombios_scaler_setup(struct drm_crtc *crtc)
}
}
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
- if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)
- && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) {
- atom_rv515_force_tv_scaler(rdev);
+ if ((is_tv || is_cv)
+ && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
+ atom_rv515_force_tv_scaler(rdev, radeon_crtc);
}
}
@@ -370,6 +389,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
pll_flags |= RADEON_PLL_USE_REF_DIV;
}
radeon_encoder = to_radeon_encoder(encoder);
+ break;
}
}
@@ -468,6 +488,11 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
}
switch (crtc->fb->bits_per_pixel) {
+ case 8:
+ fb_format =
+ AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
+ AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
+ break;
case 15:
fb_format =
AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
@@ -551,42 +576,68 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
struct radeon_device *rdev = dev->dev_private;
struct drm_encoder *encoder;
SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
+ int need_tv_timings = 0;
+ bool ret;
/* TODO color tiling */
memset(&crtc_timing, 0, sizeof(crtc_timing));
- /* TODO tv */
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
-
+ /* find tv std */
+ if (encoder->crtc == crtc) {
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+
+ if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
+ struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
+ if (tv_dac) {
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J ||
+ tv_dac->tv_std == TV_STD_PAL_M)
+ need_tv_timings = 1;
+ else
+ need_tv_timings = 2;
+ break;
+ }
+ }
+ }
}
crtc_timing.ucCRTC = radeon_crtc->crtc_id;
- crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
- crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
- crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
- crtc_timing.usH_SyncWidth =
- adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
+ if (need_tv_timings) {
+ ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1,
+ &crtc_timing, &adjusted_mode->clock);
+ if (ret == false)
+ need_tv_timings = 0;
+ }
- crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
- crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
- crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
- crtc_timing.usV_SyncWidth =
- adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
+ if (!need_tv_timings) {
+ crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
+ crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
+ crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
+ crtc_timing.usH_SyncWidth =
+ adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
- if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
- crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
+ crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
+ crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
+ crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
+ crtc_timing.usV_SyncWidth =
+ adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
- if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
- crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
- if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
- crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
- if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
- crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
- if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
- crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
+ }
atombios_crtc_set_pll(crtc, adjusted_mode);
atombios_crtc_set_timing(crtc, &crtc_timing);
diff --git a/drivers/gpu/drm/radeon/avivod.h b/drivers/gpu/drm/radeon/avivod.h
new file mode 100644
index 0000000..e2b92c4
--- /dev/null
+++ b/drivers/gpu/drm/radeon/avivod.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2009 Advanced Micro Devices, Inc.
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ * Alex Deucher
+ * Jerome Glisse
+ */
+#ifndef AVIVOD_H
+#define AVIVOD_H
+
+
+#define D1CRTC_CONTROL 0x6080
+#define CRTC_EN (1 << 0)
+#define D1CRTC_UPDATE_LOCK 0x60E8
+#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
+#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
+
+#define D2CRTC_CONTROL 0x6880
+#define D2CRTC_UPDATE_LOCK 0x68E8
+#define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
+#define D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
+
+#define D1VGA_CONTROL 0x0330
+#define DVGA_CONTROL_MODE_ENABLE (1 << 0)
+#define DVGA_CONTROL_TIMING_SELECT (1 << 8)
+#define DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9)
+#define DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10)
+#define DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16)
+#define DVGA_CONTROL_ROTATE (1 << 24)
+#define D2VGA_CONTROL 0x0338
+
+#define VGA_HDP_CONTROL 0x328
+#define VGA_MEM_PAGE_SELECT_EN (1 << 0)
+#define VGA_MEMORY_DISABLE (1 << 4)
+#define VGA_RBBM_LOCK_DISABLE (1 << 8)
+#define VGA_SOFT_RESET (1 << 16)
+#define VGA_MEMORY_BASE_ADDRESS 0x0310
+#define VGA_RENDER_CONTROL 0x0300
+#define VGA_VSTATUS_CNTL_MASK 0x00030000
+
+/* AVIVO disable VGA rendering */
+static inline void radeon_avivo_vga_render_disable(struct radeon_device *rdev)
+{
+ u32 vga_render;
+ vga_render = RREG32(VGA_RENDER_CONTROL);
+ vga_render &= ~VGA_VSTATUS_CNTL_MASK;
+ WREG32(VGA_RENDER_CONTROL, vga_render);
+}
+
+#endif
diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c
new file mode 100644
index 0000000..fb211e5
--- /dev/null
+++ b/drivers/gpu/drm/radeon/mkregtable.c
@@ -0,0 +1,720 @@
+/* utility to create the register check tables
+ * this includes inlined list.h safe for userspace.
+ *
+ * Copyright 2009 Jerome Glisse
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Authors:
+ * Jerome Glisse
+ * Dave Airlie
+ */
+
+#include <sys/types.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <regex.h>
+#include <libgen.h>
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @ptr: the pointer to the member.
+ * @type: the type of the container struct this is embedded in.
+ * @member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({ \
+ const typeof(((type *)0)->member)*__mptr = (ptr); \
+ (type *)((char *)__mptr - offsetof(type, member)); })
+
+/*
+ * Simple doubly linked list implementation.
+ *
+ * Some of the internal functions ("__xxx") are useful when
+ * manipulating whole lists rather than single entries, as
+ * sometimes we already know the next/prev entries and we can
+ * generate better code by using them directly rather than
+ * using the generic single-entry routines.
+ */
+
+struct list_head {
+ struct list_head *next, *prev;
+};
+
+#define LIST_HEAD_INIT(name) { &(name), &(name) }
+
+#define LIST_HEAD(name) \
+ struct list_head name = LIST_HEAD_INIT(name)
+
+static inline void INIT_LIST_HEAD(struct list_head *list)
+{
+ list->next = list;
+ list->prev = list;
+}
+
+/*
+ * Insert a new entry between two known consecutive entries.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+#ifndef CONFIG_DEBUG_LIST
+static inline void __list_add(struct list_head *new,
+ struct list_head *prev, struct list_head *next)
+{
+ next->prev = new;
+ new->next = next;
+ new->prev = prev;
+ prev->next = new;
+}
+#else
+extern void __list_add(struct list_head *new,
+ struct list_head *prev, struct list_head *next);
+#endif
+
+/**
+ * list_add - add a new entry
+ * @new: new entry to be added
+ * @head: list head to add it after
+ *
+ * Insert a new entry after the specified head.
+ * This is good for implementing stacks.
+ */
+static inline void list_add(struct list_head *new, struct list_head *head)
+{
+ __list_add(new, head, head->next);
+}
+
+/**
+ * list_add_tail - add a new entry
+ * @new: new entry to be added
+ * @head: list head to add it before
+ *
+ * Insert a new entry before the specified head.
+ * This is useful for implementing queues.
+ */
+static inline void list_add_tail(struct list_head *new, struct list_head *head)
+{
+ __list_add(new, head->prev, head);
+}
+
+/*
+ * Delete a list entry by making the prev/next entries
+ * point to each other.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+static inline void __list_del(struct list_head *prev, struct list_head *next)
+{
+ next->prev = prev;
+ prev->next = next;
+}
+
+/**
+ * list_del - deletes entry from list.
+ * @entry: the element to delete from the list.
+ * Note: list_empty() on entry does not return true after this, the entry is
+ * in an undefined state.
+ */
+#ifndef CONFIG_DEBUG_LIST
+static inline void list_del(struct list_head *entry)
+{
+ __list_del(entry->prev, entry->next);
+ entry->next = (void *)0xDEADBEEF;
+ entry->prev = (void *)0xBEEFDEAD;
+}
+#else
+extern void list_del(struct list_head *entry);
+#endif
+
+/**
+ * list_replace - replace old entry by new one
+ * @old : the element to be replaced
+ * @new : the new element to insert
+ *
+ * If @old was empty, it will be overwritten.
+ */
+static inline void list_replace(struct list_head *old, struct list_head *new)
+{
+ new->next = old->next;
+ new->next->prev = new;
+ new->prev = old->prev;
+ new->prev->next = new;
+}
+
+static inline void list_replace_init(struct list_head *old,
+ struct list_head *new)
+{
+ list_replace(old, new);
+ INIT_LIST_HEAD(old);
+}
+
+/**
+ * list_del_init - deletes entry from list and reinitialize it.
+ * @entry: the element to delete from the list.
+ */
+static inline void list_del_init(struct list_head *entry)
+{
+ __list_del(entry->prev, entry->next);
+ INIT_LIST_HEAD(entry);
+}
+
+/**
+ * list_move - delete from one list and add as another's head
+ * @list: the entry to move
+ * @head: the head that will precede our entry
+ */
+static inline void list_move(struct list_head *list, struct list_head *head)
+{
+ __list_del(list->prev, list->next);
+ list_add(list, head);
+}
+
+/**
+ * list_move_tail - delete from one list and add as another's tail
+ * @list: the entry to move
+ * @head: the head that will follow our entry
+ */
+static inline void list_move_tail(struct list_head *list,
+ struct list_head *head)
+{
+ __list_del(list->prev, list->next);
+ list_add_tail(list, head);
+}
+
+/**
+ * list_is_last - tests whether @list is the last entry in list @head
+ * @list: the entry to test
+ * @head: the head of the list
+ */
+static inline int list_is_last(const struct list_head *list,
+ const struct list_head *head)
+{
+ return list->next == head;
+}
+
+/**
+ * list_empty - tests whether a list is empty
+ * @head: the list to test.
+ */
+static inline int list_empty(const struct list_head *head)
+{
+ return head->next == head;
+}
+
+/**
+ * list_empty_careful - tests whether a list is empty and not being modified
+ * @head: the list to test
+ *
+ * Description:
+ * tests whether a list is empty _and_ checks that no other CPU might be
+ * in the process of modifying either member (next or prev)
+ *
+ * NOTE: using list_empty_careful() without synchronization
+ * can only be safe if the only activity that can happen
+ * to the list entry is list_del_init(). Eg. it cannot be used
+ * if another CPU could re-list_add() it.
+ */
+static inline int list_empty_careful(const struct list_head *head)
+{
+ struct list_head *next = head->next;
+ return (next == head) && (next == head->prev);
+}
+
+/**
+ * list_is_singular - tests whether a list has just one entry.
+ * @head: the list to test.
+ */
+static inline int list_is_singular(const struct list_head *head)
+{
+ return !list_empty(head) && (head->next == head->prev);
+}
+
+static inline void __list_cut_position(struct list_head *list,
+ struct list_head *head,
+ struct list_head *entry)
+{
+ struct list_head *new_first = entry->next;
+ list->next = head->next;
+ list->next->prev = list;
+ list->prev = entry;
+ entry->next = list;
+ head->next = new_first;
+ new_first->prev = head;
+}
+
+/**
+ * list_cut_position - cut a list into two
+ * @list: a new list to add all removed entries
+ * @head: a list with entries
+ * @entry: an entry within head, could be the head itself
+ * and if so we won't cut the list
+ *
+ * This helper moves the initial part of @head, up to and
+ * including @entry, from @head to @list. You should
+ * pass on @entry an element you know is on @head. @list
+ * should be an empty list or a list you do not care about
+ * losing its data.
+ *
+ */
+static inline void list_cut_position(struct list_head *list,
+ struct list_head *head,
+ struct list_head *entry)
+{
+ if (list_empty(head))
+ return;
+ if (list_is_singular(head) && (head->next != entry && head != entry))
+ return;
+ if (entry == head)
+ INIT_LIST_HEAD(list);
+ else
+ __list_cut_position(list, head, entry);
+}
+
+static inline void __list_splice(const struct list_head *list,
+ struct list_head *prev, struct list_head *next)
+{
+ struct list_head *first = list->next;
+ struct list_head *last = list->prev;
+
+ first->prev = prev;
+ prev->next = first;
+
+ last->next = next;
+ next->prev = last;
+}
+
+/**
+ * list_splice - join two lists, this is designed for stacks
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ */
+static inline void list_splice(const struct list_head *list,
+ struct list_head *head)
+{
+ if (!list_empty(list))
+ __list_splice(list, head, head->next);
+}
+
+/**
+ * list_splice_tail - join two lists, each list being a queue
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ */
+static inline void list_splice_tail(struct list_head *list,
+ struct list_head *head)
+{
+ if (!list_empty(list))
+ __list_splice(list, head->prev, head);
+}
+
+/**
+ * list_splice_init - join two lists and reinitialise the emptied list.
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ *
+ * The list at @list is reinitialised
+ */
+static inline void list_splice_init(struct list_head *list,
+ struct list_head *head)
+{
+ if (!list_empty(list)) {
+ __list_splice(list, head, head->next);
+ INIT_LIST_HEAD(list);
+ }
+}
+
+/**
+ * list_splice_tail_init - join two lists and reinitialise the emptied list
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ *
+ * Each of the lists is a queue.
+ * The list at @list is reinitialised
+ */
+static inline void list_splice_tail_init(struct list_head *list,
+ struct list_head *head)
+{
+ if (!list_empty(list)) {
+ __list_splice(list, head->prev, head);
+ INIT_LIST_HEAD(list);
+ }
+}
+
+/**
+ * list_entry - get the struct for this entry
+ * @ptr: the &struct list_head pointer.
+ * @type: the type of the struct this is embedded in.
+ * @member: the name of the list_struct within the struct.
+ */
+#define list_entry(ptr, type, member) \
+ container_of(ptr, type, member)
+
+/**
+ * list_first_entry - get the first element from a list
+ * @ptr: the list head to take the element from.
+ * @type: the type of the struct this is embedded in.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define list_first_entry(ptr, type, member) \
+ list_entry((ptr)->next, type, member)
+
+/**
+ * list_for_each - iterate over a list
+ * @pos: the &struct list_head to use as a loop cursor.
+ * @head: the head for your list.
+ */
+#define list_for_each(pos, head) \
+ for (pos = (head)->next; prefetch(pos->next), pos != (head); \
+ pos = pos->next)
+
+/**
+ * __list_for_each - iterate over a list
+ * @pos: the &struct list_head to use as a loop cursor.
+ * @head: the head for your list.
+ *
+ * This variant differs from list_for_each() in that it's the
+ * simplest possible list iteration code, no prefetching is done.
+ * Use this for code that knows the list to be very short (empty
+ * or 1 entry) most of the time.
+ */
+#define __list_for_each(pos, head) \
+ for (pos = (head)->next; pos != (head); pos = pos->next)
+
+/**
+ * list_for_each_prev - iterate over a list backwards
+ * @pos: the &struct list_head to use as a loop cursor.
+ * @head: the head for your list.
+ */
+#define list_for_each_prev(pos, head) \
+ for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \
+ pos = pos->prev)
+
+/**
+ * list_for_each_safe - iterate over a list safe against removal of list entry
+ * @pos: the &struct list_head to use as a loop cursor.
+ * @n: another &struct list_head to use as temporary storage
+ * @head: the head for your list.
+ */
+#define list_for_each_safe(pos, n, head) \
+ for (pos = (head)->next, n = pos->next; pos != (head); \
+ pos = n, n = pos->next)
+
+/**
+ * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry
+ * @pos: the &struct list_head to use as a loop cursor.
+ * @n: another &struct list_head to use as temporary storage
+ * @head: the head for your list.
+ */
+#define list_for_each_prev_safe(pos, n, head) \
+ for (pos = (head)->prev, n = pos->prev; \
+ prefetch(pos->prev), pos != (head); \
+ pos = n, n = pos->prev)
+
+/**
+ * list_for_each_entry - iterate over list of given type
+ * @pos: the type * to use as a loop cursor.
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define list_for_each_entry(pos, head, member) \
+ for (pos = list_entry((head)->next, typeof(*pos), member); \
+ &pos->member != (head); \
+ pos = list_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_reverse - iterate backwards over list of given type.
+ * @pos: the type * to use as a loop cursor.
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define list_for_each_entry_reverse(pos, head, member) \
+ for (pos = list_entry((head)->prev, typeof(*pos), member); \
+ prefetch(pos->member.prev), &pos->member != (head); \
+ pos = list_entry(pos->member.prev, typeof(*pos), member))
+
+/**
+ * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue()
+ * @pos: the type * to use as a start point
+ * @head: the head of the list
+ * @member: the name of the list_struct within the struct.
+ *
+ * Prepares a pos entry for use as a start point in list_for_each_entry_continue().
+ */
+#define list_prepare_entry(pos, head, member) \
+ ((pos) ? : list_entry(head, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_continue - continue iteration over list of given type
+ * @pos: the type * to use as a loop cursor.
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Continue to iterate over list of given type, continuing after
+ * the current position.
+ */
+#define list_for_each_entry_continue(pos, head, member) \
+ for (pos = list_entry(pos->member.next, typeof(*pos), member); \
+ prefetch(pos->member.next), &pos->member != (head); \
+ pos = list_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_continue_reverse - iterate backwards from the given point
+ * @pos: the type * to use as a loop cursor.
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Start to iterate over list of given type backwards, continuing after
+ * the current position.
+ */
+#define list_for_each_entry_continue_reverse(pos, head, member) \
+ for (pos = list_entry(pos->member.prev, typeof(*pos), member); \
+ prefetch(pos->member.prev), &pos->member != (head); \
+ pos = list_entry(pos->member.prev, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_from - iterate over list of given type from the current point
+ * @pos: the type * to use as a loop cursor.
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Iterate over list of given type, continuing from current position.
+ */
+#define list_for_each_entry_from(pos, head, member) \
+ for (; prefetch(pos->member.next), &pos->member != (head); \
+ pos = list_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @pos: the type * to use as a loop cursor.
+ * @n: another type * to use as temporary storage
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define list_for_each_entry_safe(pos, n, head, member) \
+ for (pos = list_entry((head)->next, typeof(*pos), member), \
+ n = list_entry(pos->member.next, typeof(*pos), member); \
+ &pos->member != (head); \
+ pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_safe_continue
+ * @pos: the type * to use as a loop cursor.
+ * @n: another type * to use as temporary storage
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Iterate over list of given type, continuing after current point,
+ * safe against removal of list entry.
+ */
+#define list_for_each_entry_safe_continue(pos, n, head, member) \
+ for (pos = list_entry(pos->member.next, typeof(*pos), member), \
+ n = list_entry(pos->member.next, typeof(*pos), member); \
+ &pos->member != (head); \
+ pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_safe_from
+ * @pos: the type * to use as a loop cursor.
+ * @n: another type * to use as temporary storage
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Iterate over list of given type from current point, safe against
+ * removal of list entry.
+ */
+#define list_for_each_entry_safe_from(pos, n, head, member) \
+ for (n = list_entry(pos->member.next, typeof(*pos), member); \
+ &pos->member != (head); \
+ pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_safe_reverse
+ * @pos: the type * to use as a loop cursor.
+ * @n: another type * to use as temporary storage
+ * @head: the head for your list.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Iterate backwards over list of given type, safe against removal
+ * of list entry.
+ */
+#define list_for_each_entry_safe_reverse(pos, n, head, member) \
+ for (pos = list_entry((head)->prev, typeof(*pos), member), \
+ n = list_entry(pos->member.prev, typeof(*pos), member); \
+ &pos->member != (head); \
+ pos = n, n = list_entry(n->member.prev, typeof(*n), member))
+
+struct offset {
+ struct list_head list;
+ unsigned offset;
+};
+
+struct table {
+ struct list_head offsets;
+ unsigned offset_max;
+ unsigned nentry;
+ unsigned *table;
+ char *gpu_prefix;
+};
+
+struct offset *offset_new(unsigned o)
+{
+ struct offset *offset;
+
+ offset = (struct offset *)malloc(sizeof(struct offset));
+ if (offset) {
+ INIT_LIST_HEAD(&offset->list);
+ offset->offset = o;
+ }
+ return offset;
+}
+
+void table_offset_add(struct table *t, struct offset *offset)
+{
+ list_add_tail(&offset->list, &t->offsets);
+}
+
+void table_init(struct table *t)
+{
+ INIT_LIST_HEAD(&t->offsets);
+ t->offset_max = 0;
+ t->nentry = 0;
+ t->table = NULL;
+}
+
+void table_print(struct table *t)
+{
+ unsigned nlloop, i, j, n, c, id;
+
+ nlloop = (t->nentry + 3) / 4;
+ c = t->nentry;
+ printf("static const unsigned %s_reg_safe_bm[%d] = {\n", t->gpu_prefix,
+ t->nentry);
+ for (i = 0, id = 0; i < nlloop; i++) {
+ n = 4;
+ if (n > c)
+ n = c;
+ c -= n;
+ for (j = 0; j < n; j++) {
+ if (j == 0)
+ printf("\t");
+ else
+ printf(" ");
+ printf("0x%08X,", t->table[id++]);
+ }
+ printf("\n");
+ }
+ printf("};\n");
+}
+
+int table_build(struct table *t)
+{
+ struct offset *offset;
+ unsigned i, m;
+
+ t->nentry = ((t->offset_max >> 2) + 31) / 32;
+ t->table = (unsigned *)malloc(sizeof(unsigned) * t->nentry);
+ if (t->table == NULL)
+ return -1;
+ memset(t->table, 0xff, sizeof(unsigned) * t->nentry);
+ list_for_each_entry(offset, &t->offsets, list) {
+ i = (offset->offset >> 2) / 32;
+ m = (offset->offset >> 2) & 31;
+ m = 1 << m;
+ t->table[i] ^= m;
+ }
+ return 0;
+}
+
+static char gpu_name[10];
+int parser_auth(struct table *t, const char *filename)
+{
+ FILE *file;
+ regex_t mask_rex;
+ regmatch_t match[4];
+ char buf[1024];
+ size_t end;
+ int len;
+ int done = 0;
+ int r;
+ unsigned o;
+ struct offset *offset;
+ char last_reg_s[10];
+ int last_reg;
+
+ if (regcomp
+ (&mask_rex, "(0x[0-9a-fA-F]*) *([_a-zA-Z0-9]*)", REG_EXTENDED)) {
+ fprintf(stderr, "Failed to compile regular expression\n");
+ return -1;
+ }
+ file = fopen(filename, "r");
+ if (file == NULL) {
+ fprintf(stderr, "Failed to open: %s\n", filename);
+ return -1;
+ }
+ fseek(file, 0, SEEK_END);
+ end = ftell(file);
+ fseek(file, 0, SEEK_SET);
+
+ /* get header */
+ if (fgets(buf, 1024, file) == NULL)
+ return -1;
+
+ /* first line will contain the last register
+ * and gpu name */
+ sscanf(buf, "%s %s", gpu_name, last_reg_s);
+ t->gpu_prefix = gpu_name;
+ last_reg = strtol(last_reg_s, NULL, 16);
+
+ do {
+ if (fgets(buf, 1024, file) == NULL)
+ return -1;
+ len = strlen(buf);
+ if (ftell(file) == end)
+ done = 1;
+ if (len) {
+ r = regexec(&mask_rex, buf, 4, match, 0);
+ if (r == REG_NOMATCH) {
+ } else if (r) {
+ fprintf(stderr,
+ "Error matching regular expression %d in %s\n",
+ r, filename);
+ return -1;
+ } else {
+ buf[match[0].rm_eo] = 0;
+ buf[match[1].rm_eo] = 0;
+ buf[match[2].rm_eo] = 0;
+ o = strtol(&buf[match[1].rm_so], NULL, 16);
+ offset = offset_new(o);
+ table_offset_add(t, offset);
+ if (o > t->offset_max)
+ t->offset_max = o;
+ }
+ }
+ } while (!done);
+ fclose(file);
+ if (t->offset_max < last_reg)
+ t->offset_max = last_reg;
+ return table_build(t);
+}
+
+int main(int argc, char *argv[])
+{
+ struct table t;
+
+ if (argc != 2) {
+ fprintf(stderr, "Usage: %s <authfile>\n", argv[0]);
+ exit(1);
+ }
+ table_init(&t);
+ if (parser_auth(&t, argv[1])) {
+ fprintf(stderr, "Failed to parse file %s\n", argv[1]);
+ return -1;
+ }
+ table_print(&t);
+ return 0;
+}
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 68e728e..be51c5f 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -29,15 +29,41 @@
#include "drmP.h"
#include "drm.h"
#include "radeon_drm.h"
-#include "radeon_microcode.h"
#include "radeon_reg.h"
#include "radeon.h"
+#include "r100d.h"
+
+#include <linux/firmware.h>
+#include <linux/platform_device.h>
+
+#include "r100_reg_safe.h"
+#include "rn50_reg_safe.h"
+
+/* Firmware Names */
+#define FIRMWARE_R100 "radeon/R100_cp.bin"
+#define FIRMWARE_R200 "radeon/R200_cp.bin"
+#define FIRMWARE_R300 "radeon/R300_cp.bin"
+#define FIRMWARE_R420 "radeon/R420_cp.bin"
+#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
+#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
+#define FIRMWARE_R520 "radeon/R520_cp.bin"
+
+MODULE_FIRMWARE(FIRMWARE_R100);
+MODULE_FIRMWARE(FIRMWARE_R200);
+MODULE_FIRMWARE(FIRMWARE_R300);
+MODULE_FIRMWARE(FIRMWARE_R420);
+MODULE_FIRMWARE(FIRMWARE_RS690);
+MODULE_FIRMWARE(FIRMWARE_RS600);
+MODULE_FIRMWARE(FIRMWARE_R520);
+
+#include "r100_track.h"
/* This files gather functions specifics to:
* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
*
* Some of these functions might be used by newer ASICs.
*/
+int r200_init(struct radeon_device *rdev);
void r100_hdp_reset(struct radeon_device *rdev);
void r100_gpu_init(struct radeon_device *rdev);
int r100_gui_wait_for_idle(struct radeon_device *rdev);
@@ -58,23 +84,28 @@ void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
* could end up in wrong address. */
}
-int r100_pci_gart_enable(struct radeon_device *rdev)
+int r100_pci_gart_init(struct radeon_device *rdev)
{
- uint32_t tmp;
int r;
+ if (rdev->gart.table.ram.ptr) {
+ WARN(1, "R100 PCI GART already initialized.\n");
+ return 0;
+ }
/* Initialize common gart structure */
r = radeon_gart_init(rdev);
- if (r) {
+ if (r)
return r;
- }
- if (rdev->gart.table.ram.ptr == NULL) {
- rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
- r = radeon_gart_table_ram_alloc(rdev);
- if (r) {
- return r;
- }
- }
+ rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
+ rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
+ rdev->asic->gart_set_page = &r100_pci_gart_set_page;
+ return radeon_gart_table_ram_alloc(rdev);
+}
+
+int r100_pci_gart_enable(struct radeon_device *rdev)
+{
+ uint32_t tmp;
+
/* discard memory request outside of configured range */
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
WREG32(RADEON_AIC_CNTL, tmp);
@@ -114,13 +145,11 @@ int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
return 0;
}
-int r100_gart_enable(struct radeon_device *rdev)
+void r100_pci_gart_fini(struct radeon_device *rdev)
{
- if (rdev->flags & RADEON_IS_AGP) {
- r100_pci_gart_disable(rdev);
- return 0;
- }
- return r100_pci_gart_enable(rdev);
+ r100_pci_gart_disable(rdev);
+ radeon_gart_table_ram_free(rdev);
+ radeon_gart_fini(rdev);
}
@@ -247,9 +276,6 @@ int r100_mc_init(struct radeon_device *rdev)
void r100_mc_fini(struct radeon_device *rdev)
{
- r100_pci_gart_disable(rdev);
- radeon_gart_table_ram_free(rdev);
- radeon_gart_fini(rdev);
}
@@ -273,6 +299,17 @@ int r100_irq_set(struct radeon_device *rdev)
return 0;
}
+void r100_irq_disable(struct radeon_device *rdev)
+{
+ u32 tmp;
+
+ WREG32(R_000040_GEN_INT_CNTL, 0);
+ /* Wait and acknowledge irq */
+ mdelay(1);
+ tmp = RREG32(R_000044_GEN_INT_STATUS);
+ WREG32(R_000044_GEN_INT_STATUS, tmp);
+}
+
static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
{
uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
@@ -293,6 +330,9 @@ int r100_irq_process(struct radeon_device *rdev)
if (!status) {
return IRQ_NONE;
}
+ if (rdev->shutdown) {
+ return IRQ_NONE;
+ }
while (status) {
/* SW interrupt */
if (status & RADEON_SW_INT_TEST) {
@@ -367,14 +407,21 @@ int r100_wb_init(struct radeon_device *rdev)
return r;
}
}
- WREG32(0x774, rdev->wb.gpu_addr);
- WREG32(0x70C, rdev->wb.gpu_addr + 1024);
- WREG32(0x770, 0xff);
+ WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
+ WREG32(R_00070C_CP_RB_RPTR_ADDR,
+ S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
+ WREG32(R_000770_SCRATCH_UMSK, 0xff);
return 0;
}
+void r100_wb_disable(struct radeon_device *rdev)
+{
+ WREG32(R_000770_SCRATCH_UMSK, 0);
+}
+
void r100_wb_fini(struct radeon_device *rdev)
{
+ r100_wb_disable(rdev);
if (rdev->wb.wb_obj) {
radeon_object_kunmap(rdev->wb.wb_obj);
radeon_object_unpin(rdev->wb.wb_obj);
@@ -461,6 +508,21 @@ int r100_copy_blit(struct radeon_device *rdev,
/*
* CP
*/
+static int r100_cp_wait_for_idle(struct radeon_device *rdev)
+{
+ unsigned i;
+ u32 tmp;
+
+ for (i = 0; i < rdev->usec_timeout; i++) {
+ tmp = RREG32(R_000E40_RBBM_STATUS);
+ if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
+ return 0;
+ }
+ udelay(1);
+ }
+ return -1;
+}
+
void r100_ring_start(struct radeon_device *rdev)
{
int r;
@@ -478,33 +540,33 @@ void r100_ring_start(struct radeon_device *rdev)
radeon_ring_unlock_commit(rdev);
}
-static void r100_cp_load_microcode(struct radeon_device *rdev)
+
+/* Load the microcode for the CP */
+static int r100_cp_init_microcode(struct radeon_device *rdev)
{
- int i;
+ struct platform_device *pdev;
+ const char *fw_name = NULL;
+ int err;
- if (r100_gui_wait_for_idle(rdev)) {
- printk(KERN_WARNING "Failed to wait GUI idle while "
- "programming pipes. Bad things might happen.\n");
- }
+ DRM_DEBUG("\n");
- WREG32(RADEON_CP_ME_RAM_ADDR, 0);
+ pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
+ err = IS_ERR(pdev);
+ if (err) {
+ printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
+ return -EINVAL;
+ }
if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
(rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
(rdev->family == CHIP_RS200)) {
DRM_INFO("Loading R100 Microcode\n");
- for (i = 0; i < 256; i++) {
- WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]);
- WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]);
- }
+ fw_name = FIRMWARE_R100;
} else if ((rdev->family == CHIP_R200) ||
(rdev->family == CHIP_RV250) ||
(rdev->family == CHIP_RV280) ||
(rdev->family == CHIP_RS300)) {
DRM_INFO("Loading R200 Microcode\n");
- for (i = 0; i < 256; i++) {
- WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]);
- WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]);
- }
+ fw_name = FIRMWARE_R200;
} else if ((rdev->family == CHIP_R300) ||
(rdev->family == CHIP_R350) ||
(rdev->family == CHIP_RV350) ||
@@ -512,31 +574,19 @@ static void r100_cp_load_microcode(struct radeon_device *rdev)
(rdev->family == CHIP_RS400) ||
(rdev->family == CHIP_RS480)) {
DRM_INFO("Loading R300 Microcode\n");
- for (i = 0; i < 256; i++) {
- WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
- WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
- }
+ fw_name = FIRMWARE_R300;
} else if ((rdev->family == CHIP_R420) ||
(rdev->family == CHIP_R423) ||
(rdev->family == CHIP_RV410)) {
DRM_INFO("Loading R400 Microcode\n");
- for (i = 0; i < 256; i++) {
- WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]);
- WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]);
- }
+ fw_name = FIRMWARE_R420;
} else if ((rdev->family == CHIP_RS690) ||
(rdev->family == CHIP_RS740)) {
DRM_INFO("Loading RS690/RS740 Microcode\n");
- for (i = 0; i < 256; i++) {
- WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]);
- WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]);
- }
+ fw_name = FIRMWARE_RS690;
} else if (rdev->family == CHIP_RS600) {
DRM_INFO("Loading RS600 Microcode\n");
- for (i = 0; i < 256; i++) {
- WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]);
- WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]);
- }
+ fw_name = FIRMWARE_RS600;
} else if ((rdev->family == CHIP_RV515) ||
(rdev->family == CHIP_R520) ||
(rdev->family == CHIP_RV530) ||
@@ -544,9 +594,43 @@ static void r100_cp_load_microcode(struct radeon_device *rdev)
(rdev->family == CHIP_RV560) ||
(rdev->family == CHIP_RV570)) {
DRM_INFO("Loading R500 Microcode\n");
- for (i = 0; i < 256; i++) {
- WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
- WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
+ fw_name = FIRMWARE_R520;
+ }
+
+ err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
+ platform_device_unregister(pdev);
+ if (err) {
+ printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
+ fw_name);
+ } else if (rdev->me_fw->size % 8) {
+ printk(KERN_ERR
+ "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
+ rdev->me_fw->size, fw_name);
+ err = -EINVAL;
+ release_firmware(rdev->me_fw);
+ rdev->me_fw = NULL;
+ }
+ return err;
+}
+static void r100_cp_load_microcode(struct radeon_device *rdev)
+{
+ const __be32 *fw_data;
+ int i, size;
+
+ if (r100_gui_wait_for_idle(rdev)) {
+ printk(KERN_WARNING "Failed to wait GUI idle while "
+ "programming pipes. Bad things might happen.\n");
+ }
+
+ if (rdev->me_fw) {
+ size = rdev->me_fw->size / 4;
+ fw_data = (const __be32 *)&rdev->me_fw->data[0];
+ WREG32(RADEON_CP_ME_RAM_ADDR, 0);
+ for (i = 0; i < size; i += 2) {
+ WREG32(RADEON_CP_ME_RAM_DATAH,
+ be32_to_cpup(&fw_data[i]));
+ WREG32(RADEON_CP_ME_RAM_DATAL,
+ be32_to_cpup(&fw_data[i + 1]));
}
}
}
@@ -585,6 +669,15 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
} else {
DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
}
+
+ if (!rdev->me_fw) {
+ r = r100_cp_init_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load firmware!\n");
+ return r;
+ }
+ }
+
/* Align ring size */
rb_bufsz = drm_order(ring_size / 8);
ring_size = (1 << (rb_bufsz + 1)) * 4;
@@ -658,9 +751,11 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
void r100_cp_fini(struct radeon_device *rdev)
{
+ if (r100_cp_wait_for_idle(rdev)) {
+ DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
+ }
/* Disable ring */
- rdev->cp.ready = false;
- WREG32(RADEON_CP_CSQ_CNTL, 0);
+ r100_cp_disable(rdev);
radeon_ring_fini(rdev);
DRM_INFO("radeon: cp finalized\n");
}
@@ -710,6 +805,12 @@ int r100_cp_reset(struct radeon_device *rdev)
return -1;
}
+void r100_cp_commit(struct radeon_device *rdev)
+{
+ WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
+ (void)RREG32(RADEON_CP_RB_WPTR);
+}
+
/*
* CS functions
@@ -968,147 +1069,356 @@ int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
return 0;
}
+static int r100_get_vtx_size(uint32_t vtx_fmt)
+{
+ int vtx_size;
+ vtx_size = 2;
+ /* ordered according to bits in spec */
+ if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
+ vtx_size++;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
+ vtx_size += 3;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
+ vtx_size++;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
+ vtx_size++;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
+ vtx_size += 3;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
+ vtx_size++;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
+ vtx_size++;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
+ vtx_size += 2;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
+ vtx_size += 2;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
+ vtx_size++;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
+ vtx_size += 2;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
+ vtx_size++;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
+ vtx_size += 2;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
+ vtx_size++;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
+ vtx_size++;
+ /* blend weight */
+ if (vtx_fmt & (0x7 << 15))
+ vtx_size += (vtx_fmt >> 15) & 0x7;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
+ vtx_size += 3;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
+ vtx_size += 2;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
+ vtx_size++;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
+ vtx_size++;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
+ vtx_size++;
+ if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
+ vtx_size++;
+ return vtx_size;
+}
+
static int r100_packet0_check(struct radeon_cs_parser *p,
- struct radeon_cs_packet *pkt)
+ struct radeon_cs_packet *pkt,
+ unsigned idx, unsigned reg)
{
struct radeon_cs_chunk *ib_chunk;
struct radeon_cs_reloc *reloc;
+ struct r100_cs_track *track;
volatile uint32_t *ib;
uint32_t tmp;
- unsigned reg;
- unsigned i;
- unsigned idx;
- bool onereg;
int r;
+ int i, face;
u32 tile_flags = 0;
ib = p->ib->ptr;
ib_chunk = &p->chunks[p->chunk_ib_idx];
- idx = pkt->idx + 1;
- reg = pkt->reg;
- onereg = false;
- if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) {
- onereg = true;
- }
- for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
- switch (reg) {
- case RADEON_CRTC_GUI_TRIG_VLINE:
- r = r100_cs_packet_parse_vline(p);
- if (r) {
- DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
- idx, reg);
- r100_cs_dump_packet(p, pkt);
- return r;
- }
- break;
+ track = (struct r100_cs_track *)p->track;
+
+ switch (reg) {
+ case RADEON_CRTC_GUI_TRIG_VLINE:
+ r = r100_cs_packet_parse_vline(p);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ break;
/* FIXME: only allow PACKET3 blit? easier to check for out of
* range access */
- case RADEON_DST_PITCH_OFFSET:
- case RADEON_SRC_PITCH_OFFSET:
- r = r100_cs_packet_next_reloc(p, &reloc);
- if (r) {
- DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
- idx, reg);
- r100_cs_dump_packet(p, pkt);
- return r;
- }
- tmp = ib_chunk->kdata[idx] & 0x003fffff;
- tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
-
- if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
- tile_flags |= RADEON_DST_TILE_MACRO;
- if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
- if (reg == RADEON_SRC_PITCH_OFFSET) {
- DRM_ERROR("Cannot src blit from microtiled surface\n");
- r100_cs_dump_packet(p, pkt);
- return -EINVAL;
- }
- tile_flags |= RADEON_DST_TILE_MICRO;
- }
+ case RADEON_DST_PITCH_OFFSET:
+ case RADEON_SRC_PITCH_OFFSET:
+ r = r100_reloc_pitch_offset(p, pkt, idx, reg);
+ if (r)
+ return r;
+ break;
+ case RADEON_RB3D_DEPTHOFFSET:
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ track->zb.robj = reloc->robj;
+ track->zb.offset = ib_chunk->kdata[idx];
+ ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ break;
+ case RADEON_RB3D_COLOROFFSET:
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ track->cb[0].robj = reloc->robj;
+ track->cb[0].offset = ib_chunk->kdata[idx];
+ ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ break;
+ case RADEON_PP_TXOFFSET_0:
+ case RADEON_PP_TXOFFSET_1:
+ case RADEON_PP_TXOFFSET_2:
+ i = (reg - RADEON_PP_TXOFFSET_0) / 24;
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ track->textures[i].robj = reloc->robj;
+ break;
+ case RADEON_PP_CUBIC_OFFSET_T0_0:
+ case RADEON_PP_CUBIC_OFFSET_T0_1:
+ case RADEON_PP_CUBIC_OFFSET_T0_2:
+ case RADEON_PP_CUBIC_OFFSET_T0_3:
+ case RADEON_PP_CUBIC_OFFSET_T0_4:
+ i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ track->textures[0].cube_info[i].offset = ib_chunk->kdata[idx];
+ ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ track->textures[0].cube_info[i].robj = reloc->robj;
+ break;
+ case RADEON_PP_CUBIC_OFFSET_T1_0:
+ case RADEON_PP_CUBIC_OFFSET_T1_1:
+ case RADEON_PP_CUBIC_OFFSET_T1_2:
+ case RADEON_PP_CUBIC_OFFSET_T1_3:
+ case RADEON_PP_CUBIC_OFFSET_T1_4:
+ i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ track->textures[1].cube_info[i].offset = ib_chunk->kdata[idx];
+ ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ track->textures[1].cube_info[i].robj = reloc->robj;
+ break;
+ case RADEON_PP_CUBIC_OFFSET_T2_0:
+ case RADEON_PP_CUBIC_OFFSET_T2_1:
+ case RADEON_PP_CUBIC_OFFSET_T2_2:
+ case RADEON_PP_CUBIC_OFFSET_T2_3:
+ case RADEON_PP_CUBIC_OFFSET_T2_4:
+ i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ track->textures[2].cube_info[i].offset = ib_chunk->kdata[idx];
+ ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ track->textures[2].cube_info[i].robj = reloc->robj;
+ break;
+ case RADEON_RE_WIDTH_HEIGHT:
+ track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF);
+ break;
+ case RADEON_RB3D_COLORPITCH:
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
- tmp |= tile_flags;
- ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
- break;
- case RADEON_RB3D_DEPTHOFFSET:
- case RADEON_RB3D_COLOROFFSET:
- case R300_RB3D_COLOROFFSET0:
- case R300_ZB_DEPTHOFFSET:
- case R200_PP_TXOFFSET_0:
- case R200_PP_TXOFFSET_1:
- case R200_PP_TXOFFSET_2:
- case R200_PP_TXOFFSET_3:
- case R200_PP_TXOFFSET_4:
- case R200_PP_TXOFFSET_5:
- case RADEON_PP_TXOFFSET_0:
- case RADEON_PP_TXOFFSET_1:
- case RADEON_PP_TXOFFSET_2:
- case R300_TX_OFFSET_0:
- case R300_TX_OFFSET_0+4:
- case R300_TX_OFFSET_0+8:
- case R300_TX_OFFSET_0+12:
- case R300_TX_OFFSET_0+16:
- case R300_TX_OFFSET_0+20:
- case R300_TX_OFFSET_0+24:
- case R300_TX_OFFSET_0+28:
- case R300_TX_OFFSET_0+32:
- case R300_TX_OFFSET_0+36:
- case R300_TX_OFFSET_0+40:
- case R300_TX_OFFSET_0+44:
- case R300_TX_OFFSET_0+48:
- case R300_TX_OFFSET_0+52:
- case R300_TX_OFFSET_0+56:
- case R300_TX_OFFSET_0+60:
- /* rn50 has no 3D engine so fail on any 3d setup */
- if (ASIC_IS_RN50(p->rdev)) {
- DRM_ERROR("attempt to use RN50 3D engine failed\n");
- return -EINVAL;
- }
- r = r100_cs_packet_next_reloc(p, &reloc);
- if (r) {
- DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
- idx, reg);
- r100_cs_dump_packet(p, pkt);
- return r;
- }
- ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
- break;
- case R300_RB3D_COLORPITCH0:
- case RADEON_RB3D_COLORPITCH:
- r = r100_cs_packet_next_reloc(p, &reloc);
- if (r) {
- DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
- idx, reg);
- r100_cs_dump_packet(p, pkt);
- return r;
- }
+ if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+ tile_flags |= RADEON_COLOR_TILE_ENABLE;
+ if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+ tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
- if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
- tile_flags |= RADEON_COLOR_TILE_ENABLE;
- if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
- tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
+ tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
+ tmp |= tile_flags;
+ ib[idx] = tmp;
- tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
- tmp |= tile_flags;
- ib[idx] = tmp;
+ track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK;
+ break;
+ case RADEON_RB3D_DEPTHPITCH:
+ track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK;
+ break;
+ case RADEON_RB3D_CNTL:
+ switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
+ case 7:
+ case 8:
+ case 9:
+ case 11:
+ case 12:
+ track->cb[0].cpp = 1;
break;
- case RADEON_RB3D_ZPASS_ADDR:
- r = r100_cs_packet_next_reloc(p, &reloc);
- if (r) {
- DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
- idx, reg);
- r100_cs_dump_packet(p, pkt);
- return r;
- }
- ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ case 3:
+ case 4:
+ case 15:
+ track->cb[0].cpp = 2;
+ break;
+ case 6:
+ track->cb[0].cpp = 4;
break;
default:
- /* FIXME: we don't want to allow anyothers packet */
+ DRM_ERROR("Invalid color buffer format (%d) !\n",
+ ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
+ return -EINVAL;
+ }
+ track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE);
+ break;
+ case RADEON_RB3D_ZSTENCILCNTL:
+ switch (ib_chunk->kdata[idx] & 0xf) {
+ case 0:
+ track->zb.cpp = 2;
+ break;
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 9:
+ case 11:
+ track->zb.cpp = 4;
break;
+ default:
+ break;
+ }
+ break;
+ case RADEON_RB3D_ZPASS_ADDR:
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ break;
+ case RADEON_PP_CNTL:
+ {
+ uint32_t temp = ib_chunk->kdata[idx] >> 4;
+ for (i = 0; i < track->num_texture; i++)
+ track->textures[i].enabled = !!(temp & (1 << i));
}
- if (onereg) {
- /* FIXME: forbid onereg write to register on relocate */
+ break;
+ case RADEON_SE_VF_CNTL:
+ track->vap_vf_cntl = ib_chunk->kdata[idx];
+ break;
+ case RADEON_SE_VTX_FMT:
+ track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx]);
+ break;
+ case RADEON_PP_TEX_SIZE_0:
+ case RADEON_PP_TEX_SIZE_1:
+ case RADEON_PP_TEX_SIZE_2:
+ i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
+ track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1;
+ track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
+ break;
+ case RADEON_PP_TEX_PITCH_0:
+ case RADEON_PP_TEX_PITCH_1:
+ case RADEON_PP_TEX_PITCH_2:
+ i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
+ track->textures[i].pitch = ib_chunk->kdata[idx] + 32;
+ break;
+ case RADEON_PP_TXFILTER_0:
+ case RADEON_PP_TXFILTER_1:
+ case RADEON_PP_TXFILTER_2:
+ i = (reg - RADEON_PP_TXFILTER_0) / 24;
+ track->textures[i].num_levels = ((ib_chunk->kdata[idx] & RADEON_MAX_MIP_LEVEL_MASK)
+ >> RADEON_MAX_MIP_LEVEL_SHIFT);
+ tmp = (ib_chunk->kdata[idx] >> 23) & 0x7;
+ if (tmp == 2 || tmp == 6)
+ track->textures[i].roundup_w = false;
+ tmp = (ib_chunk->kdata[idx] >> 27) & 0x7;
+ if (tmp == 2 || tmp == 6)
+ track->textures[i].roundup_h = false;
+ break;
+ case RADEON_PP_TXFORMAT_0:
+ case RADEON_PP_TXFORMAT_1:
+ case RADEON_PP_TXFORMAT_2:
+ i = (reg - RADEON_PP_TXFORMAT_0) / 24;
+ if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_NON_POWER2) {
+ track->textures[i].use_pitch = 1;
+ } else {
+ track->textures[i].use_pitch = 0;
+ track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
+ track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
+ }
+ if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
+ track->textures[i].tex_coord_type = 2;
+ switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) {
+ case RADEON_TXFORMAT_I8:
+ case RADEON_TXFORMAT_RGB332:
+ case RADEON_TXFORMAT_Y8:
+ track->textures[i].cpp = 1;
break;
+ case RADEON_TXFORMAT_AI88:
+ case RADEON_TXFORMAT_ARGB1555:
+ case RADEON_TXFORMAT_RGB565:
+ case RADEON_TXFORMAT_ARGB4444:
+ case RADEON_TXFORMAT_VYUY422:
+ case RADEON_TXFORMAT_YVYU422:
+ case RADEON_TXFORMAT_DXT1:
+ case RADEON_TXFORMAT_SHADOW16:
+ case RADEON_TXFORMAT_LDUDV655:
+ case RADEON_TXFORMAT_DUDV88:
+ track->textures[i].cpp = 2;
+ break;
+ case RADEON_TXFORMAT_ARGB8888:
+ case RADEON_TXFORMAT_RGBA8888:
+ case RADEON_TXFORMAT_DXT23:
+ case RADEON_TXFORMAT_DXT45:
+ case RADEON_TXFORMAT_SHADOW32:
+ case RADEON_TXFORMAT_LDUDUV8888:
+ track->textures[i].cpp = 4;
+ break;
+ }
+ track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf);
+ track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf);
+ break;
+ case RADEON_PP_CUBIC_FACES_0:
+ case RADEON_PP_CUBIC_FACES_1:
+ case RADEON_PP_CUBIC_FACES_2:
+ tmp = ib_chunk->kdata[idx];
+ i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
+ for (face = 0; face < 4; face++) {
+ track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
+ track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
}
+ break;
+ default:
+ printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
+ reg, idx);
+ return -EINVAL;
}
return 0;
}
@@ -1137,6 +1447,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
{
struct radeon_cs_chunk *ib_chunk;
struct radeon_cs_reloc *reloc;
+ struct r100_cs_track *track;
unsigned idx;
unsigned i, c;
volatile uint32_t *ib;
@@ -1145,9 +1456,11 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
ib = p->ib->ptr;
ib_chunk = &p->chunks[p->chunk_ib_idx];
idx = pkt->idx + 1;
+ track = (struct r100_cs_track *)p->track;
switch (pkt->opcode) {
case PACKET3_3D_LOAD_VBPNTR:
c = ib_chunk->kdata[idx++];
+ track->num_arrays = c;
for (i = 0; i < (c - 1); i += 2, idx += 3) {
r = r100_cs_packet_next_reloc(p, &reloc);
if (r) {
@@ -1157,6 +1470,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
return r;
}
ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
+ track->arrays[i + 0].robj = reloc->robj;
+ track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
+ track->arrays[i + 0].esize &= 0x7F;
r = r100_cs_packet_next_reloc(p, &reloc);
if (r) {
DRM_ERROR("No reloc for packet3 %d\n",
@@ -1165,6 +1481,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
return r;
}
ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
+ track->arrays[i + 1].robj = reloc->robj;
+ track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24;
+ track->arrays[i + 1].esize &= 0x7F;
}
if (c & 1) {
r = r100_cs_packet_next_reloc(p, &reloc);
@@ -1175,6 +1494,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
return r;
}
ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
+ track->arrays[i + 0].robj = reloc->robj;
+ track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
+ track->arrays[i + 0].esize &= 0x7F;
}
break;
case PACKET3_INDX_BUFFER:
@@ -1191,7 +1513,6 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
}
break;
case 0x23:
- /* FIXME: cleanup */
/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
r = r100_cs_packet_next_reloc(p, &reloc);
if (r) {
@@ -1200,18 +1521,71 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
return r;
}
ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ track->num_arrays = 1;
+ track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx+2]);
+
+ track->arrays[0].robj = reloc->robj;
+ track->arrays[0].esize = track->vtx_size;
+
+ track->max_indx = ib_chunk->kdata[idx+1];
+
+ track->vap_vf_cntl = ib_chunk->kdata[idx+3];
+ track->immd_dwords = pkt->count - 1;
+ r = r100_cs_track_check(p->rdev, track);
+ if (r)
+ return r;
break;
case PACKET3_3D_DRAW_IMMD:
+ if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) {
+ DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
+ return -EINVAL;
+ }
+ track->vap_vf_cntl = ib_chunk->kdata[idx+1];
+ track->immd_dwords = pkt->count - 1;
+ r = r100_cs_track_check(p->rdev, track);
+ if (r)
+ return r;
+ break;
/* triggers drawing using in-packet vertex data */
case PACKET3_3D_DRAW_IMMD_2:
+ if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) {
+ DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
+ return -EINVAL;
+ }
+ track->vap_vf_cntl = ib_chunk->kdata[idx];
+ track->immd_dwords = pkt->count;
+ r = r100_cs_track_check(p->rdev, track);
+ if (r)
+ return r;
+ break;
/* triggers drawing using in-packet vertex data */
case PACKET3_3D_DRAW_VBUF_2:
+ track->vap_vf_cntl = ib_chunk->kdata[idx];
+ r = r100_cs_track_check(p->rdev, track);
+ if (r)
+ return r;
+ break;
/* triggers drawing of vertex buffers setup elsewhere */
case PACKET3_3D_DRAW_INDX_2:
+ track->vap_vf_cntl = ib_chunk->kdata[idx];
+ r = r100_cs_track_check(p->rdev, track);
+ if (r)
+ return r;
+ break;
/* triggers drawing using indices to vertex buffer */
case PACKET3_3D_DRAW_VBUF:
+ track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
+ r = r100_cs_track_check(p->rdev, track);
+ if (r)
+ return r;
+ break;
/* triggers drawing of vertex buffers setup elsewhere */
case PACKET3_3D_DRAW_INDX:
+ track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
+ r = r100_cs_track_check(p->rdev, track);
+ if (r)
+ return r;
+ break;
/* triggers drawing using indices to vertex buffer */
case PACKET3_NOP:
break;
@@ -1225,8 +1599,12 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
int r100_cs_parse(struct radeon_cs_parser *p)
{
struct radeon_cs_packet pkt;
+ struct r100_cs_track *track;
int r;
+ track = kzalloc(sizeof(*track), GFP_KERNEL);
+ r100_cs_track_clear(p->rdev, track);
+ p->track = track;
do {
r = r100_cs_packet_parse(p, &pkt, p->idx);
if (r) {
@@ -1235,7 +1613,16 @@ int r100_cs_parse(struct radeon_cs_parser *p)
p->idx += pkt.count + 2;
switch (pkt.type) {
case PACKET_TYPE0:
- r = r100_packet0_check(p, &pkt);
+ if (p->rdev->family >= CHIP_R200)
+ r = r100_cs_parse_packet0(p, &pkt,
+ p->rdev->config.r100.reg_safe_bm,
+ p->rdev->config.r100.reg_safe_bm_size,
+ &r200_packet0_check);
+ else
+ r = r100_cs_parse_packet0(p, &pkt,
+ p->rdev->config.r100.reg_safe_bm,
+ p->rdev->config.r100.reg_safe_bm_size,
+ &r100_packet0_check);
break;
case PACKET_TYPE2:
break;
@@ -1568,6 +1955,20 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
rdev->mc.real_vram_size = rdev->mc.aper_size;
}
+void r100_vga_set_state(struct radeon_device *rdev, bool state)
+{
+ uint32_t temp;
+
+ temp = RREG32(RADEON_CONFIG_CNTL);
+ if (state == false) {
+ temp &= ~(1<<8);
+ temp |= (1<<9);
+ } else {
+ temp &= ~(1<<9);
+ }
+ WREG32(RADEON_CONFIG_CNTL, temp);
+}
+
void r100_vram_info(struct radeon_device *rdev)
{
r100_vram_get_type(rdev);
@@ -1634,6 +2035,15 @@ void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
int r100_init(struct radeon_device *rdev)
{
+ if (ASIC_IS_RN50(rdev)) {
+ rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
+ rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
+ } else if (rdev->family < CHIP_R200) {
+ rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
+ rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
+ } else {
+ return r200_init(rdev);
+ }
return 0;
}
@@ -1839,6 +2249,11 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
flags |= R300_SURF_TILE_MICRO;
}
+ if (tiling_flags & RADEON_TILING_SWAP_16BIT)
+ flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
+ if (tiling_flags & RADEON_TILING_SWAP_32BIT)
+ flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
+
DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
@@ -2334,3 +2749,460 @@ void r100_bandwidth_update(struct radeon_device *rdev)
(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
}
}
+
+static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
+{
+ DRM_ERROR("pitch %d\n", t->pitch);
+ DRM_ERROR("width %d\n", t->width);
+ DRM_ERROR("height %d\n", t->height);
+ DRM_ERROR("num levels %d\n", t->num_levels);
+ DRM_ERROR("depth %d\n", t->txdepth);
+ DRM_ERROR("bpp %d\n", t->cpp);
+ DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
+ DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
+ DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
+}
+
+static int r100_cs_track_cube(struct radeon_device *rdev,
+ struct r100_cs_track *track, unsigned idx)
+{
+ unsigned face, w, h;
+ struct radeon_object *cube_robj;
+ unsigned long size;
+
+ for (face = 0; face < 5; face++) {
+ cube_robj = track->textures[idx].cube_info[face].robj;
+ w = track->textures[idx].cube_info[face].width;
+ h = track->textures[idx].cube_info[face].height;
+
+ size = w * h;
+ size *= track->textures[idx].cpp;
+
+ size += track->textures[idx].cube_info[face].offset;
+
+ if (size > radeon_object_size(cube_robj)) {
+ DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
+ size, radeon_object_size(cube_robj));
+ r100_cs_track_texture_print(&track->textures[idx]);
+ return -1;
+ }
+ }
+ return 0;
+}
+
+static int r100_cs_track_texture_check(struct radeon_device *rdev,
+ struct r100_cs_track *track)
+{
+ struct radeon_object *robj;
+ unsigned long size;
+ unsigned u, i, w, h;
+ int ret;
+
+ for (u = 0; u < track->num_texture; u++) {
+ if (!track->textures[u].enabled)
+ continue;
+ robj = track->textures[u].robj;
+ if (robj == NULL) {
+ DRM_ERROR("No texture bound to unit %u\n", u);
+ return -EINVAL;
+ }
+ size = 0;
+ for (i = 0; i <= track->textures[u].num_levels; i++) {
+ if (track->textures[u].use_pitch) {
+ if (rdev->family < CHIP_R300)
+ w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
+ else
+ w = track->textures[u].pitch / (1 << i);
+ } else {
+ w = track->textures[u].width / (1 << i);
+ if (rdev->family >= CHIP_RV515)
+ w |= track->textures[u].width_11;
+ if (track->textures[u].roundup_w)
+ w = roundup_pow_of_two(w);
+ }
+ h = track->textures[u].height / (1 << i);
+ if (rdev->family >= CHIP_RV515)
+ h |= track->textures[u].height_11;
+ if (track->textures[u].roundup_h)
+ h = roundup_pow_of_two(h);
+ size += w * h;
+ }
+ size *= track->textures[u].cpp;
+ switch (track->textures[u].tex_coord_type) {
+ case 0:
+ break;
+ case 1:
+ size *= (1 << track->textures[u].txdepth);
+ break;
+ case 2:
+ if (track->separate_cube) {
+ ret = r100_cs_track_cube(rdev, track, u);
+ if (ret)
+ return ret;
+ } else
+ size *= 6;
+ break;
+ default:
+ DRM_ERROR("Invalid texture coordinate type %u for unit "
+ "%u\n", track->textures[u].tex_coord_type, u);
+ return -EINVAL;
+ }
+ if (size > radeon_object_size(robj)) {
+ DRM_ERROR("Texture of unit %u needs %lu bytes but is "
+ "%lu\n", u, size, radeon_object_size(robj));
+ r100_cs_track_texture_print(&track->textures[u]);
+ return -EINVAL;
+ }
+ }
+ return 0;
+}
+
+int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
+{
+ unsigned i;
+ unsigned long size;
+ unsigned prim_walk;
+ unsigned nverts;
+
+ for (i = 0; i < track->num_cb; i++) {
+ if (track->cb[i].robj == NULL) {
+ DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
+ return -EINVAL;
+ }
+ size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
+ size += track->cb[i].offset;
+ if (size > radeon_object_size(track->cb[i].robj)) {
+ DRM_ERROR("[drm] Buffer too small for color buffer %d "
+ "(need %lu have %lu) !\n", i, size,
+ radeon_object_size(track->cb[i].robj));
+ DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
+ i, track->cb[i].pitch, track->cb[i].cpp,
+ track->cb[i].offset, track->maxy);
+ return -EINVAL;
+ }
+ }
+ if (track->z_enabled) {
+ if (track->zb.robj == NULL) {
+ DRM_ERROR("[drm] No buffer for z buffer !\n");
+ return -EINVAL;
+ }
+ size = track->zb.pitch * track->zb.cpp * track->maxy;
+ size += track->zb.offset;
+ if (size > radeon_object_size(track->zb.robj)) {
+ DRM_ERROR("[drm] Buffer too small for z buffer "
+ "(need %lu have %lu) !\n", size,
+ radeon_object_size(track->zb.robj));
+ DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
+ track->zb.pitch, track->zb.cpp,
+ track->zb.offset, track->maxy);
+ return -EINVAL;
+ }
+ }
+ prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
+ nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
+ switch (prim_walk) {
+ case 1:
+ for (i = 0; i < track->num_arrays; i++) {
+ size = track->arrays[i].esize * track->max_indx * 4;
+ if (track->arrays[i].robj == NULL) {
+ DRM_ERROR("(PW %u) Vertex array %u no buffer "
+ "bound\n", prim_walk, i);
+ return -EINVAL;
+ }
+ if (size > radeon_object_size(track->arrays[i].robj)) {
+ DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
+ "have %lu dwords\n", prim_walk, i,
+ size >> 2,
+ radeon_object_size(track->arrays[i].robj) >> 2);
+ DRM_ERROR("Max indices %u\n", track->max_indx);
+ return -EINVAL;
+ }
+ }
+ break;
+ case 2:
+ for (i = 0; i < track->num_arrays; i++) {
+ size = track->arrays[i].esize * (nverts - 1) * 4;
+ if (track->arrays[i].robj == NULL) {
+ DRM_ERROR("(PW %u) Vertex array %u no buffer "
+ "bound\n", prim_walk, i);
+ return -EINVAL;
+ }
+ if (size > radeon_object_size(track->arrays[i].robj)) {
+ DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
+ "have %lu dwords\n", prim_walk, i, size >> 2,
+ radeon_object_size(track->arrays[i].robj) >> 2);
+ return -EINVAL;
+ }
+ }
+ break;
+ case 3:
+ size = track->vtx_size * nverts;
+ if (size != track->immd_dwords) {
+ DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
+ track->immd_dwords, size);
+ DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
+ nverts, track->vtx_size);
+ return -EINVAL;
+ }
+ break;
+ default:
+ DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
+ prim_walk);
+ return -EINVAL;
+ }
+ return r100_cs_track_texture_check(rdev, track);
+}
+
+void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
+{
+ unsigned i, face;
+
+ if (rdev->family < CHIP_R300) {
+ track->num_cb = 1;
+ if (rdev->family <= CHIP_RS200)
+ track->num_texture = 3;
+ else
+ track->num_texture = 6;
+ track->maxy = 2048;
+ track->separate_cube = 1;
+ } else {
+ track->num_cb = 4;
+ track->num_texture = 16;
+ track->maxy = 4096;
+ track->separate_cube = 0;
+ }
+
+ for (i = 0; i < track->num_cb; i++) {
+ track->cb[i].robj = NULL;
+ track->cb[i].pitch = 8192;
+ track->cb[i].cpp = 16;
+ track->cb[i].offset = 0;
+ }
+ track->z_enabled = true;
+ track->zb.robj = NULL;
+ track->zb.pitch = 8192;
+ track->zb.cpp = 4;
+ track->zb.offset = 0;
+ track->vtx_size = 0x7F;
+ track->immd_dwords = 0xFFFFFFFFUL;
+ track->num_arrays = 11;
+ track->max_indx = 0x00FFFFFFUL;
+ for (i = 0; i < track->num_arrays; i++) {
+ track->arrays[i].robj = NULL;
+ track->arrays[i].esize = 0x7F;
+ }
+ for (i = 0; i < track->num_texture; i++) {
+ track->textures[i].pitch = 16536;
+ track->textures[i].width = 16536;
+ track->textures[i].height = 16536;
+ track->textures[i].width_11 = 1 << 11;
+ track->textures[i].height_11 = 1 << 11;
+ track->textures[i].num_levels = 12;
+ if (rdev->family <= CHIP_RS200) {
+ track->textures[i].tex_coord_type = 0;
+ track->textures[i].txdepth = 0;
+ } else {
+ track->textures[i].txdepth = 16;
+ track->textures[i].tex_coord_type = 1;
+ }
+ track->textures[i].cpp = 64;
+ track->textures[i].robj = NULL;
+ /* CS IB emission code makes sure texture unit are disabled */
+ track->textures[i].enabled = false;
+ track->textures[i].roundup_w = true;
+ track->textures[i].roundup_h = true;
+ if (track->separate_cube)
+ for (face = 0; face < 5; face++) {
+ track->textures[i].cube_info[face].robj = NULL;
+ track->textures[i].cube_info[face].width = 16536;
+ track->textures[i].cube_info[face].height = 16536;
+ track->textures[i].cube_info[face].offset = 0;
+ }
+ }
+}
+
+int r100_ring_test(struct radeon_device *rdev)
+{
+ uint32_t scratch;
+ uint32_t tmp = 0;
+ unsigned i;
+ int r;
+
+ r = radeon_scratch_get(rdev, &scratch);
+ if (r) {
+ DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
+ return r;
+ }
+ WREG32(scratch, 0xCAFEDEAD);
+ r = radeon_ring_lock(rdev, 2);
+ if (r) {
+ DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+ radeon_scratch_free(rdev, scratch);
+ return r;
+ }
+ radeon_ring_write(rdev, PACKET0(scratch, 0));
+ radeon_ring_write(rdev, 0xDEADBEEF);
+ radeon_ring_unlock_commit(rdev);
+ for (i = 0; i < rdev->usec_timeout; i++) {
+ tmp = RREG32(scratch);
+ if (tmp == 0xDEADBEEF) {
+ break;
+ }
+ DRM_UDELAY(1);
+ }
+ if (i < rdev->usec_timeout) {
+ DRM_INFO("ring test succeeded in %d usecs\n", i);
+ } else {
+ DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
+ scratch, tmp);
+ r = -EINVAL;
+ }
+ radeon_scratch_free(rdev, scratch);
+ return r;
+}
+
+void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
+{
+ radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
+ radeon_ring_write(rdev, ib->gpu_addr);
+ radeon_ring_write(rdev, ib->length_dw);
+}
+
+int r100_ib_test(struct radeon_device *rdev)
+{
+ struct radeon_ib *ib;
+ uint32_t scratch;
+ uint32_t tmp = 0;
+ unsigned i;
+ int r;
+
+ r = radeon_scratch_get(rdev, &scratch);
+ if (r) {
+ DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
+ return r;
+ }
+ WREG32(scratch, 0xCAFEDEAD);
+ r = radeon_ib_get(rdev, &ib);
+ if (r) {
+ return r;
+ }
+ ib->ptr[0] = PACKET0(scratch, 0);
+ ib->ptr[1] = 0xDEADBEEF;
+ ib->ptr[2] = PACKET2(0);
+ ib->ptr[3] = PACKET2(0);
+ ib->ptr[4] = PACKET2(0);
+ ib->ptr[5] = PACKET2(0);
+ ib->ptr[6] = PACKET2(0);
+ ib->ptr[7] = PACKET2(0);
+ ib->length_dw = 8;
+ r = radeon_ib_schedule(rdev, ib);
+ if (r) {
+ radeon_scratch_free(rdev, scratch);
+ radeon_ib_free(rdev, &ib);
+ return r;
+ }
+ r = radeon_fence_wait(ib->fence, false);
+ if (r) {
+ return r;
+ }
+ for (i = 0; i < rdev->usec_timeout; i++) {
+ tmp = RREG32(scratch);
+ if (tmp == 0xDEADBEEF) {
+ break;
+ }
+ DRM_UDELAY(1);
+ }
+ if (i < rdev->usec_timeout) {
+ DRM_INFO("ib test succeeded in %u usecs\n", i);
+ } else {
+ DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
+ scratch, tmp);
+ r = -EINVAL;
+ }
+ radeon_scratch_free(rdev, scratch);
+ radeon_ib_free(rdev, &ib);
+ return r;
+}
+
+void r100_ib_fini(struct radeon_device *rdev)
+{
+ radeon_ib_pool_fini(rdev);
+}
+
+int r100_ib_init(struct radeon_device *rdev)
+{
+ int r;
+
+ r = radeon_ib_pool_init(rdev);
+ if (r) {
+ dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
+ r100_ib_fini(rdev);
+ return r;
+ }
+ r = r100_ib_test(rdev);
+ if (r) {
+ dev_err(rdev->dev, "failled testing IB (%d).\n", r);
+ r100_ib_fini(rdev);
+ return r;
+ }
+ return 0;
+}
+
+void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
+{
+ /* Shutdown CP we shouldn't need to do that but better be safe than
+ * sorry
+ */
+ rdev->cp.ready = false;
+ WREG32(R_000740_CP_CSQ_CNTL, 0);
+
+ /* Save few CRTC registers */
+ save->GENMO_WT = RREG32(R_0003C0_GENMO_WT);
+ save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
+ save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
+ save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
+ if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+ save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
+ save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
+ }
+
+ /* Disable VGA aperture access */
+ WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT);
+ /* Disable cursor, overlay, crtc */
+ WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
+ WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
+ S_000054_CRTC_DISPLAY_DIS(1));
+ WREG32(R_000050_CRTC_GEN_CNTL,
+ (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
+ S_000050_CRTC_DISP_REQ_EN_B(1));
+ WREG32(R_000420_OV0_SCALE_CNTL,
+ C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
+ WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
+ if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+ WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
+ S_000360_CUR2_LOCK(1));
+ WREG32(R_0003F8_CRTC2_GEN_CNTL,
+ (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
+ S_0003F8_CRTC2_DISPLAY_DIS(1) |
+ S_0003F8_CRTC2_DISP_REQ_EN_B(1));
+ WREG32(R_000360_CUR2_OFFSET,
+ C_000360_CUR2_LOCK & save->CUR2_OFFSET);
+ }
+}
+
+void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
+{
+ /* Update base address for crtc */
+ WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
+ if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+ WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
+ rdev->mc.vram_location);
+ }
+ /* Restore CRTC registers */
+ WREG32(R_0003C0_GENMO_WT, save->GENMO_WT);
+ WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
+ WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
+ if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+ WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
+ }
+}
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
new file mode 100644
index 0000000..70a82ed
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -0,0 +1,124 @@
+
+#define R100_TRACK_MAX_TEXTURE 3
+#define R200_TRACK_MAX_TEXTURE 6
+#define R300_TRACK_MAX_TEXTURE 16
+
+#define R100_MAX_CB 1
+#define R300_MAX_CB 4
+
+/*
+ * CS functions
+ */
+struct r100_cs_track_cb {
+ struct radeon_object *robj;
+ unsigned pitch;
+ unsigned cpp;
+ unsigned offset;
+};
+
+struct r100_cs_track_array {
+ struct radeon_object *robj;
+ unsigned esize;
+};
+
+struct r100_cs_cube_info {
+ struct radeon_object *robj;
+ unsigned offset;
+ unsigned width;
+ unsigned height;
+};
+
+struct r100_cs_track_texture {
+ struct radeon_object *robj;
+ struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
+ unsigned pitch;
+ unsigned width;
+ unsigned height;
+ unsigned num_levels;
+ unsigned cpp;
+ unsigned tex_coord_type;
+ unsigned txdepth;
+ unsigned width_11;
+ unsigned height_11;
+ bool use_pitch;
+ bool enabled;
+ bool roundup_w;
+ bool roundup_h;
+};
+
+struct r100_cs_track_limits {
+ unsigned num_cb;
+ unsigned num_texture;
+ unsigned max_levels;
+};
+
+struct r100_cs_track {
+ struct radeon_device *rdev;
+ unsigned num_cb;
+ unsigned num_texture;
+ unsigned maxy;
+ unsigned vtx_size;
+ unsigned vap_vf_cntl;
+ unsigned immd_dwords;
+ unsigned num_arrays;
+ unsigned max_indx;
+ struct r100_cs_track_array arrays[11];
+ struct r100_cs_track_cb cb[R300_MAX_CB];
+ struct r100_cs_track_cb zb;
+ struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
+ bool z_enabled;
+ bool separate_cube;
+
+};
+
+int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
+void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
+int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
+ struct radeon_cs_reloc **cs_reloc);
+void r100_cs_dump_packet(struct radeon_cs_parser *p,
+ struct radeon_cs_packet *pkt);
+
+int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
+
+int r200_packet0_check(struct radeon_cs_parser *p,
+ struct radeon_cs_packet *pkt,
+ unsigned idx, unsigned reg);
+
+static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
+ struct radeon_cs_packet *pkt,
+ unsigned idx,
+ unsigned reg)
+{
+ int r;
+ u32 tile_flags = 0;
+ u32 tmp;
+ struct radeon_cs_reloc *reloc;
+ struct radeon_cs_chunk *ib_chunk;
+
+ ib_chunk = &p->chunks[p->chunk_ib_idx];
+
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ tmp = ib_chunk->kdata[idx] & 0x003fffff;
+ tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
+
+ if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+ tile_flags |= RADEON_DST_TILE_MACRO;
+ if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
+ if (reg == RADEON_SRC_PITCH_OFFSET) {
+ DRM_ERROR("Cannot src blit from microtiled surface\n");
+ r100_cs_dump_packet(p, pkt);
+ return -EINVAL;
+ }
+ tile_flags |= RADEON_DST_TILE_MICRO;
+ }
+
+ tmp |= tile_flags;
+ p->ib->ptr[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
+ return 0;
+}
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h
new file mode 100644
index 0000000..c4b257e
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r100d.h
@@ -0,0 +1,607 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ * Alex Deucher
+ * Jerome Glisse
+ */
+#ifndef __R100D_H__
+#define __R100D_H__
+
+#define CP_PACKET0 0x00000000
+#define PACKET0_BASE_INDEX_SHIFT 0
+#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
+#define PACKET0_COUNT_SHIFT 16
+#define PACKET0_COUNT_MASK (0x3fff << 16)
+#define CP_PACKET1 0x40000000
+#define CP_PACKET2 0x80000000
+#define PACKET2_PAD_SHIFT 0
+#define PACKET2_PAD_MASK (0x3fffffff << 0)
+#define CP_PACKET3 0xC0000000
+#define PACKET3_IT_OPCODE_SHIFT 8
+#define PACKET3_IT_OPCODE_MASK (0xff << 8)
+#define PACKET3_COUNT_SHIFT 16
+#define PACKET3_COUNT_MASK (0x3fff << 16)
+/* PACKET3 op code */
+#define PACKET3_NOP 0x10
+#define PACKET3_3D_DRAW_VBUF 0x28
+#define PACKET3_3D_DRAW_IMMD 0x29
+#define PACKET3_3D_DRAW_INDX 0x2A
+#define PACKET3_3D_LOAD_VBPNTR 0x2F
+#define PACKET3_INDX_BUFFER 0x33
+#define PACKET3_3D_DRAW_VBUF_2 0x34
+#define PACKET3_3D_DRAW_IMMD_2 0x35
+#define PACKET3_3D_DRAW_INDX_2 0x36
+#define PACKET3_BITBLT_MULTI 0x9B
+
+#define PACKET0(reg, n) (CP_PACKET0 | \
+ REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
+ REG_SET(PACKET0_COUNT, (n)))
+#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
+#define PACKET3(op, n) (CP_PACKET3 | \
+ REG_SET(PACKET3_IT_OPCODE, (op)) | \
+ REG_SET(PACKET3_COUNT, (n)))
+
+#define PACKET_TYPE0 0
+#define PACKET_TYPE1 1
+#define PACKET_TYPE2 2
+#define PACKET_TYPE3 3
+
+#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
+#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
+#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
+#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
+#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
+
+/* Registers */
+#define R_000040_GEN_INT_CNTL 0x000040
+#define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0)
+#define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1)
+#define C_000040_CRTC_VBLANK 0xFFFFFFFE
+#define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1)
+#define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1)
+#define C_000040_CRTC_VLINE 0xFFFFFFFD
+#define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2)
+#define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1)
+#define C_000040_CRTC_VSYNC 0xFFFFFFFB
+#define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3)
+#define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1)
+#define C_000040_SNAPSHOT 0xFFFFFFF7
+#define S_000040_FP_DETECT(x) (((x) & 0x1) << 4)
+#define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1)
+#define C_000040_FP_DETECT 0xFFFFFFEF
+#define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5)
+#define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1)
+#define C_000040_CRTC2_VLINE 0xFFFFFFDF
+#define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12)
+#define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1)
+#define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF
+#define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6)
+#define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1)
+#define C_000040_CRTC2_VSYNC 0xFFFFFFBF
+#define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7)
+#define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1)
+#define C_000040_SNAPSHOT2 0xFFFFFF7F
+#define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9)
+#define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1)
+#define C_000040_CRTC2_VBLANK 0xFFFFFDFF
+#define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10)
+#define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1)
+#define C_000040_FP2_DETECT 0xFFFFFBFF
+#define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11)
+#define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1)
+#define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF
+#define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13)
+#define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1)
+#define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF
+#define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14)
+#define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1)
+#define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF
+#define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15)
+#define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1)
+#define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF
+#define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17)
+#define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1)
+#define C_000040_I2C_INT_EN 0xFFFDFFFF
+#define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19)
+#define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1)
+#define C_000040_GUI_IDLE 0xFFF7FFFF
+#define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24)
+#define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1)
+#define C_000040_VIPH_INT_EN 0xFEFFFFFF
+#define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25)
+#define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1)
+#define C_000040_SW_INT_EN 0xFDFFFFFF
+#define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27)
+#define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1)
+#define C_000040_GEYSERVILLE 0xF7FFFFFF
+#define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28)
+#define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1)
+#define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF
+#define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29)
+#define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1)
+#define C_000040_DVI_I2C_INT 0xDFFFFFFF
+#define S_000040_GUIDMA(x) (((x) & 0x1) << 30)
+#define G_000040_GUIDMA(x) (((x) >> 30) & 0x1)
+#define C_000040_GUIDMA 0xBFFFFFFF
+#define S_000040_VIDDMA(x) (((x) & 0x1) << 31)
+#define G_000040_VIDDMA(x) (((x) >> 31) & 0x1)
+#define C_000040_VIDDMA 0x7FFFFFFF
+#define R_000044_GEN_INT_STATUS 0x000044
+#define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0)
+#define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1)
+#define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE
+#define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0)
+#define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1)
+#define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE
+#define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1)
+#define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1)
+#define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD
+#define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1)
+#define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1)
+#define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD
+#define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2)
+#define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1)
+#define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB
+#define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2)
+#define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1)
+#define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB
+#define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3)
+#define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1)
+#define C_000044_SNAPSHOT_STAT 0xFFFFFFF7
+#define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3)
+#define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1)
+#define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7
+#define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4)
+#define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1)
+#define C_000044_FP_DETECT_STAT 0xFFFFFFEF
+#define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4)
+#define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1)
+#define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF
+#define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5)
+#define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1)
+#define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF
+#define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5)
+#define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1)
+#define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF
+#define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6)
+#define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1)
+#define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF
+#define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6)
+#define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1)
+#define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF
+#define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7)
+#define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1)
+#define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F
+#define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7)
+#define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1)
+#define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F
+#define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8)
+#define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1)
+#define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF
+#define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9)
+#define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1)
+#define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF
+#define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9)
+#define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1)
+#define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF
+#define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10)
+#define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1)
+#define C_000044_FP2_DETECT_STAT 0xFFFFFBFF
+#define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10)
+#define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1)
+#define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF
+#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11)
+#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1)
+#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF
+#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11)
+#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1)
+#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF
+#define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12)
+#define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1)
+#define C_000044_DMA_VIPH0_INT 0xFFFFEFFF
+#define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12)
+#define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1)
+#define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF
+#define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13)
+#define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1)
+#define C_000044_DMA_VIPH1_INT 0xFFFFDFFF
+#define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13)
+#define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1)
+#define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF
+#define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14)
+#define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1)
+#define C_000044_DMA_VIPH2_INT 0xFFFFBFFF
+#define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14)
+#define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1)
+#define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF
+#define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15)
+#define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1)
+#define C_000044_DMA_VIPH3_INT 0xFFFF7FFF
+#define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15)
+#define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1)
+#define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF
+#define S_000044_I2C_INT(x) (((x) & 0x1) << 17)
+#define G_000044_I2C_INT(x) (((x) >> 17) & 0x1)
+#define C_000044_I2C_INT 0xFFFDFFFF
+#define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17)
+#define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1)
+#define C_000044_I2C_INT_AK 0xFFFDFFFF
+#define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19)
+#define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1)
+#define C_000044_GUI_IDLE_STAT 0xFFF7FFFF
+#define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19)
+#define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1)
+#define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF
+#define S_000044_VIPH_INT(x) (((x) & 0x1) << 24)
+#define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1)
+#define C_000044_VIPH_INT 0xFEFFFFFF
+#define S_000044_SW_INT(x) (((x) & 0x1) << 25)
+#define G_000044_SW_INT(x) (((x) >> 25) & 0x1)
+#define C_000044_SW_INT 0xFDFFFFFF
+#define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25)
+#define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1)
+#define C_000044_SW_INT_AK 0xFDFFFFFF
+#define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26)
+#define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1)
+#define C_000044_SW_INT_SET 0xFBFFFFFF
+#define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27)
+#define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1)
+#define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF
+#define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27)
+#define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1)
+#define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF
+#define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28)
+#define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1)
+#define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF
+#define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28)
+#define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1)
+#define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF
+#define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29)
+#define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1)
+#define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF
+#define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29)
+#define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1)
+#define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF
+#define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30)
+#define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1)
+#define C_000044_GUIDMA_STAT 0xBFFFFFFF
+#define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30)
+#define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1)
+#define C_000044_GUIDMA_AK 0xBFFFFFFF
+#define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31)
+#define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1)
+#define C_000044_VIDDMA_STAT 0x7FFFFFFF
+#define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31)
+#define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1)
+#define C_000044_VIDDMA_AK 0x7FFFFFFF
+#define R_000050_CRTC_GEN_CNTL 0x000050
+#define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0)
+#define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1)
+#define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE
+#define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1)
+#define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1)
+#define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD
+#define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4)
+#define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1)
+#define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF
+#define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8)
+#define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF)
+#define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF
+#define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15)
+#define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1)
+#define C_000050_CRTC_ICON_EN 0xFFFF7FFF
+#define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16)
+#define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1)
+#define C_000050_CRTC_CUR_EN 0xFFFEFFFF
+#define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17)
+#define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3)
+#define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF
+#define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20)
+#define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7)
+#define C_000050_CRTC_CUR_MODE 0xFF8FFFFF
+#define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24)
+#define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1)
+#define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF
+#define S_000050_CRTC_EN(x) (((x) & 0x1) << 25)
+#define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1)
+#define C_000050_CRTC_EN 0xFDFFFFFF
+#define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26)
+#define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1)
+#define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF
+#define R_000054_CRTC_EXT_CNTL 0x000054
+#define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0)
+#define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1)
+#define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE
+#define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1)
+#define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3)
+#define C_000054_VGA_BLINK_RATE 0xFFFFFFF9
+#define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3)
+#define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1)
+#define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7
+#define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4)
+#define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1)
+#define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF
+#define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5)
+#define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1)
+#define C_000054_VGA_TEXT_132 0xFFFFFFDF
+#define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6)
+#define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1)
+#define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF
+#define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8)
+#define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1)
+#define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF
+#define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9)
+#define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1)
+#define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF
+#define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10)
+#define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1)
+#define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF
+#define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11)
+#define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1)
+#define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF
+#define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12)
+#define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1)
+#define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF
+#define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13)
+#define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1)
+#define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF
+#define S_000054_CRT_ON(x) (((x) & 0x1) << 15)
+#define G_000054_CRT_ON(x) (((x) >> 15) & 0x1)
+#define C_000054_CRT_ON 0xFFFF7FFF
+#define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17)
+#define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1)
+#define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF
+#define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18)
+#define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1)
+#define C_000054_VGA_PACK_DIS 0xFFFBFFFF
+#define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19)
+#define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1)
+#define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF
+#define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24)
+#define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F)
+#define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF
+#define R_00023C_DISPLAY_BASE_ADDR 0x00023C
+#define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00023C_DISPLAY_BASE_ADDR 0x00000000
+#define R_000260_CUR_OFFSET 0x000260
+#define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0)
+#define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF)
+#define C_000260_CUR_OFFSET 0xF8000000
+#define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31)
+#define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1)
+#define C_000260_CUR_LOCK 0x7FFFFFFF
+#define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C
+#define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000
+#define R_000360_CUR2_OFFSET 0x000360
+#define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0)
+#define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF)
+#define C_000360_CUR2_OFFSET 0xF8000000
+#define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31)
+#define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1)
+#define C_000360_CUR2_LOCK 0x7FFFFFFF
+#define R_0003C0_GENMO_WT 0x0003C0
+#define S_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0)
+#define G_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1)
+#define C_0003C0_GENMO_MONO_ADDRESS_B 0xFFFFFFFE
+#define S_0003C0_VGA_RAM_EN(x) (((x) & 0x1) << 1)
+#define G_0003C0_VGA_RAM_EN(x) (((x) >> 1) & 0x1)
+#define C_0003C0_VGA_RAM_EN 0xFFFFFFFD
+#define S_0003C0_VGA_CKSEL(x) (((x) & 0x3) << 2)
+#define G_0003C0_VGA_CKSEL(x) (((x) >> 2) & 0x3)
+#define C_0003C0_VGA_CKSEL 0xFFFFFFF3
+#define S_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5)
+#define G_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1)
+#define C_0003C0_ODD_EVEN_MD_PGSEL 0xFFFFFFDF
+#define S_0003C0_VGA_HSYNC_POL(x) (((x) & 0x1) << 6)
+#define G_0003C0_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1)
+#define C_0003C0_VGA_HSYNC_POL 0xFFFFFFBF
+#define S_0003C0_VGA_VSYNC_POL(x) (((x) & 0x1) << 7)
+#define G_0003C0_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1)
+#define C_0003C0_VGA_VSYNC_POL 0xFFFFFF7F
+#define R_0003F8_CRTC2_GEN_CNTL 0x0003F8
+#define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0)
+#define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1)
+#define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE
+#define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1)
+#define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1)
+#define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD
+#define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4)
+#define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1)
+#define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF
+#define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5)
+#define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1)
+#define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF
+#define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6)
+#define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1)
+#define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF
+#define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7)
+#define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1)
+#define C_0003F8_CRT2_ON 0xFFFFFF7F
+#define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8)
+#define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF)
+#define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF
+#define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15)
+#define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1)
+#define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF
+#define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16)
+#define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1)
+#define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF
+#define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20)
+#define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7)
+#define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF
+#define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23)
+#define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1)
+#define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF
+#define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25)
+#define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1)
+#define C_0003F8_CRTC2_EN 0xFDFFFFFF
+#define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26)
+#define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1)
+#define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF
+#define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27)
+#define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1)
+#define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF
+#define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28)
+#define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1)
+#define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF
+#define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29)
+#define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1)
+#define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF
+#define R_000420_OV0_SCALE_CNTL 0x000420
+#define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1)
+#define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1)
+#define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD
+#define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2)
+#define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1)
+#define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB
+#define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3)
+#define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1)
+#define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7
+#define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4)
+#define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1)
+#define C_000420_OV0_SIGNED_UV 0xFFFFFFEF
+#define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5)
+#define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7)
+#define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F
+#define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8)
+#define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF)
+#define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF
+#define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12)
+#define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1)
+#define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF
+#define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14)
+#define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1)
+#define C_000420_OV0_CRTC_SEL 0xFFFFBFFF
+#define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16)
+#define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F)
+#define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF
+#define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24)
+#define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1)
+#define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF
+#define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26)
+#define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1)
+#define C_000420_OV0_BANDWIDTH 0xFBFFFFFF
+#define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28)
+#define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1)
+#define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF
+#define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29)
+#define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1)
+#define C_000420_OV0_INT_EMU 0xDFFFFFFF
+#define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30)
+#define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1)
+#define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF
+#define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31)
+#define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1)
+#define C_000420_OV0_SOFT_RESET 0x7FFFFFFF
+#define R_00070C_CP_RB_RPTR_ADDR 0x00070C
+#define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0)
+#define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3)
+#define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC
+#define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2)
+#define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF)
+#define C_00070C_RB_RPTR_ADDR 0x00000003
+#define R_000740_CP_CSQ_CNTL 0x000740
+#define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0)
+#define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF)
+#define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00
+#define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8)
+#define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF)
+#define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF
+#define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28)
+#define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF)
+#define C_000740_CSQ_MODE 0x0FFFFFFF
+#define R_000770_SCRATCH_UMSK 0x000770
+#define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0)
+#define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F)
+#define C_000770_SCRATCH_UMSK 0xFFFFFFC0
+#define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16)
+#define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3)
+#define C_000770_SCRATCH_SWAP 0xFFFCFFFF
+#define R_000774_SCRATCH_ADDR 0x000774
+#define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5)
+#define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF)
+#define C_000774_SCRATCH_ADDR 0x0000001F
+#define R_000E40_RBBM_STATUS 0x000E40
+#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
+#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
+#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
+#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
+#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
+#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
+#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
+#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
+#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
+#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
+#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
+#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
+#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
+#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
+#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
+#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
+#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
+#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
+#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
+#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
+#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
+#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
+#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
+#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
+#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
+#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
+#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
+#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
+#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
+#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
+#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
+#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
+#define C_000E40_E2_BUSY 0xFFFDFFFF
+#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
+#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
+#define C_000E40_RB2D_BUSY 0xFFFBFFFF
+#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
+#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
+#define C_000E40_RB3D_BUSY 0xFFF7FFFF
+#define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20)
+#define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1)
+#define C_000E40_SE_BUSY 0xFFEFFFFF
+#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
+#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
+#define C_000E40_RE_BUSY 0xFFDFFFFF
+#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
+#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
+#define C_000E40_TAM_BUSY 0xFFBFFFFF
+#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
+#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
+#define C_000E40_TDM_BUSY 0xFF7FFFFF
+#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
+#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
+#define C_000E40_PB_BUSY 0xFEFFFFFF
+#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
+#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
+#define C_000E40_GUI_ACTIVE 0x7FFFFFFF
+
+#endif
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
new file mode 100644
index 0000000..568c74b
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -0,0 +1,456 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ * Alex Deucher
+ * Jerome Glisse
+ */
+#include "drmP.h"
+#include "drm.h"
+#include "radeon_drm.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+#include "r200_reg_safe.h"
+
+#include "r100_track.h"
+
+static int r200_get_vtx_size_0(uint32_t vtx_fmt_0)
+{
+ int vtx_size, i;
+ vtx_size = 2;
+
+ if (vtx_fmt_0 & R200_VTX_Z0)
+ vtx_size++;
+ if (vtx_fmt_0 & R200_VTX_W0)
+ vtx_size++;
+ /* blend weight */
+ if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT))
+ vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7;
+ if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL)
+ vtx_size++;
+ if (vtx_fmt_0 & R200_VTX_N0)
+ vtx_size += 3;
+ if (vtx_fmt_0 & R200_VTX_POINT_SIZE)
+ vtx_size++;
+ if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG)
+ vtx_size++;
+ if (vtx_fmt_0 & R200_VTX_SHININESS_0)
+ vtx_size++;
+ if (vtx_fmt_0 & R200_VTX_SHININESS_1)
+ vtx_size++;
+ for (i = 0; i < 8; i++) {
+ int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3;
+ switch (color_size) {
+ case 0: break;
+ case 1: vtx_size++; break;
+ case 2: vtx_size += 3; break;
+ case 3: vtx_size += 4; break;
+ }
+ }
+ if (vtx_fmt_0 & R200_VTX_XY1)
+ vtx_size += 2;
+ if (vtx_fmt_0 & R200_VTX_Z1)
+ vtx_size++;
+ if (vtx_fmt_0 & R200_VTX_W1)
+ vtx_size++;
+ if (vtx_fmt_0 & R200_VTX_N1)
+ vtx_size += 3;
+ return vtx_size;
+}
+
+static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
+{
+ int vtx_size, i, tex_size;
+ vtx_size = 0;
+ for (i = 0; i < 6; i++) {
+ tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7;
+ if (tex_size > 4)
+ continue;
+ vtx_size += tex_size;
+ }
+ return vtx_size;
+}
+
+int r200_packet0_check(struct radeon_cs_parser *p,
+ struct radeon_cs_packet *pkt,
+ unsigned idx, unsigned reg)
+{
+ struct radeon_cs_chunk *ib_chunk;
+ struct radeon_cs_reloc *reloc;
+ struct r100_cs_track *track;
+ volatile uint32_t *ib;
+ uint32_t tmp;
+ int r;
+ int i;
+ int face;
+ u32 tile_flags = 0;
+
+ ib = p->ib->ptr;
+ ib_chunk = &p->chunks[p->chunk_ib_idx];
+ track = (struct r100_cs_track *)p->track;
+
+ switch (reg) {
+ case RADEON_CRTC_GUI_TRIG_VLINE:
+ r = r100_cs_packet_parse_vline(p);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ break;
+ /* FIXME: only allow PACKET3 blit? easier to check for out of
+ * range access */
+ case RADEON_DST_PITCH_OFFSET:
+ case RADEON_SRC_PITCH_OFFSET:
+ r = r100_reloc_pitch_offset(p, pkt, idx, reg);
+ if (r)
+ return r;
+ break;
+ case RADEON_RB3D_DEPTHOFFSET:
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ track->zb.robj = reloc->robj;
+ track->zb.offset = ib_chunk->kdata[idx];
+ ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ break;
+ case RADEON_RB3D_COLOROFFSET:
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ track->cb[0].robj = reloc->robj;
+ track->cb[0].offset = ib_chunk->kdata[idx];
+ ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ break;
+ case R200_PP_TXOFFSET_0:
+ case R200_PP_TXOFFSET_1:
+ case R200_PP_TXOFFSET_2:
+ case R200_PP_TXOFFSET_3:
+ case R200_PP_TXOFFSET_4:
+ case R200_PP_TXOFFSET_5:
+ i = (reg - R200_PP_TXOFFSET_0) / 24;
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ track->textures[i].robj = reloc->robj;
+ break;
+ case R200_PP_CUBIC_OFFSET_F1_0:
+ case R200_PP_CUBIC_OFFSET_F2_0:
+ case R200_PP_CUBIC_OFFSET_F3_0:
+ case R200_PP_CUBIC_OFFSET_F4_0:
+ case R200_PP_CUBIC_OFFSET_F5_0:
+ case R200_PP_CUBIC_OFFSET_F1_1:
+ case R200_PP_CUBIC_OFFSET_F2_1:
+ case R200_PP_CUBIC_OFFSET_F3_1:
+ case R200_PP_CUBIC_OFFSET_F4_1:
+ case R200_PP_CUBIC_OFFSET_F5_1:
+ case R200_PP_CUBIC_OFFSET_F1_2:
+ case R200_PP_CUBIC_OFFSET_F2_2:
+ case R200_PP_CUBIC_OFFSET_F3_2:
+ case R200_PP_CUBIC_OFFSET_F4_2:
+ case R200_PP_CUBIC_OFFSET_F5_2:
+ case R200_PP_CUBIC_OFFSET_F1_3:
+ case R200_PP_CUBIC_OFFSET_F2_3:
+ case R200_PP_CUBIC_OFFSET_F3_3:
+ case R200_PP_CUBIC_OFFSET_F4_3:
+ case R200_PP_CUBIC_OFFSET_F5_3:
+ case R200_PP_CUBIC_OFFSET_F1_4:
+ case R200_PP_CUBIC_OFFSET_F2_4:
+ case R200_PP_CUBIC_OFFSET_F3_4:
+ case R200_PP_CUBIC_OFFSET_F4_4:
+ case R200_PP_CUBIC_OFFSET_F5_4:
+ case R200_PP_CUBIC_OFFSET_F1_5:
+ case R200_PP_CUBIC_OFFSET_F2_5:
+ case R200_PP_CUBIC_OFFSET_F3_5:
+ case R200_PP_CUBIC_OFFSET_F4_5:
+ case R200_PP_CUBIC_OFFSET_F5_5:
+ i = (reg - R200_PP_TXOFFSET_0) / 24;
+ face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ track->textures[i].cube_info[face - 1].offset = ib_chunk->kdata[idx];
+ ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ track->textures[i].cube_info[face - 1].robj = reloc->robj;
+ break;
+ case RADEON_RE_WIDTH_HEIGHT:
+ track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF);
+ break;
+ case RADEON_RB3D_COLORPITCH:
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+
+ if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+ tile_flags |= RADEON_COLOR_TILE_ENABLE;
+ if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+ tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
+
+ tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
+ tmp |= tile_flags;
+ ib[idx] = tmp;
+
+ track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK;
+ break;
+ case RADEON_RB3D_DEPTHPITCH:
+ track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK;
+ break;
+ case RADEON_RB3D_CNTL:
+ switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
+ case 7:
+ case 8:
+ case 9:
+ case 11:
+ case 12:
+ track->cb[0].cpp = 1;
+ break;
+ case 3:
+ case 4:
+ case 15:
+ track->cb[0].cpp = 2;
+ break;
+ case 6:
+ track->cb[0].cpp = 4;
+ break;
+ default:
+ DRM_ERROR("Invalid color buffer format (%d) !\n",
+ ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
+ return -EINVAL;
+ }
+ if (ib_chunk->kdata[idx] & RADEON_DEPTHXY_OFFSET_ENABLE) {
+ DRM_ERROR("No support for depth xy offset in kms\n");
+ return -EINVAL;
+ }
+
+ track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE);
+ break;
+ case RADEON_RB3D_ZSTENCILCNTL:
+ switch (ib_chunk->kdata[idx] & 0xf) {
+ case 0:
+ track->zb.cpp = 2;
+ break;
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 9:
+ case 11:
+ track->zb.cpp = 4;
+ break;
+ default:
+ break;
+ }
+ break;
+ case RADEON_RB3D_ZPASS_ADDR:
+ r = r100_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+ idx, reg);
+ r100_cs_dump_packet(p, pkt);
+ return r;
+ }
+ ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+ break;
+ case RADEON_PP_CNTL:
+ {
+ uint32_t temp = ib_chunk->kdata[idx] >> 4;
+ for (i = 0; i < track->num_texture; i++)
+ track->textures[i].enabled = !!(temp & (1 << i));
+ }
+ break;
+ case RADEON_SE_VF_CNTL:
+ track->vap_vf_cntl = ib_chunk->kdata[idx];
+ break;
+ case 0x210c:
+ /* VAP_VF_MAX_VTX_INDX */
+ track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL;
+ break;
+ case R200_SE_VTX_FMT_0:
+ track->vtx_size = r200_get_vtx_size_0(ib_chunk->kdata[idx]);
+ break;
+ case R200_SE_VTX_FMT_1:
+ track->vtx_size += r200_get_vtx_size_1(ib_chunk->kdata[idx]);
+ break;
+ case R200_PP_TXSIZE_0:
+ case R200_PP_TXSIZE_1:
+ case R200_PP_TXSIZE_2:
+ case R200_PP_TXSIZE_3:
+ case R200_PP_TXSIZE_4:
+ case R200_PP_TXSIZE_5:
+ i = (reg - R200_PP_TXSIZE_0) / 32;
+ track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1;
+ track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
+ break;
+ case R200_PP_TXPITCH_0:
+ case R200_PP_TXPITCH_1:
+ case R200_PP_TXPITCH_2:
+ case R200_PP_TXPITCH_3:
+ case R200_PP_TXPITCH_4:
+ case R200_PP_TXPITCH_5:
+ i = (reg - R200_PP_TXPITCH_0) / 32;
+ track->textures[i].pitch = ib_chunk->kdata[idx] + 32;
+ break;
+ case R200_PP_TXFILTER_0:
+ case R200_PP_TXFILTER_1:
+ case R200_PP_TXFILTER_2:
+ case R200_PP_TXFILTER_3:
+ case R200_PP_TXFILTER_4:
+ case R200_PP_TXFILTER_5:
+ i = (reg - R200_PP_TXFILTER_0) / 32;
+ track->textures[i].num_levels = ((ib_chunk->kdata[idx] & R200_MAX_MIP_LEVEL_MASK)
+ >> R200_MAX_MIP_LEVEL_SHIFT);
+ tmp = (ib_chunk->kdata[idx] >> 23) & 0x7;
+ if (tmp == 2 || tmp == 6)
+ track->textures[i].roundup_w = false;
+ tmp = (ib_chunk->kdata[idx] >> 27) & 0x7;
+ if (tmp == 2 || tmp == 6)
+ track->textures[i].roundup_h = false;
+ break;
+ case R200_PP_TXMULTI_CTL_0:
+ case R200_PP_TXMULTI_CTL_1:
+ case R200_PP_TXMULTI_CTL_2:
+ case R200_PP_TXMULTI_CTL_3:
+ case R200_PP_TXMULTI_CTL_4:
+ case R200_PP_TXMULTI_CTL_5:
+ i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
+ break;
+ case R200_PP_TXFORMAT_X_0:
+ case R200_PP_TXFORMAT_X_1:
+ case R200_PP_TXFORMAT_X_2:
+ case R200_PP_TXFORMAT_X_3:
+ case R200_PP_TXFORMAT_X_4:
+ case R200_PP_TXFORMAT_X_5:
+ i = (reg - R200_PP_TXFORMAT_X_0) / 32;
+ track->textures[i].txdepth = ib_chunk->kdata[idx] & 0x7;
+ tmp = (ib_chunk->kdata[idx] >> 16) & 0x3;
+ /* 2D, 3D, CUBE */
+ switch (tmp) {
+ case 0:
+ case 5:
+ case 6:
+ case 7:
+ track->textures[i].tex_coord_type = 0;
+ break;
+ case 1:
+ track->textures[i].tex_coord_type = 1;
+ break;
+ case 2:
+ track->textures[i].tex_coord_type = 2;
+ break;
+ }
+ break;
+ case R200_PP_TXFORMAT_0:
+ case R200_PP_TXFORMAT_1:
+ case R200_PP_TXFORMAT_2:
+ case R200_PP_TXFORMAT_3:
+ case R200_PP_TXFORMAT_4:
+ case R200_PP_TXFORMAT_5:
+ i = (reg - R200_PP_TXFORMAT_0) / 32;
+ if (ib_chunk->kdata[idx] & R200_TXFORMAT_NON_POWER2) {
+ track->textures[i].use_pitch = 1;
+ } else {
+ track->textures[i].use_pitch = 0;
+ track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
+ track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
+ }
+ switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) {
+ case R200_TXFORMAT_I8:
+ case R200_TXFORMAT_RGB332:
+ case R200_TXFORMAT_Y8:
+ track->textures[i].cpp = 1;
+ break;
+ case R200_TXFORMAT_DXT1:
+ case R200_TXFORMAT_AI88:
+ case R200_TXFORMAT_ARGB1555:
+ case R200_TXFORMAT_RGB565:
+ case R200_TXFORMAT_ARGB4444:
+ case R200_TXFORMAT_VYUY422:
+ case R200_TXFORMAT_YVYU422:
+ case R200_TXFORMAT_LDVDU655:
+ case R200_TXFORMAT_DVDU88:
+ case R200_TXFORMAT_AVYU4444:
+ track->textures[i].cpp = 2;
+ break;
+ case R200_TXFORMAT_ARGB8888:
+ case R200_TXFORMAT_RGBA8888:
+ case R200_TXFORMAT_ABGR8888:
+ case R200_TXFORMAT_BGR111110:
+ case R200_TXFORMAT_LDVDU8888:
+ case R200_TXFORMAT_DXT23:
+ case R200_TXFORMAT_DXT45:
+ track->textures[i].cpp = 4;
+ break;
+ }
+ track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf);
+ track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf);
+ break;
+ case R200_PP_CUBIC_FACES_0:
+ case R200_PP_CUBIC_FACES_1:
+ case R200_PP_CUBIC_FACES_2:
+ case R200_PP_CUBIC_FACES_3:
+ case R200_PP_CUBIC_FACES_4:
+ case R200_PP_CUBIC_FACES_5:
+ tmp = ib_chunk->kdata[idx];
+ i = (reg - R200_PP_CUBIC_FACES_0) / 32;
+ for (face = 0; face < 4; face++) {
+ track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
+ track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
+ }
+ break;
+ default:
+ printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
+ reg, idx);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+int r200_init(struct radeon_device *rdev)
+{
+ rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
+ rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);
+ return 0;
+}
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 051bca6..bb151ec 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -31,7 +31,10 @@
#include "radeon_reg.h"
#include "radeon.h"
#include "radeon_drm.h"
-#include "radeon_share.h"
+#include "r100_track.h"
+#include "r300d.h"
+
+#include "r300_reg_safe.h"
/* r300,r350,rv350,rv370,rv380 depends on : */
void r100_hdp_reset(struct radeon_device *rdev);
@@ -39,7 +42,6 @@ int r100_cp_reset(struct radeon_device *rdev);
int r100_rb2d_reset(struct radeon_device *rdev);
int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
int r100_pci_gart_enable(struct radeon_device *rdev);
-void r100_pci_gart_disable(struct radeon_device *rdev);
void r100_mc_setup(struct radeon_device *rdev);
void r100_mc_disable_clients(struct radeon_device *rdev);
int r100_gui_wait_for_idle(struct radeon_device *rdev);
@@ -47,14 +49,10 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p,
struct radeon_cs_packet *pkt,
unsigned idx);
int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
-int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
- struct radeon_cs_reloc **cs_reloc);
int r100_cs_parse_packet0(struct radeon_cs_parser *p,
struct radeon_cs_packet *pkt,
const unsigned *auth, unsigned n,
radeon_packet0_check_t check);
-void r100_cs_dump_packet(struct radeon_cs_parser *p,
- struct radeon_cs_packet *pkt);
int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
struct radeon_cs_packet *pkt,
struct radeon_object *robj);
@@ -87,26 +85,57 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
mb();
}
-int rv370_pcie_gart_enable(struct radeon_device *rdev)
+int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
+{
+ void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+
+ if (i < 0 || i > rdev->gart.num_gpu_pages) {
+ return -EINVAL;
+ }
+ addr = (lower_32_bits(addr) >> 8) |
+ ((upper_32_bits(addr) & 0xff) << 24) |
+ 0xc;
+ /* on x86 we want this to be CPU endian, on powerpc
+ * on powerpc without HW swappers, it'll get swapped on way
+ * into VRAM - so no need for cpu_to_le32 on VRAM tables */
+ writel(addr, ((void __iomem *)ptr) + (i * 4));
+ return 0;
+}
+
+int rv370_pcie_gart_init(struct radeon_device *rdev)
{
- uint32_t table_addr;
- uint32_t tmp;
int r;
+ if (rdev->gart.table.vram.robj) {
+ WARN(1, "RV370 PCIE GART already initialized.\n");
+ return 0;
+ }
/* Initialize common gart structure */
r = radeon_gart_init(rdev);
- if (r) {
+ if (r)
return r;
- }
r = rv370_debugfs_pcie_gart_info_init(rdev);
- if (r) {
+ if (r)
DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
- }
rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
- r = radeon_gart_table_vram_alloc(rdev);
- if (r) {
- return r;
+ rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
+ rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
+ return radeon_gart_table_vram_alloc(rdev);
+}
+
+int rv370_pcie_gart_enable(struct radeon_device *rdev)
+{
+ uint32_t table_addr;
+ uint32_t tmp;
+ int r;
+
+ if (rdev->gart.table.vram.robj == NULL) {
+ dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
+ return -EINVAL;
}
+ r = radeon_gart_table_vram_pin(rdev);
+ if (r)
+ return r;
/* discard memory request outside of configured range */
tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
@@ -128,7 +157,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
rv370_pcie_gart_tlb_flush(rdev);
DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
- rdev->mc.gtt_size >> 20, table_addr);
+ (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
rdev->gart.ready = true;
return 0;
}
@@ -146,45 +175,13 @@ void rv370_pcie_gart_disable(struct radeon_device *rdev)
}
}
-int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
+void rv370_pcie_gart_fini(struct radeon_device *rdev)
{
- void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
-
- if (i < 0 || i > rdev->gart.num_gpu_pages) {
- return -EINVAL;
- }
- addr = (lower_32_bits(addr) >> 8) |
- ((upper_32_bits(addr) & 0xff) << 24) |
- 0xc;
- /* on x86 we want this to be CPU endian, on powerpc
- * on powerpc without HW swappers, it'll get swapped on way
- * into VRAM - so no need for cpu_to_le32 on VRAM tables */
- writel(addr, ((void __iomem *)ptr) + (i * 4));
- return 0;
-}
-
-int r300_gart_enable(struct radeon_device *rdev)
-{
-#if __OS_HAS_AGP
- if (rdev->flags & RADEON_IS_AGP) {
- if (rdev->family > CHIP_RV350) {
- rv370_pcie_gart_disable(rdev);
- } else {
- r100_pci_gart_disable(rdev);
- }
- return 0;
- }
-#endif
- if (rdev->flags & RADEON_IS_PCIE) {
- rdev->asic->gart_disable = &rv370_pcie_gart_disable;
- rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
- rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
- return rv370_pcie_gart_enable(rdev);
- }
- return r100_pci_gart_enable(rdev);
+ rv370_pcie_gart_disable(rdev);
+ radeon_gart_table_vram_free(rdev);
+ radeon_gart_fini(rdev);
}
-
/*
* MC
*/
@@ -232,14 +229,6 @@ int r300_mc_init(struct radeon_device *rdev)
void r300_mc_fini(struct radeon_device *rdev)
{
- if (rdev->flags & RADEON_IS_PCIE) {
- rv370_pcie_gart_disable(rdev);
- radeon_gart_table_vram_free(rdev);
- } else {
- r100_pci_gart_disable(rdev);
- radeon_gart_table_ram_free(rdev);
- }
- radeon_gart_fini(rdev);
}
@@ -704,307 +693,13 @@ int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
/*
* CS functions
*/
-struct r300_cs_track_cb {
- struct radeon_object *robj;
- unsigned pitch;
- unsigned cpp;
- unsigned offset;
-};
-
-struct r300_cs_track_array {
- struct radeon_object *robj;
- unsigned esize;
-};
-
-struct r300_cs_track_texture {
- struct radeon_object *robj;
- unsigned pitch;
- unsigned width;
- unsigned height;
- unsigned num_levels;
- unsigned cpp;
- unsigned tex_coord_type;
- unsigned txdepth;
- unsigned width_11;
- unsigned height_11;
- bool use_pitch;
- bool enabled;
- bool roundup_w;
- bool roundup_h;
-};
-
-struct r300_cs_track {
- unsigned num_cb;
- unsigned maxy;
- unsigned vtx_size;
- unsigned vap_vf_cntl;
- unsigned immd_dwords;
- unsigned num_arrays;
- unsigned max_indx;
- struct r300_cs_track_array arrays[11];
- struct r300_cs_track_cb cb[4];
- struct r300_cs_track_cb zb;
- struct r300_cs_track_texture textures[16];
- bool z_enabled;
-};
-
-static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t)
-{
- DRM_ERROR("pitch %d\n", t->pitch);
- DRM_ERROR("width %d\n", t->width);
- DRM_ERROR("height %d\n", t->height);
- DRM_ERROR("num levels %d\n", t->num_levels);
- DRM_ERROR("depth %d\n", t->txdepth);
- DRM_ERROR("bpp %d\n", t->cpp);
- DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
- DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
- DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
-}
-
-static inline int r300_cs_track_texture_check(struct radeon_device *rdev,
- struct r300_cs_track *track)
-{
- struct radeon_object *robj;
- unsigned long size;
- unsigned u, i, w, h;
-
- for (u = 0; u < 16; u++) {
- if (!track->textures[u].enabled)
- continue;
- robj = track->textures[u].robj;
- if (robj == NULL) {
- DRM_ERROR("No texture bound to unit %u\n", u);
- return -EINVAL;
- }
- size = 0;
- for (i = 0; i <= track->textures[u].num_levels; i++) {
- if (track->textures[u].use_pitch) {
- w = track->textures[u].pitch / (1 << i);
- } else {
- w = track->textures[u].width / (1 << i);
- if (rdev->family >= CHIP_RV515)
- w |= track->textures[u].width_11;
- if (track->textures[u].roundup_w)
- w = roundup_pow_of_two(w);
- }
- h = track->textures[u].height / (1 << i);
- if (rdev->family >= CHIP_RV515)
- h |= track->textures[u].height_11;
- if (track->textures[u].roundup_h)
- h = roundup_pow_of_two(h);
- size += w * h;
- }
- size *= track->textures[u].cpp;
- switch (track->textures[u].tex_coord_type) {
- case 0:
- break;
- case 1:
- size *= (1 << track->textures[u].txdepth);
- break;
- case 2:
- size *= 6;
- break;
- default:
- DRM_ERROR("Invalid texture coordinate type %u for unit "
- "%u\n", track->textures[u].tex_coord_type, u);
- return -EINVAL;
- }
- if (size > radeon_object_size(robj)) {
- DRM_ERROR("Texture of unit %u needs %lu bytes but is "
- "%lu\n", u, size, radeon_object_size(robj));
- r300_cs_track_texture_print(&track->textures[u]);
- return -EINVAL;
- }
- }
- return 0;
-}
-
-int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track)
-{
- unsigned i;
- unsigned long size;
- unsigned prim_walk;
- unsigned nverts;
-
- for (i = 0; i < track->num_cb; i++) {
- if (track->cb[i].robj == NULL) {
- DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
- return -EINVAL;
- }
- size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
- size += track->cb[i].offset;
- if (size > radeon_object_size(track->cb[i].robj)) {
- DRM_ERROR("[drm] Buffer too small for color buffer %d "
- "(need %lu have %lu) !\n", i, size,
- radeon_object_size(track->cb[i].robj));
- DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
- i, track->cb[i].pitch, track->cb[i].cpp,
- track->cb[i].offset, track->maxy);
- return -EINVAL;
- }
- }
- if (track->z_enabled) {
- if (track->zb.robj == NULL) {
- DRM_ERROR("[drm] No buffer for z buffer !\n");
- return -EINVAL;
- }
- size = track->zb.pitch * track->zb.cpp * track->maxy;
- size += track->zb.offset;
- if (size > radeon_object_size(track->zb.robj)) {
- DRM_ERROR("[drm] Buffer too small for z buffer "
- "(need %lu have %lu) !\n", size,
- radeon_object_size(track->zb.robj));
- return -EINVAL;
- }
- }
- prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
- nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
- switch (prim_walk) {
- case 1:
- for (i = 0; i < track->num_arrays; i++) {
- size = track->arrays[i].esize * track->max_indx * 4;
- if (track->arrays[i].robj == NULL) {
- DRM_ERROR("(PW %u) Vertex array %u no buffer "
- "bound\n", prim_walk, i);
- return -EINVAL;
- }
- if (size > radeon_object_size(track->arrays[i].robj)) {
- DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
- "have %lu dwords\n", prim_walk, i,
- size >> 2,
- radeon_object_size(track->arrays[i].robj) >> 2);
- DRM_ERROR("Max indices %u\n", track->max_indx);
- return -EINVAL;
- }
- }
- break;
- case 2:
- for (i = 0; i < track->num_arrays; i++) {
- size = track->arrays[i].esize * (nverts - 1) * 4;
- if (track->arrays[i].robj == NULL) {
- DRM_ERROR("(PW %u) Vertex array %u no buffer "
- "bound\n", prim_walk, i);
- return -EINVAL;
- }
- if (size > radeon_object_size(track->arrays[i].robj)) {
- DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
- "have %lu dwords\n", prim_walk, i, size >> 2,
- radeon_object_size(track->arrays[i].robj) >> 2);
- return -EINVAL;
- }
- }
- break;
- case 3:
- size = track->vtx_size * nverts;
- if (size != track->immd_dwords) {
- DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
- track->immd_dwords, size);
- DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
- nverts, track->vtx_size);
- return -EINVAL;
- }
- break;
- default:
- DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
- prim_walk);
- return -EINVAL;
- }
- return r300_cs_track_texture_check(rdev, track);
-}
-
-static inline void r300_cs_track_clear(struct r300_cs_track *track)
-{
- unsigned i;
-
- track->num_cb = 4;
- track->maxy = 4096;
- for (i = 0; i < track->num_cb; i++) {
- track->cb[i].robj = NULL;
- track->cb[i].pitch = 8192;
- track->cb[i].cpp = 16;
- track->cb[i].offset = 0;
- }
- track->z_enabled = true;
- track->zb.robj = NULL;
- track->zb.pitch = 8192;
- track->zb.cpp = 4;
- track->zb.offset = 0;
- track->vtx_size = 0x7F;
- track->immd_dwords = 0xFFFFFFFFUL;
- track->num_arrays = 11;
- track->max_indx = 0x00FFFFFFUL;
- for (i = 0; i < track->num_arrays; i++) {
- track->arrays[i].robj = NULL;
- track->arrays[i].esize = 0x7F;
- }
- for (i = 0; i < 16; i++) {
- track->textures[i].pitch = 16536;
- track->textures[i].width = 16536;
- track->textures[i].height = 16536;
- track->textures[i].width_11 = 1 << 11;
- track->textures[i].height_11 = 1 << 11;
- track->textures[i].num_levels = 12;
- track->textures[i].txdepth = 16;
- track->textures[i].cpp = 64;
- track->textures[i].tex_coord_type = 1;
- track->textures[i].robj = NULL;
- /* CS IB emission code makes sure texture unit are disabled */
- track->textures[i].enabled = false;
- track->textures[i].roundup_w = true;
- track->textures[i].roundup_h = true;
- }
-}
-
-static const unsigned r300_reg_safe_bm[159] = {
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
- 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
- 0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF,
- 0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF,
- 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
- 0x00000000, 0x0000C100, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x0003FC01, 0xFFFFFCF8, 0xFF800B19,
-};
-
static int r300_packet0_check(struct radeon_cs_parser *p,
struct radeon_cs_packet *pkt,
unsigned idx, unsigned reg)
{
struct radeon_cs_chunk *ib_chunk;
struct radeon_cs_reloc *reloc;
- struct r300_cs_track *track;
+ struct r100_cs_track *track;
volatile uint32_t *ib;
uint32_t tmp, tile_flags = 0;
unsigned i;
@@ -1012,7 +707,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
ib = p->ib->ptr;
ib_chunk = &p->chunks[p->chunk_ib_idx];
- track = (struct r300_cs_track*)p->track;
+ track = (struct r100_cs_track *)p->track;
switch(reg) {
case AVIVO_D1MODE_VLINE_START_END:
case RADEON_CRTC_GUI_TRIG_VLINE:
@@ -1026,28 +721,9 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
break;
case RADEON_DST_PITCH_OFFSET:
case RADEON_SRC_PITCH_OFFSET:
- r = r100_cs_packet_next_reloc(p, &reloc);
- if (r) {
- DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
- idx, reg);
- r100_cs_dump_packet(p, pkt);
+ r = r100_reloc_pitch_offset(p, pkt, idx, reg);
+ if (r)
return r;
- }
- tmp = ib_chunk->kdata[idx] & 0x003fffff;
- tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
-
- if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
- tile_flags |= RADEON_DST_TILE_MACRO;
- if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
- if (reg == RADEON_SRC_PITCH_OFFSET) {
- DRM_ERROR("Cannot src blit from microtiled surface\n");
- r100_cs_dump_packet(p, pkt);
- return -EINVAL;
- }
- tile_flags |= RADEON_DST_TILE_MICRO;
- }
- tmp |= tile_flags;
- ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
break;
case R300_RB3D_COLOROFFSET0:
case R300_RB3D_COLOROFFSET1:
@@ -1256,42 +932,41 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
tmp = (ib_chunk->kdata[idx] >> 25) & 0x3;
track->textures[i].tex_coord_type = tmp;
switch ((ib_chunk->kdata[idx] & 0x1F)) {
- case 0:
- case 2:
- case 5:
- case 18:
- case 20:
- case 21:
+ case R300_TX_FORMAT_X8:
+ case R300_TX_FORMAT_Y4X4:
+ case R300_TX_FORMAT_Z3Y3X2:
track->textures[i].cpp = 1;
break;
- case 1:
- case 3:
- case 6:
- case 7:
- case 10:
- case 11:
- case 19:
- case 22:
- case 24:
+ case R300_TX_FORMAT_X16:
+ case R300_TX_FORMAT_Y8X8:
+ case R300_TX_FORMAT_Z5Y6X5:
+ case R300_TX_FORMAT_Z6Y5X5:
+ case R300_TX_FORMAT_W4Z4Y4X4:
+ case R300_TX_FORMAT_W1Z5Y5X5:
+ case R300_TX_FORMAT_DXT1:
+ case R300_TX_FORMAT_D3DMFT_CxV8U8:
+ case R300_TX_FORMAT_B8G8_B8G8:
+ case R300_TX_FORMAT_G8R8_G8B8:
track->textures[i].cpp = 2;
break;
- case 4:
- case 8:
- case 9:
- case 12:
- case 13:
- case 23:
- case 25:
- case 27:
- case 30:
+ case R300_TX_FORMAT_Y16X16:
+ case R300_TX_FORMAT_Z11Y11X10:
+ case R300_TX_FORMAT_Z10Y11X11:
+ case R300_TX_FORMAT_W8Z8Y8X8:
+ case R300_TX_FORMAT_W2Z10Y10X10:
+ case 0x17:
+ case R300_TX_FORMAT_FL_I32:
+ case 0x1e:
+ case R300_TX_FORMAT_DXT3:
+ case R300_TX_FORMAT_DXT5:
track->textures[i].cpp = 4;
break;
- case 14:
- case 26:
- case 28:
+ case R300_TX_FORMAT_W16Z16Y16X16:
+ case R300_TX_FORMAT_FL_R16G16B16A16:
+ case R300_TX_FORMAT_FL_I32A32:
track->textures[i].cpp = 8;
break;
- case 29:
+ case R300_TX_FORMAT_FL_R32G32B32A32:
track->textures[i].cpp = 16;
break;
default:
@@ -1319,11 +994,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
case 0x443C:
/* TX_FILTER0_[0-15] */
i = (reg - 0x4400) >> 2;
- tmp = ib_chunk->kdata[idx] & 0x7;;
+ tmp = ib_chunk->kdata[idx] & 0x7;
if (tmp == 2 || tmp == 4 || tmp == 6) {
track->textures[i].roundup_w = false;
}
- tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;;
+ tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;
if (tmp == 2 || tmp == 4 || tmp == 6) {
track->textures[i].roundup_h = false;
}
@@ -1411,8 +1086,9 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
struct radeon_cs_packet *pkt)
{
struct radeon_cs_chunk *ib_chunk;
+
struct radeon_cs_reloc *reloc;
- struct r300_cs_track *track;
+ struct r100_cs_track *track;
volatile uint32_t *ib;
unsigned idx;
unsigned i, c;
@@ -1421,7 +1097,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
ib = p->ib->ptr;
ib_chunk = &p->chunks[p->chunk_ib_idx];
idx = pkt->idx + 1;
- track = (struct r300_cs_track*)p->track;
+ track = (struct r100_cs_track *)p->track;
switch(pkt->opcode) {
case PACKET3_3D_LOAD_VBPNTR:
c = ib_chunk->kdata[idx++] & 0x1F;
@@ -1488,7 +1164,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
}
track->vap_vf_cntl = ib_chunk->kdata[idx+1];
track->immd_dwords = pkt->count - 1;
- r = r300_cs_track_check(p->rdev, track);
+ r = r100_cs_track_check(p->rdev, track);
if (r) {
return r;
}
@@ -1503,35 +1179,35 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
}
track->vap_vf_cntl = ib_chunk->kdata[idx];
track->immd_dwords = pkt->count;
- r = r300_cs_track_check(p->rdev, track);
+ r = r100_cs_track_check(p->rdev, track);
if (r) {
return r;
}
break;
case PACKET3_3D_DRAW_VBUF:
track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
- r = r300_cs_track_check(p->rdev, track);
+ r = r100_cs_track_check(p->rdev, track);
if (r) {
return r;
}
break;
case PACKET3_3D_DRAW_VBUF_2:
track->vap_vf_cntl = ib_chunk->kdata[idx];
- r = r300_cs_track_check(p->rdev, track);
+ r = r100_cs_track_check(p->rdev, track);
if (r) {
return r;
}
break;
case PACKET3_3D_DRAW_INDX:
track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
- r = r300_cs_track_check(p->rdev, track);
+ r = r100_cs_track_check(p->rdev, track);
if (r) {
return r;
}
break;
case PACKET3_3D_DRAW_INDX_2:
track->vap_vf_cntl = ib_chunk->kdata[idx];
- r = r300_cs_track_check(p->rdev, track);
+ r = r100_cs_track_check(p->rdev, track);
if (r) {
return r;
}
@@ -1548,11 +1224,12 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
int r300_cs_parse(struct radeon_cs_parser *p)
{
struct radeon_cs_packet pkt;
- struct r300_cs_track track;
+ struct r100_cs_track *track;
int r;
- r300_cs_track_clear(&track);
- p->track = &track;
+ track = kzalloc(sizeof(*track), GFP_KERNEL);
+ r100_cs_track_clear(p->rdev, track);
+ p->track = track;
do {
r = r100_cs_packet_parse(p, &pkt, p->idx);
if (r) {
@@ -1582,9 +1259,48 @@ int r300_cs_parse(struct radeon_cs_parser *p)
return 0;
}
-int r300_init(struct radeon_device *rdev)
+void r300_set_reg_safe(struct radeon_device *rdev)
{
rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
+}
+
+int r300_init(struct radeon_device *rdev)
+{
+ r300_set_reg_safe(rdev);
return 0;
}
+
+void r300_mc_program(struct radeon_device *rdev)
+{
+ struct r100_mc_save save;
+ int r;
+
+ r = r100_debugfs_mc_info_init(rdev);
+ if (r) {
+ dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
+ }
+
+ /* Stops all mc clients */
+ r100_mc_stop(rdev, &save);
+ if (rdev->flags & RADEON_IS_AGP) {
+ WREG32(R_00014C_MC_AGP_LOCATION,
+ S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
+ S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
+ WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
+ WREG32(R_00015C_AGP_BASE_2,
+ upper_32_bits(rdev->mc.agp_base) & 0xff);
+ } else {
+ WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
+ WREG32(R_000170_AGP_BASE, 0);
+ WREG32(R_00015C_AGP_BASE_2, 0);
+ }
+ /* Wait for mc idle */
+ if (r300_mc_wait_for_idle(rdev))
+ DRM_INFO("Failed to wait MC idle before programming MC.\n");
+ /* Program MC, should be a 32bits limited address space */
+ WREG32(R_000148_MC_FB_LOCATION,
+ S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
+ S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
+ r100_mc_resume(rdev, &save);
+}
diff --git a/drivers/gpu/drm/radeon/r300.h b/drivers/gpu/drm/radeon/r300.h
deleted file mode 100644
index 8486b4d..0000000
--- a/drivers/gpu/drm/radeon/r300.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- * Alex Deucher
- * Jerome Glisse
- */
-#ifndef R300_H
-#define R300_H
-
-struct r300_asic {
- const unsigned *reg_safe_bm;
- unsigned reg_safe_bm_size;
-};
-
-#endif
diff --git a/drivers/gpu/drm/radeon/r300d.h b/drivers/gpu/drm/radeon/r300d.h
new file mode 100644
index 0000000..d4fa3eb
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r300d.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ * Alex Deucher
+ * Jerome Glisse
+ */
+#ifndef __R300D_H__
+#define __R300D_H__
+
+#define CP_PACKET0 0x00000000
+#define PACKET0_BASE_INDEX_SHIFT 0
+#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
+#define PACKET0_COUNT_SHIFT 16
+#define PACKET0_COUNT_MASK (0x3fff << 16)
+#define CP_PACKET1 0x40000000
+#define CP_PACKET2 0x80000000
+#define PACKET2_PAD_SHIFT 0
+#define PACKET2_PAD_MASK (0x3fffffff << 0)
+#define CP_PACKET3 0xC0000000
+#define PACKET3_IT_OPCODE_SHIFT 8
+#define PACKET3_IT_OPCODE_MASK (0xff << 8)
+#define PACKET3_COUNT_SHIFT 16
+#define PACKET3_COUNT_MASK (0x3fff << 16)
+/* PACKET3 op code */
+#define PACKET3_NOP 0x10
+#define PACKET3_3D_DRAW_VBUF 0x28
+#define PACKET3_3D_DRAW_IMMD 0x29
+#define PACKET3_3D_DRAW_INDX 0x2A
+#define PACKET3_3D_LOAD_VBPNTR 0x2F
+#define PACKET3_INDX_BUFFER 0x33
+#define PACKET3_3D_DRAW_VBUF_2 0x34
+#define PACKET3_3D_DRAW_IMMD_2 0x35
+#define PACKET3_3D_DRAW_INDX_2 0x36
+#define PACKET3_BITBLT_MULTI 0x9B
+
+#define PACKET0(reg, n) (CP_PACKET0 | \
+ REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
+ REG_SET(PACKET0_COUNT, (n)))
+#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
+#define PACKET3(op, n) (CP_PACKET3 | \
+ REG_SET(PACKET3_IT_OPCODE, (op)) | \
+ REG_SET(PACKET3_COUNT, (n)))
+
+#define PACKET_TYPE0 0
+#define PACKET_TYPE1 1
+#define PACKET_TYPE2 2
+#define PACKET_TYPE3 3
+
+#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
+#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
+#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
+#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
+#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
+
+/* Registers */
+#define R_000148_MC_FB_LOCATION 0x000148
+#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0)
+#define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
+#define C_000148_MC_FB_START 0xFFFF0000
+#define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
+#define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
+#define C_000148_MC_FB_TOP 0x0000FFFF
+#define R_00014C_MC_AGP_LOCATION 0x00014C
+#define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0)
+#define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)
+#define C_00014C_MC_AGP_START 0xFFFF0000
+#define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)
+#define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)
+#define C_00014C_MC_AGP_TOP 0x0000FFFF
+#define R_00015C_AGP_BASE_2 0x00015C
+#define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0)
+#define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF)
+#define C_00015C_AGP_BASE_ADDR_2 0xFFFFFFF0
+#define R_000170_AGP_BASE 0x000170
+#define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_000170_AGP_BASE_ADDR 0x00000000
+
+
+#endif
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 97426a6..49a2fdc 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -29,47 +29,13 @@
#include "drmP.h"
#include "radeon_reg.h"
#include "radeon.h"
+#include "atom.h"
+#include "r420d.h"
-/* r420,r423,rv410 depends on : */
-void r100_pci_gart_disable(struct radeon_device *rdev);
-void r100_hdp_reset(struct radeon_device *rdev);
-void r100_mc_setup(struct radeon_device *rdev);
-int r100_gui_wait_for_idle(struct radeon_device *rdev);
-void r100_mc_disable_clients(struct radeon_device *rdev);
-void r300_vram_info(struct radeon_device *rdev);
-int r300_mc_wait_for_idle(struct radeon_device *rdev);
-int rv370_pcie_gart_enable(struct radeon_device *rdev);
-void rv370_pcie_gart_disable(struct radeon_device *rdev);
-
-/* This files gather functions specifics to :
- * r420,r423,rv410
- *
- * Some of these functions might be used by newer ASICs.
- */
-void r420_gpu_init(struct radeon_device *rdev);
-int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
-
-
-/*
- * MC
- */
int r420_mc_init(struct radeon_device *rdev)
{
int r;
- if (r100_debugfs_rbbm_init(rdev)) {
- DRM_ERROR("Failed to register debugfs file for RBBM !\n");
- }
- if (r420_debugfs_pipes_info_init(rdev)) {
- DRM_ERROR("Failed to register debugfs file for pipes !\n");
- }
-
- r420_gpu_init(rdev);
- r100_pci_gart_disable(rdev);
- if (rdev->flags & RADEON_IS_PCIE) {
- rv370_pcie_gart_disable(rdev);
- }
-
/* Setup GPU memory space */
rdev->mc.vram_location = 0xFFFFFFFFUL;
rdev->mc.gtt_location = 0xFFFFFFFFUL;
@@ -87,33 +53,9 @@ int r420_mc_init(struct radeon_device *rdev)
if (r) {
return r;
}
-
- /* Program GPU memory space */
- r100_mc_disable_clients(rdev);
- if (r300_mc_wait_for_idle(rdev)) {
- printk(KERN_WARNING "Failed to wait MC idle while "
- "programming pipes. Bad things might happen.\n");
- }
- r100_mc_setup(rdev);
return 0;
}
-void r420_mc_fini(struct radeon_device *rdev)
-{
- rv370_pcie_gart_disable(rdev);
- radeon_gart_table_vram_free(rdev);
- radeon_gart_fini(rdev);
-}
-
-
-/*
- * Global GPU functions
- */
-void r420_errata(struct radeon_device *rdev)
-{
- rdev->pll_errata = 0;
-}
-
void r420_pipes_init(struct radeon_device *rdev)
{
unsigned tmp;
@@ -122,6 +64,11 @@ void r420_pipes_init(struct radeon_device *rdev)
/* GA_ENHANCE workaround TCL deadlock issue */
WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
+ /* add idle wait as per freedesktop.org bug 24041 */
+ if (r100_gui_wait_for_idle(rdev)) {
+ printk(KERN_WARNING "Failed to wait GUI idle while "
+ "programming pipes. Bad things might happen.\n");
+ }
/* get max number of pipes */
gb_pipe_select = RREG32(0x402C);
num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
@@ -179,25 +126,239 @@ void r420_pipes_init(struct radeon_device *rdev)
rdev->num_gb_pipes, rdev->num_z_pipes);
}
-void r420_gpu_init(struct radeon_device *rdev)
+u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
+{
+ u32 r;
+
+ WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
+ r = RREG32(R_0001FC_MC_IND_DATA);
+ return r;
+}
+
+void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
+{
+ WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
+ S_0001F8_MC_IND_WR_EN(1));
+ WREG32(R_0001FC_MC_IND_DATA, v);
+}
+
+static void r420_debugfs(struct radeon_device *rdev)
+{
+ if (r100_debugfs_rbbm_init(rdev)) {
+ DRM_ERROR("Failed to register debugfs file for RBBM !\n");
+ }
+ if (r420_debugfs_pipes_info_init(rdev)) {
+ DRM_ERROR("Failed to register debugfs file for pipes !\n");
+ }
+}
+
+static void r420_clock_resume(struct radeon_device *rdev)
+{
+ u32 sclk_cntl;
+ sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
+ sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
+ if (rdev->family == CHIP_R420)
+ sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
+ WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
+}
+
+static int r420_startup(struct radeon_device *rdev)
{
- r100_hdp_reset(rdev);
+ int r;
+
+ r300_mc_program(rdev);
+ /* Initialize GART (initialize after TTM so we can allocate
+ * memory through TTM but finalize after TTM) */
+ if (rdev->flags & RADEON_IS_PCIE) {
+ r = rv370_pcie_gart_enable(rdev);
+ if (r)
+ return r;
+ }
+ if (rdev->flags & RADEON_IS_PCI) {
+ r = r100_pci_gart_enable(rdev);
+ if (r)
+ return r;
+ }
r420_pipes_init(rdev);
- if (r300_mc_wait_for_idle(rdev)) {
- printk(KERN_WARNING "Failed to wait MC idle while "
- "programming pipes. Bad things might happen.\n");
+ /* Enable IRQ */
+ rdev->irq.sw_int = true;
+ r100_irq_set(rdev);
+ /* 1M ring buffer */
+ r = r100_cp_init(rdev, 1024 * 1024);
+ if (r) {
+ dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
+ return r;
+ }
+ r = r100_wb_init(rdev);
+ if (r) {
+ dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
+ }
+ r = r100_ib_init(rdev);
+ if (r) {
+ dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
+ return r;
}
+ return 0;
}
+int r420_resume(struct radeon_device *rdev)
+{
+ /* Make sur GART are not working */
+ if (rdev->flags & RADEON_IS_PCIE)
+ rv370_pcie_gart_disable(rdev);
+ if (rdev->flags & RADEON_IS_PCI)
+ r100_pci_gart_disable(rdev);
+ /* Resume clock before doing reset */
+ r420_clock_resume(rdev);
+ /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+ if (radeon_gpu_reset(rdev)) {
+ dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+ RREG32(R_000E40_RBBM_STATUS),
+ RREG32(R_0007C0_CP_STAT));
+ }
+ /* check if cards are posted or not */
+ if (rdev->is_atom_bios) {
+ atom_asic_init(rdev->mode_info.atom_context);
+ } else {
+ radeon_combios_asic_init(rdev->ddev);
+ }
+ /* Resume clock after posting */
+ r420_clock_resume(rdev);
-/*
- * r420,r423,rv410 VRAM info
- */
-void r420_vram_info(struct radeon_device *rdev)
+ return r420_startup(rdev);
+}
+
+int r420_suspend(struct radeon_device *rdev)
{
- r300_vram_info(rdev);
+ r100_cp_disable(rdev);
+ r100_wb_disable(rdev);
+ r100_irq_disable(rdev);
+ if (rdev->flags & RADEON_IS_PCIE)
+ rv370_pcie_gart_disable(rdev);
+ if (rdev->flags & RADEON_IS_PCI)
+ r100_pci_gart_disable(rdev);
+ return 0;
+}
+
+void r420_fini(struct radeon_device *rdev)
+{
+ r100_cp_fini(rdev);
+ r100_wb_fini(rdev);
+ r100_ib_fini(rdev);
+ radeon_gem_fini(rdev);
+ if (rdev->flags & RADEON_IS_PCIE)
+ rv370_pcie_gart_fini(rdev);
+ if (rdev->flags & RADEON_IS_PCI)
+ r100_pci_gart_fini(rdev);
+ radeon_agp_fini(rdev);
+ radeon_irq_kms_fini(rdev);
+ radeon_fence_driver_fini(rdev);
+ radeon_object_fini(rdev);
+ if (rdev->is_atom_bios) {
+ radeon_atombios_fini(rdev);
+ } else {
+ radeon_combios_fini(rdev);
+ }
+ kfree(rdev->bios);
+ rdev->bios = NULL;
}
+int r420_init(struct radeon_device *rdev)
+{
+ int r;
+
+ rdev->new_init_path = true;
+ /* Initialize scratch registers */
+ radeon_scratch_init(rdev);
+ /* Initialize surface registers */
+ radeon_surface_init(rdev);
+ /* TODO: disable VGA need to use VGA request */
+ /* BIOS*/
+ if (!radeon_get_bios(rdev)) {
+ if (ASIC_IS_AVIVO(rdev))
+ return -EINVAL;
+ }
+ if (rdev->is_atom_bios) {
+ r = radeon_atombios_init(rdev);
+ if (r) {
+ return r;
+ }
+ } else {
+ r = radeon_combios_init(rdev);
+ if (r) {
+ return r;
+ }
+ }
+ /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+ if (radeon_gpu_reset(rdev)) {
+ dev_warn(rdev->dev,
+ "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+ RREG32(R_000E40_RBBM_STATUS),
+ RREG32(R_0007C0_CP_STAT));
+ }
+ /* check if cards are posted or not */
+ if (!radeon_card_posted(rdev) && rdev->bios) {
+ DRM_INFO("GPU not posted. posting now...\n");
+ if (rdev->is_atom_bios) {
+ atom_asic_init(rdev->mode_info.atom_context);
+ } else {
+ radeon_combios_asic_init(rdev->ddev);
+ }
+ }
+ /* Initialize clocks */
+ radeon_get_clock_info(rdev->ddev);
+ /* Get vram informations */
+ r300_vram_info(rdev);
+ /* Initialize memory controller (also test AGP) */
+ r = r420_mc_init(rdev);
+ if (r) {
+ return r;
+ }
+ r420_debugfs(rdev);
+ /* Fence driver */
+ r = radeon_fence_driver_init(rdev);
+ if (r) {
+ return r;
+ }
+ r = radeon_irq_kms_init(rdev);
+ if (r) {
+ return r;
+ }
+ /* Memory manager */
+ r = radeon_object_init(rdev);
+ if (r) {
+ return r;
+ }
+ if (rdev->flags & RADEON_IS_PCIE) {
+ r = rv370_pcie_gart_init(rdev);
+ if (r)
+ return r;
+ }
+ if (rdev->flags & RADEON_IS_PCI) {
+ r = r100_pci_gart_init(rdev);
+ if (r)
+ return r;
+ }
+ r300_set_reg_safe(rdev);
+ rdev->accel_working = true;
+ r = r420_startup(rdev);
+ if (r) {
+ /* Somethings want wront with the accel init stop accel */
+ dev_err(rdev->dev, "Disabling GPU acceleration\n");
+ r420_suspend(rdev);
+ r100_cp_fini(rdev);
+ r100_wb_fini(rdev);
+ r100_ib_fini(rdev);
+ if (rdev->flags & RADEON_IS_PCIE)
+ rv370_pcie_gart_fini(rdev);
+ if (rdev->flags & RADEON_IS_PCI)
+ r100_pci_gart_fini(rdev);
+ radeon_agp_fini(rdev);
+ radeon_irq_kms_fini(rdev);
+ rdev->accel_working = false;
+ }
+ return 0;
+}
/*
* Debugfs info
diff --git a/drivers/gpu/drm/radeon/r420d.h b/drivers/gpu/drm/radeon/r420d.h
new file mode 100644
index 0000000..a48a7db
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r420d.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ * Alex Deucher
+ * Jerome Glisse
+ */
+#ifndef R420D_H
+#define R420D_H
+
+#define R_0001F8_MC_IND_INDEX 0x0001F8
+#define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0)
+#define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F)
+#define C_0001F8_MC_IND_ADDR 0xFFFFFF80
+#define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8)
+#define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1)
+#define C_0001F8_MC_IND_WR_EN 0xFFFFFEFF
+#define R_0001FC_MC_IND_DATA 0x0001FC
+#define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_0001FC_MC_IND_DATA 0x00000000
+#define R_0007C0_CP_STAT 0x0007C0
+#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
+#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
+#define C_0007C0_MRU_BUSY 0xFFFFFFFE
+#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
+#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
+#define C_0007C0_MWU_BUSY 0xFFFFFFFD
+#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
+#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
+#define C_0007C0_RSIU_BUSY 0xFFFFFFFB
+#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
+#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
+#define C_0007C0_RCIU_BUSY 0xFFFFFFF7
+#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
+#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
+#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
+#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
+#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
+#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
+#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
+#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
+#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
+#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
+#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
+#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
+#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
+#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
+#define C_0007C0_CSI_BUSY 0xFFFFDFFF
+#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14)
+#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1)
+#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF
+#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15)
+#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1)
+#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF
+#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
+#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
+#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
+#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
+#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
+#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
+#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
+#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
+#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
+#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
+#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
+#define C_0007C0_CP_BUSY 0x7FFFFFFF
+#define R_000E40_RBBM_STATUS 0x000E40
+#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
+#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
+#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
+#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
+#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
+#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
+#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
+#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
+#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
+#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
+#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
+#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
+#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
+#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
+#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
+#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
+#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
+#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
+#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
+#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
+#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
+#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
+#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
+#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
+#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
+#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
+#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
+#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
+#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
+#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
+#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
+#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
+#define C_000E40_E2_BUSY 0xFFFDFFFF
+#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
+#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
+#define C_000E40_RB2D_BUSY 0xFFFBFFFF
+#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
+#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
+#define C_000E40_RB3D_BUSY 0xFFF7FFFF
+#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20)
+#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1)
+#define C_000E40_VAP_BUSY 0xFFEFFFFF
+#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
+#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
+#define C_000E40_RE_BUSY 0xFFDFFFFF
+#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
+#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
+#define C_000E40_TAM_BUSY 0xFFBFFFFF
+#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
+#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
+#define C_000E40_TDM_BUSY 0xFF7FFFFF
+#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
+#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
+#define C_000E40_PB_BUSY 0xFEFFFFFF
+#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25)
+#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1)
+#define C_000E40_TIM_BUSY 0xFDFFFFFF
+#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26)
+#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1)
+#define C_000E40_GA_BUSY 0xFBFFFFFF
+#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27)
+#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1)
+#define C_000E40_CBA2D_BUSY 0xF7FFFFFF
+#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
+#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
+#define C_000E40_GUI_ACTIVE 0x7FFFFFFF
+
+/* CLK registers */
+#define R_00000D_SCLK_CNTL 0x00000D
+#define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0)
+#define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7)
+#define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8
+#define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3)
+#define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1)
+#define C_00000D_CP_MAX_DYN_STOP_LAT 0xFFFFFFF7
+#define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4)
+#define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1)
+#define C_00000D_HDP_MAX_DYN_STOP_LAT 0xFFFFFFEF
+#define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5)
+#define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1)
+#define C_00000D_TV_MAX_DYN_STOP_LAT 0xFFFFFFDF
+#define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6)
+#define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1)
+#define C_00000D_E2_MAX_DYN_STOP_LAT 0xFFFFFFBF
+#define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7)
+#define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1)
+#define C_00000D_SE_MAX_DYN_STOP_LAT 0xFFFFFF7F
+#define S_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 8)
+#define G_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 8) & 0x1)
+#define C_00000D_IDCT_MAX_DYN_STOP_LAT 0xFFFFFEFF
+#define S_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 9)
+#define G_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) >> 9) & 0x1)
+#define C_00000D_VIP_MAX_DYN_STOP_LAT 0xFFFFFDFF
+#define S_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 10)
+#define G_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) >> 10) & 0x1)
+#define C_00000D_RE_MAX_DYN_STOP_LAT 0xFFFFFBFF
+#define S_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 11)
+#define G_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) >> 11) & 0x1)
+#define C_00000D_PB_MAX_DYN_STOP_LAT 0xFFFFF7FF
+#define S_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 12)
+#define G_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) >> 12) & 0x1)
+#define C_00000D_TAM_MAX_DYN_STOP_LAT 0xFFFFEFFF
+#define S_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 13)
+#define G_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) >> 13) & 0x1)
+#define C_00000D_TDM_MAX_DYN_STOP_LAT 0xFFFFDFFF
+#define S_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 14)
+#define G_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) >> 14) & 0x1)
+#define C_00000D_RB_MAX_DYN_STOP_LAT 0xFFFFBFFF
+#define S_00000D_FORCE_DISP2(x) (((x) & 0x1) << 15)
+#define G_00000D_FORCE_DISP2(x) (((x) >> 15) & 0x1)
+#define C_00000D_FORCE_DISP2 0xFFFF7FFF
+#define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16)
+#define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1)
+#define C_00000D_FORCE_CP 0xFFFEFFFF
+#define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17)
+#define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1)
+#define C_00000D_FORCE_HDP 0xFFFDFFFF
+#define S_00000D_FORCE_DISP1(x) (((x) & 0x1) << 18)
+#define G_00000D_FORCE_DISP1(x) (((x) >> 18) & 0x1)
+#define C_00000D_FORCE_DISP1 0xFFFBFFFF
+#define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19)
+#define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1)
+#define C_00000D_FORCE_TOP 0xFFF7FFFF
+#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20)
+#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1)
+#define C_00000D_FORCE_E2 0xFFEFFFFF
+#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21)
+#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1)
+#define C_00000D_FORCE_SE 0xFFDFFFFF
+#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22)
+#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1)
+#define C_00000D_FORCE_IDCT 0xFFBFFFFF
+#define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23)
+#define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1)
+#define C_00000D_FORCE_VIP 0xFF7FFFFF
+#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24)
+#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1)
+#define C_00000D_FORCE_RE 0xFEFFFFFF
+#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25)
+#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1)
+#define C_00000D_FORCE_PB 0xFDFFFFFF
+#define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26)
+#define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1)
+#define C_00000D_FORCE_PX 0xFBFFFFFF
+#define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27)
+#define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1)
+#define C_00000D_FORCE_TX 0xF7FFFFFF
+#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28)
+#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1)
+#define C_00000D_FORCE_RB 0xEFFFFFFF
+#define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29)
+#define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1)
+#define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF
+#define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30)
+#define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1)
+#define C_00000D_FORCE_SUBPIC 0xBFFFFFFF
+#define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31)
+#define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1)
+#define C_00000D_FORCE_OV0 0x7FFFFFFF
+
+#endif
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index ebd6b0f..d4b0b9d 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -28,12 +28,9 @@
#include "drmP.h"
#include "radeon_reg.h"
#include "radeon.h"
-#include "radeon_share.h"
/* r520,rv530,rv560,rv570,r580 depends on : */
void r100_hdp_reset(struct radeon_device *rdev);
-int rv370_pcie_gart_enable(struct radeon_device *rdev);
-void rv370_pcie_gart_disable(struct radeon_device *rdev);
void r420_pipes_init(struct radeon_device *rdev);
void rs600_mc_disable_clients(struct radeon_device *rdev);
void rs600_disable_vga(struct radeon_device *rdev);
@@ -119,9 +116,6 @@ int r520_mc_init(struct radeon_device *rdev)
void r520_mc_fini(struct radeon_device *rdev)
{
- rv370_pcie_gart_disable(rdev);
- radeon_gart_table_vram_free(rdev);
- radeon_gart_fini(rdev);
}
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 538cd90..eab31c1 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -25,12 +25,45 @@
* Alex Deucher
* Jerome Glisse
*/
+#include <linux/seq_file.h>
+#include <linux/firmware.h>
+#include <linux/platform_device.h>
#include "drmP.h"
-#include "radeon_reg.h"
+#include "radeon_drm.h"
#include "radeon.h"
+#include "radeon_mode.h"
+#include "r600d.h"
+#include "avivod.h"
+#include "atom.h"
-/* r600,rv610,rv630,rv620,rv635,rv670 depends on : */
-void rs600_mc_disable_clients(struct radeon_device *rdev);
+#define PFP_UCODE_SIZE 576
+#define PM4_UCODE_SIZE 1792
+#define R700_PFP_UCODE_SIZE 848
+#define R700_PM4_UCODE_SIZE 1360
+
+/* Firmware Names */
+MODULE_FIRMWARE("radeon/R600_pfp.bin");
+MODULE_FIRMWARE("radeon/R600_me.bin");
+MODULE_FIRMWARE("radeon/RV610_pfp.bin");
+MODULE_FIRMWARE("radeon/RV610_me.bin");
+MODULE_FIRMWARE("radeon/RV630_pfp.bin");
+MODULE_FIRMWARE("radeon/RV630_me.bin");
+MODULE_FIRMWARE("radeon/RV620_pfp.bin");
+MODULE_FIRMWARE("radeon/RV620_me.bin");
+MODULE_FIRMWARE("radeon/RV635_pfp.bin");
+MODULE_FIRMWARE("radeon/RV635_me.bin");
+MODULE_FIRMWARE("radeon/RV670_pfp.bin");
+MODULE_FIRMWARE("radeon/RV670_me.bin");
+MODULE_FIRMWARE("radeon/RS780_pfp.bin");
+MODULE_FIRMWARE("radeon/RS780_me.bin");
+MODULE_FIRMWARE("radeon/RV770_pfp.bin");
+MODULE_FIRMWARE("radeon/RV770_me.bin");
+MODULE_FIRMWARE("radeon/RV730_pfp.bin");
+MODULE_FIRMWARE("radeon/RV730_me.bin");
+MODULE_FIRMWARE("radeon/RV710_pfp.bin");
+MODULE_FIRMWARE("radeon/RV710_me.bin");
+
+int r600_debugfs_mc_info_init(struct radeon_device *rdev);
/* This files gather functions specifics to:
* r600,rv610,rv630,rv620,rv635,rv670
@@ -39,87 +72,293 @@ void rs600_mc_disable_clients(struct radeon_device *rdev);
*/
int r600_mc_wait_for_idle(struct radeon_device *rdev);
void r600_gpu_init(struct radeon_device *rdev);
+void r600_fini(struct radeon_device *rdev);
/*
- * MC
+ * R600 PCIE GART
*/
-int r600_mc_init(struct radeon_device *rdev)
+int r600_gart_clear_page(struct radeon_device *rdev, int i)
{
- uint32_t tmp;
+ void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+ u64 pte;
- r600_gpu_init(rdev);
+ if (i < 0 || i > rdev->gart.num_gpu_pages)
+ return -EINVAL;
+ pte = 0;
+ writeq(pte, ((void __iomem *)ptr) + (i * 8));
+ return 0;
+}
- /* setup the gart before changing location so we can ask to
- * discard unmapped mc request
- */
- /* FIXME: disable out of gart access */
- tmp = rdev->mc.gtt_location / 4096;
- tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp);
- WREG32(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp);
- tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096;
- tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp);
- WREG32(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp);
-
- rs600_mc_disable_clients(rdev);
- if (r600_mc_wait_for_idle(rdev)) {
- printk(KERN_WARNING "Failed to wait MC idle while "
- "programming pipes. Bad things might happen.\n");
+void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
+{
+ unsigned i;
+ u32 tmp;
+
+ WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
+ WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
+ WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
+ for (i = 0; i < rdev->usec_timeout; i++) {
+ /* read MC_STATUS */
+ tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
+ tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
+ if (tmp == 2) {
+ printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
+ return;
+ }
+ if (tmp) {
+ return;
+ }
+ udelay(1);
}
+}
- tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
- tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24);
- tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24);
- WREG32(R600_MC_VM_FB_LOCATION, tmp);
- tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
- tmp = REG_SET(R600_MC_AGP_TOP, tmp >> 22);
- WREG32(R600_MC_VM_AGP_TOP, tmp);
- tmp = REG_SET(R600_MC_AGP_BOT, rdev->mc.gtt_location >> 22);
- WREG32(R600_MC_VM_AGP_BOT, tmp);
- return 0;
+int r600_pcie_gart_init(struct radeon_device *rdev)
+{
+ int r;
+
+ if (rdev->gart.table.vram.robj) {
+ WARN(1, "R600 PCIE GART already initialized.\n");
+ return 0;
+ }
+ /* Initialize common gart structure */
+ r = radeon_gart_init(rdev);
+ if (r)
+ return r;
+ rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
+ return radeon_gart_table_vram_alloc(rdev);
}
-void r600_mc_fini(struct radeon_device *rdev)
+int r600_pcie_gart_enable(struct radeon_device *rdev)
{
- /* FIXME: implement */
+ u32 tmp;
+ int r, i;
+
+ if (rdev->gart.table.vram.robj == NULL) {
+ dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
+ return -EINVAL;
+ }
+ r = radeon_gart_table_vram_pin(rdev);
+ if (r)
+ return r;
+
+ /* Setup L2 cache */
+ WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
+ ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
+ EFFECTIVE_L2_QUEUE_SIZE(7));
+ WREG32(VM_L2_CNTL2, 0);
+ WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
+ /* Setup TLB control */
+ tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
+ SYSTEM_ACCESS_MODE_NOT_IN_SYS |
+ EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
+ ENABLE_WAIT_L2_QUERY;
+ WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
+ WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
+ WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
+ WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
+ WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+ (u32)(rdev->dummy_page.addr >> 12));
+ for (i = 1; i < 7; i++)
+ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
+
+ r600_pcie_gart_tlb_flush(rdev);
+ rdev->gart.ready = true;
+ return 0;
}
+void r600_pcie_gart_disable(struct radeon_device *rdev)
+{
+ u32 tmp;
+ int i;
-/*
- * Global GPU functions
- */
-void r600_errata(struct radeon_device *rdev)
+ /* Disable all tables */
+ for (i = 0; i < 7; i++)
+ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
+
+ /* Disable L2 cache */
+ WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
+ EFFECTIVE_L2_QUEUE_SIZE(7));
+ WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
+ /* Setup L1 TLB control */
+ tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
+ ENABLE_WAIT_L2_QUERY;
+ WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
+ if (rdev->gart.table.vram.robj) {
+ radeon_object_kunmap(rdev->gart.table.vram.robj);
+ radeon_object_unpin(rdev->gart.table.vram.robj);
+ }
+}
+
+void r600_pcie_gart_fini(struct radeon_device *rdev)
{
- rdev->pll_errata = 0;
+ r600_pcie_gart_disable(rdev);
+ radeon_gart_table_vram_free(rdev);
+ radeon_gart_fini(rdev);
}
int r600_mc_wait_for_idle(struct radeon_device *rdev)
{
- /* FIXME: implement */
- return 0;
+ unsigned i;
+ u32 tmp;
+
+ for (i = 0; i < rdev->usec_timeout; i++) {
+ /* read MC_STATUS */
+ tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
+ if (!tmp)
+ return 0;
+ udelay(1);
+ }
+ return -1;
}
-void r600_gpu_init(struct radeon_device *rdev)
+static void r600_mc_resume(struct radeon_device *rdev)
{
- /* FIXME: implement */
-}
+ u32 d1vga_control, d2vga_control;
+ u32 vga_render_control, vga_hdp_control;
+ u32 d1crtc_control, d2crtc_control;
+ u32 new_d1grph_primary, new_d1grph_secondary;
+ u32 new_d2grph_primary, new_d2grph_secondary;
+ u64 old_vram_start;
+ u32 tmp;
+ int i, j;
+ /* Initialize HDP */
+ for (i = 0, j = 0; i < 32; i++, j += 0x18) {
+ WREG32((0x2c14 + j), 0x00000000);
+ WREG32((0x2c18 + j), 0x00000000);
+ WREG32((0x2c1c + j), 0x00000000);
+ WREG32((0x2c20 + j), 0x00000000);
+ WREG32((0x2c24 + j), 0x00000000);
+ }
+ WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
-/*
- * VRAM info
- */
-void r600_vram_get_type(struct radeon_device *rdev)
+ d1vga_control = RREG32(D1VGA_CONTROL);
+ d2vga_control = RREG32(D2VGA_CONTROL);
+ vga_render_control = RREG32(VGA_RENDER_CONTROL);
+ vga_hdp_control = RREG32(VGA_HDP_CONTROL);
+ d1crtc_control = RREG32(D1CRTC_CONTROL);
+ d2crtc_control = RREG32(D2CRTC_CONTROL);
+ old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
+ new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
+ new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
+ new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
+ new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
+ new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
+ new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
+ new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
+ new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
+
+ /* Stop all video */
+ WREG32(D1VGA_CONTROL, 0);
+ WREG32(D2VGA_CONTROL, 0);
+ WREG32(VGA_RENDER_CONTROL, 0);
+ WREG32(D1CRTC_UPDATE_LOCK, 1);
+ WREG32(D2CRTC_UPDATE_LOCK, 1);
+ WREG32(D1CRTC_CONTROL, 0);
+ WREG32(D2CRTC_CONTROL, 0);
+ WREG32(D1CRTC_UPDATE_LOCK, 0);
+ WREG32(D2CRTC_UPDATE_LOCK, 0);
+
+ mdelay(1);
+ if (r600_mc_wait_for_idle(rdev)) {
+ printk(KERN_WARNING "[drm] MC not idle !\n");
+ }
+
+ /* Lockout access through VGA aperture*/
+ WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
+
+ /* Update configuration */
+ WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
+ WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
+ WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
+ tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
+ tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
+ WREG32(MC_VM_FB_LOCATION, tmp);
+ WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
+ WREG32(HDP_NONSURFACE_INFO, (2 << 7));
+ WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
+ if (rdev->flags & RADEON_IS_AGP) {
+ WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
+ WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
+ WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
+ } else {
+ WREG32(MC_VM_AGP_BASE, 0);
+ WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
+ WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
+ }
+ WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
+ WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
+ WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
+ WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
+ WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
+
+ /* Unlock host access */
+ WREG32(VGA_HDP_CONTROL, vga_hdp_control);
+
+ mdelay(1);
+ if (r600_mc_wait_for_idle(rdev)) {
+ printk(KERN_WARNING "[drm] MC not idle !\n");
+ }
+
+ /* Restore video state */
+ WREG32(D1CRTC_UPDATE_LOCK, 1);
+ WREG32(D2CRTC_UPDATE_LOCK, 1);
+ WREG32(D1CRTC_CONTROL, d1crtc_control);
+ WREG32(D2CRTC_CONTROL, d2crtc_control);
+ WREG32(D1CRTC_UPDATE_LOCK, 0);
+ WREG32(D2CRTC_UPDATE_LOCK, 0);
+ WREG32(D1VGA_CONTROL, d1vga_control);
+ WREG32(D2VGA_CONTROL, d2vga_control);
+ WREG32(VGA_RENDER_CONTROL, vga_render_control);
+
+ /* we need to own VRAM, so turn off the VGA renderer here
+ * to stop it overwriting our objects */
+ radeon_avivo_vga_render_disable(rdev);
+}
+
+int r600_mc_init(struct radeon_device *rdev)
{
- uint32_t tmp;
+ fixed20_12 a;
+ u32 tmp;
int chansize;
+ int r;
+ /* Get VRAM informations */
rdev->mc.vram_width = 128;
rdev->mc.vram_is_ddr = true;
-
- tmp = RREG32(R600_RAMCFG);
- if (tmp & R600_CHANSIZE_OVERRIDE) {
+ tmp = RREG32(RAMCFG);
+ if (tmp & CHANSIZE_OVERRIDE) {
chansize = 16;
- } else if (tmp & R600_CHANSIZE) {
+ } else if (tmp & CHANSIZE_MASK) {
chansize = 64;
} else {
chansize = 32;
@@ -135,36 +374,1459 @@ void r600_vram_get_type(struct radeon_device *rdev)
(rdev->family == CHIP_RV635)) {
rdev->mc.vram_width = 2 * chansize;
}
+ /* Could aper size report 0 ? */
+ rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+ rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+ /* Setup GPU memory space */
+ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
+ rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
+ if (rdev->flags & RADEON_IS_AGP) {
+ r = radeon_agp_init(rdev);
+ if (r)
+ return r;
+ /* gtt_size is setup by radeon_agp_init */
+ rdev->mc.gtt_location = rdev->mc.agp_base;
+ tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
+ /* Try to put vram before or after AGP because we
+ * we want SYSTEM_APERTURE to cover both VRAM and
+ * AGP so that GPU can catch out of VRAM/AGP access
+ */
+ if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
+ /* Enought place before */
+ rdev->mc.vram_location = rdev->mc.gtt_location -
+ rdev->mc.mc_vram_size;
+ } else if (tmp > rdev->mc.mc_vram_size) {
+ /* Enought place after */
+ rdev->mc.vram_location = rdev->mc.gtt_location +
+ rdev->mc.gtt_size;
+ } else {
+ /* Try to setup VRAM then AGP might not
+ * not work on some card
+ */
+ rdev->mc.vram_location = 0x00000000UL;
+ rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+ }
+ } else {
+ if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
+ rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
+ 0xFFFF) << 24;
+ rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+ tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
+ if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
+ /* Enough place after vram */
+ rdev->mc.gtt_location = tmp;
+ } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
+ /* Enough place before vram */
+ rdev->mc.gtt_location = 0;
+ } else {
+ /* Not enough place after or before shrink
+ * gart size
+ */
+ if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
+ rdev->mc.gtt_location = 0;
+ rdev->mc.gtt_size = rdev->mc.vram_location;
+ } else {
+ rdev->mc.gtt_location = tmp;
+ rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
+ }
+ }
+ rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+ } else {
+ rdev->mc.vram_location = 0x00000000UL;
+ rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+ rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+ }
+ }
+ rdev->mc.vram_start = rdev->mc.vram_location;
+ rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
+ rdev->mc.gtt_start = rdev->mc.gtt_location;
+ rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
+ /* FIXME: we should enforce default clock in case GPU is not in
+ * default setup
+ */
+ a.full = rfixed_const(100);
+ rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
+ rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+ return 0;
}
-void r600_vram_info(struct radeon_device *rdev)
+/* We doesn't check that the GPU really needs a reset we simply do the
+ * reset, it's up to the caller to determine if the GPU needs one. We
+ * might add an helper function to check that.
+ */
+int r600_gpu_soft_reset(struct radeon_device *rdev)
{
- r600_vram_get_type(rdev);
- rdev->mc.real_vram_size = RREG32(R600_CONFIG_MEMSIZE);
- rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
+ u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
+ S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
+ S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
+ S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
+ S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
+ S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
+ S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
+ S_008010_GUI_ACTIVE(1);
+ u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
+ S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
+ S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
+ S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
+ S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
+ S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
+ S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
+ S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
+ u32 srbm_reset = 0;
- /* Could aper size report 0 ? */
- rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
- rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+ /* Disable CP parsing/prefetching */
+ WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
+ /* Check if any of the rendering block is busy and reset it */
+ if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
+ (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
+ WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CR(1) |
+ S_008020_SOFT_RESET_DB(1) |
+ S_008020_SOFT_RESET_CB(1) |
+ S_008020_SOFT_RESET_PA(1) |
+ S_008020_SOFT_RESET_SC(1) |
+ S_008020_SOFT_RESET_SMX(1) |
+ S_008020_SOFT_RESET_SPI(1) |
+ S_008020_SOFT_RESET_SX(1) |
+ S_008020_SOFT_RESET_SH(1) |
+ S_008020_SOFT_RESET_TC(1) |
+ S_008020_SOFT_RESET_TA(1) |
+ S_008020_SOFT_RESET_VC(1) |
+ S_008020_SOFT_RESET_VGT(1));
+ (void)RREG32(R_008020_GRBM_SOFT_RESET);
+ udelay(50);
+ WREG32(R_008020_GRBM_SOFT_RESET, 0);
+ (void)RREG32(R_008020_GRBM_SOFT_RESET);
+ }
+ /* Reset CP (we always reset CP) */
+ WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CP(1));
+ (void)RREG32(R_008020_GRBM_SOFT_RESET);
+ udelay(50);
+ WREG32(R_008020_GRBM_SOFT_RESET, 0);
+ (void)RREG32(R_008020_GRBM_SOFT_RESET);
+ /* Reset others GPU block if necessary */
+ if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+ srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
+ if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
+ srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
+ if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
+ srbm_reset |= S_000E60_SOFT_RESET_IH(1);
+ if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+ srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
+ if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+ srbm_reset |= S_000E60_SOFT_RESET_MC(1);
+ if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+ srbm_reset |= S_000E60_SOFT_RESET_MC(1);
+ if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+ srbm_reset |= S_000E60_SOFT_RESET_MC(1);
+ if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+ srbm_reset |= S_000E60_SOFT_RESET_MC(1);
+ if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+ srbm_reset |= S_000E60_SOFT_RESET_MC(1);
+ if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+ srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
+ if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+ srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
+ WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
+ (void)RREG32(R_000E60_SRBM_SOFT_RESET);
+ udelay(50);
+ WREG32(R_000E60_SRBM_SOFT_RESET, 0);
+ (void)RREG32(R_000E60_SRBM_SOFT_RESET);
+ /* Wait a little for things to settle down */
+ udelay(50);
+ return 0;
}
+int r600_gpu_reset(struct radeon_device *rdev)
+{
+ return r600_gpu_soft_reset(rdev);
+}
+
+static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
+ u32 num_backends,
+ u32 backend_disable_mask)
+{
+ u32 backend_map = 0;
+ u32 enabled_backends_mask;
+ u32 enabled_backends_count;
+ u32 cur_pipe;
+ u32 swizzle_pipe[R6XX_MAX_PIPES];
+ u32 cur_backend;
+ u32 i;
+
+ if (num_tile_pipes > R6XX_MAX_PIPES)
+ num_tile_pipes = R6XX_MAX_PIPES;
+ if (num_tile_pipes < 1)
+ num_tile_pipes = 1;
+ if (num_backends > R6XX_MAX_BACKENDS)
+ num_backends = R6XX_MAX_BACKENDS;
+ if (num_backends < 1)
+ num_backends = 1;
+
+ enabled_backends_mask = 0;
+ enabled_backends_count = 0;
+ for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
+ if (((backend_disable_mask >> i) & 1) == 0) {
+ enabled_backends_mask |= (1 << i);
+ ++enabled_backends_count;
+ }
+ if (enabled_backends_count == num_backends)
+ break;
+ }
+
+ if (enabled_backends_count == 0) {
+ enabled_backends_mask = 1;
+ enabled_backends_count = 1;
+ }
+
+ if (enabled_backends_count != num_backends)
+ num_backends = enabled_backends_count;
+
+ memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
+ switch (num_tile_pipes) {
+ case 1:
+ swizzle_pipe[0] = 0;
+ break;
+ case 2:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 1;
+ break;
+ case 3:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 1;
+ swizzle_pipe[2] = 2;
+ break;
+ case 4:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 1;
+ swizzle_pipe[2] = 2;
+ swizzle_pipe[3] = 3;
+ break;
+ case 5:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 1;
+ swizzle_pipe[2] = 2;
+ swizzle_pipe[3] = 3;
+ swizzle_pipe[4] = 4;
+ break;
+ case 6:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 2;
+ swizzle_pipe[2] = 4;
+ swizzle_pipe[3] = 5;
+ swizzle_pipe[4] = 1;
+ swizzle_pipe[5] = 3;
+ break;
+ case 7:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 2;
+ swizzle_pipe[2] = 4;
+ swizzle_pipe[3] = 6;
+ swizzle_pipe[4] = 1;
+ swizzle_pipe[5] = 3;
+ swizzle_pipe[6] = 5;
+ break;
+ case 8:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 2;
+ swizzle_pipe[2] = 4;
+ swizzle_pipe[3] = 6;
+ swizzle_pipe[4] = 1;
+ swizzle_pipe[5] = 3;
+ swizzle_pipe[6] = 5;
+ swizzle_pipe[7] = 7;
+ break;
+ }
+
+ cur_backend = 0;
+ for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
+ while (((1 << cur_backend) & enabled_backends_mask) == 0)
+ cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
+
+ backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
+
+ cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
+ }
+
+ return backend_map;
+}
+
+int r600_count_pipe_bits(uint32_t val)
+{
+ int i, ret = 0;
+
+ for (i = 0; i < 32; i++) {
+ ret += val & 1;
+ val >>= 1;
+ }
+ return ret;
+}
+
+void r600_gpu_init(struct radeon_device *rdev)
+{
+ u32 tiling_config;
+ u32 ramcfg;
+ u32 tmp;
+ int i, j;
+ u32 sq_config;
+ u32 sq_gpr_resource_mgmt_1 = 0;
+ u32 sq_gpr_resource_mgmt_2 = 0;
+ u32 sq_thread_resource_mgmt = 0;
+ u32 sq_stack_resource_mgmt_1 = 0;
+ u32 sq_stack_resource_mgmt_2 = 0;
+
+ /* FIXME: implement */
+ switch (rdev->family) {
+ case CHIP_R600:
+ rdev->config.r600.max_pipes = 4;
+ rdev->config.r600.max_tile_pipes = 8;
+ rdev->config.r600.max_simds = 4;
+ rdev->config.r600.max_backends = 4;
+ rdev->config.r600.max_gprs = 256;
+ rdev->config.r600.max_threads = 192;
+ rdev->config.r600.max_stack_entries = 256;
+ rdev->config.r600.max_hw_contexts = 8;
+ rdev->config.r600.max_gs_threads = 16;
+ rdev->config.r600.sx_max_export_size = 128;
+ rdev->config.r600.sx_max_export_pos_size = 16;
+ rdev->config.r600.sx_max_export_smx_size = 128;
+ rdev->config.r600.sq_num_cf_insts = 2;
+ break;
+ case CHIP_RV630:
+ case CHIP_RV635:
+ rdev->config.r600.max_pipes = 2;
+ rdev->config.r600.max_tile_pipes = 2;
+ rdev->config.r600.max_simds = 3;
+ rdev->config.r600.max_backends = 1;
+ rdev->config.r600.max_gprs = 128;
+ rdev->config.r600.max_threads = 192;
+ rdev->config.r600.max_stack_entries = 128;
+ rdev->config.r600.max_hw_contexts = 8;
+ rdev->config.r600.max_gs_threads = 4;
+ rdev->config.r600.sx_max_export_size = 128;
+ rdev->config.r600.sx_max_export_pos_size = 16;
+ rdev->config.r600.sx_max_export_smx_size = 128;
+ rdev->config.r600.sq_num_cf_insts = 2;
+ break;
+ case CHIP_RV610:
+ case CHIP_RV620:
+ case CHIP_RS780:
+ case CHIP_RS880:
+ rdev->config.r600.max_pipes = 1;
+ rdev->config.r600.max_tile_pipes = 1;
+ rdev->config.r600.max_simds = 2;
+ rdev->config.r600.max_backends = 1;
+ rdev->config.r600.max_gprs = 128;
+ rdev->config.r600.max_threads = 192;
+ rdev->config.r600.max_stack_entries = 128;
+ rdev->config.r600.max_hw_contexts = 4;
+ rdev->config.r600.max_gs_threads = 4;
+ rdev->config.r600.sx_max_export_size = 128;
+ rdev->config.r600.sx_max_export_pos_size = 16;
+ rdev->config.r600.sx_max_export_smx_size = 128;
+ rdev->config.r600.sq_num_cf_insts = 1;
+ break;
+ case CHIP_RV670:
+ rdev->config.r600.max_pipes = 4;
+ rdev->config.r600.max_tile_pipes = 4;
+ rdev->config.r600.max_simds = 4;
+ rdev->config.r600.max_backends = 4;
+ rdev->config.r600.max_gprs = 192;
+ rdev->config.r600.max_threads = 192;
+ rdev->config.r600.max_stack_entries = 256;
+ rdev->config.r600.max_hw_contexts = 8;
+ rdev->config.r600.max_gs_threads = 16;
+ rdev->config.r600.sx_max_export_size = 128;
+ rdev->config.r600.sx_max_export_pos_size = 16;
+ rdev->config.r600.sx_max_export_smx_size = 128;
+ rdev->config.r600.sq_num_cf_insts = 2;
+ break;
+ default:
+ break;
+ }
+
+ /* Initialize HDP */
+ for (i = 0, j = 0; i < 32; i++, j += 0x18) {
+ WREG32((0x2c14 + j), 0x00000000);
+ WREG32((0x2c18 + j), 0x00000000);
+ WREG32((0x2c1c + j), 0x00000000);
+ WREG32((0x2c20 + j), 0x00000000);
+ WREG32((0x2c24 + j), 0x00000000);
+ }
+
+ WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+
+ /* Setup tiling */
+ tiling_config = 0;
+ ramcfg = RREG32(RAMCFG);
+ switch (rdev->config.r600.max_tile_pipes) {
+ case 1:
+ tiling_config |= PIPE_TILING(0);
+ break;
+ case 2:
+ tiling_config |= PIPE_TILING(1);
+ break;
+ case 4:
+ tiling_config |= PIPE_TILING(2);
+ break;
+ case 8:
+ tiling_config |= PIPE_TILING(3);
+ break;
+ default:
+ break;
+ }
+ tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
+ tiling_config |= GROUP_SIZE(0);
+ tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
+ if (tmp > 3) {
+ tiling_config |= ROW_TILING(3);
+ tiling_config |= SAMPLE_SPLIT(3);
+ } else {
+ tiling_config |= ROW_TILING(tmp);
+ tiling_config |= SAMPLE_SPLIT(tmp);
+ }
+ tiling_config |= BANK_SWAPS(1);
+ tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
+ rdev->config.r600.max_backends,
+ (0xff << rdev->config.r600.max_backends) & 0xff);
+ tiling_config |= BACKEND_MAP(tmp);
+ WREG32(GB_TILING_CONFIG, tiling_config);
+ WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
+ WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
+
+ tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
+ WREG32(CC_RB_BACKEND_DISABLE, tmp);
+
+ /* Setup pipes */
+ tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
+ tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
+ WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
+ WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
+
+ tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
+ WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
+ WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
+
+ /* Setup some CP states */
+ WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
+ WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
+
+ WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
+ SYNC_WALKER | SYNC_ALIGNER));
+ /* Setup various GPU states */
+ if (rdev->family == CHIP_RV670)
+ WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
+
+ tmp = RREG32(SX_DEBUG_1);
+ tmp |= SMX_EVENT_RELEASE;
+ if ((rdev->family > CHIP_R600))
+ tmp |= ENABLE_NEW_SMX_ADDRESS;
+ WREG32(SX_DEBUG_1, tmp);
+
+ if (((rdev->family) == CHIP_R600) ||
+ ((rdev->family) == CHIP_RV630) ||
+ ((rdev->family) == CHIP_RV610) ||
+ ((rdev->family) == CHIP_RV620) ||
+ ((rdev->family) == CHIP_RS780)) {
+ WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
+ } else {
+ WREG32(DB_DEBUG, 0);
+ }
+ WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
+ DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
+
+ WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
+ WREG32(VGT_NUM_INSTANCES, 0);
+
+ WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
+ WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
+
+ tmp = RREG32(SQ_MS_FIFO_SIZES);
+ if (((rdev->family) == CHIP_RV610) ||
+ ((rdev->family) == CHIP_RV620) ||
+ ((rdev->family) == CHIP_RS780)) {
+ tmp = (CACHE_FIFO_SIZE(0xa) |
+ FETCH_FIFO_HIWATER(0xa) |
+ DONE_FIFO_HIWATER(0xe0) |
+ ALU_UPDATE_FIFO_HIWATER(0x8));
+ } else if (((rdev->family) == CHIP_R600) ||
+ ((rdev->family) == CHIP_RV630)) {
+ tmp &= ~DONE_FIFO_HIWATER(0xff);
+ tmp |= DONE_FIFO_HIWATER(0x4);
+ }
+ WREG32(SQ_MS_FIFO_SIZES, tmp);
+
+ /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
+ * should be adjusted as needed by the 2D/3D drivers. This just sets default values
+ */
+ sq_config = RREG32(SQ_CONFIG);
+ sq_config &= ~(PS_PRIO(3) |
+ VS_PRIO(3) |
+ GS_PRIO(3) |
+ ES_PRIO(3));
+ sq_config |= (DX9_CONSTS |
+ VC_ENABLE |
+ PS_PRIO(0) |
+ VS_PRIO(1) |
+ GS_PRIO(2) |
+ ES_PRIO(3));
+
+ if ((rdev->family) == CHIP_R600) {
+ sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
+ NUM_VS_GPRS(124) |
+ NUM_CLAUSE_TEMP_GPRS(4));
+ sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
+ NUM_ES_GPRS(0));
+ sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
+ NUM_VS_THREADS(48) |
+ NUM_GS_THREADS(4) |
+ NUM_ES_THREADS(4));
+ sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
+ NUM_VS_STACK_ENTRIES(128));
+ sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
+ NUM_ES_STACK_ENTRIES(0));
+ } else if (((rdev->family) == CHIP_RV610) ||
+ ((rdev->family) == CHIP_RV620) ||
+ ((rdev->family) == CHIP_RS780)) {
+ /* no vertex cache */
+ sq_config &= ~VC_ENABLE;
+
+ sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
+ NUM_VS_GPRS(44) |
+ NUM_CLAUSE_TEMP_GPRS(2));
+ sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
+ NUM_ES_GPRS(17));
+ sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
+ NUM_VS_THREADS(78) |
+ NUM_GS_THREADS(4) |
+ NUM_ES_THREADS(31));
+ sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
+ NUM_VS_STACK_ENTRIES(40));
+ sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
+ NUM_ES_STACK_ENTRIES(16));
+ } else if (((rdev->family) == CHIP_RV630) ||
+ ((rdev->family) == CHIP_RV635)) {
+ sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
+ NUM_VS_GPRS(44) |
+ NUM_CLAUSE_TEMP_GPRS(2));
+ sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
+ NUM_ES_GPRS(18));
+ sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
+ NUM_VS_THREADS(78) |
+ NUM_GS_THREADS(4) |
+ NUM_ES_THREADS(31));
+ sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
+ NUM_VS_STACK_ENTRIES(40));
+ sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
+ NUM_ES_STACK_ENTRIES(16));
+ } else if ((rdev->family) == CHIP_RV670) {
+ sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
+ NUM_VS_GPRS(44) |
+ NUM_CLAUSE_TEMP_GPRS(2));
+ sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
+ NUM_ES_GPRS(17));
+ sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
+ NUM_VS_THREADS(78) |
+ NUM_GS_THREADS(4) |
+ NUM_ES_THREADS(31));
+ sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
+ NUM_VS_STACK_ENTRIES(64));
+ sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
+ NUM_ES_STACK_ENTRIES(64));
+ }
+
+ WREG32(SQ_CONFIG, sq_config);
+ WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
+ WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
+ WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
+ WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
+ WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
+
+ if (((rdev->family) == CHIP_RV610) ||
+ ((rdev->family) == CHIP_RV620) ||
+ ((rdev->family) == CHIP_RS780)) {
+ WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
+ } else {
+ WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
+ }
+
+ /* More default values. 2D/3D driver should adjust as needed */
+ WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
+ S1_X(0x4) | S1_Y(0xc)));
+ WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
+ S1_X(0x2) | S1_Y(0x2) |
+ S2_X(0xa) | S2_Y(0x6) |
+ S3_X(0x6) | S3_Y(0xa)));
+ WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
+ S1_X(0x4) | S1_Y(0xc) |
+ S2_X(0x1) | S2_Y(0x6) |
+ S3_X(0xa) | S3_Y(0xe)));
+ WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
+ S5_X(0x0) | S5_Y(0x0) |
+ S6_X(0xb) | S6_Y(0x4) |
+ S7_X(0x7) | S7_Y(0x8)));
+
+ WREG32(VGT_STRMOUT_EN, 0);
+ tmp = rdev->config.r600.max_pipes * 16;
+ switch (rdev->family) {
+ case CHIP_RV610:
+ case CHIP_RS780:
+ case CHIP_RV620:
+ tmp += 32;
+ break;
+ case CHIP_RV670:
+ tmp += 128;
+ break;
+ default:
+ break;
+ }
+ if (tmp > 256) {
+ tmp = 256;
+ }
+ WREG32(VGT_ES_PER_GS, 128);
+ WREG32(VGT_GS_PER_ES, tmp);
+ WREG32(VGT_GS_PER_VS, 2);
+ WREG32(VGT_GS_VERTEX_REUSE, 16);
+
+ /* more default values. 2D/3D driver should adjust as needed */
+ WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
+ WREG32(VGT_STRMOUT_EN, 0);
+ WREG32(SX_MISC, 0);
+ WREG32(PA_SC_MODE_CNTL, 0);
+ WREG32(PA_SC_AA_CONFIG, 0);
+ WREG32(PA_SC_LINE_STIPPLE, 0);
+ WREG32(SPI_INPUT_Z, 0);
+ WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
+ WREG32(CB_COLOR7_FRAG, 0);
+
+ /* Clear render buffer base addresses */
+ WREG32(CB_COLOR0_BASE, 0);
+ WREG32(CB_COLOR1_BASE, 0);
+ WREG32(CB_COLOR2_BASE, 0);
+ WREG32(CB_COLOR3_BASE, 0);
+ WREG32(CB_COLOR4_BASE, 0);
+ WREG32(CB_COLOR5_BASE, 0);
+ WREG32(CB_COLOR6_BASE, 0);
+ WREG32(CB_COLOR7_BASE, 0);
+ WREG32(CB_COLOR7_FRAG, 0);
+
+ switch (rdev->family) {
+ case CHIP_RV610:
+ case CHIP_RS780:
+ case CHIP_RV620:
+ tmp = TC_L2_SIZE(8);
+ break;
+ case CHIP_RV630:
+ case CHIP_RV635:
+ tmp = TC_L2_SIZE(4);
+ break;
+ case CHIP_R600:
+ tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
+ break;
+ default:
+ tmp = TC_L2_SIZE(0);
+ break;
+ }
+ WREG32(TC_CNTL, tmp);
+
+ tmp = RREG32(HDP_HOST_PATH_CNTL);
+ WREG32(HDP_HOST_PATH_CNTL, tmp);
+
+ tmp = RREG32(ARB_POP);
+ tmp |= ENABLE_TC128;
+ WREG32(ARB_POP, tmp);
+
+ WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
+ WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
+ NUM_CLIP_SEQ(3)));
+ WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
+}
+
+
/*
* Indirect registers accessor
*/
-uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg)
+u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
{
- uint32_t r;
+ u32 r;
- WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff));
- (void)RREG32(R600_PCIE_PORT_INDEX);
- r = RREG32(R600_PCIE_PORT_DATA);
+ WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
+ (void)RREG32(PCIE_PORT_INDEX);
+ r = RREG32(PCIE_PORT_DATA);
return r;
}
-void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
{
- WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff));
- (void)RREG32(R600_PCIE_PORT_INDEX);
- WREG32(R600_PCIE_PORT_DATA, (v));
- (void)RREG32(R600_PCIE_PORT_DATA);
+ WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
+ (void)RREG32(PCIE_PORT_INDEX);
+ WREG32(PCIE_PORT_DATA, (v));
+ (void)RREG32(PCIE_PORT_DATA);
+}
+
+
+/*
+ * CP & Ring
+ */
+void r600_cp_stop(struct radeon_device *rdev)
+{
+ WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
+}
+
+int r600_cp_init_microcode(struct radeon_device *rdev)
+{
+ struct platform_device *pdev;
+ const char *chip_name;
+ size_t pfp_req_size, me_req_size;
+ char fw_name[30];
+ int err;
+
+ DRM_DEBUG("\n");
+
+ pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
+ err = IS_ERR(pdev);
+ if (err) {
+ printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
+ return -EINVAL;
+ }
+
+ switch (rdev->family) {
+ case CHIP_R600: chip_name = "R600"; break;
+ case CHIP_RV610: chip_name = "RV610"; break;
+ case CHIP_RV630: chip_name = "RV630"; break;
+ case CHIP_RV620: chip_name = "RV620"; break;
+ case CHIP_RV635: chip_name = "RV635"; break;
+ case CHIP_RV670: chip_name = "RV670"; break;
+ case CHIP_RS780:
+ case CHIP_RS880: chip_name = "RS780"; break;
+ case CHIP_RV770: chip_name = "RV770"; break;
+ case CHIP_RV730:
+ case CHIP_RV740: chip_name = "RV730"; break;
+ case CHIP_RV710: chip_name = "RV710"; break;
+ default: BUG();
+ }
+
+ if (rdev->family >= CHIP_RV770) {
+ pfp_req_size = R700_PFP_UCODE_SIZE * 4;
+ me_req_size = R700_PM4_UCODE_SIZE * 4;
+ } else {
+ pfp_req_size = PFP_UCODE_SIZE * 4;
+ me_req_size = PM4_UCODE_SIZE * 12;
+ }
+
+ DRM_INFO("Loading %s CP Microcode\n", chip_name);
+
+ snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
+ err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
+ if (err)
+ goto out;
+ if (rdev->pfp_fw->size != pfp_req_size) {
+ printk(KERN_ERR
+ "r600_cp: Bogus length %zu in firmware \"%s\"\n",
+ rdev->pfp_fw->size, fw_name);
+ err = -EINVAL;
+ goto out;
+ }
+
+ snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
+ err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
+ if (err)
+ goto out;
+ if (rdev->me_fw->size != me_req_size) {
+ printk(KERN_ERR
+ "r600_cp: Bogus length %zu in firmware \"%s\"\n",
+ rdev->me_fw->size, fw_name);
+ err = -EINVAL;
+ }
+out:
+ platform_device_unregister(pdev);
+
+ if (err) {
+ if (err != -EINVAL)
+ printk(KERN_ERR
+ "r600_cp: Failed to load firmware \"%s\"\n",
+ fw_name);
+ release_firmware(rdev->pfp_fw);
+ rdev->pfp_fw = NULL;
+ release_firmware(rdev->me_fw);
+ rdev->me_fw = NULL;
+ }
+ return err;
+}
+
+static int r600_cp_load_microcode(struct radeon_device *rdev)
+{
+ const __be32 *fw_data;
+ int i;
+
+ if (!rdev->me_fw || !rdev->pfp_fw)
+ return -EINVAL;
+
+ r600_cp_stop(rdev);
+
+ WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
+
+ /* Reset cp */
+ WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
+ RREG32(GRBM_SOFT_RESET);
+ mdelay(15);
+ WREG32(GRBM_SOFT_RESET, 0);
+
+ WREG32(CP_ME_RAM_WADDR, 0);
+
+ fw_data = (const __be32 *)rdev->me_fw->data;
+ WREG32(CP_ME_RAM_WADDR, 0);
+ for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
+ WREG32(CP_ME_RAM_DATA,
+ be32_to_cpup(fw_data++));
+
+ fw_data = (const __be32 *)rdev->pfp_fw->data;
+ WREG32(CP_PFP_UCODE_ADDR, 0);
+ for (i = 0; i < PFP_UCODE_SIZE; i++)
+ WREG32(CP_PFP_UCODE_DATA,
+ be32_to_cpup(fw_data++));
+
+ WREG32(CP_PFP_UCODE_ADDR, 0);
+ WREG32(CP_ME_RAM_WADDR, 0);
+ WREG32(CP_ME_RAM_RADDR, 0);
+ return 0;
+}
+
+int r600_cp_start(struct radeon_device *rdev)
+{
+ int r;
+ uint32_t cp_me;
+
+ r = radeon_ring_lock(rdev, 7);
+ if (r) {
+ DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+ return r;
+ }
+ radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
+ radeon_ring_write(rdev, 0x1);
+ if (rdev->family < CHIP_RV770) {
+ radeon_ring_write(rdev, 0x3);
+ radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
+ } else {
+ radeon_ring_write(rdev, 0x0);
+ radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
+ }
+ radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
+ radeon_ring_write(rdev, 0);
+ radeon_ring_write(rdev, 0);
+ radeon_ring_unlock_commit(rdev);
+
+ cp_me = 0xff;
+ WREG32(R_0086D8_CP_ME_CNTL, cp_me);
+ return 0;
+}
+
+int r600_cp_resume(struct radeon_device *rdev)
+{
+ u32 tmp;
+ u32 rb_bufsz;
+ int r;
+
+ /* Reset cp */
+ WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
+ RREG32(GRBM_SOFT_RESET);
+ mdelay(15);
+ WREG32(GRBM_SOFT_RESET, 0);
+
+ /* Set ring buffer size */
+ rb_bufsz = drm_order(rdev->cp.ring_size / 8);
+#ifdef __BIG_ENDIAN
+ WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE |
+ (drm_order(4096/8) << 8) | rb_bufsz);
+#else
+ WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz);
+#endif
+ WREG32(CP_SEM_WAIT_TIMER, 0x4);
+
+ /* Set the write pointer delay */
+ WREG32(CP_RB_WPTR_DELAY, 0);
+
+ /* Initialize the ring buffer's read and write pointers */
+ tmp = RREG32(CP_RB_CNTL);
+ WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
+ WREG32(CP_RB_RPTR_WR, 0);
+ WREG32(CP_RB_WPTR, 0);
+ WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
+ WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
+ mdelay(1);
+ WREG32(CP_RB_CNTL, tmp);
+
+ WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
+ WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
+
+ rdev->cp.rptr = RREG32(CP_RB_RPTR);
+ rdev->cp.wptr = RREG32(CP_RB_WPTR);
+
+ r600_cp_start(rdev);
+ rdev->cp.ready = true;
+ r = radeon_ring_test(rdev);
+ if (r) {
+ rdev->cp.ready = false;
+ return r;
+ }
+ return 0;
+}
+
+void r600_cp_commit(struct radeon_device *rdev)
+{
+ WREG32(CP_RB_WPTR, rdev->cp.wptr);
+ (void)RREG32(CP_RB_WPTR);
+}
+
+void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
+{
+ u32 rb_bufsz;
+
+ /* Align ring size */
+ rb_bufsz = drm_order(ring_size / 8);
+ ring_size = (1 << (rb_bufsz + 1)) * 4;
+ rdev->cp.ring_size = ring_size;
+ rdev->cp.align_mask = 16 - 1;
+}
+
+
+/*
+ * GPU scratch registers helpers function.
+ */
+void r600_scratch_init(struct radeon_device *rdev)
+{
+ int i;
+
+ rdev->scratch.num_reg = 7;
+ for (i = 0; i < rdev->scratch.num_reg; i++) {
+ rdev->scratch.free[i] = true;
+ rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
+ }
+}
+
+int r600_ring_test(struct radeon_device *rdev)
+{
+ uint32_t scratch;
+ uint32_t tmp = 0;
+ unsigned i;
+ int r;
+
+ r = radeon_scratch_get(rdev, &scratch);
+ if (r) {
+ DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
+ return r;
+ }
+ WREG32(scratch, 0xCAFEDEAD);
+ r = radeon_ring_lock(rdev, 3);
+ if (r) {
+ DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+ radeon_scratch_free(rdev, scratch);
+ return r;
+ }
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+ radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
+ radeon_ring_write(rdev, 0xDEADBEEF);
+ radeon_ring_unlock_commit(rdev);
+ for (i = 0; i < rdev->usec_timeout; i++) {
+ tmp = RREG32(scratch);
+ if (tmp == 0xDEADBEEF)
+ break;
+ DRM_UDELAY(1);
+ }
+ if (i < rdev->usec_timeout) {
+ DRM_INFO("ring test succeeded in %d usecs\n", i);
+ } else {
+ DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
+ scratch, tmp);
+ r = -EINVAL;
+ }
+ radeon_scratch_free(rdev, scratch);
+ return r;
+}
+
+/*
+ * Writeback
+ */
+int r600_wb_init(struct radeon_device *rdev)
+{
+ int r;
+
+ if (rdev->wb.wb_obj == NULL) {
+ r = radeon_object_create(rdev, NULL, 4096,
+ true,
+ RADEON_GEM_DOMAIN_GTT,
+ false, &rdev->wb.wb_obj);
+ if (r) {
+ DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
+ return r;
+ }
+ r = radeon_object_pin(rdev->wb.wb_obj,
+ RADEON_GEM_DOMAIN_GTT,
+ &rdev->wb.gpu_addr);
+ if (r) {
+ DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
+ return r;
+ }
+ r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
+ if (r) {
+ DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
+ return r;
+ }
+ }
+ WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
+ WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
+ WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
+ WREG32(SCRATCH_UMSK, 0xff);
+ return 0;
+}
+
+void r600_wb_fini(struct radeon_device *rdev)
+{
+ if (rdev->wb.wb_obj) {
+ radeon_object_kunmap(rdev->wb.wb_obj);
+ radeon_object_unpin(rdev->wb.wb_obj);
+ radeon_object_unref(&rdev->wb.wb_obj);
+ rdev->wb.wb = NULL;
+ rdev->wb.wb_obj = NULL;
+ }
+}
+
+
+/*
+ * CS
+ */
+void r600_fence_ring_emit(struct radeon_device *rdev,
+ struct radeon_fence *fence)
+{
+ /* Emit fence sequence & fire IRQ */
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+ radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
+ radeon_ring_write(rdev, fence->seq);
+}
+
+int r600_copy_dma(struct radeon_device *rdev,
+ uint64_t src_offset,
+ uint64_t dst_offset,
+ unsigned num_pages,
+ struct radeon_fence *fence)
+{
+ /* FIXME: implement */
+ return 0;
+}
+
+int r600_copy_blit(struct radeon_device *rdev,
+ uint64_t src_offset, uint64_t dst_offset,
+ unsigned num_pages, struct radeon_fence *fence)
+{
+ r600_blit_prepare_copy(rdev, num_pages * 4096);
+ r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096);
+ r600_blit_done_copy(rdev, fence);
+ return 0;
+}
+
+int r600_irq_process(struct radeon_device *rdev)
+{
+ /* FIXME: implement */
+ return 0;
+}
+
+int r600_irq_set(struct radeon_device *rdev)
+{
+ /* FIXME: implement */
+ return 0;
+}
+
+int r600_set_surface_reg(struct radeon_device *rdev, int reg,
+ uint32_t tiling_flags, uint32_t pitch,
+ uint32_t offset, uint32_t obj_size)
+{
+ /* FIXME: implement */
+ return 0;
+}
+
+void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
+{
+ /* FIXME: implement */
+}
+
+
+bool r600_card_posted(struct radeon_device *rdev)
+{
+ uint32_t reg;
+
+ /* first check CRTCs */
+ reg = RREG32(D1CRTC_CONTROL) |
+ RREG32(D2CRTC_CONTROL);
+ if (reg & CRTC_EN)
+ return true;
+
+ /* then check MEM_SIZE, in case the crtcs are off */
+ if (RREG32(CONFIG_MEMSIZE))
+ return true;
+
+ return false;
+}
+
+int r600_startup(struct radeon_device *rdev)
+{
+ int r;
+
+ r600_gpu_reset(rdev);
+ r600_mc_resume(rdev);
+ r = r600_pcie_gart_enable(rdev);
+ if (r)
+ return r;
+ r600_gpu_init(rdev);
+
+ r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
+ &rdev->r600_blit.shader_gpu_addr);
+ if (r) {
+ DRM_ERROR("failed to pin blit object %d\n", r);
+ return r;
+ }
+
+ r = radeon_ring_init(rdev, rdev->cp.ring_size);
+ if (r)
+ return r;
+ r = r600_cp_load_microcode(rdev);
+ if (r)
+ return r;
+ r = r600_cp_resume(rdev);
+ if (r)
+ return r;
+ r = r600_wb_init(rdev);
+ if (r)
+ return r;
+ return 0;
+}
+
+void r600_vga_set_state(struct radeon_device *rdev, bool state)
+{
+ uint32_t temp;
+
+ temp = RREG32(CONFIG_CNTL);
+ if (state == false) {
+ temp &= ~(1<<0);
+ temp |= (1<<1);
+ } else {
+ temp &= ~(1<<1);
+ }
+ WREG32(CONFIG_CNTL, temp);
+}
+
+int r600_resume(struct radeon_device *rdev)
+{
+ int r;
+
+ if (radeon_gpu_reset(rdev)) {
+ /* FIXME: what do we want to do here ? */
+ }
+ /* post card */
+ if (rdev->is_atom_bios) {
+ atom_asic_init(rdev->mode_info.atom_context);
+ } else {
+ radeon_combios_asic_init(rdev->ddev);
+ }
+ /* Initialize clocks */
+ r = radeon_clocks_init(rdev);
+ if (r) {
+ return r;
+ }
+
+ r = r600_startup(rdev);
+ if (r) {
+ DRM_ERROR("r600 startup failed on resume\n");
+ return r;
+ }
+
+ r = radeon_ib_test(rdev);
+ if (r) {
+ DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+ return r;
+ }
+ return r;
+}
+
+
+int r600_suspend(struct radeon_device *rdev)
+{
+ /* FIXME: we should wait for ring to be empty */
+ r600_cp_stop(rdev);
+ rdev->cp.ready = false;
+
+ r600_pcie_gart_disable(rdev);
+ /* unpin shaders bo */
+ radeon_object_unpin(rdev->r600_blit.shader_obj);
+ return 0;
+}
+
+/* Plan is to move initialization in that function and use
+ * helper function so that radeon_device_init pretty much
+ * do nothing more than calling asic specific function. This
+ * should also allow to remove a bunch of callback function
+ * like vram_info.
+ */
+int r600_init(struct radeon_device *rdev)
+{
+ int r;
+
+ rdev->new_init_path = true;
+ r = radeon_dummy_page_init(rdev);
+ if (r)
+ return r;
+ if (r600_debugfs_mc_info_init(rdev)) {
+ DRM_ERROR("Failed to register debugfs file for mc !\n");
+ }
+ /* This don't do much */
+ r = radeon_gem_init(rdev);
+ if (r)
+ return r;
+ /* Read BIOS */
+ if (!radeon_get_bios(rdev)) {
+ if (ASIC_IS_AVIVO(rdev))
+ return -EINVAL;
+ }
+ /* Must be an ATOMBIOS */
+ if (!rdev->is_atom_bios)
+ return -EINVAL;
+ r = radeon_atombios_init(rdev);
+ if (r)
+ return r;
+ /* Post card if necessary */
+ if (!r600_card_posted(rdev) && rdev->bios) {
+ DRM_INFO("GPU not posted. posting now...\n");
+ atom_asic_init(rdev->mode_info.atom_context);
+ }
+ /* Initialize scratch registers */
+ r600_scratch_init(rdev);
+ /* Initialize surface registers */
+ radeon_surface_init(rdev);
+ radeon_get_clock_info(rdev->ddev);
+ r = radeon_clocks_init(rdev);
+ if (r)
+ return r;
+ /* Fence driver */
+ r = radeon_fence_driver_init(rdev);
+ if (r)
+ return r;
+ r = r600_mc_init(rdev);
+ if (r) {
+ if (rdev->flags & RADEON_IS_AGP) {
+ /* Retry with disabling AGP */
+ r600_fini(rdev);
+ rdev->flags &= ~RADEON_IS_AGP;
+ return r600_init(rdev);
+ }
+ return r;
+ }
+ /* Memory manager */
+ r = radeon_object_init(rdev);
+ if (r)
+ return r;
+ rdev->cp.ring_obj = NULL;
+ r600_ring_init(rdev, 1024 * 1024);
+
+ if (!rdev->me_fw || !rdev->pfp_fw) {
+ r = r600_cp_init_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load firmware!\n");
+ return r;
+ }
+ }
+
+ r = r600_pcie_gart_init(rdev);
+ if (r)
+ return r;
+
+ rdev->accel_working = true;
+ r = r600_blit_init(rdev);
+ if (r) {
+ DRM_ERROR("radeon: failled blitter (%d).\n", r);
+ return r;
+ }
+
+ r = r600_startup(rdev);
+ if (r) {
+ if (rdev->flags & RADEON_IS_AGP) {
+ /* Retry with disabling AGP */
+ r600_fini(rdev);
+ rdev->flags &= ~RADEON_IS_AGP;
+ return r600_init(rdev);
+ }
+ rdev->accel_working = false;
+ }
+ if (rdev->accel_working) {
+ r = radeon_ib_pool_init(rdev);
+ if (r) {
+ DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
+ rdev->accel_working = false;
+ }
+ r = radeon_ib_test(rdev);
+ if (r) {
+ DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+ rdev->accel_working = false;
+ }
+ }
+ return 0;
+}
+
+void r600_fini(struct radeon_device *rdev)
+{
+ /* Suspend operations */
+ r600_suspend(rdev);
+
+ r600_blit_fini(rdev);
+ radeon_ring_fini(rdev);
+ r600_pcie_gart_fini(rdev);
+ radeon_gem_fini(rdev);
+ radeon_fence_driver_fini(rdev);
+ radeon_clocks_fini(rdev);
+#if __OS_HAS_AGP
+ if (rdev->flags & RADEON_IS_AGP)
+ radeon_agp_fini(rdev);
+#endif
+ radeon_object_fini(rdev);
+ if (rdev->is_atom_bios)
+ radeon_atombios_fini(rdev);
+ else
+ radeon_combios_fini(rdev);
+ kfree(rdev->bios);
+ rdev->bios = NULL;
+ radeon_dummy_page_fini(rdev);
+}
+
+
+/*
+ * CS stuff
+ */
+void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
+{
+ /* FIXME: implement */
+ radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
+ radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
+ radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
+ radeon_ring_write(rdev, ib->length_dw);
+}
+
+int r600_ib_test(struct radeon_device *rdev)
+{
+ struct radeon_ib *ib;
+ uint32_t scratch;
+ uint32_t tmp = 0;
+ unsigned i;
+ int r;
+
+ r = radeon_scratch_get(rdev, &scratch);
+ if (r) {
+ DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
+ return r;
+ }
+ WREG32(scratch, 0xCAFEDEAD);
+ r = radeon_ib_get(rdev, &ib);
+ if (r) {
+ DRM_ERROR("radeon: failed to get ib (%d).\n", r);
+ return r;
+ }
+ ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
+ ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+ ib->ptr[2] = 0xDEADBEEF;
+ ib->ptr[3] = PACKET2(0);
+ ib->ptr[4] = PACKET2(0);
+ ib->ptr[5] = PACKET2(0);
+ ib->ptr[6] = PACKET2(0);
+ ib->ptr[7] = PACKET2(0);
+ ib->ptr[8] = PACKET2(0);
+ ib->ptr[9] = PACKET2(0);
+ ib->ptr[10] = PACKET2(0);
+ ib->ptr[11] = PACKET2(0);
+ ib->ptr[12] = PACKET2(0);
+ ib->ptr[13] = PACKET2(0);
+ ib->ptr[14] = PACKET2(0);
+ ib->ptr[15] = PACKET2(0);
+ ib->length_dw = 16;
+ r = radeon_ib_schedule(rdev, ib);
+ if (r) {
+ radeon_scratch_free(rdev, scratch);
+ radeon_ib_free(rdev, &ib);
+ DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
+ return r;
+ }
+ r = radeon_fence_wait(ib->fence, false);
+ if (r) {
+ DRM_ERROR("radeon: fence wait failed (%d).\n", r);
+ return r;
+ }
+ for (i = 0; i < rdev->usec_timeout; i++) {
+ tmp = RREG32(scratch);
+ if (tmp == 0xDEADBEEF)
+ break;
+ DRM_UDELAY(1);
+ }
+ if (i < rdev->usec_timeout) {
+ DRM_INFO("ib test succeeded in %u usecs\n", i);
+ } else {
+ DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
+ scratch, tmp);
+ r = -EINVAL;
+ }
+ radeon_scratch_free(rdev, scratch);
+ radeon_ib_free(rdev, &ib);
+ return r;
+}
+
+
+
+
+/*
+ * Debugfs info
+ */
+#if defined(CONFIG_DEBUG_FS)
+
+static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ uint32_t rdp, wdp;
+ unsigned count, i, j;
+
+ radeon_ring_free_size(rdev);
+ rdp = RREG32(CP_RB_RPTR);
+ wdp = RREG32(CP_RB_WPTR);
+ count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
+ seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
+ seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
+ seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
+ seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
+ seq_printf(m, "%u dwords in ring\n", count);
+ for (j = 0; j <= count; j++) {
+ i = (rdp + j) & rdev->cp.ptr_mask;
+ seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
+ }
+ return 0;
+}
+
+static int r600_debugfs_mc_info(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct radeon_device *rdev = dev->dev_private;
+
+ DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
+ DREG32_SYS(m, rdev, VM_L2_STATUS);
+ return 0;
+}
+
+static struct drm_info_list r600_mc_info_list[] = {
+ {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
+ {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
+};
+#endif
+
+int r600_debugfs_mc_info_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+ return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
+#else
+ return 0;
+#endif
}
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
new file mode 100644
index 0000000..dde2ccb
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -0,0 +1,850 @@
+/*
+ * Copyright 2009 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Alex Deucher <alexander.deucher@amd.com>
+ */
+#include "drmP.h"
+#include "drm.h"
+#include "radeon_drm.h"
+#include "radeon_drv.h"
+
+#include "r600_blit_shaders.h"
+
+#define DI_PT_RECTLIST 0x11
+#define DI_INDEX_SIZE_16_BIT 0x0
+#define DI_SRC_SEL_AUTO_INDEX 0x2
+
+#define FMT_8 0x1
+#define FMT_5_6_5 0x8
+#define FMT_8_8_8_8 0x1a
+#define COLOR_8 0x1
+#define COLOR_5_6_5 0x8
+#define COLOR_8_8_8_8 0x1a
+
+static inline void
+set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr)
+{
+ u32 cb_color_info;
+ int pitch, slice;
+ RING_LOCALS;
+ DRM_DEBUG("\n");
+
+ h = (h + 7) & ~7;
+ if (h < 8)
+ h = 8;
+
+ cb_color_info = ((format << 2) | (1 << 27));
+ pitch = (w / 8) - 1;
+ slice = ((w * h) / 64) - 1;
+
+ if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) &&
+ ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) {
+ BEGIN_RING(21 + 2);
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING(gpu_addr >> 8);
+ OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
+ OUT_RING(2 << 0);
+ } else {
+ BEGIN_RING(21);
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING(gpu_addr >> 8);
+ }
+
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING((pitch << 0) | (slice << 10));
+
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING(0);
+
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING(cb_color_info);
+
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING(0);
+
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING(0);
+
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING(0);
+
+ ADVANCE_RING();
+}
+
+static inline void
+cp_set_surface_sync(drm_radeon_private_t *dev_priv,
+ u32 sync_type, u32 size, u64 mc_addr)
+{
+ u32 cp_coher_size;
+ RING_LOCALS;
+ DRM_DEBUG("\n");
+
+ if (size == 0xffffffff)
+ cp_coher_size = 0xffffffff;
+ else
+ cp_coher_size = ((size + 255) >> 8);
+
+ BEGIN_RING(5);
+ OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
+ OUT_RING(sync_type);
+ OUT_RING(cp_coher_size);
+ OUT_RING((mc_addr >> 8));
+ OUT_RING(10); /* poll interval */
+ ADVANCE_RING();
+}
+
+static inline void
+set_shaders(struct drm_device *dev)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ u64 gpu_addr;
+ int i;
+ u32 *vs, *ps;
+ uint32_t sq_pgm_resources;
+ RING_LOCALS;
+ DRM_DEBUG("\n");
+
+ /* load shaders */
+ vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset);
+ ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
+
+ for (i = 0; i < r6xx_vs_size; i++)
+ vs[i] = r6xx_vs[i];
+ for (i = 0; i < r6xx_ps_size; i++)
+ ps[i] = r6xx_ps[i];
+
+ dev_priv->blit_vb->used = 512;
+
+ gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset;
+
+ /* setup shader regs */
+ sq_pgm_resources = (1 << 0);
+
+ BEGIN_RING(9 + 12);
+ /* VS */
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING(gpu_addr >> 8);
+
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING(sq_pgm_resources);
+
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING(0);
+
+ /* PS */
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING((gpu_addr + 256) >> 8);
+
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING(sq_pgm_resources | (1 << 28));
+
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING(2);
+
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+ OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING(0);
+ ADVANCE_RING();
+
+ cp_set_surface_sync(dev_priv,
+ R600_SH_ACTION_ENA, 512, gpu_addr);
+}
+
+static inline void
+set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
+{
+ uint32_t sq_vtx_constant_word2;
+ RING_LOCALS;
+ DRM_DEBUG("\n");
+
+ sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8));
+
+ BEGIN_RING(9);
+ OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
+ OUT_RING(0x460);
+ OUT_RING(gpu_addr & 0xffffffff);
+ OUT_RING(48 - 1);
+ OUT_RING(sq_vtx_constant_word2);
+ OUT_RING(1 << 0);
+ OUT_RING(0);
+ OUT_RING(0);
+ OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30);
+ ADVANCE_RING();
+
+ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
+ cp_set_surface_sync(dev_priv,
+ R600_TC_ACTION_ENA, 48, gpu_addr);
+ else
+ cp_set_surface_sync(dev_priv,
+ R600_VC_ACTION_ENA, 48, gpu_addr);
+}
+
+static inline void
+set_tex_resource(drm_radeon_private_t *dev_priv,
+ int format, int w, int h, int pitch, u64 gpu_addr)
+{
+ uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
+ RING_LOCALS;
+ DRM_DEBUG("\n");
+
+ if (h < 1)
+ h = 1;
+
+ sq_tex_resource_word0 = (1 << 0);
+ sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
+ ((w - 1) << 19));
+
+ sq_tex_resource_word1 = (format << 26);
+ sq_tex_resource_word1 |= ((h - 1) << 0);
+
+ sq_tex_resource_word4 = ((1 << 14) |
+ (0 << 16) |
+ (1 << 19) |
+ (2 << 22) |
+ (3 << 25));
+
+ BEGIN_RING(9);
+ OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
+ OUT_RING(0);
+ OUT_RING(sq_tex_resource_word0);
+ OUT_RING(sq_tex_resource_word1);
+ OUT_RING(gpu_addr >> 8);
+ OUT_RING(gpu_addr >> 8);
+ OUT_RING(sq_tex_resource_word4);
+ OUT_RING(0);
+ OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30);
+ ADVANCE_RING();
+
+}
+
+static inline void
+set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
+{
+ RING_LOCALS;
+ DRM_DEBUG("\n");
+
+ BEGIN_RING(12);
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
+ OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING((x1 << 0) | (y1 << 16));
+ OUT_RING((x2 << 0) | (y2 << 16));
+
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
+ OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
+ OUT_RING((x2 << 0) | (y2 << 16));
+
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
+ OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+ OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
+ OUT_RING((x2 << 0) | (y2 << 16));
+ ADVANCE_RING();
+}
+
+static inline void
+draw_auto(drm_radeon_private_t *dev_priv)
+{
+ RING_LOCALS;
+ DRM_DEBUG("\n");
+
+ BEGIN_RING(10);
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
+ OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2);
+ OUT_RING(DI_PT_RECTLIST);
+
+ OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
+ OUT_RING(DI_INDEX_SIZE_16_BIT);
+
+ OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
+ OUT_RING(1);
+
+ OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
+ OUT_RING(3);
+ OUT_RING(DI_SRC_SEL_AUTO_INDEX);
+
+ ADVANCE_RING();
+ COMMIT_RING();
+}
+
+static inline void
+set_default_state(drm_radeon_private_t *dev_priv)
+{
+ int i;
+ u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
+ u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
+ int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
+ int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
+ int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
+ RING_LOCALS;
+
+ switch ((dev_priv->flags & RADEON_FAMILY_MASK)) {
+ case CHIP_R600:
+ num_ps_gprs = 192;
+ num_vs_gprs = 56;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 136;
+ num_vs_threads = 48;
+ num_gs_threads = 4;
+ num_es_threads = 4;
+ num_ps_stack_entries = 128;
+ num_vs_stack_entries = 128;
+ num_gs_stack_entries = 0;
+ num_es_stack_entries = 0;
+ break;
+ case CHIP_RV630:
+ case CHIP_RV635:
+ num_ps_gprs = 84;
+ num_vs_gprs = 36;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 144;
+ num_vs_threads = 40;
+ num_gs_threads = 4;
+ num_es_threads = 4;
+ num_ps_stack_entries = 40;
+ num_vs_stack_entries = 40;
+ num_gs_stack_entries = 32;
+ num_es_stack_entries = 16;
+ break;
+ case CHIP_RV610:
+ case CHIP_RV620:
+ case CHIP_RS780:
+ case CHIP_RS880:
+ default:
+ num_ps_gprs = 84;
+ num_vs_gprs = 36;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 136;
+ num_vs_threads = 48;
+ num_gs_threads = 4;
+ num_es_threads = 4;
+ num_ps_stack_entries = 40;
+ num_vs_stack_entries = 40;
+ num_gs_stack_entries = 32;
+ num_es_stack_entries = 16;
+ break;
+ case CHIP_RV670:
+ num_ps_gprs = 144;
+ num_vs_gprs = 40;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 136;
+ num_vs_threads = 48;
+ num_gs_threads = 4;
+ num_es_threads = 4;
+ num_ps_stack_entries = 40;
+ num_vs_stack_entries = 40;
+ num_gs_stack_entries = 32;
+ num_es_stack_entries = 16;
+ break;
+ case CHIP_RV770:
+ num_ps_gprs = 192;
+ num_vs_gprs = 56;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 188;
+ num_vs_threads = 60;
+ num_gs_threads = 0;
+ num_es_threads = 0;
+ num_ps_stack_entries = 256;
+ num_vs_stack_entries = 256;
+ num_gs_stack_entries = 0;
+ num_es_stack_entries = 0;
+ break;
+ case CHIP_RV730:
+ case CHIP_RV740:
+ num_ps_gprs = 84;
+ num_vs_gprs = 36;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 188;
+ num_vs_threads = 60;
+ num_gs_threads = 0;
+ num_es_threads = 0;
+ num_ps_stack_entries = 128;
+ num_vs_stack_entries = 128;
+ num_gs_stack_entries = 0;
+ num_es_stack_entries = 0;
+ break;
+ case CHIP_RV710:
+ num_ps_gprs = 192;
+ num_vs_gprs = 56;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 144;
+ num_vs_threads = 48;
+ num_gs_threads = 0;
+ num_es_threads = 0;
+ num_ps_stack_entries = 128;
+ num_vs_stack_entries = 128;
+ num_gs_stack_entries = 0;
+ num_es_stack_entries = 0;
+ break;
+ }
+
+ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
+ sq_config = 0;
+ else
+ sq_config = R600_VC_ENABLE;
+
+ sq_config |= (R600_DX9_CONSTS |
+ R600_ALU_INST_PREFER_VECTOR |
+ R600_PS_PRIO(0) |
+ R600_VS_PRIO(1) |
+ R600_GS_PRIO(2) |
+ R600_ES_PRIO(3));
+
+ sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(num_ps_gprs) |
+ R600_NUM_VS_GPRS(num_vs_gprs) |
+ R600_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
+ sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(num_gs_gprs) |
+ R600_NUM_ES_GPRS(num_es_gprs));
+ sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(num_ps_threads) |
+ R600_NUM_VS_THREADS(num_vs_threads) |
+ R600_NUM_GS_THREADS(num_gs_threads) |
+ R600_NUM_ES_THREADS(num_es_threads));
+ sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
+ R600_NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
+ sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
+ R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries));
+
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
+ BEGIN_RING(r7xx_default_size + 10);
+ for (i = 0; i < r7xx_default_size; i++)
+ OUT_RING(r7xx_default_state[i]);
+ } else {
+ BEGIN_RING(r6xx_default_size + 10);
+ for (i = 0; i < r6xx_default_size; i++)
+ OUT_RING(r6xx_default_state[i]);
+ }
+ OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
+ OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
+ /* SQ config */
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6));
+ OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2);
+ OUT_RING(sq_config);
+ OUT_RING(sq_gpr_resource_mgmt_1);
+ OUT_RING(sq_gpr_resource_mgmt_2);
+ OUT_RING(sq_thread_resource_mgmt);
+ OUT_RING(sq_stack_resource_mgmt_1);
+ OUT_RING(sq_stack_resource_mgmt_2);
+ ADVANCE_RING();
+}
+
+static inline uint32_t i2f(uint32_t input)
+{
+ u32 result, i, exponent, fraction;
+
+ if ((input & 0x3fff) == 0)
+ result = 0; /* 0 is a special case */
+ else {
+ exponent = 140; /* exponent biased by 127; */
+ fraction = (input & 0x3fff) << 10; /* cheat and only
+ handle numbers below 2^^15 */
+ for (i = 0; i < 14; i++) {
+ if (fraction & 0x800000)
+ break;
+ else {
+ fraction = fraction << 1; /* keep
+ shifting left until top bit = 1 */
+ exponent = exponent - 1;
+ }
+ }
+ result = exponent << 23 | (fraction & 0x7fffff); /* mask
+ off top bit; assumed 1 */
+ }
+ return result;
+}
+
+
+static inline int r600_nomm_get_vb(struct drm_device *dev)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ dev_priv->blit_vb = radeon_freelist_get(dev);
+ if (!dev_priv->blit_vb) {
+ DRM_ERROR("Unable to allocate vertex buffer for blit\n");
+ return -EAGAIN;
+ }
+ return 0;
+}
+
+static inline void r600_nomm_put_vb(struct drm_device *dev)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+
+ dev_priv->blit_vb->used = 0;
+ radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb);
+}
+
+static inline void *r600_nomm_get_vb_ptr(struct drm_device *dev)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ return (((char *)dev->agp_buffer_map->handle +
+ dev_priv->blit_vb->offset + dev_priv->blit_vb->used));
+}
+
+int
+r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ DRM_DEBUG("\n");
+
+ r600_nomm_get_vb(dev);
+
+ dev_priv->blit_vb->file_priv = file_priv;
+
+ set_default_state(dev_priv);
+ set_shaders(dev);
+
+ return 0;
+}
+
+
+void
+r600_done_blit_copy(struct drm_device *dev)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ RING_LOCALS;
+ DRM_DEBUG("\n");
+
+ BEGIN_RING(5);
+ OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
+ OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
+ /* wait for 3D idle clean */
+ OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
+ OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
+ OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
+
+ ADVANCE_RING();
+ COMMIT_RING();
+
+ r600_nomm_put_vb(dev);
+}
+
+void
+r600_blit_copy(struct drm_device *dev,
+ uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
+ int size_bytes)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ int max_bytes;
+ u64 vb_addr;
+ u32 *vb;
+
+ vb = r600_nomm_get_vb_ptr(dev);
+
+ if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
+ max_bytes = 8192;
+
+ while (size_bytes) {
+ int cur_size = size_bytes;
+ int src_x = src_gpu_addr & 255;
+ int dst_x = dst_gpu_addr & 255;
+ int h = 1;
+ src_gpu_addr = src_gpu_addr & ~255;
+ dst_gpu_addr = dst_gpu_addr & ~255;
+
+ if (!src_x && !dst_x) {
+ h = (cur_size / max_bytes);
+ if (h > 8192)
+ h = 8192;
+ if (h == 0)
+ h = 1;
+ else
+ cur_size = max_bytes;
+ } else {
+ if (cur_size > max_bytes)
+ cur_size = max_bytes;
+ if (cur_size > (max_bytes - dst_x))
+ cur_size = (max_bytes - dst_x);
+ if (cur_size > (max_bytes - src_x))
+ cur_size = (max_bytes - src_x);
+ }
+
+ if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
+
+ r600_nomm_put_vb(dev);
+ r600_nomm_get_vb(dev);
+ if (!dev_priv->blit_vb)
+ return;
+ set_shaders(dev);
+ vb = r600_nomm_get_vb_ptr(dev);
+ }
+
+ vb[0] = i2f(dst_x);
+ vb[1] = 0;
+ vb[2] = i2f(src_x);
+ vb[3] = 0;
+
+ vb[4] = i2f(dst_x);
+ vb[5] = i2f(h);
+ vb[6] = i2f(src_x);
+ vb[7] = i2f(h);
+
+ vb[8] = i2f(dst_x + cur_size);
+ vb[9] = i2f(h);
+ vb[10] = i2f(src_x + cur_size);
+ vb[11] = i2f(h);
+
+ /* src */
+ set_tex_resource(dev_priv, FMT_8,
+ src_x + cur_size, h, src_x + cur_size,
+ src_gpu_addr);
+
+ cp_set_surface_sync(dev_priv,
+ R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
+
+ /* dst */
+ set_render_target(dev_priv, COLOR_8,
+ dst_x + cur_size, h,
+ dst_gpu_addr);
+
+ /* scissors */
+ set_scissors(dev_priv, dst_x, 0, dst_x + cur_size, h);
+
+ /* Vertex buffer setup */
+ vb_addr = dev_priv->gart_buffers_offset +
+ dev_priv->blit_vb->offset +
+ dev_priv->blit_vb->used;
+ set_vtx_resource(dev_priv, vb_addr);
+
+ /* draw */
+ draw_auto(dev_priv);
+
+ cp_set_surface_sync(dev_priv,
+ R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
+ cur_size * h, dst_gpu_addr);
+
+ vb += 12;
+ dev_priv->blit_vb->used += 12 * 4;
+
+ src_gpu_addr += cur_size * h;
+ dst_gpu_addr += cur_size * h;
+ size_bytes -= cur_size * h;
+ }
+ } else {
+ max_bytes = 8192 * 4;
+
+ while (size_bytes) {
+ int cur_size = size_bytes;
+ int src_x = (src_gpu_addr & 255);
+ int dst_x = (dst_gpu_addr & 255);
+ int h = 1;
+ src_gpu_addr = src_gpu_addr & ~255;
+ dst_gpu_addr = dst_gpu_addr & ~255;
+
+ if (!src_x && !dst_x) {
+ h = (cur_size / max_bytes);
+ if (h > 8192)
+ h = 8192;
+ if (h == 0)
+ h = 1;
+ else
+ cur_size = max_bytes;
+ } else {
+ if (cur_size > max_bytes)
+ cur_size = max_bytes;
+ if (cur_size > (max_bytes - dst_x))
+ cur_size = (max_bytes - dst_x);
+ if (cur_size > (max_bytes - src_x))
+ cur_size = (max_bytes - src_x);
+ }
+
+ if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
+ r600_nomm_put_vb(dev);
+ r600_nomm_get_vb(dev);
+ if (!dev_priv->blit_vb)
+ return;
+
+ set_shaders(dev);
+ vb = r600_nomm_get_vb_ptr(dev);
+ }
+
+ vb[0] = i2f(dst_x / 4);
+ vb[1] = 0;
+ vb[2] = i2f(src_x / 4);
+ vb[3] = 0;
+
+ vb[4] = i2f(dst_x / 4);
+ vb[5] = i2f(h);
+ vb[6] = i2f(src_x / 4);
+ vb[7] = i2f(h);
+
+ vb[8] = i2f((dst_x + cur_size) / 4);
+ vb[9] = i2f(h);
+ vb[10] = i2f((src_x + cur_size) / 4);
+ vb[11] = i2f(h);
+
+ /* src */
+ set_tex_resource(dev_priv, FMT_8_8_8_8,
+ (src_x + cur_size) / 4,
+ h, (src_x + cur_size) / 4,
+ src_gpu_addr);
+
+ cp_set_surface_sync(dev_priv,
+ R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
+
+ /* dst */
+ set_render_target(dev_priv, COLOR_8_8_8_8,
+ dst_x + cur_size, h,
+ dst_gpu_addr);
+
+ /* scissors */
+ set_scissors(dev_priv, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
+
+ /* Vertex buffer setup */
+ vb_addr = dev_priv->gart_buffers_offset +
+ dev_priv->blit_vb->offset +
+ dev_priv->blit_vb->used;
+ set_vtx_resource(dev_priv, vb_addr);
+
+ /* draw */
+ draw_auto(dev_priv);
+
+ cp_set_surface_sync(dev_priv,
+ R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
+ cur_size * h, dst_gpu_addr);
+
+ vb += 12;
+ dev_priv->blit_vb->used += 12 * 4;
+
+ src_gpu_addr += cur_size * h;
+ dst_gpu_addr += cur_size * h;
+ size_bytes -= cur_size * h;
+ }
+ }
+}
+
+void
+r600_blit_swap(struct drm_device *dev,
+ uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
+ int sx, int sy, int dx, int dy,
+ int w, int h, int src_pitch, int dst_pitch, int cpp)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ int cb_format, tex_format;
+ u64 vb_addr;
+ u32 *vb;
+
+ vb = r600_nomm_get_vb_ptr(dev);
+
+ if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
+
+ r600_nomm_put_vb(dev);
+ r600_nomm_get_vb(dev);
+ if (!dev_priv->blit_vb)
+ return;
+
+ set_shaders(dev);
+ vb = r600_nomm_get_vb_ptr(dev);
+ }
+
+ if (cpp == 4) {
+ cb_format = COLOR_8_8_8_8;
+ tex_format = FMT_8_8_8_8;
+ } else if (cpp == 2) {
+ cb_format = COLOR_5_6_5;
+ tex_format = FMT_5_6_5;
+ } else {
+ cb_format = COLOR_8;
+ tex_format = FMT_8;
+ }
+
+ vb[0] = i2f(dx);
+ vb[1] = i2f(dy);
+ vb[2] = i2f(sx);
+ vb[3] = i2f(sy);
+
+ vb[4] = i2f(dx);
+ vb[5] = i2f(dy + h);
+ vb[6] = i2f(sx);
+ vb[7] = i2f(sy + h);
+
+ vb[8] = i2f(dx + w);
+ vb[9] = i2f(dy + h);
+ vb[10] = i2f(sx + w);
+ vb[11] = i2f(sy + h);
+
+ /* src */
+ set_tex_resource(dev_priv, tex_format,
+ src_pitch / cpp,
+ sy + h, src_pitch / cpp,
+ src_gpu_addr);
+
+ cp_set_surface_sync(dev_priv,
+ R600_TC_ACTION_ENA, (src_pitch * (sy + h)), src_gpu_addr);
+
+ /* dst */
+ set_render_target(dev_priv, cb_format,
+ dst_pitch / cpp, dy + h,
+ dst_gpu_addr);
+
+ /* scissors */
+ set_scissors(dev_priv, dx, dy, dx + w, dy + h);
+
+ /* Vertex buffer setup */
+ vb_addr = dev_priv->gart_buffers_offset +
+ dev_priv->blit_vb->offset +
+ dev_priv->blit_vb->used;
+ set_vtx_resource(dev_priv, vb_addr);
+
+ /* draw */
+ draw_auto(dev_priv);
+
+ cp_set_surface_sync(dev_priv,
+ R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
+ dst_pitch * (dy + h), dst_gpu_addr);
+
+ dev_priv->blit_vb->used += 12 * 4;
+}
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
new file mode 100644
index 0000000..0a6f468
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -0,0 +1,805 @@
+#include "drmP.h"
+#include "drm.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+
+#include "r600d.h"
+#include "r600_blit_shaders.h"
+
+#define DI_PT_RECTLIST 0x11
+#define DI_INDEX_SIZE_16_BIT 0x0
+#define DI_SRC_SEL_AUTO_INDEX 0x2
+
+#define FMT_8 0x1
+#define FMT_5_6_5 0x8
+#define FMT_8_8_8_8 0x1a
+#define COLOR_8 0x1
+#define COLOR_5_6_5 0x8
+#define COLOR_8_8_8_8 0x1a
+
+/* emits 21 on rv770+, 23 on r600 */
+static void
+set_render_target(struct radeon_device *rdev, int format,
+ int w, int h, u64 gpu_addr)
+{
+ u32 cb_color_info;
+ int pitch, slice;
+
+ h = (h + 7) & ~7;
+ if (h < 8)
+ h = 8;
+
+ cb_color_info = ((format << 2) | (1 << 27));
+ pitch = (w / 8) - 1;
+ slice = ((w * h) / 64) - 1;
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, gpu_addr >> 8);
+
+ if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
+ radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
+ radeon_ring_write(rdev, 2 << 0);
+ }
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, 0);
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, cb_color_info);
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, 0);
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, 0);
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, 0);
+}
+
+/* emits 5dw */
+static void
+cp_set_surface_sync(struct radeon_device *rdev,
+ u32 sync_type, u32 size,
+ u64 mc_addr)
+{
+ u32 cp_coher_size;
+
+ if (size == 0xffffffff)
+ cp_coher_size = 0xffffffff;
+ else
+ cp_coher_size = ((size + 255) >> 8);
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
+ radeon_ring_write(rdev, sync_type);
+ radeon_ring_write(rdev, cp_coher_size);
+ radeon_ring_write(rdev, mc_addr >> 8);
+ radeon_ring_write(rdev, 10); /* poll interval */
+}
+
+/* emits 21dw + 1 surface sync = 26dw */
+static void
+set_shaders(struct radeon_device *rdev)
+{
+ u64 gpu_addr;
+ u32 sq_pgm_resources;
+
+ /* setup shader regs */
+ sq_pgm_resources = (1 << 0);
+
+ /* VS */
+ gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, gpu_addr >> 8);
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, sq_pgm_resources);
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, 0);
+
+ /* PS */
+ gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, gpu_addr >> 8);
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, 2);
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+ radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, 0);
+
+ gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
+ cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
+}
+
+/* emits 9 + 1 sync (5) = 14*/
+static void
+set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
+{
+ u32 sq_vtx_constant_word2;
+
+ sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
+ radeon_ring_write(rdev, 0x460);
+ radeon_ring_write(rdev, gpu_addr & 0xffffffff);
+ radeon_ring_write(rdev, 48 - 1);
+ radeon_ring_write(rdev, sq_vtx_constant_word2);
+ radeon_ring_write(rdev, 1 << 0);
+ radeon_ring_write(rdev, 0);
+ radeon_ring_write(rdev, 0);
+ radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
+
+ if ((rdev->family == CHIP_RV610) ||
+ (rdev->family == CHIP_RV620) ||
+ (rdev->family == CHIP_RS780) ||
+ (rdev->family == CHIP_RS880) ||
+ (rdev->family == CHIP_RV710))
+ cp_set_surface_sync(rdev,
+ PACKET3_TC_ACTION_ENA, 48, gpu_addr);
+ else
+ cp_set_surface_sync(rdev,
+ PACKET3_VC_ACTION_ENA, 48, gpu_addr);
+}
+
+/* emits 9 */
+static void
+set_tex_resource(struct radeon_device *rdev,
+ int format, int w, int h, int pitch,
+ u64 gpu_addr)
+{
+ uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
+
+ if (h < 1)
+ h = 1;
+
+ sq_tex_resource_word0 = (1 << 0);
+ sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
+ ((w - 1) << 19));
+
+ sq_tex_resource_word1 = (format << 26);
+ sq_tex_resource_word1 |= ((h - 1) << 0);
+
+ sq_tex_resource_word4 = ((1 << 14) |
+ (0 << 16) |
+ (1 << 19) |
+ (2 << 22) |
+ (3 << 25));
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
+ radeon_ring_write(rdev, 0);
+ radeon_ring_write(rdev, sq_tex_resource_word0);
+ radeon_ring_write(rdev, sq_tex_resource_word1);
+ radeon_ring_write(rdev, gpu_addr >> 8);
+ radeon_ring_write(rdev, gpu_addr >> 8);
+ radeon_ring_write(rdev, sq_tex_resource_word4);
+ radeon_ring_write(rdev, 0);
+ radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
+}
+
+/* emits 12 */
+static void
+set_scissors(struct radeon_device *rdev, int x1, int y1,
+ int x2, int y2)
+{
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+ radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
+ radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+ radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
+ radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+ radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
+ radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
+}
+
+/* emits 10 */
+static void
+draw_auto(struct radeon_device *rdev)
+{
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+ radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, DI_PT_RECTLIST);
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
+ radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT);
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
+ radeon_ring_write(rdev, 1);
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
+ radeon_ring_write(rdev, 3);
+ radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
+
+}
+
+/* emits 14 */
+static void
+set_default_state(struct radeon_device *rdev)
+{
+ u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
+ u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
+ int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
+ int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
+ int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
+ u64 gpu_addr;
+ int dwords;
+
+ switch (rdev->family) {
+ case CHIP_R600:
+ num_ps_gprs = 192;
+ num_vs_gprs = 56;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 136;
+ num_vs_threads = 48;
+ num_gs_threads = 4;
+ num_es_threads = 4;
+ num_ps_stack_entries = 128;
+ num_vs_stack_entries = 128;
+ num_gs_stack_entries = 0;
+ num_es_stack_entries = 0;
+ break;
+ case CHIP_RV630:
+ case CHIP_RV635:
+ num_ps_gprs = 84;
+ num_vs_gprs = 36;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 144;
+ num_vs_threads = 40;
+ num_gs_threads = 4;
+ num_es_threads = 4;
+ num_ps_stack_entries = 40;
+ num_vs_stack_entries = 40;
+ num_gs_stack_entries = 32;
+ num_es_stack_entries = 16;
+ break;
+ case CHIP_RV610:
+ case CHIP_RV620:
+ case CHIP_RS780:
+ case CHIP_RS880:
+ default:
+ num_ps_gprs = 84;
+ num_vs_gprs = 36;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 136;
+ num_vs_threads = 48;
+ num_gs_threads = 4;
+ num_es_threads = 4;
+ num_ps_stack_entries = 40;
+ num_vs_stack_entries = 40;
+ num_gs_stack_entries = 32;
+ num_es_stack_entries = 16;
+ break;
+ case CHIP_RV670:
+ num_ps_gprs = 144;
+ num_vs_gprs = 40;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 136;
+ num_vs_threads = 48;
+ num_gs_threads = 4;
+ num_es_threads = 4;
+ num_ps_stack_entries = 40;
+ num_vs_stack_entries = 40;
+ num_gs_stack_entries = 32;
+ num_es_stack_entries = 16;
+ break;
+ case CHIP_RV770:
+ num_ps_gprs = 192;
+ num_vs_gprs = 56;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 188;
+ num_vs_threads = 60;
+ num_gs_threads = 0;
+ num_es_threads = 0;
+ num_ps_stack_entries = 256;
+ num_vs_stack_entries = 256;
+ num_gs_stack_entries = 0;
+ num_es_stack_entries = 0;
+ break;
+ case CHIP_RV730:
+ case CHIP_RV740:
+ num_ps_gprs = 84;
+ num_vs_gprs = 36;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 188;
+ num_vs_threads = 60;
+ num_gs_threads = 0;
+ num_es_threads = 0;
+ num_ps_stack_entries = 128;
+ num_vs_stack_entries = 128;
+ num_gs_stack_entries = 0;
+ num_es_stack_entries = 0;
+ break;
+ case CHIP_RV710:
+ num_ps_gprs = 192;
+ num_vs_gprs = 56;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 144;
+ num_vs_threads = 48;
+ num_gs_threads = 0;
+ num_es_threads = 0;
+ num_ps_stack_entries = 128;
+ num_vs_stack_entries = 128;
+ num_gs_stack_entries = 0;
+ num_es_stack_entries = 0;
+ break;
+ }
+
+ if ((rdev->family == CHIP_RV610) ||
+ (rdev->family == CHIP_RV620) ||
+ (rdev->family == CHIP_RS780) ||
+ (rdev->family == CHIP_RS780) ||
+ (rdev->family == CHIP_RV710))
+ sq_config = 0;
+ else
+ sq_config = VC_ENABLE;
+
+ sq_config |= (DX9_CONSTS |
+ ALU_INST_PREFER_VECTOR |
+ PS_PRIO(0) |
+ VS_PRIO(1) |
+ GS_PRIO(2) |
+ ES_PRIO(3));
+
+ sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
+ NUM_VS_GPRS(num_vs_gprs) |
+ NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
+ sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
+ NUM_ES_GPRS(num_es_gprs));
+ sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
+ NUM_VS_THREADS(num_vs_threads) |
+ NUM_GS_THREADS(num_gs_threads) |
+ NUM_ES_THREADS(num_es_threads));
+ sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
+ NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
+ sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
+ NUM_ES_STACK_ENTRIES(num_es_stack_entries));
+
+ /* emit an IB pointing at default state */
+ dwords = (rdev->r600_blit.state_len + 0xf) & ~0xf;
+ gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
+ radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
+ radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
+ radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
+ radeon_ring_write(rdev, dwords);
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
+ radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
+ /* SQ config */
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
+ radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, sq_config);
+ radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
+ radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
+ radeon_ring_write(rdev, sq_thread_resource_mgmt);
+ radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
+ radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
+}
+
+static inline uint32_t i2f(uint32_t input)
+{
+ u32 result, i, exponent, fraction;
+
+ if ((input & 0x3fff) == 0)
+ result = 0; /* 0 is a special case */
+ else {
+ exponent = 140; /* exponent biased by 127; */
+ fraction = (input & 0x3fff) << 10; /* cheat and only
+ handle numbers below 2^^15 */
+ for (i = 0; i < 14; i++) {
+ if (fraction & 0x800000)
+ break;
+ else {
+ fraction = fraction << 1; /* keep
+ shifting left until top bit = 1 */
+ exponent = exponent - 1;
+ }
+ }
+ result = exponent << 23 | (fraction & 0x7fffff); /* mask
+ off top bit; assumed 1 */
+ }
+ return result;
+}
+
+int r600_blit_init(struct radeon_device *rdev)
+{
+ u32 obj_size;
+ int r, dwords;
+ void *ptr;
+ u32 packet2s[16];
+ int num_packet2s = 0;
+
+ rdev->r600_blit.state_offset = 0;
+
+ if (rdev->family >= CHIP_RV770)
+ rdev->r600_blit.state_len = r7xx_default_size;
+ else
+ rdev->r600_blit.state_len = r6xx_default_size;
+
+ dwords = rdev->r600_blit.state_len;
+ while (dwords & 0xf) {
+ packet2s[num_packet2s++] = PACKET2(0);
+ dwords++;
+ }
+
+ obj_size = dwords * 4;
+ obj_size = ALIGN(obj_size, 256);
+
+ rdev->r600_blit.vs_offset = obj_size;
+ obj_size += r6xx_vs_size * 4;
+ obj_size = ALIGN(obj_size, 256);
+
+ rdev->r600_blit.ps_offset = obj_size;
+ obj_size += r6xx_ps_size * 4;
+ obj_size = ALIGN(obj_size, 256);
+
+ r = radeon_object_create(rdev, NULL, obj_size,
+ true, RADEON_GEM_DOMAIN_VRAM,
+ false, &rdev->r600_blit.shader_obj);
+ if (r) {
+ DRM_ERROR("r600 failed to allocate shader\n");
+ return r;
+ }
+
+ DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
+ obj_size,
+ rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
+
+ r = radeon_object_kmap(rdev->r600_blit.shader_obj, &ptr);
+ if (r) {
+ DRM_ERROR("failed to map blit object %d\n", r);
+ return r;
+ }
+
+ if (rdev->family >= CHIP_RV770)
+ memcpy_toio(ptr + rdev->r600_blit.state_offset,
+ r7xx_default_state, rdev->r600_blit.state_len * 4);
+ else
+ memcpy_toio(ptr + rdev->r600_blit.state_offset,
+ r6xx_default_state, rdev->r600_blit.state_len * 4);
+ if (num_packet2s)
+ memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
+ packet2s, num_packet2s * 4);
+
+
+ memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4);
+ memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4);
+
+ radeon_object_kunmap(rdev->r600_blit.shader_obj);
+ return 0;
+}
+
+void r600_blit_fini(struct radeon_device *rdev)
+{
+ radeon_object_unpin(rdev->r600_blit.shader_obj);
+ radeon_object_unref(&rdev->r600_blit.shader_obj);
+}
+
+int r600_vb_ib_get(struct radeon_device *rdev)
+{
+ int r;
+ r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
+ if (r) {
+ DRM_ERROR("failed to get IB for vertex buffer\n");
+ return r;
+ }
+
+ rdev->r600_blit.vb_total = 64*1024;
+ rdev->r600_blit.vb_used = 0;
+ return 0;
+}
+
+void r600_vb_ib_put(struct radeon_device *rdev)
+{
+ radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
+ mutex_lock(&rdev->ib_pool.mutex);
+ list_add_tail(&rdev->r600_blit.vb_ib->list, &rdev->ib_pool.scheduled_ibs);
+ mutex_unlock(&rdev->ib_pool.mutex);
+ radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
+}
+
+int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
+{
+ int r;
+ int ring_size, line_size;
+ int max_size;
+ /* loops of emits 64 + fence emit possible */
+ int dwords_per_loop = 76, num_loops;
+
+ r = r600_vb_ib_get(rdev);
+ WARN_ON(r);
+
+ /* set_render_target emits 2 extra dwords on rv6xx */
+ if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
+ dwords_per_loop += 2;
+
+ /* 8 bpp vs 32 bpp for xfer unit */
+ if (size_bytes & 3)
+ line_size = 8192;
+ else
+ line_size = 8192*4;
+
+ max_size = 8192 * line_size;
+
+ /* major loops cover the max size transfer */
+ num_loops = ((size_bytes + max_size) / max_size);
+ /* minor loops cover the extra non aligned bits */
+ num_loops += ((size_bytes % line_size) ? 1 : 0);
+ /* calculate number of loops correctly */
+ ring_size = num_loops * dwords_per_loop;
+ /* set default + shaders */
+ ring_size += 40; /* shaders + def state */
+ ring_size += 3; /* fence emit for VB IB */
+ ring_size += 5; /* done copy */
+ ring_size += 3; /* fence emit for done copy */
+ r = radeon_ring_lock(rdev, ring_size);
+ WARN_ON(r);
+
+ set_default_state(rdev); /* 14 */
+ set_shaders(rdev); /* 26 */
+ return 0;
+}
+
+void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
+{
+ int r;
+
+ radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
+ radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
+ /* wait for 3D idle clean */
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+ radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+ radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
+
+ if (rdev->r600_blit.vb_ib)
+ r600_vb_ib_put(rdev);
+
+ if (fence)
+ r = radeon_fence_emit(rdev, fence);
+
+ radeon_ring_unlock_commit(rdev);
+}
+
+void r600_kms_blit_copy(struct radeon_device *rdev,
+ u64 src_gpu_addr, u64 dst_gpu_addr,
+ int size_bytes)
+{
+ int max_bytes;
+ u64 vb_gpu_addr;
+ u32 *vb;
+
+ DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
+ size_bytes, rdev->r600_blit.vb_used);
+ vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
+ if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
+ max_bytes = 8192;
+
+ while (size_bytes) {
+ int cur_size = size_bytes;
+ int src_x = src_gpu_addr & 255;
+ int dst_x = dst_gpu_addr & 255;
+ int h = 1;
+ src_gpu_addr = src_gpu_addr & ~255;
+ dst_gpu_addr = dst_gpu_addr & ~255;
+
+ if (!src_x && !dst_x) {
+ h = (cur_size / max_bytes);
+ if (h > 8192)
+ h = 8192;
+ if (h == 0)
+ h = 1;
+ else
+ cur_size = max_bytes;
+ } else {
+ if (cur_size > max_bytes)
+ cur_size = max_bytes;
+ if (cur_size > (max_bytes - dst_x))
+ cur_size = (max_bytes - dst_x);
+ if (cur_size > (max_bytes - src_x))
+ cur_size = (max_bytes - src_x);
+ }
+
+ if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
+ WARN_ON(1);
+
+#if 0
+ r600_vb_ib_put(rdev);
+
+ r600_nomm_put_vb(dev);
+ r600_nomm_get_vb(dev);
+ if (!dev_priv->blit_vb)
+ return;
+ set_shaders(dev);
+ vb = r600_nomm_get_vb_ptr(dev);
+#endif
+ }
+
+ vb[0] = i2f(dst_x);
+ vb[1] = 0;
+ vb[2] = i2f(src_x);
+ vb[3] = 0;
+
+ vb[4] = i2f(dst_x);
+ vb[5] = i2f(h);
+ vb[6] = i2f(src_x);
+ vb[7] = i2f(h);
+
+ vb[8] = i2f(dst_x + cur_size);
+ vb[9] = i2f(h);
+ vb[10] = i2f(src_x + cur_size);
+ vb[11] = i2f(h);
+
+ /* src 9 */
+ set_tex_resource(rdev, FMT_8,
+ src_x + cur_size, h, src_x + cur_size,
+ src_gpu_addr);
+
+ /* 5 */
+ cp_set_surface_sync(rdev,
+ PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
+
+ /* dst 23 */
+ set_render_target(rdev, COLOR_8,
+ dst_x + cur_size, h,
+ dst_gpu_addr);
+
+ /* scissors 12 */
+ set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
+
+ /* 14 */
+ vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
+ set_vtx_resource(rdev, vb_gpu_addr);
+
+ /* draw 10 */
+ draw_auto(rdev);
+
+ /* 5 */
+ cp_set_surface_sync(rdev,
+ PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
+ cur_size * h, dst_gpu_addr);
+
+ vb += 12;
+ rdev->r600_blit.vb_used += 12 * 4;
+
+ src_gpu_addr += cur_size * h;
+ dst_gpu_addr += cur_size * h;
+ size_bytes -= cur_size * h;
+ }
+ } else {
+ max_bytes = 8192 * 4;
+
+ while (size_bytes) {
+ int cur_size = size_bytes;
+ int src_x = (src_gpu_addr & 255);
+ int dst_x = (dst_gpu_addr & 255);
+ int h = 1;
+ src_gpu_addr = src_gpu_addr & ~255;
+ dst_gpu_addr = dst_gpu_addr & ~255;
+
+ if (!src_x && !dst_x) {
+ h = (cur_size / max_bytes);
+ if (h > 8192)
+ h = 8192;
+ if (h == 0)
+ h = 1;
+ else
+ cur_size = max_bytes;
+ } else {
+ if (cur_size > max_bytes)
+ cur_size = max_bytes;
+ if (cur_size > (max_bytes - dst_x))
+ cur_size = (max_bytes - dst_x);
+ if (cur_size > (max_bytes - src_x))
+ cur_size = (max_bytes - src_x);
+ }
+
+ if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
+ WARN_ON(1);
+ }
+#if 0
+ if ((rdev->blit_vb->used + 48) > rdev->blit_vb->total) {
+ r600_nomm_put_vb(dev);
+ r600_nomm_get_vb(dev);
+ if (!rdev->blit_vb)
+ return;
+
+ set_shaders(dev);
+ vb = r600_nomm_get_vb_ptr(dev);
+ }
+#endif
+
+ vb[0] = i2f(dst_x / 4);
+ vb[1] = 0;
+ vb[2] = i2f(src_x / 4);
+ vb[3] = 0;
+
+ vb[4] = i2f(dst_x / 4);
+ vb[5] = i2f(h);
+ vb[6] = i2f(src_x / 4);
+ vb[7] = i2f(h);
+
+ vb[8] = i2f((dst_x + cur_size) / 4);
+ vb[9] = i2f(h);
+ vb[10] = i2f((src_x + cur_size) / 4);
+ vb[11] = i2f(h);
+
+ /* src 9 */
+ set_tex_resource(rdev, FMT_8_8_8_8,
+ (src_x + cur_size) / 4,
+ h, (src_x + cur_size) / 4,
+ src_gpu_addr);
+ /* 5 */
+ cp_set_surface_sync(rdev,
+ PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
+
+ /* dst 23 */
+ set_render_target(rdev, COLOR_8_8_8_8,
+ dst_x + cur_size, h,
+ dst_gpu_addr);
+
+ /* scissors 12 */
+ set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
+
+ /* Vertex buffer setup 14 */
+ vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
+ set_vtx_resource(rdev, vb_gpu_addr);
+
+ /* draw 10 */
+ draw_auto(rdev);
+
+ /* 5 */
+ cp_set_surface_sync(rdev,
+ PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
+ cur_size * h, dst_gpu_addr);
+
+ /* 78 ring dwords per loop */
+ vb += 12;
+ rdev->r600_blit.vb_used += 12 * 4;
+
+ src_gpu_addr += cur_size * h;
+ dst_gpu_addr += cur_size * h;
+ size_bytes -= cur_size * h;
+ }
+ }
+}
+
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c
new file mode 100644
index 0000000..d745e81
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c
@@ -0,0 +1,1072 @@
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+const u32 r6xx_default_state[] =
+{
+ 0xc0002400,
+ 0x00000000,
+ 0xc0012800,
+ 0x80000000,
+ 0x80000000,
+ 0xc0004600,
+ 0x00000016,
+ 0xc0016800,
+ 0x00000010,
+ 0x00028000,
+ 0xc0016800,
+ 0x00000010,
+ 0x00008000,
+ 0xc0016800,
+ 0x00000542,
+ 0x07000003,
+ 0xc0016800,
+ 0x000005c5,
+ 0x00000000,
+ 0xc0016800,
+ 0x00000363,
+ 0x00000000,
+ 0xc0016800,
+ 0x0000060c,
+ 0x82000000,
+ 0xc0016800,
+ 0x0000060e,
+ 0x01020204,
+ 0xc0016f00,
+ 0x00000000,
+ 0x00000000,
+ 0xc0016f00,
+ 0x00000001,
+ 0x00000000,
+ 0xc0096900,
+ 0x0000022a,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000004,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000000a,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000000b,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000010c,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000010d,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000200,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000343,
+ 0x00000060,
+ 0xc0016900,
+ 0x00000344,
+ 0x00000040,
+ 0xc0016900,
+ 0x00000351,
+ 0x0000aa00,
+ 0xc0016900,
+ 0x00000104,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000010e,
+ 0x00000000,
+ 0xc0046900,
+ 0x00000105,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0xc0036900,
+ 0x00000109,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0xc0046900,
+ 0x0000030c,
+ 0x01000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0xc0046900,
+ 0x00000048,
+ 0x3f800000,
+ 0x00000000,
+ 0x3f800000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x0000008e,
+ 0x0000000f,
+ 0xc0016900,
+ 0x00000080,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000083,
+ 0x0000ffff,
+ 0xc0016900,
+ 0x00000084,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000085,
+ 0x20002000,
+ 0xc0016900,
+ 0x00000086,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000087,
+ 0x20002000,
+ 0xc0016900,
+ 0x00000088,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000089,
+ 0x20002000,
+ 0xc0016900,
+ 0x0000008a,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000008b,
+ 0x20002000,
+ 0xc0016900,
+ 0x0000008c,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000094,
+ 0x80000000,
+ 0xc0016900,
+ 0x00000095,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000b4,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x00000096,
+ 0x80000000,
+ 0xc0016900,
+ 0x00000097,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000b6,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x00000098,
+ 0x80000000,
+ 0xc0016900,
+ 0x00000099,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000b8,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x0000009a,
+ 0x80000000,
+ 0xc0016900,
+ 0x0000009b,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000ba,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x0000009c,
+ 0x80000000,
+ 0xc0016900,
+ 0x0000009d,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000bc,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x0000009e,
+ 0x80000000,
+ 0xc0016900,
+ 0x0000009f,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000be,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000a0,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000a1,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000c0,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000a2,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000a3,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000c2,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000a4,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000a5,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000c4,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000a6,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000a7,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000c6,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000a8,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000a9,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000c8,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000aa,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000ab,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000ca,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000ac,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000ad,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000cc,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000ae,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000af,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000ce,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000b0,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000b1,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000d0,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000b2,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000b3,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000d2,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x00000293,
+ 0x00004010,
+ 0xc0016900,
+ 0x00000300,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000301,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000312,
+ 0xffffffff,
+ 0xc0016900,
+ 0x00000307,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000308,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000283,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000292,
+ 0x00000000,
+ 0xc0066900,
+ 0x0000010f,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000206,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000207,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000208,
+ 0x00000000,
+ 0xc0046900,
+ 0x00000303,
+ 0x3f800000,
+ 0x3f800000,
+ 0x3f800000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x00000205,
+ 0x00000004,
+ 0xc0016900,
+ 0x00000280,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000281,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000037e,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000382,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000380,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000383,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000381,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000282,
+ 0x00000008,
+ 0xc0016900,
+ 0x00000302,
+ 0x0000002d,
+ 0xc0016900,
+ 0x0000037f,
+ 0x00000000,
+ 0xc0016900,
+ 0x000001b2,
+ 0x00000000,
+ 0xc0016900,
+ 0x000001b6,
+ 0x00000000,
+ 0xc0016900,
+ 0x000001b7,
+ 0x00000000,
+ 0xc0016900,
+ 0x000001b8,
+ 0x00000000,
+ 0xc0016900,
+ 0x000001b9,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000225,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000229,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000237,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000100,
+ 0x00000800,
+ 0xc0016900,
+ 0x00000101,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000102,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002a8,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002a9,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000103,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000284,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000290,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000285,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000286,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000287,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000288,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000289,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000028a,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000028b,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000028c,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000028d,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000028e,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000028f,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002a1,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002a5,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002ac,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002ad,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002ae,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002c8,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000206,
+ 0x00000100,
+ 0xc0016900,
+ 0x00000204,
+ 0x00010000,
+ 0xc0036e00,
+ 0x00000000,
+ 0x00000012,
+ 0x00000000,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000008f,
+ 0x0000000f,
+ 0xc0016900,
+ 0x000001e8,
+ 0x00000001,
+ 0xc0016900,
+ 0x00000202,
+ 0x00cc0000,
+ 0xc0016900,
+ 0x00000205,
+ 0x00000244,
+ 0xc0016900,
+ 0x00000203,
+ 0x00000210,
+ 0xc0016900,
+ 0x000001b1,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000185,
+ 0x00000000,
+ 0xc0016900,
+ 0x000001b3,
+ 0x00000001,
+ 0xc0016900,
+ 0x000001b4,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000191,
+ 0x00000b00,
+ 0xc0016900,
+ 0x000001b5,
+ 0x00000000,
+};
+
+const u32 r7xx_default_state[] =
+{
+ 0xc0012800,
+ 0x80000000,
+ 0x80000000,
+ 0xc0004600,
+ 0x00000016,
+ 0xc0016800,
+ 0x00000010,
+ 0x00028000,
+ 0xc0016800,
+ 0x00000010,
+ 0x00008000,
+ 0xc0016800,
+ 0x00000542,
+ 0x07000002,
+ 0xc0016800,
+ 0x000005c5,
+ 0x00000000,
+ 0xc0016800,
+ 0x00000363,
+ 0x00004000,
+ 0xc0016800,
+ 0x0000060c,
+ 0x00000000,
+ 0xc0016800,
+ 0x0000060e,
+ 0x00420204,
+ 0xc0016f00,
+ 0x00000000,
+ 0x00000000,
+ 0xc0016f00,
+ 0x00000001,
+ 0x00000000,
+ 0xc0096900,
+ 0x0000022a,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000004,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000000a,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000000b,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000010c,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000010d,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000200,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000343,
+ 0x00000060,
+ 0xc0016900,
+ 0x00000344,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000351,
+ 0x0000aa00,
+ 0xc0016900,
+ 0x00000104,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000010e,
+ 0x00000000,
+ 0xc0046900,
+ 0x00000105,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0xc0046900,
+ 0x0000030c,
+ 0x01000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000008e,
+ 0x0000000f,
+ 0xc0016900,
+ 0x00000080,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000083,
+ 0x0000ffff,
+ 0xc0016900,
+ 0x00000084,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000085,
+ 0x20002000,
+ 0xc0016900,
+ 0x00000086,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000087,
+ 0x20002000,
+ 0xc0016900,
+ 0x00000088,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000089,
+ 0x20002000,
+ 0xc0016900,
+ 0x0000008a,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000008b,
+ 0x20002000,
+ 0xc0016900,
+ 0x0000008c,
+ 0xaaaaaaaa,
+ 0xc0016900,
+ 0x00000094,
+ 0x80000000,
+ 0xc0016900,
+ 0x00000095,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000b4,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x00000096,
+ 0x80000000,
+ 0xc0016900,
+ 0x00000097,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000b6,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x00000098,
+ 0x80000000,
+ 0xc0016900,
+ 0x00000099,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000b8,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x0000009a,
+ 0x80000000,
+ 0xc0016900,
+ 0x0000009b,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000ba,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x0000009c,
+ 0x80000000,
+ 0xc0016900,
+ 0x0000009d,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000bc,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x0000009e,
+ 0x80000000,
+ 0xc0016900,
+ 0x0000009f,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000be,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000a0,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000a1,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000c0,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000a2,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000a3,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000c2,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000a4,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000a5,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000c4,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000a6,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000a7,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000c6,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000a8,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000a9,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000c8,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000aa,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000ab,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000ca,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000ac,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000ad,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000cc,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000ae,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000af,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000ce,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000b0,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000b1,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000d0,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x000000b2,
+ 0x80000000,
+ 0xc0016900,
+ 0x000000b3,
+ 0x20002000,
+ 0xc0026900,
+ 0x000000d2,
+ 0x00000000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x00000293,
+ 0x00514000,
+ 0xc0016900,
+ 0x00000300,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000301,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000312,
+ 0xffffffff,
+ 0xc0016900,
+ 0x00000307,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000308,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000283,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000292,
+ 0x00000000,
+ 0xc0066900,
+ 0x0000010f,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000206,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000207,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000208,
+ 0x00000000,
+ 0xc0046900,
+ 0x00000303,
+ 0x3f800000,
+ 0x3f800000,
+ 0x3f800000,
+ 0x3f800000,
+ 0xc0016900,
+ 0x00000205,
+ 0x00000004,
+ 0xc0016900,
+ 0x00000280,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000281,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000037e,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000382,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000380,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000383,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000381,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000282,
+ 0x00000008,
+ 0xc0016900,
+ 0x00000302,
+ 0x0000002d,
+ 0xc0016900,
+ 0x0000037f,
+ 0x00000000,
+ 0xc0016900,
+ 0x000001b2,
+ 0x00000001,
+ 0xc0016900,
+ 0x000001b6,
+ 0x00000000,
+ 0xc0016900,
+ 0x000001b7,
+ 0x00000000,
+ 0xc0016900,
+ 0x000001b8,
+ 0x00000000,
+ 0xc0016900,
+ 0x000001b9,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000225,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000229,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000237,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000100,
+ 0x00000800,
+ 0xc0016900,
+ 0x00000101,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000102,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002a8,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002a9,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000103,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000284,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000290,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000285,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000286,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000287,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000288,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000289,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000028a,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000028b,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000028c,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000028d,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000028e,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000028f,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002a1,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002a5,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002ac,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002ad,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002ae,
+ 0x00000000,
+ 0xc0016900,
+ 0x000002c8,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000206,
+ 0x00000100,
+ 0xc0016900,
+ 0x00000204,
+ 0x00010000,
+ 0xc0036e00,
+ 0x00000000,
+ 0x00000012,
+ 0x00000000,
+ 0x00000000,
+ 0xc0016900,
+ 0x0000008f,
+ 0x0000000f,
+ 0xc0016900,
+ 0x000001e8,
+ 0x00000001,
+ 0xc0016900,
+ 0x00000202,
+ 0x00cc0000,
+ 0xc0016900,
+ 0x00000205,
+ 0x00000244,
+ 0xc0016900,
+ 0x00000203,
+ 0x00000210,
+ 0xc0016900,
+ 0x000001b1,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000185,
+ 0x00000000,
+ 0xc0016900,
+ 0x000001b3,
+ 0x00000001,
+ 0xc0016900,
+ 0x000001b4,
+ 0x00000000,
+ 0xc0016900,
+ 0x00000191,
+ 0x00000b00,
+ 0xc0016900,
+ 0x000001b5,
+ 0x00000000,
+};
+
+/* same for r6xx/r7xx */
+const u32 r6xx_vs[] =
+{
+ 0x00000004,
+ 0x81000000,
+ 0x0000203c,
+ 0x94000b08,
+ 0x00004000,
+ 0x14200b1a,
+ 0x00000000,
+ 0x00000000,
+ 0x3c000000,
+ 0x68cd1000,
+ 0x00080000,
+ 0x00000000,
+};
+
+const u32 r6xx_ps[] =
+{
+ 0x00000002,
+ 0x80800000,
+ 0x00000000,
+ 0x94200688,
+ 0x00000010,
+ 0x000d1000,
+ 0xb0800000,
+ 0x00000000,
+};
+
+const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);
+const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);
+const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
+const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.h b/drivers/gpu/drm/radeon/r600_blit_shaders.h
new file mode 100644
index 0000000..fdc3b37
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.h
@@ -0,0 +1,14 @@
+
+#ifndef R600_BLIT_SHADERS_H
+#define R600_BLIT_SHADERS_H
+
+extern const u32 r6xx_ps[];
+extern const u32 r6xx_vs[];
+extern const u32 r7xx_default_state[];
+extern const u32 r6xx_default_state[];
+
+
+extern const u32 r6xx_ps_size, r6xx_vs_size;
+extern const u32 r6xx_default_size, r7xx_default_size;
+
+#endif
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 20f1790..6d5a711 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -31,7 +31,38 @@
#include "radeon_drm.h"
#include "radeon_drv.h"
-#include "r600_microcode.h"
+#define PFP_UCODE_SIZE 576
+#define PM4_UCODE_SIZE 1792
+#define R700_PFP_UCODE_SIZE 848
+#define R700_PM4_UCODE_SIZE 1360
+
+/* Firmware Names */
+MODULE_FIRMWARE("radeon/R600_pfp.bin");
+MODULE_FIRMWARE("radeon/R600_me.bin");
+MODULE_FIRMWARE("radeon/RV610_pfp.bin");
+MODULE_FIRMWARE("radeon/RV610_me.bin");
+MODULE_FIRMWARE("radeon/RV630_pfp.bin");
+MODULE_FIRMWARE("radeon/RV630_me.bin");
+MODULE_FIRMWARE("radeon/RV620_pfp.bin");
+MODULE_FIRMWARE("radeon/RV620_me.bin");
+MODULE_FIRMWARE("radeon/RV635_pfp.bin");
+MODULE_FIRMWARE("radeon/RV635_me.bin");
+MODULE_FIRMWARE("radeon/RV670_pfp.bin");
+MODULE_FIRMWARE("radeon/RV670_me.bin");
+MODULE_FIRMWARE("radeon/RS780_pfp.bin");
+MODULE_FIRMWARE("radeon/RS780_me.bin");
+MODULE_FIRMWARE("radeon/RV770_pfp.bin");
+MODULE_FIRMWARE("radeon/RV770_me.bin");
+MODULE_FIRMWARE("radeon/RV730_pfp.bin");
+MODULE_FIRMWARE("radeon/RV730_me.bin");
+MODULE_FIRMWARE("radeon/RV710_pfp.bin");
+MODULE_FIRMWARE("radeon/RV710_me.bin");
+
+
+int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
+ unsigned family, u32 *ib, int *l);
+void r600_cs_legacy_init(void);
+
# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
@@ -275,11 +306,93 @@ static void r600_vm_init(struct drm_device *dev)
r600_vm_flush_gart_range(dev);
}
-/* load r600 microcode */
+static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
+{
+ struct platform_device *pdev;
+ const char *chip_name;
+ size_t pfp_req_size, me_req_size;
+ char fw_name[30];
+ int err;
+
+ pdev = platform_device_register_simple("r600_cp", 0, NULL, 0);
+ err = IS_ERR(pdev);
+ if (err) {
+ printk(KERN_ERR "r600_cp: Failed to register firmware\n");
+ return -EINVAL;
+ }
+
+ switch (dev_priv->flags & RADEON_FAMILY_MASK) {
+ case CHIP_R600: chip_name = "R600"; break;
+ case CHIP_RV610: chip_name = "RV610"; break;
+ case CHIP_RV630: chip_name = "RV630"; break;
+ case CHIP_RV620: chip_name = "RV620"; break;
+ case CHIP_RV635: chip_name = "RV635"; break;
+ case CHIP_RV670: chip_name = "RV670"; break;
+ case CHIP_RS780:
+ case CHIP_RS880: chip_name = "RS780"; break;
+ case CHIP_RV770: chip_name = "RV770"; break;
+ case CHIP_RV730:
+ case CHIP_RV740: chip_name = "RV730"; break;
+ case CHIP_RV710: chip_name = "RV710"; break;
+ default: BUG();
+ }
+
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
+ pfp_req_size = R700_PFP_UCODE_SIZE * 4;
+ me_req_size = R700_PM4_UCODE_SIZE * 4;
+ } else {
+ pfp_req_size = PFP_UCODE_SIZE * 4;
+ me_req_size = PM4_UCODE_SIZE * 12;
+ }
+
+ DRM_INFO("Loading %s CP Microcode\n", chip_name);
+
+ snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
+ err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev);
+ if (err)
+ goto out;
+ if (dev_priv->pfp_fw->size != pfp_req_size) {
+ printk(KERN_ERR
+ "r600_cp: Bogus length %zu in firmware \"%s\"\n",
+ dev_priv->pfp_fw->size, fw_name);
+ err = -EINVAL;
+ goto out;
+ }
+
+ snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
+ err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
+ if (err)
+ goto out;
+ if (dev_priv->me_fw->size != me_req_size) {
+ printk(KERN_ERR
+ "r600_cp: Bogus length %zu in firmware \"%s\"\n",
+ dev_priv->me_fw->size, fw_name);
+ err = -EINVAL;
+ }
+out:
+ platform_device_unregister(pdev);
+
+ if (err) {
+ if (err != -EINVAL)
+ printk(KERN_ERR
+ "r600_cp: Failed to load firmware \"%s\"\n",
+ fw_name);
+ release_firmware(dev_priv->pfp_fw);
+ dev_priv->pfp_fw = NULL;
+ release_firmware(dev_priv->me_fw);
+ dev_priv->me_fw = NULL;
+ }
+ return err;
+}
+
static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
{
+ const __be32 *fw_data;
int i;
+ if (!dev_priv->me_fw || !dev_priv->pfp_fw)
+ return;
+
r600_do_cp_stop(dev_priv);
RADEON_WRITE(R600_CP_RB_CNTL,
@@ -292,115 +405,18 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
DRM_UDELAY(15000);
RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
+ fw_data = (const __be32 *)dev_priv->me_fw->data;
RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+ for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
+ RADEON_WRITE(R600_CP_ME_RAM_DATA,
+ be32_to_cpup(fw_data++));
- if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) {
- DRM_INFO("Loading R600 CP Microcode\n");
- for (i = 0; i < PM4_UCODE_SIZE; i++) {
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- R600_cp_microcode[i][0]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- R600_cp_microcode[i][1]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- R600_cp_microcode[i][2]);
- }
-
- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
- DRM_INFO("Loading R600 PFP Microcode\n");
- for (i = 0; i < PFP_UCODE_SIZE; i++)
- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]);
- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) {
- DRM_INFO("Loading RV610 CP Microcode\n");
- for (i = 0; i < PM4_UCODE_SIZE; i++) {
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV610_cp_microcode[i][0]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV610_cp_microcode[i][1]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV610_cp_microcode[i][2]);
- }
-
- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
- DRM_INFO("Loading RV610 PFP Microcode\n");
- for (i = 0; i < PFP_UCODE_SIZE; i++)
- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]);
- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
- DRM_INFO("Loading RV630 CP Microcode\n");
- for (i = 0; i < PM4_UCODE_SIZE; i++) {
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV630_cp_microcode[i][0]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV630_cp_microcode[i][1]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV630_cp_microcode[i][2]);
- }
-
- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
- DRM_INFO("Loading RV630 PFP Microcode\n");
- for (i = 0; i < PFP_UCODE_SIZE; i++)
- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]);
- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) {
- DRM_INFO("Loading RV620 CP Microcode\n");
- for (i = 0; i < PM4_UCODE_SIZE; i++) {
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV620_cp_microcode[i][0]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV620_cp_microcode[i][1]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV620_cp_microcode[i][2]);
- }
-
- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
- DRM_INFO("Loading RV620 PFP Microcode\n");
- for (i = 0; i < PFP_UCODE_SIZE; i++)
- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]);
- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
- DRM_INFO("Loading RV635 CP Microcode\n");
- for (i = 0; i < PM4_UCODE_SIZE; i++) {
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV635_cp_microcode[i][0]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV635_cp_microcode[i][1]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV635_cp_microcode[i][2]);
- }
-
- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
- DRM_INFO("Loading RV635 PFP Microcode\n");
- for (i = 0; i < PFP_UCODE_SIZE; i++)
- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]);
- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) {
- DRM_INFO("Loading RV670 CP Microcode\n");
- for (i = 0; i < PM4_UCODE_SIZE; i++) {
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV670_cp_microcode[i][0]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV670_cp_microcode[i][1]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RV670_cp_microcode[i][2]);
- }
-
- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
- DRM_INFO("Loading RV670 PFP Microcode\n");
- for (i = 0; i < PFP_UCODE_SIZE; i++)
- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);
- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
- ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
- DRM_INFO("Loading RS780/RS880 CP Microcode\n");
- for (i = 0; i < PM4_UCODE_SIZE; i++) {
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RS780_cp_microcode[i][0]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RS780_cp_microcode[i][1]);
- RADEON_WRITE(R600_CP_ME_RAM_DATA,
- RS780_cp_microcode[i][2]);
- }
+ fw_data = (const __be32 *)dev_priv->pfp_fw->data;
+ RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+ for (i = 0; i < PFP_UCODE_SIZE; i++)
+ RADEON_WRITE(R600_CP_PFP_UCODE_DATA,
+ be32_to_cpup(fw_data++));
- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
- DRM_INFO("Loading RS780/RS880 PFP Microcode\n");
- for (i = 0; i < PFP_UCODE_SIZE; i++)
- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]);
- }
RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
@@ -459,11 +475,14 @@ static void r700_vm_init(struct drm_device *dev)
r600_vm_flush_gart_range(dev);
}
-/* load r600 microcode */
static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
{
+ const __be32 *fw_data;
int i;
+ if (!dev_priv->me_fw || !dev_priv->pfp_fw)
+ return;
+
r600_do_cp_stop(dev_priv);
RADEON_WRITE(R600_CP_RB_CNTL,
@@ -476,48 +495,18 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
DRM_UDELAY(15000);
RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
+ fw_data = (const __be32 *)dev_priv->pfp_fw->data;
+ RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+ for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
+ RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
+ RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
- if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) {
- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
- DRM_INFO("Loading RV770/RV790 PFP Microcode\n");
- for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]);
- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-
- RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
- DRM_INFO("Loading RV770/RV790 CP Microcode\n");
- for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
- RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]);
- RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
-
- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730) ||
- ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)) {
- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
- DRM_INFO("Loading RV730/RV740 PFP Microcode\n");
- for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]);
- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-
- RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
- DRM_INFO("Loading RV730/RV740 CP Microcode\n");
- for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
- RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]);
- RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
-
- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) {
- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
- DRM_INFO("Loading RV710 PFP Microcode\n");
- for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]);
- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-
- RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
- DRM_INFO("Loading RV710 CP Microcode\n");
- for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
- RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]);
- RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+ fw_data = (const __be32 *)dev_priv->me_fw->data;
+ RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+ for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
+ RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
+ RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
- }
RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
@@ -1874,6 +1863,8 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
DRM_DEBUG("\n");
+ mutex_init(&dev_priv->cs_mutex);
+ r600_cs_legacy_init();
/* if we require new memory map but we don't have it fail */
if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
@@ -1905,7 +1896,7 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
/* Enable vblank on CRTC1 for older X servers
*/
dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
-
+ dev_priv->do_boxes = 0;
dev_priv->cp_mode = init->cp_mode;
/* We don't support anything other than bus-mastering ring mode,
@@ -1991,11 +1982,11 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
} else
#endif
{
- dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
+ dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset;
dev_priv->ring_rptr->handle =
- (void *)dev_priv->ring_rptr->offset;
+ (void *)(unsigned long)dev_priv->ring_rptr->offset;
dev->agp_buffer_map->handle =
- (void *)dev->agp_buffer_map->offset;
+ (void *)(unsigned long)dev->agp_buffer_map->offset;
DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
dev_priv->cp_ring->handle);
@@ -2147,6 +2138,14 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
r600_vm_init(dev);
}
+ if (!dev_priv->me_fw || !dev_priv->pfp_fw) {
+ int err = r600_cp_init_microcode(dev_priv);
+ if (err) {
+ DRM_ERROR("Failed to load firmware!\n");
+ r600_do_cleanup_cp(dev);
+ return err;
+ }
+ }
if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
r700_cp_load_microcode(dev_priv);
else
@@ -2291,3 +2290,239 @@ int r600_cp_dispatch_indirect(struct drm_device *dev,
return 0;
}
+
+void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ struct drm_master *master = file_priv->master;
+ struct drm_radeon_master_private *master_priv = master->driver_priv;
+ drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
+ int nbox = sarea_priv->nbox;
+ struct drm_clip_rect *pbox = sarea_priv->boxes;
+ int i, cpp, src_pitch, dst_pitch;
+ uint64_t src, dst;
+ RING_LOCALS;
+ DRM_DEBUG("\n");
+
+ if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
+ cpp = 4;
+ else
+ cpp = 2;
+
+ if (sarea_priv->pfCurrentPage == 0) {
+ src_pitch = dev_priv->back_pitch;
+ dst_pitch = dev_priv->front_pitch;
+ src = dev_priv->back_offset + dev_priv->fb_location;
+ dst = dev_priv->front_offset + dev_priv->fb_location;
+ } else {
+ src_pitch = dev_priv->front_pitch;
+ dst_pitch = dev_priv->back_pitch;
+ src = dev_priv->front_offset + dev_priv->fb_location;
+ dst = dev_priv->back_offset + dev_priv->fb_location;
+ }
+
+ if (r600_prepare_blit_copy(dev, file_priv)) {
+ DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
+ return;
+ }
+ for (i = 0; i < nbox; i++) {
+ int x = pbox[i].x1;
+ int y = pbox[i].y1;
+ int w = pbox[i].x2 - x;
+ int h = pbox[i].y2 - y;
+
+ DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
+
+ r600_blit_swap(dev,
+ src, dst,
+ x, y, x, y, w, h,
+ src_pitch, dst_pitch, cpp);
+ }
+ r600_done_blit_copy(dev);
+
+ /* Increment the frame counter. The client-side 3D driver must
+ * throttle the framerate by waiting for this value before
+ * performing the swapbuffer ioctl.
+ */
+ sarea_priv->last_frame++;
+
+ BEGIN_RING(3);
+ R600_FRAME_AGE(sarea_priv->last_frame);
+ ADVANCE_RING();
+}
+
+int r600_cp_dispatch_texture(struct drm_device *dev,
+ struct drm_file *file_priv,
+ drm_radeon_texture_t *tex,
+ drm_radeon_tex_image_t *image)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ struct drm_buf *buf;
+ u32 *buffer;
+ const u8 __user *data;
+ int size, pass_size;
+ u64 src_offset, dst_offset;
+
+ if (!radeon_check_offset(dev_priv, tex->offset)) {
+ DRM_ERROR("Invalid destination offset\n");
+ return -EINVAL;
+ }
+
+ /* this might fail for zero-sized uploads - are those illegal? */
+ if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
+ DRM_ERROR("Invalid final destination offset\n");
+ return -EINVAL;
+ }
+
+ size = tex->height * tex->pitch;
+
+ if (size == 0)
+ return 0;
+
+ dst_offset = tex->offset;
+
+ if (r600_prepare_blit_copy(dev, file_priv)) {
+ DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
+ return -EAGAIN;
+ }
+ do {
+ data = (const u8 __user *)image->data;
+ pass_size = size;
+
+ buf = radeon_freelist_get(dev);
+ if (!buf) {
+ DRM_DEBUG("EAGAIN\n");
+ if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
+ return -EFAULT;
+ return -EAGAIN;
+ }
+
+ if (pass_size > buf->total)
+ pass_size = buf->total;
+
+ /* Dispatch the indirect buffer.
+ */
+ buffer =
+ (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
+
+ if (DRM_COPY_FROM_USER(buffer, data, pass_size)) {
+ DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
+ return -EFAULT;
+ }
+
+ buf->file_priv = file_priv;
+ buf->used = pass_size;
+ src_offset = dev_priv->gart_buffers_offset + buf->offset;
+
+ r600_blit_copy(dev, src_offset, dst_offset, pass_size);
+
+ radeon_cp_discard_buffer(dev, file_priv->master, buf);
+
+ /* Update the input parameters for next time */
+ image->data = (const u8 __user *)image->data + pass_size;
+ dst_offset += pass_size;
+ size -= pass_size;
+ } while (size > 0);
+ r600_done_blit_copy(dev);
+
+ return 0;
+}
+
+/*
+ * Legacy cs ioctl
+ */
+static u32 radeon_cs_id_get(struct drm_radeon_private *radeon)
+{
+ /* FIXME: check if wrap affect last reported wrap & sequence */
+ radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF;
+ if (!radeon->cs_id_scnt) {
+ /* increment wrap counter */
+ radeon->cs_id_wcnt += 0x01000000;
+ /* valid sequence counter start at 1 */
+ radeon->cs_id_scnt = 1;
+ }
+ return (radeon->cs_id_scnt | radeon->cs_id_wcnt);
+}
+
+static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id)
+{
+ RING_LOCALS;
+
+ *id = radeon_cs_id_get(dev_priv);
+
+ /* SCRATCH 2 */
+ BEGIN_RING(3);
+ R600_CLEAR_AGE(*id);
+ ADVANCE_RING();
+ COMMIT_RING();
+}
+
+static int r600_ib_get(struct drm_device *dev,
+ struct drm_file *fpriv,
+ struct drm_buf **buffer)
+{
+ struct drm_buf *buf;
+
+ *buffer = NULL;
+ buf = radeon_freelist_get(dev);
+ if (!buf) {
+ return -EBUSY;
+ }
+ buf->file_priv = fpriv;
+ *buffer = buf;
+ return 0;
+}
+
+static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf,
+ struct drm_file *fpriv, int l, int r)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+
+ if (buf) {
+ if (!r)
+ r600_cp_dispatch_indirect(dev, buf, 0, l * 4);
+ radeon_cp_discard_buffer(dev, fpriv->master, buf);
+ COMMIT_RING();
+ }
+}
+
+int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
+{
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct drm_radeon_cs *cs = data;
+ struct drm_buf *buf;
+ unsigned family;
+ int l, r = 0;
+ u32 *ib, cs_id = 0;
+
+ if (dev_priv == NULL) {
+ DRM_ERROR("called with no initialization\n");
+ return -EINVAL;
+ }
+ family = dev_priv->flags & RADEON_FAMILY_MASK;
+ if (family < CHIP_R600) {
+ DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n");
+ return -EINVAL;
+ }
+ mutex_lock(&dev_priv->cs_mutex);
+ /* get ib */
+ r = r600_ib_get(dev, fpriv, &buf);
+ if (r) {
+ DRM_ERROR("ib_get failed\n");
+ goto out;
+ }
+ ib = dev->agp_buffer_map->handle + buf->offset;
+ /* now parse command stream */
+ r = r600_cs_legacy(dev, data, fpriv, family, ib, &l);
+ if (r) {
+ goto out;
+ }
+
+out:
+ r600_ib_free(dev, buf, fpriv, l, r);
+ /* emit cs id sequence */
+ r600_cs_id_emit(dev_priv, &cs_id);
+ cs->cs_id = cs_id;
+ mutex_unlock(&dev_priv->cs_mutex);
+ return r;
+}
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
new file mode 100644
index 0000000..33b89cd
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -0,0 +1,657 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ * Alex Deucher
+ * Jerome Glisse
+ */
+#include "drmP.h"
+#include "radeon.h"
+#include "r600d.h"
+#include "avivod.h"
+
+static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
+ struct radeon_cs_reloc **cs_reloc);
+static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
+ struct radeon_cs_reloc **cs_reloc);
+typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
+static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
+
+/**
+ * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
+ * @parser: parser structure holding parsing context.
+ * @pkt: where to store packet informations
+ *
+ * Assume that chunk_ib_index is properly set. Will return -EINVAL
+ * if packet is bigger than remaining ib size. or if packets is unknown.
+ **/
+int r600_cs_packet_parse(struct radeon_cs_parser *p,
+ struct radeon_cs_packet *pkt,
+ unsigned idx)
+{
+ struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
+ uint32_t header;
+
+ if (idx >= ib_chunk->length_dw) {
+ DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
+ idx, ib_chunk->length_dw);
+ return -EINVAL;
+ }
+ header = ib_chunk->kdata[idx];
+ pkt->idx = idx;
+ pkt->type = CP_PACKET_GET_TYPE(header);
+ pkt->count = CP_PACKET_GET_COUNT(header);
+ pkt->one_reg_wr = 0;
+ switch (pkt->type) {
+ case PACKET_TYPE0:
+ pkt->reg = CP_PACKET0_GET_REG(header);
+ break;
+ case PACKET_TYPE3:
+ pkt->opcode = CP_PACKET3_GET_OPCODE(header);
+ break;
+ case PACKET_TYPE2:
+ pkt->count = -1;
+ break;
+ default:
+ DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
+ return -EINVAL;
+ }
+ if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
+ DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
+ pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/**
+ * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
+ * @parser: parser structure holding parsing context.
+ * @data: pointer to relocation data
+ * @offset_start: starting offset
+ * @offset_mask: offset mask (to align start offset on)
+ * @reloc: reloc informations
+ *
+ * Check next packet is relocation packet3, do bo validation and compute
+ * GPU offset using the provided start.
+ **/
+static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
+ struct radeon_cs_reloc **cs_reloc)
+{
+ struct radeon_cs_chunk *ib_chunk;
+ struct radeon_cs_chunk *relocs_chunk;
+ struct radeon_cs_packet p3reloc;
+ unsigned idx;
+ int r;
+
+ if (p->chunk_relocs_idx == -1) {
+ DRM_ERROR("No relocation chunk !\n");
+ return -EINVAL;
+ }
+ *cs_reloc = NULL;
+ ib_chunk = &p->chunks[p->chunk_ib_idx];
+ relocs_chunk = &p->chunks[p->chunk_relocs_idx];
+ r = r600_cs_packet_parse(p, &p3reloc, p->idx);
+ if (r) {
+ return r;
+ }
+ p->idx += p3reloc.count + 2;
+ if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
+ DRM_ERROR("No packet3 for relocation for packet at %d.\n",
+ p3reloc.idx);
+ return -EINVAL;
+ }
+ idx = ib_chunk->kdata[p3reloc.idx + 1];
+ if (idx >= relocs_chunk->length_dw) {
+ DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
+ idx, relocs_chunk->length_dw);
+ return -EINVAL;
+ }
+ /* FIXME: we assume reloc size is 4 dwords */
+ *cs_reloc = p->relocs_ptr[(idx / 4)];
+ return 0;
+}
+
+/**
+ * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
+ * @parser: parser structure holding parsing context.
+ * @data: pointer to relocation data
+ * @offset_start: starting offset
+ * @offset_mask: offset mask (to align start offset on)
+ * @reloc: reloc informations
+ *
+ * Check next packet is relocation packet3, do bo validation and compute
+ * GPU offset using the provided start.
+ **/
+static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
+ struct radeon_cs_reloc **cs_reloc)
+{
+ struct radeon_cs_chunk *ib_chunk;
+ struct radeon_cs_chunk *relocs_chunk;
+ struct radeon_cs_packet p3reloc;
+ unsigned idx;
+ int r;
+
+ if (p->chunk_relocs_idx == -1) {
+ DRM_ERROR("No relocation chunk !\n");
+ return -EINVAL;
+ }
+ *cs_reloc = NULL;
+ ib_chunk = &p->chunks[p->chunk_ib_idx];
+ relocs_chunk = &p->chunks[p->chunk_relocs_idx];
+ r = r600_cs_packet_parse(p, &p3reloc, p->idx);
+ if (r) {
+ return r;
+ }
+ p->idx += p3reloc.count + 2;
+ if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
+ DRM_ERROR("No packet3 for relocation for packet at %d.\n",
+ p3reloc.idx);
+ return -EINVAL;
+ }
+ idx = ib_chunk->kdata[p3reloc.idx + 1];
+ if (idx >= relocs_chunk->length_dw) {
+ DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
+ idx, relocs_chunk->length_dw);
+ return -EINVAL;
+ }
+ *cs_reloc = &p->relocs[0];
+ (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
+ (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
+ return 0;
+}
+
+static int r600_packet0_check(struct radeon_cs_parser *p,
+ struct radeon_cs_packet *pkt,
+ unsigned idx, unsigned reg)
+{
+ switch (reg) {
+ case AVIVO_D1MODE_VLINE_START_END:
+ case AVIVO_D2MODE_VLINE_START_END:
+ break;
+ default:
+ printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
+ reg, idx);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
+ struct radeon_cs_packet *pkt)
+{
+ unsigned reg, i;
+ unsigned idx;
+ int r;
+
+ idx = pkt->idx + 1;
+ reg = pkt->reg;
+ for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
+ r = r600_packet0_check(p, pkt, idx, reg);
+ if (r) {
+ return r;
+ }
+ }
+ return 0;
+}
+
+static int r600_packet3_check(struct radeon_cs_parser *p,
+ struct radeon_cs_packet *pkt)
+{
+ struct radeon_cs_chunk *ib_chunk;
+ struct radeon_cs_reloc *reloc;
+ volatile u32 *ib;
+ unsigned idx;
+ unsigned i;
+ unsigned start_reg, end_reg, reg;
+ int r;
+
+ ib = p->ib->ptr;
+ ib_chunk = &p->chunks[p->chunk_ib_idx];
+ idx = pkt->idx + 1;
+ switch (pkt->opcode) {
+ case PACKET3_START_3D_CMDBUF:
+ if (p->family >= CHIP_RV770 || pkt->count) {
+ DRM_ERROR("bad START_3D\n");
+ return -EINVAL;
+ }
+ break;
+ case PACKET3_CONTEXT_CONTROL:
+ if (pkt->count != 1) {
+ DRM_ERROR("bad CONTEXT_CONTROL\n");
+ return -EINVAL;
+ }
+ break;
+ case PACKET3_INDEX_TYPE:
+ case PACKET3_NUM_INSTANCES:
+ if (pkt->count) {
+ DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
+ return -EINVAL;
+ }
+ break;
+ case PACKET3_DRAW_INDEX:
+ if (pkt->count != 3) {
+ DRM_ERROR("bad DRAW_INDEX\n");
+ return -EINVAL;
+ }
+ r = r600_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("bad DRAW_INDEX\n");
+ return -EINVAL;
+ }
+ ib[idx+0] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
+ ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+ break;
+ case PACKET3_DRAW_INDEX_AUTO:
+ if (pkt->count != 1) {
+ DRM_ERROR("bad DRAW_INDEX_AUTO\n");
+ return -EINVAL;
+ }
+ break;
+ case PACKET3_DRAW_INDEX_IMMD_BE:
+ case PACKET3_DRAW_INDEX_IMMD:
+ if (pkt->count < 2) {
+ DRM_ERROR("bad DRAW_INDEX_IMMD\n");
+ return -EINVAL;
+ }
+ break;
+ case PACKET3_WAIT_REG_MEM:
+ if (pkt->count != 5) {
+ DRM_ERROR("bad WAIT_REG_MEM\n");
+ return -EINVAL;
+ }
+ /* bit 4 is reg (0) or mem (1) */
+ if (ib_chunk->kdata[idx+0] & 0x10) {
+ r = r600_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("bad WAIT_REG_MEM\n");
+ return -EINVAL;
+ }
+ ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
+ ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+ }
+ break;
+ case PACKET3_SURFACE_SYNC:
+ if (pkt->count != 3) {
+ DRM_ERROR("bad SURFACE_SYNC\n");
+ return -EINVAL;
+ }
+ /* 0xffffffff/0x0 is flush all cache flag */
+ if (ib_chunk->kdata[idx+1] != 0xffffffff ||
+ ib_chunk->kdata[idx+2] != 0) {
+ r = r600_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("bad SURFACE_SYNC\n");
+ return -EINVAL;
+ }
+ ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+ }
+ break;
+ case PACKET3_EVENT_WRITE:
+ if (pkt->count != 2 && pkt->count != 0) {
+ DRM_ERROR("bad EVENT_WRITE\n");
+ return -EINVAL;
+ }
+ if (pkt->count) {
+ r = r600_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("bad EVENT_WRITE\n");
+ return -EINVAL;
+ }
+ ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
+ ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+ }
+ break;
+ case PACKET3_EVENT_WRITE_EOP:
+ if (pkt->count != 4) {
+ DRM_ERROR("bad EVENT_WRITE_EOP\n");
+ return -EINVAL;
+ }
+ r = r600_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("bad EVENT_WRITE\n");
+ return -EINVAL;
+ }
+ ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
+ ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+ break;
+ case PACKET3_SET_CONFIG_REG:
+ start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
+ end_reg = 4 * pkt->count + start_reg - 4;
+ if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
+ (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
+ (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
+ DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
+ return -EINVAL;
+ }
+ for (i = 0; i < pkt->count; i++) {
+ reg = start_reg + (4 * i);
+ switch (reg) {
+ case CP_COHER_BASE:
+ /* use PACKET3_SURFACE_SYNC */
+ return -EINVAL;
+ default:
+ break;
+ }
+ }
+ break;
+ case PACKET3_SET_CONTEXT_REG:
+ start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
+ end_reg = 4 * pkt->count + start_reg - 4;
+ if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
+ (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
+ (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
+ DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
+ return -EINVAL;
+ }
+ for (i = 0; i < pkt->count; i++) {
+ reg = start_reg + (4 * i);
+ switch (reg) {
+ case DB_DEPTH_BASE:
+ case CB_COLOR0_BASE:
+ case CB_COLOR1_BASE:
+ case CB_COLOR2_BASE:
+ case CB_COLOR3_BASE:
+ case CB_COLOR4_BASE:
+ case CB_COLOR5_BASE:
+ case CB_COLOR6_BASE:
+ case CB_COLOR7_BASE:
+ case SQ_PGM_START_FS:
+ case SQ_PGM_START_ES:
+ case SQ_PGM_START_VS:
+ case SQ_PGM_START_GS:
+ case SQ_PGM_START_PS:
+ r = r600_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("bad SET_CONTEXT_REG "
+ "0x%04X\n", reg);
+ return -EINVAL;
+ }
+ ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+ break;
+ case VGT_DMA_BASE:
+ case VGT_DMA_BASE_HI:
+ /* These should be handled by DRAW_INDEX packet 3 */
+ case VGT_STRMOUT_BASE_OFFSET_0:
+ case VGT_STRMOUT_BASE_OFFSET_1:
+ case VGT_STRMOUT_BASE_OFFSET_2:
+ case VGT_STRMOUT_BASE_OFFSET_3:
+ case VGT_STRMOUT_BASE_OFFSET_HI_0:
+ case VGT_STRMOUT_BASE_OFFSET_HI_1:
+ case VGT_STRMOUT_BASE_OFFSET_HI_2:
+ case VGT_STRMOUT_BASE_OFFSET_HI_3:
+ case VGT_STRMOUT_BUFFER_BASE_0:
+ case VGT_STRMOUT_BUFFER_BASE_1:
+ case VGT_STRMOUT_BUFFER_BASE_2:
+ case VGT_STRMOUT_BUFFER_BASE_3:
+ case VGT_STRMOUT_BUFFER_OFFSET_0:
+ case VGT_STRMOUT_BUFFER_OFFSET_1:
+ case VGT_STRMOUT_BUFFER_OFFSET_2:
+ case VGT_STRMOUT_BUFFER_OFFSET_3:
+ /* These should be handled by STRMOUT_BUFFER packet 3 */
+ DRM_ERROR("bad context reg: 0x%08x\n", reg);
+ return -EINVAL;
+ default:
+ break;
+ }
+ }
+ break;
+ case PACKET3_SET_RESOURCE:
+ if (pkt->count % 7) {
+ DRM_ERROR("bad SET_RESOURCE\n");
+ return -EINVAL;
+ }
+ start_reg = (ib[idx+0] << 2) + PACKET3_SET_RESOURCE_OFFSET;
+ end_reg = 4 * pkt->count + start_reg - 4;
+ if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
+ (start_reg >= PACKET3_SET_RESOURCE_END) ||
+ (end_reg >= PACKET3_SET_RESOURCE_END)) {
+ DRM_ERROR("bad SET_RESOURCE\n");
+ return -EINVAL;
+ }
+ for (i = 0; i < (pkt->count / 7); i++) {
+ switch (G__SQ_VTX_CONSTANT_TYPE(ib[idx+(i*7)+6+1])) {
+ case SQ_TEX_VTX_VALID_TEXTURE:
+ /* tex base */
+ r = r600_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("bad SET_RESOURCE\n");
+ return -EINVAL;
+ }
+ ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+ /* tex mip base */
+ r = r600_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("bad SET_RESOURCE\n");
+ return -EINVAL;
+ }
+ ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+ break;
+ case SQ_TEX_VTX_VALID_BUFFER:
+ /* vtx base */
+ r = r600_cs_packet_next_reloc(p, &reloc);
+ if (r) {
+ DRM_ERROR("bad SET_RESOURCE\n");
+ return -EINVAL;
+ }
+ ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
+ ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+ break;
+ case SQ_TEX_VTX_INVALID_TEXTURE:
+ case SQ_TEX_VTX_INVALID_BUFFER:
+ default:
+ DRM_ERROR("bad SET_RESOURCE\n");
+ return -EINVAL;
+ }
+ }
+ break;
+ case PACKET3_SET_ALU_CONST:
+ start_reg = (ib[idx+0] << 2) + PACKET3_SET_ALU_CONST_OFFSET;
+ end_reg = 4 * pkt->count + start_reg - 4;
+ if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
+ (start_reg >= PACKET3_SET_ALU_CONST_END) ||
+ (end_reg >= PACKET3_SET_ALU_CONST_END)) {
+ DRM_ERROR("bad SET_ALU_CONST\n");
+ return -EINVAL;
+ }
+ break;
+ case PACKET3_SET_BOOL_CONST:
+ start_reg = (ib[idx+0] << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
+ end_reg = 4 * pkt->count + start_reg - 4;
+ if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
+ (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
+ (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
+ DRM_ERROR("bad SET_BOOL_CONST\n");
+ return -EINVAL;
+ }
+ break;
+ case PACKET3_SET_LOOP_CONST:
+ start_reg = (ib[idx+0] << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
+ end_reg = 4 * pkt->count + start_reg - 4;
+ if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
+ (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
+ (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
+ DRM_ERROR("bad SET_LOOP_CONST\n");
+ return -EINVAL;
+ }
+ break;
+ case PACKET3_SET_CTL_CONST:
+ start_reg = (ib[idx+0] << 2) + PACKET3_SET_CTL_CONST_OFFSET;
+ end_reg = 4 * pkt->count + start_reg - 4;
+ if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
+ (start_reg >= PACKET3_SET_CTL_CONST_END) ||
+ (end_reg >= PACKET3_SET_CTL_CONST_END)) {
+ DRM_ERROR("bad SET_CTL_CONST\n");
+ return -EINVAL;
+ }
+ break;
+ case PACKET3_SET_SAMPLER:
+ if (pkt->count % 3) {
+ DRM_ERROR("bad SET_SAMPLER\n");
+ return -EINVAL;
+ }
+ start_reg = (ib[idx+0] << 2) + PACKET3_SET_SAMPLER_OFFSET;
+ end_reg = 4 * pkt->count + start_reg - 4;
+ if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
+ (start_reg >= PACKET3_SET_SAMPLER_END) ||
+ (end_reg >= PACKET3_SET_SAMPLER_END)) {
+ DRM_ERROR("bad SET_SAMPLER\n");
+ return -EINVAL;
+ }
+ break;
+ case PACKET3_SURFACE_BASE_UPDATE:
+ if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
+ DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
+ return -EINVAL;
+ }
+ if (pkt->count) {
+ DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
+ return -EINVAL;
+ }
+ break;
+ case PACKET3_NOP:
+ break;
+ default:
+ DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+int r600_cs_parse(struct radeon_cs_parser *p)
+{
+ struct radeon_cs_packet pkt;
+ int r;
+
+ do {
+ r = r600_cs_packet_parse(p, &pkt, p->idx);
+ if (r) {
+ return r;
+ }
+ p->idx += pkt.count + 2;
+ switch (pkt.type) {
+ case PACKET_TYPE0:
+ r = r600_cs_parse_packet0(p, &pkt);
+ break;
+ case PACKET_TYPE2:
+ break;
+ case PACKET_TYPE3:
+ r = r600_packet3_check(p, &pkt);
+ break;
+ default:
+ DRM_ERROR("Unknown packet type %d !\n", pkt.type);
+ return -EINVAL;
+ }
+ if (r) {
+ return r;
+ }
+ } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
+#if 0
+ for (r = 0; r < p->ib->length_dw; r++) {
+ printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
+ mdelay(1);
+ }
+#endif
+ return 0;
+}
+
+static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
+{
+ if (p->chunk_relocs_idx == -1) {
+ return 0;
+ }
+ p->relocs = kcalloc(1, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
+ if (p->relocs == NULL) {
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+/**
+ * cs_parser_fini() - clean parser states
+ * @parser: parser structure holding parsing context.
+ * @error: error number
+ *
+ * If error is set than unvalidate buffer, otherwise just free memory
+ * used by parsing context.
+ **/
+static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
+{
+ unsigned i;
+
+ kfree(parser->relocs);
+ for (i = 0; i < parser->nchunks; i++) {
+ kfree(parser->chunks[i].kdata);
+ }
+ kfree(parser->chunks);
+ kfree(parser->chunks_array);
+}
+
+int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
+ unsigned family, u32 *ib, int *l)
+{
+ struct radeon_cs_parser parser;
+ struct radeon_cs_chunk *ib_chunk;
+ struct radeon_ib fake_ib;
+ int r;
+
+ /* initialize parser */
+ memset(&parser, 0, sizeof(struct radeon_cs_parser));
+ parser.filp = filp;
+ parser.rdev = NULL;
+ parser.family = family;
+ parser.ib = &fake_ib;
+ fake_ib.ptr = ib;
+ r = radeon_cs_parser_init(&parser, data);
+ if (r) {
+ DRM_ERROR("Failed to initialize parser !\n");
+ r600_cs_parser_fini(&parser, r);
+ return r;
+ }
+ r = r600_cs_parser_relocs_legacy(&parser);
+ if (r) {
+ DRM_ERROR("Failed to parse relocation !\n");
+ r600_cs_parser_fini(&parser, r);
+ return r;
+ }
+ /* Copy the packet into the IB, the parser will read from the
+ * input memory (cached) and write to the IB (which can be
+ * uncached). */
+ ib_chunk = &parser.chunks[parser.chunk_ib_idx];
+ parser.ib->length_dw = ib_chunk->length_dw;
+ memcpy((void *)parser.ib->ptr, ib_chunk->kdata, ib_chunk->length_dw*4);
+ *l = parser.ib->length_dw;
+ r = r600_cs_parse(&parser);
+ if (r) {
+ DRM_ERROR("Invalid command stream !\n");
+ r600_cs_parser_fini(&parser, r);
+ return r;
+ }
+ r600_cs_parser_fini(&parser, r);
+ return r;
+}
+
+void r600_cs_legacy_init(void)
+{
+ r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
+}
diff --git a/drivers/gpu/drm/radeon/r600_microcode.h b/drivers/gpu/drm/radeon/r600_microcode.h
deleted file mode 100644
index 778c8b4..0000000
--- a/drivers/gpu/drm/radeon/r600_microcode.h
+++ /dev/null
@@ -1,23297 +0,0 @@
-/*
- * Copyright 2008-2009 Advanced Micro Devices, Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef R600_MICROCODE_H
-#define R600_MICROCODE_H
-
-static const int ME_JUMP_TABLE_START = 1764;
-static const int ME_JUMP_TABLE_END = 1792;
-
-#define PFP_UCODE_SIZE 576
-#define PM4_UCODE_SIZE 1792
-#define R700_PFP_UCODE_SIZE 848
-#define R700_PM4_UCODE_SIZE 1360
-
-static const u32 R600_cp_microcode[][3] = {
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0000ffff, 0x00284621, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00000000, 0x00e00000, 0x000 },
- { 0x00010000, 0xc0294620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x614 },
- { 0x00000000, 0x00600000, 0x5b2 },
- { 0x00000000, 0x00600000, 0x5c5 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000f00, 0x00281622, 0x000 },
- { 0x00000008, 0x00211625, 0x000 },
- { 0x00000020, 0x00203625, 0x000 },
- { 0x8d000000, 0x00204411, 0x000 },
- { 0x00000004, 0x002f0225, 0x000 },
- { 0x00000000, 0x0ce00000, 0x018 },
- { 0x00412000, 0x00404811, 0x019 },
- { 0x00422000, 0x00204811, 0x000 },
- { 0x8e000000, 0x00204411, 0x000 },
- { 0x00000031, 0x00204a2d, 0x000 },
- { 0x90000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x0000000c, 0x00211622, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x00000019, 0x00211a22, 0x000 },
- { 0x00000004, 0x00281a26, 0x000 },
- { 0x00000000, 0x002914c5, 0x000 },
- { 0x00000021, 0x00203625, 0x000 },
- { 0x00000000, 0x003a1402, 0x000 },
- { 0x00000016, 0x00211625, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x0000001d, 0x00200e2d, 0x000 },
- { 0xfffffffc, 0x00280e23, 0x000 },
- { 0x00000000, 0x002914a3, 0x000 },
- { 0x0000001d, 0x00203625, 0x000 },
- { 0x00008000, 0x00280e22, 0x000 },
- { 0x00000007, 0x00220e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x20000000, 0x00280e22, 0x000 },
- { 0x00000006, 0x00210e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x00000000, 0x00220222, 0x000 },
- { 0x00000000, 0x14e00000, 0x038 },
- { 0x00000000, 0x2ee00000, 0x035 },
- { 0x00000000, 0x2ce00000, 0x037 },
- { 0x00000000, 0x00400e2d, 0x039 },
- { 0x00000008, 0x00200e2d, 0x000 },
- { 0x00000009, 0x0040122d, 0x046 },
- { 0x00000001, 0x00400e2d, 0x039 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x03e },
- { 0x00000008, 0x00401c11, 0x041 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x0000000f, 0x00281e27, 0x000 },
- { 0x00000003, 0x00221e27, 0x000 },
- { 0x7fc00000, 0x00281a23, 0x000 },
- { 0x00000014, 0x00211a26, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000008, 0x00221a26, 0x000 },
- { 0x00000000, 0x00290cc7, 0x000 },
- { 0x00000030, 0x00203624, 0x000 },
- { 0x00007f00, 0x00281221, 0x000 },
- { 0x00001400, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x04b },
- { 0x00000001, 0x00290e23, 0x000 },
- { 0x00000010, 0x00203623, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfff80000, 0x00294a23, 0x000 },
- { 0x00000000, 0x003a2c02, 0x000 },
- { 0x00000002, 0x00220e2b, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x00000011, 0x00203623, 0x000 },
- { 0x00001fff, 0x00294a23, 0x000 },
- { 0x00000030, 0x00204a2d, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000032, 0x00200e2d, 0x000 },
- { 0x060a0200, 0x00294a23, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00210222, 0x000 },
- { 0x00000000, 0x14e00000, 0x061 },
- { 0x00000000, 0x2ee00000, 0x05f },
- { 0x00000000, 0x2ce00000, 0x05e },
- { 0x00000000, 0x00400e2d, 0x062 },
- { 0x00000001, 0x00400e2d, 0x062 },
- { 0x0000000a, 0x00200e2d, 0x000 },
- { 0x0000000b, 0x0040122d, 0x06a },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x7fc00000, 0x00281623, 0x000 },
- { 0x00000014, 0x00211625, 0x000 },
- { 0x00000001, 0x00331625, 0x000 },
- { 0x80000000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00290ca3, 0x000 },
- { 0x3ffffc00, 0x00290e23, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x06d },
- { 0x00000100, 0x00401c11, 0x070 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x000000f0, 0x00281e27, 0x000 },
- { 0x00000004, 0x00221e27, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0xfffff0ff, 0x00281a30, 0x000 },
- { 0x0000a028, 0x00204411, 0x000 },
- { 0x00000000, 0x002948e6, 0x000 },
- { 0x0000a018, 0x00204411, 0x000 },
- { 0x3fffffff, 0x00284a23, 0x000 },
- { 0x0000a010, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x0000002d, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a3, 0x000 },
- { 0x00000000, 0x0cc00000, 0x080 },
- { 0x0000002e, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a4, 0x000 },
- { 0x00000000, 0x0cc00000, 0x081 },
- { 0x00000000, 0x00400000, 0x087 },
- { 0x0000002d, 0x00203623, 0x000 },
- { 0x0000002e, 0x00203624, 0x000 },
- { 0x0000001d, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x087 },
- { 0x00000000, 0x00600000, 0x5ed },
- { 0x00000000, 0x00600000, 0x5e1 },
- { 0x00000002, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x08a },
- { 0x00000018, 0xc0403620, 0x090 },
- { 0x00000000, 0x2ee00000, 0x08e },
- { 0x00000000, 0x2ce00000, 0x08d },
- { 0x00000002, 0x00400e2d, 0x08f },
- { 0x00000003, 0x00400e2d, 0x08f },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000018, 0x00203623, 0x000 },
- { 0x00000003, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x095 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x09d },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x2ee00000, 0x09b },
- { 0x00000000, 0x2ce00000, 0x09a },
- { 0x00000002, 0x00400e2d, 0x09c },
- { 0x00000003, 0x00400e2d, 0x09c },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x003f0000, 0x00280e23, 0x000 },
- { 0x00000010, 0x00210e23, 0x000 },
- { 0x00000013, 0x00203623, 0x000 },
- { 0x0000001e, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0a4 },
- { 0x0000001c, 0xc0203620, 0x000 },
- { 0x0000001f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0a7 },
- { 0x0000001b, 0xc0203620, 0x000 },
- { 0x00000008, 0x00210e2b, 0x000 },
- { 0x0000007f, 0x00280e23, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0db },
- { 0x00000000, 0x27000000, 0x000 },
- { 0x00000000, 0x00600000, 0x28c },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x0000000c, 0x00221e30, 0x000 },
- { 0x99800000, 0x00204411, 0x000 },
- { 0x00000004, 0x0020122d, 0x000 },
- { 0x00000008, 0x00221224, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00291ce4, 0x000 },
- { 0x00000000, 0x00604807, 0x128 },
- { 0x9b000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x9c000000, 0x00204411, 0x000 },
- { 0x00000000, 0x0033146f, 0x000 },
- { 0x00000001, 0x00333e23, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0x00203c05, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e007, 0x00204411, 0x000 },
- { 0x0000000f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0c5 },
- { 0x00f8ff08, 0x00204811, 0x000 },
- { 0x98000000, 0x00404811, 0x0d6 },
- { 0x000000f0, 0x00280e22, 0x000 },
- { 0x000000a0, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x0d4 },
- { 0x00000013, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0cf },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0ce },
- { 0x00003f00, 0x00400c11, 0x0d0 },
- { 0x00001f00, 0x00400c11, 0x0d0 },
- { 0x00000f00, 0x00200c11, 0x000 },
- { 0x00380009, 0x00294a23, 0x000 },
- { 0x3f000000, 0x00280e2b, 0x000 },
- { 0x00000002, 0x00220e23, 0x000 },
- { 0x00000007, 0x00494a23, 0x0d6 },
- { 0x00380f09, 0x00204811, 0x000 },
- { 0x68000007, 0x00204811, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000a202, 0x00204411, 0x000 },
- { 0x00ff0000, 0x00284a22, 0x000 },
- { 0x00000030, 0x00200e2d, 0x000 },
- { 0x0000002e, 0x0020122d, 0x000 },
- { 0x00000000, 0x002f0083, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0e3 },
- { 0x00000000, 0x00600000, 0x5e7 },
- { 0x00000000, 0x00400000, 0x0e4 },
- { 0x00000000, 0x00600000, 0x5ea },
- { 0x00000007, 0x0020222d, 0x000 },
- { 0x00000005, 0x00220e22, 0x000 },
- { 0x00100000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x000000ef, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x0000001d, 0x00200e2d, 0x000 },
- { 0x00000003, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x0f1 },
- { 0x0000000b, 0x00210228, 0x000 },
- { 0x00000000, 0x14c00000, 0x0f1 },
- { 0x00000400, 0x00292228, 0x000 },
- { 0x0000001a, 0x00203628, 0x000 },
- { 0x0000001c, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x0f6 },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000001e, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x104 },
- { 0x0000a30f, 0x00204411, 0x000 },
- { 0x00000013, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x0fd },
- { 0xffffffff, 0x00404811, 0x104 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x100 },
- { 0x0000ffff, 0x00404811, 0x104 },
- { 0x00000004, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x103 },
- { 0x000000ff, 0x00404811, 0x104 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0002c400, 0x00204411, 0x000 },
- { 0x0000001f, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x10b },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x00000019, 0x00203623, 0x000 },
- { 0x00000018, 0x40224a20, 0x000 },
- { 0x00000010, 0xc0424a20, 0x10d },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x00000019, 0x00203623, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000000a, 0x00201011, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x114 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00531224, 0x110 },
- { 0xffbfffff, 0x00283a2e, 0x000 },
- { 0x0000001b, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x127 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0x00000018, 0x00220e30, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e00e, 0x00204411, 0x000 },
- { 0x07f8ff08, 0x00204811, 0x000 },
- { 0x00000000, 0x00294a23, 0x000 },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x00800000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204806, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x614 },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x613 },
- { 0x00000004, 0x00404c11, 0x12e },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x2fe },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x19f },
- { 0x00000000, 0x00600000, 0x151 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40280620, 0x000 },
- { 0x00000010, 0xc0210a20, 0x000 },
- { 0x00000000, 0x00341461, 0x000 },
- { 0x00000000, 0x00741882, 0x2a4 },
- { 0x0001a1fd, 0x00604411, 0x2c9 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x138 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x2fe },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x19f },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x151 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0681a20, 0x2a4 },
- { 0x0001a1fd, 0x00604411, 0x2c9 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x149 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000001, 0x00300a2f, 0x000 },
- { 0x00000001, 0x00210a22, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600000, 0x17c },
- { 0x00000000, 0x00600000, 0x18d },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00202c08, 0x000 },
- { 0x00000000, 0x00202411, 0x000 },
- { 0x00000000, 0x00202811, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000002, 0x00221e29, 0x000 },
- { 0x00000000, 0x007048eb, 0x189 },
- { 0x00000000, 0x00600000, 0x2a4 },
- { 0x00000001, 0x40330620, 0x000 },
- { 0x00000000, 0xc0302409, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x28c },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x173 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000001, 0x00530621, 0x16f },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0604800, 0x184 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000013, 0x0020062d, 0x000 },
- { 0x00000000, 0x0078042a, 0x2e4 },
- { 0x00000000, 0x00202809, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x165 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000210, 0x00600411, 0x2fe },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x181 },
- { 0x0000001b, 0xc0203620, 0x000 },
- { 0x0000001c, 0xc0203620, 0x000 },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x46000000, 0x00600811, 0x19f },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x188 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000021, 0x00804811, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40281620, 0x000 },
- { 0x00000010, 0xc0811a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000008, 0x00221e30, 0x000 },
- { 0x00000032, 0x00201a2d, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfffbff09, 0x00204811, 0x000 },
- { 0x00000011, 0x0020222d, 0x000 },
- { 0x00001fff, 0x00294a28, 0x000 },
- { 0x00000006, 0x0020222d, 0x000 },
- { 0x00000000, 0x002920e8, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a26, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000100, 0x00201811, 0x000 },
- { 0x00000008, 0x00621e28, 0x128 },
- { 0x00000008, 0x00822228, 0x000 },
- { 0x0002c000, 0x00204411, 0x000 },
- { 0x0000001b, 0x00600e2d, 0x1aa },
- { 0x0000001c, 0x00600e2d, 0x1aa },
- { 0x0000c008, 0x00204411, 0x000 },
- { 0x0000001d, 0x00200e2d, 0x000 },
- { 0x00000000, 0x14c00000, 0x1a6 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x39000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00804802, 0x000 },
- { 0x00000020, 0x00202e2d, 0x000 },
- { 0x00000000, 0x003b0d63, 0x000 },
- { 0x00000008, 0x00224a23, 0x000 },
- { 0x00000010, 0x00224a23, 0x000 },
- { 0x00000018, 0x00224a23, 0x000 },
- { 0x00000000, 0x00804803, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00001000, 0x00600411, 0x2fe },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x19f },
- { 0x00000007, 0x0021062f, 0x000 },
- { 0x00000019, 0x00200a2d, 0x000 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000ffff, 0x40282220, 0x000 },
- { 0x0000000f, 0x00262228, 0x000 },
- { 0x00000010, 0x40212620, 0x000 },
- { 0x0000000f, 0x00262629, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001b, 0x00204811, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1cd },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000081, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000080, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1c9 },
- { 0x00000000, 0x00600000, 0x1d6 },
- { 0x00000001, 0x00531e27, 0x1c5 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000001f, 0x00280a22, 0x000 },
- { 0x0000001f, 0x00282a2a, 0x000 },
- { 0x00000001, 0x00530621, 0x1be },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000002, 0x00304a2f, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000001, 0x00301e2f, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x1d6 },
- { 0x00000001, 0x00531e27, 0x1d2 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x0000000f, 0x00260e23, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000000f, 0x00261224, 0x000 },
- { 0x00000000, 0x00201411, 0x000 },
- { 0x00000000, 0x00601811, 0x2a4 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022b, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1e5 },
- { 0x00000010, 0x00221628, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a29, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x0020480a, 0x000 },
- { 0x00000000, 0x00202c11, 0x000 },
- { 0x00000010, 0x00221623, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a24, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x00731503, 0x1f2 },
- { 0x00000000, 0x00201805, 0x000 },
- { 0x00000000, 0x00731524, 0x1f2 },
- { 0x00000000, 0x002d14c5, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00000000, 0x00202003, 0x000 },
- { 0x00000000, 0x00802404, 0x000 },
- { 0x0000000f, 0x00210225, 0x000 },
- { 0x00000000, 0x14c00000, 0x613 },
- { 0x00000000, 0x002b1405, 0x000 },
- { 0x00000001, 0x00901625, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x2fe },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x19f },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00294a22, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a21, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000ffff, 0x40281220, 0x000 },
- { 0x00000010, 0xc0211a20, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211620, 0x000 },
- { 0x00000000, 0x00741465, 0x2a4 },
- { 0x0001a1fd, 0x00604411, 0x2c9 },
- { 0x00000001, 0x00330621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0cc00000, 0x206 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x1ff },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x5c5 },
- { 0x00000000, 0x0040040f, 0x200 },
- { 0x00000000, 0x00600000, 0x5b2 },
- { 0x00000000, 0x00600000, 0x5c5 },
- { 0x00000210, 0x00600411, 0x2fe },
- { 0x00000000, 0x00600000, 0x18d },
- { 0x00000000, 0x00600000, 0x189 },
- { 0x00000000, 0x00600000, 0x2a4 },
- { 0x00000000, 0x00600000, 0x28c },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x21f },
- { 0x00000000, 0xc0404800, 0x21c },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x00600411, 0x2e4 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x5b2 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000018, 0x40210a20, 0x000 },
- { 0x00000003, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x235 },
- { 0x0000001a, 0x0020222d, 0x000 },
- { 0x00080101, 0x00292228, 0x000 },
- { 0x0000001a, 0x00203628, 0x000 },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x23a },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000010, 0x00600411, 0x2fe },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x19f },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x00000000, 0x00600000, 0x265 },
- { 0x0000001d, 0x00201e2d, 0x000 },
- { 0x00000001, 0x00211e27, 0x000 },
- { 0x00000000, 0x14e00000, 0x253 },
- { 0x00000018, 0x00201e2d, 0x000 },
- { 0x0000ffff, 0x00281e27, 0x000 },
- { 0x00000000, 0x00341c27, 0x000 },
- { 0x00000000, 0x12c00000, 0x248 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e5, 0x000 },
- { 0x00000000, 0x08c00000, 0x24b },
- { 0x00000000, 0x00201407, 0x000 },
- { 0x00000018, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00211e27, 0x000 },
- { 0x00000000, 0x00341c47, 0x000 },
- { 0x00000000, 0x12c00000, 0x250 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x08c00000, 0x253 },
- { 0x00000000, 0x00201807, 0x000 },
- { 0x00000000, 0x00600000, 0x2aa },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000000, 0x00342023, 0x000 },
- { 0x00000000, 0x12c00000, 0x25b },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x25a },
- { 0x00000016, 0x00404811, 0x25f },
- { 0x00000018, 0x00404811, 0x25f },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x25e },
- { 0x00000017, 0x00404811, 0x25f },
- { 0x00000019, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00604411, 0x2d2 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x23f },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000010, 0x40210620, 0x000 },
- { 0x0000ffff, 0xc0280a20, 0x000 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0881a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x614 },
- { 0x00000000, 0x00600000, 0x5b2 },
- { 0x00000000, 0xc0600000, 0x28c },
- { 0x00000005, 0x00200a2d, 0x000 },
- { 0x00000008, 0x00220a22, 0x000 },
- { 0x00000034, 0x00201a2d, 0x000 },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00007000, 0x00281e27, 0x000 },
- { 0x00000000, 0x00311ce6, 0x000 },
- { 0x00000033, 0x00201a2d, 0x000 },
- { 0x0000000c, 0x00221a26, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x06e00000, 0x27b },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x00000034, 0x00203623, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00691ce2, 0x128 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x286 },
- { 0x00000001, 0x00333e2f, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000024, 0x00403627, 0x000 },
- { 0x0000000c, 0xc0220a20, 0x000 },
- { 0x00000032, 0x00203622, 0x000 },
- { 0x00000031, 0xc0403620, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000009, 0x00204811, 0x000 },
- { 0xa1000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000029, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce3, 0x000 },
- { 0x00000029, 0x00203627, 0x000 },
- { 0x0000002a, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce4, 0x000 },
- { 0x0000002a, 0x00203627, 0x000 },
- { 0x0000002b, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a3, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x0000002b, 0x00203627, 0x000 },
- { 0x0000002c, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x0000002c, 0x00803627, 0x000 },
- { 0x00000029, 0x00203623, 0x000 },
- { 0x0000002a, 0x00203624, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x0000002b, 0x00203627, 0x000 },
- { 0x00000000, 0x00311cc4, 0x000 },
- { 0x0000002c, 0x00803627, 0x000 },
- { 0x00000022, 0x00203627, 0x000 },
- { 0x00000023, 0x00203628, 0x000 },
- { 0x0000001d, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14c00000, 0x2c5 },
- { 0x00000000, 0x00400000, 0x2c2 },
- { 0x00000022, 0x00203627, 0x000 },
- { 0x00000023, 0x00203628, 0x000 },
- { 0x0000001d, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2c2 },
- { 0x00000003, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2c5 },
- { 0x0000002b, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e1, 0x000 },
- { 0x00000000, 0x02c00000, 0x2c5 },
- { 0x00000029, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a1, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2c5 },
- { 0x0000002c, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e2, 0x000 },
- { 0x00000000, 0x02c00000, 0x2c5 },
- { 0x0000002a, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2c5 },
- { 0x00000000, 0x00600000, 0x5ed },
- { 0x00000000, 0x00600000, 0x29e },
- { 0x00000000, 0x00400000, 0x2c7 },
- { 0x00000000, 0x00600000, 0x29e },
- { 0x00000000, 0x00600000, 0x5e4 },
- { 0x00000000, 0x00400000, 0x2c7 },
- { 0x00000000, 0x00600000, 0x290 },
- { 0x00000000, 0x00400000, 0x2c7 },
- { 0x00000022, 0x00201e2d, 0x000 },
- { 0x00000023, 0x0080222d, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca1, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x003808c5, 0x000 },
- { 0x00000000, 0x00300841, 0x000 },
- { 0x00000001, 0x00220a22, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x0000001d, 0x0020222d, 0x000 },
- { 0x00000000, 0x14c00000, 0x301 },
- { 0xffffffef, 0x00280621, 0x000 },
- { 0x0000001a, 0x0020222d, 0x000 },
- { 0x0000f8e0, 0x00204411, 0x000 },
- { 0x00000000, 0x00294901, 0x000 },
- { 0x00000000, 0x00894901, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00804811, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x97000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00002257, 0x00204411, 0x000 },
- { 0x00000003, 0xc0484a20, 0x000 },
- { 0x0000225d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x5c5 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x00000001, 0x40304a20, 0x000 },
- { 0x00000002, 0xc0304a20, 0x000 },
- { 0x00000001, 0x00530a22, 0x334 },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000017, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x614 },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x33d },
- { 0x00000014, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x351 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000016, 0x00604811, 0x35e },
- { 0x00002100, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x00000004, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x355 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00404811, 0x349 },
- { 0x00000028, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x349 },
- { 0x00002104, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x00000035, 0x00203626, 0x000 },
- { 0x00000049, 0x00201811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000000, 0x002f0226, 0x000 },
- { 0x00000000, 0x0cc00000, 0x360 },
- { 0x00000035, 0x00801a2d, 0x000 },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x00000015, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x376 },
- { 0x0000001e, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x380 },
- { 0x00000020, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x38c },
- { 0x0000000f, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x398 },
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- { 0x0000a2a4, 0x00204411, 0x000 },
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- { 0x00000000, 0x002914a4, 0x000 },
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- { 0x00000000, 0x002948a2, 0x000 },
- { 0x0000a1fe, 0x00204411, 0x000 },
- { 0x00000000, 0x00404803, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000015, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x614 },
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- { 0x0000210e, 0x00204411, 0x000 },
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- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x614 },
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- { 0x00000000, 0x14e00000, 0x38e },
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- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
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- { 0x00002010, 0x00204411, 0x000 },
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- { 0x00002010, 0x00204411, 0x000 },
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- { 0x0000001d, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x3b9 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000017, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x614 },
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- { 0x00000000, 0x14e00000, 0x3ab },
- { 0x00002100, 0x00204411, 0x000 },
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- { 0x00000000, 0x00204803, 0x000 },
- { 0xbabecafe, 0x00204811, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
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- { 0x00000000, 0x00204802, 0x000 },
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- { 0x81000000, 0x00204411, 0x000 },
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- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x3be },
- { 0x8c000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00003fff, 0x40280a20, 0x000 },
- { 0x80000000, 0x40280e20, 0x000 },
- { 0x40000000, 0xc0281220, 0x000 },
- { 0x00040000, 0x00694622, 0x614 },
- { 0x00000000, 0x00201410, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3cc },
- { 0x00000000, 0xc0401800, 0x3cf },
- { 0x00003fff, 0xc0281a20, 0x000 },
- { 0x00040000, 0x00694626, 0x614 },
- { 0x00000000, 0x00201810, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3d2 },
- { 0x00000000, 0xc0401c00, 0x3d5 },
- { 0x00003fff, 0xc0281e20, 0x000 },
- { 0x00040000, 0x00694627, 0x614 },
- { 0x00000000, 0x00201c10, 0x000 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0x002820c5, 0x000 },
- { 0x00000000, 0x004948e8, 0x000 },
- { 0xa5800000, 0x00200811, 0x000 },
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- { 0x83000000, 0x00604411, 0x3fd },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x0000001f, 0xc0210220, 0x000 },
- { 0x00000000, 0x14c00000, 0x3e2 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0000ffff, 0xc0481220, 0x3ea },
- { 0xa7800000, 0x00200811, 0x000 },
- { 0x0000a000, 0x00200c11, 0x000 },
- { 0x83000000, 0x00604411, 0x3fd },
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- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
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- { 0x00000000, 0x00304883, 0x000 },
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- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x1d000000, 0x000 },
- { 0x83000000, 0x00604411, 0x3fd },
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- { 0x00000000, 0xd9004800, 0x000 },
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- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
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- { 0x00000000, 0xc0204800, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000000, 0xc0200800, 0x000 },
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- { 0x0004217f, 0x00604411, 0x614 },
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- { 0x00000010, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x444 },
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- { 0x00000001, 0x00204811, 0x000 },
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- { 0x00000000, 0x00400000, 0x44d },
- { 0x81000000, 0x00204411, 0x000 },
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- { 0x00000000, 0x1ae00000, 0x44c },
- { 0x00000000, 0x002824f0, 0x000 },
- { 0x00000007, 0x00280a23, 0x000 },
- { 0x00000001, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x454 },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x04e00000, 0x46d },
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- { 0x00000000, 0x02e00000, 0x46d },
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- { 0x00000000, 0x00400000, 0x47a },
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- { 0x00000000, 0x0ae00000, 0x46d },
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- { 0x00000000, 0x0ae00000, 0x468 },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x06e00000, 0x46d },
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- { 0x00000000, 0x08e00000, 0x46d },
- { 0x00000000, 0x00400000, 0x47a },
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- { 0x00000000, 0x00404c08, 0x43c },
- { 0x00000000, 0xc0200800, 0x000 },
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- { 0x00000000, 0x14e00000, 0x48a },
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- { 0x00000000, 0xc0204800, 0x000 },
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- { 0x81000000, 0x00204411, 0x000 },
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- { 0x00000000, 0x14c00000, 0x493 },
- { 0xa0000000, 0x00204411, 0x000 },
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- { 0x00000000, 0xc0204810, 0x000 },
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- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00400000, 0x491 },
- { 0x00000000, 0xc0210a20, 0x000 },
- { 0x00000000, 0x14c00000, 0x4ae },
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- { 0x00000000, 0x00204811, 0x000 },
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- { 0x00000000, 0x1ac00000, 0x4a9 },
- { 0x9e000000, 0x00204411, 0x000 },
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- { 0x00000000, 0x1ae00000, 0x4ac },
- { 0x00000000, 0x00400000, 0x4b2 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00040000, 0xc0294620, 0x000 },
- { 0x00000000, 0xc0600000, 0x614 },
- { 0x00000001, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x4b9 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x00000000, 0xc0204400, 0x000 },
- { 0x00000000, 0xc0404810, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x614 },
- { 0x00000000, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x4bb },
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- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
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- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000003, 0x00333e2f, 0x000 },
- { 0x00000001, 0x00210221, 0x000 },
- { 0x00000000, 0x14e00000, 0x4eb },
- { 0x00000035, 0x00200a2d, 0x000 },
- { 0x00040000, 0x18e00c11, 0x4da },
- { 0x00000001, 0x00333e2f, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
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- { 0x00000008, 0x00300a22, 0x000 },
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- { 0x00000000, 0xd8c04800, 0x4ce },
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- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000036, 0x0020122d, 0x000 },
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- { 0x00002169, 0x00204411, 0x000 },
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- { 0x00000000, 0x00204803, 0x000 },
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- { 0x00000000, 0x00400000, 0x491 },
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- { 0x00000000, 0x00600000, 0x00b },
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- { 0x00000000, 0xc0400400, 0x001 },
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- { 0x00000000, 0x0cc00000, 0x4f6 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0x14c00000, 0x50b },
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- { 0x00000000, 0x0029386e, 0x000 },
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- { 0x0000a1f4, 0x00204411, 0x000 },
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- { 0x9d000000, 0x00204411, 0x000 },
- { 0x0000001f, 0x40214a20, 0x000 },
- { 0x96000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x00000000, 0xc0201000, 0x000 },
- { 0x0000001f, 0x00211624, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000025, 0x00203623, 0x000 },
- { 0x00000003, 0x00281e23, 0x000 },
- { 0x00000008, 0x00222223, 0x000 },
- { 0xfffff000, 0x00282228, 0x000 },
- { 0x00000000, 0x002920e8, 0x000 },
- { 0x00000027, 0x00203628, 0x000 },
- { 0x00000018, 0x00211e23, 0x000 },
- { 0x00000028, 0x00203627, 0x000 },
- { 0x00000002, 0x00221624, 0x000 },
- { 0x00000000, 0x003014a8, 0x000 },
- { 0x00000026, 0x00203625, 0x000 },
- { 0x00000003, 0x00211a24, 0x000 },
- { 0x10000000, 0x00281a26, 0x000 },
- { 0xefffffff, 0x00283a2e, 0x000 },
- { 0x00000000, 0x004938ce, 0x602 },
- { 0x00000001, 0x40280a20, 0x000 },
- { 0x00000006, 0x40280e20, 0x000 },
- { 0x00000300, 0xc0281220, 0x000 },
- { 0x00000008, 0x00211224, 0x000 },
- { 0x00000000, 0xc0201620, 0x000 },
- { 0x00000000, 0xc0201a20, 0x000 },
- { 0x00000000, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x541 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00002258, 0x00300a24, 0x000 },
- { 0x00040000, 0x00694622, 0x614 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x00020000, 0x00294a26, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x549 },
- { 0x00000000, 0xc0201c10, 0x000 },
- { 0x00000000, 0xc0400000, 0x55b },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x549 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00002258, 0x00300a24, 0x000 },
- { 0x00040000, 0x00694622, 0x614 },
- { 0x00000000, 0xc0201c10, 0x000 },
- { 0x00000000, 0xc0400000, 0x55b },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x54d },
- { 0x00000000, 0xc0201c00, 0x000 },
- { 0x00000000, 0xc0400000, 0x55b },
- { 0x00000004, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x559 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000216d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x1ac00000, 0x554 },
- { 0x9e000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000000, 0x1ae00000, 0x557 },
- { 0x00000000, 0x00401c10, 0x55b },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0400000, 0x000 },
- { 0x00000000, 0x0ee00000, 0x55d },
- { 0x00000000, 0x00600000, 0x5a4 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x56d },
- { 0x0000a2b7, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2b6, 0x00604411, 0x614 },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
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- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x56b },
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- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d1, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x00000001, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x57d },
- { 0x0000a2bb, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2ba, 0x00604411, 0x614 },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
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- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x57b },
- { 0x0000a2d2, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d2, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x00000002, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x58d },
- { 0x0000a2bf, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2be, 0x00604411, 0x614 },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
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- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x58b },
- { 0x0000a2d3, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d3, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x0000a2c3, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2c2, 0x00604411, 0x614 },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
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- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x599 },
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- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d4, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x85000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x0000304a, 0x00204411, 0x000 },
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- { 0x00000000, 0xc0400400, 0x001 },
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- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000005, 0x00204811, 0x000 },
- { 0x0000a1f4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x88000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0xff000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000002, 0x00804811, 0x000 },
- { 0x00000000, 0x0ee00000, 0x5b7 },
- { 0x00001000, 0x00200811, 0x000 },
- { 0x00000034, 0x00203622, 0x000 },
- { 0x00000000, 0x00600000, 0x5bb },
- { 0x00000000, 0x00600000, 0x5a4 },
- { 0x98000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00804811, 0x000 },
- { 0x00000000, 0xc0600000, 0x5bb },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000022, 0x00204811, 0x000 },
- { 0x89000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0xff000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000002, 0x00804811, 0x000 },
- { 0x0000217a, 0xc0204411, 0x000 },
- { 0x00000000, 0x00404811, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
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- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0xff000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000002, 0x00804811, 0x000 },
- { 0x00000000, 0x00600000, 0x5e1 },
- { 0x00002010, 0x00204411, 0x000 },
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- { 0x00002010, 0x00204411, 0x000 },
- { 0x00010000, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x09800000, 0x00204811, 0x000 },
- { 0xffffffff, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x614 },
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- { 0xfffffff7, 0x00281e27, 0x000 },
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- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004217f, 0x00604411, 0x614 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x613 },
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- { 0x00000001, 0x00204811, 0x000 },
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- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x013304ef, 0x059b0239, 0x000 },
- { 0x01b00159, 0x0425059b, 0x000 },
- { 0x021201f6, 0x02390142, 0x000 },
- { 0x0210022e, 0x0289022a, 0x000 },
- { 0x03c2059b, 0x059b059b, 0x000 },
- { 0x05cd05ce, 0x0308059b, 0x000 },
- { 0x059b05a0, 0x03090329, 0x000 },
- { 0x0313026b, 0x032b031d, 0x000 },
- { 0x059b059b, 0x059b059b, 0x000 },
- { 0x059b052c, 0x059b059b, 0x000 },
- { 0x03a5059b, 0x04a2032d, 0x000 },
- { 0x04810433, 0x0423059b, 0x000 },
- { 0x04bb04ed, 0x042704c8, 0x000 },
- { 0x043304f4, 0x033a0365, 0x000 },
- { 0x059b059b, 0x059b059b, 0x000 },
- { 0x059b059b, 0x059b059b, 0x000 },
- { 0x059b059b, 0x05b905a2, 0x000 },
- { 0x059b059b, 0x0007059b, 0x000 },
- { 0x059b059b, 0x059b059b, 0x000 },
- { 0x059b059b, 0x059b059b, 0x000 },
- { 0x03e303d8, 0x03f303f1, 0x000 },
- { 0x03f903f5, 0x03f703fb, 0x000 },
- { 0x04070403, 0x040f040b, 0x000 },
- { 0x04170413, 0x041f041b, 0x000 },
- { 0x059b059b, 0x059b059b, 0x000 },
- { 0x059b059b, 0x059b059b, 0x000 },
- { 0x059b059b, 0x059b059b, 0x000 },
- { 0x00020600, 0x06190006, 0x000 },
-};
-
-static const u32 R600_pfp_microcode[] = {
-0xd40071,
-0xd40072,
-0xca0400,
-0xa00000,
-0x7e828b,
-0x800003,
-0xca0400,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581a8,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0fff0,
-0x042c04,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255403,
-0x7cd580,
-0x259c03,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d4,
-0xd5c01e,
-0xca0800,
-0x80001b,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000d,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000d,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800054,
-0xd40073,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xd48060,
-0xd4401e,
-0x800002,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800002,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001b9,
-0xd4c01e,
-0xc6083e,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800002,
-0x062001,
-0xc6083e,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x80007a,
-0xd42013,
-0xc6083e,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x80008e,
-0x000000,
-0xc41432,
-0xc6183e,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800002,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xd40073,
-0xe4015e,
-0xd4001e,
-0x8001b9,
-0x062001,
-0x0a2001,
-0xd60074,
-0xc40836,
-0xc61040,
-0x988007,
-0xcc3835,
-0x95010f,
-0xd4001f,
-0xd46062,
-0x800002,
-0xd42062,
-0xcc1433,
-0x8401bc,
-0xd40070,
-0xd5401e,
-0x800002,
-0xee001e,
-0xca0c00,
-0xca1000,
-0xd4c01a,
-0x8401bc,
-0xd5001a,
-0xcc0443,
-0x35101f,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001b9,
-0xd4006d,
-0x344401,
-0xcc0c44,
-0x98403a,
-0xcc2c46,
-0x958004,
-0xcc0445,
-0x8001b9,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x8400f3,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x8400f3,
-0xcc1003,
-0x988017,
-0x043808,
-0x8400f3,
-0xcc1003,
-0x988013,
-0x043804,
-0x8400f3,
-0xcc1003,
-0x988014,
-0xcc1047,
-0x9a8009,
-0xcc1448,
-0x9840da,
-0xd4006d,
-0xcc1844,
-0xd5001a,
-0xd5401a,
-0x8000cc,
-0xd5801a,
-0x96c0d3,
-0xd4006d,
-0x8001b9,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800002,
-0xec007f,
-0x9ac0ca,
-0xd4006d,
-0x8001b9,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001b9,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809c,
-0xd4006d,
-0x98409a,
-0xd4006e,
-0xcc0847,
-0xcc0c48,
-0xcc1044,
-0xd4801a,
-0xd4c01a,
-0x800104,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482d8,
-0xca0c00,
-0xd4401e,
-0x800002,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800002,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x9882bc,
-0x000000,
-0x8401bc,
-0xd7806f,
-0x800002,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x9902af,
-0x7c738b,
-0x8401bc,
-0xd7806f,
-0x800002,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984296,
-0x000000,
-0x800164,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800002,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc1049,
-0x990004,
-0xd40071,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800002,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x95001f,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x7d8380,
-0xd5806f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0x8001b9,
-0xd60074,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800002,
-0xee001e,
-0x800002,
-0xee001f,
-0xd4001f,
-0x800002,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010174,
-0x02017b,
-0x030090,
-0x040080,
-0x050005,
-0x060040,
-0x070033,
-0x08012f,
-0x090047,
-0x0a0037,
-0x1001b7,
-0x1700a4,
-0x22013d,
-0x23014c,
-0x2000b5,
-0x240128,
-0x27004e,
-0x28006b,
-0x2a0061,
-0x2b0053,
-0x2f0066,
-0x320088,
-0x340182,
-0x3c0159,
-0x3f0073,
-0x41018f,
-0x440131,
-0x550176,
-0x56017d,
-0x60000c,
-0x610035,
-0x620039,
-0x630039,
-0x640039,
-0x650039,
-0x660039,
-0x670039,
-0x68003b,
-0x690042,
-0x6a0049,
-0x6b0049,
-0x6c0049,
-0x6d0049,
-0x6e0049,
-0x6f0049,
-0x7301b7,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-};
-
-static const u32 RV610_cp_microcode[][3] = {
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0000ffff, 0x00284621, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00000000, 0x00e00000, 0x000 },
- { 0x00010000, 0xc0294620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x00000000, 0x00600000, 0x631 },
- { 0x00000000, 0x00600000, 0x645 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000f00, 0x00281622, 0x000 },
- { 0x00000008, 0x00211625, 0x000 },
- { 0x00000018, 0x00203625, 0x000 },
- { 0x8d000000, 0x00204411, 0x000 },
- { 0x00000004, 0x002f0225, 0x000 },
- { 0x00000000, 0x0ce00000, 0x018 },
- { 0x00412000, 0x00404811, 0x019 },
- { 0x00422000, 0x00204811, 0x000 },
- { 0x8e000000, 0x00204411, 0x000 },
- { 0x00000028, 0x00204a2d, 0x000 },
- { 0x90000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x0000000c, 0x00211622, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x00000019, 0x00211a22, 0x000 },
- { 0x00000004, 0x00281a26, 0x000 },
- { 0x00000000, 0x002914c5, 0x000 },
- { 0x00000019, 0x00203625, 0x000 },
- { 0x00000000, 0x003a1402, 0x000 },
- { 0x00000016, 0x00211625, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0xfffffffc, 0x00280e23, 0x000 },
- { 0x00000000, 0x002914a3, 0x000 },
- { 0x00000017, 0x00203625, 0x000 },
- { 0x00008000, 0x00280e22, 0x000 },
- { 0x00000007, 0x00220e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x20000000, 0x00280e22, 0x000 },
- { 0x00000006, 0x00210e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x00000000, 0x00220222, 0x000 },
- { 0x00000000, 0x14e00000, 0x038 },
- { 0x00000000, 0x2ee00000, 0x035 },
- { 0x00000000, 0x2ce00000, 0x037 },
- { 0x00000000, 0x00400e2d, 0x039 },
- { 0x00000008, 0x00200e2d, 0x000 },
- { 0x00000009, 0x0040122d, 0x046 },
- { 0x00000001, 0x00400e2d, 0x039 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x03e },
- { 0x00000008, 0x00401c11, 0x041 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x0000000f, 0x00281e27, 0x000 },
- { 0x00000003, 0x00221e27, 0x000 },
- { 0x7fc00000, 0x00281a23, 0x000 },
- { 0x00000014, 0x00211a26, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000008, 0x00221a26, 0x000 },
- { 0x00000000, 0x00290cc7, 0x000 },
- { 0x00000027, 0x00203624, 0x000 },
- { 0x00007f00, 0x00281221, 0x000 },
- { 0x00001400, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x04b },
- { 0x00000001, 0x00290e23, 0x000 },
- { 0x0000000e, 0x00203623, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfff80000, 0x00294a23, 0x000 },
- { 0x00000000, 0x003a2c02, 0x000 },
- { 0x00000002, 0x00220e2b, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x0000000f, 0x00203623, 0x000 },
- { 0x00001fff, 0x00294a23, 0x000 },
- { 0x00000027, 0x00204a2d, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000029, 0x00200e2d, 0x000 },
- { 0x060a0200, 0x00294a23, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00210222, 0x000 },
- { 0x00000000, 0x14e00000, 0x061 },
- { 0x00000000, 0x2ee00000, 0x05f },
- { 0x00000000, 0x2ce00000, 0x05e },
- { 0x00000000, 0x00400e2d, 0x062 },
- { 0x00000001, 0x00400e2d, 0x062 },
- { 0x0000000a, 0x00200e2d, 0x000 },
- { 0x0000000b, 0x0040122d, 0x06a },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x7fc00000, 0x00281623, 0x000 },
- { 0x00000014, 0x00211625, 0x000 },
- { 0x00000001, 0x00331625, 0x000 },
- { 0x80000000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00290ca3, 0x000 },
- { 0x3ffffc00, 0x00290e23, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x06d },
- { 0x00000100, 0x00401c11, 0x070 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x000000f0, 0x00281e27, 0x000 },
- { 0x00000004, 0x00221e27, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0xfffff0ff, 0x00281a30, 0x000 },
- { 0x0000a028, 0x00204411, 0x000 },
- { 0x00000000, 0x002948e6, 0x000 },
- { 0x0000a018, 0x00204411, 0x000 },
- { 0x3fffffff, 0x00284a23, 0x000 },
- { 0x0000a010, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000030, 0x0020162d, 0x000 },
- { 0x00000002, 0x00291625, 0x000 },
- { 0x00000030, 0x00203625, 0x000 },
- { 0x00000025, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a3, 0x000 },
- { 0x00000000, 0x0cc00000, 0x083 },
- { 0x00000026, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a4, 0x000 },
- { 0x00000000, 0x0cc00000, 0x084 },
- { 0x00000000, 0x00400000, 0x08a },
- { 0x00000025, 0x00203623, 0x000 },
- { 0x00000026, 0x00203624, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x08a },
- { 0x00000000, 0x00600000, 0x668 },
- { 0x00000000, 0x00600000, 0x65c },
- { 0x00000002, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x08d },
- { 0x00000012, 0xc0403620, 0x093 },
- { 0x00000000, 0x2ee00000, 0x091 },
- { 0x00000000, 0x2ce00000, 0x090 },
- { 0x00000002, 0x00400e2d, 0x092 },
- { 0x00000003, 0x00400e2d, 0x092 },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000012, 0x00203623, 0x000 },
- { 0x00000003, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x098 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x0a0 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x2ee00000, 0x09e },
- { 0x00000000, 0x2ce00000, 0x09d },
- { 0x00000002, 0x00400e2d, 0x09f },
- { 0x00000003, 0x00400e2d, 0x09f },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x003f0000, 0x00280e23, 0x000 },
- { 0x00000010, 0x00210e23, 0x000 },
- { 0x00000011, 0x00203623, 0x000 },
- { 0x0000001e, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0a7 },
- { 0x00000016, 0xc0203620, 0x000 },
- { 0x0000001f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0aa },
- { 0x00000015, 0xc0203620, 0x000 },
- { 0x00000008, 0x00210e2b, 0x000 },
- { 0x0000007f, 0x00280e23, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0e1 },
- { 0x00000000, 0x27000000, 0x000 },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ae00000, 0x0b3 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x0000000c, 0x00221e30, 0x000 },
- { 0x99800000, 0x00204411, 0x000 },
- { 0x00000004, 0x0020122d, 0x000 },
- { 0x00000008, 0x00221224, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00291ce4, 0x000 },
- { 0x00000000, 0x00604807, 0x12f },
- { 0x9b000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x9c000000, 0x00204411, 0x000 },
- { 0x00000000, 0x0033146f, 0x000 },
- { 0x00000001, 0x00333e23, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0x00203c05, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e007, 0x00204411, 0x000 },
- { 0x0000000f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0cb },
- { 0x00f8ff08, 0x00204811, 0x000 },
- { 0x98000000, 0x00404811, 0x0dc },
- { 0x000000f0, 0x00280e22, 0x000 },
- { 0x000000a0, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x0da },
- { 0x00000011, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0d5 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0d4 },
- { 0x00003f00, 0x00400c11, 0x0d6 },
- { 0x00001f00, 0x00400c11, 0x0d6 },
- { 0x00000f00, 0x00200c11, 0x000 },
- { 0x00380009, 0x00294a23, 0x000 },
- { 0x3f000000, 0x00280e2b, 0x000 },
- { 0x00000002, 0x00220e23, 0x000 },
- { 0x00000007, 0x00494a23, 0x0dc },
- { 0x00380f09, 0x00204811, 0x000 },
- { 0x68000007, 0x00204811, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000a202, 0x00204411, 0x000 },
- { 0x00ff0000, 0x00280e22, 0x000 },
- { 0x00000080, 0x00294a23, 0x000 },
- { 0x00000027, 0x00200e2d, 0x000 },
- { 0x00000026, 0x0020122d, 0x000 },
- { 0x00000000, 0x002f0083, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0ea },
- { 0x00000000, 0x00600000, 0x662 },
- { 0x00000000, 0x00400000, 0x0eb },
- { 0x00000000, 0x00600000, 0x665 },
- { 0x00000007, 0x0020222d, 0x000 },
- { 0x00000005, 0x00220e22, 0x000 },
- { 0x00100000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x000000ef, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0x00000003, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x0f8 },
- { 0x0000000b, 0x00210228, 0x000 },
- { 0x00000000, 0x14c00000, 0x0f8 },
- { 0x00000400, 0x00292228, 0x000 },
- { 0x00000014, 0x00203628, 0x000 },
- { 0x0000001c, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x0fd },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000001e, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x10b },
- { 0x0000a30f, 0x00204411, 0x000 },
- { 0x00000011, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x104 },
- { 0xffffffff, 0x00404811, 0x10b },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x107 },
- { 0x0000ffff, 0x00404811, 0x10b },
- { 0x00000004, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x10a },
- { 0x000000ff, 0x00404811, 0x10b },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0002c400, 0x00204411, 0x000 },
- { 0x0000001f, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x112 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x00000013, 0x00203623, 0x000 },
- { 0x00000018, 0x40224a20, 0x000 },
- { 0x00000010, 0xc0424a20, 0x114 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x00000013, 0x00203623, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000000a, 0x00201011, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x11b },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00531224, 0x117 },
- { 0xffbfffff, 0x00283a2e, 0x000 },
- { 0x0000001b, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x12e },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0x00000018, 0x00220e30, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e00e, 0x00204411, 0x000 },
- { 0x07f8ff08, 0x00204811, 0x000 },
- { 0x00000000, 0x00294a23, 0x000 },
- { 0x0000001c, 0x00201e2d, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x00800000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204806, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x68d },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x68c },
- { 0x00000004, 0x00404c11, 0x135 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x0000001c, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68d },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x13c },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00000000, 0x00600000, 0x160 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40280620, 0x000 },
- { 0x00000010, 0xc0210a20, 0x000 },
- { 0x00000000, 0x00341461, 0x000 },
- { 0x00000000, 0x00741882, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x147 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x160 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0681a20, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x158 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000001, 0x00300a2f, 0x000 },
- { 0x00000001, 0x00210a22, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600000, 0x18f },
- { 0x00000000, 0x00600000, 0x1a0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00202c08, 0x000 },
- { 0x00000000, 0x00202411, 0x000 },
- { 0x00000000, 0x00202811, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000002, 0x00221e29, 0x000 },
- { 0x00000000, 0x007048eb, 0x19c },
- { 0x00000000, 0x00600000, 0x2bb },
- { 0x00000001, 0x40330620, 0x000 },
- { 0x00000000, 0xc0302409, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ae00000, 0x181 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x00000000, 0x00400000, 0x186 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x186 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000001, 0x00530621, 0x182 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0604800, 0x197 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000011, 0x0020062d, 0x000 },
- { 0x00000000, 0x0078042a, 0x2fb },
- { 0x00000000, 0x00202809, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x174 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000210, 0x00600411, 0x315 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x194 },
- { 0x00000015, 0xc0203620, 0x000 },
- { 0x00000016, 0xc0203620, 0x000 },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x46000000, 0x00600811, 0x1b2 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x19b },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000021, 0x00804811, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40281620, 0x000 },
- { 0x00000010, 0xc0811a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000008, 0x00221e30, 0x000 },
- { 0x00000029, 0x00201a2d, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfffbff09, 0x00204811, 0x000 },
- { 0x0000000f, 0x0020222d, 0x000 },
- { 0x00001fff, 0x00294a28, 0x000 },
- { 0x00000006, 0x0020222d, 0x000 },
- { 0x00000000, 0x002920e8, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a26, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000100, 0x00201811, 0x000 },
- { 0x00000008, 0x00621e28, 0x12f },
- { 0x00000008, 0x00822228, 0x000 },
- { 0x0002c000, 0x00204411, 0x000 },
- { 0x00000015, 0x00600e2d, 0x1bd },
- { 0x00000016, 0x00600e2d, 0x1bd },
- { 0x0000c008, 0x00204411, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0x00000000, 0x14c00000, 0x1b9 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x39000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00804802, 0x000 },
- { 0x00000018, 0x00202e2d, 0x000 },
- { 0x00000000, 0x003b0d63, 0x000 },
- { 0x00000008, 0x00224a23, 0x000 },
- { 0x00000010, 0x00224a23, 0x000 },
- { 0x00000018, 0x00224a23, 0x000 },
- { 0x00000000, 0x00804803, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00001000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00000007, 0x0021062f, 0x000 },
- { 0x00000013, 0x00200a2d, 0x000 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000ffff, 0x40282220, 0x000 },
- { 0x0000000f, 0x00262228, 0x000 },
- { 0x00000010, 0x40212620, 0x000 },
- { 0x0000000f, 0x00262629, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001b, 0x00204811, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1e0 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000081, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000080, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1dc },
- { 0x00000000, 0x00600000, 0x1e9 },
- { 0x00000001, 0x00531e27, 0x1d8 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000001f, 0x00280a22, 0x000 },
- { 0x0000001f, 0x00282a2a, 0x000 },
- { 0x00000001, 0x00530621, 0x1d1 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000002, 0x00304a2f, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000001, 0x00301e2f, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x1e9 },
- { 0x00000001, 0x00531e27, 0x1e5 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x0000000f, 0x00260e23, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000000f, 0x00261224, 0x000 },
- { 0x00000000, 0x00201411, 0x000 },
- { 0x00000000, 0x00601811, 0x2bb },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022b, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1f8 },
- { 0x00000010, 0x00221628, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a29, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x0020480a, 0x000 },
- { 0x00000000, 0x00202c11, 0x000 },
- { 0x00000010, 0x00221623, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a24, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x00731503, 0x205 },
- { 0x00000000, 0x00201805, 0x000 },
- { 0x00000000, 0x00731524, 0x205 },
- { 0x00000000, 0x002d14c5, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00000000, 0x00202003, 0x000 },
- { 0x00000000, 0x00802404, 0x000 },
- { 0x0000000f, 0x00210225, 0x000 },
- { 0x00000000, 0x14c00000, 0x68c },
- { 0x00000000, 0x002b1405, 0x000 },
- { 0x00000001, 0x00901625, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00294a22, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a21, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000ffff, 0x40281220, 0x000 },
- { 0x00000010, 0xc0211a20, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211620, 0x000 },
- { 0x00000000, 0x00741465, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00000001, 0x00330621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0cc00000, 0x219 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x212 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x645 },
- { 0x00000000, 0x0040040f, 0x213 },
- { 0x00000000, 0x00600000, 0x631 },
- { 0x00000000, 0x00600000, 0x645 },
- { 0x00000210, 0x00600411, 0x315 },
- { 0x00000000, 0x00600000, 0x1a0 },
- { 0x00000000, 0x00600000, 0x19c },
- { 0x00000000, 0x00600000, 0x2bb },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ae00000, 0x232 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x00000000, 0x00400000, 0x236 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x236 },
- { 0x00000000, 0xc0404800, 0x233 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x00600411, 0x2fb },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x631 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000018, 0x40210a20, 0x000 },
- { 0x00000003, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x24c },
- { 0x00000014, 0x0020222d, 0x000 },
- { 0x00080101, 0x00292228, 0x000 },
- { 0x00000014, 0x00203628, 0x000 },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x251 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000010, 0x00600411, 0x315 },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x00000000, 0x00600000, 0x27c },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000001, 0x00211e27, 0x000 },
- { 0x00000000, 0x14e00000, 0x26a },
- { 0x00000012, 0x00201e2d, 0x000 },
- { 0x0000ffff, 0x00281e27, 0x000 },
- { 0x00000000, 0x00341c27, 0x000 },
- { 0x00000000, 0x12c00000, 0x25f },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e5, 0x000 },
- { 0x00000000, 0x08c00000, 0x262 },
- { 0x00000000, 0x00201407, 0x000 },
- { 0x00000012, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00211e27, 0x000 },
- { 0x00000000, 0x00341c47, 0x000 },
- { 0x00000000, 0x12c00000, 0x267 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x08c00000, 0x26a },
- { 0x00000000, 0x00201807, 0x000 },
- { 0x00000000, 0x00600000, 0x2c1 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000000, 0x00342023, 0x000 },
- { 0x00000000, 0x12c00000, 0x272 },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x271 },
- { 0x00000016, 0x00404811, 0x276 },
- { 0x00000018, 0x00404811, 0x276 },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x275 },
- { 0x00000017, 0x00404811, 0x276 },
- { 0x00000019, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00604411, 0x2e9 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x256 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000010, 0x40210620, 0x000 },
- { 0x0000ffff, 0xc0280a20, 0x000 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0881a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x00000000, 0x00600000, 0x631 },
- { 0x00000000, 0xc0600000, 0x2a3 },
- { 0x00000005, 0x00200a2d, 0x000 },
- { 0x00000008, 0x00220a22, 0x000 },
- { 0x0000002b, 0x00201a2d, 0x000 },
- { 0x0000001c, 0x00201e2d, 0x000 },
- { 0x00007000, 0x00281e27, 0x000 },
- { 0x00000000, 0x00311ce6, 0x000 },
- { 0x0000002a, 0x00201a2d, 0x000 },
- { 0x0000000c, 0x00221a26, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x06e00000, 0x292 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x0000002b, 0x00203623, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00691ce2, 0x12f },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x29d },
- { 0x00000001, 0x00333e2f, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000001c, 0x00403627, 0x000 },
- { 0x0000000c, 0xc0220a20, 0x000 },
- { 0x00000029, 0x00203622, 0x000 },
- { 0x00000028, 0xc0403620, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000009, 0x00204811, 0x000 },
- { 0xa1000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce3, 0x000 },
- { 0x00000021, 0x00203627, 0x000 },
- { 0x00000022, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce4, 0x000 },
- { 0x00000022, 0x00203627, 0x000 },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a3, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x00000023, 0x00203627, 0x000 },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x00000024, 0x00803627, 0x000 },
- { 0x00000021, 0x00203623, 0x000 },
- { 0x00000022, 0x00203624, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000023, 0x00203627, 0x000 },
- { 0x00000000, 0x00311cc4, 0x000 },
- { 0x00000024, 0x00803627, 0x000 },
- { 0x0000001a, 0x00203627, 0x000 },
- { 0x0000001b, 0x00203628, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14c00000, 0x2dc },
- { 0x00000000, 0x00400000, 0x2d9 },
- { 0x0000001a, 0x00203627, 0x000 },
- { 0x0000001b, 0x00203628, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2d9 },
- { 0x00000003, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2dc },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e1, 0x000 },
- { 0x00000000, 0x02c00000, 0x2dc },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a1, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2dc },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e2, 0x000 },
- { 0x00000000, 0x02c00000, 0x2dc },
- { 0x00000022, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2dc },
- { 0x00000000, 0x00600000, 0x668 },
- { 0x00000000, 0x00600000, 0x2b5 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x00000000, 0x00600000, 0x2b5 },
- { 0x00000000, 0x00600000, 0x65f },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x00000000, 0x00600000, 0x2a7 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x0000001a, 0x00201e2d, 0x000 },
- { 0x0000001b, 0x0080222d, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca1, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x003808c5, 0x000 },
- { 0x00000000, 0x00300841, 0x000 },
- { 0x00000001, 0x00220a22, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000017, 0x0020222d, 0x000 },
- { 0x00000000, 0x14c00000, 0x318 },
- { 0xffffffef, 0x00280621, 0x000 },
- { 0x00000014, 0x0020222d, 0x000 },
- { 0x0000f8e0, 0x00204411, 0x000 },
- { 0x00000000, 0x00294901, 0x000 },
- { 0x00000000, 0x00894901, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00804811, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x97000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00002257, 0x00204411, 0x000 },
- { 0x00000003, 0xc0484a20, 0x000 },
- { 0x0000225d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x645 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x00000001, 0x40304a20, 0x000 },
- { 0x00000002, 0xc0304a20, 0x000 },
- { 0x00000001, 0x00530a22, 0x34b },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000018, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68d },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x354 },
- { 0x00000014, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x364 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00604802, 0x36e },
- { 0x00002100, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000004, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x36a },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x35f },
- { 0x00000028, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5c0 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x35f },
- { 0x0000002c, 0x00203626, 0x000 },
- { 0x00000049, 0x00201811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000000, 0x002f0226, 0x000 },
- { 0x00000000, 0x0cc00000, 0x370 },
- { 0x0000002c, 0x00801a2d, 0x000 },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x00000015, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x386 },
- { 0x00000006, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3b1 },
- { 0x00000016, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3b5 },
- { 0x00000020, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x39c },
- { 0x0000000f, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3a8 },
- { 0x00000010, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3a8 },
- { 0x0000001e, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x390 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x08000000, 0x00290a22, 0x000 },
- { 0x00000003, 0x40210e20, 0x000 },
- { 0x0000000c, 0xc0211220, 0x000 },
- { 0x00080000, 0x00281224, 0x000 },
- { 0x00000014, 0xc0221620, 0x000 },
- { 0x00000000, 0x002914a4, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x002948a2, 0x000 },
- { 0x0000a1fe, 0x00204411, 0x000 },
- { 0x00000000, 0x00404803, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68d },
- { 0x00000015, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x392 },
- { 0x0000210e, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000017, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68d },
- { 0x00000003, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x39e },
- { 0x00002108, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x80000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000010, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x3ae },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000006, 0x00404811, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36e },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x0000001d, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x3ce },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000018, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68d },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x3c0 },
- { 0x00002100, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0xbabecafe, 0x00204811, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
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- { 0x00000004, 0x00404811, 0x000 },
- { 0x00002170, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000a, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x3d3 },
- { 0x8c000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00003fff, 0x40280a20, 0x000 },
- { 0x80000000, 0x40280e20, 0x000 },
- { 0x40000000, 0xc0281220, 0x000 },
- { 0x00040000, 0x00694622, 0x68d },
- { 0x00000000, 0x00201410, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3e1 },
- { 0x00000000, 0xc0401800, 0x3e4 },
- { 0x00003fff, 0xc0281a20, 0x000 },
- { 0x00040000, 0x00694626, 0x68d },
- { 0x00000000, 0x00201810, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3e7 },
- { 0x00000000, 0xc0401c00, 0x3ea },
- { 0x00003fff, 0xc0281e20, 0x000 },
- { 0x00040000, 0x00694627, 0x68d },
- { 0x00000000, 0x00201c10, 0x000 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0x002820c5, 0x000 },
- { 0x00000000, 0x004948e8, 0x000 },
- { 0xa5800000, 0x00200811, 0x000 },
- { 0x00002000, 0x00200c11, 0x000 },
- { 0x83000000, 0x00604411, 0x412 },
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- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x0000001f, 0xc0210220, 0x000 },
- { 0x00000000, 0x14c00000, 0x3f7 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0000ffff, 0xc0481220, 0x3ff },
- { 0xa7800000, 0x00200811, 0x000 },
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- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
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- { 0x00000000, 0x00304883, 0x000 },
- { 0x84000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x1d000000, 0x000 },
- { 0x83000000, 0x00604411, 0x412 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0xa9800000, 0x00200811, 0x000 },
- { 0x0000c000, 0x00400c11, 0x3fa },
- { 0xab800000, 0x00200811, 0x000 },
- { 0x0000f8e0, 0x00400c11, 0x3fa },
- { 0xad800000, 0x00200811, 0x000 },
- { 0x0000f880, 0x00400c11, 0x3fa },
- { 0xb3800000, 0x00200811, 0x000 },
- { 0x0000f3fc, 0x00400c11, 0x3fa },
- { 0xaf800000, 0x00200811, 0x000 },
- { 0x0000e000, 0x00400c11, 0x3fa },
- { 0xb1800000, 0x00200811, 0x000 },
- { 0x0000f000, 0x00400c11, 0x3fa },
- { 0x83000000, 0x00204411, 0x000 },
- { 0x00002148, 0x00204811, 0x000 },
- { 0x84000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x1d000000, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x01182000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0218a000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0318c000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0418f8e0, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0518f880, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0618e000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0718f000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0818f3fc, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00000030, 0x00200a2d, 0x000 },
- { 0x00000000, 0xc0290c40, 0x000 },
- { 0x00000030, 0x00203623, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x86000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00404801, 0x000 },
- { 0x85000000, 0xc0204411, 0x000 },
- { 0x00000000, 0x00404801, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x00000018, 0x40210220, 0x000 },
- { 0x00000000, 0x14c00000, 0x445 },
- { 0x00800000, 0xc0494a20, 0x446 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x68d },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000000, 0x00404c02, 0x44b },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x00000000, 0xc0201000, 0x000 },
- { 0x00000000, 0xc0201400, 0x000 },
- { 0x00000000, 0xc0201800, 0x000 },
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- { 0x00004500, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x459 },
- { 0x00000000, 0xc0202000, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
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- { 0x00000010, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x461 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00040000, 0x00694624, 0x68d },
- { 0x00000000, 0x00400000, 0x466 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
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- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000000, 0x00604805, 0x692 },
- { 0x00000000, 0x002824f0, 0x000 },
- { 0x00000007, 0x00280a23, 0x000 },
- { 0x00000001, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x46d },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x04e00000, 0x486 },
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- { 0x00000000, 0x00400000, 0x493 },
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- { 0x00000000, 0x0ae00000, 0x481 },
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- { 0x00000000, 0x06e00000, 0x486 },
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- { 0x00000000, 0x08e00000, 0x486 },
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- { 0x00000000, 0xc0200000, 0x000 },
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- { 0x00000000, 0x0ae00000, 0x499 },
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- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0400000, 0x000 },
- { 0x00000000, 0x00404c08, 0x459 },
- { 0x00000000, 0xc0200800, 0x000 },
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- { 0x00000000, 0x00210225, 0x000 },
- { 0x00000000, 0x14e00000, 0x4a3 },
- { 0x00040000, 0xc0494a20, 0x4a4 },
- { 0xfffbffff, 0xc0284a20, 0x000 },
- { 0x00000000, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x4b0 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x00210224, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000c, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x4ac },
- { 0xa0000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000004, 0x00204811, 0x000 },
- { 0x0000216b, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204810, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
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- { 0x0000216c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204810, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00400000, 0x4aa },
- { 0x00000000, 0xc0210a20, 0x000 },
- { 0x00000000, 0x14c00000, 0x4c3 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000216d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0604800, 0x692 },
- { 0x00000000, 0x00400000, 0x4c7 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00040000, 0xc0294620, 0x000 },
- { 0x00000000, 0xc0600000, 0x68d },
- { 0x00000001, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x4ce },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x00000000, 0xc0204400, 0x000 },
- { 0x00000000, 0xc0404810, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68d },
- { 0x00000000, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x4d0 },
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- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
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- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000003, 0x00333e2f, 0x000 },
- { 0x00000001, 0x00210221, 0x000 },
- { 0x00000000, 0x14e00000, 0x500 },
- { 0x0000002c, 0x00200a2d, 0x000 },
- { 0x00040000, 0x18e00c11, 0x4ef },
- { 0x00000001, 0x00333e2f, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000008, 0x00300a22, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
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- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xd8c04800, 0x4e3 },
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- { 0x00000000, 0x00204802, 0x000 },
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- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
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- { 0x00000000, 0xc0204800, 0x000 },
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- { 0x00000000, 0x00400000, 0x4aa },
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- { 0x00000000, 0x00600000, 0x00b },
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- { 0x00000000, 0xc0400400, 0x001 },
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- { 0xb9000000, 0x00204411, 0x000 },
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- { 0xba000000, 0x00204411, 0x000 },
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- { 0x81000000, 0x00204411, 0x000 },
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- { 0x00000000, 0x0cc00000, 0x519 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0x14c00000, 0x52e },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x0000001c, 0x00203623, 0x000 },
- { 0x0000002b, 0x00203623, 0x000 },
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- { 0x00000028, 0x00203623, 0x000 },
- { 0x00000017, 0x00203623, 0x000 },
- { 0x00000025, 0x00203623, 0x000 },
- { 0x00000026, 0x00203623, 0x000 },
- { 0x00000015, 0x00203623, 0x000 },
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- { 0xffffe000, 0x00200c11, 0x000 },
- { 0x00000021, 0x00203623, 0x000 },
- { 0x00000022, 0x00203623, 0x000 },
- { 0x00001fff, 0x00200c11, 0x000 },
- { 0x00000023, 0x00203623, 0x000 },
- { 0x00000024, 0x00203623, 0x000 },
- { 0xf1ffffff, 0x00283a2e, 0x000 },
- { 0x0000001a, 0xc0220e20, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x0000002a, 0x40203620, 0x000 },
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- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1f4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x00000030, 0x00203623, 0x000 },
- { 0x9d000000, 0x00204411, 0x000 },
- { 0x0000001f, 0x40214a20, 0x000 },
- { 0x96000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x00000000, 0xc0201000, 0x000 },
- { 0x0000001f, 0x00211624, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x0000001d, 0x00203623, 0x000 },
- { 0x00000003, 0x00281e23, 0x000 },
- { 0x00000008, 0x00222223, 0x000 },
- { 0xfffff000, 0x00282228, 0x000 },
- { 0x00000000, 0x002920e8, 0x000 },
- { 0x0000001f, 0x00203628, 0x000 },
- { 0x00000018, 0x00211e23, 0x000 },
- { 0x00000020, 0x00203627, 0x000 },
- { 0x00000002, 0x00221624, 0x000 },
- { 0x00000000, 0x003014a8, 0x000 },
- { 0x0000001e, 0x00203625, 0x000 },
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- { 0x10000000, 0x00281a26, 0x000 },
- { 0xefffffff, 0x00283a2e, 0x000 },
- { 0x00000000, 0x004938ce, 0x67b },
- { 0x00000001, 0x40280a20, 0x000 },
- { 0x00000006, 0x40280e20, 0x000 },
- { 0x00000300, 0xc0281220, 0x000 },
- { 0x00000008, 0x00211224, 0x000 },
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- { 0x00000000, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x566 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00002258, 0x00300a24, 0x000 },
- { 0x00040000, 0x00694622, 0x68d },
- { 0x00002169, 0x00204411, 0x000 },
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- { 0x00020000, 0x00294a26, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x56e },
- { 0x00000000, 0xc0201c10, 0x000 },
- { 0x00000000, 0xc0400000, 0x57c },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x56e },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00002258, 0x00300a24, 0x000 },
- { 0x00040000, 0x00694622, 0x68d },
- { 0x00000000, 0xc0201c10, 0x000 },
- { 0x00000000, 0xc0400000, 0x57c },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x572 },
- { 0x00000000, 0xc0201c00, 0x000 },
- { 0x00000000, 0xc0400000, 0x57c },
- { 0x00000004, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x57a },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000216d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0604800, 0x692 },
- { 0x00000000, 0x00401c10, 0x57c },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0400000, 0x000 },
- { 0x00000000, 0x0ee00000, 0x57e },
- { 0x00000000, 0x00600000, 0x5c9 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x58f },
- { 0x0000a2b7, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2b6, 0x00604411, 0x68d },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x0000a2c4, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x58d },
- { 0x0000a2d1, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d1, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x00000001, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5a0 },
- { 0x0000a2bb, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2ba, 0x00604411, 0x68d },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x0000a2c5, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x59e },
- { 0x0000a2d2, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d2, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x00000002, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5b1 },
- { 0x0000a2bf, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2be, 0x00604411, 0x68d },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x0000a2c6, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x5af },
- { 0x0000a2d3, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d3, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x0000a2c3, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2c2, 0x00604411, 0x68d },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x0000a2c7, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x5be },
- { 0x0000a2d4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d4, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x85000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x0000304a, 0x00204411, 0x000 },
- { 0x01000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00400000, 0x5c4 },
- { 0xa4000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0xc0600000, 0x5c9 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000002c, 0x00203621, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000000, 0x002f0230, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5d0 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000030, 0x00403621, 0x5e3 },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00007e00, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x5e3 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a092, 0x00604411, 0x68d },
- { 0x00000031, 0x00203630, 0x000 },
- { 0x0004a093, 0x00604411, 0x68d },
- { 0x00000032, 0x00203630, 0x000 },
- { 0x0004a2b6, 0x00604411, 0x68d },
- { 0x00000033, 0x00203630, 0x000 },
- { 0x0004a2ba, 0x00604411, 0x68d },
- { 0x00000034, 0x00203630, 0x000 },
- { 0x0004a2be, 0x00604411, 0x68d },
- { 0x00000035, 0x00203630, 0x000 },
- { 0x0004a2c2, 0x00604411, 0x68d },
- { 0x00000036, 0x00203630, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x00000005, 0x00204811, 0x000 },
- { 0x0000a1f4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x88000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000001, 0x002f0230, 0x000 },
- { 0x00000000, 0x0ce00000, 0x62c },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x62c },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00007e00, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x605 },
- { 0x0000a092, 0x00204411, 0x000 },
- { 0x00000031, 0x00204a2d, 0x000 },
- { 0x0000a093, 0x00204411, 0x000 },
- { 0x00000032, 0x00204a2d, 0x000 },
- { 0x0000a2b6, 0x00204411, 0x000 },
- { 0x00000033, 0x00204a2d, 0x000 },
- { 0x0000a2ba, 0x00204411, 0x000 },
- { 0x00000034, 0x00204a2d, 0x000 },
- { 0x0000a2be, 0x00204411, 0x000 },
- { 0x00000035, 0x00204a2d, 0x000 },
- { 0x0000a2c2, 0x00204411, 0x000 },
- { 0x00000036, 0x00204a2d, 0x000 },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x000001ff, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x62b },
- { 0x00000000, 0x00210221, 0x000 },
- { 0x00000000, 0x14c00000, 0x60e },
- { 0x0004a003, 0x00604411, 0x68d },
- { 0x0000a003, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00000001, 0x00210621, 0x000 },
- { 0x00000000, 0x14c00000, 0x613 },
- { 0x0004a010, 0x00604411, 0x68d },
- { 0x0000a010, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00000001, 0x00210621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x62b },
- { 0x0004a011, 0x00604411, 0x68d },
- { 0x0000a011, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a012, 0x00604411, 0x68d },
- { 0x0000a012, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a013, 0x00604411, 0x68d },
- { 0x0000a013, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a014, 0x00604411, 0x68d },
- { 0x0000a014, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a015, 0x00604411, 0x68d },
- { 0x0000a015, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a016, 0x00604411, 0x68d },
- { 0x0000a016, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a017, 0x00604411, 0x68d },
- { 0x0000a017, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x0000002c, 0x0080062d, 0x000 },
- { 0xff000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000002, 0x00804811, 0x000 },
- { 0x00000000, 0x0ee00000, 0x63d },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00000002, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x63b },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x00001000, 0x00200811, 0x000 },
- { 0x0000002b, 0x00203622, 0x000 },
- { 0x00000000, 0x00600000, 0x641 },
- { 0x00000000, 0x00600000, 0x5c9 },
- { 0x98000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00804811, 0x000 },
- { 0x00000000, 0xc0600000, 0x641 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000022, 0x00204811, 0x000 },
- { 0x89000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00404811, 0x62d },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00404811, 0x62d },
- { 0x00000000, 0x00600000, 0x65c },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0xc0204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36e },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00010000, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x09800000, 0x00204811, 0x000 },
- { 0xffffffff, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x68d },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000004, 0x00404c11, 0x656 },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000004, 0x00291e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0xfffffffb, 0x00281e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000008, 0x00291e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0xfffffff7, 0x00281e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36e },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00010000, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x01800000, 0x00204811, 0x000 },
- { 0xffffffff, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004217f, 0x00604411, 0x68d },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x68c },
- { 0x00000010, 0x00404c11, 0x672 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x38c00000, 0x000 },
- { 0x0000001d, 0x00200a2d, 0x000 },
- { 0x0000001e, 0x00200e2d, 0x000 },
- { 0x0000001f, 0x0020122d, 0x000 },
- { 0x00000020, 0x0020162d, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000004, 0x00301224, 0x000 },
- { 0x00000000, 0x002f0064, 0x000 },
- { 0x00000000, 0x0cc00000, 0x68b },
- { 0x00000003, 0x00281a22, 0x000 },
- { 0x00000008, 0x00221222, 0x000 },
- { 0xfffff000, 0x00281224, 0x000 },
- { 0x00000000, 0x002910c4, 0x000 },
- { 0x0000001f, 0x00403624, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x1ac00000, 0x68d },
- { 0x9f000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000000, 0x1ae00000, 0x690 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x1ac00000, 0x692 },
- { 0x9e000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000000, 0x1ae00000, 0x695 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00001000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001b, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0xc0204411, 0x000 },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000024, 0x0020222d, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000022, 0x0020222d, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00404811, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x01420502, 0x05c00250, 0x000 },
- { 0x01c30168, 0x043f05c0, 0x000 },
- { 0x02250209, 0x02500151, 0x000 },
- { 0x02230245, 0x02a00241, 0x000 },
- { 0x03d705c0, 0x05c005c0, 0x000 },
- { 0x0649064a, 0x031f05c0, 0x000 },
- { 0x05c005c5, 0x03200340, 0x000 },
- { 0x032a0282, 0x03420334, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x05c00551, 0x05c005c0, 0x000 },
- { 0x03ba05c0, 0x04bb0344, 0x000 },
- { 0x049a0450, 0x043d05c0, 0x000 },
- { 0x04d005c0, 0x044104dd, 0x000 },
- { 0x04500507, 0x03510375, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x05c005c0, 0x063f05c7, 0x000 },
- { 0x05c005c0, 0x000705c0, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x03f803ed, 0x04080406, 0x000 },
- { 0x040e040a, 0x040c0410, 0x000 },
- { 0x041c0418, 0x04240420, 0x000 },
- { 0x042c0428, 0x04340430, 0x000 },
- { 0x05c005c0, 0x043805c0, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x00020679, 0x06970006, 0x000 },
-};
-
-static const u32 RV610_pfp_microcode[] = {
-0xca0400,
-0xa00000,
-0x7e828b,
-0x7c038b,
-0x8001b8,
-0x7c038b,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581a8,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0fff0,
-0x042c04,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255403,
-0x7cd580,
-0x259c03,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d3,
-0xd5c01e,
-0xca0800,
-0x80001a,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800053,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xd48060,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001b8,
-0xd4c01e,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800000,
-0x062001,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x800079,
-0xd42013,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x80008d,
-0x000000,
-0xc41432,
-0xc61843,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800000,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xe4015e,
-0xd4001e,
-0x800000,
-0x062001,
-0xca1800,
-0x0a2001,
-0xd60076,
-0xc40836,
-0x988007,
-0xc61045,
-0x950110,
-0xd4001f,
-0xd46062,
-0x800000,
-0xd42062,
-0xcc3835,
-0xcc1433,
-0x8401bb,
-0xd40072,
-0xd5401e,
-0x800000,
-0xee001e,
-0xe2001a,
-0x8401bb,
-0xe2001a,
-0xcc104b,
-0xcc0447,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001b8,
-0xd4006d,
-0x344401,
-0xcc0c48,
-0x98403a,
-0xcc2c4a,
-0x958004,
-0xcc0449,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x8400f0,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x8400f0,
-0xcc1003,
-0x988017,
-0x043808,
-0x8400f0,
-0xcc1003,
-0x988013,
-0x043804,
-0x8400f0,
-0xcc1003,
-0x988014,
-0xcc104c,
-0x9a8009,
-0xcc144d,
-0x9840dc,
-0xd4006d,
-0xcc1848,
-0xd5001a,
-0xd5401a,
-0x8000c9,
-0xd5801a,
-0x96c0d5,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800000,
-0xec007f,
-0x9ac0cc,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809e,
-0xd4006d,
-0x98409c,
-0xd4006e,
-0xcc084c,
-0xcc0c4d,
-0xcc1048,
-0xd4801a,
-0xd4c01a,
-0x800101,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482d9,
-0xca0c00,
-0xd4401e,
-0x800000,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800000,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x9882bd,
-0x000000,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x9902b0,
-0x7c738b,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984297,
-0x000000,
-0x800161,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc104e,
-0x990004,
-0xd40073,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x950021,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x042802,
-0x7d8380,
-0xd5a86f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0xc82402,
-0x8001b8,
-0xd60076,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800000,
-0xee001e,
-0x800000,
-0xee001f,
-0xd4001f,
-0x800000,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010171,
-0x020178,
-0x03008f,
-0x04007f,
-0x050003,
-0x06003f,
-0x070032,
-0x08012c,
-0x090046,
-0x0a0036,
-0x1001b6,
-0x1700a2,
-0x22013a,
-0x230149,
-0x2000b4,
-0x240125,
-0x27004d,
-0x28006a,
-0x2a0060,
-0x2b0052,
-0x2f0065,
-0x320087,
-0x34017f,
-0x3c0156,
-0x3f0072,
-0x41018c,
-0x44012e,
-0x550173,
-0x56017a,
-0x60000b,
-0x610034,
-0x620038,
-0x630038,
-0x640038,
-0x650038,
-0x660038,
-0x670038,
-0x68003a,
-0x690041,
-0x6a0048,
-0x6b0048,
-0x6c0048,
-0x6d0048,
-0x6e0048,
-0x6f0048,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-};
-
-static const u32 RV620_cp_microcode[][3] = {
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0000ffff, 0x00284621, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00000000, 0x00e00000, 0x000 },
- { 0x00010000, 0xc0294620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x00000000, 0x00600000, 0x631 },
- { 0x00000000, 0x00600000, 0x645 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000f00, 0x00281622, 0x000 },
- { 0x00000008, 0x00211625, 0x000 },
- { 0x00000018, 0x00203625, 0x000 },
- { 0x8d000000, 0x00204411, 0x000 },
- { 0x00000004, 0x002f0225, 0x000 },
- { 0x00000000, 0x0ce00000, 0x018 },
- { 0x00412000, 0x00404811, 0x019 },
- { 0x00422000, 0x00204811, 0x000 },
- { 0x8e000000, 0x00204411, 0x000 },
- { 0x00000028, 0x00204a2d, 0x000 },
- { 0x90000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x0000000c, 0x00211622, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x00000019, 0x00211a22, 0x000 },
- { 0x00000004, 0x00281a26, 0x000 },
- { 0x00000000, 0x002914c5, 0x000 },
- { 0x00000019, 0x00203625, 0x000 },
- { 0x00000000, 0x003a1402, 0x000 },
- { 0x00000016, 0x00211625, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0xfffffffc, 0x00280e23, 0x000 },
- { 0x00000000, 0x002914a3, 0x000 },
- { 0x00000017, 0x00203625, 0x000 },
- { 0x00008000, 0x00280e22, 0x000 },
- { 0x00000007, 0x00220e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x20000000, 0x00280e22, 0x000 },
- { 0x00000006, 0x00210e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x00000000, 0x00220222, 0x000 },
- { 0x00000000, 0x14e00000, 0x038 },
- { 0x00000000, 0x2ee00000, 0x035 },
- { 0x00000000, 0x2ce00000, 0x037 },
- { 0x00000000, 0x00400e2d, 0x039 },
- { 0x00000008, 0x00200e2d, 0x000 },
- { 0x00000009, 0x0040122d, 0x046 },
- { 0x00000001, 0x00400e2d, 0x039 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x03e },
- { 0x00000008, 0x00401c11, 0x041 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x0000000f, 0x00281e27, 0x000 },
- { 0x00000003, 0x00221e27, 0x000 },
- { 0x7fc00000, 0x00281a23, 0x000 },
- { 0x00000014, 0x00211a26, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000008, 0x00221a26, 0x000 },
- { 0x00000000, 0x00290cc7, 0x000 },
- { 0x00000027, 0x00203624, 0x000 },
- { 0x00007f00, 0x00281221, 0x000 },
- { 0x00001400, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x04b },
- { 0x00000001, 0x00290e23, 0x000 },
- { 0x0000000e, 0x00203623, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfff80000, 0x00294a23, 0x000 },
- { 0x00000000, 0x003a2c02, 0x000 },
- { 0x00000002, 0x00220e2b, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x0000000f, 0x00203623, 0x000 },
- { 0x00001fff, 0x00294a23, 0x000 },
- { 0x00000027, 0x00204a2d, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000029, 0x00200e2d, 0x000 },
- { 0x060a0200, 0x00294a23, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00210222, 0x000 },
- { 0x00000000, 0x14e00000, 0x061 },
- { 0x00000000, 0x2ee00000, 0x05f },
- { 0x00000000, 0x2ce00000, 0x05e },
- { 0x00000000, 0x00400e2d, 0x062 },
- { 0x00000001, 0x00400e2d, 0x062 },
- { 0x0000000a, 0x00200e2d, 0x000 },
- { 0x0000000b, 0x0040122d, 0x06a },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x7fc00000, 0x00281623, 0x000 },
- { 0x00000014, 0x00211625, 0x000 },
- { 0x00000001, 0x00331625, 0x000 },
- { 0x80000000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00290ca3, 0x000 },
- { 0x3ffffc00, 0x00290e23, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x06d },
- { 0x00000100, 0x00401c11, 0x070 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x000000f0, 0x00281e27, 0x000 },
- { 0x00000004, 0x00221e27, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0xfffff0ff, 0x00281a30, 0x000 },
- { 0x0000a028, 0x00204411, 0x000 },
- { 0x00000000, 0x002948e6, 0x000 },
- { 0x0000a018, 0x00204411, 0x000 },
- { 0x3fffffff, 0x00284a23, 0x000 },
- { 0x0000a010, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000030, 0x0020162d, 0x000 },
- { 0x00000002, 0x00291625, 0x000 },
- { 0x00000030, 0x00203625, 0x000 },
- { 0x00000025, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a3, 0x000 },
- { 0x00000000, 0x0cc00000, 0x083 },
- { 0x00000026, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a4, 0x000 },
- { 0x00000000, 0x0cc00000, 0x084 },
- { 0x00000000, 0x00400000, 0x08a },
- { 0x00000025, 0x00203623, 0x000 },
- { 0x00000026, 0x00203624, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x08a },
- { 0x00000000, 0x00600000, 0x668 },
- { 0x00000000, 0x00600000, 0x65c },
- { 0x00000002, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x08d },
- { 0x00000012, 0xc0403620, 0x093 },
- { 0x00000000, 0x2ee00000, 0x091 },
- { 0x00000000, 0x2ce00000, 0x090 },
- { 0x00000002, 0x00400e2d, 0x092 },
- { 0x00000003, 0x00400e2d, 0x092 },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000012, 0x00203623, 0x000 },
- { 0x00000003, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x098 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x0a0 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x2ee00000, 0x09e },
- { 0x00000000, 0x2ce00000, 0x09d },
- { 0x00000002, 0x00400e2d, 0x09f },
- { 0x00000003, 0x00400e2d, 0x09f },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x003f0000, 0x00280e23, 0x000 },
- { 0x00000010, 0x00210e23, 0x000 },
- { 0x00000011, 0x00203623, 0x000 },
- { 0x0000001e, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0a7 },
- { 0x00000016, 0xc0203620, 0x000 },
- { 0x0000001f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0aa },
- { 0x00000015, 0xc0203620, 0x000 },
- { 0x00000008, 0x00210e2b, 0x000 },
- { 0x0000007f, 0x00280e23, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0e1 },
- { 0x00000000, 0x27000000, 0x000 },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ae00000, 0x0b3 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x0000000c, 0x00221e30, 0x000 },
- { 0x99800000, 0x00204411, 0x000 },
- { 0x00000004, 0x0020122d, 0x000 },
- { 0x00000008, 0x00221224, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00291ce4, 0x000 },
- { 0x00000000, 0x00604807, 0x12f },
- { 0x9b000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x9c000000, 0x00204411, 0x000 },
- { 0x00000000, 0x0033146f, 0x000 },
- { 0x00000001, 0x00333e23, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0x00203c05, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e007, 0x00204411, 0x000 },
- { 0x0000000f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0cb },
- { 0x00f8ff08, 0x00204811, 0x000 },
- { 0x98000000, 0x00404811, 0x0dc },
- { 0x000000f0, 0x00280e22, 0x000 },
- { 0x000000a0, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x0da },
- { 0x00000011, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0d5 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0d4 },
- { 0x00003f00, 0x00400c11, 0x0d6 },
- { 0x00001f00, 0x00400c11, 0x0d6 },
- { 0x00000f00, 0x00200c11, 0x000 },
- { 0x00380009, 0x00294a23, 0x000 },
- { 0x3f000000, 0x00280e2b, 0x000 },
- { 0x00000002, 0x00220e23, 0x000 },
- { 0x00000007, 0x00494a23, 0x0dc },
- { 0x00380f09, 0x00204811, 0x000 },
- { 0x68000007, 0x00204811, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000a202, 0x00204411, 0x000 },
- { 0x00ff0000, 0x00280e22, 0x000 },
- { 0x00000080, 0x00294a23, 0x000 },
- { 0x00000027, 0x00200e2d, 0x000 },
- { 0x00000026, 0x0020122d, 0x000 },
- { 0x00000000, 0x002f0083, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0ea },
- { 0x00000000, 0x00600000, 0x662 },
- { 0x00000000, 0x00400000, 0x0eb },
- { 0x00000000, 0x00600000, 0x665 },
- { 0x00000007, 0x0020222d, 0x000 },
- { 0x00000005, 0x00220e22, 0x000 },
- { 0x00100000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x000000ef, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0x00000003, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x0f8 },
- { 0x0000000b, 0x00210228, 0x000 },
- { 0x00000000, 0x14c00000, 0x0f8 },
- { 0x00000400, 0x00292228, 0x000 },
- { 0x00000014, 0x00203628, 0x000 },
- { 0x0000001c, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x0fd },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000001e, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x10b },
- { 0x0000a30f, 0x00204411, 0x000 },
- { 0x00000011, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x104 },
- { 0xffffffff, 0x00404811, 0x10b },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x107 },
- { 0x0000ffff, 0x00404811, 0x10b },
- { 0x00000004, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x10a },
- { 0x000000ff, 0x00404811, 0x10b },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0002c400, 0x00204411, 0x000 },
- { 0x0000001f, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x112 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x00000013, 0x00203623, 0x000 },
- { 0x00000018, 0x40224a20, 0x000 },
- { 0x00000010, 0xc0424a20, 0x114 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x00000013, 0x00203623, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000000a, 0x00201011, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x11b },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00531224, 0x117 },
- { 0xffbfffff, 0x00283a2e, 0x000 },
- { 0x0000001b, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x12e },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0x00000018, 0x00220e30, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e00e, 0x00204411, 0x000 },
- { 0x07f8ff08, 0x00204811, 0x000 },
- { 0x00000000, 0x00294a23, 0x000 },
- { 0x0000001c, 0x00201e2d, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x00800000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204806, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x68d },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x68c },
- { 0x00000004, 0x00404c11, 0x135 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x0000001c, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68d },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x13c },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00000000, 0x00600000, 0x160 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40280620, 0x000 },
- { 0x00000010, 0xc0210a20, 0x000 },
- { 0x00000000, 0x00341461, 0x000 },
- { 0x00000000, 0x00741882, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x147 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x160 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0681a20, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x158 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000001, 0x00300a2f, 0x000 },
- { 0x00000001, 0x00210a22, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600000, 0x18f },
- { 0x00000000, 0x00600000, 0x1a0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00202c08, 0x000 },
- { 0x00000000, 0x00202411, 0x000 },
- { 0x00000000, 0x00202811, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000002, 0x00221e29, 0x000 },
- { 0x00000000, 0x007048eb, 0x19c },
- { 0x00000000, 0x00600000, 0x2bb },
- { 0x00000001, 0x40330620, 0x000 },
- { 0x00000000, 0xc0302409, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ae00000, 0x181 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x00000000, 0x00400000, 0x186 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x186 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000001, 0x00530621, 0x182 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0604800, 0x197 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000011, 0x0020062d, 0x000 },
- { 0x00000000, 0x0078042a, 0x2fb },
- { 0x00000000, 0x00202809, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x174 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000210, 0x00600411, 0x315 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x194 },
- { 0x00000015, 0xc0203620, 0x000 },
- { 0x00000016, 0xc0203620, 0x000 },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x46000000, 0x00600811, 0x1b2 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x19b },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000021, 0x00804811, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40281620, 0x000 },
- { 0x00000010, 0xc0811a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000008, 0x00221e30, 0x000 },
- { 0x00000029, 0x00201a2d, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfffbff09, 0x00204811, 0x000 },
- { 0x0000000f, 0x0020222d, 0x000 },
- { 0x00001fff, 0x00294a28, 0x000 },
- { 0x00000006, 0x0020222d, 0x000 },
- { 0x00000000, 0x002920e8, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a26, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000100, 0x00201811, 0x000 },
- { 0x00000008, 0x00621e28, 0x12f },
- { 0x00000008, 0x00822228, 0x000 },
- { 0x0002c000, 0x00204411, 0x000 },
- { 0x00000015, 0x00600e2d, 0x1bd },
- { 0x00000016, 0x00600e2d, 0x1bd },
- { 0x0000c008, 0x00204411, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0x00000000, 0x14c00000, 0x1b9 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x39000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00804802, 0x000 },
- { 0x00000018, 0x00202e2d, 0x000 },
- { 0x00000000, 0x003b0d63, 0x000 },
- { 0x00000008, 0x00224a23, 0x000 },
- { 0x00000010, 0x00224a23, 0x000 },
- { 0x00000018, 0x00224a23, 0x000 },
- { 0x00000000, 0x00804803, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00001000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00000007, 0x0021062f, 0x000 },
- { 0x00000013, 0x00200a2d, 0x000 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000ffff, 0x40282220, 0x000 },
- { 0x0000000f, 0x00262228, 0x000 },
- { 0x00000010, 0x40212620, 0x000 },
- { 0x0000000f, 0x00262629, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001b, 0x00204811, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1e0 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000081, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000080, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1dc },
- { 0x00000000, 0x00600000, 0x1e9 },
- { 0x00000001, 0x00531e27, 0x1d8 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000001f, 0x00280a22, 0x000 },
- { 0x0000001f, 0x00282a2a, 0x000 },
- { 0x00000001, 0x00530621, 0x1d1 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000002, 0x00304a2f, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000001, 0x00301e2f, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x1e9 },
- { 0x00000001, 0x00531e27, 0x1e5 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x0000000f, 0x00260e23, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000000f, 0x00261224, 0x000 },
- { 0x00000000, 0x00201411, 0x000 },
- { 0x00000000, 0x00601811, 0x2bb },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022b, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1f8 },
- { 0x00000010, 0x00221628, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a29, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x0020480a, 0x000 },
- { 0x00000000, 0x00202c11, 0x000 },
- { 0x00000010, 0x00221623, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a24, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x00731503, 0x205 },
- { 0x00000000, 0x00201805, 0x000 },
- { 0x00000000, 0x00731524, 0x205 },
- { 0x00000000, 0x002d14c5, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00000000, 0x00202003, 0x000 },
- { 0x00000000, 0x00802404, 0x000 },
- { 0x0000000f, 0x00210225, 0x000 },
- { 0x00000000, 0x14c00000, 0x68c },
- { 0x00000000, 0x002b1405, 0x000 },
- { 0x00000001, 0x00901625, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00294a22, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a21, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000ffff, 0x40281220, 0x000 },
- { 0x00000010, 0xc0211a20, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211620, 0x000 },
- { 0x00000000, 0x00741465, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00000001, 0x00330621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0cc00000, 0x219 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x212 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x645 },
- { 0x00000000, 0x0040040f, 0x213 },
- { 0x00000000, 0x00600000, 0x631 },
- { 0x00000000, 0x00600000, 0x645 },
- { 0x00000210, 0x00600411, 0x315 },
- { 0x00000000, 0x00600000, 0x1a0 },
- { 0x00000000, 0x00600000, 0x19c },
- { 0x00000000, 0x00600000, 0x2bb },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ae00000, 0x232 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x00000000, 0x00400000, 0x236 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x236 },
- { 0x00000000, 0xc0404800, 0x233 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x00600411, 0x2fb },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x631 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000018, 0x40210a20, 0x000 },
- { 0x00000003, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x24c },
- { 0x00000014, 0x0020222d, 0x000 },
- { 0x00080101, 0x00292228, 0x000 },
- { 0x00000014, 0x00203628, 0x000 },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x251 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000010, 0x00600411, 0x315 },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x00000000, 0x00600000, 0x27c },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000001, 0x00211e27, 0x000 },
- { 0x00000000, 0x14e00000, 0x26a },
- { 0x00000012, 0x00201e2d, 0x000 },
- { 0x0000ffff, 0x00281e27, 0x000 },
- { 0x00000000, 0x00341c27, 0x000 },
- { 0x00000000, 0x12c00000, 0x25f },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e5, 0x000 },
- { 0x00000000, 0x08c00000, 0x262 },
- { 0x00000000, 0x00201407, 0x000 },
- { 0x00000012, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00211e27, 0x000 },
- { 0x00000000, 0x00341c47, 0x000 },
- { 0x00000000, 0x12c00000, 0x267 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x08c00000, 0x26a },
- { 0x00000000, 0x00201807, 0x000 },
- { 0x00000000, 0x00600000, 0x2c1 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000000, 0x00342023, 0x000 },
- { 0x00000000, 0x12c00000, 0x272 },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x271 },
- { 0x00000016, 0x00404811, 0x276 },
- { 0x00000018, 0x00404811, 0x276 },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x275 },
- { 0x00000017, 0x00404811, 0x276 },
- { 0x00000019, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00604411, 0x2e9 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x256 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000010, 0x40210620, 0x000 },
- { 0x0000ffff, 0xc0280a20, 0x000 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0881a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x00000000, 0x00600000, 0x631 },
- { 0x00000000, 0xc0600000, 0x2a3 },
- { 0x00000005, 0x00200a2d, 0x000 },
- { 0x00000008, 0x00220a22, 0x000 },
- { 0x0000002b, 0x00201a2d, 0x000 },
- { 0x0000001c, 0x00201e2d, 0x000 },
- { 0x00007000, 0x00281e27, 0x000 },
- { 0x00000000, 0x00311ce6, 0x000 },
- { 0x0000002a, 0x00201a2d, 0x000 },
- { 0x0000000c, 0x00221a26, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x06e00000, 0x292 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x0000002b, 0x00203623, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00691ce2, 0x12f },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x29d },
- { 0x00000001, 0x00333e2f, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000001c, 0x00403627, 0x000 },
- { 0x0000000c, 0xc0220a20, 0x000 },
- { 0x00000029, 0x00203622, 0x000 },
- { 0x00000028, 0xc0403620, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000009, 0x00204811, 0x000 },
- { 0xa1000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce3, 0x000 },
- { 0x00000021, 0x00203627, 0x000 },
- { 0x00000022, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce4, 0x000 },
- { 0x00000022, 0x00203627, 0x000 },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a3, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x00000023, 0x00203627, 0x000 },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x00000024, 0x00803627, 0x000 },
- { 0x00000021, 0x00203623, 0x000 },
- { 0x00000022, 0x00203624, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000023, 0x00203627, 0x000 },
- { 0x00000000, 0x00311cc4, 0x000 },
- { 0x00000024, 0x00803627, 0x000 },
- { 0x0000001a, 0x00203627, 0x000 },
- { 0x0000001b, 0x00203628, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14c00000, 0x2dc },
- { 0x00000000, 0x00400000, 0x2d9 },
- { 0x0000001a, 0x00203627, 0x000 },
- { 0x0000001b, 0x00203628, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2d9 },
- { 0x00000003, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2dc },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e1, 0x000 },
- { 0x00000000, 0x02c00000, 0x2dc },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a1, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2dc },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e2, 0x000 },
- { 0x00000000, 0x02c00000, 0x2dc },
- { 0x00000022, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2dc },
- { 0x00000000, 0x00600000, 0x668 },
- { 0x00000000, 0x00600000, 0x2b5 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x00000000, 0x00600000, 0x2b5 },
- { 0x00000000, 0x00600000, 0x65f },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x00000000, 0x00600000, 0x2a7 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x0000001a, 0x00201e2d, 0x000 },
- { 0x0000001b, 0x0080222d, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca1, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x003808c5, 0x000 },
- { 0x00000000, 0x00300841, 0x000 },
- { 0x00000001, 0x00220a22, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000017, 0x0020222d, 0x000 },
- { 0x00000000, 0x14c00000, 0x318 },
- { 0xffffffef, 0x00280621, 0x000 },
- { 0x00000014, 0x0020222d, 0x000 },
- { 0x0000f8e0, 0x00204411, 0x000 },
- { 0x00000000, 0x00294901, 0x000 },
- { 0x00000000, 0x00894901, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00804811, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x97000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00002257, 0x00204411, 0x000 },
- { 0x00000003, 0xc0484a20, 0x000 },
- { 0x0000225d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x645 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x00000001, 0x40304a20, 0x000 },
- { 0x00000002, 0xc0304a20, 0x000 },
- { 0x00000001, 0x00530a22, 0x34b },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000018, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68d },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x354 },
- { 0x00000014, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x364 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00604802, 0x36e },
- { 0x00002100, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000004, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x36a },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x35f },
- { 0x00000028, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5c0 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x35f },
- { 0x0000002c, 0x00203626, 0x000 },
- { 0x00000049, 0x00201811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000000, 0x002f0226, 0x000 },
- { 0x00000000, 0x0cc00000, 0x370 },
- { 0x0000002c, 0x00801a2d, 0x000 },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x00000015, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x386 },
- { 0x00000006, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3b1 },
- { 0x00000016, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3b5 },
- { 0x00000020, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x39c },
- { 0x0000000f, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3a8 },
- { 0x00000010, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3a8 },
- { 0x0000001e, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x390 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x08000000, 0x00290a22, 0x000 },
- { 0x00000003, 0x40210e20, 0x000 },
- { 0x0000000c, 0xc0211220, 0x000 },
- { 0x00080000, 0x00281224, 0x000 },
- { 0x00000014, 0xc0221620, 0x000 },
- { 0x00000000, 0x002914a4, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x002948a2, 0x000 },
- { 0x0000a1fe, 0x00204411, 0x000 },
- { 0x00000000, 0x00404803, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68d },
- { 0x00000015, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x392 },
- { 0x0000210e, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000017, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68d },
- { 0x00000003, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x39e },
- { 0x00002108, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x80000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000010, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x3ae },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000006, 0x00404811, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36e },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x0000001d, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x3ce },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000018, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68d },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x3c0 },
- { 0x00002100, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0xbabecafe, 0x00204811, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000004, 0x00404811, 0x000 },
- { 0x00002170, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000a, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x3d3 },
- { 0x8c000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00003fff, 0x40280a20, 0x000 },
- { 0x80000000, 0x40280e20, 0x000 },
- { 0x40000000, 0xc0281220, 0x000 },
- { 0x00040000, 0x00694622, 0x68d },
- { 0x00000000, 0x00201410, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3e1 },
- { 0x00000000, 0xc0401800, 0x3e4 },
- { 0x00003fff, 0xc0281a20, 0x000 },
- { 0x00040000, 0x00694626, 0x68d },
- { 0x00000000, 0x00201810, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3e7 },
- { 0x00000000, 0xc0401c00, 0x3ea },
- { 0x00003fff, 0xc0281e20, 0x000 },
- { 0x00040000, 0x00694627, 0x68d },
- { 0x00000000, 0x00201c10, 0x000 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0x002820c5, 0x000 },
- { 0x00000000, 0x004948e8, 0x000 },
- { 0xa5800000, 0x00200811, 0x000 },
- { 0x00002000, 0x00200c11, 0x000 },
- { 0x83000000, 0x00604411, 0x412 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x0000001f, 0xc0210220, 0x000 },
- { 0x00000000, 0x14c00000, 0x3f7 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0000ffff, 0xc0481220, 0x3ff },
- { 0xa7800000, 0x00200811, 0x000 },
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- { 0x00000001, 0x00204811, 0x000 },
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- { 0x00040000, 0x00694624, 0x68d },
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- { 0x00000000, 0x00604805, 0x692 },
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- { 0x00000001, 0x002f0222, 0x000 },
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- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x04e00000, 0x486 },
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- { 0x00000001, 0x00204811, 0x000 },
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- { 0x00000001, 0x00210222, 0x000 },
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- { 0x00000001, 0x00204811, 0x000 },
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- { 0x00000000, 0x002920e8, 0x000 },
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- { 0x00000002, 0x00221624, 0x000 },
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- { 0xefffffff, 0x00283a2e, 0x000 },
- { 0x00000000, 0x004938ce, 0x67b },
- { 0x00000001, 0x40280a20, 0x000 },
- { 0x00000006, 0x40280e20, 0x000 },
- { 0x00000300, 0xc0281220, 0x000 },
- { 0x00000008, 0x00211224, 0x000 },
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- { 0x00000000, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x566 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00002258, 0x00300a24, 0x000 },
- { 0x00040000, 0x00694622, 0x68d },
- { 0x00002169, 0x00204411, 0x000 },
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- { 0x00000000, 0xc0201c10, 0x000 },
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- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x56e },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
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- { 0x00000000, 0xc0201c10, 0x000 },
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- { 0x00000000, 0x00401c10, 0x57c },
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- { 0x0000a2b7, 0x00204411, 0x000 },
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- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2b6, 0x00604411, 0x68d },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
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- { 0x00000000, 0x00404808, 0x000 },
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- { 0x00000001, 0x00504a28, 0x000 },
- { 0x00000001, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5a0 },
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- { 0x00000000, 0x00204807, 0x000 },
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- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2ba, 0x00604411, 0x68d },
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- { 0x00000000, 0x00404808, 0x000 },
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- { 0x00000001, 0x00504a28, 0x000 },
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- { 0x00000000, 0x0cc00000, 0x5b1 },
- { 0x0000a2bf, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2be, 0x00604411, 0x68d },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x0000a2c6, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x5af },
- { 0x0000a2d3, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d3, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x0000a2c3, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2c2, 0x00604411, 0x68d },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x0000a2c7, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x5be },
- { 0x0000a2d4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d4, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x85000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x0000304a, 0x00204411, 0x000 },
- { 0x01000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00400000, 0x5c4 },
- { 0xa4000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0xc0600000, 0x5c9 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000002c, 0x00203621, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000000, 0x002f0230, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5d0 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000030, 0x00403621, 0x5e3 },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00007e00, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x5e3 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a092, 0x00604411, 0x68d },
- { 0x00000031, 0x00203630, 0x000 },
- { 0x0004a093, 0x00604411, 0x68d },
- { 0x00000032, 0x00203630, 0x000 },
- { 0x0004a2b6, 0x00604411, 0x68d },
- { 0x00000033, 0x00203630, 0x000 },
- { 0x0004a2ba, 0x00604411, 0x68d },
- { 0x00000034, 0x00203630, 0x000 },
- { 0x0004a2be, 0x00604411, 0x68d },
- { 0x00000035, 0x00203630, 0x000 },
- { 0x0004a2c2, 0x00604411, 0x68d },
- { 0x00000036, 0x00203630, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x00000005, 0x00204811, 0x000 },
- { 0x0000a1f4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x88000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000001, 0x002f0230, 0x000 },
- { 0x00000000, 0x0ce00000, 0x62c },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x62c },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00007e00, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x605 },
- { 0x0000a092, 0x00204411, 0x000 },
- { 0x00000031, 0x00204a2d, 0x000 },
- { 0x0000a093, 0x00204411, 0x000 },
- { 0x00000032, 0x00204a2d, 0x000 },
- { 0x0000a2b6, 0x00204411, 0x000 },
- { 0x00000033, 0x00204a2d, 0x000 },
- { 0x0000a2ba, 0x00204411, 0x000 },
- { 0x00000034, 0x00204a2d, 0x000 },
- { 0x0000a2be, 0x00204411, 0x000 },
- { 0x00000035, 0x00204a2d, 0x000 },
- { 0x0000a2c2, 0x00204411, 0x000 },
- { 0x00000036, 0x00204a2d, 0x000 },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x000001ff, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x62b },
- { 0x00000000, 0x00210221, 0x000 },
- { 0x00000000, 0x14c00000, 0x60e },
- { 0x0004a003, 0x00604411, 0x68d },
- { 0x0000a003, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00000001, 0x00210621, 0x000 },
- { 0x00000000, 0x14c00000, 0x613 },
- { 0x0004a010, 0x00604411, 0x68d },
- { 0x0000a010, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00000001, 0x00210621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x62b },
- { 0x0004a011, 0x00604411, 0x68d },
- { 0x0000a011, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a012, 0x00604411, 0x68d },
- { 0x0000a012, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a013, 0x00604411, 0x68d },
- { 0x0000a013, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a014, 0x00604411, 0x68d },
- { 0x0000a014, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a015, 0x00604411, 0x68d },
- { 0x0000a015, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a016, 0x00604411, 0x68d },
- { 0x0000a016, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a017, 0x00604411, 0x68d },
- { 0x0000a017, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x0000002c, 0x0080062d, 0x000 },
- { 0xff000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000002, 0x00804811, 0x000 },
- { 0x00000000, 0x0ee00000, 0x63d },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00000002, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x63b },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x68d },
- { 0x00001000, 0x00200811, 0x000 },
- { 0x0000002b, 0x00203622, 0x000 },
- { 0x00000000, 0x00600000, 0x641 },
- { 0x00000000, 0x00600000, 0x5c9 },
- { 0x98000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00804811, 0x000 },
- { 0x00000000, 0xc0600000, 0x641 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000022, 0x00204811, 0x000 },
- { 0x89000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00404811, 0x62d },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00404811, 0x62d },
- { 0x00000000, 0x00600000, 0x65c },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0xc0204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36e },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00010000, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x09800000, 0x00204811, 0x000 },
- { 0xffffffff, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x68d },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000004, 0x00404c11, 0x656 },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000004, 0x00291e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0xfffffffb, 0x00281e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000008, 0x00291e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0xfffffff7, 0x00281e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36e },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00010000, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x01800000, 0x00204811, 0x000 },
- { 0xffffffff, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004217f, 0x00604411, 0x68d },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x68c },
- { 0x00000010, 0x00404c11, 0x672 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x38c00000, 0x000 },
- { 0x0000001d, 0x00200a2d, 0x000 },
- { 0x0000001e, 0x00200e2d, 0x000 },
- { 0x0000001f, 0x0020122d, 0x000 },
- { 0x00000020, 0x0020162d, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000004, 0x00301224, 0x000 },
- { 0x00000000, 0x002f0064, 0x000 },
- { 0x00000000, 0x0cc00000, 0x68b },
- { 0x00000003, 0x00281a22, 0x000 },
- { 0x00000008, 0x00221222, 0x000 },
- { 0xfffff000, 0x00281224, 0x000 },
- { 0x00000000, 0x002910c4, 0x000 },
- { 0x0000001f, 0x00403624, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x1ac00000, 0x68d },
- { 0x9f000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000000, 0x1ae00000, 0x690 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x1ac00000, 0x692 },
- { 0x9e000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000000, 0x1ae00000, 0x695 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00001000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001b, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0xc0204411, 0x000 },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000024, 0x0020222d, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000022, 0x0020222d, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00404811, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x01420502, 0x05c00250, 0x000 },
- { 0x01c30168, 0x043f05c0, 0x000 },
- { 0x02250209, 0x02500151, 0x000 },
- { 0x02230245, 0x02a00241, 0x000 },
- { 0x03d705c0, 0x05c005c0, 0x000 },
- { 0x0649064a, 0x031f05c0, 0x000 },
- { 0x05c005c5, 0x03200340, 0x000 },
- { 0x032a0282, 0x03420334, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x05c00551, 0x05c005c0, 0x000 },
- { 0x03ba05c0, 0x04bb0344, 0x000 },
- { 0x049a0450, 0x043d05c0, 0x000 },
- { 0x04d005c0, 0x044104dd, 0x000 },
- { 0x04500507, 0x03510375, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x05c005c0, 0x063f05c7, 0x000 },
- { 0x05c005c0, 0x000705c0, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x03f803ed, 0x04080406, 0x000 },
- { 0x040e040a, 0x040c0410, 0x000 },
- { 0x041c0418, 0x04240420, 0x000 },
- { 0x042c0428, 0x04340430, 0x000 },
- { 0x05c005c0, 0x043805c0, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x05c005c0, 0x05c005c0, 0x000 },
- { 0x00020679, 0x06970006, 0x000 },
-};
-
-static const u32 RV620_pfp_microcode[] = {
-0xca0400,
-0xa00000,
-0x7e828b,
-0x7c038b,
-0x8001b8,
-0x7c038b,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581a8,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0fff0,
-0x042c04,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255403,
-0x7cd580,
-0x259c03,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d3,
-0xd5c01e,
-0xca0800,
-0x80001a,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800053,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xd48060,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001b8,
-0xd4c01e,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800000,
-0x062001,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x800079,
-0xd42013,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x80008d,
-0x000000,
-0xc41432,
-0xc61843,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800000,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xe4015e,
-0xd4001e,
-0x800000,
-0x062001,
-0xca1800,
-0x0a2001,
-0xd60076,
-0xc40836,
-0x988007,
-0xc61045,
-0x950110,
-0xd4001f,
-0xd46062,
-0x800000,
-0xd42062,
-0xcc3835,
-0xcc1433,
-0x8401bb,
-0xd40072,
-0xd5401e,
-0x800000,
-0xee001e,
-0xe2001a,
-0x8401bb,
-0xe2001a,
-0xcc104b,
-0xcc0447,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001b8,
-0xd4006d,
-0x344401,
-0xcc0c48,
-0x98403a,
-0xcc2c4a,
-0x958004,
-0xcc0449,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x8400f0,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x8400f0,
-0xcc1003,
-0x988017,
-0x043808,
-0x8400f0,
-0xcc1003,
-0x988013,
-0x043804,
-0x8400f0,
-0xcc1003,
-0x988014,
-0xcc104c,
-0x9a8009,
-0xcc144d,
-0x9840dc,
-0xd4006d,
-0xcc1848,
-0xd5001a,
-0xd5401a,
-0x8000c9,
-0xd5801a,
-0x96c0d5,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800000,
-0xec007f,
-0x9ac0cc,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809e,
-0xd4006d,
-0x98409c,
-0xd4006e,
-0xcc084c,
-0xcc0c4d,
-0xcc1048,
-0xd4801a,
-0xd4c01a,
-0x800101,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482d9,
-0xca0c00,
-0xd4401e,
-0x800000,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800000,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x9882bd,
-0x000000,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x9902b0,
-0x7c738b,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984297,
-0x000000,
-0x800161,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc104e,
-0x990004,
-0xd40073,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x950021,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x042802,
-0x7d8380,
-0xd5a86f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0xc82402,
-0x8001b8,
-0xd60076,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800000,
-0xee001e,
-0x800000,
-0xee001f,
-0xd4001f,
-0x800000,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010171,
-0x020178,
-0x03008f,
-0x04007f,
-0x050003,
-0x06003f,
-0x070032,
-0x08012c,
-0x090046,
-0x0a0036,
-0x1001b6,
-0x1700a2,
-0x22013a,
-0x230149,
-0x2000b4,
-0x240125,
-0x27004d,
-0x28006a,
-0x2a0060,
-0x2b0052,
-0x2f0065,
-0x320087,
-0x34017f,
-0x3c0156,
-0x3f0072,
-0x41018c,
-0x44012e,
-0x550173,
-0x56017a,
-0x60000b,
-0x610034,
-0x620038,
-0x630038,
-0x640038,
-0x650038,
-0x660038,
-0x670038,
-0x68003a,
-0x690041,
-0x6a0048,
-0x6b0048,
-0x6c0048,
-0x6d0048,
-0x6e0048,
-0x6f0048,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-};
-
-static const u32 RV630_cp_microcode[][3] = {
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0000ffff, 0x00284621, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00000000, 0x00e00000, 0x000 },
- { 0x00010000, 0xc0294620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
- { 0x00000000, 0x00600000, 0x62e },
- { 0x00000000, 0x00600000, 0x642 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000f00, 0x00281622, 0x000 },
- { 0x00000008, 0x00211625, 0x000 },
- { 0x00000018, 0x00203625, 0x000 },
- { 0x8d000000, 0x00204411, 0x000 },
- { 0x00000004, 0x002f0225, 0x000 },
- { 0x00000000, 0x0ce00000, 0x018 },
- { 0x00412000, 0x00404811, 0x019 },
- { 0x00422000, 0x00204811, 0x000 },
- { 0x8e000000, 0x00204411, 0x000 },
- { 0x00000028, 0x00204a2d, 0x000 },
- { 0x90000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x0000000c, 0x00211622, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x00000019, 0x00211a22, 0x000 },
- { 0x00000004, 0x00281a26, 0x000 },
- { 0x00000000, 0x002914c5, 0x000 },
- { 0x00000019, 0x00203625, 0x000 },
- { 0x00000000, 0x003a1402, 0x000 },
- { 0x00000016, 0x00211625, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0xfffffffc, 0x00280e23, 0x000 },
- { 0x00000000, 0x002914a3, 0x000 },
- { 0x00000017, 0x00203625, 0x000 },
- { 0x00008000, 0x00280e22, 0x000 },
- { 0x00000007, 0x00220e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x20000000, 0x00280e22, 0x000 },
- { 0x00000006, 0x00210e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x00000000, 0x00220222, 0x000 },
- { 0x00000000, 0x14e00000, 0x038 },
- { 0x00000000, 0x2ee00000, 0x035 },
- { 0x00000000, 0x2ce00000, 0x037 },
- { 0x00000000, 0x00400e2d, 0x039 },
- { 0x00000008, 0x00200e2d, 0x000 },
- { 0x00000009, 0x0040122d, 0x046 },
- { 0x00000001, 0x00400e2d, 0x039 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x03e },
- { 0x00000008, 0x00401c11, 0x041 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x0000000f, 0x00281e27, 0x000 },
- { 0x00000003, 0x00221e27, 0x000 },
- { 0x7fc00000, 0x00281a23, 0x000 },
- { 0x00000014, 0x00211a26, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000008, 0x00221a26, 0x000 },
- { 0x00000000, 0x00290cc7, 0x000 },
- { 0x00000027, 0x00203624, 0x000 },
- { 0x00007f00, 0x00281221, 0x000 },
- { 0x00001400, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x04b },
- { 0x00000001, 0x00290e23, 0x000 },
- { 0x0000000e, 0x00203623, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfff80000, 0x00294a23, 0x000 },
- { 0x00000000, 0x003a2c02, 0x000 },
- { 0x00000002, 0x00220e2b, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x0000000f, 0x00203623, 0x000 },
- { 0x00001fff, 0x00294a23, 0x000 },
- { 0x00000027, 0x00204a2d, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000029, 0x00200e2d, 0x000 },
- { 0x060a0200, 0x00294a23, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00210222, 0x000 },
- { 0x00000000, 0x14e00000, 0x061 },
- { 0x00000000, 0x2ee00000, 0x05f },
- { 0x00000000, 0x2ce00000, 0x05e },
- { 0x00000000, 0x00400e2d, 0x062 },
- { 0x00000001, 0x00400e2d, 0x062 },
- { 0x0000000a, 0x00200e2d, 0x000 },
- { 0x0000000b, 0x0040122d, 0x06a },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x7fc00000, 0x00281623, 0x000 },
- { 0x00000014, 0x00211625, 0x000 },
- { 0x00000001, 0x00331625, 0x000 },
- { 0x80000000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00290ca3, 0x000 },
- { 0x3ffffc00, 0x00290e23, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x06d },
- { 0x00000100, 0x00401c11, 0x070 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x000000f0, 0x00281e27, 0x000 },
- { 0x00000004, 0x00221e27, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0xfffff0ff, 0x00281a30, 0x000 },
- { 0x0000a028, 0x00204411, 0x000 },
- { 0x00000000, 0x002948e6, 0x000 },
- { 0x0000a018, 0x00204411, 0x000 },
- { 0x3fffffff, 0x00284a23, 0x000 },
- { 0x0000a010, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000030, 0x0020162d, 0x000 },
- { 0x00000002, 0x00291625, 0x000 },
- { 0x00000030, 0x00203625, 0x000 },
- { 0x00000025, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a3, 0x000 },
- { 0x00000000, 0x0cc00000, 0x083 },
- { 0x00000026, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a4, 0x000 },
- { 0x00000000, 0x0cc00000, 0x084 },
- { 0x00000000, 0x00400000, 0x08a },
- { 0x00000025, 0x00203623, 0x000 },
- { 0x00000026, 0x00203624, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x08a },
- { 0x00000000, 0x00600000, 0x665 },
- { 0x00000000, 0x00600000, 0x659 },
- { 0x00000002, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x08d },
- { 0x00000012, 0xc0403620, 0x093 },
- { 0x00000000, 0x2ee00000, 0x091 },
- { 0x00000000, 0x2ce00000, 0x090 },
- { 0x00000002, 0x00400e2d, 0x092 },
- { 0x00000003, 0x00400e2d, 0x092 },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000012, 0x00203623, 0x000 },
- { 0x00000003, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x098 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x0a0 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x2ee00000, 0x09e },
- { 0x00000000, 0x2ce00000, 0x09d },
- { 0x00000002, 0x00400e2d, 0x09f },
- { 0x00000003, 0x00400e2d, 0x09f },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x003f0000, 0x00280e23, 0x000 },
- { 0x00000010, 0x00210e23, 0x000 },
- { 0x00000011, 0x00203623, 0x000 },
- { 0x0000001e, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0a7 },
- { 0x00000016, 0xc0203620, 0x000 },
- { 0x0000001f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0aa },
- { 0x00000015, 0xc0203620, 0x000 },
- { 0x00000008, 0x00210e2b, 0x000 },
- { 0x0000007f, 0x00280e23, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0e1 },
- { 0x00000000, 0x27000000, 0x000 },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ae00000, 0x0b3 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x0000000c, 0x00221e30, 0x000 },
- { 0x99800000, 0x00204411, 0x000 },
- { 0x00000004, 0x0020122d, 0x000 },
- { 0x00000008, 0x00221224, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00291ce4, 0x000 },
- { 0x00000000, 0x00604807, 0x12f },
- { 0x9b000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x9c000000, 0x00204411, 0x000 },
- { 0x00000000, 0x0033146f, 0x000 },
- { 0x00000001, 0x00333e23, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0x00203c05, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e007, 0x00204411, 0x000 },
- { 0x0000000f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0cb },
- { 0x00f8ff08, 0x00204811, 0x000 },
- { 0x98000000, 0x00404811, 0x0dc },
- { 0x000000f0, 0x00280e22, 0x000 },
- { 0x000000a0, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x0da },
- { 0x00000011, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0d5 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0d4 },
- { 0x00003f00, 0x00400c11, 0x0d6 },
- { 0x00001f00, 0x00400c11, 0x0d6 },
- { 0x00000f00, 0x00200c11, 0x000 },
- { 0x00380009, 0x00294a23, 0x000 },
- { 0x3f000000, 0x00280e2b, 0x000 },
- { 0x00000002, 0x00220e23, 0x000 },
- { 0x00000007, 0x00494a23, 0x0dc },
- { 0x00380f09, 0x00204811, 0x000 },
- { 0x68000007, 0x00204811, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000a202, 0x00204411, 0x000 },
- { 0x00ff0000, 0x00280e22, 0x000 },
- { 0x00000080, 0x00294a23, 0x000 },
- { 0x00000027, 0x00200e2d, 0x000 },
- { 0x00000026, 0x0020122d, 0x000 },
- { 0x00000000, 0x002f0083, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0ea },
- { 0x00000000, 0x00600000, 0x65f },
- { 0x00000000, 0x00400000, 0x0eb },
- { 0x00000000, 0x00600000, 0x662 },
- { 0x00000007, 0x0020222d, 0x000 },
- { 0x00000005, 0x00220e22, 0x000 },
- { 0x00100000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x000000ef, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0x00000003, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x0f8 },
- { 0x0000000b, 0x00210228, 0x000 },
- { 0x00000000, 0x14c00000, 0x0f8 },
- { 0x00000400, 0x00292228, 0x000 },
- { 0x00000014, 0x00203628, 0x000 },
- { 0x0000001c, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x0fd },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000001e, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x10b },
- { 0x0000a30f, 0x00204411, 0x000 },
- { 0x00000011, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x104 },
- { 0xffffffff, 0x00404811, 0x10b },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x107 },
- { 0x0000ffff, 0x00404811, 0x10b },
- { 0x00000004, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x10a },
- { 0x000000ff, 0x00404811, 0x10b },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0002c400, 0x00204411, 0x000 },
- { 0x0000001f, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x112 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x00000013, 0x00203623, 0x000 },
- { 0x00000018, 0x40224a20, 0x000 },
- { 0x00000010, 0xc0424a20, 0x114 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x00000013, 0x00203623, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000000a, 0x00201011, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x11b },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00531224, 0x117 },
- { 0xffbfffff, 0x00283a2e, 0x000 },
- { 0x0000001b, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x12e },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0x00000018, 0x00220e30, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e00e, 0x00204411, 0x000 },
- { 0x07f8ff08, 0x00204811, 0x000 },
- { 0x00000000, 0x00294a23, 0x000 },
- { 0x0000001c, 0x00201e2d, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x00800000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204806, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x68a },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x689 },
- { 0x00000004, 0x00404c11, 0x135 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x0000001c, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68a },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x13c },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00000000, 0x00600000, 0x160 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40280620, 0x000 },
- { 0x00000010, 0xc0210a20, 0x000 },
- { 0x00000000, 0x00341461, 0x000 },
- { 0x00000000, 0x00741882, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x147 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x160 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0681a20, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x158 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000001, 0x00300a2f, 0x000 },
- { 0x00000001, 0x00210a22, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600000, 0x18f },
- { 0x00000000, 0x00600000, 0x1a0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00202c08, 0x000 },
- { 0x00000000, 0x00202411, 0x000 },
- { 0x00000000, 0x00202811, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000002, 0x00221e29, 0x000 },
- { 0x00000000, 0x007048eb, 0x19c },
- { 0x00000000, 0x00600000, 0x2bb },
- { 0x00000001, 0x40330620, 0x000 },
- { 0x00000000, 0xc0302409, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ae00000, 0x181 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x00000000, 0x00400000, 0x186 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x186 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000001, 0x00530621, 0x182 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0604800, 0x197 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000011, 0x0020062d, 0x000 },
- { 0x00000000, 0x0078042a, 0x2fb },
- { 0x00000000, 0x00202809, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x174 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000210, 0x00600411, 0x315 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x194 },
- { 0x00000015, 0xc0203620, 0x000 },
- { 0x00000016, 0xc0203620, 0x000 },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x46000000, 0x00600811, 0x1b2 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x19b },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000021, 0x00804811, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40281620, 0x000 },
- { 0x00000010, 0xc0811a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000008, 0x00221e30, 0x000 },
- { 0x00000029, 0x00201a2d, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfffbff09, 0x00204811, 0x000 },
- { 0x0000000f, 0x0020222d, 0x000 },
- { 0x00001fff, 0x00294a28, 0x000 },
- { 0x00000006, 0x0020222d, 0x000 },
- { 0x00000000, 0x002920e8, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a26, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000100, 0x00201811, 0x000 },
- { 0x00000008, 0x00621e28, 0x12f },
- { 0x00000008, 0x00822228, 0x000 },
- { 0x0002c000, 0x00204411, 0x000 },
- { 0x00000015, 0x00600e2d, 0x1bd },
- { 0x00000016, 0x00600e2d, 0x1bd },
- { 0x0000c008, 0x00204411, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0x00000000, 0x14c00000, 0x1b9 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x39000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00804802, 0x000 },
- { 0x00000018, 0x00202e2d, 0x000 },
- { 0x00000000, 0x003b0d63, 0x000 },
- { 0x00000008, 0x00224a23, 0x000 },
- { 0x00000010, 0x00224a23, 0x000 },
- { 0x00000018, 0x00224a23, 0x000 },
- { 0x00000000, 0x00804803, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00001000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00000007, 0x0021062f, 0x000 },
- { 0x00000013, 0x00200a2d, 0x000 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000ffff, 0x40282220, 0x000 },
- { 0x0000000f, 0x00262228, 0x000 },
- { 0x00000010, 0x40212620, 0x000 },
- { 0x0000000f, 0x00262629, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001b, 0x00204811, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1e0 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000081, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000080, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1dc },
- { 0x00000000, 0x00600000, 0x1e9 },
- { 0x00000001, 0x00531e27, 0x1d8 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000001f, 0x00280a22, 0x000 },
- { 0x0000001f, 0x00282a2a, 0x000 },
- { 0x00000001, 0x00530621, 0x1d1 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000002, 0x00304a2f, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000001, 0x00301e2f, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x1e9 },
- { 0x00000001, 0x00531e27, 0x1e5 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x0000000f, 0x00260e23, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000000f, 0x00261224, 0x000 },
- { 0x00000000, 0x00201411, 0x000 },
- { 0x00000000, 0x00601811, 0x2bb },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022b, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1f8 },
- { 0x00000010, 0x00221628, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a29, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x0020480a, 0x000 },
- { 0x00000000, 0x00202c11, 0x000 },
- { 0x00000010, 0x00221623, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a24, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x00731503, 0x205 },
- { 0x00000000, 0x00201805, 0x000 },
- { 0x00000000, 0x00731524, 0x205 },
- { 0x00000000, 0x002d14c5, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00000000, 0x00202003, 0x000 },
- { 0x00000000, 0x00802404, 0x000 },
- { 0x0000000f, 0x00210225, 0x000 },
- { 0x00000000, 0x14c00000, 0x689 },
- { 0x00000000, 0x002b1405, 0x000 },
- { 0x00000001, 0x00901625, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00294a22, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a21, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000ffff, 0x40281220, 0x000 },
- { 0x00000010, 0xc0211a20, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211620, 0x000 },
- { 0x00000000, 0x00741465, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00000001, 0x00330621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0cc00000, 0x219 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x212 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x642 },
- { 0x00000000, 0x0040040f, 0x213 },
- { 0x00000000, 0x00600000, 0x62e },
- { 0x00000000, 0x00600000, 0x642 },
- { 0x00000210, 0x00600411, 0x315 },
- { 0x00000000, 0x00600000, 0x1a0 },
- { 0x00000000, 0x00600000, 0x19c },
- { 0x00000000, 0x00600000, 0x2bb },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ae00000, 0x232 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x00000000, 0x00400000, 0x236 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x236 },
- { 0x00000000, 0xc0404800, 0x233 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x00600411, 0x2fb },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x62e },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000018, 0x40210a20, 0x000 },
- { 0x00000003, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x24c },
- { 0x00000014, 0x0020222d, 0x000 },
- { 0x00080101, 0x00292228, 0x000 },
- { 0x00000014, 0x00203628, 0x000 },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x251 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000010, 0x00600411, 0x315 },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x00000000, 0x00600000, 0x27c },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000001, 0x00211e27, 0x000 },
- { 0x00000000, 0x14e00000, 0x26a },
- { 0x00000012, 0x00201e2d, 0x000 },
- { 0x0000ffff, 0x00281e27, 0x000 },
- { 0x00000000, 0x00341c27, 0x000 },
- { 0x00000000, 0x12c00000, 0x25f },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e5, 0x000 },
- { 0x00000000, 0x08c00000, 0x262 },
- { 0x00000000, 0x00201407, 0x000 },
- { 0x00000012, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00211e27, 0x000 },
- { 0x00000000, 0x00341c47, 0x000 },
- { 0x00000000, 0x12c00000, 0x267 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x08c00000, 0x26a },
- { 0x00000000, 0x00201807, 0x000 },
- { 0x00000000, 0x00600000, 0x2c1 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000000, 0x00342023, 0x000 },
- { 0x00000000, 0x12c00000, 0x272 },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x271 },
- { 0x00000016, 0x00404811, 0x276 },
- { 0x00000018, 0x00404811, 0x276 },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x275 },
- { 0x00000017, 0x00404811, 0x276 },
- { 0x00000019, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00604411, 0x2e9 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x256 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000010, 0x40210620, 0x000 },
- { 0x0000ffff, 0xc0280a20, 0x000 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0881a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
- { 0x00000000, 0x00600000, 0x62e },
- { 0x00000000, 0xc0600000, 0x2a3 },
- { 0x00000005, 0x00200a2d, 0x000 },
- { 0x00000008, 0x00220a22, 0x000 },
- { 0x0000002b, 0x00201a2d, 0x000 },
- { 0x0000001c, 0x00201e2d, 0x000 },
- { 0x00007000, 0x00281e27, 0x000 },
- { 0x00000000, 0x00311ce6, 0x000 },
- { 0x0000002a, 0x00201a2d, 0x000 },
- { 0x0000000c, 0x00221a26, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x06e00000, 0x292 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x0000002b, 0x00203623, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00691ce2, 0x12f },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x29d },
- { 0x00000001, 0x00333e2f, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000001c, 0x00403627, 0x000 },
- { 0x0000000c, 0xc0220a20, 0x000 },
- { 0x00000029, 0x00203622, 0x000 },
- { 0x00000028, 0xc0403620, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000009, 0x00204811, 0x000 },
- { 0xa1000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce3, 0x000 },
- { 0x00000021, 0x00203627, 0x000 },
- { 0x00000022, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce4, 0x000 },
- { 0x00000022, 0x00203627, 0x000 },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a3, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x00000023, 0x00203627, 0x000 },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x00000024, 0x00803627, 0x000 },
- { 0x00000021, 0x00203623, 0x000 },
- { 0x00000022, 0x00203624, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000023, 0x00203627, 0x000 },
- { 0x00000000, 0x00311cc4, 0x000 },
- { 0x00000024, 0x00803627, 0x000 },
- { 0x0000001a, 0x00203627, 0x000 },
- { 0x0000001b, 0x00203628, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14c00000, 0x2dc },
- { 0x00000000, 0x00400000, 0x2d9 },
- { 0x0000001a, 0x00203627, 0x000 },
- { 0x0000001b, 0x00203628, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2d9 },
- { 0x00000003, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2dc },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e1, 0x000 },
- { 0x00000000, 0x02c00000, 0x2dc },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a1, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2dc },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e2, 0x000 },
- { 0x00000000, 0x02c00000, 0x2dc },
- { 0x00000022, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2dc },
- { 0x00000000, 0x00600000, 0x665 },
- { 0x00000000, 0x00600000, 0x2b5 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x00000000, 0x00600000, 0x2b5 },
- { 0x00000000, 0x00600000, 0x65c },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x00000000, 0x00600000, 0x2a7 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x0000001a, 0x00201e2d, 0x000 },
- { 0x0000001b, 0x0080222d, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca1, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x003808c5, 0x000 },
- { 0x00000000, 0x00300841, 0x000 },
- { 0x00000001, 0x00220a22, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000017, 0x0020222d, 0x000 },
- { 0x00000000, 0x14c00000, 0x318 },
- { 0xffffffef, 0x00280621, 0x000 },
- { 0x00000014, 0x0020222d, 0x000 },
- { 0x0000f8e0, 0x00204411, 0x000 },
- { 0x00000000, 0x00294901, 0x000 },
- { 0x00000000, 0x00894901, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00804811, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x97000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00002257, 0x00204411, 0x000 },
- { 0x00000003, 0xc0484a20, 0x000 },
- { 0x0000225d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x642 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x00000001, 0x40304a20, 0x000 },
- { 0x00000002, 0xc0304a20, 0x000 },
- { 0x00000001, 0x00530a22, 0x34b },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000018, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68a },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x354 },
- { 0x00000014, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x364 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00604802, 0x36e },
- { 0x00002100, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000004, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x36a },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x35f },
- { 0x00000028, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5bd },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x35f },
- { 0x0000002c, 0x00203626, 0x000 },
- { 0x00000049, 0x00201811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000000, 0x002f0226, 0x000 },
- { 0x00000000, 0x0cc00000, 0x370 },
- { 0x0000002c, 0x00801a2d, 0x000 },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x00000015, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x386 },
- { 0x00000006, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3b1 },
- { 0x00000016, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3b5 },
- { 0x00000020, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x39c },
- { 0x0000000f, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3a8 },
- { 0x00000010, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3a8 },
- { 0x0000001e, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x390 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x08000000, 0x00290a22, 0x000 },
- { 0x00000003, 0x40210e20, 0x000 },
- { 0x0000000c, 0xc0211220, 0x000 },
- { 0x00080000, 0x00281224, 0x000 },
- { 0x00000014, 0xc0221620, 0x000 },
- { 0x00000000, 0x002914a4, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x002948a2, 0x000 },
- { 0x0000a1fe, 0x00204411, 0x000 },
- { 0x00000000, 0x00404803, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68a },
- { 0x00000015, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x392 },
- { 0x0000210e, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000017, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68a },
- { 0x00000003, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x39e },
- { 0x00002108, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x80000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000010, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x3ae },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000006, 0x00404811, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36e },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x0000001d, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x3ce },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000018, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68a },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x3c0 },
- { 0x00002100, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0xbabecafe, 0x00204811, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000004, 0x00404811, 0x000 },
- { 0x00002170, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000a, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x3d3 },
- { 0x8c000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00003fff, 0x40280a20, 0x000 },
- { 0x80000000, 0x40280e20, 0x000 },
- { 0x40000000, 0xc0281220, 0x000 },
- { 0x00040000, 0x00694622, 0x68a },
- { 0x00000000, 0x00201410, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3e1 },
- { 0x00000000, 0xc0401800, 0x3e4 },
- { 0x00003fff, 0xc0281a20, 0x000 },
- { 0x00040000, 0x00694626, 0x68a },
- { 0x00000000, 0x00201810, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3e7 },
- { 0x00000000, 0xc0401c00, 0x3ea },
- { 0x00003fff, 0xc0281e20, 0x000 },
- { 0x00040000, 0x00694627, 0x68a },
- { 0x00000000, 0x00201c10, 0x000 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0x002820c5, 0x000 },
- { 0x00000000, 0x004948e8, 0x000 },
- { 0xa5800000, 0x00200811, 0x000 },
- { 0x00002000, 0x00200c11, 0x000 },
- { 0x83000000, 0x00604411, 0x412 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x0000001f, 0xc0210220, 0x000 },
- { 0x00000000, 0x14c00000, 0x3f7 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0000ffff, 0xc0481220, 0x3ff },
- { 0xa7800000, 0x00200811, 0x000 },
- { 0x0000a000, 0x00200c11, 0x000 },
- { 0x83000000, 0x00604411, 0x412 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x83000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00304883, 0x000 },
- { 0x84000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x1d000000, 0x000 },
- { 0x83000000, 0x00604411, 0x412 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0xa9800000, 0x00200811, 0x000 },
- { 0x0000c000, 0x00400c11, 0x3fa },
- { 0xab800000, 0x00200811, 0x000 },
- { 0x0000f8e0, 0x00400c11, 0x3fa },
- { 0xad800000, 0x00200811, 0x000 },
- { 0x0000f880, 0x00400c11, 0x3fa },
- { 0xb3800000, 0x00200811, 0x000 },
- { 0x0000f3fc, 0x00400c11, 0x3fa },
- { 0xaf800000, 0x00200811, 0x000 },
- { 0x0000e000, 0x00400c11, 0x3fa },
- { 0xb1800000, 0x00200811, 0x000 },
- { 0x0000f000, 0x00400c11, 0x3fa },
- { 0x83000000, 0x00204411, 0x000 },
- { 0x00002148, 0x00204811, 0x000 },
- { 0x84000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x1d000000, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x01182000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0218a000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0318c000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0418f8e0, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0518f880, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0618e000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0718f000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
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- { 0x0818f3fc, 0xc0304620, 0x000 },
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- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000000, 0xc0200800, 0x000 },
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- { 0x00000010, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x45e },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
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- { 0x00000000, 0x00400000, 0x463 },
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- { 0x00000001, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x46a },
- { 0x00000000, 0x002f00c9, 0x000 },
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- { 0x00000000, 0x002f00c9, 0x000 },
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- { 0x00000000, 0xc0404800, 0x000 },
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- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0400000, 0x000 },
- { 0x00000000, 0x00404c08, 0x456 },
- { 0x00000000, 0xc0200800, 0x000 },
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- { 0x00000012, 0x40211620, 0x000 },
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- { 0x00000000, 0x00204802, 0x000 },
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- { 0x00000000, 0x14e00000, 0x4a0 },
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- { 0xfffbffff, 0xc0284a20, 0x000 },
- { 0x00000000, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x4ad },
- { 0x00000000, 0xc0204800, 0x000 },
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- { 0x00000000, 0x00210224, 0x000 },
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- { 0x81000000, 0x00204411, 0x000 },
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- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x4a9 },
- { 0xa0000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
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- { 0x00000000, 0xc0204810, 0x000 },
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- { 0x00000000, 0xc0204810, 0x000 },
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- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00400000, 0x4a7 },
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- { 0x0000216d, 0x00204411, 0x000 },
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- { 0x00000000, 0xc0604800, 0x68f },
- { 0x00000000, 0x00400000, 0x4c4 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00040000, 0xc0294620, 0x000 },
- { 0x00000000, 0xc0600000, 0x68a },
- { 0x00000001, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x4cb },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
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- { 0x00000000, 0xc0404810, 0x000 },
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- { 0x00000001, 0x00204811, 0x000 },
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- { 0x0000000e, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68a },
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- { 0x00000001, 0x00210221, 0x000 },
- { 0x00000000, 0x14e00000, 0x4fd },
- { 0x0000002c, 0x00200a2d, 0x000 },
- { 0x00040000, 0x18e00c11, 0x4ec },
- { 0x00000001, 0x00333e2f, 0x000 },
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- { 0x00000000, 0x00204802, 0x000 },
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- { 0x00000000, 0x0029386e, 0x000 },
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- { 0xefffffff, 0x00283a2e, 0x000 },
- { 0x00000000, 0x004938ce, 0x678 },
- { 0x00000001, 0x40280a20, 0x000 },
- { 0x00000006, 0x40280e20, 0x000 },
- { 0x00000300, 0xc0281220, 0x000 },
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- { 0x00000000, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x563 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
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- { 0x00040000, 0x00694622, 0x68a },
- { 0x00002169, 0x00204411, 0x000 },
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- { 0x00000000, 0x00204810, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
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- { 0x00000000, 0x0cc00000, 0x56b },
- { 0x00000000, 0xc0201c10, 0x000 },
- { 0x00000000, 0xc0400000, 0x579 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x56b },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
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- { 0x00040000, 0x00694622, 0x68a },
- { 0x00000000, 0xc0201c10, 0x000 },
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- { 0x00000000, 0xc0604800, 0x68f },
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- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2b6, 0x00604411, 0x68a },
- { 0x0000001a, 0x00212230, 0x000 },
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- { 0x00000000, 0x003048e9, 0x000 },
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- { 0x0000a2d1, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d1, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x00000001, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x59d },
- { 0x0000a2bb, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2ba, 0x00604411, 0x68a },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
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- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x59b },
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- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d2, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x00000002, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5ae },
- { 0x0000a2bf, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2be, 0x00604411, 0x68a },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
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- { 0x0000a2c6, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x5ac },
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- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d3, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x0000a2c3, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2c2, 0x00604411, 0x68a },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
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- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x5bb },
- { 0x0000a2d4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d4, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x85000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x0000304a, 0x00204411, 0x000 },
- { 0x01000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00400000, 0x5c1 },
- { 0xa4000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0xc0600000, 0x5c6 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000002c, 0x00203621, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000000, 0x002f0230, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5cd },
- { 0x00000000, 0x00200411, 0x000 },
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- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x5e0 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a092, 0x00604411, 0x68a },
- { 0x00000031, 0x00203630, 0x000 },
- { 0x0004a093, 0x00604411, 0x68a },
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- { 0x0004a2ba, 0x00604411, 0x68a },
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- { 0x0004a2be, 0x00604411, 0x68a },
- { 0x00000035, 0x00203630, 0x000 },
- { 0x0004a2c2, 0x00604411, 0x68a },
- { 0x00000036, 0x00203630, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x00000005, 0x00204811, 0x000 },
- { 0x0000a1f4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x88000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000001, 0x002f0230, 0x000 },
- { 0x00000000, 0x0ce00000, 0x629 },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x629 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00007e00, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x602 },
- { 0x0000a092, 0x00204411, 0x000 },
- { 0x00000031, 0x00204a2d, 0x000 },
- { 0x0000a093, 0x00204411, 0x000 },
- { 0x00000032, 0x00204a2d, 0x000 },
- { 0x0000a2b6, 0x00204411, 0x000 },
- { 0x00000033, 0x00204a2d, 0x000 },
- { 0x0000a2ba, 0x00204411, 0x000 },
- { 0x00000034, 0x00204a2d, 0x000 },
- { 0x0000a2be, 0x00204411, 0x000 },
- { 0x00000035, 0x00204a2d, 0x000 },
- { 0x0000a2c2, 0x00204411, 0x000 },
- { 0x00000036, 0x00204a2d, 0x000 },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x000001ff, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x628 },
- { 0x00000000, 0x00210221, 0x000 },
- { 0x00000000, 0x14c00000, 0x60b },
- { 0x0004a003, 0x00604411, 0x68a },
- { 0x0000a003, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00000001, 0x00210621, 0x000 },
- { 0x00000000, 0x14c00000, 0x610 },
- { 0x0004a010, 0x00604411, 0x68a },
- { 0x0000a010, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00000001, 0x00210621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x628 },
- { 0x0004a011, 0x00604411, 0x68a },
- { 0x0000a011, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a012, 0x00604411, 0x68a },
- { 0x0000a012, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a013, 0x00604411, 0x68a },
- { 0x0000a013, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a014, 0x00604411, 0x68a },
- { 0x0000a014, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a015, 0x00604411, 0x68a },
- { 0x0000a015, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a016, 0x00604411, 0x68a },
- { 0x0000a016, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a017, 0x00604411, 0x68a },
- { 0x0000a017, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
- { 0x0000002c, 0x0080062d, 0x000 },
- { 0xff000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000002, 0x00804811, 0x000 },
- { 0x00000000, 0x0ee00000, 0x63a },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00000002, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x638 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
- { 0x00001000, 0x00200811, 0x000 },
- { 0x0000002b, 0x00203622, 0x000 },
- { 0x00000000, 0x00600000, 0x63e },
- { 0x00000000, 0x00600000, 0x5c6 },
- { 0x98000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00804811, 0x000 },
- { 0x00000000, 0xc0600000, 0x63e },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000022, 0x00204811, 0x000 },
- { 0x89000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00404811, 0x62a },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00404811, 0x62a },
- { 0x00000000, 0x00600000, 0x659 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0xc0204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36e },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00010000, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x09800000, 0x00204811, 0x000 },
- { 0xffffffff, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x68a },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000004, 0x00404c11, 0x653 },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000004, 0x00291e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0xfffffffb, 0x00281e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000008, 0x00291e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0xfffffff7, 0x00281e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36e },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00010000, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x01800000, 0x00204811, 0x000 },
- { 0xffffffff, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004217f, 0x00604411, 0x68a },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x689 },
- { 0x00000010, 0x00404c11, 0x66f },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x38c00000, 0x000 },
- { 0x0000001d, 0x00200a2d, 0x000 },
- { 0x0000001e, 0x00200e2d, 0x000 },
- { 0x0000001f, 0x0020122d, 0x000 },
- { 0x00000020, 0x0020162d, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000004, 0x00301224, 0x000 },
- { 0x00000000, 0x002f0064, 0x000 },
- { 0x00000000, 0x0cc00000, 0x688 },
- { 0x00000003, 0x00281a22, 0x000 },
- { 0x00000008, 0x00221222, 0x000 },
- { 0xfffff000, 0x00281224, 0x000 },
- { 0x00000000, 0x002910c4, 0x000 },
- { 0x0000001f, 0x00403624, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x1ac00000, 0x68a },
- { 0x9f000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000000, 0x1ae00000, 0x68d },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x1ac00000, 0x68f },
- { 0x9e000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000000, 0x1ae00000, 0x692 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00001000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001b, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0xc0204411, 0x000 },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000024, 0x0020222d, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000022, 0x0020222d, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00404811, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x014204ff, 0x05bd0250, 0x000 },
- { 0x01c30168, 0x043f05bd, 0x000 },
- { 0x02250209, 0x02500151, 0x000 },
- { 0x02230245, 0x02a00241, 0x000 },
- { 0x03d705bd, 0x05bd05bd, 0x000 },
- { 0x06460647, 0x031f05bd, 0x000 },
- { 0x05bd05c2, 0x03200340, 0x000 },
- { 0x032a0282, 0x03420334, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x05bd054e, 0x05bd05bd, 0x000 },
- { 0x03ba05bd, 0x04b80344, 0x000 },
- { 0x0497044d, 0x043d05bd, 0x000 },
- { 0x04cd05bd, 0x044104da, 0x000 },
- { 0x044d0504, 0x03510375, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x05bd05bd, 0x063c05c4, 0x000 },
- { 0x05bd05bd, 0x000705bd, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x03f803ed, 0x04080406, 0x000 },
- { 0x040e040a, 0x040c0410, 0x000 },
- { 0x041c0418, 0x04240420, 0x000 },
- { 0x042c0428, 0x04340430, 0x000 },
- { 0x05bd05bd, 0x043805bd, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x00020676, 0x06940006, 0x000 },
-};
-
-static const u32 RV630_pfp_microcode[] = {
-0xca0400,
-0xa00000,
-0x7e828b,
-0x7c038b,
-0x8001b8,
-0x7c038b,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581a8,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0fff0,
-0x042c04,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255403,
-0x7cd580,
-0x259c03,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d3,
-0xd5c01e,
-0xca0800,
-0x80001a,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800053,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xd48060,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001b8,
-0xd4c01e,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800000,
-0x062001,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x800079,
-0xd42013,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x80008d,
-0x000000,
-0xc41432,
-0xc61843,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800000,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xe4015e,
-0xd4001e,
-0x800000,
-0x062001,
-0xca1800,
-0x0a2001,
-0xd60076,
-0xc40836,
-0x988007,
-0xc61045,
-0x950110,
-0xd4001f,
-0xd46062,
-0x800000,
-0xd42062,
-0xcc3835,
-0xcc1433,
-0x8401bb,
-0xd40072,
-0xd5401e,
-0x800000,
-0xee001e,
-0xe2001a,
-0x8401bb,
-0xe2001a,
-0xcc104b,
-0xcc0447,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001b8,
-0xd4006d,
-0x344401,
-0xcc0c48,
-0x98403a,
-0xcc2c4a,
-0x958004,
-0xcc0449,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x8400f0,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x8400f0,
-0xcc1003,
-0x988017,
-0x043808,
-0x8400f0,
-0xcc1003,
-0x988013,
-0x043804,
-0x8400f0,
-0xcc1003,
-0x988014,
-0xcc104c,
-0x9a8009,
-0xcc144d,
-0x9840dc,
-0xd4006d,
-0xcc1848,
-0xd5001a,
-0xd5401a,
-0x8000c9,
-0xd5801a,
-0x96c0d5,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800000,
-0xec007f,
-0x9ac0cc,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809e,
-0xd4006d,
-0x98409c,
-0xd4006e,
-0xcc084c,
-0xcc0c4d,
-0xcc1048,
-0xd4801a,
-0xd4c01a,
-0x800101,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482d9,
-0xca0c00,
-0xd4401e,
-0x800000,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800000,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x9882bd,
-0x000000,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x9902b0,
-0x7c738b,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984297,
-0x000000,
-0x800161,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc104e,
-0x990004,
-0xd40073,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x950021,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x042802,
-0x7d8380,
-0xd5a86f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0xc82402,
-0x8001b8,
-0xd60076,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800000,
-0xee001e,
-0x800000,
-0xee001f,
-0xd4001f,
-0x800000,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010171,
-0x020178,
-0x03008f,
-0x04007f,
-0x050003,
-0x06003f,
-0x070032,
-0x08012c,
-0x090046,
-0x0a0036,
-0x1001b6,
-0x1700a2,
-0x22013a,
-0x230149,
-0x2000b4,
-0x240125,
-0x27004d,
-0x28006a,
-0x2a0060,
-0x2b0052,
-0x2f0065,
-0x320087,
-0x34017f,
-0x3c0156,
-0x3f0072,
-0x41018c,
-0x44012e,
-0x550173,
-0x56017a,
-0x60000b,
-0x610034,
-0x620038,
-0x630038,
-0x640038,
-0x650038,
-0x660038,
-0x670038,
-0x68003a,
-0x690041,
-0x6a0048,
-0x6b0048,
-0x6c0048,
-0x6d0048,
-0x6e0048,
-0x6f0048,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-};
-
-static const u32 RV635_cp_microcode[][3] = {
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0000ffff, 0x00284621, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00000000, 0x00e00000, 0x000 },
- { 0x00010000, 0xc0294620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
- { 0x00000000, 0x00600000, 0x62e },
- { 0x00000000, 0x00600000, 0x642 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000f00, 0x00281622, 0x000 },
- { 0x00000008, 0x00211625, 0x000 },
- { 0x00000018, 0x00203625, 0x000 },
- { 0x8d000000, 0x00204411, 0x000 },
- { 0x00000004, 0x002f0225, 0x000 },
- { 0x00000000, 0x0ce00000, 0x018 },
- { 0x00412000, 0x00404811, 0x019 },
- { 0x00422000, 0x00204811, 0x000 },
- { 0x8e000000, 0x00204411, 0x000 },
- { 0x00000028, 0x00204a2d, 0x000 },
- { 0x90000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x0000000c, 0x00211622, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x00000019, 0x00211a22, 0x000 },
- { 0x00000004, 0x00281a26, 0x000 },
- { 0x00000000, 0x002914c5, 0x000 },
- { 0x00000019, 0x00203625, 0x000 },
- { 0x00000000, 0x003a1402, 0x000 },
- { 0x00000016, 0x00211625, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0xfffffffc, 0x00280e23, 0x000 },
- { 0x00000000, 0x002914a3, 0x000 },
- { 0x00000017, 0x00203625, 0x000 },
- { 0x00008000, 0x00280e22, 0x000 },
- { 0x00000007, 0x00220e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x20000000, 0x00280e22, 0x000 },
- { 0x00000006, 0x00210e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x00000000, 0x00220222, 0x000 },
- { 0x00000000, 0x14e00000, 0x038 },
- { 0x00000000, 0x2ee00000, 0x035 },
- { 0x00000000, 0x2ce00000, 0x037 },
- { 0x00000000, 0x00400e2d, 0x039 },
- { 0x00000008, 0x00200e2d, 0x000 },
- { 0x00000009, 0x0040122d, 0x046 },
- { 0x00000001, 0x00400e2d, 0x039 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x03e },
- { 0x00000008, 0x00401c11, 0x041 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x0000000f, 0x00281e27, 0x000 },
- { 0x00000003, 0x00221e27, 0x000 },
- { 0x7fc00000, 0x00281a23, 0x000 },
- { 0x00000014, 0x00211a26, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000008, 0x00221a26, 0x000 },
- { 0x00000000, 0x00290cc7, 0x000 },
- { 0x00000027, 0x00203624, 0x000 },
- { 0x00007f00, 0x00281221, 0x000 },
- { 0x00001400, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x04b },
- { 0x00000001, 0x00290e23, 0x000 },
- { 0x0000000e, 0x00203623, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfff80000, 0x00294a23, 0x000 },
- { 0x00000000, 0x003a2c02, 0x000 },
- { 0x00000002, 0x00220e2b, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x0000000f, 0x00203623, 0x000 },
- { 0x00001fff, 0x00294a23, 0x000 },
- { 0x00000027, 0x00204a2d, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000029, 0x00200e2d, 0x000 },
- { 0x060a0200, 0x00294a23, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00210222, 0x000 },
- { 0x00000000, 0x14e00000, 0x061 },
- { 0x00000000, 0x2ee00000, 0x05f },
- { 0x00000000, 0x2ce00000, 0x05e },
- { 0x00000000, 0x00400e2d, 0x062 },
- { 0x00000001, 0x00400e2d, 0x062 },
- { 0x0000000a, 0x00200e2d, 0x000 },
- { 0x0000000b, 0x0040122d, 0x06a },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x7fc00000, 0x00281623, 0x000 },
- { 0x00000014, 0x00211625, 0x000 },
- { 0x00000001, 0x00331625, 0x000 },
- { 0x80000000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00290ca3, 0x000 },
- { 0x3ffffc00, 0x00290e23, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x06d },
- { 0x00000100, 0x00401c11, 0x070 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x000000f0, 0x00281e27, 0x000 },
- { 0x00000004, 0x00221e27, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0xfffff0ff, 0x00281a30, 0x000 },
- { 0x0000a028, 0x00204411, 0x000 },
- { 0x00000000, 0x002948e6, 0x000 },
- { 0x0000a018, 0x00204411, 0x000 },
- { 0x3fffffff, 0x00284a23, 0x000 },
- { 0x0000a010, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000030, 0x0020162d, 0x000 },
- { 0x00000002, 0x00291625, 0x000 },
- { 0x00000030, 0x00203625, 0x000 },
- { 0x00000025, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a3, 0x000 },
- { 0x00000000, 0x0cc00000, 0x083 },
- { 0x00000026, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a4, 0x000 },
- { 0x00000000, 0x0cc00000, 0x084 },
- { 0x00000000, 0x00400000, 0x08a },
- { 0x00000025, 0x00203623, 0x000 },
- { 0x00000026, 0x00203624, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x08a },
- { 0x00000000, 0x00600000, 0x665 },
- { 0x00000000, 0x00600000, 0x659 },
- { 0x00000002, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x08d },
- { 0x00000012, 0xc0403620, 0x093 },
- { 0x00000000, 0x2ee00000, 0x091 },
- { 0x00000000, 0x2ce00000, 0x090 },
- { 0x00000002, 0x00400e2d, 0x092 },
- { 0x00000003, 0x00400e2d, 0x092 },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000012, 0x00203623, 0x000 },
- { 0x00000003, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x098 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x0a0 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x2ee00000, 0x09e },
- { 0x00000000, 0x2ce00000, 0x09d },
- { 0x00000002, 0x00400e2d, 0x09f },
- { 0x00000003, 0x00400e2d, 0x09f },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x003f0000, 0x00280e23, 0x000 },
- { 0x00000010, 0x00210e23, 0x000 },
- { 0x00000011, 0x00203623, 0x000 },
- { 0x0000001e, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0a7 },
- { 0x00000016, 0xc0203620, 0x000 },
- { 0x0000001f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0aa },
- { 0x00000015, 0xc0203620, 0x000 },
- { 0x00000008, 0x00210e2b, 0x000 },
- { 0x0000007f, 0x00280e23, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0e1 },
- { 0x00000000, 0x27000000, 0x000 },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ae00000, 0x0b3 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x0000000c, 0x00221e30, 0x000 },
- { 0x99800000, 0x00204411, 0x000 },
- { 0x00000004, 0x0020122d, 0x000 },
- { 0x00000008, 0x00221224, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00291ce4, 0x000 },
- { 0x00000000, 0x00604807, 0x12f },
- { 0x9b000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x9c000000, 0x00204411, 0x000 },
- { 0x00000000, 0x0033146f, 0x000 },
- { 0x00000001, 0x00333e23, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0x00203c05, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e007, 0x00204411, 0x000 },
- { 0x0000000f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0cb },
- { 0x00f8ff08, 0x00204811, 0x000 },
- { 0x98000000, 0x00404811, 0x0dc },
- { 0x000000f0, 0x00280e22, 0x000 },
- { 0x000000a0, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x0da },
- { 0x00000011, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0d5 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0d4 },
- { 0x00003f00, 0x00400c11, 0x0d6 },
- { 0x00001f00, 0x00400c11, 0x0d6 },
- { 0x00000f00, 0x00200c11, 0x000 },
- { 0x00380009, 0x00294a23, 0x000 },
- { 0x3f000000, 0x00280e2b, 0x000 },
- { 0x00000002, 0x00220e23, 0x000 },
- { 0x00000007, 0x00494a23, 0x0dc },
- { 0x00380f09, 0x00204811, 0x000 },
- { 0x68000007, 0x00204811, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000a202, 0x00204411, 0x000 },
- { 0x00ff0000, 0x00280e22, 0x000 },
- { 0x00000080, 0x00294a23, 0x000 },
- { 0x00000027, 0x00200e2d, 0x000 },
- { 0x00000026, 0x0020122d, 0x000 },
- { 0x00000000, 0x002f0083, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0ea },
- { 0x00000000, 0x00600000, 0x65f },
- { 0x00000000, 0x00400000, 0x0eb },
- { 0x00000000, 0x00600000, 0x662 },
- { 0x00000007, 0x0020222d, 0x000 },
- { 0x00000005, 0x00220e22, 0x000 },
- { 0x00100000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x000000ef, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0x00000003, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x0f8 },
- { 0x0000000b, 0x00210228, 0x000 },
- { 0x00000000, 0x14c00000, 0x0f8 },
- { 0x00000400, 0x00292228, 0x000 },
- { 0x00000014, 0x00203628, 0x000 },
- { 0x0000001c, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x0fd },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000001e, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x10b },
- { 0x0000a30f, 0x00204411, 0x000 },
- { 0x00000011, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x104 },
- { 0xffffffff, 0x00404811, 0x10b },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x107 },
- { 0x0000ffff, 0x00404811, 0x10b },
- { 0x00000004, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x10a },
- { 0x000000ff, 0x00404811, 0x10b },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0002c400, 0x00204411, 0x000 },
- { 0x0000001f, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x112 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x00000013, 0x00203623, 0x000 },
- { 0x00000018, 0x40224a20, 0x000 },
- { 0x00000010, 0xc0424a20, 0x114 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x00000013, 0x00203623, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000000a, 0x00201011, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x11b },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00531224, 0x117 },
- { 0xffbfffff, 0x00283a2e, 0x000 },
- { 0x0000001b, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x12e },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0x00000018, 0x00220e30, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e00e, 0x00204411, 0x000 },
- { 0x07f8ff08, 0x00204811, 0x000 },
- { 0x00000000, 0x00294a23, 0x000 },
- { 0x0000001c, 0x00201e2d, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x00800000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204806, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x68a },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x689 },
- { 0x00000004, 0x00404c11, 0x135 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x0000001c, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68a },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x13c },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00000000, 0x00600000, 0x160 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40280620, 0x000 },
- { 0x00000010, 0xc0210a20, 0x000 },
- { 0x00000000, 0x00341461, 0x000 },
- { 0x00000000, 0x00741882, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x147 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x160 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0681a20, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x158 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000001, 0x00300a2f, 0x000 },
- { 0x00000001, 0x00210a22, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600000, 0x18f },
- { 0x00000000, 0x00600000, 0x1a0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00202c08, 0x000 },
- { 0x00000000, 0x00202411, 0x000 },
- { 0x00000000, 0x00202811, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000002, 0x00221e29, 0x000 },
- { 0x00000000, 0x007048eb, 0x19c },
- { 0x00000000, 0x00600000, 0x2bb },
- { 0x00000001, 0x40330620, 0x000 },
- { 0x00000000, 0xc0302409, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ae00000, 0x181 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x00000000, 0x00400000, 0x186 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x186 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000001, 0x00530621, 0x182 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0604800, 0x197 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000011, 0x0020062d, 0x000 },
- { 0x00000000, 0x0078042a, 0x2fb },
- { 0x00000000, 0x00202809, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x174 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000210, 0x00600411, 0x315 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x194 },
- { 0x00000015, 0xc0203620, 0x000 },
- { 0x00000016, 0xc0203620, 0x000 },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x46000000, 0x00600811, 0x1b2 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x19b },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000021, 0x00804811, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40281620, 0x000 },
- { 0x00000010, 0xc0811a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000008, 0x00221e30, 0x000 },
- { 0x00000029, 0x00201a2d, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfffbff09, 0x00204811, 0x000 },
- { 0x0000000f, 0x0020222d, 0x000 },
- { 0x00001fff, 0x00294a28, 0x000 },
- { 0x00000006, 0x0020222d, 0x000 },
- { 0x00000000, 0x002920e8, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a26, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000100, 0x00201811, 0x000 },
- { 0x00000008, 0x00621e28, 0x12f },
- { 0x00000008, 0x00822228, 0x000 },
- { 0x0002c000, 0x00204411, 0x000 },
- { 0x00000015, 0x00600e2d, 0x1bd },
- { 0x00000016, 0x00600e2d, 0x1bd },
- { 0x0000c008, 0x00204411, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0x00000000, 0x14c00000, 0x1b9 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x39000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00804802, 0x000 },
- { 0x00000018, 0x00202e2d, 0x000 },
- { 0x00000000, 0x003b0d63, 0x000 },
- { 0x00000008, 0x00224a23, 0x000 },
- { 0x00000010, 0x00224a23, 0x000 },
- { 0x00000018, 0x00224a23, 0x000 },
- { 0x00000000, 0x00804803, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00001000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00000007, 0x0021062f, 0x000 },
- { 0x00000013, 0x00200a2d, 0x000 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000ffff, 0x40282220, 0x000 },
- { 0x0000000f, 0x00262228, 0x000 },
- { 0x00000010, 0x40212620, 0x000 },
- { 0x0000000f, 0x00262629, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001b, 0x00204811, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1e0 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000081, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000080, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1dc },
- { 0x00000000, 0x00600000, 0x1e9 },
- { 0x00000001, 0x00531e27, 0x1d8 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000001f, 0x00280a22, 0x000 },
- { 0x0000001f, 0x00282a2a, 0x000 },
- { 0x00000001, 0x00530621, 0x1d1 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000002, 0x00304a2f, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000001, 0x00301e2f, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x1e9 },
- { 0x00000001, 0x00531e27, 0x1e5 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x0000000f, 0x00260e23, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000000f, 0x00261224, 0x000 },
- { 0x00000000, 0x00201411, 0x000 },
- { 0x00000000, 0x00601811, 0x2bb },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022b, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1f8 },
- { 0x00000010, 0x00221628, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a29, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x0020480a, 0x000 },
- { 0x00000000, 0x00202c11, 0x000 },
- { 0x00000010, 0x00221623, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a24, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x00731503, 0x205 },
- { 0x00000000, 0x00201805, 0x000 },
- { 0x00000000, 0x00731524, 0x205 },
- { 0x00000000, 0x002d14c5, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00000000, 0x00202003, 0x000 },
- { 0x00000000, 0x00802404, 0x000 },
- { 0x0000000f, 0x00210225, 0x000 },
- { 0x00000000, 0x14c00000, 0x689 },
- { 0x00000000, 0x002b1405, 0x000 },
- { 0x00000001, 0x00901625, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00294a22, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a21, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000ffff, 0x40281220, 0x000 },
- { 0x00000010, 0xc0211a20, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211620, 0x000 },
- { 0x00000000, 0x00741465, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00000001, 0x00330621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0cc00000, 0x219 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x212 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x642 },
- { 0x00000000, 0x0040040f, 0x213 },
- { 0x00000000, 0x00600000, 0x62e },
- { 0x00000000, 0x00600000, 0x642 },
- { 0x00000210, 0x00600411, 0x315 },
- { 0x00000000, 0x00600000, 0x1a0 },
- { 0x00000000, 0x00600000, 0x19c },
- { 0x00000000, 0x00600000, 0x2bb },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ae00000, 0x232 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x00000000, 0x00400000, 0x236 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x236 },
- { 0x00000000, 0xc0404800, 0x233 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x00600411, 0x2fb },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x62e },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000018, 0x40210a20, 0x000 },
- { 0x00000003, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x24c },
- { 0x00000014, 0x0020222d, 0x000 },
- { 0x00080101, 0x00292228, 0x000 },
- { 0x00000014, 0x00203628, 0x000 },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x251 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000010, 0x00600411, 0x315 },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x00000000, 0x00600000, 0x27c },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000001, 0x00211e27, 0x000 },
- { 0x00000000, 0x14e00000, 0x26a },
- { 0x00000012, 0x00201e2d, 0x000 },
- { 0x0000ffff, 0x00281e27, 0x000 },
- { 0x00000000, 0x00341c27, 0x000 },
- { 0x00000000, 0x12c00000, 0x25f },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e5, 0x000 },
- { 0x00000000, 0x08c00000, 0x262 },
- { 0x00000000, 0x00201407, 0x000 },
- { 0x00000012, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00211e27, 0x000 },
- { 0x00000000, 0x00341c47, 0x000 },
- { 0x00000000, 0x12c00000, 0x267 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x08c00000, 0x26a },
- { 0x00000000, 0x00201807, 0x000 },
- { 0x00000000, 0x00600000, 0x2c1 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000000, 0x00342023, 0x000 },
- { 0x00000000, 0x12c00000, 0x272 },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x271 },
- { 0x00000016, 0x00404811, 0x276 },
- { 0x00000018, 0x00404811, 0x276 },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x275 },
- { 0x00000017, 0x00404811, 0x276 },
- { 0x00000019, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00604411, 0x2e9 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x256 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000010, 0x40210620, 0x000 },
- { 0x0000ffff, 0xc0280a20, 0x000 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0881a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
- { 0x00000000, 0x00600000, 0x62e },
- { 0x00000000, 0xc0600000, 0x2a3 },
- { 0x00000005, 0x00200a2d, 0x000 },
- { 0x00000008, 0x00220a22, 0x000 },
- { 0x0000002b, 0x00201a2d, 0x000 },
- { 0x0000001c, 0x00201e2d, 0x000 },
- { 0x00007000, 0x00281e27, 0x000 },
- { 0x00000000, 0x00311ce6, 0x000 },
- { 0x0000002a, 0x00201a2d, 0x000 },
- { 0x0000000c, 0x00221a26, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x06e00000, 0x292 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x0000002b, 0x00203623, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00691ce2, 0x12f },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x29d },
- { 0x00000001, 0x00333e2f, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000001c, 0x00403627, 0x000 },
- { 0x0000000c, 0xc0220a20, 0x000 },
- { 0x00000029, 0x00203622, 0x000 },
- { 0x00000028, 0xc0403620, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000009, 0x00204811, 0x000 },
- { 0xa1000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce3, 0x000 },
- { 0x00000021, 0x00203627, 0x000 },
- { 0x00000022, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce4, 0x000 },
- { 0x00000022, 0x00203627, 0x000 },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a3, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x00000023, 0x00203627, 0x000 },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x00000024, 0x00803627, 0x000 },
- { 0x00000021, 0x00203623, 0x000 },
- { 0x00000022, 0x00203624, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000023, 0x00203627, 0x000 },
- { 0x00000000, 0x00311cc4, 0x000 },
- { 0x00000024, 0x00803627, 0x000 },
- { 0x0000001a, 0x00203627, 0x000 },
- { 0x0000001b, 0x00203628, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14c00000, 0x2dc },
- { 0x00000000, 0x00400000, 0x2d9 },
- { 0x0000001a, 0x00203627, 0x000 },
- { 0x0000001b, 0x00203628, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2d9 },
- { 0x00000003, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2dc },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e1, 0x000 },
- { 0x00000000, 0x02c00000, 0x2dc },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a1, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2dc },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e2, 0x000 },
- { 0x00000000, 0x02c00000, 0x2dc },
- { 0x00000022, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2dc },
- { 0x00000000, 0x00600000, 0x665 },
- { 0x00000000, 0x00600000, 0x2b5 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x00000000, 0x00600000, 0x2b5 },
- { 0x00000000, 0x00600000, 0x65c },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x00000000, 0x00600000, 0x2a7 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x0000001a, 0x00201e2d, 0x000 },
- { 0x0000001b, 0x0080222d, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca1, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x003808c5, 0x000 },
- { 0x00000000, 0x00300841, 0x000 },
- { 0x00000001, 0x00220a22, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000017, 0x0020222d, 0x000 },
- { 0x00000000, 0x14c00000, 0x318 },
- { 0xffffffef, 0x00280621, 0x000 },
- { 0x00000014, 0x0020222d, 0x000 },
- { 0x0000f8e0, 0x00204411, 0x000 },
- { 0x00000000, 0x00294901, 0x000 },
- { 0x00000000, 0x00894901, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00804811, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x97000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00002257, 0x00204411, 0x000 },
- { 0x00000003, 0xc0484a20, 0x000 },
- { 0x0000225d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x642 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x00000001, 0x40304a20, 0x000 },
- { 0x00000002, 0xc0304a20, 0x000 },
- { 0x00000001, 0x00530a22, 0x34b },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000018, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68a },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x354 },
- { 0x00000014, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x364 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00604802, 0x36e },
- { 0x00002100, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000004, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x36a },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x35f },
- { 0x00000028, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5bd },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x35f },
- { 0x0000002c, 0x00203626, 0x000 },
- { 0x00000049, 0x00201811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000000, 0x002f0226, 0x000 },
- { 0x00000000, 0x0cc00000, 0x370 },
- { 0x0000002c, 0x00801a2d, 0x000 },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x00000015, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x386 },
- { 0x00000006, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3b1 },
- { 0x00000016, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3b5 },
- { 0x00000020, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x39c },
- { 0x0000000f, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3a8 },
- { 0x00000010, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3a8 },
- { 0x0000001e, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x390 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
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- { 0x0000000c, 0xc0211220, 0x000 },
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- { 0x00000000, 0x002914a4, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x002948a2, 0x000 },
- { 0x0000a1fe, 0x00204411, 0x000 },
- { 0x00000000, 0x00404803, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68a },
- { 0x00000015, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x392 },
- { 0x0000210e, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000017, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68a },
- { 0x00000003, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x39e },
- { 0x00002108, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x80000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000010, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x3ae },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000006, 0x00404811, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36e },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x0000001d, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x3ce },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000018, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68a },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x3c0 },
- { 0x00002100, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0xbabecafe, 0x00204811, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000004, 0x00404811, 0x000 },
- { 0x00002170, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000a, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x3d3 },
- { 0x8c000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00003fff, 0x40280a20, 0x000 },
- { 0x80000000, 0x40280e20, 0x000 },
- { 0x40000000, 0xc0281220, 0x000 },
- { 0x00040000, 0x00694622, 0x68a },
- { 0x00000000, 0x00201410, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3e1 },
- { 0x00000000, 0xc0401800, 0x3e4 },
- { 0x00003fff, 0xc0281a20, 0x000 },
- { 0x00040000, 0x00694626, 0x68a },
- { 0x00000000, 0x00201810, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3e7 },
- { 0x00000000, 0xc0401c00, 0x3ea },
- { 0x00003fff, 0xc0281e20, 0x000 },
- { 0x00040000, 0x00694627, 0x68a },
- { 0x00000000, 0x00201c10, 0x000 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0x002820c5, 0x000 },
- { 0x00000000, 0x004948e8, 0x000 },
- { 0xa5800000, 0x00200811, 0x000 },
- { 0x00002000, 0x00200c11, 0x000 },
- { 0x83000000, 0x00604411, 0x412 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x0000001f, 0xc0210220, 0x000 },
- { 0x00000000, 0x14c00000, 0x3f7 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0000ffff, 0xc0481220, 0x3ff },
- { 0xa7800000, 0x00200811, 0x000 },
- { 0x0000a000, 0x00200c11, 0x000 },
- { 0x83000000, 0x00604411, 0x412 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x83000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00304883, 0x000 },
- { 0x84000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x1d000000, 0x000 },
- { 0x83000000, 0x00604411, 0x412 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0xa9800000, 0x00200811, 0x000 },
- { 0x0000c000, 0x00400c11, 0x3fa },
- { 0xab800000, 0x00200811, 0x000 },
- { 0x0000f8e0, 0x00400c11, 0x3fa },
- { 0xad800000, 0x00200811, 0x000 },
- { 0x0000f880, 0x00400c11, 0x3fa },
- { 0xb3800000, 0x00200811, 0x000 },
- { 0x0000f3fc, 0x00400c11, 0x3fa },
- { 0xaf800000, 0x00200811, 0x000 },
- { 0x0000e000, 0x00400c11, 0x3fa },
- { 0xb1800000, 0x00200811, 0x000 },
- { 0x0000f000, 0x00400c11, 0x3fa },
- { 0x83000000, 0x00204411, 0x000 },
- { 0x00002148, 0x00204811, 0x000 },
- { 0x84000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x1d000000, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x01182000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0218a000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0318c000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0418f8e0, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0518f880, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0618e000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0718f000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0818f3fc, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00000030, 0x00200a2d, 0x000 },
- { 0x00000000, 0xc0290c40, 0x000 },
- { 0x00000030, 0x00203623, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x86000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00404801, 0x000 },
- { 0x85000000, 0xc0204411, 0x000 },
- { 0x00000000, 0x00404801, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x68a },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000000, 0x00404c02, 0x448 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x00000000, 0xc0201000, 0x000 },
- { 0x00000000, 0xc0201400, 0x000 },
- { 0x00000000, 0xc0201800, 0x000 },
- { 0x00000000, 0xc0201c00, 0x000 },
- { 0x00007f00, 0x00280a21, 0x000 },
- { 0x00004500, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x456 },
- { 0x00000000, 0xc0202000, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x00000010, 0x00280a23, 0x000 },
- { 0x00000010, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x45e },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00040000, 0x00694624, 0x68a },
- { 0x00000000, 0x00400000, 0x463 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000216d, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000000, 0x00604805, 0x68f },
- { 0x00000000, 0x002824f0, 0x000 },
- { 0x00000007, 0x00280a23, 0x000 },
- { 0x00000001, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x46a },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x04e00000, 0x483 },
- { 0x00000000, 0x00400000, 0x490 },
- { 0x00000002, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x46f },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x02e00000, 0x483 },
- { 0x00000000, 0x00400000, 0x490 },
- { 0x00000003, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x474 },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x0ce00000, 0x483 },
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- { 0x00000004, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x479 },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x0ae00000, 0x483 },
- { 0x00000000, 0x00400000, 0x490 },
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- { 0x00000000, 0x0ae00000, 0x47e },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x06e00000, 0x483 },
- { 0x00000000, 0x00400000, 0x490 },
- { 0x00000006, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x483 },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x08e00000, 0x483 },
- { 0x00000000, 0x00400000, 0x490 },
- { 0x00007f00, 0x00280a21, 0x000 },
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- { 0x00000000, 0x0ae00000, 0x000 },
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- { 0x00000000, 0x14c00000, 0x48d },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x00000000, 0xc0204400, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00007f00, 0x00280a21, 0x000 },
- { 0x00004500, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x496 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0400000, 0x000 },
- { 0x00000000, 0x00404c08, 0x456 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x00000011, 0x40211220, 0x000 },
- { 0x00000012, 0x40211620, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00210225, 0x000 },
- { 0x00000000, 0x14e00000, 0x4a0 },
- { 0x00040000, 0xc0494a20, 0x4a1 },
- { 0xfffbffff, 0xc0284a20, 0x000 },
- { 0x00000000, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x4ad },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x00210224, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000c, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x4a9 },
- { 0xa0000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000004, 0x00204811, 0x000 },
- { 0x0000216b, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204810, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000005, 0x00204811, 0x000 },
- { 0x0000216c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204810, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00400000, 0x4a7 },
- { 0x00000000, 0xc0210a20, 0x000 },
- { 0x00000000, 0x14c00000, 0x4c0 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000216d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0604800, 0x68f },
- { 0x00000000, 0x00400000, 0x4c4 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00040000, 0xc0294620, 0x000 },
- { 0x00000000, 0xc0600000, 0x68a },
- { 0x00000001, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x4cb },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x00000000, 0xc0204400, 0x000 },
- { 0x00000000, 0xc0404810, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x68a },
- { 0x00000000, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x4cd },
- { 0x00002180, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000003, 0x00333e2f, 0x000 },
- { 0x00000001, 0x00210221, 0x000 },
- { 0x00000000, 0x14e00000, 0x4fd },
- { 0x0000002c, 0x00200a2d, 0x000 },
- { 0x00040000, 0x18e00c11, 0x4ec },
- { 0x00000001, 0x00333e2f, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000008, 0x00300a22, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000008, 0x00300a22, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xd8c04800, 0x4e0 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000008, 0x00300a22, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000002d, 0x0020122d, 0x000 },
- { 0x00000000, 0x00290c83, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000008, 0x00300a22, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000011, 0x00210224, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000000, 0x00400000, 0x4a7 },
- { 0x0000002c, 0xc0203620, 0x000 },
- { 0x0000002d, 0xc0403620, 0x000 },
- { 0x0000000f, 0x00210221, 0x000 },
- { 0x00000000, 0x14c00000, 0x502 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0xd9000000, 0x000 },
- { 0x00000000, 0xc0400400, 0x001 },
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- { 0x00002000, 0x00204811, 0x000 },
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- { 0x0000a000, 0x00204811, 0x000 },
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- { 0x0000f880, 0x00204811, 0x000 },
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- { 0xbb000000, 0x00204411, 0x000 },
- { 0x0000f000, 0x00204811, 0x000 },
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- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000002, 0x00204811, 0x000 },
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- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x516 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0x14c00000, 0x52b },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x0000001c, 0x00203623, 0x000 },
- { 0x0000002b, 0x00203623, 0x000 },
- { 0x00000029, 0x00203623, 0x000 },
- { 0x00000028, 0x00203623, 0x000 },
- { 0x00000017, 0x00203623, 0x000 },
- { 0x00000025, 0x00203623, 0x000 },
- { 0x00000026, 0x00203623, 0x000 },
- { 0x00000015, 0x00203623, 0x000 },
- { 0x00000016, 0x00203623, 0x000 },
- { 0xffffe000, 0x00200c11, 0x000 },
- { 0x00000021, 0x00203623, 0x000 },
- { 0x00000022, 0x00203623, 0x000 },
- { 0x00001fff, 0x00200c11, 0x000 },
- { 0x00000023, 0x00203623, 0x000 },
- { 0x00000024, 0x00203623, 0x000 },
- { 0xf1ffffff, 0x00283a2e, 0x000 },
- { 0x0000001a, 0xc0220e20, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
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- { 0x87000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
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- { 0x00000000, 0x00204810, 0x000 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x00000030, 0x00203623, 0x000 },
- { 0x9d000000, 0x00204411, 0x000 },
- { 0x0000001f, 0x40214a20, 0x000 },
- { 0x96000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x00000000, 0xc0201000, 0x000 },
- { 0x0000001f, 0x00211624, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x0000001d, 0x00203623, 0x000 },
- { 0x00000003, 0x00281e23, 0x000 },
- { 0x00000008, 0x00222223, 0x000 },
- { 0xfffff000, 0x00282228, 0x000 },
- { 0x00000000, 0x002920e8, 0x000 },
- { 0x0000001f, 0x00203628, 0x000 },
- { 0x00000018, 0x00211e23, 0x000 },
- { 0x00000020, 0x00203627, 0x000 },
- { 0x00000002, 0x00221624, 0x000 },
- { 0x00000000, 0x003014a8, 0x000 },
- { 0x0000001e, 0x00203625, 0x000 },
- { 0x00000003, 0x00211a24, 0x000 },
- { 0x10000000, 0x00281a26, 0x000 },
- { 0xefffffff, 0x00283a2e, 0x000 },
- { 0x00000000, 0x004938ce, 0x678 },
- { 0x00000001, 0x40280a20, 0x000 },
- { 0x00000006, 0x40280e20, 0x000 },
- { 0x00000300, 0xc0281220, 0x000 },
- { 0x00000008, 0x00211224, 0x000 },
- { 0x00000000, 0xc0201620, 0x000 },
- { 0x00000000, 0xc0201a20, 0x000 },
- { 0x00000000, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x563 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00002258, 0x00300a24, 0x000 },
- { 0x00040000, 0x00694622, 0x68a },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x00020000, 0x00294a26, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x56b },
- { 0x00000000, 0xc0201c10, 0x000 },
- { 0x00000000, 0xc0400000, 0x579 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x56b },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00002258, 0x00300a24, 0x000 },
- { 0x00040000, 0x00694622, 0x68a },
- { 0x00000000, 0xc0201c10, 0x000 },
- { 0x00000000, 0xc0400000, 0x579 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x56f },
- { 0x00000000, 0xc0201c00, 0x000 },
- { 0x00000000, 0xc0400000, 0x579 },
- { 0x00000004, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x577 },
- { 0x81000000, 0x00204411, 0x000 },
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- { 0x0000216d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0604800, 0x68f },
- { 0x00000000, 0x00401c10, 0x579 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0400000, 0x000 },
- { 0x00000000, 0x0ee00000, 0x57b },
- { 0x00000000, 0x00600000, 0x5c6 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x58c },
- { 0x0000a2b7, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2b6, 0x00604411, 0x68a },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
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- { 0x0000a2c4, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x58a },
- { 0x0000a2d1, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d1, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x00000001, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x59d },
- { 0x0000a2bb, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2ba, 0x00604411, 0x68a },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
- { 0x0000a2c5, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x59b },
- { 0x0000a2d2, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d2, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x00000002, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5ae },
- { 0x0000a2bf, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2be, 0x00604411, 0x68a },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
- { 0x0000a2c6, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x5ac },
- { 0x0000a2d3, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d3, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x0000a2c3, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2c2, 0x00604411, 0x68a },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
- { 0x0000a2c7, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x5bb },
- { 0x0000a2d4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d4, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x85000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x0000304a, 0x00204411, 0x000 },
- { 0x01000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00400000, 0x5c1 },
- { 0xa4000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0xc0600000, 0x5c6 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000002c, 0x00203621, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000000, 0x002f0230, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5cd },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000030, 0x00403621, 0x5e0 },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00007e00, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x5e0 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a092, 0x00604411, 0x68a },
- { 0x00000031, 0x00203630, 0x000 },
- { 0x0004a093, 0x00604411, 0x68a },
- { 0x00000032, 0x00203630, 0x000 },
- { 0x0004a2b6, 0x00604411, 0x68a },
- { 0x00000033, 0x00203630, 0x000 },
- { 0x0004a2ba, 0x00604411, 0x68a },
- { 0x00000034, 0x00203630, 0x000 },
- { 0x0004a2be, 0x00604411, 0x68a },
- { 0x00000035, 0x00203630, 0x000 },
- { 0x0004a2c2, 0x00604411, 0x68a },
- { 0x00000036, 0x00203630, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x00000005, 0x00204811, 0x000 },
- { 0x0000a1f4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x88000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000001, 0x002f0230, 0x000 },
- { 0x00000000, 0x0ce00000, 0x629 },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x629 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00007e00, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x602 },
- { 0x0000a092, 0x00204411, 0x000 },
- { 0x00000031, 0x00204a2d, 0x000 },
- { 0x0000a093, 0x00204411, 0x000 },
- { 0x00000032, 0x00204a2d, 0x000 },
- { 0x0000a2b6, 0x00204411, 0x000 },
- { 0x00000033, 0x00204a2d, 0x000 },
- { 0x0000a2ba, 0x00204411, 0x000 },
- { 0x00000034, 0x00204a2d, 0x000 },
- { 0x0000a2be, 0x00204411, 0x000 },
- { 0x00000035, 0x00204a2d, 0x000 },
- { 0x0000a2c2, 0x00204411, 0x000 },
- { 0x00000036, 0x00204a2d, 0x000 },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x000001ff, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x628 },
- { 0x00000000, 0x00210221, 0x000 },
- { 0x00000000, 0x14c00000, 0x60b },
- { 0x0004a003, 0x00604411, 0x68a },
- { 0x0000a003, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00000001, 0x00210621, 0x000 },
- { 0x00000000, 0x14c00000, 0x610 },
- { 0x0004a010, 0x00604411, 0x68a },
- { 0x0000a010, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00000001, 0x00210621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x628 },
- { 0x0004a011, 0x00604411, 0x68a },
- { 0x0000a011, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a012, 0x00604411, 0x68a },
- { 0x0000a012, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a013, 0x00604411, 0x68a },
- { 0x0000a013, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a014, 0x00604411, 0x68a },
- { 0x0000a014, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a015, 0x00604411, 0x68a },
- { 0x0000a015, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a016, 0x00604411, 0x68a },
- { 0x0000a016, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a017, 0x00604411, 0x68a },
- { 0x0000a017, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
- { 0x0000002c, 0x0080062d, 0x000 },
- { 0xff000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000002, 0x00804811, 0x000 },
- { 0x00000000, 0x0ee00000, 0x63a },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00000002, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x638 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x68a },
- { 0x00001000, 0x00200811, 0x000 },
- { 0x0000002b, 0x00203622, 0x000 },
- { 0x00000000, 0x00600000, 0x63e },
- { 0x00000000, 0x00600000, 0x5c6 },
- { 0x98000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00804811, 0x000 },
- { 0x00000000, 0xc0600000, 0x63e },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000022, 0x00204811, 0x000 },
- { 0x89000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00404811, 0x62a },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00404811, 0x62a },
- { 0x00000000, 0x00600000, 0x659 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0xc0204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36e },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00010000, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x09800000, 0x00204811, 0x000 },
- { 0xffffffff, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x68a },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000004, 0x00404c11, 0x653 },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000004, 0x00291e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0xfffffffb, 0x00281e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000008, 0x00291e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0xfffffff7, 0x00281e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36e },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00010000, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x01800000, 0x00204811, 0x000 },
- { 0xffffffff, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004217f, 0x00604411, 0x68a },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x689 },
- { 0x00000010, 0x00404c11, 0x66f },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x38c00000, 0x000 },
- { 0x0000001d, 0x00200a2d, 0x000 },
- { 0x0000001e, 0x00200e2d, 0x000 },
- { 0x0000001f, 0x0020122d, 0x000 },
- { 0x00000020, 0x0020162d, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000004, 0x00301224, 0x000 },
- { 0x00000000, 0x002f0064, 0x000 },
- { 0x00000000, 0x0cc00000, 0x688 },
- { 0x00000003, 0x00281a22, 0x000 },
- { 0x00000008, 0x00221222, 0x000 },
- { 0xfffff000, 0x00281224, 0x000 },
- { 0x00000000, 0x002910c4, 0x000 },
- { 0x0000001f, 0x00403624, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x1ac00000, 0x68a },
- { 0x9f000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000000, 0x1ae00000, 0x68d },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x1ac00000, 0x68f },
- { 0x9e000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000000, 0x1ae00000, 0x692 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00001000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001b, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0xc0204411, 0x000 },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000024, 0x0020222d, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000022, 0x0020222d, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00404811, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x014204ff, 0x05bd0250, 0x000 },
- { 0x01c30168, 0x043f05bd, 0x000 },
- { 0x02250209, 0x02500151, 0x000 },
- { 0x02230245, 0x02a00241, 0x000 },
- { 0x03d705bd, 0x05bd05bd, 0x000 },
- { 0x06460647, 0x031f05bd, 0x000 },
- { 0x05bd05c2, 0x03200340, 0x000 },
- { 0x032a0282, 0x03420334, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x05bd054e, 0x05bd05bd, 0x000 },
- { 0x03ba05bd, 0x04b80344, 0x000 },
- { 0x0497044d, 0x043d05bd, 0x000 },
- { 0x04cd05bd, 0x044104da, 0x000 },
- { 0x044d0504, 0x03510375, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x05bd05bd, 0x063c05c4, 0x000 },
- { 0x05bd05bd, 0x000705bd, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x03f803ed, 0x04080406, 0x000 },
- { 0x040e040a, 0x040c0410, 0x000 },
- { 0x041c0418, 0x04240420, 0x000 },
- { 0x042c0428, 0x04340430, 0x000 },
- { 0x05bd05bd, 0x043805bd, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x05bd05bd, 0x05bd05bd, 0x000 },
- { 0x00020676, 0x06940006, 0x000 },
-};
-
-static const u32 RV635_pfp_microcode[] = {
-0xca0400,
-0xa00000,
-0x7e828b,
-0x7c038b,
-0x8001b8,
-0x7c038b,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581a8,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0fff0,
-0x042c04,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255403,
-0x7cd580,
-0x259c03,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d3,
-0xd5c01e,
-0xca0800,
-0x80001a,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800053,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xd48060,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001b8,
-0xd4c01e,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800000,
-0x062001,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x800079,
-0xd42013,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x80008d,
-0x000000,
-0xc41432,
-0xc61843,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800000,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xe4015e,
-0xd4001e,
-0x800000,
-0x062001,
-0xca1800,
-0x0a2001,
-0xd60076,
-0xc40836,
-0x988007,
-0xc61045,
-0x950110,
-0xd4001f,
-0xd46062,
-0x800000,
-0xd42062,
-0xcc3835,
-0xcc1433,
-0x8401bb,
-0xd40072,
-0xd5401e,
-0x800000,
-0xee001e,
-0xe2001a,
-0x8401bb,
-0xe2001a,
-0xcc104b,
-0xcc0447,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001b8,
-0xd4006d,
-0x344401,
-0xcc0c48,
-0x98403a,
-0xcc2c4a,
-0x958004,
-0xcc0449,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x8400f0,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x8400f0,
-0xcc1003,
-0x988017,
-0x043808,
-0x8400f0,
-0xcc1003,
-0x988013,
-0x043804,
-0x8400f0,
-0xcc1003,
-0x988014,
-0xcc104c,
-0x9a8009,
-0xcc144d,
-0x9840dc,
-0xd4006d,
-0xcc1848,
-0xd5001a,
-0xd5401a,
-0x8000c9,
-0xd5801a,
-0x96c0d5,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800000,
-0xec007f,
-0x9ac0cc,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809e,
-0xd4006d,
-0x98409c,
-0xd4006e,
-0xcc084c,
-0xcc0c4d,
-0xcc1048,
-0xd4801a,
-0xd4c01a,
-0x800101,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482d9,
-0xca0c00,
-0xd4401e,
-0x800000,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800000,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x9882bd,
-0x000000,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x9902b0,
-0x7c738b,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984297,
-0x000000,
-0x800161,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc104e,
-0x990004,
-0xd40073,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x950021,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x042802,
-0x7d8380,
-0xd5a86f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0xc82402,
-0x8001b8,
-0xd60076,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800000,
-0xee001e,
-0x800000,
-0xee001f,
-0xd4001f,
-0x800000,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010171,
-0x020178,
-0x03008f,
-0x04007f,
-0x050003,
-0x06003f,
-0x070032,
-0x08012c,
-0x090046,
-0x0a0036,
-0x1001b6,
-0x1700a2,
-0x22013a,
-0x230149,
-0x2000b4,
-0x240125,
-0x27004d,
-0x28006a,
-0x2a0060,
-0x2b0052,
-0x2f0065,
-0x320087,
-0x34017f,
-0x3c0156,
-0x3f0072,
-0x41018c,
-0x44012e,
-0x550173,
-0x56017a,
-0x60000b,
-0x610034,
-0x620038,
-0x630038,
-0x640038,
-0x650038,
-0x660038,
-0x670038,
-0x68003a,
-0x690041,
-0x6a0048,
-0x6b0048,
-0x6c0048,
-0x6d0048,
-0x6e0048,
-0x6f0048,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-};
-
-static const u32 RV670_cp_microcode[][3] = {
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0000ffff, 0x00284621, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00000000, 0x00e00000, 0x000 },
- { 0x00010000, 0xc0294620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x67c },
- { 0x00000000, 0x00600000, 0x624 },
- { 0x00000000, 0x00600000, 0x638 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000f00, 0x00281622, 0x000 },
- { 0x00000008, 0x00211625, 0x000 },
- { 0x00000018, 0x00203625, 0x000 },
- { 0x8d000000, 0x00204411, 0x000 },
- { 0x00000004, 0x002f0225, 0x000 },
- { 0x00000000, 0x0ce00000, 0x018 },
- { 0x00412000, 0x00404811, 0x019 },
- { 0x00422000, 0x00204811, 0x000 },
- { 0x8e000000, 0x00204411, 0x000 },
- { 0x00000028, 0x00204a2d, 0x000 },
- { 0x90000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x0000000c, 0x00211622, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x00000019, 0x00211a22, 0x000 },
- { 0x00000004, 0x00281a26, 0x000 },
- { 0x00000000, 0x002914c5, 0x000 },
- { 0x00000019, 0x00203625, 0x000 },
- { 0x00000000, 0x003a1402, 0x000 },
- { 0x00000016, 0x00211625, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0xfffffffc, 0x00280e23, 0x000 },
- { 0x00000000, 0x002914a3, 0x000 },
- { 0x00000017, 0x00203625, 0x000 },
- { 0x00008000, 0x00280e22, 0x000 },
- { 0x00000007, 0x00220e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x20000000, 0x00280e22, 0x000 },
- { 0x00000006, 0x00210e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x00000000, 0x00220222, 0x000 },
- { 0x00000000, 0x14e00000, 0x038 },
- { 0x00000000, 0x2ee00000, 0x035 },
- { 0x00000000, 0x2ce00000, 0x037 },
- { 0x00000000, 0x00400e2d, 0x039 },
- { 0x00000008, 0x00200e2d, 0x000 },
- { 0x00000009, 0x0040122d, 0x046 },
- { 0x00000001, 0x00400e2d, 0x039 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x03e },
- { 0x00000008, 0x00401c11, 0x041 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x0000000f, 0x00281e27, 0x000 },
- { 0x00000003, 0x00221e27, 0x000 },
- { 0x7fc00000, 0x00281a23, 0x000 },
- { 0x00000014, 0x00211a26, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000008, 0x00221a26, 0x000 },
- { 0x00000000, 0x00290cc7, 0x000 },
- { 0x00000027, 0x00203624, 0x000 },
- { 0x00007f00, 0x00281221, 0x000 },
- { 0x00001400, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x04b },
- { 0x00000001, 0x00290e23, 0x000 },
- { 0x0000000e, 0x00203623, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfff80000, 0x00294a23, 0x000 },
- { 0x00000000, 0x003a2c02, 0x000 },
- { 0x00000002, 0x00220e2b, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x0000000f, 0x00203623, 0x000 },
- { 0x00001fff, 0x00294a23, 0x000 },
- { 0x00000027, 0x00204a2d, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000029, 0x00200e2d, 0x000 },
- { 0x060a0200, 0x00294a23, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00210222, 0x000 },
- { 0x00000000, 0x14e00000, 0x061 },
- { 0x00000000, 0x2ee00000, 0x05f },
- { 0x00000000, 0x2ce00000, 0x05e },
- { 0x00000000, 0x00400e2d, 0x062 },
- { 0x00000001, 0x00400e2d, 0x062 },
- { 0x0000000a, 0x00200e2d, 0x000 },
- { 0x0000000b, 0x0040122d, 0x06a },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x7fc00000, 0x00281623, 0x000 },
- { 0x00000014, 0x00211625, 0x000 },
- { 0x00000001, 0x00331625, 0x000 },
- { 0x80000000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00290ca3, 0x000 },
- { 0x3ffffc00, 0x00290e23, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x06d },
- { 0x00000100, 0x00401c11, 0x070 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x000000f0, 0x00281e27, 0x000 },
- { 0x00000004, 0x00221e27, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0xfffff0ff, 0x00281a30, 0x000 },
- { 0x0000a028, 0x00204411, 0x000 },
- { 0x00000000, 0x002948e6, 0x000 },
- { 0x0000a018, 0x00204411, 0x000 },
- { 0x3fffffff, 0x00284a23, 0x000 },
- { 0x0000a010, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000030, 0x0020162d, 0x000 },
- { 0x00000002, 0x00291625, 0x000 },
- { 0x00000030, 0x00203625, 0x000 },
- { 0x00000025, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a3, 0x000 },
- { 0x00000000, 0x0cc00000, 0x083 },
- { 0x00000026, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a4, 0x000 },
- { 0x00000000, 0x0cc00000, 0x084 },
- { 0x00000000, 0x00400000, 0x08a },
- { 0x00000025, 0x00203623, 0x000 },
- { 0x00000026, 0x00203624, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x08a },
- { 0x00000000, 0x00600000, 0x659 },
- { 0x00000000, 0x00600000, 0x64d },
- { 0x00000002, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x08d },
- { 0x00000012, 0xc0403620, 0x093 },
- { 0x00000000, 0x2ee00000, 0x091 },
- { 0x00000000, 0x2ce00000, 0x090 },
- { 0x00000002, 0x00400e2d, 0x092 },
- { 0x00000003, 0x00400e2d, 0x092 },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000012, 0x00203623, 0x000 },
- { 0x00000003, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x098 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x0a0 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x2ee00000, 0x09e },
- { 0x00000000, 0x2ce00000, 0x09d },
- { 0x00000002, 0x00400e2d, 0x09f },
- { 0x00000003, 0x00400e2d, 0x09f },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x003f0000, 0x00280e23, 0x000 },
- { 0x00000010, 0x00210e23, 0x000 },
- { 0x00000011, 0x00203623, 0x000 },
- { 0x0000001e, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0a7 },
- { 0x00000016, 0xc0203620, 0x000 },
- { 0x0000001f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0aa },
- { 0x00000015, 0xc0203620, 0x000 },
- { 0x00000008, 0x00210e2b, 0x000 },
- { 0x0000007f, 0x00280e23, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0e1 },
- { 0x00000000, 0x27000000, 0x000 },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ae00000, 0x0b3 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x0000000c, 0x00221e30, 0x000 },
- { 0x99800000, 0x00204411, 0x000 },
- { 0x00000004, 0x0020122d, 0x000 },
- { 0x00000008, 0x00221224, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00291ce4, 0x000 },
- { 0x00000000, 0x00604807, 0x12f },
- { 0x9b000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x9c000000, 0x00204411, 0x000 },
- { 0x00000000, 0x0033146f, 0x000 },
- { 0x00000001, 0x00333e23, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0x00203c05, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e007, 0x00204411, 0x000 },
- { 0x0000000f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0cb },
- { 0x00f8ff08, 0x00204811, 0x000 },
- { 0x98000000, 0x00404811, 0x0dc },
- { 0x000000f0, 0x00280e22, 0x000 },
- { 0x000000a0, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x0da },
- { 0x00000011, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0d5 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0d4 },
- { 0x00003f00, 0x00400c11, 0x0d6 },
- { 0x00001f00, 0x00400c11, 0x0d6 },
- { 0x00000f00, 0x00200c11, 0x000 },
- { 0x00380009, 0x00294a23, 0x000 },
- { 0x3f000000, 0x00280e2b, 0x000 },
- { 0x00000002, 0x00220e23, 0x000 },
- { 0x00000007, 0x00494a23, 0x0dc },
- { 0x00380f09, 0x00204811, 0x000 },
- { 0x68000007, 0x00204811, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000a202, 0x00204411, 0x000 },
- { 0x00ff0000, 0x00280e22, 0x000 },
- { 0x00000080, 0x00294a23, 0x000 },
- { 0x00000027, 0x00200e2d, 0x000 },
- { 0x00000026, 0x0020122d, 0x000 },
- { 0x00000000, 0x002f0083, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0ea },
- { 0x00000000, 0x00600000, 0x653 },
- { 0x00000000, 0x00400000, 0x0eb },
- { 0x00000000, 0x00600000, 0x656 },
- { 0x00000007, 0x0020222d, 0x000 },
- { 0x00000005, 0x00220e22, 0x000 },
- { 0x00100000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x000000ef, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0x00000003, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x0f8 },
- { 0x0000000b, 0x00210228, 0x000 },
- { 0x00000000, 0x14c00000, 0x0f8 },
- { 0x00000400, 0x00292228, 0x000 },
- { 0x00000014, 0x00203628, 0x000 },
- { 0x0000001c, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x0fd },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000001e, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x10b },
- { 0x0000a30f, 0x00204411, 0x000 },
- { 0x00000011, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x104 },
- { 0xffffffff, 0x00404811, 0x10b },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x107 },
- { 0x0000ffff, 0x00404811, 0x10b },
- { 0x00000004, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x10a },
- { 0x000000ff, 0x00404811, 0x10b },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0002c400, 0x00204411, 0x000 },
- { 0x0000001f, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x112 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x00000013, 0x00203623, 0x000 },
- { 0x00000018, 0x40224a20, 0x000 },
- { 0x00000010, 0xc0424a20, 0x114 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x00000013, 0x00203623, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000000a, 0x00201011, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x11b },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00531224, 0x117 },
- { 0xffbfffff, 0x00283a2e, 0x000 },
- { 0x0000001b, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x12e },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0x00000018, 0x00220e30, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e00e, 0x00204411, 0x000 },
- { 0x07f8ff08, 0x00204811, 0x000 },
- { 0x00000000, 0x00294a23, 0x000 },
- { 0x0000001c, 0x00201e2d, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x00800000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204806, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x67c },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x67b },
- { 0x00000004, 0x00404c11, 0x135 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x0000001c, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x67c },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x13c },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00000000, 0x00600000, 0x160 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40280620, 0x000 },
- { 0x00000010, 0xc0210a20, 0x000 },
- { 0x00000000, 0x00341461, 0x000 },
- { 0x00000000, 0x00741882, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x147 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x160 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0681a20, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x158 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000001, 0x00300a2f, 0x000 },
- { 0x00000001, 0x00210a22, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600000, 0x18f },
- { 0x00000000, 0x00600000, 0x1a0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00202c08, 0x000 },
- { 0x00000000, 0x00202411, 0x000 },
- { 0x00000000, 0x00202811, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000002, 0x00221e29, 0x000 },
- { 0x00000000, 0x007048eb, 0x19c },
- { 0x00000000, 0x00600000, 0x2bb },
- { 0x00000001, 0x40330620, 0x000 },
- { 0x00000000, 0xc0302409, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ae00000, 0x181 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x00000000, 0x00400000, 0x186 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x186 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000001, 0x00530621, 0x182 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0604800, 0x197 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000011, 0x0020062d, 0x000 },
- { 0x00000000, 0x0078042a, 0x2fb },
- { 0x00000000, 0x00202809, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x174 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000210, 0x00600411, 0x315 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x194 },
- { 0x00000015, 0xc0203620, 0x000 },
- { 0x00000016, 0xc0203620, 0x000 },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x46000000, 0x00600811, 0x1b2 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x19b },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000021, 0x00804811, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40281620, 0x000 },
- { 0x00000010, 0xc0811a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000008, 0x00221e30, 0x000 },
- { 0x00000029, 0x00201a2d, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfffbff09, 0x00204811, 0x000 },
- { 0x0000000f, 0x0020222d, 0x000 },
- { 0x00001fff, 0x00294a28, 0x000 },
- { 0x00000006, 0x0020222d, 0x000 },
- { 0x00000000, 0x002920e8, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a26, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000100, 0x00201811, 0x000 },
- { 0x00000008, 0x00621e28, 0x12f },
- { 0x00000008, 0x00822228, 0x000 },
- { 0x0002c000, 0x00204411, 0x000 },
- { 0x00000015, 0x00600e2d, 0x1bd },
- { 0x00000016, 0x00600e2d, 0x1bd },
- { 0x0000c008, 0x00204411, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0x00000000, 0x14c00000, 0x1b9 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x39000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00804802, 0x000 },
- { 0x00000018, 0x00202e2d, 0x000 },
- { 0x00000000, 0x003b0d63, 0x000 },
- { 0x00000008, 0x00224a23, 0x000 },
- { 0x00000010, 0x00224a23, 0x000 },
- { 0x00000018, 0x00224a23, 0x000 },
- { 0x00000000, 0x00804803, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00001000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00000007, 0x0021062f, 0x000 },
- { 0x00000013, 0x00200a2d, 0x000 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000ffff, 0x40282220, 0x000 },
- { 0x0000000f, 0x00262228, 0x000 },
- { 0x00000010, 0x40212620, 0x000 },
- { 0x0000000f, 0x00262629, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001b, 0x00204811, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1e0 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000081, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000080, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1dc },
- { 0x00000000, 0x00600000, 0x1e9 },
- { 0x00000001, 0x00531e27, 0x1d8 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000001f, 0x00280a22, 0x000 },
- { 0x0000001f, 0x00282a2a, 0x000 },
- { 0x00000001, 0x00530621, 0x1d1 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000002, 0x00304a2f, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000001, 0x00301e2f, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x1e9 },
- { 0x00000001, 0x00531e27, 0x1e5 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x0000000f, 0x00260e23, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000000f, 0x00261224, 0x000 },
- { 0x00000000, 0x00201411, 0x000 },
- { 0x00000000, 0x00601811, 0x2bb },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022b, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1f8 },
- { 0x00000010, 0x00221628, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a29, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x0020480a, 0x000 },
- { 0x00000000, 0x00202c11, 0x000 },
- { 0x00000010, 0x00221623, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a24, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x00731503, 0x205 },
- { 0x00000000, 0x00201805, 0x000 },
- { 0x00000000, 0x00731524, 0x205 },
- { 0x00000000, 0x002d14c5, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00000000, 0x00202003, 0x000 },
- { 0x00000000, 0x00802404, 0x000 },
- { 0x0000000f, 0x00210225, 0x000 },
- { 0x00000000, 0x14c00000, 0x67b },
- { 0x00000000, 0x002b1405, 0x000 },
- { 0x00000001, 0x00901625, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00294a22, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a21, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000ffff, 0x40281220, 0x000 },
- { 0x00000010, 0xc0211a20, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211620, 0x000 },
- { 0x00000000, 0x00741465, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00000001, 0x00330621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0cc00000, 0x219 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x212 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x638 },
- { 0x00000000, 0x0040040f, 0x213 },
- { 0x00000000, 0x00600000, 0x624 },
- { 0x00000000, 0x00600000, 0x638 },
- { 0x00000210, 0x00600411, 0x315 },
- { 0x00000000, 0x00600000, 0x1a0 },
- { 0x00000000, 0x00600000, 0x19c },
- { 0x00000000, 0x00600000, 0x2bb },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ae00000, 0x232 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x00000000, 0x00400000, 0x236 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x236 },
- { 0x00000000, 0xc0404800, 0x233 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x00600411, 0x2fb },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x624 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000018, 0x40210a20, 0x000 },
- { 0x00000003, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x24c },
- { 0x00000014, 0x0020222d, 0x000 },
- { 0x00080101, 0x00292228, 0x000 },
- { 0x00000014, 0x00203628, 0x000 },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x251 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000010, 0x00600411, 0x315 },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x00000000, 0x00600000, 0x27c },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000001, 0x00211e27, 0x000 },
- { 0x00000000, 0x14e00000, 0x26a },
- { 0x00000012, 0x00201e2d, 0x000 },
- { 0x0000ffff, 0x00281e27, 0x000 },
- { 0x00000000, 0x00341c27, 0x000 },
- { 0x00000000, 0x12c00000, 0x25f },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e5, 0x000 },
- { 0x00000000, 0x08c00000, 0x262 },
- { 0x00000000, 0x00201407, 0x000 },
- { 0x00000012, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00211e27, 0x000 },
- { 0x00000000, 0x00341c47, 0x000 },
- { 0x00000000, 0x12c00000, 0x267 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x08c00000, 0x26a },
- { 0x00000000, 0x00201807, 0x000 },
- { 0x00000000, 0x00600000, 0x2c1 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000000, 0x00342023, 0x000 },
- { 0x00000000, 0x12c00000, 0x272 },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x271 },
- { 0x00000016, 0x00404811, 0x276 },
- { 0x00000018, 0x00404811, 0x276 },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x275 },
- { 0x00000017, 0x00404811, 0x276 },
- { 0x00000019, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00604411, 0x2e9 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x256 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000010, 0x40210620, 0x000 },
- { 0x0000ffff, 0xc0280a20, 0x000 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0881a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x67c },
- { 0x00000000, 0x00600000, 0x624 },
- { 0x00000000, 0xc0600000, 0x2a3 },
- { 0x00000005, 0x00200a2d, 0x000 },
- { 0x00000008, 0x00220a22, 0x000 },
- { 0x0000002b, 0x00201a2d, 0x000 },
- { 0x0000001c, 0x00201e2d, 0x000 },
- { 0x00007000, 0x00281e27, 0x000 },
- { 0x00000000, 0x00311ce6, 0x000 },
- { 0x0000002a, 0x00201a2d, 0x000 },
- { 0x0000000c, 0x00221a26, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x06e00000, 0x292 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x0000002b, 0x00203623, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00691ce2, 0x12f },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x29d },
- { 0x00000001, 0x00333e2f, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000001c, 0x00403627, 0x000 },
- { 0x0000000c, 0xc0220a20, 0x000 },
- { 0x00000029, 0x00203622, 0x000 },
- { 0x00000028, 0xc0403620, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000009, 0x00204811, 0x000 },
- { 0xa1000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce3, 0x000 },
- { 0x00000021, 0x00203627, 0x000 },
- { 0x00000022, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce4, 0x000 },
- { 0x00000022, 0x00203627, 0x000 },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a3, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x00000023, 0x00203627, 0x000 },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x00000024, 0x00803627, 0x000 },
- { 0x00000021, 0x00203623, 0x000 },
- { 0x00000022, 0x00203624, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000023, 0x00203627, 0x000 },
- { 0x00000000, 0x00311cc4, 0x000 },
- { 0x00000024, 0x00803627, 0x000 },
- { 0x0000001a, 0x00203627, 0x000 },
- { 0x0000001b, 0x00203628, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14c00000, 0x2dc },
- { 0x00000000, 0x00400000, 0x2d9 },
- { 0x0000001a, 0x00203627, 0x000 },
- { 0x0000001b, 0x00203628, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2d9 },
- { 0x00000003, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2dc },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e1, 0x000 },
- { 0x00000000, 0x02c00000, 0x2dc },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a1, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2dc },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e2, 0x000 },
- { 0x00000000, 0x02c00000, 0x2dc },
- { 0x00000022, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2dc },
- { 0x00000000, 0x00600000, 0x659 },
- { 0x00000000, 0x00600000, 0x2b5 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x00000000, 0x00600000, 0x2b5 },
- { 0x00000000, 0x00600000, 0x650 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x00000000, 0x00600000, 0x2a7 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x0000001a, 0x00201e2d, 0x000 },
- { 0x0000001b, 0x0080222d, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca1, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x003808c5, 0x000 },
- { 0x00000000, 0x00300841, 0x000 },
- { 0x00000001, 0x00220a22, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000017, 0x0020222d, 0x000 },
- { 0x00000000, 0x14c00000, 0x318 },
- { 0xffffffef, 0x00280621, 0x000 },
- { 0x00000014, 0x0020222d, 0x000 },
- { 0x0000f8e0, 0x00204411, 0x000 },
- { 0x00000000, 0x00294901, 0x000 },
- { 0x00000000, 0x00894901, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00804811, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x97000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00002257, 0x00204411, 0x000 },
- { 0x00000003, 0xc0484a20, 0x000 },
- { 0x0000225d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x638 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x00000001, 0x40304a20, 0x000 },
- { 0x00000002, 0xc0304a20, 0x000 },
- { 0x00000001, 0x00530a22, 0x34b },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000018, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x67c },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x354 },
- { 0x00000014, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x362 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00604802, 0x36a },
- { 0x00002100, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000004, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x366 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x35d },
- { 0x00000028, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5b3 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x35d },
- { 0x0000002c, 0x00203626, 0x000 },
- { 0x00000049, 0x00201811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000000, 0x002f0226, 0x000 },
- { 0x00000000, 0x0cc00000, 0x36c },
- { 0x0000002c, 0x00801a2d, 0x000 },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x00000015, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x382 },
- { 0x00000006, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3ad },
- { 0x00000016, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3af },
- { 0x00000020, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x398 },
- { 0x0000000f, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3a4 },
- { 0x00000010, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3a4 },
- { 0x0000001e, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x38c },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x08000000, 0x00290a22, 0x000 },
- { 0x00000003, 0x40210e20, 0x000 },
- { 0x0000000c, 0xc0211220, 0x000 },
- { 0x00080000, 0x00281224, 0x000 },
- { 0x00000014, 0xc0221620, 0x000 },
- { 0x00000000, 0x002914a4, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x002948a2, 0x000 },
- { 0x0000a1fe, 0x00204411, 0x000 },
- { 0x00000000, 0x00404803, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x67c },
- { 0x00000015, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x38e },
- { 0x0000210e, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000017, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x67c },
- { 0x00000003, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x39a },
- { 0x00002108, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x80000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000010, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x3aa },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000006, 0x00404811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36a },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x0000001d, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x3c4 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000018, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x67c },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x3b8 },
- { 0x00002100, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0xbabecafe, 0x00204811, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000004, 0x00404811, 0x000 },
- { 0x00002170, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000a, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x3c9 },
- { 0x8c000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00003fff, 0x40280a20, 0x000 },
- { 0x80000000, 0x40280e20, 0x000 },
- { 0x40000000, 0xc0281220, 0x000 },
- { 0x00040000, 0x00694622, 0x67c },
- { 0x00000000, 0x00201410, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3d7 },
- { 0x00000000, 0xc0401800, 0x3da },
- { 0x00003fff, 0xc0281a20, 0x000 },
- { 0x00040000, 0x00694626, 0x67c },
- { 0x00000000, 0x00201810, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3dd },
- { 0x00000000, 0xc0401c00, 0x3e0 },
- { 0x00003fff, 0xc0281e20, 0x000 },
- { 0x00040000, 0x00694627, 0x67c },
- { 0x00000000, 0x00201c10, 0x000 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0x002820c5, 0x000 },
- { 0x00000000, 0x004948e8, 0x000 },
- { 0xa5800000, 0x00200811, 0x000 },
- { 0x00002000, 0x00200c11, 0x000 },
- { 0x83000000, 0x00604411, 0x408 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x0000001f, 0xc0210220, 0x000 },
- { 0x00000000, 0x14c00000, 0x3ed },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0000ffff, 0xc0481220, 0x3f5 },
- { 0xa7800000, 0x00200811, 0x000 },
- { 0x0000a000, 0x00200c11, 0x000 },
- { 0x83000000, 0x00604411, 0x408 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x83000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00304883, 0x000 },
- { 0x84000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x1d000000, 0x000 },
- { 0x83000000, 0x00604411, 0x408 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0xa9800000, 0x00200811, 0x000 },
- { 0x0000c000, 0x00400c11, 0x3f0 },
- { 0xab800000, 0x00200811, 0x000 },
- { 0x0000f8e0, 0x00400c11, 0x3f0 },
- { 0xad800000, 0x00200811, 0x000 },
- { 0x0000f880, 0x00400c11, 0x3f0 },
- { 0xb3800000, 0x00200811, 0x000 },
- { 0x0000f3fc, 0x00400c11, 0x3f0 },
- { 0xaf800000, 0x00200811, 0x000 },
- { 0x0000e000, 0x00400c11, 0x3f0 },
- { 0xb1800000, 0x00200811, 0x000 },
- { 0x0000f000, 0x00400c11, 0x3f0 },
- { 0x83000000, 0x00204411, 0x000 },
- { 0x00002148, 0x00204811, 0x000 },
- { 0x84000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x1d000000, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x01182000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0218a000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0318c000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0418f8e0, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0518f880, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0618e000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0718f000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0818f3fc, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00000030, 0x00200a2d, 0x000 },
- { 0x00000000, 0xc0290c40, 0x000 },
- { 0x00000030, 0x00203623, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x86000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00404801, 0x000 },
- { 0x85000000, 0xc0204411, 0x000 },
- { 0x00000000, 0x00404801, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x67c },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000000, 0x00404c02, 0x43e },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x00000000, 0xc0201000, 0x000 },
- { 0x00000000, 0xc0201400, 0x000 },
- { 0x00000000, 0xc0201800, 0x000 },
- { 0x00000000, 0xc0201c00, 0x000 },
- { 0x00007f00, 0x00280a21, 0x000 },
- { 0x00004500, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x44c },
- { 0x00000000, 0xc0202000, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x00000010, 0x00280a23, 0x000 },
- { 0x00000010, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x454 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00040000, 0x00694624, 0x67c },
- { 0x00000000, 0x00400000, 0x459 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000216d, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000000, 0x00604805, 0x681 },
- { 0x00000000, 0x002824f0, 0x000 },
- { 0x00000007, 0x00280a23, 0x000 },
- { 0x00000001, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x460 },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x04e00000, 0x479 },
- { 0x00000000, 0x00400000, 0x486 },
- { 0x00000002, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x465 },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x02e00000, 0x479 },
- { 0x00000000, 0x00400000, 0x486 },
- { 0x00000003, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x46a },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x0ce00000, 0x479 },
- { 0x00000000, 0x00400000, 0x486 },
- { 0x00000004, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x46f },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x0ae00000, 0x479 },
- { 0x00000000, 0x00400000, 0x486 },
- { 0x00000005, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x474 },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x06e00000, 0x479 },
- { 0x00000000, 0x00400000, 0x486 },
- { 0x00000006, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x479 },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x08e00000, 0x479 },
- { 0x00000000, 0x00400000, 0x486 },
- { 0x00007f00, 0x00280a21, 0x000 },
- { 0x00004500, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x000 },
- { 0x00000008, 0x00210a23, 0x000 },
- { 0x00000000, 0x14c00000, 0x483 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x00000000, 0xc0204400, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00007f00, 0x00280a21, 0x000 },
- { 0x00004500, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x48c },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0400000, 0x000 },
- { 0x00000000, 0x00404c08, 0x44c },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x00000011, 0x40211220, 0x000 },
- { 0x00000012, 0x40211620, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00210225, 0x000 },
- { 0x00000000, 0x14e00000, 0x496 },
- { 0x00040000, 0xc0494a20, 0x497 },
- { 0xfffbffff, 0xc0284a20, 0x000 },
- { 0x00000000, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x4a3 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x00210224, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000c, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x49f },
- { 0xa0000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000004, 0x00204811, 0x000 },
- { 0x0000216b, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204810, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000005, 0x00204811, 0x000 },
- { 0x0000216c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204810, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00400000, 0x49d },
- { 0x00000000, 0xc0210a20, 0x000 },
- { 0x00000000, 0x14c00000, 0x4b6 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000216d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0604800, 0x681 },
- { 0x00000000, 0x00400000, 0x4ba },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00040000, 0xc0294620, 0x000 },
- { 0x00000000, 0xc0600000, 0x67c },
- { 0x00000001, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x4c1 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x00000000, 0xc0204400, 0x000 },
- { 0x00000000, 0xc0404810, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x67c },
- { 0x00000000, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x4c3 },
- { 0x00002180, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000003, 0x00333e2f, 0x000 },
- { 0x00000001, 0x00210221, 0x000 },
- { 0x00000000, 0x14e00000, 0x4f3 },
- { 0x0000002c, 0x00200a2d, 0x000 },
- { 0x00040000, 0x18e00c11, 0x4e2 },
- { 0x00000001, 0x00333e2f, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000008, 0x00300a22, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000008, 0x00300a22, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xd8c04800, 0x4d6 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000008, 0x00300a22, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000002d, 0x0020122d, 0x000 },
- { 0x00000000, 0x00290c83, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000008, 0x00300a22, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000011, 0x00210224, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000000, 0x00400000, 0x49d },
- { 0x0000002c, 0xc0203620, 0x000 },
- { 0x0000002d, 0xc0403620, 0x000 },
- { 0x0000000f, 0x00210221, 0x000 },
- { 0x00000000, 0x14c00000, 0x4f8 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0xd9000000, 0x000 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0xb5000000, 0x00204411, 0x000 },
- { 0x00002000, 0x00204811, 0x000 },
- { 0xb6000000, 0x00204411, 0x000 },
- { 0x0000a000, 0x00204811, 0x000 },
- { 0xb7000000, 0x00204411, 0x000 },
- { 0x0000c000, 0x00204811, 0x000 },
- { 0xb8000000, 0x00204411, 0x000 },
- { 0x0000f8e0, 0x00204811, 0x000 },
- { 0xb9000000, 0x00204411, 0x000 },
- { 0x0000f880, 0x00204811, 0x000 },
- { 0xba000000, 0x00204411, 0x000 },
- { 0x0000e000, 0x00204811, 0x000 },
- { 0xbb000000, 0x00204411, 0x000 },
- { 0x0000f000, 0x00204811, 0x000 },
- { 0xbc000000, 0x00204411, 0x000 },
- { 0x0000f3fc, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000002, 0x00204811, 0x000 },
- { 0x000000ff, 0x00280e30, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x50c },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0x14c00000, 0x521 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x0000001c, 0x00203623, 0x000 },
- { 0x0000002b, 0x00203623, 0x000 },
- { 0x00000029, 0x00203623, 0x000 },
- { 0x00000028, 0x00203623, 0x000 },
- { 0x00000017, 0x00203623, 0x000 },
- { 0x00000025, 0x00203623, 0x000 },
- { 0x00000026, 0x00203623, 0x000 },
- { 0x00000015, 0x00203623, 0x000 },
- { 0x00000016, 0x00203623, 0x000 },
- { 0xffffe000, 0x00200c11, 0x000 },
- { 0x00000021, 0x00203623, 0x000 },
- { 0x00000022, 0x00203623, 0x000 },
- { 0x00001fff, 0x00200c11, 0x000 },
- { 0x00000023, 0x00203623, 0x000 },
- { 0x00000024, 0x00203623, 0x000 },
- { 0xf1ffffff, 0x00283a2e, 0x000 },
- { 0x0000001a, 0xc0220e20, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x0000002a, 0x40203620, 0x000 },
- { 0x87000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1f4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x00000030, 0x00203623, 0x000 },
- { 0x9d000000, 0x00204411, 0x000 },
- { 0x0000001f, 0x40214a20, 0x000 },
- { 0x96000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x00000000, 0xc0201000, 0x000 },
- { 0x0000001f, 0x00211624, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x0000001d, 0x00203623, 0x000 },
- { 0x00000003, 0x00281e23, 0x000 },
- { 0x00000008, 0x00222223, 0x000 },
- { 0xfffff000, 0x00282228, 0x000 },
- { 0x00000000, 0x002920e8, 0x000 },
- { 0x0000001f, 0x00203628, 0x000 },
- { 0x00000018, 0x00211e23, 0x000 },
- { 0x00000020, 0x00203627, 0x000 },
- { 0x00000002, 0x00221624, 0x000 },
- { 0x00000000, 0x003014a8, 0x000 },
- { 0x0000001e, 0x00203625, 0x000 },
- { 0x00000003, 0x00211a24, 0x000 },
- { 0x10000000, 0x00281a26, 0x000 },
- { 0xefffffff, 0x00283a2e, 0x000 },
- { 0x00000000, 0x004938ce, 0x66a },
- { 0x00000001, 0x40280a20, 0x000 },
- { 0x00000006, 0x40280e20, 0x000 },
- { 0x00000300, 0xc0281220, 0x000 },
- { 0x00000008, 0x00211224, 0x000 },
- { 0x00000000, 0xc0201620, 0x000 },
- { 0x00000000, 0xc0201a20, 0x000 },
- { 0x00000000, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x559 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00002258, 0x00300a24, 0x000 },
- { 0x00040000, 0x00694622, 0x67c },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x00020000, 0x00294a26, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x561 },
- { 0x00000000, 0xc0201c10, 0x000 },
- { 0x00000000, 0xc0400000, 0x56f },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x561 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00002258, 0x00300a24, 0x000 },
- { 0x00040000, 0x00694622, 0x67c },
- { 0x00000000, 0xc0201c10, 0x000 },
- { 0x00000000, 0xc0400000, 0x56f },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x565 },
- { 0x00000000, 0xc0201c00, 0x000 },
- { 0x00000000, 0xc0400000, 0x56f },
- { 0x00000004, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x56d },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000216d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0604800, 0x681 },
- { 0x00000000, 0x00401c10, 0x56f },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0400000, 0x000 },
- { 0x00000000, 0x0ee00000, 0x571 },
- { 0x00000000, 0x00600000, 0x5bc },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x582 },
- { 0x0000a2b7, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2b6, 0x00604411, 0x67c },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x67c },
- { 0x0000a2c4, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x580 },
- { 0x0000a2d1, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d1, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x00000001, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x593 },
- { 0x0000a2bb, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2ba, 0x00604411, 0x67c },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x67c },
- { 0x0000a2c5, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x591 },
- { 0x0000a2d2, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d2, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x00000002, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5a4 },
- { 0x0000a2bf, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2be, 0x00604411, 0x67c },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x67c },
- { 0x0000a2c6, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x5a2 },
- { 0x0000a2d3, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d3, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x0000a2c3, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a2c2, 0x00604411, 0x67c },
- { 0x0000001a, 0x00212230, 0x000 },
- { 0x00000006, 0x00222630, 0x000 },
- { 0x00042004, 0x00604411, 0x67c },
- { 0x0000a2c7, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x5b1 },
- { 0x0000a2d4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d4, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x85000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x0000304a, 0x00204411, 0x000 },
- { 0x01000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00400000, 0x5b7 },
- { 0xa4000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0xc0600000, 0x5bc },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000002c, 0x00203621, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000000, 0x002f0230, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5c3 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000030, 0x00403621, 0x5d6 },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00007e00, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x5d6 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004a092, 0x00604411, 0x67c },
- { 0x00000031, 0x00203630, 0x000 },
- { 0x0004a093, 0x00604411, 0x67c },
- { 0x00000032, 0x00203630, 0x000 },
- { 0x0004a2b6, 0x00604411, 0x67c },
- { 0x00000033, 0x00203630, 0x000 },
- { 0x0004a2ba, 0x00604411, 0x67c },
- { 0x00000034, 0x00203630, 0x000 },
- { 0x0004a2be, 0x00604411, 0x67c },
- { 0x00000035, 0x00203630, 0x000 },
- { 0x0004a2c2, 0x00604411, 0x67c },
- { 0x00000036, 0x00203630, 0x000 },
- { 0x00042004, 0x00604411, 0x67c },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x00000005, 0x00204811, 0x000 },
- { 0x0000a1f4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x88000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000001, 0x002f0230, 0x000 },
- { 0x00000000, 0x0ce00000, 0x61f },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x61f },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00007e00, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x5f8 },
- { 0x0000a092, 0x00204411, 0x000 },
- { 0x00000031, 0x00204a2d, 0x000 },
- { 0x0000a093, 0x00204411, 0x000 },
- { 0x00000032, 0x00204a2d, 0x000 },
- { 0x0000a2b6, 0x00204411, 0x000 },
- { 0x00000033, 0x00204a2d, 0x000 },
- { 0x0000a2ba, 0x00204411, 0x000 },
- { 0x00000034, 0x00204a2d, 0x000 },
- { 0x0000a2be, 0x00204411, 0x000 },
- { 0x00000035, 0x00204a2d, 0x000 },
- { 0x0000a2c2, 0x00204411, 0x000 },
- { 0x00000036, 0x00204a2d, 0x000 },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x000001ff, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x61e },
- { 0x00000000, 0x00210221, 0x000 },
- { 0x00000000, 0x14c00000, 0x601 },
- { 0x0004a003, 0x00604411, 0x67c },
- { 0x0000a003, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00000001, 0x00210621, 0x000 },
- { 0x00000000, 0x14c00000, 0x606 },
- { 0x0004a010, 0x00604411, 0x67c },
- { 0x0000a010, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00000001, 0x00210621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x61e },
- { 0x0004a011, 0x00604411, 0x67c },
- { 0x0000a011, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a012, 0x00604411, 0x67c },
- { 0x0000a012, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a013, 0x00604411, 0x67c },
- { 0x0000a013, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a014, 0x00604411, 0x67c },
- { 0x0000a014, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a015, 0x00604411, 0x67c },
- { 0x0000a015, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a016, 0x00604411, 0x67c },
- { 0x0000a016, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x0004a017, 0x00604411, 0x67c },
- { 0x0000a017, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x00042004, 0x00604411, 0x67c },
- { 0x0000002c, 0x0080062d, 0x000 },
- { 0xff000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000002, 0x00804811, 0x000 },
- { 0x00000000, 0x0ee00000, 0x630 },
- { 0x00000030, 0x0020062d, 0x000 },
- { 0x00000002, 0x00280621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x62e },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x67c },
- { 0x00001000, 0x00200811, 0x000 },
- { 0x0000002b, 0x00203622, 0x000 },
- { 0x00000000, 0x00600000, 0x634 },
- { 0x00000000, 0x00600000, 0x5bc },
- { 0x98000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00804811, 0x000 },
- { 0x00000000, 0xc0600000, 0x634 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000022, 0x00204811, 0x000 },
- { 0x89000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00404811, 0x620 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00404811, 0x620 },
- { 0x00000000, 0x00600000, 0x64d },
- { 0x0001a2a4, 0xc0204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36a },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00010000, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x09800000, 0x00204811, 0x000 },
- { 0xffffffff, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x67c },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000004, 0x00404c11, 0x647 },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000004, 0x00291e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0xfffffffb, 0x00281e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000008, 0x00291e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0xfffffff7, 0x00281e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000016, 0x00604811, 0x36a },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00010000, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x01800000, 0x00204811, 0x000 },
- { 0xffffffff, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004217f, 0x00604411, 0x67c },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x67b },
- { 0x00000010, 0x00404c11, 0x661 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x38c00000, 0x000 },
- { 0x0000001d, 0x00200a2d, 0x000 },
- { 0x0000001e, 0x00200e2d, 0x000 },
- { 0x0000001f, 0x0020122d, 0x000 },
- { 0x00000020, 0x0020162d, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000004, 0x00301224, 0x000 },
- { 0x00000000, 0x002f0064, 0x000 },
- { 0x00000000, 0x0cc00000, 0x67a },
- { 0x00000003, 0x00281a22, 0x000 },
- { 0x00000008, 0x00221222, 0x000 },
- { 0xfffff000, 0x00281224, 0x000 },
- { 0x00000000, 0x002910c4, 0x000 },
- { 0x0000001f, 0x00403624, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x1ac00000, 0x67c },
- { 0x9f000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000000, 0x1ae00000, 0x67f },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x1ac00000, 0x681 },
- { 0x9e000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000000, 0x1ae00000, 0x684 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00001000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001b, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0xc0204411, 0x000 },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000024, 0x0020222d, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000022, 0x0020222d, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00404811, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x014204f5, 0x05b30250, 0x000 },
- { 0x01c30168, 0x043505b3, 0x000 },
- { 0x02250209, 0x02500151, 0x000 },
- { 0x02230245, 0x02a00241, 0x000 },
- { 0x03cd05b3, 0x05b305b3, 0x000 },
- { 0x063c063d, 0x031f05b3, 0x000 },
- { 0x05b305b8, 0x03200340, 0x000 },
- { 0x032a0282, 0x03420334, 0x000 },
- { 0x05b305b3, 0x05b305b3, 0x000 },
- { 0x05b30544, 0x05b305b3, 0x000 },
- { 0x03b205b3, 0x04ae0344, 0x000 },
- { 0x048d0443, 0x043305b3, 0x000 },
- { 0x04c305b3, 0x043704d0, 0x000 },
- { 0x044304fa, 0x03510371, 0x000 },
- { 0x05b305b3, 0x05b305b3, 0x000 },
- { 0x05b305b3, 0x05b305b3, 0x000 },
- { 0x05b305b3, 0x063205ba, 0x000 },
- { 0x05b305b3, 0x000705b3, 0x000 },
- { 0x05b305b3, 0x05b305b3, 0x000 },
- { 0x05b305b3, 0x05b305b3, 0x000 },
- { 0x03ee03e3, 0x03fe03fc, 0x000 },
- { 0x04040400, 0x04020406, 0x000 },
- { 0x0412040e, 0x041a0416, 0x000 },
- { 0x0422041e, 0x042a0426, 0x000 },
- { 0x05b305b3, 0x042e05b3, 0x000 },
- { 0x05b305b3, 0x05b305b3, 0x000 },
- { 0x05b305b3, 0x05b305b3, 0x000 },
- { 0x00020668, 0x06860006, 0x000 },
-};
-
-static const u32 RV670_pfp_microcode[] = {
-0xca0400,
-0xa00000,
-0x7e828b,
-0x7c038b,
-0x8001b8,
-0x7c038b,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581a8,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0fff0,
-0x042c04,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255403,
-0x7cd580,
-0x259c03,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d3,
-0xd5c01e,
-0xca0800,
-0x80001a,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800053,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xd48060,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001b8,
-0xd4c01e,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800000,
-0x062001,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x800079,
-0xd42013,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x80008d,
-0x000000,
-0xc41432,
-0xc61843,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800000,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xe4015e,
-0xd4001e,
-0x800000,
-0x062001,
-0xca1800,
-0x0a2001,
-0xd60076,
-0xc40836,
-0x988007,
-0xc61045,
-0x950110,
-0xd4001f,
-0xd46062,
-0x800000,
-0xd42062,
-0xcc3835,
-0xcc1433,
-0x8401bb,
-0xd40072,
-0xd5401e,
-0x800000,
-0xee001e,
-0xe2001a,
-0x8401bb,
-0xe2001a,
-0xcc104b,
-0xcc0447,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001b8,
-0xd4006d,
-0x344401,
-0xcc0c48,
-0x98403a,
-0xcc2c4a,
-0x958004,
-0xcc0449,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x8400f0,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x8400f0,
-0xcc1003,
-0x988017,
-0x043808,
-0x8400f0,
-0xcc1003,
-0x988013,
-0x043804,
-0x8400f0,
-0xcc1003,
-0x988014,
-0xcc104c,
-0x9a8009,
-0xcc144d,
-0x9840dc,
-0xd4006d,
-0xcc1848,
-0xd5001a,
-0xd5401a,
-0x8000c9,
-0xd5801a,
-0x96c0d5,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800000,
-0xec007f,
-0x9ac0cc,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809e,
-0xd4006d,
-0x98409c,
-0xd4006e,
-0xcc084c,
-0xcc0c4d,
-0xcc1048,
-0xd4801a,
-0xd4c01a,
-0x800101,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482d9,
-0xca0c00,
-0xd4401e,
-0x800000,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800000,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x9882bd,
-0x000000,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x9902b0,
-0x7c738b,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984297,
-0x000000,
-0x800161,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc104e,
-0x990004,
-0xd40073,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x950021,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x042802,
-0x7d8380,
-0xd5a86f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0xc82402,
-0x8001b8,
-0xd60076,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800000,
-0xee001e,
-0x800000,
-0xee001f,
-0xd4001f,
-0x800000,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010171,
-0x020178,
-0x03008f,
-0x04007f,
-0x050003,
-0x06003f,
-0x070032,
-0x08012c,
-0x090046,
-0x0a0036,
-0x1001b6,
-0x1700a2,
-0x22013a,
-0x230149,
-0x2000b4,
-0x240125,
-0x27004d,
-0x28006a,
-0x2a0060,
-0x2b0052,
-0x2f0065,
-0x320087,
-0x34017f,
-0x3c0156,
-0x3f0072,
-0x41018c,
-0x44012e,
-0x550173,
-0x56017a,
-0x60000b,
-0x610034,
-0x620038,
-0x630038,
-0x640038,
-0x650038,
-0x660038,
-0x670038,
-0x68003a,
-0x690041,
-0x6a0048,
-0x6b0048,
-0x6c0048,
-0x6d0048,
-0x6e0048,
-0x6f0048,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-};
-
-static const u32 RS780_cp_microcode[][3] = {
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0000ffff, 0x00284621, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00000000, 0x00e00000, 0x000 },
- { 0x00010000, 0xc0294620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x622 },
- { 0x00000000, 0x00600000, 0x5d1 },
- { 0x00000000, 0x00600000, 0x5de },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000f00, 0x00281622, 0x000 },
- { 0x00000008, 0x00211625, 0x000 },
- { 0x00000018, 0x00203625, 0x000 },
- { 0x8d000000, 0x00204411, 0x000 },
- { 0x00000004, 0x002f0225, 0x000 },
- { 0x00000000, 0x0ce00000, 0x018 },
- { 0x00412000, 0x00404811, 0x019 },
- { 0x00422000, 0x00204811, 0x000 },
- { 0x8e000000, 0x00204411, 0x000 },
- { 0x00000028, 0x00204a2d, 0x000 },
- { 0x90000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x0000000c, 0x00211622, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x00000019, 0x00211a22, 0x000 },
- { 0x00000004, 0x00281a26, 0x000 },
- { 0x00000000, 0x002914c5, 0x000 },
- { 0x00000019, 0x00203625, 0x000 },
- { 0x00000000, 0x003a1402, 0x000 },
- { 0x00000016, 0x00211625, 0x000 },
- { 0x00000003, 0x00281625, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0xfffffffc, 0x00280e23, 0x000 },
- { 0x00000000, 0x002914a3, 0x000 },
- { 0x00000017, 0x00203625, 0x000 },
- { 0x00008000, 0x00280e22, 0x000 },
- { 0x00000007, 0x00220e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x20000000, 0x00280e22, 0x000 },
- { 0x00000006, 0x00210e23, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x00000000, 0x00220222, 0x000 },
- { 0x00000000, 0x14e00000, 0x038 },
- { 0x00000000, 0x2ee00000, 0x035 },
- { 0x00000000, 0x2ce00000, 0x037 },
- { 0x00000000, 0x00400e2d, 0x039 },
- { 0x00000008, 0x00200e2d, 0x000 },
- { 0x00000009, 0x0040122d, 0x046 },
- { 0x00000001, 0x00400e2d, 0x039 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x03e },
- { 0x00000008, 0x00401c11, 0x041 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x0000000f, 0x00281e27, 0x000 },
- { 0x00000003, 0x00221e27, 0x000 },
- { 0x7fc00000, 0x00281a23, 0x000 },
- { 0x00000014, 0x00211a26, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000008, 0x00221a26, 0x000 },
- { 0x00000000, 0x00290cc7, 0x000 },
- { 0x00000027, 0x00203624, 0x000 },
- { 0x00007f00, 0x00281221, 0x000 },
- { 0x00001400, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x04b },
- { 0x00000001, 0x00290e23, 0x000 },
- { 0x0000000e, 0x00203623, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfff80000, 0x00294a23, 0x000 },
- { 0x00000000, 0x003a2c02, 0x000 },
- { 0x00000002, 0x00220e2b, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x0000000f, 0x00203623, 0x000 },
- { 0x00001fff, 0x00294a23, 0x000 },
- { 0x00000027, 0x00204a2d, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000029, 0x00200e2d, 0x000 },
- { 0x060a0200, 0x00294a23, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00210222, 0x000 },
- { 0x00000000, 0x14e00000, 0x061 },
- { 0x00000000, 0x2ee00000, 0x05f },
- { 0x00000000, 0x2ce00000, 0x05e },
- { 0x00000000, 0x00400e2d, 0x062 },
- { 0x00000001, 0x00400e2d, 0x062 },
- { 0x0000000a, 0x00200e2d, 0x000 },
- { 0x0000000b, 0x0040122d, 0x06a },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x003ffffc, 0x00281223, 0x000 },
- { 0x00000002, 0x00221224, 0x000 },
- { 0x7fc00000, 0x00281623, 0x000 },
- { 0x00000014, 0x00211625, 0x000 },
- { 0x00000001, 0x00331625, 0x000 },
- { 0x80000000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00290ca3, 0x000 },
- { 0x3ffffc00, 0x00290e23, 0x000 },
- { 0x0000001f, 0x00211e23, 0x000 },
- { 0x00000000, 0x14e00000, 0x06d },
- { 0x00000100, 0x00401c11, 0x070 },
- { 0x0000000d, 0x00201e2d, 0x000 },
- { 0x000000f0, 0x00281e27, 0x000 },
- { 0x00000004, 0x00221e27, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0xfffff0ff, 0x00281a30, 0x000 },
- { 0x0000a028, 0x00204411, 0x000 },
- { 0x00000000, 0x002948e6, 0x000 },
- { 0x0000a018, 0x00204411, 0x000 },
- { 0x3fffffff, 0x00284a23, 0x000 },
- { 0x0000a010, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000030, 0x0020162d, 0x000 },
- { 0x00000002, 0x00291625, 0x000 },
- { 0x00000030, 0x00203625, 0x000 },
- { 0x00000025, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a3, 0x000 },
- { 0x00000000, 0x0cc00000, 0x083 },
- { 0x00000026, 0x0020162d, 0x000 },
- { 0x00000000, 0x002f00a4, 0x000 },
- { 0x00000000, 0x0cc00000, 0x084 },
- { 0x00000000, 0x00400000, 0x08a },
- { 0x00000025, 0x00203623, 0x000 },
- { 0x00000026, 0x00203624, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x08a },
- { 0x00000000, 0x00600000, 0x5ff },
- { 0x00000000, 0x00600000, 0x5f3 },
- { 0x00000002, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x08d },
- { 0x00000012, 0xc0403620, 0x093 },
- { 0x00000000, 0x2ee00000, 0x091 },
- { 0x00000000, 0x2ce00000, 0x090 },
- { 0x00000002, 0x00400e2d, 0x092 },
- { 0x00000003, 0x00400e2d, 0x092 },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000012, 0x00203623, 0x000 },
- { 0x00000003, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x098 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x0a0 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x2ee00000, 0x09e },
- { 0x00000000, 0x2ce00000, 0x09d },
- { 0x00000002, 0x00400e2d, 0x09f },
- { 0x00000003, 0x00400e2d, 0x09f },
- { 0x0000000c, 0x00200e2d, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x003f0000, 0x00280e23, 0x000 },
- { 0x00000010, 0x00210e23, 0x000 },
- { 0x00000011, 0x00203623, 0x000 },
- { 0x0000001e, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0a7 },
- { 0x00000016, 0xc0203620, 0x000 },
- { 0x0000001f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0aa },
- { 0x00000015, 0xc0203620, 0x000 },
- { 0x00000008, 0x00210e2b, 0x000 },
- { 0x0000007f, 0x00280e23, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0e1 },
- { 0x00000000, 0x27000000, 0x000 },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ae00000, 0x0b3 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x0000000c, 0x00221e30, 0x000 },
- { 0x99800000, 0x00204411, 0x000 },
- { 0x00000004, 0x0020122d, 0x000 },
- { 0x00000008, 0x00221224, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00291ce4, 0x000 },
- { 0x00000000, 0x00604807, 0x12f },
- { 0x9b000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x9c000000, 0x00204411, 0x000 },
- { 0x00000000, 0x0033146f, 0x000 },
- { 0x00000001, 0x00333e23, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0x00203c05, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e007, 0x00204411, 0x000 },
- { 0x0000000f, 0x0021022b, 0x000 },
- { 0x00000000, 0x14c00000, 0x0cb },
- { 0x00f8ff08, 0x00204811, 0x000 },
- { 0x98000000, 0x00404811, 0x0dc },
- { 0x000000f0, 0x00280e22, 0x000 },
- { 0x000000a0, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x0da },
- { 0x00000011, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0d5 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0d4 },
- { 0x00003f00, 0x00400c11, 0x0d6 },
- { 0x00001f00, 0x00400c11, 0x0d6 },
- { 0x00000f00, 0x00200c11, 0x000 },
- { 0x00380009, 0x00294a23, 0x000 },
- { 0x3f000000, 0x00280e2b, 0x000 },
- { 0x00000002, 0x00220e23, 0x000 },
- { 0x00000007, 0x00494a23, 0x0dc },
- { 0x00380f09, 0x00204811, 0x000 },
- { 0x68000007, 0x00204811, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000a202, 0x00204411, 0x000 },
- { 0x00ff0000, 0x00280e22, 0x000 },
- { 0x00000080, 0x00294a23, 0x000 },
- { 0x00000027, 0x00200e2d, 0x000 },
- { 0x00000026, 0x0020122d, 0x000 },
- { 0x00000000, 0x002f0083, 0x000 },
- { 0x00000000, 0x0ce00000, 0x0ea },
- { 0x00000000, 0x00600000, 0x5f9 },
- { 0x00000000, 0x00400000, 0x0eb },
- { 0x00000000, 0x00600000, 0x5fc },
- { 0x00000007, 0x0020222d, 0x000 },
- { 0x00000005, 0x00220e22, 0x000 },
- { 0x00100000, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x00000000, 0x003a0c02, 0x000 },
- { 0x000000ef, 0x00280e23, 0x000 },
- { 0x00000000, 0x00292068, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0x00000003, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x0f8 },
- { 0x0000000b, 0x00210228, 0x000 },
- { 0x00000000, 0x14c00000, 0x0f8 },
- { 0x00000400, 0x00292228, 0x000 },
- { 0x00000014, 0x00203628, 0x000 },
- { 0x0000001c, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x0fd },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000001e, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x10b },
- { 0x0000a30f, 0x00204411, 0x000 },
- { 0x00000011, 0x00200e2d, 0x000 },
- { 0x00000001, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x104 },
- { 0xffffffff, 0x00404811, 0x10b },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x107 },
- { 0x0000ffff, 0x00404811, 0x10b },
- { 0x00000004, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x10a },
- { 0x000000ff, 0x00404811, 0x10b },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0002c400, 0x00204411, 0x000 },
- { 0x0000001f, 0x00210e22, 0x000 },
- { 0x00000000, 0x14c00000, 0x112 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x00000013, 0x00203623, 0x000 },
- { 0x00000018, 0x40224a20, 0x000 },
- { 0x00000010, 0xc0424a20, 0x114 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x00000013, 0x00203623, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000000a, 0x00201011, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x11b },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00531224, 0x117 },
- { 0xffbfffff, 0x00283a2e, 0x000 },
- { 0x0000001b, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x12e },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000d, 0x00204811, 0x000 },
- { 0x00000018, 0x00220e30, 0x000 },
- { 0xfc000000, 0x00280e23, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x00000000, 0x00201010, 0x000 },
- { 0x0000e00e, 0x00204411, 0x000 },
- { 0x07f8ff08, 0x00204811, 0x000 },
- { 0x00000000, 0x00294a23, 0x000 },
- { 0x0000001c, 0x00201e2d, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a24, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x00800000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204806, 0x000 },
- { 0x00000008, 0x00214a27, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x622 },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x621 },
- { 0x00000004, 0x00404c11, 0x135 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x0000001c, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x622 },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x13c },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00000000, 0x00600000, 0x160 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40280620, 0x000 },
- { 0x00000010, 0xc0210a20, 0x000 },
- { 0x00000000, 0x00341461, 0x000 },
- { 0x00000000, 0x00741882, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x147 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x160 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0681a20, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x158 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000001, 0x00300a2f, 0x000 },
- { 0x00000001, 0x00210a22, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600000, 0x18f },
- { 0x00000000, 0x00600000, 0x1a0 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00202c08, 0x000 },
- { 0x00000000, 0x00202411, 0x000 },
- { 0x00000000, 0x00202811, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000002, 0x00221e29, 0x000 },
- { 0x00000000, 0x007048eb, 0x19c },
- { 0x00000000, 0x00600000, 0x2bb },
- { 0x00000001, 0x40330620, 0x000 },
- { 0x00000000, 0xc0302409, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ae00000, 0x181 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x00000000, 0x00400000, 0x186 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x186 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000001, 0x00530621, 0x182 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0604800, 0x197 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000011, 0x0020062d, 0x000 },
- { 0x00000000, 0x0078042a, 0x2fb },
- { 0x00000000, 0x00202809, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x174 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000210, 0x00600411, 0x315 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x194 },
- { 0x00000015, 0xc0203620, 0x000 },
- { 0x00000016, 0xc0203620, 0x000 },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x46000000, 0x00600811, 0x1b2 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x19b },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000021, 0x00804811, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000ffff, 0x40281620, 0x000 },
- { 0x00000010, 0xc0811a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x00000008, 0x00221e30, 0x000 },
- { 0x00000029, 0x00201a2d, 0x000 },
- { 0x0000e000, 0x00204411, 0x000 },
- { 0xfffbff09, 0x00204811, 0x000 },
- { 0x0000000f, 0x0020222d, 0x000 },
- { 0x00001fff, 0x00294a28, 0x000 },
- { 0x00000006, 0x0020222d, 0x000 },
- { 0x00000000, 0x002920e8, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00294a26, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000100, 0x00201811, 0x000 },
- { 0x00000008, 0x00621e28, 0x12f },
- { 0x00000008, 0x00822228, 0x000 },
- { 0x0002c000, 0x00204411, 0x000 },
- { 0x00000015, 0x00600e2d, 0x1bd },
- { 0x00000016, 0x00600e2d, 0x1bd },
- { 0x0000c008, 0x00204411, 0x000 },
- { 0x00000017, 0x00200e2d, 0x000 },
- { 0x00000000, 0x14c00000, 0x1b9 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x39000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00804802, 0x000 },
- { 0x00000018, 0x00202e2d, 0x000 },
- { 0x00000000, 0x003b0d63, 0x000 },
- { 0x00000008, 0x00224a23, 0x000 },
- { 0x00000010, 0x00224a23, 0x000 },
- { 0x00000018, 0x00224a23, 0x000 },
- { 0x00000000, 0x00804803, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00001000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00000007, 0x0021062f, 0x000 },
- { 0x00000013, 0x00200a2d, 0x000 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000ffff, 0x40282220, 0x000 },
- { 0x0000000f, 0x00262228, 0x000 },
- { 0x00000010, 0x40212620, 0x000 },
- { 0x0000000f, 0x00262629, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001b, 0x00204811, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1e0 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000081, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000080, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1dc },
- { 0x00000000, 0x00600000, 0x1e9 },
- { 0x00000001, 0x00531e27, 0x1d8 },
- { 0x00000001, 0x00202c11, 0x000 },
- { 0x0000001f, 0x00280a22, 0x000 },
- { 0x0000001f, 0x00282a2a, 0x000 },
- { 0x00000001, 0x00530621, 0x1d1 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000002, 0x00304a2f, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000001, 0x00301e2f, 0x000 },
- { 0x00000000, 0x002f0227, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00600000, 0x1e9 },
- { 0x00000001, 0x00531e27, 0x1e5 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x0000000f, 0x00260e23, 0x000 },
- { 0x00000010, 0xc0211220, 0x000 },
- { 0x0000000f, 0x00261224, 0x000 },
- { 0x00000000, 0x00201411, 0x000 },
- { 0x00000000, 0x00601811, 0x2bb },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022b, 0x000 },
- { 0x00000000, 0x0ce00000, 0x1f8 },
- { 0x00000010, 0x00221628, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a29, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x0020480a, 0x000 },
- { 0x00000000, 0x00202c11, 0x000 },
- { 0x00000010, 0x00221623, 0x000 },
- { 0xffff0000, 0x00281625, 0x000 },
- { 0x0000ffff, 0x00281a24, 0x000 },
- { 0x00000000, 0x002948c5, 0x000 },
- { 0x00000000, 0x00731503, 0x205 },
- { 0x00000000, 0x00201805, 0x000 },
- { 0x00000000, 0x00731524, 0x205 },
- { 0x00000000, 0x002d14c5, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00202802, 0x000 },
- { 0x00000000, 0x00202003, 0x000 },
- { 0x00000000, 0x00802404, 0x000 },
- { 0x0000000f, 0x00210225, 0x000 },
- { 0x00000000, 0x14c00000, 0x621 },
- { 0x00000000, 0x002b1405, 0x000 },
- { 0x00000001, 0x00901625, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001a, 0x00294a22, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a21, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000ffff, 0x40281220, 0x000 },
- { 0x00000010, 0xc0211a20, 0x000 },
- { 0x0000ffff, 0x40280e20, 0x000 },
- { 0x00000010, 0xc0211620, 0x000 },
- { 0x00000000, 0x00741465, 0x2bb },
- { 0x0001a1fd, 0x00604411, 0x2e0 },
- { 0x00000001, 0x00330621, 0x000 },
- { 0x00000000, 0x002f0221, 0x000 },
- { 0x00000000, 0x0cc00000, 0x219 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x212 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x5de },
- { 0x00000000, 0x0040040f, 0x213 },
- { 0x00000000, 0x00600000, 0x5d1 },
- { 0x00000000, 0x00600000, 0x5de },
- { 0x00000210, 0x00600411, 0x315 },
- { 0x00000000, 0x00600000, 0x1a0 },
- { 0x00000000, 0x00600000, 0x19c },
- { 0x00000000, 0x00600000, 0x2bb },
- { 0x00000000, 0x00600000, 0x2a3 },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204808, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ae00000, 0x232 },
- { 0x00000000, 0x00600000, 0x13a },
- { 0x00000000, 0x00400000, 0x236 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x236 },
- { 0x00000000, 0xc0404800, 0x233 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x00600411, 0x2fb },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000000, 0x00600000, 0x5d1 },
- { 0x0000a00c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000018, 0x40210a20, 0x000 },
- { 0x00000003, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x24c },
- { 0x00000014, 0x0020222d, 0x000 },
- { 0x00080101, 0x00292228, 0x000 },
- { 0x00000014, 0x00203628, 0x000 },
- { 0x0000a30c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x251 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000010, 0x00600411, 0x315 },
- { 0x3f800000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x00000000, 0x00600000, 0x27c },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000001, 0x00211e27, 0x000 },
- { 0x00000000, 0x14e00000, 0x26a },
- { 0x00000012, 0x00201e2d, 0x000 },
- { 0x0000ffff, 0x00281e27, 0x000 },
- { 0x00000000, 0x00341c27, 0x000 },
- { 0x00000000, 0x12c00000, 0x25f },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e5, 0x000 },
- { 0x00000000, 0x08c00000, 0x262 },
- { 0x00000000, 0x00201407, 0x000 },
- { 0x00000012, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00211e27, 0x000 },
- { 0x00000000, 0x00341c47, 0x000 },
- { 0x00000000, 0x12c00000, 0x267 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x08c00000, 0x26a },
- { 0x00000000, 0x00201807, 0x000 },
- { 0x00000000, 0x00600000, 0x2c1 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x00000000, 0x00342023, 0x000 },
- { 0x00000000, 0x12c00000, 0x272 },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x271 },
- { 0x00000016, 0x00404811, 0x276 },
- { 0x00000018, 0x00404811, 0x276 },
- { 0x00000000, 0x00342044, 0x000 },
- { 0x00000000, 0x12c00000, 0x275 },
- { 0x00000017, 0x00404811, 0x276 },
- { 0x00000019, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0x00604411, 0x2e9 },
- { 0x00003fff, 0x002f022f, 0x000 },
- { 0x00000000, 0x0cc00000, 0x256 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x00000010, 0x40210620, 0x000 },
- { 0x0000ffff, 0xc0280a20, 0x000 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x00000010, 0x40211620, 0x000 },
- { 0x0000ffff, 0xc0881a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00042004, 0x00604411, 0x622 },
- { 0x00000000, 0x00600000, 0x5d1 },
- { 0x00000000, 0xc0600000, 0x2a3 },
- { 0x00000005, 0x00200a2d, 0x000 },
- { 0x00000008, 0x00220a22, 0x000 },
- { 0x0000002b, 0x00201a2d, 0x000 },
- { 0x0000001c, 0x00201e2d, 0x000 },
- { 0x00007000, 0x00281e27, 0x000 },
- { 0x00000000, 0x00311ce6, 0x000 },
- { 0x0000002a, 0x00201a2d, 0x000 },
- { 0x0000000c, 0x00221a26, 0x000 },
- { 0x00000000, 0x002f00e6, 0x000 },
- { 0x00000000, 0x06e00000, 0x292 },
- { 0x00000000, 0x00201c11, 0x000 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x0000002b, 0x00203623, 0x000 },
- { 0x00000010, 0x00201811, 0x000 },
- { 0x00000000, 0x00691ce2, 0x12f },
- { 0x93800000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x95000000, 0x00204411, 0x000 },
- { 0x00000000, 0x002f022f, 0x000 },
- { 0x00000000, 0x0ce00000, 0x29d },
- { 0x00000001, 0x00333e2f, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x92000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000001c, 0x00403627, 0x000 },
- { 0x0000000c, 0xc0220a20, 0x000 },
- { 0x00000029, 0x00203622, 0x000 },
- { 0x00000028, 0xc0403620, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000009, 0x00204811, 0x000 },
- { 0xa1000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00804811, 0x000 },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce3, 0x000 },
- { 0x00000021, 0x00203627, 0x000 },
- { 0x00000022, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002c1ce4, 0x000 },
- { 0x00000022, 0x00203627, 0x000 },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a3, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x00000023, 0x00203627, 0x000 },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x00000000, 0x002d1d07, 0x000 },
- { 0x00000024, 0x00803627, 0x000 },
- { 0x00000021, 0x00203623, 0x000 },
- { 0x00000022, 0x00203624, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000023, 0x00203627, 0x000 },
- { 0x00000000, 0x00311cc4, 0x000 },
- { 0x00000024, 0x00803627, 0x000 },
- { 0x0000001a, 0x00203627, 0x000 },
- { 0x0000001b, 0x00203628, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14c00000, 0x2dc },
- { 0x00000000, 0x00400000, 0x2d9 },
- { 0x0000001a, 0x00203627, 0x000 },
- { 0x0000001b, 0x00203628, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000002, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2d9 },
- { 0x00000003, 0x00210227, 0x000 },
- { 0x00000000, 0x14e00000, 0x2dc },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e1, 0x000 },
- { 0x00000000, 0x02c00000, 0x2dc },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120a1, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2dc },
- { 0x00000024, 0x00201e2d, 0x000 },
- { 0x00000000, 0x002e00e2, 0x000 },
- { 0x00000000, 0x02c00000, 0x2dc },
- { 0x00000022, 0x00201e2d, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x00000000, 0x002e00e8, 0x000 },
- { 0x00000000, 0x06c00000, 0x2dc },
- { 0x00000000, 0x00600000, 0x5ff },
- { 0x00000000, 0x00600000, 0x2b5 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x00000000, 0x00600000, 0x2b5 },
- { 0x00000000, 0x00600000, 0x5f6 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x00000000, 0x00600000, 0x2a7 },
- { 0x00000000, 0x00400000, 0x2de },
- { 0x0000001a, 0x00201e2d, 0x000 },
- { 0x0000001b, 0x0080222d, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000000, 0x00311ca1, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294847, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e21, 0x000 },
- { 0x00000000, 0x003120c2, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00311ca3, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294887, 0x000 },
- { 0x00000001, 0x00220a21, 0x000 },
- { 0x00000000, 0x003008a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000010, 0x00221e23, 0x000 },
- { 0x00000000, 0x003120c4, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x003808c5, 0x000 },
- { 0x00000000, 0x00300841, 0x000 },
- { 0x00000001, 0x00220a22, 0x000 },
- { 0x00000000, 0x003308a2, 0x000 },
- { 0x00000010, 0x00221e22, 0x000 },
- { 0x00000010, 0x00212222, 0x000 },
- { 0x00000000, 0x00894907, 0x000 },
- { 0x00000017, 0x0020222d, 0x000 },
- { 0x00000000, 0x14c00000, 0x318 },
- { 0xffffffef, 0x00280621, 0x000 },
- { 0x00000014, 0x0020222d, 0x000 },
- { 0x0000f8e0, 0x00204411, 0x000 },
- { 0x00000000, 0x00294901, 0x000 },
- { 0x00000000, 0x00894901, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x060a0200, 0x00804811, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x97000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0204811, 0x000 },
- { 0x8a000000, 0xc0204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00002257, 0x00204411, 0x000 },
- { 0x00000003, 0xc0484a20, 0x000 },
- { 0x0000225d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0x00600000, 0x5de },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00384a22, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0001a1fd, 0x00204411, 0x000 },
- { 0x00000000, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x00000001, 0x40304a20, 0x000 },
- { 0x00000002, 0xc0304a20, 0x000 },
- { 0x00000001, 0x00530a22, 0x355 },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000018, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x622 },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x35e },
- { 0x00000014, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x36c },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00604802, 0x374 },
- { 0x00002100, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000004, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x370 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x367 },
- { 0x00000028, 0x002f0222, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5ba },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x367 },
- { 0x0000002c, 0x00203626, 0x000 },
- { 0x00000049, 0x00201811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x00000001, 0x00331a26, 0x000 },
- { 0x00000000, 0x002f0226, 0x000 },
- { 0x00000000, 0x0cc00000, 0x376 },
- { 0x0000002c, 0x00801a2d, 0x000 },
- { 0x0000003f, 0xc0280a20, 0x000 },
- { 0x00000015, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x38c },
- { 0x00000006, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3b7 },
- { 0x00000016, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3b9 },
- { 0x00000020, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3a2 },
- { 0x0000000f, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3ae },
- { 0x00000010, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x3ae },
- { 0x0000001e, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x396 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x08000000, 0x00290a22, 0x000 },
- { 0x00000003, 0x40210e20, 0x000 },
- { 0x0000000c, 0xc0211220, 0x000 },
- { 0x00080000, 0x00281224, 0x000 },
- { 0x00000014, 0xc0221620, 0x000 },
- { 0x00000000, 0x002914a4, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x002948a2, 0x000 },
- { 0x0000a1fe, 0x00204411, 0x000 },
- { 0x00000000, 0x00404803, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000016, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x622 },
- { 0x00000015, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x398 },
- { 0x0000210e, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000017, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x622 },
- { 0x00000003, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x3a4 },
- { 0x00002108, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404802, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x80000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000010, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x3b4 },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000006, 0x00404811, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000016, 0x00604811, 0x374 },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x0000001d, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x3ce },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x00000018, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x622 },
- { 0x00000011, 0x00210230, 0x000 },
- { 0x00000000, 0x14e00000, 0x3c2 },
- { 0x00002100, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0xbabecafe, 0x00204811, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000004, 0x00404811, 0x000 },
- { 0x00002170, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000a, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x3d3 },
- { 0x8c000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00003fff, 0x40280a20, 0x000 },
- { 0x80000000, 0x40280e20, 0x000 },
- { 0x40000000, 0xc0281220, 0x000 },
- { 0x00040000, 0x00694622, 0x622 },
- { 0x00000000, 0x00201410, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3e1 },
- { 0x00000000, 0xc0401800, 0x3e4 },
- { 0x00003fff, 0xc0281a20, 0x000 },
- { 0x00040000, 0x00694626, 0x622 },
- { 0x00000000, 0x00201810, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x3e7 },
- { 0x00000000, 0xc0401c00, 0x3ea },
- { 0x00003fff, 0xc0281e20, 0x000 },
- { 0x00040000, 0x00694627, 0x622 },
- { 0x00000000, 0x00201c10, 0x000 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0x002820c5, 0x000 },
- { 0x00000000, 0x004948e8, 0x000 },
- { 0xa5800000, 0x00200811, 0x000 },
- { 0x00002000, 0x00200c11, 0x000 },
- { 0x83000000, 0x00604411, 0x412 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x40204800, 0x000 },
- { 0x0000001f, 0xc0210220, 0x000 },
- { 0x00000000, 0x14c00000, 0x3f7 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00008000, 0x00204811, 0x000 },
- { 0x0000ffff, 0xc0481220, 0x3ff },
- { 0xa7800000, 0x00200811, 0x000 },
- { 0x0000a000, 0x00200c11, 0x000 },
- { 0x83000000, 0x00604411, 0x412 },
- { 0x00000000, 0x00204402, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000ffff, 0xc0281220, 0x000 },
- { 0x83000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00304883, 0x000 },
- { 0x84000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x1d000000, 0x000 },
- { 0x83000000, 0x00604411, 0x412 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0xa9800000, 0x00200811, 0x000 },
- { 0x0000c000, 0x00400c11, 0x3fa },
- { 0xab800000, 0x00200811, 0x000 },
- { 0x0000f8e0, 0x00400c11, 0x3fa },
- { 0xad800000, 0x00200811, 0x000 },
- { 0x0000f880, 0x00400c11, 0x3fa },
- { 0xb3800000, 0x00200811, 0x000 },
- { 0x0000f3fc, 0x00400c11, 0x3fa },
- { 0xaf800000, 0x00200811, 0x000 },
- { 0x0000e000, 0x00400c11, 0x3fa },
- { 0xb1800000, 0x00200811, 0x000 },
- { 0x0000f000, 0x00400c11, 0x3fa },
- { 0x83000000, 0x00204411, 0x000 },
- { 0x00002148, 0x00204811, 0x000 },
- { 0x84000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x1d000000, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x01182000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0218a000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0318c000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0418f8e0, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0518f880, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0618e000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0718f000, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x0818f3fc, 0xc0304620, 0x000 },
- { 0x00000000, 0xd9004800, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x00000033, 0xc0300a20, 0x000 },
- { 0x00000000, 0xc0403440, 0x000 },
- { 0x00000030, 0x00200a2d, 0x000 },
- { 0x00000000, 0xc0290c40, 0x000 },
- { 0x00000030, 0x00203623, 0x000 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x00a0000a, 0x000 },
- { 0x86000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00404801, 0x000 },
- { 0x85000000, 0xc0204411, 0x000 },
- { 0x00000000, 0x00404801, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x00000018, 0x40210220, 0x000 },
- { 0x00000000, 0x14c00000, 0x447 },
- { 0x00800000, 0xc0494a20, 0x448 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000004, 0x002f0222, 0x000 },
- { 0x00000000, 0x06e00000, 0x450 },
- { 0x00000004, 0x00200811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x622 },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000000, 0x00404c02, 0x450 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x00000000, 0xc0201000, 0x000 },
- { 0x00000000, 0xc0201400, 0x000 },
- { 0x00000000, 0xc0201800, 0x000 },
- { 0x00000000, 0xc0201c00, 0x000 },
- { 0x00007f00, 0x00280a21, 0x000 },
- { 0x00004500, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x461 },
- { 0x00000000, 0xc0202000, 0x000 },
- { 0x00000004, 0x002f0228, 0x000 },
- { 0x00000000, 0x06e00000, 0x461 },
- { 0x00000004, 0x00202011, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x00000010, 0x00280a23, 0x000 },
- { 0x00000010, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ce00000, 0x469 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00040000, 0x00694624, 0x622 },
- { 0x00000000, 0x00400000, 0x46e },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000216d, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000000, 0x00604805, 0x627 },
- { 0x00000000, 0x002824f0, 0x000 },
- { 0x00000007, 0x00280a23, 0x000 },
- { 0x00000001, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x475 },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x04e00000, 0x48e },
- { 0x00000000, 0x00400000, 0x49b },
- { 0x00000002, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x47a },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x02e00000, 0x48e },
- { 0x00000000, 0x00400000, 0x49b },
- { 0x00000003, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x47f },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x0ce00000, 0x48e },
- { 0x00000000, 0x00400000, 0x49b },
- { 0x00000004, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x484 },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x0ae00000, 0x48e },
- { 0x00000000, 0x00400000, 0x49b },
- { 0x00000005, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x489 },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x06e00000, 0x48e },
- { 0x00000000, 0x00400000, 0x49b },
- { 0x00000006, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x48e },
- { 0x00000000, 0x002f00c9, 0x000 },
- { 0x00000000, 0x08e00000, 0x48e },
- { 0x00000000, 0x00400000, 0x49b },
- { 0x00007f00, 0x00280a21, 0x000 },
- { 0x00004500, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x000 },
- { 0x00000008, 0x00210a23, 0x000 },
- { 0x00000000, 0x14c00000, 0x498 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x00000000, 0xc0204400, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00007f00, 0x00280a21, 0x000 },
- { 0x00004500, 0x002f0222, 0x000 },
- { 0x00000000, 0x0ae00000, 0x4a1 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0400000, 0x000 },
- { 0x00000000, 0x00404c08, 0x461 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000010, 0x40210e20, 0x000 },
- { 0x00000011, 0x40211220, 0x000 },
- { 0x00000012, 0x40211620, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00210225, 0x000 },
- { 0x00000000, 0x14e00000, 0x4ab },
- { 0x00040000, 0xc0494a20, 0x4ac },
- { 0xfffbffff, 0xc0284a20, 0x000 },
- { 0x00000000, 0x00210223, 0x000 },
- { 0x00000000, 0x14e00000, 0x4b8 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x00210224, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x0000000c, 0x00204811, 0x000 },
- { 0x00000000, 0x00200010, 0x000 },
- { 0x00000000, 0x14c00000, 0x4b4 },
- { 0xa0000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000004, 0x00204811, 0x000 },
- { 0x0000216b, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204810, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000005, 0x00204811, 0x000 },
- { 0x0000216c, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204810, 0x000 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0ce00000, 0x000 },
- { 0x00000000, 0x00400000, 0x4b2 },
- { 0x00000000, 0xc0210a20, 0x000 },
- { 0x00000000, 0x14c00000, 0x4cb },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000216d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0604800, 0x627 },
- { 0x00000000, 0x00400000, 0x4cf },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00040000, 0xc0294620, 0x000 },
- { 0x00000000, 0xc0600000, 0x622 },
- { 0x00000001, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x4d6 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0xcafebabe, 0x00404811, 0x000 },
- { 0x00000000, 0xc0204400, 0x000 },
- { 0x00000000, 0xc0404810, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x000021f8, 0x00204411, 0x000 },
- { 0x0000000e, 0x00204811, 0x000 },
- { 0x000421f9, 0x00604411, 0x622 },
- { 0x00000000, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x4d8 },
- { 0x00002180, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000003, 0x00333e2f, 0x000 },
- { 0x00000001, 0x00210221, 0x000 },
- { 0x00000000, 0x14e00000, 0x508 },
- { 0x0000002c, 0x00200a2d, 0x000 },
- { 0x00040000, 0x18e00c11, 0x4f7 },
- { 0x00000001, 0x00333e2f, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000008, 0x00300a22, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000008, 0x00300a22, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xd8c04800, 0x4eb },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000008, 0x00300a22, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000002d, 0x0020122d, 0x000 },
- { 0x00000000, 0x00290c83, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204802, 0x000 },
- { 0x00000000, 0x00204803, 0x000 },
- { 0x00000008, 0x00300a22, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000011, 0x00210224, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000000, 0x00400000, 0x4b2 },
- { 0x0000002c, 0xc0203620, 0x000 },
- { 0x0000002d, 0xc0403620, 0x000 },
- { 0x0000000f, 0x00210221, 0x000 },
- { 0x00000000, 0x14c00000, 0x50d },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00000000, 0xd9000000, 0x000 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0xb5000000, 0x00204411, 0x000 },
- { 0x00002000, 0x00204811, 0x000 },
- { 0xb6000000, 0x00204411, 0x000 },
- { 0x0000a000, 0x00204811, 0x000 },
- { 0xb7000000, 0x00204411, 0x000 },
- { 0x0000c000, 0x00204811, 0x000 },
- { 0xb8000000, 0x00204411, 0x000 },
- { 0x0000f8e0, 0x00204811, 0x000 },
- { 0xb9000000, 0x00204411, 0x000 },
- { 0x0000f880, 0x00204811, 0x000 },
- { 0xba000000, 0x00204411, 0x000 },
- { 0x0000e000, 0x00204811, 0x000 },
- { 0xbb000000, 0x00204411, 0x000 },
- { 0x0000f000, 0x00204811, 0x000 },
- { 0xbc000000, 0x00204411, 0x000 },
- { 0x0000f3fc, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000002, 0x00204811, 0x000 },
- { 0x000000ff, 0x00280e30, 0x000 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x521 },
- { 0x00000000, 0xc0200800, 0x000 },
- { 0x00000000, 0x14c00000, 0x536 },
- { 0x00000000, 0x00200c11, 0x000 },
- { 0x0000001c, 0x00203623, 0x000 },
- { 0x0000002b, 0x00203623, 0x000 },
- { 0x00000029, 0x00203623, 0x000 },
- { 0x00000028, 0x00203623, 0x000 },
- { 0x00000017, 0x00203623, 0x000 },
- { 0x00000025, 0x00203623, 0x000 },
- { 0x00000026, 0x00203623, 0x000 },
- { 0x00000015, 0x00203623, 0x000 },
- { 0x00000016, 0x00203623, 0x000 },
- { 0xffffe000, 0x00200c11, 0x000 },
- { 0x00000021, 0x00203623, 0x000 },
- { 0x00000022, 0x00203623, 0x000 },
- { 0x00001fff, 0x00200c11, 0x000 },
- { 0x00000023, 0x00203623, 0x000 },
- { 0x00000024, 0x00203623, 0x000 },
- { 0xf1ffffff, 0x00283a2e, 0x000 },
- { 0x0000001a, 0xc0220e20, 0x000 },
- { 0x00000000, 0x0029386e, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000006, 0x00204811, 0x000 },
- { 0x0000002a, 0x40203620, 0x000 },
- { 0x87000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x0000a1f4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0x9d000000, 0x00204411, 0x000 },
- { 0x0000001f, 0x40214a20, 0x000 },
- { 0x96000000, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0200c00, 0x000 },
- { 0x00000000, 0xc0201000, 0x000 },
- { 0x0000001f, 0x00211624, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x0000001d, 0x00203623, 0x000 },
- { 0x00000003, 0x00281e23, 0x000 },
- { 0x00000008, 0x00222223, 0x000 },
- { 0xfffff000, 0x00282228, 0x000 },
- { 0x00000000, 0x002920e8, 0x000 },
- { 0x0000001f, 0x00203628, 0x000 },
- { 0x00000018, 0x00211e23, 0x000 },
- { 0x00000020, 0x00203627, 0x000 },
- { 0x00000002, 0x00221624, 0x000 },
- { 0x00000000, 0x003014a8, 0x000 },
- { 0x0000001e, 0x00203625, 0x000 },
- { 0x00000003, 0x00211a24, 0x000 },
- { 0x10000000, 0x00281a26, 0x000 },
- { 0xefffffff, 0x00283a2e, 0x000 },
- { 0x00000000, 0x004938ce, 0x610 },
- { 0x00000001, 0x40280a20, 0x000 },
- { 0x00000006, 0x40280e20, 0x000 },
- { 0x00000300, 0xc0281220, 0x000 },
- { 0x00000008, 0x00211224, 0x000 },
- { 0x00000000, 0xc0201620, 0x000 },
- { 0x00000000, 0xc0201a20, 0x000 },
- { 0x00000000, 0x00210222, 0x000 },
- { 0x00000000, 0x14c00000, 0x56c },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00002258, 0x00300a24, 0x000 },
- { 0x00040000, 0x00694622, 0x622 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x00020000, 0x00294a26, 0x000 },
- { 0x00000000, 0x00204810, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x574 },
- { 0x00000000, 0xc0201c10, 0x000 },
- { 0x00000000, 0xc0400000, 0x582 },
- { 0x00000002, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x574 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00002258, 0x00300a24, 0x000 },
- { 0x00040000, 0x00694622, 0x622 },
- { 0x00000000, 0xc0201c10, 0x000 },
- { 0x00000000, 0xc0400000, 0x582 },
- { 0x00000000, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x578 },
- { 0x00000000, 0xc0201c00, 0x000 },
- { 0x00000000, 0xc0400000, 0x582 },
- { 0x00000004, 0x002f0223, 0x000 },
- { 0x00000000, 0x0cc00000, 0x580 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x0000216d, 0x00204411, 0x000 },
- { 0x00000000, 0xc0204800, 0x000 },
- { 0x00000000, 0xc0604800, 0x627 },
- { 0x00000000, 0x00401c10, 0x582 },
- { 0x00000000, 0xc0200000, 0x000 },
- { 0x00000000, 0xc0400000, 0x000 },
- { 0x00000000, 0x0ee00000, 0x584 },
- { 0x00000000, 0x00600000, 0x5c3 },
- { 0x00000000, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x592 },
- { 0x0000a2b7, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x00000033, 0x0020262d, 0x000 },
- { 0x0000001a, 0x00212229, 0x000 },
- { 0x00000006, 0x00222629, 0x000 },
- { 0x0000a2c4, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x590 },
- { 0x0000a2d1, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d1, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x00000001, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5a0 },
- { 0x0000a2bb, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x00000034, 0x0020262d, 0x000 },
- { 0x0000001a, 0x00212229, 0x000 },
- { 0x00000006, 0x00222629, 0x000 },
- { 0x0000a2c5, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x59e },
- { 0x0000a2d2, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d2, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x00000002, 0x002f0224, 0x000 },
- { 0x00000000, 0x0cc00000, 0x5ae },
- { 0x0000a2bf, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x00000035, 0x0020262d, 0x000 },
- { 0x0000001a, 0x00212229, 0x000 },
- { 0x00000006, 0x00222629, 0x000 },
- { 0x0000a2c6, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x5ac },
- { 0x0000a2d3, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d3, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x0000a2c3, 0x00204411, 0x000 },
- { 0x00000000, 0x00204807, 0x000 },
- { 0x00000036, 0x0020262d, 0x000 },
- { 0x0000001a, 0x00212229, 0x000 },
- { 0x00000006, 0x00222629, 0x000 },
- { 0x0000a2c7, 0x00204411, 0x000 },
- { 0x00000000, 0x003048e9, 0x000 },
- { 0x00000000, 0x00e00000, 0x5b8 },
- { 0x0000a2d4, 0x00204411, 0x000 },
- { 0x00000000, 0x00404808, 0x000 },
- { 0x0000a2d4, 0x00204411, 0x000 },
- { 0x00000001, 0x00504a28, 0x000 },
- { 0x85000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0x0000304a, 0x00204411, 0x000 },
- { 0x01000000, 0x00204811, 0x000 },
- { 0x00000000, 0x00400000, 0x5be },
- { 0xa4000000, 0xc0204411, 0x000 },
- { 0x00000000, 0xc0404800, 0x000 },
- { 0x00000000, 0xc0600000, 0x5c3 },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x0000003f, 0x00204811, 0x000 },
- { 0x00000005, 0x00204811, 0x000 },
- { 0x0000a1f4, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x88000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0xff000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x00000002, 0x00804811, 0x000 },
- { 0x00000000, 0x0ee00000, 0x5d6 },
- { 0x00001000, 0x00200811, 0x000 },
- { 0x0000002b, 0x00203622, 0x000 },
- { 0x00000000, 0x00600000, 0x5da },
- { 0x00000000, 0x00600000, 0x5c3 },
- { 0x98000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00804811, 0x000 },
- { 0x00000000, 0xc0600000, 0x5da },
- { 0x00000000, 0xc0400400, 0x001 },
- { 0x0000a2a4, 0x00204411, 0x000 },
- { 0x00000022, 0x00204811, 0x000 },
- { 0x89000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00404811, 0x5cd },
- { 0x97000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x8a000000, 0x00204411, 0x000 },
- { 0x00000000, 0x00404811, 0x5cd },
- { 0x00000000, 0x00600000, 0x5f3 },
- { 0x0001a2a4, 0xc0204411, 0x000 },
- { 0x00000016, 0x00604811, 0x374 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00010000, 0x00204811, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x09800000, 0x00204811, 0x000 },
- { 0xffffffff, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x0004217f, 0x00604411, 0x622 },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x000 },
- { 0x00000004, 0x00404c11, 0x5ed },
- { 0x00000000, 0x00400000, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000004, 0x00291e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0xfffffffb, 0x00281e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0x00000008, 0x00291e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x00000017, 0x00201e2d, 0x000 },
- { 0xfffffff7, 0x00281e27, 0x000 },
- { 0x00000017, 0x00803627, 0x000 },
- { 0x0001a2a4, 0x00204411, 0x000 },
- { 0x00000016, 0x00604811, 0x374 },
- { 0x00002010, 0x00204411, 0x000 },
- { 0x00010000, 0x00204811, 0x000 },
- { 0x0000217c, 0x00204411, 0x000 },
- { 0x01800000, 0x00204811, 0x000 },
- { 0xffffffff, 0x00204811, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000000, 0x17000000, 0x000 },
- { 0x81000000, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0004217f, 0x00604411, 0x622 },
- { 0x0000001f, 0x00210230, 0x000 },
- { 0x00000000, 0x14c00000, 0x621 },
- { 0x00000010, 0x00404c11, 0x607 },
- { 0x00000000, 0xc0200400, 0x000 },
- { 0x00000000, 0x38c00000, 0x000 },
- { 0x0000001d, 0x00200a2d, 0x000 },
- { 0x0000001e, 0x00200e2d, 0x000 },
- { 0x0000001f, 0x0020122d, 0x000 },
- { 0x00000020, 0x0020162d, 0x000 },
- { 0x00002169, 0x00204411, 0x000 },
- { 0x00000000, 0x00204804, 0x000 },
- { 0x00000000, 0x00204805, 0x000 },
- { 0x00000000, 0x00204801, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000004, 0x00301224, 0x000 },
- { 0x00000000, 0x002f0064, 0x000 },
- { 0x00000000, 0x0cc00000, 0x620 },
- { 0x00000003, 0x00281a22, 0x000 },
- { 0x00000008, 0x00221222, 0x000 },
- { 0xfffff000, 0x00281224, 0x000 },
- { 0x00000000, 0x002910c4, 0x000 },
- { 0x0000001f, 0x00403624, 0x000 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x1ac00000, 0x622 },
- { 0x9f000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000000, 0x1ae00000, 0x625 },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x1ac00000, 0x627 },
- { 0x9e000000, 0x00204411, 0x000 },
- { 0xcafebabe, 0x00204811, 0x000 },
- { 0x00000000, 0x1ae00000, 0x62a },
- { 0x00000000, 0x00800000, 0x000 },
- { 0x00000000, 0x00600000, 0x00b },
- { 0x00001000, 0x00600411, 0x315 },
- { 0x00000000, 0x00200411, 0x000 },
- { 0x00000000, 0x00600811, 0x1b2 },
- { 0x0000225c, 0x00204411, 0x000 },
- { 0x00000003, 0x00204811, 0x000 },
- { 0x00002256, 0x00204411, 0x000 },
- { 0x0000001b, 0x00204811, 0x000 },
- { 0x0000a1fc, 0x00204411, 0x000 },
- { 0x00000001, 0x00204811, 0x000 },
- { 0x0001a1fd, 0xc0204411, 0x000 },
- { 0x00000021, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000024, 0x0020222d, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000022, 0x0020222d, 0x000 },
- { 0x0000ffff, 0x00282228, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00204811, 0x000 },
- { 0x00000023, 0x00201e2d, 0x000 },
- { 0x00000010, 0x00221e27, 0x000 },
- { 0x00000000, 0x00294907, 0x000 },
- { 0x00000000, 0x00404811, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
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- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
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- { 0x00000000, 0x00000000, 0x000 },
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- { 0x00000000, 0x00000000, 0x000 },
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- { 0x00000000, 0x00000000, 0x000 },
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- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x00000000, 0x00000000, 0x000 },
- { 0x0142050a, 0x05ba0250, 0x000 },
- { 0x01c30168, 0x044105ba, 0x000 },
- { 0x02250209, 0x02500151, 0x000 },
- { 0x02230245, 0x02a00241, 0x000 },
- { 0x03d705ba, 0x05ba05ba, 0x000 },
- { 0x05e205e3, 0x031f05ba, 0x000 },
- { 0x032005bf, 0x0320034a, 0x000 },
- { 0x03340282, 0x034c033e, 0x000 },
- { 0x05ba05ba, 0x05ba05ba, 0x000 },
- { 0x05ba0557, 0x05ba032a, 0x000 },
- { 0x03bc05ba, 0x04c3034e, 0x000 },
- { 0x04a20455, 0x043f05ba, 0x000 },
- { 0x04d805ba, 0x044304e5, 0x000 },
- { 0x0455050f, 0x035b037b, 0x000 },
- { 0x05ba05ba, 0x05ba05ba, 0x000 },
- { 0x05ba05ba, 0x05ba05ba, 0x000 },
- { 0x05ba05ba, 0x05d805c1, 0x000 },
- { 0x05ba05ba, 0x000705ba, 0x000 },
- { 0x05ba05ba, 0x05ba05ba, 0x000 },
- { 0x05ba05ba, 0x05ba05ba, 0x000 },
- { 0x03f803ed, 0x04080406, 0x000 },
- { 0x040e040a, 0x040c0410, 0x000 },
- { 0x041c0418, 0x04240420, 0x000 },
- { 0x042c0428, 0x04340430, 0x000 },
- { 0x05ba05ba, 0x043a0438, 0x000 },
- { 0x05ba05ba, 0x05ba05ba, 0x000 },
- { 0x05ba05ba, 0x05ba05ba, 0x000 },
- { 0x0002060e, 0x062c0006, 0x000 },
-};
-
-static const u32 RS780_pfp_microcode[] = {
-0xca0400,
-0xa00000,
-0x7e828b,
-0x7c038b,
-0x8001db,
-0x7c038b,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581cb,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0ffe0,
-0x042c08,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255407,
-0x7cd580,
-0x259c07,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d3,
-0xd5c01e,
-0xca0800,
-0x80001a,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xca0c00,
-0x8001db,
-0xd48024,
-0xca0800,
-0x7c00c0,
-0xc81425,
-0xc81824,
-0x7c9488,
-0x7c9880,
-0xc20003,
-0xd40075,
-0x7c744c,
-0x800064,
-0xd4401e,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800062,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c01,
-0xd48060,
-0x94c003,
-0x041001,
-0x041002,
-0xd50025,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001db,
-0xd4c01e,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800000,
-0x062001,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x80009c,
-0xd42013,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x8000b0,
-0x000000,
-0xc41432,
-0xc61843,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800000,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xe4015e,
-0xd4001e,
-0x800000,
-0x062001,
-0xca1800,
-0x0a2001,
-0xd60076,
-0xc40836,
-0x988007,
-0xc61045,
-0x950110,
-0xd4001f,
-0xd46062,
-0x800000,
-0xd42062,
-0xcc3835,
-0xcc1433,
-0x8401de,
-0xd40072,
-0xd5401e,
-0x800000,
-0xee001e,
-0xe2001a,
-0x8401de,
-0xe2001a,
-0xcc104b,
-0xcc0447,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001db,
-0xd4006d,
-0x344401,
-0xcc0c48,
-0x98403a,
-0xcc2c4a,
-0x958004,
-0xcc0449,
-0x8001db,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x840113,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x840113,
-0xcc1003,
-0x988017,
-0x043808,
-0x840113,
-0xcc1003,
-0x988013,
-0x043804,
-0x840113,
-0xcc1003,
-0x988014,
-0xcc104c,
-0x9a8009,
-0xcc144d,
-0x9840dc,
-0xd4006d,
-0xcc1848,
-0xd5001a,
-0xd5401a,
-0x8000ec,
-0xd5801a,
-0x96c0d5,
-0xd4006d,
-0x8001db,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800000,
-0xec007f,
-0x9ac0cc,
-0xd4006d,
-0x8001db,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001db,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809e,
-0xd4006d,
-0x98409c,
-0xd4006e,
-0xcc084c,
-0xcc0c4d,
-0xcc1048,
-0xd4801a,
-0xd4c01a,
-0x800124,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482b6,
-0xca0c00,
-0xd4401e,
-0x800000,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800000,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x98829a,
-0x000000,
-0x8401de,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x99028d,
-0x7c738b,
-0x8401de,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984274,
-0x000000,
-0x800184,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc104e,
-0x990004,
-0xd40073,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x950021,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x042802,
-0x7d8380,
-0xd5a86f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0xc82402,
-0x8001db,
-0xd60076,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800000,
-0xee001e,
-0x800000,
-0xee001f,
-0xd4001f,
-0x800000,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010194,
-0x02019b,
-0x0300b2,
-0x0400a2,
-0x050003,
-0x06003f,
-0x070032,
-0x08014f,
-0x090046,
-0x0a0036,
-0x1001d9,
-0x1700c5,
-0x22015d,
-0x23016c,
-0x2000d7,
-0x240148,
-0x26004d,
-0x27005c,
-0x28008d,
-0x290051,
-0x2a007e,
-0x2b0061,
-0x2f0088,
-0x3200aa,
-0x3401a2,
-0x36006f,
-0x3c0179,
-0x3f0095,
-0x4101af,
-0x440151,
-0x550196,
-0x56019d,
-0x60000b,
-0x610034,
-0x620038,
-0x630038,
-0x640038,
-0x650038,
-0x660038,
-0x670038,
-0x68003a,
-0x690041,
-0x6a0048,
-0x6b0048,
-0x6c0048,
-0x6d0048,
-0x6e0048,
-0x6f0048,
-0x7301d9,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-};
-
-static const u32 RV770_cp_microcode[] = {
-0xcc0003ea,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x80000001,
-0xd040007f,
-0x80000001,
-0xcc400041,
-0x7c40c000,
-0xc0160004,
-0x30d03fff,
-0x7d15000c,
-0xcc110000,
-0x28d8001e,
-0x31980001,
-0x28dc001f,
-0xc8200004,
-0x95c00006,
-0x7c424000,
-0xcc000062,
-0x7e56800c,
-0xcc290000,
-0xc8240004,
-0x7e26000b,
-0x95800006,
-0x7c42c000,
-0xcc000062,
-0x7ed7000c,
-0xcc310000,
-0xc82c0004,
-0x7e2e000c,
-0xcc000062,
-0x31103fff,
-0x80000001,
-0xce110000,
-0x7c40c000,
-0x80000001,
-0xcc400040,
-0x80000001,
-0xcc412257,
-0x7c418000,
-0xcc400045,
-0xcc400048,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xcc400045,
-0xcc400048,
-0x7c40c000,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xcc000045,
-0xcc000048,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x040ca1fd,
-0xc0120001,
-0xcc000045,
-0xcc000048,
-0x7cd0c00c,
-0xcc41225c,
-0xcc41a1fc,
-0xd04d0000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x80000001,
-0xcc41225d,
-0x7c408000,
-0x7c40c000,
-0xc02a0002,
-0x7c410000,
-0x7d29000c,
-0x30940001,
-0x30980006,
-0x309c0300,
-0x29dc0008,
-0x7c420000,
-0x7c424000,
-0x9540000f,
-0xc02e0004,
-0x05f02258,
-0x7f2f000c,
-0xcc310000,
-0xc8280004,
-0xccc12169,
-0xcd01216a,
-0xce81216b,
-0x0db40002,
-0xcc01216c,
-0x9740000e,
-0x0db40000,
-0x8000007b,
-0xc834000a,
-0x0db40002,
-0x97400009,
-0x0db40000,
-0xc02e0004,
-0x05f02258,
-0x7f2f000c,
-0xcc310000,
-0xc8280004,
-0x8000007b,
-0xc834000a,
-0x97400004,
-0x7e028000,
-0x8000007b,
-0xc834000a,
-0x0db40004,
-0x9740ff8c,
-0x00000000,
-0xce01216d,
-0xce41216e,
-0xc8280003,
-0xc834000a,
-0x9b400004,
-0x043c0005,
-0x8400026d,
-0xcc000062,
-0x0df40000,
-0x9740000b,
-0xc82c03e6,
-0xce81a2b7,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c4,
-0x80000001,
-0xcfc1a2d1,
-0x0df40001,
-0x9740000b,
-0xc82c03e7,
-0xce81a2bb,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c5,
-0x80000001,
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-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00010333,
-0x00100004,
-0x00170006,
-0x00210008,
-0x00270028,
-0x00280023,
-0x00290029,
-0x002a0026,
-0x002b0029,
-0x002d0038,
-0x002e003f,
-0x002f004a,
-0x0034004c,
-0x00360030,
-0x003900af,
-0x003a00d0,
-0x003b00e5,
-0x003c00fd,
-0x003d016c,
-0x003f00ad,
-0x00410338,
-0x0043036c,
-0x0044018f,
-0x004500fd,
-0x004601ad,
-0x004701ad,
-0x00480200,
-0x0049020e,
-0x004a0257,
-0x004b0284,
-0x00520261,
-0x00530273,
-0x00540289,
-0x0057029b,
-0x0060029f,
-0x006102ae,
-0x006202b8,
-0x006302c2,
-0x006402cc,
-0x006502d6,
-0x006602e0,
-0x006702ea,
-0x006802f4,
-0x006902f8,
-0x006a02fc,
-0x006b0300,
-0x006c0304,
-0x006d0308,
-0x006e030c,
-0x006f0310,
-0x00700314,
-0x00720386,
-0x0074038c,
-0x0079038a,
-0x007c031e,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-};
-
-static const u32 RV770_pfp_microcode[] = {
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x80000000,
-0xdc030000,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xc818000e,
-0x31980001,
-0x7c424000,
-0x95800252,
-0x7c428000,
-0xc81c001c,
-0xc037c000,
-0x7c40c000,
-0x7c410000,
-0x7cb4800b,
-0xc0360003,
-0x99c00000,
-0xc81c001c,
-0x7cb4800c,
-0x24d40002,
-0x7d654000,
-0xcd400043,
-0xce800043,
-0xcd000043,
-0xcc800040,
-0xce400040,
-0xce800040,
-0xccc00040,
-0xdc3a0000,
-0x9780ffde,
-0xcd000040,
-0x7c40c000,
-0x80000018,
-0x7c410000,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xc818000e,
-0x8000000c,
-0x31980002,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xc818000e,
-0x288c0008,
-0x30cc000f,
-0x34100001,
-0x7d0d0008,
-0x8000000c,
-0x7d91800b,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xcc4003f9,
-0x80000261,
-0xcc4003f8,
-0xc82003f8,
-0xc81c03f9,
-0xc81803fb,
-0xc037ffff,
-0x7c414000,
-0xcf41a29e,
-0x66200020,
-0x7de1c02c,
-0x7d58c008,
-0x7cdcc020,
-0x68d00020,
-0xc0360003,
-0xcc000054,
-0x7cb4800c,
-0x8000006a,
-0xcc800040,
-0x7c418000,
-0xcd81a29e,
-0xcc800040,
-0xcd800040,
-0x80000068,
-0xcc000054,
-0xc019ffff,
-0xcc800040,
-0xcd81a29e,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0xccc1a1fa,
-0xcd01a1f9,
-0xcd41a29d,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xcc400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xcc000054,
-0xcc800040,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0xccc1a1fa,
-0xcd01a1f9,
-0xcd41a29d,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x7c40c000,
-0x30d00001,
-0xccc1a29f,
-0x95000003,
-0x04140001,
-0x04140002,
-0xcd4003fb,
-0xcc800040,
-0x80000000,
-0xccc00040,
-0x7c40c000,
-0xcc800040,
-0xccc1a2a2,
-0x80000000,
-0xccc00040,
-0x7c40c000,
-0x28d4001f,
-0xcc800040,
-0x95400003,
-0x7c410000,
-0xccc00057,
-0x2918001f,
-0xccc00040,
-0x95800003,
-0xcd000040,
-0xcd000058,
-0x80000261,
-0xcc00007f,
-0xc8200017,
-0xc8300022,
-0x9a000006,
-0x0e280001,
-0xc824001e,
-0x0a640001,
-0xd4001240,
-0xce400040,
-0xc036c000,
-0x96800007,
-0x37747900,
-0x041c0001,
-0xcf400040,
-0xcdc00040,
-0xcf0003fa,
-0x7c030000,
-0xca0c0010,
-0x7c410000,
-0x94c00004,
-0x7c414000,
-0xd42002c4,
-0xcde00044,
-0x9b00000b,
-0x7c418000,
-0xcc00004b,
-0xcda00049,
-0xcd200041,
-0xcd600041,
-0xcda00041,
-0x06200001,
-0xce000056,
-0x80000261,
-0xcc00007f,
-0xc8280020,
-0xc82c0021,
-0xcc000063,
-0x7eea4001,
-0x65740020,
-0x7f53402c,
-0x269c0002,
-0x7df5c020,
-0x69f80020,
-0xce80004b,
-0xce600049,
-0xcde00041,
-0xcfa00041,
-0xce600041,
-0x271c0002,
-0x7df5c020,
-0x69f80020,
-0x7db24001,
-0xcf00004b,
-0xce600049,
-0xcde00041,
-0xcfa00041,
-0x800000bd,
-0xce600041,
-0xc8200017,
-0xc8300022,
-0x9a000006,
-0x0e280001,
-0xc824001e,
-0x0a640001,
-0xd4001240,
-0xce400040,
-0xca0c0010,
-0x7c410000,
-0x94c0000b,
-0xc036c000,
-0x96800007,
-0x37747900,
-0x041c0001,
-0xcf400040,
-0xcdc00040,
-0xcf0003fa,
-0x7c030000,
-0x800000b6,
-0x7c414000,
-0xcc000048,
-0x800000ef,
-0x00000000,
-0xc8200017,
-0xc81c0023,
-0x0e240002,
-0x99c00015,
-0x7c418000,
-0x0a200001,
-0xce000056,
-0xd4000440,
-0xcc000040,
-0xc036c000,
-0xca140013,
-0x96400007,
-0x37747900,
-0xcf400040,
-0xcc000040,
-0xc83003fa,
-0x80000104,
-0xcf000022,
-0xcc000022,
-0x9540015d,
-0xcc00007f,
-0xcca00046,
-0x80000000,
-0xcc200046,
-0x80000261,
-0xcc000064,
-0xc8200017,
-0xc810001f,
-0x96000005,
-0x09100001,
-0xd4000440,
-0xcd000040,
-0xcd000022,
-0xcc800040,
-0xd0400040,
-0xc80c0025,
-0x94c0feeb,
-0xc8100008,
-0xcd000040,
-0xd4000fc0,
-0x80000000,
-0xd4000fa2,
-0x7c40c000,
-0x7c410000,
-0xccc003fd,
-0xcd0003fc,
-0xccc00042,
-0xcd000042,
-0x2914001f,
-0x29180010,
-0x31980007,
-0x3b5c0001,
-0x7d76000b,
-0x99800005,
-0x7d5e400b,
-0xcc000042,
-0x80000261,
-0xcc00004d,
-0x29980001,
-0x292c0008,
-0x9980003d,
-0x32ec0001,
-0x96000004,
-0x2930000c,
-0x80000261,
-0xcc000042,
-0x04140010,
-0xcd400042,
-0x33300001,
-0x34280001,
-0x8400015e,
-0xc8140003,
-0x9b40001b,
-0x0438000c,
-0x8400015e,
-0xc8140003,
-0x9b400017,
-0x04380008,
-0x8400015e,
-0xc8140003,
-0x9b400013,
-0x04380004,
-0x8400015e,
-0xc8140003,
-0x9b400015,
-0xc80c03fd,
-0x9a800009,
-0xc81003fc,
-0x9b000118,
-0xcc00004d,
-0x04140010,
-0xccc00042,
-0xcd000042,
-0x80000136,
-0xcd400042,
-0x96c00111,
-0xcc00004d,
-0x80000261,
-0xcc00004e,
-0x9ac00003,
-0xcc00004d,
-0xcc00004e,
-0xdf830000,
-0x80000000,
-0xd80301ff,
-0x9ac00107,
-0xcc00004d,
-0x80000261,
-0xcc00004e,
-0xc8180003,
-0xc81c0003,
-0xc8200003,
-0x7d5d4003,
-0x7da1c003,
-0x7d5d400c,
-0x2a10001f,
-0x299c001f,
-0x7d1d000b,
-0x7d17400b,
-0x88000000,
-0x7e92800b,
-0x96400004,
-0xcc00004e,
-0x80000261,
-0xcc000042,
-0x04380008,
-0xcf800042,
-0xc8080003,
-0xc80c0003,
-0xc8100003,
-0xc8140003,
-0xc8180003,
-0xc81c0003,
-0xc8240003,
-0xc8280003,
-0x29fc001f,
-0x2ab0001f,
-0x7ff3c00b,
-0x28f0001f,
-0x7ff3c00b,
-0x2970001f,
-0x7ff3c00b,
-0x7d888001,
-0x7dccc001,
-0x7e510001,
-0x7e954001,
-0x7c908002,
-0x7cd4c002,
-0x7cbc800b,
-0x9ac00003,
-0x7c8f400b,
-0x38b40001,
-0x9b4000d8,
-0xcc00004d,
-0x9bc000d6,
-0xcc00004e,
-0xc80c03fd,
-0xc81003fc,
-0xccc00042,
-0x8000016f,
-0xcd000042,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xcc400040,
-0xcc400040,
-0xcc400040,
-0x7c40c000,
-0xccc00040,
-0xccc0000d,
-0x80000000,
-0xd0400040,
-0x7c40c000,
-0x7c410000,
-0x65140020,
-0x7d4d402c,
-0x24580002,
-0x7d598020,
-0x7c41c000,
-0xcd800042,
-0x69980020,
-0xcd800042,
-0xcdc00042,
-0xc023c000,
-0x05e40002,
-0x7ca0800b,
-0x26640010,
-0x7ca4800c,
-0xcc800040,
-0xcdc00040,
-0xccc00040,
-0x95c0000e,
-0xcd000040,
-0x09dc0001,
-0xc8280003,
-0x96800008,
-0xce800040,
-0xc834001d,
-0x97400000,
-0xc834001d,
-0x26a80008,
-0x84000264,
-0xcc2b0000,
-0x99c0fff7,
-0x09dc0001,
-0xdc3a0000,
-0x97800004,
-0x7c418000,
-0x800001a3,
-0x25980002,
-0xa0000000,
-0x7d808000,
-0xc818001d,
-0x7c40c000,
-0x64d00008,
-0x95800000,
-0xc818001d,
-0xcc130000,
-0xcc800040,
-0xccc00040,
-0x80000000,
-0xcc400040,
-0xc810001f,
-0x7c40c000,
-0xcc800040,
-0x7cd1400c,
-0xcd400040,
-0x05180001,
-0x80000000,
-0xcd800022,
-0x7c40c000,
-0x64500020,
-0x84000264,
-0xcc000061,
-0x7cd0c02c,
-0xc8200017,
-0xc8d60000,
-0x99400008,
-0x7c438000,
-0xdf830000,
-0xcfa0004f,
-0x84000264,
-0xcc000062,
-0x80000000,
-0xd040007f,
-0x80000261,
-0xcc000062,
-0x84000264,
-0xcc000061,
-0xc8200017,
-0x7c40c000,
-0xc036ff00,
-0xc810000d,
-0xc0303fff,
-0x7cf5400b,
-0x7d51800b,
-0x7d81800f,
-0x99800008,
-0x7cf3800b,
-0xdf830000,
-0xcfa0004f,
-0x84000264,
-0xcc000062,
-0x80000000,
-0xd040007f,
-0x80000261,
-0xcc000062,
-0x84000264,
-0x7c40c000,
-0x28dc0008,
-0x95c00019,
-0x30dc0010,
-0x7c410000,
-0x99c00004,
-0x64540020,
-0x80000209,
-0xc91d0000,
-0x7d15002c,
-0xc91e0000,
-0x7c420000,
-0x7c424000,
-0x7c418000,
-0x7de5c00b,
-0x7de28007,
-0x9a80000e,
-0x41ac0005,
-0x9ac00000,
-0x0aec0001,
-0x30dc0010,
-0x99c00004,
-0x00000000,
-0x8000020c,
-0xc91d0000,
-0x8000020c,
-0xc91e0000,
-0xcc800040,
-0xccc00040,
-0xd0400040,
-0xc80c0025,
-0x94c0fde3,
-0xc8100008,
-0xcd000040,
-0xd4000fc0,
-0x80000000,
-0xd4000fa2,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x7c40c000,
-0x30d00006,
-0x0d100006,
-0x99000007,
-0xc8140015,
-0x99400005,
-0xcc000052,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xccc00040,
-0x80000000,
-0xd0400040,
-0x7c40c000,
-0xcc4d0000,
-0xdc3a0000,
-0x9780fdbc,
-0x04cc0001,
-0x80000243,
-0xcc4d0000,
-0x7c40c000,
-0x7c410000,
-0x29240018,
-0x32640001,
-0x9640000f,
-0xcc800040,
-0x7c414000,
-0x7c418000,
-0x7c41c000,
-0xccc00043,
-0xcd000043,
-0x31dc7fff,
-0xcdc00043,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xcd800040,
-0x80000000,
-0xcdc00040,
-0xccc00040,
-0xcd000040,
-0x80000000,
-0xd0400040,
-0x80000000,
-0xd040007f,
-0xcc00007f,
-0x80000000,
-0xcc00007f,
-0xcc00007f,
-0x88000000,
-0xcc00007f,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00030223,
-0x0004022b,
-0x000500a0,
-0x00020003,
-0x0006003c,
-0x00070027,
-0x00080192,
-0x00090044,
-0x000a002d,
-0x0010025f,
-0x001700f1,
-0x002201d8,
-0x002301e9,
-0x0026004c,
-0x0027005f,
-0x0020011b,
-0x00280093,
-0x0029004f,
-0x002a0084,
-0x002b0065,
-0x002f008e,
-0x003200d9,
-0x00340233,
-0x00360075,
-0x0039010b,
-0x003c01fd,
-0x003f00a0,
-0x00410248,
-0x00440195,
-0x0048019e,
-0x004901c6,
-0x004a01d0,
-0x00550226,
-0x0056022e,
-0x0060000a,
-0x0061002a,
-0x00620030,
-0x00630030,
-0x00640030,
-0x00650030,
-0x00660030,
-0x00670030,
-0x00680037,
-0x0069003f,
-0x006a0047,
-0x006b0047,
-0x006c0047,
-0x006d0047,
-0x006e0047,
-0x006f0047,
-0x00700047,
-0x0073025f,
-0x007b0241,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-};
-
-static const u32 RV730_pfp_microcode[] = {
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x80000000,
-0xdc030000,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xc818000e,
-0x31980001,
-0x7c424000,
-0x9580023a,
-0x7c428000,
-0xc81c001c,
-0xc037c000,
-0x7c40c000,
-0x7c410000,
-0x7cb4800b,
-0xc0360003,
-0x99c00000,
-0xc81c001c,
-0x7cb4800c,
-0x24d40002,
-0x7d654000,
-0xcd400043,
-0xce800043,
-0xcd000043,
-0xcc800040,
-0xce400040,
-0xce800040,
-0xccc00040,
-0xdc3a0000,
-0x9780ffde,
-0xcd000040,
-0x7c40c000,
-0x80000018,
-0x7c410000,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xc818000e,
-0x8000000c,
-0x31980002,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xc818000e,
-0x288c0008,
-0x30cc000f,
-0x34100001,
-0x7d0d0008,
-0x8000000c,
-0x7d91800b,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xcc4003f9,
-0x80000249,
-0xcc4003f8,
-0xc037ffff,
-0x7c414000,
-0xcf41a29e,
-0xc82003f8,
-0xc81c03f9,
-0x66200020,
-0xc81803fb,
-0x7de1c02c,
-0x7d58c008,
-0x7cdcc020,
-0x69100020,
-0xc0360003,
-0xcc000054,
-0x7cb4800c,
-0x80000069,
-0xcc800040,
-0x7c418000,
-0xcd81a29e,
-0xcc800040,
-0x80000067,
-0xcd800040,
-0xc019ffff,
-0xcc800040,
-0xcd81a29e,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0xccc1a1fa,
-0xcd01a1f9,
-0xcd41a29d,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xcc400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xcc000054,
-0xcc800040,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0xccc1a1fa,
-0xcd01a1f9,
-0xcd41a29d,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x7c40c000,
-0x30d00001,
-0xccc1a29f,
-0x95000003,
-0x04140001,
-0x04140002,
-0xcd4003fb,
-0xcc800040,
-0x80000000,
-0xccc00040,
-0x7c40c000,
-0xcc800040,
-0xccc1a2a2,
-0x80000000,
-0xccc00040,
-0x7c40c000,
-0x28d4001f,
-0xcc800040,
-0x95400003,
-0x7c410000,
-0xccc00057,
-0x2918001f,
-0xccc00040,
-0x95800003,
-0xcd000040,
-0xcd000058,
-0x80000249,
-0xcc00007f,
-0xc8200017,
-0xc8300022,
-0x9a000006,
-0x0e280001,
-0xc824001e,
-0x0a640001,
-0xd4001240,
-0xce400040,
-0xc036c000,
-0x96800007,
-0x37747900,
-0x041c0001,
-0xcf400040,
-0xcdc00040,
-0xcf0003fa,
-0x7c030000,
-0xca0c0010,
-0x7c410000,
-0x94c00004,
-0x7c414000,
-0xd42002c4,
-0xcde00044,
-0x9b00000b,
-0x7c418000,
-0xcc00004b,
-0xcda00049,
-0xcd200041,
-0xcd600041,
-0xcda00041,
-0x06200001,
-0xce000056,
-0x80000249,
-0xcc00007f,
-0xc8280020,
-0xc82c0021,
-0xcc000063,
-0x7eea4001,
-0x65740020,
-0x7f53402c,
-0x269c0002,
-0x7df5c020,
-0x69f80020,
-0xce80004b,
-0xce600049,
-0xcde00041,
-0xcfa00041,
-0xce600041,
-0x271c0002,
-0x7df5c020,
-0x69f80020,
-0x7db24001,
-0xcf00004b,
-0xce600049,
-0xcde00041,
-0xcfa00041,
-0x800000bc,
-0xce600041,
-0xc8200017,
-0xc8300022,
-0x9a000006,
-0x0e280001,
-0xc824001e,
-0x0a640001,
-0xd4001240,
-0xce400040,
-0xca0c0010,
-0x7c410000,
-0x94c0000b,
-0xc036c000,
-0x96800007,
-0x37747900,
-0x041c0001,
-0xcf400040,
-0xcdc00040,
-0xcf0003fa,
-0x7c030000,
-0x800000b5,
-0x7c414000,
-0xcc000048,
-0x800000ee,
-0x00000000,
-0xc8200017,
-0xc81c0023,
-0x0e240002,
-0x99c00015,
-0x7c418000,
-0x0a200001,
-0xce000056,
-0xd4000440,
-0xcc000040,
-0xc036c000,
-0xca140013,
-0x96400007,
-0x37747900,
-0xcf400040,
-0xcc000040,
-0xc83003fa,
-0x80000103,
-0xcf000022,
-0xcc000022,
-0x95400146,
-0xcc00007f,
-0xcca00046,
-0x80000000,
-0xcc200046,
-0x80000249,
-0xcc000064,
-0xc8200017,
-0xc810001f,
-0x96000005,
-0x09100001,
-0xd4000440,
-0xcd000040,
-0xcd000022,
-0xcc800040,
-0xd0400040,
-0xc80c0025,
-0x94c0feec,
-0xc8100008,
-0xcd000040,
-0xd4000fc0,
-0x80000000,
-0xd4000fa2,
-0x7c40c000,
-0x7c410000,
-0xccc003fd,
-0xcd0003fc,
-0xccc00042,
-0xcd000042,
-0x2914001f,
-0x29180010,
-0x31980007,
-0x3b5c0001,
-0x7d76000b,
-0x99800005,
-0x7d5e400b,
-0xcc000042,
-0x80000249,
-0xcc00004d,
-0x29980001,
-0x292c0008,
-0x9980003d,
-0x32ec0001,
-0x96000004,
-0x2930000c,
-0x80000249,
-0xcc000042,
-0x04140010,
-0xcd400042,
-0x33300001,
-0x34280001,
-0x8400015d,
-0xc8140003,
-0x9b40001b,
-0x0438000c,
-0x8400015d,
-0xc8140003,
-0x9b400017,
-0x04380008,
-0x8400015d,
-0xc8140003,
-0x9b400013,
-0x04380004,
-0x8400015d,
-0xc8140003,
-0x9b400015,
-0xc80c03fd,
-0x9a800009,
-0xc81003fc,
-0x9b000101,
-0xcc00004d,
-0x04140010,
-0xccc00042,
-0xcd000042,
-0x80000135,
-0xcd400042,
-0x96c000fa,
-0xcc00004d,
-0x80000249,
-0xcc00004e,
-0x9ac00003,
-0xcc00004d,
-0xcc00004e,
-0xdf830000,
-0x80000000,
-0xd80301ff,
-0x9ac000f0,
-0xcc00004d,
-0x80000249,
-0xcc00004e,
-0xc8180003,
-0xc81c0003,
-0xc8200003,
-0x7d5d4003,
-0x7da1c003,
-0x7d5d400c,
-0x2a10001f,
-0x299c001f,
-0x7d1d000b,
-0x7d17400b,
-0x88000000,
-0x7e92800b,
-0x96400004,
-0xcc00004e,
-0x80000249,
-0xcc000042,
-0x04380008,
-0xcf800042,
-0xc8080003,
-0xc80c0003,
-0xc8100003,
-0xc8140003,
-0xc8180003,
-0xc81c0003,
-0xc8240003,
-0xc8280003,
-0x29fc001f,
-0x2ab0001f,
-0x7ff3c00b,
-0x28f0001f,
-0x7ff3c00b,
-0x2970001f,
-0x7ff3c00b,
-0x7d888001,
-0x7dccc001,
-0x7e510001,
-0x7e954001,
-0x7c908002,
-0x7cd4c002,
-0x7cbc800b,
-0x9ac00003,
-0x7c8f400b,
-0x38b40001,
-0x9b4000c1,
-0xcc00004d,
-0x9bc000bf,
-0xcc00004e,
-0xc80c03fd,
-0xc81003fc,
-0xccc00042,
-0x8000016e,
-0xcd000042,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xcc400040,
-0xcc400040,
-0xcc400040,
-0x7c40c000,
-0xccc00040,
-0xccc0000d,
-0x80000000,
-0xd0400040,
-0x7c40c000,
-0x7c410000,
-0x65140020,
-0x7d4d402c,
-0x24580002,
-0x7d598020,
-0x7c41c000,
-0xcd800042,
-0x69980020,
-0xcd800042,
-0xcdc00042,
-0xc023c000,
-0x05e40002,
-0x7ca0800b,
-0x26640010,
-0x7ca4800c,
-0xcc800040,
-0xcdc00040,
-0xccc00040,
-0x95c0000e,
-0xcd000040,
-0x09dc0001,
-0xc8280003,
-0x96800008,
-0xce800040,
-0xc834001d,
-0x97400000,
-0xc834001d,
-0x26a80008,
-0x8400024c,
-0xcc2b0000,
-0x99c0fff7,
-0x09dc0001,
-0xdc3a0000,
-0x97800004,
-0x7c418000,
-0x800001a2,
-0x25980002,
-0xa0000000,
-0x7d808000,
-0xc818001d,
-0x7c40c000,
-0x64d00008,
-0x95800000,
-0xc818001d,
-0xcc130000,
-0xcc800040,
-0xccc00040,
-0x80000000,
-0xcc400040,
-0xc810001f,
-0x7c40c000,
-0xcc800040,
-0x7cd1400c,
-0xcd400040,
-0x05180001,
-0x80000000,
-0xcd800022,
-0x7c40c000,
-0x64500020,
-0x8400024c,
-0xcc000061,
-0x7cd0c02c,
-0xc8200017,
-0xc8d60000,
-0x99400008,
-0x7c438000,
-0xdf830000,
-0xcfa0004f,
-0x8400024c,
-0xcc000062,
-0x80000000,
-0xd040007f,
-0x80000249,
-0xcc000062,
-0x8400024c,
-0xcc000061,
-0xc8200017,
-0x7c40c000,
-0xc036ff00,
-0xc810000d,
-0xc0303fff,
-0x7cf5400b,
-0x7d51800b,
-0x7d81800f,
-0x99800008,
-0x7cf3800b,
-0xdf830000,
-0xcfa0004f,
-0x8400024c,
-0xcc000062,
-0x80000000,
-0xd040007f,
-0x80000249,
-0xcc000062,
-0x8400024c,
-0x7c40c000,
-0x28dc0008,
-0x95c00019,
-0x30dc0010,
-0x7c410000,
-0x99c00004,
-0x64540020,
-0x80000208,
-0xc91d0000,
-0x7d15002c,
-0xc91e0000,
-0x7c420000,
-0x7c424000,
-0x7c418000,
-0x7de5c00b,
-0x7de28007,
-0x9a80000e,
-0x41ac0005,
-0x9ac00000,
-0x0aec0001,
-0x30dc0010,
-0x99c00004,
-0x00000000,
-0x8000020b,
-0xc91d0000,
-0x8000020b,
-0xc91e0000,
-0xcc800040,
-0xccc00040,
-0xd0400040,
-0xc80c0025,
-0x94c0fde4,
-0xc8100008,
-0xcd000040,
-0xd4000fc0,
-0x80000000,
-0xd4000fa2,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x7c40c000,
-0x30d00006,
-0x0d100006,
-0x99000007,
-0xc8140015,
-0x99400005,
-0xcc000052,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xccc00040,
-0x80000000,
-0xd0400040,
-0x7c40c000,
-0xcc4d0000,
-0xdc3a0000,
-0x9780fdbd,
-0x04cc0001,
-0x80000242,
-0xcc4d0000,
-0x80000000,
-0xd040007f,
-0xcc00007f,
-0x80000000,
-0xcc00007f,
-0xcc00007f,
-0x88000000,
-0xcc00007f,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00030222,
-0x0004022a,
-0x0005009f,
-0x00020003,
-0x0006003c,
-0x00070027,
-0x00080191,
-0x00090044,
-0x000a002d,
-0x00100247,
-0x001700f0,
-0x002201d7,
-0x002301e8,
-0x0026004c,
-0x0027005f,
-0x0020011a,
-0x00280092,
-0x0029004f,
-0x002a0083,
-0x002b0064,
-0x002f008d,
-0x003200d8,
-0x00340232,
-0x00360074,
-0x0039010a,
-0x003c01fc,
-0x003f009f,
-0x00410005,
-0x00440194,
-0x0048019d,
-0x004901c5,
-0x004a01cf,
-0x00550225,
-0x0056022d,
-0x0060000a,
-0x0061002a,
-0x00620030,
-0x00630030,
-0x00640030,
-0x00650030,
-0x00660030,
-0x00670030,
-0x00680037,
-0x0069003f,
-0x006a0047,
-0x006b0047,
-0x006c0047,
-0x006d0047,
-0x006e0047,
-0x006f0047,
-0x00700047,
-0x00730247,
-0x007b0240,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-};
-
-static const u32 RV730_cp_microcode[] = {
-0xcc0003ea,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x80000001,
-0xd040007f,
-0x80000001,
-0xcc400041,
-0x7c40c000,
-0xc0160004,
-0x30d03fff,
-0x7d15000c,
-0xcc110000,
-0x28d8001e,
-0x31980001,
-0x28dc001f,
-0xc8200004,
-0x95c00006,
-0x7c424000,
-0xcc000062,
-0x7e56800c,
-0xcc290000,
-0xc8240004,
-0x7e26000b,
-0x95800006,
-0x7c42c000,
-0xcc000062,
-0x7ed7000c,
-0xcc310000,
-0xc82c0004,
-0x7e2e000c,
-0xcc000062,
-0x31103fff,
-0x80000001,
-0xce110000,
-0x7c40c000,
-0x80000001,
-0xcc400040,
-0x80000001,
-0xcc412257,
-0x7c418000,
-0xcc400045,
-0xcc400048,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xcc400045,
-0xcc400048,
-0x7c40c000,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xcc000045,
-0xcc000048,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x040ca1fd,
-0xc0120001,
-0xcc000045,
-0xcc000048,
-0x7cd0c00c,
-0xcc41225c,
-0xcc41a1fc,
-0xd04d0000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x80000001,
-0xcc41225d,
-0x7c408000,
-0x7c40c000,
-0xc02a0002,
-0x7c410000,
-0x7d29000c,
-0x30940001,
-0x30980006,
-0x309c0300,
-0x29dc0008,
-0x7c420000,
-0x7c424000,
-0x9540000f,
-0xc02e0004,
-0x05f02258,
-0x7f2f000c,
-0xcc310000,
-0xc8280004,
-0xccc12169,
-0xcd01216a,
-0xce81216b,
-0x0db40002,
-0xcc01216c,
-0x9740000e,
-0x0db40000,
-0x8000007b,
-0xc834000a,
-0x0db40002,
-0x97400009,
-0x0db40000,
-0xc02e0004,
-0x05f02258,
-0x7f2f000c,
-0xcc310000,
-0xc8280004,
-0x8000007b,
-0xc834000a,
-0x97400004,
-0x7e028000,
-0x8000007b,
-0xc834000a,
-0x0db40004,
-0x9740ff8c,
-0x00000000,
-0xce01216d,
-0xce41216e,
-0xc8280003,
-0xc834000a,
-0x9b400004,
-0x043c0005,
-0x8400026b,
-0xcc000062,
-0x0df40000,
-0x9740000b,
-0xc82c03e6,
-0xce81a2b7,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c4,
-0x80000001,
-0xcfc1a2d1,
-0x0df40001,
-0x9740000b,
-0xc82c03e7,
-0xce81a2bb,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c5,
-0x80000001,
-0xcfc1a2d2,
-0x0df40002,
-0x9740000b,
-0xc82c03e8,
-0xce81a2bf,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c6,
-0x80000001,
-0xcfc1a2d3,
-0xc82c03e9,
-0xce81a2c3,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c7,
-0x80000001,
-0xcfc1a2d4,
-0x80000001,
-0xcc400042,
-0x7c40c000,
-0x7c410000,
-0x2914001d,
-0x31540001,
-0x9940000c,
-0x31181000,
-0xc81c0011,
-0x95c00000,
-0xc81c0011,
-0xccc12100,
-0xcd012101,
-0xccc12102,
-0xcd012103,
-0x04180004,
-0x8000037c,
-0xcd81a2a4,
-0xc02a0004,
-0x95800008,
-0x36a821a3,
-0xcc290000,
-0xc8280004,
-0xc81c0011,
-0x0de40040,
-0x9640ffff,
-0xc81c0011,
-0xccc12170,
-0xcd012171,
-0xc8200012,
-0x96000000,
-0xc8200012,
-0x8000037c,
-0xcc000064,
-0x7c40c000,
-0x7c410000,
-0xcc000045,
-0xcc000048,
-0x40d40003,
-0xcd41225c,
-0xcd01a1fc,
-0xc01a0001,
-0x041ca1fd,
-0x7dd9c00c,
-0x7c420000,
-0x08cc0001,
-0x06240001,
-0x06280002,
-0xce1d0000,
-0xce5d0000,
-0x98c0fffa,
-0xce9d0000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x7c40c000,
-0x30d00001,
-0x28cc0001,
-0x7c414000,
-0x95000006,
-0x7c418000,
-0xcd41216d,
-0xcd81216e,
-0x800000f2,
-0xc81c0003,
-0xc0220004,
-0x7e16000c,
-0xcc210000,
-0xc81c0004,
-0x7c424000,
-0x98c00004,
-0x7c428000,
-0x80000001,
-0xcde50000,
-0xce412169,
-0xce81216a,
-0xcdc1216b,
-0x80000001,
-0xcc01216c,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0x7c41c000,
-0x28a40008,
-0x326400ff,
-0x0e68003c,
-0x9680000a,
-0x7c020000,
-0x7c420000,
-0x1e300003,
-0xcc00006a,
-0x9b000003,
-0x42200005,
-0x04200040,
-0x8000010f,
-0x7c024000,
-0x7e024000,
-0x9a400000,
-0x0a640001,
-0x30ec0010,
-0x9ac0000a,
-0xcc000062,
-0xc02a0004,
-0xc82c0021,
-0x7e92800c,
-0xcc000041,
-0xcc290000,
-0xcec00021,
-0x8000011f,
-0xc8300004,
-0xcd01216d,
-0xcd41216e,
-0xc8300003,
-0x7f1f000b,
-0x30f40007,
-0x27780001,
-0x9740002a,
-0x07b80124,
-0x9f800000,
-0x00000000,
-0x80000134,
-0x7f1b8004,
-0x80000138,
-0x7f1b8005,
-0x8000013c,
-0x7f1b8002,
-0x80000140,
-0x7f1b8003,
-0x80000144,
-0x7f1b8007,
-0x80000148,
-0x7f1b8006,
-0x8000014d,
-0x28a40008,
-0x9b800019,
-0x28a40008,
-0x8000015d,
-0x326400ff,
-0x9b800015,
-0x28a40008,
-0x8000015d,
-0x326400ff,
-0x9b800011,
-0x28a40008,
-0x8000015d,
-0x326400ff,
-0x9b80000d,
-0x28a40008,
-0x8000015d,
-0x326400ff,
-0x9b800009,
-0x28a40008,
-0x8000015d,
-0x326400ff,
-0x9b800005,
-0x28a40008,
-0x8000015d,
-0x326400ff,
-0x28a40008,
-0x326400ff,
-0x0e68003c,
-0x9a80feb2,
-0x28ec0008,
-0x7c434000,
-0x7c438000,
-0x7c43c000,
-0x96c00007,
-0xcc000062,
-0xcf412169,
-0xcf81216a,
-0xcfc1216b,
-0x80000001,
-0xcc01216c,
-0x80000001,
-0xcff50000,
-0xcc00006b,
-0x8400037f,
-0x0e68003c,
-0x9a800004,
-0xc8280015,
-0x80000001,
-0xd040007f,
-0x9680ffab,
-0x7e024000,
-0x84000239,
-0xc00e0002,
-0xcc000041,
-0x80000237,
-0xccc1304a,
-0x7c40c000,
-0x7c410000,
-0xc01e0001,
-0x29240012,
-0xc0220002,
-0x96400005,
-0xc0260004,
-0xc027fffb,
-0x7d25000b,
-0xc0260000,
-0x7dd2800b,
-0x7e12c00b,
-0x7d25000c,
-0x7c414000,
-0x7c418000,
-0xccc12169,
-0x9a80000a,
-0xcd01216a,
-0xcd41216b,
-0x96c0fe83,
-0xcd81216c,
-0xc8300018,
-0x97000000,
-0xc8300018,
-0x80000001,
-0xcc000018,
-0x8400037f,
-0xcc00007f,
-0xc8140013,
-0xc8180014,
-0xcd41216b,
-0x96c0fe77,
-0xcd81216c,
-0x80000181,
-0xc8300018,
-0xc80c0008,
-0x98c00000,
-0xc80c0008,
-0x7c410000,
-0x95000002,
-0x00000000,
-0x7c414000,
-0xc8200009,
-0xcc400043,
-0xce01a1f4,
-0xcc400044,
-0xc00e8000,
-0x7c424000,
-0x7c428000,
-0x2aac001f,
-0x96c0fe64,
-0xc035f000,
-0xce4003e2,
-0x32780003,
-0x267c0008,
-0x7ff7c00b,
-0x7ffbc00c,
-0x2a780018,
-0xcfc003e3,
-0xcf8003e4,
-0x26b00002,
-0x7f3f0000,
-0xcf0003e5,
-0x8000031d,
-0x7c80c000,
-0x7c40c000,
-0x28d00008,
-0x3110000f,
-0x9500000f,
-0x25280001,
-0x06a801b2,
-0x9e800000,
-0x00000000,
-0x800001d3,
-0xc0120800,
-0x800001e1,
-0xc814000f,
-0x800001e8,
-0xc8140010,
-0x800001ef,
-0xccc1a2a4,
-0x800001f8,
-0xc8140011,
-0x30d0003f,
-0x0d280015,
-0x9a800012,
-0x0d28001e,
-0x9a80001e,
-0x0d280020,
-0x9a800023,
-0x0d24000f,
-0x0d280010,
-0x7e6a800c,
-0x9a800026,
-0x0d200004,
-0x0d240014,
-0x0d280028,
-0x7e62400c,
-0x7ea6800c,
-0x9a80002a,
-0xc8140011,
-0x80000001,
-0xccc1a2a4,
-0xc0120800,
-0x7c414000,
-0x7d0cc00c,
-0xc0120008,
-0x29580003,
-0x295c000c,
-0x7c420000,
-0x7dd1c00b,
-0x26200014,
-0x7e1e400c,
-0x7e4e800c,
-0xce81a2a4,
-0x80000001,
-0xcd81a1fe,
-0xc814000f,
-0x0410210e,
-0x95400000,
-0xc814000f,
-0xd0510000,
-0x80000001,
-0xccc1a2a4,
-0xc8140010,
-0x04102108,
-0x95400000,
-0xc8140010,
-0xd0510000,
-0x80000001,
-0xccc1a2a4,
-0xccc1a2a4,
-0x04100001,
-0xcd000019,
-0x8400037f,
-0xcc00007f,
-0xc8100019,
-0x99000000,
-0xc8100019,
-0x80000002,
-0x7c408000,
-0x04102100,
-0x95400000,
-0xc8140011,
-0xd0510000,
-0x8000037c,
-0xccc1a2a4,
-0x7c40c000,
-0xcc40000d,
-0x94c0fe01,
-0xcc40000e,
-0x7c410000,
-0x95000005,
-0x08cc0001,
-0xc8140005,
-0x99400014,
-0x00000000,
-0x98c0fffb,
-0x7c410000,
-0x80000002,
-0x7d008000,
-0xc8140005,
-0x7c40c000,
-0x9940000c,
-0xc818000c,
-0x7c410000,
-0x9580fdf0,
-0xc820000e,
-0xc81c000d,
-0x66200020,
-0x7e1e002c,
-0x25240002,
-0x7e624020,
-0x80000001,
-0xcce60000,
-0x7c410000,
-0xcc00006c,
-0xcc00006d,
-0xc818001f,
-0xc81c001e,
-0x65980020,
-0x7dd9c02c,
-0x7cd4c00c,
-0xccde0000,
-0x45dc0004,
-0xc8280017,
-0x9680000f,
-0xc00e0001,
-0x28680008,
-0x2aac0016,
-0x32a800ff,
-0x0eb00049,
-0x7f2f000b,
-0x97000006,
-0x00000000,
-0xc8140005,
-0x7c40c000,
-0x80000221,
-0x7c410000,
-0x80000224,
-0xd040007f,
-0x84000239,
-0xcc000041,
-0xccc1304a,
-0x94000000,
-0xc83c001a,
-0x043c0005,
-0xcfc1a2a4,
-0xc0361f90,
-0xc0387fff,
-0x7c03c010,
-0x7f7b400c,
-0xcf41217c,
-0xcfc1217d,
-0xcc01217e,
-0xc03a0004,
-0x0434217f,
-0x7f7b400c,
-0xcc350000,
-0xc83c0004,
-0x2bfc001f,
-0x04380020,
-0x97c00005,
-0xcc000062,
-0x9b800000,
-0x0bb80001,
-0x80000245,
-0xcc000071,
-0xcc01a1f4,
-0x04380016,
-0xc0360002,
-0xcf81a2a4,
-0x88000000,
-0xcf412010,
-0x7c40c000,
-0x28d0001c,
-0x95000005,
-0x04d40001,
-0xcd400065,
-0x80000001,
-0xcd400068,
-0x09540002,
-0x80000001,
-0xcd400066,
-0x8400026a,
-0xc81803ea,
-0x7c40c000,
-0x9980fd9f,
-0xc8140016,
-0x08d00001,
-0x9940002b,
-0xcd000068,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x043c0005,
-0xcfc1a2a4,
-0xcc01a1f4,
-0x8400037f,
-0xcc000046,
-0x88000000,
-0xcc00007f,
-0x8400027c,
-0xc81803ea,
-0x7c40c000,
-0x9980fd8d,
-0xc8140016,
-0x08d00001,
-0x99400019,
-0xcd000068,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x043c0022,
-0xcfc1a2a4,
-0x8400037f,
-0xcc000047,
-0x88000000,
-0xcc00007f,
-0xc8100016,
-0x9900000d,
-0xcc400067,
-0x80000002,
-0x7c408000,
-0xc81803ea,
-0x9980fd79,
-0x7c40c000,
-0x94c00003,
-0xc8100016,
-0x99000004,
-0xccc00068,
-0x80000002,
-0x7c408000,
-0x84000239,
-0xc0148000,
-0xcc000041,
-0xcd41304a,
-0xc0148000,
-0x99000000,
-0xc8100016,
-0x80000002,
-0x7c408000,
-0xc0120001,
-0x7c51400c,
-0x80000001,
-0xd0550000,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0x291c001f,
-0xccc0004a,
-0xcd00004b,
-0x95c00003,
-0xc01c8000,
-0xcdc12010,
-0xdd830000,
-0x055c2000,
-0xcc000062,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc0004c,
-0xcd00004d,
-0xdd830000,
-0x055ca000,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc0004e,
-0xcd00004f,
-0xdd830000,
-0x055cc000,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00050,
-0xcd000051,
-0xdd830000,
-0x055cf8e0,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00052,
-0xcd000053,
-0xdd830000,
-0x055cf880,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00054,
-0xcd000055,
-0xdd830000,
-0x055ce000,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00056,
-0xcd000057,
-0xdd830000,
-0x055cf000,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00058,
-0xcd000059,
-0xdd830000,
-0x055cf3fc,
-0x80000001,
-0xd81f4100,
-0xd0432000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043a000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043c000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043f8e0,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043f880,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043e000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043f000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043f3fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xc81403e0,
-0xcc430000,
-0xcc430000,
-0xcc430000,
-0x7d45c000,
-0xcdc30000,
-0xd0430000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x7c40c000,
-0xc81003e2,
-0xc81403e5,
-0xc81803e3,
-0xc81c03e4,
-0xcd812169,
-0xcdc1216a,
-0xccc1216b,
-0xcc01216c,
-0x04200004,
-0x7da18000,
-0x7d964002,
-0x9640fcd9,
-0xcd8003e3,
-0x31280003,
-0xc02df000,
-0x25180008,
-0x7dad800b,
-0x7da9800c,
-0x80000001,
-0xcd8003e3,
-0x308cffff,
-0xd04d0000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xc8140020,
-0x15580002,
-0x9580ffff,
-0xc8140020,
-0xcc00006e,
-0xcc412180,
-0x7c40c000,
-0xccc1218d,
-0xcc412181,
-0x28d0001f,
-0x34588000,
-0xcd81218c,
-0x9500fcbf,
-0xcc412182,
-0xc8140020,
-0x9940ffff,
-0xc8140020,
-0x80000002,
-0x7c408000,
-0x7c40c000,
-0x28d00018,
-0x31100001,
-0xc0160080,
-0x95000003,
-0xc02a0004,
-0x7cd4c00c,
-0xccc1217c,
-0xcc41217d,
-0xcc41217e,
-0x7c418000,
-0x1db00003,
-0x36a0217f,
-0x9b000003,
-0x419c0005,
-0x041c0040,
-0x99c00000,
-0x09dc0001,
-0xcc210000,
-0xc8240004,
-0x2a6c001f,
-0x419c0005,
-0x9ac0fffa,
-0xcc800062,
-0x80000002,
-0x7c408000,
-0x7c40c000,
-0x04d403e6,
-0x80000001,
-0xcc540000,
-0x8000037c,
-0xcc4003ea,
-0xc01c8000,
-0x044ca000,
-0xcdc12010,
-0x7c410000,
-0xc8140009,
-0x04180000,
-0x041c0008,
-0xcd800071,
-0x09dc0001,
-0x05980001,
-0xcd0d0000,
-0x99c0fffc,
-0xcc800062,
-0x8000037c,
-0xcd400071,
-0xc00e0100,
-0xcc000041,
-0xccc1304a,
-0xc83c007f,
-0xcc00007f,
-0x80000001,
-0xcc00007f,
-0xcc00007f,
-0x88000000,
-0xcc00007f,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00010331,
-0x00100004,
-0x00170006,
-0x00210008,
-0x00270028,
-0x00280023,
-0x00290029,
-0x002a0026,
-0x002b0029,
-0x002d0038,
-0x002e003f,
-0x002f004a,
-0x0034004c,
-0x00360030,
-0x003900af,
-0x003a00cf,
-0x003b00e4,
-0x003c00fc,
-0x003d016b,
-0x003f00ad,
-0x00410336,
-0x00430349,
-0x0044018e,
-0x004500fc,
-0x004601ac,
-0x004701ac,
-0x004801fe,
-0x0049020c,
-0x004a0255,
-0x004b0282,
-0x0052025f,
-0x00530271,
-0x00540287,
-0x00570299,
-0x0060029d,
-0x006102ac,
-0x006202b6,
-0x006302c0,
-0x006402ca,
-0x006502d4,
-0x006602de,
-0x006702e8,
-0x006802f2,
-0x006902f6,
-0x006a02fa,
-0x006b02fe,
-0x006c0302,
-0x006d0306,
-0x006e030a,
-0x006f030e,
-0x00700312,
-0x00720363,
-0x00740369,
-0x00790367,
-0x007c031c,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-};
-
-static const u32 RV710_pfp_microcode[] = {
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x80000000,
-0xdc030000,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xc818000e,
-0x31980001,
-0x7c424000,
-0x9580023a,
-0x7c428000,
-0xc81c001c,
-0xc037c000,
-0x7c40c000,
-0x7c410000,
-0x7cb4800b,
-0xc0360003,
-0x99c00000,
-0xc81c001c,
-0x7cb4800c,
-0x24d40002,
-0x7d654000,
-0xcd400043,
-0xce800043,
-0xcd000043,
-0xcc800040,
-0xce400040,
-0xce800040,
-0xccc00040,
-0xdc3a0000,
-0x9780ffde,
-0xcd000040,
-0x7c40c000,
-0x80000018,
-0x7c410000,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xc818000e,
-0x8000000c,
-0x31980002,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xc818000e,
-0x288c0008,
-0x30cc000f,
-0x34100001,
-0x7d0d0008,
-0x8000000c,
-0x7d91800b,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xcc4003f9,
-0x80000249,
-0xcc4003f8,
-0xc037ffff,
-0x7c414000,
-0xcf41a29e,
-0xc82003f8,
-0xc81c03f9,
-0x66200020,
-0xc81803fb,
-0x7de1c02c,
-0x7d58c008,
-0x7cdcc020,
-0x69100020,
-0xc0360003,
-0xcc000054,
-0x7cb4800c,
-0x80000069,
-0xcc800040,
-0x7c418000,
-0xcd81a29e,
-0xcc800040,
-0x80000067,
-0xcd800040,
-0xc019ffff,
-0xcc800040,
-0xcd81a29e,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0xccc1a1fa,
-0xcd01a1f9,
-0xcd41a29d,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xcc400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xcc000054,
-0xcc800040,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0xccc1a1fa,
-0xcd01a1f9,
-0xcd41a29d,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x7c40c000,
-0x30d00001,
-0xccc1a29f,
-0x95000003,
-0x04140001,
-0x04140002,
-0xcd4003fb,
-0xcc800040,
-0x80000000,
-0xccc00040,
-0x7c40c000,
-0xcc800040,
-0xccc1a2a2,
-0x80000000,
-0xccc00040,
-0x7c40c000,
-0x28d4001f,
-0xcc800040,
-0x95400003,
-0x7c410000,
-0xccc00057,
-0x2918001f,
-0xccc00040,
-0x95800003,
-0xcd000040,
-0xcd000058,
-0x80000249,
-0xcc00007f,
-0xc8200017,
-0xc8300022,
-0x9a000006,
-0x0e280001,
-0xc824001e,
-0x0a640001,
-0xd4001240,
-0xce400040,
-0xc036c000,
-0x96800007,
-0x37747900,
-0x041c0001,
-0xcf400040,
-0xcdc00040,
-0xcf0003fa,
-0x7c030000,
-0xca0c0010,
-0x7c410000,
-0x94c00004,
-0x7c414000,
-0xd42002c4,
-0xcde00044,
-0x9b00000b,
-0x7c418000,
-0xcc00004b,
-0xcda00049,
-0xcd200041,
-0xcd600041,
-0xcda00041,
-0x06200001,
-0xce000056,
-0x80000249,
-0xcc00007f,
-0xc8280020,
-0xc82c0021,
-0xcc000063,
-0x7eea4001,
-0x65740020,
-0x7f53402c,
-0x269c0002,
-0x7df5c020,
-0x69f80020,
-0xce80004b,
-0xce600049,
-0xcde00041,
-0xcfa00041,
-0xce600041,
-0x271c0002,
-0x7df5c020,
-0x69f80020,
-0x7db24001,
-0xcf00004b,
-0xce600049,
-0xcde00041,
-0xcfa00041,
-0x800000bc,
-0xce600041,
-0xc8200017,
-0xc8300022,
-0x9a000006,
-0x0e280001,
-0xc824001e,
-0x0a640001,
-0xd4001240,
-0xce400040,
-0xca0c0010,
-0x7c410000,
-0x94c0000b,
-0xc036c000,
-0x96800007,
-0x37747900,
-0x041c0001,
-0xcf400040,
-0xcdc00040,
-0xcf0003fa,
-0x7c030000,
-0x800000b5,
-0x7c414000,
-0xcc000048,
-0x800000ee,
-0x00000000,
-0xc8200017,
-0xc81c0023,
-0x0e240002,
-0x99c00015,
-0x7c418000,
-0x0a200001,
-0xce000056,
-0xd4000440,
-0xcc000040,
-0xc036c000,
-0xca140013,
-0x96400007,
-0x37747900,
-0xcf400040,
-0xcc000040,
-0xc83003fa,
-0x80000103,
-0xcf000022,
-0xcc000022,
-0x95400146,
-0xcc00007f,
-0xcca00046,
-0x80000000,
-0xcc200046,
-0x80000249,
-0xcc000064,
-0xc8200017,
-0xc810001f,
-0x96000005,
-0x09100001,
-0xd4000440,
-0xcd000040,
-0xcd000022,
-0xcc800040,
-0xd0400040,
-0xc80c0025,
-0x94c0feec,
-0xc8100008,
-0xcd000040,
-0xd4000fc0,
-0x80000000,
-0xd4000fa2,
-0x7c40c000,
-0x7c410000,
-0xccc003fd,
-0xcd0003fc,
-0xccc00042,
-0xcd000042,
-0x2914001f,
-0x29180010,
-0x31980007,
-0x3b5c0001,
-0x7d76000b,
-0x99800005,
-0x7d5e400b,
-0xcc000042,
-0x80000249,
-0xcc00004d,
-0x29980001,
-0x292c0008,
-0x9980003d,
-0x32ec0001,
-0x96000004,
-0x2930000c,
-0x80000249,
-0xcc000042,
-0x04140010,
-0xcd400042,
-0x33300001,
-0x34280001,
-0x8400015d,
-0xc8140003,
-0x9b40001b,
-0x0438000c,
-0x8400015d,
-0xc8140003,
-0x9b400017,
-0x04380008,
-0x8400015d,
-0xc8140003,
-0x9b400013,
-0x04380004,
-0x8400015d,
-0xc8140003,
-0x9b400015,
-0xc80c03fd,
-0x9a800009,
-0xc81003fc,
-0x9b000101,
-0xcc00004d,
-0x04140010,
-0xccc00042,
-0xcd000042,
-0x80000135,
-0xcd400042,
-0x96c000fa,
-0xcc00004d,
-0x80000249,
-0xcc00004e,
-0x9ac00003,
-0xcc00004d,
-0xcc00004e,
-0xdf830000,
-0x80000000,
-0xd80301ff,
-0x9ac000f0,
-0xcc00004d,
-0x80000249,
-0xcc00004e,
-0xc8180003,
-0xc81c0003,
-0xc8200003,
-0x7d5d4003,
-0x7da1c003,
-0x7d5d400c,
-0x2a10001f,
-0x299c001f,
-0x7d1d000b,
-0x7d17400b,
-0x88000000,
-0x7e92800b,
-0x96400004,
-0xcc00004e,
-0x80000249,
-0xcc000042,
-0x04380008,
-0xcf800042,
-0xc8080003,
-0xc80c0003,
-0xc8100003,
-0xc8140003,
-0xc8180003,
-0xc81c0003,
-0xc8240003,
-0xc8280003,
-0x29fc001f,
-0x2ab0001f,
-0x7ff3c00b,
-0x28f0001f,
-0x7ff3c00b,
-0x2970001f,
-0x7ff3c00b,
-0x7d888001,
-0x7dccc001,
-0x7e510001,
-0x7e954001,
-0x7c908002,
-0x7cd4c002,
-0x7cbc800b,
-0x9ac00003,
-0x7c8f400b,
-0x38b40001,
-0x9b4000c1,
-0xcc00004d,
-0x9bc000bf,
-0xcc00004e,
-0xc80c03fd,
-0xc81003fc,
-0xccc00042,
-0x8000016e,
-0xcd000042,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xcc400040,
-0xcc400040,
-0xcc400040,
-0x7c40c000,
-0xccc00040,
-0xccc0000d,
-0x80000000,
-0xd0400040,
-0x7c40c000,
-0x7c410000,
-0x65140020,
-0x7d4d402c,
-0x24580002,
-0x7d598020,
-0x7c41c000,
-0xcd800042,
-0x69980020,
-0xcd800042,
-0xcdc00042,
-0xc023c000,
-0x05e40002,
-0x7ca0800b,
-0x26640010,
-0x7ca4800c,
-0xcc800040,
-0xcdc00040,
-0xccc00040,
-0x95c0000e,
-0xcd000040,
-0x09dc0001,
-0xc8280003,
-0x96800008,
-0xce800040,
-0xc834001d,
-0x97400000,
-0xc834001d,
-0x26a80008,
-0x8400024c,
-0xcc2b0000,
-0x99c0fff7,
-0x09dc0001,
-0xdc3a0000,
-0x97800004,
-0x7c418000,
-0x800001a2,
-0x25980002,
-0xa0000000,
-0x7d808000,
-0xc818001d,
-0x7c40c000,
-0x64d00008,
-0x95800000,
-0xc818001d,
-0xcc130000,
-0xcc800040,
-0xccc00040,
-0x80000000,
-0xcc400040,
-0xc810001f,
-0x7c40c000,
-0xcc800040,
-0x7cd1400c,
-0xcd400040,
-0x05180001,
-0x80000000,
-0xcd800022,
-0x7c40c000,
-0x64500020,
-0x8400024c,
-0xcc000061,
-0x7cd0c02c,
-0xc8200017,
-0xc8d60000,
-0x99400008,
-0x7c438000,
-0xdf830000,
-0xcfa0004f,
-0x8400024c,
-0xcc000062,
-0x80000000,
-0xd040007f,
-0x80000249,
-0xcc000062,
-0x8400024c,
-0xcc000061,
-0xc8200017,
-0x7c40c000,
-0xc036ff00,
-0xc810000d,
-0xc0303fff,
-0x7cf5400b,
-0x7d51800b,
-0x7d81800f,
-0x99800008,
-0x7cf3800b,
-0xdf830000,
-0xcfa0004f,
-0x8400024c,
-0xcc000062,
-0x80000000,
-0xd040007f,
-0x80000249,
-0xcc000062,
-0x8400024c,
-0x7c40c000,
-0x28dc0008,
-0x95c00019,
-0x30dc0010,
-0x7c410000,
-0x99c00004,
-0x64540020,
-0x80000208,
-0xc91d0000,
-0x7d15002c,
-0xc91e0000,
-0x7c420000,
-0x7c424000,
-0x7c418000,
-0x7de5c00b,
-0x7de28007,
-0x9a80000e,
-0x41ac0005,
-0x9ac00000,
-0x0aec0001,
-0x30dc0010,
-0x99c00004,
-0x00000000,
-0x8000020b,
-0xc91d0000,
-0x8000020b,
-0xc91e0000,
-0xcc800040,
-0xccc00040,
-0xd0400040,
-0xc80c0025,
-0x94c0fde4,
-0xc8100008,
-0xcd000040,
-0xd4000fc0,
-0x80000000,
-0xd4000fa2,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x7c40c000,
-0x30d00006,
-0x0d100006,
-0x99000007,
-0xc8140015,
-0x99400005,
-0xcc000052,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xccc00040,
-0x80000000,
-0xd0400040,
-0x7c40c000,
-0xcc4d0000,
-0xdc3a0000,
-0x9780fdbd,
-0x04cc0001,
-0x80000242,
-0xcc4d0000,
-0x80000000,
-0xd040007f,
-0xcc00007f,
-0x80000000,
-0xcc00007f,
-0xcc00007f,
-0x88000000,
-0xcc00007f,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00030222,
-0x0004022a,
-0x0005009f,
-0x00020003,
-0x0006003c,
-0x00070027,
-0x00080191,
-0x00090044,
-0x000a002d,
-0x00100247,
-0x001700f0,
-0x002201d7,
-0x002301e8,
-0x0026004c,
-0x0027005f,
-0x0020011a,
-0x00280092,
-0x0029004f,
-0x002a0083,
-0x002b0064,
-0x002f008d,
-0x003200d8,
-0x00340232,
-0x00360074,
-0x0039010a,
-0x003c01fc,
-0x003f009f,
-0x00410005,
-0x00440194,
-0x0048019d,
-0x004901c5,
-0x004a01cf,
-0x00550225,
-0x0056022d,
-0x0060000a,
-0x0061002a,
-0x00620030,
-0x00630030,
-0x00640030,
-0x00650030,
-0x00660030,
-0x00670030,
-0x00680037,
-0x0069003f,
-0x006a0047,
-0x006b0047,
-0x006c0047,
-0x006d0047,
-0x006e0047,
-0x006f0047,
-0x00700047,
-0x00730247,
-0x007b0240,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-};
-
-static const u32 RV710_cp_microcode[] = {
-0xcc0003ea,
-0x04080003,
-0xcc800043,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x80000003,
-0xd040007f,
-0x80000003,
-0xcc400041,
-0x7c40c000,
-0xc0160004,
-0x30d03fff,
-0x7d15000c,
-0xcc110000,
-0x28d8001e,
-0x31980001,
-0x28dc001f,
-0xc8200004,
-0x95c00006,
-0x7c424000,
-0xcc000062,
-0x7e56800c,
-0xcc290000,
-0xc8240004,
-0x7e26000b,
-0x95800006,
-0x7c42c000,
-0xcc000062,
-0x7ed7000c,
-0xcc310000,
-0xc82c0004,
-0x7e2e000c,
-0xcc000062,
-0x31103fff,
-0x80000003,
-0xce110000,
-0x7c40c000,
-0x80000003,
-0xcc400040,
-0x80000003,
-0xcc412257,
-0x7c418000,
-0xcc400045,
-0xcc400048,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xcc400045,
-0xcc400048,
-0x7c40c000,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xcc000045,
-0xcc000048,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x040ca1fd,
-0xc0120001,
-0xcc000045,
-0xcc000048,
-0x7cd0c00c,
-0xcc41225c,
-0xcc41a1fc,
-0xd04d0000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x80000003,
-0xcc41225d,
-0x7c408000,
-0x7c40c000,
-0xc02a0002,
-0x7c410000,
-0x7d29000c,
-0x30940001,
-0x30980006,
-0x309c0300,
-0x29dc0008,
-0x7c420000,
-0x7c424000,
-0x9540000f,
-0xc02e0004,
-0x05f02258,
-0x7f2f000c,
-0xcc310000,
-0xc8280004,
-0xccc12169,
-0xcd01216a,
-0xce81216b,
-0x0db40002,
-0xcc01216c,
-0x9740000e,
-0x0db40000,
-0x8000007d,
-0xc834000a,
-0x0db40002,
-0x97400009,
-0x0db40000,
-0xc02e0004,
-0x05f02258,
-0x7f2f000c,
-0xcc310000,
-0xc8280004,
-0x8000007d,
-0xc834000a,
-0x97400004,
-0x7e028000,
-0x8000007d,
-0xc834000a,
-0x0db40004,
-0x9740ff8c,
-0x00000000,
-0xce01216d,
-0xce41216e,
-0xc8280003,
-0xc834000a,
-0x9b400004,
-0x043c0005,
-0x8400026d,
-0xcc000062,
-0x0df40000,
-0x9740000b,
-0xc82c03e6,
-0xce81a2b7,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c4,
-0x80000003,
-0xcfc1a2d1,
-0x0df40001,
-0x9740000b,
-0xc82c03e7,
-0xce81a2bb,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c5,
-0x80000003,
-0xcfc1a2d2,
-0x0df40002,
-0x9740000b,
-0xc82c03e8,
-0xce81a2bf,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c6,
-0x80000003,
-0xcfc1a2d3,
-0xc82c03e9,
-0xce81a2c3,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c7,
-0x80000003,
-0xcfc1a2d4,
-0x80000003,
-0xcc400042,
-0x7c40c000,
-0x7c410000,
-0x2914001d,
-0x31540001,
-0x9940000c,
-0x31181000,
-0xc81c0011,
-0x95c00000,
-0xc81c0011,
-0xccc12100,
-0xcd012101,
-0xccc12102,
-0xcd012103,
-0x04180004,
-0x8000037e,
-0xcd81a2a4,
-0xc02a0004,
-0x95800008,
-0x36a821a3,
-0xcc290000,
-0xc8280004,
-0xc81c0011,
-0x0de40040,
-0x9640ffff,
-0xc81c0011,
-0xccc12170,
-0xcd012171,
-0xc8200012,
-0x96000000,
-0xc8200012,
-0x8000037e,
-0xcc000064,
-0x7c40c000,
-0x7c410000,
-0xcc000045,
-0xcc000048,
-0x40d40003,
-0xcd41225c,
-0xcd01a1fc,
-0xc01a0001,
-0x041ca1fd,
-0x7dd9c00c,
-0x7c420000,
-0x08cc0001,
-0x06240001,
-0x06280002,
-0xce1d0000,
-0xce5d0000,
-0x98c0fffa,
-0xce9d0000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x7c40c000,
-0x30d00001,
-0x28cc0001,
-0x7c414000,
-0x95000006,
-0x7c418000,
-0xcd41216d,
-0xcd81216e,
-0x800000f4,
-0xc81c0003,
-0xc0220004,
-0x7e16000c,
-0xcc210000,
-0xc81c0004,
-0x7c424000,
-0x98c00004,
-0x7c428000,
-0x80000003,
-0xcde50000,
-0xce412169,
-0xce81216a,
-0xcdc1216b,
-0x80000003,
-0xcc01216c,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0x7c41c000,
-0x28a40008,
-0x326400ff,
-0x0e68003c,
-0x9680000a,
-0x7c020000,
-0x7c420000,
-0x1e300003,
-0xcc00006a,
-0x9b000003,
-0x42200005,
-0x04200040,
-0x80000111,
-0x7c024000,
-0x7e024000,
-0x9a400000,
-0x0a640001,
-0x30ec0010,
-0x9ac0000a,
-0xcc000062,
-0xc02a0004,
-0xc82c0021,
-0x7e92800c,
-0xcc000041,
-0xcc290000,
-0xcec00021,
-0x80000121,
-0xc8300004,
-0xcd01216d,
-0xcd41216e,
-0xc8300003,
-0x7f1f000b,
-0x30f40007,
-0x27780001,
-0x9740002a,
-0x07b80126,
-0x9f800000,
-0x00000000,
-0x80000136,
-0x7f1b8004,
-0x8000013a,
-0x7f1b8005,
-0x8000013e,
-0x7f1b8002,
-0x80000142,
-0x7f1b8003,
-0x80000146,
-0x7f1b8007,
-0x8000014a,
-0x7f1b8006,
-0x8000014f,
-0x28a40008,
-0x9b800019,
-0x28a40008,
-0x8000015f,
-0x326400ff,
-0x9b800015,
-0x28a40008,
-0x8000015f,
-0x326400ff,
-0x9b800011,
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-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00010333,
-0x00100006,
-0x00170008,
-0x0021000a,
-0x0027002a,
-0x00280025,
-0x0029002b,
-0x002a0028,
-0x002b002b,
-0x002d003a,
-0x002e0041,
-0x002f004c,
-0x0034004e,
-0x00360032,
-0x003900b1,
-0x003a00d1,
-0x003b00e6,
-0x003c00fe,
-0x003d016d,
-0x003f00af,
-0x00410338,
-0x0043034b,
-0x00440190,
-0x004500fe,
-0x004601ae,
-0x004701ae,
-0x00480200,
-0x0049020e,
-0x004a0257,
-0x004b0284,
-0x00520261,
-0x00530273,
-0x00540289,
-0x0057029b,
-0x0060029f,
-0x006102ae,
-0x006202b8,
-0x006302c2,
-0x006402cc,
-0x006502d6,
-0x006602e0,
-0x006702ea,
-0x006802f4,
-0x006902f8,
-0x006a02fc,
-0x006b0300,
-0x006c0304,
-0x006d0308,
-0x006e030c,
-0x006f0310,
-0x00700314,
-0x00720365,
-0x0074036b,
-0x00790369,
-0x007c031e,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-};
-
-#endif
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
new file mode 100644
index 0000000..4a9028a
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -0,0 +1,662 @@
+/*
+ * Copyright 2009 Advanced Micro Devices, Inc.
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ * Alex Deucher
+ * Jerome Glisse
+ */
+#ifndef R600D_H
+#define R600D_H
+
+#define CP_PACKET2 0x80000000
+#define PACKET2_PAD_SHIFT 0
+#define PACKET2_PAD_MASK (0x3fffffff << 0)
+
+#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
+
+#define R6XX_MAX_SH_GPRS 256
+#define R6XX_MAX_TEMP_GPRS 16
+#define R6XX_MAX_SH_THREADS 256
+#define R6XX_MAX_SH_STACK_ENTRIES 4096
+#define R6XX_MAX_BACKENDS 8
+#define R6XX_MAX_BACKENDS_MASK 0xff
+#define R6XX_MAX_SIMDS 8
+#define R6XX_MAX_SIMDS_MASK 0xff
+#define R6XX_MAX_PIPES 8
+#define R6XX_MAX_PIPES_MASK 0xff
+
+/* PTE flags */
+#define PTE_VALID (1 << 0)
+#define PTE_SYSTEM (1 << 1)
+#define PTE_SNOOPED (1 << 2)
+#define PTE_READABLE (1 << 5)
+#define PTE_WRITEABLE (1 << 6)
+
+/* Registers */
+#define ARB_POP 0x2418
+#define ENABLE_TC128 (1 << 30)
+#define ARB_GDEC_RD_CNTL 0x246C
+
+#define CC_GC_SHADER_PIPE_CONFIG 0x8950
+#define CC_RB_BACKEND_DISABLE 0x98F4
+#define BACKEND_DISABLE(x) ((x) << 16)
+
+#define CB_COLOR0_BASE 0x28040
+#define CB_COLOR1_BASE 0x28044
+#define CB_COLOR2_BASE 0x28048
+#define CB_COLOR3_BASE 0x2804C
+#define CB_COLOR4_BASE 0x28050
+#define CB_COLOR5_BASE 0x28054
+#define CB_COLOR6_BASE 0x28058
+#define CB_COLOR7_BASE 0x2805C
+#define CB_COLOR7_FRAG 0x280FC
+
+#define CB_COLOR0_SIZE 0x28060
+#define CB_COLOR0_VIEW 0x28080
+#define CB_COLOR0_INFO 0x280a0
+#define CB_COLOR0_TILE 0x280c0
+#define CB_COLOR0_FRAG 0x280e0
+#define CB_COLOR0_MASK 0x28100
+
+#define CONFIG_MEMSIZE 0x5428
+#define CONFIG_CNTL 0x5424
+#define CP_STAT 0x8680
+#define CP_COHER_BASE 0x85F8
+#define CP_DEBUG 0xC1FC
+#define R_0086D8_CP_ME_CNTL 0x86D8
+#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28)
+#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF)
+#define CP_ME_RAM_DATA 0xC160
+#define CP_ME_RAM_RADDR 0xC158
+#define CP_ME_RAM_WADDR 0xC15C
+#define CP_MEQ_THRESHOLDS 0x8764
+#define MEQ_END(x) ((x) << 16)
+#define ROQ_END(x) ((x) << 24)
+#define CP_PERFMON_CNTL 0x87FC
+#define CP_PFP_UCODE_ADDR 0xC150
+#define CP_PFP_UCODE_DATA 0xC154
+#define CP_QUEUE_THRESHOLDS 0x8760
+#define ROQ_IB1_START(x) ((x) << 0)
+#define ROQ_IB2_START(x) ((x) << 8)
+#define CP_RB_BASE 0xC100
+#define CP_RB_CNTL 0xC104
+#define RB_BUFSZ(x) ((x)<<0)
+#define RB_BLKSZ(x) ((x)<<8)
+#define RB_NO_UPDATE (1<<27)
+#define RB_RPTR_WR_ENA (1<<31)
+#define BUF_SWAP_32BIT (2 << 16)
+#define CP_RB_RPTR 0x8700
+#define CP_RB_RPTR_ADDR 0xC10C
+#define CP_RB_RPTR_ADDR_HI 0xC110
+#define CP_RB_RPTR_WR 0xC108
+#define CP_RB_WPTR 0xC114
+#define CP_RB_WPTR_ADDR 0xC118
+#define CP_RB_WPTR_ADDR_HI 0xC11C
+#define CP_RB_WPTR_DELAY 0x8704
+#define CP_ROQ_IB1_STAT 0x8784
+#define CP_ROQ_IB2_STAT 0x8788
+#define CP_SEM_WAIT_TIMER 0x85BC
+
+#define DB_DEBUG 0x9830
+#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
+#define DB_DEPTH_BASE 0x2800C
+#define DB_WATERMARKS 0x9838
+#define DEPTH_FREE(x) ((x) << 0)
+#define DEPTH_FLUSH(x) ((x) << 5)
+#define DEPTH_PENDING_FREE(x) ((x) << 15)
+#define DEPTH_CACHELINE_FREE(x) ((x) << 20)
+
+#define DCP_TILING_CONFIG 0x6CA0
+#define PIPE_TILING(x) ((x) << 1)
+#define BANK_TILING(x) ((x) << 4)
+#define GROUP_SIZE(x) ((x) << 6)
+#define ROW_TILING(x) ((x) << 8)
+#define BANK_SWAPS(x) ((x) << 11)
+#define SAMPLE_SPLIT(x) ((x) << 14)
+#define BACKEND_MAP(x) ((x) << 16)
+
+#define GB_TILING_CONFIG 0x98F0
+
+#define GC_USER_SHADER_PIPE_CONFIG 0x8954
+#define INACTIVE_QD_PIPES(x) ((x) << 8)
+#define INACTIVE_QD_PIPES_MASK 0x0000FF00
+#define INACTIVE_SIMDS(x) ((x) << 16)
+#define INACTIVE_SIMDS_MASK 0x00FF0000
+
+#define SQ_CONFIG 0x8c00
+# define VC_ENABLE (1 << 0)
+# define EXPORT_SRC_C (1 << 1)
+# define DX9_CONSTS (1 << 2)
+# define ALU_INST_PREFER_VECTOR (1 << 3)
+# define DX10_CLAMP (1 << 4)
+# define CLAUSE_SEQ_PRIO(x) ((x) << 8)
+# define PS_PRIO(x) ((x) << 24)
+# define VS_PRIO(x) ((x) << 26)
+# define GS_PRIO(x) ((x) << 28)
+# define ES_PRIO(x) ((x) << 30)
+#define SQ_GPR_RESOURCE_MGMT_1 0x8c04
+# define NUM_PS_GPRS(x) ((x) << 0)
+# define NUM_VS_GPRS(x) ((x) << 16)
+# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
+#define SQ_GPR_RESOURCE_MGMT_2 0x8c08
+# define NUM_GS_GPRS(x) ((x) << 0)
+# define NUM_ES_GPRS(x) ((x) << 16)
+#define SQ_THREAD_RESOURCE_MGMT 0x8c0c
+# define NUM_PS_THREADS(x) ((x) << 0)
+# define NUM_VS_THREADS(x) ((x) << 8)
+# define NUM_GS_THREADS(x) ((x) << 16)
+# define NUM_ES_THREADS(x) ((x) << 24)
+#define SQ_STACK_RESOURCE_MGMT_1 0x8c10
+# define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
+# define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
+#define SQ_STACK_RESOURCE_MGMT_2 0x8c14
+# define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
+# define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
+
+#define GRBM_CNTL 0x8000
+# define GRBM_READ_TIMEOUT(x) ((x) << 0)
+#define GRBM_STATUS 0x8010
+#define CMDFIFO_AVAIL_MASK 0x0000001F
+#define GUI_ACTIVE (1<<31)
+#define GRBM_STATUS2 0x8014
+#define GRBM_SOFT_RESET 0x8020
+#define SOFT_RESET_CP (1<<0)
+
+#define HDP_HOST_PATH_CNTL 0x2C00
+#define HDP_NONSURFACE_BASE 0x2C04
+#define HDP_NONSURFACE_INFO 0x2C08
+#define HDP_NONSURFACE_SIZE 0x2C0C
+#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
+#define HDP_TILING_CONFIG 0x2F3C
+
+#define MC_VM_AGP_TOP 0x2184
+#define MC_VM_AGP_BOT 0x2188
+#define MC_VM_AGP_BASE 0x218C
+#define MC_VM_FB_LOCATION 0x2180
+#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C
+#define ENABLE_L1_TLB (1 << 0)
+#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
+#define ENABLE_L1_STRICT_ORDERING (1 << 2)
+#define SYSTEM_ACCESS_MODE_MASK 0x000000C0
+#define SYSTEM_ACCESS_MODE_SHIFT 6
+#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
+#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
+#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
+#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
+#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
+#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
+#define ENABLE_SEMAPHORE_MODE (1 << 10)
+#define ENABLE_WAIT_L2_QUERY (1 << 11)
+#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12)
+#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000
+#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12
+#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15)
+#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000
+#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15
+#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0
+#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC
+#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204
+#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208
+#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C
+#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200
+#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4
+#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8
+#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210
+#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218
+#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C
+#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220
+#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
+#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
+#define LOGICAL_PAGE_NUMBER_SHIFT 0
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
+
+#define PA_CL_ENHANCE 0x8A14
+#define CLIP_VTX_REORDER_ENA (1 << 0)
+#define NUM_CLIP_SEQ(x) ((x) << 1)
+#define PA_SC_AA_CONFIG 0x28C04
+#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40
+#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44
+#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48
+#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C
+#define S0_X(x) ((x) << 0)
+#define S0_Y(x) ((x) << 4)
+#define S1_X(x) ((x) << 8)
+#define S1_Y(x) ((x) << 12)
+#define S2_X(x) ((x) << 16)
+#define S2_Y(x) ((x) << 20)
+#define S3_X(x) ((x) << 24)
+#define S3_Y(x) ((x) << 28)
+#define S4_X(x) ((x) << 0)
+#define S4_Y(x) ((x) << 4)
+#define S5_X(x) ((x) << 8)
+#define S5_Y(x) ((x) << 12)
+#define S6_X(x) ((x) << 16)
+#define S6_Y(x) ((x) << 20)
+#define S7_X(x) ((x) << 24)
+#define S7_Y(x) ((x) << 28)
+#define PA_SC_CLIPRECT_RULE 0x2820c
+#define PA_SC_ENHANCE 0x8BF0
+#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
+#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
+#define PA_SC_LINE_STIPPLE 0x28A0C
+#define PA_SC_LINE_STIPPLE_STATE 0x8B10
+#define PA_SC_MODE_CNTL 0x28A4C
+#define PA_SC_MULTI_CHIP_CNTL 0x8B20
+
+#define PA_SC_SCREEN_SCISSOR_TL 0x28030
+#define PA_SC_GENERIC_SCISSOR_TL 0x28240
+#define PA_SC_WINDOW_SCISSOR_TL 0x28204
+
+#define PCIE_PORT_INDEX 0x0038
+#define PCIE_PORT_DATA 0x003C
+
+#define RAMCFG 0x2408
+#define NOOFBANK_SHIFT 0
+#define NOOFBANK_MASK 0x00000001
+#define NOOFRANK_SHIFT 1
+#define NOOFRANK_MASK 0x00000002
+#define NOOFROWS_SHIFT 2
+#define NOOFROWS_MASK 0x0000001C
+#define NOOFCOLS_SHIFT 5
+#define NOOFCOLS_MASK 0x00000060
+#define CHANSIZE_SHIFT 7
+#define CHANSIZE_MASK 0x00000080
+#define BURSTLENGTH_SHIFT 8
+#define BURSTLENGTH_MASK 0x00000100
+#define CHANSIZE_OVERRIDE (1 << 10)
+
+#define SCRATCH_REG0 0x8500
+#define SCRATCH_REG1 0x8504
+#define SCRATCH_REG2 0x8508
+#define SCRATCH_REG3 0x850C
+#define SCRATCH_REG4 0x8510
+#define SCRATCH_REG5 0x8514
+#define SCRATCH_REG6 0x8518
+#define SCRATCH_REG7 0x851C
+#define SCRATCH_UMSK 0x8540
+#define SCRATCH_ADDR 0x8544
+
+#define SPI_CONFIG_CNTL 0x9100
+#define GPR_WRITE_PRIORITY(x) ((x) << 0)
+#define DISABLE_INTERP_1 (1 << 5)
+#define SPI_CONFIG_CNTL_1 0x913C
+#define VTX_DONE_DELAY(x) ((x) << 0)
+#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
+#define SPI_INPUT_Z 0x286D8
+#define SPI_PS_IN_CONTROL_0 0x286CC
+#define NUM_INTERP(x) ((x)<<0)
+#define POSITION_ENA (1<<8)
+#define POSITION_CENTROID (1<<9)
+#define POSITION_ADDR(x) ((x)<<10)
+#define PARAM_GEN(x) ((x)<<15)
+#define PARAM_GEN_ADDR(x) ((x)<<19)
+#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
+#define PERSP_GRADIENT_ENA (1<<28)
+#define LINEAR_GRADIENT_ENA (1<<29)
+#define POSITION_SAMPLE (1<<30)
+#define BARYC_AT_SAMPLE_ENA (1<<31)
+#define SPI_PS_IN_CONTROL_1 0x286D0
+#define GEN_INDEX_PIX (1<<0)
+#define GEN_INDEX_PIX_ADDR(x) ((x)<<1)
+#define FRONT_FACE_ENA (1<<8)
+#define FRONT_FACE_CHAN(x) ((x)<<9)
+#define FRONT_FACE_ALL_BITS (1<<11)
+#define FRONT_FACE_ADDR(x) ((x)<<12)
+#define FOG_ADDR(x) ((x)<<17)
+#define FIXED_PT_POSITION_ENA (1<<24)
+#define FIXED_PT_POSITION_ADDR(x) ((x)<<25)
+
+#define SQ_MS_FIFO_SIZES 0x8CF0
+#define CACHE_FIFO_SIZE(x) ((x) << 0)
+#define FETCH_FIFO_HIWATER(x) ((x) << 8)
+#define DONE_FIFO_HIWATER(x) ((x) << 16)
+#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
+#define SQ_PGM_START_ES 0x28880
+#define SQ_PGM_START_FS 0x28894
+#define SQ_PGM_START_GS 0x2886C
+#define SQ_PGM_START_PS 0x28840
+#define SQ_PGM_RESOURCES_PS 0x28850
+#define SQ_PGM_EXPORTS_PS 0x28854
+#define SQ_PGM_CF_OFFSET_PS 0x288cc
+#define SQ_PGM_START_VS 0x28858
+#define SQ_PGM_RESOURCES_VS 0x28868
+#define SQ_PGM_CF_OFFSET_VS 0x288d0
+#define SQ_VTX_CONSTANT_WORD6_0 0x38018
+#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30)
+#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3)
+#define SQ_TEX_VTX_INVALID_TEXTURE 0x0
+#define SQ_TEX_VTX_INVALID_BUFFER 0x1
+#define SQ_TEX_VTX_VALID_TEXTURE 0x2
+#define SQ_TEX_VTX_VALID_BUFFER 0x3
+
+
+#define SX_MISC 0x28350
+#define SX_DEBUG_1 0x9054
+#define SMX_EVENT_RELEASE (1 << 0)
+#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
+
+#define TA_CNTL_AUX 0x9508
+#define DISABLE_CUBE_WRAP (1 << 0)
+#define DISABLE_CUBE_ANISO (1 << 1)
+#define SYNC_GRADIENT (1 << 24)
+#define SYNC_WALKER (1 << 25)
+#define SYNC_ALIGNER (1 << 26)
+#define BILINEAR_PRECISION_6_BIT (0 << 31)
+#define BILINEAR_PRECISION_8_BIT (1 << 31)
+
+#define TC_CNTL 0x9608
+#define TC_L2_SIZE(x) ((x)<<5)
+#define L2_DISABLE_LATE_HIT (1<<9)
+
+
+#define VGT_CACHE_INVALIDATION 0x88C4
+#define CACHE_INVALIDATION(x) ((x)<<0)
+#define VC_ONLY 0
+#define TC_ONLY 1
+#define VC_AND_TC 2
+#define VGT_DMA_BASE 0x287E8
+#define VGT_DMA_BASE_HI 0x287E4
+#define VGT_ES_PER_GS 0x88CC
+#define VGT_GS_PER_ES 0x88C8
+#define VGT_GS_PER_VS 0x88E8
+#define VGT_GS_VERTEX_REUSE 0x88D4
+#define VGT_PRIMITIVE_TYPE 0x8958
+#define VGT_NUM_INSTANCES 0x8974
+#define VGT_OUT_DEALLOC_CNTL 0x28C5C
+#define DEALLOC_DIST_MASK 0x0000007F
+#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10
+#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14
+#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18
+#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c
+#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44
+#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48
+#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c
+#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50
+#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
+#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
+#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
+#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
+#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC
+#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC
+#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC
+#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C
+#define VGT_STRMOUT_EN 0x28AB0
+#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
+#define VTX_REUSE_DEPTH_MASK 0x000000FF
+#define VGT_EVENT_INITIATOR 0x28a90
+# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
+
+#define VM_CONTEXT0_CNTL 0x1410
+#define ENABLE_CONTEXT (1 << 0)
+#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
+#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
+#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
+#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554
+#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
+#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
+#define RESPONSE_TYPE_MASK 0x000000F0
+#define RESPONSE_TYPE_SHIFT 4
+#define VM_L2_CNTL 0x1400
+#define ENABLE_L2_CACHE (1 << 0)
+#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
+#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
+#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13)
+#define VM_L2_CNTL2 0x1404
+#define INVALIDATE_ALL_L1_TLBS (1 << 0)
+#define INVALIDATE_L2_CACHE (1 << 1)
+#define VM_L2_CNTL3 0x1408
+#define BANK_SELECT_0(x) (((x) & 0x1f) << 0)
+#define BANK_SELECT_1(x) (((x) & 0x1f) << 5)
+#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10)
+#define VM_L2_STATUS 0x140C
+#define L2_BUSY (1 << 0)
+
+#define WAIT_UNTIL 0x8040
+#define WAIT_2D_IDLE_bit (1 << 14)
+#define WAIT_3D_IDLE_bit (1 << 15)
+#define WAIT_2D_IDLECLEAN_bit (1 << 16)
+#define WAIT_3D_IDLECLEAN_bit (1 << 17)
+
+
+
+/*
+ * PM4
+ */
+#define PACKET_TYPE0 0
+#define PACKET_TYPE1 1
+#define PACKET_TYPE2 2
+#define PACKET_TYPE3 3
+
+#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
+#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
+#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
+#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
+#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
+ (((reg) >> 2) & 0xFFFF) | \
+ ((n) & 0x3FFF) << 16)
+#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
+ (((op) & 0xFF) << 8) | \
+ ((n) & 0x3FFF) << 16)
+
+/* Packet 3 types */
+#define PACKET3_NOP 0x10
+#define PACKET3_INDIRECT_BUFFER_END 0x17
+#define PACKET3_SET_PREDICATION 0x20
+#define PACKET3_REG_RMW 0x21
+#define PACKET3_COND_EXEC 0x22
+#define PACKET3_PRED_EXEC 0x23
+#define PACKET3_START_3D_CMDBUF 0x24
+#define PACKET3_DRAW_INDEX_2 0x27
+#define PACKET3_CONTEXT_CONTROL 0x28
+#define PACKET3_DRAW_INDEX_IMMD_BE 0x29
+#define PACKET3_INDEX_TYPE 0x2A
+#define PACKET3_DRAW_INDEX 0x2B
+#define PACKET3_DRAW_INDEX_AUTO 0x2D
+#define PACKET3_DRAW_INDEX_IMMD 0x2E
+#define PACKET3_NUM_INSTANCES 0x2F
+#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
+#define PACKET3_INDIRECT_BUFFER_MP 0x38
+#define PACKET3_MEM_SEMAPHORE 0x39
+#define PACKET3_MPEG_INDEX 0x3A
+#define PACKET3_WAIT_REG_MEM 0x3C
+#define PACKET3_MEM_WRITE 0x3D
+#define PACKET3_INDIRECT_BUFFER 0x32
+#define PACKET3_CP_INTERRUPT 0x40
+#define PACKET3_SURFACE_SYNC 0x43
+# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
+# define PACKET3_TC_ACTION_ENA (1 << 23)
+# define PACKET3_VC_ACTION_ENA (1 << 24)
+# define PACKET3_CB_ACTION_ENA (1 << 25)
+# define PACKET3_DB_ACTION_ENA (1 << 26)
+# define PACKET3_SH_ACTION_ENA (1 << 27)
+# define PACKET3_SMX_ACTION_ENA (1 << 28)
+#define PACKET3_ME_INITIALIZE 0x44
+#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
+#define PACKET3_COND_WRITE 0x45
+#define PACKET3_EVENT_WRITE 0x46
+#define PACKET3_EVENT_WRITE_EOP 0x47
+#define PACKET3_ONE_REG_WRITE 0x57
+#define PACKET3_SET_CONFIG_REG 0x68
+#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000
+#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
+#define PACKET3_SET_CONTEXT_REG 0x69
+#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000
+#define PACKET3_SET_CONTEXT_REG_END 0x00029000
+#define PACKET3_SET_ALU_CONST 0x6A
+#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000
+#define PACKET3_SET_ALU_CONST_END 0x00032000
+#define PACKET3_SET_BOOL_CONST 0x6B
+#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380
+#define PACKET3_SET_BOOL_CONST_END 0x00040000
+#define PACKET3_SET_LOOP_CONST 0x6C
+#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200
+#define PACKET3_SET_LOOP_CONST_END 0x0003e380
+#define PACKET3_SET_RESOURCE 0x6D
+#define PACKET3_SET_RESOURCE_OFFSET 0x00038000
+#define PACKET3_SET_RESOURCE_END 0x0003c000
+#define PACKET3_SET_SAMPLER 0x6E
+#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000
+#define PACKET3_SET_SAMPLER_END 0x0003cff0
+#define PACKET3_SET_CTL_CONST 0x6F
+#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0
+#define PACKET3_SET_CTL_CONST_END 0x0003e200
+#define PACKET3_SURFACE_BASE_UPDATE 0x73
+
+
+#define R_008020_GRBM_SOFT_RESET 0x8020
+#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)
+#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1)
+#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2)
+#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3)
+#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5)
+#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6)
+#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7)
+#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8)
+#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9)
+#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10)
+#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11)
+#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12)
+#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13)
+#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14)
+#define R_008010_GRBM_STATUS 0x8010
+#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0)
+#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6)
+#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7)
+#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8)
+#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10)
+#define S_008010_VC_BUSY(x) (((x) & 1) << 11)
+#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12)
+#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13)
+#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16)
+#define S_008010_VGT_BUSY(x) (((x) & 1) << 17)
+#define S_008010_TA03_BUSY(x) (((x) & 1) << 18)
+#define S_008010_TC_BUSY(x) (((x) & 1) << 19)
+#define S_008010_SX_BUSY(x) (((x) & 1) << 20)
+#define S_008010_SH_BUSY(x) (((x) & 1) << 21)
+#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22)
+#define S_008010_SMX_BUSY(x) (((x) & 1) << 23)
+#define S_008010_SC_BUSY(x) (((x) & 1) << 24)
+#define S_008010_PA_BUSY(x) (((x) & 1) << 25)
+#define S_008010_DB03_BUSY(x) (((x) & 1) << 26)
+#define S_008010_CR_BUSY(x) (((x) & 1) << 27)
+#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28)
+#define S_008010_CP_BUSY(x) (((x) & 1) << 29)
+#define S_008010_CB03_BUSY(x) (((x) & 1) << 30)
+#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31)
+#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F)
+#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1)
+#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1)
+#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1)
+#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1)
+#define G_008010_VC_BUSY(x) (((x) >> 11) & 1)
+#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1)
+#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1)
+#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1)
+#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1)
+#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1)
+#define G_008010_TC_BUSY(x) (((x) >> 19) & 1)
+#define G_008010_SX_BUSY(x) (((x) >> 20) & 1)
+#define G_008010_SH_BUSY(x) (((x) >> 21) & 1)
+#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1)
+#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1)
+#define G_008010_SC_BUSY(x) (((x) >> 24) & 1)
+#define G_008010_PA_BUSY(x) (((x) >> 25) & 1)
+#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1)
+#define G_008010_CR_BUSY(x) (((x) >> 27) & 1)
+#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1)
+#define G_008010_CP_BUSY(x) (((x) >> 29) & 1)
+#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1)
+#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1)
+#define R_008014_GRBM_STATUS2 0x8014
+#define S_008014_CR_CLEAN(x) (((x) & 1) << 0)
+#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1)
+#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8)
+#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9)
+#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10)
+#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11)
+#define S_008014_TA0_BUSY(x) (((x) & 1) << 12)
+#define S_008014_TA1_BUSY(x) (((x) & 1) << 13)
+#define S_008014_TA2_BUSY(x) (((x) & 1) << 14)
+#define S_008014_TA3_BUSY(x) (((x) & 1) << 15)
+#define S_008014_DB0_BUSY(x) (((x) & 1) << 16)
+#define S_008014_DB1_BUSY(x) (((x) & 1) << 17)
+#define S_008014_DB2_BUSY(x) (((x) & 1) << 18)
+#define S_008014_DB3_BUSY(x) (((x) & 1) << 19)
+#define S_008014_CB0_BUSY(x) (((x) & 1) << 20)
+#define S_008014_CB1_BUSY(x) (((x) & 1) << 21)
+#define S_008014_CB2_BUSY(x) (((x) & 1) << 22)
+#define S_008014_CB3_BUSY(x) (((x) & 1) << 23)
+#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1)
+#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1)
+#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1)
+#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1)
+#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1)
+#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1)
+#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1)
+#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1)
+#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1)
+#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1)
+#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1)
+#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1)
+#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1)
+#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1)
+#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1)
+#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1)
+#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1)
+#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1)
+#define R_000E50_SRBM_STATUS 0x0E50
+#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1)
+#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1)
+#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1)
+#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1)
+#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1)
+#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1)
+#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1)
+#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1)
+#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1)
+#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1)
+#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1)
+#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1)
+#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1)
+#define R_000E60_SRBM_SOFT_RESET 0x0E60
+#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1)
+#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2)
+#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3)
+#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4)
+#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5)
+#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8)
+#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9)
+#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10)
+#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11)
+#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13)
+#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14)
+#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15)
+#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16)
+#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)
+
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b519fb2..c839b60 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -51,7 +51,6 @@
#include "radeon_mode.h"
#include "radeon_reg.h"
-#include "r300.h"
/*
* Modules parameters.
@@ -66,6 +65,7 @@ extern int radeon_gart_size;
extern int radeon_benchmarking;
extern int radeon_testing;
extern int radeon_connector_table;
+extern int radeon_tv;
/*
* Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -75,6 +75,7 @@ extern int radeon_connector_table;
#define RADEON_IB_POOL_SIZE 16
#define RADEON_DEBUGFS_MAX_NUM_FILES 32
#define RADEONFB_CONN_LIMIT 4
+#define RADEON_BIOS_NUM_SCRATCH 8
enum radeon_family {
CHIP_R100,
@@ -107,14 +108,15 @@ enum radeon_family {
CHIP_R600,
CHIP_RV610,
CHIP_RV630,
+ CHIP_RV670,
CHIP_RV620,
CHIP_RV635,
- CHIP_RV670,
CHIP_RS780,
+ CHIP_RS880,
CHIP_RV770,
CHIP_RV730,
CHIP_RV710,
- CHIP_RS880,
+ CHIP_RV740,
CHIP_LAST,
};
@@ -151,10 +153,21 @@ struct radeon_device;
*/
bool radeon_get_bios(struct radeon_device *rdev);
+
/*
- * Clocks
+ * Dummy page
*/
+struct radeon_dummy_page {
+ struct page *page;
+ dma_addr_t addr;
+};
+int radeon_dummy_page_init(struct radeon_device *rdev);
+void radeon_dummy_page_fini(struct radeon_device *rdev);
+
+/*
+ * Clocks
+ */
struct radeon_clock {
struct radeon_pll p1pll;
struct radeon_pll p2pll;
@@ -165,6 +178,7 @@ struct radeon_clock {
uint32_t default_sclk;
};
+
/*
* Fences.
*/
@@ -331,14 +345,18 @@ struct radeon_mc {
resource_size_t aper_size;
resource_size_t aper_base;
resource_size_t agp_base;
- unsigned gtt_location;
- unsigned gtt_size;
- unsigned vram_location;
/* for some chips with <= 32MB we need to lie
* about vram size near mc fb location */
- unsigned mc_vram_size;
+ u64 mc_vram_size;
+ u64 gtt_location;
+ u64 gtt_size;
+ u64 gtt_start;
+ u64 gtt_end;
+ u64 vram_location;
+ u64 vram_start;
+ u64 vram_end;
unsigned vram_width;
- unsigned real_vram_size;
+ u64 real_vram_size;
int vram_mtrr;
bool vram_is_ddr;
};
@@ -385,6 +403,10 @@ struct radeon_ib {
uint32_t length_dw;
};
+/*
+ * locking -
+ * mutex protects scheduled_ibs, ready, alloc_bm
+ */
struct radeon_ib_pool {
struct mutex mutex;
struct radeon_object *robj;
@@ -410,6 +432,16 @@ struct radeon_cp {
bool ready;
};
+struct r600_blit {
+ struct radeon_object *shader_obj;
+ u64 shader_gpu_addr;
+ u32 vs_offset, ps_offset;
+ u32 state_offset;
+ u32 state_len;
+ u32 vb_used, vb_total;
+ struct radeon_ib *vb_ib;
+};
+
int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
@@ -462,6 +494,7 @@ struct radeon_cs_parser {
int chunk_relocs_idx;
struct radeon_ib *ib;
void *track;
+ unsigned family;
};
struct radeon_cs_packet {
@@ -558,13 +591,19 @@ int r100_debugfs_cp_init(struct radeon_device *rdev);
*/
struct radeon_asic {
int (*init)(struct radeon_device *rdev);
+ void (*fini)(struct radeon_device *rdev);
+ int (*resume)(struct radeon_device *rdev);
+ int (*suspend)(struct radeon_device *rdev);
void (*errata)(struct radeon_device *rdev);
void (*vram_info)(struct radeon_device *rdev);
+ void (*vga_set_state)(struct radeon_device *rdev, bool state);
int (*gpu_reset)(struct radeon_device *rdev);
int (*mc_init)(struct radeon_device *rdev);
void (*mc_fini)(struct radeon_device *rdev);
int (*wb_init)(struct radeon_device *rdev);
void (*wb_fini)(struct radeon_device *rdev);
+ int (*gart_init)(struct radeon_device *rdev);
+ void (*gart_fini)(struct radeon_device *rdev);
int (*gart_enable)(struct radeon_device *rdev);
void (*gart_disable)(struct radeon_device *rdev);
void (*gart_tlb_flush)(struct radeon_device *rdev);
@@ -572,7 +611,11 @@ struct radeon_asic {
int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
void (*cp_fini)(struct radeon_device *rdev);
void (*cp_disable)(struct radeon_device *rdev);
+ void (*cp_commit)(struct radeon_device *rdev);
void (*ring_start)(struct radeon_device *rdev);
+ int (*ring_test)(struct radeon_device *rdev);
+ void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
+ int (*ib_test)(struct radeon_device *rdev);
int (*irq_set)(struct radeon_device *rdev);
int (*irq_process)(struct radeon_device *rdev);
u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
@@ -604,8 +647,60 @@ struct radeon_asic {
void (*bandwidth_update)(struct radeon_device *rdev);
};
+/*
+ * Asic structures
+ */
+struct r100_asic {
+ const unsigned *reg_safe_bm;
+ unsigned reg_safe_bm_size;
+};
+
+struct r300_asic {
+ const unsigned *reg_safe_bm;
+ unsigned reg_safe_bm_size;
+};
+
+struct r600_asic {
+ unsigned max_pipes;
+ unsigned max_tile_pipes;
+ unsigned max_simds;
+ unsigned max_backends;
+ unsigned max_gprs;
+ unsigned max_threads;
+ unsigned max_stack_entries;
+ unsigned max_hw_contexts;
+ unsigned max_gs_threads;
+ unsigned sx_max_export_size;
+ unsigned sx_max_export_pos_size;
+ unsigned sx_max_export_smx_size;
+ unsigned sq_num_cf_insts;
+};
+
+struct rv770_asic {
+ unsigned max_pipes;
+ unsigned max_tile_pipes;
+ unsigned max_simds;
+ unsigned max_backends;
+ unsigned max_gprs;
+ unsigned max_threads;
+ unsigned max_stack_entries;
+ unsigned max_hw_contexts;
+ unsigned max_gs_threads;
+ unsigned sx_max_export_size;
+ unsigned sx_max_export_pos_size;
+ unsigned sx_max_export_smx_size;
+ unsigned sq_num_cf_insts;
+ unsigned sx_num_of_sets;
+ unsigned sc_prim_fifo_size;
+ unsigned sc_hiz_tile_fifo_size;
+ unsigned sc_earlyz_tile_fifo_fize;
+};
+
union radeon_asic_config {
struct r300_asic r300;
+ struct r100_asic r100;
+ struct r600_asic r600;
+ struct rv770_asic rv770;
};
@@ -646,6 +741,7 @@ typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
struct radeon_device {
+ struct device *dev;
struct drm_device *ddev;
struct pci_dev *pdev;
/* ASIC */
@@ -689,13 +785,20 @@ struct radeon_device {
struct radeon_asic *asic;
struct radeon_gem gem;
struct radeon_pm pm;
+ uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
struct mutex cs_mutex;
struct radeon_wb wb;
+ struct radeon_dummy_page dummy_page;
bool gpu_lockup;
bool shutdown;
bool suspend;
bool need_dma32;
+ bool new_init_path;
+ bool accel_working;
struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
+ const struct firmware *me_fw; /* all family ME firmware */
+ const struct firmware *pfp_fw; /* r6/700 PFP firmware */
+ struct r600_blit r600_blit;
};
int radeon_device_init(struct radeon_device *rdev,
@@ -705,6 +808,13 @@ int radeon_device_init(struct radeon_device *rdev,
void radeon_device_fini(struct radeon_device *rdev);
int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
+/* r600 blit */
+int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
+void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
+void r600_kms_blit_copy(struct radeon_device *rdev,
+ u64 src_gpu_addr, u64 dst_gpu_addr,
+ int size_bytes);
+
static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
{
if (reg < 0x10000)
@@ -732,6 +842,7 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
#define RREG32(reg) r100_mm_rreg(rdev, (reg))
+#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
@@ -755,6 +866,7 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
tmp_ |= ((val) & ~(mask)); \
WREG32_PLL(reg, tmp_); \
} while (0)
+#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
/*
* Indirect registers accessor
@@ -819,51 +931,6 @@ void radeon_atombios_fini(struct radeon_device *rdev);
/*
* RING helpers.
*/
-#define CP_PACKET0 0x00000000
-#define PACKET0_BASE_INDEX_SHIFT 0
-#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
-#define PACKET0_COUNT_SHIFT 16
-#define PACKET0_COUNT_MASK (0x3fff << 16)
-#define CP_PACKET1 0x40000000
-#define CP_PACKET2 0x80000000
-#define PACKET2_PAD_SHIFT 0
-#define PACKET2_PAD_MASK (0x3fffffff << 0)
-#define CP_PACKET3 0xC0000000
-#define PACKET3_IT_OPCODE_SHIFT 8
-#define PACKET3_IT_OPCODE_MASK (0xff << 8)
-#define PACKET3_COUNT_SHIFT 16
-#define PACKET3_COUNT_MASK (0x3fff << 16)
-/* PACKET3 op code */
-#define PACKET3_NOP 0x10
-#define PACKET3_3D_DRAW_VBUF 0x28
-#define PACKET3_3D_DRAW_IMMD 0x29
-#define PACKET3_3D_DRAW_INDX 0x2A
-#define PACKET3_3D_LOAD_VBPNTR 0x2F
-#define PACKET3_INDX_BUFFER 0x33
-#define PACKET3_3D_DRAW_VBUF_2 0x34
-#define PACKET3_3D_DRAW_IMMD_2 0x35
-#define PACKET3_3D_DRAW_INDX_2 0x36
-#define PACKET3_BITBLT_MULTI 0x9B
-
-#define PACKET0(reg, n) (CP_PACKET0 | \
- REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
- REG_SET(PACKET0_COUNT, (n)))
-#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
-#define PACKET3(op, n) (CP_PACKET3 | \
- REG_SET(PACKET3_IT_OPCODE, (op)) | \
- REG_SET(PACKET3_COUNT, (n)))
-
-#define PACKET_TYPE0 0
-#define PACKET_TYPE1 1
-#define PACKET_TYPE2 2
-#define PACKET_TYPE3 3
-
-#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
-#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
-#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
-#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
-#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
-
static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
{
#if DRM_DEBUG_CODE
@@ -882,14 +949,20 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
* ASICs macro.
*/
#define radeon_init(rdev) (rdev)->asic->init((rdev))
+#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
+#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
+#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
+#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
+#define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
+#define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
@@ -897,7 +970,11 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
+#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
+#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
+#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
+#define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
@@ -913,4 +990,88 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
+/* Common functions */
+extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
+extern int radeon_modeset_init(struct radeon_device *rdev);
+extern void radeon_modeset_fini(struct radeon_device *rdev);
+extern bool radeon_card_posted(struct radeon_device *rdev);
+extern int radeon_clocks_init(struct radeon_device *rdev);
+extern void radeon_clocks_fini(struct radeon_device *rdev);
+extern void radeon_scratch_init(struct radeon_device *rdev);
+extern void radeon_surface_init(struct radeon_device *rdev);
+extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
+
+/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
+struct r100_mc_save {
+ u32 GENMO_WT;
+ u32 CRTC_EXT_CNTL;
+ u32 CRTC_GEN_CNTL;
+ u32 CRTC2_GEN_CNTL;
+ u32 CUR_OFFSET;
+ u32 CUR2_OFFSET;
+};
+extern void r100_cp_disable(struct radeon_device *rdev);
+extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
+extern void r100_cp_fini(struct radeon_device *rdev);
+extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
+extern int r100_pci_gart_init(struct radeon_device *rdev);
+extern void r100_pci_gart_fini(struct radeon_device *rdev);
+extern int r100_pci_gart_enable(struct radeon_device *rdev);
+extern void r100_pci_gart_disable(struct radeon_device *rdev);
+extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
+extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
+extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
+extern void r100_ib_fini(struct radeon_device *rdev);
+extern int r100_ib_init(struct radeon_device *rdev);
+extern void r100_irq_disable(struct radeon_device *rdev);
+extern int r100_irq_set(struct radeon_device *rdev);
+extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
+extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
+extern void r100_vram_init_sizes(struct radeon_device *rdev);
+extern void r100_wb_disable(struct radeon_device *rdev);
+extern void r100_wb_fini(struct radeon_device *rdev);
+extern int r100_wb_init(struct radeon_device *rdev);
+
+/* r300,r350,rv350,rv370,rv380 */
+extern void r300_set_reg_safe(struct radeon_device *rdev);
+extern void r300_mc_program(struct radeon_device *rdev);
+extern void r300_vram_info(struct radeon_device *rdev);
+extern int rv370_pcie_gart_init(struct radeon_device *rdev);
+extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
+extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
+extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
+
+/* r420,r423,rv410 */
+extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
+extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
+extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
+
+/* rv515 */
+extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
+
+/* rs690, rs740 */
+extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
+ struct drm_display_mode *mode1,
+ struct drm_display_mode *mode2);
+
+/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
+extern bool r600_card_posted(struct radeon_device *rdev);
+extern void r600_cp_stop(struct radeon_device *rdev);
+extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
+extern int r600_cp_resume(struct radeon_device *rdev);
+extern int r600_count_pipe_bits(uint32_t val);
+extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
+extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
+extern int r600_pcie_gart_init(struct radeon_device *rdev);
+extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
+extern int r600_ib_test(struct radeon_device *rdev);
+extern int r600_ring_test(struct radeon_device *rdev);
+extern int r600_wb_init(struct radeon_device *rdev);
+extern void r600_wb_fini(struct radeon_device *rdev);
+extern void r600_scratch_init(struct radeon_device *rdev);
+extern int r600_blit_init(struct radeon_device *rdev);
+extern void r600_blit_fini(struct radeon_device *rdev);
+extern int r600_cp_init_microcode(struct radeon_device *rdev);
+extern int r600_gpu_reset(struct radeon_device *rdev);
+
#endif
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 93d8f88..8968f78 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -42,23 +42,28 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
*/
int r100_init(struct radeon_device *rdev);
+int r200_init(struct radeon_device *rdev);
uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
void r100_errata(struct radeon_device *rdev);
void r100_vram_info(struct radeon_device *rdev);
+void r100_vga_set_state(struct radeon_device *rdev, bool state);
int r100_gpu_reset(struct radeon_device *rdev);
int r100_mc_init(struct radeon_device *rdev);
void r100_mc_fini(struct radeon_device *rdev);
u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
int r100_wb_init(struct radeon_device *rdev);
void r100_wb_fini(struct radeon_device *rdev);
-int r100_gart_enable(struct radeon_device *rdev);
+int r100_pci_gart_init(struct radeon_device *rdev);
+void r100_pci_gart_fini(struct radeon_device *rdev);
+int r100_pci_gart_enable(struct radeon_device *rdev);
void r100_pci_gart_disable(struct radeon_device *rdev);
void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
void r100_cp_fini(struct radeon_device *rdev);
void r100_cp_disable(struct radeon_device *rdev);
+void r100_cp_commit(struct radeon_device *rdev);
void r100_ring_start(struct radeon_device *rdev);
int r100_irq_set(struct radeon_device *rdev);
int r100_irq_process(struct radeon_device *rdev);
@@ -77,24 +82,34 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
uint32_t offset, uint32_t obj_size);
int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
void r100_bandwidth_update(struct radeon_device *rdev);
+void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
+int r100_ib_test(struct radeon_device *rdev);
+int r100_ring_test(struct radeon_device *rdev);
static struct radeon_asic r100_asic = {
.init = &r100_init,
.errata = &r100_errata,
.vram_info = &r100_vram_info,
+ .vga_set_state = &r100_vga_set_state,
.gpu_reset = &r100_gpu_reset,
.mc_init = &r100_mc_init,
.mc_fini = &r100_mc_fini,
.wb_init = &r100_wb_init,
.wb_fini = &r100_wb_fini,
- .gart_enable = &r100_gart_enable,
+ .gart_init = &r100_pci_gart_init,
+ .gart_fini = &r100_pci_gart_fini,
+ .gart_enable = &r100_pci_gart_enable,
.gart_disable = &r100_pci_gart_disable,
.gart_tlb_flush = &r100_pci_gart_tlb_flush,
.gart_set_page = &r100_pci_gart_set_page,
.cp_init = &r100_cp_init,
.cp_fini = &r100_cp_fini,
.cp_disable = &r100_cp_disable,
+ .cp_commit = &r100_cp_commit,
.ring_start = &r100_ring_start,
+ .ring_test = &r100_ring_test,
+ .ring_ib_execute = &r100_ring_ib_execute,
+ .ib_test = &r100_ib_test,
.irq_set = &r100_irq_set,
.irq_process = &r100_irq_process,
.get_vblank_counter = &r100_get_vblank_counter,
@@ -126,7 +141,9 @@ void r300_ring_start(struct radeon_device *rdev);
void r300_fence_ring_emit(struct radeon_device *rdev,
struct radeon_fence *fence);
int r300_cs_parse(struct radeon_cs_parser *p);
-int r300_gart_enable(struct radeon_device *rdev);
+int rv370_pcie_gart_init(struct radeon_device *rdev);
+void rv370_pcie_gart_fini(struct radeon_device *rdev);
+int rv370_pcie_gart_enable(struct radeon_device *rdev);
void rv370_pcie_gart_disable(struct radeon_device *rdev);
void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
@@ -143,19 +160,26 @@ static struct radeon_asic r300_asic = {
.init = &r300_init,
.errata = &r300_errata,
.vram_info = &r300_vram_info,
+ .vga_set_state = &r100_vga_set_state,
.gpu_reset = &r300_gpu_reset,
.mc_init = &r300_mc_init,
.mc_fini = &r300_mc_fini,
.wb_init = &r100_wb_init,
.wb_fini = &r100_wb_fini,
- .gart_enable = &r300_gart_enable,
+ .gart_init = &r100_pci_gart_init,
+ .gart_fini = &r100_pci_gart_fini,
+ .gart_enable = &r100_pci_gart_enable,
.gart_disable = &r100_pci_gart_disable,
.gart_tlb_flush = &r100_pci_gart_tlb_flush,
.gart_set_page = &r100_pci_gart_set_page,
.cp_init = &r100_cp_init,
.cp_fini = &r100_cp_fini,
.cp_disable = &r100_cp_disable,
+ .cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
+ .ring_test = &r100_ring_test,
+ .ring_ib_execute = &r100_ring_ib_execute,
+ .ib_test = &r100_ib_test,
.irq_set = &r100_irq_set,
.irq_process = &r100_irq_process,
.get_vblank_counter = &r100_get_vblank_counter,
@@ -176,27 +200,35 @@ static struct radeon_asic r300_asic = {
/*
* r420,r423,rv410
*/
-void r420_errata(struct radeon_device *rdev);
-void r420_vram_info(struct radeon_device *rdev);
-int r420_mc_init(struct radeon_device *rdev);
-void r420_mc_fini(struct radeon_device *rdev);
+extern int r420_init(struct radeon_device *rdev);
+extern void r420_fini(struct radeon_device *rdev);
+extern int r420_suspend(struct radeon_device *rdev);
+extern int r420_resume(struct radeon_device *rdev);
static struct radeon_asic r420_asic = {
- .init = &r300_init,
- .errata = &r420_errata,
- .vram_info = &r420_vram_info,
+ .init = &r420_init,
+ .fini = &r420_fini,
+ .suspend = &r420_suspend,
+ .resume = &r420_resume,
+ .errata = NULL,
+ .vram_info = NULL,
+ .vga_set_state = &r100_vga_set_state,
.gpu_reset = &r300_gpu_reset,
- .mc_init = &r420_mc_init,
- .mc_fini = &r420_mc_fini,
- .wb_init = &r100_wb_init,
- .wb_fini = &r100_wb_fini,
- .gart_enable = &r300_gart_enable,
- .gart_disable = &rv370_pcie_gart_disable,
+ .mc_init = NULL,
+ .mc_fini = NULL,
+ .wb_init = NULL,
+ .wb_fini = NULL,
+ .gart_enable = NULL,
+ .gart_disable = NULL,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
.gart_set_page = &rv370_pcie_gart_set_page,
- .cp_init = &r100_cp_init,
- .cp_fini = &r100_cp_fini,
- .cp_disable = &r100_cp_disable,
+ .cp_init = NULL,
+ .cp_fini = NULL,
+ .cp_disable = NULL,
+ .cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
+ .ring_test = &r100_ring_test,
+ .ring_ib_execute = &r100_ring_ib_execute,
+ .ib_test = NULL,
.irq_set = &r100_irq_set,
.irq_process = &r100_irq_process,
.get_vblank_counter = &r100_get_vblank_counter,
@@ -222,6 +254,8 @@ void rs400_errata(struct radeon_device *rdev);
void rs400_vram_info(struct radeon_device *rdev);
int rs400_mc_init(struct radeon_device *rdev);
void rs400_mc_fini(struct radeon_device *rdev);
+int rs400_gart_init(struct radeon_device *rdev);
+void rs400_gart_fini(struct radeon_device *rdev);
int rs400_gart_enable(struct radeon_device *rdev);
void rs400_gart_disable(struct radeon_device *rdev);
void rs400_gart_tlb_flush(struct radeon_device *rdev);
@@ -232,11 +266,14 @@ static struct radeon_asic rs400_asic = {
.init = &r300_init,
.errata = &rs400_errata,
.vram_info = &rs400_vram_info,
+ .vga_set_state = &r100_vga_set_state,
.gpu_reset = &r300_gpu_reset,
.mc_init = &rs400_mc_init,
.mc_fini = &rs400_mc_fini,
.wb_init = &r100_wb_init,
.wb_fini = &r100_wb_fini,
+ .gart_init = &rs400_gart_init,
+ .gart_fini = &rs400_gart_fini,
.gart_enable = &rs400_gart_enable,
.gart_disable = &rs400_gart_disable,
.gart_tlb_flush = &rs400_gart_tlb_flush,
@@ -244,7 +281,11 @@ static struct radeon_asic rs400_asic = {
.cp_init = &r100_cp_init,
.cp_fini = &r100_cp_fini,
.cp_disable = &r100_cp_disable,
+ .cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
+ .ring_test = &r100_ring_test,
+ .ring_ib_execute = &r100_ring_ib_execute,
+ .ib_test = &r100_ib_test,
.irq_set = &r100_irq_set,
.irq_process = &r100_irq_process,
.get_vblank_counter = &r100_get_vblank_counter,
@@ -266,7 +307,7 @@ static struct radeon_asic rs400_asic = {
/*
* rs600.
*/
-int rs600_init(struct radeon_device *dev);
+int rs600_init(struct radeon_device *rdev);
void rs600_errata(struct radeon_device *rdev);
void rs600_vram_info(struct radeon_device *rdev);
int rs600_mc_init(struct radeon_device *rdev);
@@ -274,6 +315,8 @@ void rs600_mc_fini(struct radeon_device *rdev);
int rs600_irq_set(struct radeon_device *rdev);
int rs600_irq_process(struct radeon_device *rdev);
u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
+int rs600_gart_init(struct radeon_device *rdev);
+void rs600_gart_fini(struct radeon_device *rdev);
int rs600_gart_enable(struct radeon_device *rdev);
void rs600_gart_disable(struct radeon_device *rdev);
void rs600_gart_tlb_flush(struct radeon_device *rdev);
@@ -285,11 +328,14 @@ static struct radeon_asic rs600_asic = {
.init = &rs600_init,
.errata = &rs600_errata,
.vram_info = &rs600_vram_info,
+ .vga_set_state = &r100_vga_set_state,
.gpu_reset = &r300_gpu_reset,
.mc_init = &rs600_mc_init,
.mc_fini = &rs600_mc_fini,
.wb_init = &r100_wb_init,
.wb_fini = &r100_wb_fini,
+ .gart_init = &rs600_gart_init,
+ .gart_fini = &rs600_gart_fini,
.gart_enable = &rs600_gart_enable,
.gart_disable = &rs600_gart_disable,
.gart_tlb_flush = &rs600_gart_tlb_flush,
@@ -297,7 +343,11 @@ static struct radeon_asic rs600_asic = {
.cp_init = &r100_cp_init,
.cp_fini = &r100_cp_fini,
.cp_disable = &r100_cp_disable,
+ .cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
+ .ring_test = &r100_ring_test,
+ .ring_ib_execute = &r100_ring_ib_execute,
+ .ib_test = &r100_ib_test,
.irq_set = &rs600_irq_set,
.irq_process = &rs600_irq_process,
.get_vblank_counter = &rs600_get_vblank_counter,
@@ -328,11 +378,14 @@ static struct radeon_asic rs690_asic = {
.init = &rs600_init,
.errata = &rs690_errata,
.vram_info = &rs690_vram_info,
+ .vga_set_state = &r100_vga_set_state,
.gpu_reset = &r300_gpu_reset,
.mc_init = &rs690_mc_init,
.mc_fini = &rs690_mc_fini,
.wb_init = &r100_wb_init,
.wb_fini = &r100_wb_fini,
+ .gart_init = &rs400_gart_init,
+ .gart_fini = &rs400_gart_fini,
.gart_enable = &rs400_gart_enable,
.gart_disable = &rs400_gart_disable,
.gart_tlb_flush = &rs400_gart_tlb_flush,
@@ -340,7 +393,11 @@ static struct radeon_asic rs690_asic = {
.cp_init = &r100_cp_init,
.cp_fini = &r100_cp_fini,
.cp_disable = &r100_cp_disable,
+ .cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
+ .ring_test = &r100_ring_test,
+ .ring_ib_execute = &r100_ring_ib_execute,
+ .ib_test = &r100_ib_test,
.irq_set = &rs600_irq_set,
.irq_process = &rs600_irq_process,
.get_vblank_counter = &rs600_get_vblank_counter,
@@ -378,19 +435,26 @@ static struct radeon_asic rv515_asic = {
.init = &rv515_init,
.errata = &rv515_errata,
.vram_info = &rv515_vram_info,
+ .vga_set_state = &r100_vga_set_state,
.gpu_reset = &rv515_gpu_reset,
.mc_init = &rv515_mc_init,
.mc_fini = &rv515_mc_fini,
.wb_init = &r100_wb_init,
.wb_fini = &r100_wb_fini,
- .gart_enable = &r300_gart_enable,
+ .gart_init = &rv370_pcie_gart_init,
+ .gart_fini = &rv370_pcie_gart_fini,
+ .gart_enable = &rv370_pcie_gart_enable,
.gart_disable = &rv370_pcie_gart_disable,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
.gart_set_page = &rv370_pcie_gart_set_page,
.cp_init = &r100_cp_init,
.cp_fini = &r100_cp_fini,
.cp_disable = &r100_cp_disable,
+ .cp_commit = &r100_cp_commit,
.ring_start = &rv515_ring_start,
+ .ring_test = &r100_ring_test,
+ .ring_ib_execute = &r100_ring_ib_execute,
+ .ib_test = &r100_ib_test,
.irq_set = &rs600_irq_set,
.irq_process = &rs600_irq_process,
.get_vblank_counter = &rs600_get_vblank_counter,
@@ -421,19 +485,26 @@ static struct radeon_asic r520_asic = {
.init = &rv515_init,
.errata = &r520_errata,
.vram_info = &r520_vram_info,
+ .vga_set_state = &r100_vga_set_state,
.gpu_reset = &rv515_gpu_reset,
.mc_init = &r520_mc_init,
.mc_fini = &r520_mc_fini,
.wb_init = &r100_wb_init,
.wb_fini = &r100_wb_fini,
- .gart_enable = &r300_gart_enable,
+ .gart_init = &rv370_pcie_gart_init,
+ .gart_fini = &rv370_pcie_gart_fini,
+ .gart_enable = &rv370_pcie_gart_enable,
.gart_disable = &rv370_pcie_gart_disable,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
.gart_set_page = &rv370_pcie_gart_set_page,
.cp_init = &r100_cp_init,
.cp_fini = &r100_cp_fini,
.cp_disable = &r100_cp_disable,
+ .cp_commit = &r100_cp_commit,
.ring_start = &rv515_ring_start,
+ .ring_test = &r100_ring_test,
+ .ring_ib_execute = &r100_ring_ib_execute,
+ .ib_test = &r100_ib_test,
.irq_set = &rs600_irq_set,
.irq_process = &rs600_irq_process,
.get_vblank_counter = &rs600_get_vblank_counter,
@@ -452,9 +523,130 @@ static struct radeon_asic r520_asic = {
};
/*
- * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710
+ * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
*/
+int r600_init(struct radeon_device *rdev);
+void r600_fini(struct radeon_device *rdev);
+int r600_suspend(struct radeon_device *rdev);
+int r600_resume(struct radeon_device *rdev);
+void r600_vga_set_state(struct radeon_device *rdev, bool state);
+int r600_wb_init(struct radeon_device *rdev);
+void r600_wb_fini(struct radeon_device *rdev);
+void r600_cp_commit(struct radeon_device *rdev);
+void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
+int r600_cs_parse(struct radeon_cs_parser *p);
+void r600_fence_ring_emit(struct radeon_device *rdev,
+ struct radeon_fence *fence);
+int r600_copy_dma(struct radeon_device *rdev,
+ uint64_t src_offset,
+ uint64_t dst_offset,
+ unsigned num_pages,
+ struct radeon_fence *fence);
+int r600_irq_process(struct radeon_device *rdev);
+int r600_irq_set(struct radeon_device *rdev);
+int r600_gpu_reset(struct radeon_device *rdev);
+int r600_set_surface_reg(struct radeon_device *rdev, int reg,
+ uint32_t tiling_flags, uint32_t pitch,
+ uint32_t offset, uint32_t obj_size);
+int r600_clear_surface_reg(struct radeon_device *rdev, int reg);
+void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
+int r600_ib_test(struct radeon_device *rdev);
+int r600_ring_test(struct radeon_device *rdev);
+int r600_copy_blit(struct radeon_device *rdev,
+ uint64_t src_offset, uint64_t dst_offset,
+ unsigned num_pages, struct radeon_fence *fence);
+
+static struct radeon_asic r600_asic = {
+ .errata = NULL,
+ .init = &r600_init,
+ .fini = &r600_fini,
+ .suspend = &r600_suspend,
+ .resume = &r600_resume,
+ .cp_commit = &r600_cp_commit,
+ .vram_info = NULL,
+ .vga_set_state = &r600_vga_set_state,
+ .gpu_reset = &r600_gpu_reset,
+ .mc_init = NULL,
+ .mc_fini = NULL,
+ .wb_init = &r600_wb_init,
+ .wb_fini = &r600_wb_fini,
+ .gart_enable = NULL,
+ .gart_disable = NULL,
+ .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
+ .gart_set_page = &rs600_gart_set_page,
+ .cp_init = NULL,
+ .cp_fini = NULL,
+ .cp_disable = NULL,
+ .ring_start = NULL,
+ .ring_test = &r600_ring_test,
+ .ring_ib_execute = &r600_ring_ib_execute,
+ .ib_test = &r600_ib_test,
+ .irq_set = &r600_irq_set,
+ .irq_process = &r600_irq_process,
+ .fence_ring_emit = &r600_fence_ring_emit,
+ .cs_parse = &r600_cs_parse,
+ .copy_blit = &r600_copy_blit,
+ .copy_dma = &r600_copy_blit,
+ .copy = &r600_copy_blit,
+ .set_engine_clock = &radeon_atom_set_engine_clock,
+ .set_memory_clock = &radeon_atom_set_memory_clock,
+ .set_pcie_lanes = NULL,
+ .set_clock_gating = &radeon_atom_set_clock_gating,
+ .set_surface_reg = r600_set_surface_reg,
+ .clear_surface_reg = r600_clear_surface_reg,
+ .bandwidth_update = &r520_bandwidth_update,
+};
+
+/*
+ * rv770,rv730,rv710,rv740
+ */
+int rv770_init(struct radeon_device *rdev);
+void rv770_fini(struct radeon_device *rdev);
+int rv770_suspend(struct radeon_device *rdev);
+int rv770_resume(struct radeon_device *rdev);
+int rv770_gpu_reset(struct radeon_device *rdev);
+
+static struct radeon_asic rv770_asic = {
+ .errata = NULL,
+ .init = &rv770_init,
+ .fini = &rv770_fini,
+ .suspend = &rv770_suspend,
+ .resume = &rv770_resume,
+ .cp_commit = &r600_cp_commit,
+ .vram_info = NULL,
+ .gpu_reset = &rv770_gpu_reset,
+ .vga_set_state = &r600_vga_set_state,
+ .mc_init = NULL,
+ .mc_fini = NULL,
+ .wb_init = &r600_wb_init,
+ .wb_fini = &r600_wb_fini,
+ .gart_enable = NULL,
+ .gart_disable = NULL,
+ .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
+ .gart_set_page = &rs600_gart_set_page,
+ .cp_init = NULL,
+ .cp_fini = NULL,
+ .cp_disable = NULL,
+ .ring_start = NULL,
+ .ring_test = &r600_ring_test,
+ .ring_ib_execute = &r600_ring_ib_execute,
+ .ib_test = &r600_ib_test,
+ .irq_set = &r600_irq_set,
+ .irq_process = &r600_irq_process,
+ .fence_ring_emit = &r600_fence_ring_emit,
+ .cs_parse = &r600_cs_parse,
+ .copy_blit = &r600_copy_blit,
+ .copy_dma = &r600_copy_blit,
+ .copy = &r600_copy_blit,
+ .set_engine_clock = &radeon_atom_set_engine_clock,
+ .set_memory_clock = &radeon_atom_set_memory_clock,
+ .set_pcie_lanes = NULL,
+ .set_clock_gating = &radeon_atom_set_clock_gating,
+ .set_surface_reg = r600_set_surface_reg,
+ .clear_surface_reg = r600_clear_surface_reg,
+ .bandwidth_update = &r520_bandwidth_update,
+};
#endif
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index fcfe5c0..7437421 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -104,7 +104,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
uint32_t supported_device,
int *connector_type,
struct radeon_i2c_bus_rec *i2c_bus,
- uint8_t *line_mux)
+ uint16_t *line_mux)
{
/* Asus M2A-VM HDMI board lists the DVI port as HDMI */
@@ -143,20 +143,31 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
return false;
}
- /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */
- if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) ||
- (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) {
- if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
- return false;
- }
- }
-
/* ASUS HD 3600 XT board lists the DVI port as HDMI */
if ((dev->pdev->device == 0x9598) &&
(dev->pdev->subsystem_vendor == 0x1043) &&
(dev->pdev->subsystem_device == 0x01da)) {
- if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) {
- *connector_type = DRM_MODE_CONNECTOR_DVID;
+ if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
+ *connector_type = DRM_MODE_CONNECTOR_DVII;
+ }
+ }
+
+ /* ASUS HD 3450 board lists the DVI port as HDMI */
+ if ((dev->pdev->device == 0x95C5) &&
+ (dev->pdev->subsystem_vendor == 0x1043) &&
+ (dev->pdev->subsystem_device == 0x01e2)) {
+ if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
+ *connector_type = DRM_MODE_CONNECTOR_DVII;
+ }
+ }
+
+ /* some BIOSes seem to report DAC on HDMI - usually this is a board with
+ * HDMI + VGA reporting as HDMI
+ */
+ if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
+ if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
+ *connector_type = DRM_MODE_CONNECTOR_VGA;
+ *line_mux = 0;
}
}
@@ -192,11 +203,11 @@ const int object_connector_convert[] = {
DRM_MODE_CONNECTOR_Composite,
DRM_MODE_CONNECTOR_SVIDEO,
DRM_MODE_CONNECTOR_Unknown,
+ DRM_MODE_CONNECTOR_Unknown,
DRM_MODE_CONNECTOR_9PinDIN,
DRM_MODE_CONNECTOR_Unknown,
DRM_MODE_CONNECTOR_HDMIA,
DRM_MODE_CONNECTOR_HDMIB,
- DRM_MODE_CONNECTOR_HDMIB,
DRM_MODE_CONNECTOR_LVDS,
DRM_MODE_CONNECTOR_9PinDIN,
DRM_MODE_CONNECTOR_Unknown,
@@ -218,7 +229,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
ATOM_OBJECT_HEADER *obj_header;
int i, j, path_size, device_support;
int connector_type;
- uint16_t igp_lane_info;
+ uint16_t igp_lane_info, conn_id;
bool linkb;
struct radeon_i2c_bus_rec ddc_bus;
@@ -370,10 +381,6 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
&& record->
ucRecordType <=
ATOM_MAX_OBJECT_RECORD_NUMBER) {
- DRM_ERROR
- ("record type %d\n",
- record->
- ucRecordType);
switch (record->
ucRecordType) {
case ATOM_I2C_RECORD_TYPE:
@@ -409,9 +416,15 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
else
ddc_bus = radeon_lookup_gpio(dev, line_mux);
+ conn_id = le16_to_cpu(path->usConnObjectId);
+
+ if (!radeon_atom_apply_quirks
+ (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
+ &ddc_bus, &conn_id))
+ continue;
+
radeon_add_atom_connector(dev,
- le16_to_cpu(path->
- usConnObjectId),
+ conn_id,
le16_to_cpu(path->
usDeviceTag),
connector_type, &ddc_bus,
@@ -427,7 +440,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
struct bios_connector {
bool valid;
- uint8_t line_mux;
+ uint16_t line_mux;
uint16_t devices;
int connector_type;
struct radeon_i2c_bus_rec ddc_bus;
@@ -471,11 +484,6 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
continue;
}
- if (i == ATOM_DEVICE_TV1_INDEX) {
- DRM_DEBUG("Skipping TV Out\n");
- continue;
- }
-
bios_connectors[i].connector_type =
supported_devices_connector_convert[ci.sucConnectorInfo.
sbfAccess.
@@ -711,9 +719,8 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
return false;
}
-struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
- radeon_encoder
- *encoder)
+bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
+ struct radeon_encoder_int_tmds *tmds)
{
struct drm_device *dev = encoder->base.dev;
struct radeon_device *rdev = dev->dev_private;
@@ -724,7 +731,6 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
uint8_t frev, crev;
uint16_t maxfreq;
int i;
- struct radeon_encoder_int_tmds *tmds = NULL;
atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
&crev, &data_offset);
@@ -734,12 +740,6 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
data_offset);
if (tmds_info) {
- tmds =
- kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
-
- if (!tmds)
- return NULL;
-
maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
for (i = 0; i < 4; i++) {
tmds->tmds_pll[i].freq =
@@ -765,8 +765,9 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
break;
}
}
+ return true;
}
- return tmds;
+ return false;
}
union lvds_info {
@@ -858,6 +859,72 @@ radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
return p_dac;
}
+bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
+ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
+ int32_t *pixel_clock)
+{
+ struct radeon_mode_info *mode_info = &rdev->mode_info;
+ ATOM_ANALOG_TV_INFO *tv_info;
+ ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
+ ATOM_DTD_FORMAT *dtd_timings;
+ int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
+ u8 frev, crev;
+ uint16_t data_offset;
+
+ atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
+
+ switch (crev) {
+ case 1:
+ tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
+ if (index > MAX_SUPPORTED_TV_TIMING)
+ return false;
+
+ crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
+ crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
+ crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
+ crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
+
+ crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
+ crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
+ crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
+ crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
+
+ crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo;
+
+ crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight);
+ crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft);
+ crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom);
+ crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop);
+ *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
+
+ if (index == 1) {
+ /* PAL timings appear to have wrong values for totals */
+ crtc_timing->usH_Total -= 1;
+ crtc_timing->usV_Total -= 1;
+ }
+ break;
+ case 2:
+ tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
+ if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
+ return false;
+
+ dtd_timings = &tv_info_v1_2->aModeTimings[index];
+ crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time);
+ crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive);
+ crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset);
+ crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth);
+ crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time);
+ crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive);
+ crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset);
+ crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth);
+
+ crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
+ *pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
+ break;
+ }
+ return true;
+}
+
struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
{
@@ -948,10 +1015,10 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
uint32_t bios_2_scratch, bios_6_scratch;
if (rdev->family >= CHIP_R600) {
- bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH);
+ bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
} else {
- bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
+ bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
}
@@ -971,6 +1038,34 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
}
+void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
+{
+ uint32_t scratch_reg;
+ int i;
+
+ if (rdev->family >= CHIP_R600)
+ scratch_reg = R600_BIOS_0_SCRATCH;
+ else
+ scratch_reg = RADEON_BIOS_0_SCRATCH;
+
+ for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
+ rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
+}
+
+void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
+{
+ uint32_t scratch_reg;
+ int i;
+
+ if (rdev->family >= CHIP_R600)
+ scratch_reg = R600_BIOS_0_SCRATCH;
+ else
+ scratch_reg = RADEON_BIOS_0_SCRATCH;
+
+ for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
+ WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
+}
+
void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
{
struct drm_device *dev = encoder->dev;
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index a37cbce..152eef1 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -102,10 +102,12 @@ void radeon_get_clock_info(struct drm_device *dev)
p1pll->reference_div = 12;
if (p2pll->reference_div < 2)
p2pll->reference_div = 12;
- if (spll->reference_div < 2)
- spll->reference_div =
- RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
- RADEON_M_SPLL_REF_DIV_MASK;
+ if (rdev->family < CHIP_RS600) {
+ if (spll->reference_div < 2)
+ spll->reference_div =
+ RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
+ RADEON_M_SPLL_REF_DIV_MASK;
+ }
if (mpll->reference_div < 2)
mpll->reference_div = spll->reference_div;
} else {
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 2a027e0..748265a 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -863,8 +863,10 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
int tmp, i;
struct radeon_encoder_lvds *lvds = NULL;
- if (rdev->bios == NULL)
- return radeon_legacy_get_lvds_info_from_regs(rdev);
+ if (rdev->bios == NULL) {
+ lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
+ goto out;
+ }
lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
@@ -965,11 +967,13 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
lvds->native_mode.flags = 0;
}
}
- encoder->native_mode = lvds->native_mode;
} else {
DRM_INFO("No panel info found in BIOS\n");
- return radeon_legacy_get_lvds_info_from_regs(rdev);
+ lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
}
+out:
+ if (lvds)
+ encoder->native_mode = lvds->native_mode;
return lvds;
}
@@ -994,48 +998,37 @@ static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RS480 */
};
-static struct radeon_encoder_int_tmds
- *radeon_legacy_get_tmds_info_from_table(struct radeon_device *rdev)
+bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
+ struct radeon_encoder_int_tmds *tmds)
{
+ struct drm_device *dev = encoder->base.dev;
+ struct radeon_device *rdev = dev->dev_private;
int i;
- struct radeon_encoder_int_tmds *tmds = NULL;
-
- tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
-
- if (!tmds)
- return NULL;
for (i = 0; i < 4; i++) {
tmds->tmds_pll[i].value =
- default_tmds_pll[rdev->family][i].value;
+ default_tmds_pll[rdev->family][i].value;
tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
}
- return tmds;
+ return true;
}
-struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct
- radeon_encoder
- *encoder)
+bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
+ struct radeon_encoder_int_tmds *tmds)
{
struct drm_device *dev = encoder->base.dev;
struct radeon_device *rdev = dev->dev_private;
uint16_t tmds_info;
int i, n;
uint8_t ver;
- struct radeon_encoder_int_tmds *tmds = NULL;
if (rdev->bios == NULL)
- return radeon_legacy_get_tmds_info_from_table(rdev);
+ return false;
tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
if (tmds_info) {
- tmds =
- kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
-
- if (!tmds)
- return NULL;
ver = RBIOS8(tmds_info);
DRM_INFO("DFP table revision: %d\n", ver);
@@ -1073,6 +1066,23 @@ struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct
}
} else
DRM_INFO("No TMDS info found in BIOS\n");
+ return true;
+}
+
+struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct radeon_encoder *encoder)
+{
+ struct radeon_encoder_int_tmds *tmds = NULL;
+ bool ret;
+
+ tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
+
+ if (!tmds)
+ return NULL;
+
+ ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
+ if (ret == false)
+ radeon_legacy_get_tmds_info_from_table(encoder, tmds);
+
return tmds;
}
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 70ede6a..af1d551 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -28,6 +28,7 @@
#include "drm_crtc_helper.h"
#include "radeon_drm.h"
#include "radeon.h"
+#include "atom.h"
extern void
radeon_combios_connected_scratch_regs(struct drm_connector *connector,
@@ -38,6 +39,15 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
struct drm_encoder *encoder,
bool connected);
+static void radeon_property_change_mode(struct drm_encoder *encoder)
+{
+ struct drm_crtc *crtc = encoder->crtc;
+
+ if (crtc && crtc->enabled) {
+ drm_crtc_helper_set_mode(crtc, &crtc->mode,
+ crtc->x, crtc->y, crtc->fb);
+ }
+}
static void
radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_connector_status status)
{
@@ -77,6 +87,27 @@ radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_c
}
}
+struct drm_encoder *radeon_find_encoder(struct drm_connector *connector, int encoder_type)
+{
+ struct drm_mode_object *obj;
+ struct drm_encoder *encoder;
+ int i;
+
+ for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+ if (connector->encoder_ids[i] == 0)
+ break;
+
+ obj = drm_mode_object_find(connector->dev, connector->encoder_ids[i], DRM_MODE_OBJECT_ENCODER);
+ if (!obj)
+ continue;
+
+ encoder = obj_to_encoder(obj);
+ if (encoder->encoder_type == encoder_type)
+ return encoder;
+ }
+ return NULL;
+}
+
struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector)
{
int enc_id = connector->encoder_ids[0];
@@ -94,6 +125,53 @@ struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector)
return NULL;
}
+/*
+ * radeon_connector_analog_encoder_conflict_solve
+ * - search for other connectors sharing this encoder
+ * if priority is true, then set them disconnected if this is connected
+ * if priority is false, set us disconnected if they are connected
+ */
+static enum drm_connector_status
+radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector,
+ struct drm_encoder *encoder,
+ enum drm_connector_status current_status,
+ bool priority)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_connector *conflict;
+ int i;
+
+ list_for_each_entry(conflict, &dev->mode_config.connector_list, head) {
+ if (conflict == connector)
+ continue;
+
+ for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+ if (conflict->encoder_ids[i] == 0)
+ break;
+
+ /* if the IDs match */
+ if (conflict->encoder_ids[i] == encoder->base.id) {
+ if (conflict->status != connector_status_connected)
+ continue;
+
+ if (priority == true) {
+ DRM_INFO("1: conflicting encoders switching off %s\n", drm_get_connector_name(conflict));
+ DRM_INFO("in favor of %s\n", drm_get_connector_name(connector));
+ conflict->status = connector_status_disconnected;
+ radeon_connector_update_scratch_regs(conflict, connector_status_disconnected);
+ } else {
+ DRM_INFO("2: conflicting encoders switching off %s\n", drm_get_connector_name(connector));
+ DRM_INFO("in favor of %s\n", drm_get_connector_name(conflict));
+ current_status = connector_status_disconnected;
+ }
+ break;
+ }
+ }
+ }
+ return current_status;
+
+}
+
static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
@@ -126,12 +204,171 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode
return mode;
}
+static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector)
+{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct drm_display_mode *mode = NULL;
+ struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
+ int i;
+ struct mode_size {
+ int w;
+ int h;
+ } common_modes[17] = {
+ { 640, 480},
+ { 720, 480},
+ { 800, 600},
+ { 848, 480},
+ {1024, 768},
+ {1152, 768},
+ {1280, 720},
+ {1280, 800},
+ {1280, 854},
+ {1280, 960},
+ {1280, 1024},
+ {1440, 900},
+ {1400, 1050},
+ {1680, 1050},
+ {1600, 1200},
+ {1920, 1080},
+ {1920, 1200}
+ };
+
+ for (i = 0; i < 17; i++) {
+ if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+ if (common_modes[i].w > native_mode->panel_xres ||
+ common_modes[i].h > native_mode->panel_yres ||
+ (common_modes[i].w == native_mode->panel_xres &&
+ common_modes[i].h == native_mode->panel_yres))
+ continue;
+ }
+ if (common_modes[i].w < 320 || common_modes[i].h < 200)
+ continue;
+
+ mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false);
+ drm_mode_probed_add(connector, mode);
+ }
+}
+
int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property,
uint64_t val)
{
+ struct drm_device *dev = connector->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ struct drm_encoder *encoder;
+ struct radeon_encoder *radeon_encoder;
+
+ if (property == rdev->mode_info.coherent_mode_property) {
+ struct radeon_encoder_atom_dig *dig;
+
+ /* need to find digital encoder on connector */
+ encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
+ if (!encoder)
+ return 0;
+
+ radeon_encoder = to_radeon_encoder(encoder);
+
+ if (!radeon_encoder->enc_priv)
+ return 0;
+
+ dig = radeon_encoder->enc_priv;
+ dig->coherent_mode = val ? true : false;
+ radeon_property_change_mode(&radeon_encoder->base);
+ }
+
+ if (property == rdev->mode_info.tv_std_property) {
+ encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC);
+ if (!encoder) {
+ encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_DAC);
+ }
+
+ if (!encoder)
+ return 0;
+
+ radeon_encoder = to_radeon_encoder(encoder);
+ if (!radeon_encoder->enc_priv)
+ return 0;
+ if (rdev->is_atom_bios) {
+ struct radeon_encoder_atom_dac *dac_int;
+ dac_int = radeon_encoder->enc_priv;
+ dac_int->tv_std = val;
+ } else {
+ struct radeon_encoder_tv_dac *dac_int;
+ dac_int = radeon_encoder->enc_priv;
+ dac_int->tv_std = val;
+ }
+ radeon_property_change_mode(&radeon_encoder->base);
+ }
+
+ if (property == rdev->mode_info.load_detect_property) {
+ struct radeon_connector *radeon_connector =
+ to_radeon_connector(connector);
+
+ if (val == 0)
+ radeon_connector->dac_load_detect = false;
+ else
+ radeon_connector->dac_load_detect = true;
+ }
+
+ if (property == rdev->mode_info.tmds_pll_property) {
+ struct radeon_encoder_int_tmds *tmds = NULL;
+ bool ret = false;
+ /* need to find digital encoder on connector */
+ encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
+ if (!encoder)
+ return 0;
+
+ radeon_encoder = to_radeon_encoder(encoder);
+
+ tmds = radeon_encoder->enc_priv;
+ if (!tmds)
+ return 0;
+
+ if (val == 0) {
+ if (rdev->is_atom_bios)
+ ret = radeon_atombios_get_tmds_info(radeon_encoder, tmds);
+ else
+ ret = radeon_legacy_get_tmds_info_from_combios(radeon_encoder, tmds);
+ }
+ if (val == 1 || ret == false) {
+ radeon_legacy_get_tmds_info_from_table(radeon_encoder, tmds);
+ }
+ radeon_property_change_mode(&radeon_encoder->base);
+ }
+
return 0;
}
+static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder,
+ struct drm_connector *connector)
+{
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
+
+ /* Try to get native mode details from EDID if necessary */
+ if (!native_mode->dotclock) {
+ struct drm_display_mode *t, *mode;
+
+ list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
+ if (mode->hdisplay == native_mode->panel_xres &&
+ mode->vdisplay == native_mode->panel_yres) {
+ native_mode->hblank = mode->htotal - mode->hdisplay;
+ native_mode->hoverplus = mode->hsync_start - mode->hdisplay;
+ native_mode->hsync_width = mode->hsync_end - mode->hsync_start;
+ native_mode->vblank = mode->vtotal - mode->vdisplay;
+ native_mode->voverplus = mode->vsync_start - mode->vdisplay;
+ native_mode->vsync_width = mode->vsync_end - mode->vsync_start;
+ native_mode->dotclock = mode->clock;
+ DRM_INFO("Determined LVDS native mode details from EDID\n");
+ break;
+ }
+ }
+ }
+ if (!native_mode->dotclock) {
+ DRM_INFO("No LVDS native mode details, disabling RMX\n");
+ radeon_encoder->rmx_type = RMX_OFF;
+ }
+}
static int radeon_lvds_get_modes(struct drm_connector *connector)
{
@@ -143,6 +380,12 @@ static int radeon_lvds_get_modes(struct drm_connector *connector)
if (radeon_connector->ddc_bus) {
ret = radeon_ddc_get_modes(radeon_connector);
if (ret > 0) {
+ encoder = radeon_best_single_encoder(connector);
+ if (encoder) {
+ radeon_fixup_lvds_native_mode(encoder, connector);
+ /* add scaled modes */
+ radeon_add_common_modes(encoder, connector);
+ }
return ret;
}
}
@@ -156,7 +399,10 @@ static int radeon_lvds_get_modes(struct drm_connector *connector)
if (mode) {
ret = 1;
drm_mode_probed_add(connector, mode);
+ /* add scaled modes */
+ radeon_add_common_modes(encoder, connector);
}
+
return ret;
}
@@ -186,6 +432,42 @@ static void radeon_connector_destroy(struct drm_connector *connector)
kfree(connector);
}
+static int radeon_lvds_set_property(struct drm_connector *connector,
+ struct drm_property *property,
+ uint64_t value)
+{
+ struct drm_device *dev = connector->dev;
+ struct radeon_encoder *radeon_encoder;
+ enum radeon_rmx_type rmx_type;
+
+ DRM_DEBUG("\n");
+ if (property != dev->mode_config.scaling_mode_property)
+ return 0;
+
+ if (connector->encoder)
+ radeon_encoder = to_radeon_encoder(connector->encoder);
+ else {
+ struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
+ radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector));
+ }
+
+ switch (value) {
+ case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
+ case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
+ case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
+ default:
+ case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
+ }
+ if (radeon_encoder->rmx_type == rmx_type)
+ return 0;
+
+ radeon_encoder->rmx_type = rmx_type;
+
+ radeon_property_change_mode(&radeon_encoder->base);
+ return 0;
+}
+
+
struct drm_connector_helper_funcs radeon_lvds_connector_helper_funcs = {
.get_modes = radeon_lvds_get_modes,
.mode_valid = radeon_lvds_mode_valid,
@@ -197,7 +479,7 @@ struct drm_connector_funcs radeon_lvds_connector_funcs = {
.detect = radeon_lvds_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = radeon_connector_destroy,
- .set_property = radeon_connector_set_property,
+ .set_property = radeon_lvds_set_property,
};
static int radeon_vga_get_modes(struct drm_connector *connector)
@@ -213,7 +495,6 @@ static int radeon_vga_get_modes(struct drm_connector *connector)
static int radeon_vga_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
-
return MODE_OK;
}
@@ -225,22 +506,24 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
bool dret;
enum drm_connector_status ret = connector_status_disconnected;
+ encoder = radeon_best_single_encoder(connector);
+ if (!encoder)
+ ret = connector_status_disconnected;
+
radeon_i2c_do_lock(radeon_connector, 1);
dret = radeon_ddc_probe(radeon_connector);
radeon_i2c_do_lock(radeon_connector, 0);
if (dret)
ret = connector_status_connected;
else {
- /* if EDID fails to a load detect */
- encoder = radeon_best_single_encoder(connector);
- if (!encoder)
- ret = connector_status_disconnected;
- else {
+ if (radeon_connector->dac_load_detect) {
encoder_funcs = encoder->helper_private;
ret = encoder_funcs->detect(encoder, connector);
}
}
+ if (ret == connector_status_connected)
+ ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);
radeon_connector_update_scratch_regs(connector, ret);
return ret;
}
@@ -259,21 +542,97 @@ struct drm_connector_funcs radeon_vga_connector_funcs = {
.set_property = radeon_connector_set_property,
};
+static int radeon_tv_get_modes(struct drm_connector *connector)
+{
+ struct drm_device *dev = connector->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ struct drm_display_mode *tv_mode;
+ struct drm_encoder *encoder;
+
+ encoder = radeon_best_single_encoder(connector);
+ if (!encoder)
+ return 0;
+
+ /* avivo chips can scale any mode */
+ if (rdev->family >= CHIP_RS600)
+ /* add scaled modes */
+ radeon_add_common_modes(encoder, connector);
+ else {
+ /* only 800x600 is supported right now on pre-avivo chips */
+ tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false);
+ tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+ drm_mode_probed_add(connector, tv_mode);
+ }
+ return 1;
+}
+
+static int radeon_tv_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ return MODE_OK;
+}
+
+static enum drm_connector_status radeon_tv_detect(struct drm_connector *connector)
+{
+ struct drm_encoder *encoder;
+ struct drm_encoder_helper_funcs *encoder_funcs;
+ struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+ enum drm_connector_status ret = connector_status_disconnected;
+
+ if (!radeon_connector->dac_load_detect)
+ return ret;
+
+ encoder = radeon_best_single_encoder(connector);
+ if (!encoder)
+ ret = connector_status_disconnected;
+ else {
+ encoder_funcs = encoder->helper_private;
+ ret = encoder_funcs->detect(encoder, connector);
+ }
+ if (ret == connector_status_connected)
+ ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false);
+ radeon_connector_update_scratch_regs(connector, ret);
+ return ret;
+}
+
+struct drm_connector_helper_funcs radeon_tv_connector_helper_funcs = {
+ .get_modes = radeon_tv_get_modes,
+ .mode_valid = radeon_tv_mode_valid,
+ .best_encoder = radeon_best_single_encoder,
+};
+
+struct drm_connector_funcs radeon_tv_connector_funcs = {
+ .dpms = drm_helper_connector_dpms,
+ .detect = radeon_tv_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = radeon_connector_destroy,
+ .set_property = radeon_connector_set_property,
+};
+
static int radeon_dvi_get_modes(struct drm_connector *connector)
{
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
int ret;
ret = radeon_ddc_get_modes(radeon_connector);
- /* reset scratch regs here since radeon_dvi_detect doesn't check digital bit */
- radeon_connector_update_scratch_regs(connector, connector_status_connected);
return ret;
}
+/*
+ * DVI is complicated
+ * Do a DDC probe, if DDC probe passes, get the full EDID so
+ * we can do analog/digital monitor detection at this point.
+ * If the monitor is an analog monitor or we got no DDC,
+ * we need to find the DAC encoder object for this connector.
+ * If we got no DDC, we do load detection on the DAC encoder object.
+ * If we got analog DDC or load detection passes on the DAC encoder
+ * we have to check if this analog encoder is shared with anyone else (TV)
+ * if its shared we have to set the other connector to disconnected.
+ */
static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connector)
{
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
- struct drm_encoder *encoder;
+ struct drm_encoder *encoder = NULL;
struct drm_encoder_helper_funcs *encoder_funcs;
struct drm_mode_object *obj;
int i;
@@ -283,9 +642,29 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
radeon_i2c_do_lock(radeon_connector, 1);
dret = radeon_ddc_probe(radeon_connector);
radeon_i2c_do_lock(radeon_connector, 0);
- if (dret)
- ret = connector_status_connected;
- else {
+ if (dret) {
+ radeon_i2c_do_lock(radeon_connector, 1);
+ radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
+ radeon_i2c_do_lock(radeon_connector, 0);
+
+ if (!radeon_connector->edid) {
+ DRM_ERROR("DDC responded but not EDID found for %s\n",
+ drm_get_connector_name(connector));
+ } else {
+ radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
+
+ /* if this isn't a digital monitor
+ then we need to make sure we don't have any
+ TV conflicts */
+ ret = connector_status_connected;
+ }
+ }
+
+ if ((ret == connector_status_connected) && (radeon_connector->use_digital == true))
+ goto out;
+
+ /* find analog encoder */
+ if (radeon_connector->dac_load_detect) {
for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
if (connector->encoder_ids[i] == 0)
break;
@@ -300,15 +679,23 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
encoder_funcs = encoder->helper_private;
if (encoder_funcs->detect) {
- ret = encoder_funcs->detect(encoder, connector);
- if (ret == connector_status_connected) {
- radeon_connector->use_digital = 0;
- break;
+ if (ret != connector_status_connected) {
+ ret = encoder_funcs->detect(encoder, connector);
+ if (ret == connector_status_connected) {
+ radeon_connector->use_digital = false;
+ }
}
+ break;
}
}
}
+ if ((ret == connector_status_connected) && (radeon_connector->use_digital == false) &&
+ encoder) {
+ ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);
+ }
+
+out:
/* updated in get modes as well since we need to know if it's analog or digital */
radeon_connector_update_scratch_regs(connector, ret);
return ret;
@@ -332,7 +719,7 @@ struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector)
encoder = obj_to_encoder(obj);
- if (radeon_connector->use_digital) {
+ if (radeon_connector->use_digital == true) {
if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
return encoder;
} else {
@@ -379,16 +766,14 @@ radeon_add_atom_connector(struct drm_device *dev,
bool linkb,
uint32_t igp_lane_info)
{
+ struct radeon_device *rdev = dev->dev_private;
struct drm_connector *connector;
struct radeon_connector *radeon_connector;
struct radeon_connector_atom_dig *radeon_dig_connector;
uint32_t subpixel_order = SubPixelNone;
/* fixme - tv/cv/din */
- if ((connector_type == DRM_MODE_CONNECTOR_Unknown) ||
- (connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
- (connector_type == DRM_MODE_CONNECTOR_Composite) ||
- (connector_type == DRM_MODE_CONNECTOR_9PinDIN))
+ if (connector_type == DRM_MODE_CONNECTOR_Unknown)
return;
/* see if we already added it */
@@ -417,6 +802,9 @@ radeon_add_atom_connector(struct drm_device *dev,
if (!radeon_connector->ddc_bus)
goto failed;
}
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.load_detect_property,
+ 1);
break;
case DRM_MODE_CONNECTOR_DVIA:
drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
@@ -426,6 +814,9 @@ radeon_add_atom_connector(struct drm_device *dev,
if (!radeon_connector->ddc_bus)
goto failed;
}
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.load_detect_property,
+ 1);
break;
case DRM_MODE_CONNECTOR_DVII:
case DRM_MODE_CONNECTOR_DVID:
@@ -443,6 +834,12 @@ radeon_add_atom_connector(struct drm_device *dev,
goto failed;
}
subpixel_order = SubPixelHorizontalRGB;
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.coherent_mode_property,
+ 1);
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.load_detect_property,
+ 1);
break;
case DRM_MODE_CONNECTOR_HDMIA:
case DRM_MODE_CONNECTOR_HDMIB:
@@ -459,6 +856,9 @@ radeon_add_atom_connector(struct drm_device *dev,
if (!radeon_connector->ddc_bus)
goto failed;
}
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.coherent_mode_property,
+ 1);
subpixel_order = SubPixelHorizontalRGB;
break;
case DRM_MODE_CONNECTOR_DisplayPort:
@@ -480,6 +880,13 @@ radeon_add_atom_connector(struct drm_device *dev,
case DRM_MODE_CONNECTOR_SVIDEO:
case DRM_MODE_CONNECTOR_Composite:
case DRM_MODE_CONNECTOR_9PinDIN:
+ if (radeon_tv == 1) {
+ drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
+ drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
+ }
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.load_detect_property,
+ 1);
break;
case DRM_MODE_CONNECTOR_LVDS:
radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
@@ -495,6 +902,10 @@ radeon_add_atom_connector(struct drm_device *dev,
if (!radeon_connector->ddc_bus)
goto failed;
}
+ drm_mode_create_scaling_mode_property(dev);
+ drm_connector_attach_property(&radeon_connector->base,
+ dev->mode_config.scaling_mode_property,
+ DRM_MODE_SCALE_FULLSCREEN);
subpixel_order = SubPixelHorizontalRGB;
break;
}
@@ -517,15 +928,13 @@ radeon_add_legacy_connector(struct drm_device *dev,
int connector_type,
struct radeon_i2c_bus_rec *i2c_bus)
{
+ struct radeon_device *rdev = dev->dev_private;
struct drm_connector *connector;
struct radeon_connector *radeon_connector;
uint32_t subpixel_order = SubPixelNone;
/* fixme - tv/cv/din */
- if ((connector_type == DRM_MODE_CONNECTOR_Unknown) ||
- (connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
- (connector_type == DRM_MODE_CONNECTOR_Composite) ||
- (connector_type == DRM_MODE_CONNECTOR_9PinDIN))
+ if (connector_type == DRM_MODE_CONNECTOR_Unknown)
return;
/* see if we already added it */
@@ -554,6 +963,9 @@ radeon_add_legacy_connector(struct drm_device *dev,
if (!radeon_connector->ddc_bus)
goto failed;
}
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.load_detect_property,
+ 1);
break;
case DRM_MODE_CONNECTOR_DVIA:
drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
@@ -563,6 +975,9 @@ radeon_add_legacy_connector(struct drm_device *dev,
if (!radeon_connector->ddc_bus)
goto failed;
}
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.load_detect_property,
+ 1);
break;
case DRM_MODE_CONNECTOR_DVII:
case DRM_MODE_CONNECTOR_DVID:
@@ -572,12 +987,22 @@ radeon_add_legacy_connector(struct drm_device *dev,
radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI");
if (!radeon_connector->ddc_bus)
goto failed;
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.load_detect_property,
+ 1);
}
subpixel_order = SubPixelHorizontalRGB;
break;
case DRM_MODE_CONNECTOR_SVIDEO:
case DRM_MODE_CONNECTOR_Composite:
case DRM_MODE_CONNECTOR_9PinDIN:
+ if (radeon_tv == 1) {
+ drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
+ drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.load_detect_property,
+ 1);
+ }
break;
case DRM_MODE_CONNECTOR_LVDS:
drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
@@ -587,6 +1012,9 @@ radeon_add_legacy_connector(struct drm_device *dev,
if (!radeon_connector->ddc_bus)
goto failed;
}
+ drm_connector_attach_property(&radeon_connector->base,
+ dev->mode_config.scaling_mode_property,
+ DRM_MODE_SCALE_FULLSCREEN);
subpixel_order = SubPixelHorizontalRGB;
break;
}
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 7a52c46..4f7afc7 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -36,10 +36,25 @@
#include "radeon_drv.h"
#include "r300_reg.h"
-#include "radeon_microcode.h"
-
#define RADEON_FIFO_DEBUG 0
+/* Firmware Names */
+#define FIRMWARE_R100 "radeon/R100_cp.bin"
+#define FIRMWARE_R200 "radeon/R200_cp.bin"
+#define FIRMWARE_R300 "radeon/R300_cp.bin"
+#define FIRMWARE_R420 "radeon/R420_cp.bin"
+#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
+#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
+#define FIRMWARE_R520 "radeon/R520_cp.bin"
+
+MODULE_FIRMWARE(FIRMWARE_R100);
+MODULE_FIRMWARE(FIRMWARE_R200);
+MODULE_FIRMWARE(FIRMWARE_R300);
+MODULE_FIRMWARE(FIRMWARE_R420);
+MODULE_FIRMWARE(FIRMWARE_RS690);
+MODULE_FIRMWARE(FIRMWARE_RS600);
+MODULE_FIRMWARE(FIRMWARE_R520);
+
static int radeon_do_cleanup_cp(struct drm_device * dev);
static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
@@ -460,37 +475,34 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
*/
/* Load the microcode for the CP */
-static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
+static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
{
- int i;
+ struct platform_device *pdev;
+ const char *fw_name = NULL;
+ int err;
+
DRM_DEBUG("\n");
- radeon_do_wait_for_idle(dev_priv);
+ pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
+ err = IS_ERR(pdev);
+ if (err) {
+ printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
+ return -EINVAL;
+ }
- RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
DRM_INFO("Loading R100 Microcode\n");
- for (i = 0; i < 256; i++) {
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
- R100_cp_microcode[i][1]);
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
- R100_cp_microcode[i][0]);
- }
+ fw_name = FIRMWARE_R100;
} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
DRM_INFO("Loading R200 Microcode\n");
- for (i = 0; i < 256; i++) {
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
- R200_cp_microcode[i][1]);
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
- R200_cp_microcode[i][0]);
- }
+ fw_name = FIRMWARE_R200;
} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
@@ -498,39 +510,19 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
DRM_INFO("Loading R300 Microcode\n");
- for (i = 0; i < 256; i++) {
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
- R300_cp_microcode[i][1]);
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
- R300_cp_microcode[i][0]);
- }
+ fw_name = FIRMWARE_R300;
} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
DRM_INFO("Loading R400 Microcode\n");
- for (i = 0; i < 256; i++) {
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
- R420_cp_microcode[i][1]);
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
- R420_cp_microcode[i][0]);
- }
+ fw_name = FIRMWARE_R420;
} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
DRM_INFO("Loading RS690/RS740 Microcode\n");
- for (i = 0; i < 256; i++) {
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
- RS690_cp_microcode[i][1]);
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
- RS690_cp_microcode[i][0]);
- }
+ fw_name = FIRMWARE_RS690;
} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
DRM_INFO("Loading RS600 Microcode\n");
- for (i = 0; i < 256; i++) {
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
- RS600_cp_microcode[i][1]);
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
- RS600_cp_microcode[i][0]);
- }
+ fw_name = FIRMWARE_RS600;
} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
@@ -538,11 +530,41 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
DRM_INFO("Loading R500 Microcode\n");
- for (i = 0; i < 256; i++) {
+ fw_name = FIRMWARE_R520;
+ }
+
+ err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
+ platform_device_unregister(pdev);
+ if (err) {
+ printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
+ fw_name);
+ } else if (dev_priv->me_fw->size % 8) {
+ printk(KERN_ERR
+ "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
+ dev_priv->me_fw->size, fw_name);
+ err = -EINVAL;
+ release_firmware(dev_priv->me_fw);
+ dev_priv->me_fw = NULL;
+ }
+ return err;
+}
+
+static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
+{
+ const __be32 *fw_data;
+ int i, size;
+
+ radeon_do_wait_for_idle(dev_priv);
+
+ if (dev_priv->me_fw) {
+ size = dev_priv->me_fw->size / 4;
+ fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
+ RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
+ for (i = 0; i < size; i += 2) {
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
- R520_cp_microcode[i][1]);
+ be32_to_cpup(&fw_data[i]));
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
- R520_cp_microcode[i][0]);
+ be32_to_cpup(&fw_data[i + 1]));
}
}
}
@@ -594,6 +616,18 @@ static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
dev_priv->cp_running = 1;
+ /* on r420, any DMA from CP to system memory while 2D is active
+ * can cause a hang. workaround is to queue a CP RESYNC token
+ */
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
+ BEGIN_RING(3);
+ OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
+ OUT_RING(5); /* scratch reg 5 */
+ OUT_RING(0xdeadbeef);
+ ADVANCE_RING();
+ COMMIT_RING();
+ }
+
BEGIN_RING(8);
/* isync can only be written through cp on r5xx write it here */
OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
@@ -631,8 +665,19 @@ static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
*/
static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
{
+ RING_LOCALS;
DRM_DEBUG("\n");
+ /* finish the pending CP_RESYNC token */
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
+ BEGIN_RING(2);
+ OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+ OUT_RING(R300_RB3D_DC_FINISH);
+ ADVANCE_RING();
+ COMMIT_RING();
+ radeon_do_wait_for_idle(dev_priv);
+ }
+
RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
dev_priv->cp_running = 0;
@@ -1495,6 +1540,14 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
radeon_set_pcigart(dev_priv, 1);
}
+ if (!dev_priv->me_fw) {
+ int err = radeon_cp_init_microcode(dev_priv);
+ if (err) {
+ DRM_ERROR("Failed to load firmware!\n");
+ radeon_do_cleanup_cp(dev);
+ return err;
+ }
+ }
radeon_cp_load_microcode(dev_priv);
radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
@@ -1764,6 +1817,14 @@ void radeon_do_release(struct drm_device * dev)
r600_do_cleanup_cp(dev);
else
radeon_do_cleanup_cp(dev);
+ if (dev_priv->me_fw) {
+ release_firmware(dev_priv->me_fw);
+ dev_priv->me_fw = NULL;
+ }
+ if (dev_priv->pfp_fw) {
+ release_firmware(dev_priv->pfp_fw);
+ dev_priv->pfp_fw = NULL;
+ }
}
}
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index a169067..12f5990 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -145,7 +145,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
size = p->chunks[i].length_dw * sizeof(uint32_t);
- p->chunks[i].kdata = kzalloc(size, GFP_KERNEL);
+ p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
if (p->chunks[i].kdata == NULL) {
return -ENOMEM;
}
@@ -185,6 +185,7 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
mutex_unlock(&parser->rdev->ddev->struct_mutex);
}
}
+ kfree(parser->track);
kfree(parser->relocs);
kfree(parser->relocs_ptr);
for (i = 0; i < parser->nchunks; i++) {
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 7693f7c..daf5db7 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -29,6 +29,7 @@
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/radeon_drm.h>
+#include <linux/vgaarb.h>
#include "radeon_reg.h"
#include "radeon.h"
#include "radeon_asic.h"
@@ -37,7 +38,7 @@
/*
* Clear GPU surface registers.
*/
-static void radeon_surface_init(struct radeon_device *rdev)
+void radeon_surface_init(struct radeon_device *rdev)
{
/* FIXME: check this out */
if (rdev->family < CHIP_R600) {
@@ -56,7 +57,7 @@ static void radeon_surface_init(struct radeon_device *rdev)
/*
* GPU scratch registers helpers function.
*/
-static void radeon_scratch_init(struct radeon_device *rdev)
+void radeon_scratch_init(struct radeon_device *rdev)
{
int i;
@@ -156,16 +157,18 @@ int radeon_mc_setup(struct radeon_device *rdev)
tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
rdev->mc.gtt_location = tmp;
}
- DRM_INFO("radeon: VRAM %uM\n", rdev->mc.real_vram_size >> 20);
+ rdev->mc.vram_start = rdev->mc.vram_location;
+ rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
+ rdev->mc.gtt_start = rdev->mc.gtt_location;
+ rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
+ DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
- rdev->mc.vram_location,
- rdev->mc.vram_location + rdev->mc.mc_vram_size - 1);
- if (rdev->mc.real_vram_size != rdev->mc.mc_vram_size)
- DRM_INFO("radeon: VRAM less than aperture workaround enabled\n");
- DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
+ (unsigned)rdev->mc.vram_location,
+ (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
+ DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
- rdev->mc.gtt_location,
- rdev->mc.gtt_location + rdev->mc.gtt_size - 1);
+ (unsigned)rdev->mc.gtt_location,
+ (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
return 0;
}
@@ -173,7 +176,7 @@ int radeon_mc_setup(struct radeon_device *rdev)
/*
* GPU helpers function.
*/
-static bool radeon_card_posted(struct radeon_device *rdev)
+bool radeon_card_posted(struct radeon_device *rdev)
{
uint32_t reg;
@@ -205,6 +208,31 @@ static bool radeon_card_posted(struct radeon_device *rdev)
}
+int radeon_dummy_page_init(struct radeon_device *rdev)
+{
+ rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
+ if (rdev->dummy_page.page == NULL)
+ return -ENOMEM;
+ rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
+ 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+ if (!rdev->dummy_page.addr) {
+ __free_page(rdev->dummy_page.page);
+ rdev->dummy_page.page = NULL;
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+void radeon_dummy_page_fini(struct radeon_device *rdev)
+{
+ if (rdev->dummy_page.page == NULL)
+ return;
+ pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
+ PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+ __free_page(rdev->dummy_page.page);
+ rdev->dummy_page.page = NULL;
+}
+
/*
* Registers accessors functions.
@@ -243,6 +271,10 @@ void radeon_register_accessor_init(struct radeon_device *rdev)
rdev->pll_rreg = &r100_pll_rreg;
rdev->pll_wreg = &r100_pll_wreg;
}
+ if (rdev->family >= CHIP_R420) {
+ rdev->mc_rreg = &r420_mc_rreg;
+ rdev->mc_wreg = &r420_mc_wreg;
+ }
if (rdev->family >= CHIP_RV515) {
rdev->mc_rreg = &rv515_mc_rreg;
rdev->mc_wreg = &rv515_mc_wreg;
@@ -289,6 +321,14 @@ int radeon_asic_init(struct radeon_device *rdev)
case CHIP_RV350:
case CHIP_RV380:
rdev->asic = &r300_asic;
+ if (rdev->flags & RADEON_IS_PCIE) {
+ rdev->asic->gart_init = &rv370_pcie_gart_init;
+ rdev->asic->gart_fini = &rv370_pcie_gart_fini;
+ rdev->asic->gart_enable = &rv370_pcie_gart_enable;
+ rdev->asic->gart_disable = &rv370_pcie_gart_disable;
+ rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
+ rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
+ }
break;
case CHIP_R420:
case CHIP_R423:
@@ -323,9 +363,15 @@ int radeon_asic_init(struct radeon_device *rdev)
case CHIP_RV635:
case CHIP_RV670:
case CHIP_RS780:
+ case CHIP_RS880:
+ rdev->asic = &r600_asic;
+ break;
case CHIP_RV770:
case CHIP_RV730:
case CHIP_RV710:
+ case CHIP_RV740:
+ rdev->asic = &rv770_asic;
+ break;
default:
/* FIXME: not supported yet */
return -EINVAL;
@@ -341,7 +387,6 @@ int radeon_clocks_init(struct radeon_device *rdev)
{
int r;
- radeon_get_clock_info(rdev->ddev);
r = radeon_static_clocks_init(rdev->ddev);
if (r) {
return r;
@@ -436,10 +481,18 @@ void radeon_combios_fini(struct radeon_device *rdev)
{
}
-int radeon_modeset_init(struct radeon_device *rdev);
-void radeon_modeset_fini(struct radeon_device *rdev);
-
+/* if we get transitioned to only one device, tak VGA back */
+static unsigned int radeon_vga_set_decode(void *cookie, bool state)
+{
+ struct radeon_device *rdev = cookie;
+ radeon_vga_set_state(rdev, state);
+ if (state)
+ return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
+ VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
+ else
+ return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
+}
/*
* Radeon device.
*/
@@ -448,11 +501,12 @@ int radeon_device_init(struct radeon_device *rdev,
struct pci_dev *pdev,
uint32_t flags)
{
- int r, ret;
+ int r;
int dma_bits;
DRM_INFO("radeon: Initializing kernel modesetting.\n");
rdev->shutdown = false;
+ rdev->dev = &pdev->dev;
rdev->ddev = ddev;
rdev->pdev = pdev;
rdev->flags = flags;
@@ -461,37 +515,47 @@ int radeon_device_init(struct radeon_device *rdev,
rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
rdev->gpu_lockup = false;
+ rdev->accel_working = false;
/* mutex initialization are all done here so we
* can recall function without having locking issues */
mutex_init(&rdev->cs_mutex);
mutex_init(&rdev->ib_pool.mutex);
mutex_init(&rdev->cp.mutex);
rwlock_init(&rdev->fence_drv.lock);
+ INIT_LIST_HEAD(&rdev->gem.objects);
+
+ /* Set asic functions */
+ r = radeon_asic_init(rdev);
+ if (r) {
+ return r;
+ }
if (radeon_agpmode == -1) {
rdev->flags &= ~RADEON_IS_AGP;
- if (rdev->family > CHIP_RV515 ||
+ if (rdev->family >= CHIP_RV515 ||
rdev->family == CHIP_RV380 ||
rdev->family == CHIP_RV410 ||
rdev->family == CHIP_R423) {
DRM_INFO("Forcing AGP to PCIE mode\n");
rdev->flags |= RADEON_IS_PCIE;
+ rdev->asic->gart_init = &rv370_pcie_gart_init;
+ rdev->asic->gart_fini = &rv370_pcie_gart_fini;
+ rdev->asic->gart_enable = &rv370_pcie_gart_enable;
+ rdev->asic->gart_disable = &rv370_pcie_gart_disable;
+ rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
+ rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
} else {
DRM_INFO("Forcing AGP to PCI mode\n");
rdev->flags |= RADEON_IS_PCI;
+ rdev->asic->gart_init = &r100_pci_gart_init;
+ rdev->asic->gart_fini = &r100_pci_gart_fini;
+ rdev->asic->gart_enable = &r100_pci_gart_enable;
+ rdev->asic->gart_disable = &r100_pci_gart_disable;
+ rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
+ rdev->asic->gart_set_page = &r100_pci_gart_set_page;
}
}
- /* Set asic functions */
- r = radeon_asic_init(rdev);
- if (r) {
- return r;
- }
- r = radeon_init(rdev);
- if (r) {
- return r;
- }
-
/* set DMA mask + need_dma32 flags.
* PCIE - can handle 40-bits.
* IGP - can handle 40-bits (in theory)
@@ -521,156 +585,150 @@ int radeon_device_init(struct radeon_device *rdev,
DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
- /* Setup errata flags */
- radeon_errata(rdev);
- /* Initialize scratch registers */
- radeon_scratch_init(rdev);
- /* Initialize surface registers */
- radeon_surface_init(rdev);
-
- /* TODO: disable VGA need to use VGA request */
- /* BIOS*/
- if (!radeon_get_bios(rdev)) {
- if (ASIC_IS_AVIVO(rdev))
- return -EINVAL;
- }
- if (rdev->is_atom_bios) {
- r = radeon_atombios_init(rdev);
- if (r) {
- return r;
- }
- } else {
- r = radeon_combios_init(rdev);
- if (r) {
- return r;
- }
- }
- /* Reset gpu before posting otherwise ATOM will enter infinite loop */
- if (radeon_gpu_reset(rdev)) {
- /* FIXME: what do we want to do here ? */
- }
- /* check if cards are posted or not */
- if (!radeon_card_posted(rdev) && rdev->bios) {
- DRM_INFO("GPU not posted. posting now...\n");
- if (rdev->is_atom_bios) {
- atom_asic_init(rdev->mode_info.atom_context);
- } else {
- radeon_combios_asic_init(rdev->ddev);
- }
- }
- /* Initialize clocks */
- r = radeon_clocks_init(rdev);
- if (r) {
- return r;
- }
- /* Get vram informations */
- radeon_vram_info(rdev);
-
- /* Add an MTRR for the VRAM */
- rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
- MTRR_TYPE_WRCOMB, 1);
- DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
- rdev->mc.real_vram_size >> 20,
- (unsigned)rdev->mc.aper_size >> 20);
- DRM_INFO("RAM width %dbits %cDR\n",
- rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
- /* Initialize memory controller (also test AGP) */
- r = radeon_mc_init(rdev);
- if (r) {
- return r;
- }
- /* Fence driver */
- r = radeon_fence_driver_init(rdev);
- if (r) {
- return r;
- }
- r = radeon_irq_kms_init(rdev);
+ rdev->new_init_path = false;
+ r = radeon_init(rdev);
if (r) {
return r;
}
- /* Memory manager */
- r = radeon_object_init(rdev);
+
+ /* if we have > 1 VGA cards, then disable the radeon VGA resources */
+ r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
if (r) {
- return r;
- }
- /* Initialize GART (initialize after TTM so we can allocate
- * memory through TTM but finalize after TTM) */
- r = radeon_gart_enable(rdev);
- if (!r) {
- r = radeon_gem_init(rdev);
+ return -EINVAL;
}
- /* 1M ring buffer */
- if (!r) {
- r = radeon_cp_init(rdev, 1024 * 1024);
- }
- if (!r) {
- r = radeon_wb_init(rdev);
+ if (!rdev->new_init_path) {
+ /* Setup errata flags */
+ radeon_errata(rdev);
+ /* Initialize scratch registers */
+ radeon_scratch_init(rdev);
+ /* Initialize surface registers */
+ radeon_surface_init(rdev);
+
+ /* BIOS*/
+ if (!radeon_get_bios(rdev)) {
+ if (ASIC_IS_AVIVO(rdev))
+ return -EINVAL;
+ }
+ if (rdev->is_atom_bios) {
+ r = radeon_atombios_init(rdev);
+ if (r) {
+ return r;
+ }
+ } else {
+ r = radeon_combios_init(rdev);
+ if (r) {
+ return r;
+ }
+ }
+ /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+ if (radeon_gpu_reset(rdev)) {
+ /* FIXME: what do we want to do here ? */
+ }
+ /* check if cards are posted or not */
+ if (!radeon_card_posted(rdev) && rdev->bios) {
+ DRM_INFO("GPU not posted. posting now...\n");
+ if (rdev->is_atom_bios) {
+ atom_asic_init(rdev->mode_info.atom_context);
+ } else {
+ radeon_combios_asic_init(rdev->ddev);
+ }
+ }
+ /* Get clock & vram information */
+ radeon_get_clock_info(rdev->ddev);
+ radeon_vram_info(rdev);
+ /* Initialize clocks */
+ r = radeon_clocks_init(rdev);
if (r) {
- DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
return r;
}
- }
- if (!r) {
- r = radeon_ib_pool_init(rdev);
+
+ /* Initialize memory controller (also test AGP) */
+ r = radeon_mc_init(rdev);
if (r) {
- DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
return r;
}
- }
- if (!r) {
- r = radeon_ib_test(rdev);
+ /* Fence driver */
+ r = radeon_fence_driver_init(rdev);
if (r) {
- DRM_ERROR("radeon: failled testing IB (%d).\n", r);
return r;
}
+ r = radeon_irq_kms_init(rdev);
+ if (r) {
+ return r;
+ }
+ /* Memory manager */
+ r = radeon_object_init(rdev);
+ if (r) {
+ return r;
+ }
+ r = radeon_gpu_gart_init(rdev);
+ if (r)
+ return r;
+ /* Initialize GART (initialize after TTM so we can allocate
+ * memory through TTM but finalize after TTM) */
+ r = radeon_gart_enable(rdev);
+ if (r)
+ return 0;
+ r = radeon_gem_init(rdev);
+ if (r)
+ return 0;
+
+ /* 1M ring buffer */
+ r = radeon_cp_init(rdev, 1024 * 1024);
+ if (r)
+ return 0;
+ r = radeon_wb_init(rdev);
+ if (r)
+ DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
+ r = radeon_ib_pool_init(rdev);
+ if (r)
+ return 0;
+ r = radeon_ib_test(rdev);
+ if (r)
+ return 0;
+ rdev->accel_working = true;
}
- ret = r;
- r = radeon_modeset_init(rdev);
- if (r) {
- return r;
- }
- if (!ret) {
- DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
- }
+ DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
if (radeon_testing) {
radeon_test_moves(rdev);
}
if (radeon_benchmarking) {
radeon_benchmark(rdev);
}
- return ret;
+ return 0;
}
void radeon_device_fini(struct radeon_device *rdev)
{
- if (rdev == NULL || rdev->rmmio == NULL) {
- return;
- }
DRM_INFO("radeon: finishing device.\n");
rdev->shutdown = true;
/* Order matter so becarefull if you rearrange anythings */
- radeon_modeset_fini(rdev);
- radeon_ib_pool_fini(rdev);
- radeon_cp_fini(rdev);
- radeon_wb_fini(rdev);
- radeon_gem_fini(rdev);
- radeon_object_fini(rdev);
- /* mc_fini must be after object_fini */
- radeon_mc_fini(rdev);
+ if (!rdev->new_init_path) {
+ radeon_ib_pool_fini(rdev);
+ radeon_cp_fini(rdev);
+ radeon_wb_fini(rdev);
+ radeon_gpu_gart_fini(rdev);
+ radeon_gem_fini(rdev);
+ radeon_mc_fini(rdev);
#if __OS_HAS_AGP
- radeon_agp_fini(rdev);
+ radeon_agp_fini(rdev);
#endif
- radeon_irq_kms_fini(rdev);
- radeon_fence_driver_fini(rdev);
- radeon_clocks_fini(rdev);
- if (rdev->is_atom_bios) {
- radeon_atombios_fini(rdev);
+ radeon_irq_kms_fini(rdev);
+ vga_client_register(rdev->pdev, NULL, NULL, NULL);
+ radeon_fence_driver_fini(rdev);
+ radeon_clocks_fini(rdev);
+ radeon_object_fini(rdev);
+ if (rdev->is_atom_bios) {
+ radeon_atombios_fini(rdev);
+ } else {
+ radeon_combios_fini(rdev);
+ }
+ kfree(rdev->bios);
+ rdev->bios = NULL;
} else {
- radeon_combios_fini(rdev);
+ radeon_fini(rdev);
}
- kfree(rdev->bios);
- rdev->bios = NULL;
iounmap(rdev->rmmio);
rdev->rmmio = NULL;
}
@@ -708,15 +766,19 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
/* wait for gpu to finish processing current batch */
radeon_fence_wait_last(rdev);
- radeon_cp_disable(rdev);
- radeon_gart_disable(rdev);
+ radeon_save_bios_scratch_regs(rdev);
+ if (!rdev->new_init_path) {
+ radeon_cp_disable(rdev);
+ radeon_gart_disable(rdev);
+ rdev->irq.sw_int = false;
+ radeon_irq_set(rdev);
+ } else {
+ radeon_suspend(rdev);
+ }
/* evict remaining vram memory */
radeon_object_evict_vram(rdev);
- rdev->irq.sw_int = false;
- radeon_irq_set(rdev);
-
pci_save_state(dev->pdev);
if (state.event == PM_EVENT_SUSPEND) {
/* Shut down the device */
@@ -743,38 +805,43 @@ int radeon_resume_kms(struct drm_device *dev)
}
pci_set_master(dev->pdev);
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
- if (radeon_gpu_reset(rdev)) {
- /* FIXME: what do we want to do here ? */
- }
- /* post card */
- if (rdev->is_atom_bios) {
- atom_asic_init(rdev->mode_info.atom_context);
+ if (!rdev->new_init_path) {
+ if (radeon_gpu_reset(rdev)) {
+ /* FIXME: what do we want to do here ? */
+ }
+ /* post card */
+ if (rdev->is_atom_bios) {
+ atom_asic_init(rdev->mode_info.atom_context);
+ } else {
+ radeon_combios_asic_init(rdev->ddev);
+ }
+ /* Initialize clocks */
+ r = radeon_clocks_init(rdev);
+ if (r) {
+ release_console_sem();
+ return r;
+ }
+ /* Enable IRQ */
+ rdev->irq.sw_int = true;
+ radeon_irq_set(rdev);
+ /* Initialize GPU Memory Controller */
+ r = radeon_mc_init(rdev);
+ if (r) {
+ goto out;
+ }
+ r = radeon_gart_enable(rdev);
+ if (r) {
+ goto out;
+ }
+ r = radeon_cp_init(rdev, rdev->cp.ring_size);
+ if (r) {
+ goto out;
+ }
} else {
- radeon_combios_asic_init(rdev->ddev);
- }
- /* Initialize clocks */
- r = radeon_clocks_init(rdev);
- if (r) {
- release_console_sem();
- return r;
- }
- /* Enable IRQ */
- rdev->irq.sw_int = true;
- radeon_irq_set(rdev);
- /* Initialize GPU Memory Controller */
- r = radeon_mc_init(rdev);
- if (r) {
- goto out;
- }
- r = radeon_gart_enable(rdev);
- if (r) {
- goto out;
- }
- r = radeon_cp_init(rdev, rdev->cp.ring_size);
- if (r) {
- goto out;
+ radeon_resume(rdev);
}
out:
+ radeon_restore_bios_scratch_regs(rdev);
fb_set_suspend(rdev->fbdev_info, 0);
release_console_sem();
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index a8fa1bb..5d8141b 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -158,9 +158,6 @@ static void radeon_crtc_destroy(struct drm_crtc *crtc)
{
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
- if (radeon_crtc->mode_set.mode) {
- drm_mode_destroy(crtc->dev, radeon_crtc->mode_set.mode);
- }
drm_crtc_cleanup(crtc);
kfree(radeon_crtc);
}
@@ -189,9 +186,11 @@ static void radeon_crtc_init(struct drm_device *dev, int index)
radeon_crtc->crtc_id = index;
rdev->mode_info.crtcs[index] = radeon_crtc;
+#if 0
radeon_crtc->mode_set.crtc = &radeon_crtc->base;
radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
radeon_crtc->mode_set.num_connectors = 0;
+#endif
for (i = 0; i < 256; i++) {
radeon_crtc->lut_r[i] = i << 2;
@@ -313,7 +312,7 @@ static void radeon_print_display_setup(struct drm_device *dev)
}
}
-bool radeon_setup_enc_conn(struct drm_device *dev)
+static bool radeon_setup_enc_conn(struct drm_device *dev)
{
struct radeon_device *rdev = dev->dev_private;
struct drm_connector *drm_connector;
@@ -347,9 +346,13 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
if (!radeon_connector->ddc_bus)
return -1;
- radeon_i2c_do_lock(radeon_connector, 1);
- edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
- radeon_i2c_do_lock(radeon_connector, 0);
+ if (!radeon_connector->edid) {
+ radeon_i2c_do_lock(radeon_connector, 1);
+ edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
+ radeon_i2c_do_lock(radeon_connector, 0);
+ } else
+ edid = radeon_connector->edid;
+
if (edid) {
/* update digital bits here */
if (edid->input & DRM_EDID_INPUT_DIGITAL)
@@ -362,7 +365,7 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
return ret;
}
drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
- return -1;
+ return 0;
}
static int radeon_ddc_dump(struct drm_connector *connector)
@@ -620,6 +623,83 @@ static const struct drm_mode_config_funcs radeon_mode_funcs = {
.fb_changed = radeonfb_probe,
};
+struct drm_prop_enum_list {
+ int type;
+ char *name;
+};
+
+static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
+{ { 0, "driver" },
+ { 1, "bios" },
+};
+
+static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
+{ { TV_STD_NTSC, "ntsc" },
+ { TV_STD_PAL, "pal" },
+ { TV_STD_PAL_M, "pal-m" },
+ { TV_STD_PAL_60, "pal-60" },
+ { TV_STD_NTSC_J, "ntsc-j" },
+ { TV_STD_SCART_PAL, "scart-pal" },
+ { TV_STD_PAL_CN, "pal-cn" },
+ { TV_STD_SECAM, "secam" },
+};
+
+int radeon_modeset_create_props(struct radeon_device *rdev)
+{
+ int i, sz;
+
+ if (rdev->is_atom_bios) {
+ rdev->mode_info.coherent_mode_property =
+ drm_property_create(rdev->ddev,
+ DRM_MODE_PROP_RANGE,
+ "coherent", 2);
+ if (!rdev->mode_info.coherent_mode_property)
+ return -ENOMEM;
+
+ rdev->mode_info.coherent_mode_property->values[0] = 0;
+ rdev->mode_info.coherent_mode_property->values[0] = 1;
+ }
+
+ if (!ASIC_IS_AVIVO(rdev)) {
+ sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
+ rdev->mode_info.tmds_pll_property =
+ drm_property_create(rdev->ddev,
+ DRM_MODE_PROP_ENUM,
+ "tmds_pll", sz);
+ for (i = 0; i < sz; i++) {
+ drm_property_add_enum(rdev->mode_info.tmds_pll_property,
+ i,
+ radeon_tmds_pll_enum_list[i].type,
+ radeon_tmds_pll_enum_list[i].name);
+ }
+ }
+
+ rdev->mode_info.load_detect_property =
+ drm_property_create(rdev->ddev,
+ DRM_MODE_PROP_RANGE,
+ "load detection", 2);
+ if (!rdev->mode_info.load_detect_property)
+ return -ENOMEM;
+ rdev->mode_info.load_detect_property->values[0] = 0;
+ rdev->mode_info.load_detect_property->values[0] = 1;
+
+ drm_mode_create_scaling_mode_property(rdev->ddev);
+
+ sz = ARRAY_SIZE(radeon_tv_std_enum_list);
+ rdev->mode_info.tv_std_property =
+ drm_property_create(rdev->ddev,
+ DRM_MODE_PROP_ENUM,
+ "tv standard", sz);
+ for (i = 0; i < sz; i++) {
+ drm_property_add_enum(rdev->mode_info.tv_std_property,
+ i,
+ radeon_tv_std_enum_list[i].type,
+ radeon_tv_std_enum_list[i].name);
+ }
+
+ return 0;
+}
+
int radeon_modeset_init(struct radeon_device *rdev)
{
int num_crtc = 2, i;
@@ -640,6 +720,10 @@ int radeon_modeset_init(struct radeon_device *rdev)
rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
+ ret = radeon_modeset_create_props(rdev);
+ if (ret) {
+ return ret;
+ }
/* allocate crtcs - TODO single crtc */
for (i = 0; i < num_crtc; i++) {
radeon_crtc_init(rdev->ddev, i);
@@ -678,7 +762,6 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
continue;
if (first) {
radeon_crtc->rmx_type = radeon_encoder->rmx_type;
- radeon_crtc->devices = radeon_encoder->devices;
memcpy(&radeon_crtc->native_mode,
&radeon_encoder->native_mode,
sizeof(struct radeon_native_mode));
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 0bd5879..50fce49 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -38,7 +38,6 @@
#include <linux/console.h>
-#if defined(CONFIG_DRM_RADEON_KMS)
/*
* KMS wrapper.
*/
@@ -77,11 +76,9 @@ int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
int radeon_debugfs_init(struct drm_minor *minor);
void radeon_debugfs_cleanup(struct drm_minor *minor);
#endif
-#endif
int radeon_no_wb;
-#if defined(CONFIG_DRM_RADEON_KMS)
int radeon_modeset = -1;
int radeon_dynclks = -1;
int radeon_r4xx_atom = 0;
@@ -91,12 +88,11 @@ int radeon_gart_size = 512; /* default gart size */
int radeon_benchmarking = 0;
int radeon_testing = 0;
int radeon_connector_table = 0;
-#endif
+int radeon_tv = 1;
MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
module_param_named(no_wb, radeon_no_wb, int, 0444);
-#if defined(CONFIG_DRM_RADEON_KMS)
MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
module_param_named(modeset, radeon_modeset, int, 0400);
@@ -123,7 +119,9 @@ module_param_named(test, radeon_testing, int, 0444);
MODULE_PARM_DESC(connector_table, "Force connector table");
module_param_named(connector_table, radeon_connector_table, int, 0444);
-#endif
+
+MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
+module_param_named(tv, radeon_tv, int, 0444);
static int radeon_suspend(struct drm_device *dev, pm_message_t state)
{
@@ -215,7 +213,6 @@ static struct drm_driver driver_old = {
.patchlevel = DRIVER_PATCHLEVEL,
};
-#if defined(CONFIG_DRM_RADEON_KMS)
static struct drm_driver kms_driver;
static int __devinit
@@ -289,7 +286,7 @@ static struct drm_driver kms_driver = {
.poll = drm_poll,
.fasync = drm_fasync,
#ifdef CONFIG_COMPAT
- .compat_ioctl = NULL,
+ .compat_ioctl = radeon_kms_compat_ioctl,
#endif
},
@@ -309,7 +306,6 @@ static struct drm_driver kms_driver = {
.minor = KMS_DRIVER_MINOR,
.patchlevel = KMS_DRIVER_PATCHLEVEL,
};
-#endif
static struct drm_driver *driver;
@@ -317,7 +313,6 @@ static int __init radeon_init(void)
{
driver = &driver_old;
driver->num_ioctls = radeon_max_ioctl;
-#if defined(CONFIG_DRM_RADEON_KMS)
#ifdef CONFIG_VGA_CONSOLE
if (vgacon_text_force() && radeon_modeset == -1) {
DRM_INFO("VGACON disable radeon kernel modesetting.\n");
@@ -328,8 +323,13 @@ static int __init radeon_init(void)
#endif
/* if enabled by default */
if (radeon_modeset == -1) {
- DRM_INFO("radeon default to kernel modesetting.\n");
+#ifdef CONFIG_DRM_RADEON_KMS
+ DRM_INFO("radeon defaulting to kernel modesetting.\n");
radeon_modeset = 1;
+#else
+ DRM_INFO("radeon defaulting to userspace modesetting.\n");
+ radeon_modeset = 0;
+#endif
}
if (radeon_modeset == 1) {
DRM_INFO("radeon kernel modesetting enabled.\n");
@@ -339,7 +339,6 @@ static int __init radeon_init(void)
}
/* if the vga console setting is enabled still
* let modprobe override it */
-#endif
return drm_init(driver);
}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 6fa32da..cb0cfe4 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -31,6 +31,9 @@
#ifndef __RADEON_DRV_H__
#define __RADEON_DRV_H__
+#include <linux/firmware.h>
+#include <linux/platform_device.h>
+
/* General customization:
*/
@@ -353,6 +356,14 @@ typedef struct drm_radeon_private {
int r700_sc_hiz_tile_fifo_size;
int r700_sc_earlyz_tile_fifo_fize;
+ struct mutex cs_mutex;
+ u32 cs_id_scnt;
+ u32 cs_id_wcnt;
+ /* r6xx/r7xx drm blit vertex buffer */
+ struct drm_buf *blit_vb;
+
+ /* firmware */
+ const struct firmware *me_fw, *pfp_fw;
} drm_radeon_private_t;
typedef struct drm_radeon_buf_priv {
@@ -391,6 +402,9 @@ static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
(off >= gart_start && off <= gart_end));
}
+/* radeon_state.c */
+extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf);
+
/* radeon_cp.c */
extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
@@ -457,6 +471,8 @@ extern int radeon_driver_open(struct drm_device *dev,
struct drm_file *file_priv);
extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
unsigned long arg);
+extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
+ unsigned long arg);
extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
@@ -482,6 +498,22 @@ extern int r600_cp_dispatch_indirect(struct drm_device *dev,
struct drm_buf *buf, int start, int end);
extern int r600_page_table_init(struct drm_device *dev);
extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
+extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
+extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv);
+extern int r600_cp_dispatch_texture(struct drm_device *dev,
+ struct drm_file *file_priv,
+ drm_radeon_texture_t *tex,
+ drm_radeon_tex_image_t *image);
+/* r600_blit.c */
+extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv);
+extern void r600_done_blit_copy(struct drm_device *dev);
+extern void r600_blit_copy(struct drm_device *dev,
+ uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
+ int size_bytes);
+extern void r600_blit_swap(struct drm_device *dev,
+ uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
+ int sx, int sy, int dx, int dy,
+ int w, int h, int src_pitch, int dst_pitch, int cpp);
/* Flags for stats.boxes
*/
@@ -1067,6 +1099,9 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
+#define R300_CP_RESYNC_ADDR 0x0778
+#define R300_CP_RESYNC_DATA 0x077c
+
#define RADEON_AIC_CNTL 0x01d0
# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
# define RS400_MSI_REARM (1 << 3)
@@ -1109,13 +1144,71 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
-# define R600_IT_INDIRECT_BUFFER 0x00003200
-# define R600_IT_ME_INITIALIZE 0x00004400
+# define R600_IT_INDIRECT_BUFFER_END 0x00001700
+# define R600_IT_SET_PREDICATION 0x00002000
+# define R600_IT_REG_RMW 0x00002100
+# define R600_IT_COND_EXEC 0x00002200
+# define R600_IT_PRED_EXEC 0x00002300
+# define R600_IT_START_3D_CMDBUF 0x00002400
+# define R600_IT_DRAW_INDEX_2 0x00002700
+# define R600_IT_CONTEXT_CONTROL 0x00002800
+# define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900
+# define R600_IT_INDEX_TYPE 0x00002A00
+# define R600_IT_DRAW_INDEX 0x00002B00
+# define R600_IT_DRAW_INDEX_AUTO 0x00002D00
+# define R600_IT_DRAW_INDEX_IMMD 0x00002E00
+# define R600_IT_NUM_INSTANCES 0x00002F00
+# define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400
+# define R600_IT_INDIRECT_BUFFER_MP 0x00003800
+# define R600_IT_MEM_SEMAPHORE 0x00003900
+# define R600_IT_MPEG_INDEX 0x00003A00
+# define R600_IT_WAIT_REG_MEM 0x00003C00
+# define R600_IT_MEM_WRITE 0x00003D00
+# define R600_IT_INDIRECT_BUFFER 0x00003200
+# define R600_IT_CP_INTERRUPT 0x00004000
+# define R600_IT_SURFACE_SYNC 0x00004300
+# define R600_CB0_DEST_BASE_ENA (1 << 6)
+# define R600_TC_ACTION_ENA (1 << 23)
+# define R600_VC_ACTION_ENA (1 << 24)
+# define R600_CB_ACTION_ENA (1 << 25)
+# define R600_DB_ACTION_ENA (1 << 26)
+# define R600_SH_ACTION_ENA (1 << 27)
+# define R600_SMX_ACTION_ENA (1 << 28)
+# define R600_IT_ME_INITIALIZE 0x00004400
# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
-# define R600_IT_EVENT_WRITE 0x00004600
-# define R600_IT_SET_CONFIG_REG 0x00006800
-# define R600_SET_CONFIG_REG_OFFSET 0x00008000
-# define R600_SET_CONFIG_REG_END 0x0000ac00
+# define R600_IT_COND_WRITE 0x00004500
+# define R600_IT_EVENT_WRITE 0x00004600
+# define R600_IT_EVENT_WRITE_EOP 0x00004700
+# define R600_IT_ONE_REG_WRITE 0x00005700
+# define R600_IT_SET_CONFIG_REG 0x00006800
+# define R600_SET_CONFIG_REG_OFFSET 0x00008000
+# define R600_SET_CONFIG_REG_END 0x0000ac00
+# define R600_IT_SET_CONTEXT_REG 0x00006900
+# define R600_SET_CONTEXT_REG_OFFSET 0x00028000
+# define R600_SET_CONTEXT_REG_END 0x00029000
+# define R600_IT_SET_ALU_CONST 0x00006A00
+# define R600_SET_ALU_CONST_OFFSET 0x00030000
+# define R600_SET_ALU_CONST_END 0x00032000
+# define R600_IT_SET_BOOL_CONST 0x00006B00
+# define R600_SET_BOOL_CONST_OFFSET 0x0003e380
+# define R600_SET_BOOL_CONST_END 0x00040000
+# define R600_IT_SET_LOOP_CONST 0x00006C00
+# define R600_SET_LOOP_CONST_OFFSET 0x0003e200
+# define R600_SET_LOOP_CONST_END 0x0003e380
+# define R600_IT_SET_RESOURCE 0x00006D00
+# define R600_SET_RESOURCE_OFFSET 0x00038000
+# define R600_SET_RESOURCE_END 0x0003c000
+# define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0
+# define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1
+# define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2
+# define R600_SQ_TEX_VTX_VALID_BUFFER 0x3
+# define R600_IT_SET_SAMPLER 0x00006E00
+# define R600_SET_SAMPLER_OFFSET 0x0003c000
+# define R600_SET_SAMPLER_END 0x0003cff0
+# define R600_IT_SET_CTL_CONST 0x00006F00
+# define R600_SET_CTL_CONST_OFFSET 0x0003cff0
+# define R600_SET_CTL_CONST_END 0x0003e200
+# define R600_IT_SURFACE_BASE_UPDATE 0x00007300
#define RADEON_CP_PACKET_MASK 0xC0000000
#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
@@ -1593,6 +1686,52 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define R600_CB_COLOR7_BASE 0x2805c
#define R600_CB_COLOR7_FRAG 0x280fc
+#define R600_CB_COLOR0_SIZE 0x28060
+#define R600_CB_COLOR0_VIEW 0x28080
+#define R600_CB_COLOR0_INFO 0x280a0
+#define R600_CB_COLOR0_TILE 0x280c0
+#define R600_CB_COLOR0_FRAG 0x280e0
+#define R600_CB_COLOR0_MASK 0x28100
+
+#define AVIVO_D1MODE_VLINE_START_END 0x6538
+#define AVIVO_D2MODE_VLINE_START_END 0x6d38
+#define R600_CP_COHER_BASE 0x85f8
+#define R600_DB_DEPTH_BASE 0x2800c
+#define R600_SQ_PGM_START_FS 0x28894
+#define R600_SQ_PGM_START_ES 0x28880
+#define R600_SQ_PGM_START_VS 0x28858
+#define R600_SQ_PGM_RESOURCES_VS 0x28868
+#define R600_SQ_PGM_CF_OFFSET_VS 0x288d0
+#define R600_SQ_PGM_START_GS 0x2886c
+#define R600_SQ_PGM_START_PS 0x28840
+#define R600_SQ_PGM_RESOURCES_PS 0x28850
+#define R600_SQ_PGM_EXPORTS_PS 0x28854
+#define R600_SQ_PGM_CF_OFFSET_PS 0x288cc
+#define R600_VGT_DMA_BASE 0x287e8
+#define R600_VGT_DMA_BASE_HI 0x287e4
+#define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10
+#define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14
+#define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18
+#define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c
+#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44
+#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48
+#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c
+#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50
+#define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8
+#define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8
+#define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8
+#define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08
+#define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc
+#define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec
+#define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc
+#define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c
+
+#define R600_VGT_PRIMITIVE_TYPE 0x8958
+
+#define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030
+#define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240
+#define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204
+
#define R600_TC_CNTL 0x9608
# define R600_TC_L2_SIZE(x) ((x) << 5)
# define R600_L2_DISABLE_LATE_HIT (1 << 9)
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 0a92706..6216467 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -126,6 +126,23 @@ radeon_link_encoder_connector(struct drm_device *dev)
}
}
+void radeon_encoder_set_active_device(struct drm_encoder *encoder)
+{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct drm_connector *connector;
+
+ list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+ if (connector->encoder == encoder) {
+ struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+ radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
+ DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
+ radeon_encoder->active_device, radeon_encoder->devices,
+ radeon_connector->devices, encoder->encoder_type);
+ }
+ }
+}
+
static struct drm_connector *
radeon_get_connector_for_encoder(struct drm_encoder *encoder)
{
@@ -224,9 +241,12 @@ atombios_dac_setup(struct drm_encoder *encoder, int action)
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
DAC_ENCODER_CONTROL_PS_ALLOCATION args;
int index = 0, num = 0;
- /* fixme - fill in enc_priv for atom dac */
+ struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
enum radeon_tv_std tv_std = TV_STD_NTSC;
+ if (dac_info->tv_std)
+ tv_std = dac_info->tv_std;
+
memset(&args, 0, sizeof(args));
switch (radeon_encoder->encoder_id) {
@@ -244,9 +264,9 @@ atombios_dac_setup(struct drm_encoder *encoder, int action)
args.ucAction = action;
- if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
+ if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
args.ucDacStandard = ATOM_DAC1_PS2;
- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+ else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
args.ucDacStandard = ATOM_DAC1_CV;
else {
switch (tv_std) {
@@ -279,16 +299,19 @@ atombios_tv_setup(struct drm_encoder *encoder, int action)
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
TV_ENCODER_CONTROL_PS_ALLOCATION args;
int index = 0;
- /* fixme - fill in enc_priv for atom dac */
+ struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
enum radeon_tv_std tv_std = TV_STD_NTSC;
+ if (dac_info->tv_std)
+ tv_std = dac_info->tv_std;
+
memset(&args, 0, sizeof(args));
index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
args.sTVEncoder.ucAction = action;
- if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+ if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
else {
switch (tv_std) {
@@ -520,6 +543,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
switch (connector->connector_type) {
case DRM_MODE_CONNECTOR_DVII:
+ case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
return ATOM_ENCODER_MODE_HDMI;
else if (radeon_connector->use_digital)
@@ -529,7 +553,6 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
break;
case DRM_MODE_CONNECTOR_DVID:
case DRM_MODE_CONNECTOR_HDMIA:
- case DRM_MODE_CONNECTOR_HDMIB:
default:
if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
return ATOM_ENCODER_MODE_HDMI;
@@ -825,10 +848,10 @@ atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
/* XXX: fix up scratch reg handling */
temp = RREG32(reg);
- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+ if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
WREG32(reg, (ATOM_S3_TV1_ACTIVE |
(radeon_crtc->crtc_id << 18)));
- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+ else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
else
WREG32(reg, 0);
@@ -851,9 +874,19 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
int index = 0;
bool is_dig = false;
+ int devices;
memset(&args, 0, sizeof(args));
+ /* on DPMS off we have no idea if active device is meaningful */
+ if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device)
+ devices = radeon_encoder->devices;
+ else
+ devices = radeon_encoder->active_device;
+
+ DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
+ radeon_encoder->encoder_id, mode, radeon_encoder->devices,
+ radeon_encoder->active_device);
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
@@ -881,18 +914,18 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+ if (devices & (ATOM_DEVICE_TV_SUPPORT))
index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+ else if (devices & (ATOM_DEVICE_CV_SUPPORT))
index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
else
index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+ if (devices & (ATOM_DEVICE_TV_SUPPORT))
index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+ else if (devices & (ATOM_DEVICE_CV_SUPPORT))
index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
else
index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
@@ -979,18 +1012,18 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+ if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+ else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
else
args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+ if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+ else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
else
args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
@@ -1019,17 +1052,17 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+ if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+ else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
else
args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+ if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+ else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
else
args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
@@ -1097,7 +1130,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
atombios_set_encoder_crtc_source(encoder);
if (ASIC_IS_AVIVO(rdev)) {
- if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
+ if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
atombios_yuv_setup(encoder, true);
else
atombios_yuv_setup(encoder, false);
@@ -1135,7 +1168,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
atombios_dac_setup(encoder, ATOM_ENABLE);
- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
+ if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
atombios_tv_setup(encoder, ATOM_ENABLE);
break;
}
@@ -1143,11 +1176,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
}
static bool
-atombios_dac_load_detect(struct drm_encoder *encoder)
+atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct radeon_connector *radeon_connector = to_radeon_connector(connector);
if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
ATOM_DEVICE_CV_SUPPORT |
@@ -1168,15 +1202,15 @@ atombios_dac_load_detect(struct drm_encoder *encoder)
else
args.sDacload.ucDacType = ATOM_DAC_B;
- if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT)
+ if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
- else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT)
+ else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
- else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
+ else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
if (crev >= 3)
args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
- } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
+ } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
if (crev >= 3)
args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
@@ -1195,9 +1229,10 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct radeon_connector *radeon_connector = to_radeon_connector(connector);
uint32_t bios_0_scratch;
- if (!atombios_dac_load_detect(encoder)) {
+ if (!atombios_dac_load_detect(encoder, connector)) {
DRM_DEBUG("detect returned false \n");
return connector_status_unknown;
}
@@ -1207,17 +1242,20 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec
else
bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
- DRM_DEBUG("Bios 0 scratch %x\n", bios_0_scratch);
- if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
+ DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
+ if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
if (bios_0_scratch & ATOM_S0_CRT1_MASK)
return connector_status_connected;
- } else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
+ }
+ if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
if (bios_0_scratch & ATOM_S0_CRT2_MASK)
return connector_status_connected;
- } else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
+ }
+ if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
return connector_status_connected;
- } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
+ }
+ if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
return connector_status_connected; /* CTV */
else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
@@ -1230,6 +1268,8 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
{
radeon_atom_output_lock(encoder, true);
radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
+
+ radeon_encoder_set_active_device(encoder);
}
static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
@@ -1238,12 +1278,20 @@ static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
radeon_atom_output_lock(encoder, false);
}
+static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
+{
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
+ radeon_encoder->active_device = 0;
+}
+
static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
.dpms = radeon_atom_encoder_dpms,
.mode_fixup = radeon_atom_mode_fixup,
.prepare = radeon_atom_encoder_prepare,
.mode_set = radeon_atom_encoder_mode_set,
.commit = radeon_atom_encoder_commit,
+ .disable = radeon_atom_encoder_disable,
/* no detect for TMDS/LVDS yet */
};
@@ -1268,6 +1316,18 @@ static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
.destroy = radeon_enc_destroy,
};
+struct radeon_encoder_atom_dac *
+radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
+{
+ struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
+
+ if (!dac)
+ return NULL;
+
+ dac->tv_std = TV_STD_NTSC;
+ return dac;
+}
+
struct radeon_encoder_atom_dig *
radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
{
@@ -1336,6 +1396,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
+ radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
break;
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
@@ -1345,8 +1406,14 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
- drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
- radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
+ if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+ radeon_encoder->rmx_type = RMX_FULL;
+ drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
+ radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
+ } else {
+ drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
+ radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
+ }
drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
break;
}
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index ec383ed..944e4fa 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -28,15 +28,7 @@
*/
#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/tty.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
#include <linux/fb.h>
-#include <linux/init.h>
#include "drmP.h"
#include "drm.h"
@@ -45,375 +37,24 @@
#include "radeon_drm.h"
#include "radeon.h"
+#include "drm_fb_helper.h"
+
struct radeon_fb_device {
- struct radeon_device *rdev;
- struct drm_display_mode *mode;
+ struct drm_fb_helper helper;
struct radeon_framebuffer *rfb;
- int crtc_count;
- /* crtc currently bound to this */
- uint32_t crtc_ids[2];
+ struct radeon_device *rdev;
};
-static int radeonfb_setcolreg(unsigned regno,
- unsigned red,
- unsigned green,
- unsigned blue,
- unsigned transp,
- struct fb_info *info)
-{
- struct radeon_fb_device *rfbdev = info->par;
- struct drm_device *dev = rfbdev->rdev->ddev;
- struct drm_crtc *crtc;
- int i;
-
- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
- struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
- struct drm_mode_set *modeset = &radeon_crtc->mode_set;
- struct drm_framebuffer *fb = modeset->fb;
-
- for (i = 0; i < rfbdev->crtc_count; i++) {
- if (crtc->base.id == rfbdev->crtc_ids[i]) {
- break;
- }
- }
- if (i == rfbdev->crtc_count) {
- continue;
- }
- if (regno > 255) {
- return 1;
- }
- if (fb->depth == 8) {
- radeon_crtc_fb_gamma_set(crtc, red, green, blue, regno);
- return 0;
- }
-
- if (regno < 16) {
- switch (fb->depth) {
- case 15:
- fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) |
- ((green & 0xf800) >> 6) |
- ((blue & 0xf800) >> 11);
- break;
- case 16:
- fb->pseudo_palette[regno] = (red & 0xf800) |
- ((green & 0xfc00) >> 5) |
- ((blue & 0xf800) >> 11);
- break;
- case 24:
- case 32:
- fb->pseudo_palette[regno] =
- (((red >> 8) & 0xff) << info->var.red.offset) |
- (((green >> 8) & 0xff) << info->var.green.offset) |
- (((blue >> 8) & 0xff) << info->var.blue.offset);
- break;
- }
- }
- }
- return 0;
-}
-
-static int radeonfb_check_var(struct fb_var_screeninfo *var,
- struct fb_info *info)
-{
- struct radeon_fb_device *rfbdev = info->par;
- struct radeon_framebuffer *rfb = rfbdev->rfb;
- struct drm_framebuffer *fb = &rfb->base;
- int depth;
-
- if (var->pixclock == -1 || !var->pixclock) {
- return -EINVAL;
- }
- /* Need to resize the fb object !!! */
- if (var->xres > fb->width || var->yres > fb->height) {
- DRM_ERROR("Requested width/height is greater than current fb "
- "object %dx%d > %dx%d\n", var->xres, var->yres,
- fb->width, fb->height);
- DRM_ERROR("Need resizing code.\n");
- return -EINVAL;
- }
-
- switch (var->bits_per_pixel) {
- case 16:
- depth = (var->green.length == 6) ? 16 : 15;
- break;
- case 32:
- depth = (var->transp.length > 0) ? 32 : 24;
- break;
- default:
- depth = var->bits_per_pixel;
- break;
- }
-
- switch (depth) {
- case 8:
- var->red.offset = 0;
- var->green.offset = 0;
- var->blue.offset = 0;
- var->red.length = 8;
- var->green.length = 8;
- var->blue.length = 8;
- var->transp.length = 0;
- var->transp.offset = 0;
- break;
-#ifdef __LITTLE_ENDIAN
- case 15:
- var->red.offset = 10;
- var->green.offset = 5;
- var->blue.offset = 0;
- var->red.length = 5;
- var->green.length = 5;
- var->blue.length = 5;
- var->transp.length = 1;
- var->transp.offset = 15;
- break;
- case 16:
- var->red.offset = 11;
- var->green.offset = 5;
- var->blue.offset = 0;
- var->red.length = 5;
- var->green.length = 6;
- var->blue.length = 5;
- var->transp.length = 0;
- var->transp.offset = 0;
- break;
- case 24:
- var->red.offset = 16;
- var->green.offset = 8;
- var->blue.offset = 0;
- var->red.length = 8;
- var->green.length = 8;
- var->blue.length = 8;
- var->transp.length = 0;
- var->transp.offset = 0;
- break;
- case 32:
- var->red.offset = 16;
- var->green.offset = 8;
- var->blue.offset = 0;
- var->red.length = 8;
- var->green.length = 8;
- var->blue.length = 8;
- var->transp.length = 8;
- var->transp.offset = 24;
- break;
-#else
- case 24:
- var->red.offset = 8;
- var->green.offset = 16;
- var->blue.offset = 24;
- var->red.length = 8;
- var->green.length = 8;
- var->blue.length = 8;
- var->transp.length = 0;
- var->transp.offset = 0;
- break;
- case 32:
- var->red.offset = 8;
- var->green.offset = 16;
- var->blue.offset = 24;
- var->red.length = 8;
- var->green.length = 8;
- var->blue.length = 8;
- var->transp.length = 8;
- var->transp.offset = 0;
- break;
-#endif
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-/* this will let fbcon do the mode init */
-static int radeonfb_set_par(struct fb_info *info)
-{
- struct radeon_fb_device *rfbdev = info->par;
- struct drm_device *dev = rfbdev->rdev->ddev;
- struct fb_var_screeninfo *var = &info->var;
- struct drm_crtc *crtc;
- int ret;
- int i;
-
- if (var->pixclock != -1) {
- DRM_ERROR("PIXEL CLCOK SET\n");
- return -EINVAL;
- }
-
- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
- struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
-
- for (i = 0; i < rfbdev->crtc_count; i++) {
- if (crtc->base.id == rfbdev->crtc_ids[i]) {
- break;
- }
- }
- if (i == rfbdev->crtc_count) {
- continue;
- }
- if (crtc->fb == radeon_crtc->mode_set.fb) {
- mutex_lock(&dev->mode_config.mutex);
- ret = crtc->funcs->set_config(&radeon_crtc->mode_set);
- mutex_unlock(&dev->mode_config.mutex);
- if (ret) {
- return ret;
- }
- }
- }
- return 0;
-}
-
-static int radeonfb_pan_display(struct fb_var_screeninfo *var,
- struct fb_info *info)
-{
- struct radeon_fb_device *rfbdev = info->par;
- struct drm_device *dev = rfbdev->rdev->ddev;
- struct drm_mode_set *modeset;
- struct drm_crtc *crtc;
- struct radeon_crtc *radeon_crtc;
- int ret = 0;
- int i;
-
- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
- for (i = 0; i < rfbdev->crtc_count; i++) {
- if (crtc->base.id == rfbdev->crtc_ids[i]) {
- break;
- }
- }
-
- if (i == rfbdev->crtc_count) {
- continue;
- }
-
- radeon_crtc = to_radeon_crtc(crtc);
- modeset = &radeon_crtc->mode_set;
-
- modeset->x = var->xoffset;
- modeset->y = var->yoffset;
-
- if (modeset->num_connectors) {
- mutex_lock(&dev->mode_config.mutex);
- ret = crtc->funcs->set_config(modeset);
- mutex_unlock(&dev->mode_config.mutex);
- if (!ret) {
- info->var.xoffset = var->xoffset;
- info->var.yoffset = var->yoffset;
- }
- }
- }
- return ret;
-}
-
-static void radeonfb_on(struct fb_info *info)
-{
- struct radeon_fb_device *rfbdev = info->par;
- struct drm_device *dev = rfbdev->rdev->ddev;
- struct drm_crtc *crtc;
- struct drm_encoder *encoder;
- int i;
-
- /*
- * For each CRTC in this fb, find all associated encoders
- * and turn them off, then turn off the CRTC.
- */
- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
-
- for (i = 0; i < rfbdev->crtc_count; i++) {
- if (crtc->base.id == rfbdev->crtc_ids[i]) {
- break;
- }
- }
-
- mutex_lock(&dev->mode_config.mutex);
- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
- mutex_unlock(&dev->mode_config.mutex);
-
- /* Found a CRTC on this fb, now find encoders */
- list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
- if (encoder->crtc == crtc) {
- struct drm_encoder_helper_funcs *encoder_funcs;
-
- encoder_funcs = encoder->helper_private;
- mutex_lock(&dev->mode_config.mutex);
- encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
- mutex_unlock(&dev->mode_config.mutex);
- }
- }
- }
-}
-
-static void radeonfb_off(struct fb_info *info, int dpms_mode)
-{
- struct radeon_fb_device *rfbdev = info->par;
- struct drm_device *dev = rfbdev->rdev->ddev;
- struct drm_crtc *crtc;
- struct drm_encoder *encoder;
- int i;
-
- /*
- * For each CRTC in this fb, find all associated encoders
- * and turn them off, then turn off the CRTC.
- */
- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
-
- for (i = 0; i < rfbdev->crtc_count; i++) {
- if (crtc->base.id == rfbdev->crtc_ids[i]) {
- break;
- }
- }
-
- /* Found a CRTC on this fb, now find encoders */
- list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
- if (encoder->crtc == crtc) {
- struct drm_encoder_helper_funcs *encoder_funcs;
-
- encoder_funcs = encoder->helper_private;
- mutex_lock(&dev->mode_config.mutex);
- encoder_funcs->dpms(encoder, dpms_mode);
- mutex_unlock(&dev->mode_config.mutex);
- }
- }
- if (dpms_mode == DRM_MODE_DPMS_OFF) {
- mutex_lock(&dev->mode_config.mutex);
- crtc_funcs->dpms(crtc, dpms_mode);
- mutex_unlock(&dev->mode_config.mutex);
- }
- }
-}
-
-int radeonfb_blank(int blank, struct fb_info *info)
-{
- switch (blank) {
- case FB_BLANK_UNBLANK:
- radeonfb_on(info);
- break;
- case FB_BLANK_NORMAL:
- radeonfb_off(info, DRM_MODE_DPMS_STANDBY);
- break;
- case FB_BLANK_HSYNC_SUSPEND:
- radeonfb_off(info, DRM_MODE_DPMS_STANDBY);
- break;
- case FB_BLANK_VSYNC_SUSPEND:
- radeonfb_off(info, DRM_MODE_DPMS_SUSPEND);
- break;
- case FB_BLANK_POWERDOWN:
- radeonfb_off(info, DRM_MODE_DPMS_OFF);
- break;
- }
- return 0;
-}
-
static struct fb_ops radeonfb_ops = {
.owner = THIS_MODULE,
- .fb_check_var = radeonfb_check_var,
- .fb_set_par = radeonfb_set_par,
- .fb_setcolreg = radeonfb_setcolreg,
+ .fb_check_var = drm_fb_helper_check_var,
+ .fb_set_par = drm_fb_helper_set_par,
+ .fb_setcolreg = drm_fb_helper_setcolreg,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
- .fb_pan_display = radeonfb_pan_display,
- .fb_blank = radeonfb_blank,
+ .fb_pan_display = drm_fb_helper_pan_display,
+ .fb_blank = drm_fb_helper_blank,
};
/**
@@ -456,21 +97,6 @@ int radeonfb_resize(struct drm_device *dev, struct drm_crtc *crtc)
}
EXPORT_SYMBOL(radeonfb_resize);
-static struct drm_mode_set panic_mode;
-
-int radeonfb_panic(struct notifier_block *n, unsigned long ununsed,
- void *panic_str)
-{
- DRM_ERROR("panic occurred, switching back to text console\n");
- drm_crtc_helper_set_config(&panic_mode);
- return 0;
-}
-EXPORT_SYMBOL(radeonfb_panic);
-
-static struct notifier_block paniced = {
- .notifier_call = radeonfb_panic,
-};
-
static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
{
int aligned = width;
@@ -495,11 +121,16 @@ static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bo
return aligned;
}
-int radeonfb_create(struct radeon_device *rdev,
+static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
+ .gamma_set = radeon_crtc_fb_gamma_set,
+};
+
+int radeonfb_create(struct drm_device *dev,
uint32_t fb_width, uint32_t fb_height,
uint32_t surface_width, uint32_t surface_height,
- struct radeon_framebuffer **rfb_p)
+ struct drm_framebuffer **fb_p)
{
+ struct radeon_device *rdev = dev->dev_private;
struct fb_info *info;
struct radeon_fb_device *rfbdev;
struct drm_framebuffer *fb = NULL;
@@ -513,6 +144,7 @@ int radeonfb_create(struct radeon_device *rdev,
void *fbptr = NULL;
unsigned long tmp;
bool fb_tiled = false; /* useful for testing */
+ u32 tiling_flags = 0;
mode_cmd.width = surface_width;
mode_cmd.height = surface_height;
@@ -537,7 +169,22 @@ int radeonfb_create(struct radeon_device *rdev,
robj = gobj->driver_private;
if (fb_tiled)
- radeon_object_set_tiling_flags(robj, RADEON_TILING_MACRO|RADEON_TILING_SURFACE, mode_cmd.pitch);
+ tiling_flags = RADEON_TILING_MACRO;
+
+#ifdef __BIG_ENDIAN
+ switch (mode_cmd.bpp) {
+ case 32:
+ tiling_flags |= RADEON_TILING_SWAP_32BIT;
+ break;
+ case 16:
+ tiling_flags |= RADEON_TILING_SWAP_16BIT;
+ default:
+ break;
+ }
+#endif
+
+ if (tiling_flags)
+ radeon_object_set_tiling_flags(robj, tiling_flags | RADEON_TILING_SURFACE, mode_cmd.pitch);
mutex_lock(&rdev->ddev->struct_mutex);
fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
if (fb == NULL) {
@@ -554,8 +201,8 @@ int radeonfb_create(struct radeon_device *rdev,
list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);
+ *fb_p = fb;
rfb = to_radeon_framebuffer(fb);
- *rfb_p = rfb;
rdev->fbdev_rfb = rfb;
rdev->fbdev_robj = robj;
@@ -564,7 +211,15 @@ int radeonfb_create(struct radeon_device *rdev,
ret = -ENOMEM;
goto out_unref;
}
+
+ rdev->fbdev_info = info;
rfbdev = info->par;
+ rfbdev->helper.funcs = &radeon_fb_helper_funcs;
+ rfbdev->helper.dev = dev;
+ ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, 2,
+ RADEONFB_CONN_LIMIT);
+ if (ret)
+ goto out_unref;
if (fb_tiled)
radeon_object_check_tiling(robj, 0, 0);
@@ -577,33 +232,19 @@ int radeonfb_create(struct radeon_device *rdev,
memset_io(fbptr, 0, aligned_size);
strcpy(info->fix.id, "radeondrmfb");
- info->fix.type = FB_TYPE_PACKED_PIXELS;
- info->fix.visual = FB_VISUAL_TRUECOLOR;
- info->fix.type_aux = 0;
- info->fix.xpanstep = 1; /* doing it in hw */
- info->fix.ypanstep = 1; /* doing it in hw */
- info->fix.ywrapstep = 0;
- info->fix.accel = FB_ACCEL_NONE;
- info->fix.type_aux = 0;
+
+ drm_fb_helper_fill_fix(info, fb->pitch);
+
info->flags = FBINFO_DEFAULT;
info->fbops = &radeonfb_ops;
- info->fix.line_length = fb->pitch;
+
tmp = fb_gpuaddr - rdev->mc.vram_location;
info->fix.smem_start = rdev->mc.aper_base + tmp;
info->fix.smem_len = size;
info->screen_base = fbptr;
info->screen_size = size;
- info->pseudo_palette = fb->pseudo_palette;
- info->var.xres_virtual = fb->width;
- info->var.yres_virtual = fb->height;
- info->var.bits_per_pixel = fb->bits_per_pixel;
- info->var.xoffset = 0;
- info->var.yoffset = 0;
- info->var.activate = FB_ACTIVATE_NOW;
- info->var.height = -1;
- info->var.width = -1;
- info->var.xres = fb_width;
- info->var.yres = fb_height;
+
+ drm_fb_helper_fill_var(info, fb, fb_width, fb_height);
/* setup aperture base/size for vesafb takeover */
info->aperture_base = rdev->ddev->mode_config.fb_base;
@@ -626,83 +267,6 @@ int radeonfb_create(struct radeon_device *rdev,
DRM_INFO("fb depth is %d\n", fb->depth);
DRM_INFO(" pitch is %d\n", fb->pitch);
- switch (fb->depth) {
- case 8:
- info->var.red.offset = 0;
- info->var.green.offset = 0;
- info->var.blue.offset = 0;
- info->var.red.length = 8; /* 8bit DAC */
- info->var.green.length = 8;
- info->var.blue.length = 8;
- info->var.transp.offset = 0;
- info->var.transp.length = 0;
- break;
-#ifdef __LITTLE_ENDIAN
- case 15:
- info->var.red.offset = 10;
- info->var.green.offset = 5;
- info->var.blue.offset = 0;
- info->var.red.length = 5;
- info->var.green.length = 5;
- info->var.blue.length = 5;
- info->var.transp.offset = 15;
- info->var.transp.length = 1;
- break;
- case 16:
- info->var.red.offset = 11;
- info->var.green.offset = 5;
- info->var.blue.offset = 0;
- info->var.red.length = 5;
- info->var.green.length = 6;
- info->var.blue.length = 5;
- info->var.transp.offset = 0;
- break;
- case 24:
- info->var.red.offset = 16;
- info->var.green.offset = 8;
- info->var.blue.offset = 0;
- info->var.red.length = 8;
- info->var.green.length = 8;
- info->var.blue.length = 8;
- info->var.transp.offset = 0;
- info->var.transp.length = 0;
- break;
- case 32:
- info->var.red.offset = 16;
- info->var.green.offset = 8;
- info->var.blue.offset = 0;
- info->var.red.length = 8;
- info->var.green.length = 8;
- info->var.blue.length = 8;
- info->var.transp.offset = 24;
- info->var.transp.length = 8;
- break;
-#else
- case 24:
- info->var.red.offset = 8;
- info->var.green.offset = 16;
- info->var.blue.offset = 24;
- info->var.red.length = 8;
- info->var.green.length = 8;
- info->var.blue.length = 8;
- info->var.transp.offset = 0;
- info->var.transp.length = 0;
- break;
- case 32:
- info->var.red.offset = 8;
- info->var.green.offset = 16;
- info->var.blue.offset = 24;
- info->var.red.length = 8;
- info->var.green.length = 8;
- info->var.blue.length = 8;
- info->var.transp.offset = 0;
- info->var.transp.length = 8;
- break;
- default:
-#endif
- break;
- }
-
fb->fbdev = info;
rfbdev->rfb = rfb;
rfbdev->rdev = rdev;
@@ -726,145 +290,10 @@ out:
return ret;
}
-static int radeonfb_single_fb_probe(struct radeon_device *rdev)
-{
- struct drm_crtc *crtc;
- struct drm_connector *connector;
- unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1;
- unsigned int surface_width = 0, surface_height = 0;
- int new_fb = 0;
- int crtc_count = 0;
- int ret, i, conn_count = 0;
- struct radeon_framebuffer *rfb;
- struct fb_info *info;
- struct radeon_fb_device *rfbdev;
- struct drm_mode_set *modeset = NULL;
-
- /* first up get a count of crtcs now in use and new min/maxes width/heights */
- list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) {
- if (drm_helper_crtc_in_use(crtc)) {
- if (crtc->desired_mode) {
- if (crtc->desired_mode->hdisplay < fb_width)
- fb_width = crtc->desired_mode->hdisplay;
-
- if (crtc->desired_mode->vdisplay < fb_height)
- fb_height = crtc->desired_mode->vdisplay;
-
- if (crtc->desired_mode->hdisplay > surface_width)
- surface_width = crtc->desired_mode->hdisplay;
-
- if (crtc->desired_mode->vdisplay > surface_height)
- surface_height = crtc->desired_mode->vdisplay;
- }
- crtc_count++;
- }
- }
-
- if (crtc_count == 0 || fb_width == -1 || fb_height == -1) {
- /* hmm everyone went away - assume VGA cable just fell out
- and will come back later. */
- return 0;
- }
-
- /* do we have an fb already? */
- if (list_empty(&rdev->ddev->mode_config.fb_kernel_list)) {
- /* create an fb if we don't have one */
- ret = radeonfb_create(rdev, fb_width, fb_height, surface_width, surface_height, &rfb);
- if (ret) {
- return -EINVAL;
- }
- new_fb = 1;
- } else {
- struct drm_framebuffer *fb;
- fb = list_first_entry(&rdev->ddev->mode_config.fb_kernel_list, struct drm_framebuffer, filp_head);
- rfb = to_radeon_framebuffer(fb);
-
- /* if someone hotplugs something bigger than we have already allocated, we are pwned.
- As really we can't resize an fbdev that is in the wild currently due to fbdev
- not really being designed for the lower layers moving stuff around under it.
- - so in the grand style of things - punt. */
- if ((fb->width < surface_width) || (fb->height < surface_height)) {
- DRM_ERROR("Framebuffer not large enough to scale console onto.\n");
- return -EINVAL;
- }
- }
-
- info = rfb->base.fbdev;
- rdev->fbdev_info = info;
- rfbdev = info->par;
-
- crtc_count = 0;
- /* okay we need to setup new connector sets in the crtcs */
- list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) {
- struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
- modeset = &radeon_crtc->mode_set;
- modeset->fb = &rfb->base;
- conn_count = 0;
- list_for_each_entry(connector, &rdev->ddev->mode_config.connector_list, head) {
- if (connector->encoder)
- if (connector->encoder->crtc == modeset->crtc) {
- modeset->connectors[conn_count] = connector;
- conn_count++;
- if (conn_count > RADEONFB_CONN_LIMIT)
- BUG();
- }
- }
-
- for (i = conn_count; i < RADEONFB_CONN_LIMIT; i++)
- modeset->connectors[i] = NULL;
-
-
- rfbdev->crtc_ids[crtc_count++] = crtc->base.id;
-
- modeset->num_connectors = conn_count;
- if (modeset->crtc->desired_mode) {
- if (modeset->mode) {
- drm_mode_destroy(rdev->ddev, modeset->mode);
- }
- modeset->mode = drm_mode_duplicate(rdev->ddev,
- modeset->crtc->desired_mode);
- }
- }
- rfbdev->crtc_count = crtc_count;
-
- if (new_fb) {
- info->var.pixclock = -1;
- if (register_framebuffer(info) < 0)
- return -EINVAL;
- } else {
- radeonfb_set_par(info);
- }
- printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
- info->fix.id);
-
- /* Switch back to kernel console on panic */
- panic_mode = *modeset;
- atomic_notifier_chain_register(&panic_notifier_list, &paniced);
- printk(KERN_INFO "registered panic notifier\n");
-
- return 0;
-}
-
int radeonfb_probe(struct drm_device *dev)
{
int ret;
-
- /* something has changed in the lower levels of hell - deal with it
- here */
-
- /* two modes : a) 1 fb to rule all crtcs.
- b) one fb per crtc.
- two actions 1) new connected device
- 2) device removed.
- case a/1 : if the fb surface isn't big enough - resize the surface fb.
- if the fb size isn't big enough - resize fb into surface.
- if everything big enough configure the new crtc/etc.
- case a/2 : undo the configuration
- possibly resize down the fb to fit the new configuration.
- case b/1 : see if it is on a new crtc - setup a new fb and add it.
- case b/2 : teardown the new fb.
- */
- ret = radeonfb_single_fb_probe(dev->dev_private);
+ ret = drm_fb_helper_single_fb_probe(dev, &radeonfb_create);
return ret;
}
EXPORT_SYMBOL(radeonfb_probe);
@@ -880,16 +309,17 @@ int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
}
info = fb->fbdev;
if (info) {
+ struct radeon_fb_device *rfbdev = info->par;
robj = rfb->obj->driver_private;
unregister_framebuffer(info);
radeon_object_kunmap(robj);
radeon_object_unpin(robj);
+ drm_fb_helper_free(&rfbdev->helper);
framebuffer_release(info);
}
printk(KERN_INFO "unregistered panic notifier\n");
- atomic_notifier_chain_unregister(&panic_notifier_list, &paniced);
- memset(&panic_mode, 0, sizeof(struct drm_mode_set));
+
return 0;
}
EXPORT_SYMBOL(radeonfb_remove);
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index b4e48dd..3beb26d 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -53,9 +53,9 @@ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
* away
*/
WREG32(rdev->fence_drv.scratch_reg, fence->seq);
- } else {
+ } else
radeon_fence_ring_emit(rdev, fence);
- }
+
fence->emited = true;
fence->timeout = jiffies + ((2000 * HZ) / 1000);
list_del(&fence->list);
@@ -168,7 +168,38 @@ bool radeon_fence_signaled(struct radeon_fence *fence)
return signaled;
}
-int radeon_fence_wait(struct radeon_fence *fence, bool interruptible)
+int r600_fence_wait(struct radeon_fence *fence, bool intr, bool lazy)
+{
+ struct radeon_device *rdev;
+ int ret = 0;
+
+ rdev = fence->rdev;
+
+ __set_current_state(intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
+
+ while (1) {
+ if (radeon_fence_signaled(fence))
+ break;
+
+ if (time_after_eq(jiffies, fence->timeout)) {
+ ret = -EBUSY;
+ break;
+ }
+
+ if (lazy)
+ schedule_timeout(1);
+
+ if (intr && signal_pending(current)) {
+ ret = -ERESTARTSYS;
+ break;
+ }
+ }
+ __set_current_state(TASK_RUNNING);
+ return ret;
+}
+
+
+int radeon_fence_wait(struct radeon_fence *fence, bool intr)
{
struct radeon_device *rdev;
unsigned long cur_jiffies;
@@ -176,7 +207,6 @@ int radeon_fence_wait(struct radeon_fence *fence, bool interruptible)
bool expired = false;
int r;
-
if (fence == NULL) {
WARN(1, "Querying an invalid fence : %p !\n", fence);
return 0;
@@ -185,13 +215,22 @@ int radeon_fence_wait(struct radeon_fence *fence, bool interruptible)
if (radeon_fence_signaled(fence)) {
return 0;
}
+
+ if (rdev->family >= CHIP_R600) {
+ r = r600_fence_wait(fence, intr, 0);
+ if (r == -ERESTARTSYS)
+ return -EBUSY;
+ return r;
+ }
+
retry:
cur_jiffies = jiffies;
timeout = HZ / 100;
if (time_after(fence->timeout, cur_jiffies)) {
timeout = fence->timeout - cur_jiffies;
}
- if (interruptible) {
+
+ if (intr) {
r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
radeon_fence_signaled(fence), timeout);
if (unlikely(r == -ERESTARTSYS)) {
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index 2977539..a931af0 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -75,7 +75,6 @@ void radeon_gart_table_ram_free(struct radeon_device *rdev)
int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
{
- uint64_t gpu_addr;
int r;
if (rdev->gart.table.vram.robj == NULL) {
@@ -88,6 +87,14 @@ int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
return r;
}
}
+ return 0;
+}
+
+int radeon_gart_table_vram_pin(struct radeon_device *rdev)
+{
+ uint64_t gpu_addr;
+ int r;
+
r = radeon_object_pin(rdev->gart.table.vram.robj,
RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
if (r) {
diff --git a/drivers/gpu/drm/radeon/radeon_ioc32.c b/drivers/gpu/drm/radeon/radeon_ioc32.c
index 56decda..a1bf11d 100644
--- a/drivers/gpu/drm/radeon/radeon_ioc32.c
+++ b/drivers/gpu/drm/radeon/radeon_ioc32.c
@@ -422,3 +422,18 @@ long radeon_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
return ret;
}
+
+long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ unsigned int nr = DRM_IOCTL_NR(cmd);
+ int ret;
+
+ if (nr < DRM_COMMAND_BASE)
+ return drm_compat_ioctl(filp, cmd, arg);
+
+ lock_kernel(); /* XXX for now */
+ ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg);
+ unlock_kernel();
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c
index 9836c70..b79ecc4 100644
--- a/drivers/gpu/drm/radeon/radeon_irq.c
+++ b/drivers/gpu/drm/radeon/radeon_irq.c
@@ -188,6 +188,9 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
u32 stat;
u32 r500_disp_int;
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+ return IRQ_NONE;
+
/* Only consider the bits we're interested in - others could be used
* outside the DRM
*/
@@ -286,6 +289,9 @@ int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_pr
drm_radeon_irq_emit_t *emit = data;
int result;
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+ return -EINVAL;
+
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (!dev_priv) {
@@ -315,6 +321,9 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr
return -EINVAL;
}
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+ return -EINVAL;
+
return radeon_wait_irq(dev, irqwait->irq_seq);
}
@@ -326,6 +335,9 @@ void radeon_driver_irq_preinstall(struct drm_device * dev)
(drm_radeon_private_t *) dev->dev_private;
u32 dummy;
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+ return;
+
/* Disable *all* interrupts */
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
@@ -345,6 +357,9 @@ int radeon_driver_irq_postinstall(struct drm_device *dev)
dev->max_vblank_count = 0x001fffff;
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+ return 0;
+
radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
return 0;
@@ -357,6 +372,9 @@ void radeon_driver_irq_uninstall(struct drm_device * dev)
if (!dev_priv)
return;
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+ return;
+
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
/* Disable *all* interrupts */
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 9805e4b..1841145 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -28,7 +28,6 @@
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon_reg.h"
-#include "radeon_microcode.h"
#include "radeon.h"
#include "atom.h"
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index dce09ad..709bd89 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -54,12 +54,23 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
flags |= RADEON_IS_PCI;
}
+ /* radeon_device_init should report only fatal error
+ * like memory allocation failure or iomapping failure,
+ * or memory manager initialization failure, it must
+ * properly initialize the GPU MC controller and permit
+ * VRAM allocation
+ */
r = radeon_device_init(rdev, dev, dev->pdev, flags);
if (r) {
- DRM_ERROR("Failed to initialize radeon, disabling IOCTL\n");
- radeon_device_fini(rdev);
- kfree(rdev);
- dev->dev_private = NULL;
+ DRM_ERROR("Fatal error while trying to initialize radeon.\n");
+ return r;
+ }
+ /* Again modeset_init should fail only on fatal error
+ * otherwise it should provide enough functionalities
+ * for shadowfb to run
+ */
+ r = radeon_modeset_init(rdev);
+ if (r) {
return r;
}
return 0;
@@ -69,6 +80,9 @@ int radeon_driver_unload_kms(struct drm_device *dev)
{
struct radeon_device *rdev = dev->dev_private;
+ if (rdev == NULL)
+ return 0;
+ radeon_modeset_fini(rdev);
radeon_device_fini(rdev);
kfree(rdev);
dev->dev_private = NULL;
@@ -98,6 +112,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
case RADEON_INFO_NUM_Z_PIPES:
value = rdev->num_z_pipes;
break;
+ case RADEON_INFO_ACCEL_WORKING:
+ value = rdev->accel_working;
+ break;
default:
DRM_DEBUG("Invalid request %d\n", info->request);
return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 0da72f1..2b997a1 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -28,6 +28,7 @@
#include <drm/radeon_drm.h>
#include "radeon_fixed.h"
#include "radeon.h"
+#include "atom.h"
static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
struct drm_display_mode *mode,
@@ -340,6 +341,9 @@ void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
uint32_t crtc_pitch;
switch (crtc->fb->bits_per_pixel) {
+ case 8:
+ format = 2;
+ break;
case 15: /* 555 */
format = 3;
break;
@@ -400,11 +404,33 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
uint32_t crtc_pitch, pitch_pixels;
uint32_t tiling_flags;
+ int format;
+ uint32_t gen_cntl_reg, gen_cntl_val;
DRM_DEBUG("\n");
radeon_fb = to_radeon_framebuffer(crtc->fb);
+ switch (crtc->fb->bits_per_pixel) {
+ case 8:
+ format = 2;
+ break;
+ case 15: /* 555 */
+ format = 3;
+ break;
+ case 16: /* 565 */
+ format = 4;
+ break;
+ case 24: /* RGB */
+ format = 5;
+ break;
+ case 32: /* xRGB */
+ format = 6;
+ break;
+ default:
+ return false;
+ }
+
obj = radeon_fb->obj;
if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
return -EINVAL;
@@ -457,6 +483,9 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
} else {
int offset = y * pitch_pixels + x;
switch (crtc->fb->bits_per_pixel) {
+ case 8:
+ offset *= 1;
+ break;
case 15:
case 16:
offset *= 2;
@@ -475,6 +504,16 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
base &= ~7;
+ if (radeon_crtc->crtc_id == 1)
+ gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
+ else
+ gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
+
+ gen_cntl_val = RREG32(gen_cntl_reg);
+ gen_cntl_val &= ~(0xf << 8);
+ gen_cntl_val |= (format << 8);
+ WREG32(gen_cntl_reg, gen_cntl_val);
+
crtc_offset = (u32)base;
WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
@@ -501,6 +540,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
struct drm_device *dev = crtc->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct drm_encoder *encoder;
int format;
int hsync_start;
int hsync_wid;
@@ -509,10 +549,24 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
uint32_t crtc_h_sync_strt_wid;
uint32_t crtc_v_total_disp;
uint32_t crtc_v_sync_strt_wid;
+ bool is_tv = false;
DRM_DEBUG("\n");
+ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ if (encoder->crtc == crtc) {
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
+ is_tv = true;
+ DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
+ break;
+ }
+ }
+ }
switch (crtc->fb->bits_per_pixel) {
+ case 8:
+ format = 2;
+ break;
case 15: /* 555 */
format = 3;
break;
@@ -642,6 +696,11 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
}
+ if (is_tv)
+ radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
+ &crtc_h_sync_strt_wid, &crtc_v_total_disp,
+ &crtc_v_sync_strt_wid);
+
WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
@@ -668,7 +727,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
uint32_t pll_ref_div = 0;
uint32_t pll_fb_post_div = 0;
uint32_t htotal_cntl = 0;
-
+ bool is_tv = false;
struct radeon_pll *pll;
struct {
@@ -703,6 +762,13 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
if (encoder->crtc == crtc) {
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+
+ if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
+ is_tv = true;
+ break;
+ }
+
if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
@@ -766,6 +832,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
+ if (is_tv) {
+ radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
+ &pll_ref_div, &pll_fb_post_div,
+ &pixclks_cntl);
+ }
+
WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
RADEON_PIX2CLK_SRC_SEL_CPUCLK,
~(RADEON_PIX2CLK_SRC_SEL_MASK));
@@ -820,6 +892,15 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
} else {
+ uint32_t pixclks_cntl;
+
+
+ if (is_tv) {
+ pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
+ radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
+ &pll_fb_post_div, &pixclks_cntl);
+ }
+
if (rdev->flags & RADEON_IS_MOBILITY) {
/* A temporal workaround for the occational blanking on certain laptop panels.
This appears to related to the PLL divider registers (fail to lock?).
@@ -914,6 +995,8 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
RADEON_VCLK_SRC_SEL_PPLLCLK,
~(RADEON_VCLK_SRC_SEL_MASK));
+ if (is_tv)
+ WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
}
}
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 9322675..b1547f7 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -29,6 +29,15 @@
#include "radeon.h"
#include "atom.h"
+static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
+{
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct drm_encoder_helper_funcs *encoder_funcs;
+
+ encoder_funcs = encoder->helper_private;
+ encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
+ radeon_encoder->active_device = 0;
+}
static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
{
@@ -98,6 +107,8 @@ static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
else
radeon_combios_output_lock(encoder, true);
radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
+
+ radeon_encoder_set_active_device(encoder);
}
static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
@@ -195,6 +206,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
.prepare = radeon_legacy_lvds_prepare,
.mode_set = radeon_legacy_lvds_mode_set,
.commit = radeon_legacy_lvds_commit,
+ .disable = radeon_legacy_encoder_disable,
};
@@ -260,6 +272,7 @@ static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
else
radeon_combios_output_lock(encoder, true);
radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
+ radeon_encoder_set_active_device(encoder);
}
static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
@@ -402,6 +415,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_fu
.mode_set = radeon_legacy_primary_dac_mode_set,
.commit = radeon_legacy_primary_dac_commit,
.detect = radeon_legacy_primary_dac_detect,
+ .disable = radeon_legacy_encoder_disable,
};
@@ -454,6 +468,7 @@ static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
else
radeon_combios_output_lock(encoder, true);
radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
+ radeon_encoder_set_active_device(encoder);
}
static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
@@ -566,6 +581,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs
.prepare = radeon_legacy_tmds_int_prepare,
.mode_set = radeon_legacy_tmds_int_mode_set,
.commit = radeon_legacy_tmds_int_commit,
+ .disable = radeon_legacy_encoder_disable,
};
@@ -620,6 +636,7 @@ static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
else
radeon_combios_output_lock(encoder, true);
radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
+ radeon_encoder_set_active_device(encoder);
}
static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
@@ -706,6 +723,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs
.prepare = radeon_legacy_tmds_ext_prepare,
.mode_set = radeon_legacy_tmds_ext_mode_set,
.commit = radeon_legacy_tmds_ext_commit,
+ .disable = radeon_legacy_encoder_disable,
};
@@ -727,17 +745,21 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
- /* uint32_t tv_master_cntl = 0; */
-
+ uint32_t tv_master_cntl = 0;
+ bool is_tv;
DRM_DEBUG("\n");
+ is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
+
if (rdev->family == CHIP_R200)
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
else {
- crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
- /* FIXME TV */
- /* tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); */
+ if (is_tv)
+ tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
+ else
+ crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
}
@@ -746,20 +768,23 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
if (rdev->family == CHIP_R200) {
fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
} else {
- crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
- /* tv_master_cntl |= RADEON_TV_ON; */
+ if (is_tv)
+ tv_master_cntl |= RADEON_TV_ON;
+ else
+ crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
+
if (rdev->family == CHIP_R420 ||
- rdev->family == CHIP_R423 ||
- rdev->family == CHIP_RV410)
+ rdev->family == CHIP_R423 ||
+ rdev->family == CHIP_RV410)
tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
- R420_TV_DAC_GDACPD |
- R420_TV_DAC_BDACPD |
- RADEON_TV_DAC_BGSLEEP);
+ R420_TV_DAC_GDACPD |
+ R420_TV_DAC_BDACPD |
+ RADEON_TV_DAC_BGSLEEP);
else
tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
- RADEON_TV_DAC_GDACPD |
- RADEON_TV_DAC_BDACPD |
- RADEON_TV_DAC_BGSLEEP);
+ RADEON_TV_DAC_GDACPD |
+ RADEON_TV_DAC_BDACPD |
+ RADEON_TV_DAC_BGSLEEP);
}
break;
case DRM_MODE_DPMS_STANDBY:
@@ -768,8 +793,11 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
if (rdev->family == CHIP_R200)
fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
else {
- crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
- /* tv_master_cntl &= ~RADEON_TV_ON; */
+ if (is_tv)
+ tv_master_cntl &= ~RADEON_TV_ON;
+ else
+ crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+
if (rdev->family == CHIP_R420 ||
rdev->family == CHIP_R423 ||
rdev->family == CHIP_RV410)
@@ -789,8 +817,10 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
if (rdev->family == CHIP_R200) {
WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
} else {
- WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
- /* WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); */
+ if (is_tv)
+ WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
+ else
+ WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
}
@@ -809,6 +839,7 @@ static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
else
radeon_combios_output_lock(encoder, true);
radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
+ radeon_encoder_set_active_device(encoder);
}
static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
@@ -831,11 +862,15 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
struct radeon_device *rdev = dev->dev_private;
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
- uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0;
+ uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
+ bool is_tv = false;
DRM_DEBUG("\n");
+ is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
+
if (rdev->family != CHIP_R200) {
tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
if (rdev->family == CHIP_R420 ||
@@ -858,7 +893,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
}
/* FIXME TV */
- if (radeon_encoder->enc_priv) {
+ if (tv_dac) {
struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
RADEON_TV_DAC_NHOLD |
@@ -875,44 +910,93 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
if (ASIC_IS_R300(rdev)) {
gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
- } else if (rdev->family == CHIP_R200)
- fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
+ }
+
+ if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev))
+ disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
else
disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
- dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
+ if (rdev->family == CHIP_R200)
+ fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
- if (radeon_crtc->crtc_id == 0) {
- if (ASIC_IS_R300(rdev)) {
- disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
- disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
- } else if (rdev->family == CHIP_R200) {
- fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
- RADEON_FP2_DVO_RATE_SEL_SDR);
- } else
- disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
+ if (is_tv) {
+ uint32_t dac_cntl;
+
+ dac_cntl = RREG32(RADEON_DAC_CNTL);
+ dac_cntl &= ~RADEON_DAC_TVO_EN;
+ WREG32(RADEON_DAC_CNTL, dac_cntl);
+
+ if (ASIC_IS_R300(rdev))
+ gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
+
+ dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
+ if (radeon_crtc->crtc_id == 0) {
+ if (ASIC_IS_R300(rdev)) {
+ disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+ disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
+ RADEON_DISP_TV_SOURCE_CRTC);
+ }
+ if (rdev->family >= CHIP_R200) {
+ disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
+ } else {
+ disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
+ }
+ } else {
+ if (ASIC_IS_R300(rdev)) {
+ disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+ disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
+ }
+ if (rdev->family >= CHIP_R200) {
+ disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
+ } else {
+ disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
+ }
+ }
+ WREG32(RADEON_DAC_CNTL2, dac2_cntl);
} else {
- if (ASIC_IS_R300(rdev)) {
- disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
- disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
- } else if (rdev->family == CHIP_R200) {
- fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
- RADEON_FP2_DVO_RATE_SEL_SDR);
- fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
- } else
- disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
- }
- WREG32(RADEON_DAC_CNTL2, dac2_cntl);
+ dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
+
+ if (radeon_crtc->crtc_id == 0) {
+ if (ASIC_IS_R300(rdev)) {
+ disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+ disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
+ } else if (rdev->family == CHIP_R200) {
+ fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
+ RADEON_FP2_DVO_RATE_SEL_SDR);
+ } else
+ disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
+ } else {
+ if (ASIC_IS_R300(rdev)) {
+ disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+ disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
+ } else if (rdev->family == CHIP_R200) {
+ fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
+ RADEON_FP2_DVO_RATE_SEL_SDR);
+ fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
+ } else
+ disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
+ }
+ WREG32(RADEON_DAC_CNTL2, dac2_cntl);
+ }
if (ASIC_IS_R300(rdev)) {
WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
- WREG32(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl);
- } else if (rdev->family == CHIP_R200)
- WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+ WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
+ }
+
+ if (rdev->family >= CHIP_R200)
+ WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
else
WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
+ if (rdev->family == CHIP_R200)
+ WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+
+ if (is_tv)
+ radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
+
if (rdev->is_atom_bios)
radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
else
@@ -920,6 +1004,141 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
}
+static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
+ struct drm_connector *connector)
+{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
+ uint32_t disp_output_cntl, gpiopad_a, tmp;
+ bool found = false;
+
+ /* save regs needed */
+ gpiopad_a = RREG32(RADEON_GPIOPAD_A);
+ dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
+ crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
+ dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
+ tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
+ disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
+
+ WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
+
+ WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
+
+ WREG32(RADEON_CRTC2_GEN_CNTL,
+ RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
+
+ tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
+ tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
+ WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
+
+ WREG32(RADEON_DAC_EXT_CNTL,
+ RADEON_DAC2_FORCE_BLANK_OFF_EN |
+ RADEON_DAC2_FORCE_DATA_EN |
+ RADEON_DAC_FORCE_DATA_SEL_RGB |
+ (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
+
+ WREG32(RADEON_TV_DAC_CNTL,
+ RADEON_TV_DAC_STD_NTSC |
+ (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
+ (6 << RADEON_TV_DAC_DACADJ_SHIFT));
+
+ RREG32(RADEON_TV_DAC_CNTL);
+ mdelay(4);
+
+ WREG32(RADEON_TV_DAC_CNTL,
+ RADEON_TV_DAC_NBLANK |
+ RADEON_TV_DAC_NHOLD |
+ RADEON_TV_MONITOR_DETECT_EN |
+ RADEON_TV_DAC_STD_NTSC |
+ (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
+ (6 << RADEON_TV_DAC_DACADJ_SHIFT));
+
+ RREG32(RADEON_TV_DAC_CNTL);
+ mdelay(6);
+
+ tmp = RREG32(RADEON_TV_DAC_CNTL);
+ if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
+ found = true;
+ DRM_DEBUG("S-video TV connection detected\n");
+ } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
+ found = true;
+ DRM_DEBUG("Composite TV connection detected\n");
+ }
+
+ WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+ WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
+ WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
+ WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
+ WREG32(RADEON_DAC_CNTL2, dac_cntl2);
+ WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
+ return found;
+}
+
+static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
+ struct drm_connector *connector)
+{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ uint32_t tv_dac_cntl, dac_cntl2;
+ uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
+ bool found = false;
+
+ if (ASIC_IS_R300(rdev))
+ return r300_legacy_tv_detect(encoder, connector);
+
+ dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
+ tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
+ tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
+ config_cntl = RREG32(RADEON_CONFIG_CNTL);
+ tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
+
+ tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
+ WREG32(RADEON_DAC_CNTL2, tmp);
+
+ tmp = tv_master_cntl | RADEON_TV_ON;
+ tmp &= ~(RADEON_TV_ASYNC_RST |
+ RADEON_RESTART_PHASE_FIX |
+ RADEON_CRT_FIFO_CE_EN |
+ RADEON_TV_FIFO_CE_EN |
+ RADEON_RE_SYNC_NOW_SEL_MASK);
+ tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
+ WREG32(RADEON_TV_MASTER_CNTL, tmp);
+
+ tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
+ RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
+ (8 << RADEON_TV_DAC_BGADJ_SHIFT);
+
+ if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
+ tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
+ else
+ tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
+ WREG32(RADEON_TV_DAC_CNTL, tmp);
+
+ tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
+ RADEON_RED_MX_FORCE_DAC_DATA |
+ RADEON_GRN_MX_FORCE_DAC_DATA |
+ RADEON_BLU_MX_FORCE_DAC_DATA |
+ (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
+ WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
+
+ mdelay(3);
+ tmp = RREG32(RADEON_TV_DAC_CNTL);
+ if (tmp & RADEON_TV_DAC_GDACDET) {
+ found = true;
+ DRM_DEBUG("S-video TV connection detected\n");
+ } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
+ found = true;
+ DRM_DEBUG("Composite TV connection detected\n");
+ }
+
+ WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
+ WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+ WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
+ WREG32(RADEON_DAC_CNTL2, dac_cntl2);
+ return found;
+}
+
static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
struct drm_connector *connector)
{
@@ -928,9 +1147,29 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
enum drm_connector_status found = connector_status_disconnected;
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
bool color = true;
- /* FIXME tv */
+ if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
+ connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
+ connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
+ bool tv_detect;
+
+ if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
+ return connector_status_disconnected;
+
+ tv_detect = radeon_legacy_tv_detect(encoder, connector);
+ if (tv_detect && tv_dac)
+ found = connector_status_connected;
+ return found;
+ }
+
+ /* don't probe if the encoder is being used for something else not CRT related */
+ if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
+ DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
+ return connector_status_disconnected;
+ }
/* save the regs we need */
pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
@@ -1013,8 +1252,7 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
}
WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
- /* return found; */
- return connector_status_disconnected;
+ return found;
}
@@ -1025,6 +1263,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs =
.mode_set = radeon_legacy_tv_dac_mode_set,
.commit = radeon_legacy_tv_dac_commit,
.detect = radeon_legacy_tv_dac_detect,
+ .disable = radeon_legacy_encoder_disable,
};
@@ -1032,6 +1271,30 @@ static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
.destroy = radeon_enc_destroy,
};
+
+static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
+{
+ struct drm_device *dev = encoder->base.dev;
+ struct radeon_device *rdev = dev->dev_private;
+ struct radeon_encoder_int_tmds *tmds = NULL;
+ bool ret;
+
+ tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
+
+ if (!tmds)
+ return NULL;
+
+ if (rdev->is_atom_bios)
+ ret = radeon_atombios_get_tmds_info(encoder, tmds);
+ else
+ ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
+
+ if (ret == false)
+ radeon_legacy_get_tmds_info_from_table(encoder, tmds);
+
+ return tmds;
+}
+
void
radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
{
@@ -1078,10 +1341,7 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
- if (rdev->is_atom_bios)
- radeon_encoder->enc_priv = radeon_atombios_get_tmds_info(radeon_encoder);
- else
- radeon_encoder->enc_priv = radeon_combios_get_tmds_info(radeon_encoder);
+ radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
new file mode 100644
index 0000000..3a12bb0
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
@@ -0,0 +1,904 @@
+#include "drmP.h"
+#include "drm_crtc_helper.h"
+#include "radeon.h"
+
+/*
+ * Integrated TV out support based on the GATOS code by
+ * Federico Ulivi <fulivi@lycos.com>
+ */
+
+
+/*
+ * Limits of h/v positions (hPos & vPos)
+ */
+#define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */
+#define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
+
+/*
+ * Unit for hPos (in TV clock periods)
+ */
+#define H_POS_UNIT 10
+
+/*
+ * Indexes in h. code timing table for horizontal line position adjustment
+ */
+#define H_TABLE_POS1 6
+#define H_TABLE_POS2 8
+
+/*
+ * Limits of hor. size (hSize)
+ */
+#define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */
+
+/* tv standard constants */
+#define NTSC_TV_CLOCK_T 233
+#define NTSC_TV_VFTOTAL 1
+#define NTSC_TV_LINES_PER_FRAME 525
+#define NTSC_TV_ZERO_H_SIZE 479166
+#define NTSC_TV_H_SIZE_UNIT 9478
+
+#define PAL_TV_CLOCK_T 188
+#define PAL_TV_VFTOTAL 3
+#define PAL_TV_LINES_PER_FRAME 625
+#define PAL_TV_ZERO_H_SIZE 473200
+#define PAL_TV_H_SIZE_UNIT 9360
+
+/* tv pll setting for 27 mhz ref clk */
+#define NTSC_TV_PLL_M_27 22
+#define NTSC_TV_PLL_N_27 175
+#define NTSC_TV_PLL_P_27 5
+
+#define PAL_TV_PLL_M_27 113
+#define PAL_TV_PLL_N_27 668
+#define PAL_TV_PLL_P_27 3
+
+/* tv pll setting for 14 mhz ref clk */
+#define NTSC_TV_PLL_M_14 33
+#define NTSC_TV_PLL_N_14 693
+#define NTSC_TV_PLL_P_14 7
+
+#define VERT_LEAD_IN_LINES 2
+#define FRAC_BITS 0xe
+#define FRAC_MASK 0x3fff
+
+struct radeon_tv_mode_constants {
+ uint16_t hor_resolution;
+ uint16_t ver_resolution;
+ enum radeon_tv_std standard;
+ uint16_t hor_total;
+ uint16_t ver_total;
+ uint16_t hor_start;
+ uint16_t hor_syncstart;
+ uint16_t ver_syncstart;
+ unsigned def_restart;
+ uint16_t crtcPLL_N;
+ uint8_t crtcPLL_M;
+ uint8_t crtcPLL_post_div;
+ unsigned pix_to_tv;
+};
+
+static const uint16_t hor_timing_NTSC[] = {
+ 0x0007,
+ 0x003f,
+ 0x0263,
+ 0x0a24,
+ 0x2a6b,
+ 0x0a36,
+ 0x126d, /* H_TABLE_POS1 */
+ 0x1bfe,
+ 0x1a8f, /* H_TABLE_POS2 */
+ 0x1ec7,
+ 0x3863,
+ 0x1bfe,
+ 0x1bfe,
+ 0x1a2a,
+ 0x1e95,
+ 0x0e31,
+ 0x201b,
+ 0
+};
+
+static const uint16_t vert_timing_NTSC[] = {
+ 0x2001,
+ 0x200d,
+ 0x1006,
+ 0x0c06,
+ 0x1006,
+ 0x1818,
+ 0x21e3,
+ 0x1006,
+ 0x0c06,
+ 0x1006,
+ 0x1817,
+ 0x21d4,
+ 0x0002,
+ 0
+};
+
+static const uint16_t hor_timing_PAL[] = {
+ 0x0007,
+ 0x0058,
+ 0x027c,
+ 0x0a31,
+ 0x2a77,
+ 0x0a95,
+ 0x124f, /* H_TABLE_POS1 */
+ 0x1bfe,
+ 0x1b22, /* H_TABLE_POS2 */
+ 0x1ef9,
+ 0x387c,
+ 0x1bfe,
+ 0x1bfe,
+ 0x1b31,
+ 0x1eb5,
+ 0x0e43,
+ 0x201b,
+ 0
+};
+
+static const uint16_t vert_timing_PAL[] = {
+ 0x2001,
+ 0x200c,
+ 0x1005,
+ 0x0c05,
+ 0x1005,
+ 0x1401,
+ 0x1821,
+ 0x2240,
+ 0x1005,
+ 0x0c05,
+ 0x1005,
+ 0x1401,
+ 0x1822,
+ 0x2230,
+ 0x0002,
+ 0
+};
+
+/**********************************************************************
+ *
+ * availableModes
+ *
+ * Table of all allowed modes for tv output
+ *
+ **********************************************************************/
+static const struct radeon_tv_mode_constants available_tv_modes[] = {
+ { /* NTSC timing for 27 Mhz ref clk */
+ 800, /* horResolution */
+ 600, /* verResolution */
+ TV_STD_NTSC, /* standard */
+ 990, /* horTotal */
+ 740, /* verTotal */
+ 813, /* horStart */
+ 824, /* horSyncStart */
+ 632, /* verSyncStart */
+ 625592, /* defRestart */
+ 592, /* crtcPLL_N */
+ 91, /* crtcPLL_M */
+ 4, /* crtcPLL_postDiv */
+ 1022, /* pixToTV */
+ },
+ { /* PAL timing for 27 Mhz ref clk */
+ 800, /* horResolution */
+ 600, /* verResolution */
+ TV_STD_PAL, /* standard */
+ 1144, /* horTotal */
+ 706, /* verTotal */
+ 812, /* horStart */
+ 824, /* horSyncStart */
+ 669, /* verSyncStart */
+ 696700, /* defRestart */
+ 1382, /* crtcPLL_N */
+ 231, /* crtcPLL_M */
+ 4, /* crtcPLL_postDiv */
+ 759, /* pixToTV */
+ },
+ { /* NTSC timing for 14 Mhz ref clk */
+ 800, /* horResolution */
+ 600, /* verResolution */
+ TV_STD_NTSC, /* standard */
+ 1018, /* horTotal */
+ 727, /* verTotal */
+ 813, /* horStart */
+ 840, /* horSyncStart */
+ 633, /* verSyncStart */
+ 630627, /* defRestart */
+ 347, /* crtcPLL_N */
+ 14, /* crtcPLL_M */
+ 8, /* crtcPLL_postDiv */
+ 1022, /* pixToTV */
+ },
+};
+
+#define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
+
+static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder,
+ uint16_t *pll_ref_freq)
+{
+ struct drm_device *dev = radeon_encoder->base.dev;
+ struct radeon_device *rdev = dev->dev_private;
+ struct radeon_crtc *radeon_crtc;
+ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
+ const struct radeon_tv_mode_constants *const_ptr;
+ struct radeon_pll *pll;
+
+ radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);
+ if (radeon_crtc->crtc_id == 1)
+ pll = &rdev->clock.p2pll;
+ else
+ pll = &rdev->clock.p1pll;
+
+ if (pll_ref_freq)
+ *pll_ref_freq = pll->reference_freq;
+
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J ||
+ tv_dac->tv_std == TV_STD_PAL_M) {
+ if (pll->reference_freq == 2700)
+ const_ptr = &available_tv_modes[0];
+ else
+ const_ptr = &available_tv_modes[2];
+ } else {
+ if (pll->reference_freq == 2700)
+ const_ptr = &available_tv_modes[1];
+ else
+ const_ptr = &available_tv_modes[1]; /* FIX ME */
+ }
+ return const_ptr;
+}
+
+static long YCOEF_value[5] = { 2, 2, 0, 4, 0 };
+static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 };
+static long SLOPE_value[5] = { 1, 2, 2, 4, 8 };
+static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 };
+
+static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests,
+ unsigned n_wait_loops, unsigned cnt_threshold)
+{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ uint32_t save_pll_test;
+ unsigned int i, j;
+
+ WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);
+ save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL);
+ WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B);
+
+ WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL);
+ for (i = 0; i < n_tests; i++) {
+ WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0);
+ for (j = 0; j < n_wait_loops; j++)
+ if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold)
+ break;
+ }
+ WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test);
+ WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);
+}
+
+
+static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder,
+ uint16_t addr, uint32_t value)
+{
+ struct drm_device *dev = radeon_encoder->base.dev;
+ struct radeon_device *rdev = dev->dev_private;
+ uint32_t tmp;
+ int i = 0;
+
+ WREG32(RADEON_TV_HOST_WRITE_DATA, value);
+
+ WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
+ WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT);
+
+ do {
+ tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
+ if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0)
+ break;
+ i++;
+ } while (i < 10000);
+ WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
+}
+
+#if 0 /* included for completeness */
+static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr)
+{
+ struct drm_device *dev = radeon_encoder->base.dev;
+ struct radeon_device *rdev = dev->dev_private;
+ uint32_t tmp;
+ int i = 0;
+
+ WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
+ WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD);
+
+ do {
+ tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
+ if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0)
+ break;
+ i++;
+ } while (i < 10000);
+ WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
+ return RREG32(RADEON_TV_HOST_READ_DATA);
+}
+#endif
+
+static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr)
+{
+ uint16_t h_table;
+
+ switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) {
+ case 0:
+ h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL;
+ break;
+ case 1:
+ h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2;
+ break;
+ case 2:
+ h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2;
+ break;
+ default:
+ h_table = 0;
+ break;
+ }
+ return h_table;
+}
+
+static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr)
+{
+ uint16_t v_table;
+
+ switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) {
+ case 0:
+ v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1;
+ break;
+ case 1:
+ v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1;
+ break;
+ case 2:
+ v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1;
+ break;
+ default:
+ v_table = 0;
+ break;
+ }
+ return v_table;
+}
+
+static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder)
+{
+ struct drm_device *dev = radeon_encoder->base.dev;
+ struct radeon_device *rdev = dev->dev_private;
+ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
+ uint16_t h_table, v_table;
+ uint32_t tmp;
+ int i;
+
+ WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);
+ h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr);
+ v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr);
+
+ for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) {
+ tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);
+ radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp);
+ if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0)
+ break;
+ }
+ for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) {
+ tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]);
+ radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp);
+ if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0)
+ break;
+ }
+}
+
+static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder)
+{
+ struct drm_device *dev = radeon_encoder->base.dev;
+ struct radeon_device *rdev = dev->dev_private;
+ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
+ WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart);
+ WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart);
+ WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart);
+}
+
+static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder)
+{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
+ struct radeon_crtc *radeon_crtc;
+ int restart;
+ unsigned int h_total, v_total, f_total;
+ int v_offset, h_offset;
+ u16 p1, p2, h_inc;
+ bool h_changed;
+ const struct radeon_tv_mode_constants *const_ptr;
+ struct radeon_pll *pll;
+
+ radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);
+ if (radeon_crtc->crtc_id == 1)
+ pll = &rdev->clock.p2pll;
+ else
+ pll = &rdev->clock.p1pll;
+
+ const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
+ if (!const_ptr)
+ return false;
+
+ h_total = const_ptr->hor_total;
+ v_total = const_ptr->ver_total;
+
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J ||
+ tv_dac->tv_std == TV_STD_PAL_M ||
+ tv_dac->tv_std == TV_STD_PAL_60)
+ f_total = NTSC_TV_VFTOTAL + 1;
+ else
+ f_total = PAL_TV_VFTOTAL + 1;
+
+ /* adjust positions 1&2 in hor. cod timing table */
+ h_offset = tv_dac->h_pos * H_POS_UNIT;
+
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J ||
+ tv_dac->tv_std == TV_STD_PAL_M) {
+ h_offset -= 50;
+ p1 = hor_timing_NTSC[H_TABLE_POS1];
+ p2 = hor_timing_NTSC[H_TABLE_POS2];
+ } else {
+ p1 = hor_timing_PAL[H_TABLE_POS1];
+ p2 = hor_timing_PAL[H_TABLE_POS2];
+ }
+
+ p1 = (u16)((int)p1 + h_offset);
+ p2 = (u16)((int)p2 - h_offset);
+
+ h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] ||
+ p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]);
+
+ tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1;
+ tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2;
+
+ /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */
+ h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000;
+
+ /* adjust restart */
+ restart = const_ptr->def_restart;
+
+ /*
+ * convert v_pos TV lines to n. of CRTC pixels
+ */
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J ||
+ tv_dac->tv_std == TV_STD_PAL_M ||
+ tv_dac->tv_std == TV_STD_PAL_60)
+ v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME);
+ else
+ v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME);
+
+ restart -= v_offset + h_offset;
+
+ DRM_DEBUG("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n",
+ const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart);
+
+ tv_dac->tv.hrestart = restart % h_total;
+ restart /= h_total;
+ tv_dac->tv.vrestart = restart % v_total;
+ restart /= v_total;
+ tv_dac->tv.frestart = restart % f_total;
+
+ DRM_DEBUG("compute_restart: F/H/V=%u,%u,%u\n",
+ (unsigned)tv_dac->tv.frestart,
+ (unsigned)tv_dac->tv.vrestart,
+ (unsigned)tv_dac->tv.hrestart);
+
+ /* compute h_inc from hsize */
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J ||
+ tv_dac->tv_std == TV_STD_PAL_M)
+ h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) /
+ (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
+ else
+ h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) /
+ (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
+
+ tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) |
+ ((u32)h_inc << RADEON_H_INC_SHIFT);
+
+ DRM_DEBUG("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc);
+
+ return h_changed;
+}
+
+void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
+ const struct radeon_tv_mode_constants *const_ptr;
+ struct radeon_crtc *radeon_crtc;
+ int i;
+ uint16_t pll_ref_freq;
+ uint32_t vert_space, flicker_removal, tmp;
+ uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl;
+ uint32_t tv_modulator_cntl1, tv_modulator_cntl2;
+ uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2;
+ uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal;
+ uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl;
+ uint32_t m, n, p;
+ const uint16_t *hor_timing;
+ const uint16_t *vert_timing;
+
+ const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq);
+ if (!const_ptr)
+ return;
+
+ radeon_crtc = to_radeon_crtc(encoder->crtc);
+
+ tv_master_cntl = (RADEON_VIN_ASYNC_RST |
+ RADEON_CRT_FIFO_CE_EN |
+ RADEON_TV_FIFO_CE_EN |
+ RADEON_TV_ON);
+
+ if (!ASIC_IS_R300(rdev))
+ tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb;
+
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J)
+ tv_master_cntl |= RADEON_RESTART_PHASE_FIX;
+
+ tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT |
+ RADEON_SYNC_TIP_LEVEL |
+ RADEON_YFLT_EN |
+ RADEON_UVFLT_EN |
+ (6 << RADEON_CY_FILT_BLEND_SHIFT));
+
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J) {
+ tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) |
+ (0x3b << RADEON_BLANK_LEVEL_SHIFT);
+ tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) |
+ ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
+ } else if (tv_dac->tv_std == TV_STD_SCART_PAL) {
+ tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN;
+ tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) |
+ ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
+ } else {
+ tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN |
+ (0x3b << RADEON_SET_UP_LEVEL_SHIFT) |
+ (0x3b << RADEON_BLANK_LEVEL_SHIFT);
+ tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) |
+ ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
+ }
+
+
+ tv_rgb_cntl = (RADEON_RGB_DITHER_EN
+ | RADEON_TVOUT_SCALE_EN
+ | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT)
+ | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT)
+ | RADEON_RGB_ATTEN_SEL(0x3)
+ | RADEON_RGB_ATTEN_VAL(0xc));
+
+ if (radeon_crtc->crtc_id == 1)
+ tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2;
+ else {
+ if (radeon_crtc->rmx_type != RMX_OFF)
+ tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX;
+ else
+ tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1;
+ }
+
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J ||
+ tv_dac->tv_std == TV_STD_PAL_M ||
+ tv_dac->tv_std == TV_STD_PAL_60)
+ vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME;
+ else
+ vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME;
+
+ tmp = RREG32(RADEON_TV_VSCALER_CNTL1);
+ tmp &= 0xe3ff0000;
+ tmp |= (vert_space * (1 << FRAC_BITS) / 10000);
+ tv_vscaler_cntl1 = tmp;
+
+ if (pll_ref_freq == 2700)
+ tv_vscaler_cntl1 |= RADEON_RESTART_FIELD;
+
+ if (const_ptr->hor_resolution == 1024)
+ tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT);
+ else
+ tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT);
+
+ /* scale up for int divide */
+ tmp = const_ptr->ver_total * 2 * 1000;
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J ||
+ tv_dac->tv_std == TV_STD_PAL_M ||
+ tv_dac->tv_std == TV_STD_PAL_60) {
+ tmp /= NTSC_TV_LINES_PER_FRAME;
+ } else {
+ tmp /= PAL_TV_LINES_PER_FRAME;
+ }
+ flicker_removal = (tmp + 500) / 1000;
+
+ if (flicker_removal < 3)
+ flicker_removal = 3;
+ for (i = 0; i < 6; ++i) {
+ if (flicker_removal == SLOPE_limit[i])
+ break;
+ }
+
+ tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) +
+ 5001) / 10000 / 8 | ((SLOPE_value[i] *
+ (1 << (FRAC_BITS - 1)) / 8) << 16);
+ tv_y_fall_cntl =
+ (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) |
+ RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) /
+ 1024;
+ tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG|
+ (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024;
+
+ tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0;
+ tv_vscaler_cntl2 |= (0x10 << 24) |
+ RADEON_DITHER_MODE |
+ RADEON_Y_OUTPUT_DITHER_EN |
+ RADEON_UV_OUTPUT_DITHER_EN |
+ RADEON_UV_TO_BUF_DITHER_EN;
+
+ tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK;
+ tmp = ((16384 * 256 * 10) / tmp + 5) / 10;
+ tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;
+ tv_dac->tv.timing_cntl = tmp;
+
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J ||
+ tv_dac->tv_std == TV_STD_PAL_M ||
+ tv_dac->tv_std == TV_STD_PAL_60)
+ tv_dac_cntl = tv_dac->ntsc_tvdac_adj;
+ else
+ tv_dac_cntl = tv_dac->pal_tvdac_adj;
+
+ tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
+
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J)
+ tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
+ else
+ tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
+
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J) {
+ if (pll_ref_freq == 2700) {
+ m = NTSC_TV_PLL_M_27;
+ n = NTSC_TV_PLL_N_27;
+ p = NTSC_TV_PLL_P_27;
+ } else {
+ m = NTSC_TV_PLL_M_14;
+ n = NTSC_TV_PLL_N_14;
+ p = NTSC_TV_PLL_P_14;
+ }
+ } else {
+ if (pll_ref_freq == 2700) {
+ m = PAL_TV_PLL_M_27;
+ n = PAL_TV_PLL_N_27;
+ p = PAL_TV_PLL_P_27;
+ } else {
+ m = PAL_TV_PLL_M_27;
+ n = PAL_TV_PLL_N_27;
+ p = PAL_TV_PLL_P_27;
+ }
+ }
+
+ tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
+ (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
+ ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
+ (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
+ ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
+
+ tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) |
+ ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) |
+ ((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) |
+ RADEON_TVCLK_SRC_SEL_TVPLL |
+ RADEON_TVPLL_TEST_DIS);
+
+ tv_dac->tv.tv_uv_adr = 0xc8;
+
+ if (tv_dac->tv_std == TV_STD_NTSC ||
+ tv_dac->tv_std == TV_STD_NTSC_J ||
+ tv_dac->tv_std == TV_STD_PAL_M ||
+ tv_dac->tv_std == TV_STD_PAL_60) {
+ tv_ftotal = NTSC_TV_VFTOTAL;
+ hor_timing = hor_timing_NTSC;
+ vert_timing = vert_timing_NTSC;
+ } else {
+ hor_timing = hor_timing_PAL;
+ vert_timing = vert_timing_PAL;
+ tv_ftotal = PAL_TV_VFTOTAL;
+ }
+
+ for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) {
+ if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0)
+ break;
+ }
+
+ for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) {
+ if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0)
+ break;
+ }
+
+ radeon_legacy_tv_init_restarts(encoder);
+
+ /* play with DAC_CNTL */
+ /* play with GPIOPAD_A */
+ /* DISP_OUTPUT_CNTL */
+ /* use reference freq */
+
+ /* program the TV registers */
+ WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
+ RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST));
+
+ tmp = RREG32(RADEON_TV_DAC_CNTL);
+ tmp &= ~RADEON_TV_DAC_NBLANK;
+ tmp |= RADEON_TV_DAC_BGSLEEP |
+ RADEON_TV_DAC_RDACPD |
+ RADEON_TV_DAC_GDACPD |
+ RADEON_TV_DAC_BDACPD;
+ WREG32(RADEON_TV_DAC_CNTL, tmp);
+
+ /* TV PLL */
+ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);
+ WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl);
+ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET);
+
+ radeon_wait_pll_lock(encoder, 200, 800, 135);
+
+ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);
+
+ radeon_wait_pll_lock(encoder, 300, 160, 27);
+ radeon_wait_pll_lock(encoder, 200, 800, 135);
+
+ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf);
+ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL);
+
+ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK);
+ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);
+
+ /* TV HV */
+ WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl);
+ WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1);
+ WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1);
+ WREG32(RADEON_TV_HSTART, const_ptr->hor_start);
+
+ WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1);
+ WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1);
+ WREG32(RADEON_TV_FTOTAL, tv_ftotal);
+ WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1);
+ WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2);
+
+ WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl);
+ WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl);
+ WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl);
+
+ WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
+ RADEON_CRT_ASYNC_RST));
+
+ /* TV restarts */
+ radeon_legacy_write_tv_restarts(radeon_encoder);
+
+ /* tv timings */
+ radeon_restore_tv_timing_tables(radeon_encoder);
+
+ WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST));
+
+ /* tv std */
+ WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE));
+ WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl);
+ WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1);
+ WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2);
+ WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN |
+ RADEON_C_GRN_EN |
+ RADEON_CMP_BLU_EN |
+ RADEON_DAC_DITHER_EN));
+
+ WREG32(RADEON_TV_CRC_CNTL, 0);
+
+ WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
+
+ WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) |
+ (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT)));
+ WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) |
+ (0x100 << RADEON_Y_GAIN_SHIFT)));
+
+ WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+
+}
+
+void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
+ uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
+ uint32_t *v_total_disp, uint32_t *v_sync_strt_wid)
+{
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ const struct radeon_tv_mode_constants *const_ptr;
+ uint32_t tmp;
+
+ const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
+ if (!const_ptr)
+ return;
+
+ *h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
+ (((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT);
+
+ tmp = *h_sync_strt_wid;
+ tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR);
+ tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) |
+ (const_ptr->hor_syncstart & 7);
+ *h_sync_strt_wid = tmp;
+
+ *v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) |
+ ((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT);
+
+ tmp = *v_sync_strt_wid;
+ tmp &= ~RADEON_CRTC_V_SYNC_STRT;
+ tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
+ *v_sync_strt_wid = tmp;
+}
+
+static inline int get_post_div(int value)
+{
+ int post_div;
+ switch (value) {
+ case 1: post_div = 0; break;
+ case 2: post_div = 1; break;
+ case 3: post_div = 4; break;
+ case 4: post_div = 2; break;
+ case 6: post_div = 6; break;
+ case 8: post_div = 3; break;
+ case 12: post_div = 7; break;
+ case 16:
+ default: post_div = 5; break;
+ }
+ return post_div;
+}
+
+void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
+ uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
+ uint32_t *ppll_div_3, uint32_t *pixclks_cntl)
+{
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ const struct radeon_tv_mode_constants *const_ptr;
+
+ const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
+ if (!const_ptr)
+ return;
+
+ *htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN;
+
+ *ppll_ref_div = const_ptr->crtcPLL_M;
+
+ *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);
+ *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL);
+ *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK;
+}
+
+void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
+ uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
+ uint32_t *p2pll_div_0, uint32_t *pixclks_cntl)
+{
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ const struct radeon_tv_mode_constants *const_ptr;
+
+ const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
+ if (!const_ptr)
+ return;
+
+ *htotal2_cntl = (const_ptr->hor_total & 0x7);
+
+ *p2pll_ref_div = const_ptr->crtcPLL_M;
+
+ *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);
+ *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK;
+ *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL;
+}
+
diff --git a/drivers/gpu/drm/radeon/radeon_microcode.h b/drivers/gpu/drm/radeon/radeon_microcode.h
deleted file mode 100644
index a348c9e..0000000
--- a/drivers/gpu/drm/radeon/radeon_microcode.h
+++ /dev/null
@@ -1,1844 +0,0 @@
-/*
- * Copyright 2007 Advanced Micro Devices, Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef RADEON_MICROCODE_H
-#define RADEON_MICROCODE_H
-
-/* production radeon ucode r1xx-r6xx */
-static const u32 R100_cp_microcode[][2] = {
- { 0x21007000, 0000000000 },
- { 0x20007000, 0000000000 },
- { 0x000000b4, 0x00000004 },
- { 0x000000b8, 0x00000004 },
- { 0x6f5b4d4c, 0000000000 },
- { 0x4c4c427f, 0000000000 },
- { 0x5b568a92, 0000000000 },
- { 0x4ca09c6d, 0000000000 },
- { 0xad4c4c4c, 0000000000 },
- { 0x4ce1af3d, 0000000000 },
- { 0xd8afafaf, 0000000000 },
- { 0xd64c4cdc, 0000000000 },
- { 0x4cd10d10, 0000000000 },
- { 0x000f0000, 0x00000016 },
- { 0x362f242d, 0000000000 },
- { 0x00000012, 0x00000004 },
- { 0x000f0000, 0x00000016 },
- { 0x362f282d, 0000000000 },
- { 0x000380e7, 0x00000002 },
- { 0x04002c97, 0x00000002 },
- { 0x000f0001, 0x00000016 },
- { 0x333a3730, 0000000000 },
- { 0x000077ef, 0x00000002 },
- { 0x00061000, 0x00000002 },
- { 0x00000021, 0x0000001a },
- { 0x00004000, 0x0000001e },
- { 0x00061000, 0x00000002 },
- { 0x00000021, 0x0000001a },
- { 0x00004000, 0x0000001e },
- { 0x00061000, 0x00000002 },
- { 0x00000021, 0x0000001a },
- { 0x00004000, 0x0000001e },
- { 0x00000017, 0x00000004 },
- { 0x0003802b, 0x00000002 },
- { 0x040067e0, 0x00000002 },
- { 0x00000017, 0x00000004 },
- { 0x000077e0, 0x00000002 },
- { 0x00065000, 0x00000002 },
- { 0x000037e1, 0x00000002 },
- { 0x040067e1, 0x00000006 },
- { 0x000077e0, 0x00000002 },
- { 0x000077e1, 0x00000002 },
- { 0x000077e1, 0x00000006 },
- { 0xffffffff, 0000000000 },
- { 0x10000000, 0000000000 },
- { 0x0003802b, 0x00000002 },
- { 0x040067e0, 0x00000006 },
- { 0x00007675, 0x00000002 },
- { 0x00007676, 0x00000002 },
- { 0x00007677, 0x00000002 },
- { 0x00007678, 0x00000006 },
- { 0x0003802c, 0x00000002 },
- { 0x04002676, 0x00000002 },
- { 0x00007677, 0x00000002 },
- { 0x00007678, 0x00000006 },
- { 0x0000002f, 0x00000018 },
- { 0x0000002f, 0x00000018 },
- { 0000000000, 0x00000006 },
- { 0x00000030, 0x00000018 },
- { 0x00000030, 0x00000018 },
- { 0000000000, 0x00000006 },
- { 0x01605000, 0x00000002 },
- { 0x00065000, 0x00000002 },
- { 0x00098000, 0x00000002 },
- { 0x00061000, 0x00000002 },
- { 0x64c0603e, 0x00000004 },
- { 0x000380e6, 0x00000002 },
- { 0x040025c5, 0x00000002 },
- { 0x00080000, 0x00000016 },
- { 0000000000, 0000000000 },
- { 0x0400251d, 0x00000002 },
- { 0x00007580, 0x00000002 },
- { 0x00067581, 0x00000002 },
- { 0x04002580, 0x00000002 },
- { 0x00067581, 0x00000002 },
- { 0x00000049, 0x00000004 },
- { 0x00005000, 0000000000 },
- { 0x000380e6, 0x00000002 },
- { 0x040025c5, 0x00000002 },
- { 0x00061000, 0x00000002 },
- { 0x0000750e, 0x00000002 },
- { 0x00019000, 0x00000002 },
- { 0x00011055, 0x00000014 },
- { 0x00000055, 0x00000012 },
- { 0x0400250f, 0x00000002 },
- { 0x0000504f, 0x00000004 },
- { 0x000380e6, 0x00000002 },
- { 0x040025c5, 0x00000002 },
- { 0x00007565, 0x00000002 },
- { 0x00007566, 0x00000002 },
- { 0x00000058, 0x00000004 },
- { 0x000380e6, 0x00000002 },
- { 0x040025c5, 0x00000002 },
- { 0x01e655b4, 0x00000002 },
- { 0x4401b0e4, 0x00000002 },
- { 0x01c110e4, 0x00000002 },
- { 0x26667066, 0x00000018 },
- { 0x040c2565, 0x00000002 },
- { 0x00000066, 0x00000018 },
- { 0x04002564, 0x00000002 },
- { 0x00007566, 0x00000002 },
- { 0x0000005d, 0x00000004 },
- { 0x00401069, 0x00000008 },
- { 0x00101000, 0x00000002 },
- { 0x000d80ff, 0x00000002 },
- { 0x0080006c, 0x00000008 },
- { 0x000f9000, 0x00000002 },
- { 0x000e00ff, 0x00000002 },
- { 0000000000, 0x00000006 },
- { 0x0000008f, 0x00000018 },
- { 0x0000005b, 0x00000004 },
- { 0x000380e6, 0x00000002 },
- { 0x040025c5, 0x00000002 },
- { 0x00007576, 0x00000002 },
- { 0x00065000, 0x00000002 },
- { 0x00009000, 0x00000002 },
- { 0x00041000, 0x00000002 },
- { 0x0c00350e, 0x00000002 },
- { 0x00049000, 0x00000002 },
- { 0x00051000, 0x00000002 },
- { 0x01e785f8, 0x00000002 },
- { 0x00200000, 0x00000002 },
- { 0x0060007e, 0x0000000c },
- { 0x00007563, 0x00000002 },
- { 0x006075f0, 0x00000021 },
- { 0x20007073, 0x00000004 },
- { 0x00005073, 0x00000004 },
- { 0x000380e6, 0x00000002 },
- { 0x040025c5, 0x00000002 },
- { 0x00007576, 0x00000002 },
- { 0x00007577, 0x00000002 },
- { 0x0000750e, 0x00000002 },
- { 0x0000750f, 0x00000002 },
- { 0x00a05000, 0x00000002 },
- { 0x00600083, 0x0000000c },
- { 0x006075f0, 0x00000021 },
- { 0x000075f8, 0x00000002 },
- { 0x00000083, 0x00000004 },
- { 0x000a750e, 0x00000002 },
- { 0x000380e6, 0x00000002 },
- { 0x040025c5, 0x00000002 },
- { 0x0020750f, 0x00000002 },
- { 0x00600086, 0x00000004 },
- { 0x00007570, 0x00000002 },
- { 0x00007571, 0x00000002 },
- { 0x00007572, 0x00000006 },
- { 0x000380e6, 0x00000002 },
- { 0x040025c5, 0x00000002 },
- { 0x00005000, 0x00000002 },
- { 0x00a05000, 0x00000002 },
- { 0x00007568, 0x00000002 },
- { 0x00061000, 0x00000002 },
- { 0x00000095, 0x0000000c },
- { 0x00058000, 0x00000002 },
- { 0x0c607562, 0x00000002 },
- { 0x00000097, 0x00000004 },
- { 0x000380e6, 0x00000002 },
- { 0x040025c5, 0x00000002 },
- { 0x00600096, 0x00000004 },
- { 0x400070e5, 0000000000 },
- { 0x000380e6, 0x00000002 },
- { 0x040025c5, 0x00000002 },
- { 0x000380e5, 0x00000002 },
- { 0x000000a8, 0x0000001c },
- { 0x000650aa, 0x00000018 },
- { 0x040025bb, 0x00000002 },
- { 0x000610ab, 0x00000018 },
- { 0x040075bc, 0000000000 },
- { 0x000075bb, 0x00000002 },
- { 0x000075bc, 0000000000 },
- { 0x00090000, 0x00000006 },
- { 0x00090000, 0x00000002 },
- { 0x000d8002, 0x00000006 },
- { 0x00007832, 0x00000002 },
- { 0x00005000, 0x00000002 },
- { 0x000380e7, 0x00000002 },
- { 0x04002c97, 0x00000002 },
- { 0x00007820, 0x00000002 },
- { 0x00007821, 0x00000002 },
- { 0x00007800, 0000000000 },
- { 0x01200000, 0x00000002 },
- { 0x20077000, 0x00000002 },
- { 0x01200000, 0x00000002 },
- { 0x20007000, 0x00000002 },
- { 0x00061000, 0x00000002 },
- { 0x0120751b, 0x00000002 },
- { 0x8040750a, 0x00000002 },
- { 0x8040750b, 0x00000002 },
- { 0x00110000, 0x00000002 },
- { 0x000380e5, 0x00000002 },
- { 0x000000c6, 0x0000001c },
- { 0x000610ab, 0x00000018 },
- { 0x844075bd, 0x00000002 },
- { 0x000610aa, 0x00000018 },
- { 0x840075bb, 0x00000002 },
- { 0x000610ab, 0x00000018 },
- { 0x844075bc, 0x00000002 },
- { 0x000000c9, 0x00000004 },
- { 0x804075bd, 0x00000002 },
- { 0x800075bb, 0x00000002 },
- { 0x804075bc, 0x00000002 },
- { 0x00108000, 0x00000002 },
- { 0x01400000, 0x00000002 },
- { 0x006000cd, 0x0000000c },
- { 0x20c07000, 0x00000020 },
- { 0x000000cf, 0x00000012 },
- { 0x00800000, 0x00000006 },
- { 0x0080751d, 0x00000006 },
- { 0000000000, 0000000000 },
- { 0x0000775c, 0x00000002 },
- { 0x00a05000, 0x00000002 },
- { 0x00661000, 0x00000002 },
- { 0x0460275d, 0x00000020 },
- { 0x00004000, 0000000000 },
- { 0x01e00830, 0x00000002 },
- { 0x21007000, 0000000000 },
- { 0x6464614d, 0000000000 },
- { 0x69687420, 0000000000 },
- { 0x00000073, 0000000000 },
- { 0000000000, 0000000000 },
- { 0x00005000, 0x00000002 },
- { 0x000380d0, 0x00000002 },
- { 0x040025e0, 0x00000002 },
- { 0x000075e1, 0000000000 },
- { 0x00000001, 0000000000 },
- { 0x000380e0, 0x00000002 },
- { 0x04002394, 0x00000002 },
- { 0x00005000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0x00000008, 0000000000 },
- { 0x00000004, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
-};
-
-static const u32 R200_cp_microcode[][2] = {
- { 0x21007000, 0000000000 },
- { 0x20007000, 0000000000 },
- { 0x000000bf, 0x00000004 },
- { 0x000000c3, 0x00000004 },
- { 0x7a685e5d, 0000000000 },
- { 0x5d5d5588, 0000000000 },
- { 0x68659197, 0000000000 },
- { 0x5da19f78, 0000000000 },
- { 0x5d5d5d5d, 0000000000 },
- { 0x5dee5d50, 0000000000 },
- { 0xf2acacac, 0000000000 },
- { 0xe75df9e9, 0000000000 },
- { 0xb1dd0e11, 0000000000 },
- { 0xe2afafaf, 0000000000 },
- { 0x000f0000, 0x00000016 },
- { 0x452f232d, 0000000000 },
- { 0x00000013, 0x00000004 },
- { 0x000f0000, 0x00000016 },
- { 0x452f272d, 0000000000 },
- { 0x000f0001, 0x00000016 },
- { 0x3e4d4a37, 0000000000 },
- { 0x000077ef, 0x00000002 },
- { 0x00061000, 0x00000002 },
- { 0x00000020, 0x0000001a },
- { 0x00004000, 0x0000001e },
- { 0x00061000, 0x00000002 },
- { 0x00000020, 0x0000001a },
- { 0x00004000, 0x0000001e },
- { 0x00061000, 0x00000002 },
- { 0x00000020, 0x0000001a },
- { 0x00004000, 0x0000001e },
- { 0x00000016, 0x00000004 },
- { 0x0003802a, 0x00000002 },
- { 0x040067e0, 0x00000002 },
- { 0x00000016, 0x00000004 },
- { 0x000077e0, 0x00000002 },
- { 0x00065000, 0x00000002 },
- { 0x000037e1, 0x00000002 },
- { 0x040067e1, 0x00000006 },
- { 0x000077e0, 0x00000002 },
- { 0x000077e1, 0x00000002 },
- { 0x000077e1, 0x00000006 },
- { 0xffffffff, 0000000000 },
- { 0x10000000, 0000000000 },
- { 0x07f007f0, 0000000000 },
- { 0x0003802a, 0x00000002 },
- { 0x040067e0, 0x00000006 },
- { 0x0003802c, 0x00000002 },
- { 0x04002741, 0x00000002 },
- { 0x04002741, 0x00000002 },
- { 0x04002743, 0x00000002 },
- { 0x00007675, 0x00000002 },
- { 0x00007676, 0x00000002 },
- { 0x00007677, 0x00000002 },
- { 0x00007678, 0x00000006 },
- { 0x0003802c, 0x00000002 },
- { 0x04002741, 0x00000002 },
- { 0x04002741, 0x00000002 },
- { 0x04002743, 0x00000002 },
- { 0x00007676, 0x00000002 },
- { 0x00007677, 0x00000002 },
- { 0x00007678, 0x00000006 },
- { 0x0003802b, 0x00000002 },
- { 0x04002676, 0x00000002 },
- { 0x00007677, 0x00000002 },
- { 0x0003802c, 0x00000002 },
- { 0x04002741, 0x00000002 },
- { 0x04002743, 0x00000002 },
- { 0x00007678, 0x00000006 },
- { 0x0003802c, 0x00000002 },
- { 0x04002741, 0x00000002 },
- { 0x04002741, 0x00000002 },
- { 0x04002743, 0x00000002 },
- { 0x00007678, 0x00000006 },
- { 0x0000002f, 0x00000018 },
- { 0x0000002f, 0x00000018 },
- { 0000000000, 0x00000006 },
- { 0x00000037, 0x00000018 },
- { 0x00000037, 0x00000018 },
- { 0000000000, 0x00000006 },
- { 0x01605000, 0x00000002 },
- { 0x00065000, 0x00000002 },
- { 0x00098000, 0x00000002 },
- { 0x00061000, 0x00000002 },
- { 0x64c06051, 0x00000004 },
- { 0x00080000, 0x00000016 },
- { 0000000000, 0000000000 },
- { 0x0400251d, 0x00000002 },
- { 0x00007580, 0x00000002 },
- { 0x00067581, 0x00000002 },
- { 0x04002580, 0x00000002 },
- { 0x00067581, 0x00000002 },
- { 0x0000005a, 0x00000004 },
- { 0x00005000, 0000000000 },
- { 0x00061000, 0x00000002 },
- { 0x0000750e, 0x00000002 },
- { 0x00019000, 0x00000002 },
- { 0x00011064, 0x00000014 },
- { 0x00000064, 0x00000012 },
- { 0x0400250f, 0x00000002 },
- { 0x0000505e, 0x00000004 },
- { 0x00007565, 0x00000002 },
- { 0x00007566, 0x00000002 },
- { 0x00000065, 0x00000004 },
- { 0x01e655b4, 0x00000002 },
- { 0x4401b0f0, 0x00000002 },
- { 0x01c110f0, 0x00000002 },
- { 0x26667071, 0x00000018 },
- { 0x040c2565, 0x00000002 },
- { 0x00000071, 0x00000018 },
- { 0x04002564, 0x00000002 },
- { 0x00007566, 0x00000002 },
- { 0x00000068, 0x00000004 },
- { 0x00401074, 0x00000008 },
- { 0x00101000, 0x00000002 },
- { 0x000d80ff, 0x00000002 },
- { 0x00800077, 0x00000008 },
- { 0x000f9000, 0x00000002 },
- { 0x000e00ff, 0x00000002 },
- { 0000000000, 0x00000006 },
- { 0x00000094, 0x00000018 },
- { 0x00000068, 0x00000004 },
- { 0x00007576, 0x00000002 },
- { 0x00065000, 0x00000002 },
- { 0x00009000, 0x00000002 },
- { 0x00041000, 0x00000002 },
- { 0x0c00350e, 0x00000002 },
- { 0x00049000, 0x00000002 },
- { 0x00051000, 0x00000002 },
- { 0x01e785f8, 0x00000002 },
- { 0x00200000, 0x00000002 },
- { 0x00600087, 0x0000000c },
- { 0x00007563, 0x00000002 },
- { 0x006075f0, 0x00000021 },
- { 0x2000707c, 0x00000004 },
- { 0x0000507c, 0x00000004 },
- { 0x00007576, 0x00000002 },
- { 0x00007577, 0x00000002 },
- { 0x0000750e, 0x00000002 },
- { 0x0000750f, 0x00000002 },
- { 0x00a05000, 0x00000002 },
- { 0x0060008a, 0x0000000c },
- { 0x006075f0, 0x00000021 },
- { 0x000075f8, 0x00000002 },
- { 0x0000008a, 0x00000004 },
- { 0x000a750e, 0x00000002 },
- { 0x0020750f, 0x00000002 },
- { 0x0060008d, 0x00000004 },
- { 0x00007570, 0x00000002 },
- { 0x00007571, 0x00000002 },
- { 0x00007572, 0x00000006 },
- { 0x00005000, 0x00000002 },
- { 0x00a05000, 0x00000002 },
- { 0x00007568, 0x00000002 },
- { 0x00061000, 0x00000002 },
- { 0x00000098, 0x0000000c },
- { 0x00058000, 0x00000002 },
- { 0x0c607562, 0x00000002 },
- { 0x0000009a, 0x00000004 },
- { 0x00600099, 0x00000004 },
- { 0x400070f1, 0000000000 },
- { 0x000380f1, 0x00000002 },
- { 0x000000a7, 0x0000001c },
- { 0x000650a9, 0x00000018 },
- { 0x040025bb, 0x00000002 },
- { 0x000610aa, 0x00000018 },
- { 0x040075bc, 0000000000 },
- { 0x000075bb, 0x00000002 },
- { 0x000075bc, 0000000000 },
- { 0x00090000, 0x00000006 },
- { 0x00090000, 0x00000002 },
- { 0x000d8002, 0x00000006 },
- { 0x00005000, 0x00000002 },
- { 0x00007821, 0x00000002 },
- { 0x00007800, 0000000000 },
- { 0x00007821, 0x00000002 },
- { 0x00007800, 0000000000 },
- { 0x01665000, 0x00000002 },
- { 0x000a0000, 0x00000002 },
- { 0x000671cc, 0x00000002 },
- { 0x0286f1cd, 0x00000002 },
- { 0x000000b7, 0x00000010 },
- { 0x21007000, 0000000000 },
- { 0x000000be, 0x0000001c },
- { 0x00065000, 0x00000002 },
- { 0x000a0000, 0x00000002 },
- { 0x00061000, 0x00000002 },
- { 0x000b0000, 0x00000002 },
- { 0x38067000, 0x00000002 },
- { 0x000a00ba, 0x00000004 },
- { 0x20007000, 0000000000 },
- { 0x01200000, 0x00000002 },
- { 0x20077000, 0x00000002 },
- { 0x01200000, 0x00000002 },
- { 0x20007000, 0000000000 },
- { 0x00061000, 0x00000002 },
- { 0x0120751b, 0x00000002 },
- { 0x8040750a, 0x00000002 },
- { 0x8040750b, 0x00000002 },
- { 0x00110000, 0x00000002 },
- { 0x000380f1, 0x00000002 },
- { 0x000000d1, 0x0000001c },
- { 0x000610aa, 0x00000018 },
- { 0x844075bd, 0x00000002 },
- { 0x000610a9, 0x00000018 },
- { 0x840075bb, 0x00000002 },
- { 0x000610aa, 0x00000018 },
- { 0x844075bc, 0x00000002 },
- { 0x000000d4, 0x00000004 },
- { 0x804075bd, 0x00000002 },
- { 0x800075bb, 0x00000002 },
- { 0x804075bc, 0x00000002 },
- { 0x00108000, 0x00000002 },
- { 0x01400000, 0x00000002 },
- { 0x006000d8, 0x0000000c },
- { 0x20c07000, 0x00000020 },
- { 0x000000da, 0x00000012 },
- { 0x00800000, 0x00000006 },
- { 0x0080751d, 0x00000006 },
- { 0x000025bb, 0x00000002 },
- { 0x000040d4, 0x00000004 },
- { 0x0000775c, 0x00000002 },
- { 0x00a05000, 0x00000002 },
- { 0x00661000, 0x00000002 },
- { 0x0460275d, 0x00000020 },
- { 0x00004000, 0000000000 },
- { 0x00007999, 0x00000002 },
- { 0x00a05000, 0x00000002 },
- { 0x00661000, 0x00000002 },
- { 0x0460299b, 0x00000020 },
- { 0x00004000, 0000000000 },
- { 0x01e00830, 0x00000002 },
- { 0x21007000, 0000000000 },
- { 0x00005000, 0x00000002 },
- { 0x00038056, 0x00000002 },
- { 0x040025e0, 0x00000002 },
- { 0x000075e1, 0000000000 },
- { 0x00000001, 0000000000 },
- { 0x000380ed, 0x00000002 },
- { 0x04007394, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0x000078c4, 0x00000002 },
- { 0x000078c5, 0x00000002 },
- { 0x000078c6, 0x00000002 },
- { 0x00007924, 0x00000002 },
- { 0x00007925, 0x00000002 },
- { 0x00007926, 0x00000002 },
- { 0x000000f2, 0x00000004 },
- { 0x00007924, 0x00000002 },
- { 0x00007925, 0x00000002 },
- { 0x00007926, 0x00000002 },
- { 0x000000f9, 0x00000004 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
-};
-
-static const u32 R300_cp_microcode[][2] = {
- { 0x4200e000, 0000000000 },
- { 0x4000e000, 0000000000 },
- { 0x000000ae, 0x00000008 },
- { 0x000000b2, 0x00000008 },
- { 0x67554b4a, 0000000000 },
- { 0x4a4a4475, 0000000000 },
- { 0x55527d83, 0000000000 },
- { 0x4a8c8b65, 0000000000 },
- { 0x4aef4af6, 0000000000 },
- { 0x4ae14a4a, 0000000000 },
- { 0xe4979797, 0000000000 },
- { 0xdb4aebdd, 0000000000 },
- { 0x9ccc4a4a, 0000000000 },
- { 0xd1989898, 0000000000 },
- { 0x4a0f9ad6, 0000000000 },
- { 0x000ca000, 0x00000004 },
- { 0x000d0012, 0x00000038 },
- { 0x0000e8b4, 0x00000004 },
- { 0x000d0014, 0x00000038 },
- { 0x0000e8b6, 0x00000004 },
- { 0x000d0016, 0x00000038 },
- { 0x0000e854, 0x00000004 },
- { 0x000d0018, 0x00000038 },
- { 0x0000e855, 0x00000004 },
- { 0x000d001a, 0x00000038 },
- { 0x0000e856, 0x00000004 },
- { 0x000d001c, 0x00000038 },
- { 0x0000e857, 0x00000004 },
- { 0x000d001e, 0x00000038 },
- { 0x0000e824, 0x00000004 },
- { 0x000d0020, 0x00000038 },
- { 0x0000e825, 0x00000004 },
- { 0x000d0022, 0x00000038 },
- { 0x0000e830, 0x00000004 },
- { 0x000d0024, 0x00000038 },
- { 0x0000f0c0, 0x00000004 },
- { 0x000d0026, 0x00000038 },
- { 0x0000f0c1, 0x00000004 },
- { 0x000d0028, 0x00000038 },
- { 0x0000f041, 0x00000004 },
- { 0x000d002a, 0x00000038 },
- { 0x0000f184, 0x00000004 },
- { 0x000d002c, 0x00000038 },
- { 0x0000f185, 0x00000004 },
- { 0x000d002e, 0x00000038 },
- { 0x0000f186, 0x00000004 },
- { 0x000d0030, 0x00000038 },
- { 0x0000f187, 0x00000004 },
- { 0x000d0032, 0x00000038 },
- { 0x0000f180, 0x00000004 },
- { 0x000d0034, 0x00000038 },
- { 0x0000f393, 0x00000004 },
- { 0x000d0036, 0x00000038 },
- { 0x0000f38a, 0x00000004 },
- { 0x000d0038, 0x00000038 },
- { 0x0000f38e, 0x00000004 },
- { 0x0000e821, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00000043, 0x00000018 },
- { 0x00cce800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x0000003a, 0x00000008 },
- { 0x0000a000, 0000000000 },
- { 0x2000451d, 0x00000004 },
- { 0x0000e580, 0x00000004 },
- { 0x000ce581, 0x00000004 },
- { 0x08004580, 0x00000004 },
- { 0x000ce581, 0x00000004 },
- { 0x00000047, 0x00000008 },
- { 0x0000a000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x0000e50e, 0x00000004 },
- { 0x00032000, 0x00000004 },
- { 0x00022051, 0x00000028 },
- { 0x00000051, 0x00000024 },
- { 0x0800450f, 0x00000004 },
- { 0x0000a04b, 0x00000008 },
- { 0x0000e565, 0x00000004 },
- { 0x0000e566, 0x00000004 },
- { 0x00000052, 0x00000008 },
- { 0x03cca5b4, 0x00000004 },
- { 0x05432000, 0x00000004 },
- { 0x00022000, 0x00000004 },
- { 0x4ccce05e, 0x00000030 },
- { 0x08274565, 0x00000004 },
- { 0x0000005e, 0x00000030 },
- { 0x08004564, 0x00000004 },
- { 0x0000e566, 0x00000004 },
- { 0x00000055, 0x00000008 },
- { 0x00802061, 0x00000010 },
- { 0x00202000, 0x00000004 },
- { 0x001b00ff, 0x00000004 },
- { 0x01000064, 0x00000010 },
- { 0x001f2000, 0x00000004 },
- { 0x001c00ff, 0x00000004 },
- { 0000000000, 0x0000000c },
- { 0x00000080, 0x00000030 },
- { 0x00000055, 0x00000008 },
- { 0x0000e576, 0x00000004 },
- { 0x000ca000, 0x00000004 },
- { 0x00012000, 0x00000004 },
- { 0x00082000, 0x00000004 },
- { 0x1800650e, 0x00000004 },
- { 0x00092000, 0x00000004 },
- { 0x000a2000, 0x00000004 },
- { 0x000f0000, 0x00000004 },
- { 0x00400000, 0x00000004 },
- { 0x00000074, 0x00000018 },
- { 0x0000e563, 0x00000004 },
- { 0x00c0e5f9, 0x000000c2 },
- { 0x00000069, 0x00000008 },
- { 0x0000a069, 0x00000008 },
- { 0x0000e576, 0x00000004 },
- { 0x0000e577, 0x00000004 },
- { 0x0000e50e, 0x00000004 },
- { 0x0000e50f, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00000077, 0x00000018 },
- { 0x00c0e5f9, 0x000000c2 },
- { 0x00000077, 0x00000008 },
- { 0x0014e50e, 0x00000004 },
- { 0x0040e50f, 0x00000004 },
- { 0x00c0007a, 0x00000008 },
- { 0x0000e570, 0x00000004 },
- { 0x0000e571, 0x00000004 },
- { 0x0000e572, 0x0000000c },
- { 0x0000a000, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x0000e568, 0x00000004 },
- { 0x000c2000, 0x00000004 },
- { 0x00000084, 0x00000018 },
- { 0x000b0000, 0x00000004 },
- { 0x18c0e562, 0x00000004 },
- { 0x00000086, 0x00000008 },
- { 0x00c00085, 0x00000008 },
- { 0x000700e3, 0x00000004 },
- { 0x00000092, 0x00000038 },
- { 0x000ca094, 0x00000030 },
- { 0x080045bb, 0x00000004 },
- { 0x000c2095, 0x00000030 },
- { 0x0800e5bc, 0000000000 },
- { 0x0000e5bb, 0x00000004 },
- { 0x0000e5bc, 0000000000 },
- { 0x00120000, 0x0000000c },
- { 0x00120000, 0x00000004 },
- { 0x001b0002, 0x0000000c },
- { 0x0000a000, 0x00000004 },
- { 0x0000e821, 0x00000004 },
- { 0x0000e800, 0000000000 },
- { 0x0000e821, 0x00000004 },
- { 0x0000e82e, 0000000000 },
- { 0x02cca000, 0x00000004 },
- { 0x00140000, 0x00000004 },
- { 0x000ce1cc, 0x00000004 },
- { 0x050de1cd, 0x00000004 },
- { 0x00400000, 0x00000004 },
- { 0x000000a4, 0x00000018 },
- { 0x00c0a000, 0x00000004 },
- { 0x000000a1, 0x00000008 },
- { 0x000000a6, 0x00000020 },
- { 0x4200e000, 0000000000 },
- { 0x000000ad, 0x00000038 },
- { 0x000ca000, 0x00000004 },
- { 0x00140000, 0x00000004 },
- { 0x000c2000, 0x00000004 },
- { 0x00160000, 0x00000004 },
- { 0x700ce000, 0x00000004 },
- { 0x001400a9, 0x00000008 },
- { 0x4000e000, 0000000000 },
- { 0x02400000, 0x00000004 },
- { 0x400ee000, 0x00000004 },
- { 0x02400000, 0x00000004 },
- { 0x4000e000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x0240e51b, 0x00000004 },
- { 0x0080e50a, 0x00000005 },
- { 0x0080e50b, 0x00000005 },
- { 0x00220000, 0x00000004 },
- { 0x000700e3, 0x00000004 },
- { 0x000000c0, 0x00000038 },
- { 0x000c2095, 0x00000030 },
- { 0x0880e5bd, 0x00000005 },
- { 0x000c2094, 0x00000030 },
- { 0x0800e5bb, 0x00000005 },
- { 0x000c2095, 0x00000030 },
- { 0x0880e5bc, 0x00000005 },
- { 0x000000c3, 0x00000008 },
- { 0x0080e5bd, 0x00000005 },
- { 0x0000e5bb, 0x00000005 },
- { 0x0080e5bc, 0x00000005 },
- { 0x00210000, 0x00000004 },
- { 0x02800000, 0x00000004 },
- { 0x00c000c7, 0x00000018 },
- { 0x4180e000, 0x00000040 },
- { 0x000000c9, 0x00000024 },
- { 0x01000000, 0x0000000c },
- { 0x0100e51d, 0x0000000c },
- { 0x000045bb, 0x00000004 },
- { 0x000080c3, 0x00000008 },
- { 0x0000f3ce, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00cc2000, 0x00000004 },
- { 0x08c053cf, 0x00000040 },
- { 0x00008000, 0000000000 },
- { 0x0000f3d2, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00cc2000, 0x00000004 },
- { 0x08c053d3, 0x00000040 },
- { 0x00008000, 0000000000 },
- { 0x0000f39d, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00cc2000, 0x00000004 },
- { 0x08c0539e, 0x00000040 },
- { 0x00008000, 0000000000 },
- { 0x03c00830, 0x00000004 },
- { 0x4200e000, 0000000000 },
- { 0x0000a000, 0x00000004 },
- { 0x200045e0, 0x00000004 },
- { 0x0000e5e1, 0000000000 },
- { 0x00000001, 0000000000 },
- { 0x000700e0, 0x00000004 },
- { 0x0800e394, 0000000000 },
- { 0000000000, 0000000000 },
- { 0x0000e8c4, 0x00000004 },
- { 0x0000e8c5, 0x00000004 },
- { 0x0000e8c6, 0x00000004 },
- { 0x0000e928, 0x00000004 },
- { 0x0000e929, 0x00000004 },
- { 0x0000e92a, 0x00000004 },
- { 0x000000e4, 0x00000008 },
- { 0x0000e928, 0x00000004 },
- { 0x0000e929, 0x00000004 },
- { 0x0000e92a, 0x00000004 },
- { 0x000000eb, 0x00000008 },
- { 0x02c02000, 0x00000004 },
- { 0x00060000, 0x00000004 },
- { 0x000000f3, 0x00000034 },
- { 0x000000f0, 0x00000008 },
- { 0x00008000, 0x00000004 },
- { 0xc000e000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x001d0018, 0x00000004 },
- { 0x001a0001, 0x00000004 },
- { 0x000000fb, 0x00000034 },
- { 0x0000004a, 0x00000008 },
- { 0x0500a04a, 0x00000008 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
-};
-
-static const u32 R420_cp_microcode[][2] = {
- { 0x4200e000, 0000000000 },
- { 0x4000e000, 0000000000 },
- { 0x00000099, 0x00000008 },
- { 0x0000009d, 0x00000008 },
- { 0x4a554b4a, 0000000000 },
- { 0x4a4a4467, 0000000000 },
- { 0x55526f75, 0000000000 },
- { 0x4a7e7d65, 0000000000 },
- { 0xd9d3dff6, 0000000000 },
- { 0x4ac54a4a, 0000000000 },
- { 0xc8828282, 0000000000 },
- { 0xbf4acfc1, 0000000000 },
- { 0x87b04a4a, 0000000000 },
- { 0xb5838383, 0000000000 },
- { 0x4a0f85ba, 0000000000 },
- { 0x000ca000, 0x00000004 },
- { 0x000d0012, 0x00000038 },
- { 0x0000e8b4, 0x00000004 },
- { 0x000d0014, 0x00000038 },
- { 0x0000e8b6, 0x00000004 },
- { 0x000d0016, 0x00000038 },
- { 0x0000e854, 0x00000004 },
- { 0x000d0018, 0x00000038 },
- { 0x0000e855, 0x00000004 },
- { 0x000d001a, 0x00000038 },
- { 0x0000e856, 0x00000004 },
- { 0x000d001c, 0x00000038 },
- { 0x0000e857, 0x00000004 },
- { 0x000d001e, 0x00000038 },
- { 0x0000e824, 0x00000004 },
- { 0x000d0020, 0x00000038 },
- { 0x0000e825, 0x00000004 },
- { 0x000d0022, 0x00000038 },
- { 0x0000e830, 0x00000004 },
- { 0x000d0024, 0x00000038 },
- { 0x0000f0c0, 0x00000004 },
- { 0x000d0026, 0x00000038 },
- { 0x0000f0c1, 0x00000004 },
- { 0x000d0028, 0x00000038 },
- { 0x0000f041, 0x00000004 },
- { 0x000d002a, 0x00000038 },
- { 0x0000f184, 0x00000004 },
- { 0x000d002c, 0x00000038 },
- { 0x0000f185, 0x00000004 },
- { 0x000d002e, 0x00000038 },
- { 0x0000f186, 0x00000004 },
- { 0x000d0030, 0x00000038 },
- { 0x0000f187, 0x00000004 },
- { 0x000d0032, 0x00000038 },
- { 0x0000f180, 0x00000004 },
- { 0x000d0034, 0x00000038 },
- { 0x0000f393, 0x00000004 },
- { 0x000d0036, 0x00000038 },
- { 0x0000f38a, 0x00000004 },
- { 0x000d0038, 0x00000038 },
- { 0x0000f38e, 0x00000004 },
- { 0x0000e821, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00000043, 0x00000018 },
- { 0x00cce800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x0000003a, 0x00000008 },
- { 0x0000a000, 0000000000 },
- { 0x2000451d, 0x00000004 },
- { 0x0000e580, 0x00000004 },
- { 0x000ce581, 0x00000004 },
- { 0x08004580, 0x00000004 },
- { 0x000ce581, 0x00000004 },
- { 0x00000047, 0x00000008 },
- { 0x0000a000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x0000e50e, 0x00000004 },
- { 0x00032000, 0x00000004 },
- { 0x00022051, 0x00000028 },
- { 0x00000051, 0x00000024 },
- { 0x0800450f, 0x00000004 },
- { 0x0000a04b, 0x00000008 },
- { 0x0000e565, 0x00000004 },
- { 0x0000e566, 0x00000004 },
- { 0x00000052, 0x00000008 },
- { 0x03cca5b4, 0x00000004 },
- { 0x05432000, 0x00000004 },
- { 0x00022000, 0x00000004 },
- { 0x4ccce05e, 0x00000030 },
- { 0x08274565, 0x00000004 },
- { 0x0000005e, 0x00000030 },
- { 0x08004564, 0x00000004 },
- { 0x0000e566, 0x00000004 },
- { 0x00000055, 0x00000008 },
- { 0x00802061, 0x00000010 },
- { 0x00202000, 0x00000004 },
- { 0x001b00ff, 0x00000004 },
- { 0x01000064, 0x00000010 },
- { 0x001f2000, 0x00000004 },
- { 0x001c00ff, 0x00000004 },
- { 0000000000, 0x0000000c },
- { 0x00000072, 0x00000030 },
- { 0x00000055, 0x00000008 },
- { 0x0000e576, 0x00000004 },
- { 0x0000e577, 0x00000004 },
- { 0x0000e50e, 0x00000004 },
- { 0x0000e50f, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00000069, 0x00000018 },
- { 0x00c0e5f9, 0x000000c2 },
- { 0x00000069, 0x00000008 },
- { 0x0014e50e, 0x00000004 },
- { 0x0040e50f, 0x00000004 },
- { 0x00c0006c, 0x00000008 },
- { 0x0000e570, 0x00000004 },
- { 0x0000e571, 0x00000004 },
- { 0x0000e572, 0x0000000c },
- { 0x0000a000, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x0000e568, 0x00000004 },
- { 0x000c2000, 0x00000004 },
- { 0x00000076, 0x00000018 },
- { 0x000b0000, 0x00000004 },
- { 0x18c0e562, 0x00000004 },
- { 0x00000078, 0x00000008 },
- { 0x00c00077, 0x00000008 },
- { 0x000700c7, 0x00000004 },
- { 0x00000080, 0x00000038 },
- { 0x0000e5bb, 0x00000004 },
- { 0x0000e5bc, 0000000000 },
- { 0x0000a000, 0x00000004 },
- { 0x0000e821, 0x00000004 },
- { 0x0000e800, 0000000000 },
- { 0x0000e821, 0x00000004 },
- { 0x0000e82e, 0000000000 },
- { 0x02cca000, 0x00000004 },
- { 0x00140000, 0x00000004 },
- { 0x000ce1cc, 0x00000004 },
- { 0x050de1cd, 0x00000004 },
- { 0x00400000, 0x00000004 },
- { 0x0000008f, 0x00000018 },
- { 0x00c0a000, 0x00000004 },
- { 0x0000008c, 0x00000008 },
- { 0x00000091, 0x00000020 },
- { 0x4200e000, 0000000000 },
- { 0x00000098, 0x00000038 },
- { 0x000ca000, 0x00000004 },
- { 0x00140000, 0x00000004 },
- { 0x000c2000, 0x00000004 },
- { 0x00160000, 0x00000004 },
- { 0x700ce000, 0x00000004 },
- { 0x00140094, 0x00000008 },
- { 0x4000e000, 0000000000 },
- { 0x02400000, 0x00000004 },
- { 0x400ee000, 0x00000004 },
- { 0x02400000, 0x00000004 },
- { 0x4000e000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x0240e51b, 0x00000004 },
- { 0x0080e50a, 0x00000005 },
- { 0x0080e50b, 0x00000005 },
- { 0x00220000, 0x00000004 },
- { 0x000700c7, 0x00000004 },
- { 0x000000a4, 0x00000038 },
- { 0x0080e5bd, 0x00000005 },
- { 0x0000e5bb, 0x00000005 },
- { 0x0080e5bc, 0x00000005 },
- { 0x00210000, 0x00000004 },
- { 0x02800000, 0x00000004 },
- { 0x00c000ab, 0x00000018 },
- { 0x4180e000, 0x00000040 },
- { 0x000000ad, 0x00000024 },
- { 0x01000000, 0x0000000c },
- { 0x0100e51d, 0x0000000c },
- { 0x000045bb, 0x00000004 },
- { 0x000080a7, 0x00000008 },
- { 0x0000f3ce, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00cc2000, 0x00000004 },
- { 0x08c053cf, 0x00000040 },
- { 0x00008000, 0000000000 },
- { 0x0000f3d2, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00cc2000, 0x00000004 },
- { 0x08c053d3, 0x00000040 },
- { 0x00008000, 0000000000 },
- { 0x0000f39d, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00cc2000, 0x00000004 },
- { 0x08c0539e, 0x00000040 },
- { 0x00008000, 0000000000 },
- { 0x03c00830, 0x00000004 },
- { 0x4200e000, 0000000000 },
- { 0x0000a000, 0x00000004 },
- { 0x200045e0, 0x00000004 },
- { 0x0000e5e1, 0000000000 },
- { 0x00000001, 0000000000 },
- { 0x000700c4, 0x00000004 },
- { 0x0800e394, 0000000000 },
- { 0000000000, 0000000000 },
- { 0x0000e8c4, 0x00000004 },
- { 0x0000e8c5, 0x00000004 },
- { 0x0000e8c6, 0x00000004 },
- { 0x0000e928, 0x00000004 },
- { 0x0000e929, 0x00000004 },
- { 0x0000e92a, 0x00000004 },
- { 0x000000c8, 0x00000008 },
- { 0x0000e928, 0x00000004 },
- { 0x0000e929, 0x00000004 },
- { 0x0000e92a, 0x00000004 },
- { 0x000000cf, 0x00000008 },
- { 0x02c02000, 0x00000004 },
- { 0x00060000, 0x00000004 },
- { 0x000000d7, 0x00000034 },
- { 0x000000d4, 0x00000008 },
- { 0x00008000, 0x00000004 },
- { 0xc000e000, 0000000000 },
- { 0x0000e1cc, 0x00000004 },
- { 0x0500e1cd, 0x00000004 },
- { 0x000ca000, 0x00000004 },
- { 0x000000de, 0x00000034 },
- { 0x000000da, 0x00000008 },
- { 0x0000a000, 0000000000 },
- { 0x0019e1cc, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x0500a000, 0x00000004 },
- { 0x080041cd, 0x00000004 },
- { 0x000ca000, 0x00000004 },
- { 0x000000fb, 0x00000034 },
- { 0x0000004a, 0x00000008 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x001d0018, 0x00000004 },
- { 0x001a0001, 0x00000004 },
- { 0x000000fb, 0x00000034 },
- { 0x0000004a, 0x00000008 },
- { 0x0500a04a, 0x00000008 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
-};
-
-static const u32 RS600_cp_microcode[][2] = {
- { 0x4200e000, 0000000000 },
- { 0x4000e000, 0000000000 },
- { 0x000000a0, 0x00000008 },
- { 0x000000a4, 0x00000008 },
- { 0x4a554b4a, 0000000000 },
- { 0x4a4a4467, 0000000000 },
- { 0x55526f75, 0000000000 },
- { 0x4a7e7d65, 0000000000 },
- { 0x4ae74af6, 0000000000 },
- { 0x4ad34a4a, 0000000000 },
- { 0xd6898989, 0000000000 },
- { 0xcd4addcf, 0000000000 },
- { 0x8ebe4ae2, 0000000000 },
- { 0xc38a8a8a, 0000000000 },
- { 0x4a0f8cc8, 0000000000 },
- { 0x000ca000, 0x00000004 },
- { 0x000d0012, 0x00000038 },
- { 0x0000e8b4, 0x00000004 },
- { 0x000d0014, 0x00000038 },
- { 0x0000e8b6, 0x00000004 },
- { 0x000d0016, 0x00000038 },
- { 0x0000e854, 0x00000004 },
- { 0x000d0018, 0x00000038 },
- { 0x0000e855, 0x00000004 },
- { 0x000d001a, 0x00000038 },
- { 0x0000e856, 0x00000004 },
- { 0x000d001c, 0x00000038 },
- { 0x0000e857, 0x00000004 },
- { 0x000d001e, 0x00000038 },
- { 0x0000e824, 0x00000004 },
- { 0x000d0020, 0x00000038 },
- { 0x0000e825, 0x00000004 },
- { 0x000d0022, 0x00000038 },
- { 0x0000e830, 0x00000004 },
- { 0x000d0024, 0x00000038 },
- { 0x0000f0c0, 0x00000004 },
- { 0x000d0026, 0x00000038 },
- { 0x0000f0c1, 0x00000004 },
- { 0x000d0028, 0x00000038 },
- { 0x0000f041, 0x00000004 },
- { 0x000d002a, 0x00000038 },
- { 0x0000f184, 0x00000004 },
- { 0x000d002c, 0x00000038 },
- { 0x0000f185, 0x00000004 },
- { 0x000d002e, 0x00000038 },
- { 0x0000f186, 0x00000004 },
- { 0x000d0030, 0x00000038 },
- { 0x0000f187, 0x00000004 },
- { 0x000d0032, 0x00000038 },
- { 0x0000f180, 0x00000004 },
- { 0x000d0034, 0x00000038 },
- { 0x0000f393, 0x00000004 },
- { 0x000d0036, 0x00000038 },
- { 0x0000f38a, 0x00000004 },
- { 0x000d0038, 0x00000038 },
- { 0x0000f38e, 0x00000004 },
- { 0x0000e821, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00000043, 0x00000018 },
- { 0x00cce800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x0000003a, 0x00000008 },
- { 0x0000a000, 0000000000 },
- { 0x2000451d, 0x00000004 },
- { 0x0000e580, 0x00000004 },
- { 0x000ce581, 0x00000004 },
- { 0x08004580, 0x00000004 },
- { 0x000ce581, 0x00000004 },
- { 0x00000047, 0x00000008 },
- { 0x0000a000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x0000e50e, 0x00000004 },
- { 0x00032000, 0x00000004 },
- { 0x00022051, 0x00000028 },
- { 0x00000051, 0x00000024 },
- { 0x0800450f, 0x00000004 },
- { 0x0000a04b, 0x00000008 },
- { 0x0000e565, 0x00000004 },
- { 0x0000e566, 0x00000004 },
- { 0x00000052, 0x00000008 },
- { 0x03cca5b4, 0x00000004 },
- { 0x05432000, 0x00000004 },
- { 0x00022000, 0x00000004 },
- { 0x4ccce05e, 0x00000030 },
- { 0x08274565, 0x00000004 },
- { 0x0000005e, 0x00000030 },
- { 0x08004564, 0x00000004 },
- { 0x0000e566, 0x00000004 },
- { 0x00000055, 0x00000008 },
- { 0x00802061, 0x00000010 },
- { 0x00202000, 0x00000004 },
- { 0x001b00ff, 0x00000004 },
- { 0x01000064, 0x00000010 },
- { 0x001f2000, 0x00000004 },
- { 0x001c00ff, 0x00000004 },
- { 0000000000, 0x0000000c },
- { 0x00000072, 0x00000030 },
- { 0x00000055, 0x00000008 },
- { 0x0000e576, 0x00000004 },
- { 0x0000e577, 0x00000004 },
- { 0x0000e50e, 0x00000004 },
- { 0x0000e50f, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00000069, 0x00000018 },
- { 0x00c0e5f9, 0x000000c2 },
- { 0x00000069, 0x00000008 },
- { 0x0014e50e, 0x00000004 },
- { 0x0040e50f, 0x00000004 },
- { 0x00c0006c, 0x00000008 },
- { 0x0000e570, 0x00000004 },
- { 0x0000e571, 0x00000004 },
- { 0x0000e572, 0x0000000c },
- { 0x0000a000, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x0000e568, 0x00000004 },
- { 0x000c2000, 0x00000004 },
- { 0x00000076, 0x00000018 },
- { 0x000b0000, 0x00000004 },
- { 0x18c0e562, 0x00000004 },
- { 0x00000078, 0x00000008 },
- { 0x00c00077, 0x00000008 },
- { 0x000700d5, 0x00000004 },
- { 0x00000084, 0x00000038 },
- { 0x000ca086, 0x00000030 },
- { 0x080045bb, 0x00000004 },
- { 0x000c2087, 0x00000030 },
- { 0x0800e5bc, 0000000000 },
- { 0x0000e5bb, 0x00000004 },
- { 0x0000e5bc, 0000000000 },
- { 0x00120000, 0x0000000c },
- { 0x00120000, 0x00000004 },
- { 0x001b0002, 0x0000000c },
- { 0x0000a000, 0x00000004 },
- { 0x0000e821, 0x00000004 },
- { 0x0000e800, 0000000000 },
- { 0x0000e821, 0x00000004 },
- { 0x0000e82e, 0000000000 },
- { 0x02cca000, 0x00000004 },
- { 0x00140000, 0x00000004 },
- { 0x000ce1cc, 0x00000004 },
- { 0x050de1cd, 0x00000004 },
- { 0x00400000, 0x00000004 },
- { 0x00000096, 0x00000018 },
- { 0x00c0a000, 0x00000004 },
- { 0x00000093, 0x00000008 },
- { 0x00000098, 0x00000020 },
- { 0x4200e000, 0000000000 },
- { 0x0000009f, 0x00000038 },
- { 0x000ca000, 0x00000004 },
- { 0x00140000, 0x00000004 },
- { 0x000c2000, 0x00000004 },
- { 0x00160000, 0x00000004 },
- { 0x700ce000, 0x00000004 },
- { 0x0014009b, 0x00000008 },
- { 0x4000e000, 0000000000 },
- { 0x02400000, 0x00000004 },
- { 0x400ee000, 0x00000004 },
- { 0x02400000, 0x00000004 },
- { 0x4000e000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x0240e51b, 0x00000004 },
- { 0x0080e50a, 0x00000005 },
- { 0x0080e50b, 0x00000005 },
- { 0x00220000, 0x00000004 },
- { 0x000700d5, 0x00000004 },
- { 0x000000b2, 0x00000038 },
- { 0x000c2087, 0x00000030 },
- { 0x0880e5bd, 0x00000005 },
- { 0x000c2086, 0x00000030 },
- { 0x0800e5bb, 0x00000005 },
- { 0x000c2087, 0x00000030 },
- { 0x0880e5bc, 0x00000005 },
- { 0x000000b5, 0x00000008 },
- { 0x0080e5bd, 0x00000005 },
- { 0x0000e5bb, 0x00000005 },
- { 0x0080e5bc, 0x00000005 },
- { 0x00210000, 0x00000004 },
- { 0x02800000, 0x00000004 },
- { 0x00c000b9, 0x00000018 },
- { 0x4180e000, 0x00000040 },
- { 0x000000bb, 0x00000024 },
- { 0x01000000, 0x0000000c },
- { 0x0100e51d, 0x0000000c },
- { 0x000045bb, 0x00000004 },
- { 0x000080b5, 0x00000008 },
- { 0x0000f3ce, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00cc2000, 0x00000004 },
- { 0x08c053cf, 0x00000040 },
- { 0x00008000, 0000000000 },
- { 0x0000f3d2, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00cc2000, 0x00000004 },
- { 0x08c053d3, 0x00000040 },
- { 0x00008000, 0000000000 },
- { 0x0000f39d, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00cc2000, 0x00000004 },
- { 0x08c0539e, 0x00000040 },
- { 0x00008000, 0000000000 },
- { 0x03c00830, 0x00000004 },
- { 0x4200e000, 0000000000 },
- { 0x0000a000, 0x00000004 },
- { 0x200045e0, 0x00000004 },
- { 0x0000e5e1, 0000000000 },
- { 0x00000001, 0000000000 },
- { 0x000700d2, 0x00000004 },
- { 0x0800e394, 0000000000 },
- { 0000000000, 0000000000 },
- { 0x0000e8c4, 0x00000004 },
- { 0x0000e8c5, 0x00000004 },
- { 0x0000e8c6, 0x00000004 },
- { 0x0000e928, 0x00000004 },
- { 0x0000e929, 0x00000004 },
- { 0x0000e92a, 0x00000004 },
- { 0x000000d6, 0x00000008 },
- { 0x0000e928, 0x00000004 },
- { 0x0000e929, 0x00000004 },
- { 0x0000e92a, 0x00000004 },
- { 0x000000dd, 0x00000008 },
- { 0x00e00116, 0000000000 },
- { 0x000700e1, 0x00000004 },
- { 0x0800401c, 0x00000004 },
- { 0x200050e7, 0x00000004 },
- { 0x0000e01d, 0x00000004 },
- { 0x000000e4, 0x00000008 },
- { 0x02c02000, 0x00000004 },
- { 0x00060000, 0x00000004 },
- { 0x000000eb, 0x00000034 },
- { 0x000000e8, 0x00000008 },
- { 0x00008000, 0x00000004 },
- { 0xc000e000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x001d0018, 0x00000004 },
- { 0x001a0001, 0x00000004 },
- { 0x000000fb, 0x00000034 },
- { 0x0000004a, 0x00000008 },
- { 0x0500a04a, 0x00000008 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
-};
-
-static const u32 RS690_cp_microcode[][2] = {
- { 0x000000dd, 0x00000008 },
- { 0x000000df, 0x00000008 },
- { 0x000000a0, 0x00000008 },
- { 0x000000a4, 0x00000008 },
- { 0x4a554b4a, 0000000000 },
- { 0x4a4a4467, 0000000000 },
- { 0x55526f75, 0000000000 },
- { 0x4a7e7d65, 0000000000 },
- { 0x4ad74af6, 0000000000 },
- { 0x4ac94a4a, 0000000000 },
- { 0xcc898989, 0000000000 },
- { 0xc34ad3c5, 0000000000 },
- { 0x8e4a4a4a, 0000000000 },
- { 0x4a8a8a8a, 0000000000 },
- { 0x4a0f8c4a, 0000000000 },
- { 0x000ca000, 0x00000004 },
- { 0x000d0012, 0x00000038 },
- { 0x0000e8b4, 0x00000004 },
- { 0x000d0014, 0x00000038 },
- { 0x0000e8b6, 0x00000004 },
- { 0x000d0016, 0x00000038 },
- { 0x0000e854, 0x00000004 },
- { 0x000d0018, 0x00000038 },
- { 0x0000e855, 0x00000004 },
- { 0x000d001a, 0x00000038 },
- { 0x0000e856, 0x00000004 },
- { 0x000d001c, 0x00000038 },
- { 0x0000e857, 0x00000004 },
- { 0x000d001e, 0x00000038 },
- { 0x0000e824, 0x00000004 },
- { 0x000d0020, 0x00000038 },
- { 0x0000e825, 0x00000004 },
- { 0x000d0022, 0x00000038 },
- { 0x0000e830, 0x00000004 },
- { 0x000d0024, 0x00000038 },
- { 0x0000f0c0, 0x00000004 },
- { 0x000d0026, 0x00000038 },
- { 0x0000f0c1, 0x00000004 },
- { 0x000d0028, 0x00000038 },
- { 0x0000f041, 0x00000004 },
- { 0x000d002a, 0x00000038 },
- { 0x0000f184, 0x00000004 },
- { 0x000d002c, 0x00000038 },
- { 0x0000f185, 0x00000004 },
- { 0x000d002e, 0x00000038 },
- { 0x0000f186, 0x00000004 },
- { 0x000d0030, 0x00000038 },
- { 0x0000f187, 0x00000004 },
- { 0x000d0032, 0x00000038 },
- { 0x0000f180, 0x00000004 },
- { 0x000d0034, 0x00000038 },
- { 0x0000f393, 0x00000004 },
- { 0x000d0036, 0x00000038 },
- { 0x0000f38a, 0x00000004 },
- { 0x000d0038, 0x00000038 },
- { 0x0000f38e, 0x00000004 },
- { 0x0000e821, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00000043, 0x00000018 },
- { 0x00cce800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x0000003a, 0x00000008 },
- { 0x0000a000, 0000000000 },
- { 0x2000451d, 0x00000004 },
- { 0x0000e580, 0x00000004 },
- { 0x000ce581, 0x00000004 },
- { 0x08004580, 0x00000004 },
- { 0x000ce581, 0x00000004 },
- { 0x00000047, 0x00000008 },
- { 0x0000a000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x0000e50e, 0x00000004 },
- { 0x00032000, 0x00000004 },
- { 0x00022051, 0x00000028 },
- { 0x00000051, 0x00000024 },
- { 0x0800450f, 0x00000004 },
- { 0x0000a04b, 0x00000008 },
- { 0x0000e565, 0x00000004 },
- { 0x0000e566, 0x00000004 },
- { 0x00000052, 0x00000008 },
- { 0x03cca5b4, 0x00000004 },
- { 0x05432000, 0x00000004 },
- { 0x00022000, 0x00000004 },
- { 0x4ccce05e, 0x00000030 },
- { 0x08274565, 0x00000004 },
- { 0x0000005e, 0x00000030 },
- { 0x08004564, 0x00000004 },
- { 0x0000e566, 0x00000004 },
- { 0x00000055, 0x00000008 },
- { 0x00802061, 0x00000010 },
- { 0x00202000, 0x00000004 },
- { 0x001b00ff, 0x00000004 },
- { 0x01000064, 0x00000010 },
- { 0x001f2000, 0x00000004 },
- { 0x001c00ff, 0x00000004 },
- { 0000000000, 0x0000000c },
- { 0x00000072, 0x00000030 },
- { 0x00000055, 0x00000008 },
- { 0x0000e576, 0x00000004 },
- { 0x0000e577, 0x00000004 },
- { 0x0000e50e, 0x00000004 },
- { 0x0000e50f, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00000069, 0x00000018 },
- { 0x00c0e5f9, 0x000000c2 },
- { 0x00000069, 0x00000008 },
- { 0x0014e50e, 0x00000004 },
- { 0x0040e50f, 0x00000004 },
- { 0x00c0006c, 0x00000008 },
- { 0x0000e570, 0x00000004 },
- { 0x0000e571, 0x00000004 },
- { 0x0000e572, 0x0000000c },
- { 0x0000a000, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x0000e568, 0x00000004 },
- { 0x000c2000, 0x00000004 },
- { 0x00000076, 0x00000018 },
- { 0x000b0000, 0x00000004 },
- { 0x18c0e562, 0x00000004 },
- { 0x00000078, 0x00000008 },
- { 0x00c00077, 0x00000008 },
- { 0x000700cb, 0x00000004 },
- { 0x00000084, 0x00000038 },
- { 0x000ca086, 0x00000030 },
- { 0x080045bb, 0x00000004 },
- { 0x000c2087, 0x00000030 },
- { 0x0800e5bc, 0000000000 },
- { 0x0000e5bb, 0x00000004 },
- { 0x0000e5bc, 0000000000 },
- { 0x00120000, 0x0000000c },
- { 0x00120000, 0x00000004 },
- { 0x001b0002, 0x0000000c },
- { 0x0000a000, 0x00000004 },
- { 0x0000e821, 0x00000004 },
- { 0x0000e800, 0000000000 },
- { 0x0000e821, 0x00000004 },
- { 0x0000e82e, 0000000000 },
- { 0x02cca000, 0x00000004 },
- { 0x00140000, 0x00000004 },
- { 0x000ce1cc, 0x00000004 },
- { 0x050de1cd, 0x00000004 },
- { 0x00400000, 0x00000004 },
- { 0x00000096, 0x00000018 },
- { 0x00c0a000, 0x00000004 },
- { 0x00000093, 0x00000008 },
- { 0x00000098, 0x00000020 },
- { 0x4200e000, 0000000000 },
- { 0x0000009f, 0x00000038 },
- { 0x000ca000, 0x00000004 },
- { 0x00140000, 0x00000004 },
- { 0x000c2000, 0x00000004 },
- { 0x00160000, 0x00000004 },
- { 0x700ce000, 0x00000004 },
- { 0x0014009b, 0x00000008 },
- { 0x4000e000, 0000000000 },
- { 0x02400000, 0x00000004 },
- { 0x400ee000, 0x00000004 },
- { 0x02400000, 0x00000004 },
- { 0x4000e000, 0000000000 },
- { 0x00100000, 0x0000002c },
- { 0x00004000, 0000000000 },
- { 0x080045c8, 0x00000004 },
- { 0x00240005, 0x00000004 },
- { 0x08004d0b, 0x00000004 },
- { 0x000c2000, 0x00000004 },
- { 0x0240e51b, 0x00000004 },
- { 0x0080e50a, 0x00000005 },
- { 0x0080e50b, 0x00000005 },
- { 0x00220000, 0x00000004 },
- { 0x000700cb, 0x00000004 },
- { 0x000000b7, 0x00000038 },
- { 0x000c2087, 0x00000030 },
- { 0x0880e5bd, 0x00000005 },
- { 0x000c2086, 0x00000030 },
- { 0x0800e5bb, 0x00000005 },
- { 0x000c2087, 0x00000030 },
- { 0x0880e5bc, 0x00000005 },
- { 0x000000ba, 0x00000008 },
- { 0x0080e5bd, 0x00000005 },
- { 0x0000e5bb, 0x00000005 },
- { 0x0080e5bc, 0x00000005 },
- { 0x00210000, 0x00000004 },
- { 0x02800000, 0x00000004 },
- { 0x00c000be, 0x00000018 },
- { 0x4180e000, 0x00000040 },
- { 0x000000c0, 0x00000024 },
- { 0x01000000, 0x0000000c },
- { 0x0100e51d, 0x0000000c },
- { 0x000045bb, 0x00000004 },
- { 0x000080ba, 0x00000008 },
- { 0x03c00830, 0x00000004 },
- { 0x4200e000, 0000000000 },
- { 0x0000a000, 0x00000004 },
- { 0x200045e0, 0x00000004 },
- { 0x0000e5e1, 0000000000 },
- { 0x00000001, 0000000000 },
- { 0x000700c8, 0x00000004 },
- { 0x0800e394, 0000000000 },
- { 0000000000, 0000000000 },
- { 0x0000e8c4, 0x00000004 },
- { 0x0000e8c5, 0x00000004 },
- { 0x0000e8c6, 0x00000004 },
- { 0x0000e928, 0x00000004 },
- { 0x0000e929, 0x00000004 },
- { 0x0000e92a, 0x00000004 },
- { 0x000000cc, 0x00000008 },
- { 0x0000e928, 0x00000004 },
- { 0x0000e929, 0x00000004 },
- { 0x0000e92a, 0x00000004 },
- { 0x000000d3, 0x00000008 },
- { 0x02c02000, 0x00000004 },
- { 0x00060000, 0x00000004 },
- { 0x000000db, 0x00000034 },
- { 0x000000d8, 0x00000008 },
- { 0x00008000, 0x00000004 },
- { 0xc000e000, 0000000000 },
- { 0x000000e1, 0x00000030 },
- { 0x4200e000, 0000000000 },
- { 0x000000e1, 0x00000030 },
- { 0x4000e000, 0000000000 },
- { 0x0025001b, 0x00000004 },
- { 0x00230000, 0x00000004 },
- { 0x00250005, 0x00000004 },
- { 0x000000e6, 0x00000034 },
- { 0000000000, 0x0000000c },
- { 0x00244000, 0x00000004 },
- { 0x080045c8, 0x00000004 },
- { 0x00240005, 0x00000004 },
- { 0x08004d0b, 0x0000000c },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x001d0018, 0x00000004 },
- { 0x001a0001, 0x00000004 },
- { 0x000000fb, 0x00000034 },
- { 0x0000004a, 0x00000008 },
- { 0x0500a04a, 0x00000008 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
-};
-
-static const u32 R520_cp_microcode[][2] = {
- { 0x4200e000, 0000000000 },
- { 0x4000e000, 0000000000 },
- { 0x00000099, 0x00000008 },
- { 0x0000009d, 0x00000008 },
- { 0x4a554b4a, 0000000000 },
- { 0x4a4a4467, 0000000000 },
- { 0x55526f75, 0000000000 },
- { 0x4a7e7d65, 0000000000 },
- { 0xe0dae6f6, 0000000000 },
- { 0x4ac54a4a, 0000000000 },
- { 0xc8828282, 0000000000 },
- { 0xbf4acfc1, 0000000000 },
- { 0x87b04ad5, 0000000000 },
- { 0xb5838383, 0000000000 },
- { 0x4a0f85ba, 0000000000 },
- { 0x000ca000, 0x00000004 },
- { 0x000d0012, 0x00000038 },
- { 0x0000e8b4, 0x00000004 },
- { 0x000d0014, 0x00000038 },
- { 0x0000e8b6, 0x00000004 },
- { 0x000d0016, 0x00000038 },
- { 0x0000e854, 0x00000004 },
- { 0x000d0018, 0x00000038 },
- { 0x0000e855, 0x00000004 },
- { 0x000d001a, 0x00000038 },
- { 0x0000e856, 0x00000004 },
- { 0x000d001c, 0x00000038 },
- { 0x0000e857, 0x00000004 },
- { 0x000d001e, 0x00000038 },
- { 0x0000e824, 0x00000004 },
- { 0x000d0020, 0x00000038 },
- { 0x0000e825, 0x00000004 },
- { 0x000d0022, 0x00000038 },
- { 0x0000e830, 0x00000004 },
- { 0x000d0024, 0x00000038 },
- { 0x0000f0c0, 0x00000004 },
- { 0x000d0026, 0x00000038 },
- { 0x0000f0c1, 0x00000004 },
- { 0x000d0028, 0x00000038 },
- { 0x0000e000, 0x00000004 },
- { 0x000d002a, 0x00000038 },
- { 0x0000e000, 0x00000004 },
- { 0x000d002c, 0x00000038 },
- { 0x0000e000, 0x00000004 },
- { 0x000d002e, 0x00000038 },
- { 0x0000e000, 0x00000004 },
- { 0x000d0030, 0x00000038 },
- { 0x0000e000, 0x00000004 },
- { 0x000d0032, 0x00000038 },
- { 0x0000f180, 0x00000004 },
- { 0x000d0034, 0x00000038 },
- { 0x0000f393, 0x00000004 },
- { 0x000d0036, 0x00000038 },
- { 0x0000f38a, 0x00000004 },
- { 0x000d0038, 0x00000038 },
- { 0x0000f38e, 0x00000004 },
- { 0x0000e821, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00000043, 0x00000018 },
- { 0x00cce800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x08004800, 0x00000004 },
- { 0x0000003a, 0x00000008 },
- { 0x0000a000, 0000000000 },
- { 0x2000451d, 0x00000004 },
- { 0x0000e580, 0x00000004 },
- { 0x000ce581, 0x00000004 },
- { 0x08004580, 0x00000004 },
- { 0x000ce581, 0x00000004 },
- { 0x00000047, 0x00000008 },
- { 0x0000a000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x0000e50e, 0x00000004 },
- { 0x00032000, 0x00000004 },
- { 0x00022051, 0x00000028 },
- { 0x00000051, 0x00000024 },
- { 0x0800450f, 0x00000004 },
- { 0x0000a04b, 0x00000008 },
- { 0x0000e565, 0x00000004 },
- { 0x0000e566, 0x00000004 },
- { 0x00000052, 0x00000008 },
- { 0x03cca5b4, 0x00000004 },
- { 0x05432000, 0x00000004 },
- { 0x00022000, 0x00000004 },
- { 0x4ccce05e, 0x00000030 },
- { 0x08274565, 0x00000004 },
- { 0x0000005e, 0x00000030 },
- { 0x08004564, 0x00000004 },
- { 0x0000e566, 0x00000004 },
- { 0x00000055, 0x00000008 },
- { 0x00802061, 0x00000010 },
- { 0x00202000, 0x00000004 },
- { 0x001b00ff, 0x00000004 },
- { 0x01000064, 0x00000010 },
- { 0x001f2000, 0x00000004 },
- { 0x001c00ff, 0x00000004 },
- { 0000000000, 0x0000000c },
- { 0x00000072, 0x00000030 },
- { 0x00000055, 0x00000008 },
- { 0x0000e576, 0x00000004 },
- { 0x0000e577, 0x00000004 },
- { 0x0000e50e, 0x00000004 },
- { 0x0000e50f, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00000069, 0x00000018 },
- { 0x00c0e5f9, 0x000000c2 },
- { 0x00000069, 0x00000008 },
- { 0x0014e50e, 0x00000004 },
- { 0x0040e50f, 0x00000004 },
- { 0x00c0006c, 0x00000008 },
- { 0x0000e570, 0x00000004 },
- { 0x0000e571, 0x00000004 },
- { 0x0000e572, 0x0000000c },
- { 0x0000a000, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x0000e568, 0x00000004 },
- { 0x000c2000, 0x00000004 },
- { 0x00000076, 0x00000018 },
- { 0x000b0000, 0x00000004 },
- { 0x18c0e562, 0x00000004 },
- { 0x00000078, 0x00000008 },
- { 0x00c00077, 0x00000008 },
- { 0x000700c7, 0x00000004 },
- { 0x00000080, 0x00000038 },
- { 0x0000e5bb, 0x00000004 },
- { 0x0000e5bc, 0000000000 },
- { 0x0000a000, 0x00000004 },
- { 0x0000e821, 0x00000004 },
- { 0x0000e800, 0000000000 },
- { 0x0000e821, 0x00000004 },
- { 0x0000e82e, 0000000000 },
- { 0x02cca000, 0x00000004 },
- { 0x00140000, 0x00000004 },
- { 0x000ce1cc, 0x00000004 },
- { 0x050de1cd, 0x00000004 },
- { 0x00400000, 0x00000004 },
- { 0x0000008f, 0x00000018 },
- { 0x00c0a000, 0x00000004 },
- { 0x0000008c, 0x00000008 },
- { 0x00000091, 0x00000020 },
- { 0x4200e000, 0000000000 },
- { 0x00000098, 0x00000038 },
- { 0x000ca000, 0x00000004 },
- { 0x00140000, 0x00000004 },
- { 0x000c2000, 0x00000004 },
- { 0x00160000, 0x00000004 },
- { 0x700ce000, 0x00000004 },
- { 0x00140094, 0x00000008 },
- { 0x4000e000, 0000000000 },
- { 0x02400000, 0x00000004 },
- { 0x400ee000, 0x00000004 },
- { 0x02400000, 0x00000004 },
- { 0x4000e000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x0240e51b, 0x00000004 },
- { 0x0080e50a, 0x00000005 },
- { 0x0080e50b, 0x00000005 },
- { 0x00220000, 0x00000004 },
- { 0x000700c7, 0x00000004 },
- { 0x000000a4, 0x00000038 },
- { 0x0080e5bd, 0x00000005 },
- { 0x0000e5bb, 0x00000005 },
- { 0x0080e5bc, 0x00000005 },
- { 0x00210000, 0x00000004 },
- { 0x02800000, 0x00000004 },
- { 0x00c000ab, 0x00000018 },
- { 0x4180e000, 0x00000040 },
- { 0x000000ad, 0x00000024 },
- { 0x01000000, 0x0000000c },
- { 0x0100e51d, 0x0000000c },
- { 0x000045bb, 0x00000004 },
- { 0x000080a7, 0x00000008 },
- { 0x0000f3ce, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00cc2000, 0x00000004 },
- { 0x08c053cf, 0x00000040 },
- { 0x00008000, 0000000000 },
- { 0x0000f3d2, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00cc2000, 0x00000004 },
- { 0x08c053d3, 0x00000040 },
- { 0x00008000, 0000000000 },
- { 0x0000f39d, 0x00000004 },
- { 0x0140a000, 0x00000004 },
- { 0x00cc2000, 0x00000004 },
- { 0x08c0539e, 0x00000040 },
- { 0x00008000, 0000000000 },
- { 0x03c00830, 0x00000004 },
- { 0x4200e000, 0000000000 },
- { 0x0000a000, 0x00000004 },
- { 0x200045e0, 0x00000004 },
- { 0x0000e5e1, 0000000000 },
- { 0x00000001, 0000000000 },
- { 0x000700c4, 0x00000004 },
- { 0x0800e394, 0000000000 },
- { 0000000000, 0000000000 },
- { 0x0000e8c4, 0x00000004 },
- { 0x0000e8c5, 0x00000004 },
- { 0x0000e8c6, 0x00000004 },
- { 0x0000e928, 0x00000004 },
- { 0x0000e929, 0x00000004 },
- { 0x0000e92a, 0x00000004 },
- { 0x000000c8, 0x00000008 },
- { 0x0000e928, 0x00000004 },
- { 0x0000e929, 0x00000004 },
- { 0x0000e92a, 0x00000004 },
- { 0x000000cf, 0x00000008 },
- { 0xdeadbeef, 0000000000 },
- { 0x00000116, 0000000000 },
- { 0x000700d3, 0x00000004 },
- { 0x080050e7, 0x00000004 },
- { 0x000700d4, 0x00000004 },
- { 0x0800401c, 0x00000004 },
- { 0x0000e01d, 0000000000 },
- { 0x02c02000, 0x00000004 },
- { 0x00060000, 0x00000004 },
- { 0x000000de, 0x00000034 },
- { 0x000000db, 0x00000008 },
- { 0x00008000, 0x00000004 },
- { 0xc000e000, 0000000000 },
- { 0x0000e1cc, 0x00000004 },
- { 0x0500e1cd, 0x00000004 },
- { 0x000ca000, 0x00000004 },
- { 0x000000e5, 0x00000034 },
- { 0x000000e1, 0x00000008 },
- { 0x0000a000, 0000000000 },
- { 0x0019e1cc, 0x00000004 },
- { 0x001b0001, 0x00000004 },
- { 0x0500a000, 0x00000004 },
- { 0x080041cd, 0x00000004 },
- { 0x000ca000, 0x00000004 },
- { 0x000000fb, 0x00000034 },
- { 0x0000004a, 0x00000008 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0x000c2000, 0x00000004 },
- { 0x001d0018, 0x00000004 },
- { 0x001a0001, 0x00000004 },
- { 0x000000fb, 0x00000034 },
- { 0x0000004a, 0x00000008 },
- { 0x0500a04a, 0x00000008 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
- { 0000000000, 0000000000 },
-};
-
-
-#endif
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 3b09a1f..570a587 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -175,6 +175,15 @@ struct radeon_mode_info {
enum radeon_connector_table connector_table;
bool mode_config_initialized;
struct radeon_crtc *crtcs[2];
+ /* DVI-I properties */
+ struct drm_property *coherent_mode_property;
+ /* DAC enable load detect */
+ struct drm_property *load_detect_property;
+ /* TV standard load detect */
+ struct drm_property *tv_std_property;
+ /* legacy TMDS PLL detect */
+ struct drm_property *tmds_pll_property;
+
};
struct radeon_native_mode {
@@ -188,6 +197,21 @@ struct radeon_native_mode {
uint32_t flags;
};
+#define MAX_H_CODE_TIMING_LEN 32
+#define MAX_V_CODE_TIMING_LEN 32
+
+/* need to store these as reading
+ back code tables is excessive */
+struct radeon_tv_regs {
+ uint32_t tv_uv_adr;
+ uint32_t timing_cntl;
+ uint32_t hrestart;
+ uint32_t vrestart;
+ uint32_t frestart;
+ uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
+ uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
+};
+
struct radeon_crtc {
struct drm_crtc base;
int crtc_id;
@@ -195,8 +219,6 @@ struct radeon_crtc {
bool enabled;
bool can_tile;
uint32_t crtc_offset;
- struct radeon_framebuffer *fbdev_fb;
- struct drm_mode_set mode_set;
struct drm_gem_object *cursor_bo;
uint64_t cursor_addr;
int cursor_width;
@@ -204,7 +226,6 @@ struct radeon_crtc {
uint32_t legacy_display_base_addr;
uint32_t legacy_cursor_offset;
enum radeon_rmx_type rmx_type;
- uint32_t devices;
fixed20_12 vsc;
fixed20_12 hsc;
struct radeon_native_mode native_mode;
@@ -236,7 +257,13 @@ struct radeon_encoder_tv_dac {
uint32_t ntsc_tvdac_adj;
uint32_t pal_tvdac_adj;
+ int h_pos;
+ int v_pos;
+ int h_size;
+ int supported_tv_stds;
+ bool tv_on;
enum radeon_tv_std tv_std;
+ struct radeon_tv_regs tv;
};
struct radeon_encoder_int_tmds {
@@ -255,10 +282,15 @@ struct radeon_encoder_atom_dig {
struct radeon_native_mode native_mode;
};
+struct radeon_encoder_atom_dac {
+ enum radeon_tv_std tv_std;
+};
+
struct radeon_encoder {
struct drm_encoder base;
uint32_t encoder_id;
uint32_t devices;
+ uint32_t active_device;
uint32_t flags;
uint32_t pixel_clock;
enum radeon_rmx_type rmx_type;
@@ -276,8 +308,12 @@ struct radeon_connector {
uint32_t connector_id;
uint32_t devices;
struct radeon_i2c_chan *ddc_bus;
- int use_digital;
+ bool use_digital;
+ /* we need to mind the EDID between detect
+ and get modes due to analog/digital/tvencoder */
+ struct edid *edid;
void *con_priv;
+ bool dac_load_detect;
};
struct radeon_framebuffer {
@@ -310,6 +346,7 @@ struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, i
struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
+extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
@@ -337,16 +374,18 @@ extern bool radeon_atom_get_clock_info(struct drm_device *dev);
extern bool radeon_combios_get_clock_info(struct drm_device *dev);
extern struct radeon_encoder_atom_dig *
radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
-extern struct radeon_encoder_int_tmds *
-radeon_atombios_get_tmds_info(struct radeon_encoder *encoder);
+bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
+ struct radeon_encoder_int_tmds *tmds);
+bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
+ struct radeon_encoder_int_tmds *tmds);
+bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
+ struct radeon_encoder_int_tmds *tmds);
extern struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_lvds *
radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
-extern struct radeon_encoder_int_tmds *
-radeon_combios_get_tmds_info(struct radeon_encoder *encoder);
extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_tv_dac *
radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
@@ -356,6 +395,8 @@ extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
+extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
+extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
extern void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
extern void
@@ -396,6 +437,19 @@ extern int radeon_static_clocks_init(struct drm_device *dev);
bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
-void atom_rv515_force_tv_scaler(struct radeon_device *rdev);
-
+void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
+
+/* legacy tv */
+void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
+ uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
+ uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
+void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
+ uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
+ uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
+void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
+ uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
+ uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
+void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode);
#endif
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index b85fb83..73af463 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -188,6 +188,7 @@ int radeon_object_kmap(struct radeon_object *robj, void **ptr)
if (ptr) {
*ptr = robj->kptr;
}
+ radeon_object_check_tiling(robj, 0, 0);
return 0;
}
@@ -200,6 +201,7 @@ void radeon_object_kunmap(struct radeon_object *robj)
}
robj->kptr = NULL;
spin_unlock(&robj->tobj.lock);
+ radeon_object_check_tiling(robj, 0, 0);
ttm_bo_kunmap(&robj->kmap);
}
@@ -369,6 +371,14 @@ void radeon_object_force_delete(struct radeon_device *rdev)
int radeon_object_init(struct radeon_device *rdev)
{
+ /* Add an MTRR for the VRAM */
+ rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
+ MTRR_TYPE_WRCOMB, 1);
+ DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
+ rdev->mc.mc_vram_size >> 20,
+ (unsigned long long)rdev->mc.aper_size >> 20);
+ DRM_INFO("RAM width %dbits %cDR\n",
+ rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
return radeon_ttm_init(rdev);
}
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
index 473e477..10e8af6 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -37,6 +37,7 @@
* TTM.
*/
struct radeon_mman {
+ struct ttm_bo_global_ref bo_global_ref;
struct ttm_global_reference mem_global_ref;
bool mem_global_referenced;
struct ttm_bo_device bdev;
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 4df43f6..21da871 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -1945,6 +1945,11 @@
# define RADEON_TXFORMAT_DXT1 (12 << 0)
# define RADEON_TXFORMAT_DXT23 (14 << 0)
# define RADEON_TXFORMAT_DXT45 (15 << 0)
+# define RADEON_TXFORMAT_SHADOW16 (16 << 0)
+# define RADEON_TXFORMAT_SHADOW32 (17 << 0)
+# define RADEON_TXFORMAT_DUDV88 (18 << 0)
+# define RADEON_TXFORMAT_LDUDV655 (19 << 0)
+# define RADEON_TXFORMAT_LDUDUV8888 (20 << 0)
# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
# define RADEON_TXFORMAT_FORMAT_SHIFT 0
# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
@@ -2203,7 +2208,7 @@
# define RADEON_ROP_ENABLE (1 << 6)
# define RADEON_STENCIL_ENABLE (1 << 7)
# define RADEON_Z_ENABLE (1 << 8)
-# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9)
+# define RADEON_DEPTHXY_OFFSET_ENABLE (1 << 9)
# define RADEON_RB3D_COLOR_FORMAT_SHIFT 10
# define RADEON_COLOR_FORMAT_ARGB1555 3
@@ -2773,7 +2778,12 @@
# define R200_TXFORMAT_DXT1 (12 << 0)
# define R200_TXFORMAT_DXT23 (14 << 0)
# define R200_TXFORMAT_DXT45 (15 << 0)
+# define R200_TXFORMAT_DVDU88 (18 << 0)
+# define R200_TXFORMAT_LDVDU655 (19 << 0)
+# define R200_TXFORMAT_LDVDU8888 (20 << 0)
+# define R200_TXFORMAT_GR1616 (21 << 0)
# define R200_TXFORMAT_ABGR8888 (22 << 0)
+# define R200_TXFORMAT_BGR111110 (23 << 0)
# define R200_TXFORMAT_FORMAT_MASK (31 << 0)
# define R200_TXFORMAT_FORMAT_SHIFT 0
# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6)
@@ -2818,6 +2828,13 @@
#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */
#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */
+#define R200_PP_CUBIC_FACES_0 0x2c18
+#define R200_PP_CUBIC_FACES_1 0x2c38
+#define R200_PP_CUBIC_FACES_2 0x2c58
+#define R200_PP_CUBIC_FACES_3 0x2c78
+#define R200_PP_CUBIC_FACES_4 0x2c98
+#define R200_PP_CUBIC_FACES_5 0x2cb8
+
#define R200_PP_TXOFFSET_0 0x2d00
# define R200_TXO_ENDIAN_NO_SWAP (0 << 0)
# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0)
@@ -2829,11 +2846,44 @@
# define R200_TXO_MICRO_TILE (1 << 3)
# define R200_TXO_OFFSET_MASK 0xffffffe0
# define R200_TXO_OFFSET_SHIFT 5
+#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
+#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
+#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
+#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
+#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
+
#define R200_PP_TXOFFSET_1 0x2d18
+#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
+#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
+#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
+#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
+#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
+
#define R200_PP_TXOFFSET_2 0x2d30
+#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
+#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
+#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
+#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
+#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
+
#define R200_PP_TXOFFSET_3 0x2d48
+#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
+#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
+#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
+#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
+#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
#define R200_PP_TXOFFSET_4 0x2d60
+#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
+#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
+#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
+#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
+#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
#define R200_PP_TXOFFSET_5 0x2d78
+#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
+#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
+#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
+#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
+#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
#define R200_PP_TFACTOR_0 0x2ee0
#define R200_PP_TFACTOR_1 0x2ee4
@@ -3175,6 +3225,11 @@
# define R200_FORCE_INORDER_PROC (1<<31)
#define R200_PP_CNTL_X 0x2cc4
#define R200_PP_TXMULTI_CTL_0 0x2c1c
+#define R200_PP_TXMULTI_CTL_1 0x2c3c
+#define R200_PP_TXMULTI_CTL_2 0x2c5c
+#define R200_PP_TXMULTI_CTL_3 0x2c7c
+#define R200_PP_TXMULTI_CTL_4 0x2c9c
+#define R200_PP_TXMULTI_CTL_5 0x2cbc
#define R200_SE_VTX_STATE_CNTL 0x2180
# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)
@@ -3200,6 +3255,24 @@
#define RADEON_CP_RB_WPTR 0x0714
#define RADEON_CP_RB_RPTR_WR 0x071c
+#define RADEON_SCRATCH_UMSK 0x0770
+#define RADEON_SCRATCH_ADDR 0x0774
+
+#define R600_CP_RB_BASE 0xc100
+#define R600_CP_RB_CNTL 0xc104
+# define R600_RB_BUFSZ(x) ((x) << 0)
+# define R600_RB_BLKSZ(x) ((x) << 8)
+# define R600_RB_NO_UPDATE (1 << 27)
+# define R600_RB_RPTR_WR_ENA (1 << 31)
+#define R600_CP_RB_RPTR_WR 0xc108
+#define R600_CP_RB_RPTR_ADDR 0xc10c
+#define R600_CP_RB_RPTR_ADDR_HI 0xc110
+#define R600_CP_RB_WPTR 0xc114
+#define R600_CP_RB_WPTR_ADDR 0xc118
+#define R600_CP_RB_WPTR_ADDR_HI 0xc11c
+#define R600_CP_RB_RPTR 0x8700
+#define R600_CP_RB_WPTR_DELAY 0x8704
+
#define RADEON_CP_IB_BASE 0x0738
#define RADEON_CP_IB_BUFSZ 0x073c
@@ -3407,7 +3480,9 @@
# define RADEON_RGB_CONVERT_BY_PASS (1 << 10)
# define RADEON_UVRAM_READ_MARGIN_SHIFT 16
# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20
-# define RADEON_TVOUT_SCALE_EN (1 << 26)
+# define RADEON_RGB_ATTEN_SEL(x) ((x) << 24)
+# define RADEON_TVOUT_SCALE_EN (1 << 26)
+# define RADEON_RGB_ATTEN_VAL(x) ((x) << 28)
#define RADEON_TV_SYNC_CNTL 0x0808
# define RADEON_SYNC_OE (1 << 0)
# define RADEON_SYNC_OUT (1 << 1)
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 60d1593..747b4bf 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -56,10 +56,12 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
set_bit(i, rdev->ib_pool.alloc_bm);
rdev->ib_pool.ibs[i].length_dw = 0;
*ib = &rdev->ib_pool.ibs[i];
+ mutex_unlock(&rdev->ib_pool.mutex);
goto out;
}
if (list_empty(&rdev->ib_pool.scheduled_ibs)) {
/* we go do nothings here */
+ mutex_unlock(&rdev->ib_pool.mutex);
DRM_ERROR("all IB allocated none scheduled.\n");
r = -EINVAL;
goto out;
@@ -69,10 +71,13 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
struct radeon_ib, list);
if (nib->fence == NULL) {
/* we go do nothings here */
+ mutex_unlock(&rdev->ib_pool.mutex);
DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx);
r = -EINVAL;
goto out;
}
+ mutex_unlock(&rdev->ib_pool.mutex);
+
r = radeon_fence_wait(nib->fence, false);
if (r) {
DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx,
@@ -81,12 +86,17 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
goto out;
}
radeon_fence_unref(&nib->fence);
+
nib->length_dw = 0;
+
+ /* scheduled list is accessed here */
+ mutex_lock(&rdev->ib_pool.mutex);
list_del(&nib->list);
INIT_LIST_HEAD(&nib->list);
+ mutex_unlock(&rdev->ib_pool.mutex);
+
*ib = nib;
out:
- mutex_unlock(&rdev->ib_pool.mutex);
if (r) {
radeon_fence_unref(&fence);
} else {
@@ -111,47 +121,36 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
}
list_del(&tmp->list);
INIT_LIST_HEAD(&tmp->list);
- if (tmp->fence) {
+ if (tmp->fence)
radeon_fence_unref(&tmp->fence);
- }
+
tmp->length_dw = 0;
clear_bit(tmp->idx, rdev->ib_pool.alloc_bm);
mutex_unlock(&rdev->ib_pool.mutex);
}
-static void radeon_ib_align(struct radeon_device *rdev, struct radeon_ib *ib)
-{
- while ((ib->length_dw & rdev->cp.align_mask)) {
- ib->ptr[ib->length_dw++] = PACKET2(0);
- }
-}
-
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
{
int r = 0;
- mutex_lock(&rdev->ib_pool.mutex);
- radeon_ib_align(rdev, ib);
if (!ib->length_dw || !rdev->cp.ready) {
/* TODO: Nothings in the ib we should report. */
- mutex_unlock(&rdev->ib_pool.mutex);
DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx);
return -EINVAL;
}
+
/* 64 dwords should be enough for fence too */
r = radeon_ring_lock(rdev, 64);
if (r) {
DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
- mutex_unlock(&rdev->ib_pool.mutex);
return r;
}
- radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
- radeon_ring_write(rdev, ib->gpu_addr);
- radeon_ring_write(rdev, ib->length_dw);
+ radeon_ring_ib_execute(rdev, ib);
radeon_fence_emit(rdev, ib->fence);
- radeon_ring_unlock_commit(rdev);
+ mutex_lock(&rdev->ib_pool.mutex);
list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs);
mutex_unlock(&rdev->ib_pool.mutex);
+ radeon_ring_unlock_commit(rdev);
return 0;
}
@@ -162,6 +161,8 @@ int radeon_ib_pool_init(struct radeon_device *rdev)
int i;
int r = 0;
+ if (rdev->ib_pool.robj)
+ return 0;
/* Allocate 1M object buffer */
INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs);
r = radeon_object_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
@@ -215,69 +216,16 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
mutex_unlock(&rdev->ib_pool.mutex);
}
-int radeon_ib_test(struct radeon_device *rdev)
-{
- struct radeon_ib *ib;
- uint32_t scratch;
- uint32_t tmp = 0;
- unsigned i;
- int r;
-
- r = radeon_scratch_get(rdev, &scratch);
- if (r) {
- DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
- return r;
- }
- WREG32(scratch, 0xCAFEDEAD);
- r = radeon_ib_get(rdev, &ib);
- if (r) {
- return r;
- }
- ib->ptr[0] = PACKET0(scratch, 0);
- ib->ptr[1] = 0xDEADBEEF;
- ib->ptr[2] = PACKET2(0);
- ib->ptr[3] = PACKET2(0);
- ib->ptr[4] = PACKET2(0);
- ib->ptr[5] = PACKET2(0);
- ib->ptr[6] = PACKET2(0);
- ib->ptr[7] = PACKET2(0);
- ib->length_dw = 8;
- r = radeon_ib_schedule(rdev, ib);
- if (r) {
- radeon_scratch_free(rdev, scratch);
- radeon_ib_free(rdev, &ib);
- return r;
- }
- r = radeon_fence_wait(ib->fence, false);
- if (r) {
- return r;
- }
- for (i = 0; i < rdev->usec_timeout; i++) {
- tmp = RREG32(scratch);
- if (tmp == 0xDEADBEEF) {
- break;
- }
- DRM_UDELAY(1);
- }
- if (i < rdev->usec_timeout) {
- DRM_INFO("ib test succeeded in %u usecs\n", i);
- } else {
- DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
- scratch, tmp);
- r = -EINVAL;
- }
- radeon_scratch_free(rdev, scratch);
- radeon_ib_free(rdev, &ib);
- return r;
-}
-
/*
* Ring.
*/
void radeon_ring_free_size(struct radeon_device *rdev)
{
- rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
+ if (rdev->family >= CHIP_R600)
+ rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
+ else
+ rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
/* This works because ring_size is a power of 2 */
rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
rdev->cp.ring_free_dw -= rdev->cp.wptr;
@@ -320,11 +268,10 @@ void radeon_ring_unlock_commit(struct radeon_device *rdev)
count_dw_pad = (rdev->cp.align_mask + 1) -
(rdev->cp.wptr & rdev->cp.align_mask);
for (i = 0; i < count_dw_pad; i++) {
- radeon_ring_write(rdev, PACKET2(0));
+ radeon_ring_write(rdev, 2 << 30);
}
DRM_MEMORYBARRIER();
- WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
- (void)RREG32(RADEON_CP_RB_WPTR);
+ radeon_cp_commit(rdev);
mutex_unlock(&rdev->cp.mutex);
}
@@ -334,46 +281,6 @@ void radeon_ring_unlock_undo(struct radeon_device *rdev)
mutex_unlock(&rdev->cp.mutex);
}
-int radeon_ring_test(struct radeon_device *rdev)
-{
- uint32_t scratch;
- uint32_t tmp = 0;
- unsigned i;
- int r;
-
- r = radeon_scratch_get(rdev, &scratch);
- if (r) {
- DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
- return r;
- }
- WREG32(scratch, 0xCAFEDEAD);
- r = radeon_ring_lock(rdev, 2);
- if (r) {
- DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
- radeon_scratch_free(rdev, scratch);
- return r;
- }
- radeon_ring_write(rdev, PACKET0(scratch, 0));
- radeon_ring_write(rdev, 0xDEADBEEF);
- radeon_ring_unlock_commit(rdev);
- for (i = 0; i < rdev->usec_timeout; i++) {
- tmp = RREG32(scratch);
- if (tmp == 0xDEADBEEF) {
- break;
- }
- DRM_UDELAY(1);
- }
- if (i < rdev->usec_timeout) {
- DRM_INFO("ring test succeeded in %d usecs\n", i);
- } else {
- DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
- scratch, tmp);
- r = -EINVAL;
- }
- radeon_scratch_free(rdev, scratch);
- return r;
-}
-
int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
{
int r;
diff --git a/drivers/gpu/drm/radeon/radeon_share.h b/drivers/gpu/drm/radeon/radeon_share.h
deleted file mode 100644
index 63a7735..0000000
--- a/drivers/gpu/drm/radeon/radeon_share.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- * Alex Deucher
- * Jerome Glisse
- */
-#ifndef __RADEON_SHARE_H__
-#define __RADEON_SHARE_H__
-
-void r100_vram_init_sizes(struct radeon_device *rdev);
-
-void rs690_line_buffer_adjust(struct radeon_device *rdev,
- struct drm_display_mode *mode1,
- struct drm_display_mode *mode2);
-
-void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
-
-#endif
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index 2882f40..38537d9 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -1546,7 +1546,7 @@ static void radeon_cp_dispatch_vertex(struct drm_device * dev,
} while (i < nbox);
}
-static void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
+void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = master->driver_priv;
@@ -2213,7 +2213,10 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f
if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
- radeon_cp_dispatch_swap(dev, file_priv->master);
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+ r600_cp_dispatch_swap(dev, file_priv);
+ else
+ radeon_cp_dispatch_swap(dev, file_priv->master);
sarea_priv->ctx_owner = 0;
COMMIT_RING();
@@ -2412,7 +2415,10 @@ static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file
RING_SPACE_TEST_WITH_RETURN(dev_priv);
VB_AGE_TEST_WITH_RETURN(dev_priv);
- ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+ ret = r600_cp_dispatch_texture(dev, file_priv, tex, &image);
+ else
+ ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);
return ret;
}
@@ -2495,8 +2501,9 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil
radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
}
- if (indirect->discard)
+ if (indirect->discard) {
radeon_cp_discard_buffer(dev, file_priv->master, buf);
+ }
COMMIT_RING();
return 0;
@@ -3027,7 +3034,10 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
value = GET_SCRATCH(dev_priv, 2);
break;
case RADEON_PARAM_IRQ_NR:
- value = drm_dev_to_irq(dev);
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+ value = 0;
+ else
+ value = drm_dev_to_irq(dev);
break;
case RADEON_PARAM_GART_BASE:
value = dev_priv->gart_vm_start;
@@ -3227,7 +3237,8 @@ struct drm_ioctl_desc radeon_ioctls[] = {
DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
- DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH)
+ DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH)
};
int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 15c3531..acd889c 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -35,11 +35,14 @@
#include <ttm/ttm_module.h>
#include <drm/drmP.h>
#include <drm/radeon_drm.h>
+#include <linux/seq_file.h>
#include "radeon_reg.h"
#include "radeon.h"
#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
+static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
+
static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
{
struct radeon_mman *mman;
@@ -77,9 +80,25 @@ static int radeon_ttm_global_init(struct radeon_device *rdev)
global_ref->release = &radeon_ttm_mem_global_release;
r = ttm_global_item_ref(global_ref);
if (r != 0) {
- DRM_ERROR("Failed referencing a global TTM memory object.\n");
+ DRM_ERROR("Failed setting up TTM memory accounting "
+ "subsystem.\n");
+ return r;
+ }
+
+ rdev->mman.bo_global_ref.mem_glob =
+ rdev->mman.mem_global_ref.object;
+ global_ref = &rdev->mman.bo_global_ref.ref;
+ global_ref->global_type = TTM_GLOBAL_TTM_BO;
+ global_ref->size = sizeof(struct ttm_bo_global);
+ global_ref->init = &ttm_bo_global_init;
+ global_ref->release = &ttm_bo_global_release;
+ r = ttm_global_item_ref(global_ref);
+ if (r != 0) {
+ DRM_ERROR("Failed setting up TTM BO subsystem.\n");
+ ttm_global_item_unref(&rdev->mman.mem_global_ref);
return r;
}
+
rdev->mman.mem_global_referenced = true;
return 0;
}
@@ -87,6 +106,7 @@ static int radeon_ttm_global_init(struct radeon_device *rdev)
static void radeon_ttm_global_fini(struct radeon_device *rdev)
{
if (rdev->mman.mem_global_referenced) {
+ ttm_global_item_unref(&rdev->mman.bo_global_ref.ref);
ttm_global_item_unref(&rdev->mman.mem_global_ref);
rdev->mman.mem_global_referenced = false;
}
@@ -286,9 +306,11 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
r = ttm_bo_move_ttm(bo, true, no_wait, new_mem);
out_cleanup:
if (tmp_mem.mm_node) {
- spin_lock(&rdev->mman.bdev.lru_lock);
+ struct ttm_bo_global *glob = rdev->mman.bdev.glob;
+
+ spin_lock(&glob->lru_lock);
drm_mm_put_block(tmp_mem.mm_node);
- spin_unlock(&rdev->mman.bdev.lru_lock);
+ spin_unlock(&glob->lru_lock);
return r;
}
return r;
@@ -323,9 +345,11 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
}
out_cleanup:
if (tmp_mem.mm_node) {
- spin_lock(&rdev->mman.bdev.lru_lock);
+ struct ttm_bo_global *glob = rdev->mman.bdev.glob;
+
+ spin_lock(&glob->lru_lock);
drm_mm_put_block(tmp_mem.mm_node);
- spin_unlock(&rdev->mman.bdev.lru_lock);
+ spin_unlock(&glob->lru_lock);
return r;
}
return r;
@@ -352,9 +376,8 @@ static int radeon_bo_move(struct ttm_buffer_object *bo,
radeon_move_null(bo, new_mem);
return 0;
}
- if (!rdev->cp.ready) {
+ if (!rdev->cp.ready || rdev->asic->copy == NULL) {
/* use memcpy */
- DRM_ERROR("CP is not ready use memcpy.\n");
goto memcpy;
}
@@ -446,7 +469,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
}
/* No others user of address space so set it to 0 */
r = ttm_bo_device_init(&rdev->mman.bdev,
- rdev->mman.mem_global_ref.object,
+ rdev->mman.bo_global_ref.ref.object,
&radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
rdev->need_dma32);
if (r) {
@@ -471,7 +494,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
return r;
}
DRM_INFO("radeon: %uM of VRAM memory ready\n",
- rdev->mc.real_vram_size / (1024 * 1024));
+ (unsigned)rdev->mc.real_vram_size / (1024 * 1024));
r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 0,
((rdev->mc.gtt_size) >> PAGE_SHIFT));
if (r) {
@@ -479,10 +502,16 @@ int radeon_ttm_init(struct radeon_device *rdev)
return r;
}
DRM_INFO("radeon: %uM of GTT memory ready.\n",
- rdev->mc.gtt_size / (1024 * 1024));
+ (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
}
+
+ r = radeon_ttm_debugfs_init(rdev);
+ if (r) {
+ DRM_ERROR("Failed to init debugfs\n");
+ return r;
+ }
return 0;
}
@@ -657,3 +686,50 @@ struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev)
gtt->bound = false;
return &gtt->backend;
}
+
+#define RADEON_DEBUGFS_MEM_TYPES 2
+
+static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES];
+static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES][32];
+
+#if defined(CONFIG_DEBUG_FS)
+static int radeon_mm_dump_table(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = (struct drm_info_node *)m->private;
+ struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
+ struct drm_device *dev = node->minor->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ int ret;
+ struct ttm_bo_global *glob = rdev->mman.bdev.glob;
+
+ spin_lock(&glob->lru_lock);
+ ret = drm_mm_dump_table(m, mm);
+ spin_unlock(&glob->lru_lock);
+ return ret;
+}
+#endif
+
+static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
+{
+ unsigned i;
+
+#if defined(CONFIG_DEBUG_FS)
+ for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
+ if (i == 0)
+ sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
+ else
+ sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
+ radeon_mem_types_list[i].name = radeon_mem_types_names[i];
+ radeon_mem_types_list[i].show = &radeon_mm_dump_table;
+ radeon_mem_types_list[i].driver_features = 0;
+ if (i == 0)
+ radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_VRAM].manager;
+ else
+ radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_TT].manager;
+
+ }
+ return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES);
+
+#endif
+ return 0;
+}
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r100 b/drivers/gpu/drm/radeon/reg_srcs/r100
new file mode 100644
index 0000000..f7ee062
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r100
@@ -0,0 +1,105 @@
+r100 0x3294
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
+0x1810 FOG_3D_TABLE_START
+0x1814 FOG_3D_TABLE_END
+0x1a14 FOG_TABLE_INDEX
+0x1a18 FOG_TABLE_DATA
+0x1c14 PP_MISC
+0x1c18 PP_FOG_COLOR
+0x1c1c RE_SOLID_COLOR
+0x1c20 RB3D_BLENDCNTL
+0x1c4c SE_CNTL
+0x1c50 SE_COORD_FMT
+0x1c60 PP_TXCBLEND_0
+0x1c64 PP_TXABLEND_0
+0x1c68 PP_TFACTOR_0
+0x1c78 PP_TXCBLEND_1
+0x1c7c PP_TXABLEND_1
+0x1c80 PP_TFACTOR_1
+0x1c90 PP_TXCBLEND_2
+0x1c94 PP_TXABLEND_2
+0x1c98 PP_TFACTOR_2
+0x1cc8 RE_STIPPLE_ADDR
+0x1ccc RE_STIPPLE_DATA
+0x1cd0 RE_LINE_PATTERN
+0x1cd4 RE_LINE_STATE
+0x1d40 PP_BORDER_COLOR0
+0x1d44 PP_BORDER_COLOR1
+0x1d48 PP_BORDER_COLOR2
+0x1d7c RB3D_STENCILREFMASK
+0x1d80 RB3D_ROPCNTL
+0x1d84 RB3D_PLANEMASK
+0x1d98 VAP_VPORT_XSCALE
+0x1d9C VAP_VPORT_XOFFSET
+0x1da0 VAP_VPORT_YSCALE
+0x1da4 VAP_VPORT_YOFFSET
+0x1da8 VAP_VPORT_ZSCALE
+0x1dac VAP_VPORT_ZOFFSET
+0x1db0 SE_ZBIAS_FACTOR
+0x1db4 SE_ZBIAS_CONSTANT
+0x1db8 SE_LINE_WIDTH
+0x2140 SE_CNTL_STATUS
+0x2200 SE_TCL_VECTOR_INDX_REG
+0x2204 SE_TCL_VECTOR_DATA_REG
+0x2208 SE_TCL_SCALAR_INDX_REG
+0x220c SE_TCL_SCALAR_DATA_REG
+0x2210 SE_TCL_MATERIAL_EMISSIVE_RED
+0x2214 SE_TCL_MATERIAL_EMISSIVE_GREEN
+0x2218 SE_TCL_MATERIAL_EMISSIVE_BLUE
+0x221c SE_TCL_MATERIAL_EMISSIVE_ALPHA
+0x2220 SE_TCL_MATERIAL_AMBIENT_RED
+0x2224 SE_TCL_MATERIAL_AMBIENT_GREEN
+0x2228 SE_TCL_MATERIAL_AMBIENT_BLUE
+0x222c SE_TCL_MATERIAL_AMBIENT_ALPHA
+0x2230 SE_TCL_MATERIAL_DIFFUSE_RED
+0x2234 SE_TCL_MATERIAL_DIFFUSE_GREEN
+0x2238 SE_TCL_MATERIAL_DIFFUSE_BLUE
+0x223c SE_TCL_MATERIAL_DIFFUSE_ALPHA
+0x2240 SE_TCL_MATERIAL_SPECULAR_RED
+0x2244 SE_TCL_MATERIAL_SPECULAR_GREEN
+0x2248 SE_TCL_MATERIAL_SPECULAR_BLUE
+0x224c SE_TCL_MATERIAL_SPECULAR_ALPHA
+0x2250 SE_TCL_SHININESS
+0x2254 SE_TCL_OUTPUT_VTX_FMT
+0x2258 SE_TCL_OUTPUT_VTX_SEL
+0x225c SE_TCL_MATRIX_SELECT_0
+0x2260 SE_TCL_MATRIX_SELECT_1
+0x2264 SE_TCL_UCP_VERT_BLEND_CNTL
+0x2268 SE_TCL_TEXTURE_PROC_CTL
+0x226c SE_TCL_LIGHT_MODEL_CTL
+0x2270 SE_TCL_PER_LIGHT_CTL_0
+0x2274 SE_TCL_PER_LIGHT_CTL_1
+0x2278 SE_TCL_PER_LIGHT_CTL_2
+0x227c SE_TCL_PER_LIGHT_CTL_3
+0x2284 SE_TCL_STATE_FLUSH
+0x26c0 RE_TOP_LEFT
+0x26c4 RE_MISC
+0x3290 RB3D_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r200 b/drivers/gpu/drm/radeon/reg_srcs/r200
new file mode 100644
index 0000000..6021c88
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r200
@@ -0,0 +1,184 @@
+r200 0x3294
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
+0x1c14 PP_MISC
+0x1c18 PP_FOG_COLOR
+0x1c1c RE_SOLID_COLOR
+0x1c20 RB3D_BLENDCNTL
+0x1c4c SE_CNTL
+0x1c50 RE_CNTL
+0x1cc8 RE_STIPPLE_ADDR
+0x1ccc RE_STIPPLE_DATA
+0x1cd0 RE_LINE_PATTERN
+0x1cd4 RE_LINE_STATE
+0x1cd8 RE_SCISSOR_TL_0
+0x1cdc RE_SCISSOR_BR_0
+0x1ce0 RE_SCISSOR_TL_1
+0x1ce4 RE_SCISSOR_BR_1
+0x1ce8 RE_SCISSOR_TL_2
+0x1cec RE_SCISSOR_BR_2
+0x1d60 RB3D_DEPTHXY_OFFSET
+0x1d7c RB3D_STENCILREFMASK
+0x1d80 RB3D_ROPCNTL
+0x1d84 RB3D_PLANEMASK
+0x1d98 VAP_VPORT_XSCALE
+0x1d9c VAP_VPORT_XOFFSET
+0x1da0 VAP_VPORT_YSCALE
+0x1da4 VAP_VPORT_YOFFSET
+0x1da8 VAP_VPORT_ZSCALE
+0x1dac VAP_VPORT_ZOFFSET
+0x1db0 SE_ZBIAS_FACTOR
+0x1db4 SE_ZBIAS_CONSTANT
+0x1db8 SE_LINE_WIDTH
+0x2080 SE_VAP_CNTL
+0x2090 SE_TCL_OUTPUT_VTX_FMT_0
+0x2094 SE_TCL_OUTPUT_VTX_FMT_1
+0x20b0 SE_VTE_CNTL
+0x2140 SE_CNTL_STATUS
+0x2180 SE_VTX_STATE_CNTL
+0x2200 SE_TCL_VECTOR_INDX_REG
+0x2204 SE_TCL_VECTOR_DATA_REG
+0x2208 SE_TCL_SCALAR_INDX_REG
+0x220c SE_TCL_SCALAR_DATA_REG
+0x2230 SE_TCL_MATRIX_SEL_0
+0x2234 SE_TCL_MATRIX_SEL_1
+0x2238 SE_TCL_MATRIX_SEL_2
+0x223c SE_TCL_MATRIX_SEL_3
+0x2240 SE_TCL_MATRIX_SEL_4
+0x2250 SE_TCL_OUTPUT_VTX_COMP_SEL
+0x2254 SE_TCL_INPUT_VTX_VECTOR_ADDR_0
+0x2258 SE_TCL_INPUT_VTX_VECTOR_ADDR_1
+0x225c SE_TCL_INPUT_VTX_VECTOR_ADDR_2
+0x2260 SE_TCL_INPUT_VTX_VECTOR_ADDR_3
+0x2268 SE_TCL_LIGHT_MODEL_CTL_0
+0x226c SE_TCL_LIGHT_MODEL_CTL_1
+0x2270 SE_TCL_PER_LIGHT_CTL_0
+0x2274 SE_TCL_PER_LIGHT_CTL_1
+0x2278 SE_TCL_PER_LIGHT_CTL_2
+0x227c SE_TCL_PER_LIGHT_CTL_3
+0x2284 VAP_PVS_STATE_FLUSH_REG
+0x22a8 SE_TCL_TEX_PROC_CTL_2
+0x22ac SE_TCL_TEX_PROC_CTL_3
+0x22b0 SE_TCL_TEX_PROC_CTL_0
+0x22b4 SE_TCL_TEX_PROC_CTL_1
+0x22b8 SE_TCL_TEX_CYL_WRAP_CTL
+0x22c0 SE_TCL_UCP_VERT_BLEND_CNTL
+0x22c4 SE_TCL_POINT_SPRITE_CNTL
+0x2648 RE_POINTSIZE
+0x26c0 RE_TOP_LEFT
+0x26c4 RE_MISC
+0x26f0 RE_AUX_SCISSOR_CNTL
+0x2c14 PP_BORDER_COLOR_0
+0x2c34 PP_BORDER_COLOR_1
+0x2c54 PP_BORDER_COLOR_2
+0x2c74 PP_BORDER_COLOR_3
+0x2c94 PP_BORDER_COLOR_4
+0x2cb4 PP_BORDER_COLOR_5
+0x2cc4 PP_CNTL_X
+0x2cf8 PP_TRI_PERF
+0x2cfc PP_PERF_CNTL
+0x2d9c PP_TAM_DEBUG3
+0x2ee0 PP_TFACTOR_0
+0x2ee4 PP_TFACTOR_1
+0x2ee8 PP_TFACTOR_2
+0x2eec PP_TFACTOR_3
+0x2ef0 PP_TFACTOR_4
+0x2ef4 PP_TFACTOR_5
+0x2ef8 PP_TFACTOR_6
+0x2efc PP_TFACTOR_7
+0x2f00 PP_TXCBLEND_0
+0x2f04 PP_TXCBLEND2_0
+0x2f08 PP_TXABLEND_0
+0x2f0c PP_TXABLEND2_0
+0x2f10 PP_TXCBLEND_1
+0x2f14 PP_TXCBLEND2_1
+0x2f18 PP_TXABLEND_1
+0x2f1c PP_TXABLEND2_1
+0x2f20 PP_TXCBLEND_2
+0x2f24 PP_TXCBLEND2_2
+0x2f28 PP_TXABLEND_2
+0x2f2c PP_TXABLEND2_2
+0x2f30 PP_TXCBLEND_3
+0x2f34 PP_TXCBLEND2_3
+0x2f38 PP_TXABLEND_3
+0x2f3c PP_TXABLEND2_3
+0x2f40 PP_TXCBLEND_4
+0x2f44 PP_TXCBLEND2_4
+0x2f48 PP_TXABLEND_4
+0x2f4c PP_TXABLEND2_4
+0x2f50 PP_TXCBLEND_5
+0x2f54 PP_TXCBLEND2_5
+0x2f58 PP_TXABLEND_5
+0x2f5c PP_TXABLEND2_5
+0x2f60 PP_TXCBLEND_6
+0x2f64 PP_TXCBLEND2_6
+0x2f68 PP_TXABLEND_6
+0x2f6c PP_TXABLEND2_6
+0x2f70 PP_TXCBLEND_7
+0x2f74 PP_TXCBLEND2_7
+0x2f78 PP_TXABLEND_7
+0x2f7c PP_TXABLEND2_7
+0x2f80 PP_TXCBLEND_8
+0x2f84 PP_TXCBLEND2_8
+0x2f88 PP_TXABLEND_8
+0x2f8c PP_TXABLEND2_8
+0x2f90 PP_TXCBLEND_9
+0x2f94 PP_TXCBLEND2_9
+0x2f98 PP_TXABLEND_9
+0x2f9c PP_TXABLEND2_9
+0x2fa0 PP_TXCBLEND_10
+0x2fa4 PP_TXCBLEND2_10
+0x2fa8 PP_TXABLEND_10
+0x2fac PP_TXABLEND2_10
+0x2fb0 PP_TXCBLEND_11
+0x2fb4 PP_TXCBLEND2_11
+0x2fb8 PP_TXABLEND_11
+0x2fbc PP_TXABLEND2_11
+0x2fc0 PP_TXCBLEND_12
+0x2fc4 PP_TXCBLEND2_12
+0x2fc8 PP_TXABLEND_12
+0x2fcc PP_TXABLEND2_12
+0x2fd0 PP_TXCBLEND_13
+0x2fd4 PP_TXCBLEND2_13
+0x2fd8 PP_TXABLEND_13
+0x2fdc PP_TXABLEND2_13
+0x2fe0 PP_TXCBLEND_14
+0x2fe4 PP_TXCBLEND2_14
+0x2fe8 PP_TXABLEND_14
+0x2fec PP_TXABLEND2_14
+0x2ff0 PP_TXCBLEND_15
+0x2ff4 PP_TXCBLEND2_15
+0x2ff8 PP_TXABLEND_15
+0x2ffc PP_TXABLEND2_15
+0x3218 RB3D_BLENCOLOR
+0x321c RB3D_ABLENDCNTL
+0x3220 RB3D_CBLENDCNTL
+0x3290 RB3D_ZPASS_DATA
+
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300
new file mode 100644
index 0000000..19c4663
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r300
@@ -0,0 +1,729 @@
+r300 0x4f60
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
+0x1D98 VAP_VPORT_XSCALE
+0x1D9C VAP_VPORT_XOFFSET
+0x1DA0 VAP_VPORT_YSCALE
+0x1DA4 VAP_VPORT_YOFFSET
+0x1DA8 VAP_VPORT_ZSCALE
+0x1DAC VAP_VPORT_ZOFFSET
+0x2080 VAP_CNTL
+0x2090 VAP_OUT_VTX_FMT_0
+0x2094 VAP_OUT_VTX_FMT_1
+0x20B0 VAP_VTE_CNTL
+0x2138 VAP_VF_MIN_VTX_INDX
+0x2140 VAP_CNTL_STATUS
+0x2150 VAP_PROG_STREAM_CNTL_0
+0x2154 VAP_PROG_STREAM_CNTL_1
+0x2158 VAP_PROG_STREAM_CNTL_2
+0x215C VAP_PROG_STREAM_CNTL_3
+0x2160 VAP_PROG_STREAM_CNTL_4
+0x2164 VAP_PROG_STREAM_CNTL_5
+0x2168 VAP_PROG_STREAM_CNTL_6
+0x216C VAP_PROG_STREAM_CNTL_7
+0x2180 VAP_VTX_STATE_CNTL
+0x2184 VAP_VSM_VTX_ASSM
+0x2188 VAP_VTX_STATE_IND_REG_0
+0x218C VAP_VTX_STATE_IND_REG_1
+0x2190 VAP_VTX_STATE_IND_REG_2
+0x2194 VAP_VTX_STATE_IND_REG_3
+0x2198 VAP_VTX_STATE_IND_REG_4
+0x219C VAP_VTX_STATE_IND_REG_5
+0x21A0 VAP_VTX_STATE_IND_REG_6
+0x21A4 VAP_VTX_STATE_IND_REG_7
+0x21A8 VAP_VTX_STATE_IND_REG_8
+0x21AC VAP_VTX_STATE_IND_REG_9
+0x21B0 VAP_VTX_STATE_IND_REG_10
+0x21B4 VAP_VTX_STATE_IND_REG_11
+0x21B8 VAP_VTX_STATE_IND_REG_12
+0x21BC VAP_VTX_STATE_IND_REG_13
+0x21C0 VAP_VTX_STATE_IND_REG_14
+0x21C4 VAP_VTX_STATE_IND_REG_15
+0x21DC VAP_PSC_SGN_NORM_CNTL
+0x21E0 VAP_PROG_STREAM_CNTL_EXT_0
+0x21E4 VAP_PROG_STREAM_CNTL_EXT_1
+0x21E8 VAP_PROG_STREAM_CNTL_EXT_2
+0x21EC VAP_PROG_STREAM_CNTL_EXT_3
+0x21F0 VAP_PROG_STREAM_CNTL_EXT_4
+0x21F4 VAP_PROG_STREAM_CNTL_EXT_5
+0x21F8 VAP_PROG_STREAM_CNTL_EXT_6
+0x21FC VAP_PROG_STREAM_CNTL_EXT_7
+0x2200 VAP_PVS_VECTOR_INDX_REG
+0x2204 VAP_PVS_VECTOR_DATA_REG
+0x2208 VAP_PVS_VECTOR_DATA_REG_128
+0x221C VAP_CLIP_CNTL
+0x2220 VAP_GB_VERT_CLIP_ADJ
+0x2224 VAP_GB_VERT_DISC_ADJ
+0x2228 VAP_GB_HORZ_CLIP_ADJ
+0x222C VAP_GB_HORZ_DISC_ADJ
+0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0
+0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1
+0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2
+0x223C VAP_PVS_FLOW_CNTL_ADDRS_3
+0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4
+0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5
+0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6
+0x224C VAP_PVS_FLOW_CNTL_ADDRS_7
+0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8
+0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9
+0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10
+0x225C VAP_PVS_FLOW_CNTL_ADDRS_11
+0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12
+0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13
+0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14
+0x226C VAP_PVS_FLOW_CNTL_ADDRS_15
+0x2284 VAP_PVS_STATE_FLUSH_REG
+0x2288 VAP_PVS_VTX_TIMEOUT_REG
+0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
+0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1
+0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2
+0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3
+0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4
+0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5
+0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6
+0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7
+0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8
+0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9
+0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10
+0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11
+0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12
+0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13
+0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14
+0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15
+0x22D0 VAP_PVS_CODE_CNTL_0
+0x22D4 VAP_PVS_CONST_CNTL
+0x22D8 VAP_PVS_CODE_CNTL_1
+0x22DC VAP_PVS_FLOW_CNTL_OPC
+0x342C RB2D_DSTCACHE_CTLSTAT
+0x4000 GB_VAP_RASTER_VTX_FMT_0
+0x4004 GB_VAP_RASTER_VTX_FMT_1
+0x4008 GB_ENABLE
+0x401C GB_SELECT
+0x4020 GB_AA_CONFIG
+0x4024 GB_FIFO_SIZE
+0x4100 TX_INVALTAGS
+0x4200 GA_POINT_S0
+0x4204 GA_POINT_T0
+0x4208 GA_POINT_S1
+0x420C GA_POINT_T1
+0x4214 GA_TRIANGLE_STIPPLE
+0x421C GA_POINT_SIZE
+0x4230 GA_POINT_MINMAX
+0x4234 GA_LINE_CNTL
+0x4238 GA_LINE_STIPPLE_CONFIG
+0x4260 GA_LINE_STIPPLE_VALUE
+0x4264 GA_LINE_S0
+0x4268 GA_LINE_S1
+0x4278 GA_COLOR_CONTROL
+0x427C GA_SOLID_RG
+0x4280 GA_SOLID_BA
+0x4288 GA_POLY_MODE
+0x428C GA_ROUND_MODE
+0x4290 GA_OFFSET
+0x4294 GA_FOG_SCALE
+0x4298 GA_FOG_OFFSET
+0x42A0 SU_TEX_WRAP
+0x42A4 SU_POLY_OFFSET_FRONT_SCALE
+0x42A8 SU_POLY_OFFSET_FRONT_OFFSET
+0x42AC SU_POLY_OFFSET_BACK_SCALE
+0x42B0 SU_POLY_OFFSET_BACK_OFFSET
+0x42B4 SU_POLY_OFFSET_ENABLE
+0x42B8 SU_CULL_MODE
+0x42C0 SU_DEPTH_SCALE
+0x42C4 SU_DEPTH_OFFSET
+0x42C8 SU_REG_DEST
+0x4300 RS_COUNT
+0x4304 RS_INST_COUNT
+0x4310 RS_IP_0
+0x4314 RS_IP_1
+0x4318 RS_IP_2
+0x431C RS_IP_3
+0x4320 RS_IP_4
+0x4324 RS_IP_5
+0x4328 RS_IP_6
+0x432C RS_IP_7
+0x4330 RS_INST_0
+0x4334 RS_INST_1
+0x4338 RS_INST_2
+0x433C RS_INST_3
+0x4340 RS_INST_4
+0x4344 RS_INST_5
+0x4348 RS_INST_6
+0x434C RS_INST_7
+0x4350 RS_INST_8
+0x4354 RS_INST_9
+0x4358 RS_INST_10
+0x435C RS_INST_11
+0x4360 RS_INST_12
+0x4364 RS_INST_13
+0x4368 RS_INST_14
+0x436C RS_INST_15
+0x43A4 SC_HYPERZ_EN
+0x43A8 SC_EDGERULE
+0x43B0 SC_CLIP_0_A
+0x43B4 SC_CLIP_0_B
+0x43B8 SC_CLIP_1_A
+0x43BC SC_CLIP_1_B
+0x43C0 SC_CLIP_2_A
+0x43C4 SC_CLIP_2_B
+0x43C8 SC_CLIP_3_A
+0x43CC SC_CLIP_3_B
+0x43D0 SC_CLIP_RULE
+0x43E0 SC_SCISSOR0
+0x43E8 SC_SCREENDOOR
+0x4440 TX_FILTER1_0
+0x4444 TX_FILTER1_1
+0x4448 TX_FILTER1_2
+0x444C TX_FILTER1_3
+0x4450 TX_FILTER1_4
+0x4454 TX_FILTER1_5
+0x4458 TX_FILTER1_6
+0x445C TX_FILTER1_7
+0x4460 TX_FILTER1_8
+0x4464 TX_FILTER1_9
+0x4468 TX_FILTER1_10
+0x446C TX_FILTER1_11
+0x4470 TX_FILTER1_12
+0x4474 TX_FILTER1_13
+0x4478 TX_FILTER1_14
+0x447C TX_FILTER1_15
+0x4580 TX_CHROMA_KEY_0
+0x4584 TX_CHROMA_KEY_1
+0x4588 TX_CHROMA_KEY_2
+0x458C TX_CHROMA_KEY_3
+0x4590 TX_CHROMA_KEY_4
+0x4594 TX_CHROMA_KEY_5
+0x4598 TX_CHROMA_KEY_6
+0x459C TX_CHROMA_KEY_7
+0x45A0 TX_CHROMA_KEY_8
+0x45A4 TX_CHROMA_KEY_9
+0x45A8 TX_CHROMA_KEY_10
+0x45AC TX_CHROMA_KEY_11
+0x45B0 TX_CHROMA_KEY_12
+0x45B4 TX_CHROMA_KEY_13
+0x45B8 TX_CHROMA_KEY_14
+0x45BC TX_CHROMA_KEY_15
+0x45C0 TX_BORDER_COLOR_0
+0x45C4 TX_BORDER_COLOR_1
+0x45C8 TX_BORDER_COLOR_2
+0x45CC TX_BORDER_COLOR_3
+0x45D0 TX_BORDER_COLOR_4
+0x45D4 TX_BORDER_COLOR_5
+0x45D8 TX_BORDER_COLOR_6
+0x45DC TX_BORDER_COLOR_7
+0x45E0 TX_BORDER_COLOR_8
+0x45E4 TX_BORDER_COLOR_9
+0x45E8 TX_BORDER_COLOR_10
+0x45EC TX_BORDER_COLOR_11
+0x45F0 TX_BORDER_COLOR_12
+0x45F4 TX_BORDER_COLOR_13
+0x45F8 TX_BORDER_COLOR_14
+0x45FC TX_BORDER_COLOR_15
+0x4600 US_CONFIG
+0x4604 US_PIXSIZE
+0x4608 US_CODE_OFFSET
+0x460C US_RESET
+0x4610 US_CODE_ADDR_0
+0x4614 US_CODE_ADDR_1
+0x4618 US_CODE_ADDR_2
+0x461C US_CODE_ADDR_3
+0x4620 US_TEX_INST_0
+0x4624 US_TEX_INST_1
+0x4628 US_TEX_INST_2
+0x462C US_TEX_INST_3
+0x4630 US_TEX_INST_4
+0x4634 US_TEX_INST_5
+0x4638 US_TEX_INST_6
+0x463C US_TEX_INST_7
+0x4640 US_TEX_INST_8
+0x4644 US_TEX_INST_9
+0x4648 US_TEX_INST_10
+0x464C US_TEX_INST_11
+0x4650 US_TEX_INST_12
+0x4654 US_TEX_INST_13
+0x4658 US_TEX_INST_14
+0x465C US_TEX_INST_15
+0x4660 US_TEX_INST_16
+0x4664 US_TEX_INST_17
+0x4668 US_TEX_INST_18
+0x466C US_TEX_INST_19
+0x4670 US_TEX_INST_20
+0x4674 US_TEX_INST_21
+0x4678 US_TEX_INST_22
+0x467C US_TEX_INST_23
+0x4680 US_TEX_INST_24
+0x4684 US_TEX_INST_25
+0x4688 US_TEX_INST_26
+0x468C US_TEX_INST_27
+0x4690 US_TEX_INST_28
+0x4694 US_TEX_INST_29
+0x4698 US_TEX_INST_30
+0x469C US_TEX_INST_31
+0x46A4 US_OUT_FMT_0
+0x46A8 US_OUT_FMT_1
+0x46AC US_OUT_FMT_2
+0x46B0 US_OUT_FMT_3
+0x46B4 US_W_FMT
+0x46C0 US_ALU_RGB_ADDR_0
+0x46C4 US_ALU_RGB_ADDR_1
+0x46C8 US_ALU_RGB_ADDR_2
+0x46CC US_ALU_RGB_ADDR_3
+0x46D0 US_ALU_RGB_ADDR_4
+0x46D4 US_ALU_RGB_ADDR_5
+0x46D8 US_ALU_RGB_ADDR_6
+0x46DC US_ALU_RGB_ADDR_7
+0x46E0 US_ALU_RGB_ADDR_8
+0x46E4 US_ALU_RGB_ADDR_9
+0x46E8 US_ALU_RGB_ADDR_10
+0x46EC US_ALU_RGB_ADDR_11
+0x46F0 US_ALU_RGB_ADDR_12
+0x46F4 US_ALU_RGB_ADDR_13
+0x46F8 US_ALU_RGB_ADDR_14
+0x46FC US_ALU_RGB_ADDR_15
+0x4700 US_ALU_RGB_ADDR_16
+0x4704 US_ALU_RGB_ADDR_17
+0x4708 US_ALU_RGB_ADDR_18
+0x470C US_ALU_RGB_ADDR_19
+0x4710 US_ALU_RGB_ADDR_20
+0x4714 US_ALU_RGB_ADDR_21
+0x4718 US_ALU_RGB_ADDR_22
+0x471C US_ALU_RGB_ADDR_23
+0x4720 US_ALU_RGB_ADDR_24
+0x4724 US_ALU_RGB_ADDR_25
+0x4728 US_ALU_RGB_ADDR_26
+0x472C US_ALU_RGB_ADDR_27
+0x4730 US_ALU_RGB_ADDR_28
+0x4734 US_ALU_RGB_ADDR_29
+0x4738 US_ALU_RGB_ADDR_30
+0x473C US_ALU_RGB_ADDR_31
+0x4740 US_ALU_RGB_ADDR_32
+0x4744 US_ALU_RGB_ADDR_33
+0x4748 US_ALU_RGB_ADDR_34
+0x474C US_ALU_RGB_ADDR_35
+0x4750 US_ALU_RGB_ADDR_36
+0x4754 US_ALU_RGB_ADDR_37
+0x4758 US_ALU_RGB_ADDR_38
+0x475C US_ALU_RGB_ADDR_39
+0x4760 US_ALU_RGB_ADDR_40
+0x4764 US_ALU_RGB_ADDR_41
+0x4768 US_ALU_RGB_ADDR_42
+0x476C US_ALU_RGB_ADDR_43
+0x4770 US_ALU_RGB_ADDR_44
+0x4774 US_ALU_RGB_ADDR_45
+0x4778 US_ALU_RGB_ADDR_46
+0x477C US_ALU_RGB_ADDR_47
+0x4780 US_ALU_RGB_ADDR_48
+0x4784 US_ALU_RGB_ADDR_49
+0x4788 US_ALU_RGB_ADDR_50
+0x478C US_ALU_RGB_ADDR_51
+0x4790 US_ALU_RGB_ADDR_52
+0x4794 US_ALU_RGB_ADDR_53
+0x4798 US_ALU_RGB_ADDR_54
+0x479C US_ALU_RGB_ADDR_55
+0x47A0 US_ALU_RGB_ADDR_56
+0x47A4 US_ALU_RGB_ADDR_57
+0x47A8 US_ALU_RGB_ADDR_58
+0x47AC US_ALU_RGB_ADDR_59
+0x47B0 US_ALU_RGB_ADDR_60
+0x47B4 US_ALU_RGB_ADDR_61
+0x47B8 US_ALU_RGB_ADDR_62
+0x47BC US_ALU_RGB_ADDR_63
+0x47C0 US_ALU_ALPHA_ADDR_0
+0x47C4 US_ALU_ALPHA_ADDR_1
+0x47C8 US_ALU_ALPHA_ADDR_2
+0x47CC US_ALU_ALPHA_ADDR_3
+0x47D0 US_ALU_ALPHA_ADDR_4
+0x47D4 US_ALU_ALPHA_ADDR_5
+0x47D8 US_ALU_ALPHA_ADDR_6
+0x47DC US_ALU_ALPHA_ADDR_7
+0x47E0 US_ALU_ALPHA_ADDR_8
+0x47E4 US_ALU_ALPHA_ADDR_9
+0x47E8 US_ALU_ALPHA_ADDR_10
+0x47EC US_ALU_ALPHA_ADDR_11
+0x47F0 US_ALU_ALPHA_ADDR_12
+0x47F4 US_ALU_ALPHA_ADDR_13
+0x47F8 US_ALU_ALPHA_ADDR_14
+0x47FC US_ALU_ALPHA_ADDR_15
+0x4800 US_ALU_ALPHA_ADDR_16
+0x4804 US_ALU_ALPHA_ADDR_17
+0x4808 US_ALU_ALPHA_ADDR_18
+0x480C US_ALU_ALPHA_ADDR_19
+0x4810 US_ALU_ALPHA_ADDR_20
+0x4814 US_ALU_ALPHA_ADDR_21
+0x4818 US_ALU_ALPHA_ADDR_22
+0x481C US_ALU_ALPHA_ADDR_23
+0x4820 US_ALU_ALPHA_ADDR_24
+0x4824 US_ALU_ALPHA_ADDR_25
+0x4828 US_ALU_ALPHA_ADDR_26
+0x482C US_ALU_ALPHA_ADDR_27
+0x4830 US_ALU_ALPHA_ADDR_28
+0x4834 US_ALU_ALPHA_ADDR_29
+0x4838 US_ALU_ALPHA_ADDR_30
+0x483C US_ALU_ALPHA_ADDR_31
+0x4840 US_ALU_ALPHA_ADDR_32
+0x4844 US_ALU_ALPHA_ADDR_33
+0x4848 US_ALU_ALPHA_ADDR_34
+0x484C US_ALU_ALPHA_ADDR_35
+0x4850 US_ALU_ALPHA_ADDR_36
+0x4854 US_ALU_ALPHA_ADDR_37
+0x4858 US_ALU_ALPHA_ADDR_38
+0x485C US_ALU_ALPHA_ADDR_39
+0x4860 US_ALU_ALPHA_ADDR_40
+0x4864 US_ALU_ALPHA_ADDR_41
+0x4868 US_ALU_ALPHA_ADDR_42
+0x486C US_ALU_ALPHA_ADDR_43
+0x4870 US_ALU_ALPHA_ADDR_44
+0x4874 US_ALU_ALPHA_ADDR_45
+0x4878 US_ALU_ALPHA_ADDR_46
+0x487C US_ALU_ALPHA_ADDR_47
+0x4880 US_ALU_ALPHA_ADDR_48
+0x4884 US_ALU_ALPHA_ADDR_49
+0x4888 US_ALU_ALPHA_ADDR_50
+0x488C US_ALU_ALPHA_ADDR_51
+0x4890 US_ALU_ALPHA_ADDR_52
+0x4894 US_ALU_ALPHA_ADDR_53
+0x4898 US_ALU_ALPHA_ADDR_54
+0x489C US_ALU_ALPHA_ADDR_55
+0x48A0 US_ALU_ALPHA_ADDR_56
+0x48A4 US_ALU_ALPHA_ADDR_57
+0x48A8 US_ALU_ALPHA_ADDR_58
+0x48AC US_ALU_ALPHA_ADDR_59
+0x48B0 US_ALU_ALPHA_ADDR_60
+0x48B4 US_ALU_ALPHA_ADDR_61
+0x48B8 US_ALU_ALPHA_ADDR_62
+0x48BC US_ALU_ALPHA_ADDR_63
+0x48C0 US_ALU_RGB_INST_0
+0x48C4 US_ALU_RGB_INST_1
+0x48C8 US_ALU_RGB_INST_2
+0x48CC US_ALU_RGB_INST_3
+0x48D0 US_ALU_RGB_INST_4
+0x48D4 US_ALU_RGB_INST_5
+0x48D8 US_ALU_RGB_INST_6
+0x48DC US_ALU_RGB_INST_7
+0x48E0 US_ALU_RGB_INST_8
+0x48E4 US_ALU_RGB_INST_9
+0x48E8 US_ALU_RGB_INST_10
+0x48EC US_ALU_RGB_INST_11
+0x48F0 US_ALU_RGB_INST_12
+0x48F4 US_ALU_RGB_INST_13
+0x48F8 US_ALU_RGB_INST_14
+0x48FC US_ALU_RGB_INST_15
+0x4900 US_ALU_RGB_INST_16
+0x4904 US_ALU_RGB_INST_17
+0x4908 US_ALU_RGB_INST_18
+0x490C US_ALU_RGB_INST_19
+0x4910 US_ALU_RGB_INST_20
+0x4914 US_ALU_RGB_INST_21
+0x4918 US_ALU_RGB_INST_22
+0x491C US_ALU_RGB_INST_23
+0x4920 US_ALU_RGB_INST_24
+0x4924 US_ALU_RGB_INST_25
+0x4928 US_ALU_RGB_INST_26
+0x492C US_ALU_RGB_INST_27
+0x4930 US_ALU_RGB_INST_28
+0x4934 US_ALU_RGB_INST_29
+0x4938 US_ALU_RGB_INST_30
+0x493C US_ALU_RGB_INST_31
+0x4940 US_ALU_RGB_INST_32
+0x4944 US_ALU_RGB_INST_33
+0x4948 US_ALU_RGB_INST_34
+0x494C US_ALU_RGB_INST_35
+0x4950 US_ALU_RGB_INST_36
+0x4954 US_ALU_RGB_INST_37
+0x4958 US_ALU_RGB_INST_38
+0x495C US_ALU_RGB_INST_39
+0x4960 US_ALU_RGB_INST_40
+0x4964 US_ALU_RGB_INST_41
+0x4968 US_ALU_RGB_INST_42
+0x496C US_ALU_RGB_INST_43
+0x4970 US_ALU_RGB_INST_44
+0x4974 US_ALU_RGB_INST_45
+0x4978 US_ALU_RGB_INST_46
+0x497C US_ALU_RGB_INST_47
+0x4980 US_ALU_RGB_INST_48
+0x4984 US_ALU_RGB_INST_49
+0x4988 US_ALU_RGB_INST_50
+0x498C US_ALU_RGB_INST_51
+0x4990 US_ALU_RGB_INST_52
+0x4994 US_ALU_RGB_INST_53
+0x4998 US_ALU_RGB_INST_54
+0x499C US_ALU_RGB_INST_55
+0x49A0 US_ALU_RGB_INST_56
+0x49A4 US_ALU_RGB_INST_57
+0x49A8 US_ALU_RGB_INST_58
+0x49AC US_ALU_RGB_INST_59
+0x49B0 US_ALU_RGB_INST_60
+0x49B4 US_ALU_RGB_INST_61
+0x49B8 US_ALU_RGB_INST_62
+0x49BC US_ALU_RGB_INST_63
+0x49C0 US_ALU_ALPHA_INST_0
+0x49C4 US_ALU_ALPHA_INST_1
+0x49C8 US_ALU_ALPHA_INST_2
+0x49CC US_ALU_ALPHA_INST_3
+0x49D0 US_ALU_ALPHA_INST_4
+0x49D4 US_ALU_ALPHA_INST_5
+0x49D8 US_ALU_ALPHA_INST_6
+0x49DC US_ALU_ALPHA_INST_7
+0x49E0 US_ALU_ALPHA_INST_8
+0x49E4 US_ALU_ALPHA_INST_9
+0x49E8 US_ALU_ALPHA_INST_10
+0x49EC US_ALU_ALPHA_INST_11
+0x49F0 US_ALU_ALPHA_INST_12
+0x49F4 US_ALU_ALPHA_INST_13
+0x49F8 US_ALU_ALPHA_INST_14
+0x49FC US_ALU_ALPHA_INST_15
+0x4A00 US_ALU_ALPHA_INST_16
+0x4A04 US_ALU_ALPHA_INST_17
+0x4A08 US_ALU_ALPHA_INST_18
+0x4A0C US_ALU_ALPHA_INST_19
+0x4A10 US_ALU_ALPHA_INST_20
+0x4A14 US_ALU_ALPHA_INST_21
+0x4A18 US_ALU_ALPHA_INST_22
+0x4A1C US_ALU_ALPHA_INST_23
+0x4A20 US_ALU_ALPHA_INST_24
+0x4A24 US_ALU_ALPHA_INST_25
+0x4A28 US_ALU_ALPHA_INST_26
+0x4A2C US_ALU_ALPHA_INST_27
+0x4A30 US_ALU_ALPHA_INST_28
+0x4A34 US_ALU_ALPHA_INST_29
+0x4A38 US_ALU_ALPHA_INST_30
+0x4A3C US_ALU_ALPHA_INST_31
+0x4A40 US_ALU_ALPHA_INST_32
+0x4A44 US_ALU_ALPHA_INST_33
+0x4A48 US_ALU_ALPHA_INST_34
+0x4A4C US_ALU_ALPHA_INST_35
+0x4A50 US_ALU_ALPHA_INST_36
+0x4A54 US_ALU_ALPHA_INST_37
+0x4A58 US_ALU_ALPHA_INST_38
+0x4A5C US_ALU_ALPHA_INST_39
+0x4A60 US_ALU_ALPHA_INST_40
+0x4A64 US_ALU_ALPHA_INST_41
+0x4A68 US_ALU_ALPHA_INST_42
+0x4A6C US_ALU_ALPHA_INST_43
+0x4A70 US_ALU_ALPHA_INST_44
+0x4A74 US_ALU_ALPHA_INST_45
+0x4A78 US_ALU_ALPHA_INST_46
+0x4A7C US_ALU_ALPHA_INST_47
+0x4A80 US_ALU_ALPHA_INST_48
+0x4A84 US_ALU_ALPHA_INST_49
+0x4A88 US_ALU_ALPHA_INST_50
+0x4A8C US_ALU_ALPHA_INST_51
+0x4A90 US_ALU_ALPHA_INST_52
+0x4A94 US_ALU_ALPHA_INST_53
+0x4A98 US_ALU_ALPHA_INST_54
+0x4A9C US_ALU_ALPHA_INST_55
+0x4AA0 US_ALU_ALPHA_INST_56
+0x4AA4 US_ALU_ALPHA_INST_57
+0x4AA8 US_ALU_ALPHA_INST_58
+0x4AAC US_ALU_ALPHA_INST_59
+0x4AB0 US_ALU_ALPHA_INST_60
+0x4AB4 US_ALU_ALPHA_INST_61
+0x4AB8 US_ALU_ALPHA_INST_62
+0x4ABC US_ALU_ALPHA_INST_63
+0x4BC0 FG_FOG_BLEND
+0x4BC4 FG_FOG_FACTOR
+0x4BC8 FG_FOG_COLOR_R
+0x4BCC FG_FOG_COLOR_G
+0x4BD0 FG_FOG_COLOR_B
+0x4BD4 FG_ALPHA_FUNC
+0x4BD8 FG_DEPTH_SRC
+0x4C00 US_ALU_CONST_R_0
+0x4C04 US_ALU_CONST_G_0
+0x4C08 US_ALU_CONST_B_0
+0x4C0C US_ALU_CONST_A_0
+0x4C10 US_ALU_CONST_R_1
+0x4C14 US_ALU_CONST_G_1
+0x4C18 US_ALU_CONST_B_1
+0x4C1C US_ALU_CONST_A_1
+0x4C20 US_ALU_CONST_R_2
+0x4C24 US_ALU_CONST_G_2
+0x4C28 US_ALU_CONST_B_2
+0x4C2C US_ALU_CONST_A_2
+0x4C30 US_ALU_CONST_R_3
+0x4C34 US_ALU_CONST_G_3
+0x4C38 US_ALU_CONST_B_3
+0x4C3C US_ALU_CONST_A_3
+0x4C40 US_ALU_CONST_R_4
+0x4C44 US_ALU_CONST_G_4
+0x4C48 US_ALU_CONST_B_4
+0x4C4C US_ALU_CONST_A_4
+0x4C50 US_ALU_CONST_R_5
+0x4C54 US_ALU_CONST_G_5
+0x4C58 US_ALU_CONST_B_5
+0x4C5C US_ALU_CONST_A_5
+0x4C60 US_ALU_CONST_R_6
+0x4C64 US_ALU_CONST_G_6
+0x4C68 US_ALU_CONST_B_6
+0x4C6C US_ALU_CONST_A_6
+0x4C70 US_ALU_CONST_R_7
+0x4C74 US_ALU_CONST_G_7
+0x4C78 US_ALU_CONST_B_7
+0x4C7C US_ALU_CONST_A_7
+0x4C80 US_ALU_CONST_R_8
+0x4C84 US_ALU_CONST_G_8
+0x4C88 US_ALU_CONST_B_8
+0x4C8C US_ALU_CONST_A_8
+0x4C90 US_ALU_CONST_R_9
+0x4C94 US_ALU_CONST_G_9
+0x4C98 US_ALU_CONST_B_9
+0x4C9C US_ALU_CONST_A_9
+0x4CA0 US_ALU_CONST_R_10
+0x4CA4 US_ALU_CONST_G_10
+0x4CA8 US_ALU_CONST_B_10
+0x4CAC US_ALU_CONST_A_10
+0x4CB0 US_ALU_CONST_R_11
+0x4CB4 US_ALU_CONST_G_11
+0x4CB8 US_ALU_CONST_B_11
+0x4CBC US_ALU_CONST_A_11
+0x4CC0 US_ALU_CONST_R_12
+0x4CC4 US_ALU_CONST_G_12
+0x4CC8 US_ALU_CONST_B_12
+0x4CCC US_ALU_CONST_A_12
+0x4CD0 US_ALU_CONST_R_13
+0x4CD4 US_ALU_CONST_G_13
+0x4CD8 US_ALU_CONST_B_13
+0x4CDC US_ALU_CONST_A_13
+0x4CE0 US_ALU_CONST_R_14
+0x4CE4 US_ALU_CONST_G_14
+0x4CE8 US_ALU_CONST_B_14
+0x4CEC US_ALU_CONST_A_14
+0x4CF0 US_ALU_CONST_R_15
+0x4CF4 US_ALU_CONST_G_15
+0x4CF8 US_ALU_CONST_B_15
+0x4CFC US_ALU_CONST_A_15
+0x4D00 US_ALU_CONST_R_16
+0x4D04 US_ALU_CONST_G_16
+0x4D08 US_ALU_CONST_B_16
+0x4D0C US_ALU_CONST_A_16
+0x4D10 US_ALU_CONST_R_17
+0x4D14 US_ALU_CONST_G_17
+0x4D18 US_ALU_CONST_B_17
+0x4D1C US_ALU_CONST_A_17
+0x4D20 US_ALU_CONST_R_18
+0x4D24 US_ALU_CONST_G_18
+0x4D28 US_ALU_CONST_B_18
+0x4D2C US_ALU_CONST_A_18
+0x4D30 US_ALU_CONST_R_19
+0x4D34 US_ALU_CONST_G_19
+0x4D38 US_ALU_CONST_B_19
+0x4D3C US_ALU_CONST_A_19
+0x4D40 US_ALU_CONST_R_20
+0x4D44 US_ALU_CONST_G_20
+0x4D48 US_ALU_CONST_B_20
+0x4D4C US_ALU_CONST_A_20
+0x4D50 US_ALU_CONST_R_21
+0x4D54 US_ALU_CONST_G_21
+0x4D58 US_ALU_CONST_B_21
+0x4D5C US_ALU_CONST_A_21
+0x4D60 US_ALU_CONST_R_22
+0x4D64 US_ALU_CONST_G_22
+0x4D68 US_ALU_CONST_B_22
+0x4D6C US_ALU_CONST_A_22
+0x4D70 US_ALU_CONST_R_23
+0x4D74 US_ALU_CONST_G_23
+0x4D78 US_ALU_CONST_B_23
+0x4D7C US_ALU_CONST_A_23
+0x4D80 US_ALU_CONST_R_24
+0x4D84 US_ALU_CONST_G_24
+0x4D88 US_ALU_CONST_B_24
+0x4D8C US_ALU_CONST_A_24
+0x4D90 US_ALU_CONST_R_25
+0x4D94 US_ALU_CONST_G_25
+0x4D98 US_ALU_CONST_B_25
+0x4D9C US_ALU_CONST_A_25
+0x4DA0 US_ALU_CONST_R_26
+0x4DA4 US_ALU_CONST_G_26
+0x4DA8 US_ALU_CONST_B_26
+0x4DAC US_ALU_CONST_A_26
+0x4DB0 US_ALU_CONST_R_27
+0x4DB4 US_ALU_CONST_G_27
+0x4DB8 US_ALU_CONST_B_27
+0x4DBC US_ALU_CONST_A_27
+0x4DC0 US_ALU_CONST_R_28
+0x4DC4 US_ALU_CONST_G_28
+0x4DC8 US_ALU_CONST_B_28
+0x4DCC US_ALU_CONST_A_28
+0x4DD0 US_ALU_CONST_R_29
+0x4DD4 US_ALU_CONST_G_29
+0x4DD8 US_ALU_CONST_B_29
+0x4DDC US_ALU_CONST_A_29
+0x4DE0 US_ALU_CONST_R_30
+0x4DE4 US_ALU_CONST_G_30
+0x4DE8 US_ALU_CONST_B_30
+0x4DEC US_ALU_CONST_A_30
+0x4DF0 US_ALU_CONST_R_31
+0x4DF4 US_ALU_CONST_G_31
+0x4DF8 US_ALU_CONST_B_31
+0x4DFC US_ALU_CONST_A_31
+0x4E04 RB3D_BLENDCNTL_R3
+0x4E08 RB3D_ABLENDCNTL_R3
+0x4E0C RB3D_COLOR_CHANNEL_MASK
+0x4E10 RB3D_CONSTANT_COLOR
+0x4E14 RB3D_COLOR_CLEAR_VALUE
+0x4E18 RB3D_ROPCNTL_R3
+0x4E1C RB3D_CLRCMP_FLIPE_R3
+0x4E20 RB3D_CLRCMP_CLR_R3
+0x4E24 RB3D_CLRCMP_MSK_R3
+0x4E48 RB3D_DEBUG_CTL
+0x4E4C RB3D_DSTCACHE_CTLSTAT_R3
+0x4E50 RB3D_DITHER_CTL
+0x4E54 RB3D_CMASK_OFFSET0
+0x4E58 RB3D_CMASK_OFFSET1
+0x4E5C RB3D_CMASK_OFFSET2
+0x4E60 RB3D_CMASK_OFFSET3
+0x4E64 RB3D_CMASK_PITCH0
+0x4E68 RB3D_CMASK_PITCH1
+0x4E6C RB3D_CMASK_PITCH2
+0x4E70 RB3D_CMASK_PITCH3
+0x4E74 RB3D_CMASK_WRINDEX
+0x4E78 RB3D_CMASK_DWORD
+0x4E7C RB3D_CMASK_RDINDEX
+0x4E80 RB3D_AARESOLVE_OFFSET
+0x4E84 RB3D_AARESOLVE_PITCH
+0x4E88 RB3D_AARESOLVE_CTL
+0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
+0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
+0x4F04 ZB_ZSTENCILCNTL
+0x4F08 ZB_STENCILREFMASK
+0x4F14 ZB_ZTOP
+0x4F18 ZB_ZCACHE_CTLSTAT
+0x4F1C ZB_BW_CNTL
+0x4F28 ZB_DEPTHCLEARVALUE
+0x4F30 ZB_ZMASK_OFFSET
+0x4F34 ZB_ZMASK_PITCH
+0x4F38 ZB_ZMASK_WRINDEX
+0x4F3C ZB_ZMASK_DWORD
+0x4F40 ZB_ZMASK_RDINDEX
+0x4F44 ZB_HIZ_OFFSET
+0x4F48 ZB_HIZ_WRINDEX
+0x4F4C ZB_HIZ_DWORD
+0x4F50 ZB_HIZ_RDINDEX
+0x4F54 ZB_HIZ_PITCH
+0x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rn50 b/drivers/gpu/drm/radeon/reg_srcs/rn50
new file mode 100644
index 0000000..2687b63
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/rn50
@@ -0,0 +1,30 @@
+rn50 0x3294
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600
new file mode 100644
index 0000000..8e3c0b8
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/rs600
@@ -0,0 +1,729 @@
+rs600 0x6d40
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
+0x1D98 VAP_VPORT_XSCALE
+0x1D9C VAP_VPORT_XOFFSET
+0x1DA0 VAP_VPORT_YSCALE
+0x1DA4 VAP_VPORT_YOFFSET
+0x1DA8 VAP_VPORT_ZSCALE
+0x1DAC VAP_VPORT_ZOFFSET
+0x2080 VAP_CNTL
+0x2090 VAP_OUT_VTX_FMT_0
+0x2094 VAP_OUT_VTX_FMT_1
+0x20B0 VAP_VTE_CNTL
+0x2138 VAP_VF_MIN_VTX_INDX
+0x2140 VAP_CNTL_STATUS
+0x2150 VAP_PROG_STREAM_CNTL_0
+0x2154 VAP_PROG_STREAM_CNTL_1
+0x2158 VAP_PROG_STREAM_CNTL_2
+0x215C VAP_PROG_STREAM_CNTL_3
+0x2160 VAP_PROG_STREAM_CNTL_4
+0x2164 VAP_PROG_STREAM_CNTL_5
+0x2168 VAP_PROG_STREAM_CNTL_6
+0x216C VAP_PROG_STREAM_CNTL_7
+0x2180 VAP_VTX_STATE_CNTL
+0x2184 VAP_VSM_VTX_ASSM
+0x2188 VAP_VTX_STATE_IND_REG_0
+0x218C VAP_VTX_STATE_IND_REG_1
+0x2190 VAP_VTX_STATE_IND_REG_2
+0x2194 VAP_VTX_STATE_IND_REG_3
+0x2198 VAP_VTX_STATE_IND_REG_4
+0x219C VAP_VTX_STATE_IND_REG_5
+0x21A0 VAP_VTX_STATE_IND_REG_6
+0x21A4 VAP_VTX_STATE_IND_REG_7
+0x21A8 VAP_VTX_STATE_IND_REG_8
+0x21AC VAP_VTX_STATE_IND_REG_9
+0x21B0 VAP_VTX_STATE_IND_REG_10
+0x21B4 VAP_VTX_STATE_IND_REG_11
+0x21B8 VAP_VTX_STATE_IND_REG_12
+0x21BC VAP_VTX_STATE_IND_REG_13
+0x21C0 VAP_VTX_STATE_IND_REG_14
+0x21C4 VAP_VTX_STATE_IND_REG_15
+0x21DC VAP_PSC_SGN_NORM_CNTL
+0x21E0 VAP_PROG_STREAM_CNTL_EXT_0
+0x21E4 VAP_PROG_STREAM_CNTL_EXT_1
+0x21E8 VAP_PROG_STREAM_CNTL_EXT_2
+0x21EC VAP_PROG_STREAM_CNTL_EXT_3
+0x21F0 VAP_PROG_STREAM_CNTL_EXT_4
+0x21F4 VAP_PROG_STREAM_CNTL_EXT_5
+0x21F8 VAP_PROG_STREAM_CNTL_EXT_6
+0x21FC VAP_PROG_STREAM_CNTL_EXT_7
+0x2200 VAP_PVS_VECTOR_INDX_REG
+0x2204 VAP_PVS_VECTOR_DATA_REG
+0x2208 VAP_PVS_VECTOR_DATA_REG_128
+0x221C VAP_CLIP_CNTL
+0x2220 VAP_GB_VERT_CLIP_ADJ
+0x2224 VAP_GB_VERT_DISC_ADJ
+0x2228 VAP_GB_HORZ_CLIP_ADJ
+0x222C VAP_GB_HORZ_DISC_ADJ
+0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0
+0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1
+0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2
+0x223C VAP_PVS_FLOW_CNTL_ADDRS_3
+0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4
+0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5
+0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6
+0x224C VAP_PVS_FLOW_CNTL_ADDRS_7
+0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8
+0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9
+0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10
+0x225C VAP_PVS_FLOW_CNTL_ADDRS_11
+0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12
+0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13
+0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14
+0x226C VAP_PVS_FLOW_CNTL_ADDRS_15
+0x2284 VAP_PVS_STATE_FLUSH_REG
+0x2288 VAP_PVS_VTX_TIMEOUT_REG
+0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
+0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1
+0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2
+0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3
+0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4
+0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5
+0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6
+0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7
+0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8
+0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9
+0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10
+0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11
+0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12
+0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13
+0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14
+0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15
+0x22D0 VAP_PVS_CODE_CNTL_0
+0x22D4 VAP_PVS_CONST_CNTL
+0x22D8 VAP_PVS_CODE_CNTL_1
+0x22DC VAP_PVS_FLOW_CNTL_OPC
+0x342C RB2D_DSTCACHE_CTLSTAT
+0x4000 GB_VAP_RASTER_VTX_FMT_0
+0x4004 GB_VAP_RASTER_VTX_FMT_1
+0x4008 GB_ENABLE
+0x401C GB_SELECT
+0x4020 GB_AA_CONFIG
+0x4024 GB_FIFO_SIZE
+0x4100 TX_INVALTAGS
+0x4200 GA_POINT_S0
+0x4204 GA_POINT_T0
+0x4208 GA_POINT_S1
+0x420C GA_POINT_T1
+0x4214 GA_TRIANGLE_STIPPLE
+0x421C GA_POINT_SIZE
+0x4230 GA_POINT_MINMAX
+0x4234 GA_LINE_CNTL
+0x4238 GA_LINE_STIPPLE_CONFIG
+0x4260 GA_LINE_STIPPLE_VALUE
+0x4264 GA_LINE_S0
+0x4268 GA_LINE_S1
+0x4278 GA_COLOR_CONTROL
+0x427C GA_SOLID_RG
+0x4280 GA_SOLID_BA
+0x4288 GA_POLY_MODE
+0x428C GA_ROUND_MODE
+0x4290 GA_OFFSET
+0x4294 GA_FOG_SCALE
+0x4298 GA_FOG_OFFSET
+0x42A0 SU_TEX_WRAP
+0x42A4 SU_POLY_OFFSET_FRONT_SCALE
+0x42A8 SU_POLY_OFFSET_FRONT_OFFSET
+0x42AC SU_POLY_OFFSET_BACK_SCALE
+0x42B0 SU_POLY_OFFSET_BACK_OFFSET
+0x42B4 SU_POLY_OFFSET_ENABLE
+0x42B8 SU_CULL_MODE
+0x42C0 SU_DEPTH_SCALE
+0x42C4 SU_DEPTH_OFFSET
+0x42C8 SU_REG_DEST
+0x4300 RS_COUNT
+0x4304 RS_INST_COUNT
+0x4310 RS_IP_0
+0x4314 RS_IP_1
+0x4318 RS_IP_2
+0x431C RS_IP_3
+0x4320 RS_IP_4
+0x4324 RS_IP_5
+0x4328 RS_IP_6
+0x432C RS_IP_7
+0x4330 RS_INST_0
+0x4334 RS_INST_1
+0x4338 RS_INST_2
+0x433C RS_INST_3
+0x4340 RS_INST_4
+0x4344 RS_INST_5
+0x4348 RS_INST_6
+0x434C RS_INST_7
+0x4350 RS_INST_8
+0x4354 RS_INST_9
+0x4358 RS_INST_10
+0x435C RS_INST_11
+0x4360 RS_INST_12
+0x4364 RS_INST_13
+0x4368 RS_INST_14
+0x436C RS_INST_15
+0x43A4 SC_HYPERZ_EN
+0x43A8 SC_EDGERULE
+0x43B0 SC_CLIP_0_A
+0x43B4 SC_CLIP_0_B
+0x43B8 SC_CLIP_1_A
+0x43BC SC_CLIP_1_B
+0x43C0 SC_CLIP_2_A
+0x43C4 SC_CLIP_2_B
+0x43C8 SC_CLIP_3_A
+0x43CC SC_CLIP_3_B
+0x43D0 SC_CLIP_RULE
+0x43E0 SC_SCISSOR0
+0x43E8 SC_SCREENDOOR
+0x4440 TX_FILTER1_0
+0x4444 TX_FILTER1_1
+0x4448 TX_FILTER1_2
+0x444C TX_FILTER1_3
+0x4450 TX_FILTER1_4
+0x4454 TX_FILTER1_5
+0x4458 TX_FILTER1_6
+0x445C TX_FILTER1_7
+0x4460 TX_FILTER1_8
+0x4464 TX_FILTER1_9
+0x4468 TX_FILTER1_10
+0x446C TX_FILTER1_11
+0x4470 TX_FILTER1_12
+0x4474 TX_FILTER1_13
+0x4478 TX_FILTER1_14
+0x447C TX_FILTER1_15
+0x4580 TX_CHROMA_KEY_0
+0x4584 TX_CHROMA_KEY_1
+0x4588 TX_CHROMA_KEY_2
+0x458C TX_CHROMA_KEY_3
+0x4590 TX_CHROMA_KEY_4
+0x4594 TX_CHROMA_KEY_5
+0x4598 TX_CHROMA_KEY_6
+0x459C TX_CHROMA_KEY_7
+0x45A0 TX_CHROMA_KEY_8
+0x45A4 TX_CHROMA_KEY_9
+0x45A8 TX_CHROMA_KEY_10
+0x45AC TX_CHROMA_KEY_11
+0x45B0 TX_CHROMA_KEY_12
+0x45B4 TX_CHROMA_KEY_13
+0x45B8 TX_CHROMA_KEY_14
+0x45BC TX_CHROMA_KEY_15
+0x45C0 TX_BORDER_COLOR_0
+0x45C4 TX_BORDER_COLOR_1
+0x45C8 TX_BORDER_COLOR_2
+0x45CC TX_BORDER_COLOR_3
+0x45D0 TX_BORDER_COLOR_4
+0x45D4 TX_BORDER_COLOR_5
+0x45D8 TX_BORDER_COLOR_6
+0x45DC TX_BORDER_COLOR_7
+0x45E0 TX_BORDER_COLOR_8
+0x45E4 TX_BORDER_COLOR_9
+0x45E8 TX_BORDER_COLOR_10
+0x45EC TX_BORDER_COLOR_11
+0x45F0 TX_BORDER_COLOR_12
+0x45F4 TX_BORDER_COLOR_13
+0x45F8 TX_BORDER_COLOR_14
+0x45FC TX_BORDER_COLOR_15
+0x4600 US_CONFIG
+0x4604 US_PIXSIZE
+0x4608 US_CODE_OFFSET
+0x460C US_RESET
+0x4610 US_CODE_ADDR_0
+0x4614 US_CODE_ADDR_1
+0x4618 US_CODE_ADDR_2
+0x461C US_CODE_ADDR_3
+0x4620 US_TEX_INST_0
+0x4624 US_TEX_INST_1
+0x4628 US_TEX_INST_2
+0x462C US_TEX_INST_3
+0x4630 US_TEX_INST_4
+0x4634 US_TEX_INST_5
+0x4638 US_TEX_INST_6
+0x463C US_TEX_INST_7
+0x4640 US_TEX_INST_8
+0x4644 US_TEX_INST_9
+0x4648 US_TEX_INST_10
+0x464C US_TEX_INST_11
+0x4650 US_TEX_INST_12
+0x4654 US_TEX_INST_13
+0x4658 US_TEX_INST_14
+0x465C US_TEX_INST_15
+0x4660 US_TEX_INST_16
+0x4664 US_TEX_INST_17
+0x4668 US_TEX_INST_18
+0x466C US_TEX_INST_19
+0x4670 US_TEX_INST_20
+0x4674 US_TEX_INST_21
+0x4678 US_TEX_INST_22
+0x467C US_TEX_INST_23
+0x4680 US_TEX_INST_24
+0x4684 US_TEX_INST_25
+0x4688 US_TEX_INST_26
+0x468C US_TEX_INST_27
+0x4690 US_TEX_INST_28
+0x4694 US_TEX_INST_29
+0x4698 US_TEX_INST_30
+0x469C US_TEX_INST_31
+0x46A4 US_OUT_FMT_0
+0x46A8 US_OUT_FMT_1
+0x46AC US_OUT_FMT_2
+0x46B0 US_OUT_FMT_3
+0x46B4 US_W_FMT
+0x46C0 US_ALU_RGB_ADDR_0
+0x46C4 US_ALU_RGB_ADDR_1
+0x46C8 US_ALU_RGB_ADDR_2
+0x46CC US_ALU_RGB_ADDR_3
+0x46D0 US_ALU_RGB_ADDR_4
+0x46D4 US_ALU_RGB_ADDR_5
+0x46D8 US_ALU_RGB_ADDR_6
+0x46DC US_ALU_RGB_ADDR_7
+0x46E0 US_ALU_RGB_ADDR_8
+0x46E4 US_ALU_RGB_ADDR_9
+0x46E8 US_ALU_RGB_ADDR_10
+0x46EC US_ALU_RGB_ADDR_11
+0x46F0 US_ALU_RGB_ADDR_12
+0x46F4 US_ALU_RGB_ADDR_13
+0x46F8 US_ALU_RGB_ADDR_14
+0x46FC US_ALU_RGB_ADDR_15
+0x4700 US_ALU_RGB_ADDR_16
+0x4704 US_ALU_RGB_ADDR_17
+0x4708 US_ALU_RGB_ADDR_18
+0x470C US_ALU_RGB_ADDR_19
+0x4710 US_ALU_RGB_ADDR_20
+0x4714 US_ALU_RGB_ADDR_21
+0x4718 US_ALU_RGB_ADDR_22
+0x471C US_ALU_RGB_ADDR_23
+0x4720 US_ALU_RGB_ADDR_24
+0x4724 US_ALU_RGB_ADDR_25
+0x4728 US_ALU_RGB_ADDR_26
+0x472C US_ALU_RGB_ADDR_27
+0x4730 US_ALU_RGB_ADDR_28
+0x4734 US_ALU_RGB_ADDR_29
+0x4738 US_ALU_RGB_ADDR_30
+0x473C US_ALU_RGB_ADDR_31
+0x4740 US_ALU_RGB_ADDR_32
+0x4744 US_ALU_RGB_ADDR_33
+0x4748 US_ALU_RGB_ADDR_34
+0x474C US_ALU_RGB_ADDR_35
+0x4750 US_ALU_RGB_ADDR_36
+0x4754 US_ALU_RGB_ADDR_37
+0x4758 US_ALU_RGB_ADDR_38
+0x475C US_ALU_RGB_ADDR_39
+0x4760 US_ALU_RGB_ADDR_40
+0x4764 US_ALU_RGB_ADDR_41
+0x4768 US_ALU_RGB_ADDR_42
+0x476C US_ALU_RGB_ADDR_43
+0x4770 US_ALU_RGB_ADDR_44
+0x4774 US_ALU_RGB_ADDR_45
+0x4778 US_ALU_RGB_ADDR_46
+0x477C US_ALU_RGB_ADDR_47
+0x4780 US_ALU_RGB_ADDR_48
+0x4784 US_ALU_RGB_ADDR_49
+0x4788 US_ALU_RGB_ADDR_50
+0x478C US_ALU_RGB_ADDR_51
+0x4790 US_ALU_RGB_ADDR_52
+0x4794 US_ALU_RGB_ADDR_53
+0x4798 US_ALU_RGB_ADDR_54
+0x479C US_ALU_RGB_ADDR_55
+0x47A0 US_ALU_RGB_ADDR_56
+0x47A4 US_ALU_RGB_ADDR_57
+0x47A8 US_ALU_RGB_ADDR_58
+0x47AC US_ALU_RGB_ADDR_59
+0x47B0 US_ALU_RGB_ADDR_60
+0x47B4 US_ALU_RGB_ADDR_61
+0x47B8 US_ALU_RGB_ADDR_62
+0x47BC US_ALU_RGB_ADDR_63
+0x47C0 US_ALU_ALPHA_ADDR_0
+0x47C4 US_ALU_ALPHA_ADDR_1
+0x47C8 US_ALU_ALPHA_ADDR_2
+0x47CC US_ALU_ALPHA_ADDR_3
+0x47D0 US_ALU_ALPHA_ADDR_4
+0x47D4 US_ALU_ALPHA_ADDR_5
+0x47D8 US_ALU_ALPHA_ADDR_6
+0x47DC US_ALU_ALPHA_ADDR_7
+0x47E0 US_ALU_ALPHA_ADDR_8
+0x47E4 US_ALU_ALPHA_ADDR_9
+0x47E8 US_ALU_ALPHA_ADDR_10
+0x47EC US_ALU_ALPHA_ADDR_11
+0x47F0 US_ALU_ALPHA_ADDR_12
+0x47F4 US_ALU_ALPHA_ADDR_13
+0x47F8 US_ALU_ALPHA_ADDR_14
+0x47FC US_ALU_ALPHA_ADDR_15
+0x4800 US_ALU_ALPHA_ADDR_16
+0x4804 US_ALU_ALPHA_ADDR_17
+0x4808 US_ALU_ALPHA_ADDR_18
+0x480C US_ALU_ALPHA_ADDR_19
+0x4810 US_ALU_ALPHA_ADDR_20
+0x4814 US_ALU_ALPHA_ADDR_21
+0x4818 US_ALU_ALPHA_ADDR_22
+0x481C US_ALU_ALPHA_ADDR_23
+0x4820 US_ALU_ALPHA_ADDR_24
+0x4824 US_ALU_ALPHA_ADDR_25
+0x4828 US_ALU_ALPHA_ADDR_26
+0x482C US_ALU_ALPHA_ADDR_27
+0x4830 US_ALU_ALPHA_ADDR_28
+0x4834 US_ALU_ALPHA_ADDR_29
+0x4838 US_ALU_ALPHA_ADDR_30
+0x483C US_ALU_ALPHA_ADDR_31
+0x4840 US_ALU_ALPHA_ADDR_32
+0x4844 US_ALU_ALPHA_ADDR_33
+0x4848 US_ALU_ALPHA_ADDR_34
+0x484C US_ALU_ALPHA_ADDR_35
+0x4850 US_ALU_ALPHA_ADDR_36
+0x4854 US_ALU_ALPHA_ADDR_37
+0x4858 US_ALU_ALPHA_ADDR_38
+0x485C US_ALU_ALPHA_ADDR_39
+0x4860 US_ALU_ALPHA_ADDR_40
+0x4864 US_ALU_ALPHA_ADDR_41
+0x4868 US_ALU_ALPHA_ADDR_42
+0x486C US_ALU_ALPHA_ADDR_43
+0x4870 US_ALU_ALPHA_ADDR_44
+0x4874 US_ALU_ALPHA_ADDR_45
+0x4878 US_ALU_ALPHA_ADDR_46
+0x487C US_ALU_ALPHA_ADDR_47
+0x4880 US_ALU_ALPHA_ADDR_48
+0x4884 US_ALU_ALPHA_ADDR_49
+0x4888 US_ALU_ALPHA_ADDR_50
+0x488C US_ALU_ALPHA_ADDR_51
+0x4890 US_ALU_ALPHA_ADDR_52
+0x4894 US_ALU_ALPHA_ADDR_53
+0x4898 US_ALU_ALPHA_ADDR_54
+0x489C US_ALU_ALPHA_ADDR_55
+0x48A0 US_ALU_ALPHA_ADDR_56
+0x48A4 US_ALU_ALPHA_ADDR_57
+0x48A8 US_ALU_ALPHA_ADDR_58
+0x48AC US_ALU_ALPHA_ADDR_59
+0x48B0 US_ALU_ALPHA_ADDR_60
+0x48B4 US_ALU_ALPHA_ADDR_61
+0x48B8 US_ALU_ALPHA_ADDR_62
+0x48BC US_ALU_ALPHA_ADDR_63
+0x48C0 US_ALU_RGB_INST_0
+0x48C4 US_ALU_RGB_INST_1
+0x48C8 US_ALU_RGB_INST_2
+0x48CC US_ALU_RGB_INST_3
+0x48D0 US_ALU_RGB_INST_4
+0x48D4 US_ALU_RGB_INST_5
+0x48D8 US_ALU_RGB_INST_6
+0x48DC US_ALU_RGB_INST_7
+0x48E0 US_ALU_RGB_INST_8
+0x48E4 US_ALU_RGB_INST_9
+0x48E8 US_ALU_RGB_INST_10
+0x48EC US_ALU_RGB_INST_11
+0x48F0 US_ALU_RGB_INST_12
+0x48F4 US_ALU_RGB_INST_13
+0x48F8 US_ALU_RGB_INST_14
+0x48FC US_ALU_RGB_INST_15
+0x4900 US_ALU_RGB_INST_16
+0x4904 US_ALU_RGB_INST_17
+0x4908 US_ALU_RGB_INST_18
+0x490C US_ALU_RGB_INST_19
+0x4910 US_ALU_RGB_INST_20
+0x4914 US_ALU_RGB_INST_21
+0x4918 US_ALU_RGB_INST_22
+0x491C US_ALU_RGB_INST_23
+0x4920 US_ALU_RGB_INST_24
+0x4924 US_ALU_RGB_INST_25
+0x4928 US_ALU_RGB_INST_26
+0x492C US_ALU_RGB_INST_27
+0x4930 US_ALU_RGB_INST_28
+0x4934 US_ALU_RGB_INST_29
+0x4938 US_ALU_RGB_INST_30
+0x493C US_ALU_RGB_INST_31
+0x4940 US_ALU_RGB_INST_32
+0x4944 US_ALU_RGB_INST_33
+0x4948 US_ALU_RGB_INST_34
+0x494C US_ALU_RGB_INST_35
+0x4950 US_ALU_RGB_INST_36
+0x4954 US_ALU_RGB_INST_37
+0x4958 US_ALU_RGB_INST_38
+0x495C US_ALU_RGB_INST_39
+0x4960 US_ALU_RGB_INST_40
+0x4964 US_ALU_RGB_INST_41
+0x4968 US_ALU_RGB_INST_42
+0x496C US_ALU_RGB_INST_43
+0x4970 US_ALU_RGB_INST_44
+0x4974 US_ALU_RGB_INST_45
+0x4978 US_ALU_RGB_INST_46
+0x497C US_ALU_RGB_INST_47
+0x4980 US_ALU_RGB_INST_48
+0x4984 US_ALU_RGB_INST_49
+0x4988 US_ALU_RGB_INST_50
+0x498C US_ALU_RGB_INST_51
+0x4990 US_ALU_RGB_INST_52
+0x4994 US_ALU_RGB_INST_53
+0x4998 US_ALU_RGB_INST_54
+0x499C US_ALU_RGB_INST_55
+0x49A0 US_ALU_RGB_INST_56
+0x49A4 US_ALU_RGB_INST_57
+0x49A8 US_ALU_RGB_INST_58
+0x49AC US_ALU_RGB_INST_59
+0x49B0 US_ALU_RGB_INST_60
+0x49B4 US_ALU_RGB_INST_61
+0x49B8 US_ALU_RGB_INST_62
+0x49BC US_ALU_RGB_INST_63
+0x49C0 US_ALU_ALPHA_INST_0
+0x49C4 US_ALU_ALPHA_INST_1
+0x49C8 US_ALU_ALPHA_INST_2
+0x49CC US_ALU_ALPHA_INST_3
+0x49D0 US_ALU_ALPHA_INST_4
+0x49D4 US_ALU_ALPHA_INST_5
+0x49D8 US_ALU_ALPHA_INST_6
+0x49DC US_ALU_ALPHA_INST_7
+0x49E0 US_ALU_ALPHA_INST_8
+0x49E4 US_ALU_ALPHA_INST_9
+0x49E8 US_ALU_ALPHA_INST_10
+0x49EC US_ALU_ALPHA_INST_11
+0x49F0 US_ALU_ALPHA_INST_12
+0x49F4 US_ALU_ALPHA_INST_13
+0x49F8 US_ALU_ALPHA_INST_14
+0x49FC US_ALU_ALPHA_INST_15
+0x4A00 US_ALU_ALPHA_INST_16
+0x4A04 US_ALU_ALPHA_INST_17
+0x4A08 US_ALU_ALPHA_INST_18
+0x4A0C US_ALU_ALPHA_INST_19
+0x4A10 US_ALU_ALPHA_INST_20
+0x4A14 US_ALU_ALPHA_INST_21
+0x4A18 US_ALU_ALPHA_INST_22
+0x4A1C US_ALU_ALPHA_INST_23
+0x4A20 US_ALU_ALPHA_INST_24
+0x4A24 US_ALU_ALPHA_INST_25
+0x4A28 US_ALU_ALPHA_INST_26
+0x4A2C US_ALU_ALPHA_INST_27
+0x4A30 US_ALU_ALPHA_INST_28
+0x4A34 US_ALU_ALPHA_INST_29
+0x4A38 US_ALU_ALPHA_INST_30
+0x4A3C US_ALU_ALPHA_INST_31
+0x4A40 US_ALU_ALPHA_INST_32
+0x4A44 US_ALU_ALPHA_INST_33
+0x4A48 US_ALU_ALPHA_INST_34
+0x4A4C US_ALU_ALPHA_INST_35
+0x4A50 US_ALU_ALPHA_INST_36
+0x4A54 US_ALU_ALPHA_INST_37
+0x4A58 US_ALU_ALPHA_INST_38
+0x4A5C US_ALU_ALPHA_INST_39
+0x4A60 US_ALU_ALPHA_INST_40
+0x4A64 US_ALU_ALPHA_INST_41
+0x4A68 US_ALU_ALPHA_INST_42
+0x4A6C US_ALU_ALPHA_INST_43
+0x4A70 US_ALU_ALPHA_INST_44
+0x4A74 US_ALU_ALPHA_INST_45
+0x4A78 US_ALU_ALPHA_INST_46
+0x4A7C US_ALU_ALPHA_INST_47
+0x4A80 US_ALU_ALPHA_INST_48
+0x4A84 US_ALU_ALPHA_INST_49
+0x4A88 US_ALU_ALPHA_INST_50
+0x4A8C US_ALU_ALPHA_INST_51
+0x4A90 US_ALU_ALPHA_INST_52
+0x4A94 US_ALU_ALPHA_INST_53
+0x4A98 US_ALU_ALPHA_INST_54
+0x4A9C US_ALU_ALPHA_INST_55
+0x4AA0 US_ALU_ALPHA_INST_56
+0x4AA4 US_ALU_ALPHA_INST_57
+0x4AA8 US_ALU_ALPHA_INST_58
+0x4AAC US_ALU_ALPHA_INST_59
+0x4AB0 US_ALU_ALPHA_INST_60
+0x4AB4 US_ALU_ALPHA_INST_61
+0x4AB8 US_ALU_ALPHA_INST_62
+0x4ABC US_ALU_ALPHA_INST_63
+0x4BC0 FG_FOG_BLEND
+0x4BC4 FG_FOG_FACTOR
+0x4BC8 FG_FOG_COLOR_R
+0x4BCC FG_FOG_COLOR_G
+0x4BD0 FG_FOG_COLOR_B
+0x4BD4 FG_ALPHA_FUNC
+0x4BD8 FG_DEPTH_SRC
+0x4C00 US_ALU_CONST_R_0
+0x4C04 US_ALU_CONST_G_0
+0x4C08 US_ALU_CONST_B_0
+0x4C0C US_ALU_CONST_A_0
+0x4C10 US_ALU_CONST_R_1
+0x4C14 US_ALU_CONST_G_1
+0x4C18 US_ALU_CONST_B_1
+0x4C1C US_ALU_CONST_A_1
+0x4C20 US_ALU_CONST_R_2
+0x4C24 US_ALU_CONST_G_2
+0x4C28 US_ALU_CONST_B_2
+0x4C2C US_ALU_CONST_A_2
+0x4C30 US_ALU_CONST_R_3
+0x4C34 US_ALU_CONST_G_3
+0x4C38 US_ALU_CONST_B_3
+0x4C3C US_ALU_CONST_A_3
+0x4C40 US_ALU_CONST_R_4
+0x4C44 US_ALU_CONST_G_4
+0x4C48 US_ALU_CONST_B_4
+0x4C4C US_ALU_CONST_A_4
+0x4C50 US_ALU_CONST_R_5
+0x4C54 US_ALU_CONST_G_5
+0x4C58 US_ALU_CONST_B_5
+0x4C5C US_ALU_CONST_A_5
+0x4C60 US_ALU_CONST_R_6
+0x4C64 US_ALU_CONST_G_6
+0x4C68 US_ALU_CONST_B_6
+0x4C6C US_ALU_CONST_A_6
+0x4C70 US_ALU_CONST_R_7
+0x4C74 US_ALU_CONST_G_7
+0x4C78 US_ALU_CONST_B_7
+0x4C7C US_ALU_CONST_A_7
+0x4C80 US_ALU_CONST_R_8
+0x4C84 US_ALU_CONST_G_8
+0x4C88 US_ALU_CONST_B_8
+0x4C8C US_ALU_CONST_A_8
+0x4C90 US_ALU_CONST_R_9
+0x4C94 US_ALU_CONST_G_9
+0x4C98 US_ALU_CONST_B_9
+0x4C9C US_ALU_CONST_A_9
+0x4CA0 US_ALU_CONST_R_10
+0x4CA4 US_ALU_CONST_G_10
+0x4CA8 US_ALU_CONST_B_10
+0x4CAC US_ALU_CONST_A_10
+0x4CB0 US_ALU_CONST_R_11
+0x4CB4 US_ALU_CONST_G_11
+0x4CB8 US_ALU_CONST_B_11
+0x4CBC US_ALU_CONST_A_11
+0x4CC0 US_ALU_CONST_R_12
+0x4CC4 US_ALU_CONST_G_12
+0x4CC8 US_ALU_CONST_B_12
+0x4CCC US_ALU_CONST_A_12
+0x4CD0 US_ALU_CONST_R_13
+0x4CD4 US_ALU_CONST_G_13
+0x4CD8 US_ALU_CONST_B_13
+0x4CDC US_ALU_CONST_A_13
+0x4CE0 US_ALU_CONST_R_14
+0x4CE4 US_ALU_CONST_G_14
+0x4CE8 US_ALU_CONST_B_14
+0x4CEC US_ALU_CONST_A_14
+0x4CF0 US_ALU_CONST_R_15
+0x4CF4 US_ALU_CONST_G_15
+0x4CF8 US_ALU_CONST_B_15
+0x4CFC US_ALU_CONST_A_15
+0x4D00 US_ALU_CONST_R_16
+0x4D04 US_ALU_CONST_G_16
+0x4D08 US_ALU_CONST_B_16
+0x4D0C US_ALU_CONST_A_16
+0x4D10 US_ALU_CONST_R_17
+0x4D14 US_ALU_CONST_G_17
+0x4D18 US_ALU_CONST_B_17
+0x4D1C US_ALU_CONST_A_17
+0x4D20 US_ALU_CONST_R_18
+0x4D24 US_ALU_CONST_G_18
+0x4D28 US_ALU_CONST_B_18
+0x4D2C US_ALU_CONST_A_18
+0x4D30 US_ALU_CONST_R_19
+0x4D34 US_ALU_CONST_G_19
+0x4D38 US_ALU_CONST_B_19
+0x4D3C US_ALU_CONST_A_19
+0x4D40 US_ALU_CONST_R_20
+0x4D44 US_ALU_CONST_G_20
+0x4D48 US_ALU_CONST_B_20
+0x4D4C US_ALU_CONST_A_20
+0x4D50 US_ALU_CONST_R_21
+0x4D54 US_ALU_CONST_G_21
+0x4D58 US_ALU_CONST_B_21
+0x4D5C US_ALU_CONST_A_21
+0x4D60 US_ALU_CONST_R_22
+0x4D64 US_ALU_CONST_G_22
+0x4D68 US_ALU_CONST_B_22
+0x4D6C US_ALU_CONST_A_22
+0x4D70 US_ALU_CONST_R_23
+0x4D74 US_ALU_CONST_G_23
+0x4D78 US_ALU_CONST_B_23
+0x4D7C US_ALU_CONST_A_23
+0x4D80 US_ALU_CONST_R_24
+0x4D84 US_ALU_CONST_G_24
+0x4D88 US_ALU_CONST_B_24
+0x4D8C US_ALU_CONST_A_24
+0x4D90 US_ALU_CONST_R_25
+0x4D94 US_ALU_CONST_G_25
+0x4D98 US_ALU_CONST_B_25
+0x4D9C US_ALU_CONST_A_25
+0x4DA0 US_ALU_CONST_R_26
+0x4DA4 US_ALU_CONST_G_26
+0x4DA8 US_ALU_CONST_B_26
+0x4DAC US_ALU_CONST_A_26
+0x4DB0 US_ALU_CONST_R_27
+0x4DB4 US_ALU_CONST_G_27
+0x4DB8 US_ALU_CONST_B_27
+0x4DBC US_ALU_CONST_A_27
+0x4DC0 US_ALU_CONST_R_28
+0x4DC4 US_ALU_CONST_G_28
+0x4DC8 US_ALU_CONST_B_28
+0x4DCC US_ALU_CONST_A_28
+0x4DD0 US_ALU_CONST_R_29
+0x4DD4 US_ALU_CONST_G_29
+0x4DD8 US_ALU_CONST_B_29
+0x4DDC US_ALU_CONST_A_29
+0x4DE0 US_ALU_CONST_R_30
+0x4DE4 US_ALU_CONST_G_30
+0x4DE8 US_ALU_CONST_B_30
+0x4DEC US_ALU_CONST_A_30
+0x4DF0 US_ALU_CONST_R_31
+0x4DF4 US_ALU_CONST_G_31
+0x4DF8 US_ALU_CONST_B_31
+0x4DFC US_ALU_CONST_A_31
+0x4E04 RB3D_BLENDCNTL_R3
+0x4E08 RB3D_ABLENDCNTL_R3
+0x4E0C RB3D_COLOR_CHANNEL_MASK
+0x4E10 RB3D_CONSTANT_COLOR
+0x4E14 RB3D_COLOR_CLEAR_VALUE
+0x4E18 RB3D_ROPCNTL_R3
+0x4E1C RB3D_CLRCMP_FLIPE_R3
+0x4E20 RB3D_CLRCMP_CLR_R3
+0x4E24 RB3D_CLRCMP_MSK_R3
+0x4E48 RB3D_DEBUG_CTL
+0x4E4C RB3D_DSTCACHE_CTLSTAT_R3
+0x4E50 RB3D_DITHER_CTL
+0x4E54 RB3D_CMASK_OFFSET0
+0x4E58 RB3D_CMASK_OFFSET1
+0x4E5C RB3D_CMASK_OFFSET2
+0x4E60 RB3D_CMASK_OFFSET3
+0x4E64 RB3D_CMASK_PITCH0
+0x4E68 RB3D_CMASK_PITCH1
+0x4E6C RB3D_CMASK_PITCH2
+0x4E70 RB3D_CMASK_PITCH3
+0x4E74 RB3D_CMASK_WRINDEX
+0x4E78 RB3D_CMASK_DWORD
+0x4E7C RB3D_CMASK_RDINDEX
+0x4E80 RB3D_AARESOLVE_OFFSET
+0x4E84 RB3D_AARESOLVE_PITCH
+0x4E88 RB3D_AARESOLVE_CTL
+0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
+0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
+0x4F04 ZB_ZSTENCILCNTL
+0x4F08 ZB_STENCILREFMASK
+0x4F14 ZB_ZTOP
+0x4F18 ZB_ZCACHE_CTLSTAT
+0x4F1C ZB_BW_CNTL
+0x4F28 ZB_DEPTHCLEARVALUE
+0x4F30 ZB_ZMASK_OFFSET
+0x4F34 ZB_ZMASK_PITCH
+0x4F38 ZB_ZMASK_WRINDEX
+0x4F3C ZB_ZMASK_DWORD
+0x4F40 ZB_ZMASK_RDINDEX
+0x4F44 ZB_HIZ_OFFSET
+0x4F48 ZB_HIZ_WRINDEX
+0x4F4C ZB_HIZ_DWORD
+0x4F50 ZB_HIZ_RDINDEX
+0x4F54 ZB_HIZ_PITCH
+0x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
new file mode 100644
index 0000000..0102a0d
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -0,0 +1,486 @@
+rv515 0x6d40
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
+0x1D98 VAP_VPORT_XSCALE
+0x1D9C VAP_VPORT_XOFFSET
+0x1DA0 VAP_VPORT_YSCALE
+0x1DA4 VAP_VPORT_YOFFSET
+0x1DA8 VAP_VPORT_ZSCALE
+0x1DAC VAP_VPORT_ZOFFSET
+0x2080 VAP_CNTL
+0x2090 VAP_OUT_VTX_FMT_0
+0x2094 VAP_OUT_VTX_FMT_1
+0x20B0 VAP_VTE_CNTL
+0x2138 VAP_VF_MIN_VTX_INDX
+0x2140 VAP_CNTL_STATUS
+0x2150 VAP_PROG_STREAM_CNTL_0
+0x2154 VAP_PROG_STREAM_CNTL_1
+0x2158 VAP_PROG_STREAM_CNTL_2
+0x215C VAP_PROG_STREAM_CNTL_3
+0x2160 VAP_PROG_STREAM_CNTL_4
+0x2164 VAP_PROG_STREAM_CNTL_5
+0x2168 VAP_PROG_STREAM_CNTL_6
+0x216C VAP_PROG_STREAM_CNTL_7
+0x2180 VAP_VTX_STATE_CNTL
+0x2184 VAP_VSM_VTX_ASSM
+0x2188 VAP_VTX_STATE_IND_REG_0
+0x218C VAP_VTX_STATE_IND_REG_1
+0x2190 VAP_VTX_STATE_IND_REG_2
+0x2194 VAP_VTX_STATE_IND_REG_3
+0x2198 VAP_VTX_STATE_IND_REG_4
+0x219C VAP_VTX_STATE_IND_REG_5
+0x21A0 VAP_VTX_STATE_IND_REG_6
+0x21A4 VAP_VTX_STATE_IND_REG_7
+0x21A8 VAP_VTX_STATE_IND_REG_8
+0x21AC VAP_VTX_STATE_IND_REG_9
+0x21B0 VAP_VTX_STATE_IND_REG_10
+0x21B4 VAP_VTX_STATE_IND_REG_11
+0x21B8 VAP_VTX_STATE_IND_REG_12
+0x21BC VAP_VTX_STATE_IND_REG_13
+0x21C0 VAP_VTX_STATE_IND_REG_14
+0x21C4 VAP_VTX_STATE_IND_REG_15
+0x21DC VAP_PSC_SGN_NORM_CNTL
+0x21E0 VAP_PROG_STREAM_CNTL_EXT_0
+0x21E4 VAP_PROG_STREAM_CNTL_EXT_1
+0x21E8 VAP_PROG_STREAM_CNTL_EXT_2
+0x21EC VAP_PROG_STREAM_CNTL_EXT_3
+0x21F0 VAP_PROG_STREAM_CNTL_EXT_4
+0x21F4 VAP_PROG_STREAM_CNTL_EXT_5
+0x21F8 VAP_PROG_STREAM_CNTL_EXT_6
+0x21FC VAP_PROG_STREAM_CNTL_EXT_7
+0x2200 VAP_PVS_VECTOR_INDX_REG
+0x2204 VAP_PVS_VECTOR_DATA_REG
+0x2208 VAP_PVS_VECTOR_DATA_REG_128
+0x2218 VAP_TEX_TO_COLOR_CNTL
+0x221C VAP_CLIP_CNTL
+0x2220 VAP_GB_VERT_CLIP_ADJ
+0x2224 VAP_GB_VERT_DISC_ADJ
+0x2228 VAP_GB_HORZ_CLIP_ADJ
+0x222C VAP_GB_HORZ_DISC_ADJ
+0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0
+0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1
+0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2
+0x223C VAP_PVS_FLOW_CNTL_ADDRS_3
+0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4
+0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5
+0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6
+0x224C VAP_PVS_FLOW_CNTL_ADDRS_7
+0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8
+0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9
+0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10
+0x225C VAP_PVS_FLOW_CNTL_ADDRS_11
+0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12
+0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13
+0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14
+0x226C VAP_PVS_FLOW_CNTL_ADDRS_15
+0x2284 VAP_PVS_STATE_FLUSH_REG
+0x2288 VAP_PVS_VTX_TIMEOUT_REG
+0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
+0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1
+0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2
+0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3
+0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4
+0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5
+0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6
+0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7
+0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8
+0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9
+0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10
+0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11
+0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12
+0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13
+0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14
+0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15
+0x22D0 VAP_PVS_CODE_CNTL_0
+0x22D4 VAP_PVS_CONST_CNTL
+0x22D8 VAP_PVS_CODE_CNTL_1
+0x22DC VAP_PVS_FLOW_CNTL_OPC
+0x2500 VAP_PVS_FLOW_CNTL_ADDRS_LW_0
+0x2504 VAP_PVS_FLOW_CNTL_ADDRS_UW_0
+0x2508 VAP_PVS_FLOW_CNTL_ADDRS_LW_1
+0x250C VAP_PVS_FLOW_CNTL_ADDRS_UW_1
+0x2510 VAP_PVS_FLOW_CNTL_ADDRS_LW_2
+0x2514 VAP_PVS_FLOW_CNTL_ADDRS_UW_2
+0x2518 VAP_PVS_FLOW_CNTL_ADDRS_LW_3
+0x251C VAP_PVS_FLOW_CNTL_ADDRS_UW_3
+0x2520 VAP_PVS_FLOW_CNTL_ADDRS_LW_4
+0x2524 VAP_PVS_FLOW_CNTL_ADDRS_UW_4
+0x2528 VAP_PVS_FLOW_CNTL_ADDRS_LW_5
+0x252C VAP_PVS_FLOW_CNTL_ADDRS_UW_5
+0x2530 VAP_PVS_FLOW_CNTL_ADDRS_LW_6
+0x2534 VAP_PVS_FLOW_CNTL_ADDRS_UW_6
+0x2538 VAP_PVS_FLOW_CNTL_ADDRS_LW_7
+0x253C VAP_PVS_FLOW_CNTL_ADDRS_UW_7
+0x2540 VAP_PVS_FLOW_CNTL_ADDRS_LW_8
+0x2544 VAP_PVS_FLOW_CNTL_ADDRS_UW_8
+0x2548 VAP_PVS_FLOW_CNTL_ADDRS_LW_9
+0x254C VAP_PVS_FLOW_CNTL_ADDRS_UW_9
+0x2550 VAP_PVS_FLOW_CNTL_ADDRS_LW_10
+0x2554 VAP_PVS_FLOW_CNTL_ADDRS_UW_10
+0x2558 VAP_PVS_FLOW_CNTL_ADDRS_LW_11
+0x255C VAP_PVS_FLOW_CNTL_ADDRS_UW_11
+0x2560 VAP_PVS_FLOW_CNTL_ADDRS_LW_12
+0x2564 VAP_PVS_FLOW_CNTL_ADDRS_UW_12
+0x2568 VAP_PVS_FLOW_CNTL_ADDRS_LW_13
+0x256C VAP_PVS_FLOW_CNTL_ADDRS_UW_13
+0x2570 VAP_PVS_FLOW_CNTL_ADDRS_LW_14
+0x2574 VAP_PVS_FLOW_CNTL_ADDRS_UW_14
+0x2578 VAP_PVS_FLOW_CNTL_ADDRS_LW_15
+0x257C VAP_PVS_FLOW_CNTL_ADDRS_UW_15
+0x342C RB2D_DSTCACHE_CTLSTAT
+0x4000 GB_VAP_RASTER_VTX_FMT_0
+0x4004 GB_VAP_RASTER_VTX_FMT_1
+0x4008 GB_ENABLE
+0x401C GB_SELECT
+0x4020 GB_AA_CONFIG
+0x4024 GB_FIFO_SIZE
+0x4100 TX_INVALTAGS
+0x4200 GA_POINT_S0
+0x4204 GA_POINT_T0
+0x4208 GA_POINT_S1
+0x420C GA_POINT_T1
+0x4214 GA_TRIANGLE_STIPPLE
+0x421C GA_POINT_SIZE
+0x4230 GA_POINT_MINMAX
+0x4234 GA_LINE_CNTL
+0x4238 GA_LINE_STIPPLE_CONFIG
+0x4260 GA_LINE_STIPPLE_VALUE
+0x4264 GA_LINE_S0
+0x4268 GA_LINE_S1
+0x4278 GA_COLOR_CONTROL
+0x427C GA_SOLID_RG
+0x4280 GA_SOLID_BA
+0x4288 GA_POLY_MODE
+0x428C GA_ROUND_MODE
+0x4290 GA_OFFSET
+0x4294 GA_FOG_SCALE
+0x4298 GA_FOG_OFFSET
+0x42A0 SU_TEX_WRAP
+0x42A4 SU_POLY_OFFSET_FRONT_SCALE
+0x42A8 SU_POLY_OFFSET_FRONT_OFFSET
+0x42AC SU_POLY_OFFSET_BACK_SCALE
+0x42B0 SU_POLY_OFFSET_BACK_OFFSET
+0x42B4 SU_POLY_OFFSET_ENABLE
+0x42B8 SU_CULL_MODE
+0x42C0 SU_DEPTH_SCALE
+0x42C4 SU_DEPTH_OFFSET
+0x42C8 SU_REG_DEST
+0x4300 RS_COUNT
+0x4304 RS_INST_COUNT
+0x4074 RS_IP_0
+0x4078 RS_IP_1
+0x407C RS_IP_2
+0x4080 RS_IP_3
+0x4084 RS_IP_4
+0x4088 RS_IP_5
+0x408C RS_IP_6
+0x4090 RS_IP_7
+0x4094 RS_IP_8
+0x4098 RS_IP_9
+0x409C RS_IP_10
+0x40A0 RS_IP_11
+0x40A4 RS_IP_12
+0x40A8 RS_IP_13
+0x40AC RS_IP_14
+0x40B0 RS_IP_15
+0x4320 RS_INST_0
+0x4324 RS_INST_1
+0x4328 RS_INST_2
+0x432C RS_INST_3
+0x4330 RS_INST_4
+0x4334 RS_INST_5
+0x4338 RS_INST_6
+0x433C RS_INST_7
+0x4340 RS_INST_8
+0x4344 RS_INST_9
+0x4348 RS_INST_10
+0x434C RS_INST_11
+0x4350 RS_INST_12
+0x4354 RS_INST_13
+0x4358 RS_INST_14
+0x435C RS_INST_15
+0x43A4 SC_HYPERZ_EN
+0x43A8 SC_EDGERULE
+0x43B0 SC_CLIP_0_A
+0x43B4 SC_CLIP_0_B
+0x43B8 SC_CLIP_1_A
+0x43BC SC_CLIP_1_B
+0x43C0 SC_CLIP_2_A
+0x43C4 SC_CLIP_2_B
+0x43C8 SC_CLIP_3_A
+0x43CC SC_CLIP_3_B
+0x43D0 SC_CLIP_RULE
+0x43E0 SC_SCISSOR0
+0x43E8 SC_SCREENDOOR
+0x4440 TX_FILTER1_0
+0x4444 TX_FILTER1_1
+0x4448 TX_FILTER1_2
+0x444C TX_FILTER1_3
+0x4450 TX_FILTER1_4
+0x4454 TX_FILTER1_5
+0x4458 TX_FILTER1_6
+0x445C TX_FILTER1_7
+0x4460 TX_FILTER1_8
+0x4464 TX_FILTER1_9
+0x4468 TX_FILTER1_10
+0x446C TX_FILTER1_11
+0x4470 TX_FILTER1_12
+0x4474 TX_FILTER1_13
+0x4478 TX_FILTER1_14
+0x447C TX_FILTER1_15
+0x4580 TX_CHROMA_KEY_0
+0x4584 TX_CHROMA_KEY_1
+0x4588 TX_CHROMA_KEY_2
+0x458C TX_CHROMA_KEY_3
+0x4590 TX_CHROMA_KEY_4
+0x4594 TX_CHROMA_KEY_5
+0x4598 TX_CHROMA_KEY_6
+0x459C TX_CHROMA_KEY_7
+0x45A0 TX_CHROMA_KEY_8
+0x45A4 TX_CHROMA_KEY_9
+0x45A8 TX_CHROMA_KEY_10
+0x45AC TX_CHROMA_KEY_11
+0x45B0 TX_CHROMA_KEY_12
+0x45B4 TX_CHROMA_KEY_13
+0x45B8 TX_CHROMA_KEY_14
+0x45BC TX_CHROMA_KEY_15
+0x45C0 TX_BORDER_COLOR_0
+0x45C4 TX_BORDER_COLOR_1
+0x45C8 TX_BORDER_COLOR_2
+0x45CC TX_BORDER_COLOR_3
+0x45D0 TX_BORDER_COLOR_4
+0x45D4 TX_BORDER_COLOR_5
+0x45D8 TX_BORDER_COLOR_6
+0x45DC TX_BORDER_COLOR_7
+0x45E0 TX_BORDER_COLOR_8
+0x45E4 TX_BORDER_COLOR_9
+0x45E8 TX_BORDER_COLOR_10
+0x45EC TX_BORDER_COLOR_11
+0x45F0 TX_BORDER_COLOR_12
+0x45F4 TX_BORDER_COLOR_13
+0x45F8 TX_BORDER_COLOR_14
+0x45FC TX_BORDER_COLOR_15
+0x4250 GA_US_VECTOR_INDEX
+0x4254 GA_US_VECTOR_DATA
+0x4600 US_CONFIG
+0x4604 US_PIXSIZE
+0x4620 US_FC_BOOL_CONST
+0x4624 US_FC_CTRL
+0x4630 US_CODE_ADDR
+0x4634 US_CODE_RANGE
+0x4638 US_CODE_OFFSET
+0x46A4 US_OUT_FMT_0
+0x46A8 US_OUT_FMT_1
+0x46AC US_OUT_FMT_2
+0x46B0 US_OUT_FMT_3
+0x46B4 US_W_FMT
+0x4BC0 FG_FOG_BLEND
+0x4BC4 FG_FOG_FACTOR
+0x4BC8 FG_FOG_COLOR_R
+0x4BCC FG_FOG_COLOR_G
+0x4BD0 FG_FOG_COLOR_B
+0x4BD4 FG_ALPHA_FUNC
+0x4BD8 FG_DEPTH_SRC
+0x4C00 US_ALU_CONST_R_0
+0x4C04 US_ALU_CONST_G_0
+0x4C08 US_ALU_CONST_B_0
+0x4C0C US_ALU_CONST_A_0
+0x4C10 US_ALU_CONST_R_1
+0x4C14 US_ALU_CONST_G_1
+0x4C18 US_ALU_CONST_B_1
+0x4C1C US_ALU_CONST_A_1
+0x4C20 US_ALU_CONST_R_2
+0x4C24 US_ALU_CONST_G_2
+0x4C28 US_ALU_CONST_B_2
+0x4C2C US_ALU_CONST_A_2
+0x4C30 US_ALU_CONST_R_3
+0x4C34 US_ALU_CONST_G_3
+0x4C38 US_ALU_CONST_B_3
+0x4C3C US_ALU_CONST_A_3
+0x4C40 US_ALU_CONST_R_4
+0x4C44 US_ALU_CONST_G_4
+0x4C48 US_ALU_CONST_B_4
+0x4C4C US_ALU_CONST_A_4
+0x4C50 US_ALU_CONST_R_5
+0x4C54 US_ALU_CONST_G_5
+0x4C58 US_ALU_CONST_B_5
+0x4C5C US_ALU_CONST_A_5
+0x4C60 US_ALU_CONST_R_6
+0x4C64 US_ALU_CONST_G_6
+0x4C68 US_ALU_CONST_B_6
+0x4C6C US_ALU_CONST_A_6
+0x4C70 US_ALU_CONST_R_7
+0x4C74 US_ALU_CONST_G_7
+0x4C78 US_ALU_CONST_B_7
+0x4C7C US_ALU_CONST_A_7
+0x4C80 US_ALU_CONST_R_8
+0x4C84 US_ALU_CONST_G_8
+0x4C88 US_ALU_CONST_B_8
+0x4C8C US_ALU_CONST_A_8
+0x4C90 US_ALU_CONST_R_9
+0x4C94 US_ALU_CONST_G_9
+0x4C98 US_ALU_CONST_B_9
+0x4C9C US_ALU_CONST_A_9
+0x4CA0 US_ALU_CONST_R_10
+0x4CA4 US_ALU_CONST_G_10
+0x4CA8 US_ALU_CONST_B_10
+0x4CAC US_ALU_CONST_A_10
+0x4CB0 US_ALU_CONST_R_11
+0x4CB4 US_ALU_CONST_G_11
+0x4CB8 US_ALU_CONST_B_11
+0x4CBC US_ALU_CONST_A_11
+0x4CC0 US_ALU_CONST_R_12
+0x4CC4 US_ALU_CONST_G_12
+0x4CC8 US_ALU_CONST_B_12
+0x4CCC US_ALU_CONST_A_12
+0x4CD0 US_ALU_CONST_R_13
+0x4CD4 US_ALU_CONST_G_13
+0x4CD8 US_ALU_CONST_B_13
+0x4CDC US_ALU_CONST_A_13
+0x4CE0 US_ALU_CONST_R_14
+0x4CE4 US_ALU_CONST_G_14
+0x4CE8 US_ALU_CONST_B_14
+0x4CEC US_ALU_CONST_A_14
+0x4CF0 US_ALU_CONST_R_15
+0x4CF4 US_ALU_CONST_G_15
+0x4CF8 US_ALU_CONST_B_15
+0x4CFC US_ALU_CONST_A_15
+0x4D00 US_ALU_CONST_R_16
+0x4D04 US_ALU_CONST_G_16
+0x4D08 US_ALU_CONST_B_16
+0x4D0C US_ALU_CONST_A_16
+0x4D10 US_ALU_CONST_R_17
+0x4D14 US_ALU_CONST_G_17
+0x4D18 US_ALU_CONST_B_17
+0x4D1C US_ALU_CONST_A_17
+0x4D20 US_ALU_CONST_R_18
+0x4D24 US_ALU_CONST_G_18
+0x4D28 US_ALU_CONST_B_18
+0x4D2C US_ALU_CONST_A_18
+0x4D30 US_ALU_CONST_R_19
+0x4D34 US_ALU_CONST_G_19
+0x4D38 US_ALU_CONST_B_19
+0x4D3C US_ALU_CONST_A_19
+0x4D40 US_ALU_CONST_R_20
+0x4D44 US_ALU_CONST_G_20
+0x4D48 US_ALU_CONST_B_20
+0x4D4C US_ALU_CONST_A_20
+0x4D50 US_ALU_CONST_R_21
+0x4D54 US_ALU_CONST_G_21
+0x4D58 US_ALU_CONST_B_21
+0x4D5C US_ALU_CONST_A_21
+0x4D60 US_ALU_CONST_R_22
+0x4D64 US_ALU_CONST_G_22
+0x4D68 US_ALU_CONST_B_22
+0x4D6C US_ALU_CONST_A_22
+0x4D70 US_ALU_CONST_R_23
+0x4D74 US_ALU_CONST_G_23
+0x4D78 US_ALU_CONST_B_23
+0x4D7C US_ALU_CONST_A_23
+0x4D80 US_ALU_CONST_R_24
+0x4D84 US_ALU_CONST_G_24
+0x4D88 US_ALU_CONST_B_24
+0x4D8C US_ALU_CONST_A_24
+0x4D90 US_ALU_CONST_R_25
+0x4D94 US_ALU_CONST_G_25
+0x4D98 US_ALU_CONST_B_25
+0x4D9C US_ALU_CONST_A_25
+0x4DA0 US_ALU_CONST_R_26
+0x4DA4 US_ALU_CONST_G_26
+0x4DA8 US_ALU_CONST_B_26
+0x4DAC US_ALU_CONST_A_26
+0x4DB0 US_ALU_CONST_R_27
+0x4DB4 US_ALU_CONST_G_27
+0x4DB8 US_ALU_CONST_B_27
+0x4DBC US_ALU_CONST_A_27
+0x4DC0 US_ALU_CONST_R_28
+0x4DC4 US_ALU_CONST_G_28
+0x4DC8 US_ALU_CONST_B_28
+0x4DCC US_ALU_CONST_A_28
+0x4DD0 US_ALU_CONST_R_29
+0x4DD4 US_ALU_CONST_G_29
+0x4DD8 US_ALU_CONST_B_29
+0x4DDC US_ALU_CONST_A_29
+0x4DE0 US_ALU_CONST_R_30
+0x4DE4 US_ALU_CONST_G_30
+0x4DE8 US_ALU_CONST_B_30
+0x4DEC US_ALU_CONST_A_30
+0x4DF0 US_ALU_CONST_R_31
+0x4DF4 US_ALU_CONST_G_31
+0x4DF8 US_ALU_CONST_B_31
+0x4DFC US_ALU_CONST_A_31
+0x4E04 RB3D_BLENDCNTL_R3
+0x4E08 RB3D_ABLENDCNTL_R3
+0x4E0C RB3D_COLOR_CHANNEL_MASK
+0x4E10 RB3D_CONSTANT_COLOR
+0x4E14 RB3D_COLOR_CLEAR_VALUE
+0x4E18 RB3D_ROPCNTL_R3
+0x4E1C RB3D_CLRCMP_FLIPE_R3
+0x4E20 RB3D_CLRCMP_CLR_R3
+0x4E24 RB3D_CLRCMP_MSK_R3
+0x4E48 RB3D_DEBUG_CTL
+0x4E4C RB3D_DSTCACHE_CTLSTAT_R3
+0x4E50 RB3D_DITHER_CTL
+0x4E54 RB3D_CMASK_OFFSET0
+0x4E58 RB3D_CMASK_OFFSET1
+0x4E5C RB3D_CMASK_OFFSET2
+0x4E60 RB3D_CMASK_OFFSET3
+0x4E64 RB3D_CMASK_PITCH0
+0x4E68 RB3D_CMASK_PITCH1
+0x4E6C RB3D_CMASK_PITCH2
+0x4E70 RB3D_CMASK_PITCH3
+0x4E74 RB3D_CMASK_WRINDEX
+0x4E78 RB3D_CMASK_DWORD
+0x4E7C RB3D_CMASK_RDINDEX
+0x4E80 RB3D_AARESOLVE_OFFSET
+0x4E84 RB3D_AARESOLVE_PITCH
+0x4E88 RB3D_AARESOLVE_CTL
+0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
+0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
+0x4EF8 RB3D_CONSTANT_COLOR_AR
+0x4EFC RB3D_CONSTANT_COLOR_GB
+0x4F04 ZB_ZSTENCILCNTL
+0x4F08 ZB_STENCILREFMASK
+0x4F14 ZB_ZTOP
+0x4F18 ZB_ZCACHE_CTLSTAT
+0x4F1C ZB_BW_CNTL
+0x4F28 ZB_DEPTHCLEARVALUE
+0x4F30 ZB_ZMASK_OFFSET
+0x4F34 ZB_ZMASK_PITCH
+0x4F38 ZB_ZMASK_WRINDEX
+0x4F3C ZB_ZMASK_DWORD
+0x4F40 ZB_ZMASK_RDINDEX
+0x4F44 ZB_HIZ_OFFSET
+0x4F48 ZB_HIZ_WRINDEX
+0x4F4C ZB_HIZ_DWORD
+0x4F50 ZB_HIZ_RDINDEX
+0x4F54 ZB_HIZ_PITCH
+0x4F58 ZB_ZPASS_DATA
+0x4FD4 ZB_STENCILREFMASK_BF
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index b29affd..a3fbdad 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -29,7 +29,6 @@
#include <drm/drmP.h>
#include "radeon_reg.h"
#include "radeon.h"
-#include "radeon_share.h"
/* rs400,rs480 depends on : */
void r100_hdp_reset(struct radeon_device *rdev);
@@ -63,7 +62,7 @@ void rs400_gart_adjust_size(struct radeon_device *rdev)
break;
default:
DRM_ERROR("Unable to use IGP GART size %uM\n",
- rdev->mc.gtt_size >> 20);
+ (unsigned)(rdev->mc.gtt_size >> 20));
DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
DRM_ERROR("Forcing to 32M GART size\n");
rdev->mc.gtt_size = 32 * 1024 * 1024;
@@ -93,20 +92,41 @@ void rs400_gart_tlb_flush(struct radeon_device *rdev)
WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
}
-int rs400_gart_enable(struct radeon_device *rdev)
+int rs400_gart_init(struct radeon_device *rdev)
{
- uint32_t size_reg;
- uint32_t tmp;
int r;
+ if (rdev->gart.table.ram.ptr) {
+ WARN(1, "RS400 GART already initialized.\n");
+ return 0;
+ }
+ /* Check gart size */
+ switch(rdev->mc.gtt_size / (1024 * 1024)) {
+ case 32:
+ case 64:
+ case 128:
+ case 256:
+ case 512:
+ case 1024:
+ case 2048:
+ break;
+ default:
+ return -EINVAL;
+ }
/* Initialize common gart structure */
r = radeon_gart_init(rdev);
- if (r) {
+ if (r)
return r;
- }
- if (rs400_debugfs_pcie_gart_info_init(rdev)) {
+ if (rs400_debugfs_pcie_gart_info_init(rdev))
DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
- }
+ rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
+ return radeon_gart_table_ram_alloc(rdev);
+}
+
+int rs400_gart_enable(struct radeon_device *rdev)
+{
+ uint32_t size_reg;
+ uint32_t tmp;
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
@@ -137,13 +157,6 @@ int rs400_gart_enable(struct radeon_device *rdev)
default:
return -EINVAL;
}
- if (rdev->gart.table.ram.ptr == NULL) {
- rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
- r = radeon_gart_table_ram_alloc(rdev);
- if (r) {
- return r;
- }
- }
/* It should be fine to program it to max value */
if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
@@ -202,6 +215,13 @@ void rs400_gart_disable(struct radeon_device *rdev)
WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
}
+void rs400_gart_fini(struct radeon_device *rdev)
+{
+ rs400_gart_disable(rdev);
+ radeon_gart_table_ram_free(rdev);
+ radeon_gart_fini(rdev);
+}
+
int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
{
uint32_t entry;
@@ -256,14 +276,12 @@ int rs400_mc_init(struct radeon_device *rdev)
(void)RREG32(RADEON_HOST_PATH_CNTL);
WREG32(RADEON_HOST_PATH_CNTL, tmp);
(void)RREG32(RADEON_HOST_PATH_CNTL);
+
return 0;
}
void rs400_mc_fini(struct radeon_device *rdev)
{
- rs400_gart_disable(rdev);
- radeon_gart_table_ram_free(rdev);
- radeon_gart_fini(rdev);
}
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 02fd11a..0e791e26 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -28,6 +28,9 @@
#include "drmP.h"
#include "radeon_reg.h"
#include "radeon.h"
+#include "avivod.h"
+
+#include "rs600_reg_safe.h"
/* rs600 depends on : */
void r100_hdp_reset(struct radeon_device *rdev);
@@ -66,22 +69,35 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev)
tmp = RREG32_MC(RS600_MC_PT0_CNTL);
}
-int rs600_gart_enable(struct radeon_device *rdev)
+int rs600_gart_init(struct radeon_device *rdev)
{
- uint32_t tmp;
- int i;
int r;
+ if (rdev->gart.table.vram.robj) {
+ WARN(1, "RS600 GART already initialized.\n");
+ return 0;
+ }
/* Initialize common gart structure */
r = radeon_gart_init(rdev);
if (r) {
return r;
}
rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
- r = radeon_gart_table_vram_alloc(rdev);
- if (r) {
- return r;
+ return radeon_gart_table_vram_alloc(rdev);
+}
+
+int rs600_gart_enable(struct radeon_device *rdev)
+{
+ uint32_t tmp;
+ int r, i;
+
+ if (rdev->gart.table.vram.robj == NULL) {
+ dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
+ return -EINVAL;
}
+ r = radeon_gart_table_vram_pin(rdev);
+ if (r)
+ return r;
/* FIXME: setup default page */
WREG32_MC(RS600_MC_PT0_CNTL,
(RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
@@ -136,8 +152,17 @@ void rs600_gart_disable(struct radeon_device *rdev)
tmp = RREG32_MC(RS600_MC_CNTL1);
tmp &= ~RS600_ENABLE_PAGE_TABLES;
WREG32_MC(RS600_MC_CNTL1, tmp);
- radeon_object_kunmap(rdev->gart.table.vram.robj);
- radeon_object_unpin(rdev->gart.table.vram.robj);
+ if (rdev->gart.table.vram.robj) {
+ radeon_object_kunmap(rdev->gart.table.vram.robj);
+ radeon_object_unpin(rdev->gart.table.vram.robj);
+ }
+}
+
+void rs600_gart_fini(struct radeon_device *rdev)
+{
+ rs600_gart_disable(rdev);
+ radeon_gart_table_vram_free(rdev);
+ radeon_gart_fini(rdev);
}
#define R600_PTE_VALID (1 << 0)
@@ -173,6 +198,8 @@ void rs600_mc_disable_clients(struct radeon_device *rdev)
"programming pipes. Bad things might happen.\n");
}
+ radeon_avivo_vga_render_disable(rdev);
+
tmp = RREG32(AVIVO_D1VGA_CONTROL);
WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
tmp = RREG32(AVIVO_D2VGA_CONTROL);
@@ -233,9 +260,6 @@ int rs600_mc_init(struct radeon_device *rdev)
void rs600_mc_fini(struct radeon_device *rdev)
{
- rs600_gart_disable(rdev);
- radeon_gart_table_vram_free(rdev);
- radeon_gart_fini(rdev);
}
@@ -251,11 +275,9 @@ int rs600_irq_set(struct radeon_device *rdev)
tmp |= RADEON_SW_INT_ENABLE;
}
if (rdev->irq.crtc_vblank_int[0]) {
- tmp |= AVIVO_DISPLAY_INT_STATUS;
mode_int |= AVIVO_D1MODE_INT_MASK;
}
if (rdev->irq.crtc_vblank_int[1]) {
- tmp |= AVIVO_DISPLAY_INT_STATUS;
mode_int |= AVIVO_D2MODE_INT_MASK;
}
WREG32(RADEON_GEN_INT_CNTL, tmp);
@@ -410,64 +432,6 @@ void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
WREG32(RS600_MC_DATA, v);
}
-static const unsigned rs600_reg_safe_bm[219] = {
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
- 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
- 0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF,
- 0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF,
- 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
- 0x00000000, 0x0000C100, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x0003FC01, 0xFFFFFCF8, 0xFF800B19, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-};
-
int rs600_init(struct radeon_device *rdev)
{
rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 8798825..0f585ca 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -94,9 +94,6 @@ int rs690_mc_init(struct radeon_device *rdev)
void rs690_mc_fini(struct radeon_device *rdev)
{
- rs400_gart_disable(rdev);
- radeon_gart_table_ram_free(rdev);
- radeon_gart_fini(rdev);
}
@@ -652,4 +649,3 @@ void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
WREG32(RS690_MC_DATA, v);
WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
}
-
diff --git a/drivers/gpu/drm/radeon/rs780.c b/drivers/gpu/drm/radeon/rs780.c
deleted file mode 100644
index 0affcff..0000000
--- a/drivers/gpu/drm/radeon/rs780.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- * Alex Deucher
- * Jerome Glisse
- */
-#include "drmP.h"
-#include "radeon_reg.h"
-#include "radeon.h"
-
-/* rs780 depends on : */
-void rs600_mc_disable_clients(struct radeon_device *rdev);
-
-/* This files gather functions specifics to:
- * rs780
- *
- * Some of these functions might be used by newer ASICs.
- */
-int rs780_mc_wait_for_idle(struct radeon_device *rdev);
-void rs780_gpu_init(struct radeon_device *rdev);
-
-
-/*
- * MC
- */
-int rs780_mc_init(struct radeon_device *rdev)
-{
- rs780_gpu_init(rdev);
- /* FIXME: implement */
-
- rs600_mc_disable_clients(rdev);
- if (rs780_mc_wait_for_idle(rdev)) {
- printk(KERN_WARNING "Failed to wait MC idle while "
- "programming pipes. Bad things might happen.\n");
- }
- return 0;
-}
-
-void rs780_mc_fini(struct radeon_device *rdev)
-{
- /* FIXME: implement */
-}
-
-
-/*
- * Global GPU functions
- */
-void rs780_errata(struct radeon_device *rdev)
-{
- rdev->pll_errata = 0;
-}
-
-int rs780_mc_wait_for_idle(struct radeon_device *rdev)
-{
- /* FIXME: implement */
- return 0;
-}
-
-void rs780_gpu_init(struct radeon_device *rdev)
-{
- /* FIXME: implement */
-}
-
-
-/*
- * VRAM info
- */
-void rs780_vram_get_type(struct radeon_device *rdev)
-{
- /* FIXME: implement */
-}
-
-void rs780_vram_info(struct radeon_device *rdev)
-{
- rs780_vram_get_type(rdev);
-
- /* FIXME: implement */
- /* Could aper size report 0 ? */
- rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
- rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
-}
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 0566fb6..fd79974 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -27,18 +27,16 @@
*/
#include <linux/seq_file.h>
#include "drmP.h"
-#include "rv515r.h"
+#include "rv515d.h"
#include "radeon.h"
-#include "radeon_share.h"
+#include "rv515_reg_safe.h"
/* rv515 depends on : */
void r100_hdp_reset(struct radeon_device *rdev);
int r100_cp_reset(struct radeon_device *rdev);
int r100_rb2d_reset(struct radeon_device *rdev);
int r100_gui_wait_for_idle(struct radeon_device *rdev);
int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
-int rv370_pcie_gart_enable(struct radeon_device *rdev);
-void rv370_pcie_gart_disable(struct radeon_device *rdev);
void r420_pipes_init(struct radeon_device *rdev);
void rs600_mc_disable_clients(struct radeon_device *rdev);
void rs600_disable_vga(struct radeon_device *rdev);
@@ -126,9 +124,6 @@ int rv515_mc_init(struct radeon_device *rdev)
void rv515_mc_fini(struct radeon_device *rdev)
{
- rv370_pcie_gart_disable(rdev);
- radeon_gart_table_vram_free(rdev);
- radeon_gart_fini(rdev);
}
@@ -464,301 +459,244 @@ int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
#endif
}
-
/*
* Asic initialization
*/
-static const unsigned r500_reg_safe_bm[219] = {
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
- 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
- 0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF,
- 0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF,
- 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
- 0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x0003FC01, 0x3FFFFCF8, 0xFF800B19, 0xFFDFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-};
-
int rv515_init(struct radeon_device *rdev)
{
- rdev->config.r300.reg_safe_bm = r500_reg_safe_bm;
- rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm);
+ rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
+ rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
return 0;
}
-void atom_rv515_force_tv_scaler(struct radeon_device *rdev)
+void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
{
-
- WREG32(0x659C, 0x0);
- WREG32(0x6594, 0x705);
- WREG32(0x65A4, 0x10001);
- WREG32(0x65D8, 0x0);
- WREG32(0x65B0, 0x0);
- WREG32(0x65C0, 0x0);
- WREG32(0x65D4, 0x0);
- WREG32(0x6578, 0x0);
- WREG32(0x657C, 0x841880A8);
- WREG32(0x6578, 0x1);
- WREG32(0x657C, 0x84208680);
- WREG32(0x6578, 0x2);
- WREG32(0x657C, 0xBFF880B0);
- WREG32(0x6578, 0x100);
- WREG32(0x657C, 0x83D88088);
- WREG32(0x6578, 0x101);
- WREG32(0x657C, 0x84608680);
- WREG32(0x6578, 0x102);
- WREG32(0x657C, 0xBFF080D0);
- WREG32(0x6578, 0x200);
- WREG32(0x657C, 0x83988068);
- WREG32(0x6578, 0x201);
- WREG32(0x657C, 0x84A08680);
- WREG32(0x6578, 0x202);
- WREG32(0x657C, 0xBFF080F8);
- WREG32(0x6578, 0x300);
- WREG32(0x657C, 0x83588058);
- WREG32(0x6578, 0x301);
- WREG32(0x657C, 0x84E08660);
- WREG32(0x6578, 0x302);
- WREG32(0x657C, 0xBFF88120);
- WREG32(0x6578, 0x400);
- WREG32(0x657C, 0x83188040);
- WREG32(0x6578, 0x401);
- WREG32(0x657C, 0x85008660);
- WREG32(0x6578, 0x402);
- WREG32(0x657C, 0xBFF88150);
- WREG32(0x6578, 0x500);
- WREG32(0x657C, 0x82D88030);
- WREG32(0x6578, 0x501);
- WREG32(0x657C, 0x85408640);
- WREG32(0x6578, 0x502);
- WREG32(0x657C, 0xBFF88180);
- WREG32(0x6578, 0x600);
- WREG32(0x657C, 0x82A08018);
- WREG32(0x6578, 0x601);
- WREG32(0x657C, 0x85808620);
- WREG32(0x6578, 0x602);
- WREG32(0x657C, 0xBFF081B8);
- WREG32(0x6578, 0x700);
- WREG32(0x657C, 0x82608010);
- WREG32(0x6578, 0x701);
- WREG32(0x657C, 0x85A08600);
- WREG32(0x6578, 0x702);
- WREG32(0x657C, 0x800081F0);
- WREG32(0x6578, 0x800);
- WREG32(0x657C, 0x8228BFF8);
- WREG32(0x6578, 0x801);
- WREG32(0x657C, 0x85E085E0);
- WREG32(0x6578, 0x802);
- WREG32(0x657C, 0xBFF88228);
- WREG32(0x6578, 0x10000);
- WREG32(0x657C, 0x82A8BF00);
- WREG32(0x6578, 0x10001);
- WREG32(0x657C, 0x82A08CC0);
- WREG32(0x6578, 0x10002);
- WREG32(0x657C, 0x8008BEF8);
- WREG32(0x6578, 0x10100);
- WREG32(0x657C, 0x81F0BF28);
- WREG32(0x6578, 0x10101);
- WREG32(0x657C, 0x83608CA0);
- WREG32(0x6578, 0x10102);
- WREG32(0x657C, 0x8018BED0);
- WREG32(0x6578, 0x10200);
- WREG32(0x657C, 0x8148BF38);
- WREG32(0x6578, 0x10201);
- WREG32(0x657C, 0x84408C80);
- WREG32(0x6578, 0x10202);
- WREG32(0x657C, 0x8008BEB8);
- WREG32(0x6578, 0x10300);
- WREG32(0x657C, 0x80B0BF78);
- WREG32(0x6578, 0x10301);
- WREG32(0x657C, 0x85008C20);
- WREG32(0x6578, 0x10302);
- WREG32(0x657C, 0x8020BEA0);
- WREG32(0x6578, 0x10400);
- WREG32(0x657C, 0x8028BF90);
- WREG32(0x6578, 0x10401);
- WREG32(0x657C, 0x85E08BC0);
- WREG32(0x6578, 0x10402);
- WREG32(0x657C, 0x8018BE90);
- WREG32(0x6578, 0x10500);
- WREG32(0x657C, 0xBFB8BFB0);
- WREG32(0x6578, 0x10501);
- WREG32(0x657C, 0x86C08B40);
- WREG32(0x6578, 0x10502);
- WREG32(0x657C, 0x8010BE90);
- WREG32(0x6578, 0x10600);
- WREG32(0x657C, 0xBF58BFC8);
- WREG32(0x6578, 0x10601);
- WREG32(0x657C, 0x87A08AA0);
- WREG32(0x6578, 0x10602);
- WREG32(0x657C, 0x8010BE98);
- WREG32(0x6578, 0x10700);
- WREG32(0x657C, 0xBF10BFF0);
- WREG32(0x6578, 0x10701);
- WREG32(0x657C, 0x886089E0);
- WREG32(0x6578, 0x10702);
- WREG32(0x657C, 0x8018BEB0);
- WREG32(0x6578, 0x10800);
- WREG32(0x657C, 0xBED8BFE8);
- WREG32(0x6578, 0x10801);
- WREG32(0x657C, 0x89408940);
- WREG32(0x6578, 0x10802);
- WREG32(0x657C, 0xBFE8BED8);
- WREG32(0x6578, 0x20000);
- WREG32(0x657C, 0x80008000);
- WREG32(0x6578, 0x20001);
- WREG32(0x657C, 0x90008000);
- WREG32(0x6578, 0x20002);
- WREG32(0x657C, 0x80008000);
- WREG32(0x6578, 0x20003);
- WREG32(0x657C, 0x80008000);
- WREG32(0x6578, 0x20100);
- WREG32(0x657C, 0x80108000);
- WREG32(0x6578, 0x20101);
- WREG32(0x657C, 0x8FE0BF70);
- WREG32(0x6578, 0x20102);
- WREG32(0x657C, 0xBFE880C0);
- WREG32(0x6578, 0x20103);
- WREG32(0x657C, 0x80008000);
- WREG32(0x6578, 0x20200);
- WREG32(0x657C, 0x8018BFF8);
- WREG32(0x6578, 0x20201);
- WREG32(0x657C, 0x8F80BF08);
- WREG32(0x6578, 0x20202);
- WREG32(0x657C, 0xBFD081A0);
- WREG32(0x6578, 0x20203);
- WREG32(0x657C, 0xBFF88000);
- WREG32(0x6578, 0x20300);
- WREG32(0x657C, 0x80188000);
- WREG32(0x6578, 0x20301);
- WREG32(0x657C, 0x8EE0BEC0);
- WREG32(0x6578, 0x20302);
- WREG32(0x657C, 0xBFB082A0);
- WREG32(0x6578, 0x20303);
- WREG32(0x657C, 0x80008000);
- WREG32(0x6578, 0x20400);
- WREG32(0x657C, 0x80188000);
- WREG32(0x6578, 0x20401);
- WREG32(0x657C, 0x8E00BEA0);
- WREG32(0x6578, 0x20402);
- WREG32(0x657C, 0xBF8883C0);
- WREG32(0x6578, 0x20403);
- WREG32(0x657C, 0x80008000);
- WREG32(0x6578, 0x20500);
- WREG32(0x657C, 0x80188000);
- WREG32(0x6578, 0x20501);
- WREG32(0x657C, 0x8D00BE90);
- WREG32(0x6578, 0x20502);
- WREG32(0x657C, 0xBF588500);
- WREG32(0x6578, 0x20503);
- WREG32(0x657C, 0x80008008);
- WREG32(0x6578, 0x20600);
- WREG32(0x657C, 0x80188000);
- WREG32(0x6578, 0x20601);
- WREG32(0x657C, 0x8BC0BE98);
- WREG32(0x6578, 0x20602);
- WREG32(0x657C, 0xBF308660);
- WREG32(0x6578, 0x20603);
- WREG32(0x657C, 0x80008008);
- WREG32(0x6578, 0x20700);
- WREG32(0x657C, 0x80108000);
- WREG32(0x6578, 0x20701);
- WREG32(0x657C, 0x8A80BEB0);
- WREG32(0x6578, 0x20702);
- WREG32(0x657C, 0xBF0087C0);
- WREG32(0x6578, 0x20703);
- WREG32(0x657C, 0x80008008);
- WREG32(0x6578, 0x20800);
- WREG32(0x657C, 0x80108000);
- WREG32(0x6578, 0x20801);
- WREG32(0x657C, 0x8920BED0);
- WREG32(0x6578, 0x20802);
- WREG32(0x657C, 0xBED08920);
- WREG32(0x6578, 0x20803);
- WREG32(0x657C, 0x80008010);
- WREG32(0x6578, 0x30000);
- WREG32(0x657C, 0x90008000);
- WREG32(0x6578, 0x30001);
- WREG32(0x657C, 0x80008000);
- WREG32(0x6578, 0x30100);
- WREG32(0x657C, 0x8FE0BF90);
- WREG32(0x6578, 0x30101);
- WREG32(0x657C, 0xBFF880A0);
- WREG32(0x6578, 0x30200);
- WREG32(0x657C, 0x8F60BF40);
- WREG32(0x6578, 0x30201);
- WREG32(0x657C, 0xBFE88180);
- WREG32(0x6578, 0x30300);
- WREG32(0x657C, 0x8EC0BF00);
- WREG32(0x6578, 0x30301);
- WREG32(0x657C, 0xBFC88280);
- WREG32(0x6578, 0x30400);
- WREG32(0x657C, 0x8DE0BEE0);
- WREG32(0x6578, 0x30401);
- WREG32(0x657C, 0xBFA083A0);
- WREG32(0x6578, 0x30500);
- WREG32(0x657C, 0x8CE0BED0);
- WREG32(0x6578, 0x30501);
- WREG32(0x657C, 0xBF7884E0);
- WREG32(0x6578, 0x30600);
- WREG32(0x657C, 0x8BA0BED8);
- WREG32(0x6578, 0x30601);
- WREG32(0x657C, 0xBF508640);
- WREG32(0x6578, 0x30700);
- WREG32(0x657C, 0x8A60BEE8);
- WREG32(0x6578, 0x30701);
- WREG32(0x657C, 0xBF2087A0);
- WREG32(0x6578, 0x30800);
- WREG32(0x657C, 0x8900BF00);
- WREG32(0x6578, 0x30801);
- WREG32(0x657C, 0xBF008900);
+ int index_reg = 0x6578 + crtc->crtc_offset;
+ int data_reg = 0x657c + crtc->crtc_offset;
+
+ WREG32(0x659C + crtc->crtc_offset, 0x0);
+ WREG32(0x6594 + crtc->crtc_offset, 0x705);
+ WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
+ WREG32(0x65D8 + crtc->crtc_offset, 0x0);
+ WREG32(0x65B0 + crtc->crtc_offset, 0x0);
+ WREG32(0x65C0 + crtc->crtc_offset, 0x0);
+ WREG32(0x65D4 + crtc->crtc_offset, 0x0);
+ WREG32(index_reg, 0x0);
+ WREG32(data_reg, 0x841880A8);
+ WREG32(index_reg, 0x1);
+ WREG32(data_reg, 0x84208680);
+ WREG32(index_reg, 0x2);
+ WREG32(data_reg, 0xBFF880B0);
+ WREG32(index_reg, 0x100);
+ WREG32(data_reg, 0x83D88088);
+ WREG32(index_reg, 0x101);
+ WREG32(data_reg, 0x84608680);
+ WREG32(index_reg, 0x102);
+ WREG32(data_reg, 0xBFF080D0);
+ WREG32(index_reg, 0x200);
+ WREG32(data_reg, 0x83988068);
+ WREG32(index_reg, 0x201);
+ WREG32(data_reg, 0x84A08680);
+ WREG32(index_reg, 0x202);
+ WREG32(data_reg, 0xBFF080F8);
+ WREG32(index_reg, 0x300);
+ WREG32(data_reg, 0x83588058);
+ WREG32(index_reg, 0x301);
+ WREG32(data_reg, 0x84E08660);
+ WREG32(index_reg, 0x302);
+ WREG32(data_reg, 0xBFF88120);
+ WREG32(index_reg, 0x400);
+ WREG32(data_reg, 0x83188040);
+ WREG32(index_reg, 0x401);
+ WREG32(data_reg, 0x85008660);
+ WREG32(index_reg, 0x402);
+ WREG32(data_reg, 0xBFF88150);
+ WREG32(index_reg, 0x500);
+ WREG32(data_reg, 0x82D88030);
+ WREG32(index_reg, 0x501);
+ WREG32(data_reg, 0x85408640);
+ WREG32(index_reg, 0x502);
+ WREG32(data_reg, 0xBFF88180);
+ WREG32(index_reg, 0x600);
+ WREG32(data_reg, 0x82A08018);
+ WREG32(index_reg, 0x601);
+ WREG32(data_reg, 0x85808620);
+ WREG32(index_reg, 0x602);
+ WREG32(data_reg, 0xBFF081B8);
+ WREG32(index_reg, 0x700);
+ WREG32(data_reg, 0x82608010);
+ WREG32(index_reg, 0x701);
+ WREG32(data_reg, 0x85A08600);
+ WREG32(index_reg, 0x702);
+ WREG32(data_reg, 0x800081F0);
+ WREG32(index_reg, 0x800);
+ WREG32(data_reg, 0x8228BFF8);
+ WREG32(index_reg, 0x801);
+ WREG32(data_reg, 0x85E085E0);
+ WREG32(index_reg, 0x802);
+ WREG32(data_reg, 0xBFF88228);
+ WREG32(index_reg, 0x10000);
+ WREG32(data_reg, 0x82A8BF00);
+ WREG32(index_reg, 0x10001);
+ WREG32(data_reg, 0x82A08CC0);
+ WREG32(index_reg, 0x10002);
+ WREG32(data_reg, 0x8008BEF8);
+ WREG32(index_reg, 0x10100);
+ WREG32(data_reg, 0x81F0BF28);
+ WREG32(index_reg, 0x10101);
+ WREG32(data_reg, 0x83608CA0);
+ WREG32(index_reg, 0x10102);
+ WREG32(data_reg, 0x8018BED0);
+ WREG32(index_reg, 0x10200);
+ WREG32(data_reg, 0x8148BF38);
+ WREG32(index_reg, 0x10201);
+ WREG32(data_reg, 0x84408C80);
+ WREG32(index_reg, 0x10202);
+ WREG32(data_reg, 0x8008BEB8);
+ WREG32(index_reg, 0x10300);
+ WREG32(data_reg, 0x80B0BF78);
+ WREG32(index_reg, 0x10301);
+ WREG32(data_reg, 0x85008C20);
+ WREG32(index_reg, 0x10302);
+ WREG32(data_reg, 0x8020BEA0);
+ WREG32(index_reg, 0x10400);
+ WREG32(data_reg, 0x8028BF90);
+ WREG32(index_reg, 0x10401);
+ WREG32(data_reg, 0x85E08BC0);
+ WREG32(index_reg, 0x10402);
+ WREG32(data_reg, 0x8018BE90);
+ WREG32(index_reg, 0x10500);
+ WREG32(data_reg, 0xBFB8BFB0);
+ WREG32(index_reg, 0x10501);
+ WREG32(data_reg, 0x86C08B40);
+ WREG32(index_reg, 0x10502);
+ WREG32(data_reg, 0x8010BE90);
+ WREG32(index_reg, 0x10600);
+ WREG32(data_reg, 0xBF58BFC8);
+ WREG32(index_reg, 0x10601);
+ WREG32(data_reg, 0x87A08AA0);
+ WREG32(index_reg, 0x10602);
+ WREG32(data_reg, 0x8010BE98);
+ WREG32(index_reg, 0x10700);
+ WREG32(data_reg, 0xBF10BFF0);
+ WREG32(index_reg, 0x10701);
+ WREG32(data_reg, 0x886089E0);
+ WREG32(index_reg, 0x10702);
+ WREG32(data_reg, 0x8018BEB0);
+ WREG32(index_reg, 0x10800);
+ WREG32(data_reg, 0xBED8BFE8);
+ WREG32(index_reg, 0x10801);
+ WREG32(data_reg, 0x89408940);
+ WREG32(index_reg, 0x10802);
+ WREG32(data_reg, 0xBFE8BED8);
+ WREG32(index_reg, 0x20000);
+ WREG32(data_reg, 0x80008000);
+ WREG32(index_reg, 0x20001);
+ WREG32(data_reg, 0x90008000);
+ WREG32(index_reg, 0x20002);
+ WREG32(data_reg, 0x80008000);
+ WREG32(index_reg, 0x20003);
+ WREG32(data_reg, 0x80008000);
+ WREG32(index_reg, 0x20100);
+ WREG32(data_reg, 0x80108000);
+ WREG32(index_reg, 0x20101);
+ WREG32(data_reg, 0x8FE0BF70);
+ WREG32(index_reg, 0x20102);
+ WREG32(data_reg, 0xBFE880C0);
+ WREG32(index_reg, 0x20103);
+ WREG32(data_reg, 0x80008000);
+ WREG32(index_reg, 0x20200);
+ WREG32(data_reg, 0x8018BFF8);
+ WREG32(index_reg, 0x20201);
+ WREG32(data_reg, 0x8F80BF08);
+ WREG32(index_reg, 0x20202);
+ WREG32(data_reg, 0xBFD081A0);
+ WREG32(index_reg, 0x20203);
+ WREG32(data_reg, 0xBFF88000);
+ WREG32(index_reg, 0x20300);
+ WREG32(data_reg, 0x80188000);
+ WREG32(index_reg, 0x20301);
+ WREG32(data_reg, 0x8EE0BEC0);
+ WREG32(index_reg, 0x20302);
+ WREG32(data_reg, 0xBFB082A0);
+ WREG32(index_reg, 0x20303);
+ WREG32(data_reg, 0x80008000);
+ WREG32(index_reg, 0x20400);
+ WREG32(data_reg, 0x80188000);
+ WREG32(index_reg, 0x20401);
+ WREG32(data_reg, 0x8E00BEA0);
+ WREG32(index_reg, 0x20402);
+ WREG32(data_reg, 0xBF8883C0);
+ WREG32(index_reg, 0x20403);
+ WREG32(data_reg, 0x80008000);
+ WREG32(index_reg, 0x20500);
+ WREG32(data_reg, 0x80188000);
+ WREG32(index_reg, 0x20501);
+ WREG32(data_reg, 0x8D00BE90);
+ WREG32(index_reg, 0x20502);
+ WREG32(data_reg, 0xBF588500);
+ WREG32(index_reg, 0x20503);
+ WREG32(data_reg, 0x80008008);
+ WREG32(index_reg, 0x20600);
+ WREG32(data_reg, 0x80188000);
+ WREG32(index_reg, 0x20601);
+ WREG32(data_reg, 0x8BC0BE98);
+ WREG32(index_reg, 0x20602);
+ WREG32(data_reg, 0xBF308660);
+ WREG32(index_reg, 0x20603);
+ WREG32(data_reg, 0x80008008);
+ WREG32(index_reg, 0x20700);
+ WREG32(data_reg, 0x80108000);
+ WREG32(index_reg, 0x20701);
+ WREG32(data_reg, 0x8A80BEB0);
+ WREG32(index_reg, 0x20702);
+ WREG32(data_reg, 0xBF0087C0);
+ WREG32(index_reg, 0x20703);
+ WREG32(data_reg, 0x80008008);
+ WREG32(index_reg, 0x20800);
+ WREG32(data_reg, 0x80108000);
+ WREG32(index_reg, 0x20801);
+ WREG32(data_reg, 0x8920BED0);
+ WREG32(index_reg, 0x20802);
+ WREG32(data_reg, 0xBED08920);
+ WREG32(index_reg, 0x20803);
+ WREG32(data_reg, 0x80008010);
+ WREG32(index_reg, 0x30000);
+ WREG32(data_reg, 0x90008000);
+ WREG32(index_reg, 0x30001);
+ WREG32(data_reg, 0x80008000);
+ WREG32(index_reg, 0x30100);
+ WREG32(data_reg, 0x8FE0BF90);
+ WREG32(index_reg, 0x30101);
+ WREG32(data_reg, 0xBFF880A0);
+ WREG32(index_reg, 0x30200);
+ WREG32(data_reg, 0x8F60BF40);
+ WREG32(index_reg, 0x30201);
+ WREG32(data_reg, 0xBFE88180);
+ WREG32(index_reg, 0x30300);
+ WREG32(data_reg, 0x8EC0BF00);
+ WREG32(index_reg, 0x30301);
+ WREG32(data_reg, 0xBFC88280);
+ WREG32(index_reg, 0x30400);
+ WREG32(data_reg, 0x8DE0BEE0);
+ WREG32(index_reg, 0x30401);
+ WREG32(data_reg, 0xBFA083A0);
+ WREG32(index_reg, 0x30500);
+ WREG32(data_reg, 0x8CE0BED0);
+ WREG32(index_reg, 0x30501);
+ WREG32(data_reg, 0xBF7884E0);
+ WREG32(index_reg, 0x30600);
+ WREG32(data_reg, 0x8BA0BED8);
+ WREG32(index_reg, 0x30601);
+ WREG32(data_reg, 0xBF508640);
+ WREG32(index_reg, 0x30700);
+ WREG32(data_reg, 0x8A60BEE8);
+ WREG32(index_reg, 0x30701);
+ WREG32(data_reg, 0xBF2087A0);
+ WREG32(index_reg, 0x30800);
+ WREG32(data_reg, 0x8900BF00);
+ WREG32(index_reg, 0x30801);
+ WREG32(data_reg, 0xBF008900);
}
struct rv515_watermark {
diff --git a/drivers/gpu/drm/radeon/rv515r.h b/drivers/gpu/drm/radeon/rv515d.h
index f3cf840..a65e17e 100644
--- a/drivers/gpu/drm/radeon/rv515r.h
+++ b/drivers/gpu/drm/radeon/rv515d.h
@@ -25,10 +25,12 @@
* Alex Deucher
* Jerome Glisse
*/
-#ifndef RV515R_H
-#define RV515R_H
+#ifndef __RV515D_H__
+#define __RV515D_H__
-/* RV515 registers */
+/*
+ * RV515 registers
+ */
#define PCIE_INDEX 0x0030
#define PCIE_DATA 0x0034
#define MC_IND_INDEX 0x0070
@@ -166,5 +168,53 @@
#define MC_GLOBW_INIT_LAT_MASK 0xF0000000
+/*
+ * PM4 packet
+ */
+#define CP_PACKET0 0x00000000
+#define PACKET0_BASE_INDEX_SHIFT 0
+#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
+#define PACKET0_COUNT_SHIFT 16
+#define PACKET0_COUNT_MASK (0x3fff << 16)
+#define CP_PACKET1 0x40000000
+#define CP_PACKET2 0x80000000
+#define PACKET2_PAD_SHIFT 0
+#define PACKET2_PAD_MASK (0x3fffffff << 0)
+#define CP_PACKET3 0xC0000000
+#define PACKET3_IT_OPCODE_SHIFT 8
+#define PACKET3_IT_OPCODE_MASK (0xff << 8)
+#define PACKET3_COUNT_SHIFT 16
+#define PACKET3_COUNT_MASK (0x3fff << 16)
+/* PACKET3 op code */
+#define PACKET3_NOP 0x10
+#define PACKET3_3D_DRAW_VBUF 0x28
+#define PACKET3_3D_DRAW_IMMD 0x29
+#define PACKET3_3D_DRAW_INDX 0x2A
+#define PACKET3_3D_LOAD_VBPNTR 0x2F
+#define PACKET3_INDX_BUFFER 0x33
+#define PACKET3_3D_DRAW_VBUF_2 0x34
+#define PACKET3_3D_DRAW_IMMD_2 0x35
+#define PACKET3_3D_DRAW_INDX_2 0x36
+#define PACKET3_BITBLT_MULTI 0x9B
+
+#define PACKET0(reg, n) (CP_PACKET0 | \
+ REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
+ REG_SET(PACKET0_COUNT, (n)))
+#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
+#define PACKET3(op, n) (CP_PACKET3 | \
+ REG_SET(PACKET3_IT_OPCODE, (op)) | \
+ REG_SET(PACKET3_COUNT, (n)))
+
+#define PACKET_TYPE0 0
+#define PACKET_TYPE1 1
+#define PACKET_TYPE2 2
+#define PACKET_TYPE3 3
+
+#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
+#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
+#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
+#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
+#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
+
#endif
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 21d8ffd..b574c73 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -25,100 +25,1038 @@
* Alex Deucher
* Jerome Glisse
*/
+#include <linux/firmware.h>
+#include <linux/platform_device.h>
#include "drmP.h"
-#include "radeon_reg.h"
#include "radeon.h"
+#include "radeon_drm.h"
+#include "rv770d.h"
+#include "avivod.h"
+#include "atom.h"
-/* rv770,rv730,rv710 depends on : */
-void rs600_mc_disable_clients(struct radeon_device *rdev);
+#define R700_PFP_UCODE_SIZE 848
+#define R700_PM4_UCODE_SIZE 1360
-/* This files gather functions specifics to:
- * rv770,rv730,rv710
- *
- * Some of these functions might be used by newer ASICs.
- */
-int rv770_mc_wait_for_idle(struct radeon_device *rdev);
-void rv770_gpu_init(struct radeon_device *rdev);
+static void rv770_gpu_init(struct radeon_device *rdev);
+void rv770_fini(struct radeon_device *rdev);
/*
- * MC
+ * GART
*/
-int rv770_mc_init(struct radeon_device *rdev)
+int rv770_pcie_gart_enable(struct radeon_device *rdev)
{
- uint32_t tmp;
+ u32 tmp;
+ int r, i;
- rv770_gpu_init(rdev);
+ if (rdev->gart.table.vram.robj == NULL) {
+ dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
+ return -EINVAL;
+ }
+ r = radeon_gart_table_vram_pin(rdev);
+ if (r)
+ return r;
+ /* Setup L2 cache */
+ WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
+ ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
+ EFFECTIVE_L2_QUEUE_SIZE(7));
+ WREG32(VM_L2_CNTL2, 0);
+ WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
+ /* Setup TLB control */
+ tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
+ SYSTEM_ACCESS_MODE_NOT_IN_SYS |
+ SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
+ EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
+ WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
+ WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
+ WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
+ WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
+ WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
+ WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
+ WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
+ WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
+ WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+ (u32)(rdev->dummy_page.addr >> 12));
+ for (i = 1; i < 7; i++)
+ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
- /* setup the gart before changing location so we can ask to
- * discard unmapped mc request
- */
- /* FIXME: disable out of gart access */
- tmp = rdev->mc.gtt_location / 4096;
- tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp);
- WREG32(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp);
- tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096;
- tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp);
- WREG32(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp);
-
- rs600_mc_disable_clients(rdev);
- if (rv770_mc_wait_for_idle(rdev)) {
- printk(KERN_WARNING "Failed to wait MC idle while "
- "programming pipes. Bad things might happen.\n");
- }
-
- tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
- tmp = REG_SET(R700_MC_FB_TOP, tmp >> 24);
- tmp |= REG_SET(R700_MC_FB_BASE, rdev->mc.vram_location >> 24);
- WREG32(R700_MC_VM_FB_LOCATION, tmp);
- tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
- tmp = REG_SET(R700_MC_AGP_TOP, tmp >> 22);
- WREG32(R700_MC_VM_AGP_TOP, tmp);
- tmp = REG_SET(R700_MC_AGP_BOT, rdev->mc.gtt_location >> 22);
- WREG32(R700_MC_VM_AGP_BOT, tmp);
+ r600_pcie_gart_tlb_flush(rdev);
+ rdev->gart.ready = true;
return 0;
}
-void rv770_mc_fini(struct radeon_device *rdev)
+void rv770_pcie_gart_disable(struct radeon_device *rdev)
+{
+ u32 tmp;
+ int i;
+
+ /* Disable all tables */
+ for (i = 0; i < 7; i++)
+ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
+
+ /* Setup L2 cache */
+ WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
+ EFFECTIVE_L2_QUEUE_SIZE(7));
+ WREG32(VM_L2_CNTL2, 0);
+ WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
+ /* Setup TLB control */
+ tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
+ WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
+ WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
+ WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
+ WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
+ WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
+ WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
+ WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
+ if (rdev->gart.table.vram.robj) {
+ radeon_object_kunmap(rdev->gart.table.vram.robj);
+ radeon_object_unpin(rdev->gart.table.vram.robj);
+ }
+}
+
+void rv770_pcie_gart_fini(struct radeon_device *rdev)
{
- /* FIXME: implement */
+ rv770_pcie_gart_disable(rdev);
+ radeon_gart_table_vram_free(rdev);
+ radeon_gart_fini(rdev);
}
/*
- * Global GPU functions
+ * MC
*/
-void rv770_errata(struct radeon_device *rdev)
+static void rv770_mc_resume(struct radeon_device *rdev)
{
- rdev->pll_errata = 0;
+ u32 d1vga_control, d2vga_control;
+ u32 vga_render_control, vga_hdp_control;
+ u32 d1crtc_control, d2crtc_control;
+ u32 new_d1grph_primary, new_d1grph_secondary;
+ u32 new_d2grph_primary, new_d2grph_secondary;
+ u64 old_vram_start;
+ u32 tmp;
+ int i, j;
+
+ /* Initialize HDP */
+ for (i = 0, j = 0; i < 32; i++, j += 0x18) {
+ WREG32((0x2c14 + j), 0x00000000);
+ WREG32((0x2c18 + j), 0x00000000);
+ WREG32((0x2c1c + j), 0x00000000);
+ WREG32((0x2c20 + j), 0x00000000);
+ WREG32((0x2c24 + j), 0x00000000);
+ }
+ WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
+
+ d1vga_control = RREG32(D1VGA_CONTROL);
+ d2vga_control = RREG32(D2VGA_CONTROL);
+ vga_render_control = RREG32(VGA_RENDER_CONTROL);
+ vga_hdp_control = RREG32(VGA_HDP_CONTROL);
+ d1crtc_control = RREG32(D1CRTC_CONTROL);
+ d2crtc_control = RREG32(D2CRTC_CONTROL);
+ old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
+ new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
+ new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
+ new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
+ new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
+ new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
+ new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
+ new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
+ new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
+
+ /* Stop all video */
+ WREG32(D1VGA_CONTROL, 0);
+ WREG32(D2VGA_CONTROL, 0);
+ WREG32(VGA_RENDER_CONTROL, 0);
+ WREG32(D1CRTC_UPDATE_LOCK, 1);
+ WREG32(D2CRTC_UPDATE_LOCK, 1);
+ WREG32(D1CRTC_CONTROL, 0);
+ WREG32(D2CRTC_CONTROL, 0);
+ WREG32(D1CRTC_UPDATE_LOCK, 0);
+ WREG32(D2CRTC_UPDATE_LOCK, 0);
+
+ mdelay(1);
+ if (r600_mc_wait_for_idle(rdev)) {
+ printk(KERN_WARNING "[drm] MC not idle !\n");
+ }
+
+ /* Lockout access through VGA aperture*/
+ WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
+
+ /* Update configuration */
+ WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
+ WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
+ WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
+ tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
+ tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
+ WREG32(MC_VM_FB_LOCATION, tmp);
+ WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
+ WREG32(HDP_NONSURFACE_INFO, (2 << 7));
+ WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
+ if (rdev->flags & RADEON_IS_AGP) {
+ WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
+ WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
+ WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
+ } else {
+ WREG32(MC_VM_AGP_BASE, 0);
+ WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
+ WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
+ }
+ WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
+ WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
+ WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
+ WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
+ WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
+
+ /* Unlock host access */
+ WREG32(VGA_HDP_CONTROL, vga_hdp_control);
+
+ mdelay(1);
+ if (r600_mc_wait_for_idle(rdev)) {
+ printk(KERN_WARNING "[drm] MC not idle !\n");
+ }
+
+ /* Restore video state */
+ WREG32(D1CRTC_UPDATE_LOCK, 1);
+ WREG32(D2CRTC_UPDATE_LOCK, 1);
+ WREG32(D1CRTC_CONTROL, d1crtc_control);
+ WREG32(D2CRTC_CONTROL, d2crtc_control);
+ WREG32(D1CRTC_UPDATE_LOCK, 0);
+ WREG32(D2CRTC_UPDATE_LOCK, 0);
+ WREG32(D1VGA_CONTROL, d1vga_control);
+ WREG32(D2VGA_CONTROL, d2vga_control);
+ WREG32(VGA_RENDER_CONTROL, vga_render_control);
+
+ /* we need to own VRAM, so turn off the VGA renderer here
+ * to stop it overwriting our objects */
+ radeon_avivo_vga_render_disable(rdev);
}
-int rv770_mc_wait_for_idle(struct radeon_device *rdev)
+
+/*
+ * CP.
+ */
+void r700_cp_stop(struct radeon_device *rdev)
{
- /* FIXME: implement */
- return 0;
+ WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
}
-void rv770_gpu_init(struct radeon_device *rdev)
+
+static int rv770_cp_load_microcode(struct radeon_device *rdev)
{
- /* FIXME: implement */
+ const __be32 *fw_data;
+ int i;
+
+ if (!rdev->me_fw || !rdev->pfp_fw)
+ return -EINVAL;
+
+ r700_cp_stop(rdev);
+ WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
+
+ /* Reset cp */
+ WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
+ RREG32(GRBM_SOFT_RESET);
+ mdelay(15);
+ WREG32(GRBM_SOFT_RESET, 0);
+
+ fw_data = (const __be32 *)rdev->pfp_fw->data;
+ WREG32(CP_PFP_UCODE_ADDR, 0);
+ for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
+ WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
+ WREG32(CP_PFP_UCODE_ADDR, 0);
+
+ fw_data = (const __be32 *)rdev->me_fw->data;
+ WREG32(CP_ME_RAM_WADDR, 0);
+ for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
+ WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
+
+ WREG32(CP_PFP_UCODE_ADDR, 0);
+ WREG32(CP_ME_RAM_WADDR, 0);
+ WREG32(CP_ME_RAM_RADDR, 0);
+ return 0;
}
/*
- * VRAM info
+ * Core functions
*/
-void rv770_vram_get_type(struct radeon_device *rdev)
+static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
+ u32 num_backends,
+ u32 backend_disable_mask)
+{
+ u32 backend_map = 0;
+ u32 enabled_backends_mask;
+ u32 enabled_backends_count;
+ u32 cur_pipe;
+ u32 swizzle_pipe[R7XX_MAX_PIPES];
+ u32 cur_backend;
+ u32 i;
+
+ if (num_tile_pipes > R7XX_MAX_PIPES)
+ num_tile_pipes = R7XX_MAX_PIPES;
+ if (num_tile_pipes < 1)
+ num_tile_pipes = 1;
+ if (num_backends > R7XX_MAX_BACKENDS)
+ num_backends = R7XX_MAX_BACKENDS;
+ if (num_backends < 1)
+ num_backends = 1;
+
+ enabled_backends_mask = 0;
+ enabled_backends_count = 0;
+ for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
+ if (((backend_disable_mask >> i) & 1) == 0) {
+ enabled_backends_mask |= (1 << i);
+ ++enabled_backends_count;
+ }
+ if (enabled_backends_count == num_backends)
+ break;
+ }
+
+ if (enabled_backends_count == 0) {
+ enabled_backends_mask = 1;
+ enabled_backends_count = 1;
+ }
+
+ if (enabled_backends_count != num_backends)
+ num_backends = enabled_backends_count;
+
+ memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
+ switch (num_tile_pipes) {
+ case 1:
+ swizzle_pipe[0] = 0;
+ break;
+ case 2:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 1;
+ break;
+ case 3:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 2;
+ swizzle_pipe[2] = 1;
+ break;
+ case 4:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 2;
+ swizzle_pipe[2] = 3;
+ swizzle_pipe[3] = 1;
+ break;
+ case 5:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 2;
+ swizzle_pipe[2] = 4;
+ swizzle_pipe[3] = 1;
+ swizzle_pipe[4] = 3;
+ break;
+ case 6:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 2;
+ swizzle_pipe[2] = 4;
+ swizzle_pipe[3] = 5;
+ swizzle_pipe[4] = 3;
+ swizzle_pipe[5] = 1;
+ break;
+ case 7:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 2;
+ swizzle_pipe[2] = 4;
+ swizzle_pipe[3] = 6;
+ swizzle_pipe[4] = 3;
+ swizzle_pipe[5] = 1;
+ swizzle_pipe[6] = 5;
+ break;
+ case 8:
+ swizzle_pipe[0] = 0;
+ swizzle_pipe[1] = 2;
+ swizzle_pipe[2] = 4;
+ swizzle_pipe[3] = 6;
+ swizzle_pipe[4] = 3;
+ swizzle_pipe[5] = 1;
+ swizzle_pipe[6] = 7;
+ swizzle_pipe[7] = 5;
+ break;
+ }
+
+ cur_backend = 0;
+ for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
+ while (((1 << cur_backend) & enabled_backends_mask) == 0)
+ cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
+
+ backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
+
+ cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
+ }
+
+ return backend_map;
+}
+
+static void rv770_gpu_init(struct radeon_device *rdev)
{
- /* FIXME: implement */
+ int i, j, num_qd_pipes;
+ u32 sx_debug_1;
+ u32 smx_dc_ctl0;
+ u32 num_gs_verts_per_thread;
+ u32 vgt_gs_per_es;
+ u32 gs_prim_buffer_depth = 0;
+ u32 sq_ms_fifo_sizes;
+ u32 sq_config;
+ u32 sq_thread_resource_mgmt;
+ u32 hdp_host_path_cntl;
+ u32 sq_dyn_gpr_size_simd_ab_0;
+ u32 backend_map;
+ u32 gb_tiling_config = 0;
+ u32 cc_rb_backend_disable = 0;
+ u32 cc_gc_shader_pipe_config = 0;
+ u32 mc_arb_ramcfg;
+ u32 db_debug4;
+
+ /* setup chip specs */
+ switch (rdev->family) {
+ case CHIP_RV770:
+ rdev->config.rv770.max_pipes = 4;
+ rdev->config.rv770.max_tile_pipes = 8;
+ rdev->config.rv770.max_simds = 10;
+ rdev->config.rv770.max_backends = 4;
+ rdev->config.rv770.max_gprs = 256;
+ rdev->config.rv770.max_threads = 248;
+ rdev->config.rv770.max_stack_entries = 512;
+ rdev->config.rv770.max_hw_contexts = 8;
+ rdev->config.rv770.max_gs_threads = 16 * 2;
+ rdev->config.rv770.sx_max_export_size = 128;
+ rdev->config.rv770.sx_max_export_pos_size = 16;
+ rdev->config.rv770.sx_max_export_smx_size = 112;
+ rdev->config.rv770.sq_num_cf_insts = 2;
+
+ rdev->config.rv770.sx_num_of_sets = 7;
+ rdev->config.rv770.sc_prim_fifo_size = 0xF9;
+ rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
+ rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
+ break;
+ case CHIP_RV730:
+ rdev->config.rv770.max_pipes = 2;
+ rdev->config.rv770.max_tile_pipes = 4;
+ rdev->config.rv770.max_simds = 8;
+ rdev->config.rv770.max_backends = 2;
+ rdev->config.rv770.max_gprs = 128;
+ rdev->config.rv770.max_threads = 248;
+ rdev->config.rv770.max_stack_entries = 256;
+ rdev->config.rv770.max_hw_contexts = 8;
+ rdev->config.rv770.max_gs_threads = 16 * 2;
+ rdev->config.rv770.sx_max_export_size = 256;
+ rdev->config.rv770.sx_max_export_pos_size = 32;
+ rdev->config.rv770.sx_max_export_smx_size = 224;
+ rdev->config.rv770.sq_num_cf_insts = 2;
+
+ rdev->config.rv770.sx_num_of_sets = 7;
+ rdev->config.rv770.sc_prim_fifo_size = 0xf9;
+ rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
+ rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
+ if (rdev->config.rv770.sx_max_export_pos_size > 16) {
+ rdev->config.rv770.sx_max_export_pos_size -= 16;
+ rdev->config.rv770.sx_max_export_smx_size += 16;
+ }
+ break;
+ case CHIP_RV710:
+ rdev->config.rv770.max_pipes = 2;
+ rdev->config.rv770.max_tile_pipes = 2;
+ rdev->config.rv770.max_simds = 2;
+ rdev->config.rv770.max_backends = 1;
+ rdev->config.rv770.max_gprs = 256;
+ rdev->config.rv770.max_threads = 192;
+ rdev->config.rv770.max_stack_entries = 256;
+ rdev->config.rv770.max_hw_contexts = 4;
+ rdev->config.rv770.max_gs_threads = 8 * 2;
+ rdev->config.rv770.sx_max_export_size = 128;
+ rdev->config.rv770.sx_max_export_pos_size = 16;
+ rdev->config.rv770.sx_max_export_smx_size = 112;
+ rdev->config.rv770.sq_num_cf_insts = 1;
+
+ rdev->config.rv770.sx_num_of_sets = 7;
+ rdev->config.rv770.sc_prim_fifo_size = 0x40;
+ rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
+ rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
+ break;
+ case CHIP_RV740:
+ rdev->config.rv770.max_pipes = 4;
+ rdev->config.rv770.max_tile_pipes = 4;
+ rdev->config.rv770.max_simds = 8;
+ rdev->config.rv770.max_backends = 4;
+ rdev->config.rv770.max_gprs = 256;
+ rdev->config.rv770.max_threads = 248;
+ rdev->config.rv770.max_stack_entries = 512;
+ rdev->config.rv770.max_hw_contexts = 8;
+ rdev->config.rv770.max_gs_threads = 16 * 2;
+ rdev->config.rv770.sx_max_export_size = 256;
+ rdev->config.rv770.sx_max_export_pos_size = 32;
+ rdev->config.rv770.sx_max_export_smx_size = 224;
+ rdev->config.rv770.sq_num_cf_insts = 2;
+
+ rdev->config.rv770.sx_num_of_sets = 7;
+ rdev->config.rv770.sc_prim_fifo_size = 0x100;
+ rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
+ rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
+
+ if (rdev->config.rv770.sx_max_export_pos_size > 16) {
+ rdev->config.rv770.sx_max_export_pos_size -= 16;
+ rdev->config.rv770.sx_max_export_smx_size += 16;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Initialize HDP */
+ j = 0;
+ for (i = 0; i < 32; i++) {
+ WREG32((0x2c14 + j), 0x00000000);
+ WREG32((0x2c18 + j), 0x00000000);
+ WREG32((0x2c1c + j), 0x00000000);
+ WREG32((0x2c20 + j), 0x00000000);
+ WREG32((0x2c24 + j), 0x00000000);
+ j += 0x18;
+ }
+
+ WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+
+ /* setup tiling, simd, pipe config */
+ mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
+
+ switch (rdev->config.rv770.max_tile_pipes) {
+ case 1:
+ gb_tiling_config |= PIPE_TILING(0);
+ break;
+ case 2:
+ gb_tiling_config |= PIPE_TILING(1);
+ break;
+ case 4:
+ gb_tiling_config |= PIPE_TILING(2);
+ break;
+ case 8:
+ gb_tiling_config |= PIPE_TILING(3);
+ break;
+ default:
+ break;
+ }
+
+ if (rdev->family == CHIP_RV770)
+ gb_tiling_config |= BANK_TILING(1);
+ else
+ gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK);
+
+ gb_tiling_config |= GROUP_SIZE(0);
+
+ if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) {
+ gb_tiling_config |= ROW_TILING(3);
+ gb_tiling_config |= SAMPLE_SPLIT(3);
+ } else {
+ gb_tiling_config |=
+ ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
+ gb_tiling_config |=
+ SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
+ }
+
+ gb_tiling_config |= BANK_SWAPS(1);
+
+ backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
+ rdev->config.rv770.max_backends,
+ (0xff << rdev->config.rv770.max_backends) & 0xff);
+ gb_tiling_config |= BACKEND_MAP(backend_map);
+
+ cc_gc_shader_pipe_config =
+ INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
+ cc_gc_shader_pipe_config |=
+ INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
+
+ cc_rb_backend_disable =
+ BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
+
+ WREG32(GB_TILING_CONFIG, gb_tiling_config);
+ WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
+ WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
+
+ WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
+ WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
+ WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
+
+ WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
+ WREG32(CGTS_SYS_TCC_DISABLE, 0);
+ WREG32(CGTS_TCC_DISABLE, 0);
+ WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
+ WREG32(CGTS_USER_TCC_DISABLE, 0);
+
+ num_qd_pipes =
+ R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK);
+ WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
+ WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
+
+ /* set HW defaults for 3D engine */
+ WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
+ ROQ_IB2_START(0x2b)));
+
+ WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
+
+ WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
+ SYNC_GRADIENT |
+ SYNC_WALKER |
+ SYNC_ALIGNER));
+
+ sx_debug_1 = RREG32(SX_DEBUG_1);
+ sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
+ WREG32(SX_DEBUG_1, sx_debug_1);
+
+ smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
+ smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
+ smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
+ WREG32(SMX_DC_CTL0, smx_dc_ctl0);
+
+ WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
+ GS_FLUSH_CTL(4) |
+ ACK_FLUSH_CTL(3) |
+ SYNC_FLUSH_CTL));
+
+ if (rdev->family == CHIP_RV770)
+ WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
+ else {
+ db_debug4 = RREG32(DB_DEBUG4);
+ db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
+ WREG32(DB_DEBUG4, db_debug4);
+ }
+
+ WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
+ POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
+ SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
+
+ WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
+ SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
+ SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
+
+ WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
+
+ WREG32(VGT_NUM_INSTANCES, 1);
+
+ WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
+
+ WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
+
+ WREG32(CP_PERFMON_CNTL, 0);
+
+ sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
+ DONE_FIFO_HIWATER(0xe0) |
+ ALU_UPDATE_FIFO_HIWATER(0x8));
+ switch (rdev->family) {
+ case CHIP_RV770:
+ sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
+ break;
+ case CHIP_RV730:
+ case CHIP_RV710:
+ case CHIP_RV740:
+ default:
+ sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
+ break;
+ }
+ WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
+
+ /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
+ * should be adjusted as needed by the 2D/3D drivers. This just sets default values
+ */
+ sq_config = RREG32(SQ_CONFIG);
+ sq_config &= ~(PS_PRIO(3) |
+ VS_PRIO(3) |
+ GS_PRIO(3) |
+ ES_PRIO(3));
+ sq_config |= (DX9_CONSTS |
+ VC_ENABLE |
+ EXPORT_SRC_C |
+ PS_PRIO(0) |
+ VS_PRIO(1) |
+ GS_PRIO(2) |
+ ES_PRIO(3));
+ if (rdev->family == CHIP_RV710)
+ /* no vertex cache */
+ sq_config &= ~VC_ENABLE;
+
+ WREG32(SQ_CONFIG, sq_config);
+
+ WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
+ NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
+ NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
+
+ WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
+ NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
+
+ sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
+ NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
+ NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
+ if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
+ sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
+ else
+ sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
+ WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
+
+ WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
+ NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
+
+ WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
+ NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
+
+ sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
+ SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
+ SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
+ SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
+
+ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
+ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
+ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
+ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
+ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
+ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
+ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
+ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
+
+ WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
+ FORCE_EOV_MAX_REZ_CNT(255)));
+
+ if (rdev->family == CHIP_RV710)
+ WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
+ AUTO_INVLD_EN(ES_AND_GS_AUTO)));
+ else
+ WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
+ AUTO_INVLD_EN(ES_AND_GS_AUTO)));
+
+ switch (rdev->family) {
+ case CHIP_RV770:
+ case CHIP_RV730:
+ case CHIP_RV740:
+ gs_prim_buffer_depth = 384;
+ break;
+ case CHIP_RV710:
+ gs_prim_buffer_depth = 128;
+ break;
+ default:
+ break;
+ }
+
+ num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
+ vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
+ /* Max value for this is 256 */
+ if (vgt_gs_per_es > 256)
+ vgt_gs_per_es = 256;
+
+ WREG32(VGT_ES_PER_GS, 128);
+ WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
+ WREG32(VGT_GS_PER_VS, 2);
+
+ /* more default values. 2D/3D driver should adjust as needed */
+ WREG32(VGT_GS_VERTEX_REUSE, 16);
+ WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
+ WREG32(VGT_STRMOUT_EN, 0);
+ WREG32(SX_MISC, 0);
+ WREG32(PA_SC_MODE_CNTL, 0);
+ WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
+ WREG32(PA_SC_AA_CONFIG, 0);
+ WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
+ WREG32(PA_SC_LINE_STIPPLE, 0);
+ WREG32(SPI_INPUT_Z, 0);
+ WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
+ WREG32(CB_COLOR7_FRAG, 0);
+
+ /* clear render buffer base addresses */
+ WREG32(CB_COLOR0_BASE, 0);
+ WREG32(CB_COLOR1_BASE, 0);
+ WREG32(CB_COLOR2_BASE, 0);
+ WREG32(CB_COLOR3_BASE, 0);
+ WREG32(CB_COLOR4_BASE, 0);
+ WREG32(CB_COLOR5_BASE, 0);
+ WREG32(CB_COLOR6_BASE, 0);
+ WREG32(CB_COLOR7_BASE, 0);
+
+ WREG32(TCP_CNTL, 0);
+
+ hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
+ WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
+
+ WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
+
+ WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
+ NUM_CLIP_SEQ(3)));
+
}
-void rv770_vram_info(struct radeon_device *rdev)
+int rv770_mc_init(struct radeon_device *rdev)
{
- rv770_vram_get_type(rdev);
+ fixed20_12 a;
+ u32 tmp;
+ int r;
- /* FIXME: implement */
+ /* Get VRAM informations */
+ /* FIXME: Don't know how to determine vram width, need to check
+ * vram_width usage
+ */
+ rdev->mc.vram_width = 128;
+ rdev->mc.vram_is_ddr = true;
/* Could aper size report 0 ? */
rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+ /* Setup GPU memory space */
+ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
+ rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
+ if (rdev->flags & RADEON_IS_AGP) {
+ r = radeon_agp_init(rdev);
+ if (r)
+ return r;
+ /* gtt_size is setup by radeon_agp_init */
+ rdev->mc.gtt_location = rdev->mc.agp_base;
+ tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
+ /* Try to put vram before or after AGP because we
+ * we want SYSTEM_APERTURE to cover both VRAM and
+ * AGP so that GPU can catch out of VRAM/AGP access
+ */
+ if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
+ /* Enought place before */
+ rdev->mc.vram_location = rdev->mc.gtt_location -
+ rdev->mc.mc_vram_size;
+ } else if (tmp > rdev->mc.mc_vram_size) {
+ /* Enought place after */
+ rdev->mc.vram_location = rdev->mc.gtt_location +
+ rdev->mc.gtt_size;
+ } else {
+ /* Try to setup VRAM then AGP might not
+ * not work on some card
+ */
+ rdev->mc.vram_location = 0x00000000UL;
+ rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+ }
+ } else {
+ rdev->mc.vram_location = 0x00000000UL;
+ rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+ rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+ }
+ rdev->mc.vram_start = rdev->mc.vram_location;
+ rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
+ rdev->mc.gtt_start = rdev->mc.gtt_location;
+ rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
+ /* FIXME: we should enforce default clock in case GPU is not in
+ * default setup
+ */
+ a.full = rfixed_const(100);
+ rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
+ rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+ return 0;
+}
+int rv770_gpu_reset(struct radeon_device *rdev)
+{
+ /* FIXME: implement any rv770 specific bits */
+ return r600_gpu_reset(rdev);
+}
+
+static int rv770_startup(struct radeon_device *rdev)
+{
+ int r;
+
+ radeon_gpu_reset(rdev);
+ rv770_mc_resume(rdev);
+ r = rv770_pcie_gart_enable(rdev);
+ if (r)
+ return r;
+ rv770_gpu_init(rdev);
+
+ r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
+ &rdev->r600_blit.shader_gpu_addr);
+ if (r) {
+ DRM_ERROR("failed to pin blit object %d\n", r);
+ return r;
+ }
+
+ r = radeon_ring_init(rdev, rdev->cp.ring_size);
+ if (r)
+ return r;
+ r = rv770_cp_load_microcode(rdev);
+ if (r)
+ return r;
+ r = r600_cp_resume(rdev);
+ if (r)
+ return r;
+ r = r600_wb_init(rdev);
+ if (r)
+ return r;
+ return 0;
+}
+
+int rv770_resume(struct radeon_device *rdev)
+{
+ int r;
+
+ if (radeon_gpu_reset(rdev)) {
+ /* FIXME: what do we want to do here ? */
+ }
+ /* post card */
+ if (rdev->is_atom_bios) {
+ atom_asic_init(rdev->mode_info.atom_context);
+ } else {
+ radeon_combios_asic_init(rdev->ddev);
+ }
+ /* Initialize clocks */
+ r = radeon_clocks_init(rdev);
+ if (r) {
+ return r;
+ }
+
+ r = rv770_startup(rdev);
+ if (r) {
+ DRM_ERROR("r600 startup failed on resume\n");
+ return r;
+ }
+
+ r = radeon_ib_test(rdev);
+ if (r) {
+ DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+ return r;
+ }
+ return r;
+
+}
+
+int rv770_suspend(struct radeon_device *rdev)
+{
+ /* FIXME: we should wait for ring to be empty */
+ r700_cp_stop(rdev);
+ rdev->cp.ready = false;
+ rv770_pcie_gart_disable(rdev);
+
+ /* unpin shaders bo */
+ radeon_object_unpin(rdev->r600_blit.shader_obj);
+ return 0;
+}
+
+/* Plan is to move initialization in that function and use
+ * helper function so that radeon_device_init pretty much
+ * do nothing more than calling asic specific function. This
+ * should also allow to remove a bunch of callback function
+ * like vram_info.
+ */
+int rv770_init(struct radeon_device *rdev)
+{
+ int r;
+
+ rdev->new_init_path = true;
+ r = radeon_dummy_page_init(rdev);
+ if (r)
+ return r;
+ /* This don't do much */
+ r = radeon_gem_init(rdev);
+ if (r)
+ return r;
+ /* Read BIOS */
+ if (!radeon_get_bios(rdev)) {
+ if (ASIC_IS_AVIVO(rdev))
+ return -EINVAL;
+ }
+ /* Must be an ATOMBIOS */
+ if (!rdev->is_atom_bios)
+ return -EINVAL;
+ r = radeon_atombios_init(rdev);
+ if (r)
+ return r;
+ /* Post card if necessary */
+ if (!r600_card_posted(rdev) && rdev->bios) {
+ DRM_INFO("GPU not posted. posting now...\n");
+ atom_asic_init(rdev->mode_info.atom_context);
+ }
+ /* Initialize scratch registers */
+ r600_scratch_init(rdev);
+ /* Initialize surface registers */
+ radeon_surface_init(rdev);
+ radeon_get_clock_info(rdev->ddev);
+ r = radeon_clocks_init(rdev);
+ if (r)
+ return r;
+ /* Fence driver */
+ r = radeon_fence_driver_init(rdev);
+ if (r)
+ return r;
+ r = rv770_mc_init(rdev);
+ if (r) {
+ if (rdev->flags & RADEON_IS_AGP) {
+ /* Retry with disabling AGP */
+ rv770_fini(rdev);
+ rdev->flags &= ~RADEON_IS_AGP;
+ return rv770_init(rdev);
+ }
+ return r;
+ }
+ /* Memory manager */
+ r = radeon_object_init(rdev);
+ if (r)
+ return r;
+ rdev->cp.ring_obj = NULL;
+ r600_ring_init(rdev, 1024 * 1024);
+
+ if (!rdev->me_fw || !rdev->pfp_fw) {
+ r = r600_cp_init_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load firmware!\n");
+ return r;
+ }
+ }
+
+ r = r600_pcie_gart_init(rdev);
+ if (r)
+ return r;
+
+ rdev->accel_working = true;
+ r = r600_blit_init(rdev);
+ if (r) {
+ DRM_ERROR("radeon: failled blitter (%d).\n", r);
+ rdev->accel_working = false;
+ }
+
+ r = rv770_startup(rdev);
+ if (r) {
+ if (rdev->flags & RADEON_IS_AGP) {
+ /* Retry with disabling AGP */
+ rv770_fini(rdev);
+ rdev->flags &= ~RADEON_IS_AGP;
+ return rv770_init(rdev);
+ }
+ rdev->accel_working = false;
+ }
+ if (rdev->accel_working) {
+ r = radeon_ib_pool_init(rdev);
+ if (r) {
+ DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
+ rdev->accel_working = false;
+ }
+ r = radeon_ib_test(rdev);
+ if (r) {
+ DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+ rdev->accel_working = false;
+ }
+ }
+ return 0;
+}
+
+void rv770_fini(struct radeon_device *rdev)
+{
+ rv770_suspend(rdev);
+
+ r600_blit_fini(rdev);
+ radeon_ring_fini(rdev);
+ rv770_pcie_gart_fini(rdev);
+ radeon_gem_fini(rdev);
+ radeon_fence_driver_fini(rdev);
+ radeon_clocks_fini(rdev);
+#if __OS_HAS_AGP
+ if (rdev->flags & RADEON_IS_AGP)
+ radeon_agp_fini(rdev);
+#endif
+ radeon_object_fini(rdev);
+ if (rdev->is_atom_bios) {
+ radeon_atombios_fini(rdev);
+ } else {
+ radeon_combios_fini(rdev);
+ }
+ kfree(rdev->bios);
+ rdev->bios = NULL;
+ radeon_dummy_page_fini(rdev);
}
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
new file mode 100644
index 0000000..4b9c3d6
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -0,0 +1,341 @@
+/*
+ * Copyright 2009 Advanced Micro Devices, Inc.
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ * Alex Deucher
+ * Jerome Glisse
+ */
+#ifndef RV770_H
+#define RV770_H
+
+#define R7XX_MAX_SH_GPRS 256
+#define R7XX_MAX_TEMP_GPRS 16
+#define R7XX_MAX_SH_THREADS 256
+#define R7XX_MAX_SH_STACK_ENTRIES 4096
+#define R7XX_MAX_BACKENDS 8
+#define R7XX_MAX_BACKENDS_MASK 0xff
+#define R7XX_MAX_SIMDS 16
+#define R7XX_MAX_SIMDS_MASK 0xffff
+#define R7XX_MAX_PIPES 8
+#define R7XX_MAX_PIPES_MASK 0xff
+
+/* Registers */
+#define CB_COLOR0_BASE 0x28040
+#define CB_COLOR1_BASE 0x28044
+#define CB_COLOR2_BASE 0x28048
+#define CB_COLOR3_BASE 0x2804C
+#define CB_COLOR4_BASE 0x28050
+#define CB_COLOR5_BASE 0x28054
+#define CB_COLOR6_BASE 0x28058
+#define CB_COLOR7_BASE 0x2805C
+#define CB_COLOR7_FRAG 0x280FC
+
+#define CC_GC_SHADER_PIPE_CONFIG 0x8950
+#define CC_RB_BACKEND_DISABLE 0x98F4
+#define BACKEND_DISABLE(x) ((x) << 16)
+#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
+
+#define CGTS_SYS_TCC_DISABLE 0x3F90
+#define CGTS_TCC_DISABLE 0x9148
+#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
+#define CGTS_USER_TCC_DISABLE 0x914C
+
+#define CONFIG_MEMSIZE 0x5428
+
+#define CP_ME_CNTL 0x86D8
+#define CP_ME_HALT (1<<28)
+#define CP_PFP_HALT (1<<26)
+#define CP_ME_RAM_DATA 0xC160
+#define CP_ME_RAM_RADDR 0xC158
+#define CP_ME_RAM_WADDR 0xC15C
+#define CP_MEQ_THRESHOLDS 0x8764
+#define STQ_SPLIT(x) ((x) << 0)
+#define CP_PERFMON_CNTL 0x87FC
+#define CP_PFP_UCODE_ADDR 0xC150
+#define CP_PFP_UCODE_DATA 0xC154
+#define CP_QUEUE_THRESHOLDS 0x8760
+#define ROQ_IB1_START(x) ((x) << 0)
+#define ROQ_IB2_START(x) ((x) << 8)
+#define CP_RB_CNTL 0xC104
+#define RB_BUFSZ(x) ((x)<<0)
+#define RB_BLKSZ(x) ((x)<<8)
+#define RB_NO_UPDATE (1<<27)
+#define RB_RPTR_WR_ENA (1<<31)
+#define BUF_SWAP_32BIT (2 << 16)
+#define CP_RB_RPTR 0x8700
+#define CP_RB_RPTR_ADDR 0xC10C
+#define CP_RB_RPTR_ADDR_HI 0xC110
+#define CP_RB_RPTR_WR 0xC108
+#define CP_RB_WPTR 0xC114
+#define CP_RB_WPTR_ADDR 0xC118
+#define CP_RB_WPTR_ADDR_HI 0xC11C
+#define CP_RB_WPTR_DELAY 0x8704
+#define CP_SEM_WAIT_TIMER 0x85BC
+
+#define DB_DEBUG3 0x98B0
+#define DB_CLK_OFF_DELAY(x) ((x) << 11)
+#define DB_DEBUG4 0x9B8C
+#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
+
+#define DCP_TILING_CONFIG 0x6CA0
+#define PIPE_TILING(x) ((x) << 1)
+#define BANK_TILING(x) ((x) << 4)
+#define GROUP_SIZE(x) ((x) << 6)
+#define ROW_TILING(x) ((x) << 8)
+#define BANK_SWAPS(x) ((x) << 11)
+#define SAMPLE_SPLIT(x) ((x) << 14)
+#define BACKEND_MAP(x) ((x) << 16)
+
+#define GB_TILING_CONFIG 0x98F0
+
+#define GC_USER_SHADER_PIPE_CONFIG 0x8954
+#define INACTIVE_QD_PIPES(x) ((x) << 8)
+#define INACTIVE_QD_PIPES_MASK 0x0000FF00
+#define INACTIVE_SIMDS(x) ((x) << 16)
+#define INACTIVE_SIMDS_MASK 0x00FF0000
+
+#define GRBM_CNTL 0x8000
+#define GRBM_READ_TIMEOUT(x) ((x) << 0)
+#define GRBM_SOFT_RESET 0x8020
+#define SOFT_RESET_CP (1<<0)
+#define GRBM_STATUS 0x8010
+#define CMDFIFO_AVAIL_MASK 0x0000000F
+#define GUI_ACTIVE (1<<31)
+#define GRBM_STATUS2 0x8014
+
+#define HDP_HOST_PATH_CNTL 0x2C00
+#define HDP_NONSURFACE_BASE 0x2C04
+#define HDP_NONSURFACE_INFO 0x2C08
+#define HDP_NONSURFACE_SIZE 0x2C0C
+#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
+#define HDP_TILING_CONFIG 0x2F3C
+
+#define MC_ARB_RAMCFG 0x2760
+#define NOOFBANK_SHIFT 0
+#define NOOFBANK_MASK 0x00000003
+#define NOOFRANK_SHIFT 2
+#define NOOFRANK_MASK 0x00000004
+#define NOOFROWS_SHIFT 3
+#define NOOFROWS_MASK 0x00000038
+#define NOOFCOLS_SHIFT 6
+#define NOOFCOLS_MASK 0x000000C0
+#define CHANSIZE_SHIFT 8
+#define CHANSIZE_MASK 0x00000100
+#define BURSTLENGTH_SHIFT 9
+#define BURSTLENGTH_MASK 0x00000200
+#define MC_VM_AGP_TOP 0x2028
+#define MC_VM_AGP_BOT 0x202C
+#define MC_VM_AGP_BASE 0x2030
+#define MC_VM_FB_LOCATION 0x2024
+#define MC_VM_MB_L1_TLB0_CNTL 0x2234
+#define MC_VM_MB_L1_TLB1_CNTL 0x2238
+#define MC_VM_MB_L1_TLB2_CNTL 0x223C
+#define MC_VM_MB_L1_TLB3_CNTL 0x2240
+#define ENABLE_L1_TLB (1 << 0)
+#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
+#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
+#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
+#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
+#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
+#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
+#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
+#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
+#define MC_VM_MD_L1_TLB0_CNTL 0x2654
+#define MC_VM_MD_L1_TLB1_CNTL 0x2658
+#define MC_VM_MD_L1_TLB2_CNTL 0x265C
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
+
+#define PA_CL_ENHANCE 0x8A14
+#define CLIP_VTX_REORDER_ENA (1 << 0)
+#define NUM_CLIP_SEQ(x) ((x) << 1)
+#define PA_SC_AA_CONFIG 0x28C04
+#define PA_SC_CLIPRECT_RULE 0x2820C
+#define PA_SC_EDGERULE 0x28230
+#define PA_SC_FIFO_SIZE 0x8BCC
+#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
+#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
+#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
+#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0)
+#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16)
+#define PA_SC_LINE_STIPPLE 0x28A0C
+#define PA_SC_LINE_STIPPLE_STATE 0x8B10
+#define PA_SC_MODE_CNTL 0x28A4C
+#define PA_SC_MULTI_CHIP_CNTL 0x8B20
+#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
+
+#define SCRATCH_REG0 0x8500
+#define SCRATCH_REG1 0x8504
+#define SCRATCH_REG2 0x8508
+#define SCRATCH_REG3 0x850C
+#define SCRATCH_REG4 0x8510
+#define SCRATCH_REG5 0x8514
+#define SCRATCH_REG6 0x8518
+#define SCRATCH_REG7 0x851C
+#define SCRATCH_UMSK 0x8540
+#define SCRATCH_ADDR 0x8544
+
+#define SMX_DC_CTL0 0xA020
+#define USE_HASH_FUNCTION (1 << 0)
+#define CACHE_DEPTH(x) ((x) << 1)
+#define FLUSH_ALL_ON_EVENT (1 << 10)
+#define STALL_ON_EVENT (1 << 11)
+#define SMX_EVENT_CTL 0xA02C
+#define ES_FLUSH_CTL(x) ((x) << 0)
+#define GS_FLUSH_CTL(x) ((x) << 3)
+#define ACK_FLUSH_CTL(x) ((x) << 6)
+#define SYNC_FLUSH_CTL (1 << 8)
+
+#define SPI_CONFIG_CNTL 0x9100
+#define GPR_WRITE_PRIORITY(x) ((x) << 0)
+#define DISABLE_INTERP_1 (1 << 5)
+#define SPI_CONFIG_CNTL_1 0x913C
+#define VTX_DONE_DELAY(x) ((x) << 0)
+#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
+#define SPI_INPUT_Z 0x286D8
+#define SPI_PS_IN_CONTROL_0 0x286CC
+#define NUM_INTERP(x) ((x)<<0)
+#define POSITION_ENA (1<<8)
+#define POSITION_CENTROID (1<<9)
+#define POSITION_ADDR(x) ((x)<<10)
+#define PARAM_GEN(x) ((x)<<15)
+#define PARAM_GEN_ADDR(x) ((x)<<19)
+#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
+#define PERSP_GRADIENT_ENA (1<<28)
+#define LINEAR_GRADIENT_ENA (1<<29)
+#define POSITION_SAMPLE (1<<30)
+#define BARYC_AT_SAMPLE_ENA (1<<31)
+
+#define SQ_CONFIG 0x8C00
+#define VC_ENABLE (1 << 0)
+#define EXPORT_SRC_C (1 << 1)
+#define DX9_CONSTS (1 << 2)
+#define ALU_INST_PREFER_VECTOR (1 << 3)
+#define DX10_CLAMP (1 << 4)
+#define CLAUSE_SEQ_PRIO(x) ((x) << 8)
+#define PS_PRIO(x) ((x) << 24)
+#define VS_PRIO(x) ((x) << 26)
+#define GS_PRIO(x) ((x) << 28)
+#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0
+#define SIMDA_RING0(x) ((x)<<0)
+#define SIMDA_RING1(x) ((x)<<8)
+#define SIMDB_RING0(x) ((x)<<16)
+#define SIMDB_RING1(x) ((x)<<24)
+#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4
+#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8
+#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC
+#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0
+#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4
+#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8
+#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC
+#define ES_PRIO(x) ((x) << 30)
+#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
+#define NUM_PS_GPRS(x) ((x) << 0)
+#define NUM_VS_GPRS(x) ((x) << 16)
+#define DYN_GPR_ENABLE (1 << 27)
+#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
+#define SQ_GPR_RESOURCE_MGMT_2 0x8C08
+#define NUM_GS_GPRS(x) ((x) << 0)
+#define NUM_ES_GPRS(x) ((x) << 16)
+#define SQ_MS_FIFO_SIZES 0x8CF0
+#define CACHE_FIFO_SIZE(x) ((x) << 0)
+#define FETCH_FIFO_HIWATER(x) ((x) << 8)
+#define DONE_FIFO_HIWATER(x) ((x) << 16)
+#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
+#define SQ_STACK_RESOURCE_MGMT_1 0x8C10
+#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
+#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
+#define SQ_STACK_RESOURCE_MGMT_2 0x8C14
+#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
+#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
+#define SQ_THREAD_RESOURCE_MGMT 0x8C0C
+#define NUM_PS_THREADS(x) ((x) << 0)
+#define NUM_VS_THREADS(x) ((x) << 8)
+#define NUM_GS_THREADS(x) ((x) << 16)
+#define NUM_ES_THREADS(x) ((x) << 24)
+
+#define SX_DEBUG_1 0x9058
+#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
+#define SX_EXPORT_BUFFER_SIZES 0x900C
+#define COLOR_BUFFER_SIZE(x) ((x) << 0)
+#define POSITION_BUFFER_SIZE(x) ((x) << 8)
+#define SMX_BUFFER_SIZE(x) ((x) << 16)
+#define SX_MISC 0x28350
+
+#define TA_CNTL_AUX 0x9508
+#define DISABLE_CUBE_WRAP (1 << 0)
+#define DISABLE_CUBE_ANISO (1 << 1)
+#define SYNC_GRADIENT (1 << 24)
+#define SYNC_WALKER (1 << 25)
+#define SYNC_ALIGNER (1 << 26)
+#define BILINEAR_PRECISION_6_BIT (0 << 31)
+#define BILINEAR_PRECISION_8_BIT (1 << 31)
+
+#define TCP_CNTL 0x9610
+
+#define VGT_CACHE_INVALIDATION 0x88C4
+#define CACHE_INVALIDATION(x) ((x)<<0)
+#define VC_ONLY 0
+#define TC_ONLY 1
+#define VC_AND_TC 2
+#define AUTO_INVLD_EN(x) ((x) << 6)
+#define NO_AUTO 0
+#define ES_AUTO 1
+#define GS_AUTO 2
+#define ES_AND_GS_AUTO 3
+#define VGT_ES_PER_GS 0x88CC
+#define VGT_GS_PER_ES 0x88C8
+#define VGT_GS_PER_VS 0x88E8
+#define VGT_GS_VERTEX_REUSE 0x88D4
+#define VGT_NUM_INSTANCES 0x8974
+#define VGT_OUT_DEALLOC_CNTL 0x28C5C
+#define DEALLOC_DIST_MASK 0x0000007F
+#define VGT_STRMOUT_EN 0x28AB0
+#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
+#define VTX_REUSE_DEPTH_MASK 0x000000FF
+
+#define VM_CONTEXT0_CNTL 0x1410
+#define ENABLE_CONTEXT (1 << 0)
+#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
+#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
+#define VM_L2_CNTL 0x1400
+#define ENABLE_L2_CACHE (1 << 0)
+#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
+#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
+#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
+#define VM_L2_CNTL2 0x1404
+#define INVALIDATE_ALL_L1_TLBS (1 << 0)
+#define INVALIDATE_L2_CACHE (1 << 1)
+#define VM_L2_CNTL3 0x1408
+#define BANK_SELECT(x) ((x) << 0)
+#define CACHE_UPDATE_MODE(x) ((x) << 6)
+#define VM_L2_STATUS 0x140C
+#define L2_BUSY (1 << 0)
+
+#define WAIT_UNTIL 0x8040
+
+#endif
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