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-rw-r--r--drivers/clocksource/clksrc-dbx500-prcmu.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c
index 0ac5093..59feefe 100644
--- a/drivers/clocksource/clksrc-dbx500-prcmu.c
+++ b/drivers/clocksource/clksrc-dbx500-prcmu.c
@@ -31,7 +31,7 @@
#define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */
-void __iomem *clksrc_dbx500_timer_base;
+static void __iomem *clksrc_dbx500_timer_base;
static cycle_t clksrc_dbx500_prcmu_read(struct clocksource *cs)
{
@@ -79,8 +79,10 @@ static void notrace clksrc_dbx500_prcmu_update_sched_clock(void)
}
#endif
-void __init clksrc_dbx500_prcmu_init(void)
+void __init clksrc_dbx500_prcmu_init(void __iomem *base)
{
+ clksrc_dbx500_timer_base = base;
+
/*
* The A9 sub system expects the timer to be configured as
* a continous looping timer.
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