diff options
Diffstat (limited to 'arch')
27 files changed, 33 insertions, 33 deletions
diff --git a/arch/avr32/include/asm/addrspace.h b/arch/avr32/include/asm/addrspace.h index 3667948..5a47a79 100644 --- a/arch/avr32/include/asm/addrspace.h +++ b/arch/avr32/include/asm/addrspace.h @@ -1,5 +1,5 @@ /* - * Defitions for the address spaces of the AVR32 CPUs. Heavily based on + * Definitions for the address spaces of the AVR32 CPUs. Heavily based on * include/asm-sh/addrspace.h * * Copyright (C) 2004-2006 Atmel Corporation diff --git a/arch/blackfin/lib/udivsi3.S b/arch/blackfin/lib/udivsi3.S index 748a6a2..90bfa80 100644 --- a/arch/blackfin/lib/udivsi3.S +++ b/arch/blackfin/lib/udivsi3.S @@ -154,7 +154,7 @@ ENTRY(___udivsi3) CC = R7 < 0; /* Check quotient(AQ) */ /* If AQ==0, we'll sub divisor */ IF CC R5 = R1; /* and if AQ==1, we'll add it. */ - R3 = R3 + R5; /* Add/sub divsor to partial remainder */ + R3 = R3 + R5; /* Add/sub divisor to partial remainder */ R7 = R3 ^ R1; /* Generate next quotient bit */ R5 = R7 >> 31; /* Get AQ */ diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h index 35caa7b..3933e91 100644 --- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h +++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h @@ -2689,7 +2689,7 @@ #define L2CTL0_STAT 0xFFCA3010 /* L2CTL0 L2 Status Register */ #define L2CTL0_RPCR 0xFFCA3014 /* L2CTL0 L2 Read Priority Count Register */ #define L2CTL0_WPCR 0xFFCA3018 /* L2CTL0 L2 Write Priority Count Register */ -#define L2CTL0_RFA 0xFFCA3024 /* L2CTL0 L2 Refresh Address Regsiter */ +#define L2CTL0_RFA 0xFFCA3024 /* L2CTL0 L2 Refresh Address Register */ #define L2CTL0_ERRADDR0 0xFFCA3040 /* L2CTL0 L2 Bank 0 ECC Error Address Register */ #define L2CTL0_ERRADDR1 0xFFCA3044 /* L2CTL0 L2 Bank 1 ECC Error Address Register */ #define L2CTL0_ERRADDR2 0xFFCA3048 /* L2CTL0 L2 Bank 2 ECC Error Address Register */ diff --git a/arch/c6x/include/asm/clock.h b/arch/c6x/include/asm/clock.h index bcf42b2..e2f818a 100644 --- a/arch/c6x/include/asm/clock.h +++ b/arch/c6x/include/asm/clock.h @@ -101,7 +101,7 @@ struct clk { #define CLK_PLL BIT(2) /* PLL-derived clock */ #define PRE_PLL BIT(3) /* source is before PLL mult/div */ #define FIXED_DIV_PLL BIT(4) /* fixed divisor from PLL */ -#define FIXED_RATE_PLL BIT(5) /* fixed ouput rate PLL */ +#define FIXED_RATE_PLL BIT(5) /* fixed output rate PLL */ #define MAX_PLL_SYSCLKS 16 diff --git a/arch/c6x/platforms/cache.c b/arch/c6x/platforms/cache.c index 46fd2d5..ec3c887 100644 --- a/arch/c6x/platforms/cache.c +++ b/arch/c6x/platforms/cache.c @@ -145,7 +145,7 @@ loop: spin_lock_irqsave(&cache_lock, flags); /* - * If another cache operation is occuring + * If another cache operation is occurring */ if (unlikely(imcr_get(wc_reg))) { spin_unlock_irqrestore(&cache_lock, flags); diff --git a/arch/cris/arch-v10/drivers/axisflashmap.c b/arch/cris/arch-v10/drivers/axisflashmap.c index a4bbdfd..60d57c5 100644 --- a/arch/cris/arch-v10/drivers/axisflashmap.c +++ b/arch/cris/arch-v10/drivers/axisflashmap.c @@ -212,7 +212,7 @@ static struct mtd_info *probe_cs(struct map_info *map_cs) /* * Probe each chip select individually for flash chips. If there are chips on * both cse0 and cse1, the mtd_info structs will be concatenated to one struct - * so that MTD partitions can cross chip boundries. + * so that MTD partitions can cross chip boundaries. * * The only known restriction to how you can mount your chips is that each * chip select must hold similar flash chips. But you need external hardware diff --git a/arch/cris/arch-v32/drivers/axisflashmap.c b/arch/cris/arch-v32/drivers/axisflashmap.c index c6309a1..bd10d3b 100644 --- a/arch/cris/arch-v32/drivers/axisflashmap.c +++ b/arch/cris/arch-v32/drivers/axisflashmap.c @@ -246,7 +246,7 @@ static struct mtd_info *probe_cs(struct map_info *map_cs) /* * Probe each chip select individually for flash chips. If there are chips on * both cse0 and cse1, the mtd_info structs will be concatenated to one struct - * so that MTD partitions can cross chip boundries. + * so that MTD partitions can cross chip boundaries. * * The only known restriction to how you can mount your chips is that each * chip select must hold similar flash chips. But you need external hardware diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c index 617645d..2081d8b 100644 --- a/arch/cris/arch-v32/drivers/cryptocop.c +++ b/arch/cris/arch-v32/drivers/cryptocop.c @@ -525,7 +525,7 @@ static int setup_cipher_iv_desc(struct cryptocop_tfrm_ctx *tc, struct cryptocop_ return 0; } -/* Map the ouput length of the transform to operation output starting on the inject index. */ +/* Map the output length of the transform to operation output starting on the inject index. */ static int create_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **id, int alloc_flag) { int err = 0; diff --git a/arch/cris/arch-v32/mach-a3/dram_init.S b/arch/cris/arch-v32/mach-a3/dram_init.S index ec8648b..5c4f24d 100644 --- a/arch/cris/arch-v32/mach-a3/dram_init.S +++ b/arch/cris/arch-v32/mach-a3/dram_init.S @@ -11,7 +11,7 @@ */ /* Just to be certain the config file is included, we include it here - * explicitely instead of depending on it being included in the file that + * explicitly instead of depending on it being included in the file that * uses this code. */ diff --git a/arch/cris/arch-v32/mach-fs/dram_init.S b/arch/cris/arch-v32/mach-fs/dram_init.S index 6fbad33..d3ce2eb 100644 --- a/arch/cris/arch-v32/mach-fs/dram_init.S +++ b/arch/cris/arch-v32/mach-fs/dram_init.S @@ -11,7 +11,7 @@ */ /* Just to be certain the config file is included, we include it here - * explicitely instead of depending on it being included in the file that + * explicitly instead of depending on it being included in the file that * uses this code. */ diff --git a/arch/hexagon/include/asm/hexagon_vm.h b/arch/hexagon/include/asm/hexagon_vm.h index 1f6918b..e8990c9 100644 --- a/arch/hexagon/include/asm/hexagon_vm.h +++ b/arch/hexagon/include/asm/hexagon_vm.h @@ -237,7 +237,7 @@ static inline long __vmintop_clear(long i) /* * The initial program gets to find a system environment descriptor - * on its stack when it begins exection. The first word is a version + * on its stack when it begins execution. The first word is a version * code to indicate what is there. Zero means nothing more. */ diff --git a/arch/hexagon/include/asm/vm_mmu.h b/arch/hexagon/include/asm/vm_mmu.h index 096537d..6fc29d9 100644 --- a/arch/hexagon/include/asm/vm_mmu.h +++ b/arch/hexagon/include/asm/vm_mmu.h @@ -78,7 +78,7 @@ #define __HEXAGON_C_WB_L2 0x7 /* Write-back, with L2 */ /* - * This can be overriden, but we're defaulting to the most aggressive + * This can be overridden, but we're defaulting to the most aggressive * cache policy, the better to find bugs sooner. */ diff --git a/arch/hexagon/kernel/kgdb.c b/arch/hexagon/kernel/kgdb.c index 038580c..62dece3 100644 --- a/arch/hexagon/kernel/kgdb.c +++ b/arch/hexagon/kernel/kgdb.c @@ -236,9 +236,9 @@ static struct notifier_block kgdb_notifier = { }; /** - * kgdb_arch_init - Perform any architecture specific initalization. + * kgdb_arch_init - Perform any architecture specific initialization. * - * This function will handle the initalization of any architecture + * This function will handle the initialization of any architecture * specific callbacks. */ int kgdb_arch_init(void) diff --git a/arch/hexagon/kernel/vm_ops.S b/arch/hexagon/kernel/vm_ops.S index 9fb77b3..58f2b92 100644 --- a/arch/hexagon/kernel/vm_ops.S +++ b/arch/hexagon/kernel/vm_ops.S @@ -26,7 +26,7 @@ * could be, and perhaps some day will be, handled as in-line * macros, but for tracing/debugging it's handy to have * a single point of invocation for each of them. - * Conveniently, they take paramters and return values + * Conveniently, they take parameters and return values * consistent with the ABI calling convention. */ diff --git a/arch/hexagon/lib/memcpy.S b/arch/hexagon/lib/memcpy.S index 81c561c..a46093a 100644 --- a/arch/hexagon/lib/memcpy.S +++ b/arch/hexagon/lib/memcpy.S @@ -39,7 +39,7 @@ * DJH 10/14/09 Version 1.3 added special loop for aligned case, was * overreading bloated codesize back up to 892 * DJH 4/20/10 Version 1.4 fixed Ldword_loop_epilog loop to prevent loads - * occuring if only 1 left outstanding, fixes bug + * occurring if only 1 left outstanding, fixes bug * # 3888, corrected for all alignments. Peeled off * 1 32byte chunk from kernel loop and extended 8byte * loop at end to solve all combinations and prevent diff --git a/arch/ia64/include/asm/sn/ioc3.h b/arch/ia64/include/asm/sn/ioc3.h index 95ed6cc..6eaa3cc 100644 --- a/arch/ia64/include/asm/sn/ioc3.h +++ b/arch/ia64/include/asm/sn/ioc3.h @@ -131,7 +131,7 @@ struct ioc3 { #define SSCR_PAUSE_STATE 0x40000000 /* set when PAUSE takes effect*/ #define SSCR_RESET 0x80000000 /* reset DMA channels */ -/* all producer/comsumer pointers are the same bitfield */ +/* all producer/consumer pointers are the same bitfield */ #define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */ #define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */ #define PROD_CONS_PTR_OFF 3 diff --git a/arch/ia64/include/asm/sn/shubio.h b/arch/ia64/include/asm/sn/shubio.h index ecb8a49..8a1ec13 100644 --- a/arch/ia64/include/asm/sn/shubio.h +++ b/arch/ia64/include/asm/sn/shubio.h @@ -1385,7 +1385,7 @@ typedef union ii_ibcr_u { * respones are captured until IXSS[VALID] is cleared by setting the * * appropriate bit in IECLR. Every time a spurious read response is * * detected, the SPUR_RD bit of the PRB corresponding to the incoming * - * message's SIDN field is set. This always happens, regarless of * + * message's SIDN field is set. This always happens, regardless of * * whether a header is captured. The programmer should check * * IXSM[SIDN] to determine which widget sent the spurious response, * * because there may be more than one SPUR_RD bit set in the PRB * @@ -2997,7 +2997,7 @@ typedef union ii_ippr_u { /* * Values for field imsgtype */ -#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ +#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming message from Xtalk */ #define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ #define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */ #define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ diff --git a/arch/ia64/kernel/efi.c b/arch/ia64/kernel/efi.c index bf0865c..3b7a60e 100644 --- a/arch/ia64/kernel/efi.c +++ b/arch/ia64/kernel/efi.c @@ -964,7 +964,7 @@ efi_uart_console_only(void) /* * Look for the first granule aligned memory descriptor memory * that is big enough to hold EFI memory map. Make sure this - * descriptor is atleast granule sized so it does not get trimmed + * descriptor is at least granule sized so it does not get trimmed */ struct kern_memdesc * find_memmap_space (void) diff --git a/arch/ia64/lib/idiv32.S b/arch/ia64/lib/idiv32.S index 2ac28bf..c91b5b0 100644 --- a/arch/ia64/lib/idiv32.S +++ b/arch/ia64/lib/idiv32.S @@ -11,7 +11,7 @@ * * For more details on the theory behind these algorithms, see "IA-64 * and Elementary Functions" by Peter Markstein; HP Professional Books - * (http://www.hp.com/go/retailbooks/) + * (http://www.goodreads.com/book/show/2019887.Ia_64_and_Elementary_Functions) */ #include <asm/asmmacro.h> diff --git a/arch/ia64/lib/idiv64.S b/arch/ia64/lib/idiv64.S index f69bd2b..627573c 100644 --- a/arch/ia64/lib/idiv64.S +++ b/arch/ia64/lib/idiv64.S @@ -11,7 +11,7 @@ * * For more details on the theory behind these algorithms, see "IA-64 * and Elementary Functions" by Peter Markstein; HP Professional Books - * (http://www.hp.com/go/retailbooks/) + * (http://www.goodreads.com/book/show/2019887.Ia_64_and_Elementary_Functions) */ #include <asm/asmmacro.h> diff --git a/arch/metag/include/asm/metag_regs.h b/arch/metag/include/asm/metag_regs.h index acf4b8e..40c3f67 100644 --- a/arch/metag/include/asm/metag_regs.h +++ b/arch/metag/include/asm/metag_regs.h @@ -1165,7 +1165,7 @@ #define TXSTATUS_IPTOGGLE_BIT 0x80000000 /* Prev PToggle of TXPRIVEXT */ #define TXSTATUS_ISTATE_BIT 0x40000000 /* IState bit */ #define TXSTATUS_IWAIT_BIT 0x20000000 /* wait indefinitely in decision step*/ -#define TXSTATUS_IEXCEPT_BIT 0x10000000 /* Indicate an exception occured */ +#define TXSTATUS_IEXCEPT_BIT 0x10000000 /* Indicate an exception occurred */ #define TXSTATUS_IRPCOUNT_BITS 0x0E000000 /* Number of 'dirty' date entries*/ #define TXSTATUS_IRPCOUNT_S 25 #define TXSTATUS_IRQSTAT_BITS 0x0000F000 /* IRQEnc bits, trigger or interrupts */ diff --git a/arch/metag/include/asm/tbx.h b/arch/metag/include/asm/tbx.h index 703b9cb..5cd2a6c 100644 --- a/arch/metag/include/asm/tbx.h +++ b/arch/metag/include/asm/tbx.h @@ -668,7 +668,7 @@ typedef union _tbires_tag_ { State.Sig.TrigMask will indicate the bits set within TXMASKI at the time of the handler call that have all been cleared to prevent - nested interrupt occuring immediately. + nested interrupt occurring immediately. State.Sig.SaveMask is a bit-mask which will be set to Zero when a trigger occurs at background level and TBICTX_CRIT_BIT and optionally @@ -1083,7 +1083,7 @@ TBIRES __TBINestInts( TBIRES State, void *pExt, int NoNestMask ); /* This routine causes the TBICTX structure specified in State.Sig.pCtx to be restored. This implies that execution will not return to the caller. The State.Sig.TrigMask field will be restored during the context switch - such that any immediately occuring interrupts occur in the context of the + such that any immediately occurring interrupts occur in the context of the newly specified task. The State.Sig.SaveMask parameter is ignored. */ void __TBIASyncResume( TBIRES State ); @@ -1305,7 +1305,7 @@ extern const char __TBISigNames[]; /* * Calculate linear PC value from real PC and Minim mode control, the LSB of - * the result returned indicates if address compression has occured. + * the result returned indicates if address compression has occurred. */ #ifndef __ASSEMBLY__ #define METAG_LINPC( PCVal ) (\ diff --git a/arch/metag/tbx/tbipcx.S b/arch/metag/tbx/tbipcx.S index de0626f..163c79a 100644 --- a/arch/metag/tbx/tbipcx.S +++ b/arch/metag/tbx/tbipcx.S @@ -15,7 +15,7 @@ #include <asm/tbx.h> /* BEGIN HACK */ -/* define these for now while doing inital conversion to GAS +/* define these for now while doing initial conversion to GAS will fix properly later */ /* Signal identifiers always have the TBID_SIGNAL_BIT set and contain the diff --git a/arch/metag/tbx/tbisoft.S b/arch/metag/tbx/tbisoft.S index 0346fe8..b04f50d 100644 --- a/arch/metag/tbx/tbisoft.S +++ b/arch/metag/tbx/tbisoft.S @@ -56,7 +56,7 @@ ___TBIJumpX: /* * TBIRES __TBISwitch( TBIRES Switch, PTBICTX *rpSaveCtx ) * - * Software syncronous context switch between soft threads, save only the + * Software synchronous context switch between soft threads, save only the * registers which are actually valid on call entry. * * A0FrP, D0RtP, D0.5, D0.6, D0.7 - Saved on stack @@ -76,7 +76,7 @@ $LSwitchStart: SETL [A0StP+#8++],D0FrT,D1RtP /* * Save current frame state - we save all regs because we don't want - * uninitialised crap in the TBICTX structure that the asyncronous resumption + * uninitialised crap in the TBICTX structure that the asynchronous resumption * of a thread will restore. */ MOVT D1Re0,#HI($LSwitchExit) /* ASync resume point here */ @@ -117,7 +117,7 @@ $LSwitchExit: * This routine causes the TBICTX structure specified in State.Sig.pCtx to * be restored. This implies that execution will not return to the caller. * The State.Sig.TrigMask field will be ored into TXMASKI during the - * context switch such that any immediately occuring interrupts occur in + * context switch such that any immediately occurring interrupts occur in * the context of the newly specified task. The State.Sig.SaveMask parameter * is ignored. */ diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c index b2eb468..671fd51 100644 --- a/arch/powerpc/kernel/mce.c +++ b/arch/powerpc/kernel/mce.c @@ -284,7 +284,7 @@ void machine_check_print_event_info(struct machine_check_event *evt) printk("%s Effective address: %016llx\n", level, evt->u.ue_error.effective_address); if (evt->u.ue_error.physical_address_provided) - printk("%s Physial address: %016llx\n", + printk("%s Physical address: %016llx\n", level, evt->u.ue_error.physical_address); break; case MCE_ERROR_TYPE_SLB: diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index cbb3cf0..65cbbcd 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -422,7 +422,7 @@ static void show_saved_mc(void) data_size = get_datasize(mc_saved_header); date = mc_saved_header->date; - pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, toal size=0x%x, date = %04x-%02x-%02x\n", + pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n", i, sig, pf, rev, total_size, date & 0xffff, date >> 24, diff --git a/arch/x86/kvm/iommu.c b/arch/x86/kvm/iommu.c index a22a488..3069281 100644 --- a/arch/x86/kvm/iommu.c +++ b/arch/x86/kvm/iommu.c @@ -254,7 +254,7 @@ int kvm_iommu_map_guest(struct kvm *kvm) !iommu_capable(&pci_bus_type, IOMMU_CAP_INTR_REMAP)) { printk(KERN_WARNING "%s: No interrupt remapping support," " disallowing device assignment." - " Re-enble with \"allow_unsafe_assigned_interrupts=1\"" + " Re-enable with \"allow_unsafe_assigned_interrupts=1\"" " module option.\n", __func__); iommu_domain_free(kvm->arch.iommu_domain); kvm->arch.iommu_domain = NULL; |
