diff options
Diffstat (limited to 'arch')
627 files changed, 25380 insertions, 11880 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4797b24..dc6ef9a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -6,12 +6,13 @@ config ARM select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAVE_CUSTOM_GPIO_H select ARCH_MIGHT_HAVE_PC_PARPORT + select ARCH_USE_BUILTIN_BSWAP select ARCH_USE_CMPXCHG_LOCKREF select ARCH_WANT_IPC_PARSE_VERSION select BUILDTIME_EXTABLE_SORT if MMU select CLONE_BACKWARDS select CPU_PM if (SUSPEND || CPU_IDLE) - select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU + select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_IDLE_POLL_SETUP @@ -36,6 +37,7 @@ config ARM select HAVE_DMA_ATTRS select HAVE_DMA_CONTIGUOUS if MMU select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) + select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) @@ -63,6 +65,7 @@ config ARM select IRQ_FORCED_THREADING select KTIME_SCALAR select MODULES_USE_ELF_REL + select NO_BOOTMEM select OLD_SIGACTION select OLD_SIGSUSPEND3 select PERF_USE_VMALLOC @@ -314,6 +317,8 @@ config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" select ARCH_HAS_CPUFREQ select ARM_AMBA + select ARM_PATCH_PHYS_VIRT + select AUTO_ZRELADDR select COMMON_CLK select COMMON_CLK_VERSATILE select GENERIC_CLOCKEVENTS @@ -411,6 +416,26 @@ config ARCH_EBSA110 Ethernet interface, two PCMCIA sockets, two serial ports and a parallel port. +config ARCH_EFM32 + bool "Energy Micro efm32" + depends on !MMU + select ARCH_REQUIRE_GPIOLIB + select ARM_NVIC + # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged, + # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO + select CLKSRC_MMIO + select CLKSRC_OF + select COMMON_CLK + select CPU_V7M + select GENERIC_CLOCKEVENTS + select NO_DMA + select NO_IOPORT + select SPARSE_IRQ + select USE_OF + help + Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko + processors. + config ARCH_EP93XX bool "EP93xx-based" select ARCH_HAS_HOLES_MEMORYMODEL @@ -632,10 +657,10 @@ config ARCH_PXA help Support for Intel/Marvell's PXA2xx/PXA3xx processor line. -config ARCH_MSM +config ARCH_MSM_NODT bool "Qualcomm MSM" + select ARCH_MSM select ARCH_REQUIRE_GPIOLIB - select CLKSRC_OF if OF select COMMON_CLK select GENERIC_CLOCKEVENTS help @@ -645,8 +670,9 @@ config ARCH_MSM stack and controls some vital subsystems (clock and power control, etc). -config ARCH_SHMOBILE - bool "Renesas SH-Mobile / R-Mobile" +config ARCH_SHMOBILE_LEGACY + bool "Renesas ARM SoCs (non-multiplatform)" + select ARCH_SHMOBILE select ARM_PATCH_PHYS_VIRT select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS @@ -661,7 +687,9 @@ config ARCH_SHMOBILE select PM_GENERIC_DOMAINS if PM select SPARSE_IRQ help - Support for Renesas's SH-Mobile and R-Mobile ARM platforms. + Support for Renesas ARM SoC platforms using a non-multiplatform + kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car + and RZ families. config ARCH_RPC bool "RiscPC" @@ -728,7 +756,7 @@ config ARCH_S3C64XX select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM select COMMON_CLK - select CPU_V6 + select CPU_V6K select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG select HAVE_S3C2410_I2C if I2C @@ -740,7 +768,6 @@ config ARCH_S3C64XX select S3C_DEV_NAND select S3C_GPIO_TRACK select SAMSUNG_ATAGS - select SAMSUNG_GPIOLIB_4BIT select SAMSUNG_WAKEMASK select SAMSUNG_WDT_RESET select USB_ARCH_HAS_OHCI @@ -911,6 +938,8 @@ source "arch/arm/mach-bcm/Kconfig" source "arch/arm/mach-bcm2835/Kconfig" +source "arch/arm/mach-berlin/Kconfig" + source "arch/arm/mach-clps711x/Kconfig" source "arch/arm/mach-cns3xxx/Kconfig" @@ -927,6 +956,8 @@ source "arch/arm/mach-gemini/Kconfig" source "arch/arm/mach-highbank/Kconfig" +source "arch/arm/mach-hisi/Kconfig" + source "arch/arm/mach-integrator/Kconfig" source "arch/arm/mach-iop32x/Kconfig" @@ -945,6 +976,8 @@ source "arch/arm/mach-ks8695/Kconfig" source "arch/arm/mach-msm/Kconfig" +source "arch/arm/mach-moxart/Kconfig" + source "arch/arm/mach-mv78xx0/Kconfig" source "arch/arm/mach-imx/Kconfig" @@ -1053,6 +1086,8 @@ config ARM_TIMER_SP804 select CLKSRC_MMIO select CLKSRC_OF if OF +source "arch/arm/firmware/Kconfig" + source arch/arm/mm/Kconfig config ARM_NR_BANKS @@ -1611,7 +1646,7 @@ config HZ_FIXED default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ ARCH_S5PV210 || ARCH_EXYNOS4 default AT91_TIMER_HZ if ARCH_AT91 - default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE + default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY default 0 choice @@ -1651,9 +1686,6 @@ config HZ config SCHED_HRTICK def_bool HIGH_RES_TIMERS -config SCHED_HRTICK - def_bool HIGH_RES_TIMERS - config THUMB2_KERNEL bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K @@ -1796,10 +1828,10 @@ config ARCH_WANT_GENERAL_HUGETLB source "mm/Kconfig" config FORCE_MAX_ZONEORDER - int "Maximum zone order" if ARCH_SHMOBILE - range 11 64 if ARCH_SHMOBILE + int "Maximum zone order" if ARCH_SHMOBILE_LEGACY + range 11 64 if ARCH_SHMOBILE_LEGACY default "12" if SOC_AM33XX - default "9" if SA1111 + default "9" if SA1111 || ARCH_EFM32 default "11" help The kernel memory allocator divides physically contiguous memory @@ -1934,6 +1966,7 @@ config ZBOOT_ROM_BSS config ZBOOT_ROM bool "Compressed boot loader in ROM/flash" depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS + depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR help Say Y here if you intend to execute your compressed kernel image (zImage) directly from ROM or flash. If unsure, say N. @@ -1969,7 +2002,7 @@ endchoice config ARM_APPENDED_DTB bool "Use appended device tree blob to zImage (EXPERIMENTAL)" - depends on OF && !ZBOOT_ROM + depends on OF help With this option, the boot code will look for a device tree binary (DTB) appended to zImage @@ -2057,7 +2090,7 @@ endchoice config XIP_KERNEL bool "Kernel Execute-In-Place from ROM" - depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM + depends on !ARM_LPAE && !ARCH_MULTIPLATFORM help Execute-In-Place allows the kernel to run from non-volatile storage directly addressable by the CPU, such as NOR flash. This saves RAM @@ -2120,7 +2153,6 @@ config CRASH_DUMP config AUTO_ZRELADDR bool "Auto calculation of the decompressed kernel image address" - depends on !ZBOOT_ROM help ZRELADDR is the physical address where the decompressed kernel image will be placed. If AUTO_ZRELADDR is selected, the address diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 5765abf..0531da8 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -2,6 +2,18 @@ menu "Kernel hacking" source "lib/Kconfig.debug" +config ARM_PTDUMP + bool "Export kernel pagetable layout to userspace via debugfs" + depends on DEBUG_KERNEL + select DEBUG_FS + ---help--- + Say Y here if you want to show the kernel pagetable layout in a + debugfs file. This information is only useful for kernel developers + who are working in architecture specific areas of the kernel. + It is probably not a good idea to enable this feature in a production + kernel. + If in doubt, say "N" + config STRICT_DEVMEM bool "Filter access to /dev/mem" depends on MMU @@ -94,6 +106,25 @@ choice depends on ARCH_BCM2835 select DEBUG_UART_PL01X + config DEBUG_BCM_KONA_UART + bool "Kernel low-level debugging messages via BCM KONA UART" + depends on ARCH_BCM + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Broadcom SoC platforms. + This low level debug works for Broadcom + mobile SoCs in the Kona family of chips (e.g. bcm28155, + bcm11351, etc...) + + config DEBUG_BERLIN_UART + bool "Marvell Berlin SoC Debug UART" + depends on ARCH_BERLIN + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Marvell Berlin SoC based platforms. + config DEBUG_CLPS711X_UART1 bool "Kernel low-level debugging messages via UART1" depends on ARCH_CLPS711X @@ -255,6 +286,13 @@ choice Say Y here if you want kernel low-level debugging support on i.MX35. + config DEBUG_IMX50_UART + bool "i.MX50 Debug UART" + depends on SOC_IMX50 + help + Say Y here if you want kernel low-level debugging support + on i.MX50. + config DEBUG_IMX51_UART bool "i.MX51 Debug UART" depends on SOC_IMX51 @@ -897,6 +935,7 @@ config DEBUG_IMX_UART_PORT DEBUG_IMX21_IMX27_UART || \ DEBUG_IMX31_UART || \ DEBUG_IMX35_UART || \ + DEBUG_IMX50_UART || \ DEBUG_IMX51_UART || \ DEBUG_IMX53_UART || \ DEBUG_IMX6Q_UART || \ @@ -931,6 +970,7 @@ config DEBUG_LL_INCLUDE DEBUG_IMX21_IMX27_UART || \ DEBUG_IMX31_UART || \ DEBUG_IMX35_UART || \ + DEBUG_IMX50_UART || \ DEBUG_IMX51_UART || \ DEBUG_IMX53_UART ||\ DEBUG_IMX6Q_UART || \ @@ -988,6 +1028,7 @@ config DEBUG_UART_PHYS default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 default 0x20201000 if DEBUG_BCM2835 + default 0x3e000000 if DEBUG_BCM_KONA_UART default 0x4000e400 if DEBUG_LL_UART_EFM32 default 0x40090000 if ARCH_LPC32XX default 0x40100000 if DEBUG_PXA_UART1 @@ -1011,6 +1052,7 @@ config DEBUG_UART_PHYS default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \ ARCH_ORION5X + default 0xf7fc9000 if DEBUG_BERLIN_UART default 0xf8b00000 if DEBUG_HI3716_UART default 0xfcb00000 if DEBUG_HI3620_UART default 0xfe800000 if ARCH_IOP32X @@ -1036,6 +1078,7 @@ config DEBUG_UART_VIRT default 0xf2100000 if DEBUG_PXA_UART1 default 0xf4090000 if ARCH_LPC32XX default 0xf4200000 if ARCH_GEMINI + default 0xf7fc9000 if DEBUG_BERLIN_UART default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9 default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1 default 0xfb009000 if DEBUG_REALVIEW_STD_PORT @@ -1049,6 +1092,7 @@ config DEBUG_UART_VIRT default 0xfe018000 if DEBUG_MMP_UART3 default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART default 0xfe230000 if DEBUG_PICOXCELL_UART + default 0xfe300000 if DEBUG_BCM_KONA_UART default 0xfe800000 if ARCH_IOP32X default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HI3716_UART default 0xfeb24000 if DEBUG_RK3X_UART0 @@ -1091,7 +1135,8 @@ config DEBUG_UART_8250_WORD default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \ ARCH_KEYSTONE || \ DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ - DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 + DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 || \ + DEBUG_BCM_KONA_UART config DEBUG_UART_8250_FLOW_CONTROL bool "Enable flow control for 8250 UART" @@ -1150,4 +1195,15 @@ config PID_IN_CONTEXTIDR additional instructions during context switch. Say Y here only if you are planning to use hardware trace tools with this kernel. +config DEBUG_SET_MODULE_RONX + bool "Set loadable kernel module data as NX and text as RO" + depends on MODULES + ---help--- + This option helps catch unintended modifications to loadable + kernel module's text and read-only data. It also prevents execution + of module data. Such protection may interfere with run-time code + patching and dynamic kernel tracing - and they might also protect + against certain classes of kernel exploits. + If in doubt, say "N". + endmenu diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 55b4255..23d5e39 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -144,15 +144,18 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 machine-$(CONFIG_ARCH_AT91) += at91 machine-$(CONFIG_ARCH_BCM) += bcm machine-$(CONFIG_ARCH_BCM2835) += bcm2835 +machine-$(CONFIG_ARCH_BERLIN) += berlin machine-$(CONFIG_ARCH_CLPS711X) += clps711x machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_DOVE) += dove machine-$(CONFIG_ARCH_EBSA110) += ebsa110 +machine-$(CONFIG_ARCH_EFM32) += efm32 machine-$(CONFIG_ARCH_EP93XX) += ep93xx machine-$(CONFIG_ARCH_EXYNOS) += exynos machine-$(CONFIG_ARCH_GEMINI) += gemini machine-$(CONFIG_ARCH_HIGHBANK) += highbank +machine-$(CONFIG_ARCH_HI3xxx) += hisi machine-$(CONFIG_ARCH_INTEGRATOR) += integrator machine-$(CONFIG_ARCH_IOP13XX) += iop13xx machine-$(CONFIG_ARCH_IOP32X) += iop32x @@ -163,6 +166,7 @@ machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood machine-$(CONFIG_ARCH_KS8695) += ks8695 machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MMP) += mmp +machine-$(CONFIG_ARCH_MOXART) += moxart machine-$(CONFIG_ARCH_MSM) += msm machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 machine-$(CONFIG_ARCH_MVEBU) += mvebu @@ -186,7 +190,6 @@ machine-$(CONFIG_ARCH_S5PC100) += s5pc100 machine-$(CONFIG_ARCH_S5PV210) += s5pv210 machine-$(CONFIG_ARCH_SA1100) += sa1100 machine-$(CONFIG_ARCH_SHMOBILE) += shmobile -machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile machine-$(CONFIG_ARCH_SIRF) += prima2 machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_STI) += sti @@ -264,6 +267,7 @@ core-$(CONFIG_KVM_ARM_HOST) += arch/arm/kvm/ core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/ core-y += arch/arm/net/ core-y += arch/arm/crypto/ +core-y += arch/arm/firmware/ core-y += $(machdirs) $(platdirs) drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index e7190bb..68c9183 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -64,7 +64,7 @@ else endif endif -ifeq ($(CONFIG_ARCH_SHMOBILE),y) +ifeq ($(CONFIG_ARCH_SHMOBILE_LEGACY),y) OBJS += head-shmobile.o endif @@ -108,12 +108,12 @@ endif targets := vmlinux vmlinux.lds \ piggy.$(suffix_y) piggy.$(suffix_y).o \ - lib1funcs.o lib1funcs.S ashldi3.o ashldi3.S \ - font.o font.c head.o misc.o $(OBJS) + lib1funcs.o lib1funcs.S ashldi3.o ashldi3.S bswapsdi2.o \ + bswapsdi2.S font.o font.c head.o misc.o $(OBJS) # Make sure files are removed during clean extra-y += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern piggy.lz4 \ - lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs) \ + lib1funcs.S ashldi3.S bswapsdi2.S $(libfdt) $(libfdt_hdrs) \ hyp-stub.S ifeq ($(CONFIG_FUNCTION_TRACER),y) @@ -156,6 +156,12 @@ ashldi3 = $(obj)/ashldi3.o $(obj)/ashldi3.S: $(srctree)/arch/$(SRCARCH)/lib/ashldi3.S $(call cmd,shipped) +# For __bswapsi2, __bswapdi2 +bswapsdi2 = $(obj)/bswapsdi2.o + +$(obj)/bswapsdi2.S: $(srctree)/arch/$(SRCARCH)/lib/bswapsdi2.S + $(call cmd,shipped) + # We need to prevent any GOTOFF relocs being used with references # to symbols in the .bss section since we cannot relocate them # independently from the rest at run time. This can be achieved by @@ -177,7 +183,8 @@ if [ $(words $(ZRELADDR)) -gt 1 -a "$(CONFIG_AUTO_ZRELADDR)" = "" ]; then \ fi $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \ - $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) $(ashldi3) FORCE + $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) $(ashldi3) \ + $(bswapsdi2) FORCE @$(check_for_multiple_zreladdr) $(call if_changed,ld) @$(check_for_bad_syms) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d57c1a6..ede21c1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb dtb-$(CONFIG_ARCH_AT91) += mpa1600.dtb # sam9260 dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb +dtb-$(CONFIG_ARCH_AT91) += at91-qil_a9260.dtb dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb @@ -30,6 +31,7 @@ dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb # sam9x5 dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb +dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb @@ -40,11 +42,16 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb +dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb + dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \ bcm28155-ap.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb +dtb-$(CONFIG_ARCH_BERLIN) += \ + berlin2-sony-nsz-gs7.dtb \ + berlin2cd-google-chromecast.dtb dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ da850-evm.dtb dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ @@ -52,6 +59,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ dove-d2plug.dtb \ dove-d3plug.dtb \ dove-dove-db.dtb +dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ @@ -59,13 +67,16 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4412-odroidx.dtb \ exynos4412-origen.dtb \ exynos4412-smdk4412.dtb \ + exynos4412-tiny4412.dtb \ exynos4412-trats2.dtb \ exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ + exynos5420-arndale-octa.dtb \ exynos5420-smdk5420.dtb \ exynos5440-sd5v1.dtb \ exynos5440-ssdk5440.dtb +dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ ecx-2000.dtb dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ @@ -85,11 +96,13 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ kirkwood-iomega_ix2_200.dtb \ kirkwood-is2.dtb \ kirkwood-km_kirkwood.dtb \ + kirkwood-laplug.dtb \ kirkwood-lschlv2.dtb \ kirkwood-lsxhl.dtb \ kirkwood-mplcec4.dtb \ kirkwood-mv88f6281gtw-ge.dtb \ kirkwood-netgear_readynas_duo_v2.dtb \ + kirkwood-netgear_readynas_nv+_v2.dtb \ kirkwood-ns2.dtb \ kirkwood-ns2lite.dtb \ kirkwood-ns2max.dtb \ @@ -104,8 +117,10 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ kirkwood-ts219-6281.dtb \ kirkwood-ts219-6282.dtb dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb +dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \ - qcom-msm8960-cdp.dtb + qcom-msm8960-cdp.dtb \ + qcom-apq8074-dragonboard.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ armada-370-mirabox.dtb \ armada-370-netgear-rn102.dtb \ @@ -114,6 +129,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ armada-xp-gp.dtb \ + armada-xp-netgear-rn2120.dtb \ armada-xp-matrix.dtb \ armada-xp-openblocks-ax3-4.dtb dtb-$(CONFIG_ARCH_MXC) += \ @@ -173,12 +189,19 @@ dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ nspire-tp.dtb \ nspire-clp.dtb dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ + omap2430-sdp.dtb \ + omap2420-n800.dtb \ + omap2420-n810.dtb \ + omap2420-n810-wimax.dtb \ omap3430-sdp.dtb \ omap3-beagle.dtb \ + omap3-cm-t3730.dtb \ + omap3-sbc-t3730.dtb \ omap3-devkit8000.dtb \ omap3-beagle-xm.dtb \ omap3-evm.dtb \ omap3-evm-37xx.dtb \ + omap3-ldp.dtb \ omap3-n900.dtb \ omap3-n9.dtb \ omap3-n950.dtb \ @@ -216,8 +239,9 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ s3c6410-smdk6410.dtb -dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ +dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \ r7s72100-genmai.dtb \ + r7s72100-genmai-reference.dtb \ r8a7740-armadillo800eva.dtb \ r8a7778-bockw.dtb \ r8a7778-bockw-reference.dtb \ @@ -226,13 +250,15 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a7779-marzen-reference.dtb \ r8a7791-koelsch.dtb \ r8a7790-lager.dtb \ - r8a7790-lager-reference.dtb \ sh73a0-kzm9g.dtb \ sh73a0-kzm9g-reference.dtb \ r8a73a4-ape6evm.dtb \ r8a73a4-ape6evm-reference.dtb \ sh7372-mackerel.dtb -dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb +dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ + r7s72100-genmai-reference.dtb \ + r8a7791-koelsch.dtb \ + r8a7790-lager.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_sockit.dtb \ @@ -255,6 +281,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ sun4i-a10-hackberry.dtb \ sun5i-a10s-olinuxino-micro.dtb \ sun5i-a13-olinuxino.dtb \ + sun5i-a13-olinuxino-micro.dtb \ sun6i-a31-colombus.dtb \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index 03fcbf0..b4127c6 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -17,6 +17,21 @@ device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; + + vmmc_fixed: vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&davinci_emac { + status = "okay"; +}; + +&davinci_mdio { + status = "okay"; }; &i2c1 { @@ -30,3 +45,17 @@ &i2c3 { clock-frequency = <400000>; }; + +&mmc1 { + vmmc-supply = <&vmmc_fixed>; + bus-width = <4>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 3a1de9e..3c4f6d9 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -90,34 +90,19 @@ nand-on-flash-bbt; status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x8000>; - }; - - barebox@8000 { + barebox@0 { label = "barebox"; - reg = <0x8000 0x40000>; - }; - - bareboxenv@48000 { - label = "bareboxenv"; - reg = <0x48000 0x8000>; - }; - - user_block@0x50000 { - label = "user_block"; - reg = <0x50000 0xb0000>; + reg = <0x0 0x58000>; }; - kernel@100000 { - label = "kernel"; - reg = <0x100000 0x1b0000>; + u_boot_env@58000 { + label = "u_boot_env"; + reg = <0x58000 0x8000>; }; - root@2b0000 { - label = "root"; - reg = <0x2b0000 0x1D50000>; + ubi@60000 { + label = "ubi"; + reg = <0x60000 0x1FA0000>; }; }; diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 2471d9d..944e878 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -74,13 +74,13 @@ green_pwr_led { label = "mirabox:green:pwr"; gpios = <&gpio1 31 1>; - linux,default-trigger = "heartbeat"; + default-state = "keep"; }; blue_stat_led { label = "mirabox:blue:stat"; gpios = <&gpio2 0 1>; - linux,default-trigger = "cpu0"; + default-state = "off"; }; green_stat_led { @@ -139,6 +139,27 @@ reg = <0x25>; }; }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + partition@400000 { + label = "Linux"; + reg = <0x400000 0x400000>; + }; + partition@800000 { + label = "Filesystem"; + reg = <0x800000 0x3f800000>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 8ac2ac1..651aeb5 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -11,6 +11,8 @@ /dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> #include "armada-370.dtsi" / { @@ -62,6 +64,7 @@ marvell,pins = "mpp57"; marvell,function = "gpio"; }; + sata1_led_pin: sata1-led-pin { marvell,pins = "mpp15"; marvell,function = "gpio"; @@ -77,6 +80,21 @@ marvell,function = "gpio"; }; + backup_button_pin: backup-button-pin { + marvell,pins = "mpp58"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp62"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + poweroff: poweroff { marvell,pins = "mpp8"; marvell,function = "gpio"; @@ -84,7 +102,7 @@ }; mdio { - phy0: ethernet-phy@0 { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ reg = <0>; }; }; @@ -104,6 +122,11 @@ clock-frequency = <100000>; status = "okay"; + isl12057: isl12057@68 { + compatible = "isl,isl12057"; + reg = <0x68>; + }; + g762: g762@3e { compatible = "gmt,g762"; reg = <0x3e>; @@ -113,82 +136,116 @@ pwm_polarity = <0>; }; }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; /* 1.5MB */ + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; /* 128KB */ + read-only; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; /* 6MB */ + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x400000>; /* 4MB */ + }; + + /* Last MB is for the BBT, i.e. not writable */ + partition@c00000 { + label = "ubifs"; + reg = <0x0c00000 0x7400000>; /* 116MB */ + }; + }; }; }; clocks { - #address-cells = <1>; - #size-cells = <0>; - - g762_clk: fixedclk { + g762_clk: g762-oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <8192>; }; }; - gpio_leds { + gpio-leds { compatible = "gpio-leds"; - pinctrl-0 = < &power_led_pin - &sata1_led_pin - &sata2_led_pin - &backup_led_pin >; + pinctrl-0 = <&power_led_pin + &sata1_led_pin + &sata2_led_pin + &backup_led_pin>; pinctrl-names = "default"; - blue_power_led { + blue-power-led { label = "rn102:blue:pwr"; - gpios = <&gpio1 25 1>; /* GPIO 57 Active Low */ - linux,default-trigger = "heartbeat"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + default-state = "keep"; }; - green_sata1_led { + green-sata1-led { label = "rn102:green:sata1"; - gpios = <&gpio0 15 1>; /* GPIO 15 Active Low */ + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; default-state = "on"; }; - green_sata2_led { + green-sata2-led { label = "rn102:green:sata2"; - gpios = <&gpio0 14 1>; /* GPIO 14 Active Low */ + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; default-state = "on"; }; - green_backup_led { + green-backup-led { label = "rn102:green:backup"; - gpios = <&gpio1 24 1>; /* GPIO 56 Active Low */ + gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; default-state = "on"; }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; + pinctrl-0 = <&power_button_pin + &reset_button_pin + &backup_button_pin>; + pinctrl-names = "default"; - button@1 { + power-button { label = "Power Button"; - linux,code = <116>; /* KEY_POWER */ - gpios = <&gpio1 30 0>; + linux,code = <KEY_POWER>; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; }; - button@2 { + reset-button { label = "Reset Button"; - linux,code = <0x198>; /* KEY_RESTART */ - gpios = <&gpio0 6 1>; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; - button@3 { + backup-button { label = "Backup Button"; - linux,code = <133>; /* KEY_COPY */ - gpios = <&gpio1 26 1>; + linux,code = <KEY_COPY>; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; }; }; - gpio_poweroff { + gpio-poweroff { compatible = "gpio-poweroff"; pinctrl-0 = <&poweroff>; pinctrl-names = "default"; - gpios = <&gpio0 8 1>; + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; }; - }; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index b0b32f5..4e27587 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -11,6 +11,8 @@ /dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> #include "armada-370.dtsi" / { @@ -58,12 +60,12 @@ marvell,function = "gpio"; }; - backup_key_pin: backup-key-pin { + backup_button_pin: backup-button-pin { marvell,pins = "mpp52"; marvell,function = "gpio"; }; - power_key_pin: power-key-pin { + power_button_pin: power-button-pin { marvell,pins = "mpp62"; marvell,function = "gpio"; }; @@ -78,18 +80,18 @@ marvell,function = "gpio"; }; - reset_key_pin: reset-key-pin { + reset_button_pin: reset-button-pin { marvell,pins = "mpp65"; marvell,function = "gpio"; }; }; mdio { - phy0: ethernet-phy@0 { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ reg = <0>; }; - phy1: ethernet-phy@1 { + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ reg = <1>; }; }; @@ -115,6 +117,11 @@ clock-frequency = <100000>; status = "okay"; + isl12057: isl12057@68 { + compatible = "isl,isl12057"; + reg = <0x68>; + }; + g762: g762@3e { compatible = "gmt,g762"; reg = <0x3e>; @@ -123,71 +130,133 @@ fan_startv = <1>; pwm_polarity = <0>; }; + + pca9554: pca9554@23 { + compatible = "nxp,pca9554"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x23>; + }; + }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; /* 1.5MB */ + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; /* 128KB */ + read-only; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; /* 6MB */ + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x400000>; /* 4MB */ + }; + + /* Last MB is for the BBT, i.e. not writable */ + partition@c00000 { + label = "ubifs"; + reg = <0x0c00000 0x7400000>; /* 116MB */ + }; }; }; }; clocks { - #address-cells = <1>; - #size-cells = <0>; - - g762_clk: fixedclk { + g762_clk: g762-oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <8192>; }; }; - gpio_leds { + gpio-leds { compatible = "gpio-leds"; pinctrl-0 = <&backup_led_pin &power_led_pin>; pinctrl-names = "default"; - blue_backup_led { + blue-backup-led { label = "rn104:blue:backup"; - gpios = <&gpio1 31 0>; /* GPIO 63 Active High */ + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - blue_power_led { + blue-power-led { label = "rn104:blue:pwr"; - gpios = <&gpio2 0 1>; /* GPIO 64 Active Low */ + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "keep"; }; + + blue-sata1-led { + label = "rn104:blue:sata1"; + gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + blue-sata2-led { + label = "rn104:blue:sata2"; + gpios = <&pca9554 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + blue-sata3-led { + label = "rn104:blue:sata3"; + gpios = <&pca9554 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + blue-sata4-led { + label = "rn104:blue:sata4"; + gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&backup_key_pin - &power_key_pin - &reset_key_pin>; + pinctrl-0 = <&backup_button_pin + &power_button_pin + &reset_button_pin>; pinctrl-names = "default"; - button@1 { + backup-button { label = "Backup Button"; - linux,code = <133>; /* KEY_COPY */ - gpios = <&gpio1 20 1>; + linux,code = <KEY_COPY>; + gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; }; - button@2 { + power-button { label = "Power Button"; - linux,code = <116>; /* KEY_POWER */ - gpios = <&gpio1 30 0>; + linux,code = <KEY_POWER>; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; }; - button@3 { + reset-button { label = "Reset Button"; - linux,code = <0x198>; /* KEY_RESTART */ - gpios = <&gpio2 1 1>; + linux,code = <KEY_RESTART>; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; }; }; - gpio_poweroff { + gpio-poweroff { compatible = "gpio-poweroff"; pinctrl-0 = <&poweroff>; pinctrl-names = "default"; - gpios = <&gpio1 28 1>; + gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index f81810a..abbb807 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -104,6 +104,27 @@ gpios = <&gpio0 6 1>; }; }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 80ffacd..74b5964 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -103,22 +103,52 @@ #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>; + rtc@10300 { + compatible = "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <50>; }; - mpic: interrupt-controller@20000 { - compatible = "marvell,mpic"; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; + spi0: spi@10600 { + compatible = "marvell,orion-spi"; + reg = <0x10600 0x28>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <30>; + clocks = <&coreclk 0>; + status = "disabled"; }; - coherency-fabric@20200 { - compatible = "marvell,coherency-fabric"; - reg = <0x20200 0xb0>, <0x21010 0x1c>; + spi1: spi@10680 { + compatible = "marvell,orion-spi"; + reg = <0x10680 0x28>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <92>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <31>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <32>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; }; serial@12000 { @@ -146,25 +176,41 @@ clock-output-names = "nand"; }; + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>; + }; + + mpic: interrupt-controller@20000 { + compatible = "marvell,mpic"; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + }; + + coherency-fabric@20200 { + compatible = "marvell,coherency-fabric"; + reg = <0x20200 0xb0>, <0x21010 0x1c>; + }; + timer@20300 { reg = <0x20300 0x30>, <0x21040 0x30>; interrupts = <37>, <38>, <39>, <40>, <5>, <6>; }; - sata@a0000 { - compatible = "marvell,armada-370-sata"; - reg = <0xa0000 0x5000>; - interrupts = <55>; - clocks = <&gateclk 15>, <&gateclk 30>; - clock-names = "0", "1"; + usb@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x500>; + interrupts = <45>; status = "disabled"; }; - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x72004 0x4>; + usb@51000 { + compatible = "marvell,orion-ehci"; + reg = <0x51000 0x500>; + interrupts = <46>; + status = "disabled"; }; eth0: ethernet@70000 { @@ -175,6 +221,13 @@ status = "disabled"; }; + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x72004 0x4>; + }; + eth1: ethernet@74000 { compatible = "marvell,armada-370-neta"; reg = <0x74000 0x4000>; @@ -183,32 +236,25 @@ status = "disabled"; }; - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <31>; - timeout-ms = <1000>; - clocks = <&coreclk 0>; + sata@a0000 { + compatible = "marvell,armada-370-sata"; + reg = <0xa0000 0x5000>; + interrupts = <55>; + clocks = <&gateclk 15>, <&gateclk 30>; + clock-names = "0", "1"; status = "disabled"; }; - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; + nand@d0000 { + compatible = "marvell,armada370-nand"; + reg = <0xd0000 0x54>; #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - timeout-ms = <1000>; - clocks = <&coreclk 0>; + #size-cells = <1>; + interrupts = <113>; + clocks = <&coredivclk 0>; status = "disabled"; }; - rtc@10300 { - compatible = "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <50>; - }; - mvsdio@d4000 { compatible = "marvell,orion-sdio"; reg = <0xd4000 0x200>; @@ -220,43 +266,6 @@ cap-mmc-highspeed; status = "disabled"; }; - - usb@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x500>; - interrupts = <45>; - status = "disabled"; - }; - - usb@51000 { - compatible = "marvell,orion-ehci"; - reg = <0x51000 0x500>; - interrupts = <46>; - status = "disabled"; - }; - - spi0: spi@10600 { - compatible = "marvell,orion-spi"; - reg = <0x10600 0x28>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <30>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,orion-spi"; - reg = <0x10680 0x28>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <92>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - }; }; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 7a4b82e..0d8530c 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -91,11 +91,6 @@ }; internal-regs { - system-controller@18200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x100>; - }; - L2: l2-cache { compatible = "marvell,aurora-outer-cache"; reg = <0x08000 0x1000>; @@ -103,8 +98,17 @@ wt-override; }; - interrupt-controller@20000 { - reg = <0x20a00 0x1d0>, <0x21870 0x58>; + i2c0: i2c@11000 { + reg = <0x11000 0x20>; + }; + + i2c1: i2c@11100 { + reg = <0x11100 0x20>; + }; + + system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x100>; }; pinctrl { @@ -163,9 +167,11 @@ interrupts = <91>; }; - timer@20300 { - compatible = "marvell,armada-370-timer"; - clocks = <&coreclk 2>; + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-370-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; }; coreclk: mvebu-sar@18230 { @@ -174,11 +180,28 @@ #clock-cells = <1>; }; - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-370-gating-clock"; - reg = <0x18220 0x4>; + thermal@18300 { + compatible = "marvell,armada370-thermal"; + reg = <0x18300 0x4 + 0x18304 0x4>; + status = "okay"; + }; + + interrupt-controller@20000 { + reg = <0x20a00 0x1d0>, <0x21870 0x58>; + }; + + timer@20300 { + compatible = "marvell,armada-370-timer"; + clocks = <&coreclk 2>; + }; + + usb@50000 { + clocks = <&coreclk 0>; + }; + + usb@51000 { clocks = <&coreclk 0>; - #clock-cells = <1>; }; xor@60800 { @@ -218,29 +241,6 @@ dmacap,memset; }; }; - - i2c0: i2c@11000 { - reg = <0x11000 0x20>; - }; - - i2c1: i2c@11100 { - reg = <0x11100 0x20>; - }; - - usb@50000 { - clocks = <&coreclk 0>; - }; - - usb@51000 { - clocks = <&coreclk 0>; - }; - - thermal@18300 { - compatible = "marvell,armada370-thermal"; - reg = <0x18300 0x4 - 0x18304 0x4>; - status = "okay"; - }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 2298e4a..274e2ad 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -175,6 +175,14 @@ spi-max-frequency = <108000000>; }; }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts new file mode 100644 index 0000000..ff049ee --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -0,0 +1,327 @@ +/* + * Device Tree file for NETGEAR ReadyNAS 2120 + * + * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "armada-xp-mv78230.dtsi" + +/ { + model = "NETGEAR ReadyNAS 2120"; + compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x80000000>; /* 2GB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>; + + pcie-controller { + status = "okay"; + + /* Connected to first Marvell 88SE9170 SATA controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected to second Marvell 88SE9170 SATA controller */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Connected to Fresco Logic FL1009 USB 3.0 controller */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + pinctrl { + poweroff: poweroff { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + sata1_led_pin: sata1-led-pin { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + sata2_led_pin: sata2-led-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + sata3_led_pin: sata3-led-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + sata4_led_pin: sata4-led-pin { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + sata1_power_pin: sata1-power-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + sata2_power_pin: sata2-power-pin { + marvell,pins = "mpp25"; + marvell,function = "gpio"; + }; + + sata3_power_pin: sata3-power-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + sata4_power_pin: sata4-power-pin { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + sata1_pres_pin: sata1-pres-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + + sata2_pres_pin: sata2-pres-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + sata3_pres_pin: sata3-pres-pin { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + sata4_pres_pin: sata4-pres-pin { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + err_led_pin: err-led-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + clocks = <&coreclk 0>; + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ + reg = <1>; + }; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + /* Front USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + clock-frequency = <400000>; + status = "okay"; + + isl12057: isl12057@68 { + compatible = "isl,isl12057"; + reg = <0x68>; + }; + + /* Controller for rear fan #1 of 3 (Protechnic + * MGT4012XB-O20, 8000RPM) near eSATA port */ + g762_fan1: g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + + /* Controller for rear (center) fan #2 of 3 */ + g762_fan2: g762@48 { + compatible = "gmt,g762"; + reg = <0x48>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + + /* Controller for rear fan #3 of 3 */ + g762_fan3: g762@49 { + compatible = "gmt,g762"; + reg = <0x49>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + + /* Temperature sensor */ + g751: g751@4c { + compatible = "gmt,g751"; + reg = <0x4c>; + }; + }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; /* 1.5MB */ + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; /* 128KB */ + read-only; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; /* 6MB */ + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x400000>; /* 4MB */ + }; + + /* Last MB is for the BBT, i.e. not writable */ + partition@c00000 { + label = "ubifs"; + reg = <0x0c00000 0x7400000>; /* 116MB */ + }; + }; + }; + }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&sata1_led_pin &sata2_led_pin &err_led_pin + &sata3_led_pin &sata4_led_pin>; + pinctrl-names = "default"; + + red-sata1-led { + label = "rn2120:red:sata1"; + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red-sata2-led { + label = "rn2120:red:sata2"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red-sata3-led { + label = "rn2120:red:sata3"; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red-sata4-led { + label = "rn2120:red:sata4"; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red-err-led { + label = "rn2120:red:err"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&power_button_pin &reset_button_pin>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = <KEY_POWER>; + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + }; + + reset-button { + label = "Reset Button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&poweroff>; + pinctrl-names = "default"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 5695afc..99bcf76 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -103,8 +103,7 @@ green_led { label = "green_led"; gpios = <&gpio1 21 1>; - default-state = "off"; - linux,default-trigger = "heartbeat"; + default-state = "keep"; }; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 281c644..b8b84a2 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -42,13 +42,14 @@ wt-override; }; - interrupt-controller@20000 { - reg = <0x20a00 0x2d0>, <0x21070 0x58>; + i2c0: i2c@11000 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; }; - armada-370-xp-pmsu@22000 { - compatible = "marvell,armada-370-xp-pmsu"; - reg = <0x22100 0x430>, <0x20800 0x20>; + i2c1: i2c@11100 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x100>; }; serial@12200 { @@ -68,10 +69,16 @@ status = "disabled"; }; - timer@20300 { - compatible = "marvell,armada-xp-timer"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; + system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x500>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-xp-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; }; coreclk: mvebu-sar@18230 { @@ -80,6 +87,13 @@ #clock-cells = <1>; }; + thermal@182b0 { + compatible = "marvell,armadaxp-thermal"; + reg = <0x182b0 0x4 + 0x184d0 0x4>; + status = "okay"; + }; + cpuclk: clock-complex@18700 { #clock-cells = <1>; compatible = "marvell,armada-xp-cpu-clock"; @@ -87,16 +101,19 @@ clocks = <&coreclk 1>; }; - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-xp-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; + interrupt-controller@20000 { + reg = <0x20a00 0x2d0>, <0x21070 0x58>; }; - system-controller@18200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x500>; + timer@20300 { + compatible = "marvell,armada-xp-timer"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + + armada-370-xp-pmsu@22000 { + compatible = "marvell,armada-370-xp-pmsu"; + reg = <0x22100 0x400>, <0x20800 0x20>; }; eth2: ethernet@30000 { @@ -107,6 +124,22 @@ status = "disabled"; }; + usb@50000 { + clocks = <&gateclk 18>; + }; + + usb@51000 { + clocks = <&gateclk 19>; + }; + + usb@52000 { + compatible = "marvell,orion-ehci"; + reg = <0x52000 0x500>; + interrupts = <47>; + clocks = <&gateclk 20>; + status = "disabled"; + }; + xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 @@ -146,39 +179,6 @@ dmacap,memset; }; }; - - i2c0: i2c@11000 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; - }; - - usb@50000 { - clocks = <&gateclk 18>; - }; - - usb@51000 { - clocks = <&gateclk 19>; - }; - - usb@52000 { - compatible = "marvell,orion-ehci"; - reg = <0x52000 0x500>; - interrupts = <47>; - clocks = <&gateclk 20>; - status = "disabled"; - }; - - thermal@182b0 { - compatible = "marvell,armadaxp-thermal"; - reg = <0x182b0 0x4 - 0x184d0 0x4>; - status = "okay"; - }; }; }; diff --git a/arch/arm/boot/dts/armv7-m.dtsi b/arch/arm/boot/dts/armv7-m.dtsi new file mode 100644 index 0000000..5a660d0 --- /dev/null +++ b/arch/arm/boot/dts/armv7-m.dtsi @@ -0,0 +1,18 @@ +#include "skeleton.dtsi" + +/ { + nvic: nv-interrupt-controller { + compatible = "arm,armv7m-nvic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xe000e100 0xc00>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&nvic>; + ranges; + }; +}; diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi new file mode 100644 index 0000000..2093c4d --- /dev/null +++ b/arch/arm/boot/dts/at91-cosino.dtsi @@ -0,0 +1,122 @@ +/* + * at91-cosino.dtsi - Device Tree file for Cosino core module + * + * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it> + * HCE Engineering + * + * Derived from at91sam9x5ek.dtsi by: + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> + * + * Licensed under GPLv2 or later. + */ + +#include "at91sam9g35.dtsi" + +/ { + model = "HCE Cosino core module"; + compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait"; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + mmc0: mmc@f0008000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + usart0: serial@f801c000 { + status = "okay"; + }; + + i2c0: i2c@f8010000 { + status = "okay"; + }; + + adc0: adc@f804c000 { + atmel,adc-clock-rate = <1000000>; + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + pinctrl@fffff400 { + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */ + }; + }; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; /* Enable PMECC */ + atmel,pmecc-cap = <4>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0x80000>; + }; + + ubootenv@c0000 { + label = "U-Boot Env"; + reg = <0xc0000 0x140000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts new file mode 100644 index 0000000..f9415dd --- /dev/null +++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts @@ -0,0 +1,84 @@ +/* + * at91-cosino_mega2560.dts - Device Tree file for Cosino board with + * Mega 2560 extension + * + * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it> + * HCE Engineering + * + * Derived from at91sam9g35ek.dts by: + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; +#include "at91-cosino.dtsi" + +/ { + model = "HCE Cosino Mega 2560"; + compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + + adc0: adc@f804c000 { + atmel,adc-clock-rate = <1000000>; + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + + tsadcc: tsadcc@f804c000 { + status = "okay"; + }; + + rtc@fffffeb0 { + status = "okay"; + }; + + usart1: serial@f8020000 { + status = "okay"; + }; + + usart2: serial@f8024000 { + status = "okay"; + }; + + usb2: gadget@f803c000 { + atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc1: mmc@f000c000 { + pinctrl-0 = < + &pinctrl_mmc1_slot0_clk_cmd_dat0 + &pinctrl_mmc1_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + non-removable; + }; + }; + }; + + usb0: ohci@00600000 { + status = "okay"; + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */ + &pioD 19 GPIO_ACTIVE_LOW + &pioD 20 GPIO_ACTIVE_LOW + >; + }; + + usb1: ehci@00700000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts new file mode 100644 index 0000000..5576ae8 --- /dev/null +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -0,0 +1,185 @@ +/* + * at91-qil_a9260.dts - Device Tree file for Calao QIL A9260 board + * + * Copyright (C) 2011-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Licensed under GPLv2. + */ +/dts-v1/; +#include "at91sam9260.dtsi" +/ { + model = "Calao QIL A9260"; + compatible = "calao,qil-a9260", "atmel,at91sam9260", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc0: mmc@fffa8000 { + pinctrl-0 = < + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot0_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; + }; + + usart1: serial@fffb4000 { + pinctrl-0 = + <&pinctrl_usart1 + &pinctrl_usart1_rts + &pinctrl_usart1_cts>; + status = "okay"; + }; + + usart2: serial@fffb8000 { + pinctrl-0 = + <&pinctrl_usart2 + &pinctrl_usart2_rts + &pinctrl_usart2_cts>; + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + spi0: spi@fffc8000 { + status = "okay"; + cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>; + + m41t94@0 { + compatible = "st,m41t94"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@a0000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@c0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4c0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7cc0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led { + label = "user_led"; + gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user_pb { + label = "user_pb"; + gpios = <&pioB 10 GPIO_ACTIVE_LOW>; + linux,code = <28>; + gpio-key,wakeup; + }; + }; + + i2c@0 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index f770655..c61b16f 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -191,12 +191,12 @@ AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */ }; - pinctrl_uart0_rts: uart0_rts-0 { + pinctrl_uart0_cts: uart0_cts-0 { atmel,pins = <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ }; - pinctrl_uart0_cts: uart0_cts-0 { + pinctrl_uart0_rts: uart0_rts-0 { atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ }; diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index d2d72c3..df6b0aa 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -29,10 +29,22 @@ ahb { apb { - dbgu: serial@fffff200 { + usb1: gadget@fffb0000 { + atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; + atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + + phy0: ethernet-phy { + interrupt-parent = <&pioC>; + interrupts = <4 IRQ_TYPE_EDGE_BOTH>; + }; + }; + usart1: serial@fffc4000 { pinctrl-0 = <&pinctrl_uart1 @@ -44,16 +56,6 @@ status = "okay"; }; - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffb0000 { - atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - spi0: spi@fffe0000 { status = "okay"; cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; @@ -63,12 +65,45 @@ reg = <0>; }; }; + + dbgu: serial@fffff200 { + status = "okay"; + }; }; usb0: ohci@00300000 { num-ports = <2>; status = "okay"; }; + + nor_flash@10000000 { + compatible = "cfi-flash"; + reg = <0x10000000 0x800000>; + linux,mtd-name = "physmap-flash.0"; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + barebox@0 { + label = "barebox"; + reg = <0x00000 0x40000>; + }; + + bareboxenv@40000 { + label = "bareboxenv"; + reg = <0x40000 0x10000>; + }; + + kernel@50000 { + label = "kernel"; + reg = <0x50000 0x300000>; + }; + + root@350000 { + label = "root"; + reg = <0x350000 0x4B0000>; + }; + }; }; leds { diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index d5bd65f..c8fa9b9 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -30,6 +30,7 @@ i2c0 = &i2c0; ssc0 = &ssc0; ssc1 = &ssc1; + pwm0 = &pwm0; }; cpus { #address-cells = <0>; @@ -366,6 +367,34 @@ }; }; + fb { + pinctrl_fb: fb-0 { + atmel,pins = + <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A */ + AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB9 periph B */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 periph A */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 periph A */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A */ + AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A */ + AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A */ + AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC12 periph B */ + AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC18 periph A */ + AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A */ + AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC24 periph A */ + AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC17 periph B */ + AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC26 periph A */ + AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */ + }; + }; + pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; @@ -547,6 +576,23 @@ pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; }; + + pwm0: pwm@fffb8000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xfffb8000 0x300>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + fb0: fb@0x00700000 { + compatible = "atmel,at91sam9263-lcdc"; + reg = <0x00700000 0x1000>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + status = "disabled"; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 70f835b..15009c9 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -95,6 +95,36 @@ }; }; + fb0: fb@0x00700000 { + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <1>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <4965000>; + hactive = <240>; + vactive = <320>; + hback-porch = <1>; + hfront-porch = <33>; + vback-porch = <1>; + vfront-porch = <0>; + hsync-len = <5>; + vsync-len = <1>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; + }; + nand0: nand@40000000 { nand-bus-width = <8>; nand-ecc-mode = "soft"; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index c3e5148..ef0857c 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -37,6 +37,7 @@ i2c1 = &i2c1; ssc0 = &ssc0; ssc1 = &ssc1; + pwm0 = &pwm0; }; cpus { #address-cells = <0>; @@ -143,6 +144,22 @@ }; }; + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */ + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */ + }; + }; + usart0 { pinctrl_usart0: usart0-0 { atmel,pins = @@ -425,6 +442,42 @@ }; }; + fb { + pinctrl_fb: fb-0 { + atmel,pins = + <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */ + AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */ + AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */ + AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */ + AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */ + AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */ + AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */ + AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */ + AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */ + AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */ + AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */ + AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */ + AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */ + AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */ + AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */ + AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */ + AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */ + AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */ + AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */ + AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */ + AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ + AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */ + AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ + AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ + AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ + AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ + AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ + AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ + AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ + AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ + }; + }; + pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; @@ -542,6 +595,8 @@ compatible = "atmel,at91sam9g10-i2c"; reg = <0xfff84000 0x100>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -551,6 +606,8 @@ compatible = "atmel,at91sam9g10-i2c"; reg = <0xfff88000 0x100>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -614,10 +671,19 @@ }; }; + pwm0: pwm@fffb8000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xfffb8000 0x300>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + status = "disabled"; + }; + mmc0: mmc@fff80000 { compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; #address-cells = <1>; @@ -629,6 +695,7 @@ compatible = "atmel,hsmci"; reg = <0xfffd0000 0x600>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; dma-names = "rxtx"; #address-cells = <1>; @@ -727,6 +794,15 @@ }; }; + fb0: fb@0x00500000 { + compatible = "atmel,at91sam9g45-lcdc"; + reg = <0x00500000 0x1000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + status = "disabled"; + }; + nand0: nand@40000000 { compatible = "atmel,at91rm9200-nand"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index a4b00e5..7ff665a 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -105,6 +105,14 @@ AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */ }; }; + + pwm0 { + pinctrl_pwm_leds: pwm-led { + atmel,pins = + <AT91_PIOD 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD0 periph B */ + AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PD31 periph B */ + }; + }; }; spi0: spi@fffa4000{ @@ -121,6 +129,42 @@ atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>; status = "okay"; }; + + pwm0: pwm@fffb8000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_leds>; + }; + }; + + fb0: fb@0x00500000 { + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <32>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <9>; + atmel,lcd-wiring-mode = "RGB"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hback-porch = <1>; + hfront-porch = <1>; + vback-porch = <40>; + vfront-porch = <1>; + hsync-len = <45>; + vsync-len = <1>; + }; + }; + }; }; nand0: nand@40000000 { @@ -165,16 +209,22 @@ gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; + }; + + pwmleds { + compatible = "pwm-leds"; d6 { label = "d6"; - gpios = <&pioD 0 GPIO_ACTIVE_LOW>; + pwms = <&pwm0 3 5000 0>; + max-brightness = <255>; linux,default-trigger = "nand-disk"; }; d7 { label = "d7"; - gpios = <&pioD 31 GPIO_ACTIVE_LOW>; + pwms = <&pwm0 1 5000 0>; + max-brightness = <255>; linux,default-trigger = "mmc0"; }; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 6224f9f..7248270 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -33,6 +33,7 @@ i2c0 = &i2c0; i2c1 = &i2c1; ssc0 = &ssc0; + pwm0 = &pwm0; }; cpus { #address-cells = <0>; @@ -542,6 +543,14 @@ reg = <0xfffffe40 0x10>; status = "disabled"; }; + + pwm0: pwm@f8034000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xf8034000 0x300>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + status = "disabled"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 40267a1..6e5e9cf 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -35,6 +35,7 @@ i2c1 = &i2c1; i2c2 = &i2c2; ssc0 = &ssc0; + pwm0 = &pwm0; }; cpus { #address-cells = <0>; @@ -762,6 +763,14 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; status = "disabled"; }; + + pwm0: pwm@f8034000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xf8034000 0x300>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + status = "disabled"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 978bab4..f8674bc 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -27,6 +27,15 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + clocks = <&clks 12>; + operating-points = < + /* kHz uV */ + 200000 1025000 + 400000 1025000 + 600000 1050000 + 800000 1100000 + >; + clock-latency = <150000>; }; }; @@ -69,6 +78,7 @@ cphifbg@88030000 { compatible = "sirf,prima2-cphifbg"; reg = <0x88030000 0x1000>; + clocks = <&clks 42>; }; }; @@ -546,6 +556,12 @@ sirf,function = "usp1"; }; }; + usp1_uart_nostreamctrl_pins_a: usp1@1 { + usp1 { + sirf,pins = "usp1_uart_nostreamctrl_grp"; + sirf,function = "usp1_uart_nostreamctrl"; + }; + }; usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 { usb0_upli_drvbus { sirf,pins = "usb0_upli_drvbusgrp"; @@ -636,6 +652,7 @@ reg = <0x56100000 0x100000>; interrupts = <38>; status = "disabled"; + bus-width = <4>; clocks = <&clks 36>; }; @@ -645,6 +662,7 @@ reg = <0x56200000 0x100000>; interrupts = <23>; status = "disabled"; + bus-width = <4>; clocks = <&clks 37>; }; @@ -654,6 +672,7 @@ reg = <0x56300000 0x100000>; interrupts = <23>; status = "disabled"; + bus-width = <4>; clocks = <&clks 37>; }; @@ -663,6 +682,7 @@ reg = <0x56500000 0x100000>; interrupts = <39>; status = "disabled"; + bus-width = <4>; clocks = <&clks 38>; }; @@ -697,6 +717,12 @@ interrupts = <52 53 54>; }; + minigpsrtc@2000 { + compatible = "sirf,prima2-minigpsrtc"; + reg = <0x2000 0x1000>; + interrupts = <54>; + }; + pwrc@3000 { compatible = "sirf,prima2-pwrc"; reg = <0x3000 0x1000>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 6e9deb7..2a3b1c1 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -23,10 +23,15 @@ &gpio { pinctrl-names = "default"; - pinctrl-0 = <&alt0 &alt3>; + pinctrl-0 = <&gpioout &alt0 &alt3>; + + gpioout: gpioout { + brcm,pins = <6>; + brcm,function = <1>; /* GPIO out */ + }; alt0: alt0 { - brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 14 15 40 45>; + brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; brcm,function = <4>; /* alt0 */ }; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index aa537ed..b021c96 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -107,6 +107,12 @@ clocks = <&clk_mmc>; status = "disabled"; }; + + usb { + compatible = "brcm,bcm2835-usb"; + reg = <0x7e980000 0x10000>; + interrupts = <1 9>; + }; }; clocks { diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts new file mode 100644 index 0000000..c72bfd4 --- /dev/null +++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts @@ -0,0 +1,29 @@ +/* + * Device Tree file for Sony NSZ-GS7 + * + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "berlin2.dtsi" + +/ { + model = "Sony NSZ-GS7"; + compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; +}; + +&uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi new file mode 100644 index 0000000..56a1af2 --- /dev/null +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -0,0 +1,227 @@ +/* + * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC + * + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * + * based on GPL'ed 2.6 kernel sources + * (c) Marvell International Ltd. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Marvell Armada 1500 (BG2) SoC"; + compatible = "marvell,berlin2", "marvell,berlin"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "marvell,pj4b"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <0>; + }; + + cpu@1 { + compatible = "marvell,pj4b"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <1>; + }; + }; + + clocks { + smclk: sysmgr-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + cfgclk: cfg-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + sysclk: system-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + ranges = <0 0xf7000000 0x1000000>; + + l2: l2-cache-controller@ac0000 { + compatible = "marvell,tauros3-cache", "arm,pl310-cache"; + reg = <0xac0000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + gic: interrupt-controller@ad1000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xad1000 0x1000>, <0xad0100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + local-timer@ad0600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xad0600 0x20>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysclk>; + }; + + apb@e80000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xe80000 0x10000>; + interrupt-parent = <&aic>; + + timer0: timer@2c00 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c00 0x14>; + interrupts = <8>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "okay"; + }; + + timer1: timer@2c14 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c14 0x14>; + interrupts = <9>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "okay"; + }; + + timer2: timer@2c28 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c28 0x14>; + interrupts = <10>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "disabled"; + }; + + timer3: timer@2c3c { + compatible = "snps,dw-apb-timer"; + reg = <0x2c3c 0x14>; + interrupts = <11>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "disabled"; + }; + + timer4: timer@2c50 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c50 0x14>; + interrupts = <12>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "disabled"; + }; + + timer5: timer@2c64 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c64 0x14>; + interrupts = <13>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "disabled"; + }; + + timer6: timer@2c78 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c78 0x14>; + interrupts = <14>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "disabled"; + }; + + timer7: timer@2c8c { + compatible = "snps,dw-apb-timer"; + reg = <0x2c8c 0x14>; + interrupts = <15>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "disabled"; + }; + + aic: interrupt-controller@3000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x3000 0xc00>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + apb@fc0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xfc0000 0x10000>; + interrupt-parent = <&sic>; + + uart0: serial@9000 { + compatible = "snps,dw-apb-uart"; + reg = <0x9000 0x100>; + reg-shift = <2>; + reg-io-width = <1>; + interrupts = <8>; + clocks = <&smclk>; + status = "disabled"; + }; + + uart1: serial@a000 { + compatible = "snps,dw-apb-uart"; + reg = <0xa000 0x100>; + reg-shift = <2>; + reg-io-width = <1>; + interrupts = <9>; + clocks = <&smclk>; + status = "disabled"; + }; + + uart2: serial@b000 { + compatible = "snps,dw-apb-uart"; + reg = <0xb000 0x100>; + reg-shift = <2>; + reg-io-width = <1>; + interrupts = <10>; + clocks = <&smclk>; + status = "disabled"; + }; + + sic: interrupt-controller@e000 { + compatible = "snps,dw-apb-ictl"; + reg = <0xe000 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts new file mode 100644 index 0000000..bcd81ff --- /dev/null +++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts @@ -0,0 +1,29 @@ +/* + * Device Tree file for Google Chromecast + * + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "berlin2cd.dtsi" + +/ { + model = "Google Chromecast"; + compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; +}; + +&uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi new file mode 100644 index 0000000..094968c --- /dev/null +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -0,0 +1,210 @@ +/* + * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC + * + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * + * based on GPL'ed 2.6 kernel sources + * (c) Marvell International Ltd. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Marvell Armada 1500-mini (BG2CD) SoC"; + compatible = "marvell,berlin2cd", "marvell,berlin"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <0>; + }; + }; + + clocks { + smclk: sysmgr-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + cfgclk: cfg-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <75000000>; + }; + + sysclk: system-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + ranges = <0 0xf7000000 0x1000000>; + + l2: l2-cache-controller@ac0000 { + compatible = "arm,pl310-cache"; + reg = <0xac0000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + gic: interrupt-controller@ad1000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xad1000 0x1000>, <0xad0100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + local-timer@ad0600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xad0600 0x20>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysclk>; + }; + + apb@e80000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xe80000 0x10000>; + interrupt-parent = <&aic>; + + timer0: timer@2c00 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c00 0x14>; + interrupts = <8>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "okay"; + }; + + timer1: timer@2c14 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c14 0x14>; + interrupts = <9>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "okay"; + }; + + timer2: timer@2c28 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c28 0x14>; + interrupts = <10>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "disabled"; + }; + + timer3: timer@2c3c { + compatible = "snps,dw-apb-timer"; + reg = <0x2c3c 0x14>; + interrupts = <11>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "disabled"; + }; + + timer4: timer@2c50 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c50 0x14>; + interrupts = <12>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "disabled"; + }; + + timer5: timer@2c64 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c64 0x14>; + interrupts = <13>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "disabled"; + }; + + timer6: timer@2c78 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c78 0x14>; + interrupts = <14>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "disabled"; + }; + + timer7: timer@2c8c { + compatible = "snps,dw-apb-timer"; + reg = <0x2c8c 0x14>; + interrupts = <15>; + clocks = <&cfgclk>; + clock-names = "timer"; + status = "disabled"; + }; + + aic: interrupt-controller@3000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x3000 0xc00>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + apb@fc0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xfc0000 0x10000>; + interrupt-parent = <&sic>; + + uart0: serial@9000 { + compatible = "snps,dw-apb-uart"; + reg = <0x9000 0x100>; + reg-shift = <2>; + reg-io-width = <1>; + interrupts = <8>; + clocks = <&smclk>; + status = "disabled"; + }; + + uart1: serial@a000 { + compatible = "snps,dw-apb-uart"; + reg = <0xa000 0x100>; + reg-shift = <2>; + reg-io-width = <1>; + interrupts = <9>; + clocks = <&smclk>; + status = "disabled"; + }; + + sic: interrupt-controller@e000 { + compatible = "snps,dw-apb-ictl"; + reg = <0xe000 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 588ce58..1e11e5a 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -101,6 +101,9 @@ pinctrl-names = "default"; pinctrl-0 = <&mii_pins>; }; + gpio: gpio@1e26000 { + status = "okay"; + }; }; nand_cs3@62000000 { status = "okay"; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 8d17346..b695548 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -8,6 +8,7 @@ * option) any later version. */ #include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> / { arm { @@ -256,6 +257,19 @@ 36 >; }; + gpio: gpio@1e26000 { + compatible = "ti,dm6441-gpio"; + gpio-controller; + reg = <0x226000 0x1000>; + interrupts = <42 IRQ_TYPE_EDGE_BOTH + 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH + 45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH + 47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH + 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>; + ti,ngpio = <144>; + ti,davinci-gpio-unbanked = <0>; + status = "disabled"; + }; }; nand_cs3@62000000 { compatible = "ti,davinci-nand"; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 8349a24..7a70f4ca 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -23,7 +23,7 @@ power { label = "Power"; gpios = <&gpio0 18 1>; - linux,default-trigger = "default-on"; + default-state = "keep"; }; }; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 113a8bc..8de1031 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -107,51 +107,29 @@ 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ - mbusc: mbus-ctrl@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x800100 0x8>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; + spi0: spi-ctrl@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <6>; + reg = <0x10600 0x28>; clocks = <&core_clk 0>; + pinctrl-0 = <&pmx_spi0>; + pinctrl-names = "default"; + status = "disabled"; }; - intc: main-interrupt-ctrl@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <0>; - marvell,#interrupts = <5>; - }; - - core_clk: core-clocks@d0214 { - compatible = "marvell,dove-core-clock"; - reg = <0xd0214 0x4>; - #clock-cells = <1>; - }; - - gate_clk: clock-gating-ctrl@d0038 { - compatible = "marvell,dove-gating-clock"; - reg = <0xd0038 0x4>; + i2c0: i2c-ctrl@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <11>; + clock-frequency = <400000>; + timeout-ms = <1000>; clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - thermal: thermal-diode@d001c { - compatible = "marvell,dove-thermal"; - reg = <0xd001c 0x0c>, <0xd005c 0x08>; + status = "disabled"; }; uart0: serial@12000 { @@ -192,34 +170,224 @@ status = "disabled"; }; - gpio0: gpio-ctrl@d0400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xd0400 0x20>; - ngpios = <32>; + spi1: spi-ctrl@14600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <5>; + reg = <0x14600 0x28>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + mbusc: mbus-ctrl@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x80>, <0x800100 0x8>; + }; + + bridge_intc: bridge-interrupt-ctrl@20110 { + compatible = "marvell,orion-bridge-intc"; interrupt-controller; - #interrupt-cells = <2>; - interrupts = <12>, <13>, <14>, <60>; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <0>; + marvell,#interrupts = <5>; }; - gpio1: gpio-ctrl@d0420 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xd0420 0x20>; - ngpios = <32>; + intc: main-interrupt-ctrl@20200 { + compatible = "marvell,orion-intc"; interrupt-controller; - #interrupt-cells = <2>; - interrupts = <61>; + #interrupt-cells = <1>; + reg = <0x20200 0x10>, <0x20210 0x10>; }; - gpio2: gpio-ctrl@e8400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xe8400 0x0c>; - ngpios = <8>; + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; + + crypto: crypto-engine@30000 { + compatible = "marvell,orion-crypto"; + reg = <0x30000 0x10000>, + <0xffffe000 0x800>; + reg-names = "regs", "sram"; + interrupts = <31>; + clocks = <&gate_clk 15>; + status = "okay"; + }; + + ehci0: usb-host@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <24>; + clocks = <&gate_clk 0>; + status = "okay"; + }; + + ehci1: usb-host@51000 { + compatible = "marvell,orion-ehci"; + reg = <0x51000 0x1000>; + interrupts = <25>; + clocks = <&gate_clk 1>; + status = "okay"; + }; + + xor0: dma-engine@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60a00 0x100>; + clocks = <&gate_clk 23>; + status = "okay"; + + channel0 { + interrupts = <39>; + dmacap,memcpy; + dmacap,xor; + }; + + channel1 { + interrupts = <40>; + dmacap,memcpy; + dmacap,xor; + }; + }; + + xor1: dma-engine@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gate_clk 24>; + status = "okay"; + + channel0 { + interrupts = <42>; + dmacap,memcpy; + dmacap,xor; + }; + + channel1 { + interrupts = <43>; + dmacap,memcpy; + dmacap,xor; + }; + }; + + sdio1: sdio-host@90000 { + compatible = "marvell,dove-sdhci"; + reg = <0x90000 0x100>; + interrupts = <36>, <38>; + clocks = <&gate_clk 9>; + pinctrl-0 = <&pmx_sdio1>; + pinctrl-names = "default"; + status = "disabled"; + }; + + eth: ethernet-ctrl@72000 { + compatible = "marvell,orion-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72000 0x4000>; + clocks = <&gate_clk 2>; + marvell,tx-checksum-limit = <1600>; + status = "disabled"; + + ethernet-port@0 { + device_type = "network"; + compatible = "marvell,orion-eth-port"; + reg = <0>; + interrupts = <29>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <ðphy>; + }; + }; + + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <30>; + clocks = <&gate_clk 2>; + status = "disabled"; + + ethphy: ethernet-phy { + device_type = "ethernet-phy"; + /* set phy address in board file */ + }; + }; + + sdio0: sdio-host@92000 { + compatible = "marvell,dove-sdhci"; + reg = <0x92000 0x100>; + interrupts = <35>, <37>; + clocks = <&gate_clk 8>; + pinctrl-0 = <&pmx_sdio0>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sata0: sata-host@a0000 { + compatible = "marvell,orion-sata"; + reg = <0xa0000 0x2400>; + interrupts = <62>; + clocks = <&gate_clk 3>; + phys = <&sata_phy0>; + phy-names = "port0"; + nr-ports = <1>; + status = "disabled"; + }; + + sata_phy0: sata-phy@a2000 { + compatible = "marvell,mvebu-sata-phy"; + reg = <0xa2000 0x0334>; + clocks = <&gate_clk 3>; + clock-names = "sata"; + #phy-cells = <0>; + status = "ok"; + }; + + audio0: audio-controller@b0000 { + compatible = "marvell,dove-audio"; + reg = <0xb0000 0x2210>; + interrupts = <19>, <20>; + clocks = <&gate_clk 12>; + clock-names = "internal"; + status = "disabled"; + }; + + audio1: audio-controller@b4000 { + compatible = "marvell,dove-audio"; + reg = <0xb4000 0x2210>; + interrupts = <21>, <22>; + clocks = <&gate_clk 13>; + clock-names = "internal"; + status = "disabled"; + }; + + thermal: thermal-diode@d001c { + compatible = "marvell,dove-thermal"; + reg = <0xd001c 0x0c>, <0xd005c 0x08>; + }; + + gate_clk: clock-gating-ctrl@d0038 { + compatible = "marvell,dove-gating-clock"; + reg = <0xd0038 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; + + pmu_intc: pmu-interrupt-ctrl@d0050 { + compatible = "marvell,dove-pmu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd0050 0x8>; + interrupts = <33>; + marvell,#interrupts = <7>; }; pinctrl: pin-ctrl@d0200 { @@ -413,193 +581,47 @@ }; }; - spi0: spi-ctrl@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <6>; - reg = <0x10600 0x28>; - clocks = <&core_clk 0>; - pinctrl-0 = <&pmx_spi0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - spi1: spi-ctrl@14600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <5>; - reg = <0x14600 0x28>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - i2c0: i2c-ctrl@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <11>; - clock-frequency = <400000>; - timeout-ms = <1000>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - ehci0: usb-host@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <24>; - clocks = <&gate_clk 0>; - status = "okay"; - }; - - ehci1: usb-host@51000 { - compatible = "marvell,orion-ehci"; - reg = <0x51000 0x1000>; - interrupts = <25>; - clocks = <&gate_clk 1>; - status = "okay"; - }; - - sdio0: sdio-host@92000 { - compatible = "marvell,dove-sdhci"; - reg = <0x92000 0x100>; - interrupts = <35>, <37>; - clocks = <&gate_clk 8>; - pinctrl-0 = <&pmx_sdio0>; - pinctrl-names = "default"; - status = "disabled"; + core_clk: core-clocks@d0214 { + compatible = "marvell,dove-core-clock"; + reg = <0xd0214 0x4>; + #clock-cells = <1>; }; - sdio1: sdio-host@90000 { - compatible = "marvell,dove-sdhci"; - reg = <0x90000 0x100>; - interrupts = <36>, <38>; - clocks = <&gate_clk 9>; - pinctrl-0 = <&pmx_sdio1>; - pinctrl-names = "default"; - status = "disabled"; + gpio0: gpio-ctrl@d0400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xd0400 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <12>, <13>, <14>, <60>; }; - sata0: sata-host@a0000 { - compatible = "marvell,orion-sata"; - reg = <0xa0000 0x2400>; - interrupts = <62>; - clocks = <&gate_clk 3>; - nr-ports = <1>; - status = "disabled"; + gpio1: gpio-ctrl@d0420 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xd0420 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <61>; }; rtc: real-time-clock@d8500 { compatible = "marvell,orion-rtc"; reg = <0xd8500 0x20>; + interrupt-parent = <&pmu_intc>; + interrupts = <5>; }; - crypto: crypto-engine@30000 { - compatible = "marvell,orion-crypto"; - reg = <0x30000 0x10000>, - <0xffffe000 0x800>; - reg-names = "regs", "sram"; - interrupts = <31>; - clocks = <&gate_clk 15>; - status = "okay"; - }; - - xor0: dma-engine@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60a00 0x100>; - clocks = <&gate_clk 23>; - status = "okay"; - - channel0 { - interrupts = <39>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <40>; - dmacap,memcpy; - dmacap,xor; - }; - }; - - xor1: dma-engine@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gate_clk 24>; - status = "okay"; - - channel0 { - interrupts = <42>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <43>; - dmacap,memcpy; - dmacap,xor; - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <30>; - clocks = <&gate_clk 2>; - status = "disabled"; - - ethphy: ethernet-phy { - device-type = "ethernet-phy"; - /* set phy address in board file */ - }; - }; - - eth: ethernet-ctrl@72000 { - compatible = "marvell,orion-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - clocks = <&gate_clk 2>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - ethernet-port@0 { - device_type = "network"; - compatible = "marvell,orion-eth-port"; - reg = <0>; - interrupts = <29>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - phy-handle = <ðphy>; - }; - }; - - audio0: audio-controller@b0000 { - compatible = "marvell,dove-audio"; - reg = <0xb0000 0x2210>; - interrupts = <19>, <20>; - clocks = <&gate_clk 12>; - clock-names = "internal"; - status = "disabled"; - }; - - audio1: audio-controller@b4000 { - compatible = "marvell,dove-audio"; - reg = <0xb4000 0x2210>; - interrupts = <21>, <22>; - clocks = <&gate_clk 13>; - clock-names = "internal"; - status = "disabled"; + gpio2: gpio-ctrl@e8400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xe8400 0x0c>; + ngpios = <8>; }; }; }; diff --git a/arch/arm/boot/dts/efm32gg-dk3750.dts b/arch/arm/boot/dts/efm32gg-dk3750.dts new file mode 100644 index 0000000..aa5c0f6 --- /dev/null +++ b/arch/arm/boot/dts/efm32gg-dk3750.dts @@ -0,0 +1,86 @@ +/* + * Device tree for EFM32GG-DK3750 development board. + * + * Documentation available from + * http://www.silabs.com/Support%20Documents/TechnicalDocs/efm32gg-dk3750-ug.pdf + */ + +/dts-v1/; +#include "efm32gg.dtsi" + +/ { + model = "Energy Micro Giant Gecko Development Kit"; + compatible = "efm32,dk3750"; + + chosen { + bootargs = "console=ttyefm4,115200 init=/linuxrc ignore_loglevel ihash_entries=64 dhash_entries=64 earlyprintk uclinux.physaddr=0x8c400000 root=/dev/mtdblock0"; + }; + + memory { + reg = <0x88000000 0x400000>; + }; + + soc { + adc@40002000 { + status = "ok"; + }; + + i2c@4000a000 { + location = <3>; + status = "ok"; + + temp@48 { + compatible = "st,stds75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "microchip,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + }; + + spi0: spi@4000c000 { /* USART0 */ + cs-gpios = <&gpio 68 1>; // E4 + location = <1>; + status = "ok"; + + microsd@0 { + compatible = "mmc-spi-slot"; + spi-max-frequency = <100000>; + voltage-ranges = <3200 3400>; + broken-cd; + reg = <0>; + }; + }; + + spi1: spi@4000c400 { /* USART1 */ + cs-gpios = <&gpio 51 1>; // D3 + location = <1>; + status = "ok"; + + ks8851@0 { + compatible = "ks8851"; + spi-max-frequency = <6000000>; + reg = <0>; + interrupt-parent = <&boardfpga>; + interrupts = <4>; + }; + }; + + uart4: uart@4000e400 { /* UART1 */ + location = <2>; + status = "ok"; + }; + + boardfpga: boardfpga { + compatible = "efm32board"; + reg = <0x80000000 0x400>; + irq-gpios = <&gpio 64 1>; + interrupt-controller; + #interrupt-cells = <1>; + status = "ok"; + }; + }; +}; diff --git a/arch/arm/boot/dts/efm32gg.dtsi b/arch/arm/boot/dts/efm32gg.dtsi new file mode 100644 index 0000000..a342ab0 --- /dev/null +++ b/arch/arm/boot/dts/efm32gg.dtsi @@ -0,0 +1,172 @@ +/* + * Device tree for Energy Micro EFM32 Giant Gecko SoC. + * + * Documentation available from + * http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf + */ +#include "armv7-m.dtsi" +#include "dt-bindings/clock/efm32-cmu.h" + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + }; + + soc { + adc: adc@40002000 { + compatible = "efm32,adc"; + reg = <0x40002000 0x400>; + interrupts = <7>; + clocks = <&cmu clk_HFPERCLKADC0>; + status = "disabled"; + }; + + gpio: gpio@40006000 { + compatible = "efm32,gpio"; + reg = <0x40006000 0x1000>; + interrupts = <1 11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&cmu clk_HFPERCLKGPIO>; + status = "ok"; + }; + + i2c0: i2c@4000a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "efm32,i2c"; + reg = <0x4000a000 0x400>; + interrupts = <9>; + clocks = <&cmu clk_HFPERCLKI2C0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@4000a400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "efm32,i2c"; + reg = <0x4000a400 0x400>; + interrupts = <10>; + clocks = <&cmu clk_HFPERCLKI2C1>; + clock-frequency = <100000>; + status = "disabled"; + }; + + spi0: spi@4000c000 { /* USART0 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "efm32,spi"; + reg = <0x4000c000 0x400>; + interrupts = <3 4>; + clocks = <&cmu clk_HFPERCLKUSART0>; + status = "disabled"; + }; + + spi1: spi@4000c400 { /* USART1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "efm32,spi"; + reg = <0x4000c400 0x400>; + interrupts = <15 16>; + clocks = <&cmu clk_HFPERCLKUSART1>; + status = "disabled"; + }; + + spi2: spi@40x4000c800 { /* USART2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "efm32,spi"; + reg = <0x4000c800 0x400>; + interrupts = <18 19>; + clocks = <&cmu clk_HFPERCLKUSART2>; + status = "disabled"; + }; + + uart0: uart@4000c000 { /* USART0 */ + compatible = "efm32,uart"; + reg = <0x4000c000 0x400>; + interrupts = <3 4>; + clocks = <&cmu clk_HFPERCLKUSART0>; + status = "disabled"; + }; + + uart1: uart@4000c400 { /* USART1 */ + compatible = "efm32,uart"; + reg = <0x4000c400 0x400>; + interrupts = <15 16>; + clocks = <&cmu clk_HFPERCLKUSART1>; + status = "disabled"; + }; + + uart2: uart@40x4000c800 { /* USART2 */ + compatible = "efm32,uart"; + reg = <0x4000c800 0x400>; + interrupts = <18 19>; + clocks = <&cmu clk_HFPERCLKUSART2>; + status = "disabled"; + }; + + uart3: uart@4000e000 { /* UART0 */ + compatible = "efm32,uart"; + reg = <0x4000e000 0x400>; + interrupts = <20 21>; + clocks = <&cmu clk_HFPERCLKUART0>; + status = "disabled"; + }; + + uart4: uart@4000e400 { /* UART1 */ + compatible = "efm32,uart"; + reg = <0x4000e400 0x400>; + interrupts = <22 23>; + clocks = <&cmu clk_HFPERCLKUART1>; + status = "disabled"; + }; + + timer0: timer@40010000 { + compatible = "efm32,timer"; + reg = <0x40010000 0x400>; + interrupts = <2>; + clocks = <&cmu clk_HFPERCLKTIMER0>; + }; + + timer1: timer@40010400 { + compatible = "efm32,timer"; + reg = <0x40010400 0x400>; + interrupts = <12>; + clocks = <&cmu clk_HFPERCLKTIMER1>; + }; + + timer2: timer@40010800 { + compatible = "efm32,timer"; + reg = <0x40010800 0x400>; + interrupts = <13>; + clocks = <&cmu clk_HFPERCLKTIMER2>; + }; + + timer3: timer@40010c00 { + compatible = "efm32,timer"; + reg = <0x40010c00 0x400>; + interrupts = <14>; + clocks = <&cmu clk_HFPERCLKTIMER3>; + }; + + cmu: cmu@400c8000 { + compatible = "efm32gg,cmu"; + reg = <0x400c8000 0x400>; + interrupts = <32>; + #clock-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 861aa7d..50ccd15 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -9,7 +9,10 @@ */ /dts-v1/; -/include/ "emev2.dtsi" +#include "emev2.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> / { model = "EMEV2 KZM9D Board"; @@ -47,11 +50,46 @@ reg = <0x20000000 0x10000>; phy-mode = "mii"; interrupt-parent = <&gpio0>; - interrupts = <1 1>; /* active high */ + interrupts = <1 IRQ_TYPE_EDGE_RISING>; reg-io-width = <4>; smsc,irq-active-high; smsc,irq-push-pull; vddvario-supply = <®_1p8v>; vdd33a-supply = <®_3p3v>; }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + debounce_interval = <50>; + wakeup = <1>; + label = "DSW2-1"; + linux,code = <KEY_1>; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + button@2 { + debounce_interval = <50>; + wakeup = <1>; + label = "DSW2-2"; + linux,code = <KEY_2>; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + button@3 { + debounce_interval = <50>; + wakeup = <1>; + label = "DSW2-3"; + linux,code = <KEY_3>; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + button@4 { + debounce_interval = <50>; + wakeup = <1>; + label = "DSW2-4"; + linux,code = <KEY_4>; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + }; + }; }; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index 9063a443..e37985f 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -8,7 +8,8 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> / { compatible = "renesas,emev2"; @@ -48,44 +49,129 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 120 4>, - <0 121 4>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, + <0 121 IRQ_TYPE_LEVEL_HIGH>; + }; + + smu@e0110000 { + compatible = "renesas,emev2-smu"; + reg = <0xe0110000 0x10000>; + #address-cells = <2>; + #size-cells = <0>; + + c32ki: c32ki { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + pll3_fo: pll3_fo { + compatible = "fixed-factor-clock"; + clocks = <&c32ki>; + clock-div = <1>; + clock-mult = <7000>; + #clock-cells = <0>; + }; + usia_u0_sclkdiv: usia_u0_sclkdiv { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x610 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usib_u1_sclkdiv: usib_u1_sclkdiv { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x65c 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usib_u2_sclkdiv: usib_u2_sclkdiv { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x65c 16>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usib_u3_sclkdiv: usib_u3_sclkdiv { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x660 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usia_u0_sclk: usia_u0_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4a0 1>; + clocks = <&usia_u0_sclkdiv>; + #clock-cells = <0>; + }; + usib_u1_sclk: usib_u1_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4b8 1>; + clocks = <&usib_u1_sclkdiv>; + #clock-cells = <0>; + }; + usib_u2_sclk: usib_u2_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4bc 1>; + clocks = <&usib_u2_sclkdiv>; + #clock-cells = <0>; + }; + usib_u3_sclk: usib_u3_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4c0 1>; + clocks = <&usib_u3_sclkdiv>; + #clock-cells = <0>; + }; + sti_sclk: sti_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x528 1>; + clocks = <&c32ki>; + #clock-cells = <0>; + }; }; sti@e0180000 { compatible = "renesas,em-sti"; reg = <0xe0180000 0x54>; - interrupts = <0 125 0>; + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sti_sclk>; + clock-names = "sclk"; }; uart@e1020000 { compatible = "renesas,em-uart"; reg = <0xe1020000 0x38>; - interrupts = <0 8 0>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usia_u0_sclk>; + clock-names = "sclk"; }; uart@e1030000 { compatible = "renesas,em-uart"; reg = <0xe1030000 0x38>; - interrupts = <0 9 0>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usib_u1_sclk>; + clock-names = "sclk"; }; uart@e1040000 { compatible = "renesas,em-uart"; reg = <0xe1040000 0x38>; - interrupts = <0 10 0>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usib_u2_sclk>; + clock-names = "sclk"; }; uart@e1050000 { compatible = "renesas,em-uart"; reg = <0xe1050000 0x38>; - interrupts = <0 11 0>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usib_u3_sclk>; + clock-names = "sclk"; }; gpio0: gpio@e0050000 { compatible = "renesas,em-gio"; reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; - interrupts = <0 67 0>, <0 68 0>; + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>, + <0 68 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; ngpios = <32>; @@ -95,7 +181,8 @@ gpio1: gpio@e0050080 { compatible = "renesas,em-gio"; reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; - interrupts = <0 69 0>, <0 70 0>; + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>, + <0 70 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; ngpios = <32>; @@ -105,7 +192,8 @@ gpio2: gpio@e0050100 { compatible = "renesas,em-gio"; reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; - interrupts = <0 71 0>, <0 72 0>; + interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>, + <0 72 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; ngpios = <32>; @@ -115,7 +203,8 @@ gpio3: gpio@e0050180 { compatible = "renesas,em-gio"; reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; - interrupts = <0 73 0>, <0 74 0>; + interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>, + <0 74 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; ngpios = <32>; @@ -125,7 +214,8 @@ gpio4: gpio@e0050200 { compatible = "renesas,em-gio"; reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; - interrupts = <0 75 0>, <0 76 0>; + interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>, + <0 76 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; ngpios = <31>; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index a73eeb5..08452e1 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -85,21 +85,21 @@ reg = <0x10023CE0 0x20>; }; - gic:interrupt-controller@10490000 { + gic: interrupt-controller@10490000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x10490000 0x1000>, <0x10480000 0x100>; }; - combiner:interrupt-controller@10440000 { + combiner: interrupt-controller@10440000 { compatible = "samsung,exynos4210-combiner"; #interrupt-cells = <2>; interrupt-controller; reg = <0x10440000 0x1000>; }; - sys_reg: sysreg { + sys_reg: syscon@10010000 { compatible = "samsung,exynos4-sysreg", "syscon"; reg = <0x10010000 0x400>; }; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 1a12fb2..2aa13cb 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -313,7 +313,7 @@ display-timings { native-mode = <&timing0>; timing0: timing { - clock-frequency = <50000>; + clock-frequency = <47500000>; hactive = <1024>; vactive = <600>; hfront-porch = <64>; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 057d682..48ecd7a 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -36,11 +36,11 @@ reg = <0x10023CA0 0x20>; }; - gic:interrupt-controller@10490000 { + gic: interrupt-controller@10490000 { cpu-offset = <0x8000>; }; - combiner:interrupt-controller@10440000 { + combiner: interrupt-controller@10440000 { samsung,combiner-nr = <16>; interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, @@ -51,24 +51,21 @@ mct@10050000 { compatible = "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; - interrupt-controller; - #interrups-cells = <2>; interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>; clocks = <&clock 3>, <&clock 344>; clock-names = "fin_pll", "mct"; mct_map: mct-map { - #interrupt-cells = <2>; + #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &gic 0 69 0>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 0 42 0>, - <0x5 0 &gic 0 48 0>; + interrupt-map = <0 &gic 0 57 0>, + <1 &gic 0 69 0>, + <2 &combiner 12 6>, + <3 &combiner 12 7>, + <4 &gic 0 42 0>, + <5 &gic 0 48 0>; }; }; diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index 6f34d7f..94a43f9 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -22,7 +22,7 @@ / { compatible = "samsung,exynos4212"; - gic:interrupt-controller@10490000 { + gic: interrupt-controller@10490000 { cpu-offset = <0x8000>; }; @@ -34,26 +34,4 @@ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, <0 107 0>, <0 108 0>; }; - - mct@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - interrupt-controller; - #interrups-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &combiner 12 5>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 1 12 0>, - <0x5 0 &gic 1 12 0>; - }; - }; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 46c678e..9804fcb 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -38,9 +38,7 @@ }; }; - mshc@12550000 { - #address-cells = <1>; - #size-cells = <0>; + mmc@12550000 { pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; vmmc-supply = <&ldo20_reg &buck8_reg>; @@ -49,7 +47,6 @@ num-slots = <1>; supports-highspeed; broken-cd; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -119,6 +116,7 @@ max77686: pmic@09 { compatible = "maxim,max77686"; reg = <0x09>; + #clock-cells = <1>; voltage-regulators { ldo1_reg: LDO1 { diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index d65984c..6bc0539 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -122,9 +122,7 @@ status = "okay"; }; - mshc@12550000 { - #address-cells = <1>; - #size-cells = <0>; + mmc@12550000 { pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; status = "okay"; @@ -132,7 +130,6 @@ num-slots = <1>; supports-highspeed; broken-cd; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -159,7 +156,7 @@ display-timings { native-mode = <&timing0>; timing0: timing { - clock-frequency = <50000>; + clock-frequency = <47500000>; hactive = <1024>; vactive = <600>; hfront-porch = <64>; diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts new file mode 100644 index 0000000..0a98312 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts @@ -0,0 +1,93 @@ +/* + * FriendlyARM's Exynos4412 based TINY4412 board device tree source + * + * Copyright (c) 2013 Alex Ling <kasimling@gmail.com> + * + * Device tree source file for FriendlyARM's TINY4412 board which is based on + * Samsung's Exynos4412 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos4412.dtsi" + +/ { + model = "FriendlyARM TINY4412 board based on Exynos4412"; + compatible = "friendlyarm,tiny4412", "samsung,exynos4412"; + + memory { + reg = <0x40000000 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + label = "led1"; + gpios = <&gpm4 0 1>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "led2"; + gpios = <&gpm4 1 1>; + default-state = "off"; + }; + + led3 { + label = "led3"; + gpios = <&gpm4 2 1>; + default-state = "off"; + }; + + led4 { + label = "led4"; + gpios = <&gpm4 3 1>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; + + rtc@10070000 { + status = "okay"; + }; + + sdhci@12530000 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-names = "default"; + status = "okay"; + }; + + serial@13800000 { + status = "okay"; + }; + + serial@13810000 { + status = "okay"; + }; + + serial@13820000 { + status = "okay"; + }; + + serial@13830000 { + status = "okay"; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index fb7b9ae..4f851cc 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -139,6 +139,7 @@ interrupt-parent = <&gpx0>; interrupts = <7 0>; reg = <0x09>; + #clock-cells = <1>; voltage-regulators { ldo1_reg: ldo1 { @@ -442,13 +443,25 @@ }; }; - sdhci@12510000 { - bus-width = <8>; + mmc@12550000 { + num-slots = <1>; + supports-highspeed; + broken-cd; non-removable; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; - pinctrl-names = "default"; + card-detect-delay = <200>; vmmc-supply = <&vemmc_reg>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <0>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; }; serial@13800000 { diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index e743e67..87b339c7 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -22,7 +22,7 @@ / { compatible = "samsung,exynos4412"; - gic:interrupt-controller@10490000 { + gic: interrupt-controller@10490000 { cpu-offset = <0x4000>; }; @@ -35,37 +35,4 @@ <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; }; - mct@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - interrupt-controller; - #interrups-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>, <6 0>, <7 0>; - clocks = <&clock 3>, <&clock 344>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &combiner 12 5>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 1 12 0>, - <0x5 0 &gic 1 12 0>, - <0x6 0 &gic 1 12 0>, - <0x7 0 &gic 1 12 0>; - }; - }; - - mshc@12550000 { - compatible = "samsung,exynos4412-dw-mshc"; - reg = <0x12550000 0x1000>; - interrupts = <0 77 0>; - #address-cells = <1>; - #size-cells = <0>; - }; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index ad531fe..5c412aa 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -28,6 +28,7 @@ pinctrl3 = &pinctrl_3; fimc-lite0 = &fimc_lite_0; fimc-lite1 = &fimc_lite_1; + mshc0 = &mshc_0; }; pd_isp: isp-power-domain@10023CA0 { @@ -41,6 +42,26 @@ #clock-cells = <1>; }; + mct@10050000 { + compatible = "samsung,exynos4412-mct"; + reg = <0x10050000 0x800>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, <4>; + clocks = <&clock 3>, <&clock 344>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &gic 0 57 0>, + <1 &combiner 12 5>, + <2 &combiner 12 6>, + <3 &combiner 12 7>, + <4 &gic 1 12 0>; + }; + }; + pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4x12-pinctrl"; reg = <0x11400000 0x1000>; @@ -176,4 +197,16 @@ }; }; }; + + mshc_0: mmc@12550000 { + compatible = "samsung,exynos4412-dw-mshc"; + reg = <0x12550000 0x1000>; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <0x80>; + clocks = <&clock 301>, <&clock 149>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 074739d..258dca4 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -23,7 +23,7 @@ reg = <0x10000000 0x100>; }; - combiner:interrupt-controller@10440000 { + combiner: interrupt-controller@10440000 { compatible = "samsung,exynos4210-combiner"; #interrupt-cells = <2>; interrupt-controller; @@ -39,7 +39,7 @@ <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; }; - gic:interrupt-controller@10481000 { + gic: interrupt-controller@10481000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -50,27 +50,6 @@ interrupts = <1 9 0xf04>; }; - dwmmc_0: dwmmc0@12200000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - dwmmc_1: dwmmc1@12210000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 76 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - dwmmc_2: dwmmc2@12220000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 77 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - serial@12C00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 6845270..b42e658 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -34,6 +34,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <20000>; samsung,i2c-slave-addr = <0x66>; + status = "okay"; s5m8767_pmic@66 { compatible = "samsung,s5m8767-pmic"; @@ -266,7 +267,7 @@ buck2_reg: BUCK2 { regulator-name = "vdd_arm"; - regulator-min-microvolt = <925000>; + regulator-min-microvolt = <912500>; regulator-max-microvolt = <1300000>; regulator-always-on; regulator-boot-on; @@ -302,11 +303,13 @@ buck7_reg: BUCK7 { regulator-name = "PVDD_BUCK7"; regulator-always-on; + op_mode = <1>; }; buck8_reg: BUCK8 { regulator-name = "PVDD_BUCK8"; regulator-always-on; + op_mode = <1>; }; buck9_reg: BUCK9 { @@ -319,11 +322,9 @@ }; }; - i2c@12C70000 { - status = "disabled"; - }; - i2c@12C80000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; samsung,i2c-slave-addr = <0x50>; @@ -335,7 +336,10 @@ }; i2c@12C90000 { + status = "okay"; + wm1811a@1a { + compatible = "wlf,wm1811"; reg = <0x1a>; @@ -353,23 +357,9 @@ }; }; - i2c@12CA0000 { - status = "disabled"; - }; - - i2c@12CB0000 { - status = "disabled"; - }; - - i2c@12CC0000 { - status = "disabled"; - }; - - i2c@12CD0000 { - status = "disabled"; - }; - i2c@12CE0000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; samsung,i2c-slave-addr = <0x38>; @@ -380,15 +370,11 @@ }; }; - i2c@121D0000 { - status = "disabled"; - }; - - dwmmc_0: dwmmc0@12200000 { + mmc_0: mmc@12200000 { + status = "okay"; num-slots = <1>; supports-highspeed; broken-cd; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -403,14 +389,10 @@ }; }; - dwmmc_1: dwmmc1@12210000 { - status = "disabled"; - }; - - dwmmc_2: dwmmc2@12220000 { + mmc_2: mmc@12220000 { + status = "okay"; num-slots = <1>; supports-highspeed; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -426,26 +408,10 @@ }; }; - dwmmc_3: dwmmc3@12230000 { - status = "disabled"; - }; - i2s0: i2s@03830000 { status = "okay"; }; - spi_0: spi@12d20000 { - status = "disabled"; - }; - - spi_1: spi@12d30000 { - status = "disabled"; - }; - - spi_2: spi@12d40000 { - status = "disabled"; - }; - gpio_keys { compatible = "gpio-keys"; diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi index 9b186ac..2c1560d 100644 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi @@ -37,6 +37,7 @@ }; i2c@12C60000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; @@ -48,6 +49,7 @@ pinctrl-0 = <&max77686_irq>; wakeup-source; reg = <0x09>; + #clock-cells = <1>; voltage-regulators { ldo1_reg: LDO1 { @@ -185,6 +187,7 @@ }; i2c@12C70000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; @@ -198,6 +201,7 @@ }; i2c@12C80000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; @@ -208,30 +212,31 @@ }; i2c@12C90000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; }; i2c@12CA0000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; }; i2c@12CB0000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; }; - i2c@12CC0000 { - status = "disabled"; - }; - i2c@12CD0000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; }; i2c@12CE0000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; @@ -241,11 +246,10 @@ }; }; - dwmmc0@12200000 { + mmc@12200000 { num-slots = <1>; supports-highspeed; broken-cd; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -259,14 +263,9 @@ }; }; - dwmmc1@12210000 { - status = "disabled"; - }; - - dwmmc2@12220000 { + mmc@12220000 { num-slots = <1>; supports-highspeed; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -281,11 +280,10 @@ }; }; - dwmmc3@12230000 { + mmc@12230000 { num-slots = <1>; supports-highspeed; broken-cd; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -298,19 +296,12 @@ }; }; - spi_0: spi@12d20000 { - status = "disabled"; - }; - spi_1: spi@12d30000 { + status = "okay"; samsung,spi-src-clk = <0>; num-cs = <1>; }; - spi_2: spi@12d40000 { - status = "disabled"; - }; - hdmi { hpd-gpio = <&gpx3 7 0>; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index f86d567..3e69837 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -30,6 +30,7 @@ i2c@12C60000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <20000>; + status = "okay"; eeprom@50 { compatible = "samsung,s524ad0xd1"; @@ -37,7 +38,7 @@ }; }; - vdd:fixed-regulator@0 { + vdd: fixed-regulator@0 { compatible = "regulator-fixed"; regulator-name = "vdd-supply"; regulator-min-microvolt = <1800000>; @@ -45,7 +46,7 @@ regulator-always-on; }; - dbvdd:fixed-regulator@1 { + dbvdd: fixed-regulator@1 { compatible = "regulator-fixed"; regulator-name = "dbvdd-supply"; regulator-min-microvolt = <3300000>; @@ -53,7 +54,7 @@ regulator-always-on; }; - spkvdd:fixed-regulator@2 { + spkvdd: fixed-regulator@2 { compatible = "regulator-fixed"; regulator-name = "spkvdd-supply"; regulator-min-microvolt = <5000000>; @@ -64,6 +65,7 @@ i2c@12C70000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <20000>; + status = "okay"; eeprom@51 { compatible = "samsung,s524ad0xd1"; @@ -77,6 +79,9 @@ gpio-controller; #gpio-cells = <2>; + clocks = <&codec_mclk>; + clock-names = "MCLK1"; + AVDD2-supply = <&vdd>; CPVDD-supply = <&vdd>; DBVDD-supply = <&dbvdd>; @@ -89,6 +94,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <40000>; samsung,i2c-slave-addr = <0x38>; + status = "okay"; sata-phy { compatible = "samsung,sata-phy"; @@ -103,6 +109,7 @@ i2c@12C80000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + status = "okay"; hdmiddc@50 { compatible = "samsung,exynos4210-hdmiddc"; @@ -110,29 +117,10 @@ }; }; - i2c@12C90000 { - status = "disabled"; - }; - - i2c@12CA0000 { - status = "disabled"; - }; - - i2c@12CB0000 { - status = "disabled"; - }; - - i2c@12CC0000 { - status = "disabled"; - }; - - i2c@12CD0000 { - status = "disabled"; - }; - i2c@12CE0000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + status = "okay"; hdmiphy@38 { compatible = "samsung,exynos4212-hdmiphy"; @@ -140,11 +128,11 @@ }; }; - dwmmc0@12200000 { + mmc@12200000 { + status = "okay"; num-slots = <1>; supports-highspeed; broken-cd; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -158,14 +146,10 @@ }; }; - dwmmc1@12210000 { - status = "disabled"; - }; - - dwmmc2@12220000 { + mmc@12220000 { + status = "okay"; num-slots = <1>; supports-highspeed; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -180,15 +164,13 @@ }; }; - dwmmc3@12230000 { - status = "disabled"; - }; - spi_0: spi@12d20000 { status = "disabled"; }; spi_1: spi@12d30000 { + status = "okay"; + w25q80bw@0 { #address-cells = <1>; #size-cells = <1>; @@ -214,10 +196,6 @@ }; }; - spi_2: spi@12d40000 { - status = "disabled"; - }; - hdmi { hpd-gpio = <&gpx3 7 0>; }; @@ -279,5 +257,11 @@ compatible = "samsung,clock-xxti"; clock-frequency = <24000000>; }; + + codec_mclk: codec-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16934000>; + }; }; }; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index fd711e2..7e45eea 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -10,7 +10,7 @@ /dts-v1/; #include "exynos5250.dtsi" -#include "cros5250-common.dtsi" +#include "exynos5250-cros-common.dtsi" / { model = "Google Snow"; @@ -85,7 +85,7 @@ keypad,num-rows = <8>; keypad,num-columns = <13>; google,needs-ghost-filter; - linux,keymap = <0x0001003a /* CAPSLK */ + linux,keymap = <0x0001007d /* L_META */ 0x0002003b /* F1 */ 0x00030030 /* B */ 0x00040044 /* F10 */ @@ -130,6 +130,7 @@ 0x04060024 /* J */ 0x04080027 /* ; */ 0x04090026 /* L */ + 0x040a002b /* \ */ 0x040b001c /* ENTER */ 0x0501002c /* Z */ @@ -171,11 +172,20 @@ }; }; + mmc@12200000 { + status = "okay"; + }; + + mmc@12220000 { + status = "okay"; + }; + /* * On Snow we've got SIP WiFi and so can keep drive strengths low to * reduce EMI. */ - dwmmc3@12230000 { + mmc@12230000 { + status = "okay"; slot@0 { pinctrl-names = "default"; pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 177becd..b7dec41 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -33,10 +33,10 @@ gsc1 = &gsc_1; gsc2 = &gsc_2; gsc3 = &gsc_3; - mshc0 = &dwmmc_0; - mshc1 = &dwmmc_1; - mshc2 = &dwmmc_2; - mshc3 = &dwmmc_3; + mshc0 = &mmc_0; + mshc1 = &mmc_1; + mshc2 = &mmc_2; + mshc3 = &mmc_3; i2c0 = &i2c_0; i2c1 = &i2c_1; i2c2 = &i2c_2; @@ -60,11 +60,13 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + clock-frequency = <1700000000>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; + clock-frequency = <1700000000>; }; }; @@ -88,6 +90,8 @@ compatible = "samsung,exynos5250-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; + clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; timer { @@ -242,6 +246,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_bus>; + status = "disabled"; }; i2c_1: i2c@12C70000 { @@ -254,6 +259,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_bus>; + status = "disabled"; }; i2c_2: i2c@12C80000 { @@ -266,6 +272,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c2_bus>; + status = "disabled"; }; i2c_3: i2c@12C90000 { @@ -278,6 +285,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c3_bus>; + status = "disabled"; }; i2c_4: i2c@12CA0000 { @@ -290,6 +298,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c4_bus>; + status = "disabled"; }; i2c_5: i2c@12CB0000 { @@ -302,6 +311,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c5_bus>; + status = "disabled"; }; i2c_6: i2c@12CC0000 { @@ -314,6 +324,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c6_bus>; + status = "disabled"; }; i2c_7: i2c@12CD0000 { @@ -326,6 +337,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c7_bus>; + status = "disabled"; }; i2c_8: i2c@12CE0000 { @@ -336,6 +348,7 @@ #size-cells = <0>; clocks = <&clock 302>; clock-names = "i2c"; + status = "disabled"; }; i2c@121D0000 { @@ -345,10 +358,12 @@ #size-cells = <0>; clocks = <&clock 288>; clock-names = "i2c"; + status = "disabled"; }; spi_0: spi@12d20000 { compatible = "samsung,exynos4210-spi"; + status = "disabled"; reg = <0x12d20000 0x100>; interrupts = <0 66 0>; dmas = <&pdma0 5 @@ -364,6 +379,7 @@ spi_1: spi@12d30000 { compatible = "samsung,exynos4210-spi"; + status = "disabled"; reg = <0x12d30000 0x100>; interrupts = <0 67 0>; dmas = <&pdma1 5 @@ -379,6 +395,7 @@ spi_2: spi@12d40000 { compatible = "samsung,exynos4210-spi"; + status = "disabled"; reg = <0x12d40000 0x100>; interrupts = <0 68 0>; dmas = <&pdma0 7 @@ -392,25 +409,43 @@ pinctrl-0 = <&spi2_bus>; }; - dwmmc_0: dwmmc0@12200000 { + mmc_0: mmc@12200000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; reg = <0x12200000 0x1000>; clocks = <&clock 280>, <&clock 139>; clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; }; - dwmmc_1: dwmmc1@12210000 { + mmc_1: mmc@12210000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; reg = <0x12210000 0x1000>; clocks = <&clock 281>, <&clock 140>; clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; }; - dwmmc_2: dwmmc2@12220000 { + mmc_2: mmc@12220000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; reg = <0x12220000 0x1000>; clocks = <&clock 282>, <&clock 141>; clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; }; - dwmmc_3: dwmmc3@12230000 { + mmc_3: mmc@12230000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12230000 0x1000>; interrupts = <0 78 0>; @@ -418,6 +453,8 @@ #size-cells = <0>; clocks = <&clock 283>, <&clock 142>; clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; }; i2s0: i2s@03830000 { @@ -526,6 +563,15 @@ }; }; + pwm: pwm@12dd0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x12dd0000 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + clocks = <&clock 311>; + clock-names = "timers"; + }; + amba { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts new file mode 100644 index 0000000..7340745 --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -0,0 +1,66 @@ +/* + * Samsung's Exynos5420 based Arndale Octa board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos5420.dtsi" + +/ { + model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; + compatible = "insignal,arndale-octa", "samsung,exynos5420"; + + memory { + reg = <0x20000000 0x80000000>; + }; + + chosen { + bootargs = "console=ttySAC3,115200"; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + mmc@12200000 { + status = "okay"; + broken-cd; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; + }; + + mmc@12220000 { + status = "okay"; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index e695aba..e62c8eb 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -64,7 +64,7 @@ samsung,pins = "gpx0-7"; samsung,pin-function = <3>; samsung,pin-pud = <0>; - samaung,pin-drv = <0>; + samsung,pin-drv = <0>; }; }; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 79524c7..fb5a1e2 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -31,6 +31,39 @@ }; }; + mmc@12200000 { + status = "okay"; + broken-cd; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; + }; + + mmc@12220000 { + status = "okay"; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + dp-controller@145B0000 { pinctrl-names = "default"; pinctrl-0 = <&dp_hpd>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 09aa06c..8db792b 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -22,6 +22,9 @@ compatible = "samsung,exynos5420"; aliases { + mshc0 = &mmc_0; + mshc1 = &mmc_1; + mshc2 = &mmc_2; pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; @@ -31,6 +34,18 @@ i2c1 = &i2c_1; i2c2 = &i2c_2; i2c3 = &i2c_3; + i2c4 = &hsi2c_4; + i2c5 = &hsi2c_5; + i2c6 = &hsi2c_6; + i2c7 = &hsi2c_7; + i2c8 = &hsi2c_8; + i2c9 = &hsi2c_9; + i2c10 = &hsi2c_10; + gsc0 = &gsc_0; + gsc1 = &gsc_1; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; }; cpus { @@ -64,6 +79,34 @@ reg = <0x3>; clock-frequency = <1800000000>; }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <1000000000>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <1000000000>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <1000000000>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <1000000000>; + }; }; clock: clock-controller@10010000 { @@ -76,8 +119,8 @@ compatible = "samsung,exynos5420-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; - clocks = <&clock 148>; - clock-names = "sclk_audio"; + clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; codec@11000000 { @@ -88,13 +131,50 @@ clock-names = "mfc"; }; + mmc_0: mmc@12200000 { + compatible = "samsung,exynos5420-dw-mshc-smu"; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12200000 0x2000>; + clocks = <&clock 351>, <&clock 132>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mmc_1: mmc@12210000 { + compatible = "samsung,exynos5420-dw-mshc-smu"; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12210000 0x2000>; + clocks = <&clock 352>, <&clock 133>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mmc_2: mmc@12220000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12220000 0x1000>; + clocks = <&clock 353>, <&clock 134>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; interrupt-controller; #interrups-cells = <1>; interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>; clocks = <&clock 1>, <&clock 315>; clock-names = "fin_pll", "mct"; @@ -109,7 +189,11 @@ <4 &gic 0 120 0>, <5 &gic 0 121 0>, <6 &gic 0 122 0>, - <7 &gic 0 123 0>; + <7 &gic 0 123 0>, + <8 &gic 0 128 0>, + <9 &gic 0 129 0>, + <10 &gic 0 130 0>, + <11 &gic 0 131 0>; }; }; @@ -190,6 +274,106 @@ status = "okay"; }; + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@121A0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121A0000 0x1000>; + interrupts = <0 34 0>; + clocks = <&clock 362>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@121B0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121B0000 0x1000>; + interrupts = <0 35 0>; + clocks = <&clock 363>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + mdma0: mdma@10800000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10800000 0x1000>; + interrupts = <0 33 0>; + clocks = <&clock 473>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + }; + + mdma1: mdma@11C10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11C10000 0x1000>; + interrupts = <0 124 0>; + clocks = <&clock 442>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + }; + }; + + spi_0: spi@12d20000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d20000 0x100>; + interrupts = <0 66 0>; + dmas = <&pdma0 5 + &pdma0 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + clocks = <&clock 271>, <&clock 135>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; + }; + + spi_1: spi@12d30000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d30000 0x100>; + interrupts = <0 67 0>; + dmas = <&pdma1 5 + &pdma1 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + clocks = <&clock 272>, <&clock 136>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; + }; + + spi_2: spi@12d40000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d40000 0x100>; + interrupts = <0 68 0>; + dmas = <&pdma0 7 + &pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + clocks = <&clock 273>, <&clock 137>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; + }; + serial@12C00000 { clocks = <&clock 257>, <&clock 128>; clock-names = "uart", "clk_uart_baud0"; @@ -210,6 +394,15 @@ clock-names = "uart", "clk_uart_baud0"; }; + pwm: pwm@12dd0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x12dd0000 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + clocks = <&clock 279>; + clock-names = "timers"; + }; + dp_phy: video-phy@10040728 { compatible = "samsung,exynos5250-dp-video-phy"; reg = <0x10040728 4>; @@ -292,6 +485,97 @@ status = "disabled"; }; + hsi2c_4: i2c@12CA0000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CA0000 0x1000>; + interrupts = <0 60 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_hs_bus>; + clocks = <&clock 265>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_5: i2c@12CB0000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CB0000 0x1000>; + interrupts = <0 61 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_hs_bus>; + clocks = <&clock 266>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_6: i2c@12CC0000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CC0000 0x1000>; + interrupts = <0 62 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_hs_bus>; + clocks = <&clock 267>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_7: i2c@12CD0000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CD0000 0x1000>; + interrupts = <0 63 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_hs_bus>; + clocks = <&clock 268>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_8: i2c@12E00000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E00000 0x1000>; + interrupts = <0 87 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_hs_bus>; + clocks = <&clock 281>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_9: i2c@12E10000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E10000 0x1000>; + interrupts = <0 88 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c9_hs_bus>; + clocks = <&clock 282>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_10: i2c@12E20000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E20000 0x1000>; + interrupts = <0 203 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c10_hs_bus>; + clocks = <&clock 283>; + clock-names = "hsi2c"; + status = "disabled"; + }; + hdmi@14530000 { compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x70000>; @@ -310,4 +594,62 @@ clocks = <&clock 431>, <&clock 143>; clock-names = "mixer", "sclk_hdmi"; }; + + gsc_0: video-scaler@13e00000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e00000 0x1000>; + interrupts = <0 85 0>; + clocks = <&clock 465>; + clock-names = "gscl"; + samsung,power-domain = <&gsc_pd>; + }; + + gsc_1: video-scaler@13e10000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e10000 0x1000>; + interrupts = <0 86 0>; + clocks = <&clock 466>; + clock-names = "gscl"; + samsung,power-domain = <&gsc_pd>; + }; + + tmu_cpu0: tmu@10060000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10060000 0x100>; + interrupts = <0 65 0>; + clocks = <&clock 318>; + clock-names = "tmu_apbif"; + }; + + tmu_cpu1: tmu@10064000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10064000 0x100>; + interrupts = <0 183 0>; + clocks = <&clock 318>; + clock-names = "tmu_apbif"; + }; + + tmu_cpu2: tmu@10068000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x10068000 0x100>, <0x1006c000 0x4>; + interrupts = <0 184 0>; + clocks = <&clock 318>, <&clock 318>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + }; + + tmu_cpu3: tmu@1006c000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x1006c000 0x100>, <0x100a0000 0x4>; + interrupts = <0 185 0>; + clocks = <&clock 318>, <&clock 319>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + }; + + tmu_gpu: tmu@100a0000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x100a0000 0x100>, <0x10068000 0x4>; + interrupts = <0 215 0>; + clocks = <&clock 319>, <&clock 318>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + }; }; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 8da1070..02a0a12 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -29,7 +29,7 @@ #clock-cells = <1>; }; - gic:interrupt-controller@2E0000 { + gic: interrupt-controller@2E0000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hi3620-hi4511.dts new file mode 100644 index 0000000..fe62392 --- /dev/null +++ b/arch/arm/boot/dts/hi3620-hi4511.dts @@ -0,0 +1,649 @@ +/* + * Copyright (C) 2012-2013 Linaro Ltd. + * Author: Haojian Zhuang <haojian.zhuang@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +/dts-v1/; + +#include "hi3620.dtsi" + +/ { + model = "Hisilicon Hi4511 Development Board"; + compatible = "hisilicon,hi3620-hi4511"; + + chosen { + bootargs = "console=ttyAMA0,115200 root=/dev/ram0 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; + + amba { + dual_timer0: dual_timer@800000 { + status = "ok"; + }; + + uart0: uart@b00000 { /* console */ + pinctrl-names = "default", "idle"; + pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; + pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>; + status = "ok"; + }; + + uart1: uart@b01000 { /* modem */ + pinctrl-names = "default", "idle"; + pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; + pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>; + status = "ok"; + }; + + uart2: uart@b02000 { /* audience */ + pinctrl-names = "default", "idle"; + pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; + pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>; + status = "ok"; + }; + + uart3: uart@b03000 { + pinctrl-names = "default", "idle"; + pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; + pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>; + status = "ok"; + }; + + uart4: uart@b04000 { + pinctrl-names = "default", "idle"; + pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; + pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>; + status = "ok"; + }; + + pmx0: pinmux@803000 { + pinctrl-names = "default"; + pinctrl-0 = <&board_pmx_pins>; + + board_pmx_pins: board_pmx_pins { + pinctrl-single,pins = < + 0x008 0x0 /* GPIO -- eFUSE_DOUT */ + 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */ + >; + }; + uart0_pmx_func: uart0_pmx_func { + pinctrl-single,pins = < + 0x0f0 0x0 + 0x0f4 0x0 /* UART0_RX & UART0_TX */ + >; + }; + uart0_pmx_idle: uart0_pmx_idle { + pinctrl-single,pins = < + /*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */ + 0x0f4 0x1 /* UART0_RX & UART0_TX */ + >; + }; + uart1_pmx_func: uart1_pmx_func { + pinctrl-single,pins = < + 0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */ + 0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */ + >; + }; + uart1_pmx_idle: uart1_pmx_idle { + pinctrl-single,pins = < + 0x0f8 0x1 /* GPIO (IOMG61) */ + 0x0fc 0x1 /* GPIO (IOMG62) */ + >; + }; + uart2_pmx_func: uart2_pmx_func { + pinctrl-single,pins = < + 0x104 0x2 /* UART2_RXD (IOMG96) */ + 0x108 0x2 /* UART2_TXD (IOMG64) */ + >; + }; + uart2_pmx_idle: uart2_pmx_idle { + pinctrl-single,pins = < + 0x104 0x1 /* GPIO (IOMG96) */ + 0x108 0x1 /* GPIO (IOMG64) */ + >; + }; + uart3_pmx_func: uart3_pmx_func { + pinctrl-single,pins = < + 0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */ + 0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */ + >; + }; + uart3_pmx_idle: uart3_pmx_idle { + pinctrl-single,pins = < + 0x160 0x1 /* GPIO (IOMG85) */ + 0x164 0x1 /* GPIO (IOMG86) */ + >; + }; + uart4_pmx_func: uart4_pmx_func { + pinctrl-single,pins = < + 0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */ + 0x16c 0x0 /* UART4_RXD (IOMG88) */ + 0x170 0x0 /* UART4_TXD (IOMG93) */ + >; + }; + uart4_pmx_idle: uart4_pmx_idle { + pinctrl-single,pins = < + 0x168 0x1 /* GPIO (IOMG87) */ + 0x16c 0x1 /* GPIO (IOMG88) */ + 0x170 0x1 /* GPIO (IOMG93) */ + >; + }; + i2c0_pmx_func: i2c0_pmx_func { + pinctrl-single,pins = < + 0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */ + >; + }; + i2c0_pmx_idle: i2c0_pmx_idle { + pinctrl-single,pins = < + 0x0b4 0x1 /* GPIO (IOMG45) */ + >; + }; + i2c1_pmx_func: i2c1_pmx_func { + pinctrl-single,pins = < + 0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */ + >; + }; + i2c1_pmx_idle: i2c1_pmx_idle { + pinctrl-single,pins = < + 0x0b8 0x1 /* GPIO (IOMG46) */ + >; + }; + i2c2_pmx_func: i2c2_pmx_func { + pinctrl-single,pins = < + 0x068 0x0 /* I2C2_SCL (IOMG26) */ + 0x06c 0x0 /* I2C2_SDA (IOMG27) */ + >; + }; + i2c2_pmx_idle: i2c2_pmx_idle { + pinctrl-single,pins = < + 0x068 0x1 /* GPIO (IOMG26) */ + 0x06c 0x1 /* GPIO (IOMG27) */ + >; + }; + i2c3_pmx_func: i2c3_pmx_func { + pinctrl-single,pins = < + 0x050 0x2 /* I2C3_SCL (IOMG20) */ + 0x054 0x2 /* I2C3_SDA (IOMG21) */ + >; + }; + i2c3_pmx_idle: i2c3_pmx_idle { + pinctrl-single,pins = < + 0x050 0x1 /* GPIO (IOMG20) */ + 0x054 0x1 /* GPIO (IOMG21) */ + >; + }; + spi0_pmx_func: spi0_pmx_func { + pinctrl-single,pins = < + 0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */ + 0x0d8 0x0 /* SPI0_CS0 (IOMG54) */ + 0x0dc 0x0 /* SPI0_CS1 (IOMG55) */ + 0x0e0 0x0 /* SPI0_CS2 (IOMG56) */ + 0x0e4 0x0 /* SPI0_CS3 (IOMG57) */ + >; + }; + spi0_pmx_idle: spi0_pmx_idle { + pinctrl-single,pins = < + 0x0d4 0x1 /* GPIO (IOMG53) */ + 0x0d8 0x1 /* GPIO (IOMG54) */ + 0x0dc 0x1 /* GPIO (IOMG55) */ + 0x0e0 0x1 /* GPIO (IOMG56) */ + 0x0e4 0x1 /* GPIO (IOMG57) */ + >; + }; + spi1_pmx_func: spi1_pmx_func { + pinctrl-single,pins = < + 0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */ + 0x0e8 0x0 /* SPI1_DO (IOMG58) */ + 0x0ec 0x0 /* SPI1_CS (IOMG95) */ + >; + }; + spi1_pmx_idle: spi1_pmx_idle { + pinctrl-single,pins = < + 0x184 0x1 /* GPIO (IOMG98) */ + 0x0e8 0x1 /* GPIO (IOMG58) */ + 0x0ec 0x1 /* GPIO (IOMG95) */ + >; + }; + kpc_pmx_func: kpc_pmx_func { + pinctrl-single,pins = < + 0x12c 0x0 /* KEY_IN0 (IOMG73) */ + 0x130 0x0 /* KEY_IN1 (IOMG74) */ + 0x134 0x0 /* KEY_IN2 (IOMG75) */ + 0x10c 0x0 /* KEY_OUT0 (IOMG65) */ + 0x110 0x0 /* KEY_OUT1 (IOMG66) */ + 0x114 0x0 /* KEY_OUT2 (IOMG67) */ + >; + }; + kpc_pmx_idle: kpc_pmx_idle { + pinctrl-single,pins = < + 0x12c 0x1 /* GPIO (IOMG73) */ + 0x130 0x1 /* GPIO (IOMG74) */ + 0x134 0x1 /* GPIO (IOMG75) */ + 0x10c 0x1 /* GPIO (IOMG65) */ + 0x110 0x1 /* GPIO (IOMG66) */ + 0x114 0x1 /* GPIO (IOMG67) */ + >; + }; + gpio_key_func: gpio_key_func { + pinctrl-single,pins = < + 0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */ + 0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */ + >; + }; + emmc_pmx_func: emmc_pmx_func { + pinctrl-single,pins = < + 0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */ + 0x018 0x0 /* NAND_CS3_N (IOMG6) */ + 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ + 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ + 0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */ + >; + }; + emmc_pmx_idle: emmc_pmx_idle { + pinctrl-single,pins = < + 0x030 0x0 /* GPIO (IOMG12) */ + 0x018 0x1 /* GPIO (IOMG6) */ + 0x024 0x1 /* GPIO (IOMG8) */ + 0x028 0x1 /* GPIO (IOMG9) */ + 0x02c 0x1 /* GPIO (IOMG10) */ + >; + }; + sd_pmx_func: sd_pmx_func { + pinctrl-single,pins = < + 0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */ + 0x0c0 0x0 /* SD_DATA3 (IOMG48) */ + >; + }; + sd_pmx_idle: sd_pmx_idle { + pinctrl-single,pins = < + 0x0bc 0x1 /* GPIO (IOMG47) */ + 0x0c0 0x1 /* GPIO (IOMG48) */ + >; + }; + nand_pmx_func: nand_pmx_func { + pinctrl-single,pins = < + 0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */ + 0x010 0x0 /* NAND_CS1_N (IOMG4) */ + 0x014 0x0 /* NAND_CS2_N (IOMG5) */ + 0x018 0x0 /* NAND_CS3_N (IOMG6) */ + 0x01c 0x0 /* NAND_BUSY0_N (IOMG94) */ + 0x020 0x0 /* NAND_BUSY1_N (IOMG7) */ + 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ + 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ + 0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */ + >; + }; + nand_pmx_idle: nand_pmx_idle { + pinctrl-single,pins = < + 0x00c 0x1 /* GPIO (IOMG3) */ + 0x010 0x1 /* GPIO (IOMG4) */ + 0x014 0x1 /* GPIO (IOMG5) */ + 0x018 0x1 /* GPIO (IOMG6) */ + 0x01c 0x1 /* GPIO (IOMG94) */ + 0x020 0x1 /* GPIO (IOMG7) */ + 0x024 0x1 /* GPIO (IOMG8) */ + 0x028 0x1 /* GPIO (IOMG9) */ + 0x02c 0x1 /* GPIO (IOMG10) */ + >; + }; + sdio_pmx_func: sdio_pmx_func { + pinctrl-single,pins = < + 0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */ + >; + }; + sdio_pmx_idle: sdio_pmx_idle { + pinctrl-single,pins = < + 0x0c4 0x1 /* GPIO (IOMG49) */ + >; + }; + audio_out_pmx_func: audio_out_pmx_func { + pinctrl-single,pins = < + 0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */ + >; + }; + }; + + pmx1: pinmux@803800 { + pinctrl-names = "default"; + pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins + &board_np_pins &board_ps_pins &kpc_cfg_func + &audio_out_cfg_func>; + board_pu_pins: board_pu_pins { + pinctrl-single,pins = < + 0x014 0 /* GPIO_158 (IOCFG2) */ + 0x018 0 /* GPIO_159 (IOCFG3) */ + 0x01c 0 /* BOOT_MODE0 (IOCFG4) */ + 0x020 0 /* BOOT_MODE1 (IOCFG5) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <1 1 0 1>; + }; + board_pd_pins: board_pd_pins { + pinctrl-single,pins = < + 0x038 0 /* eFUSE_DOUT (IOCFG11) */ + 0x150 0 /* ISP_GPIO8 (IOCFG93) */ + 0x154 0 /* ISP_GPIO9 (IOCFG94) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + board_pd_ps_pins: board_pd_ps_pins { + pinctrl-single,pins = < + 0x2d8 0 /* CLK_OUT0 (IOCFG190) */ + 0x004 0 /* PMU_SPI_DATA (IOCFG192) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + board_np_pins: board_np_pins { + pinctrl-single,pins = < + 0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + board_ps_pins: board_ps_pins { + pinctrl-single,pins = < + 0x000 0 /* PMU_SPI_CLK (IOCFG191) */ + 0x008 0 /* PMU_SPI_CS_N (IOCFG193) */ + >; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + uart0_cfg_func: uart0_cfg_func { + pinctrl-single,pins = < + 0x208 0 /* UART0_RXD (IOCFG138) */ + 0x20c 0 /* UART0_TXD (IOCFG139) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart0_cfg_idle: uart0_cfg_idle { + pinctrl-single,pins = < + 0x208 0 /* UART0_RXD (IOCFG138) */ + 0x20c 0 /* UART0_TXD (IOCFG139) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart1_cfg_func: uart1_cfg_func { + pinctrl-single,pins = < + 0x210 0 /* UART1_CTS (IOCFG140) */ + 0x214 0 /* UART1_RTS (IOCFG141) */ + 0x218 0 /* UART1_RXD (IOCFG142) */ + 0x21c 0 /* UART1_TXD (IOCFG143) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart1_cfg_idle: uart1_cfg_idle { + pinctrl-single,pins = < + 0x210 0 /* UART1_CTS (IOCFG140) */ + 0x214 0 /* UART1_RTS (IOCFG141) */ + 0x218 0 /* UART1_RXD (IOCFG142) */ + 0x21c 0 /* UART1_TXD (IOCFG143) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart2_cfg_func: uart2_cfg_func { + pinctrl-single,pins = < + 0x220 0 /* UART2_CTS (IOCFG144) */ + 0x224 0 /* UART2_RTS (IOCFG145) */ + 0x228 0 /* UART2_RXD (IOCFG146) */ + 0x22c 0 /* UART2_TXD (IOCFG147) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart2_cfg_idle: uart2_cfg_idle { + pinctrl-single,pins = < + 0x220 0 /* GPIO (IOCFG144) */ + 0x224 0 /* GPIO (IOCFG145) */ + 0x228 0 /* GPIO (IOCFG146) */ + 0x22c 0 /* GPIO (IOCFG147) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart3_cfg_func: uart3_cfg_func { + pinctrl-single,pins = < + 0x294 0 /* UART3_CTS (IOCFG173) */ + 0x298 0 /* UART3_RTS (IOCFG174) */ + 0x29c 0 /* UART3_RXD (IOCFG175) */ + 0x2a0 0 /* UART3_TXD (IOCFG176) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart3_cfg_idle: uart3_cfg_idle { + pinctrl-single,pins = < + 0x294 0 /* UART3_CTS (IOCFG173) */ + 0x298 0 /* UART3_RTS (IOCFG174) */ + 0x29c 0 /* UART3_RXD (IOCFG175) */ + 0x2a0 0 /* UART3_TXD (IOCFG176) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + uart4_cfg_func: uart4_cfg_func { + pinctrl-single,pins = < + 0x2a4 0 /* UART4_CTS (IOCFG177) */ + 0x2a8 0 /* UART4_RTS (IOCFG178) */ + 0x2ac 0 /* UART4_RXD (IOCFG179) */ + 0x2b0 0 /* UART4_TXD (IOCFG180) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + i2c0_cfg_func: i2c0_cfg_func { + pinctrl-single,pins = < + 0x17c 0 /* I2C0_SCL (IOCFG103) */ + 0x180 0 /* I2C0_SDA (IOCFG104) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + i2c1_cfg_func: i2c1_cfg_func { + pinctrl-single,pins = < + 0x184 0 /* I2C1_SCL (IOCFG105) */ + 0x188 0 /* I2C1_SDA (IOCFG106) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + i2c2_cfg_func: i2c2_cfg_func { + pinctrl-single,pins = < + 0x118 0 /* I2C2_SCL (IOCFG79) */ + 0x11c 0 /* I2C2_SDA (IOCFG80) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + i2c3_cfg_func: i2c3_cfg_func { + pinctrl-single,pins = < + 0x100 0 /* I2C3_SCL (IOCFG73) */ + 0x104 0 /* I2C3_SDA (IOCFG74) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + spi0_cfg_func1: spi0_cfg_func1 { + pinctrl-single,pins = < + 0x1d4 0 /* SPI0_CLK (IOCFG125) */ + 0x1d8 0 /* SPI0_DI (IOCFG126) */ + 0x1dc 0 /* SPI0_DO (IOCFG127) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + spi0_cfg_func2: spi0_cfg_func2 { + pinctrl-single,pins = < + 0x1e0 0 /* SPI0_CS0 (IOCFG128) */ + 0x1e4 0 /* SPI0_CS1 (IOCFG129) */ + 0x1e8 0 /* SPI0_CS2 (IOCFG130 */ + 0x1ec 0 /* SPI0_CS3 (IOCFG131) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <1 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + spi1_cfg_func1: spi1_cfg_func1 { + pinctrl-single,pins = < + 0x1f0 0 /* SPI1_CLK (IOCFG132) */ + 0x1f4 0 /* SPI1_DI (IOCFG133) */ + 0x1f8 0 /* SPI1_DO (IOCFG134) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + spi1_cfg_func2: spi1_cfg_func2 { + pinctrl-single,pins = < + 0x1fc 0 /* SPI1_CS (IOCFG135) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <1 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + kpc_cfg_func: kpc_cfg_func { + pinctrl-single,pins = < + 0x250 0 /* KEY_IN0 (IOCFG156) */ + 0x254 0 /* KEY_IN1 (IOCFG157) */ + 0x258 0 /* KEY_IN2 (IOCFG158) */ + 0x230 0 /* KEY_OUT0 (IOCFG148) */ + 0x234 0 /* KEY_OUT1 (IOCFG149) */ + 0x238 0 /* KEY_OUT2 (IOCFG150) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + emmc_cfg_func: emmc_cfg_func { + pinctrl-single,pins = < + 0x0ac 0 /* eMMC_CMD (IOCFG40) */ + 0x0b0 0 /* eMMC_CLK (IOCFG41) */ + 0x058 0 /* NAND_CS3_N (IOCFG19) */ + 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ + 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ + 0x08c 0 /* NAND_DATA8 (IOCFG32) */ + 0x090 0 /* NAND_DATA9 (IOCFG33) */ + 0x094 0 /* NAND_DATA10 (IOCFG34) */ + 0x098 0 /* NAND_DATA11 (IOCFG35) */ + 0x09c 0 /* NAND_DATA12 (IOCFG36) */ + 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ + 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ + 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <1 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + sd_cfg_func1: sd_cfg_func1 { + pinctrl-single,pins = < + 0x18c 0 /* SD_CLK (IOCFG107) */ + 0x190 0 /* SD_CMD (IOCFG108) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + sd_cfg_func2: sd_cfg_func2 { + pinctrl-single,pins = < + 0x194 0 /* SD_DATA0 (IOCFG109) */ + 0x198 0 /* SD_DATA1 (IOCFG110) */ + 0x19c 0 /* SD_DATA2 (IOCFG111) */ + 0x1a0 0 /* SD_DATA3 (IOCFG112) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x70 0xf0>; + }; + nand_cfg_func1: nand_cfg_func1 { + pinctrl-single,pins = < + 0x03c 0 /* NAND_ALE (IOCFG12) */ + 0x040 0 /* NAND_CLE (IOCFG13) */ + 0x06c 0 /* NAND_DATA0 (IOCFG24) */ + 0x070 0 /* NAND_DATA1 (IOCFG25) */ + 0x074 0 /* NAND_DATA2 (IOCFG26) */ + 0x078 0 /* NAND_DATA3 (IOCFG27) */ + 0x07c 0 /* NAND_DATA4 (IOCFG28) */ + 0x080 0 /* NAND_DATA5 (IOCFG29) */ + 0x084 0 /* NAND_DATA6 (IOCFG30) */ + 0x088 0 /* NAND_DATA7 (IOCFG31) */ + 0x08c 0 /* NAND_DATA8 (IOCFG32) */ + 0x090 0 /* NAND_DATA9 (IOCFG33) */ + 0x094 0 /* NAND_DATA10 (IOCFG34) */ + 0x098 0 /* NAND_DATA11 (IOCFG35) */ + 0x09c 0 /* NAND_DATA12 (IOCFG36) */ + 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ + 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ + 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + nand_cfg_func2: nand_cfg_func2 { + pinctrl-single,pins = < + 0x044 0 /* NAND_RE_N (IOCFG14) */ + 0x048 0 /* NAND_WE_N (IOCFG15) */ + 0x04c 0 /* NAND_CS0_N (IOCFG16) */ + 0x050 0 /* NAND_CS1_N (IOCFG17) */ + 0x054 0 /* NAND_CS2_N (IOCFG18) */ + 0x058 0 /* NAND_CS3_N (IOCFG19) */ + 0x05c 0 /* NAND_BUSY0_N (IOCFG20) */ + 0x060 0 /* NAND_BUSY1_N (IOCFG21) */ + 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ + 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <1 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + sdio_cfg_func: sdio_cfg_func { + pinctrl-single,pins = < + 0x1a4 0 /* SDIO0_CLK (IOCG113) */ + 0x1a8 0 /* SDIO0_CMD (IOCG114) */ + 0x1ac 0 /* SDIO0_DATA0 (IOCG115) */ + 0x1b0 0 /* SDIO0_DATA1 (IOCG116) */ + 0x1b4 0 /* SDIO0_DATA2 (IOCG117) */ + 0x1b8 0 /* SDIO0_DATA3 (IOCG118) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; + audio_out_cfg_func: audio_out_cfg_func { + pinctrl-single,pins = < + 0x200 0 /* GPIO (IOCFG136) */ + 0x204 0 /* GPIO (IOCFG137) */ + >; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + call { + label = "call"; + gpios = <&gpio17 2 0>; + linux,code = <169>; /* KEY_PHONE */ + }; + }; +}; diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi new file mode 100644 index 0000000..ab1116d --- /dev/null +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -0,0 +1,565 @@ +/* + * Hisilicon Ltd. Hi3620 SoC + * + * Copyright (C) 2012-2013 Hisilicon Ltd. + * Copyright (C) 2012-2013 Linaro Ltd. + * + * Author: Haojian Zhuang <haojian.zhuang@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/clock/hi3620-clock.h> + +/ { + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + pclk: clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "apb_pclk"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + amba { + + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges = <0 0xfc000000 0x2000000>; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xfc10000 0x100000>; + interrupts = <0 15 4>; + cache-unified; + cache-level = <2>; + }; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + /* gic dist base, gic cpu base */ + reg = <0x1000 0x1000>, <0x100 0x100>; + }; + + sysctrl: system-controller@802000 { + compatible = "hisilicon,sysctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x802000 0x1000>; + reg = <0x802000 0x1000>; + + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + + clock: clock@0 { + compatible = "hisilicon,hi3620-clock"; + reg = <0 0x10000>; + #clock-cells = <1>; + }; + }; + + dual_timer0: dual_timer@800000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x800000 0x1000>; + /* timer00 & timer01 */ + interrupts = <0 0 4>, <0 1 4>; + clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + dual_timer1: dual_timer@801000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x801000 0x1000>; + /* timer10 & timer11 */ + interrupts = <0 2 4>, <0 3 4>; + clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + dual_timer2: dual_timer@a01000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xa01000 0x1000>; + /* timer20 & timer21 */ + interrupts = <0 4 4>, <0 5 4>; + clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + dual_timer3: dual_timer@a02000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xa02000 0x1000>; + /* timer30 & timer31 */ + interrupts = <0 6 4>, <0 7 4>; + clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + dual_timer4: dual_timer@a03000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xa03000 0x1000>; + /* timer40 & timer41 */ + interrupts = <0 96 4>, <0 97 4>; + clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + timer5: timer@600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x600 0x20>; + interrupts = <1 13 0xf01>; + }; + + uart0: uart@b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb00000 0x1000>; + interrupts = <0 20 4>; + clocks = <&clock HI3620_UARTCLK0>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart1: uart@b01000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb01000 0x1000>; + interrupts = <0 21 4>; + clocks = <&clock HI3620_UARTCLK1>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart2: uart@b02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb02000 0x1000>; + interrupts = <0 22 4>; + clocks = <&clock HI3620_UARTCLK2>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart3: uart@b03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb03000 0x1000>; + interrupts = <0 23 4>; + clocks = <&clock HI3620_UARTCLK3>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart4: uart@b04000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb04000 0x1000>; + interrupts = <0 24 4>; + clocks = <&clock HI3620_UARTCLK4>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio0: gpio@806000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x806000 0x1000>; + interrupts = <0 64 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1 + &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK0>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@807000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x807000 0x1000>; + interrupts = <0 65 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 + &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1 + &pmx0 6 5 1 &pmx0 7 6 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK1>; + clock-names = "apb_pclk"; + }; + + gpio2: gpio@808000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x808000 0x1000>; + interrupts = <0 66 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1 + &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1 + &pmx0 6 3 1 &pmx0 7 3 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK2>; + clock-names = "apb_pclk"; + }; + + gpio3: gpio@809000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x809000 0x1000>; + interrupts = <0 67 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 + &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1 + &pmx0 6 11 1 &pmx0 7 11 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK3>; + clock-names = "apb_pclk"; + }; + + gpio4: gpio@80a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x80a000 0x1000>; + interrupts = <0 68 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1 + &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1 + &pmx0 6 13 1 &pmx0 7 13 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK4>; + clock-names = "apb_pclk"; + }; + + gpio5: gpio@80b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x80b000 0x1000>; + interrupts = <0 69 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1 + &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1 + &pmx0 6 16 1 &pmx0 7 16 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK5>; + clock-names = "apb_pclk"; + }; + + gpio6: gpio@80c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x80c000 0x1000>; + interrupts = <0 70 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1 + &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1 + &pmx0 6 18 1 &pmx0 7 19 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK6>; + clock-names = "apb_pclk"; + }; + + gpio7: gpio@80d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x80d000 0x1000>; + interrupts = <0 71 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1 + &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1 + &pmx0 6 25 1 &pmx0 7 26 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK7>; + clock-names = "apb_pclk"; + }; + + gpio8: gpio@80e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x80e000 0x1000>; + interrupts = <0 72 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1 + &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1 + &pmx0 6 33 1 &pmx0 7 34 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK8>; + clock-names = "apb_pclk"; + }; + + gpio9: gpio@80f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x80f000 0x1000>; + interrupts = <0 73 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1 + &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1 + &pmx0 6 41 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK9>; + clock-names = "apb_pclk"; + }; + + gpio10: gpio@810000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x810000 0x1000>; + interrupts = <0 74 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1 + &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK10>; + clock-names = "apb_pclk"; + }; + + gpio11: gpio@811000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x811000 0x1000>; + interrupts = <0 75 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1 + &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1 + &pmx0 6 49 1 &pmx0 7 49 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK11>; + clock-names = "apb_pclk"; + }; + + gpio12: gpio@812000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x812000 0x1000>; + interrupts = <0 76 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1 + &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1 + &pmx0 6 51 1 &pmx0 7 52 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK12>; + clock-names = "apb_pclk"; + }; + + gpio13: gpio@813000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x813000 0x1000>; + interrupts = <0 77 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1 + &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1 + &pmx0 6 55 1 &pmx0 7 56 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK13>; + clock-names = "apb_pclk"; + }; + + gpio14: gpio@814000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x814000 0x1000>; + interrupts = <0 78 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1 + &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1 + &pmx0 6 60 1 &pmx0 7 61 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK14>; + clock-names = "apb_pclk"; + }; + + gpio15: gpio@815000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x815000 0x1000>; + interrupts = <0 79 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1 + &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1 + &pmx0 6 64 1 &pmx0 7 65 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK15>; + clock-names = "apb_pclk"; + }; + + gpio16: gpio@816000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x816000 0x1000>; + interrupts = <0 80 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1 + &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1 + &pmx0 6 72 1 &pmx0 7 73 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK16>; + clock-names = "apb_pclk"; + }; + + gpio17: gpio@817000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x817000 0x1000>; + interrupts = <0 81 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1 + &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1 + &pmx0 6 80 1 &pmx0 7 81 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK17>; + clock-names = "apb_pclk"; + }; + + gpio18: gpio@818000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x818000 0x1000>; + interrupts = <0 82 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1 + &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1 + &pmx0 6 86 1 &pmx0 7 87 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK18>; + clock-names = "apb_pclk"; + }; + + gpio19: gpio@819000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x819000 0x1000>; + interrupts = <0 83 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1 + &pmx0 3 88 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK19>; + clock-names = "apb_pclk"; + }; + + gpio20: gpio@81a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x81a000 0x1000>; + interrupts = <0 84 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1 + &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK20>; + clock-names = "apb_pclk"; + }; + + gpio21: gpio@81b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x81b000 0x1000>; + interrupts = <0 85 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clock HI3620_GPIOCLK21>; + clock-names = "apb_pclk"; + }; + + pmx0: pinmux@803000 { + compatible = "pinctrl-single"; + reg = <0x803000 0x188>; + #address-cells = <1>; + #size-cells = <1>; + #gpio-range-cells = <3>; + ranges; + + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 + &range 12 1 0 &range 13 29 1 + &range 43 1 0 &range 44 49 1 + &range 94 1 1 &range 96 2 1>; + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + }; + + pmx1: pinmux@803800 { + compatible = "pinconf-single"; + reg = <0x803800 0x2dc>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pinctrl-single,register-width = <32>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index c96ceae..581b754 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -337,8 +337,10 @@ }; dcp@80028000 { + compatible = "fsl,imx23-dcp"; reg = <0x80028000 0x2000>; - status = "disabled"; + interrupts = <53 54>; + status = "okay"; }; pxp@8002a000 { diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index cda19c8..f8e9b20 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -813,9 +813,10 @@ }; dcp: dcp@80028000 { + compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; reg = <0x80028000 0x2000>; interrupts = <52 53 54>; - compatible = "fsl-dcp"; + status = "okay"; }; pxp: pxp@8002a000 { diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index 0f06f86..88e3d477 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi @@ -10,6 +10,11 @@ reg = <0x10000000 0x200>; }; + ebi@12000000 { + compatible = "arm,external-bus-interface"; + reg = <0x12000000 0x100>; + }; + timer@13000000 { reg = <0x13000000 0x100>; interrupt-parent = <&pic>; diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index 7deb3a3..a21c17d 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts @@ -47,8 +47,11 @@ valid-mask = <0x00000007>; }; + /* The SIC is cascaded off IRQ 26 on the PIC */ sic: sic@ca000000 { compatible = "arm,versatile-fpga-irq"; + interrupt-parent = <&pic>; + interrupts = <26>; #interrupt-cells = <1>; interrupt-controller; reg = <0xca000000 0x100>; diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts new file mode 100644 index 0000000..eaefdfe --- /dev/null +++ b/arch/arm/boot/dts/k2hk-evm.dts @@ -0,0 +1,63 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * + * Keystone 2 Kepler/Hawking EVM device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "keystone.dtsi" + +/ { + compatible = "ti,keystone-evm"; + + soc { + clock { + refclksys: refclksys { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-sys"; + }; + + refclkpass: refclkpass { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-pass"; + }; + + refclkarm: refclkarm { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "refclk-arm"; + }; + + refclkddr3a: refclkddr3a { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3a"; + }; + + refclkddr3b: refclkddr3b { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3b"; + }; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi index d6713b1..2363593 100644 --- a/arch/arm/boot/dts/keystone-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-clocks.dtsi @@ -13,17 +13,10 @@ clocks { #size-cells = <1>; ranges; - refclkmain: refclkmain { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-main"; - }; - mainpllclk: mainpllclk@2310110 { #clock-cells = <0>; compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclkmain>; + clocks = <&refclksys>; reg = <0x02620350 4>, <0x02310110 4>; reg-names = "control", "multiplier"; fixed-postdiv = <2>; @@ -32,47 +25,43 @@ clocks { papllclk: papllclk@2620358 { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; - clocks = <&refclkmain>; + clocks = <&refclkpass>; clock-output-names = "pa-pll-clk"; reg = <0x02620358 4>; reg-names = "control"; - fixed-postdiv = <6>; }; - ddr3allclk: ddr3apllclk@2620360 { + ddr3apllclk: ddr3apllclk@2620360 { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; - clocks = <&refclkmain>; + clocks = <&refclkddr3a>; clock-output-names = "ddr-3a-pll-clk"; reg = <0x02620360 4>; reg-names = "control"; - fixed-postdiv = <6>; }; - ddr3bllclk: ddr3bpllclk@2620368 { + ddr3bpllclk: ddr3bpllclk@2620368 { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; - clocks = <&refclkmain>; + clocks = <&refclkddr3b>; clock-output-names = "ddr-3b-pll-clk"; reg = <0x02620368 4>; reg-names = "control"; - fixed-postdiv = <6>; }; armpllclk: armpllclk@2620370 { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; - clocks = <&refclkmain>; + clocks = <&refclkarm>; clock-output-names = "arm-pll-clk"; reg = <0x02620370 4>; reg-names = "control"; - fixed-postdiv = <6>; }; mainmuxclk: mainmuxclk@2310108 { #clock-cells = <0>; compatible = "ti,keystone,pll-mux-clock"; - clocks = <&mainpllclk>, <&refclkmain>; + clocks = <&mainpllclk>, <&refclksys>; reg = <0x02310108 4>; bit-shift = <23>; bit-mask = <1>; @@ -135,6 +124,15 @@ clocks { clock-output-names = "chipclk13"; }; + paclk13: paclk13 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&papllclk>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "paclk13"; + }; + chipclk14: chipclk14 { #clock-cells = <0>; compatible = "fixed-factor-clock"; diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dtsi index 100bdf5..b420290 100644 --- a/arch/arm/boot/dts/keystone.dts +++ b/arch/arm/boot/dts/keystone.dtsi @@ -6,14 +6,12 @@ * published by the Free Software Foundation. */ -/dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> #include "skeleton.dtsi" / { model = "Texas Instruments Keystone 2 SoC"; - compatible = "ti,keystone-evm"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; @@ -64,7 +62,11 @@ #address-cells = <1>; interrupt-controller; reg = <0x0 0x02561000 0x0 0x1000>, - <0x0 0x02562000 0x0 0x2000>; + <0x0 0x02562000 0x0 0x2000>, + <0x0 0x02564000 0x0 0x1000>, + <0x0 0x02566000 0x0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; }; timer { @@ -179,5 +181,32 @@ interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>; clocks = <&clkspi>; }; + + usb_phy: usb_phy@2620738 { + compatible = "ti,keystone-usbphy"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2620738 32>; + status = "disabled"; + }; + + usb: usb@2680000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2680000 0x10000>; + clocks = <&clkusb>; + clock-names = "usb"; + interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; + ranges; + status = "disabled"; + + dwc3@2690000 { + compatible = "synopsys,dwc3"; + reg = <0x2690000 0x70000>; + interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; + usb-phy = <&usb_phy>, <&usb_phy>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi new file mode 100644 index 0000000..3916937 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-6192.dtsi @@ -0,0 +1,107 @@ +/ { + mbus { + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + compatible = "marvell,88f6192-pinctrl"; + reg = <0x10000 0x20>; + + pmx_nand: pmx-nand { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp18", + "mpp19"; + marvell,function = "nand"; + }; + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp5", "mpp21", "mpp23"; + marvell,function = "sata0"; + }; + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp4", "mpp20", "mpp22"; + marvell,function = "sata1"; + }; + pmx_spi: pmx-spi { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + pmx_twsi0: pmx-twsi0 { + marvell,pins = "mpp8", "mpp9"; + marvell,function = "twsi0"; + }; + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp10", "mpp11"; + marvell,function = "uart0"; + }; + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp13", "mpp14"; + marvell,function = "uart1"; + }; + pmx_sdio: pmx-sdio { + marvell,pins = "mpp12", "mpp13", "mpp14", + "mpp15", "mpp16", "mpp17"; + marvell,function = "sdio"; + }; + }; + + rtc@10300 { + compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + clocks = <&gate_clk 7>; + }; + + sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <21>; + clocks = <&gate_clk 14>, <&gate_clk 15>; + clock-names = "0", "1"; + status = "disabled"; + }; + + mvsdio@90000 { + compatible = "marvell,orion-sdio"; + reg = <0x90000 0x200>; + interrupts = <28>; + clocks = <&gate_clk 4>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index 650ef30..416d96e 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -89,6 +89,8 @@ interrupts = <21>; clocks = <&gate_clk 14>, <&gate_clk 15>; clock-names = "0", "1"; + phys = <&sata_phy0>, <&sata_phy1>; + phy-names = "port0", "port1"; status = "disabled"; }; @@ -97,6 +99,8 @@ reg = <0x90000 0x200>; interrupts = <28>; clocks = <&gate_clk 4>; + pinctrl-0 = <&pmx_sdio>; + pinctrl-names = "default"; bus-width = <4>; cap-sdio-irq; cap-sd-highspeed; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 3933a33..2902e0d 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -104,6 +104,12 @@ }; }; + thermal@10078 { + compatible = "marvell,kirkwood-thermal"; + reg = <0x10078 0x4>; + status = "okay"; + }; + rtc@10300 { compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; reg = <0x10300 0x20>; @@ -111,12 +117,25 @@ clocks = <&gate_clk 7>; }; + i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <32>; + clock-frequency = <100000>; + clocks = <&gate_clk 7>; + status = "disabled"; + }; + sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; interrupts = <21>; clocks = <&gate_clk 14>, <&gate_clk 15>; clock-names = "0", "1"; + phys = <&sata_phy0>, <&sata_phy1>; + phy-names = "port0", "port1"; status = "disabled"; }; @@ -125,29 +144,13 @@ reg = <0x90000 0x200>; interrupts = <28>; clocks = <&gate_clk 4>; + pinctrl-0 = <&pmx_sdio>; + pinctrl-names = "default"; bus-width = <4>; cap-sdio-irq; cap-sd-highspeed; cap-mmc-highspeed; status = "disabled"; }; - - thermal@10078 { - compatible = "marvell,kirkwood-thermal"; - reg = <0x10078 0x4>; - status = "okay"; - }; - - i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - status = "disabled"; - }; - }; }; diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 142b9cd..bb4df40 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts @@ -66,8 +66,8 @@ button@1 { label = "Power push button"; - linux,code = <116>; - gpios = <&gpio0 16 1>; + linux,code = <KEY_POWER>; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; }; }; @@ -76,17 +76,17 @@ red-fail { label = "cloudbox:red:fail"; - gpios = <&gpio0 14 0>; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; }; blue-sata { label = "cloudbox:blue:sata"; - gpios = <&gpio0 15 0>; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; }; gpio_poweroff { compatible = "gpio-poweroff"; - gpios = <&gpio0 17 0>; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi index 053aa20..afebc15 100644 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -51,8 +51,8 @@ mvsdio@90000 { pinctrl-0 = <&pmx_sdio_gpios>; pinctrl-names = "default"; - wp-gpios = <&gpio1 5 0>; - cd-gpios = <&gpio1 6 0>; + wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts index e112ca6..bf7fe8a 100644 --- a/arch/arm/boot/dts/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/kirkwood-dns320.dts @@ -24,24 +24,24 @@ blue-power { label = "dns320:blue:power"; - gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ - linux,default-trigger = "default-on"; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + default-state = "keep"; }; blue-usb { label = "dns320:blue:usb"; - gpios = <&gpio1 11 1>; /* GPIO 43 Active Low */ + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; orange-l_hdd { label = "dns320:orange:l_hdd"; - gpios = <&gpio0 28 1>; /* GPIO 28 Active Low */ + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; orange-r_hdd { label = "dns320:orange:r_hdd"; - gpios = <&gpio0 27 1>; /* GPIO 27 Active Low */ + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; }; orange-usb { label = "dns320:orange:usb"; - gpios = <&gpio1 3 1>; /* GPIO 35 Active Low */ + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; /* GPIO 35 */ }; }; diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts index 5119fb8..cb9978c 100644 --- a/arch/arm/boot/dts/kirkwood-dns325.dts +++ b/arch/arm/boot/dts/kirkwood-dns325.dts @@ -24,24 +24,24 @@ white-power { label = "dns325:white:power"; - gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ - linux,default-trigger = "default-on"; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + default-state = "keep"; }; white-usb { label = "dns325:white:usb"; - gpios = <&gpio1 11 1>; /* GPIO 43 Active Low */ + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */ }; red-l_hdd { label = "dns325:red:l_hdd"; - gpios = <&gpio0 28 1>; /* GPIO 28 Active Low */ + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; red-r_hdd { label = "dns325:red:r_hdd"; - gpios = <&gpio0 27 1>; /* GPIO 27 Active Low */ + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; }; red-usb { label = "dns325:red:usb"; - gpios = <&gpio0 29 1>; /* GPIO 29 Active Low */ + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index aefa375..1208756 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -15,18 +15,18 @@ button@1 { label = "Power button"; - linux,code = <116>; - gpios = <&gpio1 2 1>; + linux,code = <KEY_POWER>; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; }; button@2 { label = "USB unmount button"; - linux,code = <161>; - gpios = <&gpio1 15 1>; + linux,code = <KEY_EJECTCD>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; button@3 { label = "Reset button"; - linux,code = <0x198>; - gpios = <&gpio1 16 1>; + linux,code = <KEY_RESTART>; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; @@ -35,8 +35,8 @@ compatible = "gpio-fan"; pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>; pinctrl-names = "default"; - gpios = <&gpio1 14 1 - &gpio1 13 1>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW + &gpio1 13 GPIO_ACTIVE_LOW>; gpio-fan,speed-map = <0 0 3000 1 6000 2>; @@ -46,7 +46,7 @@ compatible = "gpio-poweroff"; pinctrl-0 = <&pmx_power_off>; pinctrl-names = "default"; - gpios = <&gpio1 4 0>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index 33ff368..2a41c75 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -42,12 +42,12 @@ health { label = "status:green:health"; - gpios = <&gpio1 14 1>; - linux,default-trigger = "default-on"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + default-state = "keep"; }; fault { label = "status:orange:fault"; - gpios = <&gpio1 15 1>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; }; regulators { diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 6f62af9..a755837 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts @@ -87,15 +87,15 @@ bluetooth { label = "dreamplug:blue:bluetooth"; - gpios = <&gpio1 15 1>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; wifi { label = "dreamplug:green:wifi"; - gpios = <&gpio1 16 1>; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; wifi-ap { label = "dreamplug:green:wifi_ap"; - gpios = <&gpio1 17 1>; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index a43bebb..c2e5129 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -85,44 +85,44 @@ health { label = "status:green:health"; - gpios = <&gpio1 14 1>; - linux,default-trigger = "default-on"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + default-state = "keep"; }; fault { label = "status:orange:fault"; - gpios = <&gpio1 15 1>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; left0 { label = "status:white:left0"; - gpios = <&gpio1 10 0>; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; left1 { label = "status:white:left1"; - gpios = <&gpio1 11 0>; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; left2 { label = "status:white:left2"; - gpios = <&gpio1 12 0>; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; }; left3 { label = "status:white:left3"; - gpios = <&gpio1 13 0>; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; right0 { label = "status:white:right0"; - gpios = <&gpio1 6 0>; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; }; right1 { label = "status:white:right1"; - gpios = <&gpio1 7 0>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; right2 { label = "status:white:right2"; - gpios = <&gpio1 8 0>; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; right3 { label = "status:white:right3"; - gpios = <&gpio1 9 0>; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; }; regulators { @@ -141,7 +141,7 @@ enable-active-high; regulator-always-on; regulator-boot-on; - gpio = <&gpio0 29 0>; + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index d30a91a..0b557d5 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -45,10 +45,10 @@ nr-ports = <1>; }; + /* AzureWave AW-GH381 WiFi/BT */ mvsdio@90000 { status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; + non-removable; }; }; @@ -60,19 +60,19 @@ health-r { label = "guruplug:red:health"; - gpios = <&gpio1 14 1>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; health-g { label = "guruplug:green:health"; - gpios = <&gpio1 15 1>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; wmode-r { label = "guruplug:red:wmode"; - gpios = <&gpio1 16 1>; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; wmode-g { label = "guruplug:green:wmode"; - gpios = <&gpio1 17 1>; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index c5fb02f..6ccc788 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -63,13 +63,13 @@ button@1 { label = "USB Copy"; - linux,code = <133>; - gpios = <&gpio0 29 1>; + linux,code = <KEY_COPY>; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; button@2 { label = "Reset"; - linux,code = <0x198>; - gpios = <&gpio0 28 1>; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; }; @@ -81,16 +81,16 @@ green-os { label = "ib62x0:green:os"; - gpios = <&gpio0 25 0>; - linux,default-trigger = "default-on"; + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + default-state = "keep"; }; red-os { label = "ib62x0:red:os"; - gpios = <&gpio0 22 0>; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; }; usb-copy { label = "ib62x0:red:usb_copy"; - gpios = <&gpio0 27 0>; + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; }; }; @@ -98,7 +98,7 @@ compatible = "gpio-poweroff"; pinctrl-0 = <&pmx_power_off>; pinctrl-names = "default"; - gpios = <&gpio0 24 0>; + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 4a62b20..f763629 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -94,37 +94,37 @@ led-level { label = "led_level"; - gpios = <&gpio1 9 0>; - linux,default-trigger = "default-on"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; power-blue { label = "power:blue"; - gpios = <&gpio1 10 0>; - linux,default-trigger = "timer"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + default-state = "keep"; }; power-red { label = "power:red"; - gpios = <&gpio1 11 0>; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; usb1 { label = "usb1:blue"; - gpios = <&gpio1 12 0>; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; }; usb2 { label = "usb2:blue"; - gpios = <&gpio1 13 0>; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; usb3 { label = "usb3:blue"; - gpios = <&gpio1 14 0>; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; usb4 { label = "usb4:blue"; - gpios = <&gpio1 15 0>; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; }; otb { label = "otb:blue"; - gpios = <&gpio1 16 0>; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; }; }; @@ -137,14 +137,14 @@ button@1 { label = "OTB Button"; - linux,code = <133>; - gpios = <&gpio1 3 1>; + linux,code = <KEY_COPY>; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; button@2 { label = "Reset"; - linux,code = <0x198>; - gpios = <&gpio0 12 1>; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index d15395d..5890006 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -127,20 +127,20 @@ power_led { label = "status:white:power_led"; - gpios = <&gpio0 16 0>; - linux,default-trigger = "default-on"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + default-state = "keep"; }; rebuild_led { label = "status:white:rebuild_led"; - gpios = <&gpio1 4 0>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; health_led { label = "status:red:health_led"; - gpios = <&gpio1 5 0>; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; }; backup_led { label = "status:blue:backup_led"; - gpios = <&gpio0 15 0>; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; }; gpio-keys { @@ -154,18 +154,18 @@ Power { label = "Power Button"; - linux,code = <116>; - gpios = <&gpio0 14 1>; + linux,code = <KEY_POWER>; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; }; Reset { label = "Reset Button"; - linux,code = <0x198>; - gpios = <&gpio0 12 1>; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; }; OTB { label = "OTB Button"; - linux,code = <133>; - gpios = <&gpio1 3 1>; + linux,code = <KEY_COPY>; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index cd44f37..5b5808e 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -38,8 +38,8 @@ i2c@0 { compatible = "i2c-gpio"; - gpios = < &gpio0 8 0 /* sda */ - &gpio0 9 0 >; /* scl */ + gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */ + &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */ i2c-gpio,delay-us = <2>; /* ~100 kHz */ }; }; diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts new file mode 100644 index 0000000..c9e82ef --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-laplug.dts @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2013 Maxime Hadjinlian <maxime.hadjinlian@gmail.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "kirkwood.dtsi" +#include "kirkwood-6192.dtsi" + +/ { + model = "LaCie LaPlug"; + compatible = "lacie,laplug", "marvell,kirkwood-88f6192", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; /* 128 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + mbus { + pcie-controller { + status = "okay"; + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + status = "okay"; + }; + + i2c@11000 { + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; + status = "okay"; + + eeprom@50 { + compatible = "at,24c04"; + pagesize = <16>; + reg = <0x50>; + }; + }; + + pinctrl: pinctrl@10000 { + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button@1{ + label = "Power push button"; + linux,code = <KEY_POWER>; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + red-fail { + label = "laplug_v2:red:power"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + blue-power { + label = "laplug_v2:blue:power"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; + + usb_power_back1: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power Back 1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + + usb_power_back2: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "USB Power Back 2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + + usb_power_front: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "USB Power Front"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + /* Total size : 512MB */ + status = "okay"; + pinctrl-0 = <&pmx_nand>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; /* 1MB */ + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x1000000>; /* 16MB */ + }; + + partition@1100000 { + label = "rootfs"; + reg = <0x1100000 0x1EF00000>; /* 495MB */ + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 4e8f9e4..fc1cd3b 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -108,20 +108,20 @@ button@1 { label = "Function Button"; - linux,code = <357>; - gpios = <&gpio1 9 1>; + linux,code = <KEY_OPTION>; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; button@2 { label = "Power-on Switch"; - linux,code = <0>; + linux,code = <KEY_RESERVED>; linux,input-type = <5>; - gpios = <&gpio1 10 1>; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; button@3 { label = "Power-auto Switch"; - linux,code = <1>; + linux,code = <KEY_ESC>; linux,input-type = <5>; - gpios = <&gpio1 11 1>; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; }; @@ -134,28 +134,28 @@ led@1 { label = "lsxl:blue:func"; - gpios = <&gpio1 4 1>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; led@2 { label = "lsxl:red:alarm"; - gpios = <&gpio1 5 1>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; led@3 { label = "lsxl:amber:info"; - gpios = <&gpio1 6 1>; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; led@4 { label = "lsxl:blue:power"; - gpios = <&gpio1 7 1>; - linux,default-trigger = "default-on"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + default-state = "keep"; }; led@5 { label = "lsxl:red:func"; - gpios = <&gpio1 16 1>; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; @@ -163,13 +163,13 @@ compatible = "gpio-fan"; pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; pinctrl-names = "default"; - gpios = <&gpio0 19 1 - &gpio0 18 1>; + gpios = <&gpio0 19 GPIO_ACTIVE_LOW + &gpio0 18 GPIO_ACTIVE_LOW>; gpio-fan,speed-map = <0 3 1500 2 3250 1 5000 0>; - alarm-gpios = <&gpio1 8 0>; + alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; restart_poweroff { diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 6c1ec27..c20607c 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -110,7 +110,7 @@ pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; pinctrl-names = "default"; status = "okay"; - cd-gpios = <&gpio1 15 1>; + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; /* No WP GPIO */ }; }; @@ -126,36 +126,36 @@ health { label = "status:green:health"; - gpios = <&gpio0 7 1>; + gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; }; user1o { label = "user1:orange"; - gpios = <&gpio1 8 1>; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; default-state = "on"; }; user1g { label = "user1:green"; - gpios = <&gpio1 9 1>; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; default-state = "on"; }; user0o { label = "user0:orange"; - gpios = <&gpio1 12 1>; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; default-state = "on"; }; user0g { label = "user0:green"; - gpios = <&gpio1 13 1>; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; default-state = "on"; }; misc { label = "status:orange:misc"; - gpios = <&gpio1 14 1>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; default-state = "on"; }; diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index 6317e1d..dc86429 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -90,17 +90,17 @@ green-status { label = "gtw:green:Status"; - gpios = <&gpio0 20 0>; + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; }; red-status { label = "gtw:red:Status"; - gpios = <&gpio0 21 0>; + gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; }; green-usb { label = "gtw:green:USB"; - gpios = <&gpio0 12 0>; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; }; @@ -113,13 +113,13 @@ button@1 { label = "SWR Button"; - linux,code = <0x198>; /* KEY_RESTART */ - gpios = <&gpio1 15 1>; + linux,code = <KEY_RESTART>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; button@2 { label = "WPS Button"; - linux,code = <0x211>; /* KEY_WPS_BUTTON */ - gpios = <&gpio1 14 1>; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index e6a102c..4d2a8db 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -1,3 +1,14 @@ +/* + * Device Tree file for NETGEAR ReadyNAS Duo v2 + * + * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + /dts-v1/; #include "kirkwood.dtsi" @@ -32,41 +43,50 @@ marvell,pins = "mpp47"; marvell,function = "gpio"; }; + pmx_button_backup: pmx-button-backup { marvell,pins = "mpp45"; marvell,function = "gpio"; }; + pmx_button_reset: pmx-button-reset { marvell,pins = "mpp13"; marvell,function = "gpio"; }; + pmx_led_blue_power: pmx-led-blue-power { marvell,pins = "mpp31"; marvell,function = "gpio"; }; + pmx_led_blue_activity: pmx-led-blue-activity { marvell,pins = "mpp38"; marvell,function = "gpio"; }; + pmx_led_blue_disk1: pmx-led-blue-disk1 { marvell,pins = "mpp23"; marvell,function = "gpio"; }; + pmx_led_blue_disk2: pmx-led-blue-disk2 { marvell,pins = "mpp22"; marvell,function = "gpio"; }; + pmx_led_blue_backup: pmx-led-blue-backup { marvell,pins = "mpp29"; marvell,function = "gpio"; }; + + pmx_poweroff: pmx-poweroff { + marvell,pins = "mpp30"; + marvell,function = "gpio"; + }; }; clocks { - #address-cells = <1>; - #size-cells = <0>; - - g762_clk: fixedclk { + g762_clk: g762-oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <8192>; @@ -112,69 +132,80 @@ power_led { label = "status:blue:power_led"; - gpios = <&gpio0 31 1>; /* GPIO 31 Active Low */ - linux,default-trigger = "default-on"; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + default-state = "keep"; }; + activity_led { label = "status:blue:activity_led"; - gpios = <&gpio1 6 1>; /* GPIO 38 Active Low */ + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; + disk1_led { label = "status:blue:disk1_led"; - gpios = <&gpio0 23 1>; /* GPIO 23 Active Low */ + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; }; + disk2_led { label = "status:blue:disk2_led"; - gpios = <&gpio0 22 1>; /* GPIO 22 Active Low */ + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; }; + backup_led { label = "status:blue:backup_led"; - gpios = <&gpio0 29 1>; /* GPIO 29 Active Low*/ + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_power &pmx_button_backup &pmx_button_reset>; pinctrl-names = "default"; - button@1 { + power-button { label = "Power Button"; - linux,code = <116>; /* KEY_POWER */ - gpios = <&gpio1 15 1>; + linux,code = <KEY_POWER>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - button@2 { + + reset-button { label = "Reset Button"; - linux,code = <0x198>; /* KEY_RESTART */ - gpios = <&gpio0 13 1>; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; }; - button@3 { + + backup-button { label = "Backup Button"; - linux,code = <133>; /* KEY_COPY */ - gpios = <&gpio1 13 1>; + linux,code = <KEY_COPY>; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB 3.0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 14 0>; - }; - }; + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_poweroff>; + pinctrl-names = "default"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb3_regulator: usb3-regulator { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB 3.0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; }; &nand { @@ -210,7 +241,7 @@ &mdio { status = "okay"; - ethphy0: ethernet-phy@0 { + ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ device_type = "ethernet-phy"; reg = <0>; }; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts new file mode 100644 index 0000000..7c8a0d9 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts @@ -0,0 +1,268 @@ +/* + * Device Tree file for NETGEAR ReadyNAS NV+ v2 + * + * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "NETGEAR ReadyNAS NV+ v2"; + compatible = "netgear,readynas-nv+-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { /* 256 MB */ + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + mbus { + pcie-controller { + status = "okay"; + + /* Connected to NEC uPD720200 USB 3.0 controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + pmx_button_power: pmx-button-power { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_button_backup: pmx-button-backup { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_led_blue_power: pmx-led-blue-power { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + pmx_led_blue_backup: pmx-led-blue-backup { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk1: pmx-led-blue-disk1 { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk2: pmx-led-blue-disk2 { + marvell,pins = "mpp23"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk3: pmx-led-blue-disk3 { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk4: pmx-led-blue-disk4 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_poweroff: pmx-poweroff { + marvell,pins = "mpp30"; + marvell,function = "gpio"; + }; + }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8192>; + }; + }; + + i2c@11000 { + status = "okay"; + + rs5c372a: rs5c372a@32 { + compatible = "ricoh,rs5c372a"; + reg = <0x32>; + }; + + g762: g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + }; + + serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + status = "okay"; + }; + + sata@80000 { /* Connected to Marvell 88SM4140 SATA port multiplier */ + status = "okay"; + nr-ports = <1>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup + &pmx_led_blue_disk1 &pmx_led_blue_disk2 + &pmx_led_blue_disk3 &pmx_led_blue_disk3 >; + pinctrl-names = "default"; + + power_led { + label = "status:blue:power_led"; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + backup_led { + label = "status:blue:backup_led"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + + disk1_led { + label = "status:blue:disk1_led"; + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + }; + + disk2_led { + label = "status:blue:disk2_led"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + disk3_led { + label = "status:blue:disk3_led"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + + disk4_led { + label = "status:blue:disk4_led"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_button_power &pmx_button_backup + &pmx_button_reset>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = <KEY_POWER>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reset-button { + label = "Reset Button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + + backup-button { + label = "Backup Button"; + linux,code = <KEY_COPY>; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_poweroff>; + pinctrl-names = "default"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb3_regulator: usb3-regulator { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB 3.0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x1000000>; + }; + + partition@1800000 { + label = "jffs2"; + reg = <0x1800000 0x6800000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index 2fcb82e..ae1ccbe 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -64,8 +64,8 @@ button@1 { label = "Power push button"; - linux,code = <116>; - gpios = <&gpio1 0 0>; + linux,code = <KEY_POWER>; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; }; }; @@ -74,13 +74,13 @@ red-fail { label = "ns2:red:fail"; - gpios = <&gpio0 12 0>; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; }; gpio_poweroff { compatible = "gpio-poweroff"; - gpios = <&gpio0 31 0>; + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts index 2796070..1f2ca60 100644 --- a/arch/arm/boot/dts/kirkwood-ns2lite.dts +++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts @@ -25,8 +25,8 @@ blue-sata { label = "ns2:blue:sata"; - gpios = <&gpio0 30 1>; - linux,default-trigger = "default-on"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ide-disk"; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts index defdc77..72c78d0 100644 --- a/arch/arm/boot/dts/kirkwood-ns2max.dts +++ b/arch/arm/boot/dts/kirkwood-ns2max.dts @@ -22,10 +22,10 @@ gpio_fan { compatible = "gpio-fan"; - gpios = <&gpio0 22 1 - &gpio0 7 1 - &gpio1 1 1 - &gpio0 23 1>; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW + &gpio0 7 GPIO_ACTIVE_LOW + &gpio1 1 GPIO_ACTIVE_LOW + &gpio0 23 GPIO_ACTIVE_LOW>; gpio-fan,speed-map = < 0 0 1500 15 @@ -36,7 +36,7 @@ 3300 10 4300 9 5500 8>; - alarm-gpios = <&gpio0 25 1>; + alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; }; ns2-leds { diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts index adbafdd..c441bf6 100644 --- a/arch/arm/boot/dts/kirkwood-ns2mini.dts +++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts @@ -23,10 +23,10 @@ gpio_fan { compatible = "gpio-fan"; - gpios = <&gpio0 22 1 - &gpio0 7 1 - &gpio1 1 1 - &gpio0 23 1>; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW + &gpio0 7 GPIO_ACTIVE_LOW + &gpio1 1 GPIO_ACTIVE_LOW + &gpio0 23 GPIO_ACTIVE_LOW>; gpio-fan,speed-map = < 0 0 3000 15 @@ -37,7 +37,7 @@ 7140 10 7980 9 9200 8>; - alarm-gpios = <&gpio0 25 1>; + alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; }; ns2-leds { diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi index e3f915d..aa78c2d 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi @@ -40,7 +40,7 @@ compatible = "gpio-poweroff"; pinctrl-0 = <&pmx_pwr_off>; pinctrl-names = "default"; - gpios = <&gpio1 16 0>; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; }; regulators { @@ -58,7 +58,7 @@ regulator-max-microvolt = <5000000>; regulator-always-on; regulator-boot-on; - gpio = <&gpio0 21 0>; + gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index b5418bc..03fa24c 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -119,18 +119,18 @@ button@1 { label = "Power Button"; - linux,code = <116>; - gpios = <&gpio1 14 0>; + linux,code = <KEY_POWER>; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; button@2 { label = "Copy Button"; - linux,code = <133>; - gpios = <&gpio1 5 1>; + linux,code = <KEY_COPY>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; button@3 { label = "Reset Button"; - linux,code = <0x198>; - gpios = <&gpio1 4 1>; + linux,code = <KEY_RESTART>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; }; @@ -145,43 +145,43 @@ green-sys { label = "nsa310:green:sys"; - gpios = <&gpio0 28 0>; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; }; red-sys { label = "nsa310:red:sys"; - gpios = <&gpio0 29 0>; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; green-hdd { label = "nsa310:green:hdd"; - gpios = <&gpio1 9 0>; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; red-hdd { label = "nsa310:red:hdd"; - gpios = <&gpio1 10 0>; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; green-esata { label = "nsa310:green:esata"; - gpios = <&gpio0 12 0>; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; red-esata { label = "nsa310:red:esata"; - gpios = <&gpio0 13 0>; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; }; green-usb { label = "nsa310:green:usb"; - gpios = <&gpio0 15 0>; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; red-usb { label = "nsa310:red:usb"; - gpios = <&gpio0 16 0>; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; }; green-copy { label = "nsa310:green:copy"; - gpios = <&gpio1 7 0>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; red-copy { label = "nsa310:red:copy"; - gpios = <&gpio1 8 0>; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts index ab0212b..a5e7794 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310a.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts @@ -107,18 +107,18 @@ button@1 { label = "Power Button"; - linux,code = <116>; - gpios = <&gpio1 14 0>; + linux,code = <KEY_POWER>; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; button@2 { label = "Copy Button"; - linux,code = <133>; - gpios = <&gpio1 5 1>; + linux,code = <KEY_COPY>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; button@3 { label = "Reset Button"; - linux,code = <0x198>; - gpios = <&gpio1 4 1>; + linux,code = <KEY_RESTART>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; }; @@ -127,39 +127,39 @@ green-sys { label = "nsa310:green:sys"; - gpios = <&gpio0 28 0>; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; }; red-sys { label = "nsa310:red:sys"; - gpios = <&gpio0 29 0>; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; green-hdd { label = "nsa310:green:hdd"; - gpios = <&gpio1 9 0>; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; red-hdd { label = "nsa310:red:hdd"; - gpios = <&gpio1 10 0>; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; green-esata { label = "nsa310:green:esata"; - gpios = <&gpio0 12 0>; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; red-esata { label = "nsa310:red:esata"; - gpios = <&gpio0 13 0>; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; }; green-usb { label = "nsa310:green:usb"; - gpios = <&gpio0 15 0>; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; green-copy { label = "nsa310:green:copy"; - gpios = <&gpio1 7 0>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; red-copy { label = "nsa310:red:copy"; - gpios = <&gpio1 8 0>; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index f0e3d21..5c6a4f1 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -101,17 +101,17 @@ led-red { label = "obsa6:red:stat"; - gpios = <&gpio1 9 1>; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; led-green { label = "obsa6:green:stat"; - gpios = <&gpio1 10 1>; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; led-yellow { label = "obsa6:yellow:stat"; - gpios = <&gpio1 11 1>; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; }; @@ -124,8 +124,8 @@ button@1 { label = "Init Button"; - linux,code = <116>; - gpios = <&gpio1 6 0>; + linux,code = <KEY_POWER>; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index 851fb2a..c054ef6 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -126,17 +126,17 @@ led-red { label = "obsa7:red:stat"; - gpios = <&gpio1 9 1>; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; led-green { label = "obsa7:green:stat"; - gpios = <&gpio1 10 1>; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; led-yellow { label = "obsa7:yellow:stat"; - gpios = <&gpio1 11 1>; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; }; @@ -149,8 +149,8 @@ button@1 { label = "Init Button"; - linux,code = <116>; - gpios = <&gpio1 6 0>; + linux,code = <KEY_POWER>; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi index 1173d7f..7b1cd99 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi @@ -1,5 +1,5 @@ /* - * kirkwood-sheevaplug-common.dts - Common parts for Sheevaplugs + * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs * * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> * diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts index eac6a21..e2b4ea4 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts @@ -24,8 +24,8 @@ pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; pinctrl-names = "default"; status = "okay"; - cd-gpios = <&gpio1 12 1>; - wp-gpios = <&gpio1 15 0>; + cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; }; }; @@ -36,8 +36,8 @@ health { label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 1>; - linux,default-trigger = "default-on"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + default-state = "keep"; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts index bb61918..82f6abf 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts +++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts @@ -1,5 +1,5 @@ /* - * kirkwood-sheevaplug-esata.dts - Device tree file for Sheevaplug + * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug * * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> * @@ -31,13 +31,13 @@ health { label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 1>; - linux,default-trigger = "default-on"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + default-state = "keep"; }; misc { label = "sheevaplug:red:misc"; - gpios = <&gpio1 14 1>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 320da67..40d6adf 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -131,25 +131,25 @@ disk { label = "topkick:yellow:disk"; - gpios = <&gpio0 21 1>; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; linux,default-trigger = "ide-disk"; }; system2 { label = "topkick:red:system"; - gpios = <&gpio1 5 1>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; system { label = "topkick:blue:system"; - gpios = <&gpio1 6 1>; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; default-state = "on"; }; wifi { label = "topkick:green:wifi"; - gpios = <&gpio1 7 1>; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; }; wifi2 { label = "topkick:yellow:wifi"; - gpios = <&gpio1 16 1>; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; regulators { diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index f755bc1..c17ae45 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts @@ -41,13 +41,13 @@ button@1 { label = "USB Copy"; - linux,code = <133>; - gpios = <&gpio0 15 1>; + linux,code = <KEY_COPY>; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; }; button@2 { label = "Reset"; - linux,code = <0x198>; - gpios = <&gpio0 16 1>; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index 345562f..0713d072 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -51,13 +51,13 @@ button@1 { label = "USB Copy"; - linux,code = <133>; - gpios = <&gpio1 11 1>; + linux,code = <KEY_COPY>; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; button@2 { label = "Reset"; - linux,code = <0x198>; - gpios = <&gpio1 5 1>; + linux,code = <KEY_RESTART>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 8b73c80..81e6c40 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -1,4 +1,6 @@ /include/ "skeleton.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) @@ -68,39 +70,21 @@ #address-cells = <1>; #size-cells = <1>; - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x1500 0x20>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - intc: main-interrupt-ctrl@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <1>; - marvell,#interrupts = <6>; - }; - core_clk: core-clocks@10030 { compatible = "marvell,kirkwood-core-clock"; reg = <0x10030 0x4>; - #clock-cells = <1>; + #clock-cells = <1>; + }; + + spi@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <23>; + reg = <0x10600 0x28>; + clocks = <&gate_clk 7>; + status = "disabled"; }; gpio0: gpio@10100 { @@ -127,6 +111,17 @@ clocks = <&gate_clk 7>; }; + i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <29>; + clock-frequency = <100000>; + clocks = <&gate_clk 7>; + status = "disabled"; + }; + serial@12000 { compatible = "ns16550a"; reg = <0x12000 0x100>; @@ -145,15 +140,18 @@ status = "disabled"; }; - spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <23>; - reg = <0x10600 0x28>; - clocks = <&gate_clk 7>; - status = "disabled"; + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x80>, <0x1500 0x20>; + }; + + bridge_intc: bridge-interrupt-ctrl@20110 { + compatible = "marvell,orion-bridge-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <1>; + marvell,#interrupts = <6>; }; gate_clk: clock-gating-control@2011c { @@ -163,6 +161,21 @@ #clock-cells = <1>; }; + intc: main-interrupt-ctrl@20200 { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20200 0x10>, <0x20210 0x10>; + }; + + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; + wdt: watchdog-timer@20300 { compatible = "marvell,orion-wdt"; reg = <0x20300 0x28>; @@ -172,6 +185,14 @@ status = "okay"; }; + ehci@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <19>; + clocks = <&gate_clk 3>; + status = "okay"; + }; + xor@60800 { compatible = "marvell,orion-xor"; reg = <0x60800 0x100 @@ -212,37 +233,6 @@ }; }; - ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <19>; - clocks = <&gate_clk 3>; - status = "okay"; - }; - - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <29>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - status = "disabled"; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <46>; - clocks = <&gate_clk 0>; - status = "disabled"; - - /* add phy nodes in board file */ - }; - eth0: ethernet-controller@72000 { compatible = "marvell,kirkwood-eth"; #address-cells = <1>; @@ -263,6 +253,18 @@ }; }; + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <46>; + clocks = <&gate_clk 0>; + status = "disabled"; + + /* add phy nodes in board file */ + }; + eth1: ethernet-controller@76000 { compatible = "marvell,kirkwood-eth"; #address-cells = <1>; @@ -282,5 +284,23 @@ /* set phy-handle property in board file */ }; }; + + sata_phy0: sata-phy@82000 { + compatible = "marvell,mvebu-sata-phy"; + reg = <0x82000 0x0334>; + clocks = <&gate_clk 14>; + clock-names = "sata"; + #phy-cells = <0>; + status = "ok"; + }; + + sata_phy1: sata-phy@84000 { + compatible = "marvell,mvebu-sata-phy"; + reg = <0x84000 0x0334>; + clocks = <&gate_clk 15>; + clock-names = "sata"; + #phy-cells = <0>; + status = "ok"; + }; }; }; diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxart-uc7112lx.dts new file mode 100644 index 0000000..90749d5 --- /dev/null +++ b/arch/arm/boot/dts/moxart-uc7112lx.dts @@ -0,0 +1,109 @@ +/* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX + * + * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com> + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; +/include/ "moxart.dtsi" + +/ { + model = "MOXA UC-7112-LX"; + compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart"; + + memory { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + flash@80000000,0 { + compatible = "numonyx,js28f128", "cfi-flash"; + reg = <0x80000000 0x1000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "bootloader"; + reg = <0x0 0x40000>; + }; + partition@40000 { + label = "linux kernel"; + reg = <0x40000 0x1C0000>; + }; + partition@200000 { + label = "root filesystem"; + reg = <0x200000 0x800000>; + }; + partition@a00000 { + label = "user filesystem"; + reg = <0xa00000 0x600000>; + }; + }; + + leds { + compatible = "gpio-leds"; + user-led { + label = "ready-led"; + gpios = <&gpio 27 0x1>; + default-state = "on"; + linux,default-trigger = "default-on"; + }; + }; + + gpio_keys_polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <500>; + button@25 { + label = "GPIO Reset"; + linux,code = <116>; + gpios = <&gpio 25 1>; + }; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p1 rw rootwait"; + }; +}; + +&clk_pll { + clocks = <&ref12>; +}; + +&sdhci { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + ethphy0: ethernet-phy@1 { + device_type = "ethernet-phy"; + compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mdio1 { + status = "okay"; + + ethphy1: ethernet-phy@1 { + device_type = "ethernet-phy"; + compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mac0 { + status = "okay"; +}; + +&mac1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi new file mode 100644 index 0000000..da1d8ef --- /dev/null +++ b/arch/arm/boot/dts/moxart.dtsi @@ -0,0 +1,154 @@ +/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC + * + * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com> + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "moxa,moxart"; + model = "MOXART"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "faraday,fa526"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref12: ref12M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x90000000 0x10000000>; + ranges; + + intc: interrupt-controller@98800000 { + compatible = "moxa,moxart-ic"; + reg = <0x98800000 0x38>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-mask = <0x00080000>; + }; + + clk_pll: clk_pll@98100000 { + compatible = "moxa,moxart-pll-clock"; + #clock-cells = <0>; + reg = <0x98100000 0x34>; + }; + + clk_apb: clk_apb@98100000 { + compatible = "moxa,moxart-apb-clock"; + #clock-cells = <0>; + reg = <0x98100000 0x34>; + clocks = <&clk_pll>; + }; + + timer: timer@98400000 { + compatible = "moxa,moxart-timer"; + reg = <0x98400000 0x42>; + interrupts = <19 1>; + clocks = <&clk_apb>; + }; + + gpio: gpio@98700000 { + gpio-controller; + #gpio-cells = <2>; + compatible = "moxa,moxart-gpio"; + reg = <0x98700000 0xC>; + }; + + rtc: rtc { + compatible = "moxa,moxart-rtc"; + gpio-rtc-sclk = <&gpio 5 0>; + gpio-rtc-data = <&gpio 6 0>; + gpio-rtc-reset = <&gpio 7 0>; + }; + + dma: dma@90500000 { + compatible = "moxa,moxart-dma"; + reg = <0x90500080 0x40>; + interrupts = <24 0>; + #dma-cells = <1>; + }; + + watchdog: watchdog@98500000 { + compatible = "moxa,moxart-watchdog"; + reg = <0x98500000 0x10>; + clocks = <&clk_apb>; + }; + + sdhci: sdhci@98e00000 { + compatible = "moxa,moxart-sdhci"; + reg = <0x98e00000 0x5C>; + interrupts = <5 0>; + clocks = <&clk_apb>; + dmas = <&dma 5>, + <&dma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mdio0: mdio@90900090 { + compatible = "moxa,moxart-mdio"; + reg = <0x90900090 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mdio1: mdio@92000090 { + compatible = "moxa,moxart-mdio"; + reg = <0x92000090 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mac0: mac@90900000 { + compatible = "moxa,moxart-mac"; + reg = <0x90900000 0x90>; + interrupts = <25 0>; + phy-handle = <ðphy0>; + phy-mode = "mii"; + status = "disabled"; + }; + + mac1: mac@92000000 { + compatible = "moxa,moxart-mac"; + reg = <0x92000000 0x90>; + interrupts = <27 0>; + phy-handle = <ðphy1>; + phy-mode = "mii"; + status = "disabled"; + }; + + uart0: uart@98200000 { + compatible = "ns16550a"; + reg = <0x98200000 0x20>; + interrupts = <31 8>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14745600>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index d0c5b37..5377ddf 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -145,7 +145,7 @@ compatible = "ti,omap2-rng"; ti,hwmods = "rng"; reg = <0x480a0000 0x50>; - interrupts = <36>; + interrupts = <52>; }; sham: sham@480a4000 { diff --git a/arch/arm/boot/dts/omap2420-n800.dts b/arch/arm/boot/dts/omap2420-n800.dts new file mode 100644 index 0000000..d8c1b42 --- /dev/null +++ b/arch/arm/boot/dts/omap2420-n800.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "omap2420-n8x0-common.dtsi" + +/ { + model = "Nokia N800"; + compatible = "nokia,n800", "nokia,n8x0", "ti,omap2420", "ti,omap2"; +}; diff --git a/arch/arm/boot/dts/omap2420-n810-wimax.dts b/arch/arm/boot/dts/omap2420-n810-wimax.dts new file mode 100644 index 0000000..6b25b03 --- /dev/null +++ b/arch/arm/boot/dts/omap2420-n810-wimax.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "omap2420-n8x0-common.dtsi" + +/ { + model = "Nokia N810 WiMax"; + compatible = "nokia,n810-wimax", "nokia,n8x0", "ti,omap2420", "ti,omap2"; +}; diff --git a/arch/arm/boot/dts/omap2420-n810.dts b/arch/arm/boot/dts/omap2420-n810.dts new file mode 100644 index 0000000..21baec1 --- /dev/null +++ b/arch/arm/boot/dts/omap2420-n810.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "omap2420-n8x0-common.dtsi" + +/ { + model = "Nokia N810"; + compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2"; +}; diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi new file mode 100644 index 0000000..89608b2 --- /dev/null +++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi @@ -0,0 +1,99 @@ +#include "omap2420.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x8000000>; /* 128 MB */ + }; + + ocp { + i2c@0 { + compatible = "i2c-cbus-gpio"; + gpios = <&gpio3 2 0 /* gpio66 clk */ + &gpio3 1 0 /* gpio65 dat */ + &gpio3 0 0 /* gpio64 sel */ + >; + #address-cells = <1>; + #size-cells = <0>; + retu_mfd: retu@1 { + compatible = "retu-mfd"; + interrupt-parent = <&gpio4>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + reg = <0x1>; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&gpmc { + ranges = <0 0 0x04000000 0x10000000>; + + /* gpio-irq for dma: 26 */ + + onenand@0,0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x10000000>; + + gpmc,sync-read; + gpmc,burst-length = <16>; + gpmc,burst-read; + gpmc,burst-wrap; + gpmc,device-width = <2>; + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <127>; + gpmc,cs-wr-off-ns = <109>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <18>; + gpmc,adv-wr-off-ns = <18>; + gpmc,oe-on-ns = <27>; + gpmc,oe-off-ns = <127>; + gpmc,we-on-ns = <27>; + gpmc,we-off-ns = <72>; + gpmc,rd-cycle-ns = <145>; + gpmc,wr-cycle-ns = <136>; + gpmc,access-ns = <118>; + gpmc,page-burst-access-ns = <27>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <9>; + gpmc,sync-clk-ps = <27000>; + + /* MTD partition table corresponding to old board-n8x0 file. */ + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x00020000>; + read-only; + }; + partition@1 { + label = "config"; + reg = <0x00020000 0x00060000>; + }; + partition@2 { + label = "kernel"; + reg = <0x00080000 0x00200000>; + }; + partition@3 { + label = "initfs"; + reg = <0x00280000 0x00400000>; + }; + partition@4 { + label = "rootfs"; + reg = <0x00680000 0x0f980000>; + }; + partition@5 { + label = "omap2-onenand"; + reg = <0x00000000 0x10000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/omap2430-sdp.dts new file mode 100644 index 0000000..2c90d29 --- /dev/null +++ b/arch/arm/boot/dts/omap2430-sdp.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap2430.dtsi" + +/ { + model = "TI OMAP2430 SDP"; + compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x8000000>; /* 128 MB */ + }; +}; + +&i2c2 { + clock-frequency = <100000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + }; +}; + +#include "twl4030.dtsi" + +&mmc1 { + vmmc-supply = <&vmmc1>; + bus-width = <4>; +}; + +&gpmc { + ranges = <5 0 0x08000000 0x01000000>; + ethernet@gpmc { + compatible = "smsc,lan91c94"; + interrupt-parent = <&gpio5>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */ + reg = <5 0x300 0xf>; + bank-width = <2>; + gpmc,mux-add-data; + }; +}; + diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index df33a50..447e714 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -99,7 +99,7 @@ &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = < - &hsusbb2_pins + &hsusb2_pins >; uart3_pins: pinmux_uart3_pins { @@ -109,20 +109,32 @@ >; }; - hsusbb2_pins: pinmux_hsusbb2_pins { + hsusb2_pins: pinmux_hsusb2_pins { pinctrl-single,pins = < - 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ >; }; }; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 3ba4a62..5053766d 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -93,23 +93,17 @@ &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = < - &hsusbb2_pins + &hsusb2_pins >; - hsusbb2_pins: pinmux_hsusbb2_pins { + hsusb2_pins: pinmux_hsusb2_pins { pinctrl-single,pins = < - 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ >; }; @@ -121,6 +115,24 @@ }; }; +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; +}; + &i2c1 { clock-frequency = <2600000>; diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts new file mode 100644 index 0000000..486f4d6 --- /dev/null +++ b/arch/arm/boot/dts/omap3-cm-t3730.dts @@ -0,0 +1,104 @@ +/* + * Support for CompuLab CM-T3730 + */ +/dts-v1/; + +#include "omap36xx.dtsi" +#include "omap3-cm-t3x30.dtsi" + +/ { + model = "CompuLab CM-T3730"; + compatible = "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; + + wl12xx_vmmc2: wl12xx_vmmc2 { + compatible = "regulator-fixed"; + regulator-name = "vw1271"; + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; /* gpio73 */ + startup-delay-us = <20000>; + enable-active-high; + }; + + wl12xx_vaux2: wl12xx_vaux2 { + compatible = "regulator-fixed"; + regulator-name = "vwl1271_vaux2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vaux2>; + }; +}; + +&omap3_pmx_core { + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + >; + }; + + smsc1_pins: pinmux_smsc1_pins { + pinctrl-single,pins = < + 0x88 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ + 0x16a (PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + wl12xx_gpio: pinmux_wl12xx_gpio { + pinctrl-single,pins = < + 0xb2 (PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ + 0x134 (PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ + >; + }; +}; + +&mmc1 { + vmmc-supply = <&vmmc1>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&wl12xx_vmmc2>; + vmmc_aux-supply = <&wl12xx_vaux2>; + non-removable; + bus-width = <4>; + cap-power-off-card; +}; + +&smsc1 { + pinctrl-names = "default"; + pinctrl-0 = <&smsc1_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi new file mode 100644 index 0000000..3a9f004 --- /dev/null +++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi @@ -0,0 +1,95 @@ +/* + * Common support for CompuLab CM-T3530 and CM-T3730 + */ + +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + leds { + compatible = "gpio-leds"; + ledb { + label = "cm-t35:green"; + gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */ + linux,default-trigger = "heartbeat"; + }; + }; + + vddvario: regulator-vddvario { + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; + }; + + vdd33a: regulator-vdd33a { + compatible = "regulator-fixed"; + regulator-name = "vdd33a"; + regulator-always-on; + }; +}; + +&gpmc { + ranges = <5 0 0x2c000000 0x01000000>; + + smsc1: ethernet@5,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + interrupt-parent = <&gpio6>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + reg = <5 0 0xff>; + bank-width = <2>; + gpmc,mux-add-data; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <186>; + gpmc,cs-wr-off-ns = <186>; + gpmc,adv-on-ns = <12>; + gpmc,adv-rd-off-ns = <48>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <54>; + gpmc,oe-off-ns = <168>; + gpmc,we-on-ns = <54>; + gpmc,we-off-ns = <168>; + gpmc,rd-cycle-ns = <186>; + gpmc,wr-cycle-ns = <186>; + gpmc,access-ns = <114>; + gpmc,page-burst-access-ns = <6>; + gpmc,bus-turnaround-ns = <12>; + gpmc,cycle2cycle-delay-ns = <18>; + gpmc,wr-data-mux-bus-ns = <90>; + gpmc,wr-access-ns = <186>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + vddvario-supply = <&vddvario>; + vdd33a-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&i2c3 { + clock-frequency = <400000>; +}; + +&twl_gpio { + ti,use-leds; +}; diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index 165aaf7..c1700932 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -133,8 +133,6 @@ 0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ >; }; - - leds_pins: pinmux_leds_pins { }; }; &i2c1 { diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index 1c7e74d..25a2b5f 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts @@ -66,28 +66,10 @@ &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = < - &hsusbb1_pins &tfp410_pins &dss_pins >; - hsusbb1_pins: pinmux_hsusbb1_pins { - pinctrl-single,pins = < - 0x5aa (PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ - 0x5a8 (PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ - 0x5bc (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ - 0x5be (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ - 0x5ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ - 0x5ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ - 0x5b0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ - 0x5b2 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ - 0x5b4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ - 0x5b6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ - 0x5b8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ - 0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ - >; - }; - tfp410_pins: tfp410_dvi_pins { pinctrl-single,pins = < 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ @@ -128,12 +110,36 @@ }; }; -&leds_pins { - pinctrl-single,pins = < - 0x5c4 (PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ - 0x5c6 (PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ - 0x5c8 (PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb1_pins >; + + hsusbb1_pins: pinmux_hsusbb1_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ + OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ + OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ + OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ + OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ + OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ + >; + }; + + leds_pins: pinmux_leds_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ + >; + }; }; &i2c3 { diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts index 02a23f8..145c58c 100644 --- a/arch/arm/boot/dts/omap3-igep0030.dts +++ b/arch/arm/boot/dts/omap3-igep0030.dts @@ -46,10 +46,12 @@ }; }; -&leds_pins { - pinctrl-single,pins = < - 0x5b0 (PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ - >; +&omap3_pmx_core2 { + leds_pins: pinmux_leds_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ + >; + }; }; &gpmc { diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts new file mode 100644 index 0000000..ddce0d8 --- /dev/null +++ b/arch/arm/boot/dts/omap3-ldp.dts @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap34xx.dtsi" +#include "omap-gpmc-smsc911x.dtsi" + +/ { + model = "TI OMAP3430 LDP (Zoom1 Labrador)"; + compatible = "ti,omap3-ldp", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x8000000>; /* 128 MB */ + }; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_pins>; + + key_enter { + label = "enter"; + gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* gpio101 */ + linux,code = <0x0107001c>; /* KEY_ENTER */ + gpio-key,wakeup; + }; + + key_f1 { + label = "f1"; + gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* gpio102 */ + linux,code = <0x0303003b>; /* KEY_F1 */ + gpio-key,wakeup; + }; + + key_f2 { + label = "f2"; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* gpio103 */ + linux,code = <0x0403003c>; /* KEY_F2 */ + gpio-key,wakeup; + }; + + key_f3 { + label = "f3"; + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* gpio104 */ + linux,code = <0x0503003d>; /* KEY_F3 */ + gpio-key,wakeup; + }; + + key_f4 { + label = "f4"; + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* gpio105 */ + linux,code = <0x0704003e>; /* KEY_F4 */ + gpio-key,wakeup; + }; + + key_left { + label = "left"; + gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */ + linux,code = <0x04070069>; /* KEY_LEFT */ + gpio-key,wakeup; + }; + + key_right { + label = "right"; + gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* gpio107 */ + linux,code = <0x0507006a>; /* KEY_RIGHT */ + gpio-key,wakeup; + }; + + key_up { + label = "up"; + gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* gpio108 */ + linux,code = <0x06070067>; /* KEY_UP */ + gpio-key,wakeup; + }; + + key_down { + label = "down"; + gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* gpio109 */ + linux,code = <0x0707006c>; /* KEY_DOWN */ + gpio-key,wakeup; + }; + }; +}; + +&gpmc { + ranges = <0 0 0x00000000 0x01000000>, + <1 0 0x08000000 0x01000000>; + + nand@0,0 { + linux,mtd-name= "micron,nand"; + reg = <0 0 0>; + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@80000 { + label = "U-Boot"; + reg = <0x80000 0x140000>; + }; + partition@1c0000 { + label = "Environment"; + reg = <0x1c0000 0x40000>; + }; + partition@200000 { + label = "Kernel"; + reg = <0x200000 0x1e00000>; + }; + partition@2000000 { + label = "Filesystem"; + reg = <0x2000000 0xe000000>; + }; + }; + + ethernet@gpmc { + interrupt-parent = <&gpio5>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + reg = <1 0 0xff>; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; +}; + +&mmc1 { + vmmc-supply = <&vmmc1>; + bus-width = <4>; +}; + +&omap3_pmx_core { + gpio_key_pins: pinmux_gpio_key_pins { + pinctrl-single,pins = < + 0xea (PIN_INPUT | MUX_MODE4) /* cam_d2.gpio_101 */ + 0xec (PIN_INPUT | MUX_MODE4) /* cam_d3.gpio_102 */ + 0xee (PIN_INPUT | MUX_MODE4) /* cam_d4.gpio_103 */ + 0xf0 (PIN_INPUT | MUX_MODE4) /* cam_d5.gpio_104 */ + 0xf2 (PIN_INPUT | MUX_MODE4) /* cam_d6.gpio_105 */ + 0xf4 (PIN_INPUT | MUX_MODE4) /* cam_d7.gpio_106 */ + 0xf6 (PIN_INPUT | MUX_MODE4) /* cam_d8.gpio_107 */ + 0xf8 (PIN_INPUT | MUX_MODE4) /* cam_d9.gpio_108 */ + 0xfa (PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ + >; + }; + + musb_pins: pinmux_musb_pins { + pinctrl-single,pins = < + 0x172 (PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ + 0x17a (PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ + 0x17c (PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ + 0x17e (PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ + 0x180 (PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ + 0x182 (PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ + 0x184 (PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ + 0x186 (PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ + 0x188 (PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ + 0x176 (PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ + 0x178 (PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ + 0x174 (PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ + >; + }; +}; + +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&musb_pins>; + interface-type = <0>; + usb-phy = <&usb2_phy>; + mode = <3>; + power = <50>; +}; + +&vaux1 { + /* Needed for ads7846 */ + regulator-name = "vcc"; +}; + +&vpll2 { + /* Needed for DSS */ + regulator-name = "vdds_dsi"; +}; diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi new file mode 100644 index 0000000..b9a2fed --- /dev/null +++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi @@ -0,0 +1,40 @@ +/* + * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 + */ + +&gpmc { + ranges = <4 0 0x2d000000 0x01000000>; + + smsc2: ethernet@4,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + reg = <4 0 0xff>; + bank-width = <2>; + gpmc,mux-add-data; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <186>; + gpmc,cs-wr-off-ns = <186>; + gpmc,adv-on-ns = <12>; + gpmc,adv-rd-off-ns = <48>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <54>; + gpmc,oe-off-ns = <168>; + gpmc,we-on-ns = <54>; + gpmc,we-off-ns = <168>; + gpmc,rd-cycle-ns = <186>; + gpmc,wr-cycle-ns = <186>; + gpmc,access-ns = <114>; + gpmc,page-burst-access-ns = <6>; + gpmc,bus-turnaround-ns = <12>; + gpmc,cycle2cycle-delay-ns = <18>; + gpmc,wr-data-mux-bus-ns = <90>; + gpmc,wr-access-ns = <186>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + vddvario-supply = <&vddvario>; + vdd33a-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + }; +}; diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts new file mode 100644 index 0000000..c119bd5 --- /dev/null +++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts @@ -0,0 +1,30 @@ +/* + * Suppport for CompuLab SBC-T3730 with CM-T3730 + */ + +#include "omap3-cm-t3730.dts" +#include "omap3-sb-t35.dtsi" + +/ { + model = "CompuLab SBC-T3730 with CM-T3730"; + compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; +}; + +&gpmc { + ranges = <5 0 0x2c000000 0x01000000>, + <4 0 0x2d000000 0x01000000>; +}; + +&smsc2 { + pinctrl-names = "default"; + pinctrl-0 = <&smsc2_pins>; +}; + +&omap3_pmx_core { + smsc2_pins: pinmux_smsc2_pins { + pinctrl-single,pins = < + 0x86 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ + 0xa2 (PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ + >; + }; +};
\ No newline at end of file diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts index 15eb9fe..6644f51 100644 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ b/arch/arm/boot/dts/omap3-zoom3.dts @@ -80,13 +80,8 @@ mmc3_pins: pinmux_mmc3_pins { pinctrl-single,pins = < - 0x168 (PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ - 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ - 0x5a8 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - 0x5b4 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ - 0x5b6 (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ - 0x5b8 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ - 0x5b2 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ + OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ + OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ >; }; @@ -125,6 +120,18 @@ }; }; +&omap3_pmx_core2 { + mmc3_2_pins: pinmux_mmc3_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ + OMAP3630_CORE2_IOPAD(0x25e6, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ + OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ + >; + }; +}; + &omap3_pmx_wkup { wlan_host_wkup: pinmux_wlan_host_wkup_pins { pinctrl-single,pins = < @@ -187,7 +194,7 @@ bus-width = <4>; cap-power-off-card; pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; + pinctrl-0 = <&mmc3_pins &mmc3_2_pins>; }; &uart1 { diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index daabf99..427395c 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -117,7 +117,7 @@ omap3_pmx_core: pinmux@48002030 { compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x48002030 0x05cc>; + reg = <0x48002030 0x0238>; #address-cells = <1>; #size-cells = <0>; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 5355d61..77d1246 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -25,4 +25,17 @@ clock-latency = <300000>; /* From legacy driver */ }; }; + + ocp { + omap3_pmx_core2: pinmux@480025d8 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x480025d8 0x24>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + }; }; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 380c22e..b7c7bd9 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -38,5 +38,16 @@ ti,hwmods = "uart4"; clock-frequency = <48000000>; }; + + omap3_pmx_core2: pinmux@480025a0 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x480025a0 0x5c>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; }; }; diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index aed83de..fcc5bb6 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -58,7 +58,7 @@ status = "okay"; ethphy: ethernet-phy { - device-type = "ethernet-phy"; + device_type = "ethernet-phy"; reg = <8>; }; }; diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index e06c37e..9f51538 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -42,6 +42,25 @@ interrupts = <6>, <7>, <8>, <9>; }; + spi@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + reg = <0x10600 0x28>; + status = "disabled"; + }; + + i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <5>; + clock-frequency = <100000>; + status = "disabled"; + }; + serial@12000 { compatible = "ns16550a"; reg = <0x12000 0x100>; @@ -60,15 +79,6 @@ status = "disabled"; }; - spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - reg = <0x10600 0x28>; - status = "disabled"; - }; - wdt@20300 { compatible = "marvell,orion-wdt"; reg = <0x20300 0x28>; @@ -82,30 +92,6 @@ status = "disabled"; }; - ehci@a0000 { - compatible = "marvell,orion-ehci"; - reg = <0xa0000 0x1000>; - interrupts = <12>; - status = "disabled"; - }; - - sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <29>; - status = "disabled"; - }; - - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <5>; - clock-frequency = <100000>; - status = "disabled"; - }; - xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 @@ -125,26 +111,6 @@ }; }; - crypto@90000 { - compatible = "marvell,orion-crypto"; - reg = <0x90000 0x10000>, - <0xf2200000 0x800>; - reg-names = "regs", "sram"; - interrupts = <28>; - status = "okay"; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <22>; - status = "disabled"; - - /* add phy nodes in board file */ - }; - eth: ethernet-controller@72000 { compatible = "marvell,orion-eth"; #address-cells = <1>; @@ -162,5 +128,39 @@ /* set phy-handle property in board file */ }; }; + + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <22>; + status = "disabled"; + + /* add phy nodes in board file */ + }; + + sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <29>; + status = "disabled"; + }; + + crypto@90000 { + compatible = "marvell,orion-crypto"; + reg = <0x90000 0x10000>, + <0xf2200000 0x800>; + reg-names = "regs", "sram"; + interrupts = <28>; + status = "okay"; + }; + + ehci@a0000 { + compatible = "marvell,orion-ehci"; + reg = <0xa0000 0x1000>; + interrupts = <12>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index daee5894..0e21993 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -29,6 +29,15 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + clocks = <&clks 12>; + operating-points = < + /* kHz uV */ + 200000 1025000 + 400000 1025000 + 664000 1050000 + 800000 1100000 + >; + clock-latency = <150000>; }; }; @@ -80,6 +89,7 @@ cphifbg@88030000 { compatible = "sirf,prima2-cphifbg"; reg = <0x88030000 0x1000>; + clocks = <&clks 42>; }; }; @@ -540,6 +550,18 @@ "usp0_uart_nostreamctrl"; }; }; + usp0_only_utfs_pins_a: usp0@2 { + usp0 { + sirf,pins = "usp0_only_utfs_grp"; + sirf,function = "usp0_only_utfs"; + }; + }; + usp0_only_urfs_pins_a: usp0@3 { + usp0 { + sirf,pins = "usp0_only_urfs_grp"; + sirf,function = "usp0_only_urfs"; + }; + }; usp1_pins_a: usp1@0 { usp1 { sirf,pins = "usp1grp"; @@ -648,6 +670,9 @@ compatible = "sirf,prima2-sdhc"; reg = <0x56000000 0x100000>; interrupts = <38>; + status = "disabled"; + bus-width = <8>; + clocks = <&clks 36>; }; sd1: sdhci@56100000 { @@ -655,6 +680,9 @@ compatible = "sirf,prima2-sdhc"; reg = <0x56100000 0x100000>; interrupts = <38>; + status = "disabled"; + bus-width = <4>; + clocks = <&clks 36>; }; sd2: sdhci@56200000 { @@ -662,6 +690,8 @@ compatible = "sirf,prima2-sdhc"; reg = <0x56200000 0x100000>; interrupts = <23>; + status = "disabled"; + clocks = <&clks 37>; }; sd3: sdhci@56300000 { @@ -669,6 +699,8 @@ compatible = "sirf,prima2-sdhc"; reg = <0x56300000 0x100000>; interrupts = <23>; + status = "disabled"; + clocks = <&clks 37>; }; sd4: sdhci@56400000 { @@ -676,6 +708,8 @@ compatible = "sirf,prima2-sdhc"; reg = <0x56400000 0x100000>; interrupts = <39>; + status = "disabled"; + clocks = <&clks 38>; }; sd5: sdhci@56500000 { @@ -683,6 +717,7 @@ compatible = "sirf,prima2-sdhc"; reg = <0x56500000 0x100000>; interrupts = <39>; + clocks = <&clks 38>; }; pci-copy@57900000 { @@ -716,6 +751,12 @@ interrupts = <52 53 54>; }; + minigpsrtc@2000 { + compatible = "sirf,prima2-minigpsrtc"; + reg = <0x2000 0x1000>; + interrupts = <54>; + }; + pwrc@3000 { compatible = "sirf,prima2-pwrc"; reg = <0x3000 0x1000>; diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index d7c5d72..a705469 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -10,5 +10,29 @@ marvell,intc-priority; marvell,intc-nr-irqs = <34>; }; + + pwm0: pwm@40b00000 { + compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; + reg = <0x40b00000 0x10>; + #pwm-cells = <1>; + }; + + pwm1: pwm@40b00010 { + compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; + reg = <0x40b00010 0x10>; + #pwm-cells = <1>; + }; + + pwm2: pwm@40c00000 { + compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; + reg = <0x40c00000 0x10>; + #pwm-cells = <1>; + }; + + pwm3: pwm@40c00010 { + compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; + reg = <0x40c00010 0x10>; + #pwm-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts new file mode 100644 index 0000000..13ac3e2 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -0,0 +1,6 @@ +#include "qcom-msm8974.dtsi" + +/ { + model = "Qualcomm APQ8074 Dragonboard"; + compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; +}; diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts index 386d428..1187185 100644 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts @@ -28,11 +28,11 @@ msmgpio: gpio@800000 { compatible = "qcom,msm-gpio"; - reg = <0x00800000 0x1000>; + reg = <0x00800000 0x4000>; gpio-controller; #gpio-cells = <2>; ngpio = <173>; - interrupts = <0 32 0x4>; + interrupts = <0 16 0x4>; interrupt-controller; #interrupt-cells = <2>; }; diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 93e9f7e..6ccbac7 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts @@ -31,7 +31,7 @@ gpio-controller; #gpio-cells = <2>; ngpio = <150>; - interrupts = <0 32 0x4>; + interrupts = <0 16 0x4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x800000 0x4000>; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi new file mode 100644 index 0000000..6ac9496 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -0,0 +1,97 @@ +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + model = "Qualcomm MSM8974"; + compatible = "qcom,msm8974"; + interrupt-parent = <&intc>; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0xf08>, + <1 3 0xf08>, + <1 4 0xf08>, + <1 1 0xf08>; + clock-frequency = <19200000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/r7s72100-genmai-reference.dts b/arch/arm/boot/dts/r7s72100-genmai-reference.dts new file mode 100644 index 0000000..da19c70 --- /dev/null +++ b/arch/arm/boot/dts/r7s72100-genmai-reference.dts @@ -0,0 +1,31 @@ +/* + * Device Tree Source for the Genmai board + * + * Copyright (C) 2013 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +/include/ "r7s72100.dtsi" + +/ { + model = "Genmai"; + compatible = "renesas,genmai-reference", "renesas,r7s72100"; + + chosen { + bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + }; + + memory { + device_type = "memory"; + reg = <0x08000000 0x08000000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index 1fb20f2..b1deaf7 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "r7s72100.dtsi" +#include "r7s72100.dtsi" / { model = "Genmai"; diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts index 9443e93..70b1fff 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "r8a73a4.dtsi" +#include "r8a73a4.dtsi" #include <dt-bindings/gpio/gpio.h> / { @@ -25,6 +25,11 @@ reg = <0 0x40000000 0 0x40000000>; }; + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; + vcc_mmc0: regulator@0 { compatible = "regulator-fixed"; regulator-name = "MMC0 Vcc"; @@ -88,22 +93,22 @@ pinctrl-0 = <&scifa0_pins>; pinctrl-names = "default"; - scifa0_pins: scifa0 { + scifa0_pins: serial0 { renesas,groups = "scifa0_data"; renesas,function = "scifa0"; }; - mmc0_pins: mmcif { + mmc0_pins: mmc { renesas,groups = "mmc0_data8", "mmc0_ctrl"; renesas,function = "mmc0"; }; - sdhi0_pins: sdhi0 { + sdhi0_pins: sd0 { renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; renesas,function = "sdhi0"; }; - sdhi1_pins: sdhi1 { + sdhi1_pins: sd1 { renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; renesas,function = "sdhi1"; }; diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 91436b5..ce085fa 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -9,7 +9,8 @@ */ /dts-v1/; -/include/ "r8a73a4.dtsi" +#include "r8a73a4.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> / { model = "APE6EVM"; @@ -24,6 +25,11 @@ reg = <0 0x40000000 0 0x40000000>; }; + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; + ape6evm_fixed_3v3: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "3V3"; @@ -40,7 +46,7 @@ compatible = "smsc,lan9118", "smsc,lan9115"; reg = <0x08000000 0x1000>; interrupt-parent = <&irqc1>; - interrupts = <8 0x4>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; phy-mode = "mii"; reg-io-width = <4>; smsc,irq-active-high; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 287e047..62d0211 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -9,6 +9,9 @@ * kind, whether express or implied. */ +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + / { compatible = "renesas,r8a73a4"; interrupt-parent = <&gic>; @@ -36,15 +39,15 @@ <0 0xf1002000 0 0x1000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; timer { compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; irqc0: interrupt-controller@e61c0000 { @@ -53,14 +56,38 @@ interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupt-parent = <&gic>; - interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>, - <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>, - <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>, - <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>, - <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>, - <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>, - <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>, - <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 4 IRQ_TYPE_LEVEL_HIGH>, + <0 5 IRQ_TYPE_LEVEL_HIGH>, + <0 6 IRQ_TYPE_LEVEL_HIGH>, + <0 7 IRQ_TYPE_LEVEL_HIGH>, + <0 8 IRQ_TYPE_LEVEL_HIGH>, + <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>, + <0 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>, + <0 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 IRQ_TYPE_LEVEL_HIGH>, + <0 21 IRQ_TYPE_LEVEL_HIGH>, + <0 22 IRQ_TYPE_LEVEL_HIGH>, + <0 23 IRQ_TYPE_LEVEL_HIGH>, + <0 24 IRQ_TYPE_LEVEL_HIGH>, + <0 25 IRQ_TYPE_LEVEL_HIGH>, + <0 26 IRQ_TYPE_LEVEL_HIGH>, + <0 27 IRQ_TYPE_LEVEL_HIGH>, + <0 28 IRQ_TYPE_LEVEL_HIGH>, + <0 29 IRQ_TYPE_LEVEL_HIGH>, + <0 30 IRQ_TYPE_LEVEL_HIGH>, + <0 31 IRQ_TYPE_LEVEL_HIGH>; }; irqc1: interrupt-controller@e61c0200 { @@ -69,13 +96,32 @@ interrupt-controller; reg = <0 0xe61c0200 0 0x200>; interrupt-parent = <&gic>; - interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>, - <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>, - <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>, - <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>, - <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>, - <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>, - <0 56 4>, <0 57 4>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, + <0 33 IRQ_TYPE_LEVEL_HIGH>, + <0 34 IRQ_TYPE_LEVEL_HIGH>, + <0 35 IRQ_TYPE_LEVEL_HIGH>, + <0 36 IRQ_TYPE_LEVEL_HIGH>, + <0 37 IRQ_TYPE_LEVEL_HIGH>, + <0 38 IRQ_TYPE_LEVEL_HIGH>, + <0 39 IRQ_TYPE_LEVEL_HIGH>, + <0 40 IRQ_TYPE_LEVEL_HIGH>, + <0 41 IRQ_TYPE_LEVEL_HIGH>, + <0 42 IRQ_TYPE_LEVEL_HIGH>, + <0 43 IRQ_TYPE_LEVEL_HIGH>, + <0 44 IRQ_TYPE_LEVEL_HIGH>, + <0 45 IRQ_TYPE_LEVEL_HIGH>, + <0 46 IRQ_TYPE_LEVEL_HIGH>, + <0 47 IRQ_TYPE_LEVEL_HIGH>, + <0 48 IRQ_TYPE_LEVEL_HIGH>, + <0 49 IRQ_TYPE_LEVEL_HIGH>, + <0 50 IRQ_TYPE_LEVEL_HIGH>, + <0 51 IRQ_TYPE_LEVEL_HIGH>, + <0 52 IRQ_TYPE_LEVEL_HIGH>, + <0 53 IRQ_TYPE_LEVEL_HIGH>, + <0 54 IRQ_TYPE_LEVEL_HIGH>, + <0 55 IRQ_TYPE_LEVEL_HIGH>, + <0 56 IRQ_TYPE_LEVEL_HIGH>, + <0 57 IRQ_TYPE_LEVEL_HIGH>; }; dmac: dma-multiplexer@0 { @@ -91,27 +137,27 @@ compatible = "renesas,shdma-r8a73a4"; reg = <0 0xe6700020 0 0x89e0>; interrupt-parent = <&gic>; - interrupts = <0 220 4 - 0 200 4 - 0 201 4 - 0 202 4 - 0 203 4 - 0 204 4 - 0 205 4 - 0 206 4 - 0 207 4 - 0 208 4 - 0 209 4 - 0 210 4 - 0 211 4 - 0 212 4 - 0 213 4 - 0 214 4 - 0 215 4 - 0 216 4 - 0 217 4 - 0 218 4 - 0 219 4>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH + 0 200 IRQ_TYPE_LEVEL_HIGH + 0 201 IRQ_TYPE_LEVEL_HIGH + 0 202 IRQ_TYPE_LEVEL_HIGH + 0 203 IRQ_TYPE_LEVEL_HIGH + 0 204 IRQ_TYPE_LEVEL_HIGH + 0 205 IRQ_TYPE_LEVEL_HIGH + 0 206 IRQ_TYPE_LEVEL_HIGH + 0 207 IRQ_TYPE_LEVEL_HIGH + 0 208 IRQ_TYPE_LEVEL_HIGH + 0 209 IRQ_TYPE_LEVEL_HIGH + 0 210 IRQ_TYPE_LEVEL_HIGH + 0 211 IRQ_TYPE_LEVEL_HIGH + 0 212 IRQ_TYPE_LEVEL_HIGH + 0 213 IRQ_TYPE_LEVEL_HIGH + 0 214 IRQ_TYPE_LEVEL_HIGH + 0 215 IRQ_TYPE_LEVEL_HIGH + 0 216 IRQ_TYPE_LEVEL_HIGH + 0 217 IRQ_TYPE_LEVEL_HIGH + 0 218 IRQ_TYPE_LEVEL_HIGH + 0 219 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", @@ -126,7 +172,7 @@ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; interrupt-parent = <&gic>; - interrupts = <0 69 4>; + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; }; i2c0: i2c@e6500000 { @@ -135,7 +181,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 174 0x4>; + interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -145,7 +191,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 175 0x4>; + interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -155,7 +201,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6520000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 176 0x4>; + interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -165,7 +211,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6530000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 177 0x4>; + interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -175,7 +221,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6540000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 178 0x4>; + interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -185,7 +231,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 179 0x4>; + interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -195,7 +241,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6550000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 184 0x4>; + interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -205,7 +251,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6560000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 185 0x4>; + interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -215,24 +261,24 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6570000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 173 0x4>; + interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - mmcif0: mmcif@ee200000 { + mmcif0: mmc@ee200000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupt-parent = <&gic>; - interrupts = <0 169 0x4>; + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; status = "disabled"; }; - mmcif1: mmcif@ee220000 { + mmcif1: mmc@ee220000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupt-parent = <&gic>; - interrupts = <0 170 0x4>; + interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; status = "disabled"; }; @@ -242,31 +288,47 @@ reg = <0 0xe6050000 0 0x9000>; gpio-controller; #gpio-cells = <2>; + interrupts-extended = + <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, + <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, + <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, + <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, + <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, + <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, + <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, + <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, + <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, + <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, + <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, + <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, + <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, + <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, + <&irqc1 24 0>, <&irqc1 25 0>; }; - sdhi0: sdhi@ee100000 { + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee100000 0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 165 4>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; }; - sdhi1: sdhi@ee120000 { + sdhi1: sd@ee120000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee120000 0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 166 4>; + interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; }; - sdhi2: sdhi@ee140000 { + sdhi2: sd@ee140000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee140000 0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 167 4>; + interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; }; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 1c56c5e..95a849b 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -9,8 +9,9 @@ */ /dts-v1/; -/include/ "r8a7740.dtsi" +#include "r8a7740.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pwm/pwm.h> / { @@ -62,6 +63,44 @@ enable-active-high; }; + reg_5p0v: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-5.0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power-key { + gpios = <&pfc 99 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "SW3"; + gpio-key,wakeup; + }; + + back-key { + gpios = <&pfc 100 GPIO_ACTIVE_LOW>; + linux,code = <158>; + label = "SW4"; + }; + + menu-key { + gpios = <&pfc 97 GPIO_ACTIVE_LOW>; + linux,code = <139>; + label = "SW5"; + }; + + home-key { + gpios = <&pfc 98 GPIO_ACTIVE_LOW>; + linux,code = <102>; + label = "SW6"; + }; + }; + leds { compatible = "gpio-leds"; led1 { @@ -85,32 +124,58 @@ default-brightness-level = <9>; pinctrl-0 = <&backlight_pins>; pinctrl-names = "default"; + power-supply = <®_5p0v>; + enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&sh_fsi2 0>; + bitclock-inversion; + }; + + simple-audio-card,codec { + sound-dai = <&wm8978>; + bitclock-master; + frame-master; + system-clock-frequency = <12288000>; + }; }; }; &i2c0 { status = "okay"; - touchscreen: st1232@55 { + touchscreen@55 { compatible = "sitronix,st1232"; reg = <0x55>; interrupt-parent = <&irqpin1>; - interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */ + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&st1232_pins>; pinctrl-names = "default"; gpios = <&pfc 166 GPIO_ACTIVE_LOW>; }; + + wm8978: wm8978@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8978"; + reg = <0x1a>; + }; }; &pfc { pinctrl-0 = <&scifa1_pins>; pinctrl-names = "default"; - scifa1_pins: scifa1 { + scifa1_pins: serial1 { renesas,groups = "scifa1_data"; renesas,function = "scifa1"; }; - st1232_pins: st1232 { + st1232_pins: touchscreen { renesas,groups = "intc_irq10"; renesas,function = "intc"; }; @@ -125,10 +190,16 @@ renesas,function = "mmc0"; }; - sdhi0_pins: sdhi0 { + sdhi0_pins: sd0 { renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; renesas,function = "sdhi0"; }; + + fsia_pins: sounda { + renesas,groups = "fsia_sclk_in", "fsia_mclk_out", + "fsia_data_in_1", "fsia_data_out_0"; + renesas,function = "fsia"; + }; }; &tpu { @@ -155,3 +226,10 @@ cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&sh_fsi2 { + pinctrl-0 = <&fsia_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index 426cd9c..a06a11e 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "r8a7740.dtsi" +#include "r8a7740.dtsi" / { model = "armadillo 800 eva"; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index ae1e230..8280884 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -10,6 +10,8 @@ /include/ "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + / { compatible = "renesas,r8a7740"; @@ -34,12 +36,12 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 83 4>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; }; /* irqpin0: IRQ0 - IRQ7 */ irqpin0: irqpin@e6900000 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe6900000 4>, @@ -48,19 +50,19 @@ <0xe6900040 1>, <0xe6900060 1>; interrupt-parent = <&gic>; - interrupts = <0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH>; }; /* irqpin1: IRQ8 - IRQ15 */ irqpin1: irqpin@e6900004 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe6900004 4>, @@ -69,19 +71,19 @@ <0xe6900044 1>, <0xe6900064 1>; interrupt-parent = <&gic>; - interrupts = <0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH>; }; /* irqpin2: IRQ16 - IRQ23 */ irqpin2: irqpin@e6900008 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe6900008 4>, @@ -90,19 +92,19 @@ <0xe6900048 1>, <0xe6900068 1>; interrupt-parent = <&gic>; - interrupts = <0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH>; }; /* irqpin3: IRQ24 - IRQ31 */ irqpin3: irqpin@e690000c { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe690000c 4>, @@ -111,14 +113,14 @@ <0xe690004c 1>, <0xe690006c 1>; interrupt-parent = <&gic>; - interrupts = <0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH>; }; i2c0: i2c@fff20000 { @@ -127,10 +129,10 @@ compatible = "renesas,rmobile-iic"; reg = <0xfff20000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 201 0x4 - 0 202 0x4 - 0 203 0x4 - 0 204 0x4>; + interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH + 0 202 IRQ_TYPE_LEVEL_HIGH + 0 203 IRQ_TYPE_LEVEL_HIGH + 0 204 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -140,10 +142,10 @@ compatible = "renesas,rmobile-iic"; reg = <0xe6c20000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 70 0x4 - 0 71 0x4 - 0 72 0x4 - 0 73 0x4>; + interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH + 0 71 IRQ_TYPE_LEVEL_HIGH + 0 72 IRQ_TYPE_LEVEL_HIGH + 0 73 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -153,6 +155,15 @@ <0xe605800c 0x20>; gpio-controller; #gpio-cells = <2>; + interrupts-extended = + <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, + <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, + <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, + <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, + <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, + <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, + <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, + <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; }; tpu: pwm@e6600000 { @@ -162,36 +173,57 @@ #pwm-cells = <3>; }; - mmcif0: mmcif@e6bd0000 { + mmcif0: mmc@e6bd0000 { compatible = "renesas,sh-mmcif"; reg = <0xe6bd0000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 56 4 - 0 57 4>; + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH + 0 57 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - sdhi0: sdhi@e6850000 { + sdhi0: sd@e6850000 { compatible = "renesas,sdhi-r8a7740"; reg = <0xe6850000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 117 4 - 0 118 4 - 0 119 4>; + interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH + 0 118 IRQ_TYPE_LEVEL_HIGH + 0 119 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; }; - sdhi1: sdhi@e6860000 { + sdhi1: sd@e6860000 { compatible = "renesas,sdhi-r8a7740"; reg = <0xe6860000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 121 4 - 0 122 4 - 0 123 4>; + interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH + 0 122 IRQ_TYPE_LEVEL_HIGH + 0 123 IRQ_TYPE_LEVEL_HIGH>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi2: sd@e6870000 { + compatible = "renesas,sdhi-r8a7740"; + reg = <0xe6870000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH + 0 126 IRQ_TYPE_LEVEL_HIGH + 0 127 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; }; + + sh_fsi2: sound@fe1f0000 { + #sound-dai-cells = <1>; + compatible = "renesas,sh_fsi2"; + reg = <0xfe1f0000 0x400>; + interrupt-parent = <&gic>; + interrupts = <0 9 0x4>; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 969e386..bb62c7a 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -15,7 +15,8 @@ */ /dts-v1/; -/include/ "r8a7778.dtsi" +#include "r8a7778.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> / { model = "bockw"; @@ -45,13 +46,65 @@ phy-mode = "mii"; interrupt-parent = <&irqpin>; - interrupts = <0 0>; /* IRQ0: hwirq 0 on irqpin */ + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; reg-io-width = <4>; vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; }; + +}; + +&mmcif { + pinctrl-0 = <&mmc_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <8>; + broken-cd; + status = "okay"; }; &irqpin { status = "okay"; }; + +&pfc { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + scif0_pins: serial0 { + renesas,groups = "scif0_data_a", "scif0_ctrl"; + renesas,function = "scif0"; + }; + + mmc_pins: mmc { + renesas,groups = "mmc_data8", "mmc_ctrl"; + renesas,function = "mmc"; + }; + + sdhi0_pins: sd0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl", + "sdhi0_cd", "sdhi0_wp"; + renesas,function = "sdhi0"; + }; + + hspi0_pins: hspi0 { + renesas,groups = "hspi0_a"; + renesas,function = "hspi0"; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <4>; + status = "okay"; +}; + +&hspi0 { + pinctrl-0 = <&hspi0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts index 12bbebc..46a884d 100644 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -15,7 +15,7 @@ */ /dts-v1/; -/include/ "r8a7778.dtsi" +#include "r8a7778.dtsi" / { model = "bockw"; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index a6308a3..ddb3bd7 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -16,6 +16,8 @@ /include/ "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + / { compatible = "renesas,r8a7778"; @@ -25,6 +27,12 @@ }; }; + aliases { + spi0 = &hspi0; + spi1 = &hspi1; + spi2 = &hspi2; + }; + gic: interrupt-controller@fe438000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -35,7 +43,7 @@ /* irqpin: IRQ0 - IRQ3 */ irqpin: irqpin@fe78001c { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; status = "disabled"; /* default off */ @@ -45,10 +53,10 @@ <0xfe780044 4>, <0xfe780064 4>; interrupt-parent = <&gic>; - interrupts = <0 27 0x4 - 0 28 0x4 - 0 29 0x4 - 0 30 0x4>; + interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH + 0 28 IRQ_TYPE_LEVEL_HIGH + 0 29 IRQ_TYPE_LEVEL_HIGH + 0 30 IRQ_TYPE_LEVEL_HIGH>; sense-bitfield-width = <2>; }; @@ -56,7 +64,7 @@ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc40000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 103 0x4>; + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 0 32>; @@ -68,7 +76,7 @@ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc41000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 103 0x4>; + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 32 32>; @@ -80,7 +88,7 @@ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc42000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 103 0x4>; + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 64 32>; @@ -92,7 +100,7 @@ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc43000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 103 0x4>; + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 96 32>; @@ -104,7 +112,7 @@ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc44000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 103 0x4>; + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 128 27>; @@ -114,6 +122,148 @@ pfc: pfc@fffc0000 { compatible = "renesas,pfc-r8a7778"; - reg = <0xfffc000 0x118>; + reg = <0xfffc0000 0x118>; + }; + + i2c0: i2c@ffc70000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc70000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c1: i2c@ffc71000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc71000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c2: i2c@ffc72000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc72000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c3: i2c@ffc73000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc73000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + mmcif: mmc@ffe4e000 { + compatible = "renesas,sh-mmcif"; + reg = <0xffe4e000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sdhi0: sd@ffe4c000 { + compatible = "renesas,sdhi-r8a7778"; + reg = <0xffe4c000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: sd@ffe4d000 { + compatible = "renesas,sdhi-r8a7778"; + reg = <0xffe4d000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi2: sd@ffe4f000 { + compatible = "renesas,sdhi-r8a7778"; + reg = <0xffe4f000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + i2c0: i2c@ffc70000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc70000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c1: i2c@ffc71000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc71000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c2: i2c@ffc72000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc72000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c3: i2c@ffc73000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc73000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + hspi0: spi@fffc7000 { + compatible = "renesas,hspi"; + reg = <0xfffc7000 0x18>; + interrupt-controller = <&gic>; + interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + hspi1: spi@fffc8000 { + compatible = "renesas,hspi"; + reg = <0xfffc8000 0x18>; + interrupt-controller = <&gic>; + interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + hspi2: spi@fffc6000 { + compatible = "renesas,hspi"; + reg = <0xfffc6000 0x18>; + interrupt-controller = <&gic>; + interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index ab4110a..76f5eef 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -10,8 +10,9 @@ */ /dts-v1/; -/include/ "r8a7779.dtsi" +#include "r8a7779.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> / { model = "marzen"; @@ -43,7 +44,7 @@ phy-mode = "mii"; interrupt-parent = <&irqpin0>; - interrupts = <1 0>; /* IRQ1: hwirq 1 on irqpin0 */ + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; reg-io-width = <4>; vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; @@ -68,7 +69,7 @@ }; &pfc { - pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>; + pinctrl-0 = <&scif2_pins &scif4_pins>; pinctrl-names = "default"; lan0_pins: lan0 { @@ -82,19 +83,38 @@ }; }; - scif2_pins: scif2 { + scif2_pins: serial2 { renesas,groups = "scif2_data_c"; renesas,function = "scif2"; }; - scif4_pins: scif4 { + scif4_pins: serial4 { renesas,groups = "scif4_data"; renesas,function = "scif4"; }; - sdhi0_pins: sdhi0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", - "sdhi0_wp"; + sdhi0_pins: sd0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; renesas,function = "sdhi0"; }; + + hspi0_pins: hspi0 { + renesas,groups = "hspi0"; + renesas,function = "hspi0"; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <4>; + status = "okay"; +}; + +&hspi0 { + pinctrl-0 = <&hspi0_pins>; + pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index f3f7f79..a7af2c2 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "r8a7779.dtsi" +#include "r8a7779.dtsi" / { model = "marzen"; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 19faeac..d0561d4 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -11,6 +11,8 @@ /include/ "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + / { compatible = "renesas,r8a7779"; @@ -40,6 +42,12 @@ }; }; + aliases { + spi0 = &hspi0; + spi1 = &hspi1; + spi2 = &hspi2; + }; + gic: interrupt-controller@f0001000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -52,7 +60,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc40000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 141 0x4>; + interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 0 32>; @@ -64,7 +72,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc41000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 142 0x4>; + interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 32 32>; @@ -76,7 +84,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc42000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 143 0x4>; + interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 64 32>; @@ -88,7 +96,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc43000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 144 0x4>; + interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 96 32>; @@ -100,7 +108,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc44000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 145 0x4>; + interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 128 32>; @@ -112,7 +120,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc45000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 146 0x4>; + interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 160 32>; @@ -124,7 +132,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc46000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 147 0x4>; + interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 192 9>; @@ -133,7 +141,7 @@ }; irqpin0: irqpin@fe780010 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; #interrupt-cells = <2>; status = "disabled"; interrupt-controller; @@ -143,50 +151,50 @@ <0xfe780044 4>, <0xfe780064 4>; interrupt-parent = <&gic>; - interrupts = <0 27 0x4 - 0 28 0x4 - 0 29 0x4 - 0 30 0x4>; + interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH + 0 28 IRQ_TYPE_LEVEL_HIGH + 0 29 IRQ_TYPE_LEVEL_HIGH + 0 30 IRQ_TYPE_LEVEL_HIGH>; sense-bitfield-width = <2>; }; i2c0: i2c@ffc70000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,i2c-r8a7779"; reg = <0xffc70000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 79 0x4>; + interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; i2c1: i2c@ffc71000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,i2c-r8a7779"; reg = <0xffc71000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 82 0x4>; + interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; i2c2: i2c@ffc72000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,i2c-r8a7779"; reg = <0xffc72000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 80 0x4>; + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; i2c3: i2c@ffc73000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,i2c-r8a7779"; reg = <0xffc73000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 81 0x4>; + interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -204,6 +212,70 @@ compatible = "renesas,rcar-sata"; reg = <0xfc600000 0x2000>; interrupt-parent = <&gic>; - interrupts = <0 100 0x4>; + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + }; + + sdhi0: sd@ffe4c000 { + compatible = "renesas,sdhi-r8a7779"; + reg = <0xffe4c000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: sd@ffe4d000 { + compatible = "renesas,sdhi-r8a7779"; + reg = <0xffe4d000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi2: sd@ffe4e000 { + compatible = "renesas,sdhi-r8a7779"; + reg = <0xffe4e000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi3: sd@ffe4f000 { + compatible = "renesas,sdhi-r8a7779"; + reg = <0xffe4f000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + hspi0: spi@fffc7000 { + compatible = "renesas,hspi"; + reg = <0xfffc7000 0x18>; + interrupt-controller = <&gic>; + interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + hspi1: spi@fffc8000 { + compatible = "renesas,hspi"; + reg = <0xfffc8000 0x18>; + interrupt-controller = <&gic>; + interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + hspi2: spi@fffc6000 { + compatible = "renesas,hspi"; + reg = <0xfffc6000 0x18>; + interrupt-controller = <&gic>; + interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts deleted file mode 100644 index c462ef1..0000000 --- a/arch/arm/boot/dts/r8a7790-lager-reference.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Device Tree Source for the Lager board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -/include/ "r8a7790.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Lager"; - compatible = "renesas,lager-reference", "renesas,r8a7790"; - - chosen { - bootargs = "console=ttySC6,115200 ignore_loglevel rw"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - }; - led7 { - gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; - }; - led8 { - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 203bd08..57569cb 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -9,7 +9,8 @@ */ /dts-v1/; -/include/ "r8a7790.dtsi" +#include "r8a7790.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Lager"; @@ -24,8 +25,69 @@ reg = <0 0x40000000 0 0x80000000>; }; + memory@180000000 { + device_type = "memory"; + reg = <1 0x80000000 0 0x80000000>; + }; + lbsc { #address-cells = <1>; #size-cells = <1>; }; + + leds { + compatible = "gpio-leds"; + led6 { + gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + }; + led7 { + gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + }; + led8 { + gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + }; + }; + + fixedregulator3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + pinctrl-0 = <&scif0_pins &scif1_pins>; + pinctrl-names = "default"; + + scif0_pins: serial0 { + renesas,groups = "scif0_data"; + renesas,function = "scif0"; + }; + + scif1_pins: serial1 { + renesas,groups = "scif1_data"; + renesas,function = "scif1"; + }; + + mmc1_pins: mmc1 { + renesas,groups = "mmc1_data8", "mmc1_ctrl"; + renesas,function = "mmc1"; + }; +}; + +&mmcif1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <8>; + non-removable; + status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 9987dd0e..f48487c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -8,6 +8,10 @@ * kind, whether express or implied. */ +#include <dt-bindings/clock/r8a7790-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + / { compatible = "renesas,r8a7790"; interrupt-parent = <&gic>; @@ -84,14 +88,14 @@ <0 0xf1002000 0 0x1000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6050000 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 4 0x4>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 0 32>; @@ -103,7 +107,7 @@ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6051000 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 5 0x4>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 32 32>; @@ -115,7 +119,7 @@ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6052000 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 6 0x4>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 64 32>; @@ -127,7 +131,7 @@ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6053000 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 7 0x4>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 96 32>; @@ -139,7 +143,7 @@ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6054000 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 8 0x4>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 128 32>; @@ -151,7 +155,7 @@ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6055000 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 9 0x4>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 160 32>; @@ -159,21 +163,31 @@ interrupt-controller; }; + thermal@e61f0000 { + compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; + interrupt-parent = <&gic>; + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + }; + timer { compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc"; + compatible = "renesas,irqc-r8a7790", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupt-parent = <&gic>; - interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>; }; i2c0: i2c@e6508000 { @@ -182,7 +196,8 @@ compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6508000 0 0x40>; interrupt-parent = <&gic>; - interrupts = <0 287 0x4>; + interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_I2C0>; status = "disabled"; }; @@ -192,7 +207,8 @@ compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6518000 0 0x40>; interrupt-parent = <&gic>; - interrupts = <0 288 0x4>; + interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_I2C1>; status = "disabled"; }; @@ -202,7 +218,8 @@ compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6530000 0 0x40>; interrupt-parent = <&gic>; - interrupts = <0 286 0x4>; + interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_I2C2>; status = "disabled"; }; @@ -212,24 +229,27 @@ compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6540000 0 0x40>; interrupt-parent = <&gic>; - interrupts = <0 290 0x4>; + interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_I2C3>; status = "disabled"; }; mmcif0: mmcif@ee200000 { - compatible = "renesas,sh-mmcif"; + compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupt-parent = <&gic>; - interrupts = <0 169 0x4>; + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; reg-io-width = <4>; status = "disabled"; }; - mmcif1: mmcif@ee220000 { - compatible = "renesas,sh-mmcif"; + mmcif1: mmc@ee220000 { + compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupt-parent = <&gic>; - interrupts = <0 170 0x4>; + interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; reg-io-width = <4>; status = "disabled"; }; @@ -239,39 +259,372 @@ reg = <0 0xe6060000 0 0x250>; }; - sdhi0: sdhi@ee100000 { + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee100000 0 0x200>; interrupt-parent = <&gic>; - interrupts = <0 165 4>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; cap-sd-highspeed; status = "disabled"; }; - sdhi1: sdhi@ee120000 { + sdhi1: sd@ee120000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee120000 0 0x200>; interrupt-parent = <&gic>; - interrupts = <0 166 4>; + interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; cap-sd-highspeed; status = "disabled"; }; - sdhi2: sdhi@ee140000 { + sdhi2: sd@ee140000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee140000 0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 167 4>; + interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; cap-sd-highspeed; status = "disabled"; }; - sdhi3: sdhi@ee160000 { + sdhi3: sd@ee160000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee160000 0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 168 4>; + interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; cap-sd-highspeed; status = "disabled"; }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* External root clock */ + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7790-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "sd1", + "z"; + }; + + /* Variable factor clocks */ + sd2_clk: sd2_clk@e6150078 { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd2"; + }; + sd3_clk: sd3_clk@e615007c { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615007c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd3"; + }; + mmc0_clk: mmc0_clk@e6150240 { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150240 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc0"; + }; + mmc1_clk: mmc1_clk@e6150244 { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150244 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc1"; + }; + ssp_clk: ssp_clk@e6150248 { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150248 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "ssp"; + }; + ssprs_clk: ssprs_clk@e615024c { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615024c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "ssprs"; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + z2_clk: z2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "z2"; + }; + zg_clk: zg_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zg"; + }; + zx_clk: zx_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zx"; + }; + zs_clk: zs_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zs"; + }; + hp_clk: hp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "hp"; + }; + i_clk: i_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "i"; + }; + b_clk: b_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "b"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + cl_clk: cl_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + clock-output-names = "cl"; + }; + m2_clk: m2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "m2"; + }; + imp_clk: imp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "imp"; + }; + rclk_clk: rclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(48 * 1024)>; + clock-mult = <1>; + clock-output-names = "rclk"; + }; + oscclk_clk: oscclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(12 * 1024)>; + clock-mult = <1>; + clock-output-names = "oscclk"; + }; + zb3_clk: zb3_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "zb3"; + }; + zb3d2_clk: zb3d2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "zb3d2"; + }; + ddr_clk: ddr_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "ddr"; + }; + mp_clk: mp_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + clock-output-names = "mp"; + }; + cp_clk: cp_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "cp"; + }; + + /* Gate clocks */ + mstp0_clks: mstp0_clks@e6150130 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; + clocks = <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = <R8A7790_CLK_MSIOF0>; + clock-output-names = "msiof0"; + }; + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, + <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, + <&zs_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 + R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 + R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY + >; + clock-output-names = + "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", + "vsp1-du0", "vsp1-rt", "vsp1-sy"; + }; + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 + R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 + R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 + >; + clock-output-names = + "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", + "scifb1", "msiof1", "msiof3", "scifb2"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, + <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, + <&mmc0_clk>, <&rclk_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 + R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 + R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1 + >; + clock-output-names = + "tpu0", "mmcif1", "sdhi3", "sdhi2", + "sdhi1", "sdhi0", "mmcif0", "cmt1"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&extal_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; + clock-output-names = "thermal", "pwm"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, + <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, + <&zx_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 + R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 + R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 + R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 + >; + clock-output-names = + "ehci", "hsusb", "hscif1", "hscif0", "scif1", + "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; + }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = <R8A7790_CLK_ETHER>; + clock-output-names = "ether"; + }; + mstp9_clks: mstp9_clks@e6150994 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; + clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD + R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 + R8A7790_CLK_I2C0 + >; + clock-output-names = + "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; + }; + }; }; diff --git a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts new file mode 100644 index 0000000..588ca17 --- /dev/null +++ b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts @@ -0,0 +1,115 @@ +/* + * Device Tree Source for the Koelsch board + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7791.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Koelsch"; + compatible = "renesas,koelsch-reference", "renesas,r8a7791"; + + chosen { + bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-a { + gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + linux,code = <30>; + label = "SW30"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-b { + gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; + linux,code = <48>; + label = "SW31"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-c { + gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; + linux,code = <46>; + label = "SW32"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-d { + gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; + linux,code = <32>; + label = "SW33"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-e { + gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; + linux,code = <18>; + label = "SW34"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-f { + gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; + linux,code = <33>; + label = "SW35"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-g { + gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + linux,code = <34>; + label = "SW36"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + }; + + leds { + compatible = "gpio-leds"; + led6 { + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + }; + led7 { + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + }; + led8 { + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pfc { + pinctrl-0 = <&scif0_pins &scif1_pins>; + pinctrl-names = "default"; + + scif0_pins: serial0 { + renesas,groups = "scif0_data_d"; + renesas,function = "scif0"; + }; + + scif1_pins: serial1 { + renesas,groups = "scif1_data_d"; + renesas,function = "scif1"; + }; +}; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 1ce5250..fd556c3 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -10,7 +10,8 @@ */ /dts-v1/; -/include/ "r8a7791.dtsi" +#include "r8a7791.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Koelsch"; @@ -29,4 +30,36 @@ #address-cells = <1>; #size-cells = <1>; }; + + leds { + compatible = "gpio-leds"; + led6 { + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + }; + led7 { + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + }; + led8 { + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + pinctrl-0 = <&scif0_pins &scif1_pins>; + pinctrl-names = "default"; + + scif0_pins: serial0 { + renesas,groups = "scif0_data_d"; + renesas,function = "scif0"; + }; + + scif1_pins: serial1 { + renesas,groups = "scif1_data_d"; + renesas,function = "scif1"; + }; }; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index fea5cfe..19c6550 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -9,6 +9,10 @@ * kind, whether express or implied. */ +#include <dt-bindings/clock/r8a7791-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + / { compatible = "renesas,r8a7791"; interrupt-parent = <&gic>; @@ -43,32 +47,463 @@ <0 0xf1002000 0 0x1000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xe6055800 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 26>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + thermal@e61f0000 { + compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; + interrupt-parent = <&gic>; + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; }; timer { compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc"; + compatible = "renesas,irqc-r8a7791", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupt-parent = <&gic>; - interrupts = <0 0 4>, - <0 1 4>, - <0 2 4>, - <0 3 4>, - <0 12 4>, - <0 13 4>, - <0 14 4>, - <0 15 4>, - <0 16 4>, - <0 17 4>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>, + <0 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 IRQ_TYPE_LEVEL_HIGH>; + }; + + pfc: pfc@e6060000 { + compatible = "renesas,pfc-r8a7791"; + reg = <0 0xe6060000 0 0x250>; + #gpio-range-cells = <3>; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* External root clock */ + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7791-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "z"; + }; + + /* Variable factor clocks */ + sd1_clk: sd2_clk@e6150078 { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd1"; + }; + sd2_clk: sd3_clk@e615007c { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615007c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd2"; + }; + mmc0_clk: mmc0_clk@e6150240 { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150240 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc0"; + }; + ssp_clk: ssp_clk@e6150248 { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150248 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "ssp"; + }; + ssprs_clk: ssprs_clk@e615024c { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615024c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "ssprs"; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + zg_clk: zg_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zg"; + }; + zx_clk: zx_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zx"; + }; + zs_clk: zs_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zs"; + }; + hp_clk: hp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "hp"; + }; + i_clk: i_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "i"; + }; + b_clk: b_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "b"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + cl_clk: cl_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + clock-output-names = "cl"; + }; + m2_clk: m2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "m2"; + }; + imp_clk: imp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "imp"; + }; + rclk_clk: rclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(48 * 1024)>; + clock-mult = <1>; + clock-output-names = "rclk"; + }; + oscclk_clk: oscclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(12 * 1024)>; + clock-mult = <1>; + clock-output-names = "oscclk"; + }; + zb3_clk: zb3_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "zb3"; + }; + zb3d2_clk: zb3d2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "zb3d2"; + }; + ddr_clk: ddr_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "ddr"; + }; + mp_clk: mp_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + clock-output-names = "mp"; + }; + cp_clk: cp_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "cp"; + }; + + /* Gate clocks */ + mstp0_clks: mstp0_clks@e6150130 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; + clocks = <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = <R8A7791_CLK_MSIOF0>; + clock-output-names = "msiof0"; + }; + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, + <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 + R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 + R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY + >; + clock-output-names = + "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", + "vsp1-du0", "vsp1-sy"; + }; + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>, <&mp_clk>, <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 + R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 + R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 + >; + clock-output-names = + "scifa2", "scifa1", "scifa0", "misof2", "scifb0", + "scifb1", "msiof1", "scifb2"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, + <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 + R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1 + >; + clock-output-names = + "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&extal_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; + clock-output-names = "thermal", "pwm"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, + <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&zx_clk>, <&zx_clk>, <&zx_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 + R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 + R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 + R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 + R8A7791_CLK_LVDS0 + >; + clock-output-names = + "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", + "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; + }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = <R8A7791_CLK_ETHER>; + clock-output-names = "ether"; + }; + mstp9_clks: mstp9_clks@e6150994 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; + clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD + R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 + R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 + >; + clock-output-names = + "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3", + "i2c2", "i2c1", "i2c0"; + }; + mstp11_clks: mstp11_clks@e615099c { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 + >; + clock-output-names = "scifa3", "scifa4", "scifa5"; + }; }; }; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 5cdaba4..1105558 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1,6 +1,6 @@ /* * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC - * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC + * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC * * Copyright (C) 2013 Atmel, * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> @@ -13,6 +13,7 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clk/at91.h> / { model = "Atmel SAMA5D3 family SoC"; @@ -36,6 +37,7 @@ i2c2 = &i2c2; ssc0 = &ssc0; ssc1 = &ssc1; + pwm0 = &pwm0; }; cpus { #address-cells = <1>; @@ -56,6 +58,14 @@ reg = <0x20000000 0x8000000>; }; + clocks { + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -79,6 +89,8 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; }; spi0: spi@f0004000 { @@ -92,6 +104,8 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -101,6 +115,8 @@ interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; status = "disabled"; }; @@ -108,6 +124,8 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf0010000 0x100>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>; + clock-names = "t0_clk"; }; i2c0: i2c@f0014000 { @@ -121,6 +139,7 @@ pinctrl-0 = <&pinctrl_i2c0>; #address-cells = <1>; #size-cells = <0>; + clocks = <&twi0_clk>; status = "disabled"; }; @@ -135,6 +154,7 @@ pinctrl-0 = <&pinctrl_i2c1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&twi1_clk>; status = "disabled"; }; @@ -144,6 +164,8 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -153,6 +175,17 @@ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + pwm0: pwm@f002c000 { + compatible = "atmel,sama5d3-pwm"; + reg = <0xf002c000 0x300>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; status = "disabled"; }; @@ -174,6 +207,8 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; + clocks = <&mci1_clk>; + clock-names = "mci_clk"; }; spi1: spi@f8008000 { @@ -187,6 +222,8 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -196,6 +233,8 @@ interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&ssc1_clk>; + clock-names = "pclk"; status = "disabled"; }; @@ -219,6 +258,9 @@ &pinctrl_adc0_ad10 &pinctrl_adc0_ad11 >; + clocks = <&adc_clk>, + <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; atmel,adc-channel-base = <0x50>; atmel,adc-channels-used = <0xfff>; atmel,adc-drdy-mask = <0x1000000>; @@ -272,8 +314,11 @@ dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; #address-cells = <1>; #size-cells = <0>; + clocks = <&twi2_clk>; status = "disabled"; }; @@ -283,6 +328,8 @@ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -292,25 +339,41 @@ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; status = "disabled"; }; sha@f8034000 { - compatible = "atmel,sam9g46-sha"; + compatible = "atmel,at91sam9g46-sha"; reg = <0xf8034000 0x100>; interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; + dma-names = "tx"; + clocks = <&sha_clk>; + clock-names = "sha_clk"; }; aes@f8038000 { - compatible = "atmel,sam9g46-aes"; + compatible = "atmel,at91sam9g46-aes"; reg = <0xf8038000 0x100>; - interrupts = <43 4 0>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; + dma-names = "tx", "rx"; + clocks = <&aes_clk>; + clock-names = "aes_clk"; }; tdes@f803c000 { - compatible = "atmel,sam9g46-tdes"; + compatible = "atmel,at91sam9g46-tdes"; reg = <0xf803c000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; + dma-names = "tx", "rx"; + clocks = <&tdes_clk>; + clock-names = "tdes_clk"; }; dma0: dma-controller@ffffe600 { @@ -318,6 +381,8 @@ reg = <0xffffe600 0x200>; interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; }; dma1: dma-controller@ffffe800 { @@ -325,6 +390,8 @@ reg = <0xffffe800 0x200>; interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; + clocks = <&dma1_clk>; + clock-names = "dma_clk"; }; ramc0: ramc@ffffea00 { @@ -338,6 +405,8 @@ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&dbgu_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -443,6 +512,14 @@ }; }; + i2c2 { + pinctrl_i2c2: i2c2-0 { + atmel,pins = + <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */ + AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ + }; + }; + isi { pinctrl_isi: isi-0 { atmel,pins = @@ -626,6 +703,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioA_clk>; }; pioB: gpio@fffff400 { @@ -636,6 +714,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioB_clk>; }; pioC: gpio@fffff600 { @@ -646,6 +725,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioC_clk>; }; pioD: gpio@fffff800 { @@ -656,6 +736,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioD_clk>; }; pioE: gpio@fffffa00 { @@ -666,12 +747,334 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioE_clk>; }; }; pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc"; + compatible = "atmel,sama5d3-pmc"; reg = <0xfffffc00 0x120>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + clk32k: slck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + main: mainck { + compatible = "atmel,at91rm9200-clk-main"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCS>; + clocks = <&clk32k>; + }; + + plla: pllack { + compatible = "atmel,sama5d3-clk-pll"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <8000000 50000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_LOCKU>; + clocks = <&main>; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; + atmel,clk-output-range = <0 166000000>; + atmel,clk-divisors = <1 2 4 3>; + }; + + usb: usbck { + compatible = "atmel,at91sam9x5-clk-usb"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = <AT91_PMC_PCKRDY(0)>; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = <AT91_PMC_PCKRDY(1)>; + }; + + prog2: prog2 { + #clock-cells = <0>; + reg = <2>; + interrupts = <AT91_PMC_PCKRDY(2)>; + }; + }; + + smd: smdclk { + compatible = "atmel,at91sam9x5-clk-smd"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + ddrck: ddrck { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + smdck: smdck { + #clock-cells = <0>; + reg = <4>; + clocks = <&smd>; + }; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck2 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + }; + + periphck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + dbgu_clk: dbgu_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <6>; + }; + + pioB_clk: pioB_clk { + #clock-cells = <0>; + reg = <7>; + }; + + pioC_clk: pioC_clk { + #clock-cells = <0>; + reg = <8>; + }; + + pioD_clk: pioD_clk { + #clock-cells = <0>; + reg = <9>; + }; + + pioE_clk: pioE_clk { + #clock-cells = <0>; + reg = <10>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <12>; + atmel,clk-output-range = <0 66000000>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <13>; + atmel,clk-output-range = <0 66000000>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <14>; + atmel,clk-output-range = <0 66000000>; + }; + + usart3_clk: usart3_clk { + #clock-cells = <0>; + reg = <15>; + atmel,clk-output-range = <0 66000000>; + }; + + twi0_clk: twi0_clk { + reg = <18>; + #clock-cells = <0>; + atmel,clk-output-range = <0 16625000>; + }; + + twi1_clk: twi1_clk { + #clock-cells = <0>; + reg = <19>; + atmel,clk-output-range = <0 16625000>; + }; + + twi2_clk: twi2_clk { + #clock-cells = <0>; + reg = <20>; + atmel,clk-output-range = <0 16625000>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <21>; + }; + + mci1_clk: mci1_clk { + #clock-cells = <0>; + reg = <22>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <24>; + atmel,clk-output-range = <0 133000000>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <25>; + atmel,clk-output-range = <0 133000000>; + }; + + tcb0_clk: tcb0_clk { + #clock-cells = <0>; + reg = <26>; + atmel,clk-output-range = <0 133000000>; + }; + + pwm_clk: pwm_clk { + #clock-cells = <0>; + reg = <28>; + }; + + adc_clk: adc_clk { + #clock-cells = <0>; + reg = <29>; + atmel,clk-output-range = <0 66000000>; + }; + + dma0_clk: dma0_clk { + #clock-cells = <0>; + reg = <30>; + }; + + dma1_clk: dma1_clk { + #clock-cells = <0>; + reg = <31>; + }; + + uhphs_clk: uhphs_clk { + #clock-cells = <0>; + reg = <32>; + }; + + udphs_clk: udphs_clk { + #clock-cells = <0>; + reg = <33>; + }; + + isi_clk: isi_clk { + #clock-cells = <0>; + reg = <37>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <38>; + atmel,clk-output-range = <0 66000000>; + }; + + ssc1_clk: ssc1_clk { + #clock-cells = <0>; + reg = <39>; + atmel,clk-output-range = <0 66000000>; + }; + + sha_clk: sha_clk { + #clock-cells = <0>; + reg = <42>; + }; + + aes_clk: aes_clk { + #clock-cells = <0>; + reg = <43>; + }; + + tdes_clk: tdes_clk { + #clock-cells = <0>; + reg = <44>; + }; + + trng_clk: trng_clk { + #clock-cells = <0>; + reg = <45>; + }; + + fuse_clk: fuse_clk { + #clock-cells = <0>; + reg = <48>; + }; + }; }; rstc@fffffe00 { @@ -683,6 +1086,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&mck>; }; watchdog@fffffe40 { @@ -705,6 +1109,8 @@ reg = <0x00500000 0x100000 0xf8030000 0x4000>; interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&utmi>; + clock-names = "pclk", "hclk"; status = "disabled"; ep0 { @@ -817,6 +1223,9 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>, + <&uhpck>; + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -824,6 +1233,8 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&uhphs_clk>, <&uhpck>; + clock-names = "usb_clk", "ehci_clk", "uhpck"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sama5d36.dtsi b/arch/arm/boot/dts/sama5d36.dtsi new file mode 100644 index 0000000..6c31c26 --- /dev/null +++ b/arch/arm/boot/dts/sama5d36.dtsi @@ -0,0 +1,20 @@ +/* + * sama5d36.dtsi - Device Tree Include file for SAMA5D36 SoC + * + * Copyright (C) 2013 Atmel, + * 2013 Josh Wu <josh.wu@atmel.com> + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_can.dtsi" +#include "sama5d3_emac.dtsi" +#include "sama5d3_gmac.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_mci2.dtsi" +#include "sama5d3_tcb1.dtsi" +#include "sama5d3_uart.dtsi" + +/ { + compatible = "atmel,samad36", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/boot/dts/sama5d36ek.dts b/arch/arm/boot/dts/sama5d36ek.dts new file mode 100644 index 0000000..59576c6 --- /dev/null +++ b/arch/arm/boot/dts/sama5d36ek.dts @@ -0,0 +1,53 @@ +/* + * sama5d36ek.dts - Device Tree file for SAMA5D36-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Josh Wu <josh.wu@atmel.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d36.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D36-EK"; + compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi index 8ed3260..a077585 100644 --- a/arch/arm/boot/dts/sama5d3_can.dtsi +++ b/arch/arm/boot/dts/sama5d3_can.dtsi @@ -32,12 +32,30 @@ }; + pmc: pmc@fffffc00 { + periphck { + can0_clk: can0_clk { + #clock-cells = <0>; + reg = <40>; + atmel,clk-output-range = <0 66000000>; + }; + + can1_clk: can0_clk { + #clock-cells = <0>; + reg = <41>; + atmel,clk-output-range = <0 66000000>; + }; + }; + }; + can0: can@f000c000 { compatible = "atmel,at91sam9x5-can"; reg = <0xf000c000 0x300>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_rx_tx>; + clocks = <&can0_clk>; + clock-names = "can_clk"; status = "disabled"; }; @@ -47,6 +65,8 @@ interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_rx_tx>; + clocks = <&can1_clk>; + clock-names = "can_clk"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi index 4d4f351..fe2af92 100644 --- a/arch/arm/boot/dts/sama5d3_emac.dtsi +++ b/arch/arm/boot/dts/sama5d3_emac.dtsi @@ -31,12 +31,23 @@ }; }; + pmc: pmc@fffffc00 { + periphck { + macb1_clk: macb1_clk { + #clock-cells = <0>; + reg = <35>; + }; + }; + }; + macb1: ethernet@f802c000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xf802c000 0x100>; interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb1_rmii>; + clocks = <&macb1_clk>, <&macb1_clk>; + clock-names = "hclk", "pclk"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi index 0ba8be3..a6cb050 100644 --- a/arch/arm/boot/dts/sama5d3_gmac.dtsi +++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi @@ -64,12 +64,23 @@ }; }; + pmc: pmc@fffffc00 { + periphck { + macb0_clk: macb0_clk { + #clock-cells = <0>; + reg = <34>; + }; + }; + }; + macb0: ethernet@f0028000 { compatible = "cdns,pc302-gem", "cdns,gem"; reg = <0xf0028000 0x100>; interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi index 01f52a7..85d3027 100644 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi @@ -50,6 +50,23 @@ }; }; }; + + pmc: pmc@fffffc00 { + periphck { + lcdc_clk: lcdc_clk { + #clock-cells = <0>; + reg = <36>; + }; + }; + + systemck { + lcdck: lcdck { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi index 38e88e3..b029fe7 100644 --- a/arch/arm/boot/dts/sama5d3_mci2.dtsi +++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clk/at91.h> / { ahb { @@ -30,6 +31,15 @@ }; }; + pmc: pmc@fffffc00 { + periphck { + mci2_clk: mci2_clk { + #clock-cells = <0>; + reg = <23>; + }; + }; + }; + mmc2: mmc@f8004000 { compatible = "atmel,hsmci"; reg = <0xf8004000 0x600>; @@ -38,6 +48,8 @@ dma-names = "rxtx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; + clocks = <&mci2_clk>; + clock-names = "mci_clk"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi index 5264bb4..382b044 100644 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clk/at91.h> / { aliases { @@ -17,10 +18,21 @@ ahb { apb { + pmc: pmc@fffffc00 { + periphck { + tcb1_clk: tcb1_clk { + #clock-cells = <0>; + reg = <27>; + }; + }; + }; + tcb1: timer@f8014000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8014000 0x100>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb1_clk>; + clock-names = "t0_clk"; }; }; }; diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi index 98fcb2d..a9fa75e 100644 --- a/arch/arm/boot/dts/sama5d3_uart.dtsi +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi @@ -9,8 +9,14 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clk/at91.h> / { + aliases { + serial5 = &uart0; + serial6 = &uart1; + }; + ahb { apb { pinctrl@fffff200 { @@ -31,12 +37,30 @@ }; }; + pmc: pmc@fffffc00 { + periphck { + uart0_clk: uart0_clk { + #clock-cells = <0>; + reg = <16>; + atmel,clk-output-range = <0 66000000>; + }; + + uart1_clk: uart1_clk { + #clock-cells = <0>; + reg = <17>; + atmel,clk-output-range = <0 66000000>; + }; + }; + }; + uart0: serial@f0024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf0024000 0x200>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -46,6 +70,8 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart1_clk>; + clock-names = "usart"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 726a0f3..f55ed07 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -18,17 +18,6 @@ reg = <0x20000000 0x20000000>; }; - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <12000000>; - }; - }; - ahb { apb { spi0: spi@f0004000 { @@ -38,6 +27,12 @@ macb0: ethernet@f0028000 { phy-mode = "rgmii"; }; + + pmc: pmc@fffffc00 { + main: mainck { + clock-frequency = <12000000>; + }; + }; }; nand0: nand@60000000 { diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi index 1c296d6..f9bdde5 100644 --- a/arch/arm/boot/dts/sama5d3xdm.dtsi +++ b/arch/arm/boot/dts/sama5d3xdm.dtsi @@ -18,6 +18,7 @@ interrupts = <31 0x0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qt1070_irq>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/sh7372-mackerel.dts b/arch/arm/boot/dts/sh7372-mackerel.dts index 8acf51e..a759a27 100644 --- a/arch/arm/boot/dts/sh7372-mackerel.dts +++ b/arch/arm/boot/dts/sh7372-mackerel.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "sh7372.dtsi" +#include "sh7372.dtsi" / { model = "Mackerel (AP4 EVM 2nd)"; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 8ee06dd..eb8886b 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -12,8 +12,9 @@ */ /dts-v1/; -/include/ "sh73a0.dtsi" +#include "sh73a0.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> / { model = "KZM-A9-GT"; @@ -82,7 +83,7 @@ reg = <0x10000000 0x100>; phy-mode = "mii"; interrupt-parent = <&irqpin0>; - interrupts = <3 0>; /* active low */ + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; reg-io-width = <4>; smsc,irq-push-pull; smsc,save-mac-address; @@ -105,6 +106,66 @@ gpios = <&pfc 23 GPIO_ACTIVE_LOW>; }; }; + + gpio-keys { + compatible = "gpio-keys"; + + back-key { + gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; + linux,code = <158>; + label = "SW3"; + }; + + right-key { + gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; + linux,code = <106>; + label = "SW2-R"; + }; + + left-key { + gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; + linux,code = <105>; + label = "SW2-L"; + }; + + enter-key { + gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; + linux,code = <28>; + label = "SW2-P"; + }; + + up-key { + gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; + linux,code = <103>; + label = "SW2-U"; + }; + + down-key { + gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; + linux,code = <108>; + label = "SW2-D"; + }; + + home-key { + gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; + linux,code = <102>; + label = "SW1"; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "left_j"; + simple-audio-card,cpu { + sound-dai = <&sh_fsi2 0>; + }; + simple-audio-card,codec { + sound-dai = <&ak4648>; + bitclock-master; + frame-master; + system-clock-frequency = <11289600>; + }; + }; }; &i2c0 { @@ -179,12 +240,29 @@ }; }; }; + + ak4648: ak4648@0x12 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak4648"; + reg = <0x12>; + }; }; &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; status = "okay"; + + pcf8575: gpio@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + interrupt-parent = <&irqpin2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; &mmcif { @@ -205,7 +283,7 @@ renesas,function = "i2c3"; }; - mmcif_pins: mmcif { + mmcif_pins: mmc { mux { renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; renesas,function = "mmc0"; @@ -217,20 +295,26 @@ }; }; - scifa4_pins: scifa4 { + scifa4_pins: serial4 { renesas,groups = "scifa4_data", "scifa4_ctrl"; renesas,function = "scifa4"; }; - sdhi0_pins: sdhi0 { + sdhi0_pins: sd0 { renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; renesas,function = "sdhi0"; }; - sdhi2_pins: sdhi2 { + sdhi2_pins: sd2 { renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; renesas,function = "sdhi2"; }; + + fsia_pins: sounda { + renesas,groups = "fsia_mclk_in", "fsia_sclk_in", + "fsia_data_in", "fsia_data_out"; + renesas,function = "fsia"; + }; }; &sdhi0 { @@ -251,3 +335,10 @@ broken-cd; status = "okay"; }; + +&sh_fsi2 { + pinctrl-0 = <&fsia_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index 0f1ca77..27c5f42 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "sh73a0.dtsi" +#include "sh73a0.dtsi" / { model = "KZM-A9-GT"; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index fcf2688..b7bd3b9 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -10,6 +10,8 @@ /include/ "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + / { compatible = "renesas,sh73a0"; @@ -40,12 +42,12 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 55 4>, - <0 56 4>; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>, + <0 56 IRQ_TYPE_LEVEL_HIGH>; }; irqpin0: irqpin@e6900000 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe6900000 4>, @@ -54,18 +56,18 @@ <0xe6900040 1>, <0xe6900060 1>; interrupt-parent = <&gic>; - interrupts = <0 1 0x4 - 0 2 0x4 - 0 3 0x4 - 0 4 0x4 - 0 5 0x4 - 0 6 0x4 - 0 7 0x4 - 0 8 0x4>; + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH + 0 2 IRQ_TYPE_LEVEL_HIGH + 0 3 IRQ_TYPE_LEVEL_HIGH + 0 4 IRQ_TYPE_LEVEL_HIGH + 0 5 IRQ_TYPE_LEVEL_HIGH + 0 6 IRQ_TYPE_LEVEL_HIGH + 0 7 IRQ_TYPE_LEVEL_HIGH + 0 8 IRQ_TYPE_LEVEL_HIGH>; }; irqpin1: irqpin@e6900004 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe6900004 4>, @@ -74,19 +76,19 @@ <0xe6900044 1>, <0xe6900064 1>; interrupt-parent = <&gic>; - interrupts = <0 9 0x4 - 0 10 0x4 - 0 11 0x4 - 0 12 0x4 - 0 13 0x4 - 0 14 0x4 - 0 15 0x4 - 0 16 0x4>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH + 0 10 IRQ_TYPE_LEVEL_HIGH + 0 11 IRQ_TYPE_LEVEL_HIGH + 0 12 IRQ_TYPE_LEVEL_HIGH + 0 13 IRQ_TYPE_LEVEL_HIGH + 0 14 IRQ_TYPE_LEVEL_HIGH + 0 15 IRQ_TYPE_LEVEL_HIGH + 0 16 IRQ_TYPE_LEVEL_HIGH>; control-parent; }; irqpin2: irqpin@e6900008 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe6900008 4>, @@ -95,18 +97,18 @@ <0xe6900048 1>, <0xe6900068 1>; interrupt-parent = <&gic>; - interrupts = <0 17 0x4 - 0 18 0x4 - 0 19 0x4 - 0 20 0x4 - 0 21 0x4 - 0 22 0x4 - 0 23 0x4 - 0 24 0x4>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH + 0 18 IRQ_TYPE_LEVEL_HIGH + 0 19 IRQ_TYPE_LEVEL_HIGH + 0 20 IRQ_TYPE_LEVEL_HIGH + 0 21 IRQ_TYPE_LEVEL_HIGH + 0 22 IRQ_TYPE_LEVEL_HIGH + 0 23 IRQ_TYPE_LEVEL_HIGH + 0 24 IRQ_TYPE_LEVEL_HIGH>; }; irqpin3: irqpin@e690000c { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe690000c 4>, @@ -115,14 +117,14 @@ <0xe690004c 1>, <0xe690006c 1>; interrupt-parent = <&gic>; - interrupts = <0 25 0x4 - 0 26 0x4 - 0 27 0x4 - 0 28 0x4 - 0 29 0x4 - 0 30 0x4 - 0 31 0x4 - 0 32 0x4>; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH + 0 26 IRQ_TYPE_LEVEL_HIGH + 0 27 IRQ_TYPE_LEVEL_HIGH + 0 28 IRQ_TYPE_LEVEL_HIGH + 0 29 IRQ_TYPE_LEVEL_HIGH + 0 30 IRQ_TYPE_LEVEL_HIGH + 0 31 IRQ_TYPE_LEVEL_HIGH + 0 32 IRQ_TYPE_LEVEL_HIGH>; }; i2c0: i2c@e6820000 { @@ -131,10 +133,10 @@ compatible = "renesas,rmobile-iic"; reg = <0xe6820000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 167 0x4 - 0 168 0x4 - 0 169 0x4 - 0 170 0x4>; + interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH + 0 168 IRQ_TYPE_LEVEL_HIGH + 0 169 IRQ_TYPE_LEVEL_HIGH + 0 170 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -144,10 +146,10 @@ compatible = "renesas,rmobile-iic"; reg = <0xe6822000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 51 0x4 - 0 52 0x4 - 0 53 0x4 - 0 54 0x4>; + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH + 0 52 IRQ_TYPE_LEVEL_HIGH + 0 53 IRQ_TYPE_LEVEL_HIGH + 0 54 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -157,10 +159,10 @@ compatible = "renesas,rmobile-iic"; reg = <0xe6824000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 171 0x4 - 0 172 0x4 - 0 173 0x4 - 0 174 0x4>; + interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH + 0 172 IRQ_TYPE_LEVEL_HIGH + 0 173 IRQ_TYPE_LEVEL_HIGH + 0 174 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -170,10 +172,10 @@ compatible = "renesas,rmobile-iic"; reg = <0xe6826000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 183 0x4 - 0 184 0x4 - 0 185 0x4 - 0 186 0x4>; + interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH + 0 184 IRQ_TYPE_LEVEL_HIGH + 0 185 IRQ_TYPE_LEVEL_HIGH + 0 186 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -183,52 +185,52 @@ compatible = "renesas,rmobile-iic"; reg = <0xe6828000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 187 0x4 - 0 188 0x4 - 0 189 0x4 - 0 190 0x4>; + interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH + 0 188 IRQ_TYPE_LEVEL_HIGH + 0 189 IRQ_TYPE_LEVEL_HIGH + 0 190 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - mmcif: mmcif@e6bd0000 { + mmcif: mmc@e6bd0000 { compatible = "renesas,sh-mmcif"; reg = <0xe6bd0000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 140 0x4 - 0 141 0x4>; + interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH + 0 141 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; status = "disabled"; }; - sdhi0: sdhi@ee100000 { - compatible = "renesas,sdhi-r8a7740"; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-sh73a0"; reg = <0xee100000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 83 4 - 0 84 4 - 0 85 4>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH + 0 84 IRQ_TYPE_LEVEL_HIGH + 0 85 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; }; /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ - sdhi1: sdhi@ee120000 { - compatible = "renesas,sdhi-r8a7740"; + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-sh73a0"; reg = <0xee120000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 88 4 - 0 89 4>; + interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH + 0 89 IRQ_TYPE_LEVEL_HIGH>; toshiba,mmc-wrprotect-disable; cap-sd-highspeed; status = "disabled"; }; - sdhi2: sdhi@ee140000 { - compatible = "renesas,sdhi-r8a7740"; + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-sh73a0"; reg = <0xee140000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 104 4 - 0 105 4>; + interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH + 0 105 IRQ_TYPE_LEVEL_HIGH>; toshiba,mmc-wrprotect-disable; cap-sd-highspeed; status = "disabled"; @@ -240,5 +242,23 @@ <0xe605801c 0x1c>; gpio-controller; #gpio-cells = <2>; + interrupts-extended = + <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, + <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, + <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, + <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, + <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, + <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, + <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, + <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; + }; + + sh_fsi2: sound@ec230000 { + #sound-dai-cells = <1>; + compatible = "renesas,sh_fsi2"; + reg = <0xec230000 0x400>; + interrupt-parent = <&gic>; + interrupts = <0 146 0x4>; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index f936476..537f1a5 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -79,6 +79,8 @@ #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; }; }; @@ -467,6 +469,8 @@ interrupts = <0 38 0x04>; cache-unified; cache-level = <2>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <2 1 1>; }; /* Local timer */ diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h index 8c45d85..4851c38 100644 --- a/arch/arm/boot/dts/st-pincfg.h +++ b/arch/arm/boot/dts/st-pincfg.h @@ -15,7 +15,7 @@ /* Pull Up */ #define PU (1 << 26) /* Open Drain */ -#define OD (1 << 26) +#define OD (1 << 25) #define RT (1 << 23) #define INVERTCLK (1 << 22) #define CLKNOTDATA (1 << 21) diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 7da99fe..e0853ea 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -913,6 +913,10 @@ interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ + <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ + dma-names = "rx", "tx"; + clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; clock-names = "msp", "apb_pclk"; @@ -925,6 +929,9 @@ interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ + dma-names = "tx"; + clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; clock-names = "msp", "apb_pclk"; @@ -938,6 +945,11 @@ interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ + <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev + HighPrio - Fixed */ + dma-names = "rx", "tx"; + clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; clock-names = "msp", "apb_pclk"; @@ -950,6 +962,9 @@ interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ + dma-names = "rx"; + clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; clock-names = "msp", "apb_pclk"; @@ -987,6 +1002,23 @@ status = "disabled"; }; + mcde@a0350000 { + compatible = "stericsson,mcde"; + reg = <0xa0350000 0x1000>, /* MCDE */ + <0xa0351000 0x1000>, /* DSI link 1 */ + <0xa0352000 0x1000>, /* DSI link 2 */ + <0xa0353000 0x1000>; /* DSI link 3 */ + interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ + <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ + <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */ + <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */ + <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */ + <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */ + <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */ + <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */ + }; + cryp@a03cb000 { compatible = "stericsson,ux500-cryp"; reg = <0xa03cb000 0x1000>; diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi new file mode 100644 index 0000000..addfcc7 --- /dev/null +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -0,0 +1,745 @@ +/* + * Copyright 2013 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "ste-nomadik-pinctrl.dtsi" + +/ { + soc { + pinctrl { + /* Settings for all UART default and sleep states */ + uart0 { + uart0_default_mode: uart0_default { + default_mux { + ste,function = "u0"; + ste,pins = "u0_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ + ste,config = <&in_pu>; + }; + + default_cfg2 { + ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ + ste,config = <&out_hi>; + }; + }; + + uart0_sleep_mode: uart0_sleep { + sleep_cfg1 { + ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ + ste,config = <&slpm_in_wkup_pdis>; + }; + + sleep_cfg2 { + ste,pins = "GPIO1_AJ3"; /* RTS */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + + sleep_cfg3 { + ste,pins = "GPIO3_AH3"; /* TXD */ + ste,config = <&slpm_out_wkup_pdis>; + }; + }; + }; + + uart1 { + uart1_default_mode: uart1_default { + default_mux { + ste,function = "u1"; + ste,pins = "u1rxtx_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO4_AH6"; /* RXD */ + ste,config = <&in_pu>; + }; + + default_cfg2 { + ste,pins = "GPIO5_AG6"; /* TXD */ + ste,config = <&out_hi>; + }; + }; + + uart1_sleep_mode: uart1_sleep { + sleep_cfg1 { + ste,pins = "GPIO4_AH6"; /* RXD */ + ste,config = <&slpm_in_wkup_pdis>; + }; + + sleep_cfg2 { + ste,pins = "GPIO5_AG6"; /* TXD */ + ste,config = <&slpm_out_wkup_pdis>; + }; + }; + }; + + uart2 { + uart2_default_mode: uart2_default { + default_mux { + ste,function = "u2"; + ste,pins = "u2rxtx_c_1"; + }; + default_cfg1 { + ste,pins = "GPIO29_W2"; /* RXD */ + ste,config = <&in_pu>; + }; + + default_cfg2 { + ste,pins = "GPIO30_W3"; /* TXD */ + ste,config = <&out_hi>; + }; + }; + + uart2_sleep_mode: uart2_sleep { + sleep_cfg1 { + ste,pins = "GPIO29_W2"; /* RXD */ + ste,config = <&in_wkup_pdis>; + }; + + sleep_cfg2 { + ste,pins = "GPIO30_W3"; /* TXD */ + ste,config = <&out_wkup_pdis>; + }; + }; + }; + + /* Settings for all I2C default and sleep states */ + i2c0 { + i2c0_default_mode: i2c_default { + default_mux { + ste,function = "i2c0"; + ste,pins = "i2c0_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ + ste,config = <&in_pu>; + }; + }; + + i2c0_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + i2c1 { + i2c1_default_mode: i2c_default { + default_mux { + ste,function = "i2c1"; + ste,pins = "i2c1_b_2"; + }; + default_cfg1 { + ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ + ste,config = <&in_pu>; + }; + }; + + i2c1_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + i2c2 { + i2c2_default_mode: i2c_default { + default_mux { + ste,function = "i2c2"; + ste,pins = "i2c2_b_2"; + }; + default_cfg1 { + ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ + ste,config = <&in_pu>; + }; + }; + + i2c2_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + i2c3 { + i2c3_default_mode: i2c_default { + default_mux { + ste,function = "i2c3"; + ste,pins = "i2c3_c_2"; + }; + default_cfg1 { + ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ + ste,config = <&in_pu>; + }; + }; + + i2c3_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + /* + * Activating I2C4 will conflict with UART1 about the same pins so do not + * enable I2C4 and UART1 at the same time. + */ + i2c4 { + i2c4_default_mode: i2c_default { + default_mux { + ste,function = "i2c4"; + ste,pins = "i2c4_b_1"; + }; + default_cfg1 { + ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ + ste,config = <&in_pu>; + }; + }; + + i2c4_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + /* Settings for all SPI default and sleep states */ + spi2 { + spi2_default_mode: spi_default { + default_mux { + ste,function = "spi2"; + ste,pins = "spi2_oc1_2"; + }; + default_cfg1 { + ste,pins = "GPIO216_AG12"; /* FRM */ + ste,config = <&gpio_out_hi>; + }; + default_cfg2 { + ste,pins = "GPIO218_AH11"; /* RXD */ + ste,config = <&in_pd>; + }; + default_cfg3 { + ste,pins = + "GPIO215_AH13", /* TXD */ + "GPIO217_AH12"; /* CLK */ + ste,config = <&out_lo>; + }; + }; + + spi2_idle_mode: spi_idle { + /* + * The idle mode is basically sleep mode sans wakeups. Also + * note that we have muxes the pins off the function here + * as we do not state any muxing. + */ + idle_cfg1 { + ste,pins = "GPIO218_AH11"; /* RXD */ + ste,config = <&slpm_in_pdis>; + }; + idle_cfg2 { + ste,pins = "GPIO215_AH13"; /* TXD */ + ste,config = <&slpm_out_lo_pdis>; + }; + idle_cfg3 { + ste,pins = "GPIO217_AH12"; /* CLK */ + ste,config = <&slpm_pdis>; + }; + }; + + spi2_sleep_mode: spi_sleep { + sleep_cfg1 { + ste,pins = + "GPIO216_AG12", /* FRM */ + "GPIO218_AH11"; /* RXD */ + ste,config = <&slpm_in_wkup_pdis>; + }; + sleep_cfg2 { + ste,pins = "GPIO215_AH13"; /* TXD */ + ste,config = <&slpm_out_lo_wkup_pdis>; + }; + sleep_cfg3 { + ste,pins = "GPIO217_AH12"; /* CLK */ + ste,config = <&slpm_wkup_pdis>; + }; + }; + }; + + /* Settings for all MMC/SD/SDIO default and sleep states */ + sdi0 { + /* This is the external SD card slot, 4 bits wide */ + sdi0_default_mode: sdi0_default { + default_mux { + ste,function = "mc0"; + ste,pins = "mc0_a_1"; + }; + default_cfg1 { + ste,pins = + "GPIO18_AC2", /* CMDDIR */ + "GPIO19_AC1", /* DAT0DIR */ + "GPIO20_AB4"; /* DAT2DIR */ + ste,config = <&out_hi>; + }; + default_cfg2 { + ste,pins = "GPIO22_AA3"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + default_cfg3 { + ste,pins = "GPIO23_AA4"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg4 { + ste,pins = + "GPIO24_AB2", /* CMD */ + "GPIO25_Y4", /* DAT0 */ + "GPIO26_Y2", /* DAT1 */ + "GPIO27_AA2", /* DAT2 */ + "GPIO28_AA1"; /* DAT3 */ + ste,config = <&in_pu>; + }; + }; + + sdi0_sleep_mode: sdi0_sleep { + sleep_cfg1 { + ste,pins = + "GPIO18_AC2", /* CMDDIR */ + "GPIO19_AC1", /* DAT0DIR */ + "GPIO20_AB4"; /* DAT2DIR */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + sleep_cfg2 { + ste,pins = + "GPIO22_AA3", /* FBCLK */ + "GPIO24_AB2", /* CMD */ + "GPIO25_Y4", /* DAT0 */ + "GPIO26_Y2", /* DAT1 */ + "GPIO27_AA2", /* DAT2 */ + "GPIO28_AA1"; /* DAT3 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + sleep_cfg3 { + ste,pins = "GPIO23_AA4"; /* CLK */ + ste,config = <&slpm_out_lo_wkup_pdis>; + }; + }; + }; + + sdi1 { + /* This is the WLAN SDIO 4 bits wide */ + sdi1_default_mode: sdi1_default { + default_mux { + ste,function = "mc1"; + ste,pins = "mc1_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO208_AH16"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg2 { + ste,pins = "GPIO209_AG15"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + default_cfg3 { + ste,pins = + "GPIO210_AJ15", /* CMD */ + "GPIO211_AG14", /* DAT0 */ + "GPIO212_AF13", /* DAT1 */ + "GPIO213_AG13", /* DAT2 */ + "GPIO214_AH15"; /* DAT3 */ + ste,config = <&in_pu>; + }; + }; + + sdi1_sleep_mode: sdi1_sleep { + sleep_cfg1 { + ste,pins = "GPIO208_AH16"; /* CLK */ + ste,config = <&slpm_out_lo_wkup_pdis>; + }; + sleep_cfg2 { + ste,pins = + "GPIO209_AG15", /* FBCLK */ + "GPIO210_AJ15", /* CMD */ + "GPIO211_AG14", /* DAT0 */ + "GPIO212_AF13", /* DAT1 */ + "GPIO213_AG13", /* DAT2 */ + "GPIO214_AH15"; /* DAT3 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + sdi2 { + /* This is the eMMC 8 bits wide, usually PoP eMMC */ + sdi2_default_mode: sdi2_default { + default_mux { + ste,function = "mc2"; + ste,pins = "mc2_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO128_A5"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg2 { + ste,pins = "GPIO130_C8"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + default_cfg3 { + ste,pins = + "GPIO129_B4", /* CMD */ + "GPIO131_A12", /* DAT0 */ + "GPIO132_C10", /* DAT1 */ + "GPIO133_B10", /* DAT2 */ + "GPIO134_B9", /* DAT3 */ + "GPIO135_A9", /* DAT4 */ + "GPIO136_C7", /* DAT5 */ + "GPIO137_A7", /* DAT6 */ + "GPIO138_C5"; /* DAT7 */ + ste,config = <&in_pu>; + }; + }; + + sdi2_sleep_mode: sdi2_sleep { + sleep_cfg1 { + ste,pins = "GPIO128_A5"; /* CLK */ + ste,config = <&out_lo_wkup_pdis>; + }; + sleep_cfg2 { + ste,pins = + "GPIO130_C8", /* FBCLK */ + "GPIO129_B4"; /* CMD */ + ste,config = <&in_wkup_pdis_en>; + }; + sleep_cfg3 { + ste,pins = + "GPIO131_A12", /* DAT0 */ + "GPIO132_C10", /* DAT1 */ + "GPIO133_B10", /* DAT2 */ + "GPIO134_B9", /* DAT3 */ + "GPIO135_A9", /* DAT4 */ + "GPIO136_C7", /* DAT5 */ + "GPIO137_A7", /* DAT6 */ + "GPIO138_C5"; /* DAT7 */ + ste,config = <&in_wkup_pdis>; + }; + }; + }; + + sdi4 { + /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */ + sdi4_default_mode: sdi4_default { + default_mux { + ste,function = "mc4"; + ste,pins = "mc4_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO203_AE23"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg2 { + ste,pins = "GPIO202_AF25"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + default_cfg3 { + ste,pins = + "GPIO201_AF24", /* CMD */ + "GPIO200_AH26", /* DAT0 */ + "GPIO199_AH23", /* DAT1 */ + "GPIO198_AG25", /* DAT2 */ + "GPIO197_AH24", /* DAT3 */ + "GPIO207_AJ23", /* DAT4 */ + "GPIO206_AG24", /* DAT5 */ + "GPIO205_AG23", /* DAT6 */ + "GPIO204_AF23"; /* DAT7 */ + ste,config = <&in_pu>; + }; + }; + + sdi4_sleep_mode: sdi4_sleep { + sleep_cfg1 { + ste,pins = "GPIO203_AE23"; /* CLK */ + ste,config = <&out_lo_wkup_pdis>; + }; + sleep_cfg2 { + ste,pins = + "GPIO202_AF25", /* FBCLK */ + "GPIO201_AF24", /* CMD */ + "GPIO200_AH26", /* DAT0 */ + "GPIO199_AH23", /* DAT1 */ + "GPIO198_AG25", /* DAT2 */ + "GPIO197_AH24", /* DAT3 */ + "GPIO207_AJ23", /* DAT4 */ + "GPIO206_AG24", /* DAT5 */ + "GPIO205_AG23", /* DAT6 */ + "GPIO204_AF23"; /* DAT7 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + /* + * Multi-rate serial ports (MSPs) - MSP3 output is internal and + * cannot be muxed onto any pins. + */ + msp0 { + msp0_default_mode: msp0_default { + default_msp0_mux { + ste,function = "msp0"; + ste,pins = "msp0txrx_a_1", "msp0tfstck_a_1"; + }; + default_msp0_cfg { + ste,pins = + "GPIO12_AC4", /* TXD */ + "GPIO15_AC3", /* RXD */ + "GPIO13_AF3", /* TFS */ + "GPIO14_AE3"; /* TCK */ + ste,config = <&in_nopull>; + }; + }; + }; + + msp1 { + msp1_default_mode: msp1_default { + default_mux { + ste,function = "msp1"; + ste,pins = "msp1txrx_a_1", "msp1_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO33_AF2"; + ste,config = <&out_lo>; + }; + default_cfg2 { + ste,pins = + "GPIO34_AE1", + "GPIO35_AE2", + "GPIO36_AG2"; + ste,config = <&in_nopull>; + }; + + }; + }; + + msp2 { + msp2_default_mode: msp2_default { + /* MSP2 usually used for HDMI audio */ + default_mux { + ste,function = "msp2"; + ste,pins = "msp2_a_1"; + }; + default_cfg1 { + ste,pins = + "GPIO193_AH27", /* TXD */ + "GPIO194_AF27", /* TCK */ + "GPIO195_AG28"; /* TFS */ + ste,config = <&in_pd>; + }; + default_cfg2 { + ste,pins = "GPIO196_AG26"; /* RXD */ + ste,config = <&out_lo>; + }; + }; + }; + + + musb { + musb_default_mode: musb_default { + default_mux { + ste,function = "usb"; + ste,pins = "usb_a_1"; + }; + default_cfg1 { + ste,pins = + "GPIO256_AF28", /* NXT */ + "GPIO258_AD29", /* XCLK */ + "GPIO259_AC29", /* DIR */ + "GPIO260_AD28", /* DAT7 */ + "GPIO261_AD26", /* DAT6 */ + "GPIO262_AE26", /* DAT5 */ + "GPIO263_AG29", /* DAT4 */ + "GPIO264_AE27", /* DAT3 */ + "GPIO265_AD27", /* DAT2 */ + "GPIO266_AC28", /* DAT1 */ + "GPIO267_AC27"; /* DAT0 */ + ste,config = <&in_nopull>; + }; + default_cfg2 { + ste,pins = "GPIO257_AE29"; /* STP */ + ste,config = <&out_hi>; + }; + }; + + musb_sleep_mode: musb_sleep { + sleep_cfg1 { + ste,pins = + "GPIO256_AF28", /* NXT */ + "GPIO258_AD29", /* XCLK */ + "GPIO259_AC29"; /* DIR */ + ste,config = <&slpm_wkup_pdis_en>; + }; + sleep_cfg2 { + ste,pins = "GPIO257_AE29"; /* STP */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + sleep_cfg3 { + ste,pins = + "GPIO260_AD28", /* DAT7 */ + "GPIO261_AD26", /* DAT6 */ + "GPIO262_AE26", /* DAT5 */ + "GPIO263_AG29", /* DAT4 */ + "GPIO264_AE27", /* DAT3 */ + "GPIO265_AD27", /* DAT2 */ + "GPIO266_AC28", /* DAT1 */ + "GPIO267_AC27"; /* DAT0 */ + ste,config = <&slpm_in_wkup_pdis_en>; + }; + }; + }; + + mcde { + lcd_default_mode: lcd_default { + default_mux { + /* Mux in VSI0 and all the data lines */ + ste,function = "lcd"; + ste,pins = + "lcdvsi0_a_1", /* VSI0 for LCD */ + "lcd_d0_d7_a_1", /* Data lines */ + "lcd_d8_d11_a_1", /* TV-out */ + "lcdaclk_b_1", /* Clock line for TV-out */ + "lcdvsi1_a_1"; /* VSI1 for HDMI */ + }; + default_cfg1 { + ste,pins = + "GPIO68_E1", /* VSI0 */ + "GPIO69_E2"; /* VSI1 */ + ste,config = <&in_pu>; + }; + }; + lcd_sleep_mode: lcd_sleep { + sleep_cfg1 { + ste,pins = "GPIO69_E2"; /* VSI1 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + ske { + /* SKE keys on position 2 in an 8x8 matrix */ + ske_kpa2_default_mode: ske_kpa2_default { + default_mux { + ste,function = "kp"; + ste,pins = "kp_a_2"; + }; + default_cfg1 { + ste,pins = + "GPIO153_B17", /* I7 */ + "GPIO154_C16", /* I6 */ + "GPIO155_C19", /* I5 */ + "GPIO156_C17", /* I4 */ + "GPIO161_D21", /* I3 */ + "GPIO162_D20", /* I2 */ + "GPIO163_C20", /* I1 */ + "GPIO164_B21"; /* I0 */ + ste,config = <&in_pd>; + }; + default_cfg2 { + ste,pins = + "GPIO157_A18", /* O7 */ + "GPIO158_C18", /* O6 */ + "GPIO159_B19", /* O5 */ + "GPIO160_B20", /* O4 */ + "GPIO165_C21", /* O3 */ + "GPIO166_A22", /* O2 */ + "GPIO167_B24", /* O1 */ + "GPIO168_C22"; /* O0 */ + ste,config = <&out_lo>; + }; + }; + ske_kpa2_sleep_mode: ske_kpa2_sleep { + sleep_cfg1 { + ste,pins = + "GPIO153_B17", /* I7 */ + "GPIO154_C16", /* I6 */ + "GPIO155_C19", /* I5 */ + "GPIO156_C17", /* I4 */ + "GPIO161_D21", /* I3 */ + "GPIO162_D20", /* I2 */ + "GPIO163_C20", /* I1 */ + "GPIO164_B21"; /* I0 */ + ste,config = <&slpm_in_pu_wkup_pdis_en>; + }; + sleep_cfg2 { + ste,pins = + "GPIO157_A18", /* O7 */ + "GPIO158_C18", /* O6 */ + "GPIO159_B19", /* O5 */ + "GPIO160_B20", /* O4 */ + "GPIO165_C21", /* O3 */ + "GPIO166_A22", /* O2 */ + "GPIO167_B24", /* O1 */ + "GPIO168_C22"; /* O0 */ + ste,config = <&slpm_out_lo_pdis>; + }; + }; + /* + * SKE keys on position 1 and "other C1" combi giving + * six rows of six keys. + */ + ske_kpaoc1_default_mode: ske_kpaoc1_default { + default_mux { + ste,function = "kp"; + ste,pins = "kp_a_1", "kp_oc1_1"; + }; + default_cfg1 { + ste,pins = + "GPIO91_B6", /* KP_O0 */ + "GPIO90_A3", /* KP_O1 */ + "GPIO87_B3", /* KP_O2 */ + "GPIO86_C6", /* KP_O3 */ + "GPIO96_D8", /* KP_O6 */ + "GPIO94_D7"; /* KP_O7 */ + ste,config = <&out_lo>; + }; + default_cfg2 { + ste,pins = + "GPIO93_B7", /* KP_I0 */ + "GPIO92_D6", /* KP_I1 */ + "GPIO89_E6", /* KP_I2 */ + "GPIO88_C4", /* KP_I3 */ + "GPIO97_D9", /* KP_I6 */ + "GPIO95_E8"; /* KP_I7 */ + ste,config = <&in_pu>; + }; + }; + }; + + wlan { + wlan_default_mode: wlan_default { + /* + * Activate this mode with the WLAN chip. + * These are plain GPIO pins used by WLAN + */ + default_cfg1 { + ste,pins = + "GPIO226_AF8", /* WLAN_PMU_EN */ + "GPIO85_D5"; /* WLAN_ENA */ + ste,config = <&gpio_out_lo>; + }; + default_cfg2 { + ste,pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi index 76704ec..1c35744 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -12,6 +12,28 @@ #include <dt-bindings/interrupt-controller/irq.h> / { + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&prox_stuib_mode>, <&hall_stuib_mode>; + + button@139 { + /* Proximity sensor */ + gpios = <&gpio6 25 0x4>; + linux,code = <11>; /* SW_FRONT_PROXIMITY */ + label = "SFH7741 Proximity Sensor"; + }; + button@145 { + /* Hall sensor */ + gpios = <&gpio4 17 0x4>; + linux,code = <0>; /* SW_LID */ + label = "HED54XXU11 Hall Effect Sensor"; + }; + }; + soc { i2c@80004000 { stmpe1601: stmpe1601@40 { @@ -74,5 +96,24 @@ rohm,flip-y; }; }; + + pinctrl { + prox { + prox_stuib_mode: prox_stuib { + stuib_cfg { + ste,pins = "GPIO217_AH12"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + hall { + hall_stuib_mode: stuib_tvk { + stuib_cfg { + ste,pins = "GPIO145_C13"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi index 76d3ef1..c405653 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi @@ -14,27 +14,105 @@ #include <dt-bindings/interrupt-controller/irq.h> / { + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>; + + button@139 { + /* Proximity sensor */ + gpios = <&gpio6 25 0x4>; + linux,code = <11>; /* SW_FRONT_PROXIMITY */ + label = "SFH7741 Proximity Sensor"; + }; + button@145 { + /* Hall sensor */ + gpios = <&gpio4 17 0x4>; + linux,code = <0>; /* SW_LID */ + label = "HED54XXU11 Hall Effect Sensor"; + }; + }; + soc { - /* Add Synaptics touch screen, TC35892 keypad etc here */ + /* Add Synaptics touch screen, TC35893 keypad etc here */ i2c@80004000 { - tc3589x@44 { - compatible = "tc3589x"; + tc35893@44 { + compatible = "toshiba,tc35893"; reg = <0x44>; interrupt-parent = <&gpio6>; interrupts = <26 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&tc35893_tvk_mode>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; tc3589x_gpio { - compatible = "tc3589x-gpio"; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; + compatible = "toshiba,tc3589x-gpio"; + interrupts = <0>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; }; + tc3589x_keypad { + compatible = "toshiba,tc3589x-keypad"; + interrupts = <6>; + debounce-delay-ms = <4>; + keypad,num-columns = <8>; + keypad,num-rows = <8>; + linux,no-autorepeat; + linux,wakeup; + linux,keymap = <0x0301006b + 0x04010066 + 0x06040072 + 0x040200d7 + 0x0303006a + 0x0205000e + 0x0607008b + 0x0500001c + 0x0403000b + 0x03040034 + 0x05020067 + 0x0305006c + 0x040500e7 + 0x0005009e + 0x06020073 + 0x01030039 + 0x07060069 + 0x050500d9>; + }; + }; + }; + pinctrl { + /* Pull up this GPIO pin */ + tc35893 { + tc35893_tvk_mode: tc35893_tvk { + tvk_cfg { + ste,pins = "GPIO218_AH11"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + prox { + prox_tvk_mode: prox_tvk { + tvk_cfg { + ste,pins = "GPIO217_AH12"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + hall { + hall_tvk_mode: hall_tvk { + tvk_cfg { + ste,pins = "GPIO145_C13"; + ste,config = <&gpio_in_pu>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index aa3f020..0c1e8d8 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -11,37 +11,57 @@ #include <dt-bindings/interrupt-controller/irq.h> #include "ste-dbx5x0.dtsi" +#include "ste-href-family-pinctrl.dtsi" / { memory { reg = <0x00000000 0x20000000>; }; - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - linux,code = <11>; - label = "SFH7741 Proximity Sensor"; + soc { + usb_per5@a03e0000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&musb_default_mode>; + pinctrl-1 = <&musb_sleep_mode>; }; - }; - soc { uart@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart0_default_mode>; + pinctrl-1 = <&uart0_sleep_mode>; status = "okay"; }; uart@80121000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_default_mode>; + pinctrl-1 = <&uart1_sleep_mode>; status = "okay"; }; uart@80007000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart2_default_mode>; + pinctrl-1 = <&uart2_sleep_mode>; status = "okay"; }; + i2c@80004000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c0_default_mode>; + pinctrl-1 = <&i2c0_sleep_mode>; + }; + + i2c@80122000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c1_default_mode>; + pinctrl-1 = <&i2c1_sleep_mode>; + }; + i2c@80128000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c2_default_mode>; + pinctrl-1 = <&i2c2_sleep_mode>; lp5521@33 { compatible = "national,lp5521"; reg = <0x33>; @@ -85,6 +105,12 @@ }; }; + i2c@80110000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c3_default_mode>; + pinctrl-1 = <&i2c3_sleep_mode>; + }; + // External Micro SD slot sdi0_per1@80126000 { arm,primecell-periphid = <0x10480180>; @@ -94,8 +120,9 @@ mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; vqmmc-supply = <&vmmci>; - - cd-gpios = <&tc3589x_gpio 3 0x4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi0_default_mode>; + pinctrl-1 = <&sdi0_sleep_mode>; status = "okay"; }; @@ -105,6 +132,9 @@ arm,primecell-periphid = <0x10480180>; max-frequency = <100000000>; bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi1_default_mode>; + pinctrl-1 = <&sdi1_sleep_mode>; status = "okay"; }; @@ -115,6 +145,9 @@ max-frequency = <100000000>; bus-width = <8>; mmc-cap-mmc-highspeed; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi2_default_mode>; + pinctrl-1 = <&sdi2_sleep_mode>; status = "okay"; }; @@ -126,6 +159,9 @@ bus-width = <8>; mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux2_reg>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi4_default_mode>; + pinctrl-1 = <&sdi4_sleep_mode>; status = "okay"; }; @@ -137,7 +173,21 @@ stericsson,audio-codec = <&codec>; }; + msp0: msp@80123000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp0_default_mode>; + status = "okay"; + }; + msp1: msp@80124000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp1_default_mode>; + status = "okay"; + }; + + msp2: msp@80117000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp2_default_mode>; status = "okay"; }; @@ -198,5 +248,11 @@ }; }; }; + + mcde@a0350000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_default_mode>; + pinctrl-1 = <&lcd_sleep_mode>; + }; }; }; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index b2cd7bc..40f0ecd 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -28,18 +28,20 @@ reg = <0x33>; }; - tc3589x@42 { - compatible = "tc3589x"; + tc35892@42 { + compatible = "toshiba,tc35892"; reg = <0x42>; interrupt-parent = <&gpio6>; interrupts = <25 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&tc35892_hrefprev60_mode>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; tc3589x_gpio: tc3589x_gpio { compatible = "tc3589x-gpio"; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; + interrupts = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -49,11 +51,77 @@ }; }; + ssp@80002000 { + /* + * On the first generation boards, this SSP/SPI port was connected + * to the AB8500. + */ + pinctrl-names = "default"; + pinctrl-0 = <&ssp0_hrefprev60_mode>; + }; + + // External Micro SD slot + sdi0_per1@80126000 { + cd-gpios = <&tc3589x_gpio 3 0x4>; + }; + vmmci: regulator-gpio { gpios = <&tc3589x_gpio 18 0x4>; enable-gpio = <&tc3589x_gpio 17 0x4>; + }; + + pinctrl { + /* Set this up using hogs */ + pinctrl-names = "default"; + pinctrl-0 = <&ipgpio_hrefprev60_mode>; - status = "okay"; + ssp0 { + ssp0_hrefprev60_mode: ssp0_hrefprev60_default { + hrefprev60_mux { + ste,function = "ssp0"; + ste,pins = "ssp0_a_1"; + }; + hrefprev60_cfg1 { + ste,pins = "GPIO145_C13"; /* RXD */ + ste,config = <&in_pd>; + }; + + }; + }; + sdi0 { + /* This additional pin needed on early MOP500 and HREFs previous to v60 */ + sdi0_default_mode: sdi0_default { + hrefprev60_mux { + ste,function = "mc0"; + ste,pins = "mc0dat31dir_a_1"; + }; + hrefprev60_cfg1 { + ste,pins = "GPIO21_AB3"; /* DAT31DIR */ + ste,config = <&out_hi>; + }; + + }; + }; + tc35892 { + tc35892_hrefprev60_mode: tc35892_hrefprev60 { + hrefprev60_cfg { + ste,pins = "GPIO217_AH12"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + ipgpio { + ipgpio_hrefprev60_mode: ipgpio_hrefprev60 { + hrefprev60_mux { + ste,function = "ipgpio"; + ste,pins = "ipgpio0_c_1", "ipgpio1_c_1"; + }; + hrefprev60_cfg1 { + ste,pins = "GPIO6_AF6", "GPIO7_AG5"; + ste,config = <&in_pu>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index aed511b..3b6d118 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -16,55 +16,226 @@ model = "ST-Ericsson HREF (v60+) platform with Device Tree"; compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; - gpio_keys { - button@1 { - gpios = <&gpio5 25 0x4>; - }; - }; - soc { // External Micro SD slot sdi0_per1@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - mmc-cap-sd-highspeed; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - cd-gpios = <&gpio2 31 0x4>; // 95 - - status = "okay"; }; - // WLAN SDIO channel - sdi1_per2@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - - status = "okay"; - }; - - // PoP:ed eMMC - sdi2_per3@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - mmc-cap-mmc-highspeed; - - status = "okay"; + vmmci: regulator-gpio { + gpios = <&gpio0 5 0x4>; + enable-gpio = <&gpio5 9 0x4>; }; - // On-board eMMC - sdi4_per2@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux2_reg>; + pinctrl { + /* + * Set this up using hogs, as time goes by and as seems fit, these + * can be moved over to being controlled by respective device. + */ + pinctrl-names = "default"; + pinctrl-0 = <&ipgpio_hrefv60_mode>, + <&accel_hrefv60_mode>, + <&magneto_hrefv60_mode>, + <&etm_hrefv60_mode>, + <&nahj_hrefv60_mode>, + <&nfc_hrefv60_mode>, + <&force_hrefv60_mode>, + <&dipro_hrefv60_mode>, + <&vaudio_hf_hrefv60_mode>, + <&gbf_hrefv60_mode>, + <&hdtv_hrefv60_mode>, + <&touch_hrefv60_mode>; - status = "okay"; + sdi0 { + /* SD card detect GPIO pin, extend default state */ + sdi0_default_mode: sdi0_default { + default_hrefv60_cfg1 { + ste,pins = "GPIO95_E8"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + ipgpio { + /* + * XENON Flashgun on image processor GPIO (controlled from image + * processor firmware), mux in these image processor GPIO lines 0 + * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant + * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias + * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output. + */ + ipgpio_hrefv60_mode: ipgpio_hrefv60 { + hrefv60_mux { + ste,function = "ipgpio"; + ste,pins = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1"; + }; + hrefv60_cfg1 { + ste,pins = "GPIO6_AF6", "GPIO7_AG5"; + ste,config = <&in_pu>; + }; + hrefv60_cfg2 { + ste,pins = "GPIO21_AB3"; + ste,config = <&gpio_out_lo>; + }; + hrefv60_cfg3 { + ste,pins = "GPIO64_F3"; + ste,config = <&out_lo>; + }; + }; + }; + accelerometer { + accel_hrefv60_mode: accel_hrefv60 { + /* Accelerometer interrupt lines 1 & 2 */ + hrefv60_cfg1 { + ste,pins = "GPIO82_C1", "GPIO83_D3"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + magnetometer { + magneto_hrefv60_mode: magneto_hrefv60 { + /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ + hrefv60_cfg1 { + ste,pins = "GPIO31_V3"; + ste,config = <&gpio_in_pu>; + }; + hrefv60_cfg2 { + ste,pins = "GPIO32_V2"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + etm { + /* + * Drive D19-D23 for the ETM PTM trace interface low, + * (presumably pins are unconnected therefore grounded here, + * the "other alt C1" setting enables these pins) + */ + etm_hrefv60_mode: etm_hrefv60 { + hrefv60_cfg1 { + ste,pins = + "GPIO70_G5", + "GPIO71_G4", + "GPIO72_H4", + "GPIO73_H3", + "GPIO74_J3"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + nahj { + nahj_hrefv60_mode: nahj_hrefv60 { + /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */ + hrefv60_cfg1 { + ste,pins = "GPIO76_J2"; + ste,config = <&gpio_out_lo>; + }; + hrefv60_cfg2 { + ste,pins = "GPIO216_AG12"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + nfc { + nfc_hrefv60_mode: nfc_hrefv60 { + /* NFC ENA and RESET to low, pulldown IRQ line */ + hrefv60_cfg1 { + ste,pins = + "GPIO77_H1", /* NFC_ENA */ + "GPIO142_C11"; /* NFC_RESET */ + ste,config = <&gpio_out_lo>; + }; + hrefv60_cfg2 { + ste,pins = "GPIO144_B13"; /* NFC_IRQ */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + force { + force_hrefv60_mode: force_hrefv60 { + hrefv60_cfg1 { + ste,pins = "GPIO91_B6"; /* FORCE_SENSING_INT */ + ste,config = <&gpio_in_pu>; + }; + hrefv60_cfg2 { + ste,pins = + "GPIO92_D6", /* FORCE_SENSING_RST */ + "GPIO97_D9"; /* FORCE_SENSING_WU */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + dipro { + dipro_hrefv60_mode: dipro_hrefv60 { + hrefv60_cfg1 { + ste,pins = "GPIO139_C9"; /* DIPRO_INT */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + vaudio_hf { + vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 { + /* Audio Amplifier HF enable GPIO */ + hrefv60_cfg1 { + ste,pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */ + ste,config = <&gpio_out_hi>; + }; + }; + }; + gbf { + gbf_hrefv60_mode: gbf_hrefv60 { + /* + * GBF (GPS, Bluetooth, FM-radio) interface, + * pull low to reset state + */ + hrefv60_cfg1 { + ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + hdtv { + hdtv_hrefv60_mode: hdtv_hrefv60 { + /* MSP : HDTV INTERFACE GPIO line */ + hrefv60_cfg1 { + ste,pins = "GPIO192_AJ27"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + touch { + touch_hrefv60_mode: touch_hrefv60 { + /* + * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and + * GPIO 67 for interrupts. Pull-up the IRQ line and drive both + * reset signals low. + */ + hrefv60_cfg1 { + ste,pins = "GPIO143_D12", "GPIO146_D13"; + ste,config = <&gpio_out_lo>; + }; + hrefv60_cfg2 { + ste,pins = "GPIO67_G2"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + mcde { + lcd_hrefv60_mode: lcd_hrefv60 { + /* + * Display Interface 1 uses GPIO 65 for RST (reset). + * Display Interface 2 uses GPIO 66 for RST (reset). + * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) + */ + hrefv60_cfg1 { + ste,pins ="GPIO65_F1"; + ste,config = <&gpio_out_hi>; + }; + hrefv60_cfg2 { + ste,pins ="GPIO66_G3"; + ste,config = <&gpio_out_lo>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi index efddee9..e6f22b2 100644 --- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi @@ -31,17 +31,57 @@ ste,output = <OUTPUT_LOW>; }; + gpio_in_pu: gpio_input_pull_up { + ste,gpio = <GPIOMODE_ENABLED>; + ste,input = <INPUT_PULLUP>; + }; + + gpio_in_pd: gpio_input_pull_down { + ste,gpio = <GPIOMODE_ENABLED>; + ste,input = <INPUT_PULLDOWN>; + }; + gpio_out_lo: gpio_output_low { ste,gpio = <GPIOMODE_ENABLED>; ste,output = <OUTPUT_LOW>; }; + gpio_out_hi: gpio_output_high { + ste,gpio = <GPIOMODE_ENABLED>; + ste,output = <OUTPUT_HIGH>; + }; + + slpm_pdis: slpm_pdis { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; + }; + + slpm_wkup_pdis: slpm_wkup_pdis { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; + }; + + slpm_wkup_pdis_en: slpm_wkup_pdis_en { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>; + }; + slpm_in_pu: slpm_in_pu { ste,sleep = <SLPM_ENABLED>; ste,sleep-input = <SLPM_INPUT_PULLUP>; ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; }; + slpm_in_pdis: slpm_in_pdis { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-input = <SLPM_DIR_INPUT>; + ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; + }; + slpm_in_wkup_pdis: slpm_in_wkup_pdis { ste,sleep = <SLPM_ENABLED>; ste,sleep-input = <SLPM_DIR_INPUT>; @@ -49,6 +89,20 @@ ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; }; + slpm_in_wkup_pdis_en: slpm_in_wkup_pdis_en { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-input = <SLPM_DIR_INPUT>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>; + }; + + slpm_in_pu_wkup_pdis_en: slpm_in_wkup_pdis_en { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-input = <SLPM_INPUT_PULLUP>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>; + }; + slpm_out_lo: slpm_out_lo { ste,sleep = <SLPM_ENABLED>; ste,sleep-output = <SLPM_OUTPUT_LOW>; @@ -68,6 +122,20 @@ ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; }; + slpm_out_lo_pdis: slpm_out_lo_pdis { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-output = <SLPM_OUTPUT_LOW>; + ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; + }; + + slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-output = <SLPM_OUTPUT_LOW>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; + }; + slpm_out_wkup_pdis: slpm_out_wkup_pdis { ste,sleep = <SLPM_ENABLED>; ste,sleep-output = <SLPM_DIR_OUTPUT>; @@ -81,6 +149,18 @@ ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; }; + in_wkup_pdis_en: in_wkup_pdis_en { + ste,sleep-input = <SLPM_DIR_INPUT>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>; + }; + + out_lo_wkup_pdis: out_lo_wkup_pdis { + ste,sleep-output = <SLPM_OUTPUT_LOW>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; + }; + out_hi_wkup_pdis: out_hi_wkup_pdis { ste,sleep-output = <SLPM_OUTPUT_HIGH>; ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts index 16c3888..f557feb 100644 --- a/arch/arm/boot/dts/ste-nomadik-s8815.dts +++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts @@ -67,10 +67,6 @@ /* Custom board node with GPIO pins to active etc */ usb-s8815 { - /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */ - ethernet-gpio { - gpios = <&gpio3 8 0x1>; - }; /* This will bias the MMC/SD card detect line */ mmcsd-gpio { gpios = <&gpio3 16 0x1>; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 79425e3..5acc044 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -769,14 +769,14 @@ #size-cells = <1>; ranges; - vica: intc@0x10140000 { + vica: intc@10140000 { compatible = "arm,versatile-vic"; interrupt-controller; #interrupt-cells = <1>; reg = <0x10140000 0x20>; }; - vicb: intc@0x10140020 { + vicb: intc@10140020 { compatible = "arm,versatile-vic"; interrupt-controller; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index f0b39f8..97d5d21 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "ste-dbx5x0.dtsi" +#include "ste-href-family-pinctrl.dtsi" / { model = "Calao Systems Snowball platform with device tree"; @@ -75,6 +76,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpioled_snowball_mode>; used-led { label = "user_led"; gpios = <&gpio4 14 0x4>; @@ -84,6 +87,11 @@ }; soc { + usb_per5@a03e0000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&musb_default_mode>; + pinctrl-1 = <&musb_sleep_mode>; + }; sound { compatible = "stericsson,snd-soc-mop500"; @@ -92,7 +100,21 @@ stericsson,audio-codec = <&codec>; }; + msp0: msp@80123000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp0_default_mode>; + status = "okay"; + }; + msp1: msp@80124000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp1_default_mode>; + status = "okay"; + }; + + msp2: msp@80117000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp2_default_mode>; status = "okay"; }; @@ -110,6 +132,8 @@ interrupt-parent = <&gpio4>; vdd33a-supply = <&en_3v3_reg>; vddvario-supply = <&db8500_vape_reg>; + pinctrl-names = "default"; + pinctrl-0 = <ð_snowball_mode>; reg-shift = <1>; reg-io-width = <2>; @@ -122,10 +146,8 @@ }; vmmci: regulator-gpio { - gpios = <&gpio6 25 0x4>; - enable-gpio = <&gpio7 4 0x4>; - - status = "okay"; + gpios = <&gpio7 4 0x4>; + enable-gpio = <&gpio6 25 0x4>; }; // External Micro SD slot @@ -136,6 +158,9 @@ mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; vqmmc-supply = <&vmmci>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi0_default_mode>; + pinctrl-1 = <&sdi0_sleep_mode>; cd-gpios = <&gpio6 26 0x4>; // 218 cd-inverted; @@ -143,6 +168,27 @@ status = "okay"; }; + // WLAN SDIO channel + sdi1_per2@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi1_default_mode>; + pinctrl-1 = <&sdi1_sleep_mode>; + + status = "okay"; + }; + + // Unused PoP eMMC - register and put it to sleep by default */ + sdi2_per3@80005000 { + arm,primecell-periphid = <0x10480180>; + pinctrl-names = "default"; + pinctrl-0 = <&sdi2_sleep_mode>; + + status = "okay"; + }; + // On-board eMMC sdi4_per2@80114000 { arm,primecell-periphid = <0x10480180>; @@ -150,22 +196,63 @@ bus-width = <8>; mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux2_reg>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi4_default_mode>; + pinctrl-1 = <&sdi4_sleep_mode>; status = "okay"; }; uart@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart0_default_mode>; + pinctrl-1 = <&uart0_sleep_mode>; status = "okay"; }; uart@80121000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_default_mode>; + pinctrl-1 = <&uart1_sleep_mode>; status = "okay"; }; uart@80007000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart2_default_mode>; + pinctrl-1 = <&uart2_sleep_mode>; status = "okay"; }; + i2c@80004000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c0_default_mode>; + pinctrl-1 = <&i2c0_sleep_mode>; + }; + + i2c@80122000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c1_default_mode>; + pinctrl-1 = <&i2c1_sleep_mode>; + }; + + i2c@80128000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c2_default_mode>; + pinctrl-1 = <&i2c2_sleep_mode>; + }; + + i2c@80110000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c3_default_mode>; + pinctrl-1 = <&i2c3_sleep_mode>; + }; + + ssp@80002000 { + pinctrl-names = "default"; + pinctrl-0 = <&ssp0_snowball_mode>; + }; + cpufreq-cooling { status = "okay"; }; @@ -266,5 +353,141 @@ }; }; }; + + pinctrl { + /* + * Set this up using hogs, as time goes by and as seems fit, these + * can be moved over to being controlled by respective device. + */ + pinctrl-names = "default"; + pinctrl-0 = <&accel_snowball_mode>, + <&magneto_snowball_mode>, + <&gbf_snowball_mode>, + <&wlan_snowball_mode>; + + ethernet { + /* + * Mux in "SM" which is used for the + * SMSC911x Ethernet adapter + */ + eth_snowball_mode: eth_snowball { + snowball_mux { + ste,function = "sm"; + ste,pins = "sm_b_1"; + }; + /* LAN IRQ pin */ + snowball_cfg1 { + ste,pins = "GPIO140_B11"; + ste,config = <&in_nopull>; + }; + /* LAN reset pin */ + snowball_cfg2 { + ste,pins = "GPIO141_C12"; + ste,config = <&gpio_out_hi>; + }; + + }; + }; + sdi0 { + sdi0_default_mode: sdi0_default { + snowball_mux { + ste,function = "mc0"; + ste,pins = "mc0dat31dir_a_1"; + }; + snowball_cfg1 { + ste,pins = "GPIO21_AB3"; /* DAT31DIR */ + ste,config = <&out_hi>; + }; + + }; + }; + ssp0 { + ssp0_snowball_mode: ssp0_snowball_default { + snowball_mux { + ste,function = "ssp0"; + ste,pins = "ssp0_a_1"; + }; + snowball_cfg1 { + ste,pins = "GPIO144_B13"; /* FRM */ + ste,config = <&gpio_out_hi>; + }; + snowball_cfg2 { + ste,pins = "GPIO145_C13"; /* RXD */ + ste,config = <&in_pd>; + }; + snowball_cfg3 { + ste,pins = + "GPIO146_D13", /* TXD */ + "GPIO143_D12"; /* CLK */ + ste,config = <&out_lo>; + }; + + }; + }; + gpio_led { + gpioled_snowball_mode: gpioled_default { + snowball_cfg1 { + ste,pins = "GPIO142_C11"; + ste,config = <&gpio_out_hi>; + }; + + }; + }; + accelerometer { + accel_snowball_mode: accel_snowball { + /* Accelerometer lines */ + snowball_cfg1 { + ste,pins = + "GPIO163_C20", /* ACCEL_IRQ1 */ + "GPIO164_B21"; /* ACCEL_IRQ2 */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + magnetometer { + magneto_snowball_mode: magneto_snowball { + snowball_cfg1 { + ste,pins = "GPIO165_C21"; /* MAG_DRDY */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + gbf { + gbf_snowball_mode: gbf_snowball { + /* + * GBF (GPS, Bluetooth, FM-radio) interface, + * pull low to reset state + */ + snowball_cfg1 { + ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + wlan { + wlan_snowball_mode: wlan_snowball { + /* + * Activate this mode with the WLAN chip. + * These are plain GPIO pins used by WLAN + */ + snowball_cfg1 { + ste,pins = + "GPIO161_D21", /* WLAN_PMU_EN */ + "GPIO215_AH13"; /* WLAN_ENA */ + ste,config = <&gpio_out_lo>; + }; + snowball_cfg2 { + ste,pins = "GPIO216_AG12"; /* WLAN_IRQ */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + }; + + mcde@a0350000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_default_mode>; + pinctrl-1 = <&lcd_sleep_mode>; + }; }; }; diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts index 8a1032c..a9da480 100644 --- a/arch/arm/boot/dts/ste-u300.dts +++ b/arch/arm/boot/dts/ste-u300.dts @@ -307,7 +307,7 @@ clocks = <&i2c0_clk>; #address-cells = <1>; #size-cells = <0>; - ab3100: ab3100@0x48 { + ab3100: ab3100@48 { compatible = "stericsson,ab3100"; reg = <0x48>; interrupt-parent = <&vica>; @@ -385,10 +385,10 @@ clocks = <&i2c1_clk>; #address-cells = <1>; #size-cells = <0>; - fwcam0: fwcam@0x10 { + fwcam0: fwcam@10 { reg = <0x10>; }; - fwcam1: fwcam@0x5d { + fwcam1: fwcam@5d { reg = <0x5d>; }; }; diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index 1d322b2..e56449d 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -86,6 +86,24 @@ }; }; }; + + sbc_i2c0 { + pinctrl_sbc_i2c0_default: sbc_i2c0-default { + st,pins { + sda = <&PIO4 6 ALT1 BIDIR>; + scl = <&PIO4 5 ALT1 BIDIR>; + }; + }; + }; + + sbc_i2c1 { + pinctrl_sbc_i2c1_default: sbc_i2c1-default { + st,pins { + sda = <&PIO3 2 ALT2 BIDIR>; + scl = <&PIO3 1 ALT2 BIDIR>; + }; + }; + }; }; pin-controller-front { @@ -143,6 +161,24 @@ reg = <0x7000 0x100>; st,bank-name = "PIO12"; }; + + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&PIO9 3 ALT1 BIDIR>; + scl = <&PIO9 2 ALT1 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&PIO12 1 ALT1 BIDIR>; + scl = <&PIO12 0 ALT1 BIDIR>; + }; + }; + }; }; pin-controller-rear { diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index 74ab8de..d9c7dd1 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi @@ -9,6 +9,7 @@ #include "stih41x.dtsi" #include "stih415-clock.dtsi" #include "stih415-pinctrl.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> / { L2: cache-controller { @@ -83,5 +84,57 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; }; + + i2c@fed40000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfed40000 0x110>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + status = "disabled"; + }; + + i2c@fed41000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfed41000 0x110>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + + status = "disabled"; + }; + + i2c@fe540000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfe540000 0x110>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c0_default>; + + status = "disabled"; + }; + + i2c@fe541000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfe541000 0x110>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c1_default>; + + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index 0f246c9..b29ff4b 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -97,6 +97,24 @@ }; }; }; + + sbc_i2c0 { + pinctrl_sbc_i2c0_default: sbc_i2c0-default { + st,pins { + sda = <&PIO4 6 ALT1 BIDIR>; + scl = <&PIO4 5 ALT1 BIDIR>; + }; + }; + }; + + sbc_i2c1 { + pinctrl_sbc_i2c1_default: sbc_i2c1-default { + st,pins { + sda = <&PIO3 2 ALT2 BIDIR>; + scl = <&PIO3 1 ALT2 BIDIR>; + }; + }; + }; }; pin-controller-front { @@ -175,6 +193,23 @@ }; }; + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&PIO9 3 ALT1 BIDIR>; + scl = <&PIO9 2 ALT1 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&PIO12 1 ALT1 BIDIR>; + scl = <&PIO12 0 ALT1 BIDIR>; + }; + }; + }; }; pin-controller-rear { diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 1a0326e..b7ab47b 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -9,6 +9,7 @@ #include "stih41x.dtsi" #include "stih416-clock.dtsi" #include "stih416-pinctrl.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> / { L2: cache-controller { compatible = "arm,pl310-cache"; @@ -92,5 +93,57 @@ pinctrl-0 = <&pinctrl_sbc_serial1>; clocks = <&CLK_SYSIN>; }; + + i2c@fed40000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfed40000 0x110>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&CLK_S_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + status = "disabled"; + }; + + i2c@fed41000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfed41000 0x110>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&CLK_S_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + + status = "disabled"; + }; + + i2c@fe540000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfe540000 0x110>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c0_default>; + + status = "disabled"; + }; + + i2c@fe541000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfe541000 0x110>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c1_default>; + + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi index 8e694d2..1e6aa92 100644 --- a/arch/arm/boot/dts/stih41x-b2000.dtsi +++ b/arch/arm/boot/dts/stih41x-b2000.dtsi @@ -37,5 +37,14 @@ }; }; + /* HDMI Tx I2C */ + i2c@fed41000 { + /* HDMI V1.3a supports Standard mode only */ + clock-frequency = <100000>; + i2c-min-scl-pulse-width-us = <0>; + i2c-min-sda-pulse-width-us = <5>; + + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi index 133e181..0ef0a69 100644 --- a/arch/arm/boot/dts/stih41x-b2020.dtsi +++ b/arch/arm/boot/dts/stih41x-b2020.dtsi @@ -38,5 +38,27 @@ default-state = "off"; }; }; + + i2c@fed40000 { + status = "okay"; + }; + + /* HDMI Tx I2C */ + i2c@fed41000 { + /* HDMI V1.3a supports Standard mode only */ + clock-frequency = <100000>; + i2c-min-scl-pulse-width-us = <0>; + i2c-min-sda-pulse-width-us = <5>; + + status = "okay"; + }; + + i2c@fe540000 { + status = "okay"; + }; + + i2c@fe541000 { + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index eb4d73b..d4b081d 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -18,10 +18,6 @@ model = "Mele A1000"; compatible = "mele,a1000", "allwinner,sun4i-a10"; - aliases { - serial0 = &uart0; - }; - soc@01c00000 { emac: ethernet@01c0b000 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 425a7db..b139ee6 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -17,15 +17,6 @@ model = "Cubietech Cubieboard"; compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10"; - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - bootargs = "earlyprintk console=ttyS0,115200"; - }; - soc@01c00000 { emac: ethernet@01c0b000 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index b3ae51f..3a1595f 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -18,10 +18,6 @@ model = "Miniand Hackberry"; compatible = "miniand,hackberry", "allwinner,sun4i-a10"; - chosen { - bootargs = "earlyprintk console=ttyS0,115200"; - }; - soc@01c00000 { emac: ethernet@01c0b000 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index 0c1447c..70b3323 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -18,10 +18,6 @@ model = "PineRiver Mini X-Plus"; compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; - chosen { - bootargs = "earlyprintk console=ttyS0,115200"; - }; - soc@01c00000 { uart0: serial@01c28000 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 319cc6b..040bb0e 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -15,6 +15,12 @@ / { interrupt-parent = <&intc>; + aliases { + ethernet0 = &emac; + serial0 = &uart0; + serial1 = &uart1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -66,6 +72,29 @@ clocks = <&osc24M>; }; + pll4: pll4@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + + pll5: pll5@01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: pll6@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; @@ -131,12 +160,11 @@ "apb0_ir1", "apb0_keypad"; }; - /* dummy is pll62 */ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&dummy>, <&osc32k>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; }; apb1: apb1@01c20058 { @@ -158,6 +186,126 @@ "apb1_uart4", "apb1_uart5", "apb1_uart6", "apb1_uart7"; }; + + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + ms_clk: clk@01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ms"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc2"; + }; + + mmc3_clk: clk@01c20094 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20094 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc3"; + }; + + ts_clk: clk@01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ts"; + }; + + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ss"; + }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi2"; + }; + + pata_clk: clk@01c200ac { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200ac 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "pata"; + }; + + ir0_clk: clk@01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir0"; + }; + + ir1_clk: clk@01c200b4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir1"; + }; + + spi3_clk: clk@01c200d4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200d4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi3"; + }; }; soc@01c00000 { @@ -266,11 +414,23 @@ reg = <0x01c20c90 0x10>; }; + rtc: rtc@01c20d00 { + compatible = "allwinner,sun4i-rtc"; + reg = <0x01c20d00 0x20>; + interrupts = <24>; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun4i-sid"; reg = <0x01c23800 0x10>; }; + rtp: rtp@01c25000 { + compatible = "allwinner,sun4i-ts"; + reg = <0x01c25000 0x100>; + interrupts = <29>; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index e674c94..ea16054 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -16,6 +16,10 @@ / { interrupt-parent = <&intc>; + aliases { + ethernet0 = &emac; + }; + cpus { cpu@0 { compatible = "arm,cortex-a8"; @@ -63,6 +67,29 @@ clocks = <&osc24M>; }; + pll4: pll4@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + + pll5: pll5@01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: pll6@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; @@ -123,12 +150,11 @@ "apb0_ir", "apb0_keypad"; }; - /* dummy is pll62 */ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&dummy>, <&osc32k>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; }; apb1: apb1@01c20058 { @@ -147,6 +173,102 @@ "apb1_i2c2", "apb1_uart0", "apb1_uart1", "apb1_uart2", "apb1_uart3"; }; + + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + ms_clk: clk@01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ms"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc2"; + }; + + ts_clk: clk@01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ts"; + }; + + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ss"; + }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi2"; + }; + + ir0_clk: clk@01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir0"; + }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mbus"; + }; }; soc@01c00000 { @@ -260,6 +382,12 @@ reg = <0x01c23800 0x10>; }; + rtp: rtp@01c25000 { + compatible = "allwinner,sun4i-ts"; + reg = <0x01c25000 0x100>; + interrupts = <29>; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts new file mode 100644 index 0000000..fe2ce0a --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -0,0 +1,68 @@ +/* + * Copyright 2012 Maxime Ripard + * Copyright 2013 Hans de Goede <hdegoede@redhat.com> + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun5i-a13.dtsi" + +/ { + model = "Olimex A13-Olinuxino Micro"; + compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; + + soc@01c00000 { + pinctrl@01c20800 { + led_pins_olinuxinom: led_pins@0 { + allwinner,pins = "PG9"; + allwinner,function = "gpio_out"; + allwinner,drive = <1>; + allwinner,pull = <0>; + }; + }; + + uart1: serial@01c28400 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinom>; + + power { + label = "a13-olinuxino-micro:green:power"; + gpios = <&pio 6 9 0>; + default-state = "on"; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 9e508dc..a4ba5ff 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -18,10 +18,6 @@ model = "Olimex A13-Olinuxino"; compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; - chosen { - bootargs = "earlyprintk console=ttyS0,115200"; - }; - soc@01c00000 { pinctrl@01c20800 { led_pins_olinuxino: led_pins@0 { diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 1ccd75d..320335a 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -67,6 +67,29 @@ clocks = <&osc24M>; }; + pll4: pll4@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + + pll5: pll5@01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: pll6@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; @@ -125,12 +148,11 @@ clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; }; - /* dummy is pll6 */ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&dummy>, <&osc32k>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; }; apb1: apb1@01c20058 { @@ -148,6 +170,102 @@ clock-output-names = "apb1_i2c0", "apb1_i2c1", "apb1_i2c2", "apb1_uart1", "apb1_uart3"; }; + + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + ms_clk: clk@01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ms"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc2"; + }; + + ts_clk: clk@01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ts"; + }; + + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ss"; + }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi2"; + }; + + ir0_clk: clk@01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir0"; + }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mbus"; + }; }; soc@01c00000 { @@ -227,6 +345,12 @@ reg = <0x01c23800 0x10>; }; + rtp: rtp@01c25000 { + compatible = "allwinner,sun4i-ts"; + reg = <0x01c25000 0x100>; + interrupts = <29>; + }; + uart1: serial@01c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 7f5878c..5256ad9 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -212,6 +212,24 @@ }; }; + ahb1_rst: reset@01c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-ahb1-reset"; + reg = <0x01c202c0 0xc>; + }; + + apb1_rst: reset@01c202d0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d0 0x4>; + }; + + apb2_rst: reset@01c202d8 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d8 0x4>; + }; + timer@01c20c00 { compatible = "allwinner,sun4i-timer"; reg = <0x01c20c00 0xa0>; @@ -235,6 +253,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 16>; + resets = <&apb2_rst 16>; status = "disabled"; }; @@ -245,6 +264,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 17>; + resets = <&apb2_rst 17>; status = "disabled"; }; @@ -255,6 +275,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 18>; + resets = <&apb2_rst 18>; status = "disabled"; }; @@ -265,6 +286,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 19>; + resets = <&apb2_rst 19>; status = "disabled"; }; @@ -275,6 +297,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 20>; + resets = <&apb2_rst 20>; status = "disabled"; }; @@ -285,6 +308,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 21>; + resets = <&apb2_rst 21>; status = "disabled"; }; @@ -298,5 +322,15 @@ #interrupt-cells = <3>; interrupts = <1 9 0xf04>; }; + + cpucfg@01f01c00 { + compatible = "allwinner,sun6i-a31-cpuconfig"; + reg = <0x01f01c00 0x300>; + }; + + prcm@01f01c00 { + compatible = "allwinner,sun6i-a31-prcm"; + reg = <0x01f01400 0x200>; + }; }; }; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 8a1009d..f9dcb61 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -33,6 +33,24 @@ pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; }; leds { diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 0135039..119f066 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -16,6 +16,10 @@ / { interrupt-parent = <&gic>; + aliases { + ethernet0 = &emac; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -49,10 +53,11 @@ clock-frequency = <24000000>; }; - osc32k: osc32k { + osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-output-names = "osc32k"; }; pll1: pll1@01c20000 { @@ -62,23 +67,34 @@ clocks = <&osc24M>; }; - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - pll6: pll6 { + pll4: pll4@01c20018 { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + + pll5: pll5@01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: pll6@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; }; cpu: cpu@01c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-cpu-clk"; reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; }; axi: axi@01c20054 { @@ -137,7 +153,7 @@ #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6>, <&osc32k>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; }; apb1: apb1@01c20058 { @@ -159,6 +175,162 @@ "apb1_uart2", "apb1_uart3", "apb1_uart4", "apb1_uart5", "apb1_uart6", "apb1_uart7"; }; + + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + ms_clk: clk@01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ms"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc2"; + }; + + mmc3_clk: clk@01c20094 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20094 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc3"; + }; + + ts_clk: clk@01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ts"; + }; + + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ss"; + }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi2"; + }; + + pata_clk: clk@01c200ac { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200ac 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "pata"; + }; + + ir0_clk: clk@01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir0"; + }; + + ir1_clk: clk@01c200b4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir1"; + }; + + spi3_clk: clk@01c200d4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200d4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi3"; + }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; + clock-output-names = "mbus"; + }; + + /* + * Dummy clock used by output clocks + */ + osc24M_32k: clk@1 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <750>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "osc24M_32k"; + }; + + clk_out_a: clk@01c201f0 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-out-clk"; + reg = <0x01c201f0 0x4>; + clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; + clock-output-names = "clk_out_a"; + }; + + clk_out_b: clk@01c201f4 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-out-clk"; + reg = <0x01c201f4 0x4>; + clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; + clock-output-names = "clk_out_b"; + }; }; soc@01c00000 { @@ -246,6 +418,20 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + clk_out_a_pins_a: clk_out_a@0 { + allwinner,pins = "PI12"; + allwinner,function = "clk_out_a"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + clk_out_b_pins_a: clk_out_b@0 { + allwinner,pins = "PI13"; + allwinner,function = "clk_out_b"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { @@ -265,11 +451,23 @@ reg = <0x01c20c90 0x10>; }; + rtc: rtc@01c20d00 { + compatible = "allwinner,sun7i-a20-rtc"; + reg = <0x01c20d00 0x20>; + interrupts = <0 24 1>; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; }; + rtp: rtp@01c25000 { + compatible = "allwinner,sun4i-ts"; + reg = <0x01c25000 0x100>; + interrupts = <0 29 4>; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index cb5ec23..73aecfb 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -7,11 +7,42 @@ model = "NVIDIA Tegra114 Dalmore evaluation board"; compatible = "nvidia,dalmore", "nvidia,tegra114"; + aliases { + rtc0 = "/i2c@7000d000/tps65913@58"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x80000000 0x40000000>; }; - pinmux { + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&vdd_hdmi_reg>; + pll-supply = <&palmas_smps3_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + + dsi@54300000 { + status = "okay"; + + panel@0 { + compatible = "panasonic,vvx10f004b00", + "simple-panel"; + reg = <0>; + + power-supply = <&avdd_lcd_reg>; + backlight = <&backlight>; + }; + }; + }; + + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -19,41 +50,41 @@ clk1_out_pw4 { nvidia,pins = "clk1_out_pw4"; nvidia,function = "extperiph1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; dap1_din_pn1 { nvidia,pins = "dap1_din_pn1"; nvidia,function = "i2s0"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; dap1_dout_pn2 { nvidia,pins = "dap1_dout_pn2", "dap1_fs_pn0", "dap1_sclk_pn3"; nvidia,function = "i2s0"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; dap2_din_pa4 { nvidia,pins = "dap2_din_pa4"; nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; dap2_dout_pa5 { nvidia,pins = "dap2_dout_pa5", "dap2_fs_pa2", "dap2_sclk_pa3"; nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; dap4_din_pp5 { nvidia,pins = "dap4_din_pp5", @@ -61,17 +92,17 @@ "dap4_fs_pp4", "dap4_sclk_pp7"; nvidia,function = "i2s3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; dvfs_pwm_px0 { nvidia,pins = "dvfs_pwm_px0", "dvfs_clk_px2"; nvidia,function = "cldvfs"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; ulpi_clk_py0 { nvidia,pins = "ulpi_clk_py0", @@ -84,128 +115,128 @@ "ulpi_data6_po7", "ulpi_data7_po0"; nvidia,function = "ulpi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; ulpi_dir_py1 { nvidia,pins = "ulpi_dir_py1", "ulpi_nxt_py2"; nvidia,function = "ulpi"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; ulpi_stp_py3 { nvidia,pins = "ulpi_stp_py3"; nvidia,function = "ulpi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; cam_i2c_scl_pbb1 { nvidia,pins = "cam_i2c_scl_pbb1", "cam_i2c_sda_pbb2"; nvidia,function = "i2c3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; }; cam_mclk_pcc0 { nvidia,pins = "cam_mclk_pcc0", "pbb0"; nvidia,function = "vi_alt3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - nvidia,lock = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; }; gen2_i2c_scl_pt5 { nvidia,pins = "gen2_i2c_scl_pt5", "gen2_i2c_sda_pt6"; nvidia,function = "i2c2"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; }; gmi_a16_pj7 { nvidia,pins = "gmi_a16_pj7"; nvidia,function = "uartd"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; gmi_a17_pb0 { nvidia,pins = "gmi_a17_pb0", "gmi_a18_pb1"; nvidia,function = "uartd"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; gmi_a19_pk7 { nvidia,pins = "gmi_a19_pk7"; nvidia,function = "uartd"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; gmi_ad5_pg5 { nvidia,pins = "gmi_ad5_pg5", "gmi_cs6_n_pi3", "gmi_wr_n_pi0"; nvidia,function = "spi4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; gmi_ad6_pg6 { nvidia,pins = "gmi_ad6_pg6", "gmi_ad7_pg7"; nvidia,function = "spi4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; gmi_ad12_ph4 { nvidia,pins = "gmi_ad12_ph4"; nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; gmi_ad9_ph1 { nvidia,pins = "gmi_ad9_ph1"; nvidia,function = "pwm1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; gmi_cs1_n_pj2 { nvidia,pins = "gmi_cs1_n_pj2", "gmi_oe_n_pi1"; nvidia,function = "soc"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; clk2_out_pw5 { nvidia,pins = "clk2_out_pw5"; nvidia,function = "extperiph2"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; sdmmc1_clk_pz0 { nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; sdmmc1_cmd_pz1 { nvidia,pins = "sdmmc1_cmd_pz1", @@ -214,23 +245,23 @@ "sdmmc1_dat2_py5", "sdmmc1_dat3_py4"; nvidia,function = "sdmmc1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; sdmmc1_wp_n_pv3 { nvidia,pins = "sdmmc1_wp_n_pv3"; nvidia,function = "spi4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; sdmmc3_cmd_pa7 { nvidia,pins = "sdmmc3_cmd_pa7", @@ -242,16 +273,16 @@ "sdmmc3_clk_lb_out_pee4", "sdmmc3_clk_lb_in_pee5"; nvidia,function = "sdmmc3"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; sdmmc4_clk_pcc4 { nvidia,pins = "sdmmc4_clk_pcc4"; nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; sdmmc4_cmd_pt7 { nvidia,pins = "sdmmc4_cmd_pt7", @@ -264,16 +295,16 @@ "sdmmc4_dat6_paa6", "sdmmc4_dat7_paa7"; nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; clk_32k_out_pa0 { nvidia,pins = "clk_32k_out_pa0"; nvidia,function = "blink"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; kb_col0_pq0 { nvidia,pins = "kb_col0_pq0", @@ -283,265 +314,265 @@ "kb_row1_pr1", "kb_row2_pr2"; nvidia,function = "kbc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; dap3_din_pp1 { nvidia,pins = "dap3_din_pp1", "dap3_sclk_pp3"; nvidia,function = "displayb"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; pv0 { nvidia,pins = "pv0"; nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; kb_row7_pr7 { nvidia,pins = "kb_row7_pr7"; nvidia,function = "rsvd2"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; kb_row10_ps2 { nvidia,pins = "kb_row10_ps2"; nvidia,function = "uarta"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; kb_row9_ps1 { nvidia,pins = "kb_row9_ps1"; nvidia,function = "uarta"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; pwr_i2c_scl_pz6 { nvidia,pins = "pwr_i2c_scl_pz6", "pwr_i2c_sda_pz7"; nvidia,function = "i2cpwr"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; }; sys_clk_req_pz5 { nvidia,pins = "sys_clk_req_pz5"; nvidia,function = "sysclk"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; core_pwr_req { nvidia,pins = "core_pwr_req"; nvidia,function = "pwron"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; cpu_pwr_req { nvidia,pins = "cpu_pwr_req"; nvidia,function = "cpu"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; pwr_int_n { nvidia,pins = "pwr_int_n"; nvidia,function = "pmi"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; reset_out_n { nvidia,pins = "reset_out_n"; nvidia,function = "reset_out_n"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; clk3_out_pee0 { nvidia,pins = "clk3_out_pee0"; nvidia,function = "extperiph3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; gen1_i2c_scl_pc4 { nvidia,pins = "gen1_i2c_scl_pc4", "gen1_i2c_sda_pc5"; nvidia,function = "i2c1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; }; uart2_cts_n_pj5 { nvidia,pins = "uart2_cts_n_pj5"; nvidia,function = "uartb"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; uart2_rts_n_pj6 { nvidia,pins = "uart2_rts_n_pj6"; nvidia,function = "uartb"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; uart2_rxd_pc3 { nvidia,pins = "uart2_rxd_pc3"; nvidia,function = "irda"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; uart2_txd_pc2 { nvidia,pins = "uart2_txd_pc2"; nvidia,function = "irda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; uart3_cts_n_pa1 { nvidia,pins = "uart3_cts_n_pa1", "uart3_rxd_pw7"; nvidia,function = "uartc"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; uart3_rts_n_pc0 { nvidia,pins = "uart3_rts_n_pc0", "uart3_txd_pw6"; nvidia,function = "uartc"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; owr { nvidia,pins = "owr"; nvidia,function = "owr"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; hdmi_cec_pee3 { nvidia,pins = "hdmi_cec_pee3"; nvidia,function = "cec"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; }; ddc_scl_pv4 { nvidia,pins = "ddc_scl_pv4", "ddc_sda_pv5"; nvidia,function = "i2c4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,rcv-sel = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; }; spdif_in_pk6 { nvidia,pins = "spdif_in_pk6"; nvidia,function = "usb"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; }; usb_vbus_en0_pn4 { nvidia,pins = "usb_vbus_en0_pn4"; nvidia,function = "usb"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; }; gpio_x6_aud_px6 { nvidia,pins = "gpio_x6_aud_px6"; nvidia,function = "spi6"; - nvidia,pull = <2>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; gpio_x4_aud_px4 { nvidia,pins = "gpio_x4_aud_px4", "gpio_x7_aud_px7"; nvidia,function = "rsvd1"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; gpio_x5_aud_px5 { nvidia,pins = "gpio_x5_aud_px5"; nvidia,function = "rsvd1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; gpio_w2_aud_pw2 { nvidia,pins = "gpio_w2_aud_pw2"; nvidia,function = "rsvd2"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; gpio_w3_aud_pw3 { nvidia,pins = "gpio_w3_aud_pw3"; nvidia,function = "spi6"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; gpio_x1_aud_px1 { nvidia,pins = "gpio_x1_aud_px1"; nvidia,function = "rsvd4"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; gpio_x3_aud_px3 { nvidia,pins = "gpio_x3_aud_px3"; nvidia,function = "rsvd4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; dap3_fs_pp0 { nvidia,pins = "dap3_fs_pp0"; nvidia,function = "i2s2"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; dap3_dout_pp2 { nvidia,pins = "dap3_dout_pp2"; nvidia,function = "i2s2"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; pv1 { nvidia,pins = "pv1"; nvidia,function = "rsvd1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; pbb3 { nvidia,pins = "pbb3", @@ -549,25 +580,25 @@ "pbb6", "pbb7"; nvidia,function = "rsvd4"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; pcc1 { nvidia,pins = "pcc1", "pcc2"; nvidia,function = "rsvd4"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; gmi_ad0_pg0 { nvidia,pins = "gmi_ad0_pg0", "gmi_ad1_pg1"; nvidia,function = "gmi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; gmi_ad10_ph2 { nvidia,pins = "gmi_ad10_ph2", @@ -576,17 +607,17 @@ "gmi_ad8_ph0", "gmi_clk_pk1"; nvidia,function = "gmi"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; gmi_ad2_pg2 { nvidia,pins = "gmi_ad2_pg2", "gmi_ad3_pg3"; nvidia,function = "gmi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; gmi_adv_n_pk0 { nvidia,pins = "gmi_adv_n_pk0", @@ -598,39 +629,39 @@ "gmi_iordy_pi5", "gmi_wp_n_pc7"; nvidia,function = "gmi"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; gmi_cs3_n_pk4 { nvidia,pins = "gmi_cs3_n_pk4"; nvidia,function = "gmi"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; clk2_req_pcc5 { nvidia,pins = "clk2_req_pcc5"; nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; kb_col3_pq3 { nvidia,pins = "kb_col3_pq3", "kb_col6_pq6", "kb_col7_pq7"; nvidia,function = "kbc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; kb_col5_pq5 { nvidia,pins = "kb_col5_pq5"; nvidia,function = "kbc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; kb_row3_pr3 { nvidia,pins = "kb_row3_pr3", @@ -638,77 +669,77 @@ "kb_row6_pr6", "kb_row8_ps0"; nvidia,function = "kbc"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; clk3_req_pee1 { nvidia,pins = "clk3_req_pee1"; nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; pu4 { nvidia,pins = "pu4"; nvidia,function = "displayb"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; pu5 { nvidia,pins = "pu5", "pu6"; nvidia,function = "displayb"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; hdmi_int_pn7 { nvidia,pins = "hdmi_int_pn7"; nvidia,function = "rsvd1"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; clk1_req_pee2 { nvidia,pins = "clk1_req_pee2", "usb_vbus_en1_pn5"; nvidia,function = "rsvd4"; - nvidia,pull = <1>; - nvidia,tristate = <1>; - nvidia,enable-input = <0>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; drive_sdio1 { nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <1>; - nvidia,schmitt = <0>; - nvidia,low-power-mode = <3>; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; nvidia,pull-down-strength = <36>; nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = <2>; - nvidia,slew-rate-falling = <2>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; }; drive_sdio3 { nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <1>; - nvidia,schmitt = <0>; - nvidia,low-power-mode = <3>; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; nvidia,pull-down-strength = <22>; nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = <0>; - nvidia,slew-rate-falling = <0>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; }; drive_gma { nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = <1>; - nvidia,schmitt = <0>; - nvidia,low-power-mode = <3>; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; nvidia,pull-down-strength = <2>; nvidia,pull-up-strength = <1>; - nvidia,slew-rate-rising = <0>; - nvidia,slew-rate-falling = <0>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; nvidia,drive-type = <1>; }; }; @@ -718,11 +749,15 @@ status = "okay"; }; + pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { status = "okay"; clock-frequency = <100000>; - battery: smart-battery { + battery: smart-battery@b { compatible = "ti,bq20z45", "sbs,sbs-battery"; reg = <0xb>; battery-name = "battery"; @@ -731,7 +766,7 @@ power-supplies = <&charger>; }; - rt5640: rt5640 { + rt5640: rt5640@1c { compatible = "realtek,rt5640"; reg = <0x1c>; interrupt-parent = <&gpio>; @@ -749,11 +784,15 @@ }; }; + hdmi_ddc: i2c@7000c700 { + status = "okay"; + }; + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; - tps51632 { + tps51632@43 { compatible = "ti,tps51632"; reg = <0x43>; regulator-name = "vdd-cpu"; @@ -763,7 +802,7 @@ regulator-always-on; }; - tps65090 { + tps65090@48 { compatible = "ti,tps65090"; reg = <0x48>; interrupt-parent = <&gpio>; @@ -806,7 +845,7 @@ regulator-boot-on; }; - fet1 { + vdd_bl_reg: fet1 { regulator-name = "vdd-lcd-bl"; }; @@ -814,7 +853,7 @@ regulator-name = "vdd-modem-3v3"; }; - fet4 { + avdd_lcd_reg: fet4 { regulator-name = "avdd-lcd"; }; @@ -846,7 +885,7 @@ }; }; - palmas: tps65913 { + palmas: tps65913@58 { compatible = "ti,palmas"; reg = <0x58>; interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>; @@ -1046,7 +1085,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <500>; @@ -1057,7 +1096,7 @@ nvidia,sys-clock-req-active-high; }; - ahub { + ahub@70080000 { i2s@70080400 { status = "okay"; }; @@ -1084,12 +1123,23 @@ vbus-supply = <&usb3_vbus_reg>; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; @@ -1150,16 +1200,6 @@ gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; }; - lcd_bl_en_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "lcd_bl_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - }; - usb1_vbus_reg: regulator@3 { compatible = "regulator-fixed"; reg = <3>; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 8d42787..389e987 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -1,5 +1,6 @@ #include <dt-bindings/clock/tegra114-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "skeleton.dtsi" @@ -15,7 +16,113 @@ serial3 = &uartd; }; - gic: interrupt-controller { + host1x@50000000 { + compatible = "nvidia,tegra114-host1x", "simple-bus"; + reg = <0x50000000 0x00028000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ + clocks = <&tegra_car TEGRA114_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x01000000>; + + gr2d@54140000 { + compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d"; + reg = <0x54140000 0x00040000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_GR2D>; + resets = <&tegra_car 21>; + reset-names = "2d"; + }; + + gr3d@54180000 { + compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d"; + reg = <0x54180000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_GR3D>; + resets = <&tegra_car 24>; + reset-names = "3d"; + }; + + dc@54200000 { + compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_DISP1>, + <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + rgb { + status = "disabled"; + }; + }; + + dc@54240000 { + compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + reg = <0x54240000 0x00040000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_DISP2>, + <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + rgb { + status = "disabled"; + }; + }; + + hdmi@54280000 { + compatible = "nvidia,tegra114-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_HDMI>, + <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + status = "disabled"; + }; + + dsi@54300000 { + compatible = "nvidia,tegra114-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_DSIA>, + <&tegra_car TEGRA114_CLK_DSIALP>, + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi@54400000 { + compatible = "nvidia,tegra114-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_DSIB>, + <&tegra_car TEGRA114_CLK_DSIBLP>, + <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gic: interrupt-controller@50041000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -39,13 +146,14 @@ clocks = <&tegra_car TEGRA114_CLK_TIMER>; }; - tegra_car: clock { + tegra_car: clock@60006000 { compatible = "nvidia,tegra114-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; - apbdma: dma { + apbdma: dma@6000a000 { compatible = "nvidia,tegra114-apbdma"; reg = <0x6000a000 0x1400>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, @@ -81,14 +189,17 @@ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; }; - ahb: ahb { + ahb: ahb@6000c004 { compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; reg = <0x6000c004 0x14c>; }; - gpio: gpio { + gpio: gpio@6000d000 { compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, @@ -105,7 +216,7 @@ interrupt-controller; }; - pinmux: pinmux { + pinmux: pinmux@70000868 { compatible = "nvidia,tegra114-pinmux"; reg = <0x70000868 0x148 /* Pad control registers */ 0x70003000 0x40c>; /* Mux registers */ @@ -124,9 +235,12 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 8>; - status = "disabled"; clocks = <&tegra_car TEGRA114_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; }; uartb: serial@70006040 { @@ -134,9 +248,12 @@ reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 9>; - status = "disabled"; clocks = <&tegra_car TEGRA114_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; }; uartc: serial@70006200 { @@ -144,9 +261,12 @@ reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 10>; - status = "disabled"; clocks = <&tegra_car TEGRA114_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; }; uartd: serial@70006300 { @@ -154,16 +274,21 @@ reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 19>; - status = "disabled"; clocks = <&tegra_car TEGRA114_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; }; - pwm: pwm { + pwm: pwm@7000a000 { compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; clocks = <&tegra_car TEGRA114_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; status = "disabled"; }; @@ -175,6 +300,10 @@ #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_I2C1>; clock-names = "div-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -186,6 +315,10 @@ #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_I2C2>; clock-names = "div-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -197,6 +330,10 @@ #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_I2C3>; clock-names = "div-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -208,6 +345,10 @@ #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_I2C4>; clock-names = "div-clk"; + resets = <&tegra_car 103>; + reset-names = "i2c"; + dmas = <&apbdma 26>, <&apbdma 26>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -219,6 +360,10 @@ #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_I2C5>; clock-names = "div-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -226,11 +371,14 @@ compatible = "nvidia,tegra114-spi"; reg = <0x7000d400 0x200>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 15>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC1>; clock-names = "spi"; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -238,11 +386,14 @@ compatible = "nvidia,tegra114-spi"; reg = <0x7000d600 0x200>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 16>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC2>; clock-names = "spi"; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -250,11 +401,14 @@ compatible = "nvidia,tegra114-spi"; reg = <0x7000d800 0x200>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC3>; clock-names = "spi"; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -262,11 +416,14 @@ compatible = "nvidia,tegra114-spi"; reg = <0x7000da00 0x200>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 18>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC4>; clock-names = "spi"; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -274,11 +431,14 @@ compatible = "nvidia,tegra114-spi"; reg = <0x7000dc00 0x200>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 27>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC5>; clock-names = "spi"; + resets = <&tegra_car 104>; + reset-names = "spi"; + dmas = <&apbdma 27>, <&apbdma 27>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -286,37 +446,42 @@ compatible = "nvidia,tegra114-spi"; reg = <0x7000de00 0x200>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 28>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC6>; clock-names = "spi"; + resets = <&tegra_car 105>; + reset-names = "spi"; + dmas = <&apbdma 28>, <&apbdma 28>; + dma-names = "rx", "tx"; status = "disabled"; }; - rtc { + rtc@7000e000 { compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_RTC>; }; - kbc { + kbc@7000e200 { compatible = "nvidia,tegra114-kbc"; reg = <0x7000e200 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_KBC>; + resets = <&tegra_car 36>; + reset-names = "kbc"; status = "disabled"; }; - pmc { + pmc@7000e400 { compatible = "nvidia,tegra114-pmc"; reg = <0x7000e400 0x400>; clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; }; - iommu { + iommu@70019010 { compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; reg = <0x70019010 0x02c 0x700191f0 0x010 @@ -327,32 +492,45 @@ nvidia,ahb = <&ahb>; }; - ahub { + ahub@70080000 { compatible = "nvidia,tegra114-ahub"; reg = <0x70080000 0x200>, <0x70080200 0x100>, <0x70081000 0x200>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>, - <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>, - <&apbdma 12>, <&apbdma 13>, <&apbdma 14>, - <&apbdma 29>; clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, - <&tegra_car TEGRA114_CLK_APBIF>, - <&tegra_car TEGRA114_CLK_I2S0>, - <&tegra_car TEGRA114_CLK_I2S1>, - <&tegra_car TEGRA114_CLK_I2S2>, - <&tegra_car TEGRA114_CLK_I2S3>, - <&tegra_car TEGRA114_CLK_I2S4>, - <&tegra_car TEGRA114_CLK_DAM0>, - <&tegra_car TEGRA114_CLK_DAM1>, - <&tegra_car TEGRA114_CLK_DAM2>, - <&tegra_car TEGRA114_CLK_SPDIF_IN>, - <&tegra_car TEGRA114_CLK_AMX>, - <&tegra_car TEGRA114_CLK_ADX>; - clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + <&tegra_car TEGRA114_CLK_APBIF>; + clock-names = "d_audio", "apbif"; + resets = <&tegra_car 106>, /* d_audio */ + <&tegra_car 107>, /* apbif */ + <&tegra_car 30>, /* i2s0 */ + <&tegra_car 11>, /* i2s1 */ + <&tegra_car 18>, /* i2s2 */ + <&tegra_car 101>, /* i2s3 */ + <&tegra_car 102>, /* i2s4 */ + <&tegra_car 108>, /* dam0 */ + <&tegra_car 109>, /* dam1 */ + <&tegra_car 110>, /* dam2 */ + <&tegra_car 10>, /* spdif */ + <&tegra_car 153>, /* amx */ + <&tegra_car 154>; /* adx */ + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif_in", "amx", "adx"; + "spdif", "amx", "adx"; + dmas = <&apbdma 1>, <&apbdma 1>, + <&apbdma 2>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 3>, + <&apbdma 4>, <&apbdma 4>, + <&apbdma 6>, <&apbdma 6>, + <&apbdma 7>, <&apbdma 7>, + <&apbdma 12>, <&apbdma 12>, + <&apbdma 13>, <&apbdma 13>, + <&apbdma 14>, <&apbdma 14>, + <&apbdma 29>, <&apbdma 29>; + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", + "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", + "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", + "rx9", "tx9"; ranges; #address-cells = <1>; #size-cells = <1>; @@ -362,6 +540,8 @@ reg = <0x70080300 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks = <&tegra_car TEGRA114_CLK_I2S0>; + resets = <&tegra_car 30>; + reset-names = "i2s"; status = "disabled"; }; @@ -370,6 +550,8 @@ reg = <0x70080400 0x100>; nvidia,ahub-cif-ids = <5 5>; clocks = <&tegra_car TEGRA114_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; status = "disabled"; }; @@ -378,6 +560,8 @@ reg = <0x70080500 0x100>; nvidia,ahub-cif-ids = <6 6>; clocks = <&tegra_car TEGRA114_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; status = "disabled"; }; @@ -386,6 +570,8 @@ reg = <0x70080600 0x100>; nvidia,ahub-cif-ids = <7 7>; clocks = <&tegra_car TEGRA114_CLK_I2S3>; + resets = <&tegra_car 101>; + reset-names = "i2s"; status = "disabled"; }; @@ -394,15 +580,26 @@ reg = <0x70080700 0x100>; nvidia,ahub-cif-ids = <8 8>; clocks = <&tegra_car TEGRA114_CLK_I2S4>; + resets = <&tegra_car 102>; + reset-names = "i2s"; status = "disabled"; }; }; + mipi: mipi@700e3000 { + compatible = "nvidia,tegra114-mipi"; + reg = <0x700e3000 0x100>; + clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; + #nvidia,mipi-calibrate-cells = <1>; + }; + sdhci@78000000 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; status = "disable"; }; @@ -411,6 +608,8 @@ reg = <0x78000200 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; status = "disable"; }; @@ -419,6 +618,8 @@ reg = <0x78000400 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; status = "disable"; }; @@ -427,6 +628,8 @@ reg = <0x78000600 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; status = "disable"; }; @@ -436,6 +639,8 @@ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; nvidia,phy = <&phy1>; status = "disabled"; }; @@ -467,6 +672,8 @@ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; nvidia,phy = <&phy3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 431d67a..c6dcef5 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1,19 +1,917 @@ /dts-v1/; +#include <dt-bindings/input/input.h> #include "tegra124.dtsi" / { model = "NVIDIA Tegra124 Venice2"; compatible = "nvidia,venice2", "nvidia,tegra124"; + aliases { + rtc0 = "/i2c@7000d000/as3722@40"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x80000000 0x80000000>; }; + pinmux: pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: common { + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2", + "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + pg4 { + nvidia,pins = "pg4", + "pg5", + "pg6", + "pi3"; + nvidia,function = "spi4"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + pk0 { + nvidia,pins = "pk0", + "kb_row15_ps7", + "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0", + "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5", + "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; + }; + pj7 { + nvidia,pins = "pj7", + "pk7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pb0 { + nvidia,pins = "pb0", + "pb1"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "displaya_alt"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <32>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <20>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + drive_gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <1>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,drive-type = <1>; + }; + als_irq_l { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + codec_irq_l { + nvidia,pins = "ph4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_bl_en { + nvidia,pins = "ph2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch_irq_l { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + tpm_davint_l { + nvidia,pins = "ph6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ts_irq_l { + nvidia,pins = "pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ts_reset_l { + nvidia,pins = "pk4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ts_shdn_l { + nvidia,pins = "pk1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col0_ap { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lid_open { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + en_vdd_sd { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ac_ok { + nvidia,pins = "pj0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sensor_irq_l { + nvidia,pins = "pi6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wifi_en { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + wifi_rst_l { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hp_det_l { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; + serial@70006000 { status = "okay"; }; + pwm: pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + acodec: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; + }; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + as3722: as3722@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1_2_4_7 { + pins = "gpio1", "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_6 { + pins = "gpio3", "gpio6"; + bias-high-impedance; + }; + + gpio5 { + pins = "gpio5"; + function = "clk32k-out"; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_ac_bat_reg>; + vsup-sd3-supply = <&vdd_ac_bat_reg>; + vsup-sd4-supply = <&vdd_ac_bat_reg>; + vsup-sd5-supply = <&vdd_ac_bat_reg>; + vin-ldo0-supply = <&as3722_sd2>; + vin-ldo1-6-supply = <&vdd_ac_bat_reg>; + vin-ldo2-5-7-supply = <&as3722_sd5>; + vin-ldo3-4-supply = <&vdd_ac_bat_reg>; + vin-ldo9-10-supply = <&vdd_ac_bat_reg>; + vin-ldo11-supply = <&vdd_ac_bat_reg>; + + sd0 { + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,external-control = <2>; + }; + + sd1 { + regulator-name = "vdd-core"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <2500000>; + regulator-always-on; + regulator-boot-on; + ams,external-control = <1>; + }; + + as3722_sd2: sd2 { + regulator-name = "vddio-ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "vddio-ddr-2phase"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd4 { + regulator-name = "avdd-pex-sata"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + }; + + as3722_sd5: sd5 { + regulator-name = "vddio-sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sd6 { + regulator-name = "vdd-gpu"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo0 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,external-control = <1>; + }; + + ldo1 { + regulator-name = "run-cam-1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "gen-avdd,vddio-hsic"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "vdd-rtc"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + ldo4 { + regulator-name = "vdd-cam"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd-cam-front"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo6 { + regulator-name = "vddio-sdmmc3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7 { + regulator-name = "vdd-cam-rear"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "vdd-touch"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "vdd-cam-af"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "vpp-fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + spi@7000d400 { + status = "okay"; + + cros-ec@0 { + compatible = "google,cros-ec-spi"; + spi-max-frequency = <4000000>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; + reg = <0>; + + google,cros-ec-spi-msg-delay = <2000>; + + cros-ec-keyb { + compatible = "google,cros-ec-keyb"; + keypad,num-rows = <8>; + keypad,num-columns = <13>; + google,needs-ghost-filter; + + linux,keymap = < + MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) + MATRIX_KEY(0x00, 0x02, KEY_F1) + MATRIX_KEY(0x00, 0x03, KEY_B) + MATRIX_KEY(0x00, 0x04, KEY_F10) + MATRIX_KEY(0x00, 0x06, KEY_N) + MATRIX_KEY(0x00, 0x08, KEY_EQUAL) + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) + + MATRIX_KEY(0x01, 0x01, KEY_ESC) + MATRIX_KEY(0x01, 0x02, KEY_F4) + MATRIX_KEY(0x01, 0x03, KEY_G) + MATRIX_KEY(0x01, 0x04, KEY_F7) + MATRIX_KEY(0x01, 0x06, KEY_H) + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) + MATRIX_KEY(0x01, 0x09, KEY_F9) + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) + + MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) + MATRIX_KEY(0x02, 0x01, KEY_TAB) + MATRIX_KEY(0x02, 0x02, KEY_F3) + MATRIX_KEY(0x02, 0x03, KEY_T) + MATRIX_KEY(0x02, 0x04, KEY_F6) + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) + MATRIX_KEY(0x02, 0x06, KEY_Y) + MATRIX_KEY(0x02, 0x07, KEY_102ND) + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) + MATRIX_KEY(0x02, 0x09, KEY_F8) + + MATRIX_KEY(0x03, 0x01, KEY_GRAVE) + MATRIX_KEY(0x03, 0x02, KEY_F2) + MATRIX_KEY(0x03, 0x03, KEY_5) + MATRIX_KEY(0x03, 0x04, KEY_F5) + MATRIX_KEY(0x03, 0x06, KEY_6) + MATRIX_KEY(0x03, 0x08, KEY_MINUS) + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) + + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) + MATRIX_KEY(0x04, 0x01, KEY_A) + MATRIX_KEY(0x04, 0x02, KEY_D) + MATRIX_KEY(0x04, 0x03, KEY_F) + MATRIX_KEY(0x04, 0x04, KEY_S) + MATRIX_KEY(0x04, 0x05, KEY_K) + MATRIX_KEY(0x04, 0x06, KEY_J) + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) + MATRIX_KEY(0x04, 0x09, KEY_L) + MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) + MATRIX_KEY(0x04, 0x0b, KEY_ENTER) + + MATRIX_KEY(0x05, 0x01, KEY_Z) + MATRIX_KEY(0x05, 0x02, KEY_C) + MATRIX_KEY(0x05, 0x03, KEY_V) + MATRIX_KEY(0x05, 0x04, KEY_X) + MATRIX_KEY(0x05, 0x05, KEY_COMMA) + MATRIX_KEY(0x05, 0x06, KEY_M) + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) + MATRIX_KEY(0x05, 0x08, KEY_SLASH) + MATRIX_KEY(0x05, 0x09, KEY_DOT) + MATRIX_KEY(0x05, 0x0b, KEY_SPACE) + + MATRIX_KEY(0x06, 0x01, KEY_1) + MATRIX_KEY(0x06, 0x02, KEY_3) + MATRIX_KEY(0x06, 0x03, KEY_4) + MATRIX_KEY(0x06, 0x04, KEY_2) + MATRIX_KEY(0x06, 0x05, KEY_8) + MATRIX_KEY(0x06, 0x06, KEY_7) + MATRIX_KEY(0x06, 0x08, KEY_0) + MATRIX_KEY(0x06, 0x09, KEY_9) + MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) + MATRIX_KEY(0x06, 0x0b, KEY_DOWN) + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) + + MATRIX_KEY(0x07, 0x01, KEY_Q) + MATRIX_KEY(0x07, 0x02, KEY_E) + MATRIX_KEY(0x07, 0x03, KEY_R) + MATRIX_KEY(0x07, 0x04, KEY_W) + MATRIX_KEY(0x07, 0x05, KEY_I) + MATRIX_KEY(0x07, 0x06, KEY_U) + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) + MATRIX_KEY(0x07, 0x08, KEY_P) + MATRIX_KEY(0x07, 0x09, KEY_O) + MATRIX_KEY(0x07, 0x0b, KEY_UP) + MATRIX_KEY(0x07, 0x0c, KEY_LEFT) + >; + }; + }; + }; + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; @@ -24,4 +922,170 @@ nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; }; + + sdhci@700b0400 { + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + status = "okay"; + bus-width = <4>; + }; + + sdhci@700b0600 { + status = "okay"; + bus-width = <8>; + }; + + ahub@70300000 { + i2s@70301100 { + status = "okay"; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_ac_bat_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; + }; + + vdd_3v3_modem_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd-modem-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_hdmi_5v0_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd-hdmi-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + }; + + vdd_bl_reg: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd-bl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_LOW>; + }; + + vdd_ts_sw_5v0: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vdd_ts_sw"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_LOW>; + }; + + usb1_vbus_reg: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + }; + + usb3_vbus_reg: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + }; + + panel_3v3_reg: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "panel_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-venice2", + "nvidia,tegra-audio-max98090"; + nvidia,model = "NVIDIA Tegra Venice2"; + + nvidia,audio-routing = + "Headphones", "HPR", + "Headphones", "HPL", + "Speakers", "SPKR", + "Speakers", "SPKL", + "Mic Jack", "MICBIAS", + "IN34", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&acodec>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index b741300..ec0698a 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1,4 +1,6 @@ +#include <dt-bindings/clock/tegra124-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "skeleton.dtsi" @@ -28,6 +30,14 @@ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_TIMER>; + }; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra124-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; }; gpio: gpio@6000d000 { @@ -47,6 +57,53 @@ interrupt-controller; }; + apbdma: dma@60020000 { + compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; + reg = <0x60020000 0x1400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; + }; + + pinmux: pinmux@70000868 { + compatible = "nvidia,tegra124-pinmux"; + reg = <0x70000868 0x164>, /* Pad control registers */ + <0x70003000 0x434>; /* Mux registers */ + }; + /* * There are two serial driver i.e. 8250 based simple serial * driver and APB DMA based serial driver for higher baudrate @@ -60,6 +117,11 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -68,6 +130,11 @@ reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -76,6 +143,11 @@ reg = <0x70006200 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -84,6 +156,11 @@ reg = <0x70006300 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -92,6 +169,201 @@ reg = <0x70006400 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + pwm@7000a000 { + compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + clocks = <&tegra_car TEGRA124_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; + status = "disabled"; + }; + + i2c@7000c000 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C1>; + clock-names = "div-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c400 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c400 0x100>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C2>; + clock-names = "div-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c500 0x100>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C3>; + clock-names = "div-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c700 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c700 0x100>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C4>; + clock-names = "div-clk"; + resets = <&tegra_car 103>; + reset-names = "i2c"; + dmas = <&apbdma 26>, <&apbdma 26>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000d000 0x100>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C5>; + clock-names = "div-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d100 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000d100 0x100>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C6>; + clock-names = "div-clk"; + resets = <&tegra_car 166>; + reset-names = "i2c"; + dmas = <&apbdma 30>, <&apbdma 30>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d400 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d400 0x200>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC1>; + clock-names = "spi"; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC2>; + clock-names = "spi"; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d800 0x200>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC3>; + clock-names = "spi"; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000da00 0x200>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC4>; + clock-names = "spi"; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000dc00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000dc00 0x200>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC5>; + clock-names = "spi"; + resets = <&tegra_car 104>; + reset-names = "spi"; + dmas = <&apbdma 27>, <&apbdma 27>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000de00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000de00 0x200>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC6>; + clock-names = "spi"; + resets = <&tegra_car 105>; + reset-names = "spi"; + dmas = <&apbdma 28>, <&apbdma 28>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -99,11 +371,157 @@ compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_RTC>; }; pmc@7000e400 { compatible = "nvidia,tegra124-pmc"; reg = <0x7000e400 0x400>; + clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + }; + + sdhci@700b0000 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0000 0x200>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + status = "disable"; + }; + + sdhci@700b0200 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0200 0x200>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; + status = "disable"; + }; + + sdhci@700b0400 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0400 0x200>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; + status = "disable"; + }; + + sdhci@700b0600 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0600 0x200>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; + status = "disable"; + }; + + ahub@70300000 { + compatible = "nvidia,tegra124-ahub"; + reg = <0x70300000 0x200>, + <0x70300800 0x800>, + <0x70300200 0x600>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, + <&tegra_car TEGRA124_CLK_APBIF>; + clock-names = "d_audio", "apbif"; + resets = <&tegra_car 106>, /* d_audio */ + <&tegra_car 107>, /* apbif */ + <&tegra_car 30>, /* i2s0 */ + <&tegra_car 11>, /* i2s1 */ + <&tegra_car 18>, /* i2s2 */ + <&tegra_car 101>, /* i2s3 */ + <&tegra_car 102>, /* i2s4 */ + <&tegra_car 108>, /* dam0 */ + <&tegra_car 109>, /* dam1 */ + <&tegra_car 110>, /* dam2 */ + <&tegra_car 10>, /* spdif */ + <&tegra_car 153>, /* amx */ + <&tegra_car 185>, /* amx1 */ + <&tegra_car 154>, /* adx */ + <&tegra_car 180>, /* adx1 */ + <&tegra_car 186>, /* afc0 */ + <&tegra_car 187>, /* afc1 */ + <&tegra_car 188>, /* afc2 */ + <&tegra_car 189>, /* afc3 */ + <&tegra_car 190>, /* afc4 */ + <&tegra_car 191>; /* afc5 */ + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + "i2s3", "i2s4", "dam0", "dam1", "dam2", + "spdif", "amx", "amx1", "adx", "adx1", + "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; + dmas = <&apbdma 1>, <&apbdma 1>, + <&apbdma 2>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 3>, + <&apbdma 4>, <&apbdma 4>, + <&apbdma 6>, <&apbdma 6>, + <&apbdma 7>, <&apbdma 7>, + <&apbdma 12>, <&apbdma 12>, + <&apbdma 13>, <&apbdma 13>, + <&apbdma 14>, <&apbdma 14>, + <&apbdma 29>, <&apbdma 29>; + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", + "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", + "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", + "rx9", "tx9"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + tegra_i2s0: i2s@70301000 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301000 0x100>; + nvidia,ahub-cif-ids = <4 4>; + clocks = <&tegra_car TEGRA124_CLK_I2S0>; + resets = <&tegra_car 30>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s1: i2s@70301100 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301100 0x100>; + nvidia,ahub-cif-ids = <5 5>; + clocks = <&tegra_car TEGRA124_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s2: i2s@70301200 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301200 0x100>; + nvidia,ahub-cif-ids = <6 6>; + clocks = <&tegra_car TEGRA124_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s3: i2s@70301300 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301300 0x100>; + nvidia,ahub-cif-ids = <7 7>; + clocks = <&tegra_car TEGRA124_CLK_I2S3>; + resets = <&tegra_car 101>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s4: i2s@70301400 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301400 0x100>; + nvidia,ahub-cif-ids = <8 8>; + clocks = <&tegra_car TEGRA124_CLK_I2S4>; + resets = <&tegra_car 102>; + reset-names = "i2s"; + status = "disabled"; + }; }; cpus { diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index cbe89ff..8e0066a 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -4,12 +4,17 @@ model = "Toradex Colibri T20 512MB"; compatible = "toradex,colibri_t20-512", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x20000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { vdd-supply = <&hdmi_vdd_reg>; pll-supply = <&hdmi_pll_reg>; @@ -19,7 +24,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -27,20 +32,20 @@ audio_refclk { nvidia,pins = "cdev1"; nvidia,function = "plla_out"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; crt { nvidia,pins = "crtp"; nvidia,function = "crt"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; dap3 { nvidia,pins = "dap3"; nvidia,function = "dap3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; displaya { nvidia,pins = "ld0", "ld1", "ld2", "ld3", @@ -50,155 +55,163 @@ "lhs", "lpw0", "lpw2", "lsc0", "lsc1", "lsck", "lsda", "lspi", "lvs"; nvidia,function = "displaya"; - nvidia,tristate = <1>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; gpio_dte { nvidia,pins = "dte"; nvidia,function = "rsvd1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; gpio_gmi { nvidia,pins = "ata", "atc", "atd", "ate", "dap1", "dap2", "dap4", "gpu", "irrx", "irtx", "spia", "spib", "spic"; nvidia,function = "gmi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; gpio_pta { nvidia,pins = "pta"; nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; gpio_uac { nvidia,pins = "uac"; nvidia,function = "rsvd2"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; hdint { nvidia,pins = "hdint"; nvidia,function = "hdmi"; - nvidia,tristate = <1>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; i2c1 { nvidia,pins = "rm"; nvidia,function = "i2c1"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; i2c3 { nvidia,pins = "dtf"; nvidia,function = "i2c3"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; i2cddc { nvidia,pins = "ddc"; nvidia,function = "i2c2"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; i2cp { nvidia,pins = "i2cp"; nvidia,function = "i2cp"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; irda { nvidia,pins = "uad"; nvidia,function = "irda"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; nand { nvidia,pins = "kbca", "kbcc", "kbcd", "kbce", "kbcf"; nvidia,function = "nand"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; owc { nvidia,pins = "owc"; nvidia,function = "owr"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; pmc { nvidia,pins = "pmc"; nvidia,function = "pwr_on"; - nvidia,tristate = <0>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; pwm { nvidia,pins = "sdb", "sdc", "sdd"; nvidia,function = "pwm"; - nvidia,tristate = <1>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; sdio4 { nvidia,pins = "atb", "gma", "gme"; nvidia,function = "sdio4"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; spi1 { nvidia,pins = "spid", "spie", "spif"; nvidia,function = "spi1"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; spi4 { nvidia,pins = "slxa", "slxc", "slxd", "slxk"; nvidia,function = "spi4"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; uarta { nvidia,pins = "sdio1"; nvidia,function = "uarta"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; uartd { nvidia,pins = "gmc"; nvidia,function = "uartd"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; ulpi { nvidia,pins = "uaa", "uab", "uda"; nvidia,function = "ulpi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; ulpi_refclk { nvidia,pins = "cdev2"; nvidia,function = "pllp_out4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; usb_gpio { nvidia,pins = "spig", "spih"; nvidia,function = "spi2_alt"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; vi { nvidia,pins = "dta", "dtb", "dtc", "dtd"; nvidia,function = "vi"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; vi_sc { nvidia,pins = "csus"; nvidia,function = "vi_sensor_clk"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; }; }; + ac97: ac97@70002000 { + status = "okay"; + nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) + GPIO_ACTIVE_HIGH>; + nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) + GPIO_ACTIVE_HIGH>; + }; + i2c@7000c000 { clock-frequency = <400000>; }; @@ -225,15 +238,15 @@ #gpio-cells = <2>; gpio-controller; - sys-supply = <&vdd_5v0_reg>; + sys-supply = <&vdd_3v3_reg>; vin-sm0-supply = <&sys_reg>; vin-sm1-supply = <&sys_reg>; vin-sm2-supply = <&sys_reg>; vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; + vinldo23-supply = <&vdd_3v3_reg>; + vinldo4-supply = <&vdd_3v3_reg>; + vinldo678-supply = <&vdd_3v3_reg>; + vinldo9-supply = <&vdd_3v3_reg>; regulators { #address-cells = <1>; @@ -250,8 +263,8 @@ reg = <1>; regulator-compatible = "sm0"; regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1275000>; - regulator-max-microvolt = <1275000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; regulator-always-on; }; @@ -259,8 +272,8 @@ reg = <2>; regulator-compatible = "sm1"; regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; regulator-always-on; }; @@ -316,8 +329,8 @@ reg = <10>; regulator-compatible = "ldo6"; regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; }; hdmi_vdd_reg: regulator@11 { @@ -362,7 +375,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; nvidia,cpu-pwr-off-time = <5000>; @@ -442,14 +455,6 @@ }; }; - ac97: ac97 { - status = "okay"; - nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_HIGH>; - nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) - GPIO_ACTIVE_HIGH>; - }; - usb@c5004000 { status = "okay"; nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) @@ -471,7 +476,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; @@ -479,37 +484,17 @@ }; }; - sound { - compatible = "nvidia,tegra-audio-wm9712-colibri_t20", - "nvidia,tegra-audio-wm9712"; - nvidia,model = "Colibri T20 AC97 Audio"; - - nvidia,audio-routing = - "Headphone", "HPOUTL", - "Headphone", "HPOUTR", - "LineIn", "LINEINL", - "LineIn", "LINEINR", - "Mic", "MIC1"; - - nvidia,ac97-controller = <&ac97>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; - vdd_5v0_reg: regulator@100 { + vdd_3v3_reg: regulator@100 { compatible = "regulator-fixed"; reg = <100>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; }; @@ -525,4 +510,24 @@ gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; }; }; + + sound { + compatible = "nvidia,tegra-audio-wm9712-colibri_t20", + "nvidia,tegra-audio-wm9712"; + nvidia,model = "Colibri T20 AC97 Audio"; + + nvidia,audio-routing = + "Headphone", "HPOUTL", + "Headphone", "HPOUTR", + "LineIn", "LINEINL", + "LineIn", "LINEINR", + "Mic", "MIC1"; + + nvidia,ac97-controller = <&ac97>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index e156ab3..3fb1f50 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -1,17 +1,31 @@ /dts-v1/; +#include <dt-bindings/input/input.h> #include "tegra20.dtsi" / { model = "NVIDIA Tegra20 Harmony evaluation board"; compatible = "nvidia,harmony", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x40000000>; }; - host1x { - hdmi { + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + + hdmi@54280000 { status = "okay"; vdd-supply = <&hdmi_vdd_reg>; @@ -23,7 +37,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -184,50 +198,50 @@ "gmb", "gmc", "gmd", "gme", "gpu7", "gpv", "i2cp", "pta", "rm", "slxa", "slxk", "spia", "spib", "uac"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; }; conf_csus { nvidia,pins = "csus", "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_crtp { nvidia,pins = "crtp", "dap2", "dap3", "dap4", "dtc", "dte", "dtf", "gpu", "sdio1", "slxc", "slxd", "spdi", "spdo", "spig", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_ddc { nvidia,pins = "ddc", "dta", "dtd", "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf", "sdc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_hdint { nvidia,pins = "hdint", "lcsn", "ldc", "lm1", "lpw1", "lsc1", "lsck", "lsda", "lsdi", "lvp0", "owc", "sdb"; - nvidia,tristate = <1>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_irrx { nvidia,pins = "irrx", "irtx", "sdd", "spic", "spie", "spih", "uaa", "uab", "uad", "uca", "ucb"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_lc { nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; }; conf_ld0 { nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", @@ -237,12 +251,12 @@ "lhp1", "lhp2", "lhs", "lm0", "lpp", "lpw0", "lpw2", "lsc0", "lspi", "lvp1", "lvs", "pmc"; - nvidia,tristate = <0>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; }; }; }; @@ -255,6 +269,10 @@ status = "okay"; }; + pwm: pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { status = "okay"; clock-frequency = <400000>; @@ -415,7 +433,124 @@ }; }; - pmc { + kbc@7000e200 { + status = "okay"; + nvidia,debounce-delay-ms = <2>; + nvidia,repeat-delay-ms = <160>; + nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; + linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W) + MATRIX_KEY(0x00, 0x03, KEY_S) + MATRIX_KEY(0x00, 0x04, KEY_A) + MATRIX_KEY(0x00, 0x05, KEY_Z) + MATRIX_KEY(0x00, 0x07, KEY_FN) + MATRIX_KEY(0x01, 0x07, KEY_MENU) + MATRIX_KEY(0x02, 0x06, KEY_LEFTALT) + MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT) + MATRIX_KEY(0x03, 0x00, KEY_5) + MATRIX_KEY(0x03, 0x01, KEY_4) + MATRIX_KEY(0x03, 0x02, KEY_R) + MATRIX_KEY(0x03, 0x03, KEY_E) + MATRIX_KEY(0x03, 0x04, KEY_F) + MATRIX_KEY(0x03, 0x05, KEY_D) + MATRIX_KEY(0x03, 0x06, KEY_X) + MATRIX_KEY(0x04, 0x00, KEY_7) + MATRIX_KEY(0x04, 0x01, KEY_6) + MATRIX_KEY(0x04, 0x02, KEY_T) + MATRIX_KEY(0x04, 0x03, KEY_H) + MATRIX_KEY(0x04, 0x04, KEY_G) + MATRIX_KEY(0x04, 0x05, KEY_V) + MATRIX_KEY(0x04, 0x06, KEY_C) + MATRIX_KEY(0x04, 0x07, KEY_SPACE) + MATRIX_KEY(0x05, 0x00, KEY_9) + MATRIX_KEY(0x05, 0x01, KEY_8) + MATRIX_KEY(0x05, 0x02, KEY_U) + MATRIX_KEY(0x05, 0x03, KEY_Y) + MATRIX_KEY(0x05, 0x04, KEY_J) + MATRIX_KEY(0x05, 0x05, KEY_N) + MATRIX_KEY(0x05, 0x06, KEY_B) + MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH) + MATRIX_KEY(0x06, 0x00, KEY_MINUS) + MATRIX_KEY(0x06, 0x01, KEY_0) + MATRIX_KEY(0x06, 0x02, KEY_O) + MATRIX_KEY(0x06, 0x03, KEY_I) + MATRIX_KEY(0x06, 0x04, KEY_L) + MATRIX_KEY(0x06, 0x05, KEY_K) + MATRIX_KEY(0x06, 0x06, KEY_COMMA) + MATRIX_KEY(0x06, 0x07, KEY_M) + MATRIX_KEY(0x07, 0x01, KEY_EQUAL) + MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE) + MATRIX_KEY(0x07, 0x03, KEY_ENTER) + MATRIX_KEY(0x07, 0x07, KEY_MENU) + MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT) + MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT) + MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL) + MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL) + MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE) + MATRIX_KEY(0x0B, 0x01, KEY_P) + MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE) + MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON) + MATRIX_KEY(0x0B, 0x04, KEY_SLASH) + MATRIX_KEY(0x0B, 0x05, KEY_DOT) + MATRIX_KEY(0x0C, 0x00, KEY_F10) + MATRIX_KEY(0x0C, 0x01, KEY_F9) + MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE) + MATRIX_KEY(0x0C, 0x03, KEY_3) + MATRIX_KEY(0x0C, 0x04, KEY_2) + MATRIX_KEY(0x0C, 0x05, KEY_UP) + MATRIX_KEY(0x0C, 0x06, KEY_PRINT) + MATRIX_KEY(0x0C, 0x07, KEY_PAUSE) + MATRIX_KEY(0x0D, 0x00, KEY_INSERT) + MATRIX_KEY(0x0D, 0x01, KEY_DELETE) + MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP ) + MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN) + MATRIX_KEY(0x0D, 0x05, KEY_RIGHT) + MATRIX_KEY(0x0D, 0x06, KEY_DOWN) + MATRIX_KEY(0x0D, 0x07, KEY_LEFT) + MATRIX_KEY(0x0E, 0x00, KEY_F11) + MATRIX_KEY(0x0E, 0x01, KEY_F12) + MATRIX_KEY(0x0E, 0x02, KEY_F8) + MATRIX_KEY(0x0E, 0x03, KEY_Q) + MATRIX_KEY(0x0E, 0x04, KEY_F4) + MATRIX_KEY(0x0E, 0x05, KEY_F3) + MATRIX_KEY(0x0E, 0x06, KEY_1) + MATRIX_KEY(0x0E, 0x07, KEY_F7) + MATRIX_KEY(0x0F, 0x00, KEY_ESC) + MATRIX_KEY(0x0F, 0x01, KEY_GRAVE) + MATRIX_KEY(0x0F, 0x02, KEY_F5) + MATRIX_KEY(0x0F, 0x03, KEY_TAB) + MATRIX_KEY(0x0F, 0x04, KEY_F1) + MATRIX_KEY(0x0F, 0x05, KEY_F2) + MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK) + MATRIX_KEY(0x0F, 0x07, KEY_F6) + MATRIX_KEY(0x14, 0x00, KEY_KP7) + MATRIX_KEY(0x15, 0x00, KEY_KP9) + MATRIX_KEY(0x15, 0x01, KEY_KP8) + MATRIX_KEY(0x15, 0x02, KEY_KP4) + MATRIX_KEY(0x15, 0x04, KEY_KP1) + MATRIX_KEY(0x16, 0x01, KEY_KPSLASH) + MATRIX_KEY(0x16, 0x02, KEY_KP6) + MATRIX_KEY(0x16, 0x03, KEY_KP5) + MATRIX_KEY(0x16, 0x04, KEY_KP3) + MATRIX_KEY(0x16, 0x05, KEY_KP2) + MATRIX_KEY(0x16, 0x07, KEY_KP0) + MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK) + MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS) + MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS) + MATRIX_KEY(0x1B, 0x05, KEY_KPDOT) + MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP) + MATRIX_KEY(0x1D, 0x03, KEY_HOME) + MATRIX_KEY(0x1D, 0x04, KEY_END) + MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN) + MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK) + MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK) + MATRIX_KEY(0x1E, 0x02, KEY_MUTE) + MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>; + }; + + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; @@ -425,7 +560,7 @@ nvidia,sys-clock-req-active-high; }; - pcie-controller { + pcie-controller@80003000 { pex-clk-supply = <&pci_clk_reg>; vdd-supply = <&pci_vdd_reg>; status = "okay"; @@ -483,12 +618,23 @@ bus-width = <8>; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; @@ -502,126 +648,18 @@ power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = <116>; /* KEY_POWER */ + linux,code = <KEY_POWER>; gpio-key,wakeup; }; }; - kbc { - status = "okay"; - nvidia,debounce-delay-ms = <2>; - nvidia,repeat-delay-ms = <160>; - nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; - nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; - linux,keymap = <0x00020011 /* KEY_W */ - 0x0003001F /* KEY_S */ - 0x0004001E /* KEY_A */ - 0x0005002C /* KEY_Z */ - 0x000701D0 /* KEY_FN */ - 0x0107008B /* KEY_MENU */ - 0x02060038 /* KEY_LEFTALT */ - 0x02070064 /* KEY_RIGHTALT */ - 0x03000006 /* KEY_5 */ - 0x03010005 /* KEY_4 */ - 0x03020013 /* KEY_R */ - 0x03030012 /* KEY_E */ - 0x03040021 /* KEY_F */ - 0x03050020 /* KEY_D */ - 0x0306002D /* KEY_X */ - 0x04000008 /* KEY_7 */ - 0x04010007 /* KEY_6 */ - 0x04020014 /* KEY_T */ - 0x04030023 /* KEY_H */ - 0x04040022 /* KEY_G */ - 0x0405002F /* KEY_V */ - 0x0406002E /* KEY_C */ - 0x04070039 /* KEY_SPACE */ - 0x0500000A /* KEY_9 */ - 0x05010009 /* KEY_8 */ - 0x05020016 /* KEY_U */ - 0x05030015 /* KEY_Y */ - 0x05040024 /* KEY_J */ - 0x05050031 /* KEY_N */ - 0x05060030 /* KEY_B */ - 0x0507002B /* KEY_BACKSLASH */ - 0x0600000C /* KEY_MINUS */ - 0x0601000B /* KEY_0 */ - 0x06020018 /* KEY_O */ - 0x06030017 /* KEY_I */ - 0x06040026 /* KEY_L */ - 0x06050025 /* KEY_K */ - 0x06060033 /* KEY_COMMA */ - 0x06070032 /* KEY_M */ - 0x0701000D /* KEY_EQUAL */ - 0x0702001B /* KEY_RIGHTBRACE */ - 0x0703001C /* KEY_ENTER */ - 0x0707008B /* KEY_MENU */ - 0x0804002A /* KEY_LEFTSHIFT */ - 0x08050036 /* KEY_RIGHTSHIFT */ - 0x0905001D /* KEY_LEFTCTRL */ - 0x09070061 /* KEY_RIGHTCTRL */ - 0x0B00001A /* KEY_LEFTBRACE */ - 0x0B010019 /* KEY_P */ - 0x0B020028 /* KEY_APOSTROPHE */ - 0x0B030027 /* KEY_SEMICOLON */ - 0x0B040035 /* KEY_SLASH */ - 0x0B050034 /* KEY_DOT */ - 0x0C000044 /* KEY_F10 */ - 0x0C010043 /* KEY_F9 */ - 0x0C02000E /* KEY_BACKSPACE */ - 0x0C030004 /* KEY_3 */ - 0x0C040003 /* KEY_2 */ - 0x0C050067 /* KEY_UP */ - 0x0C0600D2 /* KEY_PRINT */ - 0x0C070077 /* KEY_PAUSE */ - 0x0D00006E /* KEY_INSERT */ - 0x0D01006F /* KEY_DELETE */ - 0x0D030068 /* KEY_PAGEUP */ - 0x0D04006D /* KEY_PAGEDOWN */ - 0x0D05006A /* KEY_RIGHT */ - 0x0D06006C /* KEY_DOWN */ - 0x0D070069 /* KEY_LEFT */ - 0x0E000057 /* KEY_F11 */ - 0x0E010058 /* KEY_F12 */ - 0x0E020042 /* KEY_F8 */ - 0x0E030010 /* KEY_Q */ - 0x0E04003E /* KEY_F4 */ - 0x0E05003D /* KEY_F3 */ - 0x0E060002 /* KEY_1 */ - 0x0E070041 /* KEY_F7 */ - 0x0F000001 /* KEY_ESC */ - 0x0F010029 /* KEY_GRAVE */ - 0x0F02003F /* KEY_F5 */ - 0x0F03000F /* KEY_TAB */ - 0x0F04003B /* KEY_F1 */ - 0x0F05003C /* KEY_F2 */ - 0x0F06003A /* KEY_CAPSLOCK */ - 0x0F070040 /* KEY_F6 */ - 0x14000047 /* KEY_KP7 */ - 0x15000049 /* KEY_KP9 */ - 0x15010048 /* KEY_KP8 */ - 0x1502004B /* KEY_KP4 */ - 0x1504004F /* KEY_KP1 */ - 0x1601004E /* KEY_KPSLASH */ - 0x1602004D /* KEY_KP6 */ - 0x1603004C /* KEY_KP5 */ - 0x16040051 /* KEY_KP3 */ - 0x16050050 /* KEY_KP2 */ - 0x16070052 /* KEY_KP0 */ - 0x1B010037 /* KEY_KPASTERISK */ - 0x1B03004A /* KEY_KPMINUS */ - 0x1B04004E /* KEY_KPPLUS */ - 0x1B050053 /* KEY_KPDOT */ - 0x1C050073 /* KEY_VOLUMEUP */ - 0x1D030066 /* KEY_HOME */ - 0x1D04006B /* KEY_END */ - 0x1D0500E1 /* KEY_BRIGHTNESSUP */ - 0x1D060072 /* KEY_VOLUMEDOWN */ - 0x1D0700E0 /* KEY_BRIGHTNESSDOWN */ - 0x1E000045 /* KEY_NUMLOCK */ - 0x1E010046 /* KEY_SCROLLLOCK */ - 0x1E020071 /* KEY_MUTE */ - 0x1F0400D6>; /* KEY_QUESTION */ + panel: panel { + compatible = "auo,b101aw03", "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; }; regulators { @@ -667,7 +705,7 @@ enable-active-high; }; - regulator@4 { + vdd_pnl_reg: regulator@4 { compatible = "regulator-fixed"; reg = <4>; regulator-name = "vdd_pnl"; @@ -677,7 +715,7 @@ enable-active-high; }; - regulator@5 { + vdd_bl_reg: regulator@5 { compatible = "regulator-fixed"; reg = <5>; regulator-name = "vdd_bl"; diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts index f2222bd..8cfb83f 100644 --- a/arch/arm/boot/dts/tegra20-iris-512.dts +++ b/arch/arm/boot/dts/tegra20-iris-512.dts @@ -6,61 +6,61 @@ model = "Toradex Colibri T20 512MB on Iris"; compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; }; }; - pinmux { + pinmux@70000014 { state_default: pinmux { hdint { - nvidia,tristate = <0>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; i2cddc { - nvidia,tristate = <0>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdio4 { - nvidia,tristate = <0>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; uarta { - nvidia,tristate = <0>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; uartd { - nvidia,tristate = <0>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; }; }; - usb@c5000000 { + serial@70006000 { status = "okay"; }; - usb-phy@c5000000 { + serial@70006300 { status = "okay"; }; - usb@c5008000 { + i2c_ddc: i2c@7000c400 { status = "okay"; }; - usb-phy@c5008000 { + usb@c5000000 { status = "okay"; }; - serial@70006000 { + usb-phy@c5000000 { status = "okay"; }; - serial@70006300 { + usb@c5008000 { status = "okay"; }; - i2c_ddc: i2c@7000c400 { + usb-phy@c5008000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index 7580578..6d3a4cb 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -6,7 +6,7 @@ model = "Avionic Design Medcom-Wide board"; compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; - pwm { + pwm@7000a000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 8d71fc9..c7cd8e6 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -1,17 +1,23 @@ /dts-v1/; +#include <dt-bindings/input/input.h> #include "tegra20.dtsi" / { model = "Toshiba AC100 / Dynabook AZ"; compatible = "compal,paz00", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x20000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&hdmi_vdd_reg>; @@ -23,7 +29,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -177,39 +183,39 @@ "gpu", "gpu7", "gpv", "i2cp", "pta", "rm", "sdio1", "slxk", "spdo", "uac", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; }; conf_crtp { nvidia,pins = "crtp", "dap3", "dap4", "dtb", "dtc", "dte", "slxa", "slxc", "slxd", "spdi"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_csus { nvidia,pins = "csus", "spia", "spib", "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_ddc { nvidia,pins = "ddc", "irrx", "irtx", "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf", "spic", "spig", "uaa", "uab"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_dta { nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", "spie", "spih", "uad", "uca", "ucb"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_hdint { nvidia,pins = "hdint", "ld0", "ld1", "ld2", @@ -218,23 +224,23 @@ "ld13", "ld14", "ld15", "ld16", "ld17", "ldc", "ldi", "lhs", "lsc0", "lspi", "lvs", "pmc"; - nvidia,tristate = <0>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_lc { nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; }; conf_lcsn { nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", "lm0", "lm1", "lpp", "lpw0", "lpw1", "lpw2", "lsc1", "lsck", "lsda", "lsdi", "lvp0", "lvp1", "sdb"; - nvidia,tristate = <1>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; }; }; }; @@ -268,7 +274,7 @@ clock-frequency = <100000>; }; - nvec { + nvec@7000c500 { compatible = "nvidia,nvec"; reg = <0x7000c500 0x100>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; @@ -280,6 +286,8 @@ clocks = <&tegra_car TEGRA20_CLK_I2C3>, <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; }; i2c@7000d000 { @@ -415,7 +423,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <2000>; @@ -472,7 +480,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; @@ -486,7 +494,7 @@ power { label = "Power"; gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; - linux,code = <116>; /* KEY_POWER */ + linux,code = <KEY_POWER>; gpio-key,wakeup; }; }; diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts index d7a358a..29051a2 100644 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -6,8 +6,8 @@ model = "Avionic Design Plutux board"; compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 315aae2..a11b6e7 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -1,17 +1,23 @@ /dts-v1/; +#include <dt-bindings/input/input.h> #include "tegra20.dtsi" / { model = "NVIDIA Seaboard"; compatible = "nvidia,seaboard", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x40000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&hdmi_vdd_reg>; @@ -23,7 +29,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -189,53 +195,53 @@ "irtx", "pta", "rm", "sdc", "sdd", "slxd", "slxk", "spdi", "spdo", "uac", "uad", "uca", "ucb", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_ate { nvidia,pins = "ate", "csus", "dap3", "gpv", "owc", "slxc", "spib", "spid", "spie"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; }; conf_crtp { nvidia,pins = "crtp", "gmb", "slxa", "spia", "spig", "spih"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_dta { nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = <1>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_dte { nvidia,pins = "dte", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_hdint { nvidia,pins = "hdint", "lcsn", "ldc", "lm1", "lpw1", "lsc1", "lsck", "lsda", "lsdi", "lvp0"; - nvidia,tristate = <1>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_kbca { nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf", "sdio1", "spic", "uaa", "uab"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_lc { nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; }; conf_ld0 { nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", @@ -245,22 +251,22 @@ "lhp1", "lhp2", "lhs", "lm0", "lpp", "lpw0", "lpw2", "lsc0", "lspi", "lvp1", "lvs", "pmc", "sdb"; - nvidia,tristate = <0>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; }; drive_sdio1 { nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <0>; - nvidia,low-power-mode = <3>; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; nvidia,pull-down-strength = <31>; nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = <3>; - nvidia,slew-rate-falling = <3>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; }; }; @@ -386,6 +392,13 @@ status = "okay"; clock-frequency = <400000>; + magnetometer@c { + compatible = "ak,ak8975"; + reg = <0xc>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; + }; + pmic: tps6586x@34 { compatible = "ti,tps6586x"; reg = <0x34>; @@ -507,16 +520,149 @@ compatible = "onnn,nct1008"; reg = <0x4c>; }; + }; - magnetometer@c { - compatible = "ak,ak8975"; - reg = <0xc>; - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; - }; + kbc@7000e200 { + status = "okay"; + nvidia,debounce-delay-ms = <32>; + nvidia,repeat-delay-ms = <160>; + nvidia,ghost-filter; + nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; + linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W) + MATRIX_KEY(0x00, 0x03, KEY_S) + MATRIX_KEY(0x00, 0x04, KEY_A) + MATRIX_KEY(0x00, 0x05, KEY_Z) + MATRIX_KEY(0x00, 0x07, KEY_FN) + + MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA) + MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT) + MATRIX_KEY(0x02, 0x07, KEY_LEFTALT) + + MATRIX_KEY(0x03, 0x00, KEY_5) + MATRIX_KEY(0x03, 0x01, KEY_4) + MATRIX_KEY(0x03, 0x02, KEY_R) + MATRIX_KEY(0x03, 0x03, KEY_E) + MATRIX_KEY(0x03, 0x04, KEY_F) + MATRIX_KEY(0x03, 0x05, KEY_D) + MATRIX_KEY(0x03, 0x06, KEY_X) + + MATRIX_KEY(0x04, 0x00, KEY_7) + MATRIX_KEY(0x04, 0x01, KEY_6) + MATRIX_KEY(0x04, 0x02, KEY_T) + MATRIX_KEY(0x04, 0x03, KEY_H) + MATRIX_KEY(0x04, 0x04, KEY_G) + MATRIX_KEY(0x04, 0x05, KEY_V) + MATRIX_KEY(0x04, 0x06, KEY_C) + MATRIX_KEY(0x04, 0x07, KEY_SPACE) + + MATRIX_KEY(0x05, 0x00, KEY_9) + MATRIX_KEY(0x05, 0x01, KEY_8) + MATRIX_KEY(0x05, 0x02, KEY_U) + MATRIX_KEY(0x05, 0x03, KEY_Y) + MATRIX_KEY(0x05, 0x04, KEY_J) + MATRIX_KEY(0x05, 0x05, KEY_N) + MATRIX_KEY(0x05, 0x06, KEY_B) + MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH) + + MATRIX_KEY(0x06, 0x00, KEY_MINUS) + MATRIX_KEY(0x06, 0x01, KEY_0) + MATRIX_KEY(0x06, 0x02, KEY_O) + MATRIX_KEY(0x06, 0x03, KEY_I) + MATRIX_KEY(0x06, 0x04, KEY_L) + MATRIX_KEY(0x06, 0x05, KEY_K) + MATRIX_KEY(0x06, 0x06, KEY_COMMA) + MATRIX_KEY(0x06, 0x07, KEY_M) + + MATRIX_KEY(0x07, 0x01, KEY_EQUAL) + MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE) + MATRIX_KEY(0x07, 0x03, KEY_ENTER) + MATRIX_KEY(0x07, 0x07, KEY_MENU) + + MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT) + MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT) + + MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL) + MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL) + + MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE) + MATRIX_KEY(0x0B, 0x01, KEY_P) + MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE) + MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON) + MATRIX_KEY(0x0B, 0x04, KEY_SLASH) + MATRIX_KEY(0x0B, 0x05, KEY_DOT) + + MATRIX_KEY(0x0C, 0x00, KEY_F10) + MATRIX_KEY(0x0C, 0x01, KEY_F9) + MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE) + MATRIX_KEY(0x0C, 0x03, KEY_3) + MATRIX_KEY(0x0C, 0x04, KEY_2) + MATRIX_KEY(0x0C, 0x05, KEY_UP) + MATRIX_KEY(0x0C, 0x06, KEY_PRINT) + MATRIX_KEY(0x0C, 0x07, KEY_PAUSE) + + MATRIX_KEY(0x0D, 0x00, KEY_INSERT) + MATRIX_KEY(0x0D, 0x01, KEY_DELETE) + MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP ) + MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN) + MATRIX_KEY(0x0D, 0x05, KEY_RIGHT) + MATRIX_KEY(0x0D, 0x06, KEY_DOWN) + MATRIX_KEY(0x0D, 0x07, KEY_LEFT) + + MATRIX_KEY(0x0E, 0x00, KEY_F11) + MATRIX_KEY(0x0E, 0x01, KEY_F12) + MATRIX_KEY(0x0E, 0x02, KEY_F8) + MATRIX_KEY(0x0E, 0x03, KEY_Q) + MATRIX_KEY(0x0E, 0x04, KEY_F4) + MATRIX_KEY(0x0E, 0x05, KEY_F3) + MATRIX_KEY(0x0E, 0x06, KEY_1) + MATRIX_KEY(0x0E, 0x07, KEY_F7) + + MATRIX_KEY(0x0F, 0x00, KEY_ESC) + MATRIX_KEY(0x0F, 0x01, KEY_GRAVE) + MATRIX_KEY(0x0F, 0x02, KEY_F5) + MATRIX_KEY(0x0F, 0x03, KEY_TAB) + MATRIX_KEY(0x0F, 0x04, KEY_F1) + MATRIX_KEY(0x0F, 0x05, KEY_F2) + MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK) + MATRIX_KEY(0x0F, 0x07, KEY_F6) + + /* Software Handled Function Keys */ + MATRIX_KEY(0x14, 0x00, KEY_KP7) + + MATRIX_KEY(0x15, 0x00, KEY_KP9) + MATRIX_KEY(0x15, 0x01, KEY_KP8) + MATRIX_KEY(0x15, 0x02, KEY_KP4) + MATRIX_KEY(0x15, 0x04, KEY_KP1) + + MATRIX_KEY(0x16, 0x01, KEY_KPSLASH) + MATRIX_KEY(0x16, 0x02, KEY_KP6) + MATRIX_KEY(0x16, 0x03, KEY_KP5) + MATRIX_KEY(0x16, 0x04, KEY_KP3) + MATRIX_KEY(0x16, 0x05, KEY_KP2) + MATRIX_KEY(0x16, 0x07, KEY_KP0) + + MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK) + MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS) + MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS) + MATRIX_KEY(0x1B, 0x05, KEY_KPDOT) + + MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP) + + MATRIX_KEY(0x1D, 0x03, KEY_HOME) + MATRIX_KEY(0x1D, 0x04, KEY_END) + MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN) + MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP) + + MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK) + MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK) + MATRIX_KEY(0x1E, 0x02, KEY_MUTE) + + MATRIX_KEY(0x1F, 0x04, KEY_HELP)>; }; - pmc { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; @@ -621,7 +767,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; @@ -635,7 +781,7 @@ power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = <116>; /* KEY_POWER */ + linux,code = <KEY_POWER>; gpio-key,wakeup; }; @@ -649,145 +795,6 @@ }; }; - kbc { - status = "okay"; - nvidia,debounce-delay-ms = <32>; - nvidia,repeat-delay-ms = <160>; - nvidia,ghost-filter; - nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; - nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; - linux,keymap = <0x00020011 /* KEY_W */ - 0x0003001F /* KEY_S */ - 0x0004001E /* KEY_A */ - 0x0005002C /* KEY_Z */ - 0x000701d0 /* KEY_FN */ - - 0x0107007D /* KEY_LEFTMETA */ - 0x02060064 /* KEY_RIGHTALT */ - 0x02070038 /* KEY_LEFTALT */ - - 0x03000006 /* KEY_5 */ - 0x03010005 /* KEY_4 */ - 0x03020013 /* KEY_R */ - 0x03030012 /* KEY_E */ - 0x03040021 /* KEY_F */ - 0x03050020 /* KEY_D */ - 0x0306002D /* KEY_X */ - - 0x04000008 /* KEY_7 */ - 0x04010007 /* KEY_6 */ - 0x04020014 /* KEY_T */ - 0x04030023 /* KEY_H */ - 0x04040022 /* KEY_G */ - 0x0405002F /* KEY_V */ - 0x0406002E /* KEY_C */ - 0x04070039 /* KEY_SPACE */ - - 0x0500000A /* KEY_9 */ - 0x05010009 /* KEY_8 */ - 0x05020016 /* KEY_U */ - 0x05030015 /* KEY_Y */ - 0x05040024 /* KEY_J */ - 0x05050031 /* KEY_N */ - 0x05060030 /* KEY_B */ - 0x0507002B /* KEY_BACKSLASH */ - - 0x0600000C /* KEY_MINUS */ - 0x0601000B /* KEY_0 */ - 0x06020018 /* KEY_O */ - 0x06030017 /* KEY_I */ - 0x06040026 /* KEY_L */ - 0x06050025 /* KEY_K */ - 0x06060033 /* KEY_COMMA */ - 0x06070032 /* KEY_M */ - - 0x0701000D /* KEY_EQUAL */ - 0x0702001B /* KEY_RIGHTBRACE */ - 0x0703001C /* KEY_ENTER */ - 0x0707008B /* KEY_MENU */ - - 0x08040036 /* KEY_RIGHTSHIFT */ - 0x0805002A /* KEY_LEFTSHIFT */ - - 0x09050061 /* KEY_RIGHTCTRL */ - 0x0907001D /* KEY_LEFTCTRL */ - - 0x0B00001A /* KEY_LEFTBRACE */ - 0x0B010019 /* KEY_P */ - 0x0B020028 /* KEY_APOSTROPHE */ - 0x0B030027 /* KEY_SEMICOLON */ - 0x0B040035 /* KEY_SLASH */ - 0x0B050034 /* KEY_DOT */ - - 0x0C000044 /* KEY_F10 */ - 0x0C010043 /* KEY_F9 */ - 0x0C02000E /* KEY_BACKSPACE */ - 0x0C030004 /* KEY_3 */ - 0x0C040003 /* KEY_2 */ - 0x0C050067 /* KEY_UP */ - 0x0C0600D2 /* KEY_PRINT */ - 0x0C070077 /* KEY_PAUSE */ - - 0x0D00006E /* KEY_INSERT */ - 0x0D01006F /* KEY_DELETE */ - 0x0D030068 /* KEY_PAGEUP */ - 0x0D04006D /* KEY_PAGEDOWN */ - 0x0D05006A /* KEY_RIGHT */ - 0x0D06006C /* KEY_DOWN */ - 0x0D070069 /* KEY_LEFT */ - - 0x0E000057 /* KEY_F11 */ - 0x0E010058 /* KEY_F12 */ - 0x0E020042 /* KEY_F8 */ - 0x0E030010 /* KEY_Q */ - 0x0E04003E /* KEY_F4 */ - 0x0E05003D /* KEY_F3 */ - 0x0E060002 /* KEY_1 */ - 0x0E070041 /* KEY_F7 */ - - 0x0F000001 /* KEY_ESC */ - 0x0F010029 /* KEY_GRAVE */ - 0x0F02003F /* KEY_F5 */ - 0x0F03000F /* KEY_TAB */ - 0x0F04003B /* KEY_F1 */ - 0x0F05003C /* KEY_F2 */ - 0x0F06003A /* KEY_CAPSLOCK */ - 0x0F070040 /* KEY_F6 */ - - /* Software Handled Function Keys */ - 0x14000047 /* KEY_KP7 */ - - 0x15000049 /* KEY_KP9 */ - 0x15010048 /* KEY_KP8 */ - 0x1502004B /* KEY_KP4 */ - 0x1504004F /* KEY_KP1 */ - - 0x1601004E /* KEY_KPSLASH */ - 0x1602004D /* KEY_KP6 */ - 0x1603004C /* KEY_KP5 */ - 0x16040051 /* KEY_KP3 */ - 0x16050050 /* KEY_KP2 */ - 0x16070052 /* KEY_KP0 */ - - 0x1B010037 /* KEY_KPASTERISK */ - 0x1B03004A /* KEY_KPMINUS */ - 0x1B04004E /* KEY_KPPLUS */ - 0x1B050053 /* KEY_KPDOT */ - - 0x1C050073 /* KEY_VOLUMEUP */ - - 0x1D030066 /* KEY_HOME */ - 0x1D04006B /* KEY_END */ - 0x1D0500E0 /* KEY_BRIGHTNESSDOWN */ - 0x1D060072 /* KEY_VOLUMEDOWN */ - 0x1D0700E1 /* KEY_BRIGHTNESSUP */ - - 0x1E000045 /* KEY_NUMLOCK */ - 0x1E010046 /* KEY_SCROLLLOCK */ - 0x1E020071 /* KEY_MUTE */ - - 0x1F04008A>; /* KEY_HELP */ - }; regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 7726dab..a1b0d96 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -4,12 +4,17 @@ model = "Avionic Design Tamonten SOM"; compatible = "ad,tamonten", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x20000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { vdd-supply = <&hdmi_vdd_reg>; pll-supply = <&hdmi_pll_reg>; @@ -19,7 +24,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -176,50 +181,50 @@ "gmb", "gmc", "gmd", "gme", "gpu7", "gpv", "i2cp", "pta", "rm", "slxa", "slxk", "spia", "spib", "uac"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; }; conf_csus { nvidia,pins = "csus", "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_crtp { nvidia,pins = "crtp", "dap2", "dap3", "dap4", "dtc", "dte", "dtf", "gpu", "sdio1", "slxc", "slxd", "spdi", "spdo", "spig", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_ddc { nvidia,pins = "ddc", "dta", "dtd", "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf", "sdc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_hdint { nvidia,pins = "hdint", "lcsn", "ldc", "lm1", "lpw1", "lsc1", "lsck", "lsda", "lsdi", "lvp0", "owc", "sdb"; - nvidia,tristate = <1>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_irrx { nvidia,pins = "irrx", "irtx", "sdd", "spic", "spie", "spih", "uaa", "uab", "uad", "uca", "ucb"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_lc { nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; }; conf_ld0 { nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", @@ -229,12 +234,12 @@ "lhp1", "lhp2", "lhs", "lm0", "lpp", "lpw0", "lpw2", "lsc0", "lspi", "lvp1", "lvs", "pmc"; - nvidia,tristate = <0>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; }; }; @@ -457,7 +462,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; @@ -467,7 +472,7 @@ nvidia,sys-clock-req-active-high; }; - pcie-controller { + pcie-controller@80003000 { pex-clk-supply = <&pci_clk_reg>; vdd-supply = <&pci_vdd_reg>; }; @@ -492,7 +497,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 3ada3cb..890562c 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -6,8 +6,8 @@ model = "Avionic Design Tamonten Evaluation Carrier"; compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; }; }; @@ -32,7 +32,7 @@ }; }; - pcie-controller { + pcie-controller@80003000 { status = "okay"; pci@1,0 { diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 78deea5..216fa6d 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -1,17 +1,23 @@ /dts-v1/; +#include <dt-bindings/input/input.h> #include "tegra20.dtsi" / { model = "Compulab TrimSlice board"; compatible = "compulab,trimslice", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000c500/rtc@56"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x40000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&hdmi_vdd_reg>; @@ -23,7 +29,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -191,49 +197,49 @@ "dtb", "dtc", "dtd", "dte", "gmb", "gme", "i2cp", "pta", "slxc", "slxd", "spdi", "spdo", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_atb { nvidia,pins = "atb", "cdev1", "cdev2", "dap1", "gma", "gmc", "gmd", "gpu", "gpu7", "gpv", "sdio1", "slxa", "slxk", "uac"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; }; conf_csus { nvidia,pins = "csus", "spia", "spib", "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_ddc { nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_hdint { nvidia,pins = "hdint", "lcsn", "ldc", "lm1", "lpw1", "lsc1", "lsck", "lsda", "lsdi", "lvp0", "pmc"; - nvidia,tristate = <1>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_irrx { nvidia,pins = "irrx", "irtx", "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf", "owc", "spic", "spie", "spig", "spih", "uaa", "uab", "uad", "uca", "ucb"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_lc { nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; }; conf_ld0 { nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", @@ -243,17 +249,17 @@ "lhp1", "lhp2", "lhs", "lm0", "lpp", "lpw0", "lpw2", "lsc0", "lspi", "lvp1", "lvs", "sdb"; - nvidia,tristate = <0>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; }; conf_spif { nvidia,pins = "spif"; - nvidia,pull = <1>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; }; }; @@ -301,7 +307,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; nvidia,cpu-pwr-off-time = <5000>; @@ -310,7 +316,7 @@ nvidia,sys-clock-req-active-high; }; - pcie-controller { + pcie-controller@80003000 { status = "okay"; pex-clk-supply = <&pci_clk_reg>; vdd-supply = <&pci_vdd_reg>; @@ -366,7 +372,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; @@ -380,7 +386,7 @@ power { label = "Power"; gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; - linux,code = <116>; /* KEY_POWER */ + linux,code = <KEY_POWER>; gpio-key,wakeup; }; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index aab872c..571d12e 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -1,17 +1,23 @@ /dts-v1/; +#include <dt-bindings/input/input.h> #include "tegra20.dtsi" / { model = "NVIDIA Tegra20 Ventana evaluation board"; compatible = "nvidia,ventana", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x40000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&hdmi_vdd_reg>; @@ -23,7 +29,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -189,50 +195,50 @@ "irtx", "pta", "rm", "sdc", "sdd", "slxc", "slxd", "slxk", "spdi", "spdo", "uac", "uad", "uca", "ucb", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_ate { nvidia,pins = "ate", "csus", "dap3", "gmd", "gpv", "owc", "spia", "spib", "spic", "spid", "spie", "spig"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; }; conf_crtp { nvidia,pins = "crtp", "gmb", "slxa", "spih"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_dta { nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = <1>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_dte { nvidia,pins = "dte", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_hdint { nvidia,pins = "hdint", "lcsn", "ldc", "lm1", "lpw1", "lsck", "lsda", "lsdi", "lvp0"; - nvidia,tristate = <1>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_kbca { nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf", "sdio1", "uaa", "uab"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_lc { nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; }; conf_ld0 { nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", @@ -242,22 +248,22 @@ "lhp1", "lhp2", "lhs", "lm0", "lpp", "lpw0", "lpw2", "lsc0", "lsc1", "lspi", "lvp1", "lvs", "pmc", "sdb"; - nvidia,tristate = <0>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; }; drive_sdio1 { nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <1>; - nvidia,low-power-mode = <3>; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; nvidia,pull-down-strength = <31>; nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = <3>; - nvidia,slew-rate-falling = <3>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; }; }; @@ -492,7 +498,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <2000>; @@ -556,7 +562,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; @@ -570,7 +576,7 @@ power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = <116>; /* KEY_POWER */ + linux,code = <KEY_POWER>; gpio-key,wakeup; }; }; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index d33a73cf..1843725 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -1,17 +1,23 @@ /dts-v1/; +#include <dt-bindings/input/input.h> #include "tegra20.dtsi" / { model = "NVIDIA Tegra20 Whistler evaluation board"; compatible = "nvidia,whistler", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/max8907@3c"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x20000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&hdmi_vdd_reg>; @@ -23,7 +29,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -189,8 +195,8 @@ "kbcf", "sdc", "sdd", "spie", "spig", "spih", "uaa", "uab", "uad", "uca", "ucb"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_atd { nvidia,pins = "atd", "ate", "cdev1", "csus", @@ -198,54 +204,54 @@ "dtf", "gpu", "gpu7", "gpv", "i2cp", "rm", "sdio1", "slxa", "slxc", "slxd", "slxk", "spdi", "spdo", "uac", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_cdev2 { nvidia,pins = "cdev2", "spia", "spib"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "lc", "pmca", "pmcb", "pmcc", "pmcd", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; }; conf_crtp { nvidia,pins = "crtp"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_dta { nvidia,pins = "dta", "dtb", "dtc", "dtd", "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; conf_gme { nvidia,pins = "gme", "owc", "pta", "spic"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; }; conf_ls { nvidia,pins = "ls", "pmce"; - nvidia,pull = <2>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; }; drive_dap1 { nvidia,pins = "drive_dap1"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <1>; - nvidia,low-power-mode = <0>; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>; nvidia,pull-down-strength = <0>; nvidia,pull-up-strength = <0>; - nvidia,slew-rate-rising = <0>; - nvidia,slew-rate-falling = <0>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; }; }; }; @@ -495,7 +501,20 @@ }; }; - pmc { + kbc@7000e200 { + status = "okay"; + nvidia,debounce-delay-ms = <20>; + nvidia,repeat-delay-ms = <160>; + nvidia,kbc-row-pins = <0 1 2>; + nvidia,kbc-col-pins = <16 17>; + nvidia,wakeup-source; + linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER) + MATRIX_KEY(0x01, 0x00, KEY_HOME) + MATRIX_KEY(0x01, 0x01, KEY_BACK) + MATRIX_KEY(0x02, 0x01, KEY_MENU)>; + }; + + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <2000>; @@ -543,7 +562,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; @@ -551,25 +570,12 @@ }; }; - kbc { - status = "okay"; - nvidia,debounce-delay-ms = <20>; - nvidia,repeat-delay-ms = <160>; - nvidia,kbc-row-pins = <0 1 2>; - nvidia,kbc-col-pins = <16 17>; - nvidia,wakeup-source; - linux,keymap = <0x00000074 /* KEY_POWER */ - 0x01000066 /* KEY_HOME */ - 0x0101009E /* KEY_BACK */ - 0x0201008B>; /* KEY_MENU */ - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; - usb0_vbus_reg: regulator { + usb0_vbus_reg: regulator@0 { compatible = "regulator-fixed"; reg = <0>; regulator-name = "usb0_vbus"; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index df40b54..480ecda 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -1,5 +1,6 @@ #include <dt-bindings/clock/tegra20-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "skeleton.dtsi" @@ -16,57 +17,71 @@ serial4 = &uarte; }; - host1x { + host1x@50000000 { compatible = "nvidia,tegra20-host1x", "simple-bus"; reg = <0x50000000 0x00024000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ clocks = <&tegra_car TEGRA20_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; #address-cells = <1>; #size-cells = <1>; ranges = <0x54000000 0x54000000 0x04000000>; - mpe { + mpe@54040000 { compatible = "nvidia,tegra20-mpe"; reg = <0x54040000 0x00040000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&tegra_car 60>; + reset-names = "mpe"; }; - vi { + vi@54080000 { compatible = "nvidia,tegra20-vi"; reg = <0x54080000 0x00040000>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_VI>; + resets = <&tegra_car 20>; + reset-names = "vi"; }; - epp { + epp@540c0000 { compatible = "nvidia,tegra20-epp"; reg = <0x540c0000 0x00040000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_EPP>; + resets = <&tegra_car 19>; + reset-names = "epp"; }; - isp { + isp@54100000 { compatible = "nvidia,tegra20-isp"; reg = <0x54100000 0x00040000>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_ISP>; + resets = <&tegra_car 23>; + reset-names = "isp"; }; - gr2d { + gr2d@54140000 { compatible = "nvidia,tegra20-gr2d"; reg = <0x54140000 0x00040000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_GR2D>; + resets = <&tegra_car 21>; + reset-names = "2d"; }; - gr3d { + gr3d@54140000 { compatible = "nvidia,tegra20-gr3d"; - reg = <0x54180000 0x00040000>; + reg = <0x54140000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_GR3D>; + resets = <&tegra_car 24>; + reset-names = "3d"; }; dc@54200000 { @@ -75,7 +90,9 @@ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_DISP1>, <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "disp1", "parent"; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; rgb { status = "disabled"; @@ -88,24 +105,28 @@ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_DISP2>, <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "disp2", "parent"; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; rgb { status = "disabled"; }; }; - hdmi { + hdmi@54280000 { compatible = "nvidia,tegra20-hdmi"; reg = <0x54280000 0x00040000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_HDMI>, <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; status = "disabled"; }; - tvo { + tvo@542c0000 { compatible = "nvidia,tegra20-tvo"; reg = <0x542c0000 0x00040000>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; @@ -113,10 +134,12 @@ status = "disabled"; }; - dsi { + dsi@542c0000 { compatible = "nvidia,tegra20-dsi"; - reg = <0x54300000 0x00040000>; + reg = <0x542c0000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_DSI>; + resets = <&tegra_car 48>; + reset-names = "dsi"; status = "disabled"; }; }; @@ -129,7 +152,7 @@ clocks = <&tegra_car TEGRA20_CLK_TWD>; }; - intc: interrupt-controller { + intc: interrupt-controller@50041000 { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000 0x50040100 0x0100>; @@ -137,7 +160,7 @@ #interrupt-cells = <3>; }; - cache-controller { + cache-controller@50043000 { compatible = "arm,pl310-cache"; reg = <0x50043000 0x1000>; arm,data-latency = <5 5 2>; @@ -156,13 +179,14 @@ clocks = <&tegra_car TEGRA20_CLK_TIMER>; }; - tegra_car: clock { + tegra_car: clock@60006000 { compatible = "nvidia,tegra20-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; - apbdma: dma { + apbdma: dma@6000a000 { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, @@ -182,14 +206,17 @@ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; }; - ahb { + ahb@6000c004 { compatible = "nvidia,tegra20-ahb"; reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ }; - gpio: gpio { + gpio: gpio@6000d000 { compatible = "nvidia,tegra20-gpio"; reg = <0x6000d000 0x1000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, @@ -205,7 +232,7 @@ interrupt-controller; }; - pinmux: pinmux { + pinmux: pinmux@70000014 { compatible = "nvidia,tegra20-pinmux"; reg = <0x70000014 0x10 /* Tri-state registers */ 0x70000080 0x20 /* Mux registers */ @@ -213,17 +240,20 @@ 0x70000868 0xa8>; /* Pad control registers */ }; - das { + das@70000c00 { compatible = "nvidia,tegra20-das"; reg = <0x70000c00 0x80>; }; - tegra_ac97: ac97 { + tegra_ac97: ac97@70002000 { compatible = "nvidia,tegra20-ac97"; reg = <0x70002000 0x200>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 12>; clocks = <&tegra_car TEGRA20_CLK_AC97>; + resets = <&tegra_car 3>; + reset-names = "ac97"; + dmas = <&apbdma 12>, <&apbdma 12>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -231,8 +261,11 @@ compatible = "nvidia,tegra20-i2s"; reg = <0x70002800 0x200>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 2>; clocks = <&tegra_car TEGRA20_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; + dmas = <&apbdma 2>, <&apbdma 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -240,8 +273,11 @@ compatible = "nvidia,tegra20-i2s"; reg = <0x70002a00 0x200>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 1>; clocks = <&tegra_car TEGRA20_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; + dmas = <&apbdma 1>, <&apbdma 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -257,8 +293,11 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 8>; clocks = <&tegra_car TEGRA20_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -267,8 +306,11 @@ reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 9>; clocks = <&tegra_car TEGRA20_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -277,8 +319,11 @@ reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 10>; clocks = <&tegra_car TEGRA20_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -287,8 +332,11 @@ reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 19>; clocks = <&tegra_car TEGRA20_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -297,20 +345,25 @@ reg = <0x70006400 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 20>; clocks = <&tegra_car TEGRA20_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; status = "disabled"; }; - pwm: pwm { + pwm: pwm@7000a000 { compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; clocks = <&tegra_car TEGRA20_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; status = "disabled"; }; - rtc { + rtc@7000e000 { compatible = "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -326,6 +379,10 @@ clocks = <&tegra_car TEGRA20_CLK_I2C1>, <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -333,10 +390,13 @@ compatible = "nvidia,tegra20-sflash"; reg = <0x7000c380 0x80>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 11>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SPI>; + resets = <&tegra_car 43>; + reset-names = "spi"; + dmas = <&apbdma 11>, <&apbdma 11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -349,6 +409,10 @@ clocks = <&tegra_car TEGRA20_CLK_I2C2>, <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -361,6 +425,10 @@ clocks = <&tegra_car TEGRA20_CLK_I2C3>, <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -373,6 +441,10 @@ clocks = <&tegra_car TEGRA20_CLK_DVC>, <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -380,10 +452,13 @@ compatible = "nvidia,tegra20-slink"; reg = <0x7000d400 0x200>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 15>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SBC1>; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -391,10 +466,13 @@ compatible = "nvidia,tegra20-slink"; reg = <0x7000d600 0x200>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 16>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SBC2>; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -402,10 +480,13 @@ compatible = "nvidia,tegra20-slink"; reg = <0x7000d800 0x200>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SBC3>; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -413,22 +494,27 @@ compatible = "nvidia,tegra20-slink"; reg = <0x7000da00 0x200>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 18>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SBC4>; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; status = "disabled"; }; - kbc { + kbc@7000e200 { compatible = "nvidia,tegra20-kbc"; reg = <0x7000e200 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_KBC>; + resets = <&tegra_car 36>; + reset-names = "kbc"; status = "disabled"; }; - pmc { + pmc@7000e400 { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; @@ -442,7 +528,7 @@ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; }; - iommu { + iommu@7000f024 { compatible = "nvidia,tegra20-gart"; reg = <0x7000f024 0x00000018 /* controller registers */ 0x58000000 0x02000000>; /* GART aperture */ @@ -455,7 +541,7 @@ #size-cells = <0>; }; - pcie-controller { + pcie-controller@80003000 { compatible = "nvidia,tegra20-pcie"; device_type = "pci"; reg = <0x80003000 0x00000800 /* PADS registers */ @@ -478,9 +564,12 @@ clocks = <&tegra_car TEGRA20_CLK_PEX>, <&tegra_car TEGRA20_CLK_AFI>, - <&tegra_car TEGRA20_CLK_PCIE_XCLK>, <&tegra_car TEGRA20_CLK_PLL_E>; - clock-names = "pex", "afi", "pcie_xclk", "pll_e"; + clock-names = "pex", "afi", "pll_e"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; status = "disabled"; pci@1,0 { @@ -517,6 +606,8 @@ phy_type = "utmi"; nvidia,has-legacy-mode; clocks = <&tegra_car TEGRA20_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; nvidia,needs-double-reset; nvidia,phy = <&phy1>; status = "disabled"; @@ -548,6 +639,8 @@ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>; + resets = <&tegra_car 58>; + reset-names = "usb"; nvidia,phy = <&phy2>; status = "disabled"; }; @@ -569,6 +662,8 @@ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA20_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; nvidia,phy = <&phy3>; status = "disabled"; }; @@ -597,6 +692,8 @@ reg = <0xc8000000 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; status = "disabled"; }; @@ -605,6 +702,8 @@ reg = <0xc8000200 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; status = "disabled"; }; @@ -613,6 +712,8 @@ reg = <0xc8000400 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; status = "disabled"; }; @@ -621,6 +722,8 @@ reg = <0xc8000600 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 08cad69..e93fe45b 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -6,11 +6,16 @@ model = "NVIDIA Tegra30 Beaver evaluation board"; compatible = "nvidia,beaver", "nvidia,tegra30"; + aliases { + rtc0 = "/i2c@7000d000/tps65911@2d"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x80000000 0x7ff00000>; }; - pcie-controller { + pcie-controller@00003000 { status = "okay"; pex-clk-supply = <&sys_3v3_pexs_reg>; vdd-supply = <&ldo1_reg>; @@ -31,8 +36,8 @@ }; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&sys_3v3_reg>; @@ -44,7 +49,7 @@ }; }; - pinmux { + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -52,8 +57,8 @@ sdmmc1_clk_pz0 { nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc1_cmd_pz1 { nvidia,pins = "sdmmc1_cmd_pz1", @@ -62,14 +67,14 @@ "sdmmc1_dat2_py5", "sdmmc1_dat3_py4"; nvidia,function = "sdmmc1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc3_cmd_pa7 { nvidia,pins = "sdmmc3_cmd_pa7", @@ -78,15 +83,15 @@ "sdmmc3_dat2_pb5", "sdmmc3_dat3_pb4"; nvidia,function = "sdmmc3"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc4_clk_pcc4 { nvidia,pins = "sdmmc4_clk_pcc4", "sdmmc4_rst_n_pcc3"; nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc4_dat0_paa0 { nvidia,pins = "sdmmc4_dat0_paa0", @@ -98,8 +103,8 @@ "sdmmc4_dat6_paa6", "sdmmc4_dat7_paa7"; nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; dap2_fs_pa2 { nvidia,pins = "dap2_fs_pa2", @@ -107,18 +112,18 @@ "dap2_din_pa4", "dap2_dout_pa5"; nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; pex_l1_prsnt_n_pdd4 { nvidia,pins = "pex_l1_prsnt_n_pdd4", "pex_l1_clkreq_n_pdd6"; - nvidia,pull = <2>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; }; sdio3 { nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <0>; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; nvidia,pull-down-strength = <46>; nvidia,pull-up-strength = <42>; nvidia,slew-rate-rising = <1>; @@ -159,7 +164,7 @@ status = "okay"; clock-frequency = <100000>; - rt5640: rt5640 { + rt5640: rt5640@1c { compatible = "realtek,rt5640"; reg = <0x1c>; interrupt-parent = <&gpio>; @@ -168,19 +173,6 @@ <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; }; - tps62361 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - }; - pmic: tps65911@2d { compatible = "ti,tps65911"; reg = <0x2d>; @@ -284,6 +276,19 @@ }; }; }; + + tps62361@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + }; }; spi@7000da00 { @@ -296,13 +301,7 @@ }; }; - ahub { - i2s@70080400 { - status = "okay"; - }; - }; - - pmc { + pmc@7000e400 { status = "okay"; nvidia,invert-interrupt; nvidia,suspend-mode = <1>; @@ -314,6 +313,12 @@ nvidia,sys-clock-req-active-high; }; + ahub@70080000 { + i2s@70080400 { + status = "okay"; + }; + }; + sdhci@78000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; @@ -328,6 +333,15 @@ non-removable; }; + usb@7d004000 { + status = "okay"; + }; + + phy2: usb-phy@7d004000 { + vbus-supply = <&sys_3v3_reg>; + status = "okay"; + }; + usb@7d008000 { status = "okay"; }; @@ -342,7 +356,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; @@ -350,6 +364,19 @@ }; }; + gpio-leds { + compatible = "gpio-leds"; + + gpled1 { + label = "LED1"; /* CR5A1 (blue) */ + gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; + }; + gpled2 { + label = "LED2"; /* CR4A2 (green) */ + gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -453,19 +480,6 @@ }; }; - gpio-leds { - compatible = "gpio-leds"; - - gpled1 { - label = "LED1"; /* CR5A1 (blue) */ - gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; - }; - gpled2 { - label = "LED2"; /* CR4A2 (green) */ - gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; - }; - }; - sound { compatible = "nvidia,tegra-audio-rt5640-beaver", "nvidia,tegra-audio-rt5640"; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts index 1082c5e..c9bfedc 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -8,6 +8,13 @@ model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; + sdhci@78000400 { + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -83,12 +90,5 @@ gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; }; }; - - sdhci@78000400 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index bf012bdd..fadf55e 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -8,6 +8,13 @@ model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; + sdhci@78000400 { + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -95,11 +102,4 @@ gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; }; }; - - sdhci@78000400 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 5ea7dfa..9104224 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -27,11 +27,16 @@ model = "NVIDIA Tegra30 Cardhu evaluation board"; compatible = "nvidia,cardhu", "nvidia,tegra30"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x80000000 0x40000000>; }; - pcie-controller { + pcie-controller@00003000 { status = "okay"; pex-clk-supply = <&pex_hvdd_3v3_reg>; vdd-supply = <&ldo1_reg>; @@ -51,7 +56,17 @@ }; }; - pinmux { + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + }; + + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -59,8 +74,8 @@ sdmmc1_clk_pz0 { nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc1_cmd_pz1 { nvidia,pins = "sdmmc1_cmd_pz1", @@ -69,14 +84,14 @@ "sdmmc1_dat2_py5", "sdmmc1_dat3_py4"; nvidia,function = "sdmmc1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc3_cmd_pa7 { nvidia,pins = "sdmmc3_cmd_pa7", @@ -85,15 +100,15 @@ "sdmmc3_dat2_pb5", "sdmmc3_dat3_pb4"; nvidia,function = "sdmmc3"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc4_clk_pcc4 { nvidia,pins = "sdmmc4_clk_pcc4", "sdmmc4_rst_n_pcc3"; nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc4_dat0_paa0 { nvidia,pins = "sdmmc4_dat0_paa0", @@ -105,8 +120,8 @@ "sdmmc4_dat6_paa6", "sdmmc4_dat7_paa7"; nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; dap2_fs_pa2 { nvidia,pins = "dap2_fs_pa2", @@ -114,17 +129,17 @@ "dap2_din_pa4", "dap2_dout_pa5"; nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdio3 { nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <0>; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; nvidia,pull-down-strength = <46>; nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = <1>; - nvidia,slew-rate-falling = <1>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; }; uart3_txd_pw6 { nvidia,pins = "uart3_txd_pw6", @@ -132,8 +147,8 @@ "uart3_rts_n_pc0", "uart3_rxd_pw7"; nvidia,function = "uartc"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; }; }; @@ -147,7 +162,11 @@ status = "okay"; }; - i2c@7000c000 { + pwm@7000a000 { + status = "okay"; + }; + + panelddc: i2c@7000c000 { status = "okay"; clock-frequency = <100000>; }; @@ -302,7 +321,7 @@ interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>; }; - tps62361 { + tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; @@ -326,13 +345,7 @@ }; }; - ahub { - i2s@70080400 { - status = "okay"; - }; - }; - - pmc { + pmc@7000e400 { status = "okay"; nvidia,invert-interrupt; nvidia,suspend-mode = <1>; @@ -344,6 +357,12 @@ nvidia,sys-clock-req-active-high; }; + ahub@70080000 { + i2s@70080400 { + status = "okay"; + }; + }; + sdhci@78000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; @@ -367,12 +386,23 @@ status = "okay"; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; @@ -380,6 +410,16 @@ }; }; + panel: panel { + compatible = "chunghwa,claa101wb01", "simple-panel"; + ddc-i2c-bus = <&panelddc>; + + power-supply = <&vdd_pnl1_reg>; + enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 2bd55cf..ed8e770 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -1,5 +1,6 @@ #include <dt-bindings/clock/tegra30-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "skeleton.dtsi" @@ -16,7 +17,7 @@ serial4 = &uarte; }; - pcie-controller { + pcie-controller@00003000 { compatible = "nvidia,tegra30-pcie"; device_type = "pci"; reg = <0x00003000 0x00000800 /* PADS registers */ @@ -40,10 +41,13 @@ clocks = <&tegra_car TEGRA30_CLK_PCIE>, <&tegra_car TEGRA30_CLK_AFI>, - <&tegra_car TEGRA30_CLK_PCIEX>, <&tegra_car TEGRA30_CLK_PLL_E>, <&tegra_car TEGRA30_CLK_CML0>; - clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml"; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; status = "disabled"; pci@1,0 { @@ -86,59 +90,74 @@ }; }; - host1x { + host1x@50000000 { compatible = "nvidia,tegra30-host1x", "simple-bus"; reg = <0x50000000 0x00024000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ clocks = <&tegra_car TEGRA30_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; #address-cells = <1>; #size-cells = <1>; ranges = <0x54000000 0x54000000 0x04000000>; - mpe { + mpe@54040000 { compatible = "nvidia,tegra30-mpe"; reg = <0x54040000 0x00040000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_MPE>; + resets = <&tegra_car 60>; + reset-names = "mpe"; }; - vi { + vi@54080000 { compatible = "nvidia,tegra30-vi"; reg = <0x54080000 0x00040000>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_VI>; + resets = <&tegra_car 20>; + reset-names = "vi"; }; - epp { + epp@540c0000 { compatible = "nvidia,tegra30-epp"; reg = <0x540c0000 0x00040000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_EPP>; + resets = <&tegra_car 19>; + reset-names = "epp"; }; - isp { + isp@54100000 { compatible = "nvidia,tegra30-isp"; reg = <0x54100000 0x00040000>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_ISP>; + resets = <&tegra_car 23>; + reset-names = "isp"; }; - gr2d { + gr2d@54140000 { compatible = "nvidia,tegra30-gr2d"; reg = <0x54140000 0x00040000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + resets = <&tegra_car 21>; + reset-names = "2d"; clocks = <&tegra_car TEGRA30_CLK_GR2D>; }; - gr3d { + gr3d@54180000 { compatible = "nvidia,tegra30-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA30_CLK_GR3D &tegra_car TEGRA30_CLK_GR3D2>; clock-names = "3d", "3d2"; + resets = <&tegra_car 24>, + <&tegra_car 98>; + reset-names = "3d", "3d2"; }; dc@54200000 { @@ -147,7 +166,9 @@ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_DISP1>, <&tegra_car TEGRA30_CLK_PLL_P>; - clock-names = "disp1", "parent"; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; rgb { status = "disabled"; @@ -160,24 +181,28 @@ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_DISP2>, <&tegra_car TEGRA30_CLK_PLL_P>; - clock-names = "disp2", "parent"; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; rgb { status = "disabled"; }; }; - hdmi { + hdmi@54280000 { compatible = "nvidia,tegra30-hdmi"; reg = <0x54280000 0x00040000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_HDMI>, <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; status = "disabled"; }; - tvo { + tvo@542c0000 { compatible = "nvidia,tegra30-tvo"; reg = <0x542c0000 0x00040000>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; @@ -185,10 +210,12 @@ status = "disabled"; }; - dsi { + dsi@54300000 { compatible = "nvidia,tegra30-dsi"; reg = <0x54300000 0x00040000>; clocks = <&tegra_car TEGRA30_CLK_DSIA>; + resets = <&tegra_car 48>; + reset-names = "dsi"; status = "disabled"; }; }; @@ -201,7 +228,7 @@ clocks = <&tegra_car TEGRA30_CLK_TWD>; }; - intc: interrupt-controller { + intc: interrupt-controller@50041000 { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000 0x50040100 0x0100>; @@ -209,7 +236,7 @@ #interrupt-cells = <3>; }; - cache-controller { + cache-controller@50043000 { compatible = "arm,pl310-cache"; reg = <0x50043000 0x1000>; arm,data-latency = <6 6 2>; @@ -230,13 +257,14 @@ clocks = <&tegra_car TEGRA30_CLK_TIMER>; }; - tegra_car: clock { + tegra_car: clock@60006000 { compatible = "nvidia,tegra30-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; - apbdma: dma { + apbdma: dma@6000a000 { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, @@ -272,14 +300,17 @@ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; }; - ahb: ahb { + ahb: ahb@6000c004 { compatible = "nvidia,tegra30-ahb"; reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ }; - gpio: gpio { + gpio: gpio@6000d000 { compatible = "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, @@ -296,7 +327,7 @@ interrupt-controller; }; - pinmux: pinmux { + pinmux: pinmux@70000868 { compatible = "nvidia,tegra30-pinmux"; reg = <0x70000868 0xd4 /* Pad control registers */ 0x70003000 0x3e4>; /* Mux registers */ @@ -315,8 +346,11 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 8>; clocks = <&tegra_car TEGRA30_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -325,8 +359,11 @@ reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 9>; clocks = <&tegra_car TEGRA30_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -335,8 +372,11 @@ reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 10>; clocks = <&tegra_car TEGRA30_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -345,8 +385,11 @@ reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 19>; clocks = <&tegra_car TEGRA30_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -355,20 +398,25 @@ reg = <0x70006400 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 20>; clocks = <&tegra_car TEGRA30_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; status = "disabled"; }; - pwm: pwm { + pwm: pwm@7000a000 { compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; clocks = <&tegra_car TEGRA30_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; status = "disabled"; }; - rtc { + rtc@7000e000 { compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -384,6 +432,10 @@ clocks = <&tegra_car TEGRA30_CLK_I2C1>, <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -396,6 +448,10 @@ clocks = <&tegra_car TEGRA30_CLK_I2C2>, <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -408,6 +464,10 @@ clocks = <&tegra_car TEGRA30_CLK_I2C3>, <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -419,7 +479,11 @@ #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_I2C4>, <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; + resets = <&tegra_car 103>; + reset-names = "i2c"; clock-names = "div-clk", "fast-clk"; + dmas = <&apbdma 26>, <&apbdma 26>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -432,6 +496,10 @@ clocks = <&tegra_car TEGRA30_CLK_I2C5>, <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -439,10 +507,13 @@ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000d400 0x200>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 15>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC1>; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -450,10 +521,13 @@ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000d600 0x200>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 16>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC2>; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -461,10 +535,13 @@ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000d800 0x200>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC3>; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -472,10 +549,13 @@ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000da00 0x200>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 18>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC4>; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -483,10 +563,13 @@ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000dc00 0x200>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 27>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC5>; + resets = <&tegra_car 104>; + reset-names = "spi"; + dmas = <&apbdma 27>, <&apbdma 27>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -494,29 +577,34 @@ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000de00 0x200>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 28>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC6>; + resets = <&tegra_car 106>; + reset-names = "spi"; + dmas = <&apbdma 28>, <&apbdma 28>; + dma-names = "rx", "tx"; status = "disabled"; }; - kbc { + kbc@7000e200 { compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; reg = <0x7000e200 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_KBC>; + resets = <&tegra_car 36>; + reset-names = "kbc"; status = "disabled"; }; - pmc { + pmc@7000e400 { compatible = "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; }; - memory-controller { + memory-controller@7000f000 { compatible = "nvidia,tegra30-mc"; reg = <0x7000f000 0x010 0x7000f03c 0x1b4 @@ -525,7 +613,7 @@ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; }; - iommu { + iommu@7000f010 { compatible = "nvidia,tegra30-smmu"; reg = <0x7000f010 0x02c 0x7000f1f0 0x010 @@ -535,26 +623,34 @@ nvidia,ahb = <&ahb>; }; - ahub { + ahub@70080000 { compatible = "nvidia,tegra30-ahub"; reg = <0x70080000 0x200 0x70080200 0x100>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 1>; clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, - <&tegra_car TEGRA30_CLK_APBIF>, - <&tegra_car TEGRA30_CLK_I2S0>, - <&tegra_car TEGRA30_CLK_I2S1>, - <&tegra_car TEGRA30_CLK_I2S2>, - <&tegra_car TEGRA30_CLK_I2S3>, - <&tegra_car TEGRA30_CLK_I2S4>, - <&tegra_car TEGRA30_CLK_DAM0>, - <&tegra_car TEGRA30_CLK_DAM1>, - <&tegra_car TEGRA30_CLK_DAM2>, - <&tegra_car TEGRA30_CLK_SPDIF_IN>; - clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + <&tegra_car TEGRA30_CLK_APBIF>; + clock-names = "d_audio", "apbif"; + resets = <&tegra_car 106>, /* d_audio */ + <&tegra_car 107>, /* apbif */ + <&tegra_car 30>, /* i2s0 */ + <&tegra_car 11>, /* i2s1 */ + <&tegra_car 18>, /* i2s2 */ + <&tegra_car 101>, /* i2s3 */ + <&tegra_car 102>, /* i2s4 */ + <&tegra_car 108>, /* dam0 */ + <&tegra_car 109>, /* dam1 */ + <&tegra_car 110>, /* dam2 */ + <&tegra_car 10>; /* spdif */ + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif_in"; + "spdif"; + dmas = <&apbdma 1>, <&apbdma 1>, + <&apbdma 2>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 3>, + <&apbdma 4>, <&apbdma 4>; + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", + "rx3", "tx3"; ranges; #address-cells = <1>; #size-cells = <1>; @@ -564,6 +660,8 @@ reg = <0x70080300 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks = <&tegra_car TEGRA30_CLK_I2S0>; + resets = <&tegra_car 30>; + reset-names = "i2s"; status = "disabled"; }; @@ -572,6 +670,8 @@ reg = <0x70080400 0x100>; nvidia,ahub-cif-ids = <5 5>; clocks = <&tegra_car TEGRA30_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; status = "disabled"; }; @@ -580,6 +680,8 @@ reg = <0x70080500 0x100>; nvidia,ahub-cif-ids = <6 6>; clocks = <&tegra_car TEGRA30_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; status = "disabled"; }; @@ -588,6 +690,8 @@ reg = <0x70080600 0x100>; nvidia,ahub-cif-ids = <7 7>; clocks = <&tegra_car TEGRA30_CLK_I2S3>; + resets = <&tegra_car 101>; + reset-names = "i2s"; status = "disabled"; }; @@ -596,6 +700,8 @@ reg = <0x70080700 0x100>; nvidia,ahub-cif-ids = <8 8>; clocks = <&tegra_car TEGRA30_CLK_I2S4>; + resets = <&tegra_car 102>; + reset-names = "i2s"; status = "disabled"; }; }; @@ -605,6 +711,8 @@ reg = <0x78000000 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; status = "disabled"; }; @@ -613,6 +721,8 @@ reg = <0x78000200 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; status = "disabled"; }; @@ -621,6 +731,8 @@ reg = <0x78000400 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; status = "disabled"; }; @@ -629,6 +741,8 @@ reg = <0x78000600 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; status = "disabled"; }; @@ -638,6 +752,8 @@ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; nvidia,needs-double-reset; nvidia,phy = <&phy1>; status = "disabled"; @@ -669,20 +785,33 @@ compatible = "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d004000 0x4000>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - phy_type = "ulpi"; + phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB2>; + resets = <&tegra_car 58>; + reset-names = "usb"; nvidia,phy = <&phy2>; status = "disabled"; }; phy2: usb-phy@7d004000 { compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d004000 0x4000>; - phy_type = "ulpi"; + reg = <0x7d004000 0x4000 0x7d000000 0x4000>; + phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB2>, <&tegra_car TEGRA30_CLK_PLL_U>, - <&tegra_car TEGRA30_CLK_CDEV2>; - clock-names = "reg", "pll_u", "ulpi-link"; + <&tegra_car TEGRA30_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <51>; + nvidia.xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + nvidia,xcvr-hsslew = <32>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; status = "disabled"; }; @@ -692,6 +821,8 @@ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; nvidia,phy = <&phy3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index e7f73b2..5d7681b 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -15,6 +15,25 @@ / { compatible = "xlnx,zynq-7000"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + clocks = <&clkc 3>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + clocks = <&clkc 3>; + }; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; @@ -65,6 +84,24 @@ interrupts = <0 50 4>; }; + gem0: ethernet@e000b000 { + compatible = "cdns,gem"; + reg = <0xe000b000 0x4000>; + status = "disabled"; + interrupts = <0 22 4>; + clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + + gem1: ethernet@e000c000 { + compatible = "cdns,gem"; + reg = <0xe000c000 0x4000>; + status = "disabled"; + interrupts = <0 45 4>; + clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + slcr: slcr@f8000000 { compatible = "xlnx,zynq-slcr"; reg = <0xF8000000 0x1000>; @@ -106,7 +143,6 @@ compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; - clock-ranges; }; ttc1: ttc1@f8002000 { @@ -115,7 +151,6 @@ compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; - clock-ranges; }; scutimer: scutimer@f8f00600 { interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 21aea99..34d680a 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -29,6 +29,11 @@ }; +&gem0 { + status = "okay"; + phy-mode = "rgmii"; +}; + &uart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index 79009e0..b2835d5 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -30,6 +30,11 @@ }; +&gem0 { + status = "okay"; + phy-mode = "rgmii"; +}; + &uart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts index d6acf2b..2eda068 100644 --- a/arch/arm/boot/dts/zynq-zed.dts +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -30,6 +30,11 @@ }; +&gem0 { + status = "okay"; + phy-mode = "rgmii"; +}; + &uart1 { status = "okay"; }; diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c index 26020a0..1e361ab 100644 --- a/arch/arm/common/mcpm_entry.c +++ b/arch/arm/common/mcpm_entry.c @@ -35,8 +35,7 @@ void mcpm_set_early_poke(unsigned cpu, unsigned cluster, unsigned long *poke = &mcpm_entry_early_pokes[cluster][cpu][0]; poke[0] = poke_phys_addr; poke[1] = poke_val; - __cpuc_flush_dcache_area((void *)poke, 8); - outer_clean_range(__pa(poke), __pa(poke + 2)); + __sync_cache_range_w(poke, 2 * sizeof(*poke)); } static const struct mcpm_platform_ops *platform_ops; @@ -167,7 +166,7 @@ void __mcpm_cpu_down(unsigned int cpu, unsigned int cluster) dmb(); mcpm_sync.clusters[cluster].cpus[cpu].cpu = CPU_DOWN; sync_cache_w(&mcpm_sync.clusters[cluster].cpus[cpu].cpu); - dsb_sev(); + sev(); } /* @@ -183,7 +182,7 @@ void __mcpm_outbound_leave_critical(unsigned int cluster, int state) dmb(); mcpm_sync.clusters[cluster].cluster = state; sync_cache_w(&mcpm_sync.clusters[cluster].cluster); - dsb_sev(); + sev(); } /* diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c index ce922d0..53c6a26 100644 --- a/arch/arm/common/timer-sp.c +++ b/arch/arm/common/timer-sp.c @@ -66,7 +66,7 @@ static long __init sp804_get_clock_rate(struct clk *clk) static void __iomem *sched_clock_base; -static u32 sp804_read(void) +static u64 notrace sp804_read(void) { return ~readl_relaxed(sched_clock_base + TIMER_VALUE); } @@ -104,7 +104,7 @@ void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, if (use_sched_clock) { sched_clock_base = base; - setup_sched_clock(sp804_read, 32, rate); + sched_clock_register(sp804_read, 32, rate); } } diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig index 1ce3994..cb26c62 100644 --- a/arch/arm/configs/ape6evm_defconfig +++ b/arch/arm/configs/ape6evm_defconfig @@ -13,7 +13,7 @@ CONFIG_EMBEDDED=y CONFIG_PERF_EVENTS=y CONFIG_SLAB=y # CONFIG_BLOCK is not set -CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_SHMOBILE_LEGACY=y CONFIG_ARCH_R8A73A4=y CONFIG_MACH_APE6EVM=y # CONFIG_ARM_THUMB is not set diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig index fae939d..9287a62 100644 --- a/arch/arm/configs/armadillo800eva_defconfig +++ b/arch/arm/configs/armadillo800eva_defconfig @@ -15,7 +15,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_SHMOBILE_LEGACY=y CONFIG_ARCH_R8A7740=y CONFIG_MACH_ARMADILLO800EVA=y # CONFIG_SH_TIMER_TMU is not set @@ -105,6 +105,7 @@ CONFIG_FB=y CONFIG_FB_SH_MOBILE_LCDC=y CONFIG_FB_SH_MOBILE_HDMI=y CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_LOGO=y @@ -130,6 +131,8 @@ CONFIG_DMADEVICES=y CONFIG_SH_DMAE=y CONFIG_UIO=y CONFIG_UIO_PDRV_GENIRQ=y +CONFIG_PWM=y +CONFIG_PWM_RENESAS_TPU=y # CONFIG_DNOTIFY is not set CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 690e892..0b4e9b5 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -22,7 +22,6 @@ CONFIG_SOC_AT91SAM9X5=y CONFIG_SOC_AT91SAM9N12=y CONFIG_MACH_AT91RM9200_DT=y CONFIG_MACH_AT91SAM9_DT=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_TIMER_HZ=128 CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig index 75502c4..bf05771 100644 --- a/arch/arm/configs/at91rm9200_defconfig +++ b/arch/arm/configs/at91rm9200_defconfig @@ -31,7 +31,6 @@ CONFIG_MACH_YL9200=y CONFIG_MACH_CPUAT91=y CONFIG_MACH_ECO920=y CONFIG_MTD_AT91_DATAFLASH_CARD=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_TIMER_HZ=100 # CONFIG_ARM_THUMB is not set CONFIG_PCCARD=y diff --git a/arch/arm/configs/at91sam9260_9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig index 69b6928..2cd8329 100644 --- a/arch/arm/configs/at91sam9260_9g20_defconfig +++ b/arch/arm/configs/at91sam9260_9g20_defconfig @@ -15,7 +15,6 @@ CONFIG_MACH_AT91SAM9260EK=y CONFIG_MACH_CAM60=y CONFIG_MACH_SAM9_L9260=y CONFIG_MACH_AFEB9260=y -CONFIG_MACH_QIL_A9260=y CONFIG_MACH_CPU9260=y CONFIG_MACH_FLEXIBITY=y CONFIG_MACH_AT91SAM9G20EK=y @@ -28,7 +27,6 @@ CONFIG_MACH_PCONTROL_G20=y CONFIG_MACH_GSIA18S=y CONFIG_MACH_SNAPPER_9260=y CONFIG_MACH_AT91SAM9_DT=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_SLOW_CLOCK=y # CONFIG_ARM_THUMB is not set CONFIG_AEABI=y diff --git a/arch/arm/configs/at91sam9261_9g10_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig index 9d35cd8..f80e993 100644 --- a/arch/arm/configs/at91sam9261_9g10_defconfig +++ b/arch/arm/configs/at91sam9261_9g10_defconfig @@ -18,7 +18,6 @@ CONFIG_ARCH_AT91=y CONFIG_ARCH_AT91SAM9261=y CONFIG_MACH_AT91SAM9261EK=y CONFIG_MACH_AT91SAM9G10EK=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y # CONFIG_ARM_THUMB is not set CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig index 08166cd..e181a50 100644 --- a/arch/arm/configs/at91sam9g45_defconfig +++ b/arch/arm/configs/at91sam9g45_defconfig @@ -18,7 +18,6 @@ CONFIG_ARCH_AT91=y CONFIG_ARCH_AT91SAM9G45=y CONFIG_MACH_AT91SAM9M10G45EK=y CONFIG_MACH_AT91SAM9_DT=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_SLOW_CLOCK=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set diff --git a/arch/arm/configs/at91sam9rl_defconfig b/arch/arm/configs/at91sam9rl_defconfig index 7cf8785..7b6f131 100644 --- a/arch/arm/configs/at91sam9rl_defconfig +++ b/arch/arm/configs/at91sam9rl_defconfig @@ -13,7 +13,6 @@ CONFIG_MODULE_UNLOAD=y CONFIG_ARCH_AT91=y CONFIG_ARCH_AT91SAM9RL=y CONFIG_MACH_AT91SAM9RLEK=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y # CONFIG_ARM_THUMB is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig index 34e9780..f43392d 100644 --- a/arch/arm/configs/bcm2835_defconfig +++ b/arch/arm/configs/bcm2835_defconfig @@ -44,17 +44,26 @@ CONFIG_VFP=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_SUSPEND is not set CONFIG_NET=y +CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y CONFIG_NETWORK_SECMARK=y -# CONFIG_WIRELESS is not set +CONFIG_NETFILTER=y +CONFIG_CFG80211=y +CONFIG_MAC80211=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_NETDEVICES=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_SMSC95XX=y +CONFIG_ZD1211RW=y +CONFIG_INPUT_EVDEV=y # CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set CONFIG_SERIAL_AMBA_PL011=y @@ -71,15 +80,13 @@ CONFIG_FB=y CONFIG_FB_SIMPLE=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_USB_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_BCM2835=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_ONESHOT=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y @@ -88,6 +95,8 @@ CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=y CONFIG_LEDS_TRIGGER_CAMERA=y +CONFIG_STAGING=y +CONFIG_USB_DWC2=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y @@ -109,20 +118,20 @@ CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_UNUSED_SYMBOLS=y -CONFIG_LOCKUP_DETECTOR=y -CONFIG_DEBUG_INFO=y CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_LOCKUP_DETECTOR=y CONFIG_SCHED_TRACER=y CONFIG_STACK_TRACER=y CONFIG_FUNCTION_PROFILER=y -CONFIG_DYNAMIC_DEBUG=y +CONFIG_TEST_KSTRTOX=y CONFIG_KGDB=y CONFIG_KGDB_KDB=y -CONFIG_TEST_KSTRTOX=y CONFIG_STRICT_DEVMEM=y CONFIG_DEBUG_LL=y CONFIG_EARLY_PRINTK=y diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig index bede511..2c38fdf 100644 --- a/arch/arm/configs/bcm_defconfig +++ b/arch/arm/configs/bcm_defconfig @@ -29,11 +29,9 @@ CONFIG_ARCH_BCM_MOBILE=y CONFIG_ARM_THUMBEE=y CONFIG_PREEMPT=y CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set # CONFIG_COMPACTION is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ARM_APPENDED_DTB=y CONFIG_CMDLINE="console=ttyS0,115200n8 mem=128M" CONFIG_CPU_IDLE=y CONFIG_VFP=y @@ -120,6 +118,7 @@ CONFIG_DETECT_HUNG_TASK=y CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110 CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y # CONFIG_FTRACE is not set +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRC_CCITT=y CONFIG_CRC_T10DIF=y CONFIG_CRC_ITU_T=y diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig index b38cd10..80cff50 100644 --- a/arch/arm/configs/bockw_defconfig +++ b/arch/arm/configs/bockw_defconfig @@ -8,7 +8,7 @@ CONFIG_SYSCTL_SYSCALL=y CONFIG_EMBEDDED=y CONFIG_SLAB=y # CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_SHMOBILE_LEGACY=y CONFIG_ARCH_R8A7778=y CONFIG_MACH_BOCKW=y CONFIG_MEMORY_START=0x60000000 @@ -27,12 +27,12 @@ CONFIG_HIGHMEM=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y -CONFIG_CMDLINE="console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp" -CONFIG_CMDLINE_FORCE=y +CONFIG_VFP=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_SUSPEND is not set CONFIG_PM_RUNTIME=y CONFIG_NET=y +CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_PNP=y @@ -44,8 +44,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set @@ -82,6 +80,7 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y # CONFIG_HWMON is not set CONFIG_I2C=y CONFIG_I2C_RCAR=y +CONFIG_REGULATOR=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y @@ -108,11 +107,12 @@ CONFIG_MMC_SDHI=y CONFIG_MMC_SH_MMCIF=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_RX8581=y +CONFIG_DMADEVICES=y +CONFIG_RCAR_HPB_DMAE=y CONFIG_UIO=y CONFIG_UIO_PDRV_GENIRQ=y # CONFIG_IOMMU_SUPPORT is not set # CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY_USER is not set CONFIG_TMPFS=y # CONFIG_MISC_FILESYSTEMS is not set CONFIG_NFS_FS=y diff --git a/arch/arm/configs/efm32_defconfig b/arch/arm/configs/efm32_defconfig new file mode 100644 index 0000000..f59fffb --- /dev/null +++ b/arch/arm/configs/efm32_defconfig @@ -0,0 +1,102 @@ +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=12 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_UID16 is not set +# CONFIG_BASE_FULL is not set +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_MMU is not set +CONFIG_ARCH_EFM32=y +# CONFIG_KUSER_HELPERS is not set +CONFIG_SET_MEM_PARAM=y +CONFIG_DRAM_BASE=0x88000000 +CONFIG_DRAM_SIZE=0x00400000 +CONFIG_FLASH_MEM_BASE=0x8c000000 +CONFIG_FLASH_SIZE=0x01000000 +CONFIG_PREEMPT=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_XIP_KERNEL=y +CONFIG_XIP_PHYS_ADDR=0x8c000000 +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_SHARED_FLAT=y +# CONFIG_COREDUMP is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_BLOCK_RO=y +CONFIG_MTD_ROM=y +CONFIG_MTD_UCLINUX=y +CONFIG_PROC_DEVICETREE=y +# CONFIG_BLK_DEV is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +CONFIG_KS8851=y +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_UNIX98_PTYS is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_EFM32_UART=y +CONFIG_SERIAL_EFM32_UART_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_SPI=y +CONFIG_SPI_EFM32=y +CONFIG_GPIO_SYSFS=y +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_SPI=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_MTD=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index ad7dfbb..dbe1f1c 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -13,7 +13,7 @@ CONFIG_S3C24XX_PWM=y CONFIG_ARCH_EXYNOS5=y CONFIG_MACH_EXYNOS4_DT=y CONFIG_SMP=y -CONFIG_NR_CPUS=2 +CONFIG_NR_CPUS=8 CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_HIGHMEM=y @@ -79,6 +79,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MAX8997=y CONFIG_REGULATOR_MAX77686=y +CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y CONFIG_FB=y diff --git a/arch/arm/configs/genmai_defconfig b/arch/arm/configs/genmai_defconfig new file mode 100644 index 0000000..aa0b704 --- /dev/null +++ b/arch/arm/configs/genmai_defconfig @@ -0,0 +1,116 @@ +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +CONFIG_SLAB=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_SHMOBILE_LEGACY=y +CONFIG_ARCH_R7S72100=y +CONFIG_MACH_GENMAI=y +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +CONFIG_ARM_ERRATA_430973=y +CONFIG_ARM_ERRATA_458693=y +CONFIG_ARM_ERRATA_460075=y +CONFIG_ARM_ERRATA_743622=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_FORCE_MAX_ZONEORDER=13 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_KEXEC=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_NETDEVICES=y +# CONFIG_NET_CORE is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_SH_ETH=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=10 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C_SH_MOBILE=y +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_RCAR_THERMAL=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_DRM=y +CONFIG_DRM_RCAR_DU=y +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_SDHI=y +CONFIG_MMC_SH_MMCIF=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_RTC_CLASS=y +CONFIG_DMADEVICES=y +CONFIG_SH_DMAE=y +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_DNOTIFY is not set +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_CONFIGFS_FS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set diff --git a/arch/arm/configs/hi3xxx_defconfig b/arch/arm/configs/hi3xxx_defconfig new file mode 100644 index 0000000..f186bdf --- /dev/null +++ b/arch/arm/configs/hi3xxx_defconfig @@ -0,0 +1,56 @@ +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_RD_LZMA=y +CONFIG_ARCH_HI3xxx=y +CONFIG_SMP=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_NET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_NETDEVICES=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_SPI=y +CONFIG_SPI_PL022=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_REGULATOR_GPIO=y +CONFIG_DRM=y +CONFIG_FB_SIMPLE=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_MMC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PL031=y +CONFIG_DMADEVICES=y +CONFIG_DW_DMAC=y +CONFIG_PL330_DMA=y +CONFIG_PWM=y +CONFIG_EXT4_FS=y +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_LOCKUP_DETECTOR=y diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index e958ebe..6309ee5 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -91,6 +91,7 @@ CONFIG_SMSC911X=y CONFIG_SMSC_PHY=y # CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_IMX=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y @@ -118,6 +119,7 @@ CONFIG_IMX2_WDT=y CONFIG_MFD_MC13XXX_SPI=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y CONFIG_MEDIA_SUPPORT=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 8d0c5a0..53e82c2 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -28,11 +28,13 @@ CONFIG_MACH_QONG=y CONFIG_MACH_ARMADILLO5X0=y CONFIG_MACH_KZM_ARM11_01=y CONFIG_MACH_IMX31_DT=y +CONFIG_MACH_IMX35_DT=y CONFIG_MACH_PCM043=y CONFIG_MACH_MX35_3DS=y CONFIG_MACH_VPR200=y CONFIG_MACH_IMX51_DT=y CONFIG_MACH_EUKREA_CPUIMX51SD=y +CONFIG_SOC_IMX50=y CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6SL=y @@ -41,7 +43,7 @@ CONFIG_SMP=y CONFIG_VMSPLIT_2G=y CONFIG_PREEMPT_VOLUNTARY=y CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" CONFIG_VFP=y CONFIG_NEON=y @@ -89,7 +91,6 @@ CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_SRAM=y CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=y # CONFIG_SCSI_PROC_FS is not set @@ -118,6 +119,7 @@ CONFIG_SMC91X=y CONFIG_SMC911X=y CONFIG_SMSC911X=y # CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_AT803X_PHY=y CONFIG_BRCMFMAC=m # CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_EVDEV=y @@ -129,6 +131,8 @@ CONFIG_MOUSE_PS2_ELANTECH=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_EGALAX=y CONFIG_TOUCHSCREEN_MC13783=y +CONFIG_TOUCHSCREEN_TSC2007=y +CONFIG_TOUCHSCREEN_STMPE=y CONFIG_INPUT_MISC=y CONFIG_INPUT_MMA8450=y CONFIG_SERIO_SERPORT=m @@ -156,14 +160,19 @@ CONFIG_IMX2_WDT=y CONFIG_MFD_DA9052_I2C=y CONFIG_MFD_MC13XXX_SPI=y CONFIG_MFD_MC13XXX_I2C=y +CONFIG_MFD_STMPE=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_DA9052=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_PFUZE100=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_RC_SUPPORT=y +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_SOC_CAMERA=y CONFIG_VIDEO_MX3=y diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig index 9943e5d..a018244 100644 --- a/arch/arm/configs/keystone_defconfig +++ b/arch/arm/configs/keystone_defconfig @@ -115,6 +115,8 @@ CONFIG_MTD_UBI=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_EEPROM_AT24=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y CONFIG_NETDEVICES=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y @@ -129,10 +131,24 @@ CONFIG_SPI_DAVINCI=y CONFIG_SPI_SPIDEV=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y -# CONFIG_USB_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_MON=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_DEBUG=y +CONFIG_USB_DWC3_VERBOSE=y +CONFIG_KEYSTONE_USB_PHY=y CONFIG_DMADEVICES=y CONFIG_COMMON_CLK_DEBUG=y CONFIG_MEMORY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_WBUF_VERIFY=y @@ -144,6 +160,8 @@ CONFIG_ROOT_NFS=y CONFIG_NFSD=y CONFIG_NFSD_V3=y CONFIG_NFSD_V3_ACL=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_SHIRQ=y CONFIG_DEBUG_INFO=y diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index 0ae0eaeb..2e762d9 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -27,6 +27,7 @@ CONFIG_PCI_MVEBU=y CONFIG_PREEMPT=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CPU_FREQ=y diff --git a/arch/arm/configs/koelsch_defconfig b/arch/arm/configs/koelsch_defconfig index 825c16d..e248f49 100644 --- a/arch/arm/configs/koelsch_defconfig +++ b/arch/arm/configs/koelsch_defconfig @@ -9,7 +9,7 @@ CONFIG_EMBEDDED=y CONFIG_PERF_EVENTS=y CONFIG_SLAB=y # CONFIG_BLOCK is not set -CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_SHMOBILE_LEGACY=y CONFIG_ARCH_R8A7791=y CONFIG_MACH_KOELSCH=y # CONFIG_SWP_EMULATE is not set @@ -29,7 +29,29 @@ CONFIG_VFP=y CONFIG_NEON=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_SH_ETH=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_LEGACY_PTYS is not set @@ -45,10 +67,11 @@ CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y # CONFIG_IOMMU_SUPPORT is not set # CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY_USER is not set CONFIG_TMPFS=y CONFIG_CONFIGFS_FS=y # CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set # CONFIG_ARM_UNWIND is not set diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig index 6c37f4a..e42ce37 100644 --- a/arch/arm/configs/kzm9d_defconfig +++ b/arch/arm/configs/kzm9d_defconfig @@ -13,7 +13,7 @@ CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_SHMOBILE_LEGACY=y CONFIG_ARCH_EMEV2=y CONFIG_MACH_KZM9D=y CONFIG_MEMORY_START=0x40000000 @@ -32,6 +32,7 @@ CONFIG_FORCE_MAX_ZONEORDER=13 CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y +CONFIG_AUTO_ZRELADDR=y CONFIG_VFP=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_PM_RUNTIME=y diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig index 1ad0280..9934dbc 100644 --- a/arch/arm/configs/kzm9g_defconfig +++ b/arch/arm/configs/kzm9g_defconfig @@ -22,7 +22,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_SHMOBILE_LEGACY=y CONFIG_ARCH_SH73A0=y CONFIG_MACH_KZM9G=y CONFIG_MEMORY_START=0x41000000 diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig index 35bff5e..883443f 100644 --- a/arch/arm/configs/lager_defconfig +++ b/arch/arm/configs/lager_defconfig @@ -12,7 +12,7 @@ CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_SHMOBILE_LEGACY=y CONFIG_ARCH_R8A7790=y CONFIG_MACH_LAGER=y # CONFIG_SH_TIMER_TMU is not set @@ -80,7 +80,7 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_GPIO=y -CONFIG_I2C_SH_MOBILE=y +CONFIG_I2C_RCAR=y CONFIG_GPIO_SH_PFC=y CONFIG_GPIOLIB=y CONFIG_GPIO_RCAR=y @@ -89,6 +89,7 @@ CONFIG_THERMAL=y CONFIG_RCAR_THERMAL=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y CONFIG_DRM=y CONFIG_DRM_RCAR_DU=y # CONFIG_USB_SUPPORT is not set diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig index 9fb1189..a61e165 100644 --- a/arch/arm/configs/mackerel_defconfig +++ b/arch/arm/configs/mackerel_defconfig @@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_SHMOBILE_LEGACY=y CONFIG_ARCH_SH7372=y CONFIG_MACH_MACKEREL=y CONFIG_MEMORY_SIZE=0x10000000 diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig index 5cc6360..f21bd40 100644 --- a/arch/arm/configs/marzen_defconfig +++ b/arch/arm/configs/marzen_defconfig @@ -9,7 +9,7 @@ CONFIG_SYSCTL_SYSCALL=y CONFIG_EMBEDDED=y CONFIG_SLAB=y # CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_SHMOBILE_LEGACY=y CONFIG_ARCH_R8A7779=y CONFIG_MACH_MARZEN=y CONFIG_MEMORY_START=0x60000000 @@ -30,12 +30,12 @@ CONFIG_HIGHMEM=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y -CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on" -CONFIG_CMDLINE_FORCE=y +CONFIG_VFP=y CONFIG_KEXEC=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_PM_RUNTIME=y CONFIG_NET=y +CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_PNP=y @@ -43,8 +43,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set @@ -61,7 +59,6 @@ CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_SEEQ is not set -CONFIG_SMC911X=y CONFIG_SMSC911X=y # CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_WLAN is not set @@ -106,11 +103,12 @@ CONFIG_USB_STORAGE=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y +CONFIG_DMADEVICES=y +CONFIG_RCAR_HPB_DMAE=y CONFIG_UIO=y CONFIG_UIO_PDRV_GENIRQ=y # CONFIG_IOMMU_SUPPORT is not set # CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY_USER is not set CONFIG_TMPFS=y # CONFIG_MISC_FILESYSTEMS is not set CONFIG_NFS_FS=y diff --git a/arch/arm/configs/moxart_defconfig b/arch/arm/configs/moxart_defconfig new file mode 100644 index 0000000..a3cb76c --- /dev/null +++ b/arch/arm/configs/moxart_defconfig @@ -0,0 +1,149 @@ +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_ELF_CORE is not set +# CONFIG_BASE_FULL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_MULTI_V4T=y +# CONFIG_ARCH_MULTI_V7 is not set +CONFIG_KEYBOARD_GPIO_POLLED=y +CONFIG_ARCH_MOXART=y +CONFIG_MACH_UC7112LX=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +# CONFIG_ATAGS is not set +CONFIG_ARM_APPENDED_DTB=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_PROC_DEVICETREE=y +CONFIG_NETDEVICES=y +CONFIG_NETCONSOLE=y +CONFIG_NETCONSOLE_DYNAMIC=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +CONFIG_ARM_MOXART_ETHER=y +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_REALTEK_PHY=y +CONFIG_MDIO_MOXART=y +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_MOXART=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_MOXART_WDT=y +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_SDHCI_MOXART=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MOXART=y +CONFIG_DMADEVICES=y +CONFIG_MOXART_DMA=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT3_FS=y +CONFIG_TMPFS=y +CONFIG_CONFIGFS_FS=y +CONFIG_JFFS2_FS=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_DEBUG_PAGEALLOC=y +CONFIG_DEBUG_OBJECTS=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_STACK_USAGE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_PROVE_LOCKING=y +CONFIG_DMA_API_DEBUG=y +CONFIG_KGDB=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_UART_8250=y +CONFIG_DEBUG_UART_PHYS=0x98200000 +CONFIG_DEBUG_UART_VIRT=0xf9820000 +CONFIG_EARLY_PRINTK=y +CONFIG_KEYS=y +CONFIG_CRC32_BIT=y diff --git a/arch/arm/configs/msm_defconfig b/arch/arm/configs/msm_defconfig index 690b5f9..0219c65 100644 --- a/arch/arm/configs/msm_defconfig +++ b/arch/arm/configs/msm_defconfig @@ -17,9 +17,10 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_PARTITION_ADVANCED=y -CONFIG_ARCH_MSM=y +CONFIG_ARCH_MSM_DT=y CONFIG_ARCH_MSM8X60=y CONFIG_ARCH_MSM8960=y +CONFIG_ARCH_MSM8974=y CONFIG_SMP=y CONFIG_PREEMPT=y CONFIG_AEABI=y @@ -29,7 +30,6 @@ CONFIG_CLEANCACHE=y CONFIG_CC_STACKPROTECTOR=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_AUTO_ZRELADDR=y CONFIG_VFP=y CONFIG_NEON=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set @@ -62,7 +62,6 @@ CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y -CONFIG_PHYLIB=y CONFIG_SLIP=y CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_MODE_SLIP6=y @@ -81,13 +80,15 @@ CONFIG_SERIO_LIBPS2=y CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_SPI=y -CONFIG_SSBI=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y CONFIG_POWER_SUPPLY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_MSM=y CONFIG_THERMAL=y CONFIG_REGULATOR=y CONFIG_MEDIA_SUPPORT=y @@ -101,7 +102,6 @@ CONFIG_SND_DYNAMIC_MINORS=y CONFIG_SND_SOC=y CONFIG_HID_BATTERY_STRENGTH=y CONFIG_USB=y -CONFIG_USB_PHY=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y @@ -128,10 +128,10 @@ CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_CIFS=y CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y CONFIG_LOCKUP_DETECTOR=y # CONFIG_DETECT_HUNG_TASK is not set # CONFIG_SCHED_DEBUG is not set CONFIG_TIMER_STATS=y -CONFIG_DEBUG_INFO=y -CONFIG_DYNAMIC_DEBUG=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index c1df4e9..687e4e8 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -7,8 +7,12 @@ CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_XP=y CONFIG_ARCH_BCM=y CONFIG_ARCH_BCM_MOBILE=y +CONFIG_ARCH_BERLIN=y +CONFIG_MACH_BERLIN_BG2=y +CONFIG_MACH_BERLIN_BG2CD=y CONFIG_GPIO_PCA953X=y CONFIG_ARCH_HIGHBANK=y +CONFIG_ARCH_HI3xxx=y CONFIG_ARCH_KEYSTONE=y CONFIG_ARCH_MXC=y CONFIG_MACH_IMX51_DT=y @@ -68,6 +72,7 @@ CONFIG_NET_CALXEDA_XGMAC=y CONFIG_KS8851=y CONFIG_SMSC911X=y CONFIG_STMMAC_ETH=y +CONFIG_ICPLUS_PHY=y CONFIG_MDIO_SUN4I=y CONFIG_TI_CPSW=y CONFIG_KEYBOARD_SPEAR=y @@ -91,6 +96,8 @@ CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_ST_ASC=y +CONFIG_SERIAL_ST_ASC_CONSOLE=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_SIRF=y CONFIG_I2C_TEGRA=y diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index 594d706..0f4511d 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -55,6 +55,8 @@ CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_STAA=y CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_PXA3xx=y CONFIG_SERIAL_8250_DW=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y @@ -69,6 +71,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_MMC=y CONFIG_MMC_MVSDIO=y CONFIG_NEW_LEDS=y +CONFIG_LEDS_GPIO=y CONFIG_LEDS_CLASS=m CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index bfa80a1..3a0b53d 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -208,6 +208,8 @@ CONFIG_SND_DEBUG=y CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=m CONFIG_SND_OMAP_SOC=m +CONFIG_SND_AM33XX_SOC_EVM=m +CONFIG_SND_DAVINCI_SOC=m CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m @@ -222,6 +224,7 @@ CONFIG_USB_TEST=y CONFIG_NOP_USB_XCEIV=y CONFIG_OMAP_USB2=y CONFIG_OMAP_USB3=y +CONFIG_AM335X_PHY_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DEBUG=y CONFIG_USB_GADGET_DEBUG_FILES=y diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index f6e78f8..dc3881e 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -20,7 +20,6 @@ CONFIG_ARCH_AT91=y CONFIG_SOC_SAM_V7=y CONFIG_SOC_SAMA5D3=y CONFIG_MACH_SAMA5_DT=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_UACCESS_WITH_MEMCPY=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 4934295..5fdc9a0 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -33,11 +33,12 @@ CONFIG_PCI=y CONFIG_PCI_MSI=y CONFIG_PCI_TEGRA=y CONFIG_PCIEPORTBUS=y +CONFIG_TRUSTED_FOUNDATIONS=y CONFIG_SMP=y CONFIG_PREEMPT=y CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set CONFIG_HIGHMEM=y +CONFIG_CMA=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_KEXEC=y @@ -63,7 +64,6 @@ CONFIG_INET_ESP=y # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set CONFIG_IPV6=y -CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_OPTIMISTIC_DAD=y CONFIG_INET6_AH=y @@ -85,7 +85,6 @@ CONFIG_RFKILL_GPIO=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_CMA=y CONFIG_DMA_CMA=y CONFIG_MTD=y CONFIG_MTD_M25P80=y @@ -114,6 +113,7 @@ CONFIG_RT2800USB=m CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_TEGRA=y +CONFIG_KEYBOARD_CROS_EC=y CONFIG_MOUSE_PS2_ELANTECH=y CONFIG_INPUT_MISC=y CONFIG_INPUT_MPU3050=y @@ -132,6 +132,7 @@ CONFIG_SPI=y CONFIG_SPI_TEGRA114=y CONFIG_SPI_TEGRA20_SFLASH=y CONFIG_SPI_TEGRA20_SLINK=y +CONFIG_PINCTRL_AS3722=y CONFIG_PINCTRL_PALMAS=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_PALMAS=y @@ -143,6 +144,9 @@ CONFIG_CHARGER_TPS65090=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y CONFIG_SENSORS_LM90=y +CONFIG_MFD_AS3722=y +CONFIG_MFD_CROS_EC=y +CONFIG_MFD_CROS_EC_SPI=y CONFIG_MFD_MAX8907=y CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65090=y @@ -151,6 +155,7 @@ CONFIG_MFD_TPS65910=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +CONFIG_REGULATOR_AS3722=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MAX8907=y CONFIG_REGULATOR_PALMAS=y @@ -164,7 +169,8 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_DRM=y -CONFIG_TEGRA_HOST1X=y +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_TEGRA=y CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set @@ -187,6 +193,7 @@ CONFIG_SND_SOC_TEGRA_WM8753=y CONFIG_SND_SOC_TEGRA_WM8903=y CONFIG_SND_SOC_TEGRA_TRIMSLICE=y CONFIG_SND_SOC_TEGRA_ALC5632=y +CONFIG_SND_SOC_TEGRA_MAX98090=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y @@ -211,6 +218,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=y CONFIG_LEDS_TRIGGER_CAMERA=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AS3722=y CONFIG_RTC_DRV_MAX8907=y CONFIG_RTC_DRV_PALMAS=y CONFIG_RTC_DRV_TPS6586X=y @@ -256,16 +264,15 @@ CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y +CONFIG_DEBUG_SLAB=y +CONFIG_DEBUG_VM=y CONFIG_DETECT_HUNG_TASK=y CONFIG_SCHEDSTATS=y CONFIG_TIMER_STATS=y -CONFIG_DEBUG_SLAB=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_VM=y CONFIG_DEBUG_SG=y CONFIG_DEBUG_LL=y CONFIG_EARLY_PRINTK=y diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index c6ebc18..65f7788 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -119,6 +119,7 @@ CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig index 2ba9e63..073541a 100644 --- a/arch/arm/configs/versatile_defconfig +++ b/arch/arm/configs/versatile_defconfig @@ -1,5 +1,3 @@ -CONFIG_ARCH_VERSATILE=y -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 @@ -7,15 +5,16 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_VERSATILE=y CONFIG_MACH_VERSATILE_AB=y -CONFIG_LEDS=y -CONFIG_LEDS_CPU=y +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="root=1f03 mem=32M" CONFIG_FPE_NWFPE=y CONFIG_VFP=y -CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -26,9 +25,7 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -37,10 +34,10 @@ CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_RAM=y CONFIG_EEPROM_LEGACY=m CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y # CONFIG_SERIO_SERPORT is not set CONFIG_SERIO_AMBAKMI=y +CONFIG_LEGACY_PTY_COUNT=16 CONFIG_SERIAL_8250=m CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y @@ -48,15 +45,14 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_RSA=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_LEGACY_PTY_COUNT=16 CONFIG_I2C=y CONFIG_I2C_CHARDEV=m +CONFIG_GPIOLIB=y +CONFIG_GPIO_PL061=y # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_ARMCLCD=y CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FONTS=y -CONFIG_FONT_ACORN_8x8=y CONFIG_SOUND=y CONFIG_SND=m CONFIG_SND_MIXER_OSS=m @@ -64,6 +60,9 @@ CONFIG_SND_PCM_OSS=m CONFIG_SND_ARMAACI=m CONFIG_MMC=y CONFIG_MMC_ARMMMCI=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y CONFIG_EXT2_FS=y CONFIG_VFAT_FS=m CONFIG_JFFS2_FS=y @@ -71,15 +70,14 @@ CONFIG_CRAMFS=y CONFIG_MINIX_FS=y CONFIG_ROMFS_FS=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y CONFIG_NFSD=y CONFIG_NFSD_V3=y -CONFIG_PARTITION_ADVANCED=y CONFIG_NLS_CODEPAGE_850=m CONFIG_NLS_ISO8859_1=m CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y +CONFIG_FONTS=y +CONFIG_FONT_ACORN_8x8=y diff --git a/arch/arm/firmware/Kconfig b/arch/arm/firmware/Kconfig new file mode 100644 index 0000000..bb00ccf --- /dev/null +++ b/arch/arm/firmware/Kconfig @@ -0,0 +1,28 @@ +config ARCH_SUPPORTS_FIRMWARE + bool + +config ARCH_SUPPORTS_TRUSTED_FOUNDATIONS + bool + select ARCH_SUPPORTS_FIRMWARE + +menu "Firmware options" + depends on ARCH_SUPPORTS_FIRMWARE + +config TRUSTED_FOUNDATIONS + bool "Trusted Foundations secure monitor support" + depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS + help + Some devices (including most Tegra-based consumer devices on the + market) are booted with the Trusted Foundations secure monitor + active, requiring some core operations to be performed by the secure + monitor instead of the kernel. + + This option allows the kernel to invoke the secure monitor whenever + required on devices using Trusted Foundations. See + arch/arm/include/asm/trusted_foundations.h or the + tl,trusted-foundations device tree binding documentation for details + on how to use it. + + Say n if you don't know what this is about. + +endmenu diff --git a/arch/arm/firmware/Makefile b/arch/arm/firmware/Makefile new file mode 100644 index 0000000..a71f165 --- /dev/null +++ b/arch/arm/firmware/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c new file mode 100644 index 0000000..ef1e3d8 --- /dev/null +++ b/arch/arm/firmware/trusted_foundations.c @@ -0,0 +1,81 @@ +/* + * Trusted Foundations support for ARM CPUs + * + * Copyright (c) 2013, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/of.h> +#include <asm/firmware.h> +#include <asm/trusted_foundations.h> + +#define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 + +static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2) +{ + asm volatile( + ".arch_extension sec\n\t" + "stmfd sp!, {r4 - r11, lr}\n\t" + __asmeq("%0", "r0") + __asmeq("%1", "r1") + __asmeq("%2", "r2") + "mov r3, #0\n\t" + "mov r4, #0\n\t" + "smc #0\n\t" + "ldmfd sp!, {r4 - r11, pc}" + : + : "r" (type), "r" (arg1), "r" (arg2) + : "memory"); +} + +static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr) +{ + tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, boot_addr, 0); + + return 0; +} + +static const struct firmware_ops trusted_foundations_ops = { + .set_cpu_boot_addr = tf_set_cpu_boot_addr, +}; + +void register_trusted_foundations(struct trusted_foundations_platform_data *pd) +{ + /* + * we are not using version information for now since currently + * supported SMCs are compatible with all TF releases + */ + register_firmware_ops(&trusted_foundations_ops); +} + +void of_register_trusted_foundations(void) +{ + struct device_node *node; + struct trusted_foundations_platform_data pdata; + int err; + + node = of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations"); + if (!node) + return; + + err = of_property_read_u32(node, "tlm,version-major", + &pdata.version_major); + if (err != 0) + panic("Trusted Foundation: missing version-major property\n"); + err = of_property_read_u32(node, "tlm,version-minor", + &pdata.version_minor); + if (err != 0) + panic("Trusted Foundation: missing version-minor property\n"); + register_trusted_foundations(&pdata); +} diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index e691ec9..b2e298a 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -254,25 +254,59 @@ static inline int constant_fls(int x) } /* - * On ARMv5 and above those functions can be implemented around - * the clz instruction for much better code efficiency. + * On ARMv5 and above those functions can be implemented around the + * clz instruction for much better code efficiency. __clz returns + * the number of leading zeros, zero input will return 32, and + * 0x80000000 will return 0. */ +static inline unsigned int __clz(unsigned int x) +{ + unsigned int ret; + + asm("clz\t%0, %1" : "=r" (ret) : "r" (x)); + return ret; +} + +/* + * fls() returns zero if the input is zero, otherwise returns the bit + * position of the last set bit, where the LSB is 1 and MSB is 32. + */ static inline int fls(int x) { - int ret; - if (__builtin_constant_p(x)) return constant_fls(x); - asm("clz\t%0, %1" : "=r" (ret) : "r" (x)); - ret = 32 - ret; - return ret; + return 32 - __clz(x); +} + +/* + * __fls() returns the bit position of the last bit set, where the + * LSB is 0 and MSB is 31. Zero input is undefined. + */ +static inline unsigned long __fls(unsigned long x) +{ + return fls(x) - 1; +} + +/* + * ffs() returns zero if the input was zero, otherwise returns the bit + * position of the first set bit, where the LSB is 1 and MSB is 32. + */ +static inline int ffs(int x) +{ + return fls(x & -x); +} + +/* + * __ffs() returns the bit position of the first bit set, where the + * LSB is 0 and MSB is 31. Zero input is undefined. + */ +static inline unsigned long __ffs(unsigned long x) +{ + return ffs(x) - 1; } -#define __fls(x) (fls(x) - 1) -#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); }) -#define __ffs(x) (ffs(x) - 1) #define ffz(x) __ffs( ~(x) ) #endif diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index ee753f1..e9a49fe 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -481,4 +481,9 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size) : : : "r0","r1","r2","r3","r4","r5","r6","r7", \ "r9","r10","lr","memory" ) +int set_memory_ro(unsigned long addr, int numpages); +int set_memory_rw(unsigned long addr, int numpages); +int set_memory_x(unsigned long addr, int numpages); +int set_memory_nx(unsigned long addr, int numpages); + #endif diff --git a/arch/arm/include/asm/checksum.h b/arch/arm/include/asm/checksum.h index 6dcc164..5233151 100644 --- a/arch/arm/include/asm/checksum.h +++ b/arch/arm/include/asm/checksum.h @@ -87,19 +87,33 @@ static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, unsigned short proto, __wsum sum) { - __asm__( - "adds %0, %1, %2 @ csum_tcpudp_nofold \n\ - adcs %0, %0, %3 \n" + u32 lenprot = len | proto << 16; + if (__builtin_constant_p(sum) && sum == 0) { + __asm__( + "adds %0, %1, %2 @ csum_tcpudp_nofold0 \n\t" #ifdef __ARMEB__ - "adcs %0, %0, %4 \n" + "adcs %0, %0, %3 \n\t" #else - "adcs %0, %0, %4, lsl #8 \n" + "adcs %0, %0, %3, ror #8 \n\t" #endif - "adcs %0, %0, %5 \n\ - adc %0, %0, #0" - : "=&r"(sum) - : "r" (sum), "r" (daddr), "r" (saddr), "r" (len), "Ir" (htons(proto)) - : "cc"); + "adc %0, %0, #0" + : "=&r" (sum) + : "r" (daddr), "r" (saddr), "r" (lenprot) + : "cc"); + } else { + __asm__( + "adds %0, %1, %2 @ csum_tcpudp_nofold \n\t" + "adcs %0, %0, %3 \n\t" +#ifdef __ARMEB__ + "adcs %0, %0, %4 \n\t" +#else + "adcs %0, %0, %4, ror #8 \n\t" +#endif + "adc %0, %0, #0" + : "=&r"(sum) + : "r" (sum), "r" (daddr), "r" (saddr), "r" (lenprot) + : "cc"); + } return sum; } /* diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h index 80751c1..4e8a4b2 100644 --- a/arch/arm/include/asm/clkdev.h +++ b/arch/arm/include/asm/clkdev.h @@ -14,12 +14,14 @@ #include <linux/slab.h> +#ifndef CONFIG_COMMON_CLK #ifdef CONFIG_HAVE_MACH_CLKDEV #include <mach/clkdev.h> #else #define __clk_get(clk) ({ 1; }) #define __clk_put(clk) do { } while (0) #endif +#endif static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) { diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 3b2c40b..6795ff7 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -131,6 +131,7 @@ struct l2x0_regs { unsigned long prefetch_ctrl; unsigned long pwr_ctrl; unsigned long ctrl; + unsigned long aux2_ctrl; }; extern struct l2x0_regs l2x0_saved_regs; diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h index 2fe141f..f98c7f3 100644 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h @@ -22,18 +22,21 @@ struct map_desc { }; /* types 0-3 are defined in asm/io.h */ -#define MT_UNCACHED 4 -#define MT_CACHECLEAN 5 -#define MT_MINICLEAN 6 -#define MT_LOW_VECTORS 7 -#define MT_HIGH_VECTORS 8 -#define MT_MEMORY 9 -#define MT_ROM 10 -#define MT_MEMORY_NONCACHED 11 -#define MT_MEMORY_DTCM 12 -#define MT_MEMORY_ITCM 13 -#define MT_MEMORY_SO 14 -#define MT_MEMORY_DMA_READY 15 +enum { + MT_UNCACHED = 4, + MT_CACHECLEAN, + MT_MINICLEAN, + MT_LOW_VECTORS, + MT_HIGH_VECTORS, + MT_MEMORY_RWX, + MT_MEMORY_RW, + MT_ROM, + MT_MEMORY_RWX_NONCACHED, + MT_MEMORY_RW_DTCM, + MT_MEMORY_RWX_ITCM, + MT_MEMORY_RW_SO, + MT_MEMORY_DMA_READY, +}; #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h index a98a2e1..680a83e 100644 --- a/arch/arm/include/asm/pci.h +++ b/arch/arm/include/asm/pci.h @@ -57,12 +57,9 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); -/* - * Dummy implementation; always return 0. - */ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) { - return 0; + return channel ? 15 : 14; } #endif /* __KERNEL__ */ diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index 86a659a..dfff709 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -160,6 +160,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) return (pmd_t *)pud; } +#define pmd_large(pmd) (pmd_val(pmd) & 2) #define pmd_bad(pmd) (pmd_val(pmd) & 2) #define copy_pmd(pmdpd,pmdps) \ diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index 4f95039..03243f7 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -142,6 +142,7 @@ PMD_TYPE_TABLE) #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ PMD_TYPE_SECT) +#define pmd_large(pmd) pmd_sect(pmd) #define pud_clear(pudp) \ do { \ diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 1571d12..7d59b52 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -254,6 +254,8 @@ PTE_BIT_FUNC(mkclean, &= ~L_PTE_DIRTY); PTE_BIT_FUNC(mkdirty, |= L_PTE_DIRTY); PTE_BIT_FUNC(mkold, &= ~L_PTE_YOUNG); PTE_BIT_FUNC(mkyoung, |= L_PTE_YOUNG); +PTE_BIT_FUNC(mkexec, &= ~L_PTE_XN); +PTE_BIT_FUNC(mknexec, |= L_PTE_XN); static inline pte_t pte_mkspecial(pte_t pte) { return pte; } diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h new file mode 100644 index 0000000..3bd36e2 --- /dev/null +++ b/arch/arm/include/asm/trusted_foundations.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* + * Support for the Trusted Foundations secure monitor. + * + * Trusted Foundation comes active on some ARM consumer devices (most + * Tegra-based devices sold on the market are concerned). Such devices can only + * perform some basic operations, like setting the CPU reset vector, through + * SMC calls to the secure monitor. The calls are completely specific to + * Trusted Foundations, and do *not* follow the SMC calling convention or the + * PSCI standard. + */ + +#ifndef __ASM_ARM_TRUSTED_FOUNDATIONS_H +#define __ASM_ARM_TRUSTED_FOUNDATIONS_H + +#include <linux/kconfig.h> +#include <linux/printk.h> +#include <linux/bug.h> +#include <linux/of.h> + +struct trusted_foundations_platform_data { + unsigned int version_major; + unsigned int version_minor; +}; + +#if IS_ENABLED(CONFIG_TRUSTED_FOUNDATIONS) + +void register_trusted_foundations(struct trusted_foundations_platform_data *pd); +void of_register_trusted_foundations(void); + +#else /* CONFIG_TRUSTED_FOUNDATIONS */ + +static inline void register_trusted_foundations( + struct trusted_foundations_platform_data *pd) +{ + /* + * If we try to register TF, this means the system needs it to continue. + * Its absence if thus a fatal error. + */ + panic("No support for Trusted Foundations, stopping...\n"); +} + +static inline void of_register_trusted_foundations(void) +{ + /* + * If we find the target should enable TF but does not support it, + * fail as the system won't be able to do much anyway + */ + if (of_find_compatible_node(NULL, NULL, "tl,trusted-foundations")) + register_trusted_foundations(NULL); +} +#endif /* CONFIG_TRUSTED_FOUNDATIONS */ + +#endif diff --git a/arch/arm/include/asm/word-at-a-time.h b/arch/arm/include/asm/word-at-a-time.h index 4d52f92..a6d0a29 100644 --- a/arch/arm/include/asm/word-at-a-time.h +++ b/arch/arm/include/asm/word-at-a-time.h @@ -48,10 +48,14 @@ static inline unsigned long find_zero(unsigned long mask) return ret; } -#ifdef CONFIG_DCACHE_WORD_ACCESS - #define zero_bytemask(mask) (mask) +#else /* __ARMEB__ */ +#include <asm-generic/word-at-a-time.h> +#endif + +#ifdef CONFIG_DCACHE_WORD_ACCESS + /* * Load an unaligned word from kernel space. * @@ -73,7 +77,11 @@ static inline unsigned long load_unaligned_zeropad(const void *addr) " bic %2, %2, #0x3\n" " ldr %0, [%2]\n" " lsl %1, %1, #0x3\n" +#ifndef __ARMEB__ " lsr %0, %0, %1\n" +#else + " lsl %0, %0, %1\n" +#endif " b 2b\n" " .popsection\n" " .pushsection __ex_table,\"a\"\n" @@ -86,11 +94,5 @@ static inline unsigned long load_unaligned_zeropad(const void *addr) return ret; } - #endif /* DCACHE_WORD_ACCESS */ - -#else /* __ARMEB__ */ -#include <asm-generic/word-at-a-time.h> -#endif - #endif /* __ASM_ARM_WORD_AT_A_TIME_H */ diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h index 29da84e..42b823c 100644 --- a/arch/arm/include/debug/imx-uart.h +++ b/arch/arm/include/debug/imx-uart.h @@ -43,6 +43,14 @@ #define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR #define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n) +#define IMX50_UART1_BASE_ADDR 0x53fbc000 +#define IMX50_UART2_BASE_ADDR 0x53fc0000 +#define IMX50_UART3_BASE_ADDR 0x5000c000 +#define IMX50_UART4_BASE_ADDR 0x53ff0000 +#define IMX50_UART5_BASE_ADDR 0x63f90000 +#define IMX50_UART_BASE_ADDR(n) IMX50_UART##n##_BASE_ADDR +#define IMX50_UART_BASE(n) IMX50_UART_BASE_ADDR(n) + #define IMX51_UART1_BASE_ADDR 0x73fbc000 #define IMX51_UART2_BASE_ADDR 0x73fc0000 #define IMX51_UART3_BASE_ADDR 0x7000c000 @@ -85,6 +93,8 @@ #define UART_PADDR IMX_DEBUG_UART_BASE(IMX31) #elif defined(CONFIG_DEBUG_IMX35_UART) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX35) +#elif defined(CONFIG_DEBUG_IMX50_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX50) #elif defined(CONFIG_DEBUG_IMX51_UART) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX51) #elif defined(CONFIG_DEBUG_IMX53_UART) diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S index be6a720..f98763f 100644 --- a/arch/arm/include/debug/tegra.S +++ b/arch/arm/include/debug/tegra.S @@ -46,10 +46,10 @@ #define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804) /* - * Must be 1MB-aligned since a 1MB mapping is used early on. + * Must be section-aligned since a section mapping is used early on. * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[]. */ -#define UART_VIRTUAL_BASE 0xfe100000 +#define UART_VIRTUAL_BASE 0xfe800000 #define checkuart(rp, rv, lhu, bit, uart) \ /* Load address of CLK_RST register */ \ @@ -156,28 +156,6 @@ 92: and \rv, \rp, #0xffffff @ offset within 1MB section add \rv, \rv, #UART_VIRTUAL_BASE str \rv, [\tmp, #8] @ Store in tegra_uart_virt - movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff - movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16 - ldr \rv, [\rv, #0] @ Load HIDREV - ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version - cmp \rv, #0x20 @ Tegra20? - moveq \rv, #0x75 @ Tegra20 divisor - movne \rv, #0xdd @ Tegra30 divisor - str \rv, [\tmp, #12] @ Save divisor to scratch - /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */ - mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB - str \rv, [\rp, #UART_LCR << UART_SHIFT] - /* uart[UART_DLL] = div & 0xff; */ - ldr \rv, [\tmp, #12] - and \rv, \rv, #0xff - str \rv, [\rp, #UART_DLL << UART_SHIFT] - /* uart[UART_DLM] = div >> 8; */ - ldr \rv, [\tmp, #12] - lsr \rv, \rv, #8 - str \rv, [\rp, #UART_DLM << UART_SHIFT] - /* uart[UART_LCR] = UART_LCR_WLEN8; */ - mov \rv, #UART_LCR_WLEN8 - str \rv, [\rp, #UART_LCR << UART_SHIFT] b 100f .align @@ -205,8 +183,8 @@ cmp \rx, #0 beq 1002f 1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT] - and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE - teq \rd, #UART_LSR_TEMT | UART_LSR_THRE + and \rd, \rd, #UART_LSR_THRE + teq \rd, #UART_LSR_THRE bne 1001b 1002: .endm @@ -225,7 +203,7 @@ /* * Storage for the state maintained by the macros above. * - * In the kernel proper, this data is located in arch/arm/mach-tegra/common.c. + * In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c. * That's because this header is included from multiple files, and we only * want a single copy of the data. In particular, the UART probing code above * assumes it's running using physical addresses. This is true when this file @@ -247,6 +225,4 @@ tegra_uart_config: .word 0 /* Debug UART virtual address */ .word 0 - /* Scratch space for debug macro */ - .word 0 #endif diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index 1f031dd..85e664b 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c @@ -35,6 +35,8 @@ extern void __ucmpdi2(void); extern void __udivsi3(void); extern void __umodsi3(void); extern void __do_div64(void); +extern void __bswapsi2(void); +extern void __bswapdi2(void); extern void __aeabi_idiv(void); extern void __aeabi_idivmod(void); @@ -114,6 +116,8 @@ EXPORT_SYMBOL(__ucmpdi2); EXPORT_SYMBOL(__udivsi3); EXPORT_SYMBOL(__umodsi3); EXPORT_SYMBOL(__do_div64); +EXPORT_SYMBOL(__bswapsi2); +EXPORT_SYMBOL(__bswapdi2); #ifdef CONFIG_AEABI EXPORT_SYMBOL(__aeabi_idiv); diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S index 52b2643..2260f18 100644 --- a/arch/arm/kernel/entry-v7m.S +++ b/arch/arm/kernel/entry-v7m.S @@ -14,8 +14,6 @@ #include <asm/thread_notify.h> #include <asm/v7m.h> -#include <mach/entry-macro.S> - #include "entry-header.S" #ifdef CONFIG_TRACE_IRQFLAGS diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c index 8ff0ecd..131a6ab 100644 --- a/arch/arm/kernel/etm.c +++ b/arch/arm/kernel/etm.c @@ -385,7 +385,6 @@ out: return ret; out_unmap: - amba_set_drvdata(dev, NULL); iounmap(t->etb_regs); out_release: @@ -398,8 +397,6 @@ static int etb_remove(struct amba_device *dev) { struct tracectx *t = amba_get_drvdata(dev); - amba_set_drvdata(dev, NULL); - iounmap(t->etb_regs); t->etb_regs = NULL; @@ -588,7 +585,6 @@ out: return ret; out_unmap: - amba_set_drvdata(dev, NULL); iounmap(t->etm_regs); out_release: @@ -601,8 +597,6 @@ static int etm_remove(struct amba_device *dev) { struct tracectx *t = amba_get_drvdata(dev); - amba_set_drvdata(dev, NULL); - iounmap(t->etm_regs); t->etm_regs = NULL; diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 8ce1cbd..1e8b030 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -334,7 +334,7 @@ static void __init cacheid_init(void) cacheid = CACHEID_VIVT; } - printk("CPU: %s data cache, %s instruction cache\n", + pr_info("CPU: %s data cache, %s instruction cache\n", cache_is_vivt() ? "VIVT" : cache_is_vipt_aliasing() ? "VIPT aliasing" : cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown", @@ -416,7 +416,7 @@ void notrace cpu_init(void) struct stack *stk = &stacks[cpu]; if (cpu >= NR_CPUS) { - printk(KERN_CRIT "CPU%u: bad primary CPU number\n", cpu); + pr_crit("CPU%u: bad primary CPU number\n", cpu); BUG(); } @@ -484,7 +484,7 @@ void __init smp_setup_processor_id(void) */ set_my_cpu_offset(0); - printk(KERN_INFO "Booting Linux on physical CPU 0x%x\n", mpidr); + pr_info("Booting Linux on physical CPU 0x%x\n", mpidr); } struct mpidr_hash mpidr_hash; @@ -564,8 +564,8 @@ static void __init setup_processor(void) */ list = lookup_processor_type(read_cpuid_id()); if (!list) { - printk("CPU configuration botched (ID %08x), unable " - "to continue.\n", read_cpuid_id()); + pr_err("CPU configuration botched (ID %08x), unable to continue.\n", + read_cpuid_id()); while (1); } @@ -585,9 +585,9 @@ static void __init setup_processor(void) cpu_cache = *list->cache; #endif - printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n", - cpu_name, read_cpuid_id(), read_cpuid_id() & 15, - proc_arch[cpu_architecture()], cr_alignment); + pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n", + cpu_name, read_cpuid_id(), read_cpuid_id() & 15, + proc_arch[cpu_architecture()], cr_alignment); snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c", list->arch_name, ENDIANNESS); @@ -629,8 +629,8 @@ int __init arm_add_memory(u64 start, u64 size) u64 aligned_start; if (meminfo.nr_banks >= NR_BANKS) { - printk(KERN_CRIT "NR_BANKS too low, " - "ignoring memory at 0x%08llx\n", (long long)start); + pr_crit("NR_BANKS too low, ignoring memory at 0x%08llx\n", + (long long)start); return -EINVAL; } @@ -643,14 +643,14 @@ int __init arm_add_memory(u64 start, u64 size) #ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT if (aligned_start > ULONG_MAX) { - printk(KERN_CRIT "Ignoring memory at 0x%08llx outside " - "32-bit physical address space\n", (long long)start); + pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n", + (long long)start); return -EINVAL; } if (aligned_start + size > ULONG_MAX) { - printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in " - "32-bit physical address space\n", (long long)start); + pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n", + (long long)start); /* * To ensure bank->start + bank->size is representable in * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB. @@ -660,6 +660,20 @@ int __init arm_add_memory(u64 start, u64 size) } #endif + if (aligned_start < PHYS_OFFSET) { + if (aligned_start + size <= PHYS_OFFSET) { + pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n", + aligned_start, aligned_start + size); + return -EINVAL; + } + + pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n", + aligned_start, (u64)PHYS_OFFSET); + + size -= PHYS_OFFSET - aligned_start; + aligned_start = PHYS_OFFSET; + } + bank->start = aligned_start; bank->size = size & ~(phys_addr_t)(PAGE_SIZE - 1); @@ -817,18 +831,17 @@ static void __init reserve_crashkernel(void) if (ret) return; - ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE); + ret = memblock_reserve(crash_base, crash_size); if (ret < 0) { - printk(KERN_WARNING "crashkernel reservation failed - " - "memory is in use (0x%lx)\n", (unsigned long)crash_base); + pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n", + (unsigned long)crash_base); return; } - printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " - "for crashkernel (System RAM: %ldMB)\n", - (unsigned long)(crash_size >> 20), - (unsigned long)(crash_base >> 20), - (unsigned long)(total_mem >> 20)); + pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n", + (unsigned long)(crash_size >> 20), + (unsigned long)(crash_base >> 20), + (unsigned long)(total_mem >> 20)); crashk_res.start = crash_base; crashk_res.end = crash_base + crash_size - 1; diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index dc894ab..b7b4c86 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -105,8 +105,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) secondary_data.pgdir = get_arch_pgd(idmap_pgd); secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir); #endif - __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data)); - outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1)); + sync_cache_w(&secondary_data); /* * Now bring the CPU into our world. @@ -294,6 +293,9 @@ void __ref cpu_die(void) if (smp_ops.cpu_die) smp_ops.cpu_die(cpu); + pr_warn("CPU%u: smp_ops.cpu_die() returned, trying to resuscitate\n", + cpu); + /* * Do not return to the idle loop - jump back to the secondary * cpu initialisation. There's some initialisation which needs diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c index f50f19e..7a3be1d 100644 --- a/arch/arm/kernel/tcm.c +++ b/arch/arm/kernel/tcm.c @@ -52,7 +52,7 @@ static struct map_desc dtcm_iomap[] __initdata = { .virtual = DTCM_OFFSET, .pfn = __phys_to_pfn(DTCM_OFFSET), .length = 0, - .type = MT_MEMORY_DTCM + .type = MT_MEMORY_RW_DTCM } }; @@ -61,7 +61,7 @@ static struct map_desc itcm_iomap[] __initdata = { .virtual = ITCM_OFFSET, .pfn = __phys_to_pfn(ITCM_OFFSET), .length = 0, - .type = MT_MEMORY_ITCM + .type = MT_MEMORY_RWX_ITCM, } }; diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 85a8737..0bc94b1 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -68,16 +68,16 @@ struct cpu_efficiency { * Processors that are not defined in the table, * use the default SCHED_POWER_SCALE value for cpu_scale. */ -struct cpu_efficiency table_efficiency[] = { +static const struct cpu_efficiency table_efficiency[] = { {"arm,cortex-a15", 3891}, {"arm,cortex-a7", 2048}, {NULL, }, }; -unsigned long *__cpu_capacity; +static unsigned long *__cpu_capacity; #define cpu_capacity(cpu) __cpu_capacity[cpu] -unsigned long middle_capacity = 1; +static unsigned long middle_capacity = 1; /* * Iterate all CPUs' descriptor in DT and compute the efficiency @@ -89,7 +89,7 @@ unsigned long middle_capacity = 1; */ static void __init parse_dt_topology(void) { - struct cpu_efficiency *cpu_eff; + const struct cpu_efficiency *cpu_eff; struct device_node *cn = NULL; unsigned long min_capacity = (unsigned long)(-1); unsigned long max_capacity = 0; @@ -158,7 +158,7 @@ static void __init parse_dt_topology(void) * boot. The update of all CPUs is in O(n^2) for heteregeneous system but the * function returns directly for SMP system. */ -void update_cpu_power(unsigned int cpu) +static void update_cpu_power(unsigned int cpu) { if (!cpu_capacity(cpu)) return; @@ -185,7 +185,7 @@ const struct cpumask *cpu_coregroup_mask(int cpu) return &cpu_topology[cpu].core_sibling; } -void update_siblings_masks(unsigned int cpuid) +static void update_siblings_masks(unsigned int cpuid) { struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid]; int cpu; diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 4636d56..172ee18 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -62,7 +62,7 @@ static void dump_mem(const char *, const char *, unsigned long, unsigned long); void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame) { #ifdef CONFIG_KALLSYMS - printk("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from); + printk("[<%08lx>] (%ps) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from); #else printk("Function entered at [<%08lx>] from [<%08lx>]\n", where, from); #endif diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 47d7338..0573faa 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -13,7 +13,7 @@ lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \ ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ ucmpdi2.o lib1funcs.o div64.o \ io-readsb.o io-writesb.o io-readsl.o io-writesl.o \ - call_with_stack.o + call_with_stack.o bswapsdi2.o mmu-y := clear_user.o copy_page.o getuser.o putuser.o diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S index cd07b58..4102be6 100644 --- a/arch/arm/lib/backtrace.S +++ b/arch/arm/lib/backtrace.S @@ -80,14 +80,14 @@ for_each_frame: tst frame, mask @ Check for address exceptions ldr r1, [sv_pc, #-4] @ if stmfd sp!, {args} exists, ldr r3, .Ldsi+4 - teq r3, r1, lsr #10 + teq r3, r1, lsr #11 ldreq r0, [frame, #-8] @ get sp subeq r0, r0, #4 @ point at the last arg bleq .Ldumpstm @ dump saved registers 1004: ldr r1, [sv_pc, #0] @ if stmfd sp!, {..., fp, ip, lr, pc} ldr r3, .Ldsi @ instruction exists, - teq r3, r1, lsr #10 + teq r3, r1, lsr #11 subeq r0, frame, #16 bleq .Ldumpstm @ dump saved registers @@ -128,11 +128,11 @@ ENDPROC(c_backtrace) beq 2f add r7, r7, #1 teq r7, #6 - moveq r7, #1 - moveq r1, #'\n' - movne r1, #' ' - ldr r3, [stack], #-4 - mov r2, reg + moveq r7, #0 + adr r3, .Lcr + addne r3, r3, #1 @ skip newline + ldr r2, [stack], #-4 + mov r1, reg adr r0, .Lfp bl printk 2: subs reg, reg, #1 @@ -142,11 +142,11 @@ ENDPROC(c_backtrace) blne printk ldmfd sp!, {instr, reg, stack, r7, pc} -.Lfp: .asciz "%cr%d:%08x" +.Lfp: .asciz " r%d:%08x%s" .Lcr: .asciz "\n" .Lbad: .asciz "Backtrace aborted due to bad frame pointer <%p>\n" .align -.Ldsi: .word 0xe92dd800 >> 10 @ stmfd sp!, {... fp, ip, lr, pc} - .word 0xe92d0000 >> 10 @ stmfd sp!, {} +.Ldsi: .word 0xe92dd800 >> 11 @ stmfd sp!, {... fp, ip, lr, pc} + .word 0xe92d0000 >> 11 @ stmfd sp!, {} #endif diff --git a/arch/arm/lib/bswapsdi2.S b/arch/arm/lib/bswapsdi2.S new file mode 100644 index 0000000..9fcdd15 --- /dev/null +++ b/arch/arm/lib/bswapsdi2.S @@ -0,0 +1,36 @@ +#include <linux/linkage.h> + +#if __LINUX_ARM_ARCH__ >= 6 +ENTRY(__bswapsi2) + rev r0, r0 + bx lr +ENDPROC(__bswapsi2) + +ENTRY(__bswapdi2) + rev r3, r0 + rev r0, r1 + mov r1, r3 + bx lr +ENDPROC(__bswapdi2) +#else +ENTRY(__bswapsi2) + eor r3, r0, r0, ror #16 + mov r3, r3, lsr #8 + bic r3, r3, #0xff00 + eor r0, r3, r0, ror #8 + mov pc, lr +ENDPROC(__bswapsi2) + +ENTRY(__bswapdi2) + mov ip, r1 + eor r3, ip, ip, ror #16 + eor r1, r0, r0, ror #16 + mov r1, r1, lsr #8 + mov r3, r3, lsr #8 + bic r3, r3, #0xff00 + bic r1, r1, #0xff00 + eor r1, r1, r0, ror #8 + eor r0, r3, ip, ror #8 + mov pc, lr +ENDPROC(__bswapdi2) +#endif diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 699b71e..4f0e800 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -1,15 +1,33 @@ if ARCH_AT91 +config HAVE_AT91_UTMI + bool + +config HAVE_AT91_USB_CLK + bool + config HAVE_AT91_DBGU0 bool config HAVE_AT91_DBGU1 bool +config AT91_USE_OLD_CLK + bool + config AT91_PMC_UNIT bool default !ARCH_AT91X40 +config COMMON_CLK_AT91 + bool + default AT91_PMC_UNIT && USE_OF && !AT91_USE_OLD_CLK + select COMMON_CLK + +config OLD_CLK_AT91 + bool + default AT91_PMC_UNIT && AT91_USE_OLD_CLK + config AT91_SAM9_ALT_RESET bool default !ARCH_AT91X40 @@ -21,6 +39,9 @@ config AT91_SAM9G45_RESET config AT91_SAM9_TIME bool +config HAVE_AT91_SMD + bool + config SOC_AT91SAM9 bool select AT91_SAM9_TIME @@ -61,13 +82,15 @@ comment "Atmel AT91 Processor" if SOC_SAM_V7 config SOC_SAMA5D3 bool "SAMA5D3 family" - depends on SOC_SAM_V7 select SOC_SAMA5 select HAVE_FB_ATMEL select HAVE_AT91_DBGU1 + select HAVE_AT91_UTMI + select HAVE_AT91_SMD + select HAVE_AT91_USB_CLK help Select this if you are using one of Atmel's SAMA5D3 family SoC. - This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35. + This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36. endif if SOC_SAM_V4_V5 @@ -78,11 +101,15 @@ config SOC_AT91RM9200 select HAVE_AT91_DBGU0 select MULTI_IRQ_HANDLER select SPARSE_IRQ + select AT91_USE_OLD_CLK + select HAVE_AT91_USB_CLK config SOC_AT91SAM9260 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" select HAVE_AT91_DBGU0 select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_USB_CLK help Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE or AT91SAM9G20 SoC. @@ -92,6 +119,8 @@ config SOC_AT91SAM9261 select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_USB_CLK help Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. @@ -100,18 +129,25 @@ config SOC_AT91SAM9263 select HAVE_AT91_DBGU1 select HAVE_FB_ATMEL select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_USB_CLK config SOC_AT91SAM9RL bool "AT91SAM9RL" select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_UTMI config SOC_AT91SAM9G45 bool "AT91SAM9G45 or AT91SAM9M10 families" select HAVE_AT91_DBGU1 select HAVE_FB_ATMEL select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_UTMI + select HAVE_AT91_USB_CLK help Select this if you are using one of Atmel's AT91SAM9G45 family SoC. This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. @@ -121,6 +157,10 @@ config SOC_AT91SAM9X5 select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_UTMI + select HAVE_AT91_SMD + select HAVE_AT91_USB_CLK help Select this if you are using one of Atmel's AT91SAM9x5 family SoC. This means that your SAM9 name finishes with a '5' (except if it is @@ -133,6 +173,8 @@ config SOC_AT91SAM9N12 select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_USB_CLK help Select this if you are using Atmel's AT91SAM9N12 SoC. @@ -172,12 +214,6 @@ config MACH_SAMA5_DT comment "AT91 Feature Selections" -config AT91_PROGRAMMABLE_CLOCKS - bool "Programmable Clocks" - help - Select this if you need to program one or more of the PCK0..PCK3 - programmable clock outputs. - config AT91_SLOW_CLOCK bool "Suspend-to-RAM disables main oscillator" depends on SUSPEND diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt index 0363dba..1f73e9b 100644 --- a/arch/arm/mach-at91/Kconfig.non_dt +++ b/arch/arm/mach-at91/Kconfig.non_dt @@ -12,26 +12,32 @@ config ARCH_AT91_NONE config ARCH_AT91RM9200 bool "AT91RM9200" select SOC_AT91RM9200 + select AT91_USE_OLD_CLK config ARCH_AT91SAM9260 bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20" select SOC_AT91SAM9260 + select AT91_USE_OLD_CLK config ARCH_AT91SAM9261 bool "AT91SAM9261 or AT91SAM9G10" select SOC_AT91SAM9261 + select AT91_USE_OLD_CLK config ARCH_AT91SAM9263 bool "AT91SAM9263" select SOC_AT91SAM9263 + select AT91_USE_OLD_CLK config ARCH_AT91SAM9RL bool "AT91SAM9RL" select SOC_AT91SAM9RL + select AT91_USE_OLD_CLK config ARCH_AT91SAM9G45 bool "AT91SAM9G45" select SOC_AT91SAM9G45 + select AT91_USE_OLD_CLK config ARCH_AT91X40 bool "AT91x40" @@ -176,12 +182,6 @@ config MACH_AFEB9260 <svn://194.85.238.22/home/users/george/svn/arm9eb> <http://groups.google.com/group/arm9fpga-evolution-board> -config MACH_QIL_A9260 - bool "CALAO QIL-A9260 board" - help - Select this if you are using a Calao Systems QIL-A9260 Board. - <http://www.calao-systems.com> - config MACH_CPU9260 bool "Eukrea CPU9260 board" help diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 90aab2d..78e9cec 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -7,7 +7,7 @@ obj-m := obj-n := obj- := -obj-$(CONFIG_AT91_PMC_UNIT) += clock.o +obj-$(CONFIG_OLD_CLK_AT91) += clock.o obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o @@ -52,7 +52,6 @@ obj-$(CONFIG_MACH_RSI_EWS) += board-rsi-ews.o obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o obj-$(CONFIG_MACH_CAM60) += board-cam60.o obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o -obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o obj-$(CONFIG_MACH_FLEXIBITY) += board-flexibity.o diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 25805f2..e47f5fd 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -12,13 +12,13 @@ #include <linux/module.h> #include <linux/reboot.h> +#include <linux/clk/at91_pmc.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/system_misc.h> #include <mach/at91rm9200.h> -#include <mach/at91_pmc.h> #include <mach/at91_st.h> #include <mach/cpu.h> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index d6a1fa8..6c821e5 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -11,6 +11,7 @@ */ #include <linux/module.h> +#include <linux/clk/at91_pmc.h> #include <asm/proc-fns.h> #include <asm/irq.h> @@ -20,7 +21,6 @@ #include <mach/cpu.h> #include <mach/at91_dbgu.h> #include <mach/at91sam9260.h> -#include <mach/at91_pmc.h> #include "at91_aic.h" #include "at91_rstc.h" diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 23ba1d8..6276b4c 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -11,6 +11,7 @@ */ #include <linux/module.h> +#include <linux/clk/at91_pmc.h> #include <asm/proc-fns.h> #include <asm/irq.h> @@ -19,7 +20,6 @@ #include <asm/system_misc.h> #include <mach/cpu.h> #include <mach/at91sam9261.h> -#include <mach/at91_pmc.h> #include "at91_aic.h" #include "at91_rstc.h" diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 7eccb0f..37b90f4 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -11,6 +11,7 @@ */ #include <linux/module.h> +#include <linux/clk/at91_pmc.h> #include <asm/proc-fns.h> #include <asm/irq.h> @@ -18,7 +19,6 @@ #include <asm/mach/map.h> #include <asm/system_misc.h> #include <mach/at91sam9263.h> -#include <mach/at91_pmc.h> #include "at91_aic.h" #include "at91_rstc.h" diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index bb39232..0f04ffe 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c @@ -39,6 +39,7 @@ static u32 pit_cycle; /* write-once */ static u32 pit_cnt; /* access only w/system irq blocked */ static void __iomem *pit_base_addr __read_mostly; +static struct clk *mck; static inline unsigned int pit_read(unsigned int reg_offset) { @@ -195,10 +196,14 @@ static int __init of_at91sam926x_pit_init(void) if (!pit_base_addr) goto node_err; + mck = of_clk_get(np, 0); + /* Get the interrupts property */ ret = irq_of_parse_and_map(np, 0); if (!ret) { pr_crit("AT91: PIT: Unable to get IRQ from DT\n"); + if (!IS_ERR(mck)) + clk_put(mck); goto ioremap_err; } at91sam926x_pit_irq.irq = ret; @@ -230,6 +235,8 @@ void __init at91sam926x_pit_init(void) unsigned bits; int ret; + mck = ERR_PTR(-ENOENT); + /* For device tree enabled device: initialize here */ of_at91sam926x_pit_init(); @@ -237,7 +244,12 @@ void __init at91sam926x_pit_init(void) * Use our actual MCK to figure out how many MCK/16 ticks per * 1/HZ period (instead of a compile-time constant LATCH). */ - pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16; + if (IS_ERR(mck)) + mck = clk_get(NULL, "mck"); + + if (IS_ERR(mck)) + panic("AT91: PIT: Unable to get mck clk\n"); + pit_rate = clk_get_rate(mck) / 16; pit_cycle = (pit_rate + HZ/2) / HZ; WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0); diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 9405aa0..2f455ce 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -12,13 +12,13 @@ #include <linux/module.h> #include <linux/dma-mapping.h> +#include <linux/clk/at91_pmc.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/system_misc.h> #include <mach/at91sam9g45.h> -#include <mach/at91_pmc.h> #include <mach/cpu.h> #include "at91_aic.h" diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index 388ec3a..4ef088c 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c @@ -8,12 +8,12 @@ #include <linux/module.h> #include <linux/dma-mapping.h> +#include <linux/clk/at91_pmc.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/at91sam9n12.h> -#include <mach/at91_pmc.h> #include <mach/cpu.h> #include "board.h" diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 0750ffb..3651517 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -10,6 +10,7 @@ */ #include <linux/module.h> +#include <linux/clk/at91_pmc.h> #include <asm/proc-fns.h> #include <asm/irq.h> @@ -19,7 +20,6 @@ #include <mach/cpu.h> #include <mach/at91_dbgu.h> #include <mach/at91sam9rl.h> -#include <mach/at91_pmc.h> #include "at91_aic.h" #include "at91_rstc.h" diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index e8a2e07..3e8ec26 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c @@ -8,12 +8,12 @@ #include <linux/module.h> #include <linux/dma-mapping.h> +#include <linux/clk/at91_pmc.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/at91sam9x5.h> -#include <mach/at91_pmc.h> #include <mach/cpu.h> #include "board.h" diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c index bf00d15..075ec05 100644 --- a/arch/arm/mach-at91/board-dt-sama5.c +++ b/arch/arm/mach-at91/board-dt-sama5.c @@ -16,6 +16,7 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/phy.h> +#include <linux/clk-provider.h> #include <asm/setup.h> #include <asm/irq.h> @@ -26,6 +27,13 @@ #include "at91_aic.h" #include "generic.h" +static void __init sama5_dt_timer_init(void) +{ +#if defined(CONFIG_COMMON_CLK) + of_clk_init(NULL); +#endif + at91sam926x_pit_init(); +} static const struct of_device_id irq_of_match[] __initconst = { @@ -72,7 +80,7 @@ static const char *sama5_dt_board_compat[] __initdata = { DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") /* Maintainer: Atmel */ - .init_time = at91sam926x_pit_init, + .init_time = sama5_dt_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic5_handle_irq, .init_early = at91_dt_initialize, diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c deleted file mode 100644 index aa3bc9b..0000000 --- a/arch/arm/mach-at91/board-qil-a9260.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * linux/arch/arm/mach-at91/board-qil-a9260.c - * - * Copyright (C) 2005 SAN People - * Copyright (C) 2006 Atmel - * Copyright (C) 2007 Calao-systems - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/types.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> -#include <linux/gpio_keys.h> -#include <linux/input.h> -#include <linux/clk.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/irq.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <mach/at91sam9_smc.h> - -#include "at91_aic.h" -#include "at91_shdwc.h" -#include "board.h" -#include "sam9_smc.h" -#include "generic.h" - - -static void __init ek_init_early(void) -{ - /* Initialize processor: 12.000 MHz crystal */ - at91_initialize(12000000); -} - -/* - * USB Host port - */ -static struct at91_usbh_data __initdata ek_usbh_data = { - .ports = 2, - .vbus_pin = {-EINVAL, -EINVAL}, - .overcurrent_pin= {-EINVAL, -EINVAL}, -}; - -/* - * USB Device port - */ -static struct at91_udc_data __initdata ek_udc_data = { - .vbus_pin = AT91_PIN_PC5, - .pullup_pin = -EINVAL, /* pull-up driven by UDC */ -}; - -/* - * SPI devices. - */ -static struct spi_board_info ek_spi_devices[] = { -#if defined(CONFIG_RTC_DRV_M41T94) - { /* M41T94 RTC */ - .modalias = "m41t94", - .chip_select = 0, - .max_speed_hz = 1 * 1000 * 1000, - .bus_num = 0, - } -#endif -}; - -/* - * MACB Ethernet device - */ -static struct macb_platform_data __initdata ek_macb_data = { - .phy_irq_pin = AT91_PIN_PA31, - .is_rmii = 1, -}; - -/* - * NAND flash - */ -static struct mtd_partition __initdata ek_nand_partition[] = { - { - .name = "Uboot & Kernel", - .offset = 0, - .size = SZ_16M, - }, - { - .name = "Root FS", - .offset = MTDPART_OFS_NXTBLK, - .size = 120 * SZ_1M, - }, - { - .name = "FS", - .offset = MTDPART_OFS_NXTBLK, - .size = 120 * SZ_1M, - }, -}; - -static struct atmel_nand_data __initdata ek_nand_data = { - .ale = 21, - .cle = 22, - .det_pin = -EINVAL, - .rdy_pin = AT91_PIN_PC13, - .enable_pin = AT91_PIN_PC14, - .ecc_mode = NAND_ECC_SOFT, - .on_flash_bbt = 1, - .parts = ek_nand_partition, - .num_parts = ARRAY_SIZE(ek_nand_partition), -}; - -static struct sam9_smc_config __initdata ek_nand_smc_config = { - .ncs_read_setup = 0, - .nrd_setup = 1, - .ncs_write_setup = 0, - .nwe_setup = 1, - - .ncs_read_pulse = 3, - .nrd_pulse = 3, - .ncs_write_pulse = 3, - .nwe_pulse = 3, - - .read_cycle = 5, - .write_cycle = 5, - - .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, - .tdf_cycles = 2, -}; - -static void __init ek_add_device_nand(void) -{ - /* configure chip-select 3 (NAND) */ - sam9_smc_configure(0, 3, &ek_nand_smc_config); - - at91_add_device_nand(&ek_nand_data); -} - -/* - * MCI (SD/MMC) - */ -static struct mci_platform_data __initdata ek_mci0_data = { - .slot[0] = { - .bus_width = 4, - .detect_pin = -EINVAL, - .wp_pin = -EINVAL, - }, -}; - -/* - * GPIO Buttons - */ -#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) -static struct gpio_keys_button ek_buttons[] = { - { /* USER PUSH BUTTON */ - .code = KEY_ENTER, - .gpio = AT91_PIN_PB10, - .active_low = 1, - .desc = "user_pb", - .wakeup = 1, - } -}; - -static struct gpio_keys_platform_data ek_button_data = { - .buttons = ek_buttons, - .nbuttons = ARRAY_SIZE(ek_buttons), -}; - -static struct platform_device ek_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &ek_button_data, - } -}; - -static void __init ek_add_device_buttons(void) -{ - at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */ - at91_set_deglitch(AT91_PIN_PB10, 1); - - platform_device_register(&ek_button_device); -} -#else -static void __init ek_add_device_buttons(void) {} -#endif - -/* - * LEDs - */ -static struct gpio_led ek_leds[] = { - { /* user_led (green) */ - .name = "user_led", - .gpio = AT91_PIN_PB21, - .active_low = 0, - .default_trigger = "heartbeat", - } -}; - -static void __init ek_board_init(void) -{ - /* Serial */ - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); - at91_add_device_serial(); - /* USB Host */ - at91_add_device_usbh(&ek_usbh_data); - /* USB Device */ - at91_add_device_udc(&ek_udc_data); - /* SPI */ - at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); - /* NAND */ - ek_add_device_nand(); - /* I2C */ - at91_add_device_i2c(NULL, 0); - /* Ethernet */ - at91_add_device_eth(&ek_macb_data); - /* MMC */ - at91_add_device_mci(0, &ek_mci0_data); - /* Push Buttons */ - ek_add_device_buttons(); - /* LEDs */ - at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); - /* shutdown controller, wakeup button (5 msec low) */ - at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW - | AT91_SHDW_RTTWKEN); -} - -MACHINE_START(QIL_A9260, "CALAO QIL_A9260") - /* Maintainer: calao-systems */ - .init_time = at91sam926x_pit_init, - .map_io = at91_map_io, - .handle_irq = at91_aic_handle_irq, - .init_early = ek_init_early, - .init_irq = at91_init_irq_default, - .init_machine = ek_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 6b2630a..034529d 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -24,9 +24,9 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/of_address.h> +#include <linux/clk/at91_pmc.h> #include <mach/hardware.h> -#include <mach/at91_pmc.h> #include <mach/cpu.h> #include <asm/proc-fns.h> @@ -330,8 +330,6 @@ EXPORT_SYMBOL(clk_get_rate); /*------------------------------------------------------------------------*/ -#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS - /* * For now, only the programmable clocks support reparenting (MCK could * do this too, with care) or rate changing (the PLLs could do this too, @@ -459,8 +457,6 @@ static void __init init_programmable_clock(struct clk *clk) clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr); } -#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ - /*------------------------------------------------------------------------*/ #ifdef CONFIG_DEBUG_FS @@ -577,12 +573,10 @@ int __init clk_register(struct clk *clk) clk->parent = &mck; clk->mode = pmc_sys_mode; } -#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS else if (clk_is_programmable(clk)) { clk->mode = pmc_sys_mode; init_programmable_clock(clk); } -#endif at91_clk_add(clk); @@ -884,6 +878,11 @@ static int __init at91_pmc_init(unsigned long main_clock) #if defined(CONFIG_OF) static struct of_device_id pmc_ids[] = { { .compatible = "atmel,at91rm9200-pmc" }, + { .compatible = "atmel,at91sam9260-pmc" }, + { .compatible = "atmel,at91sam9g45-pmc" }, + { .compatible = "atmel,at91sam9n12-pmc" }, + { .compatible = "atmel,at91sam9x5-pmc" }, + { .compatible = "atmel,sama5d3-pmc" }, { /*sentinel*/ } }; diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 26dee3c..631fa3b 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -46,11 +46,12 @@ extern void at91sam926x_pit_init(void); extern void at91x40_timer_init(void); /* Clocks */ -#ifdef CONFIG_AT91_PMC_UNIT +#ifdef CONFIG_OLD_CLK_AT91 extern int __init at91_clock_init(unsigned long main_clock); extern int __init at91_dt_clock_init(void); #else static int inline at91_clock_init(unsigned long main_clock) { return 0; } +static int inline at91_dt_clock_init(void) { return 0; } #endif struct device; diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h deleted file mode 100644 index c604cc6..0000000 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91_pmc.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Power Management Controller (PMC) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PMC_H -#define AT91_PMC_H - -#ifndef __ASSEMBLY__ -extern void __iomem *at91_pmc_base; - -#define at91_pmc_read(field) \ - __raw_readl(at91_pmc_base + field) - -#define at91_pmc_write(field, value) \ - __raw_writel(value, at91_pmc_base + field) -#else -.extern at91_pmc_base -#endif - -#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ -#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ - -#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ -#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ -#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ -#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ -#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ -#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ -#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ -#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ -#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ -#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ - -#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */ -#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ -#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ - -#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ -#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ -#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ -#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ -#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ - -#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ -#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ -#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ -#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ -#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ -#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ -#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ - -#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ -#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ -#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ - -#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ -#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ -#define AT91_PMC_DIV (0xff << 0) /* Divider */ -#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ -#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ -#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ -#define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) -#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */ -#define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) -#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ -#define AT91_PMC_USBDIV_1 (0 << 28) -#define AT91_PMC_USBDIV_2 (1 << 28) -#define AT91_PMC_USBDIV_4 (2 << 28) -#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ - -#define AT91_PMC_MCKR 0x30 /* Master Clock Register */ -#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ -#define AT91_PMC_CSS_SLOW (0 << 0) -#define AT91_PMC_CSS_MAIN (1 << 0) -#define AT91_PMC_CSS_PLLA (2 << 0) -#define AT91_PMC_CSS_PLLB (3 << 0) -#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ -#define PMC_PRES_OFFSET 2 -#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ -#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) -#define PMC_ALT_PRES_OFFSET 4 -#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ -#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ -#define AT91RM9200_PMC_MDIV_2 (1 << 8) -#define AT91RM9200_PMC_MDIV_3 (2 << 8) -#define AT91RM9200_PMC_MDIV_4 (3 << 8) -#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ -#define AT91SAM9_PMC_MDIV_2 (1 << 8) -#define AT91SAM9_PMC_MDIV_4 (2 << 8) -#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ -#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ -#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ -#define AT91_PMC_PDIV_1 (0 << 12) -#define AT91_PMC_PDIV_2 (1 << 12) -#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ -#define AT91_PMC_PLLADIV2_OFF (0 << 12) -#define AT91_PMC_PLLADIV2_ON (1 << 12) - -#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ -#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ -#define AT91_PMC_USBS_PLLA (0 << 0) -#define AT91_PMC_USBS_UPLL (1 << 0) -#define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */ -#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ -#define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8) -#define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8) - -#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ -#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ -#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ -#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) - -#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ -#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ -#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ -#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ -#define AT91_PMC_CSSMCK_CSS (0 << 8) -#define AT91_PMC_CSSMCK_MCK (1 << 8) - -#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ -#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ -#define AT91_PMC_SR 0x68 /* Status Register */ -#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ -#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ -#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ -#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ -#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */ -#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ -#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ -#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ -#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ - -#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ -#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ -#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ -#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ - -#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */ -#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ -#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ - -#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ -#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ -#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ - -#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ -#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ -#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ -#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */ -#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ -#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ -#define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */ -#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */ -#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index d3d7b99..86c71de 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -53,6 +53,7 @@ #define ARCH_EXID_SAMA5D33 0x00414300 #define ARCH_EXID_SAMA5D34 0x00414301 #define ARCH_EXID_SAMA5D35 0x00584300 +#define ARCH_EXID_SAMA5D36 0x00004301 #define ARCH_FAMILY_AT91X92 0x09200000 #define ARCH_FAMILY_AT91SAM9 0x01900000 @@ -105,7 +106,7 @@ enum at91_soc_subtype { /* SAMA5D3 */ AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, - AT91_SOC_SAMA5D35, + AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36, /* No subtype for this SoC */ AT91_SOC_SUBTYPE_NONE, diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 9986542..590b52d 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -19,13 +19,13 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/clk/at91_pmc.h> #include <asm/irq.h> #include <linux/atomic.h> #include <asm/mach/time.h> #include <asm/mach/irq.h> -#include <mach/at91_pmc.h> #include <mach/cpu.h> #include "at91_aic.h" @@ -155,9 +155,6 @@ static int at91_pm_verify_clocks(void) } } - if (!IS_ENABLED(CONFIG_AT91_PROGRAMMABLE_CLOCKS)) - return 1; - /* PCK0..PCK3 must be disabled, or configured to use clk32k */ for (i = 0; i < 4; i++) { u32 css; diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index 098c28d..2001877 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S @@ -13,8 +13,8 @@ */ #include <linux/linkage.h> +#include <linux/clk/at91_pmc.h> #include <mach/hardware.h> -#include <mach/at91_pmc.h> #include <mach/at91_ramc.h> diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index 99a0a1d2..b26156b 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -101,7 +101,7 @@ static void sam9_smc_cs_read(void __iomem *base, /* Pulse register */ val = __raw_readl(base + AT91_SMC_PULSE); - config->nwe_setup = val & AT91_SMC_NWEPULSE; + config->nwe_pulse = val & AT91_SMC_NWEPULSE; config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8; config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16; config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24; diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c index a28873f..3d775d0 100644 --- a/arch/arm/mach-at91/sama5d3.c +++ b/arch/arm/mach-at91/sama5d3.c @@ -9,360 +9,19 @@ #include <linux/module.h> #include <linux/dma-mapping.h> +#include <linux/clk/at91_pmc.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/sama5d3.h> -#include <mach/at91_pmc.h> #include <mach/cpu.h> #include "soc.h" #include "generic.h" -#include "clock.h" #include "sam9_smc.h" /* -------------------------------------------------------------------- - * Clocks - * -------------------------------------------------------------------- */ - -/* - * The peripheral clocks. - */ - -static struct clk pioA_clk = { - .name = "pioA_clk", - .pid = SAMA5D3_ID_PIOA, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioB_clk = { - .name = "pioB_clk", - .pid = SAMA5D3_ID_PIOB, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioC_clk = { - .name = "pioC_clk", - .pid = SAMA5D3_ID_PIOC, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioD_clk = { - .name = "pioD_clk", - .pid = SAMA5D3_ID_PIOD, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioE_clk = { - .name = "pioE_clk", - .pid = SAMA5D3_ID_PIOE, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart0_clk = { - .name = "usart0_clk", - .pid = SAMA5D3_ID_USART0, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk usart1_clk = { - .name = "usart1_clk", - .pid = SAMA5D3_ID_USART1, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk usart2_clk = { - .name = "usart2_clk", - .pid = SAMA5D3_ID_USART2, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk usart3_clk = { - .name = "usart3_clk", - .pid = SAMA5D3_ID_USART3, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk uart0_clk = { - .name = "uart0_clk", - .pid = SAMA5D3_ID_UART0, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk uart1_clk = { - .name = "uart1_clk", - .pid = SAMA5D3_ID_UART1, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk twi0_clk = { - .name = "twi0_clk", - .pid = SAMA5D3_ID_TWI0, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV8, -}; -static struct clk twi1_clk = { - .name = "twi1_clk", - .pid = SAMA5D3_ID_TWI1, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV8, -}; -static struct clk twi2_clk = { - .name = "twi2_clk", - .pid = SAMA5D3_ID_TWI2, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV8, -}; -static struct clk mmc0_clk = { - .name = "mci0_clk", - .pid = SAMA5D3_ID_HSMCI0, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk mmc1_clk = { - .name = "mci1_clk", - .pid = SAMA5D3_ID_HSMCI1, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk mmc2_clk = { - .name = "mci2_clk", - .pid = SAMA5D3_ID_HSMCI2, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk spi0_clk = { - .name = "spi0_clk", - .pid = SAMA5D3_ID_SPI0, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk spi1_clk = { - .name = "spi1_clk", - .pid = SAMA5D3_ID_SPI1, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk tcb0_clk = { - .name = "tcb0_clk", - .pid = SAMA5D3_ID_TC0, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk tcb1_clk = { - .name = "tcb1_clk", - .pid = SAMA5D3_ID_TC1, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk adc_clk = { - .name = "adc_clk", - .pid = SAMA5D3_ID_ADC, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk adc_op_clk = { - .name = "adc_op_clk", - .type = CLK_TYPE_PERIPHERAL, - .rate_hz = 5000000, -}; -static struct clk dma0_clk = { - .name = "dma0_clk", - .pid = SAMA5D3_ID_DMA0, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk dma1_clk = { - .name = "dma1_clk", - .pid = SAMA5D3_ID_DMA1, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk uhphs_clk = { - .name = "uhphs", - .pid = SAMA5D3_ID_UHPHS, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk udphs_clk = { - .name = "udphs_clk", - .pid = SAMA5D3_ID_UDPHS, - .type = CLK_TYPE_PERIPHERAL, -}; -/* gmac only for sama5d33, sama5d34, sama5d35 */ -static struct clk macb0_clk = { - .name = "macb0_clk", - .pid = SAMA5D3_ID_GMAC, - .type = CLK_TYPE_PERIPHERAL, -}; -/* emac only for sama5d31, sama5d35 */ -static struct clk macb1_clk = { - .name = "macb1_clk", - .pid = SAMA5D3_ID_EMAC, - .type = CLK_TYPE_PERIPHERAL, -}; -/* lcd only for sama5d31, sama5d33, sama5d34 */ -static struct clk lcdc_clk = { - .name = "lcdc_clk", - .pid = SAMA5D3_ID_LCDC, - .type = CLK_TYPE_PERIPHERAL, -}; -/* isi only for sama5d33, sama5d35 */ -static struct clk isi_clk = { - .name = "isi_clk", - .pid = SAMA5D3_ID_ISI, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk can0_clk = { - .name = "can0_clk", - .pid = SAMA5D3_ID_CAN0, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk can1_clk = { - .name = "can1_clk", - .pid = SAMA5D3_ID_CAN1, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk ssc0_clk = { - .name = "ssc0_clk", - .pid = SAMA5D3_ID_SSC0, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk ssc1_clk = { - .name = "ssc1_clk", - .pid = SAMA5D3_ID_SSC1, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk sha_clk = { - .name = "sha_clk", - .pid = SAMA5D3_ID_SHA, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV8, -}; -static struct clk aes_clk = { - .name = "aes_clk", - .pid = SAMA5D3_ID_AES, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk tdes_clk = { - .name = "tdes_clk", - .pid = SAMA5D3_ID_TDES, - .type = CLK_TYPE_PERIPHERAL, -}; - -static struct clk *periph_clocks[] __initdata = { - &pioA_clk, - &pioB_clk, - &pioC_clk, - &pioD_clk, - &pioE_clk, - &usart0_clk, - &usart1_clk, - &usart2_clk, - &usart3_clk, - &uart0_clk, - &uart1_clk, - &twi0_clk, - &twi1_clk, - &twi2_clk, - &mmc0_clk, - &mmc1_clk, - &mmc2_clk, - &spi0_clk, - &spi1_clk, - &tcb0_clk, - &tcb1_clk, - &adc_clk, - &adc_op_clk, - &dma0_clk, - &dma1_clk, - &uhphs_clk, - &udphs_clk, - &macb0_clk, - &macb1_clk, - &lcdc_clk, - &isi_clk, - &can0_clk, - &can1_clk, - &ssc0_clk, - &ssc1_clk, - &sha_clk, - &aes_clk, - &tdes_clk, -}; - -static struct clk pck0 = { - .name = "pck0", - .pmc_mask = AT91_PMC_PCK0, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 0, -}; - -static struct clk pck1 = { - .name = "pck1", - .pmc_mask = AT91_PMC_PCK1, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 1, -}; - -static struct clk pck2 = { - .name = "pck2", - .pmc_mask = AT91_PMC_PCK2, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 2, -}; - -static struct clk_lookup periph_clocks_lookups[] = { - /* lookup table for DT entries */ - CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), - CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk), - CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk), - CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk), - CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk), - CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk), - CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk), - CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk), - CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk), - CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk), - CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk), - CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk), - CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk), - CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk), - CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk), - CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk), - CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk), - CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk), - CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk), - CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk), - CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk), - CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk), - CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk), - CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk), - CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk), - CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk), - CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk), - CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk), - CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk), - CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk), - CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk), - CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk), - CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk), - CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk), - CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk), - CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk), - CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk), - CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk), - CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk), -}; - -static void __init sama5d3_register_clocks(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) - clk_register(periph_clocks[i]); - - clkdev_add_table(periph_clocks_lookups, - ARRAY_SIZE(periph_clocks_lookups)); - - clk_register(&pck0); - clk_register(&pck1); - clk_register(&pck2); -} - -/* -------------------------------------------------------------------- * AT91SAM9x5 processor initialization * -------------------------------------------------------------------- */ @@ -378,6 +37,5 @@ static void __init sama5d3_initialize(void) AT91_SOC_START(sama5d3) .map_io = sama5d3_map_io, - .register_clocks = sama5d3_register_clocks, .init = sama5d3_initialize, AT91_SOC_END diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 094b345..f7ca97b 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -11,6 +11,7 @@ #include <linux/pm.h> #include <linux/of_address.h> #include <linux/pinctrl/machine.h> +#include <linux/clk/at91_pmc.h> #include <asm/system_misc.h> #include <asm/mach/map.h> @@ -18,7 +19,6 @@ #include <mach/hardware.h> #include <mach/cpu.h> #include <mach/at91_dbgu.h> -#include <mach/at91_pmc.h> #include "at91_shdwc.h" #include "soc.h" @@ -81,7 +81,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length) desc->pfn = __phys_to_pfn(base); desc->length = length; - desc->type = MT_MEMORY_NONCACHED; + desc->type = MT_MEMORY_RWX_NONCACHED; pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n", base, length, desc->virtual); @@ -233,6 +233,9 @@ static void __init soc_detect(u32 dbgu_base) case ARCH_EXID_SAMA5D35: at91_soc_initdata.subtype = AT91_SOC_SAMA5D35; break; + case ARCH_EXID_SAMA5D36: + at91_soc_initdata.subtype = AT91_SOC_SAMA5D36; + break; } } } @@ -275,6 +278,7 @@ static const char *soc_subtype_name[] = { [AT91_SOC_SAMA5D33] = "sama5d33", [AT91_SOC_SAMA5D34] = "sama5d34", [AT91_SOC_SAMA5D35] = "sama5d35", + [AT91_SOC_SAMA5D36] = "sama5d36", [AT91_SOC_SUBTYPE_NONE] = "None", [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown", }; @@ -491,7 +495,8 @@ void __init at91rm9200_dt_initialize(void) at91_dt_clock_init(); /* Register the processor-specific clocks */ - at91_boot_soc.register_clocks(); + if (at91_boot_soc.register_clocks) + at91_boot_soc.register_clocks(); at91_boot_soc.init(); } @@ -506,7 +511,8 @@ void __init at91_dt_initialize(void) at91_dt_clock_init(); /* Register the processor-specific clocks */ - at91_boot_soc.register_clocks(); + if (at91_boot_soc.register_clocks) + at91_boot_soc.register_clocks(); if (at91_boot_soc.init) at91_boot_soc.init(); diff --git a/arch/arm/mach-bcm2835/Kconfig b/arch/arm/mach-bcm2835/Kconfig index 560045c..d1f9612 100644 --- a/arch/arm/mach-bcm2835/Kconfig +++ b/arch/arm/mach-bcm2835/Kconfig @@ -12,4 +12,4 @@ config ARCH_BCM2835 select PINCTRL_BCM2835 help This enables support for the Broadcom BCM2835 SoC. This SoC is - use in the Raspberry Pi, and Roku 2 devices. + used in the Raspberry Pi and Roku 2 devices. diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig new file mode 100644 index 0000000..7a02d22 --- /dev/null +++ b/arch/arm/mach-berlin/Kconfig @@ -0,0 +1,29 @@ +config ARCH_BERLIN + bool "Marvell Berlin SoCs" if ARCH_MULTI_V7 + select ARM_GIC + select GENERIC_CLOCKEVENTS + select GENERIC_IRQ_CHIP + select COMMON_CLK + select DW_APB_ICTL + select DW_APB_TIMER_OF + +if ARCH_BERLIN + +menu "Marvell Berlin SoC variants" + +config MACH_BERLIN_BG2 + bool "Marvell Armada 1500 (BG2)" + select CACHE_L2X0 + select CPU_PJ4B + select HAVE_ARM_TWD if SMP + select HAVE_SMP + +config MACH_BERLIN_BG2CD + bool "Marvell Armada 1500-mini (BG2CD)" + select CACHE_L2X0 + select CPU_V7 + select HAVE_ARM_TWD if SMP + +endmenu + +endif diff --git a/arch/arm/mach-berlin/Makefile b/arch/arm/mach-berlin/Makefile new file mode 100644 index 0000000..ab69fe9 --- /dev/null +++ b/arch/arm/mach-berlin/Makefile @@ -0,0 +1 @@ +obj-y += berlin.o diff --git a/arch/arm/mach-berlin/berlin.c b/arch/arm/mach-berlin/berlin.c new file mode 100644 index 0000000..025bcb5 --- /dev/null +++ b/arch/arm/mach-berlin/berlin.c @@ -0,0 +1,39 @@ +/* + * Device Tree support for Marvell Berlin SoCs. + * + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * + * based on GPL'ed 2.6 kernel sources + * (c) Marvell International Ltd. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/of_platform.h> +#include <asm/hardware/cache-l2x0.h> +#include <asm/mach/arch.h> + +static void __init berlin_init_machine(void) +{ + /* + * with DT probing for L2CCs, berlin_init_machine can be removed. + * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc + */ + l2x0_of_init(0x70c00000, 0xfeffffff); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char * const berlin_dt_compat[] = { + "marvell,berlin", + NULL, +}; + +DT_MACHINE_START(BERLIN_DT, "Marvell Berlin") + .dt_compat = berlin_dt_compat, + .init_machine = berlin_init_machine, +MACHINE_END diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index 134641d..a193591 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c @@ -259,7 +259,7 @@ asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs) } while (1); } -static u32 notrace clps711x_sched_clock_read(void) +static u64 notrace clps711x_sched_clock_read(void) { return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D); } @@ -366,7 +366,7 @@ void __init clps711x_timer_init(void) tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M); clps_writel(tmp, SYSCON1); - setup_sched_clock(clps711x_sched_clock_read, 16, timl); + sched_clock_register(clps711x_sched_clock_read, 16, timl); clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D, "clps711x_clocksource", timl, 300, 16, diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index dc9a470..985e5fd 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -133,7 +133,7 @@ EXPORT_SYMBOL(clk_get_rate); long clk_round_rate(struct clk *clk, unsigned long rate) { if (clk == NULL || IS_ERR(clk)) - return -EINVAL; + return 0; if (clk->round_rate) return clk->round_rate(clk, rate); diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 0813b51..115d573 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -385,7 +385,7 @@ static struct clk_lookup da830_clks[] = { CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), CLK("i2c_davinci.1", NULL, &i2c0_clk), CLK(NULL, "timer0", &timerp64_0_clk), - CLK("watchdog", NULL, &timerp64_1_clk), + CLK("davinci-wdt", NULL, &timerp64_1_clk), CLK(NULL, "arm_rom", &arm_rom_clk), CLK(NULL, "scr0_ss", &scr0_ss_clk), CLK(NULL, "scr1_ss", &scr1_ss_clk), @@ -1153,7 +1153,6 @@ static struct davinci_id da830_ids[] = { static struct davinci_gpio_platform_data da830_gpio_platform_data = { .ngpio = 128, - .intc_irq_num = DA830_N_CP_INTC_IRQ, }; int __init da830_register_gpio(void) diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 352984e..2ab0043 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -443,7 +443,7 @@ static struct clk_lookup da850_clks[] = { CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), CLK("i2c_davinci.1", NULL, &i2c0_clk), CLK(NULL, "timer0", &timerp64_0_clk), - CLK("watchdog", NULL, &timerp64_1_clk), + CLK("davinci-wdt", NULL, &timerp64_1_clk), CLK(NULL, "arm_rom", &arm_rom_clk), CLK(NULL, "tpcc0", &tpcc0_clk), CLK(NULL, "tptc0", &tptc0_clk), @@ -1283,7 +1283,6 @@ int __init da850_register_vpif_capture(struct vpif_capture_config static struct davinci_gpio_platform_data da850_gpio_platform_data = { .ngpio = 144, - .intc_irq_num = DA850_N_CP_INTC_IRQ, }; int __init da850_register_gpio(void) diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index d2bc574..ed19287 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -32,7 +32,7 @@ static void __init da8xx_init_irq(void) static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL), - OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "watchdog", NULL), + OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "davinci-wdt", NULL), OF_DEV_AUXDATA("ti,da830-mmc", 0x01c40000, "da830-mmc.0", NULL), OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f00000, "ehrpwm", NULL), OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f02000, "ehrpwm", NULL), diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 78829c5..0486cdf 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -389,7 +389,7 @@ static struct resource da8xx_watchdog_resources[] = { }; static struct platform_device da8xx_wdt_device = { - .name = "watchdog", + .name = "davinci-wdt", .id = -1, .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), .resource = da8xx_watchdog_resources, @@ -399,7 +399,7 @@ void da8xx_restart(enum reboot_mode mode, const char *cmd) { struct device *dev; - dev = bus_find_device_by_name(&platform_bus_type, NULL, "watchdog"); + dev = bus_find_device_by_name(&platform_bus_type, NULL, "davinci-wdt"); if (!dev) { pr_err("%s: failed to find watchdog device\n", __func__); return; diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 3996e98..5cf9a02 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -302,7 +302,7 @@ static struct resource wdt_resources[] = { }; struct platform_device davinci_wdt_device = { - .name = "watchdog", + .name = "davinci-wdt", .id = -1, .num_resources = ARRAY_SIZE(wdt_resources), .resource = wdt_resources, diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 6117fc6..4668c0e 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -375,7 +375,7 @@ static struct clk_lookup dm355_clks[] = { CLK(NULL, "pwm3", &pwm3_clk), CLK(NULL, "timer0", &timer0_clk), CLK(NULL, "timer1", &timer1_clk), - CLK("watchdog", NULL, &timer2_clk), + CLK("davinci-wdt", NULL, &timer2_clk), CLK(NULL, "timer3", &timer3_clk), CLK(NULL, "rto", &rto_clk), CLK(NULL, "usb", &usb_clk), @@ -901,7 +901,6 @@ static struct resource dm355_gpio_resources[] = { static struct davinci_gpio_platform_data dm355_gpio_platform_data = { .ngpio = 104, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, }; int __init dm355_gpio_register(void) diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index d7c6f85..b44b49e 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -473,7 +473,7 @@ static struct clk_lookup dm365_clks[] = { CLK(NULL, "pwm3", &pwm3_clk), CLK(NULL, "timer0", &timer0_clk), CLK(NULL, "timer1", &timer1_clk), - CLK("watchdog", NULL, &timer2_clk), + CLK("davinci-wdt", NULL, &timer2_clk), CLK(NULL, "timer3", &timer3_clk), CLK(NULL, "usb", &usb_clk), CLK("davinci_emac.1", NULL, &emac_clk), @@ -713,7 +713,6 @@ static struct resource dm365_gpio_resources[] = { static struct davinci_gpio_platform_data dm365_gpio_platform_data = { .ngpio = 104, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, .gpio_unbanked = 8, }; diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 3ce4799..5c3e0be 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -322,7 +322,7 @@ static struct clk_lookup dm644x_clks[] = { CLK(NULL, "pwm2", &pwm2_clk), CLK(NULL, "timer0", &timer0_clk), CLK(NULL, "timer1", &timer1_clk), - CLK("watchdog", NULL, &timer2_clk), + CLK("davinci-wdt", NULL, &timer2_clk), CLK(NULL, NULL, NULL), }; @@ -787,7 +787,6 @@ static struct resource dm644_gpio_resources[] = { static struct davinci_gpio_platform_data dm644_gpio_platform_data = { .ngpio = 71, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, }; int __init dm644x_gpio_register(void) diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 0e81fea65..81768dd 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -356,7 +356,7 @@ static struct clk_lookup dm646x_clks[] = { CLK(NULL, "pwm1", &pwm1_clk), CLK(NULL, "timer0", &timer0_clk), CLK(NULL, "timer1", &timer1_clk), - CLK("watchdog", NULL, &timer2_clk), + CLK("davinci-wdt", NULL, &timer2_clk), CLK("palm_bk3710", NULL, &ide_clk), CLK(NULL, "vpif0", &vpif0_clk), CLK(NULL, "vpif1", &vpif1_clk), @@ -763,7 +763,6 @@ static struct resource dm646x_gpio_resources[] = { static struct davinci_gpio_platform_data dm646x_gpio_platform_data = { .ngpio = 43, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, }; int __init dm646x_gpio_register(void) diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 56c6eb5..24ad30f 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -285,7 +285,7 @@ static struct clocksource clocksource_davinci = { /* * Overwrite weak default sched_clock with something more precise */ -static u32 notrace davinci_read_sched_clock(void) +static u64 notrace davinci_read_sched_clock(void) { return timer32_read(&timers[TID_CLOCKSOURCE]); } @@ -391,7 +391,7 @@ void __init davinci_timer_init(void) davinci_clock_tick_rate)) printk(err, clocksource_davinci.name); - setup_sched_clock(davinci_read_sched_clock, 32, + sched_clock_register(davinci_read_sched_clock, 32, davinci_clock_tick_rate); /* setup clockevent */ diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index c122bcf..0d1a892 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -162,7 +162,7 @@ void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) /***************************************************************************** * SoC RTC ****************************************************************************/ -void __init dove_rtc_init(void) +static void __init dove_rtc_init(void) { orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); } @@ -257,18 +257,9 @@ void __init dove_timer_init(void) } /***************************************************************************** - * Cryptographic Engines and Security Accelerator (CESA) - ****************************************************************************/ -void __init dove_crypto_init(void) -{ - orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE, - DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO); -} - -/***************************************************************************** * XOR 0 ****************************************************************************/ -void __init dove_xor0_init(void) +static void __init dove_xor0_init(void) { orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); @@ -277,7 +268,7 @@ void __init dove_xor0_init(void) /***************************************************************************** * XOR 1 ****************************************************************************/ -void __init dove_xor1_init(void) +static void __init dove_xor1_init(void) { orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); diff --git a/arch/arm/mach-efm32/Makefile b/arch/arm/mach-efm32/Makefile new file mode 100644 index 0000000..3a74af7 --- /dev/null +++ b/arch/arm/mach-efm32/Makefile @@ -0,0 +1 @@ +obj-y += dtmachine.o diff --git a/arch/arm/mach-efm32/Makefile.boot b/arch/arm/mach-efm32/Makefile.boot new file mode 100644 index 0000000..eacfc3f --- /dev/null +++ b/arch/arm/mach-efm32/Makefile.boot @@ -0,0 +1,3 @@ +# Empty file waiting for deletion once Makefile.boot isn't needed any more. +# Patch waits for application at +# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 . diff --git a/arch/arm/mach-efm32/dtmachine.c b/arch/arm/mach-efm32/dtmachine.c new file mode 100644 index 0000000..2367495 --- /dev/null +++ b/arch/arm/mach-efm32/dtmachine.c @@ -0,0 +1,15 @@ +#include <linux/kernel.h> + +#include <asm/v7m.h> + +#include <asm/mach/arch.h> + +static const char *const efm32gg_compat[] __initconst = { + "efm32,dk3750", + NULL +}; + +DT_MACHINE_START(EFM32DT, "EFM32 (Device Tree Support)") + .dt_compat = efm32gg_compat, + .restart = armv7m_restart, +MACHINE_END diff --git a/arch/arm/mach-efm32/include/mach/entry-macro.S b/arch/arm/mach-efm32/include/mach/entry-macro.S new file mode 100644 index 0000000..322159d --- /dev/null +++ b/arch/arm/mach-efm32/include/mach/entry-macro.S @@ -0,0 +1,4 @@ +/* + * Empty file waiting for deletion once <mach/entry-macro.S> isn't needed any + * more. Patch "ARM: v7-M: drop using mach/entry-macro.S" sitting in next. + */ diff --git a/arch/arm/mach-efm32/include/mach/timex.h b/arch/arm/mach-efm32/include/mach/timex.h new file mode 100644 index 0000000..7a8b26d --- /dev/null +++ b/arch/arm/mach-efm32/include/mach/timex.h @@ -0,0 +1,3 @@ +/* + * Empty file waiting for deletion once <mach/timex.h> isn't needed any more. + */ diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 93e54fd..bec570a 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -5,6 +5,7 @@ menu "Cirrus EP93xx Implementation Options" config EP93XX_SOC_COMMON bool default y + select SOC_BUS select LEDS_GPIO_REGISTER config CRUNCH diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index d95ee28a..157ba88 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -21,6 +21,7 @@ #include <linux/platform_device.h> #include <linux/interrupt.h> #include <linux/dma-mapping.h> +#include <linux/sys_soc.h> #include <linux/timex.h> #include <linux/irq.h> #include <linux/io.h> @@ -44,6 +45,7 @@ #include <linux/platform_data/spi-ep93xx.h> #include <mach/gpio-ep93xx.h> +#include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -137,7 +139,7 @@ static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) static struct irqaction ep93xx_timer_irq = { .name = "ep93xx timer", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_TIMER | IRQF_IRQPOLL, .handler = ep93xx_timer_interrupt, }; @@ -925,8 +927,108 @@ void ep93xx_ide_release_gpio(struct platform_device *pdev) } EXPORT_SYMBOL(ep93xx_ide_release_gpio); -void __init ep93xx_init_devices(void) +/************************************************************************* + * EP93xx Security peripheral + *************************************************************************/ + +/* + * The Maverick Key is 256 bits of micro fuses blown at the factory during + * manufacturing to uniquely identify a part. + * + * See: http://arm.cirrus.com/forum/viewtopic.php?t=486&highlight=maverick+key + */ +#define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x)) +#define EP93XX_SECURITY_SECFLG EP93XX_SECURITY_REG(0x2400) +#define EP93XX_SECURITY_FUSEFLG EP93XX_SECURITY_REG(0x2410) +#define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440) +#define EP93XX_SECURITY_UNIQCHK EP93XX_SECURITY_REG(0x2450) +#define EP93XX_SECURITY_UNIQVAL EP93XX_SECURITY_REG(0x2460) +#define EP93XX_SECURITY_SECID1 EP93XX_SECURITY_REG(0x2500) +#define EP93XX_SECURITY_SECID2 EP93XX_SECURITY_REG(0x2504) +#define EP93XX_SECURITY_SECCHK1 EP93XX_SECURITY_REG(0x2520) +#define EP93XX_SECURITY_SECCHK2 EP93XX_SECURITY_REG(0x2524) +#define EP93XX_SECURITY_UNIQID2 EP93XX_SECURITY_REG(0x2700) +#define EP93XX_SECURITY_UNIQID3 EP93XX_SECURITY_REG(0x2704) +#define EP93XX_SECURITY_UNIQID4 EP93XX_SECURITY_REG(0x2708) +#define EP93XX_SECURITY_UNIQID5 EP93XX_SECURITY_REG(0x270c) + +static char ep93xx_soc_id[33]; + +static const char __init *ep93xx_get_soc_id(void) { + unsigned int id, id2, id3, id4, id5; + + if (__raw_readl(EP93XX_SECURITY_UNIQVAL) != 1) + return "bad Hamming code"; + + id = __raw_readl(EP93XX_SECURITY_UNIQID); + id2 = __raw_readl(EP93XX_SECURITY_UNIQID2); + id3 = __raw_readl(EP93XX_SECURITY_UNIQID3); + id4 = __raw_readl(EP93XX_SECURITY_UNIQID4); + id5 = __raw_readl(EP93XX_SECURITY_UNIQID5); + + if (id != id2) + return "invalid"; + + snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id), + "%08x%08x%08x%08x", id2, id3, id4, id5); + + return ep93xx_soc_id; +} + +static const char __init *ep93xx_get_soc_rev(void) +{ + int rev = ep93xx_chip_revision(); + + switch (rev) { + case EP93XX_CHIP_REV_D0: + return "D0"; + case EP93XX_CHIP_REV_D1: + return "D1"; + case EP93XX_CHIP_REV_E0: + return "E0"; + case EP93XX_CHIP_REV_E1: + return "E1"; + case EP93XX_CHIP_REV_E2: + return "E2"; + default: + return "unknown"; + } +} + +static const char __init *ep93xx_get_machine_name(void) +{ + return kasprintf(GFP_KERNEL,"%s", machine_desc->name); +} + +static struct device __init *ep93xx_init_soc(void) +{ + struct soc_device_attribute *soc_dev_attr; + struct soc_device *soc_dev; + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return NULL; + + soc_dev_attr->machine = ep93xx_get_machine_name(); + soc_dev_attr->family = "Cirrus Logic EP93xx"; + soc_dev_attr->revision = ep93xx_get_soc_rev(); + soc_dev_attr->soc_id = ep93xx_get_soc_id(); + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr->machine); + kfree(soc_dev_attr); + return NULL; + } + + return soc_device_to_device(soc_dev); +} + +struct device __init *ep93xx_init_devices(void) +{ + struct device *parent; + /* Disallow access to MaverickCrunch initially */ ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); @@ -937,6 +1039,8 @@ void __init ep93xx_init_devices(void) EP93XX_SYSCON_DEVCFG_GONIDE | EP93XX_SYSCON_DEVCFG_HONIDE); + parent = ep93xx_init_soc(); + /* Get the GPIO working early, other devices need it */ platform_device_register(&ep93xx_gpio_device); @@ -949,6 +1053,8 @@ void __init ep93xx_init_devices(void) platform_device_register(&ep93xx_wdt_device); gpio_led_register_device(-1, &ep93xx_led_data); + + return parent; } void ep93xx_restart(enum reboot_mode mode, const char *cmd) diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h index e256e0b..4c0bbd9 100644 --- a/arch/arm/mach-ep93xx/include/mach/platform.h +++ b/arch/arm/mach-ep93xx/include/mach/platform.h @@ -6,6 +6,7 @@ #include <linux/reboot.h> +struct device; struct i2c_gpio_platform_data; struct i2c_board_info; struct spi_board_info; @@ -54,7 +55,7 @@ void ep93xx_register_ide(void); int ep93xx_ide_acquire_gpio(struct platform_device *pdev); void ep93xx_ide_release_gpio(struct platform_device *pdev); -void ep93xx_init_devices(void); +struct device *ep93xx_init_devices(void); extern void ep93xx_timer_init(void); void ep93xx_restart(enum reboot_mode, const char *); diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index f9d67a0..4c414af 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -24,6 +24,7 @@ config ARCH_EXYNOS4 select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL + select PM_GENERIC_DOMAINS if PM select S5P_DEV_MFC help Samsung EXYNOS4 SoCs based systems @@ -48,7 +49,6 @@ config CPU_EXYNOS4210 select ARCH_HAS_BANDGAP select ARM_CPU_SUSPEND if PM select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM select S5P_PM if PM select S5P_SLEEP if PM select SAMSUNG_DMADEV @@ -61,7 +61,6 @@ config SOC_EXYNOS4212 depends on ARCH_EXYNOS4 select ARCH_HAS_BANDGAP select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM select S5P_PM if PM select S5P_SLEEP if PM select SAMSUNG_DMADEV @@ -74,7 +73,6 @@ config SOC_EXYNOS4412 depends on ARCH_EXYNOS4 select ARCH_HAS_BANDGAP select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM select SAMSUNG_DMADEV help Enable EXYNOS4412 SoC support diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 61d2906..72ae5d3 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -23,6 +23,7 @@ #include <linux/of.h> #include <linux/of_fdt.h> #include <linux/of_irq.h> +#include <linux/pm_domain.h> #include <linux/export.h> #include <linux/irqdomain.h> #include <linux/of_address.h> @@ -37,14 +38,13 @@ #include <asm/mach/irq.h> #include <asm/cacheflush.h> -#include <mach/regs-irq.h> -#include <mach/regs-pmu.h> - #include <plat/cpu.h> #include <plat/pm.h> #include <plat/regs-serial.h> #include "common.h" +#include "regs-pmu.h" + #define L2_AUX_VAL 0x7C470001 #define L2_AUX_MASK 0xC200ffff @@ -309,7 +309,7 @@ void __init exynos_init_late(void) /* to be supported later */ return; - exynos_pm_late_initcall(); + pm_genpd_poweroff_unused(); } static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index ff9b6a9..0c31b34 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -26,12 +26,6 @@ void exynos_init_late(void); void exynos_firmware_init(void); -#ifdef CONFIG_PM_GENERIC_DOMAINS -int exynos_pm_late_initcall(void); -#else -static inline int exynos_pm_late_initcall(void) { return 0; } -#endif - extern struct smp_operations exynos_smp_ops; extern void exynos_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index ddbfe87..da65b03 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -22,13 +22,15 @@ #include <asm/suspend.h> #include <asm/unified.h> #include <asm/cpuidle.h> -#include <mach/regs-clock.h> -#include <mach/regs-pmu.h> #include <plat/cpu.h> #include <plat/pm.h> +#include <mach/pm-core.h> +#include <mach/map.h> + #include "common.h" +#include "regs-pmu.h" #define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ @@ -39,6 +41,25 @@ #define S5P_CHECK_AFTR 0xFCBA0D10 +#define EXYNOS5_PWR_CTRL1 (S5P_VA_CMU + 0x01020) +#define EXYNOS5_PWR_CTRL2 (S5P_VA_CMU + 0x01024) + +#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) +#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) +#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) +#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) +#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) +#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) +#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) +#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) + +#define PWR_CTRL2_DIV2_UP_EN (1 << 25) +#define PWR_CTRL2_DIV1_UP_EN (1 << 24) +#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) +#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) +#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) +#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) + static int exynos4_enter_lowpower(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c index af90cfa..5eead53 100644 --- a/arch/arm/mach-exynos/hotplug.c +++ b/arch/arm/mach-exynos/hotplug.c @@ -19,10 +19,10 @@ #include <asm/cp15.h> #include <asm/smp_plat.h> -#include <mach/regs-pmu.h> #include <plat/cpu.h> #include "common.h" +#include "regs-pmu.h" static inline void cpu_enter_lowpower_a9(void) { diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h index 2b00833..dc0697c 100644 --- a/arch/arm/mach-exynos/include/mach/pm-core.h +++ b/arch/arm/mach-exynos/include/mach/pm-core.h @@ -19,7 +19,10 @@ #define __ASM_ARCH_PM_CORE_H __FILE__ #include <linux/of.h> -#include <mach/regs-pmu.h> +#include <mach/map.h> + +#define S5P_EINT_WAKEUP_MASK (S5P_VA_PMU + 0x0604) +#define S5P_WAKEUP_MASK (S5P_VA_PMU + 0x0608) #ifdef CONFIG_PINCTRL_EXYNOS extern u32 exynos_get_eint_wake_mask(void); diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h deleted file mode 100644 index d36ad76..0000000 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ /dev/null @@ -1,372 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - Clock register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_CLOCK_H -#define __ASM_ARCH_REGS_CLOCK_H __FILE__ - -#include <plat/cpu.h> -#include <mach/map.h> - -#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x)) - -#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500) -#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600) -#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800) - -#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500) -#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600) -#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800) - -#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010) -#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020) - -#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110) -#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114) -#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120) -#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124) - -#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210) -#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214) -#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220) -#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224) -#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228) -#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C) -#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230) -#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234) -#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C) -#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240) -#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250) -#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254) - -#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310) -#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320) -#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324) -#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334) -#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C) -#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340) -#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350) -#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354) - -#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510) -#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520) -#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524) -#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528) -#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C) -#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530) -#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534) -#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C) -#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540) -#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544) -#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548) -#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C) -#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550) -#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554) -#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558) -#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C) -#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560) -#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564) -#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580) - -#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610) -#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628) - -#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820) -#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920) -#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924) -#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928) -#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C) -#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x0C930) : \ - EXYNOS_CLKREG(0x04930)) -#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930) -#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930) -#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934) -#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940) -#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C) -#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950) -#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x0C960) : \ - EXYNOS_CLKREG(0x08960)) -#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960) -#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960) -#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970) - -#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300) -#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200) -#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500) -#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504) -#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600) -#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604) -#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900) - -#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094) -#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0) - -#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000) -#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x14004) : \ - EXYNOS_CLKREG(0x10008)) -#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100) -#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104) -#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x14108) : \ - EXYNOS_CLKREG(0x10108)) -#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x1410C) : \ - EXYNOS_CLKREG(0x1010C)) - -#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200) -#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400) - -#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500) -#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504) -#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600) -#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604) - -#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800) -#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900) - -#define EXYNOS4_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x18800) -#define EXYNOS4_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x18804) - -#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */ - -#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31) -#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29) -#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) -#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) - -#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31) -#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) - -#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31) -#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) - -#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) -#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) - -#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0) -#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4) -#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8) -#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12) -#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16) -#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20) -#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24) -#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28 -#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT) - -#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0 -#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) -#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4 -#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) -#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8 -#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT) - -#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) -#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4) -#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8) -#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12) -#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16) -#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20) -#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24) -#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28) -#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT) - -#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0) -#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4) -#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8) -#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12) -#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16) -#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24) -#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT) - -#define EXYNOS4_CLKDIV_MFC_SHIFT (0) -#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT) - -#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0) -#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4) -#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8) -#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12) -#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16) -#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20) -#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24) -#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT) - -#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0) -#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) -#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4) -#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT) - -#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0) -#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) -#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4) -#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) -#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8) -#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) -#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12) -#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT) - -/* Only for EXYNOS4210 */ - -#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238) -#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338) -#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538) -#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938) - -/* Only for EXYNOS4212 */ - -#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568) - -#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668) - -#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) -#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) - -/* For EXYNOS5250 */ - -#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000) -#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100) -#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200) -#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400) -#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500) -#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504) -#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600) -#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604) - -#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020) -#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024) - -#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100) -#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204) - -#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900) - -#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500) - -#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130) -#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134) -#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138) -#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140) -#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144) -#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148) -#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120) - -#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210) -#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214) -#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218) -#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C) -#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220) -#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C) -#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240) -#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244) -#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250) -#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254) -#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270) - -#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310) -#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320) -#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C) -#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334) -#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340) -#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350) -#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354) - -#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510) -#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514) -#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520) -#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C) -#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C) -#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544) -#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548) -#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C) -#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550) -#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554) -#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558) -#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C) -#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560) -#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564) -#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568) -#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C) -#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580) - -#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800) -#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800) -#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804) -#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920) -#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928) -#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C) -#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930) -#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934) -#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944) -#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C) -#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950) -#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960) -#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980) - -#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110) -#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) -#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) - -#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24) - -#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030) - -#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) - -#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) -#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) -#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) -#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) -#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) -#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) -#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) -#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) - -#define PWR_CTRL2_DIV2_UP_EN (1 << 25) -#define PWR_CTRL2_DIV1_UP_EN (1 << 24) -#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) -#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) -#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) -#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) - -/* Compatibility defines and inclusion */ - -#include <mach/regs-pmu.h> - -#define S5P_EPLL_CON EXYNOS4_EPLL_CON0 - -#endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-exynos/include/mach/regs-irq.h b/arch/arm/mach-exynos/include/mach/regs-irq.h deleted file mode 100644 index f2b5050..0000000 --- a/arch/arm/mach-exynos/include/mach/regs-irq.h +++ /dev/null @@ -1,19 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - IRQ register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_IRQ_H -#define __ASM_ARCH_REGS_IRQ_H __FILE__ - -#include <linux/irqchip/arm-gic.h> -#include <mach/map.h> - -#endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 1fe075a..65a4646 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -14,10 +14,10 @@ #include <linux/io.h> #include <asm/mach/arch.h> -#include <mach/regs-pmu.h> #include <plat/mfc.h> #include "common.h" +#include "regs-pmu.h" static void __init exynos5_dt_machine_init(void) { diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 58b43e6..8ea02f6 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -27,12 +27,11 @@ #include <asm/firmware.h> #include <mach/hardware.h> -#include <mach/regs-clock.h> -#include <mach/regs-pmu.h> #include <plat/cpu.h> #include "common.h" +#include "regs-pmu.h" extern void exynos4_secondary_startup(void); @@ -64,8 +63,7 @@ static void write_pen_release(int val) { pen_release = val; smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + sync_cache_w(&pen_release); } static void __iomem *scu_base_addr(void) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index c679db5..e00025b 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -29,14 +29,37 @@ #include <plat/pll.h> #include <plat/regs-srom.h> -#include <mach/regs-irq.h> -#include <mach/regs-clock.h> -#include <mach/regs-pmu.h> +#include <mach/map.h> #include <mach/pm-core.h> #include "common.h" +#include "regs-pmu.h" -static struct sleep_save exynos4_set_clksrc[] = { +#define EXYNOS4_EPLL_LOCK (S5P_VA_CMU + 0x0C010) +#define EXYNOS4_VPLL_LOCK (S5P_VA_CMU + 0x0C020) + +#define EXYNOS4_EPLL_CON0 (S5P_VA_CMU + 0x0C110) +#define EXYNOS4_EPLL_CON1 (S5P_VA_CMU + 0x0C114) +#define EXYNOS4_VPLL_CON0 (S5P_VA_CMU + 0x0C120) +#define EXYNOS4_VPLL_CON1 (S5P_VA_CMU + 0x0C124) + +#define EXYNOS4_CLKSRC_MASK_TOP (S5P_VA_CMU + 0x0C310) +#define EXYNOS4_CLKSRC_MASK_CAM (S5P_VA_CMU + 0x0C320) +#define EXYNOS4_CLKSRC_MASK_TV (S5P_VA_CMU + 0x0C324) +#define EXYNOS4_CLKSRC_MASK_LCD0 (S5P_VA_CMU + 0x0C334) +#define EXYNOS4_CLKSRC_MASK_MAUDIO (S5P_VA_CMU + 0x0C33C) +#define EXYNOS4_CLKSRC_MASK_FSYS (S5P_VA_CMU + 0x0C340) +#define EXYNOS4_CLKSRC_MASK_PERIL0 (S5P_VA_CMU + 0x0C350) +#define EXYNOS4_CLKSRC_MASK_PERIL1 (S5P_VA_CMU + 0x0C354) + +#define EXYNOS4_CLKSRC_MASK_DMC (S5P_VA_CMU + 0x10300) + +#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) +#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) + +#define EXYNOS4210_CLKSRC_MASK_LCD1 (S5P_VA_CMU + 0x0C338) + +static const struct sleep_save exynos4_set_clksrc[] = { { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, }, { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, }, @@ -48,7 +71,7 @@ static struct sleep_save exynos4_set_clksrc[] = { { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, }, }; -static struct sleep_save exynos4210_set_clksrc[] = { +static const struct sleep_save exynos4210_set_clksrc[] = { { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, }; diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 1703593..8fd2488 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -22,9 +22,10 @@ #include <linux/of_platform.h> #include <linux/sched.h> -#include <mach/regs-pmu.h> #include <plat/devs.h> +#include "regs-pmu.h" + /* * Exynos specific wrapper around the generic power domain */ @@ -183,9 +184,3 @@ static __init int exynos4_pm_init_power_domain(void) return 0; } arch_initcall(exynos4_pm_init_power_domain); - -int __init exynos_pm_late_initcall(void) -{ - pm_genpd_poweroff_unused(); - return 0; -} diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index 97d6885..05c7ce1 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -13,13 +13,14 @@ #include <linux/kernel.h> #include <linux/bug.h> -#include <mach/regs-clock.h> +#include <plat/cpu.h> #include "common.h" +#include "regs-pmu.h" -static struct exynos_pmu_conf *exynos_pmu_config; +static const struct exynos_pmu_conf *exynos_pmu_config; -static struct exynos_pmu_conf exynos4210_pmu_config[] = { +static const struct exynos_pmu_conf exynos4210_pmu_config[] = { /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, @@ -95,7 +96,7 @@ static struct exynos_pmu_conf exynos4210_pmu_config[] = { { PMU_TABLE_END,}, }; -static struct exynos_pmu_conf exynos4x12_pmu_config[] = { +static const struct exynos_pmu_conf exynos4x12_pmu_config[] = { { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, @@ -203,7 +204,7 @@ static struct exynos_pmu_conf exynos4x12_pmu_config[] = { { PMU_TABLE_END,}, }; -static struct exynos_pmu_conf exynos4412_pmu_config[] = { +static const struct exynos_pmu_conf exynos4412_pmu_config[] = { { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, @@ -213,7 +214,7 @@ static struct exynos_pmu_conf exynos4412_pmu_config[] = { { PMU_TABLE_END,}, }; -static struct exynos_pmu_conf exynos5250_pmu_config[] = { +static const struct exynos_pmu_conf exynos5250_pmu_config[] = { /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, @@ -317,7 +318,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = { { PMU_TABLE_END,}, }; -static void __iomem *exynos5_list_both_cnt_feed[] = { +static void __iomem * const exynos5_list_both_cnt_feed[] = { EXYNOS5_ARM_CORE0_OPTION, EXYNOS5_ARM_CORE1_OPTION, EXYNOS5_ARM_COMMON_OPTION, @@ -331,7 +332,7 @@ static void __iomem *exynos5_list_both_cnt_feed[] = { EXYNOS5_TOP_PWR_SYSMEM_OPTION, }; -static void __iomem *exynos5_list_diable_wfi_wfe[] = { +static void __iomem * const exynos5_list_diable_wfi_wfe[] = { EXYNOS5_ARM_CORE1_OPTION, EXYNOS5_FSYS_ARM_OPTION, EXYNOS5_ISP_ARM_OPTION, diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 2cdb63e..7c029ce 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -24,31 +24,16 @@ #define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208) #define S5P_USE_STANDBY_WFI0 (1 << 16) -#define S5P_USE_STANDBY_WFI1 (1 << 17) -#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18) #define S5P_USE_STANDBY_WFE0 (1 << 24) -#define S5P_USE_STANDBY_WFE1 (1 << 25) -#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26) #define S5P_SWRESET S5P_PMUREG(0x0400) #define EXYNOS_SWRESET S5P_PMUREG(0x0400) #define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4) #define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) -#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) -#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) - -#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700) -#define S5P_HDMI_PHY_ENABLE (1 << 0) - -#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C) -#define S5P_DAC_PHY_ENABLE (1 << 0) #define S5P_INFORM0 S5P_PMUREG(0x0800) #define S5P_INFORM1 S5P_PMUREG(0x0804) -#define S5P_INFORM2 S5P_PMUREG(0x0808) -#define S5P_INFORM3 S5P_PMUREG(0x080C) -#define S5P_INFORM4 S5P_PMUREG(0x0810) #define S5P_INFORM5 S5P_PMUREG(0x0814) #define S5P_INFORM6 S5P_PMUREG(0x0818) #define S5P_INFORM7 S5P_PMUREG(0x081C) @@ -119,23 +104,8 @@ #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) -#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) -#define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008) #define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) #define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084) -#define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088) - -#define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408) -#define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48) -#define S5P_CAM_OPTION S5P_PMUREG(0x3C08) -#define S5P_TV_OPTION S5P_PMUREG(0x3C28) -#define S5P_MFC_OPTION S5P_PMUREG(0x3C48) -#define S5P_G3D_OPTION S5P_PMUREG(0x3C68) -#define S5P_LCD0_OPTION S5P_PMUREG(0x3C88) -#define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8) -#define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8) -#define S5P_GPS_OPTION S5P_PMUREG(0x3CE8) -#define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08) #define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) #define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108) @@ -145,28 +115,12 @@ #define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188) #define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) -#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) -#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) -#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) -#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) -#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) -#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) - -#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 #define S5P_CORE_LOCAL_PWR_EN 0x3 #define S5P_INT_LOCAL_PWR_EN 0x7 #define S5P_CHECK_SLEEP 0x00000BAD /* Only for EXYNOS4210 */ -#define S5P_USBDEVICE_PHY_CONTROL S5P_PMUREG(0x0704) -#define S5P_USBDEVICE_PHY_ENABLE (1 << 0) - -#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708) -#define S5P_USBHOST_PHY_ENABLE (1 << 0) - -#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720) - #define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) #define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) #define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) @@ -174,8 +128,6 @@ #define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) #define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) -#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) - /* Only for EXYNOS4x12 */ #define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) @@ -343,13 +295,9 @@ #define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48) #define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8) #define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48) -#define EXYNOS5_GSCL_STATUS S5P_PMUREG(0x4004) -#define EXYNOS5_ISP_STATUS S5P_PMUREG(0x4024) #define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008) #define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028) #define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048) -#define EXYNOS5_G3D_CONFIGURATION S5P_PMUREG(0x4060) -#define EXYNOS5_G3D_STATUS S5P_PMUREG(0x4064) #define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068) #define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8) #define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8) @@ -357,7 +305,6 @@ #define EXYNOS5_USE_SC_FEEDBACK (1 << 1) #define EXYNOS5_USE_SC_COUNTER (1 << 0) -#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL (1 << 2) #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) #define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24) diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index e009168..9e8220e 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -143,11 +143,6 @@ static struct map_desc fb_common_io_desc[] __initdata = { .pfn = __phys_to_pfn(DC21285_ARMCSR_BASE), .length = ARMCSR_SIZE, .type = MT_DEVICE, - }, { - .virtual = XBUS_BASE, - .pfn = __phys_to_pfn(0x40000000), - .length = XBUS_SIZE, - .type = MT_DEVICE, } }; diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h index 56607b3..b911e55 100644 --- a/arch/arm/mach-footbridge/common.h +++ b/arch/arm/mach-footbridge/common.h @@ -10,3 +10,5 @@ extern void footbridge_init_irq(void); extern void isa_init_irq(unsigned int irq); extern void footbridge_restart(enum reboot_mode, const char *); + +extern void footbridge_sched_clock(void); diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index 782f6c7..3971104 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c @@ -9,6 +9,7 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/sched_clock.h> #include <asm/irq.h> @@ -46,6 +47,16 @@ static struct clocksource cksrc_dc21285 = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +static int ckevt_dc21285_set_next_event(unsigned long delta, + struct clock_event_device *c) +{ + *CSR_TIMER1_CLR = 0; + *CSR_TIMER1_LOAD = delta; + *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; + + return 0; +} + static void ckevt_dc21285_set_mode(enum clock_event_mode mode, struct clock_event_device *c) { @@ -58,7 +69,9 @@ static void ckevt_dc21285_set_mode(enum clock_event_mode mode, TIMER_CNTL_DIV16; break; - default: + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: *CSR_TIMER1_CNTL = 0; break; } @@ -66,9 +79,11 @@ static void ckevt_dc21285_set_mode(enum clock_event_mode mode, static struct clock_event_device ckevt_dc21285 = { .name = "dc21285_timer1", - .features = CLOCK_EVT_FEAT_PERIODIC, + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, .rating = 200, .irq = IRQ_TIMER1, + .set_next_event = ckevt_dc21285_set_next_event, .set_mode = ckevt_dc21285_set_mode, }; @@ -78,6 +93,10 @@ static irqreturn_t timer1_interrupt(int irq, void *dev_id) *CSR_TIMER1_CLR = 0; + /* Stop the timer if in one-shot mode */ + if (ce->mode == CLOCK_EVT_MODE_ONESHOT) + *CSR_TIMER1_CNTL = 0; + ce->event_handler(ce); return IRQ_HANDLED; @@ -105,3 +124,19 @@ void __init footbridge_timer_init(void) ce->cpumask = cpumask_of(smp_processor_id()); clockevents_config_and_register(ce, rate, 0x4, 0xffffff); } + +static u32 notrace footbridge_read_sched_clock(void) +{ + return ~*CSR_TIMER3_VALUE; +} + +void __init footbridge_sched_clock(void) +{ + unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16); + + *CSR_TIMER3_LOAD = 0; + *CSR_TIMER3_CLR = 0; + *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; + + setup_sched_clock(footbridge_read_sched_clock, 24, rate); +} diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c index 1a7235f..aee8300 100644 --- a/arch/arm/mach-footbridge/ebsa285.c +++ b/arch/arm/mach-footbridge/ebsa285.c @@ -4,6 +4,7 @@ * EBSA285 machine fixup */ #include <linux/init.h> +#include <linux/io.h> #include <linux/spinlock.h> #include <linux/slab.h> #include <linux/leds.h> @@ -17,6 +18,11 @@ /* LEDs */ #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS) +#define XBUS_AMBER_L BIT(0) +#define XBUS_GREEN_L BIT(1) +#define XBUS_RED_L BIT(2) +#define XBUS_TOGGLE BIT(7) + struct ebsa285_led { struct led_classdev cdev; u8 mask; @@ -36,6 +42,7 @@ static const struct { }; static unsigned char hw_led_state; +static void __iomem *xbus; static void ebsa285_led_set(struct led_classdev *cdev, enum led_brightness b) @@ -47,7 +54,7 @@ static void ebsa285_led_set(struct led_classdev *cdev, hw_led_state |= led->mask; else hw_led_state &= ~led->mask; - *XBUS_LEDS = hw_led_state; + writeb(hw_led_state, xbus); } static enum led_brightness ebsa285_led_get(struct led_classdev *cdev) @@ -65,9 +72,13 @@ static int __init ebsa285_leds_init(void) if (!machine_is_ebsa285()) return -ENODEV; + xbus = ioremap(XBUS_CS2, SZ_4K); + if (!xbus) + return -ENOMEM; + /* 3 LEDS all off */ - hw_led_state = XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED; - *XBUS_LEDS = hw_led_state; + hw_led_state = XBUS_AMBER_L | XBUS_GREEN_L | XBUS_RED_L; + writeb(hw_led_state, xbus); for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) { struct ebsa285_led *led; @@ -104,6 +115,7 @@ MACHINE_START(EBSA285, "EBSA285") .video_start = 0x000a0000, .video_end = 0x000bffff, .map_io = footbridge_map_io, + .init_early = footbridge_sched_clock, .init_irq = footbridge_init_irq, .init_time = footbridge_timer_init, .restart = footbridge_restart, diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h index e3d6cca..02f6d7a 100644 --- a/arch/arm/mach-footbridge/include/mach/hardware.h +++ b/arch/arm/mach-footbridge/include/mach/hardware.h @@ -51,11 +51,7 @@ #define PCIMEM_SIZE 0x01000000 #define PCIMEM_BASE MMU_IO(0xf0000000, 0x80000000) -#define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000)) -#define XBUS_LED_AMBER (1 << 0) -#define XBUS_LED_GREEN (1 << 1) -#define XBUS_LED_RED (1 << 2) -#define XBUS_LED_TOGGLE (1 << 8) +#define XBUS_CS2 0x40012000 #define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000)) #define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15) diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig new file mode 100644 index 0000000..018ad67 --- /dev/null +++ b/arch/arm/mach-hisi/Kconfig @@ -0,0 +1,17 @@ +config ARCH_HI3xxx + bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7 + select ARM_AMBA + select ARM_GIC + select ARM_TIMER_SP804 + select ARCH_WANT_OPTIONAL_GPIOLIB + select CACHE_L2X0 + select CLKSRC_OF + select GENERIC_CLOCKEVENTS + select HAVE_ARM_SCU + select HAVE_ARM_TWD + select HAVE_SMP + select PINCTRL + select PINCTRL_SINGLE + select SMP + help + Support for Hisilicon Hi36xx/Hi37xx processor family diff --git a/arch/arm/mach-hisi/Makefile b/arch/arm/mach-hisi/Makefile new file mode 100644 index 0000000..6870058 --- /dev/null +++ b/arch/arm/mach-hisi/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for Hisilicon processors family +# + +obj-y += hisilicon.o +obj-$(CONFIG_SMP) += platsmp.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-hisi/core.h b/arch/arm/mach-hisi/core.h new file mode 100644 index 0000000..af23ec2 --- /dev/null +++ b/arch/arm/mach-hisi/core.h @@ -0,0 +1,15 @@ +#ifndef __HISILICON_CORE_H +#define __HISILICON_CORE_H + +#include <linux/reboot.h> + +extern void hi3xxx_set_cpu_jump(int cpu, void *jump_addr); +extern int hi3xxx_get_cpu_jump(int cpu); +extern void secondary_startup(void); +extern struct smp_operations hi3xxx_smp_ops; + +extern void hi3xxx_cpu_die(unsigned int cpu); +extern int hi3xxx_cpu_kill(unsigned int cpu); +extern void hi3xxx_set_cpu(int cpu, bool enable); + +#endif diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c new file mode 100644 index 0000000..741faf3 --- /dev/null +++ b/arch/arm/mach-hisi/hisilicon.c @@ -0,0 +1,90 @@ +/* + * (Hisilicon's SoC based) flattened device tree enabled machine + * + * Copyright (c) 2012-2013 Hisilicon Ltd. + * Copyright (c) 2012-2013 Linaro Ltd. + * + * Author: Haojian Zhuang <haojian.zhuang@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/clk-provider.h> +#include <linux/clocksource.h> +#include <linux/irqchip.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> + +#include <asm/proc-fns.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include "core.h" + +#define HI3620_SYSCTRL_PHYS_BASE 0xfc802000 +#define HI3620_SYSCTRL_VIRT_BASE 0xfe802000 + +/* + * This table is only for optimization. Since ioremap() could always share + * the same mapping if it's defined as static IO mapping. + * + * Without this table, system could also work. The cost is some virtual address + * spaces wasted since ioremap() may be called multi times for the same + * IO space. + */ +static struct map_desc hi3620_io_desc[] __initdata = { + { + /* sysctrl */ + .pfn = __phys_to_pfn(HI3620_SYSCTRL_PHYS_BASE), + .virtual = HI3620_SYSCTRL_VIRT_BASE, + .length = 0x1000, + .type = MT_DEVICE, + }, +}; + +static void __init hi3620_map_io(void) +{ + debug_ll_io_init(); + iotable_init(hi3620_io_desc, ARRAY_SIZE(hi3620_io_desc)); +} + +static void hi3xxx_restart(enum reboot_mode mode, const char *cmd) +{ + struct device_node *np; + void __iomem *base; + int offset; + + np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); + if (!np) { + pr_err("failed to find hisilicon,sysctrl node\n"); + return; + } + base = of_iomap(np, 0); + if (!base) { + pr_err("failed to map address in hisilicon,sysctrl node\n"); + return; + } + if (of_property_read_u32(np, "reboot-offset", &offset) < 0) { + pr_err("failed to find reboot-offset property\n"); + return; + } + writel_relaxed(0xdeadbeef, base + offset); + + while (1) + cpu_do_idle(); +} + +static const char *hi3xxx_compat[] __initconst = { + "hisilicon,hi3620-hi4511", + NULL, +}; + +DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)") + .map_io = hi3620_map_io, + .dt_compat = hi3xxx_compat, + .smp = smp_ops(hi3xxx_smp_ops), + .restart = hi3xxx_restart, +MACHINE_END diff --git a/arch/arm/mach-hisi/hotplug.c b/arch/arm/mach-hisi/hotplug.c new file mode 100644 index 0000000..b909854 --- /dev/null +++ b/arch/arm/mach-hisi/hotplug.c @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2013 Linaro Ltd. + * Copyright (c) 2013 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#include <linux/cpu.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <asm/cacheflush.h> +#include <asm/smp_plat.h> +#include "core.h" + +/* Sysctrl registers in Hi3620 SoC */ +#define SCISOEN 0xc0 +#define SCISODIS 0xc4 +#define SCPERPWREN 0xd0 +#define SCPERPWRDIS 0xd4 +#define SCCPUCOREEN 0xf4 +#define SCCPUCOREDIS 0xf8 +#define SCPERCTRL0 0x200 +#define SCCPURSTEN 0x410 +#define SCCPURSTDIS 0x414 + +/* + * bit definition in SCISOEN/SCPERPWREN/... + * + * CPU2_ISO_CTRL (1 << 5) + * CPU3_ISO_CTRL (1 << 6) + * ... + */ +#define CPU2_ISO_CTRL (1 << 5) + +/* + * bit definition in SCPERCTRL0 + * + * CPU0_WFI_MASK_CFG (1 << 28) + * CPU1_WFI_MASK_CFG (1 << 29) + * ... + */ +#define CPU0_WFI_MASK_CFG (1 << 28) + +/* + * bit definition in SCCPURSTEN/... + * + * CPU0_SRST_REQ_EN (1 << 0) + * CPU1_SRST_REQ_EN (1 << 1) + * ... + */ +#define CPU0_HPM_SRST_REQ_EN (1 << 22) +#define CPU0_DBG_SRST_REQ_EN (1 << 12) +#define CPU0_NEON_SRST_REQ_EN (1 << 4) +#define CPU0_SRST_REQ_EN (1 << 0) + +enum { + HI3620_CTRL, + ERROR_CTRL, +}; + +static void __iomem *ctrl_base; +static int id; + +static void set_cpu_hi3620(int cpu, bool enable) +{ + u32 val = 0; + + if (enable) { + /* MTCMOS set */ + if ((cpu == 2) || (cpu == 3)) + writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), + ctrl_base + SCPERPWREN); + udelay(100); + + /* Enable core */ + writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN); + + /* unreset */ + val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN + | CPU0_SRST_REQ_EN; + writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); + /* reset */ + val |= CPU0_HPM_SRST_REQ_EN; + writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); + + /* ISO disable */ + if ((cpu == 2) || (cpu == 3)) + writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), + ctrl_base + SCISODIS); + udelay(1); + + /* WFI Mask */ + val = readl_relaxed(ctrl_base + SCPERCTRL0); + val &= ~(CPU0_WFI_MASK_CFG << cpu); + writel_relaxed(val, ctrl_base + SCPERCTRL0); + + /* Unreset */ + val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN + | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN; + writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); + } else { + /* wfi mask */ + val = readl_relaxed(ctrl_base + SCPERCTRL0); + val |= (CPU0_WFI_MASK_CFG << cpu); + writel_relaxed(val, ctrl_base + SCPERCTRL0); + + /* disable core*/ + writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS); + + if ((cpu == 2) || (cpu == 3)) { + /* iso enable */ + writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), + ctrl_base + SCISOEN); + udelay(1); + } + + /* reset */ + val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN + | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN; + writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); + + if ((cpu == 2) || (cpu == 3)) { + /* MTCMOS unset */ + writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), + ctrl_base + SCPERPWRDIS); + udelay(100); + } + } +} + +static int hi3xxx_hotplug_init(void) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); + if (node) { + ctrl_base = of_iomap(node, 0); + id = HI3620_CTRL; + return 0; + } + id = ERROR_CTRL; + return -ENOENT; +} + +void hi3xxx_set_cpu(int cpu, bool enable) +{ + if (!ctrl_base) { + if (hi3xxx_hotplug_init() < 0) + return; + } + + if (id == HI3620_CTRL) + set_cpu_hi3620(cpu, enable); +} + +static inline void cpu_enter_lowpower(void) +{ + unsigned int v; + + flush_cache_all(); + + /* + * Turn off coherency and L1 D-cache + */ + asm volatile( + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, #0x40\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, #0x04\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0) + : "cc"); +} + +void hi3xxx_cpu_die(unsigned int cpu) +{ + cpu_enter_lowpower(); + hi3xxx_set_cpu_jump(cpu, phys_to_virt(0)); + cpu_do_idle(); + + /* We should have never returned from idle */ + panic("cpu %d unexpectedly exit from shutdown\n", cpu); +} + +int hi3xxx_cpu_kill(unsigned int cpu) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(50); + + while (hi3xxx_get_cpu_jump(cpu)) + if (time_after(jiffies, timeout)) + return 0; + hi3xxx_set_cpu(cpu, false); + return 1; +} diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c new file mode 100644 index 0000000..471f1ee --- /dev/null +++ b/arch/arm/mach-hisi/platsmp.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2013 Linaro Ltd. + * Copyright (c) 2013 Hisilicon Limited. + * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ +#include <linux/smp.h> +#include <linux/io.h> +#include <linux/of_address.h> + +#include <asm/cacheflush.h> +#include <asm/smp_plat.h> +#include <asm/smp_scu.h> + +#include "core.h" + +static void __iomem *ctrl_base; + +void hi3xxx_set_cpu_jump(int cpu, void *jump_addr) +{ + cpu = cpu_logical_map(cpu); + if (!cpu || !ctrl_base) + return; + writel_relaxed(virt_to_phys(jump_addr), ctrl_base + ((cpu - 1) << 2)); +} + +int hi3xxx_get_cpu_jump(int cpu) +{ + cpu = cpu_logical_map(cpu); + if (!cpu || !ctrl_base) + return 0; + return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); +} + +static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *np = NULL; + unsigned long base = 0; + u32 offset = 0; + void __iomem *scu_base = NULL; + + if (scu_a9_has_base()) { + base = scu_a9_get_base(); + scu_base = ioremap(base, SZ_4K); + if (!scu_base) { + pr_err("ioremap(scu_base) failed\n"); + return; + } + scu_enable(scu_base); + iounmap(scu_base); + } + if (!ctrl_base) { + np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); + if (!np) { + pr_err("failed to find hisilicon,sysctrl node\n"); + return; + } + ctrl_base = of_iomap(np, 0); + if (!ctrl_base) { + pr_err("failed to map address\n"); + return; + } + if (of_property_read_u32(np, "smp-offset", &offset) < 0) { + pr_err("failed to find smp-offset property\n"); + return; + } + ctrl_base += offset; + } +} + +static int hi3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + hi3xxx_set_cpu(cpu, true); + hi3xxx_set_cpu_jump(cpu, secondary_startup); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + return 0; +} + +struct smp_operations hi3xxx_smp_ops __initdata = { + .smp_prepare_cpus = hi3xxx_smp_prepare_cpus, + .smp_boot_secondary = hi3xxx_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = hi3xxx_cpu_die, + .cpu_kill = hi3xxx_cpu_kill, +#endif +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 7a6e6f7..33567aa 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -3,7 +3,6 @@ config ARCH_MXC select ARCH_REQUIRE_GPIOLIB select ARM_CPU_SUSPEND if PM select ARM_PATCH_PHYS_VIRT - select AUTO_ZRELADDR if !ZBOOT_ROM select CLKSRC_MMIO select COMMON_CLK select GENERIC_ALLOCATOR @@ -11,6 +10,7 @@ config ARCH_MXC select GENERIC_IRQ_CHIP select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7 select MULTI_IRQ_HANDLER + select PINCTRL select SOC_BUS select SPARSE_IRQ select USE_OF @@ -20,16 +20,6 @@ config ARCH_MXC menu "Freescale i.MX support" depends on ARCH_MXC -config MXC_IRQ_PRIOR - bool "Use IRQ priority" - help - Select this if you want to use prioritized IRQ handling. - This feature prevents higher priority ISR to be interrupted - by lower priority IRQ. - This may be useful in embedded applications, where are strong - requirements for timing. - Say N here, unless you have a specialized requirement. - config MXC_TZIC bool @@ -109,6 +99,7 @@ config SOC_IMX25 select ARCH_MXC_IOMUX_V3 select CPU_ARM926T select MXC_AVIC + select PINCTRL_IMX25 config SOC_IMX27 bool @@ -118,6 +109,7 @@ config SOC_IMX27 select IMX_HAVE_IOMUX_V1 select MACH_MX27 select MXC_AVIC + select PINCTRL_IMX27 config SOC_IMX31 bool @@ -133,6 +125,7 @@ config SOC_IMX35 select HAVE_EPIT select MXC_AVIC select SMP_ON_UP if SMP + select PINCTRL config SOC_IMX5 bool @@ -145,7 +138,6 @@ config SOC_IMX5 config SOC_IMX51 bool select HAVE_IMX_SRC - select PINCTRL select PINCTRL_IMX51 select SOC_IMX5 @@ -619,6 +611,13 @@ config MACH_IMX31_DT comment "MX35 platforms:" +config MACH_IMX35_DT + bool "Support i.MX35 platforms from device tree" + select SOC_IMX35 + help + Include support for Freescale i.MX35 based platforms + using the device tree for discovery. + config MACH_PCM043 bool "Support Phytec pcm043 (i.MX35) platforms" select IMX_HAVE_PLATFORM_FLEXCAN @@ -766,11 +765,19 @@ endchoice comment "Device tree only" +config SOC_IMX50 + bool "i.MX50 support" + select HAVE_IMX_SRC + select PINCTRL_IMX50 + select SOC_IMX5 + + help + This enables support for Freescale i.MX50 processor. + config SOC_IMX53 bool "i.MX53 support" select HAVE_IMX_SRC select IMX_HAVE_PLATFORM_IMX2_WDT - select PINCTRL select PINCTRL_IMX53 select SOC_IMX5 @@ -796,7 +803,6 @@ config SOC_IMX6Q select MFD_SYSCON select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI - select PINCTRL select PINCTRL_IMX6Q select PL310_ERRATA_588369 if CACHE_PL310 select PL310_ERRATA_727915 if CACHE_PL310 @@ -817,7 +823,6 @@ config SOC_IMX6SL select HAVE_IMX_MMDC select HAVE_IMX_SRC select MFD_SYSCON - select PINCTRL select PINCTRL_IMX6SL select PL310_ERRATA_588369 if CACHE_PL310 select PL310_ERRATA_727915 if CACHE_PL310 @@ -831,7 +836,6 @@ config SOC_VF610 select CPU_V7 select ARM_GIC select CLKSRC_OF - select PINCTRL select PINCTRL_VF610 select VF_PIT_TIMER select PL310_ERRATA_588369 if CACHE_PL310 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 1789e2b..befcaf5 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o +obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o @@ -112,6 +113,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o +obj-$(CONFIG_SOC_IMX50) += mach-imx50.o obj-$(CONFIG_SOC_IMX53) += mach-imx53.o obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c index e163ec7..8d1df2e 100644 --- a/arch/arm/mach-imx/avic.c +++ b/arch/arm/mach-imx/avic.c @@ -54,28 +54,6 @@ static void __iomem *avic_base; static struct irq_domain *domain; -#ifdef CONFIG_MXC_IRQ_PRIOR -static int avic_irq_set_priority(unsigned char irq, unsigned char prio) -{ - struct irq_data *d = irq_get_irq_data(irq); - unsigned int temp; - unsigned int mask = 0x0F << irq % 8 * 4; - - irq = d->hwirq; - - if (irq >= AVIC_NUM_IRQS) - return -EINVAL; - - temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8)); - temp &= ~mask; - temp |= prio & mask; - - __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); - - return 0; -} -#endif - #ifdef CONFIG_FIQ static int avic_set_irq_fiq(unsigned int irq, unsigned int type) { @@ -102,9 +80,6 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type) static struct mxc_extra_irq avic_extra_irq = { -#ifdef CONFIG_MXC_IRQ_PRIOR - .set_priority = avic_irq_set_priority, -#endif #ifdef CONFIG_FIQ .set_irq_fiq = avic_set_irq_fiq, #endif diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c index a63e415..a2ecc00 100644 --- a/arch/arm/mach-imx/clk-gate2.c +++ b/arch/arm/mach-imx/clk-gate2.c @@ -72,7 +72,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw) reg = readl(gate->reg); - if (((reg >> gate->bit_idx) & 3) == 3) + if (((reg >> gate->bit_idx) & 1) == 1) return 1; return 0; diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c index 2193c83..a4d5e42 100644 --- a/arch/arm/mach-imx/clk-imx35.c +++ b/arch/arm/mach-imx/clk-imx35.c @@ -45,6 +45,8 @@ static struct arm_ahb_div clk_consumer[] = { static char hsp_div_532[] = { 4, 8, 3, 0 }; static char hsp_div_400[] = { 3, 6, 3, 0 }; +static struct clk_onecell_data clk_data; + static const char *std_sel[] = {"ppll", "arm"}; static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"}; @@ -286,3 +288,15 @@ int __init mx35_clocks_init(void) return 0; } + +static int __init mx35_clocks_init_dt(struct device_node *ccm_node) +{ + clk_data.clks = clk; + clk_data.clk_num = ARRAY_SIZE(clk); + of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data); + + mx35_clocks_init(); + + return 0; +} +CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt); diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index ce37af2..19fca1f 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -12,11 +12,11 @@ #include <linux/io.h> #include <linux/clkdev.h> #include <linux/clk-provider.h> -#include <linux/of.h> #include <linux/err.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <dt-bindings/clock/imx5-clock.h> #include "crm-regs-imx5.h" #include "clk.h" @@ -83,50 +83,7 @@ static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_ static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", }; static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; - -enum imx5_clks { - dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred, - uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s, - emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred, - usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di_unused, - tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate, - uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate, - gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate, - gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate, - esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate, - ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate, - ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s, - ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate, - vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate, - uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate, - esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate, - mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate, - ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div, - ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm, - periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2, - tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf, - esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate, - usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw, - pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw, - ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate, - usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root, - ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel, - ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred, - ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred, - ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate, - ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, - epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, - can_sel, can1_serial_gate, can1_ipg_gate, - owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate, - cko1_sel, cko1_podf, cko1, - cko2_sel, cko2_podf, cko2, - srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel, - spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf, - spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate, - ocram, clk_max -}; - -static struct clk *clk[clk_max]; +static struct clk *clk[IMX5_CLK_END]; static struct clk_onecell_data clk_data; static void __init mx5_clocks_common_init(unsigned long rate_ckil, @@ -135,236 +92,296 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, { int i; - clk[dummy] = imx_clk_fixed("dummy", 0); - clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil); - clk[osc] = imx_obtain_fixed_clock("osc", rate_osc); - clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1); - clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2); - - clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, - lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); - clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, - periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); - clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, - main_bus_sel, ARRAY_SIZE(main_bus_sel)); - clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, - per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); - clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); - clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); - clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); - clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1, - per_root_sel, ARRAY_SIZE(per_root_sel)); - clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); - clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); - clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24); - clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26); - clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0); - clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2); - clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4); - clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0); - clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2); - clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3); - clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3); - clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2, - standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); - clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3); - clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3); - - clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2, - standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); - clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2, - standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); - clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3); - clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3); - clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3); - clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3); - clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel)); - clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel)); - - clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1, - emi_slow_sel, ARRAY_SIZE(emi_slow_sel)); - clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3); - clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3); - clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2, - standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); - clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3); - clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6); - clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2, - standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); - clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3); - clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2); - clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3); - clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3); - clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1, - usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str)); - clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3); - clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3); - clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); - clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); - clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8); - clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10); - clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12); - clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14); - clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); - clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); - clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); - clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); - clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12); - clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); - clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16); - clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); - clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20); - clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); - clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); - clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); - clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0); - clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4); - clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8); - clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12); - clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16); - clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20); - clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24); - clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18); - clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20); - clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22); - clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24); - clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26); - clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30); - clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14); - clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16); - clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel)); - clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10); - clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); - clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); - clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); - clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel)); - clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel)); - clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2); - clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4); - clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14); - clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel)); - clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6); - clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8); - clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8); - clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10); - clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12); - clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14); - clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24); - - clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels)); - clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); - clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); - clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels)); - clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); - clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); - clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels)); - clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels)); - clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3); - clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6); - clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3); - clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6); - clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3); - clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6); - clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3); - clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6); - clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18); - clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22); - clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); - clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); - clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); - clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); - clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4); - clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); - clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); - clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); - clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28); - clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); - clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel)); - clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3); - clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6); - clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1, - spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT); - clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); - clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); + clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); + clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", rate_ckil); + clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", rate_osc); + clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", rate_ckih1); + clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", rate_ckih2); + + clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, + periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); + clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, + main_bus_sel, ARRAY_SIZE(main_bus_sel)); + clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, + per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); + clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); + clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); + clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); + clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1, + per_root_sel, ARRAY_SIZE(per_root_sel)); + clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); + clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); + clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24); + clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26); + clk[IMX5_CLK_TMAX1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0); + clk[IMX5_CLK_TMAX2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2); + clk[IMX5_CLK_TMAX3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4); + clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0); + clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2); + clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3); + clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3); + clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2, + standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); + clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3); + clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3); + + clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2, + standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); + clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2, + standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); + clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3); + clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3); + clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3); + clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3); + clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel)); + clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel)); + + clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1, + emi_slow_sel, ARRAY_SIZE(emi_slow_sel)); + clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3); + clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3); + clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2, + standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); + clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3); + clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6); + clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2, + standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); + clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3); + clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2); + clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3); + clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3); + clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1, + usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str)); + clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3); + clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3); + clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); + clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); + clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8); + clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10); + clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12); + clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14); + clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); + clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); + clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); + clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); + clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12); + clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); + clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16); + clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); + clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20); + clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); + clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); + clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); + clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0); + clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4); + clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8); + clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12); + clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16); + clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20); + clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24); + clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18); + clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20); + clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22); + clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24); + clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26); + clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30); + clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14); + clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16); + clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel)); + clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10); + clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); + clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); + clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); + clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel)); + clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel)); + clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2); + clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4); + clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14); + clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel)); + clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6); + clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8); + clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8); + clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10); + clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12); + clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14); + clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24); + + clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels)); + clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); + clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); + clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels)); + clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); + clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); + clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels)); + clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels)); + clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3); + clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6); + clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3); + clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6); + clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3); + clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6); + clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3); + clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6); + clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18); + clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22); + clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); + clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); + clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); + clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); + clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4); + clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); + clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); + clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); + clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28); + clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); + clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel)); + clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3); + clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6); + clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1, + spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT); + clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); + clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); + clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14); + clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1); for (i = 0; i < ARRAY_SIZE(clk); i++) if (IS_ERR(clk[i])) pr_err("i.MX5 clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); - clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0"); - clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0"); - clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); - clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1"); - clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1"); - clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2"); - clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2"); - clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3"); - clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3"); - clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4"); - clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4"); - clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0"); - clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0"); - clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1"); - clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1"); - clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2"); - clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0"); - clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1"); - clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); - clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); - clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0"); - clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0"); - clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0"); - clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1"); - clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1"); - clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1"); - clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2"); - clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2"); - clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2"); - clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51"); - clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51"); - clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51"); - clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand"); - clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); - clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); - clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2"); - clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); - clk_register_clkdev(clk[cpu_podf], NULL, "cpu0"); - clk_register_clkdev(clk[iim_gate], "iim", NULL); - clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1"); - clk_register_clkdev(clk[dummy], NULL, "imx-keypad"); - clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0"); - clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL); - clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0"); - clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0"); - clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1"); - clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1"); + clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0"); + clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0"); + clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0"); + clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); + clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1"); + clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); + clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2"); + clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); + clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3"); + clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); + clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4"); + clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4"); + clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0"); + clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0"); + clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1"); + clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1"); + clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2"); + clk_register_clkdev(clk[IMX5_CLK_PWM1_IPG_GATE], "pwm", "mxc_pwm.0"); + clk_register_clkdev(clk[IMX5_CLK_PWM2_IPG_GATE], "pwm", "mxc_pwm.1"); + clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0"); + clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1"); + clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0"); + clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0"); + clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0"); + clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1"); + clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1"); + clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1"); + clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2"); + clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2"); + clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2"); + clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51"); + clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51"); + clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51"); + clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand"); + clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0"); + clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1"); + clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2"); + clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma"); + clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0"); + clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL); + clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0"); + clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1"); + clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad"); + clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0"); + clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL); + clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0"); + clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0"); + clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1"); + clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1"); /* Set SDHC parents to be PLL2 */ - clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]); - clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]); + clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); + clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); /* move usb phy clk to 24MHz */ - clk_set_parent(clk[usb_phy_sel], clk[osc]); - - clk_prepare_enable(clk[gpc_dvfs]); - clk_prepare_enable(clk[ahb_max]); /* esdhc3 */ - clk_prepare_enable(clk[aips_tz1]); - clk_prepare_enable(clk[aips_tz2]); /* fec */ - clk_prepare_enable(clk[spba]); - clk_prepare_enable(clk[emi_fast_gate]); /* fec */ - clk_prepare_enable(clk[emi_slow_gate]); /* eim */ - clk_prepare_enable(clk[mipi_hsc1_gate]); - clk_prepare_enable(clk[mipi_hsc2_gate]); - clk_prepare_enable(clk[mipi_esc_gate]); - clk_prepare_enable(clk[mipi_hsp_gate]); - clk_prepare_enable(clk[tmax1]); - clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */ - clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */ + clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); + + clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); + clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ + clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); + clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ + clk_prepare_enable(clk[IMX5_CLK_SPBA]); + clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ + clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ + clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); + clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); + clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); + clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); + clk_prepare_enable(clk[IMX5_CLK_TMAX1]); + clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ + clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ } +static void __init mx50_clocks_init(struct device_node *np) +{ + void __iomem *base; + unsigned long r; + int i, irq; + + clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); + clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); + clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); + + clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, + lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); + clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); + clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); + clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); + clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); + clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); + clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); + clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); + + clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, + mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); + clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); + clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); + + clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, + mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); + clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); + clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); + + for (i = 0; i < ARRAY_SIZE(clk); i++) + if (IS_ERR(clk[i])) + pr_err("i.MX50 clk %d: register failed with %ld\n", + i, PTR_ERR(clk[i])); + + clk_data.clks = clk; + clk_data.clk_num = ARRAY_SIZE(clk); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + + mx5_clocks_common_init(0, 0, 0, 0); + + /* set SDHC root clock to 200MHZ*/ + clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); + clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); + + clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); + imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1); + clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); + + r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); + clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"); + base = of_iomap(np, 0); + WARN_ON(!base); + irq = irq_of_parse_and_map(np, 0); + mxc_timer_init(base, irq); +} +CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); + int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, unsigned long rate_ckih1, unsigned long rate_ckih2) { @@ -372,38 +389,40 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, u32 val; struct device_node *np; - clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); - clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE); - clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE); - clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, - mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel)); - clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, - mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel)); - clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, - mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT); - clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, - mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel)); - clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30); - clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3); - clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); - clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6); - clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10); - clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); - clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0); - clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22); - clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6); - clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); - clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); - clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); - clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, - mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel)); - clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2, - spdif_sel, ARRAY_SIZE(spdif_sel)); - clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); - clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6); - clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1, - mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); - clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); + clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); + clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE); + clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE); + clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, + lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); + clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, + mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel)); + clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, + mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel)); + clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, + mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT); + clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, + mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel)); + clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30); + clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3); + clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); + clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6); + clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10); + clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); + clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0); + clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22); + clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6); + clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); + clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); + clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); + clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, + mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel)); + clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2, + spdif_sel, ARRAY_SIZE(spdif_sel)); + clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); + clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6); + clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1, + mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); + clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); for (i = 0; i < ARRAY_SIZE(clk); i++) if (IS_ERR(clk[i])) @@ -417,37 +436,37 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); - clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2"); - clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL); - clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0"); - clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); - clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0"); - clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0"); - clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0"); - clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1"); - clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1"); - clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2"); - clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2"); - clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3"); - clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3"); + clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2"); + clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL); + clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx51-vpu.0"); + clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0"); + clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0"); + clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1"); + clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2"); + clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3"); + clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3"); /* set the usboh3 parent to pll2_sw */ - clk_set_parent(clk[usboh3_sel], clk[pll2_sw]); + clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); /* set SDHC root clock to 166.25MHZ*/ - clk_set_rate(clk[esdhc_a_podf], 166250000); - clk_set_rate(clk[esdhc_b_podf], 166250000); + clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); + clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); /* System timer */ mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT); - clk_prepare_enable(clk[iim_gate]); + clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX51", mx51_revision()); - clk_disable_unprepare(clk[iim_gate]); + clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); /* * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no @@ -479,57 +498,59 @@ static void __init mx53_clocks_init(struct device_node *np) unsigned long r; void __iomem *base; - clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); - clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); - clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); - clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE); - - clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); - clk[ldb_di1_div] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0); - clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1, - mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT); - clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3); - clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); - clk[ldb_di0_div] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0); - clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1, - mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT); - clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); - clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); - clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, - mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel)); - clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, - mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel)); - clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, - mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT); - clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); - clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3); - clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); - clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); - clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); - clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); - clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); - clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); - clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2, - mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); - clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); - clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); - clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2); - clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); - clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); - clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); - clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2); - - clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, - mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); - clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); - clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); - - clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, - mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); - clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); - clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); - clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, - mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); + clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); + clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); + clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); + clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE); + + clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, + lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); + clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); + clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0); + clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1, + mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT); + clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3); + clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); + clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0); + clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1, + mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT); + clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); + clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); + clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, + mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel)); + clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, + mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel)); + clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, + mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT); + clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); + clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3); + clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); + clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); + clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); + clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); + clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); + clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); + clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2, + mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); + clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); + clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); + clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2); + clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); + clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); + clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); + clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2); + + clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, + mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); + clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); + clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); + + clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, + mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); + clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); + clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); + clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, + mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); for (i = 0; i < ARRAY_SIZE(clk); i++) if (IS_ERR(clk[i])) @@ -542,33 +563,36 @@ static void __init mx53_clocks_init(struct device_node *np) mx5_clocks_common_init(0, 0, 0, 0); - clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0"); - clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); - clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0"); - clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0"); - clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0"); - clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0"); - clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1"); - clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1"); - clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2"); - clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2"); - clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3"); - clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3"); + clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx53-vpu.0"); + clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2"); + clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0"); + clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0"); + clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1"); + clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2"); + clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3"); + clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3"); + clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3"); /* set SDHC root clock to 200MHZ*/ - clk_set_rate(clk[esdhc_a_podf], 200000000); - clk_set_rate(clk[esdhc_b_podf], 200000000); + clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); + clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); + + /* move can bus clk to 24MHz */ + clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); - clk_prepare_enable(clk[iim_gate]); + clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX53", mx53_revision()); - clk_disable_unprepare(clk[iim_gate]); + clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); - r = clk_round_rate(clk[usboh3_per_gate], 54000000); - clk_set_rate(clk[usboh3_per_gate], r); + r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); + clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"); base = of_iomap(np, 0); diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 04cfd0f..af2e582 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -114,7 +114,7 @@ static struct clk *clk[clk_max]; static struct clk_onecell_data clk_data; static enum mx6q_clks const clks_init_on[] __initconst = { - mmdc_ch0_axi, rom, pll1_sys, + mmdc_ch0_axi, rom, arm, }; static struct clk_div_table clk_enet_ref_table[] = { @@ -475,6 +475,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) if (ret) pr_warn("failed to set up CLKO: %d\n", ret); + /* Audio-related clocks configuration */ + clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]); + /* All existing boards with PCIe use LVDS1 */ if (IS_ENABLED(CONFIG_PCI_IMX6)) clk_set_parent(clk[lvds1_sel], clk[sata_ref]); diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index c0c4ef5..3781a18 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -29,14 +29,14 @@ static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf" static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; -static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", }; +static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", }; static const char const *perclk_sels[] = { "ipg", "osc", }; static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", }; static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; -static const char const *audio_sels[] = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; +static const char const *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; static const char const *ecspi_sels[] = { "pll3_60m", "osc", }; static const char const *uart_sels[] = { "pll3_80m", "osc", }; @@ -63,7 +63,7 @@ static struct clk_div_table video_div_table[] = { { } }; -static struct clk *clks[IMX6SL_CLK_CLK_END]; +static struct clk *clks[IMX6SL_CLK_END]; static struct clk_onecell_data clk_data; static void __init imx6sl_clocks_init(struct device_node *ccm_node) @@ -104,6 +104,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) /* dev name parent_name flags reg shift width div: flags, div_table lock */ clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); + clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); @@ -232,6 +233,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); + clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18); clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20); @@ -261,6 +263,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); } + /* Audio-related clocks configuration */ + clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); + np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt"); base = of_iomap(np, 0); WARN_ON(!base); diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c index e2ed416..0b0f6f6 100644 --- a/arch/arm/mach-imx/clk-pfd.c +++ b/arch/arm/mach-imx/clk-pfd.c @@ -109,12 +109,23 @@ static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static int clk_pfd_is_enabled(struct clk_hw *hw) +{ + struct clk_pfd *pfd = to_clk_pfd(hw); + + if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1))) + return 0; + + return 1; +} + static const struct clk_ops clk_pfd_ops = { .enable = clk_pfd_enable, .disable = clk_pfd_disable, .recalc_rate = clk_pfd_recalc_rate, .round_rate = clk_pfd_round_rate, .set_rate = clk_pfd_set_rate, + .is_enabled = clk_pfd_is_enabled, }; struct clk *imx_clk_pfd(const char *name, const char *parent_name, diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c index c1eaee3..d21d14c 100644 --- a/arch/arm/mach-imx/clk-pllv1.c +++ b/arch/arm/mach-imx/clk-pllv1.c @@ -18,6 +18,11 @@ * * PLL clock version 1, found on i.MX1/21/25/27/31/35 */ + +#define MFN_BITS (10) +#define MFN_SIGN (BIT(MFN_BITS - 1)) +#define MFN_MASK (MFN_SIGN - 1) + struct clk_pllv1 { struct clk_hw hw; void __iomem *base; @@ -25,6 +30,11 @@ struct clk_pllv1 { #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk)) +static inline bool mfn_is_negative(unsigned int mfn) +{ + return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN); +} + static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -58,10 +68,15 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, /* * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit - * 2's complements number + * 2's complements number. + * On i.MX27 the bit 9 is the sign bit. */ - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) - mfn_abs = 0x400 - mfn; + if (mfn_is_negative(mfn)) { + if (cpu_is_mx27()) + mfn_abs = mfn & MFN_MASK; + else + mfn_abs = BIT(MFN_BITS) - mfn; + } rate = parent_rate * 2; rate /= pd + 1; @@ -70,7 +85,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, do_div(ll, mfd + 1); - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) + if (mfn_is_negative(mfn)) ll = -ll; ll = (rate * mfi) + ll; diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index b169a39..ecd66d8 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c @@ -298,6 +298,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0)); clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4)); + clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4)); + clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5)); + clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1)); + clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2)); + clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 24a7899..59c3b9b 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -108,6 +108,7 @@ void tzic_handle_irq(struct pt_regs *); #define imx27_handle_irq avic_handle_irq #define imx31_handle_irq avic_handle_irq #define imx35_handle_irq avic_handle_irq +#define imx50_handle_irq tzic_handle_irq #define imx51_handle_irq tzic_handle_irq #define imx53_handle_irq tzic_handle_irq diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c index 818a1cc..e1e70ef 100644 --- a/arch/arm/mach-imx/imx31-dt.c +++ b/arch/arm/mach-imx/imx31-dt.c @@ -25,7 +25,7 @@ static void __init imx31_dt_init(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -static const char *imx31_dt_board_compat[] __initdata = { +static const char *imx31_dt_board_compat[] __initconst = { "fsl,imx31", NULL }; diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c new file mode 100644 index 0000000..9d48e00 --- /dev/null +++ b/arch/arm/mach-imx/imx35-dt.c @@ -0,0 +1,50 @@ +/* + * Copyright 2012 Steffen Trumtrar, Pengutronix + * + * based on imx27-dt.c + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include <linux/irq.h> +#include <linux/irqdomain.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <linux/clk-provider.h> +#include <linux/clocksource.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/hardware/cache-l2x0.h> +#include "common.h" +#include "mx35.h" + +static void __init imx35_dt_init(void) +{ + mxc_arch_reset_init_dt(); + + of_platform_populate(NULL, of_default_bus_match_table, + NULL, NULL); +} + +static void __init imx35_irq_init(void) +{ + imx_init_l2cache(); + mx35_init_irq(); +} + +static const char *imx35_dt_board_compat[] __initconst = { + "fsl,imx35", + NULL +}; + +DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)") + .map_io = mx35_map_io, + .init_early = imx35_init_early, + .init_irq = imx35_irq_init, + .handle_irq = imx35_handle_irq, + .init_machine = imx35_dt_init, + .dt_compat = imx35_dt_board_compat, + .restart = mxc_restart, +MACHINE_END diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c index bece8a6..0230d78 100644 --- a/arch/arm/mach-imx/imx51-dt.c +++ b/arch/arm/mach-imx/imx51-dt.c @@ -29,7 +29,7 @@ static void __init imx51_dt_init(void) platform_device_register_full(&devinfo); } -static const char *imx51_dt_board_compat[] __initdata = { +static const char *imx51_dt_board_compat[] __initconst = { "fsl,imx51", NULL }; diff --git a/arch/arm/mach-imx/irq-common.h b/arch/arm/mach-imx/irq-common.h index 5b2dabb..6e3175d 100644 --- a/arch/arm/mach-imx/irq-common.h +++ b/arch/arm/mach-imx/irq-common.h @@ -24,7 +24,6 @@ struct mxc_extra_irq { - int (*set_priority)(unsigned char irq, unsigned char prio); int (*set_irq_fiq)(unsigned int irq, unsigned int type); }; diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c new file mode 100644 index 0000000..77b77a9 --- /dev/null +++ b/arch/arm/mach-imx/mach-imx50.c @@ -0,0 +1,38 @@ +/* + * Copyright 2013 Greg Ungerer <gerg@uclinux.org> + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/of_platform.h> +#include <asm/mach/arch.h> + +#include "common.h" + +static void __init imx50_dt_init(void) +{ + mxc_arch_reset_init_dt(); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char *imx50_dt_board_compat[] __initconst = { + "fsl,imx50", + NULL +}; + +DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)") + .map_io = mx53_map_io, + .init_irq = mx53_init_irq, + .handle_irq = imx50_handle_irq, + .init_machine = imx50_dt_init, + .dt_compat = imx50_dt_board_compat, + .restart = mxc_restart, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index c9c4d8d..6585090 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -31,7 +31,7 @@ static void __init imx53_dt_init(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -static const char *imx53_dt_board_compat[] __initdata = { +static const char *imx53_dt_board_compat[] __initconst = { "fsl,imx53", NULL }; diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index d0cfb22..d2ea6e6 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -13,6 +13,7 @@ #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/cpu.h> +#include <linux/delay.h> #include <linux/export.h> #include <linux/init.h> #include <linux/io.h> @@ -23,6 +24,7 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/pm_opp.h> +#include <linux/pci.h> #include <linux/phy.h> #include <linux/reboot.h> #include <linux/regmap.h> @@ -78,6 +80,34 @@ static int ksz9031rn_phy_fixup(struct phy_device *dev) return 0; } +/* + * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High + * as they are used for slots1-7 PERST# + */ +static void ventana_pciesw_early_fixup(struct pci_dev *dev) +{ + u32 dw; + + if (!of_machine_is_compatible("gw,ventana")) + return; + + if (dev->devfn != 0) + return; + + pci_read_config_dword(dev, 0x62c, &dw); + dw |= 0xaaa8; // GPIO1-7 outputs + pci_write_config_dword(dev, 0x62c, dw); + + pci_read_config_dword(dev, 0x644, &dw); + dw |= 0xfe; // GPIO1-7 output high + pci_write_config_dword(dev, 0x644, dw); + + msleep(100); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup); + static int ar8031_phy_fixup(struct phy_device *dev) { u16 val; @@ -243,7 +273,7 @@ static void __init imx6q_init_irq(void) irqchip_init(); } -static const char *imx6q_dt_compat[] __initdata = { +static const char *imx6q_dt_compat[] __initconst = { "fsl,imx6dl", "fsl,imx6q", NULL, diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 2f952e3..0f4fd4c 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -34,6 +34,13 @@ static void __init imx6sl_fec_init(void) } } +static void __init imx6sl_init_late(void) +{ + /* imx6sl reuses imx6q cpufreq driver */ + if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) + platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); +} + static void __init imx6sl_init_machine(void) { struct device *parent; @@ -61,7 +68,7 @@ static void __init imx6sl_init_irq(void) irqchip_init(); } -static const char *imx6sl_dt_compat[] __initdata = { +static const char *imx6sl_dt_compat[] __initconst = { "fsl,imx6sl", NULL, }; @@ -70,6 +77,7 @@ DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)") .map_io = debug_ll_io_init, .init_irq = imx6sl_init_irq, .init_machine = imx6sl_init_machine, + .init_late = imx6sl_init_late, .dt_compat = imx6sl_dt_compat, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c index af0cb8a..2d8aef5 100644 --- a/arch/arm/mach-imx/mach-vf610.c +++ b/arch/arm/mach-imx/mach-vf610.c @@ -26,7 +26,7 @@ static void __init vf610_init_irq(void) irqchip_init(); } -static const char *vf610_dt_compat[] __initdata = { +static const char *vf610_dt_compat[] __initconst = { "fsl,vf610", NULL, }; diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index d1d5260..4c11202 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -89,15 +89,7 @@ void __init imx51_init_early(void) void __init imx53_init_early(void) { - struct device_node *np; - void __iomem *base; - mxc_set_cpu_type(MXC_CPU_MX53); - - np = of_find_compatible_node(NULL, NULL, "fsl,imx53-iomuxc"); - base = of_iomap(np, 0); - WARN_ON(!base); - mxc_iomux_v3_init(base); imx_src_init(); } diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index 1f24c1f..5b57c17 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -92,8 +92,7 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus) * secondary cores when booting them. */ asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc"); - __cpuc_flush_dcache_area(&g_diag_reg, sizeof(g_diag_reg)); - outer_clean_range(__pa(&g_diag_reg), __pa(&g_diag_reg + 1)); + sync_cache_w(&g_diag_reg); } struct smp_operations imx_smp_ops __initdata = { diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index aecd9f8..9d47adc 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -156,10 +156,16 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) } /* - * Unmask the always pending IOMUXC interrupt #32 as wakeup source to - * deassert dsm_request signal, so that we can ensure dsm_request - * is not asserted when we're going to write CLPCR register to set LPM. - * After setting up LPM bits, we need to mask this wakeup source. + * ERR007265: CCM: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #32 (IOMUX) to be always pending + * by setting IOMUX_GPR1_GINT. + * 2) Software should then unmask IRQ #32 in GPC before setting CCM + * Low-Power mode. + * 3) Software should mask IRQ #32 right after CCM Low-Power mode + * is set (set bits 0-1 of CCM_CLPCR). */ iomuxc_irq_desc = irq_to_desc(32); imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data); @@ -219,6 +225,8 @@ void __init imx6q_pm_init(void) WARN_ON(!ccm_base); /* + * This is for SW workaround step #1 of ERR007265, see comments + * in imx6q_set_lpm for details of this errata. * Force IOMUXC irq pending, so that the interrupt to GPC can be * used to deassert dsm_request signal when the signal gets * asserted unexpectedly. diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index 9b6638a..1a3a5f6 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -111,7 +111,7 @@ static void gpt_irq_acknowledge(void) static void __iomem *sched_clock_reg; -static u32 notrace mxc_read_sched_clock(void) +static u64 notrace mxc_read_sched_clock(void) { return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; } @@ -123,7 +123,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk) sched_clock_reg = reg; - setup_sched_clock(mxc_read_sched_clock, 32, c); + sched_clock_register(mxc_read_sched_clock, 32, c); return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, clocksource_mmio_readl_up); } diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index d50dc2d..17c0fe6 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -63,6 +63,9 @@ /* Base address to the AP system controller */ void __iomem *ap_syscon_base; +/* Base address to the external bus interface */ +static void __iomem *ebi_base; + /* * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx @@ -72,15 +75,11 @@ void __iomem *ap_syscon_base; * just for now). */ #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) -#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE) -#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC) /* * Logical Physical * ef000000 Cache flush - * f1000000 10000000 Core module registers * f1100000 11000000 System controller registers - * f1200000 12000000 EBI registers * f1300000 13000000 Counter/Timer * f1400000 14000000 Interrupt controller * f1600000 16000000 UART 0 @@ -91,16 +90,6 @@ void __iomem *ap_syscon_base; static struct map_desc ap_io_desc[] __initdata __maybe_unused = { { - .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { - .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), .length = SZ_4K, @@ -174,9 +163,6 @@ device_initcall(irq_syscore_init); /* * Flash handling. */ -#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) -#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) - static int ap_flash_init(struct platform_device *dev) { u32 tmp; @@ -184,13 +170,15 @@ static int ap_flash_init(struct platform_device *dev) writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); - tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE; - writel(tmp, EBI_CSR1); + tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) | + INTEGRATOR_EBI_WRITE_ENABLE; + writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); - if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) { - writel(0xa05f, EBI_LOCK); - writel(tmp, EBI_CSR1); - writel(0, EBI_LOCK); + if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) + & INTEGRATOR_EBI_WRITE_ENABLE)) { + writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); + writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); + writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); } return 0; } @@ -202,13 +190,15 @@ static void ap_flash_exit(struct platform_device *dev) writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); - tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE; - writel(tmp, EBI_CSR1); + tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) & + ~INTEGRATOR_EBI_WRITE_ENABLE; + writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); - if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) { - writel(0xa05f, EBI_LOCK); - writel(tmp, EBI_CSR1); - writel(0, EBI_LOCK); + if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) & + INTEGRATOR_EBI_WRITE_ENABLE) { + writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); + writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); + writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); } } @@ -277,7 +267,7 @@ struct amba_pl010_data ap_uart_data = { static unsigned long timer_reload; -static u32 notrace integrator_read_sched_clock(void) +static u64 notrace integrator_read_sched_clock(void) { return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE); } @@ -298,7 +288,7 @@ static void integrator_clocksource_init(unsigned long inrate, clocksource_mmio_init(base + TIMER_VALUE, "timer2", rate, 200, 16, clocksource_mmio_readl_down); - setup_sched_clock(integrator_read_sched_clock, 16, rate); + sched_clock_register(integrator_read_sched_clock, 16, rate); } static void __iomem * clkevt_base; @@ -475,11 +465,17 @@ static const struct of_device_id ap_syscon_match[] = { { }, }; +static const struct of_device_id ebi_match[] = { + { .compatible = "arm,external-bus-interface"}, + { }, +}; + static void __init ap_init_of(void) { unsigned long sc_dec; struct device_node *root; struct device_node *syscon; + struct device_node *ebi; struct device *parent; struct soc_device *soc_dev; struct soc_device_attribute *soc_dev_attr; @@ -495,10 +491,16 @@ static void __init ap_init_of(void) syscon = of_find_matching_node(root, ap_syscon_match); if (!syscon) return; + ebi = of_find_matching_node(root, ebi_match); + if (!ebi) + return; ap_syscon_base = of_iomap(syscon, 0); if (!ap_syscon_base) return; + ebi_base = of_iomap(ebi, 0); + if (!ebi_base) + return; ap_sc_id = readl(ap_syscon_base); diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 4fc0a19..5e84149 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -64,9 +64,6 @@ static void __iomem *intcp_con_base; /* * Logical Physical - * f1000000 10000000 Core module registers - * f1100000 11000000 System controller registers - * f1200000 12000000 EBI registers * f1300000 13000000 Counter/Timer * f1400000 14000000 Interrupt controller * f1600000 16000000 UART 0 @@ -74,21 +71,10 @@ static void __iomem *intcp_con_base; * f1a00000 1a000000 Debug LEDs * fc900000 c9000000 GPIO * fca00000 ca000000 SIC - * fcb00000 cb000000 CP system control */ static struct map_desc intcp_io_desc[] __initdata __maybe_unused = { { - .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { - .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), .length = SZ_4K, diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index a7906eb..6d68aed 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -475,7 +475,7 @@ void __init ixp4xx_sys_init(void) /* * sched_clock() */ -static u32 notrace ixp4xx_read_sched_clock(void) +static u64 notrace ixp4xx_read_sched_clock(void) { return *IXP4XX_OSTS; } @@ -493,7 +493,7 @@ unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ; EXPORT_SYMBOL(ixp4xx_timer_freq); static void __init ixp4xx_clocksource_init(void) { - setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq); + sched_clock_register(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq); clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32, ixp4xx_clocksource_read); diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index f20c53e..dabc5ee 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -11,6 +11,8 @@ config ARCH_KEYSTONE select ARM_ERRATA_798181 if SMP select COMMON_CLK_KEYSTONE select TI_EDMA + select ARCH_SUPPORTS_BIG_ENDIAN + select ZONE_DMA if ARM_LPAE help Support for boards based on the Texas Instruments Keystone family of SoCs. diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c index b661c5c..6e6bb7d 100644 --- a/arch/arm/mach-keystone/keystone.c +++ b/arch/arm/mach-keystone/keystone.c @@ -41,6 +41,7 @@ static void __init keystone_init(void) if (WARN_ON(!keystone_rstctrl)) pr_warn("ti,keystone-reset iomap error\n"); + keystone_pm_runtime_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } @@ -68,6 +69,9 @@ void keystone_restart(enum reboot_mode mode, const char *cmd) } DT_MACHINE_START(KEYSTONE, "Keystone") +#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE) + .dma_zone_size = SZ_2G, +#endif .smp = smp_ops(keystone_smp_ops), .init_machine = keystone_init, .dt_compat = keystone_match, diff --git a/arch/arm/mach-keystone/keystone.h b/arch/arm/mach-keystone/keystone.h index 60bef9d..cd04a1c 100644 --- a/arch/arm/mach-keystone/keystone.h +++ b/arch/arm/mach-keystone/keystone.h @@ -18,6 +18,7 @@ extern struct smp_operations keystone_smp_ops; extern void secondary_startup(void); extern u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr); +extern int keystone_pm_runtime_init(void); #endif /* __ASSEMBLER__ */ #endif /* __KEYSTONE_H__ */ diff --git a/arch/arm/mach-keystone/pm_domain.c b/arch/arm/mach-keystone/pm_domain.c index 2962523..ca79dda 100644 --- a/arch/arm/mach-keystone/pm_domain.c +++ b/arch/arm/mach-keystone/pm_domain.c @@ -74,9 +74,7 @@ int __init keystone_pm_runtime_init(void) if (!np) return 0; - of_clk_init(NULL); pm_clk_add_notifier(&platform_bus_type, &platform_domain_notifier); return 0; } -subsys_initcall(keystone_pm_runtime_init); diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 9caa4fe..7818815 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -10,55 +10,21 @@ * warranty of any kind, whether express or implied. */ +#include <linux/clk.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_net.h> #include <linux/of_platform.h> -#include <linux/clk-provider.h> #include <linux/dma-mapping.h> #include <linux/irqchip.h> #include <linux/kexec.h> #include <asm/mach/arch.h> -#include <asm/mach/map.h> #include <mach/bridge-regs.h> -#include <linux/platform_data/usb-ehci-orion.h> -#include <plat/irq.h> #include <plat/common.h> #include "common.h" -/* - * There are still devices that doesn't know about DT yet. Get clock - * gates here and add a clock lookup alias, so that old platform - * devices still work. -*/ - -static void __init kirkwood_legacy_clk_init(void) -{ - - struct device_node *np = of_find_compatible_node( - NULL, NULL, "marvell,kirkwood-gating-clock"); - struct of_phandle_args clkspec; - struct clk *clk; - - clkspec.np = np; - clkspec.args_count = 1; - - /* - * The ethernet interfaces forget the MAC address assigned by - * u-boot if the clocks are turned off. Until proper DT support - * is available we always enable them for now. - */ - clkspec.args[0] = CGC_BIT_GE0; - clk = of_clk_get_from_provider(&clkspec); - clk_prepare_enable(clk); - - clkspec.args[0] = CGC_BIT_GE1; - clk = of_clk_get_from_provider(&clkspec); - clk_prepare_enable(clk); -} - #define MV643XX_ETH_MAC_ADDR_LOW 0x0414 #define MV643XX_ETH_MAC_ADDR_HIGH 0x0418 @@ -140,7 +106,7 @@ eth_fixup_skip: static void __init kirkwood_dt_init(void) { - pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk); + pr_info("Kirkwood: %s.\n", kirkwood_id()); /* * Disable propagation of mbus errors to the CPU local bus, @@ -156,8 +122,6 @@ static void __init kirkwood_dt_init(void) kirkwood_cpufreq_init(); kirkwood_cpuidle_init(); - /* Setup clocks for legacy devices */ - kirkwood_legacy_clk_init(); kirkwood_pm_init(); kirkwood_dt_eth_fixup(); diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index ebdda83..ebdba87 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -136,4 +136,7 @@ config USB_EHCI_MV_U2O help Enables support for OTG controller which can be switched to host mode. +config MMP_SRAM + bool + endif diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 9b702a1..98f0f63 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -7,7 +7,8 @@ obj-y += common.o devices.o time.o # SoC support obj-$(CONFIG_CPU_PXA168) += pxa168.o obj-$(CONFIG_CPU_PXA910) += pxa910.o -obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o +obj-$(CONFIG_CPU_MMP2) += mmp2.o +obj-$(CONFIG_MMP_SRAM) += sram.o ifeq ($(CONFIG_COMMON_CLK), ) obj-y += clock.o diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 7ac41e8..024022d 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -61,7 +61,7 @@ static inline uint32_t timer_read(void) return __raw_readl(mmp_timer_base + TMR_CVWR(1)); } -static u32 notrace mmp_read_sched_clock(void) +static u64 notrace mmp_read_sched_clock(void) { return timer_read(); } @@ -195,7 +195,7 @@ void __init timer_init(int irq) { timer_config(); - setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE); + sched_clock_register(mmp_read_sched_clock, 32, CLOCK_TICK_RATE); ckevt.cpumask = cpumask_of(0); diff --git a/arch/arm/mach-moxart/Kconfig b/arch/arm/mach-moxart/Kconfig new file mode 100644 index 0000000..ba470d6 --- /dev/null +++ b/arch/arm/mach-moxart/Kconfig @@ -0,0 +1,31 @@ +config ARCH_MOXART + bool "MOXA ART SoC" if ARCH_MULTI_V4T + select CPU_FA526 + select ARM_DMA_MEM_BUFFERABLE + select DMA_OF + select USE_OF + select CLKSRC_OF + select CLKSRC_MMIO + select HAVE_CLK + select COMMON_CLK + select GENERIC_IRQ_CHIP + select ARCH_REQUIRE_GPIOLIB + select GENERIC_CLOCKEVENTS + select PHYLIB if NETDEVICES + help + Say Y here if you want to run your kernel on hardware with a + MOXA ART SoC. + The MOXA ART SoC is based on a Faraday FA526 ARMv4 32-bit + 192 MHz CPU with MMU and 16KB/8KB D/I-cache (UC-7112-LX). + Used on models UC-7101, UC-7112/UC-7110, IA240/IA241, IA3341. + +if ARCH_MOXART + +config MACH_UC7112LX + bool "MOXA UC-7112-LX" + depends on ARCH_MOXART + help + Say Y here if you intend to run this kernel on a MOXA + UC-7112-LX embedded computer. + +endif diff --git a/arch/arm/mach-moxart/Makefile b/arch/arm/mach-moxart/Makefile new file mode 100644 index 0000000..fa022eb --- /dev/null +++ b/arch/arm/mach-moxart/Makefile @@ -0,0 +1,3 @@ +# Object file lists. + +obj-$(CONFIG_MACH_UC7112LX) += moxart.o diff --git a/arch/arm/mach-moxart/moxart.c b/arch/arm/mach-moxart/moxart.c new file mode 100644 index 0000000..86b6d9b --- /dev/null +++ b/arch/arm/mach-moxart/moxart.c @@ -0,0 +1,15 @@ +/* + * arch/arm/mach-moxart/moxart.c + * + * (C) Copyright 2013, Jonas Jensen <jonas.jensen@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 2586c28..9625cf3 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -1,12 +1,50 @@ +config ARCH_MSM + bool + +config ARCH_MSM_DT + bool "Qualcomm MSM DT Support" if ARCH_MULTI_V7 + select ARCH_MSM + select ARCH_REQUIRE_GPIOLIB + select CLKSRC_OF + select GENERIC_CLOCKEVENTS + help + Support for Qualcomm's devicetree based MSM systems. + if ARCH_MSM -comment "Qualcomm MSM SoC Type" +menu "Qualcomm MSM SoC Selection" depends on ARCH_MSM_DT +config ARCH_MSM8X60 + bool "Enable support for MSM8X60" + select ARM_GIC + select CPU_V7 + select HAVE_SMP + select MSM_SCM if SMP + select MSM_TIMER + +config ARCH_MSM8960 + bool "Enable support for MSM8960" + select ARM_GIC + select CPU_V7 + select HAVE_SMP + select MSM_SCM if SMP + select MSM_TIMER + +config ARCH_MSM8974 + bool "Enable support for MSM8974" + select ARM_GIC + select CPU_V7 + select HAVE_ARM_ARCH_TIMER + select HAVE_SMP + select MSM_SCM if SMP + +endmenu + choice prompt "Qualcomm MSM SoC Type" default ARCH_MSM7X00A - depends on !ARCH_MSM_DT + depends on ARCH_MSM_NODT config ARCH_MSM7X00A bool "MSM7x00A / MSM7x01A" @@ -16,6 +54,7 @@ config ARCH_MSM7X00A select MACH_TROUT if !MACH_HALIBUT select MSM_PROC_COMM select MSM_SMD + select MSM_TIMER select MSM_SMD_PKG3 config ARCH_MSM7X30 @@ -27,6 +66,7 @@ config ARCH_MSM7X30 select MSM_GPIOMUX select MSM_PROC_COMM select MSM_SMD + select MSM_TIMER select MSM_VIC config ARCH_QSD8X50 @@ -38,32 +78,11 @@ config ARCH_QSD8X50 select MSM_GPIOMUX select MSM_PROC_COMM select MSM_SMD + select MSM_TIMER select MSM_VIC endchoice -config ARCH_MSM8X60 - bool "MSM8X60" - select ARM_GIC - select CPU_V7 - select GPIO_MSM_V2 - select HAVE_SMP - select MSM_SCM if SMP - -config ARCH_MSM8960 - bool "MSM8960" - select ARM_GIC - select CPU_V7 - select HAVE_SMP - select GPIO_MSM_V2 - select MSM_SCM if SMP - -config ARCH_MSM_DT - def_bool y - depends on (ARCH_MSM8X60 || ARCH_MSM8960) - select SPARSE_IRQ - select USE_OF - config MSM_HAS_DEBUG_UART_HS bool @@ -80,7 +99,7 @@ config MSM_VIC bool menu "Qualcomm MSM Board Type" - depends on !ARCH_MSM_DT + depends on ARCH_MSM_NODT config MACH_HALIBUT depends on ARCH_MSM @@ -128,10 +147,13 @@ config MSM_SMD config MSM_GPIOMUX bool - depends on !ARCH_MSM_DT help Support for MSM V1 TLMM GPIOMUX architecture. config MSM_SCM bool + +config MSM_TIMER + bool + endif diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 7ed4c1b..8e307a1 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -1,5 +1,5 @@ -obj-y += timer.o -obj-y += clock.o +obj-$(CONFIG_MSM_TIMER) += timer.o +obj-$(CONFIG_MSM_PROC_COMM) += clock.o obj-$(CONFIG_MSM_VIC) += irq-vic.o diff --git a/arch/arm/mach-msm/board-dt.c b/arch/arm/mach-msm/board-dt.c index 16e6183..1f11d93 100644 --- a/arch/arm/mach-msm/board-dt.c +++ b/arch/arm/mach-msm/board-dt.c @@ -26,7 +26,16 @@ static const char * const msm_dt_match[] __initconst = { NULL }; +static const char * const apq8074_dt_match[] __initconst = { + "qcom,apq8074-dragonboard", + NULL +}; + DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") .smp = smp_ops(msm_smp_ops), .dt_compat = msm_dt_match, MACHINE_END + +DT_MACHINE_START(APQ_DT, "Qualcomm MSM (Flattened Device Tree)") + .dt_compat = apq8074_dt_match, +MACHINE_END diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index f9af5a4..46de789 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -30,6 +30,7 @@ #include <asm/memory.h> #include <asm/setup.h> +#include <mach/clk.h> #include <mach/msm_iomap.h> #include <mach/dma.h> @@ -60,10 +61,44 @@ static int hsusb_phy_init_seq[] = { -1 }; +static int hsusb_link_clk_reset(struct clk *link_clk, bool assert) +{ + int ret; + + if (assert) { + ret = clk_reset(link_clk, CLK_RESET_ASSERT); + if (ret) + pr_err("usb hs_clk assert failed\n"); + } else { + ret = clk_reset(link_clk, CLK_RESET_DEASSERT); + if (ret) + pr_err("usb hs_clk deassert failed\n"); + } + return ret; +} + +static int hsusb_phy_clk_reset(struct clk *phy_clk) +{ + int ret; + + ret = clk_reset(phy_clk, CLK_RESET_ASSERT); + if (ret) { + pr_err("usb phy clk assert failed\n"); + return ret; + } + usleep_range(10000, 12000); + ret = clk_reset(phy_clk, CLK_RESET_DEASSERT); + if (ret) + pr_err("usb phy clk deassert failed\n"); + return ret; +} + static struct msm_otg_platform_data msm_otg_pdata = { .phy_init_seq = hsusb_phy_init_seq, .mode = USB_PERIPHERAL, .otg_control = OTG_PHY_CONTROL, + .link_clk_reset = hsusb_link_clk_reset, + .phy_clk_reset = hsusb_phy_clk_reset, }; struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 5f933bc..9169ec3 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -31,6 +31,7 @@ #include <mach/irqs.h> #include <mach/sirc.h> #include <mach/vreg.h> +#include <mach/clk.h> #include <linux/platform_data/mmc-msm_sdcc.h> #include "devices.h" @@ -81,10 +82,44 @@ static int hsusb_phy_init_seq[] = { -1 }; +static int hsusb_link_clk_reset(struct clk *link_clk, bool assert) +{ + int ret; + + if (assert) { + ret = clk_reset(link_clk, CLK_RESET_ASSERT); + if (ret) + pr_err("usb hs_clk assert failed\n"); + } else { + ret = clk_reset(link_clk, CLK_RESET_DEASSERT); + if (ret) + pr_err("usb hs_clk deassert failed\n"); + } + return ret; +} + +static int hsusb_phy_clk_reset(struct clk *phy_clk) +{ + int ret; + + ret = clk_reset(phy_clk, CLK_RESET_ASSERT); + if (ret) { + pr_err("usb phy clk assert failed\n"); + return ret; + } + usleep_range(10000, 12000); + ret = clk_reset(phy_clk, CLK_RESET_DEASSERT); + if (ret) + pr_err("usb phy clk deassert failed\n"); + return ret; +} + static struct msm_otg_platform_data msm_otg_pdata = { .phy_init_seq = hsusb_phy_init_seq, .mode = USB_PERIPHERAL, .otg_control = OTG_PHY_CONTROL, + .link_clk_reset = hsusb_link_clk_reset, + .phy_clk_reset = hsusb_phy_clk_reset, }; static struct platform_device *devices[] __initdata = { diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index ccf6621..015d544 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. * */ +#define pr_fmt(fmt) "%s: " fmt, __func__ #include <linux/kernel.h> #include <linux/init.h> @@ -68,12 +69,11 @@ static void __init trout_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); -#ifdef CONFIG_MMC - rc = trout_init_mmc(system_rev); - if (rc) - printk(KERN_CRIT "%s: MMC init failure (%d)\n", __func__, rc); -#endif - + if (IS_ENABLED(CONFIG_MMC)) { + rc = trout_init_mmc(system_rev); + if (rc) + pr_crit("MMC init failure (%d)\n", rc); + } } static struct map_desc trout_io_desc[] __initdata = { diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index 3f06edc..f10a1f5 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -99,8 +99,7 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle) * "cpu" is Linux's internal ID. */ pen_release = cpu_logical_map(cpu); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + sync_cache_w(&pen_release); /* * Send the secondary CPU a soft interrupt, thereby causing diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 1e9c338..fd16449 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -187,7 +187,7 @@ static struct notifier_block msm_timer_cpu_nb = { .notifier_call = msm_timer_cpu_notify, }; -static notrace u32 msm_sched_clock_read(void) +static u64 notrace msm_sched_clock_read(void) { return msm_clocksource.read(&msm_clocksource); } @@ -229,7 +229,7 @@ err: res = clocksource_register_hz(cs, dgt_hz); if (res) pr_err("clocksource_register failed\n"); - setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz); + sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz); } #ifdef CONFIG_OF diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 2d04f0e..878aebe 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -3,7 +3,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a -obj-y += system-controller.o +obj-y += system-controller.o mvebu-soc-id.o obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index e2acff9..f6c9d1d 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -21,6 +21,7 @@ #include <linux/clocksource.h> #include <linux/dma-mapping.h> #include <linux/mbus.h> +#include <linux/slab.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -28,6 +29,7 @@ #include "armada-370-xp.h" #include "common.h" #include "coherency.h" +#include "mvebu-soc-id.h" static void __init armada_370_xp_map_io(void) { @@ -45,8 +47,38 @@ static void __init armada_370_xp_timer_and_clk_init(void) #endif } +static void __init i2c_quirk(void) +{ + struct device_node *np; + u32 dev, rev; + + /* + * Only revisons more recent than A0 support the offload + * mechanism. We can exit only if we are sure that we can + * get the SoC revision and it is more recent than A0. + */ + if (mvebu_get_soc_id(&rev, &dev) == 0 && dev > MV78XX0_A0_REV) + return; + + for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") { + struct property *new_compat; + + new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL); + + new_compat->name = kstrdup("compatible", GFP_KERNEL); + new_compat->length = sizeof("marvell,mv78230-a0-i2c"); + new_compat->value = kstrdup("marvell,mv78230-a0-i2c", + GFP_KERNEL); + + of_update_property(np, new_compat); + } + return; +} + static void __init armada_370_xp_dt_init(void) { + if (of_machine_is_compatible("plathome,openblocks-ax3-4")) + i2c_quirk(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h index c612b2c..237c86b 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.h +++ b/arch/arm/mach-mvebu/armada-370-xp.h @@ -18,8 +18,12 @@ #ifdef CONFIG_SMP #include <linux/cpumask.h> +#define ARMADA_XP_MAX_CPUS 4 + void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq); void armada_xp_mpic_smp_cpu_init(void); +void armada_xp_secondary_startup(void); +extern struct smp_operations armada_xp_smp_ops; #endif #endif /* __MACH_ARMADA_370_XP_H */ diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 58adf2f..4e9d581 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -27,6 +27,7 @@ #include <asm/smp_plat.h> #include <asm/cacheflush.h> #include "armada-370-xp.h" +#include "coherency.h" unsigned long coherency_phys_base; static void __iomem *coherency_base; diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h index df33ad8..760226c 100644 --- a/arch/arm/mach-mvebu/coherency.h +++ b/arch/arm/mach-mvebu/coherency.h @@ -14,7 +14,9 @@ #ifndef __MACH_370_XP_COHERENCY_H #define __MACH_370_XP_COHERENCY_H -int set_cpu_coherent(int cpu_id, int smp_group_id); +extern unsigned long coherency_phys_base; + +int set_cpu_coherent(unsigned int cpu_id, int smp_group_id); int coherency_init(void); #endif /* __MACH_370_XP_COHERENCY_H */ diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h index e366010..55449c4 100644 --- a/arch/arm/mach-mvebu/common.h +++ b/arch/arm/mach-mvebu/common.h @@ -15,18 +15,10 @@ #ifndef __ARCH_MVEBU_COMMON_H #define __ARCH_MVEBU_COMMON_H -#define ARMADA_XP_MAX_CPUS 4 - #include <linux/reboot.h> void mvebu_restart(enum reboot_mode mode, const char *cmd); -void armada_370_xp_init_irq(void); -void armada_370_xp_handle_irq(struct pt_regs *regs); - void armada_xp_cpu_die(unsigned int cpu); -int armada_370_xp_coherency_init(void); -int armada_370_xp_pmsu_init(void); -void armada_xp_secondary_startup(void); -extern struct smp_operations armada_xp_smp_ops; + #endif diff --git a/arch/arm/mach-mvebu/hotplug.c b/arch/arm/mach-mvebu/hotplug.c index b228b6a..d95e910 100644 --- a/arch/arm/mach-mvebu/hotplug.c +++ b/arch/arm/mach-mvebu/hotplug.c @@ -15,6 +15,7 @@ #include <linux/errno.h> #include <linux/smp.h> #include <asm/proc-fns.h> +#include "common.h" /* * platform-specific code to shutdown a CPU diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c new file mode 100644 index 0000000..fe4fc1c --- /dev/null +++ b/arch/arm/mach-mvebu/mvebu-soc-id.c @@ -0,0 +1,119 @@ +/* + * ID and revision information for mvebu SoCs + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * All the mvebu SoCs have information related to their variant and + * revision that can be read from the PCI control register. This is + * done before the PCI initialization to avoid any conflict. Once the + * ID and revision are retrieved, the mapping is freed. + */ + +#define pr_fmt(fmt) "mvebu-soc-id: " fmt + +#include <linux/clk.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include "mvebu-soc-id.h" + +#define PCIE_DEV_ID_OFF 0x0 +#define PCIE_DEV_REV_OFF 0x8 + +#define SOC_ID_MASK 0xFFFF0000 +#define SOC_REV_MASK 0xFF + +static u32 soc_dev_id; +static u32 soc_rev; +static bool is_id_valid; + +static const struct of_device_id mvebu_pcie_of_match_table[] = { + { .compatible = "marvell,armada-xp-pcie", }, + { .compatible = "marvell,armada-370-pcie", }, + {}, +}; + +int mvebu_get_soc_id(u32 *dev, u32 *rev) +{ + if (is_id_valid) { + *dev = soc_dev_id; + *rev = soc_rev; + return 0; + } else + return -1; +} + +static int __init mvebu_soc_id_init(void) +{ + struct device_node *np; + int ret = 0; + void __iomem *pci_base; + struct clk *clk; + struct device_node *child; + + np = of_find_matching_node(NULL, mvebu_pcie_of_match_table); + if (!np) + return ret; + + /* + * ID and revision are available from any port, so we + * just pick the first one + */ + child = of_get_next_child(np, NULL); + if (child == NULL) { + pr_err("cannot get pci node\n"); + ret = -ENOMEM; + goto clk_err; + } + + clk = of_clk_get_by_name(child, NULL); + if (IS_ERR(clk)) { + pr_err("cannot get clock\n"); + ret = -ENOMEM; + goto clk_err; + } + + ret = clk_prepare_enable(clk); + if (ret) { + pr_err("cannot enable clock\n"); + goto clk_err; + } + + pci_base = of_iomap(child, 0); + if (IS_ERR(pci_base)) { + pr_err("cannot map registers\n"); + ret = -ENOMEM; + goto res_ioremap; + } + + /* SoC ID */ + soc_dev_id = readl(pci_base + PCIE_DEV_ID_OFF) >> 16; + + /* SoC revision */ + soc_rev = readl(pci_base + PCIE_DEV_REV_OFF) & SOC_REV_MASK; + + is_id_valid = true; + + pr_info("MVEBU SoC ID=0x%X, Rev=0x%X\n", soc_dev_id, soc_rev); + + iounmap(pci_base); + +res_ioremap: + clk_disable_unprepare(clk); + +clk_err: + of_node_put(child); + of_node_put(np); + + return ret; +} +core_initcall(mvebu_soc_id_init); + diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.h b/arch/arm/mach-mvebu/mvebu-soc-id.h new file mode 100644 index 0000000..3165425 --- /dev/null +++ b/arch/arm/mach-mvebu/mvebu-soc-id.h @@ -0,0 +1,32 @@ +/* + * Marvell EBU SoC ID and revision definitions. + * + * Copyright (C) 2014 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __LINUX_MVEBU_SOC_ID_H +#define __LINUX_MVEBU_SOC_ID_H + +/* Armada XP ID */ +#define MV78230_DEV_ID 0x7823 +#define MV78260_DEV_ID 0x7826 +#define MV78460_DEV_ID 0x7846 + +/* Armada XP Revision */ +#define MV78XX0_A0_REV 0x1 +#define MV78XX0_B0_REV 0x2 + +#ifdef CONFIG_ARCH_MVEBU +int mvebu_get_soc_id(u32 *dev, u32 *rev); +#else +static inline int mvebu_get_soc_id(u32 *dev, u32 *rev) +{ + return -1; +} +#endif + +#endif /* __LINUX_MVEBU_SOC_ID_H */ diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index ff69c2d..a6da03f 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c @@ -46,7 +46,7 @@ static struct clk *__init get_cpu_clk(int cpu) return cpu_clk; } -void __init set_secondary_cpus_clock(void) +static void __init set_secondary_cpus_clock(void) { int thiscpu, cpu; unsigned long rate; @@ -94,7 +94,7 @@ static void __init armada_xp_smp_init_cpus(void) set_smp_cross_call(armada_mpic_send_doorbell); } -void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) +static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) { struct device_node *node; struct resource res; diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c index 27fc4f0..d71ef53 100644 --- a/arch/arm/mach-mvebu/pmsu.c +++ b/arch/arm/mach-mvebu/pmsu.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <linux/smp.h> #include <asm/smp_plat.h> +#include "pmsu.h" static void __iomem *pmsu_mp_base; static void __iomem *pmsu_reset_base; @@ -58,7 +59,7 @@ int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr) } #endif -int __init armada_370_xp_pmsu_init(void) +static int __init armada_370_xp_pmsu_init(void) { struct device_node *np; diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index 5175083c..a7fb89a 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c @@ -27,6 +27,7 @@ #include <linux/of_address.h> #include <linux/io.h> #include <linux/reboot.h> +#include "common.h" static void __iomem *system_controller_base; @@ -39,14 +40,14 @@ struct mvebu_system_controller { }; static struct mvebu_system_controller *mvebu_sc; -const struct mvebu_system_controller armada_370_xp_system_controller = { +static const struct mvebu_system_controller armada_370_xp_system_controller = { .rstoutn_mask_offset = 0x60, .system_soft_reset_offset = 0x64, .rstoutn_mask_reset_out_en = 0x1, .system_soft_reset = 0x1, }; -const struct mvebu_system_controller orion_system_controller = { +static const struct mvebu_system_controller orion_system_controller = { .rstoutn_mask_offset = 0x108, .system_soft_reset_offset = 0x10c, .rstoutn_mask_reset_out_en = 0x4, diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index cce2c9d..4a1065e 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@ -110,38 +110,6 @@ static void cpu8815_restart(enum reboot_mode mode, const char *cmd) } /* - * The SMSC911x IRQ is connected to a GPIO pin, but the driver expects - * to simply request an IRQ passed as a resource. So the GPIO pin needs - * to be requested by this hog and set as input. - */ -static int __init cpu8815_eth_init(void) -{ - struct device_node *eth; - int gpio, irq, err; - - eth = of_find_node_by_path("/usb-s8815/ethernet-gpio"); - if (!eth) { - pr_info("could not find any ethernet GPIO\n"); - return 0; - } - gpio = of_get_gpio(eth, 0); - err = gpio_request(gpio, "eth_irq"); - if (err) { - pr_info("failed to request ethernet GPIO\n"); - return -ENODEV; - } - err = gpio_direction_input(gpio); - if (err) { - pr_info("failed to set ethernet GPIO as input\n"); - return -ENODEV; - } - irq = gpio_to_irq(gpio); - pr_info("enabled USB-S8815 ethernet GPIO %d, IRQ %d\n", gpio, irq); - return 0; -} -device_initcall(cpu8815_eth_init); - -/* * This GPIO pin turns on a line that is used to detect card insertion * on this board. */ diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index 6b5f298..a7588cf 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -181,7 +181,7 @@ static __init void omap_init_mpu_timer(unsigned long rate) * --------------------------------------------------------------------------- */ -static u32 notrace omap_mpu_read_sched_clock(void) +static u64 notrace omap_mpu_read_sched_clock(void) { return ~omap_mpu_timer_read(1); } @@ -193,7 +193,7 @@ static void __init omap_init_clocksource(unsigned long rate) "%s: can't register clocksource!\n"; omap_mpu_timer_start(1, ~0, 1); - setup_sched_clock(omap_mpu_read_sched_clock, 32, rate); + sched_clock_register(omap_mpu_read_sched_clock, 32, rate); if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate, 300, 32, clocksource_mmio_readl_down)) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index dc21df1..4191ae0 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -192,19 +192,6 @@ config MACH_OMAP2_TUSB6010 depends on ARCH_OMAP2 && SOC_OMAP2420 default y if MACH_NOKIA_N8X0 -config MACH_OMAP_H4 - bool "OMAP 2420 H4 board" - depends on SOC_OMAP2420 - default y - select OMAP_DEBUG_DEVICES - select OMAP_PACKAGE_ZAF - -config MACH_OMAP_2430SDP - bool "OMAP 2430 SDP board" - depends on SOC_OMAP2430 - default y - select OMAP_PACKAGE_ZAC - config MACH_OMAP3_BEAGLE bool "OMAP3 BEAGLE board" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index adcef40..f78b177 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -66,8 +66,6 @@ obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o # Pin multiplexing -obj-$(CONFIG_SOC_OMAP2420) += mux2420.o -obj-$(CONFIG_SOC_OMAP2430) += mux2430.o obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o # SMS/SDRC @@ -237,8 +235,6 @@ obj-$(CONFIG_SOC_OMAP2420) += msdi.o # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o -obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o -obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c deleted file mode 100644 index c711ad6..0000000 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/board-2430sdp.c - * - * Copyright (C) 2006 Texas Instruments - * - * Modified from mach-omap2/board-generic.c - * - * Initial Code : Based on a patch from Komal Shah and Richard Woodruff - * Updated the Code for 2430 SDP : Syed Mohammed Khasim - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/mmc/host.h> -#include <linux/delay.h> -#include <linux/i2c/twl.h> -#include <linux/regulator/machine.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/usb/phy.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "gpmc.h" -#include "gpmc-smc91x.h" - -#include <video/omapdss.h> -#include <video/omap-panel-data.h> - -#include "mux.h" -#include "hsmmc.h" -#include "common-board-devices.h" - -#define SDP2430_CS0_BASE 0x04000000 -#define SECONDARY_LCD_GPIO 147 - -static struct mtd_partition sdp2430_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_256K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* file system */ - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - } -}; - -static struct physmap_flash_data sdp2430_flash_data = { - .width = 2, - .parts = sdp2430_partitions, - .nr_parts = ARRAY_SIZE(sdp2430_partitions), -}; - -static struct resource sdp2430_flash_resource = { - .start = SDP2430_CS0_BASE, - .end = SDP2430_CS0_BASE + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device sdp2430_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &sdp2430_flash_data, - }, - .num_resources = 1, - .resource = &sdp2430_flash_resource, -}; - -/* LCD */ -#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91 -#define SDP2430_LCD_PANEL_ENABLE_GPIO 154 - -static const struct display_timing sdp2430_lcd_videomode = { - .pixelclock = { 0, 5400000, 0 }, - - .hactive = { 0, 240, 0 }, - .hfront_porch = { 0, 3, 0 }, - .hback_porch = { 0, 39, 0 }, - .hsync_len = { 0, 3, 0 }, - - .vactive = { 0, 320, 0 }, - .vfront_porch = { 0, 2, 0 }, - .vback_porch = { 0, 7, 0 }, - .vsync_len = { 0, 1, 0 }, - - .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | - DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, -}; - -static struct panel_dpi_platform_data sdp2430_lcd_pdata = { - .name = "lcd", - .source = "dpi.0", - - .data_lines = 16, - - .display_timing = &sdp2430_lcd_videomode, - - .enable_gpio = SDP2430_LCD_PANEL_ENABLE_GPIO, - .backlight_gpio = SDP2430_LCD_PANEL_BACKLIGHT_GPIO, -}; - -static struct platform_device sdp2430_lcd_device = { - .name = "panel-dpi", - .id = 0, - .dev.platform_data = &sdp2430_lcd_pdata, -}; - -static struct omap_dss_board_info sdp2430_dss_data = { - .default_display_name = "lcd", -}; - -static struct platform_device *sdp2430_devices[] __initdata = { - &sdp2430_flash_device, - &sdp2430_lcd_device, -}; - -#if IS_ENABLED(CONFIG_SMC91X) - -static struct omap_smc91x_platform_data board_smc91x_data = { - .cs = 5, - .gpio_irq = 149, - .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 | - IORESOURCE_IRQ_LOWLEVEL, - -}; - -static void __init board_smc91x_init(void) -{ - omap_mux_init_gpio(149, OMAP_PIN_INPUT); - gpmc_smc91x_init(&board_smc91x_data); -} - -#else - -static inline void board_smc91x_init(void) -{ -} - -#endif - -static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = { - REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), -}; - -/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ -static struct regulator_init_data sdp2430_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(sdp2430_vmmc1_supplies), - .consumer_supplies = &sdp2430_vmmc1_supplies[0], -}; - -static struct twl4030_gpio_platform_data sdp2430_gpio_data = { -}; - -static struct twl4030_platform_data sdp2430_twldata = { - /* platform_data for children goes here */ - .gpio = &sdp2430_gpio_data, - .vmmc1 = &sdp2430_vmmc1, -}; - -static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = { - { - I2C_BOARD_INFO("isp1301_omap", 0x2D), - .flags = I2C_CLIENT_WAKE, - }, -}; - -static int __init omap2430_i2c_init(void) -{ - sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78); - omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo, - ARRAY_SIZE(sdp2430_i2c1_boardinfo)); - omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START, - &sdp2430_twldata); - return 0; -} - -static struct omap2_hsmmc_info mmc[] __initdata = { - { - .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - .ext_clock = 1, - }, - {} /* Terminator */ -}; - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#endif - -static void __init omap_2430sdp_init(void) -{ - omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC); - - omap2430_i2c_init(); - - platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); - omap_serial_init(); - omap_sdrc_init(NULL, NULL); - omap_hsmmc_init(mmc); - - omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP); - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); - usb_musb_init(NULL); - - board_smc91x_init(); - - /* Turn off secondary LCD backlight */ - gpio_request_one(SECONDARY_LCD_GPIO, GPIOF_OUT_INIT_LOW, - "Secondary LCD backlight"); - - omap_display_init(&sdp2430_dss_data); -} - -MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") - /* Maintainer: Syed Khasim - Texas Instruments Inc */ - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap243x_map_io, - .init_early = omap2430_init_early, - .init_irq = omap2_init_irq, - .handle_irq = omap2_intc_handle_irq, - .init_machine = omap_2430sdp_init, - .init_late = omap2430_init_late, - .init_time = omap2_sync32k_timer_init, - .restart = omap2xxx_restart, -MACHINE_END diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 8d972ff1..8e3daa1 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -78,6 +78,7 @@ MACHINE_END #ifdef CONFIG_ARCH_OMAP3 static const char *omap3_boards_compat[] __initdata = { + "ti,omap3430", "ti,omap3", NULL, }; @@ -173,6 +174,8 @@ MACHINE_END #ifdef CONFIG_ARCH_OMAP4 static const char *omap4_boards_compat[] __initdata = { + "ti,omap4460", + "ti,omap4430", "ti,omap4", NULL, }; @@ -193,6 +196,8 @@ MACHINE_END #ifdef CONFIG_SOC_OMAP5 static const char *omap5_boards_compat[] __initdata = { + "ti,omap5432", + "ti,omap5430", "ti,omap5", NULL, }; @@ -213,6 +218,7 @@ MACHINE_END #ifdef CONFIG_SOC_AM43XX static const char *am43_boards_compat[] __initdata = { + "ti,am4372", "ti,am43", NULL, }; @@ -230,6 +236,7 @@ MACHINE_END #ifdef CONFIG_SOC_DRA7XX static const char *dra7xx_boards_compat[] __initdata = { + "ti,dra7xx", "ti,dra7", NULL, }; diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c deleted file mode 100644 index f780834..0000000 --- a/arch/arm/mach-omap2/board-h4.c +++ /dev/null @@ -1,365 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/board-h4.c - * - * Copyright (C) 2005 Nokia Corporation - * Author: Paul Mundt <paul.mundt@nokia.com> - * - * Modified from mach-omap/omap1/board-generic.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/delay.h> -#include <linux/workqueue.h> -#include <linux/i2c.h> -#include <linux/platform_data/at24.h> -#include <linux/input.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/input/matrix_keypad.h> -#include <linux/mfd/menelaus.h> -#include <linux/omap-dma.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <video/omapdss.h> -#include <video/omap-panel-data.h> - -#include "common.h" -#include "mux.h" -#include "control.h" -#include "gpmc.h" -#include "gpmc-smc91x.h" - -#define H4_FLASH_CS 0 - -#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE) -static const uint32_t board_matrix_keys[] = { - KEY(0, 0, KEY_LEFT), - KEY(1, 0, KEY_RIGHT), - KEY(2, 0, KEY_A), - KEY(3, 0, KEY_B), - KEY(4, 0, KEY_C), - KEY(0, 1, KEY_DOWN), - KEY(1, 1, KEY_UP), - KEY(2, 1, KEY_E), - KEY(3, 1, KEY_F), - KEY(4, 1, KEY_G), - KEY(0, 2, KEY_ENTER), - KEY(1, 2, KEY_I), - KEY(2, 2, KEY_J), - KEY(3, 2, KEY_K), - KEY(4, 2, KEY_3), - KEY(0, 3, KEY_M), - KEY(1, 3, KEY_N), - KEY(2, 3, KEY_O), - KEY(3, 3, KEY_P), - KEY(4, 3, KEY_Q), - KEY(0, 4, KEY_R), - KEY(1, 4, KEY_4), - KEY(2, 4, KEY_T), - KEY(3, 4, KEY_U), - KEY(4, 4, KEY_ENTER), - KEY(0, 5, KEY_V), - KEY(1, 5, KEY_W), - KEY(2, 5, KEY_L), - KEY(3, 5, KEY_S), - KEY(4, 5, KEY_ENTER), -}; - -static const struct matrix_keymap_data board_keymap_data = { - .keymap = board_matrix_keys, - .keymap_size = ARRAY_SIZE(board_matrix_keys), -}; - -static unsigned int board_keypad_row_gpios[] = { - 88, 89, 124, 11, 6, 96 -}; - -static unsigned int board_keypad_col_gpios[] = { - 90, 91, 100, 36, 12, 97, 98 -}; - -static struct matrix_keypad_platform_data board_keypad_platform_data = { - .keymap_data = &board_keymap_data, - .row_gpios = board_keypad_row_gpios, - .num_row_gpios = ARRAY_SIZE(board_keypad_row_gpios), - .col_gpios = board_keypad_col_gpios, - .num_col_gpios = ARRAY_SIZE(board_keypad_col_gpios), - .active_low = 1, - - .debounce_ms = 20, - .col_scan_delay_us = 5, -}; - -static struct platform_device board_keyboard = { - .name = "matrix-keypad", - .id = -1, - .dev = { - .platform_data = &board_keypad_platform_data, - }, -}; -static void __init board_mkp_init(void) -{ - omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP); - omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP); - omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP); - omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP); - if (omap_has_menelaus()) { - omap_mux_init_signal("sdrc_a14.gpio0", - OMAP_PULL_ENA | OMAP_PULL_UP); - omap_mux_init_signal("vlynq_rx0.gpio_15", 0); - omap_mux_init_signal("gpio_98", 0); - board_keypad_row_gpios[5] = 0; - board_keypad_col_gpios[2] = 15; - board_keypad_col_gpios[6] = 18; - } else { - omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP); - omap_mux_init_signal("gpio_100", 0); - omap_mux_init_signal("gpio_98", 0); - } - omap_mux_init_signal("gpio_90", 0); - omap_mux_init_signal("gpio_91", 0); - omap_mux_init_signal("gpio_36", 0); - omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0); - omap_mux_init_signal("gpio_97", 0); - - platform_device_register(&board_keyboard); -} -#else -static inline void board_mkp_init(void) -{ -} -#endif - -static struct mtd_partition h4_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* file system */ - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - } -}; - -static struct physmap_flash_data h4_flash_data = { - .width = 2, - .parts = h4_partitions, - .nr_parts = ARRAY_SIZE(h4_partitions), -}; - -static struct resource h4_flash_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device h4_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &h4_flash_data, - }, - .num_resources = 1, - .resource = &h4_flash_resource, -}; - -static const struct display_timing cm_t35_lcd_videomode = { - .pixelclock = { 0, 6250000, 0 }, - - .hactive = { 0, 240, 0 }, - .hfront_porch = { 0, 15, 0 }, - .hback_porch = { 0, 60, 0 }, - .hsync_len = { 0, 15, 0 }, - - .vactive = { 0, 320, 0 }, - .vfront_porch = { 0, 1, 0 }, - .vback_porch = { 0, 1, 0 }, - .vsync_len = { 0, 1, 0 }, - - .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | - DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, -}; - -static struct panel_dpi_platform_data cm_t35_lcd_pdata = { - .name = "lcd", - .source = "dpi.0", - - .data_lines = 16, - - .display_timing = &cm_t35_lcd_videomode, - - .enable_gpio = -1, - .backlight_gpio = -1, -}; - -static struct platform_device cm_t35_lcd_device = { - .name = "panel-dpi", - .id = 0, - .dev.platform_data = &cm_t35_lcd_pdata, -}; - -static struct platform_device *h4_devices[] __initdata = { - &h4_flash_device, - &cm_t35_lcd_device, -}; - -static struct omap_dss_board_info h4_dss_data = { - .default_display_name = "lcd", -}; - -/* 2420 Sysboot setup (2430 is different) */ -static u32 get_sysboot_value(void) -{ - return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) & - (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK | - OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK | - OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK)); -} - -/* H4-2420's always used muxed mode, H4-2422's always use non-muxed - * - * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423 - * correctly. The macro needs to look at production_id not just hawkeye. - */ -static u32 is_gpmc_muxed(void) -{ - u32 mux; - mux = get_sysboot_value(); - if ((mux & 0xF) == 0xd) - return 1; /* NAND config (could be either) */ - if (mux & 0x2) /* if mux'ed */ - return 1; - else - return 0; -} - -#if IS_ENABLED(CONFIG_SMC91X) - -static struct omap_smc91x_platform_data board_smc91x_data = { - .cs = 1, - .gpio_irq = 92, - .flags = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_LOWLEVEL, -}; - -static void __init board_smc91x_init(void) -{ - if (is_gpmc_muxed()) - board_smc91x_data.flags |= GPMC_MUX_ADD_DATA; - - omap_mux_init_gpio(board_smc91x_data.gpio_irq, OMAP_PIN_INPUT); - gpmc_smc91x_init(&board_smc91x_data); -} - -#else - -static inline void board_smc91x_init(void) -{ -} - -#endif - -static void __init h4_init_flash(void) -{ - unsigned long base; - - if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) { - printk("Can't request GPMC CS for flash\n"); - return; - } - h4_flash_resource.start = base; - h4_flash_resource.end = base + SZ_64M - 1; -} - -static struct at24_platform_data m24c01 = { - .byte_len = SZ_1K / 8, - .page_size = 16, -}; - -static struct i2c_board_info __initdata h4_i2c_board_info[] = { - { - I2C_BOARD_INFO("isp1301_omap", 0x2d), - }, - { /* EEPROM on mainboard */ - I2C_BOARD_INFO("24c01", 0x52), - .platform_data = &m24c01, - }, - { /* EEPROM on cpu card */ - I2C_BOARD_INFO("24c01", 0x57), - .platform_data = &m24c01, - }, -}; - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#endif - -static void __init omap_h4_init(void) -{ - omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF); - - /* - * Make sure the serial ports are muxed on at this point. - * You have to mux them off in device drivers later on - * if not needed. - */ - - board_mkp_init(); - h4_i2c_board_info[0].irq = gpio_to_irq(125); - i2c_register_board_info(1, h4_i2c_board_info, - ARRAY_SIZE(h4_i2c_board_info)); - - platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); - omap_serial_init(); - omap_sdrc_init(NULL, NULL); - h4_init_flash(); - board_smc91x_init(); - - omap_display_init(&h4_dss_data); -} - -MACHINE_START(OMAP_H4, "OMAP2420 H4 board") - /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap242x_map_io, - .init_early = omap2420_init_early, - .init_irq = omap2_init_irq, - .handle_irq = omap2_intc_handle_irq, - .init_machine = omap_h4_init, - .init_late = omap2420_init_late, - .init_time = omap2_sync32k_timer_init, - .restart = omap2xxx_restart, -MACHINE_END diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 827d150..aead77a 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -21,7 +21,6 @@ #include <linux/i2c.h> #include <linux/spi/spi.h> #include <linux/usb/musb.h> -#include <linux/platform_data/i2c-cbus-gpio.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/platform_data/mtd-onenand-omap2.h> #include <linux/mfd/menelaus.h> @@ -32,8 +31,7 @@ #include "common.h" #include "mmc.h" - -#include "mux.h" +#include "soc.h" #include "gpmc-onenand.h" #define TUSB6010_ASYNC_CS 1 @@ -42,44 +40,30 @@ #define TUSB6010_GPIO_ENABLE 0 #define TUSB6010_DMACHAN 0x3f -#if defined(CONFIG_I2C_CBUS_GPIO) || defined(CONFIG_I2C_CBUS_GPIO_MODULE) -static struct i2c_cbus_platform_data n8x0_cbus_data = { - .clk_gpio = 66, - .dat_gpio = 65, - .sel_gpio = 64, -}; +#define NOKIA_N810_WIMAX (1 << 2) +#define NOKIA_N810 (1 << 1) +#define NOKIA_N800 (1 << 0) -static struct platform_device n8x0_cbus_device = { - .name = "i2c-cbus-gpio", - .id = 3, - .dev = { - .platform_data = &n8x0_cbus_data, - }, -}; +static u32 board_caps; -static struct i2c_board_info n8x0_i2c_board_info_3[] __initdata = { - { - I2C_BOARD_INFO("retu-mfd", 0x01), - }, -}; +#define board_is_n800() (board_caps & NOKIA_N800) +#define board_is_n810() (board_caps & NOKIA_N810) +#define board_is_n810_wimax() (board_caps & NOKIA_N810_WIMAX) -static void __init n8x0_cbus_init(void) +static void board_check_revision(void) { - const int retu_irq_gpio = 108; + if (of_have_populated_dt()) { + if (of_machine_is_compatible("nokia,n800")) + board_caps = NOKIA_N800; + else if (of_machine_is_compatible("nokia,n810")) + board_caps = NOKIA_N810; + else if (of_machine_is_compatible("nokia,n810-wimax")) + board_caps = NOKIA_N810_WIMAX; + } - if (gpio_request_one(retu_irq_gpio, GPIOF_IN, "Retu IRQ")) - return; - irq_set_irq_type(gpio_to_irq(retu_irq_gpio), IRQ_TYPE_EDGE_RISING); - n8x0_i2c_board_info_3[0].irq = gpio_to_irq(retu_irq_gpio); - i2c_register_board_info(3, n8x0_i2c_board_info_3, - ARRAY_SIZE(n8x0_i2c_board_info_3)); - platform_device_register(&n8x0_cbus_device); -} -#else /* CONFIG_I2C_CBUS_GPIO */ -static void __init n8x0_cbus_init(void) -{ + if (!board_caps) + pr_err("Unknown board\n"); } -#endif /* CONFIG_I2C_CBUS_GPIO */ #if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) /* @@ -178,49 +162,6 @@ static struct spi_board_info n800_spi_board_info[] __initdata = { }, }; -#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ - defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) - -static struct mtd_partition onenand_partitions[] = { - { - .name = "bootloader", - .offset = 0, - .size = 0x20000, - .mask_flags = MTD_WRITEABLE, /* Force read-only */ - }, - { - .name = "config", - .offset = MTDPART_OFS_APPEND, - .size = 0x60000, - }, - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = 0x200000, - }, - { - .name = "initfs", - .offset = MTDPART_OFS_APPEND, - .size = 0x400000, - }, - { - .name = "rootfs", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct omap_onenand_platform_data board_onenand_data[] = { - { - .cs = 0, - .gpio_irq = 26, - .parts = onenand_partitions, - .nr_parts = ARRAY_SIZE(onenand_partitions), - .flags = ONENAND_SYNC_READ, - } -}; -#endif - #if defined(CONFIG_MENELAUS) && \ (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)) @@ -342,7 +283,7 @@ static void n810_set_power_emmc(struct device *dev, static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on, int vdd) { - if (machine_is_nokia_n800() || slot == 0) + if (board_is_n800() || slot == 0) return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd); n810_set_power_emmc(dev, power_on); @@ -388,7 +329,7 @@ static void n8x0_mmc_callback(void *data, u8 card_mask) { int bit, *openp, index; - if (machine_is_nokia_n800()) { + if (board_is_n800()) { bit = 1 << 1; openp = &slot2_cover_open; index = 1; @@ -421,7 +362,7 @@ static int n8x0_mmc_late_init(struct device *dev) if (r < 0) return r; - if (machine_is_nokia_n800()) + if (board_is_n800()) vs2sel = 0; else vs2sel = 2; @@ -444,7 +385,7 @@ static int n8x0_mmc_late_init(struct device *dev) if (r < 0) return r; - if (machine_is_nokia_n800()) { + if (board_is_n800()) { bit = 1 << 1; openp = &slot2_cover_open; } else { @@ -471,7 +412,7 @@ static void n8x0_mmc_shutdown(struct device *dev) { int vs2sel; - if (machine_is_nokia_n800()) + if (board_is_n800()) vs2sel = 0; else vs2sel = 2; @@ -486,7 +427,7 @@ static void n8x0_mmc_cleanup(struct device *dev) gpio_free(N8X0_SLOT_SWITCH_GPIO); - if (machine_is_nokia_n810()) { + if (board_is_n810()) { gpio_free(N810_EMMC_VSD_GPIO); gpio_free(N810_EMMC_VIO_GPIO); } @@ -497,7 +438,7 @@ static void n8x0_mmc_cleanup(struct device *dev) * MMC controller2 is not in use. */ static struct omap_mmc_platform_data mmc1_data = { - .nr_slots = 2, + .nr_slots = 0, .switch_slot = n8x0_mmc_switch_slot, .init = n8x0_mmc_late_init, .cleanup = n8x0_mmc_cleanup, @@ -537,7 +478,7 @@ static void __init n8x0_mmc_init(void) { int err; - if (machine_is_nokia_n810()) { + if (board_is_n810()) { mmc1_data.slots[0].name = "external"; /* @@ -555,7 +496,7 @@ static void __init n8x0_mmc_init(void) if (err) return; - if (machine_is_nokia_n810()) { + if (board_is_n810()) { err = gpio_request_array(n810_emmc_gpios, ARRAY_SIZE(n810_emmc_gpios)); if (err) { @@ -564,11 +505,11 @@ static void __init n8x0_mmc_init(void) } } + mmc1_data.nr_slots = 2; mmc_data[0] = &mmc1_data; - omap242x_init_mmc(mmc_data); } #else - +static struct omap_mmc_platform_data mmc1_data; void __init n8x0_mmc_init(void) { } @@ -650,109 +591,32 @@ static struct i2c_board_info n810_i2c_board_info_2[] __initdata = { }, }; -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - /* I2S codec port pins for McBSP block */ - OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -static struct omap_device_pad serial2_pads[] __initdata = { - { - .name = "uart3_rx_irrx.uart3_rx_irrx", - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, - .enable = OMAP_MUX_MODE0, - .idle = OMAP_MUX_MODE3 /* Mux as GPIO for idle */ - }, -}; - -static inline void board_serial_init(void) +static int __init n8x0_late_initcall(void) { - struct omap_board_data bdata; - - bdata.flags = 0; - bdata.pads = NULL; - bdata.pads_cnt = 0; - - bdata.id = 0; - omap_serial_init_port(&bdata, NULL); - - bdata.id = 1; - omap_serial_init_port(&bdata, NULL); - - bdata.id = 2; - bdata.pads = serial2_pads; - bdata.pads_cnt = ARRAY_SIZE(serial2_pads); - omap_serial_init_port(&bdata, NULL); -} + if (!board_caps) + return -ENODEV; -#else + n8x0_mmc_init(); + n8x0_usb_init(); -static inline void board_serial_init(void) -{ - omap_serial_init(); + return 0; } +omap_late_initcall(n8x0_late_initcall); -#endif - -static void __init n8x0_init_machine(void) +/* + * Legacy init pdata init for n8x0. Note that we want to follow the + * I2C bus numbering starting at 0 for device tree like other omaps. + */ +void * __init n8x0_legacy_init(void) { - omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); - /* FIXME: add n810 spi devices */ + board_check_revision(); spi_register_board_info(n800_spi_board_info, ARRAY_SIZE(n800_spi_board_info)); - omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, - ARRAY_SIZE(n8x0_i2c_board_info_1)); - omap_register_i2c_bus(2, 400, NULL, 0); - if (machine_is_nokia_n810()) - i2c_register_board_info(2, n810_i2c_board_info_2, + i2c_register_board_info(0, n8x0_i2c_board_info_1, + ARRAY_SIZE(n8x0_i2c_board_info_1)); + if (board_is_n810()) + i2c_register_board_info(1, n810_i2c_board_info_2, ARRAY_SIZE(n810_i2c_board_info_2)); - board_serial_init(); - omap_sdrc_init(NULL, NULL); - gpmc_onenand_init(board_onenand_data); - n8x0_mmc_init(); - n8x0_usb_init(); - n8x0_cbus_init(); -} -MACHINE_START(NOKIA_N800, "Nokia N800") - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap242x_map_io, - .init_early = omap2420_init_early, - .init_irq = omap2_init_irq, - .handle_irq = omap2_intc_handle_irq, - .init_machine = n8x0_init_machine, - .init_late = omap2420_init_late, - .init_time = omap2_sync32k_timer_init, - .restart = omap2xxx_restart, -MACHINE_END - -MACHINE_START(NOKIA_N810, "Nokia N810") - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap242x_map_io, - .init_early = omap2420_init_early, - .init_irq = omap2_init_irq, - .handle_irq = omap2_intc_handle_irq, - .init_machine = n8x0_init_machine, - .init_late = omap2420_init_late, - .init_time = omap2_sync32k_timer_init, - .restart = omap2xxx_restart, -MACHINE_END - -MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap242x_map_io, - .init_early = omap2420_init_early, - .init_irq = omap2_init_irq, - .handle_irq = omap2_intc_handle_irq, - .init_machine = n8x0_init_machine, - .init_late = omap2420_init_late, - .init_time = omap2_sync32k_timer_init, - .restart = omap2xxx_restart, -MACHINE_END + return &mmc1_data; +} diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h index 72bb41b..f338177 100644 --- a/arch/arm/mach-omap2/common-board-devices.h +++ b/arch/arm/mach-omap2/common-board-devices.h @@ -10,5 +10,6 @@ struct ads7846_platform_data; void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, struct ads7846_platform_data *board_pdata); +void *n8x0_legacy_init(void); #endif /* __OMAP_COMMON_BOARD_DEVICES__ */ diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index e30ef67..240db38 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -293,6 +293,7 @@ static inline void omap4_cpu_resume(void) #endif void pdata_quirks_init(struct of_device_id *); +void omap_auxdata_legacy_init(struct device *dev); void omap_pcs_legacy_init(int irq, void (*rearm)(void)); struct omap_sdrc_params; diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 662c7fd..174caec 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -65,6 +65,22 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) return 1; } +/* This function will go away once the device-tree convertion is complete */ +static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data, + struct gpmc_settings *s) +{ + /* Enable RD PIN Monitoring Reg */ + if (gpmc_nand_data->dev_ready) { + s->wait_on_read = true; + s->wait_on_write = true; + } + + if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) + s->device_width = GPMC_DEVWIDTH_16BIT; + else + s->device_width = GPMC_DEVWIDTH_8BIT; +} + int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, struct gpmc_timings *gpmc_t) { @@ -98,32 +114,22 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, dev_err(dev, "Unable to set gpmc timings: %d\n", err); return err; } + } - if (gpmc_nand_data->of_node) { - gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); - } else { - /* Enable RD PIN Monitoring Reg */ - if (gpmc_nand_data->dev_ready) { - s.wait_on_read = true; - s.wait_on_write = true; - } - } - - s.device_nand = true; + if (gpmc_nand_data->of_node) + gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); + else + gpmc_set_legacy(gpmc_nand_data, &s); - if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) - s.device_width = GPMC_DEVWIDTH_16BIT; - else - s.device_width = GPMC_DEVWIDTH_8BIT; + s.device_nand = true; - err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); - if (err < 0) - goto out_free_cs; + err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); + if (err < 0) + goto out_free_cs; - err = gpmc_configure(GPMC_CONFIG_WP, 0); - if (err < 0) - goto out_free_cs; - } + err = gpmc_configure(GPMC_CONFIG_WP, 0); + if (err < 0) + goto out_free_cs; gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index cd22262..07b68d5 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -244,7 +244,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = { .virtual = OMAP4_SRAM_VA, .pfn = __phys_to_pfn(OMAP4_SRAM_PA), .length = PAGE_SIZE, - .type = MT_MEMORY_SO, + .type = MT_MEMORY_RW_SO, }, #endif @@ -282,7 +282,7 @@ static struct map_desc omap54xx_io_desc[] __initdata = { .virtual = OMAP4_SRAM_VA, .pfn = __phys_to_pfn(OMAP4_SRAM_PA), .length = PAGE_SIZE, - .type = MT_MEMORY_SO, + .type = MT_MEMORY_RW_SO, }, #endif }; diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c index c52d8b4..828e0db 100644 --- a/arch/arm/mach-omap2/msdi.c +++ b/arch/arm/mach-omap2/msdi.c @@ -88,72 +88,3 @@ int omap_msdi_reset(struct omap_hwmod *oh) return 0; } - -#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) - -static inline void omap242x_mmc_mux(struct omap_mmc_platform_data - *mmc_controller) -{ - if ((mmc_controller->slots[0].switch_pin > 0) && \ - (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) - omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, - OMAP_PIN_INPUT_PULLUP); - if ((mmc_controller->slots[0].gpio_wp > 0) && \ - (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) - omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, - OMAP_PIN_INPUT_PULLUP); - - omap_mux_init_signal("sdmmc_cmd", 0); - omap_mux_init_signal("sdmmc_clki", 0); - omap_mux_init_signal("sdmmc_clko", 0); - omap_mux_init_signal("sdmmc_dat0", 0); - omap_mux_init_signal("sdmmc_dat_dir0", 0); - omap_mux_init_signal("sdmmc_cmd_dir", 0); - if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { - omap_mux_init_signal("sdmmc_dat1", 0); - omap_mux_init_signal("sdmmc_dat2", 0); - omap_mux_init_signal("sdmmc_dat3", 0); - omap_mux_init_signal("sdmmc_dat_dir1", 0); - omap_mux_init_signal("sdmmc_dat_dir2", 0); - omap_mux_init_signal("sdmmc_dat_dir3", 0); - } - - /* - * Use internal loop-back in MMC/SDIO Module Input Clock - * selection - */ - if (mmc_controller->slots[0].internal_clock) { - u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - v |= (1 << 24); - omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); - } -} - -void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) -{ - struct platform_device *pdev; - struct omap_hwmod *oh; - int id = 0; - char *oh_name = "msdi1"; - char *dev_name = "mmci-omap"; - - if (!mmc_data[0]) { - pr_err("%s fails: Incomplete platform data\n", __func__); - return; - } - - omap242x_mmc_mux(mmc_data[0]); - - oh = omap_hwmod_lookup(oh_name); - if (!oh) { - pr_err("Could not look up %s\n", oh_name); - return; - } - pdev = omap_device_build(dev_name, id, oh, mmc_data[0], - sizeof(struct omap_mmc_platform_data)); - if (IS_ERR(pdev)) - WARN(1, "Can'd build omap_device for %s:%s.\n", - dev_name, oh->name); -} - -#endif diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index 16f78a9..a722330 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -7,8 +7,6 @@ * published by the Free Software Foundation. */ -#include "mux2420.h" -#include "mux2430.h" #include "mux34xx.h" #define OMAP_MUX_TERMINATOR 0xffff diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c deleted file mode 100644 index cf6de097..0000000 --- a/arch/arm/mach-omap2/mux2420.c +++ /dev/null @@ -1,690 +0,0 @@ -/* - * Copyright (C) 2010 Nokia - * Copyright (C) 2010 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/module.h> -#include <linux/init.h> - -#include "mux.h" - -#ifdef CONFIG_OMAP_MUX - -#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ -{ \ - .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ - .gpio = (g), \ - .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ -} - -#else - -#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ -{ \ - .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ - .gpio = (g), \ -} - -#endif - -#define _OMAP2420_BALLENTRY(M0, bb, bt) \ -{ \ - .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ - .balls = { bb, bt }, \ -} - -/* - * Superset of all mux modes for omap2420 - */ -static struct omap_mux __initdata omap2420_muxmodes[] = { - _OMAP2420_MUXENTRY(CAM_D0, 54, - "cam_d0", "hw_dbg2", "sti_dout", "gpio_54", - NULL, NULL, "etk_d2", NULL), - _OMAP2420_MUXENTRY(CAM_D1, 53, - "cam_d1", "hw_dbg3", "sti_din", "gpio_53", - NULL, NULL, "etk_d3", NULL), - _OMAP2420_MUXENTRY(CAM_D2, 52, - "cam_d2", "hw_dbg4", "mcbsp1_clkx", "gpio_52", - NULL, NULL, "etk_d4", NULL), - _OMAP2420_MUXENTRY(CAM_D3, 51, - "cam_d3", "hw_dbg5", "mcbsp1_dr", "gpio_51", - NULL, NULL, "etk_d5", NULL), - _OMAP2420_MUXENTRY(CAM_D4, 50, - "cam_d4", "hw_dbg6", "mcbsp1_fsr", "gpio_50", - NULL, NULL, "etk_d6", NULL), - _OMAP2420_MUXENTRY(CAM_D5, 49, - "cam_d5", "hw_dbg7", "mcbsp1_clkr", "gpio_49", - NULL, NULL, "etk_d7", NULL), - _OMAP2420_MUXENTRY(CAM_D6, 0, - "cam_d6", "hw_dbg8", NULL, NULL, - NULL, NULL, "etk_d8", NULL), - _OMAP2420_MUXENTRY(CAM_D7, 0, - "cam_d7", "hw_dbg9", NULL, NULL, - NULL, NULL, "etk_d9", NULL), - _OMAP2420_MUXENTRY(CAM_D8, 54, - "cam_d8", "hw_dbg10", NULL, "gpio_54", - NULL, NULL, "etk_d10", NULL), - _OMAP2420_MUXENTRY(CAM_D9, 53, - "cam_d9", "hw_dbg11", NULL, "gpio_53", - NULL, NULL, "etk_d11", NULL), - _OMAP2420_MUXENTRY(CAM_HS, 55, - "cam_hs", "hw_dbg1", "mcbsp1_dx", "gpio_55", - NULL, NULL, "etk_d1", NULL), - _OMAP2420_MUXENTRY(CAM_LCLK, 57, - "cam_lclk", NULL, "mcbsp_clks", "gpio_57", - NULL, NULL, "etk_c1", NULL), - _OMAP2420_MUXENTRY(CAM_VS, 56, - "cam_vs", "hw_dbg0", "mcbsp1_fsx", "gpio_56", - NULL, NULL, "etk_d0", NULL), - _OMAP2420_MUXENTRY(CAM_XCLK, 0, - "cam_xclk", NULL, "sti_clk", NULL, - NULL, NULL, "etk_c2", NULL), - _OMAP2420_MUXENTRY(DSS_ACBIAS, 48, - "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA10, 40, - "dss_data10", NULL, NULL, "gpio_40", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA11, 41, - "dss_data11", NULL, NULL, "gpio_41", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA12, 42, - "dss_data12", NULL, NULL, "gpio_42", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA13, 43, - "dss_data13", NULL, NULL, "gpio_43", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA14, 44, - "dss_data14", NULL, NULL, "gpio_44", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA15, 45, - "dss_data15", NULL, NULL, "gpio_45", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA16, 46, - "dss_data16", NULL, NULL, "gpio_46", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA17, 47, - "dss_data17", NULL, NULL, "gpio_47", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA8, 38, - "dss_data8", NULL, NULL, "gpio_38", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(DSS_DATA9, 39, - "dss_data9", NULL, NULL, "gpio_39", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_AC_DIN, 115, - "eac_ac_din", "mcbsp2_dr", NULL, "gpio_115", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_AC_DOUT, 116, - "eac_ac_dout", "mcbsp2_dx", NULL, "gpio_116", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_AC_FS, 114, - "eac_ac_fs", "mcbsp2_fsx", NULL, "gpio_114", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_AC_MCLK, 117, - "eac_ac_mclk", NULL, NULL, "gpio_117", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_AC_RST, 118, - "eac_ac_rst", "eac_bt_din", NULL, "gpio_118", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_AC_SCLK, 113, - "eac_ac_sclk", "mcbsp2_clkx", NULL, "gpio_113", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(EAC_BT_DIN, 73, - "eac_bt_din", NULL, NULL, "gpio_73", - NULL, NULL, "etk_d9", NULL), - _OMAP2420_MUXENTRY(EAC_BT_DOUT, 74, - "eac_bt_dout", NULL, "sti_clk", "gpio_74", - NULL, NULL, "etk_d8", NULL), - _OMAP2420_MUXENTRY(EAC_BT_FS, 72, - "eac_bt_fs", NULL, NULL, "gpio_72", - NULL, NULL, "etk_d10", NULL), - _OMAP2420_MUXENTRY(EAC_BT_SCLK, 71, - "eac_bt_sclk", NULL, NULL, "gpio_71", - NULL, NULL, "etk_d11", NULL), - _OMAP2420_MUXENTRY(GPIO_119, 119, - "gpio_119", NULL, "sti_din", "gpio_119", - NULL, "sys_boot0", "etk_d12", NULL), - _OMAP2420_MUXENTRY(GPIO_120, 120, - "gpio_120", NULL, "sti_dout", "gpio_120", - "cam_d9", "sys_boot1", "etk_d13", NULL), - _OMAP2420_MUXENTRY(GPIO_121, 121, - "gpio_121", NULL, NULL, "gpio_121", - "jtag_emu2", "sys_boot2", "etk_d14", NULL), - _OMAP2420_MUXENTRY(GPIO_122, 122, - "gpio_122", NULL, NULL, "gpio_122", - "jtag_emu3", "sys_boot3", "etk_d15", NULL), - _OMAP2420_MUXENTRY(GPIO_124, 124, - "gpio_124", NULL, NULL, "gpio_124", - NULL, "sys_boot5", NULL, NULL), - _OMAP2420_MUXENTRY(GPIO_125, 125, - "gpio_125", "sys_jtagsel1", "sys_jtagsel2", "gpio_125", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPIO_36, 36, - "gpio_36", NULL, NULL, "gpio_36", - NULL, "sys_boot4", NULL, NULL), - _OMAP2420_MUXENTRY(GPIO_62, 62, - "gpio_62", "uart1_rx", "usb1_dat", "gpio_62", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPIO_6, 6, - "gpio_6", "tv_detpulse", NULL, "gpio_6", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A10, 3, - "gpmc_a10", NULL, "sys_ndmareq5", "gpio_3", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A1, 12, - "gpmc_a1", "dss_data18", NULL, "gpio_12", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A2, 11, - "gpmc_a2", "dss_data19", NULL, "gpio_11", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A3, 10, - "gpmc_a3", "dss_data20", NULL, "gpio_10", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A4, 9, - "gpmc_a4", "dss_data21", NULL, "gpio_9", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A5, 8, - "gpmc_a5", "dss_data22", NULL, "gpio_8", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A6, 7, - "gpmc_a6", "dss_data23", NULL, "gpio_7", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A7, 6, - "gpmc_a7", NULL, "sys_ndmareq2", "gpio_6", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A8, 5, - "gpmc_a8", NULL, "sys_ndmareq3", "gpio_5", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_A9, 4, - "gpmc_a9", NULL, "sys_ndmareq4", "gpio_4", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_CLK, 21, - "gpmc_clk", NULL, NULL, "gpio_21", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D10, 18, - "gpmc_d10", "ssi2_rdy_rx", NULL, "gpio_18", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D11, 17, - "gpmc_d11", "ssi2_flag_rx", NULL, "gpio_17", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D12, 16, - "gpmc_d12", "ssi2_dat_rx", NULL, "gpio_16", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D13, 15, - "gpmc_d13", "ssi2_rdy_tx", NULL, "gpio_15", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D14, 14, - "gpmc_d14", "ssi2_flag_tx", NULL, "gpio_14", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D15, 13, - "gpmc_d15", "ssi2_dat_tx", NULL, "gpio_13", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D8, 20, - "gpmc_d8", NULL, NULL, "gpio_20", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_D9, 19, - "gpmc_d9", "ssi2_wake", NULL, "gpio_19", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NBE0, 29, - "gpmc_nbe0", NULL, NULL, "gpio_29", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NBE1, 30, - "gpmc_nbe1", NULL, NULL, "gpio_30", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS1, 22, - "gpmc_ncs1", NULL, NULL, "gpio_22", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS2, 23, - "gpmc_ncs2", NULL, NULL, "gpio_23", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS3, 24, - "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS4, 25, - "gpmc_ncs4", NULL, NULL, "gpio_25", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS5, 26, - "gpmc_ncs5", NULL, NULL, "gpio_26", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS6, 27, - "gpmc_ncs6", NULL, NULL, "gpio_27", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NCS7, 28, - "gpmc_ncs7", "gpmc_io_dir", "gpio_28", NULL, - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_NWP, 31, - "gpmc_nwp", NULL, NULL, "gpio_31", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_WAIT1, 33, - "gpmc_wait1", NULL, NULL, "gpio_33", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_WAIT2, 34, - "gpmc_wait2", NULL, NULL, "gpio_34", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(GPMC_WAIT3, 35, - "gpmc_wait3", NULL, NULL, "gpio_35", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(HDQ_SIO, 101, - "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(I2C2_SCL, 99, - "i2c2_scl", NULL, "gpt9_pwm_evt", "gpio_99", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(I2C2_SDA, 100, - "i2c2_sda", NULL, "spi2_ncs1", "gpio_100", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(JTAG_EMU0, 127, - "jtag_emu0", NULL, NULL, "gpio_127", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(JTAG_EMU1, 126, - "jtag_emu1", NULL, NULL, "gpio_126", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP1_CLKR, 92, - "mcbsp1_clkr", "ssi2_dat_tx", "vlynq_tx1", "gpio_92", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP1_CLKX, 98, - "mcbsp1_clkx", "ssi2_wake", "vlynq_nla", "gpio_98", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP1_DR, 95, - "mcbsp1_dr", "ssi2_dat_rx", "vlynq_rx1", "gpio_95", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP1_DX, 94, - "mcbsp1_dx", "ssi2_rdy_tx", "vlynq_clk", "gpio_94", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP1_FSR, 93, - "mcbsp1_fsr", "ssi2_flag_tx", "vlynq_tx0", "gpio_93", - "spi2_ncs1", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP1_FSX, 97, - "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP2_CLKX, 12, - "mcbsp2_clkx", NULL, "dss_data23", "gpio_12", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP2_DR, 11, - "mcbsp2_dr", NULL, "dss_data22", "gpio_11", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MCBSP_CLKS, 96, - "mcbsp_clks", "ssi2_flag_rx", "vlynq_rx0", "gpio_96", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_CLKI, 59, - "sdmmc_clki", "ms_clki", NULL, "gpio_59", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_CLKO, 0, - "sdmmc_clko", "ms_clko", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_CMD_DIR, 8, - "sdmmc_cmd_dir", NULL, NULL, "gpio_8", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_CMD, 0, - "sdmmc_cmd", "ms_bs", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT_DIR0, 7, - "sdmmc_dat_dir0", "ms_dat0_dir", NULL, "gpio_7", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT0, 0, - "sdmmc_dat0", "ms_dat0", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT_DIR1, 78, - "sdmmc_dat_dir1", "ms_datu_dir", "uart2_rts", "gpio_78", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT1, 75, - "sdmmc_dat1", "ms_dat1", NULL, "gpio_75", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT_DIR2, 79, - "sdmmc_dat_dir2", "ms_datu_dir", "uart2_tx", "gpio_79", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT2, 76, - "sdmmc_dat2", "ms_dat2", "uart2_cts", "gpio_76", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT_DIR3, 80, - "sdmmc_dat_dir3", "ms_datu_dir", "uart2_rx", "gpio_80", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(MMC_DAT3, 77, - "sdmmc_dat3", "ms_dat3", NULL, "gpio_77", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SDRC_A12, 2, - "sdrc_a12", NULL, NULL, "gpio_2", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SDRC_A13, 1, - "sdrc_a13", NULL, NULL, "gpio_1", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SDRC_A14, 0, - "sdrc_a14", NULL, NULL, "gpio_0", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SDRC_CKE1, 38, - "sdrc_cke1", NULL, NULL, "gpio_38", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SDRC_NCS1, 37, - "sdrc_ncs1", NULL, NULL, "gpio_37", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_CLK, 81, - "spi1_clk", NULL, NULL, "gpio_81", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_NCS0, 84, - "spi1_ncs0", NULL, NULL, "gpio_84", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_NCS1, 85, - "spi1_ncs1", NULL, NULL, "gpio_85", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_NCS2, 86, - "spi1_ncs2", NULL, NULL, "gpio_86", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_NCS3, 87, - "spi1_ncs3", NULL, NULL, "gpio_87", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_SIMO, 82, - "spi1_simo", NULL, NULL, "gpio_82", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI1_SOMI, 83, - "spi1_somi", NULL, NULL, "gpio_83", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI2_CLK, 88, - "spi2_clk", NULL, NULL, "gpio_88", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI2_NCS0, 91, - "spi2_ncs0", "gpt12_pwm_evt", NULL, "gpio_91", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI2_SIMO, 89, - "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SPI2_SOMI, 90, - "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_DAT_RX, 63, - "ssi1_dat_rx", "eac_md_sclk", NULL, "gpio_63", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_DAT_TX, 59, - "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_FLAG_RX, 64, - "ssi1_flag_rx", "eac_md_din", NULL, "gpio_64", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_FLAG_TX, 25, - "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_25", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_RDY_RX, 65, - "ssi1_rdy_rx", "eac_md_dout", NULL, "gpio_65", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_RDY_TX, 61, - "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SSI1_WAKE, 66, - "ssi1_wake", "eac_md_fs", NULL, "gpio_66", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SYS_CLKOUT, 123, - "sys_clkout", NULL, NULL, "gpio_123", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SYS_CLKREQ, 52, - "sys_clkreq", NULL, NULL, "gpio_52", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(SYS_NIRQ, 60, - "sys_nirq", NULL, NULL, "gpio_60", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART1_CTS, 32, - "uart1_cts", NULL, "dss_data18", "gpio_32", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART1_RTS, 8, - "uart1_rts", NULL, "dss_data19", "gpio_8", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART1_RX, 10, - "uart1_rx", NULL, "dss_data21", "gpio_10", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART1_TX, 9, - "uart1_tx", NULL, "dss_data20", "gpio_9", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART2_CTS, 67, - "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART2_RTS, 68, - "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART2_RX, 70, - "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART2_TX, 69, - "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART3_CTS_RCTX, 102, - "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART3_RTS_SD, 103, - "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART3_RX_IRRX, 105, - "uart3_rx_irrx", NULL, NULL, "gpio_105", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(UART3_TX_IRTX, 104, - "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_DAT, 112, - "usb0_dat", "uart3_rx_irrx", "uart2_rx", "gpio_112", - "uart2_tx", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_PUEN, 106, - "usb0_puen", "mcbsp2_dx", NULL, "gpio_106", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_RCV, 109, - "usb0_rcv", "mcbsp2_fsx", NULL, "gpio_109", - "uart2_cts", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_SE0, 111, - "usb0_se0", "uart3_tx_irtx", "uart2_tx", "gpio_111", - "uart2_rx", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_TXEN, 110, - "usb0_txen", "uart3_cts_rctx", "uart2_cts", "gpio_110", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_VM, 108, - "usb0_vm", "mcbsp2_clkx", NULL, "gpio_108", - "uart2_rx", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(USB0_VP, 107, - "usb0_vp", "mcbsp2_dr", NULL, "gpio_107", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(VLYNQ_CLK, 13, - "vlynq_clk", "usb2_se0", "sys_ndmareq0", "gpio_13", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(VLYNQ_NLA, 58, - "vlynq_nla", NULL, NULL, "gpio_58", - "cam_d6", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(VLYNQ_RX0, 15, - "vlynq_rx0", "usb2_tllse0", NULL, "gpio_15", - "cam_d7", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(VLYNQ_RX1, 14, - "vlynq_rx1", "usb2_rcv", "sys_ndmareq1", "gpio_14", - "cam_d8", NULL, NULL, NULL), - _OMAP2420_MUXENTRY(VLYNQ_TX0, 17, - "vlynq_tx0", "usb2_txen", NULL, "gpio_17", - NULL, NULL, NULL, NULL), - _OMAP2420_MUXENTRY(VLYNQ_TX1, 16, - "vlynq_tx1", "usb2_dat", "sys_clkout2", "gpio_16", - NULL, NULL, NULL, NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -/* - * Balls for 447-pin POP package - */ -#ifdef CONFIG_DEBUG_FS -static struct omap_ball __initdata omap2420_pop_ball[] = { - _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL), - _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL), - _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL), - _OMAP2420_BALLENTRY(CAM_D3, "ab3", NULL), - _OMAP2420_BALLENTRY(CAM_D4, "v2", NULL), - _OMAP2420_BALLENTRY(CAM_D5, "ad3", NULL), - _OMAP2420_BALLENTRY(CAM_D6, "aa4", NULL), - _OMAP2420_BALLENTRY(CAM_D7, "ab4", NULL), - _OMAP2420_BALLENTRY(CAM_D8, "ac6", NULL), - _OMAP2420_BALLENTRY(CAM_D9, "ac7", NULL), - _OMAP2420_BALLENTRY(CAM_HS, "v4", NULL), - _OMAP2420_BALLENTRY(CAM_LCLK, "ad6", NULL), - _OMAP2420_BALLENTRY(CAM_VS, "p7", NULL), - _OMAP2420_BALLENTRY(CAM_XCLK, "w4", NULL), - _OMAP2420_BALLENTRY(DSS_ACBIAS, "ae8", NULL), - _OMAP2420_BALLENTRY(DSS_DATA10, "ac12", NULL), - _OMAP2420_BALLENTRY(DSS_DATA11, "ae11", NULL), - _OMAP2420_BALLENTRY(DSS_DATA12, "ae13", NULL), - _OMAP2420_BALLENTRY(DSS_DATA13, "ad13", NULL), - _OMAP2420_BALLENTRY(DSS_DATA14, "ac13", NULL), - _OMAP2420_BALLENTRY(DSS_DATA15, "y12", NULL), - _OMAP2420_BALLENTRY(DSS_DATA16, "ad14", NULL), - _OMAP2420_BALLENTRY(DSS_DATA17, "y13", NULL), - _OMAP2420_BALLENTRY(DSS_DATA8, "ad11", NULL), - _OMAP2420_BALLENTRY(DSS_DATA9, "ad12", NULL), - _OMAP2420_BALLENTRY(EAC_AC_DIN, "ad19", NULL), - _OMAP2420_BALLENTRY(EAC_AC_DOUT, "af22", NULL), - _OMAP2420_BALLENTRY(EAC_AC_FS, "ad16", NULL), - _OMAP2420_BALLENTRY(EAC_AC_MCLK, "y17", NULL), - _OMAP2420_BALLENTRY(EAC_AC_RST, "ae22", NULL), - _OMAP2420_BALLENTRY(EAC_AC_SCLK, "ac18", NULL), - _OMAP2420_BALLENTRY(EAC_BT_DIN, "u8", NULL), - _OMAP2420_BALLENTRY(EAC_BT_DOUT, "ad5", NULL), - _OMAP2420_BALLENTRY(EAC_BT_FS, "w7", NULL), - _OMAP2420_BALLENTRY(EAC_BT_SCLK, "ad4", NULL), - _OMAP2420_BALLENTRY(GPIO_119, "af6", NULL), - _OMAP2420_BALLENTRY(GPIO_120, "af4", NULL), - _OMAP2420_BALLENTRY(GPIO_121, "ae6", NULL), - _OMAP2420_BALLENTRY(GPIO_122, "w3", NULL), - _OMAP2420_BALLENTRY(GPIO_124, "y19", NULL), - _OMAP2420_BALLENTRY(GPIO_125, "ae24", NULL), - _OMAP2420_BALLENTRY(GPIO_36, "y18", NULL), - _OMAP2420_BALLENTRY(GPIO_6, "d6", NULL), - _OMAP2420_BALLENTRY(GPIO_62, "ad18", NULL), - _OMAP2420_BALLENTRY(GPMC_A1, "m8", NULL), - _OMAP2420_BALLENTRY(GPMC_A10, "d5", NULL), - _OMAP2420_BALLENTRY(GPMC_A2, "w9", NULL), - _OMAP2420_BALLENTRY(GPMC_A3, "af10", NULL), - _OMAP2420_BALLENTRY(GPMC_A4, "w8", NULL), - _OMAP2420_BALLENTRY(GPMC_A5, "ae16", NULL), - _OMAP2420_BALLENTRY(GPMC_A6, "af9", NULL), - _OMAP2420_BALLENTRY(GPMC_A7, "e4", NULL), - _OMAP2420_BALLENTRY(GPMC_A8, "j7", NULL), - _OMAP2420_BALLENTRY(GPMC_A9, "ae18", NULL), - _OMAP2420_BALLENTRY(GPMC_CLK, "p1", "l1"), - _OMAP2420_BALLENTRY(GPMC_D10, "t1", "n1"), - _OMAP2420_BALLENTRY(GPMC_D11, "u2", "p2"), - _OMAP2420_BALLENTRY(GPMC_D12, "u1", "p1"), - _OMAP2420_BALLENTRY(GPMC_D13, "p2", "m1"), - _OMAP2420_BALLENTRY(GPMC_D14, "h2", "j2"), - _OMAP2420_BALLENTRY(GPMC_D15, "h1", "k2"), - _OMAP2420_BALLENTRY(GPMC_D8, "v1", "r1"), - _OMAP2420_BALLENTRY(GPMC_D9, "y1", "t1"), - _OMAP2420_BALLENTRY(GPMC_NBE0, "af12", "aa10"), - _OMAP2420_BALLENTRY(GPMC_NBE1, "u3", NULL), - _OMAP2420_BALLENTRY(GPMC_NCS1, "af14", "w1"), - _OMAP2420_BALLENTRY(GPMC_NCS2, "g4", NULL), - _OMAP2420_BALLENTRY(GPMC_NCS3, "t8", NULL), - _OMAP2420_BALLENTRY(GPMC_NCS4, "h8", NULL), - _OMAP2420_BALLENTRY(GPMC_NCS5, "k3", NULL), - _OMAP2420_BALLENTRY(GPMC_NCS6, "m7", NULL), - _OMAP2420_BALLENTRY(GPMC_NCS7, "p3", NULL), - _OMAP2420_BALLENTRY(GPMC_NWP, "ae15", "y5"), - _OMAP2420_BALLENTRY(GPMC_WAIT1, "ae20", "y8"), - _OMAP2420_BALLENTRY(GPMC_WAIT2, "n2", NULL), - _OMAP2420_BALLENTRY(GPMC_WAIT3, "t4", NULL), - _OMAP2420_BALLENTRY(HDQ_SIO, "t23", NULL), - _OMAP2420_BALLENTRY(I2C2_SCL, "l2", NULL), - _OMAP2420_BALLENTRY(I2C2_SDA, "k19", NULL), - _OMAP2420_BALLENTRY(JTAG_EMU0, "n24", NULL), - _OMAP2420_BALLENTRY(JTAG_EMU1, "ac22", NULL), - _OMAP2420_BALLENTRY(MCBSP1_CLKR, "y24", NULL), - _OMAP2420_BALLENTRY(MCBSP1_CLKX, "t19", NULL), - _OMAP2420_BALLENTRY(MCBSP1_DR, "u23", NULL), - _OMAP2420_BALLENTRY(MCBSP1_DX, "r24", NULL), - _OMAP2420_BALLENTRY(MCBSP1_FSR, "r20", NULL), - _OMAP2420_BALLENTRY(MCBSP1_FSX, "r23", NULL), - _OMAP2420_BALLENTRY(MCBSP2_CLKX, "t24", NULL), - _OMAP2420_BALLENTRY(MCBSP2_DR, "p20", NULL), - _OMAP2420_BALLENTRY(MCBSP_CLKS, "p23", NULL), - _OMAP2420_BALLENTRY(MMC_CLKI, "c23", NULL), - _OMAP2420_BALLENTRY(MMC_CLKO, "h23", NULL), - _OMAP2420_BALLENTRY(MMC_CMD, "j23", NULL), - _OMAP2420_BALLENTRY(MMC_CMD_DIR, "j24", NULL), - _OMAP2420_BALLENTRY(MMC_DAT0, "h17", NULL), - _OMAP2420_BALLENTRY(MMC_DAT_DIR0, "f23", NULL), - _OMAP2420_BALLENTRY(MMC_DAT1, "g19", NULL), - _OMAP2420_BALLENTRY(MMC_DAT_DIR1, "d23", NULL), - _OMAP2420_BALLENTRY(MMC_DAT2, "h20", NULL), - _OMAP2420_BALLENTRY(MMC_DAT_DIR2, "g23", NULL), - _OMAP2420_BALLENTRY(MMC_DAT3, "d24", NULL), - _OMAP2420_BALLENTRY(MMC_DAT_DIR3, "e23", NULL), - _OMAP2420_BALLENTRY(SDRC_A12, "w26", "r21"), - _OMAP2420_BALLENTRY(SDRC_A13, "w25", "aa15"), - _OMAP2420_BALLENTRY(SDRC_A14, "aa26", "y12"), - _OMAP2420_BALLENTRY(SDRC_CKE1, "ae25", "y13"), - _OMAP2420_BALLENTRY(SDRC_NCS1, "y25", "t20"), - _OMAP2420_BALLENTRY(SPI1_CLK, "y23", NULL), - _OMAP2420_BALLENTRY(SPI1_NCS0, "w24", NULL), - _OMAP2420_BALLENTRY(SPI1_NCS1, "w23", NULL), - _OMAP2420_BALLENTRY(SPI1_NCS2, "v23", NULL), - _OMAP2420_BALLENTRY(SPI1_NCS3, "u20", NULL), - _OMAP2420_BALLENTRY(SPI1_SIMO, "h10", NULL), - _OMAP2420_BALLENTRY(SPI1_SOMI, "v19", NULL), - _OMAP2420_BALLENTRY(SPI2_CLK, "v24", NULL), - _OMAP2420_BALLENTRY(SPI2_NCS0, "aa24", NULL), - _OMAP2420_BALLENTRY(SPI2_SIMO, "u24", NULL), - _OMAP2420_BALLENTRY(SPI2_SOMI, "v25", NULL), - _OMAP2420_BALLENTRY(SSI1_DAT_RX, "w15", NULL), - _OMAP2420_BALLENTRY(SSI1_DAT_TX, "w13", NULL), - _OMAP2420_BALLENTRY(SSI1_FLAG_RX, "af11", NULL), - _OMAP2420_BALLENTRY(SSI1_FLAG_TX, "ac15", NULL), - _OMAP2420_BALLENTRY(SSI1_RDY_RX, "ac16", NULL), - _OMAP2420_BALLENTRY(SSI1_RDY_TX, "af15", NULL), - _OMAP2420_BALLENTRY(SSI1_WAKE, "ad15", NULL), - _OMAP2420_BALLENTRY(SYS_CLKOUT, "ae19", NULL), - _OMAP2420_BALLENTRY(SYS_CLKREQ, "ad20", NULL), - _OMAP2420_BALLENTRY(SYS_NIRQ, "y20", NULL), - _OMAP2420_BALLENTRY(UART1_CTS, "g20", NULL), - _OMAP2420_BALLENTRY(UART1_RTS, "k20", NULL), - _OMAP2420_BALLENTRY(UART1_RX, "t20", NULL), - _OMAP2420_BALLENTRY(UART1_TX, "h12", NULL), - _OMAP2420_BALLENTRY(UART2_CTS, "ac24", NULL), - _OMAP2420_BALLENTRY(UART2_RTS, "w20", NULL), - _OMAP2420_BALLENTRY(UART2_RX, "ad24", NULL), - _OMAP2420_BALLENTRY(UART2_TX, "ab24", NULL), - _OMAP2420_BALLENTRY(UART3_CTS_RCTX, "k24", NULL), - _OMAP2420_BALLENTRY(UART3_RTS_SD, "m20", NULL), - _OMAP2420_BALLENTRY(UART3_RX_IRRX, "h24", NULL), - _OMAP2420_BALLENTRY(UART3_TX_IRTX, "g24", NULL), - _OMAP2420_BALLENTRY(USB0_DAT, "j25", NULL), - _OMAP2420_BALLENTRY(USB0_PUEN, "l23", NULL), - _OMAP2420_BALLENTRY(USB0_RCV, "k23", NULL), - _OMAP2420_BALLENTRY(USB0_SE0, "l24", NULL), - _OMAP2420_BALLENTRY(USB0_TXEN, "m24", NULL), - _OMAP2420_BALLENTRY(USB0_VM, "n23", NULL), - _OMAP2420_BALLENTRY(USB0_VP, "m23", NULL), - _OMAP2420_BALLENTRY(VLYNQ_CLK, "w12", NULL), - _OMAP2420_BALLENTRY(VLYNQ_NLA, "ae10", NULL), - _OMAP2420_BALLENTRY(VLYNQ_RX0, "ad7", NULL), - _OMAP2420_BALLENTRY(VLYNQ_RX1, "w10", NULL), - _OMAP2420_BALLENTRY(VLYNQ_TX0, "y15", NULL), - _OMAP2420_BALLENTRY(VLYNQ_TX1, "w14", NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap2420_pop_ball NULL -#endif - -int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags) -{ - struct omap_ball *package_balls = NULL; - - switch (flags & OMAP_PACKAGE_MASK) { - case OMAP_PACKAGE_ZAC: - package_balls = omap2420_pop_ball; - break; - case OMAP_PACKAGE_ZAF: - /* REVISIT: Please add data */ - default: - pr_warning("%s: No ball data available for omap2420 package\n", - __func__); - } - - return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3, - OMAP2420_CONTROL_PADCONF_MUX_PBASE, - OMAP2420_CONTROL_PADCONF_MUX_SIZE, - omap2420_muxmodes, NULL, board_subset, - package_balls); -} diff --git a/arch/arm/mach-omap2/mux2420.h b/arch/arm/mach-omap2/mux2420.h deleted file mode 100644 index 0f555aa..0000000 --- a/arch/arm/mach-omap2/mux2420.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright (C) 2009 Nokia - * Copyright (C) 2009 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define OMAP2420_CONTROL_PADCONF_MUX_PBASE 0x48000030LU - -#define OMAP2420_MUX(mode0, mux_value) \ -{ \ - .reg_offset = (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET), \ - .value = (mux_value), \ -} - -/* - * OMAP2420 CONTROL_PADCONF* register offsets for pin-muxing - * - * Extracted from the TRM. Add 0x48000030 to these values to get the - * absolute addresses. The name in the macro is the mode-0 name of - * the pin. NOTE: These registers are 8-bits wide. - */ -#define OMAP2420_CONTROL_PADCONF_SDRC_A14_OFFSET 0x000 -#define OMAP2420_CONTROL_PADCONF_SDRC_A13_OFFSET 0x001 -#define OMAP2420_CONTROL_PADCONF_SDRC_A12_OFFSET 0x002 -#define OMAP2420_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x003 -#define OMAP2420_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x004 -#define OMAP2420_CONTROL_PADCONF_SDRC_A11_OFFSET 0x005 -#define OMAP2420_CONTROL_PADCONF_SDRC_A10_OFFSET 0x006 -#define OMAP2420_CONTROL_PADCONF_SDRC_A9_OFFSET 0x007 -#define OMAP2420_CONTROL_PADCONF_SDRC_A8_OFFSET 0x008 -#define OMAP2420_CONTROL_PADCONF_SDRC_A7_OFFSET 0x009 -#define OMAP2420_CONTROL_PADCONF_SDRC_A6_OFFSET 0x00a -#define OMAP2420_CONTROL_PADCONF_SDRC_A5_OFFSET 0x00b -#define OMAP2420_CONTROL_PADCONF_SDRC_A4_OFFSET 0x00c -#define OMAP2420_CONTROL_PADCONF_SDRC_A3_OFFSET 0x00d -#define OMAP2420_CONTROL_PADCONF_SDRC_A2_OFFSET 0x00e -#define OMAP2420_CONTROL_PADCONF_SDRC_A1_OFFSET 0x00f -#define OMAP2420_CONTROL_PADCONF_SDRC_A0_OFFSET 0x010 -#define OMAP2420_CONTROL_PADCONF_SDRC_D31_OFFSET 0x021 -#define OMAP2420_CONTROL_PADCONF_SDRC_D30_OFFSET 0x022 -#define OMAP2420_CONTROL_PADCONF_SDRC_D29_OFFSET 0x023 -#define OMAP2420_CONTROL_PADCONF_SDRC_D28_OFFSET 0x024 -#define OMAP2420_CONTROL_PADCONF_SDRC_D27_OFFSET 0x025 -#define OMAP2420_CONTROL_PADCONF_SDRC_D26_OFFSET 0x026 -#define OMAP2420_CONTROL_PADCONF_SDRC_D25_OFFSET 0x027 -#define OMAP2420_CONTROL_PADCONF_SDRC_D24_OFFSET 0x028 -#define OMAP2420_CONTROL_PADCONF_SDRC_D23_OFFSET 0x029 -#define OMAP2420_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02a -#define OMAP2420_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02b -#define OMAP2420_CONTROL_PADCONF_SDRC_D20_OFFSET 0x02c -#define OMAP2420_CONTROL_PADCONF_SDRC_D19_OFFSET 0x02d -#define OMAP2420_CONTROL_PADCONF_SDRC_D18_OFFSET 0x02e -#define OMAP2420_CONTROL_PADCONF_SDRC_D17_OFFSET 0x02f -#define OMAP2420_CONTROL_PADCONF_SDRC_D16_OFFSET 0x030 -#define OMAP2420_CONTROL_PADCONF_SDRC_D15_OFFSET 0x031 -#define OMAP2420_CONTROL_PADCONF_SDRC_D14_OFFSET 0x032 -#define OMAP2420_CONTROL_PADCONF_SDRC_D13_OFFSET 0x033 -#define OMAP2420_CONTROL_PADCONF_SDRC_D12_OFFSET 0x034 -#define OMAP2420_CONTROL_PADCONF_SDRC_D11_OFFSET 0x035 -#define OMAP2420_CONTROL_PADCONF_SDRC_D10_OFFSET 0x036 -#define OMAP2420_CONTROL_PADCONF_SDRC_D9_OFFSET 0x037 -#define OMAP2420_CONTROL_PADCONF_SDRC_D8_OFFSET 0x038 -#define OMAP2420_CONTROL_PADCONF_SDRC_D7_OFFSET 0x039 -#define OMAP2420_CONTROL_PADCONF_SDRC_D6_OFFSET 0x03a -#define OMAP2420_CONTROL_PADCONF_SDRC_D5_OFFSET 0x03b -#define OMAP2420_CONTROL_PADCONF_SDRC_D4_OFFSET 0x03c -#define OMAP2420_CONTROL_PADCONF_SDRC_D3_OFFSET 0x03d -#define OMAP2420_CONTROL_PADCONF_SDRC_D2_OFFSET 0x03e -#define OMAP2420_CONTROL_PADCONF_SDRC_D1_OFFSET 0x03f -#define OMAP2420_CONTROL_PADCONF_SDRC_D0_OFFSET 0x040 -#define OMAP2420_CONTROL_PADCONF_GPMC_A10_OFFSET 0x041 -#define OMAP2420_CONTROL_PADCONF_GPMC_A9_OFFSET 0x042 -#define OMAP2420_CONTROL_PADCONF_GPMC_A8_OFFSET 0x043 -#define OMAP2420_CONTROL_PADCONF_GPMC_A7_OFFSET 0x044 -#define OMAP2420_CONTROL_PADCONF_GPMC_A6_OFFSET 0x045 -#define OMAP2420_CONTROL_PADCONF_GPMC_A5_OFFSET 0x046 -#define OMAP2420_CONTROL_PADCONF_GPMC_A4_OFFSET 0x047 -#define OMAP2420_CONTROL_PADCONF_GPMC_A3_OFFSET 0x048 -#define OMAP2420_CONTROL_PADCONF_GPMC_A2_OFFSET 0x049 -#define OMAP2420_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a -#define OMAP2420_CONTROL_PADCONF_GPMC_D15_OFFSET 0x04b -#define OMAP2420_CONTROL_PADCONF_GPMC_D14_OFFSET 0x04c -#define OMAP2420_CONTROL_PADCONF_GPMC_D13_OFFSET 0x04d -#define OMAP2420_CONTROL_PADCONF_GPMC_D12_OFFSET 0x04e -#define OMAP2420_CONTROL_PADCONF_GPMC_D11_OFFSET 0x04f -#define OMAP2420_CONTROL_PADCONF_GPMC_D10_OFFSET 0x050 -#define OMAP2420_CONTROL_PADCONF_GPMC_D9_OFFSET 0x051 -#define OMAP2420_CONTROL_PADCONF_GPMC_D8_OFFSET 0x052 -#define OMAP2420_CONTROL_PADCONF_GPMC_D7_OFFSET 0x053 -#define OMAP2420_CONTROL_PADCONF_GPMC_D6_OFFSET 0x054 -#define OMAP2420_CONTROL_PADCONF_GPMC_D5_OFFSET 0x055 -#define OMAP2420_CONTROL_PADCONF_GPMC_D4_OFFSET 0x056 -#define OMAP2420_CONTROL_PADCONF_GPMC_D3_OFFSET 0x057 -#define OMAP2420_CONTROL_PADCONF_GPMC_D2_OFFSET 0x058 -#define OMAP2420_CONTROL_PADCONF_GPMC_D1_OFFSET 0x059 -#define OMAP2420_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05a -#define OMAP2420_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x05b -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x05c -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x05d -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x05e -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x05f -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x060 -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x061 -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x062 -#define OMAP2420_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x063 -#define OMAP2420_CONTROL_PADCONF_GPMC_NALE_ALE_OFFSET 0x064 -#define OMAP2420_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x065 -#define OMAP2420_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x066 -#define OMAP2420_CONTROL_PADCONF_GPMC_NBE0_OFFSET 0x067 -#define OMAP2420_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x068 -#define OMAP2420_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x069 -#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x06a -#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x06b -#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x06c -#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x06d -#define OMAP2420_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x06e -#define OMAP2420_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x06f -#define OMAP2420_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x070 -#define OMAP2420_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x071 -#define OMAP2420_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x072 -#define OMAP2420_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x073 -#define OMAP2420_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x074 -#define OMAP2420_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x075 -#define OMAP2420_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x076 -#define OMAP2420_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x077 -#define OMAP2420_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x078 -#define OMAP2420_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x079 -#define OMAP2420_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x07a -#define OMAP2420_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x07f -#define OMAP2420_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x080 -#define OMAP2420_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x081 -#define OMAP2420_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x082 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x083 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x084 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x085 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x086 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x087 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x088 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x089 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x08a -#define OMAP2420_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x08b -#define OMAP2420_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x08c -#define OMAP2420_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x08d -#define OMAP2420_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x08e -#define OMAP2420_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x08f -#define OMAP2420_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x090 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x091 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x092 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x093 -#define OMAP2420_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x094 -#define OMAP2420_CONTROL_PADCONF_UART1_CTS_OFFSET 0x095 -#define OMAP2420_CONTROL_PADCONF_UART1_RTS_OFFSET 0x096 -#define OMAP2420_CONTROL_PADCONF_UART1_TX_OFFSET 0x097 -#define OMAP2420_CONTROL_PADCONF_UART1_RX_OFFSET 0x098 -#define OMAP2420_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x099 -#define OMAP2420_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x09a -#define OMAP2420_CONTROL_PADCONF_DSS_PCL_OFFSET 0x09b -#define OMAP2420_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x09c -#define OMAP2420_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x09d -#define OMAP2420_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x09e -#define OMAP2420_CONTROL_PADCONF_CAM_D9_OFFSET 0x09f -#define OMAP2420_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a0 -#define OMAP2420_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a1 -#define OMAP2420_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a2 -#define OMAP2420_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a3 -#define OMAP2420_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a4 -#define OMAP2420_CONTROL_PADCONF_CAM_D3_OFFSET 0x0a5 -#define OMAP2420_CONTROL_PADCONF_CAM_D2_OFFSET 0x0a6 -#define OMAP2420_CONTROL_PADCONF_CAM_D1_OFFSET 0x0a7 -#define OMAP2420_CONTROL_PADCONF_CAM_D0_OFFSET 0x0a8 -#define OMAP2420_CONTROL_PADCONF_CAM_HS_OFFSET 0x0a9 -#define OMAP2420_CONTROL_PADCONF_CAM_VS_OFFSET 0x0aa -#define OMAP2420_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0ab -#define OMAP2420_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0ac -#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0ad -#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0ae -#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0af -#define OMAP2420_CONTROL_PADCONF_GPIO_62_OFFSET 0x0b0 -#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0b1 -#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0b2 -#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0b3 -#define OMAP2420_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0b4 -#define OMAP2420_CONTROL_PADCONF_VLYNQ_CLK_OFFSET 0x0b5 -#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX1_OFFSET 0x0b6 -#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX0_OFFSET 0x0b7 -#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX1_OFFSET 0x0b8 -#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX0_OFFSET 0x0b9 -#define OMAP2420_CONTROL_PADCONF_VLYNQ_NLA_OFFSET 0x0ba -#define OMAP2420_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0bb -#define OMAP2420_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0bc -#define OMAP2420_CONTROL_PADCONF_UART2_TX_OFFSET 0x0bd -#define OMAP2420_CONTROL_PADCONF_UART2_RX_OFFSET 0x0be -#define OMAP2420_CONTROL_PADCONF_EAC_BT_SCLK_OFFSET 0x0bf -#define OMAP2420_CONTROL_PADCONF_EAC_BT_FS_OFFSET 0x0c0 -#define OMAP2420_CONTROL_PADCONF_EAC_BT_DIN_OFFSET 0x0c1 -#define OMAP2420_CONTROL_PADCONF_EAC_BT_DOUT_OFFSET 0x0c2 -#define OMAP2420_CONTROL_PADCONF_MMC_CLKO_OFFSET 0x0c3 -#define OMAP2420_CONTROL_PADCONF_MMC_CMD_OFFSET 0x0c4 -#define OMAP2420_CONTROL_PADCONF_MMC_DAT0_OFFSET 0x0c5 -#define OMAP2420_CONTROL_PADCONF_MMC_DAT1_OFFSET 0x0c6 -#define OMAP2420_CONTROL_PADCONF_MMC_DAT2_OFFSET 0x0c7 -#define OMAP2420_CONTROL_PADCONF_MMC_DAT3_OFFSET 0x0c8 -#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR0_OFFSET 0x0c9 -#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR1_OFFSET 0x0ca -#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR2_OFFSET 0x0cb -#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR3_OFFSET 0x0cc -#define OMAP2420_CONTROL_PADCONF_MMC_CMD_DIR_OFFSET 0x0cd -#define OMAP2420_CONTROL_PADCONF_MMC_CLKI_OFFSET 0x0ce -#define OMAP2420_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0cf -#define OMAP2420_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0d0 -#define OMAP2420_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0d1 -#define OMAP2420_CONTROL_PADCONF_SPI1_NCS0_OFFSET 0x0d2 -#define OMAP2420_CONTROL_PADCONF_SPI1_NCS1_OFFSET 0x0d3 -#define OMAP2420_CONTROL_PADCONF_SPI1_NCS2_OFFSET 0x0d4 -#define OMAP2420_CONTROL_PADCONF_SPI1_NCS3_OFFSET 0x0d5 -#define OMAP2420_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0d6 -#define OMAP2420_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0d7 -#define OMAP2420_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0d8 -#define OMAP2420_CONTROL_PADCONF_SPI2_NCS0_OFFSET 0x0d9 -#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0da -#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0db -#define OMAP2420_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0dc -#define OMAP2420_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0dd -#define OMAP2420_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0de -#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0df -#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0e0 -#define OMAP2420_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0e1 -#define OMAP2420_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0e2 -#define OMAP2420_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0e3 -#define OMAP2420_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0e4 -#define OMAP2420_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0e5 -#define OMAP2420_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0e6 -#define OMAP2420_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0e7 -#define OMAP2420_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0e8 -#define OMAP2420_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0e9 -#define OMAP2420_CONTROL_PADCONF_TV_CVBS_OFFSET 0x0ea -#define OMAP2420_CONTROL_PADCONF_TV_VREF_OFFSET 0x0eb -#define OMAP2420_CONTROL_PADCONF_TV_RREF_OFFSET 0x0ec -#define OMAP2420_CONTROL_PADCONF_USB0_PUEN_OFFSET 0x0ed -#define OMAP2420_CONTROL_PADCONF_USB0_VP_OFFSET 0x0ee -#define OMAP2420_CONTROL_PADCONF_USB0_VM_OFFSET 0x0ef -#define OMAP2420_CONTROL_PADCONF_USB0_RCV_OFFSET 0x0f0 -#define OMAP2420_CONTROL_PADCONF_USB0_TXEN_OFFSET 0x0f1 -#define OMAP2420_CONTROL_PADCONF_USB0_SE0_OFFSET 0x0f2 -#define OMAP2420_CONTROL_PADCONF_USB0_DAT_OFFSET 0x0f3 -#define OMAP2420_CONTROL_PADCONF_EAC_AC_SCLK_OFFSET 0x0f4 -#define OMAP2420_CONTROL_PADCONF_EAC_AC_FS_OFFSET 0x0f5 -#define OMAP2420_CONTROL_PADCONF_EAC_AC_DIN_OFFSET 0x0f6 -#define OMAP2420_CONTROL_PADCONF_EAC_AC_DOUT_OFFSET 0x0f7 -#define OMAP2420_CONTROL_PADCONF_EAC_AC_MCLK_OFFSET 0x0f8 -#define OMAP2420_CONTROL_PADCONF_EAC_AC_RST_OFFSET 0x0f9 -#define OMAP2420_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x0fa -#define OMAP2420_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x0fb -#define OMAP2420_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x0fc -#define OMAP2420_CONTROL_PADCONF_SYS_NV_OFFSET 0x0fd -#define OMAP2420_CONTROL_PADCONF_GPIO_119_OFFSET 0x0fe -#define OMAP2420_CONTROL_PADCONF_GPIO_120_OFFSET 0x0ff -#define OMAP2420_CONTROL_PADCONF_GPIO_121_OFFSET 0x100 -#define OMAP2420_CONTROL_PADCONF_GPIO_122_OFFSET 0x101 -#define OMAP2420_CONTROL_PADCONF_SYS_32K_OFFSET 0x102 -#define OMAP2420_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x103 -#define OMAP2420_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x104 -#define OMAP2420_CONTROL_PADCONF_GPIO_36_OFFSET 0x105 -#define OMAP2420_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x106 -#define OMAP2420_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x107 -#define OMAP2420_CONTROL_PADCONF_GPIO_6_OFFSET 0x108 -#define OMAP2420_CONTROL_PADCONF_GPIO_124_OFFSET 0x109 -#define OMAP2420_CONTROL_PADCONF_GPIO_125_OFFSET 0x10a -#define OMAP2420_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x10b -#define OMAP2420_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x10c -#define OMAP2420_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x10d -#define OMAP2420_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x10e -#define OMAP2420_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x10f -#define OMAP2420_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x110 -#define OMAP2420_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x111 -#define OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x112 - -#define OMAP2420_CONTROL_PADCONF_MUX_SIZE \ - (OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x1) diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c deleted file mode 100644 index 4185f92..0000000 --- a/arch/arm/mach-omap2/mux2430.c +++ /dev/null @@ -1,793 +0,0 @@ -/* - * Copyright (C) 2010 Nokia - * Copyright (C) 2010 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/module.h> -#include <linux/init.h> - -#include "mux.h" - -#ifdef CONFIG_OMAP_MUX - -#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ -{ \ - .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ - .gpio = (g), \ - .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ -} - -#else - -#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ -{ \ - .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ - .gpio = (g), \ -} - -#endif - -#define _OMAP2430_BALLENTRY(M0, bb, bt) \ -{ \ - .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ - .balls = { bb, bt }, \ -} - -/* - * Superset of all mux modes for omap2430 - */ -static struct omap_mux __initdata omap2430_muxmodes[] = { - _OMAP2430_MUXENTRY(CAM_D0, 133, - "cam_d0", "hw_dbg0", "sti_dout", "gpio_133", - NULL, NULL, "etk_d2", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D10, 146, - "cam_d10", NULL, NULL, "gpio_146", - NULL, NULL, "etk_d12", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D11, 145, - "cam_d11", NULL, NULL, "gpio_145", - NULL, NULL, "etk_d13", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D1, 132, - "cam_d1", "hw_dbg1", "sti_din", "gpio_132", - NULL, NULL, "etk_d3", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D2, 129, - "cam_d2", "hw_dbg2", "mcbsp1_clkx", "gpio_129", - NULL, NULL, "etk_d4", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D3, 128, - "cam_d3", "hw_dbg3", "mcbsp1_dr", "gpio_128", - NULL, NULL, "etk_d5", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D4, 143, - "cam_d4", "hw_dbg4", "mcbsp1_fsr", "gpio_143", - NULL, NULL, "etk_d6", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D5, 112, - "cam_d5", "hw_dbg5", "mcbsp1_clkr", "gpio_112", - NULL, NULL, "etk_d7", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D6, 137, - "cam_d6", "hw_dbg6", NULL, "gpio_137", - NULL, NULL, "etk_d8", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D7, 136, - "cam_d7", "hw_dbg7", NULL, "gpio_136", - NULL, NULL, "etk_d9", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D8, 135, - "cam_d8", "hw_dbg8", NULL, "gpio_135", - NULL, NULL, "etk_d10", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_D9, 134, - "cam_d9", "hw_dbg9", NULL, "gpio_134", - NULL, NULL, "etk_d11", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_HS, 11, - "cam_hs", "hw_dbg10", "mcbsp1_dx", "gpio_11", - NULL, NULL, "etk_d1", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_LCLK, 0, - "cam_lclk", NULL, "mcbsp_clks", NULL, - NULL, NULL, "etk_c1", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_VS, 12, - "cam_vs", "hw_dbg11", "mcbsp1_fsx", "gpio_12", - NULL, NULL, "etk_d0", "safe_mode"), - _OMAP2430_MUXENTRY(CAM_XCLK, 0, - "cam_xclk", NULL, "sti_clk", NULL, - NULL, NULL, "etk_c2", NULL), - _OMAP2430_MUXENTRY(DSS_ACBIAS, 48, - "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA0, 40, - "dss_data0", "uart1_cts", NULL, "gpio_40", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA10, 128, - "dss_data10", "sdi_data1n", NULL, "gpio_128", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA11, 129, - "dss_data11", "sdi_data1p", NULL, "gpio_129", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA12, 130, - "dss_data12", "sdi_data2n", NULL, "gpio_130", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA13, 131, - "dss_data13", "sdi_data2p", NULL, "gpio_131", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA14, 132, - "dss_data14", "sdi_data3n", NULL, "gpio_132", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA15, 133, - "dss_data15", "sdi_data3p", NULL, "gpio_133", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA16, 46, - "dss_data16", NULL, NULL, "gpio_46", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA17, 47, - "dss_data17", NULL, NULL, "gpio_47", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA1, 41, - "dss_data1", "uart1_rts", NULL, "gpio_41", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA2, 42, - "dss_data2", "uart1_tx", NULL, "gpio_42", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA3, 43, - "dss_data3", "uart1_rx", NULL, "gpio_43", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA4, 44, - "dss_data4", "uart3_rx_irrx", NULL, "gpio_44", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA5, 45, - "dss_data5", "uart3_tx_irtx", NULL, "gpio_45", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA6, 144, - "dss_data6", NULL, NULL, "gpio_144", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA7, 147, - "dss_data7", NULL, NULL, "gpio_147", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA8, 38, - "dss_data8", NULL, NULL, "gpio_38", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_DATA9, 39, - "dss_data9", NULL, NULL, "gpio_39", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(DSS_HSYNC, 110, - "dss_hsync", NULL, NULL, "gpio_110", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_113, 113, - "gpio_113", "mcbsp2_clkx", NULL, "gpio_113", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_114, 114, - "gpio_114", "mcbsp2_fsx", NULL, "gpio_114", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_115, 115, - "gpio_115", "mcbsp2_dr", NULL, "gpio_115", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_116, 116, - "gpio_116", "mcbsp2_dx", NULL, "gpio_116", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_128, 128, - "gpio_128", NULL, "sti_din", "gpio_128", - NULL, "sys_boot0", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_129, 129, - "gpio_129", NULL, "sti_dout", "gpio_129", - NULL, "sys_boot1", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_130, 130, - "gpio_130", NULL, NULL, "gpio_130", - "jtag_emu2", "sys_boot2", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_131, 131, - "gpio_131", NULL, NULL, "gpio_131", - "jtag_emu3", "sys_boot3", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_132, 132, - "gpio_132", NULL, NULL, "gpio_132", - NULL, "sys_boot4", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_133, 133, - "gpio_133", NULL, NULL, "gpio_133", - NULL, "sys_boot5", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_134, 134, - "gpio_134", "ccp_datn", NULL, "gpio_134", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_135, 135, - "gpio_135", "ccp_datp", NULL, "gpio_135", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_136, 136, - "gpio_136", "ccp_clkn", NULL, "gpio_136", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_137, 137, - "gpio_137", "ccp_clkp", NULL, "gpio_137", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_138, 138, - "gpio_138", "spi3_clk", NULL, "gpio_138", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_139, 139, - "gpio_139", "spi3_cs0", "sys_ndmareq3", "gpio_139", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_140, 140, - "gpio_140", "spi3_simo", "sys_ndmareq4", "gpio_140", - NULL, NULL, "etk_d14", "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_141, 141, - "gpio_141", "spi3_somi", NULL, "gpio_141", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_142, 142, - "gpio_142", "spi3_cs1", "sys_ndmareq2", "gpio_142", - NULL, NULL, "etk_d15", "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_148, 148, - "gpio_148", "mcbsp5_fsx", NULL, "gpio_148", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_149, 149, - "gpio_149", "mcbsp5_dx", NULL, "gpio_149", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_150, 150, - "gpio_150", "mcbsp5_dr", NULL, "gpio_150", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_151, 151, - "gpio_151", "sys_pwrok", NULL, "gpio_151", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_152, 152, - "gpio_152", "uart1_cts", "sys_ndmareq1", "gpio_152", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_153, 153, - "gpio_153", "uart1_rx", "sys_ndmareq0", "gpio_153", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_154, 154, - "gpio_154", "mcbsp5_clkx", NULL, "gpio_154", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_63, 63, - "gpio_63", "mcbsp4_clkx", NULL, "gpio_63", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_78, 78, - "gpio_78", NULL, "uart2_rts", "gpio_78", - "uart3_rts_sd", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_79, 79, - "gpio_79", "secure_indicator", "uart2_tx", "gpio_79", - "uart3_tx_irtx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_7, 7, - "gpio_7", NULL, "uart2_cts", "gpio_7", - "uart3_cts_rctx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPIO_80, 80, - "gpio_80", NULL, "uart2_rx", "gpio_80", - "uart3_rx_irrx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A10, 3, - "gpmc_a10", NULL, "sys_ndmareq0", "gpio_3", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A1, 31, - "gpmc_a1", NULL, NULL, "gpio_31", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A2, 30, - "gpmc_a2", NULL, NULL, "gpio_30", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A3, 29, - "gpmc_a3", NULL, NULL, "gpio_29", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A4, 49, - "gpmc_a4", NULL, NULL, "gpio_49", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A5, 53, - "gpmc_a5", NULL, NULL, "gpio_53", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A6, 52, - "gpmc_a6", NULL, NULL, "gpio_52", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A7, 6, - "gpmc_a7", NULL, NULL, "gpio_6", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A8, 5, - "gpmc_a8", NULL, NULL, "gpio_5", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_A9, 4, - "gpmc_a9", NULL, "sys_ndmareq1", "gpio_4", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_CLK, 21, - "gpmc_clk", NULL, NULL, "gpio_21", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D10, 18, - "gpmc_d10", NULL, NULL, "gpio_18", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D11, 57, - "gpmc_d11", NULL, NULL, "gpio_57", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D12, 77, - "gpmc_d12", NULL, NULL, "gpio_77", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D13, 76, - "gpmc_d13", NULL, NULL, "gpio_76", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D14, 55, - "gpmc_d14", NULL, NULL, "gpio_55", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D15, 54, - "gpmc_d15", NULL, NULL, "gpio_54", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D8, 20, - "gpmc_d8", NULL, NULL, "gpio_20", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_D9, 19, - "gpmc_d9", NULL, NULL, "gpio_19", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS1, 22, - "gpmc_ncs1", NULL, NULL, "gpio_22", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS2, 23, - "gpmc_ncs2", NULL, NULL, "gpio_23", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS3, 24, - "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS4, 25, - "gpmc_ncs4", NULL, NULL, "gpio_25", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS5, 26, - "gpmc_ncs5", NULL, NULL, "gpio_26", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS6, 27, - "gpmc_ncs6", NULL, NULL, "gpio_27", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_NCS7, 28, - "gpmc_ncs7", "gpmc_io_dir", NULL, "gpio_28", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_WAIT1, 33, - "gpmc_wait1", NULL, NULL, "gpio_33", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_WAIT2, 34, - "gpmc_wait2", NULL, NULL, "gpio_34", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(GPMC_WAIT3, 35, - "gpmc_wait3", NULL, NULL, "gpio_35", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(HDQ_SIO, 101, - "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101", - "uart3_rx_irrx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(I2C1_SCL, 50, - "i2c1_scl", NULL, NULL, "gpio_50", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(I2C1_SDA, 51, - "i2c1_sda", NULL, NULL, "gpio_51", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(I2C2_SCL, 99, - "i2c2_scl", NULL, NULL, "gpio_99", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(I2C2_SDA, 100, - "i2c2_sda", NULL, NULL, "gpio_100", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(JTAG_EMU0, 127, - "jtag_emu0", "secure_indicator", NULL, "gpio_127", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(JTAG_EMU1, 126, - "jtag_emu1", NULL, NULL, "gpio_126", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP1_CLKR, 92, - "mcbsp1_clkr", "ssi2_dat_tx", NULL, "gpio_92", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP1_CLKX, 98, - "mcbsp1_clkx", "ssi2_wake", NULL, "gpio_98", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP1_DR, 95, - "mcbsp1_dr", "ssi2_dat_rx", NULL, "gpio_95", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP1_DX, 94, - "mcbsp1_dx", "ssi2_rdy_tx", NULL, "gpio_94", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP1_FSR, 93, - "mcbsp1_fsr", "ssi2_flag_tx", NULL, "gpio_93", - "spi2_cs1", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP1_FSX, 97, - "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP2_CLKX, 147, - "mcbsp2_clkx", "sdi_clkp", "dss_data23", "gpio_147", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP2_DR, 144, - "mcbsp2_dr", "sdi_clkn", "dss_data22", "gpio_144", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP3_CLKX, 71, - "mcbsp3_clkx", NULL, NULL, "gpio_71", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP3_DR, 73, - "mcbsp3_dr", NULL, NULL, "gpio_73", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP3_DX, 74, - "mcbsp3_dx", NULL, "sti_clk", "gpio_74", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP3_FSX, 72, - "mcbsp3_fsx", NULL, NULL, "gpio_72", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(MCBSP_CLKS, 96, - "mcbsp_clks", "ssi2_flag_rx", NULL, "gpio_96", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC1_CLKO, 0, - "sdmmc1_clko", "ms_clko", NULL, NULL, - NULL, "hw_dbg9", "hw_dbg3", "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC1_CMD, 0, - "sdmmc1_cmd", "ms_bs", NULL, NULL, - NULL, "hw_dbg8", "hw_dbg2", "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC1_DAT0, 0, - "sdmmc1_dat0", "ms_dat0", NULL, NULL, - NULL, "hw_dbg7", "hw_dbg1", "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC1_DAT1, 75, - "sdmmc1_dat1", "ms_dat1", NULL, "gpio_75", - NULL, "hw_dbg6", "hw_dbg0", "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC1_DAT2, 0, - "sdmmc1_dat2", "ms_dat2", NULL, NULL, - NULL, "hw_dbg5", "hw_dbg10", "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC1_DAT3, 0, - "sdmmc1_dat3", "ms_dat3", NULL, NULL, - NULL, "hw_dbg4", "hw_dbg11", "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC2_CLKO, 13, - "sdmmc2_clko", NULL, NULL, "gpio_13", - NULL, "spi3_clk", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC2_CMD, 15, - "sdmmc2_cmd", "usb2_rcv", NULL, "gpio_15", - NULL, "spi3_simo", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC2_DAT0, 16, - "sdmmc2_dat0", "usb2_tllse0", NULL, "gpio_16", - NULL, "spi3_somi", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC2_DAT1, 58, - "sdmmc2_dat1", "usb2_txen", NULL, "gpio_58", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC2_DAT2, 17, - "sdmmc2_dat2", "usb2_dat", NULL, "gpio_17", - NULL, "spi3_cs1", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDMMC2_DAT3, 14, - "sdmmc2_dat3", "usb2_se0", NULL, "gpio_14", - NULL, "spi3_cs0", NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDRC_A12, 2, - "sdrc_a12", NULL, NULL, "gpio_2", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDRC_A13, 1, - "sdrc_a13", NULL, NULL, "gpio_1", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDRC_A14, 0, - "sdrc_a14", NULL, NULL, "gpio_0", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDRC_CKE1, 36, - "sdrc_cke1", NULL, NULL, "gpio_36", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SDRC_NCS1, 37, - "sdrc_ncs1", NULL, NULL, "gpio_37", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_CLK, 81, - "spi1_clk", NULL, NULL, "gpio_81", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_CS0, 84, - "spi1_cs0", NULL, NULL, "gpio_84", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_CS1, 85, - "spi1_cs1", NULL, NULL, "gpio_85", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_CS2, 86, - "spi1_cs2", NULL, NULL, "gpio_86", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_CS3, 87, - "spi1_cs3", "spi2_cs1", NULL, "gpio_87", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_SIMO, 82, - "spi1_simo", NULL, NULL, "gpio_82", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI1_SOMI, 83, - "spi1_somi", NULL, NULL, "gpio_83", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI2_CLK, 88, - "spi2_clk", "gpt9_pwm_evt", NULL, "gpio_88", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI2_CS0, 91, - "spi2_cs0", "gpt12_pwm_evt", NULL, "gpio_91", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI2_SIMO, 89, - "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SPI2_SOMI, 90, - "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_DAT_RX, 62, - "ssi1_dat_rx", "uart1_rx", "usb1_dat", "gpio_62", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_DAT_TX, 59, - "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_FLAG_RX, 64, - "ssi1_flag_rx", "mcbsp4_dr", NULL, "gpio_64", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_FLAG_TX, 60, - "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_60", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_RDY_RX, 65, - "ssi1_rdy_rx", "mcbsp4_dx", NULL, "gpio_65", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_RDY_TX, 61, - "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SSI1_WAKE, 66, - "ssi1_wake", "mcbsp4_fsx", NULL, "gpio_66", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SYS_CLKOUT, 111, - "sys_clkout", NULL, NULL, "gpio_111", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SYS_DRM_MSECURE, 118, - "sys_drm_msecure", NULL, "sys_ndmareq6", "gpio_118", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SYS_NIRQ0, 56, - "sys_nirq0", NULL, NULL, "gpio_56", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(SYS_NIRQ1, 125, - "sys_nirq1", NULL, "sys_ndmareq5", "gpio_125", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART1_CTS, 32, - "uart1_cts", "sdi_vsync", "dss_data18", "gpio_32", - "mcbsp5_clkx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART1_RTS, 8, - "uart1_rts", "sdi_hsync", "dss_data19", "gpio_8", - "mcbsp5_fsx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART1_RX, 10, - "uart1_rx", "sdi_stp", "dss_data21", "gpio_10", - "mcbsp5_dr", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART1_TX, 9, - "uart1_tx", "sdi_den", "dss_data20", "gpio_9", - "mcbsp5_dx", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART2_CTS, 67, - "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART2_RTS, 68, - "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART2_RX, 70, - "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART2_TX, 69, - "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART3_CTS_RCTX, 102, - "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART3_RTS_SD, 103, - "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART3_RX_IRRX, 105, - "uart3_rx_irrx", NULL, NULL, "gpio_105", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(UART3_TX_IRTX, 104, - "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_CLK, 120, - "usb0hs_clk", NULL, NULL, "gpio_120", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA0, 0, - "usb0hs_data0", "uart3_tx_irtx", NULL, NULL, - "usb0_txen", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA1, 0, - "usb0hs_data1", "uart3_rx_irrx", NULL, NULL, - "usb0_dat", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA2, 0, - "usb0hs_data2", "uart3_rts_sd", NULL, NULL, - "usb0_se0", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA3, 106, - "usb0hs_data3", NULL, "uart3_cts_rctx", "gpio_106", - "usb0_puen", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA4, 107, - "usb0hs_data4", "mcbsp2_dr", NULL, "gpio_107", - "usb0_vp", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA5, 108, - "usb0hs_data5", "mcbsp2_dx", NULL, "gpio_108", - "usb0_vm", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA6, 109, - "usb0hs_data6", "mcbsp2_fsx", NULL, "gpio_109", - "usb0_rcv", NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DATA7, 124, - "usb0hs_data7", "mcbsp2_clkx", NULL, "gpio_124", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_DIR, 121, - "usb0hs_dir", NULL, NULL, "gpio_121", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_NXT, 123, - "usb0hs_nxt", NULL, NULL, "gpio_123", - NULL, NULL, NULL, "safe_mode"), - _OMAP2430_MUXENTRY(USB0HS_STP, 122, - "usb0hs_stp", NULL, NULL, "gpio_122", - NULL, NULL, NULL, "safe_mode"), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -/* - * Balls for POP package - * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom) - */ -#ifdef CONFIG_DEBUG_FS -static struct omap_ball __initdata omap2430_pop_ball[] = { - _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL), - _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL), - _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL), - _OMAP2430_BALLENTRY(CAM_D11, "w3", NULL), - _OMAP2430_BALLENTRY(CAM_D2, "r2", NULL), - _OMAP2430_BALLENTRY(CAM_D3, "u3", NULL), - _OMAP2430_BALLENTRY(CAM_D4, "u2", NULL), - _OMAP2430_BALLENTRY(CAM_D5, "v1", NULL), - _OMAP2430_BALLENTRY(CAM_D6, "t3", NULL), - _OMAP2430_BALLENTRY(CAM_D7, "r3", NULL), - _OMAP2430_BALLENTRY(CAM_D8, "u7", NULL), - _OMAP2430_BALLENTRY(CAM_D9, "t7", NULL), - _OMAP2430_BALLENTRY(CAM_HS, "p2", NULL), - _OMAP2430_BALLENTRY(CAM_LCLK, "r7", NULL), - _OMAP2430_BALLENTRY(CAM_VS, "n2", NULL), - _OMAP2430_BALLENTRY(CAM_XCLK, "p3", NULL), - _OMAP2430_BALLENTRY(DSS_ACBIAS, "y3", NULL), - _OMAP2430_BALLENTRY(DSS_DATA0, "v8", NULL), - _OMAP2430_BALLENTRY(DSS_DATA1, "w1", NULL), - _OMAP2430_BALLENTRY(DSS_DATA10, "k25", NULL), - _OMAP2430_BALLENTRY(DSS_DATA11, "j25", NULL), - _OMAP2430_BALLENTRY(DSS_DATA12, "k24", NULL), - _OMAP2430_BALLENTRY(DSS_DATA13, "j24", NULL), - _OMAP2430_BALLENTRY(DSS_DATA14, "h25", NULL), - _OMAP2430_BALLENTRY(DSS_DATA15, "g25", NULL), - _OMAP2430_BALLENTRY(DSS_DATA16, "ac3", NULL), - _OMAP2430_BALLENTRY(DSS_DATA17, "y7", NULL), - _OMAP2430_BALLENTRY(DSS_DATA2, "u8", NULL), - _OMAP2430_BALLENTRY(DSS_DATA3, "u4", NULL), - _OMAP2430_BALLENTRY(DSS_DATA4, "v3", NULL), - _OMAP2430_BALLENTRY(DSS_DATA5, "aa4", NULL), - _OMAP2430_BALLENTRY(DSS_DATA6, "w8", NULL), - _OMAP2430_BALLENTRY(DSS_DATA7, "y1", NULL), - _OMAP2430_BALLENTRY(DSS_DATA8, "aa2", NULL), - _OMAP2430_BALLENTRY(DSS_DATA9, "ab4", NULL), - _OMAP2430_BALLENTRY(DSS_HSYNC, "v2", NULL), - _OMAP2430_BALLENTRY(GPIO_113, "ad16", NULL), - _OMAP2430_BALLENTRY(GPIO_114, "ac10", NULL), - _OMAP2430_BALLENTRY(GPIO_115, "ad13", NULL), - _OMAP2430_BALLENTRY(GPIO_116, "ae15", NULL), - _OMAP2430_BALLENTRY(GPIO_128, "p1", NULL), - _OMAP2430_BALLENTRY(GPIO_129, "r1", NULL), - _OMAP2430_BALLENTRY(GPIO_130, "p7", NULL), - _OMAP2430_BALLENTRY(GPIO_131, "l8", NULL), - _OMAP2430_BALLENTRY(GPIO_132, "w24", NULL), - _OMAP2430_BALLENTRY(GPIO_133, "aa24", NULL), - _OMAP2430_BALLENTRY(GPIO_134, "ae12", NULL), - _OMAP2430_BALLENTRY(GPIO_135, "ae11", NULL), - _OMAP2430_BALLENTRY(GPIO_136, "ad12", NULL), - _OMAP2430_BALLENTRY(GPIO_137, "ad11", NULL), - _OMAP2430_BALLENTRY(GPIO_138, "y12", NULL), - _OMAP2430_BALLENTRY(GPIO_139, "ad17", NULL), - _OMAP2430_BALLENTRY(GPIO_140, "l7", NULL), - _OMAP2430_BALLENTRY(GPIO_141, "ac24", NULL), - _OMAP2430_BALLENTRY(GPIO_142, "m3", NULL), - _OMAP2430_BALLENTRY(GPIO_148, "af12", NULL), - _OMAP2430_BALLENTRY(GPIO_149, "k7", NULL), - _OMAP2430_BALLENTRY(GPIO_150, "m1", NULL), - _OMAP2430_BALLENTRY(GPIO_151, "ad14", NULL), - _OMAP2430_BALLENTRY(GPIO_152, "ad18", NULL), - _OMAP2430_BALLENTRY(GPIO_153, "u24", NULL), - _OMAP2430_BALLENTRY(GPIO_154, "ae16", NULL), - _OMAP2430_BALLENTRY(GPIO_63, "n3", NULL), - _OMAP2430_BALLENTRY(GPIO_7, "ac23", NULL), - _OMAP2430_BALLENTRY(GPIO_78, "ad10", NULL), - _OMAP2430_BALLENTRY(GPIO_79, "ae10", NULL), - _OMAP2430_BALLENTRY(GPIO_80, "ae13", NULL), - _OMAP2430_BALLENTRY(GPMC_A1, "a9", NULL), - _OMAP2430_BALLENTRY(GPMC_A10, "g12", NULL), - _OMAP2430_BALLENTRY(GPMC_A2, "b8", NULL), - _OMAP2430_BALLENTRY(GPMC_A3, "g10", NULL), - _OMAP2430_BALLENTRY(GPMC_A4, "g11", NULL), - _OMAP2430_BALLENTRY(GPMC_A5, "a10", NULL), - _OMAP2430_BALLENTRY(GPMC_A6, "g13", NULL), - _OMAP2430_BALLENTRY(GPMC_A7, "a6", NULL), - _OMAP2430_BALLENTRY(GPMC_A8, "h1", NULL), - _OMAP2430_BALLENTRY(GPMC_A9, "c8", NULL), - _OMAP2430_BALLENTRY(GPMC_CLK, "n1", "l1"), - _OMAP2430_BALLENTRY(GPMC_D10, "d1", "n1"), - _OMAP2430_BALLENTRY(GPMC_D11, "d2", "p2"), - _OMAP2430_BALLENTRY(GPMC_D12, "e1", "p1"), - _OMAP2430_BALLENTRY(GPMC_D13, "e3", "m1"), - _OMAP2430_BALLENTRY(GPMC_D14, "c7", "j2"), - _OMAP2430_BALLENTRY(GPMC_D15, "f3", "k2"), - _OMAP2430_BALLENTRY(GPMC_D8, "e2", "r1"), - _OMAP2430_BALLENTRY(GPMC_D9, "ab1", "t1"), - _OMAP2430_BALLENTRY(GPMC_NCS1, "ac1", "w1"), - _OMAP2430_BALLENTRY(GPMC_NCS2, "c6", NULL), - _OMAP2430_BALLENTRY(GPMC_NCS3, "b9", NULL), - _OMAP2430_BALLENTRY(GPMC_NCS4, "b4", NULL), - _OMAP2430_BALLENTRY(GPMC_NCS5, "a4", NULL), - _OMAP2430_BALLENTRY(GPMC_NCS6, "f1", NULL), - _OMAP2430_BALLENTRY(GPMC_NCS7, "a7", NULL), - _OMAP2430_BALLENTRY(GPMC_WAIT1, "j1", "y8"), - _OMAP2430_BALLENTRY(GPMC_WAIT2, "b7", NULL), - _OMAP2430_BALLENTRY(GPMC_WAIT3, "g14", NULL), - _OMAP2430_BALLENTRY(HDQ_SIO, "h20", NULL), - _OMAP2430_BALLENTRY(I2C1_SCL, "y17", NULL), - _OMAP2430_BALLENTRY(I2C1_SDA, "ac19", NULL), - _OMAP2430_BALLENTRY(I2C2_SCL, "n7", NULL), - _OMAP2430_BALLENTRY(I2C2_SDA, "m4", NULL), - _OMAP2430_BALLENTRY(JTAG_EMU0, "e25", NULL), - _OMAP2430_BALLENTRY(JTAG_EMU1, "e24", NULL), - _OMAP2430_BALLENTRY(MCBSP1_CLKR, "ab2", NULL), - _OMAP2430_BALLENTRY(MCBSP1_CLKX, "y9", NULL), - _OMAP2430_BALLENTRY(MCBSP1_DR, "af3", NULL), - _OMAP2430_BALLENTRY(MCBSP1_DX, "aa1", NULL), - _OMAP2430_BALLENTRY(MCBSP1_FSR, "ad5", NULL), - _OMAP2430_BALLENTRY(MCBSP1_FSX, "ab3", NULL), - _OMAP2430_BALLENTRY(MCBSP2_CLKX, "j26", NULL), - _OMAP2430_BALLENTRY(MCBSP2_DR, "k26", NULL), - _OMAP2430_BALLENTRY(MCBSP3_CLKX, "ac9", NULL), - _OMAP2430_BALLENTRY(MCBSP3_DR, "ae2", NULL), - _OMAP2430_BALLENTRY(MCBSP3_DX, "af4", NULL), - _OMAP2430_BALLENTRY(MCBSP3_FSX, "ae4", NULL), - _OMAP2430_BALLENTRY(MCBSP_CLKS, "ad6", NULL), - _OMAP2430_BALLENTRY(SDMMC1_CLKO, "n23", NULL), - _OMAP2430_BALLENTRY(SDMMC1_CMD, "l23", NULL), - _OMAP2430_BALLENTRY(SDMMC1_DAT0, "m24", NULL), - _OMAP2430_BALLENTRY(SDMMC1_DAT1, "p23", NULL), - _OMAP2430_BALLENTRY(SDMMC1_DAT2, "t20", NULL), - _OMAP2430_BALLENTRY(SDMMC1_DAT3, "r20", NULL), - _OMAP2430_BALLENTRY(SDMMC2_CLKO, "v26", NULL), - _OMAP2430_BALLENTRY(SDMMC2_CMD, "w20", NULL), - _OMAP2430_BALLENTRY(SDMMC2_DAT0, "v23", NULL), - _OMAP2430_BALLENTRY(SDMMC2_DAT1, "y24", NULL), - _OMAP2430_BALLENTRY(SDMMC2_DAT2, "v25", NULL), - _OMAP2430_BALLENTRY(SDMMC2_DAT3, "v24", NULL), - _OMAP2430_BALLENTRY(SDRC_A12, "w26", "r21"), - _OMAP2430_BALLENTRY(SDRC_A13, "af20", "aa15"), - _OMAP2430_BALLENTRY(SDRC_A14, "af16", "y12"), - _OMAP2430_BALLENTRY(SDRC_CKE1, "af15", "y13"), - _OMAP2430_BALLENTRY(SDRC_NCS1, "aa25", "t20"), - _OMAP2430_BALLENTRY(SPI1_CLK, "y18", NULL), - _OMAP2430_BALLENTRY(SPI1_CS0, "u1", NULL), - _OMAP2430_BALLENTRY(SPI1_CS1, "af19", NULL), - _OMAP2430_BALLENTRY(SPI1_CS2, "ae19", NULL), - _OMAP2430_BALLENTRY(SPI1_CS3, "h24", NULL), - _OMAP2430_BALLENTRY(SPI1_SIMO, "ad15", NULL), - _OMAP2430_BALLENTRY(SPI1_SOMI, "ae17", NULL), - _OMAP2430_BALLENTRY(SPI2_CLK, "y20", NULL), - _OMAP2430_BALLENTRY(SPI2_CS0, "y19", NULL), - _OMAP2430_BALLENTRY(SPI2_SIMO, "ac20", NULL), - _OMAP2430_BALLENTRY(SPI2_SOMI, "ad19", NULL), - _OMAP2430_BALLENTRY(SSI1_DAT_RX, "aa26", NULL), - _OMAP2430_BALLENTRY(SSI1_DAT_TX, "ad24", NULL), - _OMAP2430_BALLENTRY(SSI1_FLAG_RX, "ad23", NULL), - _OMAP2430_BALLENTRY(SSI1_FLAG_TX, "ab24", NULL), - _OMAP2430_BALLENTRY(SSI1_RDY_RX, "ab25", NULL), - _OMAP2430_BALLENTRY(SSI1_RDY_TX, "y25", NULL), - _OMAP2430_BALLENTRY(SSI1_WAKE, "ac25", NULL), - _OMAP2430_BALLENTRY(SYS_CLKOUT, "r25", NULL), - _OMAP2430_BALLENTRY(SYS_DRM_MSECURE, "ae3", NULL), - _OMAP2430_BALLENTRY(SYS_NIRQ0, "w25", NULL), - _OMAP2430_BALLENTRY(SYS_NIRQ1, "ad21", NULL), - _OMAP2430_BALLENTRY(UART1_CTS, "p24", NULL), - _OMAP2430_BALLENTRY(UART1_RTS, "p25", NULL), - _OMAP2430_BALLENTRY(UART1_RX, "n24", NULL), - _OMAP2430_BALLENTRY(UART1_TX, "r24", NULL), - _OMAP2430_BALLENTRY(UART2_CTS, "u25", NULL), - _OMAP2430_BALLENTRY(UART2_RTS, "t23", NULL), - _OMAP2430_BALLENTRY(UART2_RX, "t24", NULL), - _OMAP2430_BALLENTRY(UART2_TX, "u20", NULL), - _OMAP2430_BALLENTRY(UART3_CTS_RCTX, "m2", NULL), - _OMAP2430_BALLENTRY(UART3_RTS_SD, "k2", NULL), - _OMAP2430_BALLENTRY(UART3_RX_IRRX, "l3", NULL), - _OMAP2430_BALLENTRY(UART3_TX_IRTX, "l2", NULL), - _OMAP2430_BALLENTRY(USB0HS_CLK, "ae8", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA0, "ad4", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA1, "ae6", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA2, "af9", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA3, "ad9", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA4, "y11", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA5, "ad7", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA6, "ae7", NULL), - _OMAP2430_BALLENTRY(USB0HS_DATA7, "ac7", NULL), - _OMAP2430_BALLENTRY(USB0HS_DIR, "ad8", NULL), - _OMAP2430_BALLENTRY(USB0HS_NXT, "ae9", NULL), - _OMAP2430_BALLENTRY(USB0HS_STP, "ae5", NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap2430_pop_ball NULL -#endif - -int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags) -{ - struct omap_ball *package_balls = NULL; - - switch (flags & OMAP_PACKAGE_MASK) { - case OMAP_PACKAGE_ZAC: - package_balls = omap2430_pop_ball; - break; - default: - pr_warning("%s: No ball data available for omap2420 package\n", - __func__); - } - - return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3, - OMAP2430_CONTROL_PADCONF_MUX_PBASE, - OMAP2430_CONTROL_PADCONF_MUX_SIZE, - omap2430_muxmodes, NULL, board_subset, - package_balls); -} diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h deleted file mode 100644 index 9fd9314..0000000 --- a/arch/arm/mach-omap2/mux2430.h +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (C) 2009 Nokia - * Copyright (C) 2009 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define OMAP2430_CONTROL_PADCONF_MUX_PBASE 0x49002030LU - -#define OMAP2430_MUX(mode0, mux_value) \ -{ \ - .reg_offset = (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET), \ - .value = (mux_value), \ -} - -/* - * OMAP2430 CONTROL_PADCONF* register offsets for pin-muxing - * - * Extracted from the TRM. Add 0x49002030 to these values to get the - * absolute addresses. The name in the macro is the mode-0 name of - * the pin. NOTE: These registers are 8-bits wide. - * - * Note that these defines use SDMMC instead of MMC for compatibility - * with signal names used in 3630. - */ -#define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x000 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x001 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x002 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x003 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x004 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x005 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x006 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x007 -#define OMAP2430_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x008 -#define OMAP2430_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x009 -#define OMAP2430_CONTROL_PADCONF_GPMC_NOE_NRE_OFFSET 0x00a -#define OMAP2430_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x00b -#define OMAP2430_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x00c -#define OMAP2430_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x00d -#define OMAP2430_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x00e -#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x00f -#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x010 -#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x011 -#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x012 -#define OMAP2430_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x013 -#define OMAP2430_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x014 -#define OMAP2430_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x015 -#define OMAP2430_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x016 -#define OMAP2430_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x017 -#define OMAP2430_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x018 -#define OMAP2430_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x019 -#define OMAP2430_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x01a -#define OMAP2430_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x01b -#define OMAP2430_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x01c -#define OMAP2430_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x01d -#define OMAP2430_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x01e -#define OMAP2430_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x01f -#define OMAP2430_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x020 -#define OMAP2430_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x021 -#define OMAP2430_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x022 -#define OMAP2430_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x023 -#define OMAP2430_CONTROL_PADCONF_SDRC_A14_OFFSET 0x024 -#define OMAP2430_CONTROL_PADCONF_SDRC_A13_OFFSET 0x025 -#define OMAP2430_CONTROL_PADCONF_SDRC_A12_OFFSET 0x026 -#define OMAP2430_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x027 -#define OMAP2430_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x028 -#define OMAP2430_CONTROL_PADCONF_SDRC_A11_OFFSET 0x029 -#define OMAP2430_CONTROL_PADCONF_SDRC_A10_OFFSET 0x02a -#define OMAP2430_CONTROL_PADCONF_SDRC_A9_OFFSET 0x02b -#define OMAP2430_CONTROL_PADCONF_SDRC_A8_OFFSET 0x02c -#define OMAP2430_CONTROL_PADCONF_SDRC_A7_OFFSET 0x02d -#define OMAP2430_CONTROL_PADCONF_SDRC_A6_OFFSET 0x02e -#define OMAP2430_CONTROL_PADCONF_SDRC_A5_OFFSET 0x02f -#define OMAP2430_CONTROL_PADCONF_SDRC_A4_OFFSET 0x030 -#define OMAP2430_CONTROL_PADCONF_SDRC_A3_OFFSET 0x031 -#define OMAP2430_CONTROL_PADCONF_SDRC_A2_OFFSET 0x032 -#define OMAP2430_CONTROL_PADCONF_SDRC_A1_OFFSET 0x033 -#define OMAP2430_CONTROL_PADCONF_SDRC_A0_OFFSET 0x034 -#define OMAP2430_CONTROL_PADCONF_SDRC_D31_OFFSET 0x035 -#define OMAP2430_CONTROL_PADCONF_SDRC_D30_OFFSET 0x036 -#define OMAP2430_CONTROL_PADCONF_SDRC_D29_OFFSET 0x037 -#define OMAP2430_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038 -#define OMAP2430_CONTROL_PADCONF_SDRC_D27_OFFSET 0x039 -#define OMAP2430_CONTROL_PADCONF_SDRC_D26_OFFSET 0x03a -#define OMAP2430_CONTROL_PADCONF_SDRC_D25_OFFSET 0x03b -#define OMAP2430_CONTROL_PADCONF_SDRC_D24_OFFSET 0x03c -#define OMAP2430_CONTROL_PADCONF_SDRC_D23_OFFSET 0x03d -#define OMAP2430_CONTROL_PADCONF_SDRC_D22_OFFSET 0x03e -#define OMAP2430_CONTROL_PADCONF_SDRC_D21_OFFSET 0x03f -#define OMAP2430_CONTROL_PADCONF_SDRC_D20_OFFSET 0x040 -#define OMAP2430_CONTROL_PADCONF_SDRC_D19_OFFSET 0x041 -#define OMAP2430_CONTROL_PADCONF_SDRC_D18_OFFSET 0x042 -#define OMAP2430_CONTROL_PADCONF_SDRC_D17_OFFSET 0x043 -#define OMAP2430_CONTROL_PADCONF_SDRC_D16_OFFSET 0x044 -#define OMAP2430_CONTROL_PADCONF_SDRC_D15_OFFSET 0x045 -#define OMAP2430_CONTROL_PADCONF_SDRC_D14_OFFSET 0x046 -#define OMAP2430_CONTROL_PADCONF_SDRC_D13_OFFSET 0x047 -#define OMAP2430_CONTROL_PADCONF_SDRC_D12_OFFSET 0x048 -#define OMAP2430_CONTROL_PADCONF_SDRC_D11_OFFSET 0x049 -#define OMAP2430_CONTROL_PADCONF_SDRC_D10_OFFSET 0x04a -#define OMAP2430_CONTROL_PADCONF_SDRC_D9_OFFSET 0x04b -#define OMAP2430_CONTROL_PADCONF_SDRC_D8_OFFSET 0x04c -#define OMAP2430_CONTROL_PADCONF_SDRC_D7_OFFSET 0x04d -#define OMAP2430_CONTROL_PADCONF_SDRC_D6_OFFSET 0x04e -#define OMAP2430_CONTROL_PADCONF_SDRC_D5_OFFSET 0x04f -#define OMAP2430_CONTROL_PADCONF_SDRC_D4_OFFSET 0x050 -#define OMAP2430_CONTROL_PADCONF_SDRC_D3_OFFSET 0x051 -#define OMAP2430_CONTROL_PADCONF_SDRC_D2_OFFSET 0x052 -#define OMAP2430_CONTROL_PADCONF_SDRC_D1_OFFSET 0x053 -#define OMAP2430_CONTROL_PADCONF_SDRC_D0_OFFSET 0x054 -#define OMAP2430_CONTROL_PADCONF_GPMC_A10_OFFSET 0x055 -#define OMAP2430_CONTROL_PADCONF_GPMC_A9_OFFSET 0x056 -#define OMAP2430_CONTROL_PADCONF_GPMC_A8_OFFSET 0x057 -#define OMAP2430_CONTROL_PADCONF_GPMC_A7_OFFSET 0x058 -#define OMAP2430_CONTROL_PADCONF_GPMC_A6_OFFSET 0x059 -#define OMAP2430_CONTROL_PADCONF_GPMC_A5_OFFSET 0x05a -#define OMAP2430_CONTROL_PADCONF_GPMC_A4_OFFSET 0x05b -#define OMAP2430_CONTROL_PADCONF_GPMC_A3_OFFSET 0x05c -#define OMAP2430_CONTROL_PADCONF_GPMC_A2_OFFSET 0x05d -#define OMAP2430_CONTROL_PADCONF_GPMC_A1_OFFSET 0x05e -#define OMAP2430_CONTROL_PADCONF_GPMC_D15_OFFSET 0x05f -#define OMAP2430_CONTROL_PADCONF_GPMC_D14_OFFSET 0x060 -#define OMAP2430_CONTROL_PADCONF_GPMC_D13_OFFSET 0x061 -#define OMAP2430_CONTROL_PADCONF_GPMC_D12_OFFSET 0x062 -#define OMAP2430_CONTROL_PADCONF_GPMC_D11_OFFSET 0x063 -#define OMAP2430_CONTROL_PADCONF_GPMC_D10_OFFSET 0x064 -#define OMAP2430_CONTROL_PADCONF_GPMC_D9_OFFSET 0x065 -#define OMAP2430_CONTROL_PADCONF_GPMC_D8_OFFSET 0x066 -#define OMAP2430_CONTROL_PADCONF_GPMC_D7_OFFSET 0x067 -#define OMAP2430_CONTROL_PADCONF_GPMC_D6_OFFSET 0x068 -#define OMAP2430_CONTROL_PADCONF_GPMC_D5_OFFSET 0x069 -#define OMAP2430_CONTROL_PADCONF_GPMC_D4_OFFSET 0x06a -#define OMAP2430_CONTROL_PADCONF_GPMC_D3_OFFSET 0x06b -#define OMAP2430_CONTROL_PADCONF_GPMC_D2_OFFSET 0x06c -#define OMAP2430_CONTROL_PADCONF_GPMC_D1_OFFSET 0x06d -#define OMAP2430_CONTROL_PADCONF_GPMC_D0_OFFSET 0x06e -#define OMAP2430_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x06f -#define OMAP2430_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x070 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x071 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x072 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x073 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x074 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x075 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x076 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x077 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x078 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x079 -#define OMAP2430_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x07a -#define OMAP2430_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x07b -#define OMAP2430_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x07c -#define OMAP2430_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x07d -#define OMAP2430_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x07e -#define OMAP2430_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x07f -#define OMAP2430_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x080 -#define OMAP2430_CONTROL_PADCONF_UART1_CTS_OFFSET 0x081 -#define OMAP2430_CONTROL_PADCONF_UART1_RTS_OFFSET 0x082 -#define OMAP2430_CONTROL_PADCONF_UART1_TX_OFFSET 0x083 -#define OMAP2430_CONTROL_PADCONF_UART1_RX_OFFSET 0x084 -#define OMAP2430_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x085 -#define OMAP2430_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x086 -#define OMAP2430_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x087 -#define OMAP2430_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x088 -#define OMAP2430_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x089 -#define OMAP2430_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x08a -#define OMAP2430_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x08b -#define OMAP2430_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x08c -#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ0_OFFSET 0x08d -#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ1_OFFSET 0x08e -#define OMAP2430_CONTROL_PADCONF_SYS_VMODE_OFFSET 0x08f -#define OMAP2430_CONTROL_PADCONF_GPIO_128_OFFSET 0x090 -#define OMAP2430_CONTROL_PADCONF_GPIO_129_OFFSET 0x091 -#define OMAP2430_CONTROL_PADCONF_GPIO_130_OFFSET 0x092 -#define OMAP2430_CONTROL_PADCONF_GPIO_131_OFFSET 0x093 -#define OMAP2430_CONTROL_PADCONF_SYS_32K_OFFSET 0x094 -#define OMAP2430_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x095 -#define OMAP2430_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x096 -#define OMAP2430_CONTROL_PADCONF_GPIO_132_OFFSET 0x097 -#define OMAP2430_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x098 -#define OMAP2430_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x099 -#define OMAP2430_CONTROL_PADCONF_GPIO_151_OFFSET 0x09a -#define OMAP2430_CONTROL_PADCONF_GPIO_133_OFFSET 0x09b -#define OMAP2430_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x09c -#define OMAP2430_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x09d -#define OMAP2430_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x09e -#define OMAP2430_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x09f -#define OMAP2430_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x0a0 -#define OMAP2430_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x0a1 -#define OMAP2430_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x0a2 -#define OMAP2430_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x0a3 -#define OMAP2430_CONTROL_PADCONF_CAM_D9_OFFSET 0x0a4 -#define OMAP2430_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a5 -#define OMAP2430_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a6 -#define OMAP2430_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a7 -#define OMAP2430_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a8 -#define OMAP2430_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a9 -#define OMAP2430_CONTROL_PADCONF_CAM_D3_OFFSET 0x0aa -#define OMAP2430_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ab -#define OMAP2430_CONTROL_PADCONF_CAM_D1_OFFSET 0x0ac -#define OMAP2430_CONTROL_PADCONF_CAM_D0_OFFSET 0x0ad -#define OMAP2430_CONTROL_PADCONF_CAM_HS_OFFSET 0x0ae -#define OMAP2430_CONTROL_PADCONF_CAM_VS_OFFSET 0x0af -#define OMAP2430_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0b0 -#define OMAP2430_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0b1 -#define OMAP2430_CONTROL_PADCONF_CAM_D11_OFFSET 0x0b2 -#define OMAP2430_CONTROL_PADCONF_CAM_D10_OFFSET 0x0b3 -#define OMAP2430_CONTROL_PADCONF_GPIO_134_OFFSET 0x0b4 -#define OMAP2430_CONTROL_PADCONF_GPIO_135_OFFSET 0x0b5 -#define OMAP2430_CONTROL_PADCONF_GPIO_136_OFFSET 0x0b6 -#define OMAP2430_CONTROL_PADCONF_GPIO_137_OFFSET 0x0b7 -#define OMAP2430_CONTROL_PADCONF_GPIO_138_OFFSET 0x0b8 -#define OMAP2430_CONTROL_PADCONF_GPIO_139_OFFSET 0x0b9 -#define OMAP2430_CONTROL_PADCONF_GPIO_140_OFFSET 0x0ba -#define OMAP2430_CONTROL_PADCONF_GPIO_141_OFFSET 0x0bb -#define OMAP2430_CONTROL_PADCONF_GPIO_142_OFFSET 0x0bc -#define OMAP2430_CONTROL_PADCONF_GPIO_154_OFFSET 0x0bd -#define OMAP2430_CONTROL_PADCONF_GPIO_148_OFFSET 0x0be -#define OMAP2430_CONTROL_PADCONF_GPIO_149_OFFSET 0x0bf -#define OMAP2430_CONTROL_PADCONF_GPIO_150_OFFSET 0x0c0 -#define OMAP2430_CONTROL_PADCONF_GPIO_152_OFFSET 0x0c1 -#define OMAP2430_CONTROL_PADCONF_GPIO_153_OFFSET 0x0c2 -#define OMAP2430_CONTROL_PADCONF_SDMMC1_CLKO_OFFSET 0x0c3 -#define OMAP2430_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x0c4 -#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x0c5 -#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x0c6 -#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x0c7 -#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x0c8 -#define OMAP2430_CONTROL_PADCONF_SDMMC2_CLKO_OFFSET 0x0c9 -#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x0ca -#define OMAP2430_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x0cb -#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x0cc -#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x0cd -#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x0ce -#define OMAP2430_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0cf -#define OMAP2430_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0d0 -#define OMAP2430_CONTROL_PADCONF_UART2_TX_OFFSET 0x0d1 -#define OMAP2430_CONTROL_PADCONF_UART2_RX_OFFSET 0x0d2 -#define OMAP2430_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x0d3 -#define OMAP2430_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x0d4 -#define OMAP2430_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x0d5 -#define OMAP2430_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x0d6 -#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0d7 -#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0d8 -#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0d9 -#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0da -#define OMAP2430_CONTROL_PADCONF_GPIO_63_OFFSET 0x0db -#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0dc -#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0dd -#define OMAP2430_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0de -#define OMAP2430_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0df -#define OMAP2430_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0e0 -#define OMAP2430_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0e1 -#define OMAP2430_CONTROL_PADCONF_SPI1_CS0_OFFSET 0x0e2 -#define OMAP2430_CONTROL_PADCONF_SPI1_CS1_OFFSET 0x0e3 -#define OMAP2430_CONTROL_PADCONF_SPI1_CS2_OFFSET 0x0e4 -#define OMAP2430_CONTROL_PADCONF_SPI1_CS3_OFFSET 0x0e5 -#define OMAP2430_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0e6 -#define OMAP2430_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0e7 -#define OMAP2430_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0e8 -#define OMAP2430_CONTROL_PADCONF_SPI2_CS0_OFFSET 0x0e9 -#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0ea -#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0eb -#define OMAP2430_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0ec -#define OMAP2430_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0ed -#define OMAP2430_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0ee -#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0ef -#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0f0 -#define OMAP2430_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0f1 -#define OMAP2430_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0f2 -#define OMAP2430_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0f3 -#define OMAP2430_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0f4 -#define OMAP2430_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0f5 -#define OMAP2430_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0f6 -#define OMAP2430_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0f7 -#define OMAP2430_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0f8 -#define OMAP2430_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0f9 -#define OMAP2430_CONTROL_PADCONF_GPIO_7_OFFSET 0x0fa -#define OMAP2430_CONTROL_PADCONF_GPIO_78_OFFSET 0x0fb -#define OMAP2430_CONTROL_PADCONF_GPIO_79_OFFSET 0x0fc -#define OMAP2430_CONTROL_PADCONF_GPIO_80_OFFSET 0x0fd -#define OMAP2430_CONTROL_PADCONF_GPIO_113_OFFSET 0x0fe -#define OMAP2430_CONTROL_PADCONF_GPIO_114_OFFSET 0x0ff -#define OMAP2430_CONTROL_PADCONF_GPIO_115_OFFSET 0x100 -#define OMAP2430_CONTROL_PADCONF_GPIO_116_OFFSET 0x101 -#define OMAP2430_CONTROL_PADCONF_SYS_DRM_MSECURE_OFFSET 0x102 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA3_OFFSET 0x103 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA4_OFFSET 0x104 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA5_OFFSET 0x105 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA6_OFFSET 0x106 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA2_OFFSET 0x107 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA0_OFFSET 0x108 -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA1_OFFSET 0x109 -#define OMAP2430_CONTROL_PADCONF_USB0HS_CLK_OFFSET 0x10a -#define OMAP2430_CONTROL_PADCONF_USB0HS_DIR_OFFSET 0x10b -#define OMAP2430_CONTROL_PADCONF_USB0HS_STP_OFFSET 0x10c -#define OMAP2430_CONTROL_PADCONF_USB0HS_NXT_OFFSET 0x10d -#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA7_OFFSET 0x10e -#define OMAP2430_CONTROL_PADCONF_TV_OUT_OFFSET 0x10f -#define OMAP2430_CONTROL_PADCONF_TV_VREF_OFFSET 0x110 -#define OMAP2430_CONTROL_PADCONF_TV_RSET_OFFSET 0x111 -#define OMAP2430_CONTROL_PADCONF_TV_VFB_OFFSET 0x112 -#define OMAP2430_CONTROL_PADCONF_TV_DACOUT_OFFSET 0x113 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD0_OFFSET 0x114 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD1_OFFSET 0x115 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD2_OFFSET 0x116 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD3_OFFSET 0x117 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD4_OFFSET 0x118 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD5_OFFSET 0x119 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD6_OFFSET 0x11a -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD7_OFFSET 0x11b -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD8_OFFSET 0x11c -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD9_OFFSET 0x11d -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD10_OFFSET 0x11e -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD11_OFFSET 0x11f -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD12_OFFSET 0x120 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD13_OFFSET 0x121 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD14_OFFSET 0x122 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD15_OFFSET 0x123 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD16_OFFSET 0x124 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD17_OFFSET 0x125 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD18_OFFSET 0x126 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD19_OFFSET 0x127 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD20_OFFSET 0x128 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD21_OFFSET 0x129 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD22_OFFSET 0x12a -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD23_OFFSET 0x12b -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD24_OFFSET 0x12c -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD25_OFFSET 0x12d -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD26_OFFSET 0x12e -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD27_OFFSET 0x12f -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD28_OFFSET 0x130 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD29_OFFSET 0x131 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD30_OFFSET 0x132 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD31_OFFSET 0x133 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD32_OFFSET 0x134 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD33_OFFSET 0x135 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD34_OFFSET 0x136 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD35_OFFSET 0x137 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD36_OFFSET 0x138 -#define OMAP2430_CONTROL_PADCONF_AD2DMCAD37_OFFSET 0x139 -#define OMAP2430_CONTROL_PADCONF_AD2DMWRITE_OFFSET 0x13a -#define OMAP2430_CONTROL_PADCONF_D2DCLK26MI_OFFSET 0x13b -#define OMAP2430_CONTROL_PADCONF_D2DNRESPWRON1_OFFSET 0x13c -#define OMAP2430_CONTROL_PADCONF_D2DNRESWARM_OFFSET 0x13d -#define OMAP2430_CONTROL_PADCONF_D2DARM9NIRQ_OFFSET 0x13e -#define OMAP2430_CONTROL_PADCONF_D2DUMA2P6FIQ_OFFSET 0x13f -#define OMAP2430_CONTROL_PADCONF_D2DSPINT_OFFSET 0x140 -#define OMAP2430_CONTROL_PADCONF_D2DFRINT_OFFSET 0x141 -#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ0_OFFSET 0x142 -#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ1_OFFSET 0x143 -#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ2_OFFSET 0x144 -#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ3_OFFSET 0x145 -#define OMAP2430_CONTROL_PADCONF_D2DN3GTRST_OFFSET 0x146 -#define OMAP2430_CONTROL_PADCONF_D2DN3GTDI_OFFSET 0x147 -#define OMAP2430_CONTROL_PADCONF_D2DN3GTDO_OFFSET 0x148 -#define OMAP2430_CONTROL_PADCONF_D2DN3GTMS_OFFSET 0x149 -#define OMAP2430_CONTROL_PADCONF_D2DN3GTCK_OFFSET 0x14a -#define OMAP2430_CONTROL_PADCONF_D2DN3GRTCK_OFFSET 0x14b -#define OMAP2430_CONTROL_PADCONF_D2DMSTDBY_OFFSET 0x14c -#define OMAP2430_CONTROL_PADCONF_AD2DSREAD_OFFSET 0x14d -#define OMAP2430_CONTROL_PADCONF_D2DSWAKEUP_OFFSET 0x14e -#define OMAP2430_CONTROL_PADCONF_D2DIDLEREQ_OFFSET 0x14f -#define OMAP2430_CONTROL_PADCONF_D2DIDLEACK_OFFSET 0x150 -#define OMAP2430_CONTROL_PADCONF_D2DSPARE0_OFFSET 0x151 -#define OMAP2430_CONTROL_PADCONF_AD2DSWRITE_OFFSET 0x152 -#define OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET 0x153 - -#define OMAP2430_CONTROL_PADCONF_MUX_SIZE \ - (OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET + 0x1) diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index c0ab9b2..dd893ec 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -87,7 +87,7 @@ void __init omap_barriers_init(void) dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA; dram_io_desc[0].pfn = __phys_to_pfn(paddr); dram_io_desc[0].length = size; - dram_io_desc[0].type = MT_MEMORY_SO; + dram_io_desc[0].type = MT_MEMORY_RW_SO; iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); dram_sync = (void __iomem *) dram_io_desc[0].virtual; sram_sync = (void __iomem *) OMAP4_SRAM_VA; diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index e0a398c..01ef59d 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -36,6 +36,7 @@ #include <linux/of.h> #include <linux/notifier.h> +#include "common.h" #include "soc.h" #include "omap_device.h" #include "omap_hwmod.h" @@ -204,6 +205,7 @@ static int _omap_device_notifier_call(struct notifier_block *nb, case BUS_NOTIFY_ADD_DEVICE: if (pdev->dev.of_node) omap_device_build_from_dt(pdev); + omap_auxdata_legacy_init(dev); /* fall through */ default: od = to_omap_device(pdev); diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index d8b9d60..2f15979 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -108,8 +108,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { /* I2C1 */ static struct omap_hwmod omap2420_i2c1_hwmod = { .name = "i2c1", - .mpu_irqs = omap2_i2c1_mpu_irqs, - .sdma_reqs = omap2_i2c1_sdma_reqs, .main_clk = "i2c1_fck", .prcm = { .omap2 = { @@ -133,8 +131,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = { /* I2C2 */ static struct omap_hwmod omap2420_i2c2_hwmod = { .name = "i2c2", - .mpu_irqs = omap2_i2c2_mpu_irqs, - .sdma_reqs = omap2_i2c2_sdma_reqs, .main_clk = "i2c2_fck", .prcm = { .omap2 = { @@ -179,16 +175,9 @@ static struct omap_mbox_pdata omap2420_mailbox_attrs = { .info = omap2420_mailbox_info, }; -static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { - { .name = "dsp", .irq = 26 + OMAP_INTC_START, }, - { .name = "iva", .irq = 34 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2420_mailbox_hwmod = { .name = "mailbox", .class = &omap2xxx_mailbox_hwmod_class, - .mpu_irqs = omap2420_mailbox_irqs, .main_clk = "mailboxes_ick", .prcm = { .omap2 = { @@ -217,17 +206,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { }; /* mcbsp1 */ -static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { - { .name = "tx", .irq = 59 + OMAP_INTC_START, }, - { .name = "rx", .irq = 60 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2420_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap2420_mcbsp_hwmod_class, - .mpu_irqs = omap2420_mcbsp1_irqs, - .sdma_reqs = omap2_mcbsp1_sdma_reqs, .main_clk = "mcbsp1_fck", .prcm = { .omap2 = { @@ -243,17 +224,9 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = { }; /* mcbsp2 */ -static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { - { .name = "tx", .irq = 62 + OMAP_INTC_START, }, - { .name = "rx", .irq = 63 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2420_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap2420_mcbsp_hwmod_class, - .mpu_irqs = omap2420_mcbsp2_irqs, - .sdma_reqs = omap2_mcbsp2_sdma_reqs, .main_clk = "mcbsp2_fck", .prcm = { .omap2 = { @@ -283,22 +256,9 @@ static struct omap_hwmod_class omap2420_msdi_hwmod_class = { }; /* msdi1 */ -static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = { - { .irq = 83 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = { - { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */ - { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */ - { .dma_req = -1 } -}; - static struct omap_hwmod omap2420_msdi1_hwmod = { .name = "msdi1", .class = &omap2420_msdi_hwmod_class, - .mpu_irqs = omap2420_msdi1_irqs, - .sdma_reqs = omap2420_msdi1_sdma_reqs, .main_clk = "mmc_fck", .prcm = { .omap2 = { @@ -315,7 +275,6 @@ static struct omap_hwmod omap2420_msdi1_hwmod = { /* HDQ1W/1-wire */ static struct omap_hwmod omap2420_hdq1w_hwmod = { .name = "hdq1w", - .mpu_irqs = omap2_hdq1w_mpu_irqs, .main_clk = "hdq_fck", .prcm = { .omap2 = { @@ -338,7 +297,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_i2c1_hwmod, .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -347,7 +305,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_i2c2_hwmod, .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -367,111 +324,51 @@ static struct omap_hwmod_ocp_if omap2420_l3__dsp = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { - { - .pa_start = 0x48028000, - .pa_end = 0x48028000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> timer1 */ static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_timer1_hwmod, .clk = "gpt1_ick", - .addr = omap2420_timer1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { - { - .pa_start = 0x48022000, - .pa_end = 0x4802207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_wd_timer2_hwmod, .clk = "mpu_wdt_ick", - .addr = omap2420_wd_timer2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio1 */ -static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { - { - .pa_start = 0x48018000, - .pa_end = 0x480181ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio1_hwmod, .clk = "gpios_ick", - .addr = omap2420_gpio1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio2 */ -static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { - { - .pa_start = 0x4801a000, - .pa_end = 0x4801a1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio2_hwmod, .clk = "gpios_ick", - .addr = omap2420_gpio2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio3 */ -static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { - { - .pa_start = 0x4801c000, - .pa_end = 0x4801c1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio3_hwmod, .clk = "gpios_ick", - .addr = omap2420_gpio3_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio4 */ -static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { - { - .pa_start = 0x4801e000, - .pa_end = 0x4801e1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio4_hwmod, .clk = "gpios_ick", - .addr = omap2420_gpio4_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -496,7 +393,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_mailbox_hwmod, - .addr = omap2_mailbox_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -505,7 +401,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_mcbsp1_hwmod, .clk = "mcbsp1_ick", - .addr = omap2_mcbsp1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -514,25 +409,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_mcbsp2_hwmod, .clk = "mcbsp2_ick", - .addr = omap2xxx_mcbsp2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = { - { - .pa_start = 0x4809c000, - .pa_end = 0x4809c000 + SZ_128 - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - /* l4_core -> msdi1 */ static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_msdi1_hwmod, .clk = "mmc_ick", - .addr = omap2420_msdi1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -541,36 +425,16 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_hdq1w_hwmod, .clk = "hdq_ick", - .addr = omap2_hdq1w_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, }; /* l4_wkup -> 32ksync_counter */ -static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = { - { - .pa_start = 0x48004000, - .pa_end = 0x4800401f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = { - { - .pa_start = 0x6800a000, - .pa_end = 0x6800afff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_counter_32k_hwmod, .clk = "sync_32k_ick", - .addr = omap2420_counter_32k_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -578,7 +442,6 @@ static struct omap_hwmod_ocp_if omap2420_l3__gpmc = { .master = &omap2xxx_l3_main_hwmod, .slave = &omap2xxx_gpmc_hwmod, .clk = "core_l3_ck", - .addr = omap2420_gpmc_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 5b90834..6d1b609 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -86,8 +86,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { static struct omap_hwmod omap2430_i2c1_hwmod = { .name = "i2c1", .flags = HWMOD_16BIT_REG, - .mpu_irqs = omap2_i2c1_mpu_irqs, - .sdma_reqs = omap2_i2c1_sdma_reqs, .main_clk = "i2chs1_fck", .prcm = { .omap2 = { @@ -114,8 +112,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = { static struct omap_hwmod omap2430_i2c2_hwmod = { .name = "i2c2", .flags = HWMOD_16BIT_REG, - .mpu_irqs = omap2_i2c2_mpu_irqs, - .sdma_reqs = omap2_i2c2_sdma_reqs, .main_clk = "i2chs2_fck", .prcm = { .omap2 = { @@ -131,15 +127,9 @@ static struct omap_hwmod omap2430_i2c2_hwmod = { }; /* gpio5 */ -static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { - { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */ - { .irq = -1 }, -}; - static struct omap_hwmod omap2430_gpio5_hwmod = { .name = "gpio5", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap243x_gpio5_irqs, .main_clk = "gpio5_fck", .prcm = { .omap2 = { @@ -182,15 +172,9 @@ static struct omap_mbox_pdata omap2430_mailbox_attrs = { .info = omap2430_mailbox_info, }; -static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { - { .irq = 26 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2430_mailbox_hwmod = { .name = "mailbox", .class = &omap2xxx_mailbox_hwmod_class, - .mpu_irqs = omap2430_mailbox_irqs, .main_clk = "mailboxes_ick", .prcm = { .omap2 = { @@ -205,27 +189,12 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { }; /* mcspi3 */ -static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { - { .irq = 91 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { - { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ - { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ - { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ - { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ - { .dma_req = -1 } -}; - static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { .num_chipselect = 2, }; static struct omap_hwmod omap2430_mcspi3_hwmod = { .name = "mcspi3", - .mpu_irqs = omap2430_mcspi3_mpu_irqs, - .sdma_reqs = omap2430_mcspi3_sdma_reqs, .main_clk = "mcspi3_fck", .prcm = { .omap2 = { @@ -259,16 +228,8 @@ static struct omap_hwmod_class usbotg_class = { }; /* usb_otg_hs */ -static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { - - { .name = "mc", .irq = 92 + OMAP_INTC_START, }, - { .name = "dma", .irq = 93 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2430_usbhsotg_hwmod = { .name = "usb_otg_hs", - .mpu_irqs = omap2430_usbhsotg_mpu_irqs, .main_clk = "usbhs_ick", .prcm = { .omap2 = { @@ -313,19 +274,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { }; /* mcbsp1 */ -static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { - { .name = "tx", .irq = 59 + OMAP_INTC_START, }, - { .name = "rx", .irq = 60 + OMAP_INTC_START, }, - { .name = "ovr", .irq = 61 + OMAP_INTC_START, }, - { .name = "common", .irq = 64 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2430_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp1_irqs, - .sdma_reqs = omap2_mcbsp1_sdma_reqs, .main_clk = "mcbsp1_fck", .prcm = { .omap2 = { @@ -341,18 +292,9 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = { }; /* mcbsp2 */ -static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { - { .name = "tx", .irq = 62 + OMAP_INTC_START, }, - { .name = "rx", .irq = 63 + OMAP_INTC_START, }, - { .name = "common", .irq = 16 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2430_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp2_irqs, - .sdma_reqs = omap2_mcbsp2_sdma_reqs, .main_clk = "mcbsp2_fck", .prcm = { .omap2 = { @@ -368,18 +310,9 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = { }; /* mcbsp3 */ -static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { - { .name = "tx", .irq = 89 + OMAP_INTC_START, }, - { .name = "rx", .irq = 90 + OMAP_INTC_START, }, - { .name = "common", .irq = 17 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod omap2430_mcbsp3_hwmod = { .name = "mcbsp3", .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp3_irqs, - .sdma_reqs = omap2_mcbsp3_sdma_reqs, .main_clk = "mcbsp3_fck", .prcm = { .omap2 = { @@ -395,24 +328,9 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = { }; /* mcbsp4 */ -static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { - { .name = "tx", .irq = 54 + OMAP_INTC_START, }, - { .name = "rx", .irq = 55 + OMAP_INTC_START, }, - { .name = "common", .irq = 18 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { - { .name = "rx", .dma_req = 20 }, - { .name = "tx", .dma_req = 19 }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap2430_mcbsp4_hwmod = { .name = "mcbsp4", .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp4_irqs, - .sdma_reqs = omap2430_mcbsp4_sdma_chs, .main_clk = "mcbsp4_fck", .prcm = { .omap2 = { @@ -428,24 +346,9 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = { }; /* mcbsp5 */ -static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { - { .name = "tx", .irq = 81 + OMAP_INTC_START, }, - { .name = "rx", .irq = 82 + OMAP_INTC_START, }, - { .name = "common", .irq = 19 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { - { .name = "rx", .dma_req = 22 }, - { .name = "tx", .dma_req = 21 }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap2430_mcbsp5_hwmod = { .name = "mcbsp5", .class = &omap2430_mcbsp_hwmod_class, - .mpu_irqs = omap2430_mcbsp5_irqs, - .sdma_reqs = omap2430_mcbsp5_sdma_chs, .main_clk = "mcbsp5_fck", .prcm = { .omap2 = { @@ -478,17 +381,6 @@ static struct omap_hwmod_class omap2430_mmc_class = { }; /* MMC/SD/SDIO1 */ -static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { - { .irq = 83 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { - { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ - { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { { .role = "dbck", .clk = "mmchsdb1_fck" }, }; @@ -500,8 +392,6 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = { static struct omap_hwmod omap2430_mmc1_hwmod = { .name = "mmc1", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2430_mmc1_mpu_irqs, - .sdma_reqs = omap2430_mmc1_sdma_reqs, .opt_clks = omap2430_mmc1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), .main_clk = "mmchs1_fck", @@ -519,17 +409,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { }; /* MMC/SD/SDIO2 */ -static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { - { .irq = 86 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { - { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ - { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { { .role = "dbck", .clk = "mmchsdb2_fck" }, }; @@ -537,8 +416,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { static struct omap_hwmod omap2430_mmc2_hwmod = { .name = "mmc2", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2430_mmc2_mpu_irqs, - .sdma_reqs = omap2430_mmc2_sdma_reqs, .opt_clks = omap2430_mmc2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), .main_clk = "mmchs2_fck", @@ -557,7 +434,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = { /* HDQ1W/1-wire */ static struct omap_hwmod omap2430_hdq1w_hwmod = { .name = "hdq1w", - .mpu_irqs = omap2_hdq1w_mpu_irqs, .main_clk = "hdq_fck", .prcm = { .omap2 = { @@ -589,7 +465,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_i2c1_hwmod, .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -598,25 +473,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_i2c2_hwmod, .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { - { - .pa_start = OMAP243X_HS_BASE, - .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_core ->usbhsotg interface */ static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_usbhsotg_hwmod, .clk = "usb_l4_ick", - .addr = omap2430_usbhsotg_addrs, .user = OCP_USER_MPU, }; @@ -625,7 +489,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mmc1_hwmod, .clk = "mmchs1_ick", - .addr = omap2430_mmc1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -634,7 +497,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mmc2_hwmod, .clk = "mmchs2_ick", - .addr = omap2430_mmc2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -643,7 +505,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mcspi3_hwmod, .clk = "mcspi3_ick", - .addr = omap2430_mcspi3_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -655,129 +516,59 @@ static struct omap_hwmod_ocp_if omap2430_l3__iva = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { - { - .pa_start = 0x49018000, - .pa_end = 0x49018000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> timer1 */ static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_timer1_hwmod, .clk = "gpt1_ick", - .addr = omap2430_timer1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { - { - .pa_start = 0x49016000, - .pa_end = 0x4901607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_wd_timer2_hwmod, .clk = "mpu_wdt_ick", - .addr = omap2430_wd_timer2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio1 */ -static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { - { - .pa_start = 0x4900C000, - .pa_end = 0x4900C1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio1_hwmod, .clk = "gpios_ick", - .addr = omap2430_gpio1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio2 */ -static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { - { - .pa_start = 0x4900E000, - .pa_end = 0x4900E1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio2_hwmod, .clk = "gpios_ick", - .addr = omap2430_gpio2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio3 */ -static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { - { - .pa_start = 0x49010000, - .pa_end = 0x490101ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio3_hwmod, .clk = "gpios_ick", - .addr = omap2430_gpio3_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_wkup -> gpio4 */ -static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { - { - .pa_start = 0x49012000, - .pa_end = 0x490121ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_gpio4_hwmod, .clk = "gpios_ick", - .addr = omap2430_gpio4_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_core -> gpio5 */ -static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { - { - .pa_start = 0x480B6000, - .pa_end = 0x480B61ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_gpio5_hwmod, .clk = "gpio5_ick", - .addr = omap2430_gpio5_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -802,7 +593,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mailbox_hwmod, - .addr = omap2_mailbox_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -811,7 +601,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mcbsp1_hwmod, .clk = "mcbsp1_ick", - .addr = omap2_mcbsp1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -820,64 +609,30 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mcbsp2_hwmod, .clk = "mcbsp2_ick", - .addr = omap2xxx_mcbsp2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4808C000, - .pa_end = 0x4808C0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_core -> mcbsp3 */ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mcbsp3_hwmod, .clk = "mcbsp3_ick", - .addr = omap2430_mcbsp3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4808E000, - .pa_end = 0x4808E0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_core -> mcbsp4 */ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mcbsp4_hwmod, .clk = "mcbsp4_ick", - .addr = omap2430_mcbsp4_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { - { - .name = "mpu", - .pa_start = 0x48096000, - .pa_end = 0x480960ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_core -> mcbsp5 */ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_mcbsp5_hwmod, .clk = "mcbsp5_ick", - .addr = omap2430_mcbsp5_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -886,35 +641,15 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_hdq1w_hwmod, .clk = "hdq_ick", - .addr = omap2_hdq1w_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, }; /* l4_wkup -> 32ksync_counter */ -static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = { - { - .pa_start = 0x49020000, - .pa_end = 0x4902001f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = { - { - .pa_start = 0x6e000000, - .pa_end = 0x6e000fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_counter_32k_hwmod, .clk = "sync_32k_ick", - .addr = omap2430_counter_32k_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -922,7 +657,6 @@ static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { .master = &omap2xxx_l3_main_hwmod, .slave = &omap2xxx_gpmc_hwmod, .clk = "core_l3_ck", - .addr = omap2430_gpmc_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c index 5fd40d4..656861c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c @@ -20,142 +20,6 @@ #include "omap_hwmod_common_data.h" -static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { - { - .pa_start = OMAP2_UART1_BASE, - .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { - { - .pa_start = OMAP2_UART2_BASE, - .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { - { - .pa_start = OMAP2_UART3_BASE, - .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { - { - .pa_start = 0x4802a000, - .pa_end = 0x4802a000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { - { - .pa_start = 0x48078000, - .pa_end = 0x48078000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { - { - .pa_start = 0x4807a000, - .pa_end = 0x4807a000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { - { - .pa_start = 0x4807c000, - .pa_end = 0x4807c000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { - { - .pa_start = 0x4807e000, - .pa_end = 0x4807e000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { - { - .pa_start = 0x48080000, - .pa_end = 0x48080000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { - { - .pa_start = 0x48082000, - .pa_end = 0x48082000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = { - { - .pa_start = 0x48084000, - .pa_end = 0x48084000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = { - { - .name = "mpu", - .pa_start = 0x48076000, - .pa_end = 0x480760ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2_rng_addr_space[] = { - { - .pa_start = 0x480a0000, - .pa_end = 0x480a004f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = { - { - .pa_start = 0x480a4000, - .pa_end = 0x480a4000 + 0x64 - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = { - { - .pa_start = 0x480a6000, - .pa_end = 0x480a6000 + 0x50 - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* * Common interconnect data */ @@ -182,7 +46,7 @@ struct omap_hwmod_ocp_if omap2xxx_dss__l3 = { .omap2 = { .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, .flags = OMAP_FIREWALL_L3, - } + }, }, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -199,7 +63,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_uart1_hwmod, .clk = "uart1_ick", - .addr = omap2xxx_uart1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -208,7 +71,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_uart2_hwmod, .clk = "uart2_ick", - .addr = omap2xxx_uart2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -217,7 +79,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_uart3_hwmod, .clk = "uart3_ick", - .addr = omap2xxx_uart3_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -226,7 +87,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_mcspi1_hwmod, .clk = "mcspi1_ick", - .addr = omap2_mcspi1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -235,7 +95,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_mcspi2_hwmod, .clk = "mcspi2_ick", - .addr = omap2_mcspi2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -244,7 +103,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer2_hwmod, .clk = "gpt2_ick", - .addr = omap2xxx_timer2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -253,7 +111,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer3_hwmod, .clk = "gpt3_ick", - .addr = omap2xxx_timer3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -262,7 +119,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer4_hwmod, .clk = "gpt4_ick", - .addr = omap2xxx_timer4_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -271,7 +127,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer5_hwmod, .clk = "gpt5_ick", - .addr = omap2xxx_timer5_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -280,7 +135,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer6_hwmod, .clk = "gpt6_ick", - .addr = omap2xxx_timer6_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -289,7 +143,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer7_hwmod, .clk = "gpt7_ick", - .addr = omap2xxx_timer7_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -298,7 +151,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer8_hwmod, .clk = "gpt8_ick", - .addr = omap2xxx_timer8_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -307,7 +159,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer9_hwmod, .clk = "gpt9_ick", - .addr = omap2xxx_timer9_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -316,7 +167,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer10_hwmod, .clk = "gpt10_ick", - .addr = omap2_timer10_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -325,7 +175,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer11_hwmod, .clk = "gpt11_ick", - .addr = omap2_timer11_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -334,7 +183,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_timer12_hwmod, .clk = "gpt12_ick", - .addr = omap2xxx_timer12_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -348,7 +196,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = { .omap2 = { .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, .flags = OMAP_FIREWALL_L4, - } + }, }, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -363,7 +211,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = { .omap2 = { .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, .flags = OMAP_FIREWALL_L4, - } + }, }, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -378,7 +226,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = { .omap2 = { .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, .flags = OMAP_FIREWALL_L4, - } + }, }, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -393,7 +241,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = { .omap2 = { .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, .flags = OMAP_FIREWALL_L4, - } + }, }, .flags = OCPIF_SWSUP_IDLE, .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -404,7 +252,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_rng_hwmod, .clk = "rng_ick", - .addr = omap2_rng_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -413,7 +260,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_sham_hwmod, .clk = "sha_ick", - .addr = omap2xxx_sham_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -422,6 +268,5 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2xxx_aes_hwmod, .clk = "aes_ick", - .addr = omap2xxx_aes_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index d23c77f..8821b9d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -20,14 +20,9 @@ #include "prm-regbits-24xx.h" #include "wd_timer.h" -struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { - { .irq = 48 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { { .name = "dispc", .dma_req = 5 }, - { .dma_req = -1 } + { .dma_req = -1, }, }; /* @@ -219,14 +214,8 @@ struct omap_hwmod omap2xxx_l4_wkup_hwmod = { }; /* MPU */ -static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = { - { .name = "pmu", .irq = 3 + OMAP_INTC_START }, - { .irq = -1 } -}; - struct omap_hwmod omap2xxx_mpu_hwmod = { .name = "mpu", - .mpu_irqs = omap2xxx_mpu_irqs, .class = &mpu_hwmod_class, .main_clk = "mpu_ck", }; @@ -256,7 +245,6 @@ static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { struct omap_hwmod omap2xxx_timer1_hwmod = { .name = "timer1", - .mpu_irqs = omap2_timer1_mpu_irqs, .main_clk = "gpt1_fck", .prcm = { .omap2 = { @@ -276,7 +264,6 @@ struct omap_hwmod omap2xxx_timer1_hwmod = { struct omap_hwmod omap2xxx_timer2_hwmod = { .name = "timer2", - .mpu_irqs = omap2_timer2_mpu_irqs, .main_clk = "gpt2_fck", .prcm = { .omap2 = { @@ -295,7 +282,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = { struct omap_hwmod omap2xxx_timer3_hwmod = { .name = "timer3", - .mpu_irqs = omap2_timer3_mpu_irqs, .main_clk = "gpt3_fck", .prcm = { .omap2 = { @@ -314,7 +300,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = { struct omap_hwmod omap2xxx_timer4_hwmod = { .name = "timer4", - .mpu_irqs = omap2_timer4_mpu_irqs, .main_clk = "gpt4_fck", .prcm = { .omap2 = { @@ -333,7 +318,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = { struct omap_hwmod omap2xxx_timer5_hwmod = { .name = "timer5", - .mpu_irqs = omap2_timer5_mpu_irqs, .main_clk = "gpt5_fck", .prcm = { .omap2 = { @@ -353,7 +337,6 @@ struct omap_hwmod omap2xxx_timer5_hwmod = { struct omap_hwmod omap2xxx_timer6_hwmod = { .name = "timer6", - .mpu_irqs = omap2_timer6_mpu_irqs, .main_clk = "gpt6_fck", .prcm = { .omap2 = { @@ -373,7 +356,6 @@ struct omap_hwmod omap2xxx_timer6_hwmod = { struct omap_hwmod omap2xxx_timer7_hwmod = { .name = "timer7", - .mpu_irqs = omap2_timer7_mpu_irqs, .main_clk = "gpt7_fck", .prcm = { .omap2 = { @@ -393,7 +375,6 @@ struct omap_hwmod omap2xxx_timer7_hwmod = { struct omap_hwmod omap2xxx_timer8_hwmod = { .name = "timer8", - .mpu_irqs = omap2_timer8_mpu_irqs, .main_clk = "gpt8_fck", .prcm = { .omap2 = { @@ -413,7 +394,6 @@ struct omap_hwmod omap2xxx_timer8_hwmod = { struct omap_hwmod omap2xxx_timer9_hwmod = { .name = "timer9", - .mpu_irqs = omap2_timer9_mpu_irqs, .main_clk = "gpt9_fck", .prcm = { .omap2 = { @@ -433,7 +413,6 @@ struct omap_hwmod omap2xxx_timer9_hwmod = { struct omap_hwmod omap2xxx_timer10_hwmod = { .name = "timer10", - .mpu_irqs = omap2_timer10_mpu_irqs, .main_clk = "gpt10_fck", .prcm = { .omap2 = { @@ -453,7 +432,6 @@ struct omap_hwmod omap2xxx_timer10_hwmod = { struct omap_hwmod omap2xxx_timer11_hwmod = { .name = "timer11", - .mpu_irqs = omap2_timer11_mpu_irqs, .main_clk = "gpt11_fck", .prcm = { .omap2 = { @@ -473,7 +451,6 @@ struct omap_hwmod omap2xxx_timer11_hwmod = { struct omap_hwmod omap2xxx_timer12_hwmod = { .name = "timer12", - .mpu_irqs = omap2xxx_timer12_mpu_irqs, .main_clk = "gpt12_fck", .prcm = { .omap2 = { @@ -509,8 +486,6 @@ struct omap_hwmod omap2xxx_wd_timer2_hwmod = { struct omap_hwmod omap2xxx_uart1_hwmod = { .name = "uart1", - .mpu_irqs = omap2_uart1_mpu_irqs, - .sdma_reqs = omap2_uart1_sdma_reqs, .main_clk = "uart1_fck", .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, .prcm = { @@ -529,8 +504,6 @@ struct omap_hwmod omap2xxx_uart1_hwmod = { struct omap_hwmod omap2xxx_uart2_hwmod = { .name = "uart2", - .mpu_irqs = omap2_uart2_mpu_irqs, - .sdma_reqs = omap2_uart2_sdma_reqs, .main_clk = "uart2_fck", .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT, .prcm = { @@ -549,8 +522,6 @@ struct omap_hwmod omap2xxx_uart2_hwmod = { struct omap_hwmod omap2xxx_uart3_hwmod = { .name = "uart3", - .mpu_irqs = omap2_uart3_mpu_irqs, - .sdma_reqs = omap2_uart3_sdma_reqs, .main_clk = "uart3_fck", .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT, .prcm = { @@ -610,7 +581,7 @@ struct omap_hwmod omap2xxx_dss_dispc_hwmod = { }, }, .flags = HWMOD_NO_IDLEST, - .dev_attr = &omap2_3_dss_dispc_dev_attr + .dev_attr = &omap2_3_dss_dispc_dev_attr, }; static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { @@ -657,7 +628,6 @@ struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = { struct omap_hwmod omap2xxx_gpio1_hwmod = { .name = "gpio1", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio1_irqs, .main_clk = "gpios_fck", .prcm = { .omap2 = { @@ -676,7 +646,6 @@ struct omap_hwmod omap2xxx_gpio1_hwmod = { struct omap_hwmod omap2xxx_gpio2_hwmod = { .name = "gpio2", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio2_irqs, .main_clk = "gpios_fck", .prcm = { .omap2 = { @@ -695,7 +664,6 @@ struct omap_hwmod omap2xxx_gpio2_hwmod = { struct omap_hwmod omap2xxx_gpio3_hwmod = { .name = "gpio3", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio3_irqs, .main_clk = "gpios_fck", .prcm = { .omap2 = { @@ -714,7 +682,6 @@ struct omap_hwmod omap2xxx_gpio3_hwmod = { struct omap_hwmod omap2xxx_gpio4_hwmod = { .name = "gpio4", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio4_irqs, .main_clk = "gpios_fck", .prcm = { .omap2 = { @@ -736,8 +703,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { struct omap_hwmod omap2xxx_mcspi1_hwmod = { .name = "mcspi1", - .mpu_irqs = omap2_mcspi1_mpu_irqs, - .sdma_reqs = omap2_mcspi1_sdma_reqs, .main_clk = "mcspi1_fck", .prcm = { .omap2 = { @@ -759,8 +724,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { struct omap_hwmod omap2xxx_mcspi2_hwmod = { .name = "mcspi2", - .mpu_irqs = omap2_mcspi2_mpu_irqs, - .sdma_reqs = omap2_mcspi2_sdma_reqs, .main_clk = "mcspi2_fck", .prcm = { .omap2 = { @@ -795,15 +758,9 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = { }; /* gpmc */ -static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = { - { .irq = 20 + OMAP_INTC_START, }, - { .irq = -1 } -}; - struct omap_hwmod omap2xxx_gpmc_hwmod = { .name = "gpmc", .class = &omap2xxx_gpmc_hwmod_class, - .mpu_irqs = omap2xxx_gpmc_irqs, .main_clk = "gpmc_fck", /* * XXX HWMOD_INIT_NO_RESET should not be needed for this IP @@ -840,14 +797,8 @@ static struct omap_hwmod_class omap2_rng_hwmod_class = { .sysc = &omap2_rng_sysc, }; -static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = { - { .irq = 52 + OMAP_INTC_START, }, - { .irq = -1 } -}; - struct omap_hwmod omap2xxx_rng_hwmod = { .name = "rng", - .mpu_irqs = omap2_rng_mpu_irqs, .main_clk = "l4_ck", .prcm = { .omap2 = { @@ -884,20 +835,8 @@ static struct omap_hwmod_class omap2xxx_sham_class = { .sysc = &omap2_sham_sysc, }; -static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = { - { .irq = 51 + OMAP_INTC_START, }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = { - { .name = "rx", .dma_req = 13 }, - { .dma_req = -1 } -}; - struct omap_hwmod omap2xxx_sham_hwmod = { .name = "sham", - .mpu_irqs = omap2_sham_mpu_irqs, - .sdma_reqs = omap2_sham_sdma_chs, .main_clk = "l4_ck", .prcm = { .omap2 = { @@ -927,15 +866,8 @@ static struct omap_hwmod_class omap2xxx_aes_class = { .sysc = &omap2_aes_sysc, }; -static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = { - { .name = "tx", .dma_req = 9 }, - { .name = "rx", .dma_req = 10 }, - { .dma_req = -1 } -}; - struct omap_hwmod omap2xxx_aes_hwmod = { .name = "aes", - .sdma_reqs = omap2_aes_sdma_chs, .main_clk = "l4_ck", .prcm = { .omap2 = { diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index 6e04ff7..2c38c6b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -18,9 +18,6 @@ #include "common.h" #include "display.h" -/* Common address space across OMAP2xxx */ -extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[]; - /* Common address space across OMAP2xxx/3xxx */ extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[]; extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[]; @@ -41,8 +38,6 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[]; extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[]; /* Common IP block data across OMAP2xxx */ -extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[]; -extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[]; extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr; extern struct omap_hwmod omap2xxx_l3_main_hwmod; extern struct omap_hwmod omap2xxx_l4_core_hwmod; diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 39f020c..3d5b24d 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -8,6 +8,7 @@ * published by the Free Software Foundation. */ #include <linux/clk.h> +#include <linux/davinci_emac.h> #include <linux/gpio.h> #include <linux/init.h> #include <linux/kernel.h> @@ -16,6 +17,7 @@ #include <linux/platform_data/pinctrl-single.h> +#include "am35xx.h" #include "common.h" #include "common-board-devices.h" #include "dss-common.h" @@ -26,6 +28,9 @@ struct pdata_init { void (*fn)(void); }; +struct of_dev_auxdata omap_auxdata_lookup[]; +static struct twl4030_gpio_platform_data twl_gpio_auxdata; + /* * Create alias for USB host PHY clock. * Remove this when clock phandle can be provided via DT @@ -68,6 +73,15 @@ static inline void legacy_init_wl12xx(unsigned ref_clock, } #endif +#ifdef CONFIG_MACH_NOKIA_N8X0 +static void __init omap2420_n8x0_legacy_init(void) +{ + omap_auxdata_lookup[0].platform_data = n8x0_legacy_init(); +} +#else +#define omap2420_n8x0_legacy_init NULL +#endif + #ifdef CONFIG_ARCH_OMAP3 static void __init hsmmc2_internal_input_clk(void) { @@ -78,6 +92,33 @@ static void __init hsmmc2_internal_input_clk(void) omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1); } +static int omap3_sbc_t3730_twl_callback(struct device *dev, + unsigned gpio, + unsigned ngpio) +{ + int res; + + res = gpio_request_one(gpio + 2, GPIOF_OUT_INIT_HIGH, + "wlan rst"); + if (res) + return res; + + gpio_export(gpio, 0); + + return 0; +} + +static void __init omap3_sbc_t3730_twl_init(void) +{ + twl_gpio_auxdata.setup = omap3_sbc_t3730_twl_callback; +} + +static void __init omap3_sbc_t3730_legacy_init(void) +{ + legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 136); + omap_ads7846_init(1, 57, 0, NULL); +} + static void __init omap3_igep0020_legacy_init(void) { omap3_igep2_display_init_of(); @@ -92,6 +133,42 @@ static void __init omap3_zoom_legacy_init(void) { legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162); } + +static void am35xx_enable_emac_int(void) +{ + u32 v; + + v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR | + AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR); + omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR); + omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */ +} + +static void am35xx_disable_emac_int(void) +{ + u32 v; + + v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR); + omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR); + omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */ +} + +static struct emac_platform_data am35xx_emac_pdata = { + .interrupt_enable = am35xx_enable_emac_int, + .interrupt_disable = am35xx_disable_emac_int, +}; + +static void __init am3517_evm_legacy_init(void) +{ + u32 v; + + v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); + v &= ~AM35XX_CPGMACSS_SW_RST; + omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET); + omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */ +} #endif /* CONFIG_ARCH_OMAP3 */ #ifdef CONFIG_ARCH_OMAP4 @@ -125,10 +202,48 @@ void omap_pcs_legacy_init(int irq, void (*rearm)(void)) pcs_pdata.rearm = rearm; } +/* + * GPIOs for TWL are initialized by the I2C bus and need custom + * handing until DSS has device tree bindings. + */ +void omap_auxdata_legacy_init(struct device *dev) +{ + if (dev->platform_data) + return; + + if (strcmp("twl4030-gpio", dev_name(dev))) + return; + + dev->platform_data = &twl_gpio_auxdata; +} + +/* + * Few boards still need auxdata populated before we populate + * the dev entries in of_platform_populate(). + */ +static struct pdata_init auxdata_quirks[] __initdata = { +#ifdef CONFIG_SOC_OMAP2420 + { "nokia,n800", omap2420_n8x0_legacy_init, }, + { "nokia,n810", omap2420_n8x0_legacy_init, }, + { "nokia,n810-wimax", omap2420_n8x0_legacy_init, }, +#endif +#ifdef CONFIG_ARCH_OMAP3 + { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_twl_init, }, +#endif + { /* sentinel */ }, +}; + struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { +#ifdef CONFIG_MACH_NOKIA_N8X0 + OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL), +#endif #ifdef CONFIG_ARCH_OMAP3 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata), OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata), + /* Only on am3517 */ + OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL), + OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0", + &am35xx_emac_pdata), #endif #ifdef CONFIG_ARCH_OMAP4 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata), @@ -137,14 +252,20 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { { /* sentinel */ }, }; +/* + * Few boards still need to initialize some legacy devices with + * platform data until the drivers support device tree. + */ static struct pdata_init pdata_quirks[] __initdata = { #ifdef CONFIG_ARCH_OMAP3 + { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_legacy_init, }, { "nokia,omap3-n900", hsmmc2_internal_input_clk, }, { "nokia,omap3-n9", hsmmc2_internal_input_clk, }, { "nokia,omap3-n950", hsmmc2_internal_input_clk, }, { "isee,omap3-igep0020", omap3_igep0020_legacy_init, }, { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, { "ti,omap3-zoom3", omap3_zoom_legacy_init, }, + { "ti,am3517-evm", am3517_evm_legacy_init, }, #endif #ifdef CONFIG_ARCH_OMAP4 { "ti,omap4-sdp", omap4_sdp_legacy_init, }, @@ -156,14 +277,8 @@ static struct pdata_init pdata_quirks[] __initdata = { { /* sentinel */ }, }; -void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table) +static void pdata_quirks_check(struct pdata_init *quirks) { - struct pdata_init *quirks = pdata_quirks; - - omap_sdrc_init(NULL, NULL); - of_platform_populate(NULL, omap_dt_match_table, - omap_auxdata_lookup, NULL); - while (quirks->compatible) { if (of_machine_is_compatible(quirks->compatible)) { if (quirks->fn) @@ -173,3 +288,12 @@ void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table) quirks++; } } + +void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table) +{ + omap_sdrc_init(NULL, NULL); + pdata_quirks_check(auxdata_quirks); + of_platform_populate(NULL, omap_dt_match_table, + omap_auxdata_lookup, NULL); + pdata_quirks_check(pdata_quirks); +} diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 3ca81e0..ec084d1 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -379,7 +379,7 @@ static struct clocksource clocksource_gpt = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; -static u32 notrace dmtimer_read_sched_clock(void) +static u64 notrace dmtimer_read_sched_clock(void) { if (clksrc.reserved) return __omap_dm_timer_read_counter(&clksrc, @@ -471,7 +471,7 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id, __omap_dm_timer_load_start(&clksrc, OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, OMAP_TIMER_NONPOSTED); - setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); + sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate); if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) pr_err("Could not register clocksource %s\n", diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index b91002c..c134a82 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -21,7 +21,7 @@ #include <plat/irq.h> #include "common.h" -struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = { +static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL), OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0", NULL), diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 91a5852..3f1de11 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -24,7 +24,6 @@ #include <asm/page.h> #include <asm/setup.h> #include <asm/system_misc.h> -#include <asm/timex.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -135,7 +134,7 @@ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) /***************************************************************************** * SPI ****************************************************************************/ -void __init orion5x_spi_init() +void __init orion5x_spi_init(void) { orion_spi_init(SPI_PHYS_BASE); } @@ -185,7 +184,7 @@ static void __init orion5x_crypto_init(void) /***************************************************************************** * Watchdog ****************************************************************************/ -void __init orion5x_wdt_init(void) +static void __init orion5x_wdt_init(void) { orion_wdt_init(); } @@ -246,7 +245,7 @@ void orion5x_setup_wins(void) int orion5x_tclk; -int __init orion5x_find_tclk(void) +static int __init orion5x_find_tclk(void) { u32 dev, rev; diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 4b2aefd..dc01c4f 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -202,7 +202,7 @@ __initcall(db88f5281_7seg_init); * PCI ****************************************************************************/ -void __init db88f5281_pci_preinit(void) +static void __init db88f5281_pci_preinit(void) { int pin; diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index 30a192b..9654b0c 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -16,6 +16,7 @@ #include <mach/bridge-regs.h> #include <plat/orion-gpio.h> #include <plat/irq.h> +#include "common.h" static int __initdata gpio0_irqs[4] = { IRQ_ORION5X_GPIO_0_7, diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 7fab670..87a12d6 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -240,11 +240,11 @@ static int __init pcie_setup(struct pci_sys_data *sys) #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ - ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) + ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL) #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ - ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) + ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL) #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index b1cf684..b576ef5 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -108,7 +108,7 @@ static struct platform_device rd88f5182_gpio_leds = { * PCI ****************************************************************************/ -void __init rd88f5182_pci_preinit(void) +static void __init rd88f5182_pci_preinit(void) { int pin; diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index 7e90648..6208d12 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -77,7 +77,7 @@ static struct platform_device tsp2_nor_flash = { #define TSP2_PCI_SLOT0_OFFS 7 #define TSP2_PCI_SLOT0_IRQ_PIN 11 -void __init tsp2_pci_preinit(void) +static void __init tsp2_pci_preinit(void) { int pin; diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index e90c061..9136797 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -106,7 +106,7 @@ static struct platform_device qnap_ts209_nor_flash = { #define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6 #define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7 -void __init qnap_ts209_pci_preinit(void) +static void __init qnap_ts209_pci_preinit(void) { int pin; diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index e960855..db16dae 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -57,7 +57,7 @@ static struct map_desc ts78xx_io_desc[] __initdata = { }, }; -void __init ts78xx_map_io(void) +static void __init ts78xx_map_io(void) { orion5x_map_io(); iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc)); diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c index 3dbcb1a..e358b07 100644 --- a/arch/arm/mach-prima2/platsmp.c +++ b/arch/arm/mach-prima2/platsmp.c @@ -106,8 +106,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle) * "cpu" is Linux's internal ID. */ pen_release = cpu_logical_map(cpu); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + sync_cache_w(&pen_release); /* * Send the secondary CPU SEV, thereby causing the boot monitor to read diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c index ffa6d81..12fb0f4 100644 --- a/arch/arm/mach-pxa/am200epd.c +++ b/arch/arm/mach-pxa/am200epd.c @@ -293,8 +293,7 @@ static int am200_setup_irq(struct fb_info *info) int ret; ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am200_handle_irq, - IRQF_DISABLED|IRQF_TRIGGER_FALLING, - "AM200", info->par); + IRQF_TRIGGER_FALLING, "AM200", info->par); if (ret) dev_err(&am200_device->dev, "request_irq failed: %d\n", ret); diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c index 3dfec1e..c9f309a 100644 --- a/arch/arm/mach-pxa/am300epd.c +++ b/arch/arm/mach-pxa/am300epd.c @@ -241,8 +241,7 @@ static int am300_setup_irq(struct fb_info *info) struct broadsheetfb_par *par = info->par; ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am300_handle_irq, - IRQF_DISABLED|IRQF_TRIGGER_RISING, - "AM300", par); + IRQF_TRIGGER_RISING, "AM300", par); if (ret) dev_err(&am300_device->dev, "request_irq failed: %d\n", ret); diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 8eb4e23..6915a9f 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -564,8 +564,7 @@ static int em_x270_mci_init(struct device *dev, } err = request_irq(gpio_to_irq(mmc_cd), em_x270_detect_int, - IRQF_DISABLED | IRQF_TRIGGER_RISING | - IRQF_TRIGGER_FALLING, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "MMC card detect", data); if (err) { dev_err(dev, "can't request MMC card detect IRQ: %d\n", err); diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index b6cc181..0eecd83 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -235,8 +235,6 @@ static const struct of_device_id intc_ids[] __initconst = { void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) { struct device_node *node; - const struct of_device_id *of_id; - struct pxa_intc_conf *conf; struct resource res; int n, ret; @@ -245,8 +243,6 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) pr_err("Failed to find interrupt controller in arch-pxa\n"); return; } - of_id = of_match_node(intc_ids, node); - conf = of_id->data; ret = of_property_read_u32(node, "marvell,intc-nr-irqs", &pxa_internal_irq_nr); diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index fab30d6..a9761c2 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -634,7 +634,7 @@ static struct platform_device bq24022 = { static int magician_mci_init(struct device *dev, irq_handler_t detect_irq, void *data) { - return request_irq(IRQ_MAGICIAN_SD, detect_irq, IRQF_DISABLED, + return request_irq(IRQ_MAGICIAN_SD, detect_irq, 0, "mmc card detect", data); } diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 08ccc07..78b84c0 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -401,7 +401,7 @@ static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_in */ MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL; - err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED, + err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, 0, "MMC card detect", data); if (err) printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 9a4e470..2897da2 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -327,7 +327,7 @@ static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int, { int err; - err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, IRQF_DISABLED, + err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, 0, "MMC card detect", data); if (err) printk(KERN_ERR "pcm990_mci_init: MMC/SD: can't request MMC " diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index 0a36d35..051a655 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -860,18 +860,18 @@ static int sharpsl_pm_probe(struct platform_device *pdev) /* Register interrupt handlers */ irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_acin); - if (request_irq(irq, sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) { + if (request_irq(irq, sharpsl_ac_isr, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) { dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq); } irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batlock); - if (request_irq(irq, sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) { + if (request_irq(irq, sharpsl_fatal_isr, IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) { dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq); } if (sharpsl_pm.machinfo->gpio_fatal) { irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_fatal); - if (request_irq(irq, sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) { + if (request_irq(irq, sharpsl_fatal_isr, IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) { dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq); } } @@ -879,7 +879,7 @@ static int sharpsl_pm_probe(struct platform_device *pdev) if (sharpsl_pm.machinfo->batfull_irq) { /* Register interrupt handler. */ irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batfull); - if (request_irq(irq, sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) { + if (request_irq(irq, sharpsl_chrg_full_isr, IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) { dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq); } } diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 9aa852a..fca174e 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -33,7 +33,7 @@ * calls to sched_clock() which should always be the case in practice. */ -static u32 notrace pxa_read_sched_clock(void) +static u64 notrace pxa_read_sched_clock(void) { return readl_relaxed(OSCR); } @@ -137,7 +137,7 @@ static struct clock_event_device ckevt_pxa_osmr0 = { static struct irqaction pxa_ost0_irq = { .name = "ost0", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_TIMER | IRQF_IRQPOLL, .handler = pxa_ost0_interrupt, .dev_id = &ckevt_pxa_osmr0, }; @@ -149,7 +149,7 @@ void __init pxa_timer_init(void) writel_relaxed(0, OIER); writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); - setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate); + sched_clock_register(pxa_read_sched_clock, 32, clock_tick_rate); ckevt_pxa_osmr0.cpumask = cpumask_of(0); diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index c580434..872dcb2 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -332,8 +332,7 @@ static int trizeps4_mci_init(struct device *dev, irq_handler_t mci_detect_int, int err; err = request_irq(TRIZEPS4_MMC_IRQ, mci_detect_int, - IRQF_DISABLED | IRQF_TRIGGER_RISING, - "MMC card detect", data); + IRQF_TRIGGER_RISING, "MMC card detect", data); if (err) { printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request" "MMC card detect IRQ\n"); diff --git a/arch/arm/mach-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c index 4a65cba..a8dafc1 100644 --- a/arch/arm/mach-s3c24xx/dma.c +++ b/arch/arm/mach-s3c24xx/dma.c @@ -742,7 +742,7 @@ int s3c2410_dma_request(enum dma_ch channel, chan->irq_claimed = 1; local_irq_restore(flags); - err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED, + err = request_irq(chan->irq, s3c2410_dma_irq, 0, client->name, (void *)chan); local_irq_save(flags); diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c24xx/simtec-usb.c index 8dea917..b70aa66 100644 --- a/arch/arm/mach-s3c24xx/simtec-usb.c +++ b/arch/arm/mach-s3c24xx/simtec-usb.c @@ -79,8 +79,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on) if (on) { ret = request_irq(BAST_IRQ_USBOC, usb_simtec_ocirq, - IRQF_DISABLED | IRQF_TRIGGER_RISING | - IRQF_TRIGGER_FALLING, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "USB Over-current", info); if (ret != 0) { printk(KERN_ERR "failed to request usb oc irq\n"); diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c index 8c84d34..8d553a4 100644 --- a/arch/arm/mach-s3c64xx/mach-mini6410.c +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c @@ -37,7 +37,9 @@ #include <plat/devs.h> #include <plat/fb.h> #include <linux/platform_data/mtd-nand-s3c2410.h> +#include <linux/platform_data/mmc-sdhci-s3c.h> #include <plat/regs-serial.h> +#include <plat/sdhci.h> #include <linux/platform_data/touchscreen-s3c2410.h> #include <video/platform_lcd.h> @@ -215,6 +217,13 @@ static struct platform_device mini6410_lcd_powerdev = { .dev.platform_data = &mini6410_lcd_power_data, }; +static struct s3c_sdhci_platdata mini6410_hsmmc1_pdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S3C64XX_GPN(10), + .ext_cd_gpio_invert = true, +}; + static struct platform_device *mini6410_devices[] __initdata = { &mini6410_device_eth, &s3c_device_hsmmc0, @@ -322,6 +331,7 @@ static void __init mini6410_machine_init(void) s3c_nand_set_platdata(&mini6410_nand_info); s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]); + s3c_sdhci1_set_platdata(&mini6410_hsmmc1_pdata); s3c24xx_ts_set_platdata(NULL); /* configure nCS1 width to 16 bits */ diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c index 5629df9..6e72bd5 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.c +++ b/arch/arm/mach-s3c64xx/mach-smartq.c @@ -107,7 +107,7 @@ static void smartq_usb_host_enableoc(struct s3c2410_hcd_info *info, int on) if (on) { ret = request_irq(gpio_to_irq(S3C64XX_GPL(10)), - smartq_usb_host_ocirq, IRQF_DISABLED | + smartq_usb_host_ocirq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "USB host overcurrent", info); if (ret != 0) diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index c9808c6..8443a27 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -75,12 +75,143 @@ void ASSABET_BCR_frob(unsigned int mask, unsigned int val) EXPORT_SYMBOL(ASSABET_BCR_frob); +/* + * The codec reset goes to three devices, so we need to release + * the rest when any one of these requests it. However, that + * causes the ADV7171 to consume around 100mA - more than half + * the LCD-blanked power. + * + * With the ADV7171, LCD and backlight enabled, we go over + * budget on the MAX846 Li-Ion charger, and if no Li-Ion battery + * is connected, the Assabet crashes. + */ +#define RST_UCB1X00 (1 << 0) +#define RST_UDA1341 (1 << 1) +#define RST_ADV7171 (1 << 2) + +#define SDA GPIO_GPIO(15) +#define SCK GPIO_GPIO(18) +#define MOD GPIO_GPIO(17) + +static void adv7171_start(void) +{ + GPSR = SCK; + udelay(1); + GPSR = SDA; + udelay(2); + GPCR = SDA; +} + +static void adv7171_stop(void) +{ + GPSR = SCK; + udelay(2); + GPSR = SDA; + udelay(1); +} + +static void adv7171_send(unsigned byte) +{ + unsigned i; + + for (i = 0; i < 8; i++, byte <<= 1) { + GPCR = SCK; + udelay(1); + if (byte & 0x80) + GPSR = SDA; + else + GPCR = SDA; + udelay(1); + GPSR = SCK; + udelay(1); + } + GPCR = SCK; + udelay(1); + GPSR = SDA; + udelay(1); + GPDR &= ~SDA; + GPSR = SCK; + udelay(1); + if (GPLR & SDA) + printk(KERN_WARNING "No ACK from ADV7171\n"); + udelay(1); + GPCR = SCK | SDA; + udelay(1); + GPDR |= SDA; + udelay(1); +} + +static void adv7171_write(unsigned reg, unsigned val) +{ + unsigned gpdr = GPDR; + unsigned gplr = GPLR; + + ASSABET_BCR = BCR_value | ASSABET_BCR_AUDIO_ON; + udelay(100); + + GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */ + GPDR = (GPDR | SCK | MOD) & ~SDA; + udelay(10); + if (!(GPLR & SDA)) + printk(KERN_WARNING "Something dragging SDA down?\n"); + GPDR |= SDA; + + adv7171_start(); + adv7171_send(0x54); + adv7171_send(reg); + adv7171_send(val); + adv7171_stop(); + + /* Restore GPIO state for L3 bus */ + GPSR = gplr & (SDA | SCK | MOD); + GPCR = (~gplr) & (SDA | SCK | MOD); + GPDR = gpdr; +} + +static void adv7171_sleep(void) +{ + /* Put the ADV7171 into sleep mode */ + adv7171_write(0x04, 0x40); +} + +static unsigned codec_nreset; + +static void assabet_codec_reset(unsigned mask, int set) +{ + unsigned long flags; + bool old; + + local_irq_save(flags); + old = !codec_nreset; + if (set) + codec_nreset &= ~mask; + else + codec_nreset |= mask; + + if (old != !codec_nreset) { + if (codec_nreset) { + ASSABET_BCR_set(ASSABET_BCR_NCODEC_RST); + adv7171_sleep(); + } else { + ASSABET_BCR_clear(ASSABET_BCR_NCODEC_RST); + } + } + local_irq_restore(flags); +} + static void assabet_ucb1x00_reset(enum ucb1x00_reset state) { - if (state == UCB_RST_PROBE) - ASSABET_BCR_set(ASSABET_BCR_CODEC_RST); + int set = state == UCB_RST_REMOVE || state == UCB_RST_SUSPEND || + state == UCB_RST_PROBE_FAIL; + assabet_codec_reset(RST_UCB1X00, set); } +void assabet_uda1341_reset(int set) +{ + assabet_codec_reset(RST_UDA1341, set); +} +EXPORT_SYMBOL(assabet_uda1341_reset); + /* * Assabet flash support code. @@ -155,12 +286,9 @@ static int assabet_irda_set_power(struct device *dev, unsigned int state) 0 }; - if (state < 4) { - state = bcr_state[state]; - ASSABET_BCR_clear(state ^ (ASSABET_BCR_IRDA_MD1| - ASSABET_BCR_IRDA_MD0)); - ASSABET_BCR_set(state); - } + if (state < 4) + ASSABET_BCR_frob(ASSABET_BCR_IRDA_MD1 | ASSABET_BCR_IRDA_MD0, + bcr_state[state]); return 0; } @@ -180,6 +308,7 @@ static struct irda_platform_data assabet_irda_data = { static struct ucb1x00_plat_data assabet_ucb1x00_data = { .reset = assabet_ucb1x00_reset, .gpio_base = -1, + .can_wakeup = 1, }; static struct mcp_plat_data assabet_mcp_data = { diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index 7fb96eb..831a158 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c @@ -27,6 +27,8 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/timer.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> #include <linux/gpio.h> #include <linux/pda_power.h> @@ -242,10 +244,43 @@ struct platform_device collie_locomo_device = { .resource = locomo_resources, }; +static struct gpio_keys_button collie_gpio_keys[] = { + { + .type = EV_PWR, + .code = KEY_RESERVED, + .gpio = COLLIE_GPIO_ON_KEY, + .desc = "On key", + .wakeup = 1, + .active_low = 1, + }, + { + .type = EV_PWR, + .code = KEY_WAKEUP, + .gpio = COLLIE_GPIO_WAKEUP, + .desc = "Sync", + .wakeup = 1, + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data collie_gpio_keys_data = { + .buttons = collie_gpio_keys, + .nbuttons = ARRAY_SIZE(collie_gpio_keys), +}; + +static struct platform_device collie_gpio_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &collie_gpio_keys_data, + }, +}; + static struct platform_device *devices[] __initdata = { &collie_locomo_device, &colliescoop_device, &collie_power_device, + &collie_gpio_keys_device, }; static struct mtd_partition collie_partitions[] = { diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c index b8f2b15..daa27c4 100644 --- a/arch/arm/mach-sa1100/h3100.c +++ b/arch/arm/mach-sa1100/h3100.c @@ -28,15 +28,35 @@ /* * helper for sa1100fb */ +static struct gpio h3100_lcd_gpio[] = { + { H3100_GPIO_LCD_3V_ON, GPIOF_OUT_INIT_LOW, "LCD 3V" }, + { H3XXX_EGPIO_LCD_ON, GPIOF_OUT_INIT_LOW, "LCD ON" }, +}; + +static bool h3100_lcd_request(void) +{ + static bool h3100_lcd_ok; + int rc; + + if (h3100_lcd_ok) + return true; + + rc = gpio_request_array(h3100_lcd_gpio, ARRAY_SIZE(h3100_lcd_gpio)); + if (rc) + pr_err("%s: can't request GPIOs\n", __func__); + else + h3100_lcd_ok = true; + + return h3100_lcd_ok; +} + static void h3100_lcd_power(int enable) { - if (!gpio_request(H3XXX_EGPIO_LCD_ON, "LCD ON")) { - gpio_set_value(H3100_GPIO_LCD_3V_ON, enable); - gpio_direction_output(H3XXX_EGPIO_LCD_ON, enable); - gpio_free(H3XXX_EGPIO_LCD_ON); - } else { - pr_err("%s: can't request H3XXX_EGPIO_LCD_ON\n", __func__); - } + if (!h3100_lcd_request()) + return; + + gpio_set_value(H3100_GPIO_LCD_3V_ON, enable); + gpio_set_value(H3XXX_EGPIO_LCD_ON, enable); } static struct sa1100fb_mach_info h3100_lcd_info = { @@ -69,6 +89,11 @@ static void __init h3100_map_io(void) /* * This turns the IRDA power on or off on the Compaq H3100 */ +static struct gpio h3100_irda_gpio[] = { + { H3100_GPIO_IR_ON, GPIOF_OUT_INIT_LOW, "IrDA power" }, + { H3100_GPIO_IR_FSEL, GPIOF_OUT_INIT_LOW, "IrDA fsel" }, +}; + static int h3100_irda_set_power(struct device *dev, unsigned int state) { gpio_set_value(H3100_GPIO_IR_ON, state); @@ -80,18 +105,27 @@ static void h3100_irda_set_speed(struct device *dev, unsigned int speed) gpio_set_value(H3100_GPIO_IR_FSEL, !(speed < 4000000)); } +static int h3100_irda_startup(struct device *dev) +{ + return gpio_request_array(h3100_irda_gpio, sizeof(h3100_irda_gpio)); +} + +static void h3100_irda_shutdown(struct device *dev) +{ + return gpio_free_array(h3100_irda_gpio, sizeof(h3100_irda_gpio)); +} + static struct irda_platform_data h3100_irda_data = { .set_power = h3100_irda_set_power, .set_speed = h3100_irda_set_speed, + .startup = h3100_irda_startup, + .shutdown = h3100_irda_shutdown, }; static struct gpio_default_state h3100_default_gpio[] = { - { H3100_GPIO_IR_ON, GPIO_MODE_OUT0, "IrDA power" }, - { H3100_GPIO_IR_FSEL, GPIO_MODE_OUT0, "IrDA fsel" }, { H3XXX_GPIO_COM_DCD, GPIO_MODE_IN, "COM DCD" }, { H3XXX_GPIO_COM_CTS, GPIO_MODE_IN, "COM CTS" }, { H3XXX_GPIO_COM_RTS, GPIO_MODE_OUT0, "COM RTS" }, - { H3100_GPIO_LCD_3V_ON, GPIO_MODE_OUT0, "LCD 3v" }, }; static void __init h3100_mach_init(void) diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c index b8dc5bd..a663e72 100644 --- a/arch/arm/mach-sa1100/h3600.c +++ b/arch/arm/mach-sa1100/h3600.c @@ -28,35 +28,39 @@ /* * helper for sa1100fb */ +static struct gpio h3600_lcd_gpio[] = { + { H3XXX_EGPIO_LCD_ON, GPIOF_OUT_INIT_LOW, "LCD power" }, + { H3600_EGPIO_LCD_PCI, GPIOF_OUT_INIT_LOW, "LCD control" }, + { H3600_EGPIO_LCD_5V_ON, GPIOF_OUT_INIT_LOW, "LCD 5v" }, + { H3600_EGPIO_LVDD_ON, GPIOF_OUT_INIT_LOW, "LCD 9v/-6.5v" }, +}; + +static bool h3600_lcd_request(void) +{ + static bool h3600_lcd_ok; + int rc; + + if (h3600_lcd_ok) + return true; + + rc = gpio_request_array(h3600_lcd_gpio, ARRAY_SIZE(h3600_lcd_gpio)); + if (rc) + pr_err("%s: can't request GPIOs\n", __func__); + else + h3600_lcd_ok = true; + + return h3600_lcd_ok; +} + static void h3600_lcd_power(int enable) { - if (gpio_request(H3XXX_EGPIO_LCD_ON, "LCD power")) { - pr_err("%s: can't request H3XXX_EGPIO_LCD_ON\n", __func__); - goto err1; - } - if (gpio_request(H3600_EGPIO_LCD_PCI, "LCD control")) { - pr_err("%s: can't request H3XXX_EGPIO_LCD_PCI\n", __func__); - goto err2; - } - if (gpio_request(H3600_EGPIO_LCD_5V_ON, "LCD 5v")) { - pr_err("%s: can't request H3XXX_EGPIO_LCD_5V_ON\n", __func__); - goto err3; - } - if (gpio_request(H3600_EGPIO_LVDD_ON, "LCD 9v/-6.5v")) { - pr_err("%s: can't request H3600_EGPIO_LVDD_ON\n", __func__); - goto err4; - } + if (!h3600_lcd_request()) + return; gpio_direction_output(H3XXX_EGPIO_LCD_ON, enable); gpio_direction_output(H3600_EGPIO_LCD_PCI, enable); gpio_direction_output(H3600_EGPIO_LCD_5V_ON, enable); gpio_direction_output(H3600_EGPIO_LVDD_ON, enable); - - gpio_free(H3600_EGPIO_LVDD_ON); -err4: gpio_free(H3600_EGPIO_LCD_5V_ON); -err3: gpio_free(H3600_EGPIO_LCD_PCI); -err2: gpio_free(H3XXX_EGPIO_LCD_ON); -err1: return; } static const struct sa1100fb_rgb h3600_rgb_16 = { @@ -93,6 +97,11 @@ static void __init h3600_map_io(void) /* * This turns the IRDA power on or off on the Compaq H3600 */ +static struct gpio h3600_irda_gpio[] = { + { H3600_EGPIO_IR_ON, GPIOF_OUT_INIT_LOW, "IrDA power" }, + { H3600_EGPIO_IR_FSEL, GPIOF_OUT_INIT_LOW, "IrDA fsel" }, +}; + static int h3600_irda_set_power(struct device *dev, unsigned int state) { gpio_set_value(H3600_EGPIO_IR_ON, state); @@ -106,29 +115,12 @@ static void h3600_irda_set_speed(struct device *dev, unsigned int speed) static int h3600_irda_startup(struct device *dev) { - int err = gpio_request(H3600_EGPIO_IR_ON, "IrDA power"); - if (err) - goto err1; - err = gpio_direction_output(H3600_EGPIO_IR_ON, 0); - if (err) - goto err2; - err = gpio_request(H3600_EGPIO_IR_FSEL, "IrDA fsel"); - if (err) - goto err2; - err = gpio_direction_output(H3600_EGPIO_IR_FSEL, 0); - if (err) - goto err3; - return 0; - -err3: gpio_free(H3600_EGPIO_IR_FSEL); -err2: gpio_free(H3600_EGPIO_IR_ON); -err1: return err; + return gpio_request_array(h3600_irda_gpio, sizeof(h3600_irda_gpio)); } static void h3600_irda_shutdown(struct device *dev) { - gpio_free(H3600_EGPIO_IR_ON); - gpio_free(H3600_EGPIO_IR_FSEL); + return gpio_free_array(h3600_irda_gpio, sizeof(h3600_irda_gpio)); } static struct irda_platform_data h3600_irda_data = { diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h index 3073914..c23fcdb 100644 --- a/arch/arm/mach-sa1100/include/mach/assabet.h +++ b/arch/arm/mach-sa1100/include/mach/assabet.h @@ -39,8 +39,8 @@ extern unsigned long SCR_value; #define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */ #define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */ -#define ASSABET_BCR_GFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */ -#define ASSABET_BCR_CODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */ +#define ASSABET_BCR_NGFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */ +#define ASSABET_BCR_NCODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */ #define ASSABET_BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */ #define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */ #define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */ @@ -69,6 +69,8 @@ extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set); #define ASSABET_BCR_frob(x,y) do { } while (0) #endif +extern void assabet_uda1341_reset(int set); + #define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x)) #define ASSABET_BCR_clear(x) ASSABET_BCR_frob((x), 0) diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index 713c86cd..6fd4acb 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -20,7 +20,7 @@ #include <mach/hardware.h> #include <mach/irqs.h> -static u32 notrace sa1100_read_sched_clock(void) +static u64 notrace sa1100_read_sched_clock(void) { return readl_relaxed(OSCR); } @@ -122,7 +122,7 @@ void __init sa1100_timer_init(void) writel_relaxed(0, OIER); writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); - setup_sched_clock(sa1100_read_sched_clock, 32, 3686400); + sched_clock_register(sa1100_read_sched_clock, 32, 3686400); ckevt_sa1100_osmr0.cpumask = cpumask_of(0); diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index a4a4b75..3386406 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -1,6 +1,10 @@ +config ARCH_SHMOBILE + bool + config ARCH_SHMOBILE_MULTI - bool "SH-Mobile Series" if ARCH_MULTI_V7 + bool "Renesas ARM SoCs" if ARCH_MULTI_V7 depends on MMU + select ARCH_SHMOBILE select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP @@ -8,6 +12,7 @@ config ARCH_SHMOBILE_MULTI select HAVE_SMP select ARM_GIC select MIGHT_HAVE_CACHE_L2X0 + select MIGHT_HAVE_PCI select NO_IOPORT select PINCTRL select ARCH_REQUIRE_GPIOLIB @@ -15,24 +20,47 @@ config ARCH_SHMOBILE_MULTI if ARCH_SHMOBILE_MULTI -comment "SH-Mobile System Type" +comment "Renesas ARM SoCs System Type" config ARCH_EMEV2 bool "Emma Mobile EV2" -comment "SH-Mobile Board Type" +config ARCH_R7S72100 + bool "RZ/A1H (R7S72100)" + +config ARCH_R8A7790 + bool "R-Car H2 (R8A77900)" + select RENESAS_IRQC + +config ARCH_R8A7791 + bool "R-Car M2 (R8A77910)" + select RENESAS_IRQC + +comment "Renesas ARM SoCs Board Type" + +config MACH_GENMAI + bool "Genmai board" + depends on ARCH_R7S72100 + +config MACH_KOELSCH + bool "Koelsch board" + depends on ARCH_R8A7791 config MACH_KZM9D bool "KZM9D board" depends on ARCH_EMEV2 select REGULATOR_FIXED_VOLTAGE if REGULATOR -comment "SH-Mobile System Configuration" +config MACH_LAGER + bool "Lager board" + depends on ARCH_R8A7790 + +comment "Renesas ARM SoCs System Configuration" endif -if ARCH_SHMOBILE +if ARCH_SHMOBILE_LEGACY -comment "SH-Mobile System Type" +comment "Renesas ARM SoCs System Type" config ARCH_SH7372 bool "SH-Mobile AP4 (SH7372)" @@ -92,28 +120,36 @@ config ARCH_R8A7790 select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_GIC select CPU_V7 + select MIGHT_HAVE_PCI select SH_CLK_CPG select RENESAS_IRQC config ARCH_R8A7791 bool "R-Car M2 (R8A77910)" + select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_GIC select CPU_V7 + select MIGHT_HAVE_PCI select SH_CLK_CPG + select RENESAS_IRQC config ARCH_EMEV2 bool "Emma Mobile EV2" select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_GIC select CPU_V7 + select MIGHT_HAVE_PCI + select USE_OF + select AUTO_ZRELADDR config ARCH_R7S72100 bool "RZ/A1H (R7S72100)" + select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_GIC select CPU_V7 select SH_CLK_CPG -comment "SH-Mobile Board Type" +comment "Renesas ARM SoCs Board Type" config MACH_APE6EVM bool "APE6EVM board" @@ -190,6 +226,17 @@ config MACH_GENMAI depends on ARCH_R7S72100 select USE_OF +config MACH_GENMAI_REFERENCE + bool "Genmai board - Reference Device Tree Implementation" + depends on ARCH_R7S72100 + select USE_OF + ---help--- + Use reference implementation of Genmai board support + which makes use of device tree at the expense + of not supporting a number of devices. + + This is intended to aid developers + config MACH_MARZEN bool "MARZEN board" depends on ARCH_R8A7779 @@ -215,27 +262,11 @@ config MACH_LAGER depends on ARCH_R8A7790 select USE_OF -config MACH_LAGER_REFERENCE - bool "Lager board - Reference Device Tree Implementation" - depends on ARCH_R8A7790 - select USE_OF - ---help--- - Use reference implementation of Lager board support - which makes use of device tree at the expense - of not supporting a number of devices. - - This is intended to aid developers - config MACH_KOELSCH bool "Koelsch board" depends on ARCH_R8A7791 select USE_OF - -config MACH_KZM9D - bool "KZM9D board" - depends on ARCH_EMEV2 - select REGULATOR_FIXED_VOLTAGE if REGULATOR - select USE_OF + select MICREL_PHY if SH_ETH config MACH_KZM9G bool "KZM-A9-GT board" @@ -261,7 +292,7 @@ config MACH_KZM9G_REFERENCE This is intended to aid developers -comment "SH-Mobile System Configuration" +comment "Renesas ARM SoCs System Configuration" config CPU_HAS_INTEVT bool @@ -274,7 +305,7 @@ source "drivers/sh/Kconfig" endif -if ARCH_SHMOBILE || ARCH_SHMOBILE_MULTI +if ARCH_SHMOBILE menu "Timer and clock configuration" @@ -286,8 +317,8 @@ config SHMOBILE_TIMER_HZ Allows the configuration of the timer frequency. It is customary to have the timer interrupt run at 1000 Hz or 100 Hz, but in the case of low timer frequencies other values may be more suitable. - SH-Mobile systems using a 32768 Hz RCLK for clock events may want - to select a HZ value such as 128 that can evenly divide RCLK. + Renesas ARM SoC systems using a 32768 Hz RCLK for clock events may + want to select a HZ value such as 128 that can evenly divide RCLK. A HZ value that does not divide evenly may cause timer drift. config SH_TIMER_CMT diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 51db2bc..fe7d4ff 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -56,7 +56,10 @@ obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o # Board objects ifdef CONFIG_ARCH_SHMOBILE_MULTI +obj-$(CONFIG_MACH_GENMAI) += board-genmai-reference.o +obj-$(CONFIG_MACH_KOELSCH) += board-koelsch-reference.o obj-$(CONFIG_MACH_KZM9D) += board-kzm9d-reference.o +obj-$(CONFIG_MACH_LAGER) += board-lager-reference.o else obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o obj-$(CONFIG_MACH_APE6EVM_REFERENCE) += board-ape6evm-reference.o @@ -64,14 +67,13 @@ obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o obj-$(CONFIG_MACH_BOCKW) += board-bockw.o obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o obj-$(CONFIG_MACH_GENMAI) += board-genmai.o +obj-$(CONFIG_MACH_GENMAI_REFERENCE) += board-genmai-reference.o obj-$(CONFIG_MACH_MARZEN) += board-marzen.o obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o obj-$(CONFIG_MACH_LAGER) += board-lager.o -obj-$(CONFIG_MACH_LAGER_REFERENCE) += board-lager-reference.o obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o -obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o endif diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot index 391d72a..99455ec 100644 --- a/arch/arm/mach-shmobile/Makefile.boot +++ b/arch/arm/mach-shmobile/Makefile.boot @@ -6,13 +6,12 @@ loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000 loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 -loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000 +loadaddr-$(CONFIG_MACH_GENMAI) += 0x08008000 +loadaddr-$(CONFIG_MACH_GENMAI_REFERENCE) += 0x08008000 loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000 -loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000 loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 -loadaddr-$(CONFIG_MACH_LAGER_REFERENCE) += 0x40008000 loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000 loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000 diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c index 0fa068e..fe071a9 100644 --- a/arch/arm/mach-shmobile/board-ape6evm.c +++ b/arch/arm/mach-shmobile/board-ape6evm.c @@ -168,7 +168,7 @@ static const struct sh_mmcif_plat_data mmcif0_pdata __initconst = { }; static const struct resource mmcif0_resources[] __initconst = { - DEFINE_RES_MEM_NAMED(0xee200000, 0x100, "MMCIF0"), + DEFINE_RES_MEM(0xee200000, 0x100), DEFINE_RES_IRQ(gic_spi(169)), }; @@ -179,7 +179,7 @@ static const struct sh_mobile_sdhi_info sdhi0_pdata __initconst = { }; static const struct resource sdhi0_resources[] __initconst = { - DEFINE_RES_MEM_NAMED(0xee100000, 0x100, "SDHI0"), + DEFINE_RES_MEM(0xee100000, 0x100), DEFINE_RES_IRQ(gic_spi(165)), }; @@ -191,7 +191,7 @@ static const struct sh_mobile_sdhi_info sdhi1_pdata __initconst = { }; static const struct resource sdhi1_resources[] __initconst = { - DEFINE_RES_MEM_NAMED(0xee120000, 0x100, "SDHI1"), + DEFINE_RES_MEM(0xee120000, 0x100), DEFINE_RES_IRQ(gic_spi(166)), }; diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index 8ea87bd..93533e2 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -423,7 +423,7 @@ static struct platform_pwm_backlight_data pwm_backlight_data = { .max_brightness = 255, .dft_brightness = 255, .pwm_period_ns = 33333, /* 30kHz */ - .enable_gpio = -1, + .enable_gpio = 61, }; static struct platform_device pwm_backlight_device = { @@ -963,7 +963,7 @@ static struct resource fsi_resources[] = { [0] = { .name = "FSI", .start = 0xfe1f0000, - .end = 0xfe1f8400 - 1, + .end = 0xfe1f0400 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -1210,9 +1210,6 @@ static void __init eva_init(void) r8a7740_pinmux_init(); r8a7740_meram_workaround(); - /* LCDC0 */ - gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ - /* GETHER */ gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c index ae88fda..027373f 100644 --- a/arch/arm/mach-shmobile/board-bockw-reference.c +++ b/arch/arm/mach-shmobile/board-bockw-reference.c @@ -19,7 +19,6 @@ */ #include <linux/of_platform.h> -#include <linux/pinctrl/machine.h> #include <mach/common.h> #include <mach/r8a7778.h> #include <asm/mach/arch.h> @@ -28,27 +27,19 @@ * see board-bock.c for checking detail of dip-switch */ -static const struct pinctrl_map bockw_pinctrl_map[] = { - /* SCIF0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", - "scif0_data_a", "scif0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", - "scif0_ctrl", "scif0"), -}; - #define FPGA 0x18200000 #define IRQ0MR 0x30 #define COMCTLR 0x101c + +#define PFC 0xfffc0000 +#define PUPR4 0x110 static void __init bockw_init(void) { - static void __iomem *fpga; + void __iomem *fpga; + void __iomem *pfc; r8a7778_clock_init(); r8a7778_init_irq_extpin_dt(1); - - pinctrl_register_mappings(bockw_pinctrl_map, - ARRAY_SIZE(bockw_pinctrl_map)); - r8a7778_pinmux_init(); r8a7778_add_dt_devices(); fpga = ioremap_nocache(FPGA, SZ_1M); @@ -63,6 +54,19 @@ static void __init bockw_init(void) u16 val = ioread16(fpga + IRQ0MR); val &= ~(1 << 4); /* enable SMSC911x */ iowrite16(val, fpga + IRQ0MR); + + iounmap(fpga); + } + + pfc = ioremap_nocache(PFC, 0x200); + if (pfc) { + /* + * FIXME + * + * SDHI CD/WP pin needs pull-up + */ + iowrite32(ioread32(pfc + PUPR4) | (3 << 26), pfc + PUPR4); + iounmap(pfc); } of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index 3c4995a..c475220 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c @@ -25,6 +25,7 @@ #include <linux/mmc/sh_mmcif.h> #include <linux/mtd/partitions.h> #include <linux/pinctrl/machine.h> +#include <linux/platform_data/camera-rcar.h> #include <linux/platform_data/usb-rcar-phy.h> #include <linux/platform_device.h> #include <linux/regulator/fixed.h> @@ -116,6 +117,11 @@ static struct regulator_consumer_supply dummy_supplies[] = { REGULATOR_SUPPLY("vdd33a", "smsc911x"), }; +static struct regulator_consumer_supply fixed3v3_power_consumers[] = { + REGULATOR_SUPPLY("vmmc", "sh_mmcif"), + REGULATOR_SUPPLY("vqmmc", "sh_mmcif"), +}; + static struct smsc911x_platform_config smsc911x_data __initdata = { .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, @@ -271,7 +277,6 @@ static struct resource mmc_resources[] __initdata = { static struct sh_mmcif_plat_data sh_mmcif_plat __initdata = { .sup_pclk = 0, - .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_NEEDS_POLL, @@ -328,11 +333,11 @@ static struct rsnd_ssi_platform_info rsnd_ssi[] = { RSND_SSI_UNUSED, /* SSI 1 */ RSND_SSI_UNUSED, /* SSI 2 */ RSND_SSI_SET(1, 0, gic_iid(0x85), RSND_SSI_PLAY), - RSND_SSI_SET(2, 0, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE | RSND_SSI_CLK_FROM_ADG), + RSND_SSI_SET(2, 0, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE), RSND_SSI_SET(0, 0, gic_iid(0x86), RSND_SSI_PLAY), RSND_SSI_SET(0, 0, gic_iid(0x86), 0), RSND_SSI_SET(3, 0, gic_iid(0x86), RSND_SSI_PLAY), - RSND_SSI_SET(4, 0, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE | RSND_SSI_CLK_FROM_ADG), + RSND_SSI_SET(4, 0, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE), }; static struct rsnd_scu_platform_info rsnd_scu[9] = { @@ -614,6 +619,10 @@ static void __init bockw_init(void) &usb_phy_platform_data, sizeof(struct rcar_phy_platform_data)); + regulator_register_fixed(0, dummy_supplies, + ARRAY_SIZE(dummy_supplies)); + regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers, + ARRAY_SIZE(fixed3v3_power_consumers), 3300000); /* for SMSC */ fpga = ioremap_nocache(FPGA, SZ_1M); @@ -629,9 +638,6 @@ static void __init bockw_init(void) val &= ~(1 << 4); /* enable SMSC911x */ iowrite16(val, fpga + IRQ0MR); - regulator_register_fixed(0, dummy_supplies, - ARRAY_SIZE(dummy_supplies)); - platform_device_register_resndata( &platform_bus, "smsc911x", -1, smsc911x_resources, ARRAY_SIZE(smsc911x_resources), diff --git a/arch/arm/mach-shmobile/board-genmai-reference.c b/arch/arm/mach-shmobile/board-genmai-reference.c new file mode 100644 index 0000000..7630c10 --- /dev/null +++ b/arch/arm/mach-shmobile/board-genmai-reference.c @@ -0,0 +1,49 @@ +/* + * Genmai board support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/clk-provider.h> +#include <linux/kernel.h> +#include <linux/of_platform.h> +#include <mach/common.h> +#include <mach/r7s72100.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +static void __init genmai_add_standard_devices(void) +{ +#ifdef CONFIG_COMMON_CLK + of_clk_init(NULL); +#else + r7s72100_clock_init(); +#endif + r7s72100_add_dt_devices(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char * const genmai_boards_compat_dt[] __initconst = { + "renesas,genmai-reference", + NULL, +}; + +DT_MACHINE_START(GENMAI_DT, "genmai") + .init_early = r7s72100_init_early, + .init_machine = genmai_add_standard_devices, + .dt_compat = genmai_boards_compat_dt, +MACHINE_END diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c new file mode 100644 index 0000000..652b592 --- /dev/null +++ b/arch/arm/mach-shmobile/board-koelsch-reference.c @@ -0,0 +1,79 @@ +/* + * Koelsch board support - Reference DT implementation + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/kernel.h> +#include <linux/of_platform.h> +#include <mach/common.h> +#include <mach/rcar-gen2.h> +#include <mach/r8a7791.h> +#include <asm/mach/arch.h> + +static void __init koelsch_add_standard_devices(void) +{ +#ifdef CONFIG_COMMON_CLK + /* + * This is a really crude hack to provide clkdev support to the SCIF + * and CMT devices until they get moved to DT. + */ + static const char * const scif_names[] = { + "scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifa2", + "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scifa3", + "scifa4", "scifa5", + }; + struct clk *clk; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(scif_names); ++i) { + clk = clk_get(NULL, scif_names[i]); + if (clk) { + clk_register_clkdev(clk, NULL, "sh-sci.%u", i); + clk_put(clk); + } + } + + clk = clk_get(NULL, "cmt0"); + if (clk) { + clk_register_clkdev(clk, NULL, "sh_cmt.0"); + clk_put(clk); + } +#else + r8a7791_clock_init(); +#endif + r8a7791_add_dt_devices(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char * const koelsch_boards_compat_dt[] __initconst = { + "renesas,koelsch", + "renesas,koelsch-reference", + NULL, +}; + +DT_MACHINE_START(KOELSCH_DT, "koelsch") + .smp = smp_ops(r8a7791_smp_ops), + .init_early = r8a7791_init_early, + .init_time = rcar_gen2_timer_init, + .init_machine = koelsch_add_standard_devices, + .init_late = shmobile_init_late, + .dt_compat = koelsch_boards_compat_dt, +MACHINE_END diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c index ace1711..de7cc64 100644 --- a/arch/arm/mach-shmobile/board-koelsch.c +++ b/arch/arm/mach-shmobile/board-koelsch.c @@ -19,18 +19,205 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/dma-mapping.h> +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> #include <linux/kernel.h> +#include <linux/leds.h> +#include <linux/phy.h> +#include <linux/pinctrl/machine.h> +#include <linux/platform_data/gpio-rcar.h> +#include <linux/platform_data/rcar-du.h> #include <linux/platform_device.h> +#include <linux/sh_eth.h> #include <mach/common.h> +#include <mach/irqs.h> #include <mach/r8a7791.h> #include <mach/rcar-gen2.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> +/* DU */ +static struct rcar_du_encoder_data koelsch_du_encoders[] = { + { + .type = RCAR_DU_ENCODER_NONE, + .output = RCAR_DU_OUTPUT_LVDS0, + .connector.lvds.panel = { + .width_mm = 210, + .height_mm = 158, + .mode = { + .clock = 65000, + .hdisplay = 1024, + .hsync_start = 1048, + .hsync_end = 1184, + .htotal = 1344, + .vdisplay = 768, + .vsync_start = 771, + .vsync_end = 777, + .vtotal = 806, + .flags = 0, + }, + }, + }, +}; + +static const struct rcar_du_platform_data koelsch_du_pdata __initconst = { + .encoders = koelsch_du_encoders, + .num_encoders = ARRAY_SIZE(koelsch_du_encoders), +}; + +static const struct resource du_resources[] __initconst = { + DEFINE_RES_MEM(0xfeb00000, 0x40000), + DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"), + DEFINE_RES_IRQ(gic_spi(256)), + DEFINE_RES_IRQ(gic_spi(268)), +}; + +static void __init koelsch_add_du_device(void) +{ + struct platform_device_info info = { + .name = "rcar-du-r8a7791", + .id = -1, + .res = du_resources, + .num_res = ARRAY_SIZE(du_resources), + .data = &koelsch_du_pdata, + .size_data = sizeof(koelsch_du_pdata), + .dma_mask = DMA_BIT_MASK(32), + }; + + platform_device_register_full(&info); +} + +/* Ether */ +static const struct sh_eth_plat_data ether_pdata __initconst = { + .phy = 0x1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .phy_interface = PHY_INTERFACE_MODE_RMII, + .ether_link_active_low = 1, +}; + +static const struct resource ether_resources[] __initconst = { + DEFINE_RES_MEM(0xee700000, 0x400), + DEFINE_RES_IRQ(gic_spi(162)), +}; + +/* LEDS */ +static struct gpio_led koelsch_leds[] = { + { + .name = "led8", + .gpio = RCAR_GP_PIN(2, 21), + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, { + .name = "led7", + .gpio = RCAR_GP_PIN(2, 20), + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, { + .name = "led6", + .gpio = RCAR_GP_PIN(2, 19), + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, +}; + +static const struct gpio_led_platform_data koelsch_leds_pdata __initconst = { + .leds = koelsch_leds, + .num_leds = ARRAY_SIZE(koelsch_leds), +}; + +/* GPIO KEY */ +#define GPIO_KEY(c, g, d, ...) \ + { .code = c, .gpio = g, .desc = d, .active_low = 1, \ + .wakeup = 1, .debounce_interval = 20 } + +static struct gpio_keys_button gpio_buttons[] = { + GPIO_KEY(KEY_4, RCAR_GP_PIN(5, 3), "SW2-pin4"), + GPIO_KEY(KEY_3, RCAR_GP_PIN(5, 2), "SW2-pin3"), + GPIO_KEY(KEY_2, RCAR_GP_PIN(5, 1), "SW2-pin2"), + GPIO_KEY(KEY_1, RCAR_GP_PIN(5, 0), "SW2-pin1"), + GPIO_KEY(KEY_G, RCAR_GP_PIN(7, 6), "SW36"), + GPIO_KEY(KEY_F, RCAR_GP_PIN(7, 5), "SW35"), + GPIO_KEY(KEY_E, RCAR_GP_PIN(7, 4), "SW34"), + GPIO_KEY(KEY_D, RCAR_GP_PIN(7, 3), "SW33"), + GPIO_KEY(KEY_C, RCAR_GP_PIN(7, 2), "SW32"), + GPIO_KEY(KEY_B, RCAR_GP_PIN(7, 1), "SW31"), + GPIO_KEY(KEY_A, RCAR_GP_PIN(7, 0), "SW30"), +}; + +static const struct gpio_keys_platform_data koelsch_keys_pdata __initconst = { + .buttons = gpio_buttons, + .nbuttons = ARRAY_SIZE(gpio_buttons), +}; + +static const struct pinctrl_map koelsch_pinctrl_map[] = { + /* DU */ + PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791", + "du_rgb666", "du"), + PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791", + "du_sync", "du"), + PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791", + "du_clk_out_0", "du"), + /* Ether */ + PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791", + "eth_link", "eth"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791", + "eth_mdio", "eth"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791", + "eth_rmii", "eth"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791", + "intc_irq0", "intc"), + /* SCIF0 (CN19: DEBUG SERIAL0) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7791", + "scif0_data_d", "scif0"), + /* SCIF1 (CN20: DEBUG SERIAL1) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7791", + "scif1_data_d", "scif1"), +}; + static void __init koelsch_add_standard_devices(void) { r8a7791_clock_init(); + pinctrl_register_mappings(koelsch_pinctrl_map, + ARRAY_SIZE(koelsch_pinctrl_map)); + r8a7791_pinmux_init(); r8a7791_add_standard_devices(); + platform_device_register_resndata(&platform_bus, "r8a7791-ether", -1, + ether_resources, + ARRAY_SIZE(ether_resources), + ðer_pdata, sizeof(ether_pdata)); + platform_device_register_data(&platform_bus, "leds-gpio", -1, + &koelsch_leds_pdata, + sizeof(koelsch_leds_pdata)); + platform_device_register_data(&platform_bus, "gpio-keys", -1, + &koelsch_keys_pdata, + sizeof(koelsch_keys_pdata)); + + koelsch_add_du_device(); +} + +/* + * Ether LEDs on the Koelsch board are named LINK and ACTIVE which corresponds + * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits + * 14-15. We have to set them back to 01 from the default 00 value each time + * the PHY is reset. It's also important because the PHY's LED0 signal is + * connected to SoC's ETH_LINK signal and in the PHY's default mode it will + * bounce on and off after each packet, which we apparently want to avoid. + */ +static int koelsch_ksz8041_fixup(struct phy_device *phydev) +{ + u16 phyctrl1 = phy_read(phydev, 0x1e); + + phyctrl1 &= ~0xc000; + phyctrl1 |= 0x4000; + return phy_write(phydev, 0x1e, phyctrl1); +} + +static void __init koelsch_init(void) +{ + koelsch_add_standard_devices(); + + if (IS_ENABLED(CONFIG_PHYLIB)) + phy_register_fixup_for_id("r8a7791-ether-ff:01", + koelsch_ksz8041_fixup); } static const char * const koelsch_boards_compat_dt[] __initconst = { @@ -41,7 +228,8 @@ static const char * const koelsch_boards_compat_dt[] __initconst = { DT_MACHINE_START(KOELSCH_DT, "koelsch") .smp = smp_ops(r8a7791_smp_ops), .init_early = r8a7791_init_early, - .init_machine = koelsch_add_standard_devices, .init_time = rcar_gen2_timer_init, + .init_machine = koelsch_init, + .init_late = shmobile_init_late, .dt_compat = koelsch_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c deleted file mode 100644 index 30c2cc6..0000000 --- a/arch/arm/mach-shmobile/board-kzm9d.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * kzm9d board support - * - * Copyright (C) 2012 Renesas Solutions Corp. - * Copyright (C) 2012 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/machine.h> -#include <linux/smsc911x.h> -#include <mach/common.h> -#include <mach/emev2.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -/* Dummy supplies, where voltage doesn't matter */ -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vddvario", "smsc911x"), - REGULATOR_SUPPLY("vdd33a", "smsc911x"), -}; - -/* Ether */ -static struct resource smsc911x_resources[] = { - [0] = { - .start = 0x20000000, - .end = 0x2000ffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = EMEV2_GPIO_IRQ(1), - .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, - }, -}; - -static struct smsc911x_platform_config smsc911x_platdata = { - .flags = SMSC911X_USE_32BIT, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, -}; - -static struct platform_device smsc91x_device = { - .name = "smsc911x", - .id = -1, - .dev = { - .platform_data = &smsc911x_platdata, - }, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, -}; - -static struct platform_device *kzm9d_devices[] __initdata = { - &smsc91x_device, -}; - -void __init kzm9d_add_standard_devices(void) -{ - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - emev2_add_standard_devices(); - - platform_add_devices(kzm9d_devices, ARRAY_SIZE(kzm9d_devices)); -} - -static const char *kzm9d_boards_compat_dt[] __initdata = { - "renesas,kzm9d", - NULL, -}; - -DT_MACHINE_START(KZM9D_DT, "kzm9d") - .smp = smp_ops(emev2_smp_ops), - .map_io = emev2_map_io, - .init_early = emev2_init_delay, - .init_machine = kzm9d_add_standard_devices, - .init_late = shmobile_init_late, - .dt_compat = kzm9d_boards_compat_dt, -MACHINE_END diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c index 1a1a4a8..a6e271d 100644 --- a/arch/arm/mach-shmobile/board-lager-reference.c +++ b/arch/arm/mach-shmobile/board-lager-reference.c @@ -18,21 +18,53 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/clk.h> +#include <linux/clkdev.h> #include <linux/init.h> #include <linux/of_platform.h> +#include <mach/common.h> +#include <mach/rcar-gen2.h> #include <mach/r8a7790.h> #include <asm/mach/arch.h> static void __init lager_add_standard_devices(void) { - /* clocks are setup late during boot in the case of DT */ +#ifdef CONFIG_COMMON_CLK + /* + * This is a really crude hack to provide clkdev support to the SCIF + * and CMT devices until they get moved to DT. + */ + static const char * const scif_names[] = { + "scifa0", "scifa1", "scifb0", "scifb1", + "scifb2", "scifa2", "scif0", "scif1", + "hscif0", "hscif1", + }; + struct clk *clk; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(scif_names); ++i) { + clk = clk_get(NULL, scif_names[i]); + if (clk) { + clk_register_clkdev(clk, NULL, "sh-sci.%u", i); + clk_put(clk); + } + } + + clk = clk_get(NULL, "cmt0"); + if (clk) { + clk_register_clkdev(clk, NULL, "sh_cmt.0"); + clk_put(clk); + } +#else r8a7790_clock_init(); +#endif r8a7790_add_dt_devices(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char *lager_boards_compat_dt[] __initdata = { + "renesas,lager", "renesas,lager-reference", NULL, }; @@ -42,5 +74,6 @@ DT_MACHINE_START(LAGER_DT, "lager") .init_early = r8a7790_init_early, .init_time = rcar_gen2_timer_init, .init_machine = lager_add_standard_devices, + .init_late = shmobile_init_late, .dt_compat = lager_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index e0406fd..f20c10a 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -31,7 +31,9 @@ #include <linux/platform_data/rcar-du.h> #include <linux/platform_device.h> #include <linux/phy.h> +#include <linux/regulator/driver.h> #include <linux/regulator/fixed.h> +#include <linux/regulator/gpio-regulator.h> #include <linux/regulator/machine.h> #include <linux/sh_eth.h> #include <mach/common.h> @@ -39,6 +41,11 @@ #include <mach/r8a7790.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/mtd.h> +#include <linux/spi/flash.h> +#include <linux/spi/rspi.h> +#include <linux/spi/spi.h> /* DU */ static struct rcar_du_encoder_data lager_du_encoders[] = { @@ -120,7 +127,8 @@ static const struct gpio_led_platform_data lager_leds_pdata __initconst = { /* GPIO KEY */ #define GPIO_KEY(c, g, d, ...) \ - { .code = c, .gpio = g, .desc = d, .active_low = 1 } + { .code = c, .gpio = g, .desc = d, .active_low = 1, \ + .wakeup = 1, .debounce_interval = 20 } static struct gpio_keys_button gpio_buttons[] = { GPIO_KEY(KEY_4, RCAR_GP_PIN(1, 28), "SW2-pin4"), @@ -140,6 +148,71 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] = REGULATOR_SUPPLY("vmmc", "sh_mmcif.1"), }; +/* + * SDHI regulator macro + * + ** FIXME** + * Lager board vqmmc is provided via DA9063 PMIC chip, + * and we should use ${LINK}/drivers/mfd/da9063-* driver for it. + * but, it doesn't have regulator support at this point. + * It uses gpio-regulator for vqmmc as quick-hack. + */ +#define SDHI_REGULATOR(idx, vdd_pin, vccq_pin) \ +static struct regulator_consumer_supply vcc_sdhi##idx##_consumer = \ + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi." #idx); \ + \ +static struct regulator_init_data vcc_sdhi##idx##_init_data = { \ + .constraints = { \ + .valid_ops_mask = REGULATOR_CHANGE_STATUS, \ + }, \ + .consumer_supplies = &vcc_sdhi##idx##_consumer, \ + .num_consumer_supplies = 1, \ +}; \ + \ +static const struct fixed_voltage_config vcc_sdhi##idx##_info __initconst = {\ + .supply_name = "SDHI" #idx "Vcc", \ + .microvolts = 3300000, \ + .gpio = vdd_pin, \ + .enable_high = 1, \ + .init_data = &vcc_sdhi##idx##_init_data, \ +}; \ + \ +static struct regulator_consumer_supply vccq_sdhi##idx##_consumer = \ + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi." #idx); \ + \ +static struct regulator_init_data vccq_sdhi##idx##_init_data = { \ + .constraints = { \ + .input_uV = 3300000, \ + .min_uV = 1800000, \ + .max_uV = 3300000, \ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | \ + REGULATOR_CHANGE_STATUS, \ + }, \ + .consumer_supplies = &vccq_sdhi##idx##_consumer, \ + .num_consumer_supplies = 1, \ +}; \ + \ +static struct gpio vccq_sdhi##idx##_gpio = \ + { vccq_pin, GPIOF_OUT_INIT_HIGH, "vccq-sdhi" #idx }; \ + \ +static struct gpio_regulator_state vccq_sdhi##idx##_states[] = { \ + { .value = 1800000, .gpios = 0 }, \ + { .value = 3300000, .gpios = 1 }, \ +}; \ + \ +static const struct gpio_regulator_config vccq_sdhi##idx##_info __initconst = {\ + .supply_name = "vqmmc", \ + .gpios = &vccq_sdhi##idx##_gpio, \ + .nr_gpios = 1, \ + .states = vccq_sdhi##idx##_states, \ + .nr_states = ARRAY_SIZE(vccq_sdhi##idx##_states), \ + .type = REGULATOR_VOLTAGE, \ + .init_data = &vccq_sdhi##idx##_init_data, \ +}; + +SDHI_REGULATOR(0, RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 29)); +SDHI_REGULATOR(2, RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 30)); + /* MMCIF */ static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = { .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, @@ -148,7 +221,7 @@ static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = { }; static const struct resource mmcif1_resources[] __initconst = { - DEFINE_RES_MEM_NAMED(0xee220000, 0x80, "MMCIF1"), + DEFINE_RES_MEM(0xee220000, 0x80), DEFINE_RES_IRQ(gic_spi(170)), }; @@ -165,6 +238,59 @@ static const struct resource ether_resources[] __initconst = { DEFINE_RES_IRQ(gic_spi(162)), }; +/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64Mb) */ +static struct mtd_partition spi_flash_part[] = { + /* Reserved for user loader program, read-only */ + { + .name = "loader", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, + }, + /* Reserved for user program, read-only */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = MTD_WRITEABLE, + }, + /* All else is writable (e.g. JFFS2) */ + { + .name = "flash", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct flash_platform_data spi_flash_data = { + .name = "m25p80", + .parts = spi_flash_part, + .nr_parts = ARRAY_SIZE(spi_flash_part), + .type = "s25fl512s", +}; + +static const struct rspi_plat_data qspi_pdata __initconst = { + .num_chipselect = 1, +}; + +static const struct spi_board_info spi_info[] __initconst = { + { + .modalias = "m25p80", + .platform_data = &spi_flash_data, + .mode = SPI_MODE_0, + .max_speed_hz = 30000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +/* QSPI resource */ +static const struct resource qspi_resources[] __initconst = { + DEFINE_RES_MEM(0xe6b10000, 0x1000), + DEFINE_RES_IRQ(gic_spi(184)), +}; + static const struct pinctrl_map lager_pinctrl_map[] = { /* DU (CN10: ARGB0, CN13: LVDS) */ PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790", @@ -197,6 +323,9 @@ static const struct pinctrl_map lager_pinctrl_map[] = { static void __init lager_add_standard_devices(void) { + int fixed_regulator_idx = 0; + int gpio_regulator_idx = 0; + r8a7790_clock_init(); pinctrl_register_mappings(lager_pinctrl_map, @@ -210,7 +339,8 @@ static void __init lager_add_standard_devices(void) platform_device_register_data(&platform_bus, "gpio-keys", -1, &lager_keys_pdata, sizeof(lager_keys_pdata)); - regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, + regulator_register_always_on(fixed_regulator_idx++, + "fixed-3.3V", fixed3v3_power_consumers, ARRAY_SIZE(fixed3v3_power_consumers), 3300000); platform_device_register_resndata(&platform_bus, "sh_mmcif", 1, mmcif1_resources, ARRAY_SIZE(mmcif1_resources), @@ -222,6 +352,22 @@ static void __init lager_add_standard_devices(void) ðer_pdata, sizeof(ether_pdata)); lager_add_du_device(); + + platform_device_register_resndata(&platform_bus, "qspi", 0, + qspi_resources, + ARRAY_SIZE(qspi_resources), + &qspi_pdata, sizeof(qspi_pdata)); + spi_register_board_info(spi_info, ARRAY_SIZE(spi_info)); + + platform_device_register_data(&platform_bus, "reg-fixed-voltage", fixed_regulator_idx++, + &vcc_sdhi0_info, sizeof(struct fixed_voltage_config)); + platform_device_register_data(&platform_bus, "reg-fixed-voltage", fixed_regulator_idx++, + &vcc_sdhi2_info, sizeof(struct fixed_voltage_config)); + + platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++, + &vccq_sdhi0_info, sizeof(struct gpio_regulator_config)); + platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++, + &vccq_sdhi2_info, sizeof(struct gpio_regulator_config)); } /* @@ -260,5 +406,6 @@ DT_MACHINE_START(LAGER_DT, "lager") .init_early = r8a7790_init_early, .init_time = rcar_gen2_timer_init, .init_machine = lager_init, + .init_late = shmobile_init_late, .dt_compat = lager_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index e721d2c..3aba037 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -41,6 +41,7 @@ #include <linux/mtd/physmap.h> #include <linux/mtd/sh_flctl.h> #include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf-generic.h> #include <linux/platform_data/gpio_backlight.h> #include <linux/pm_clock.h> #include <linux/regulator/fixed.h> @@ -548,9 +549,9 @@ static void __init hdmi_init_pm_clock(void) clk_get_rate(&sh7372_pllc2_clk)); rate = clk_round_rate(&sh7372_pllc2_clk, 594000000); - if (rate < 0) { + if (rate <= 0) { pr_err("Cannot get suitable rate: %ld\n", rate); - ret = rate; + ret = -EINVAL; goto out; } @@ -1311,6 +1312,10 @@ static struct i2c_board_info i2c1_devices[] = { }, }; +static unsigned long pin_pulldown_conf[] = { + PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0), +}; + static const struct pinctrl_map mackerel_pinctrl_map[] = { /* ADXL34X */ PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372", @@ -1396,17 +1401,19 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { /* USBHS0 */ PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372", "usb0_vbus", "usb0"), + PIN_MAP_CONFIGS_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372", + "usb0_vbus", pin_pulldown_conf), /* USBHS1 */ PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372", "usb1_vbus", "usb1"), + PIN_MAP_CONFIGS_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372", + "usb1_vbus", pin_pulldown_conf), PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372", "usb1_otg_id_0", "usb1"), }; #define GPIO_PORT9CR IOMEM(0xE6051009) #define GPIO_PORT10CR IOMEM(0xE605100A) -#define GPIO_PORT167CR IOMEM(0xE60520A7) -#define GPIO_PORT168CR IOMEM(0xE60520A8) #define SRCR4 IOMEM(0xe61580bc) #define USCCR1 IOMEM(0xE6058144) static void __init mackerel_init(void) @@ -1446,12 +1453,6 @@ static void __init mackerel_init(void) gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ - /* USBHS0 */ - gpio_request_pulldown(GPIO_PORT168CR); /* VBUS0_0 pull down */ - - /* USBHS1 */ - gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */ - /* FSI2 port A (ak4643) */ gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index da1352f..d832a44 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -29,6 +29,7 @@ #include <linux/leds.h> #include <linux/dma-mapping.h> #include <linux/pinctrl/machine.h> +#include <linux/platform_data/camera-rcar.h> #include <linux/platform_data/gpio-rcar.h> #include <linux/platform_data/rcar-du.h> #include <linux/platform_data/usb-rcar-phy.h> @@ -259,10 +260,30 @@ static struct platform_device leds_device = { }, }; +/* VIN */ static struct rcar_vin_platform_data vin_platform_data __initdata = { .flags = RCAR_VIN_BT656, }; +#define MARZEN_VIN(idx) \ +static struct resource vin##idx##_resources[] __initdata = { \ + DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ + DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \ +}; \ + \ +static struct platform_device_info vin##idx##_info __initdata = { \ + .parent = &platform_bus, \ + .name = "r8a7779-vin", \ + .id = idx, \ + .res = vin##idx##_resources, \ + .num_res = ARRAY_SIZE(vin##idx##_resources), \ + .dma_mask = DMA_BIT_MASK(32), \ + .data = &vin_platform_data, \ + .size_data = sizeof(vin_platform_data), \ +} +MARZEN_VIN(1); +MARZEN_VIN(3); + #define MARZEN_CAMERA(idx) \ static struct i2c_board_info camera##idx##_info = { \ I2C_BOARD_INFO("adv7180", 0x20 + (idx)), \ @@ -326,8 +347,6 @@ static const struct pinctrl_map marzen_pinctrl_map[] = { "sdhi0_ctrl", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", "sdhi0_cd", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", - "sdhi0_wp", "sdhi0"), /* SMSC */ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", "intc_irq1_b", "intc"), @@ -367,8 +386,8 @@ static void __init marzen_init(void) r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */ r8a7779_add_standard_devices(); - r8a7779_add_vin_device(1, &vin_platform_data); - r8a7779_add_vin_device(3, &vin_platform_data); + platform_device_register_full(&vin1_info); + platform_device_register_full(&vin3_info); platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); marzen_add_du_device(); } diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c index 4aba20c..e6ab0cd 100644 --- a/arch/arm/mach-shmobile/clock-r7s72100.c +++ b/arch/arm/mach-shmobile/clock-r7s72100.c @@ -27,6 +27,7 @@ #define FRQCR2 0xfcfe0014 #define STBCR3 0xfcfe0420 #define STBCR4 0xfcfe0424 +#define STBCR9 0xfcfe0438 #define PLL_RATE 30 @@ -144,10 +145,15 @@ struct clk div4_clks[DIV4_NR] = { | CLK_ENABLE_ON_INIT), }; -enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, +enum { MSTP97, MSTP96, MSTP95, MSTP94, + MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, MSTP33, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { + [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */ + [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */ + [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */ + [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */ [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ @@ -170,6 +176,9 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), /* MSTP clocks */ + CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]), + + /* ICK */ CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]), CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]), CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]), diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 571409b..7348d58 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -584,15 +584,15 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]), CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), - CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), + CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]), CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), - CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), - CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), - CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), - CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]), CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]), CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]), CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]), diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index c826bca..dd989f9 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -585,22 +585,23 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), + CLKDEV_DEV_ID("fe1f0000.sound", &mstp_clks[MSTP328]), CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), - CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("e6850000.sd", &mstp_clks[MSTP314]), CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), - CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("e6860000.sd", &mstp_clks[MSTP313]), CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), - CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]), CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]), CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]), CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), - CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), + CLKDEV_DEV_ID("e6870000.sd", &mstp_clks[MSTP415]), /* ICK */ CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index fb6af83..9783945 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -115,6 +115,8 @@ static struct clk *main_clks[] = { }; enum { + MSTP531, MSTP530, + MSTP529, MSTP528, MSTP527, MSTP526, MSTP525, MSTP524, MSTP523, MSTP331, MSTP323, MSTP322, MSTP321, MSTP311, MSTP310, @@ -129,6 +131,15 @@ enum { MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { + [MSTP531] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 31, 0), /* SCU0 */ + [MSTP530] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 30, 0), /* SCU1 */ + [MSTP529] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 29, 0), /* SCU2 */ + [MSTP528] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 28, 0), /* SCU3 */ + [MSTP527] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 27, 0), /* SCU4 */ + [MSTP526] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 26, 0), /* SCU5 */ + [MSTP525] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 25, 0), /* SCU6 */ + [MSTP524] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 24, 0), /* SCU7 */ + [MSTP523] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 23, 0), /* SCU8 */ [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */ [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ @@ -173,9 +184,13 @@ static struct clk_lookup lookups[] = { /* MSTP32 clocks */ CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */ + CLKDEV_DEV_ID("ffe4e000.mmc", &mstp_clks[MSTP331]), /* MMC */ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ + CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ + CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ + CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP321]), /* SDHI2 */ CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ @@ -183,9 +198,13 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */ CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ + CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */ CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ + CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */ CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ + CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */ CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ + CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ @@ -195,8 +214,11 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ + CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */ CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ + CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */ CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ + CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */ CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */ CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]), @@ -208,6 +230,15 @@ static struct clk_lookup lookups[] = { CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]), CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]), CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]), + CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]), + CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]), + CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]), + CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]), + CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]), + CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]), + CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]), + CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]), + CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]), }; void __init r8a7778_clock_init(void) diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 1f7080f..f1fb89b 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -184,9 +184,13 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */ CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */ CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ + CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */ CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ + CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */ CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ + CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */ CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ + CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ @@ -194,12 +198,19 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ + CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */ CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ + CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */ CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ + CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ + CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ + CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ + CLKDEV_DEV_ID("ffe4e000.sd", &mstp_clks[MSTP321]), /* SDHI2 */ CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ + CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP320]), /* SDHI3 */ CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ }; diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index a64f965..f44987a 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -53,6 +53,7 @@ #define SMSTPCR7 0xe615014c #define SMSTPCR8 0xe6150990 #define SMSTPCR9 0xe6150994 +#define SMSTPCR10 0xe6150998 #define SDCKCR 0xE6150074 #define SD2CKCR 0xE6150078 @@ -77,7 +78,7 @@ static struct sh_clk_ops followparent_clk_ops = { }; static struct clk main_clk = { - /* .parent will be set r8a73a4_clock_init */ + /* .parent will be set r8a7790_clock_init */ .ops = &followparent_clk_ops, }; @@ -182,10 +183,14 @@ static struct clk div6_clks[DIV6_NR] = { /* MSTP */ enum { + MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010, + MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005, MSTP931, MSTP930, MSTP929, MSTP928, + MSTP917, MSTP813, MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, MSTP717, MSTP716, + MSTP704, MSTP522, MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, @@ -194,10 +199,22 @@ enum { }; static struct clk mstp_clks[MSTP_NR] = { - [MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */ - [MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */ - [MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */ - [MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */ + [MSTP1015] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 15, 0), /* SSI0 */ + [MSTP1014] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 14, 0), /* SSI1 */ + [MSTP1013] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 13, 0), /* SSI2 */ + [MSTP1012] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 12, 0), /* SSI3 */ + [MSTP1011] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 11, 0), /* SSI4 */ + [MSTP1010] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 10, 0), /* SSI5 */ + [MSTP1009] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 9, 0), /* SSI6 */ + [MSTP1008] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 8, 0), /* SSI7 */ + [MSTP1007] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 7, 0), /* SSI8 */ + [MSTP1006] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 6, 0), /* SSI9 */ + [MSTP1005] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 5, 0), /* SSI ALL */ + [MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */ + [MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */ + [MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */ + [MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */ + [MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */ [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */ @@ -208,6 +225,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ + [MSTP704] = SH_CLK_MSTP32(&mp_clk, SMSTPCR7, 4, 0), /* HSUSB */ [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ @@ -262,11 +280,7 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), /* MSTP */ - CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]), - CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]), - CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]), - CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]), - CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]), + CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]), CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), @@ -278,24 +292,50 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]), + CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]), CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]), + CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]), CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]), + CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]), CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]), + CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]), CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), + CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), - CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]), CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), - CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), - CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), - CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), - CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]), + CLKDEV_DEV_ID("ee160000.sd", &mstp_clks[MSTP311]), CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]), - CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), + CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]), CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), + CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), + CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]), + + /* ICK */ + CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]), + CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]), + CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]), + CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]), + CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]), + CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]), + CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]), + CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]), + CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]), + CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]), + CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]), + CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]), + CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]), + CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]), + CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]), + CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]), + }; #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ @@ -321,10 +361,10 @@ void __init r8a7790_clock_init(void) R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); break; case MD(14): - R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102); + R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102); break; case MD(13) | MD(14): - R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88); + R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88); break; } diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c index c9a26f1..f546126 100644 --- a/arch/arm/mach-shmobile/clock-r8a7791.c +++ b/arch/arm/mach-shmobile/clock-r8a7791.c @@ -103,6 +103,7 @@ SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12); SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); +SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3); static struct clk *main_clks[] = { &extal_clk, @@ -116,12 +117,15 @@ static struct clk *main_clks[] = { &rclk_clk, &mp_clk, &cp_clk, + &zx_clk, }; /* MSTP */ enum { - MSTP721, MSTP720, + MSTP813, + MSTP726, MSTP724, MSTP723, MSTP721, MSTP720, MSTP719, MSTP718, MSTP715, MSTP714, + MSTP522, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, MSTP124, @@ -129,12 +133,17 @@ enum { }; static struct clk mstp_clks[MSTP_NR] = { + [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ + [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ + [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */ + [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */ [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */ [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */ [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */ [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */ + [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ @@ -164,6 +173,9 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("peripheral_clk", &hp_clk), /* MSTP */ + CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7791", &mstp_clks[MSTP726]), + CLKDEV_ICK_ID("du.0", "rcar-du-r8a7791", &mstp_clks[MSTP724]), + CLKDEV_ICK_ID("du.1", "rcar-du-r8a7791", &mstp_clks[MSTP723]), CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */ @@ -180,6 +192,9 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), + CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), + CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), + CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */ }; #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 5390c6b..2848997 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -504,10 +504,6 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]), CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]), CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]), - CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]), - CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), - CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), - CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), /* MSTP32 clocks */ CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */ @@ -574,6 +570,11 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */ + /* ICK */ + CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]), + CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), + CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), + CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1", &div6_reparent_clks[DIV6_HDMI]), CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]), diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index c92c023..23edf836 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -625,12 +625,6 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]), CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]), CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]), - CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]), - CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), - CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), - CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), - CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk), - CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk), /* MSTP32 clocks */ CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */ @@ -658,18 +652,19 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */ + CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */ CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */ CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ - CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */ + CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), /* SDHI0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ - CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */ + CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ - CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */ + CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]), /* MMCIF0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */ - CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */ + CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP311]), /* SDHI2 */ CLKDEV_DEV_ID("renesas-tpu-pwm.0", &mstp_clks[MSTP304]), /* TPU0 */ CLKDEV_DEV_ID("renesas-tpu-pwm.1", &mstp_clks[MSTP303]), /* TPU1 */ CLKDEV_DEV_ID("renesas-tpu-pwm.2", &mstp_clks[MSTP302]), /* TPU2 */ @@ -680,6 +675,14 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */ CLKDEV_DEV_ID("e6828000.i2c", &mstp_clks[MSTP410]), /* I2C4 */ CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ + + /* ICK */ + CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]), + CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), + CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), + CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), + CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk), + CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk), }; void __init sh73a0_clock_init(void) diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h index c2eb756..fcb142a 100644 --- a/arch/arm/mach-shmobile/include/mach/emev2.h +++ b/arch/arm/mach-shmobile/include/mach/emev2.h @@ -3,12 +3,7 @@ extern void emev2_map_io(void); extern void emev2_init_delay(void); -extern void emev2_add_standard_devices(void); extern void emev2_clock_init(void); - -#define EMEV2_GPIO_BASE 200 -#define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n)) - extern struct smp_operations emev2_smp_ops; #endif /* __ASM_EMEV2_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h index 441886c..f4076a5 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7778.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h @@ -20,13 +20,50 @@ #define __ASM_R8A7778_H__ #include <linux/sh_eth.h> -#include <linux/platform_data/camera-rcar.h> /* HPB-DMA slave IDs */ enum { HPBDMA_SLAVE_DUMMY, HPBDMA_SLAVE_SDHI0_TX, HPBDMA_SLAVE_SDHI0_RX, + HPBDMA_SLAVE_SSI0_TX, + HPBDMA_SLAVE_SSI0_RX, + HPBDMA_SLAVE_SSI1_TX, + HPBDMA_SLAVE_SSI1_RX, + HPBDMA_SLAVE_SSI2_TX, + HPBDMA_SLAVE_SSI2_RX, + HPBDMA_SLAVE_SSI3_TX, + HPBDMA_SLAVE_SSI3_RX, + HPBDMA_SLAVE_SSI4_TX, + HPBDMA_SLAVE_SSI4_RX, + HPBDMA_SLAVE_SSI5_TX, + HPBDMA_SLAVE_SSI5_RX, + HPBDMA_SLAVE_SSI6_TX, + HPBDMA_SLAVE_SSI6_RX, + HPBDMA_SLAVE_SSI7_TX, + HPBDMA_SLAVE_SSI7_RX, + HPBDMA_SLAVE_SSI8_TX, + HPBDMA_SLAVE_SSI8_RX, + HPBDMA_SLAVE_HPBIF0_TX, + HPBDMA_SLAVE_HPBIF0_RX, + HPBDMA_SLAVE_HPBIF1_TX, + HPBDMA_SLAVE_HPBIF1_RX, + HPBDMA_SLAVE_HPBIF2_TX, + HPBDMA_SLAVE_HPBIF2_RX, + HPBDMA_SLAVE_HPBIF3_TX, + HPBDMA_SLAVE_HPBIF3_RX, + HPBDMA_SLAVE_HPBIF4_TX, + HPBDMA_SLAVE_HPBIF4_RX, + HPBDMA_SLAVE_HPBIF5_TX, + HPBDMA_SLAVE_HPBIF5_RX, + HPBDMA_SLAVE_HPBIF6_TX, + HPBDMA_SLAVE_HPBIF6_RX, + HPBDMA_SLAVE_HPBIF7_TX, + HPBDMA_SLAVE_HPBIF7_RX, + HPBDMA_SLAVE_HPBIF8_TX, + HPBDMA_SLAVE_HPBIF8_RX, + HPBDMA_SLAVE_USBFUNC_TX, + HPBDMA_SLAVE_USBFUNC_RX, }; extern void r8a7778_add_standard_devices(void); diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index 17af34e..b40e136 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -3,8 +3,6 @@ #include <linux/sh_clk.h> #include <linux/pm_domain.h> -#include <linux/sh_eth.h> -#include <linux/platform_data/camera-rcar.h> /* HPB-DMA slave IDs */ enum { @@ -13,8 +11,6 @@ enum { HPBDMA_SLAVE_SDHI0_RX, }; -struct platform_device; - struct r8a7779_pm_ch { unsigned long chan_offs; unsigned int chan_bit; @@ -40,9 +36,6 @@ extern void r8a7779_earlytimer_init(void); extern void r8a7779_add_early_devices(void); extern void r8a7779_add_standard_devices(void); extern void r8a7779_add_standard_devices_dt(void); -extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata); -extern void r8a7779_add_vin_device(int idx, - struct rcar_vin_platform_data *pdata); extern void r8a7779_init_late(void); extern void r8a7779_clock_init(void); extern void r8a7779_pinmux_init(void); diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h index 051ead3..200fa699 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7791.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7791.h @@ -4,6 +4,7 @@ void r8a7791_add_standard_devices(void); void r8a7791_add_dt_devices(void); void r8a7791_clock_init(void); +void r8a7791_pinmux_init(void); void r8a7791_init_early(void); extern struct smp_operations r8a7791_smp_ops; diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index 3ad531c..c8f2a1a 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c @@ -16,24 +16,15 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/clk-provider.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/platform_data/gpio-em.h> #include <linux/of_platform.h> -#include <linux/delay.h> -#include <linux/input.h> -#include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/emev2.h> -#include <mach/irqs.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/mach/time.h> static struct map_desc emev2_io_desc[] __initdata = { #ifdef CONFIG_SMP @@ -52,150 +43,20 @@ void __init emev2_map_io(void) iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc)); } -/* UART */ -static struct resource uart0_resources[] = { - DEFINE_RES_MEM(0xe1020000, 0x38), - DEFINE_RES_IRQ(40), -}; - -static struct resource uart1_resources[] = { - DEFINE_RES_MEM(0xe1030000, 0x38), - DEFINE_RES_IRQ(41), -}; - -static struct resource uart2_resources[] = { - DEFINE_RES_MEM(0xe1040000, 0x38), - DEFINE_RES_IRQ(42), -}; - -static struct resource uart3_resources[] = { - DEFINE_RES_MEM(0xe1050000, 0x38), - DEFINE_RES_IRQ(43), -}; - -#define emev2_register_uart(idx) \ - platform_device_register_simple("serial8250-em", idx, \ - uart##idx##_resources, \ - ARRAY_SIZE(uart##idx##_resources)) - -/* STI */ -static struct resource sti_resources[] = { - DEFINE_RES_MEM(0xe0180000, 0x54), - DEFINE_RES_IRQ(157), -}; - -#define emev2_register_sti() \ - platform_device_register_simple("em_sti", 0, \ - sti_resources, \ - ARRAY_SIZE(sti_resources)) - -/* GIO */ -static struct gpio_em_config gio0_config = { - .gpio_base = 0, - .irq_base = EMEV2_GPIO_IRQ(0), - .number_of_pins = 32, -}; - -static struct resource gio0_resources[] = { - DEFINE_RES_MEM(0xe0050000, 0x2c), - DEFINE_RES_MEM(0xe0050040, 0x20), - DEFINE_RES_IRQ(99), - DEFINE_RES_IRQ(100), -}; - -static struct gpio_em_config gio1_config = { - .gpio_base = 32, - .irq_base = EMEV2_GPIO_IRQ(32), - .number_of_pins = 32, -}; - -static struct resource gio1_resources[] = { - DEFINE_RES_MEM(0xe0050080, 0x2c), - DEFINE_RES_MEM(0xe00500c0, 0x20), - DEFINE_RES_IRQ(101), - DEFINE_RES_IRQ(102), -}; - -static struct gpio_em_config gio2_config = { - .gpio_base = 64, - .irq_base = EMEV2_GPIO_IRQ(64), - .number_of_pins = 32, -}; - -static struct resource gio2_resources[] = { - DEFINE_RES_MEM(0xe0050100, 0x2c), - DEFINE_RES_MEM(0xe0050140, 0x20), - DEFINE_RES_IRQ(103), - DEFINE_RES_IRQ(104), -}; - -static struct gpio_em_config gio3_config = { - .gpio_base = 96, - .irq_base = EMEV2_GPIO_IRQ(96), - .number_of_pins = 32, -}; - -static struct resource gio3_resources[] = { - DEFINE_RES_MEM(0xe0050180, 0x2c), - DEFINE_RES_MEM(0xe00501c0, 0x20), - DEFINE_RES_IRQ(105), - DEFINE_RES_IRQ(106), -}; - -static struct gpio_em_config gio4_config = { - .gpio_base = 128, - .irq_base = EMEV2_GPIO_IRQ(128), - .number_of_pins = 31, -}; - -static struct resource gio4_resources[] = { - DEFINE_RES_MEM(0xe0050200, 0x2c), - DEFINE_RES_MEM(0xe0050240, 0x20), - DEFINE_RES_IRQ(107), - DEFINE_RES_IRQ(108), -}; - -#define emev2_register_gio(idx) \ - platform_device_register_resndata(&platform_bus, "em_gio", \ - idx, gio##idx##_resources, \ - ARRAY_SIZE(gio##idx##_resources), \ - &gio##idx##_config, \ - sizeof(struct gpio_em_config)) - -static struct resource pmu_resources[] = { - DEFINE_RES_IRQ(152), - DEFINE_RES_IRQ(153), -}; - -#define emev2_register_pmu() \ - platform_device_register_simple("arm-pmu", -1, \ - pmu_resources, \ - ARRAY_SIZE(pmu_resources)) - -void __init emev2_add_standard_devices(void) -{ - if (!IS_ENABLED(CONFIG_COMMON_CLK)) - emev2_clock_init(); - - emev2_register_uart(0); - emev2_register_uart(1); - emev2_register_uart(2); - emev2_register_uart(3); - emev2_register_sti(); - emev2_register_gio(0); - emev2_register_gio(1); - emev2_register_gio(2); - emev2_register_gio(3); - emev2_register_gio(4); - emev2_register_pmu(); -} - void __init emev2_init_delay(void) { shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ } -#ifdef CONFIG_USE_OF +static void __init emev2_add_standard_devices_dt(void) +{ +#ifdef CONFIG_COMMON_CLK + of_clk_init(NULL); +#else + emev2_clock_init(); +#endif + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} static const char *emev2_boards_compat_dt[] __initdata = { "renesas,emev2", @@ -206,7 +67,7 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") .smp = smp_ops(emev2_smp_ops), .map_io = emev2_map_io, .init_early = emev2_init_delay, + .init_machine = emev2_add_standard_devices_dt, + .init_late = shmobile_init_late, .dt_compat = emev2_boards_compat_dt, MACHINE_END - -#endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c index d4eb509..9c0b3a9 100644 --- a/arch/arm/mach-shmobile/setup-r7s72100.c +++ b/arch/arm/mach-shmobile/setup-r7s72100.c @@ -22,52 +22,76 @@ #include <linux/kernel.h> #include <linux/of_platform.h> #include <linux/serial_sci.h> +#include <linux/sh_timer.h> #include <mach/common.h> #include <mach/irqs.h> #include <mach/r7s72100.h> #include <asm/mach/arch.h> -#define SCIF_DATA(index, baseaddr, irq) \ -[index] = { \ +#define R7S72100_SCIF(index, baseaddr, irq) \ +static const struct plat_sci_port scif##index##_platform_data = { \ .type = PORT_SCIF, \ .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \ .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ - .scbrr_algo_id = SCBRR_ALGO_2, \ .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \ SCSCR_REIE, \ - .mapbase = baseaddr, \ - .irqs = { irq + 1, irq + 2, irq + 3, irq }, \ -} +}; \ + \ +static struct resource scif##index##_resources[] = { \ + DEFINE_RES_MEM(baseaddr, 0x100), \ + DEFINE_RES_IRQ(irq + 1), \ + DEFINE_RES_IRQ(irq + 2), \ + DEFINE_RES_IRQ(irq + 3), \ + DEFINE_RES_IRQ(irq), \ +} \ + +R7S72100_SCIF(0, 0xe8007000, gic_iid(221)); +R7S72100_SCIF(1, 0xe8007800, gic_iid(225)); +R7S72100_SCIF(2, 0xe8008000, gic_iid(229)); +R7S72100_SCIF(3, 0xe8008800, gic_iid(233)); +R7S72100_SCIF(4, 0xe8009000, gic_iid(237)); +R7S72100_SCIF(5, 0xe8009800, gic_iid(241)); +R7S72100_SCIF(6, 0xe800a000, gic_iid(245)); +R7S72100_SCIF(7, 0xe800a800, gic_iid(249)); -enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 }; +#define r7s72100_register_scif(index) \ + platform_device_register_resndata(&platform_bus, "sh-sci", index, \ + scif##index##_resources, \ + ARRAY_SIZE(scif##index##_resources), \ + &scif##index##_platform_data, \ + sizeof(scif##index##_platform_data)) -static const struct plat_sci_port scif[] __initconst = { - SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */ - SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */ - SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */ - SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */ - SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */ - SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */ - SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */ - SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */ + +static struct sh_timer_config mtu2_0_platform_data __initdata = { + .name = "MTU2_0", + .timer_bit = 0, + .channel_offset = -0x80, + .clockevent_rating = 200, }; -static inline void r7s72100_register_scif(int idx) -{ - platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], - sizeof(struct plat_sci_port)); -} +static struct resource mtu2_0_resources[] __initdata = { + DEFINE_RES_MEM(0xfcff0300, 0x27), + DEFINE_RES_IRQ(gic_iid(139)), /* MTU2 TGI0A */ +}; + +#define r7s72100_register_mtu2(idx) \ + platform_device_register_resndata(&platform_bus, "sh_mtu2", \ + idx, mtu2_##idx##_resources, \ + ARRAY_SIZE(mtu2_##idx##_resources), \ + &mtu2_##idx##_platform_data, \ + sizeof(struct sh_timer_config)) void __init r7s72100_add_dt_devices(void) { - r7s72100_register_scif(SCIF0); - r7s72100_register_scif(SCIF1); - r7s72100_register_scif(SCIF2); - r7s72100_register_scif(SCIF3); - r7s72100_register_scif(SCIF4); - r7s72100_register_scif(SCIF5); - r7s72100_register_scif(SCIF6); - r7s72100_register_scif(SCIF7); + r7s72100_register_scif(0); + r7s72100_register_scif(1); + r7s72100_register_scif(2); + r7s72100_register_scif(3); + r7s72100_register_scif(4); + r7s72100_register_scif(5); + r7s72100_register_scif(6); + r7s72100_register_scif(7); + r7s72100_register_mtu2(0); } void __init r7s72100_init_early(void) diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index b0f2749..cd36f80 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -40,41 +40,39 @@ void __init r8a73a4_pinmux_init(void) ARRAY_SIZE(pfc_resources)); } -#define SCIF_COMMON(scif_type, baseaddr, irq) \ +#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \ +static struct plat_sci_port scif##index##_platform_data = { \ .type = scif_type, \ - .mapbase = baseaddr, \ .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ - .scbrr_algo_id = SCBRR_ALGO_4, \ - .irqs = SCIx_IRQ_MUXED(irq) - -#define SCIFA_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ + .scscr = _scscr, \ +}; \ + \ +static struct resource scif##index##_resources[] = { \ + DEFINE_RES_MEM(baseaddr, 0x100), \ + DEFINE_RES_IRQ(irq), \ } -#define SCIFB_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ - .scscr = SCSCR_RE | SCSCR_TE, \ -} +#define R8A73A4_SCIFA(index, baseaddr, irq) \ + R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ + index, baseaddr, irq) -enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 }; +#define R8A73A4_SCIFB(index, baseaddr, irq) \ + R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \ + index, baseaddr, irq) -static const struct plat_sci_port scif[] = { - SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ - SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ - SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ - SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ - SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ - SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */ -}; +R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ +R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ +R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ +R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ +R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ +R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */ -static inline void r8a73a4_register_scif(int idx) -{ - platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], - sizeof(struct plat_sci_port)); -} +#define r8a73a4_register_scif(index) \ + platform_device_register_resndata(&platform_bus, "sh-sci", index, \ + scif##index##_resources, \ + ARRAY_SIZE(scif##index##_resources), \ + &scif##index##_platform_data, \ + sizeof(scif##index##_platform_data)) static const struct renesas_irqc_config irqc0_data = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ @@ -192,12 +190,12 @@ static struct resource cmt10_resources[] = { void __init r8a73a4_add_dt_devices(void) { - r8a73a4_register_scif(SCIFA0); - r8a73a4_register_scif(SCIFA1); - r8a73a4_register_scif(SCIFB0); - r8a73a4_register_scif(SCIFB1); - r8a73a4_register_scif(SCIFB2); - r8a73a4_register_scif(SCIFB3); + r8a73a4_register_scif(0); + r8a73a4_register_scif(1); + r8a73a4_register_scif(2); + r8a73a4_register_scif(3); + r8a73a4_register_scif(4); + r8a73a4_register_scif(5); r8a7790_register_cmt(10); } @@ -275,7 +273,7 @@ static const struct sh_dmae_pdata dma_pdata = { static struct resource dma_resources[] = { DEFINE_RES_MEM(0xe6700020, 0x89e0), - DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"), + DEFINE_RES_IRQ(gic_spi(220)), { /* IRQ for channels 0-19 */ .start = gic_spi(200), diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index b7d4b2c..8f3c681 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -203,167 +203,38 @@ static struct platform_device irqpin3_device = { }, }; -/* SCIFA0 */ -static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xe6c40000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(100)), -}; - -static struct platform_device scif0_device = { - .name = "sh-sci", - .id = 0, - .dev = { - .platform_data = &scif0_platform_data, - }, -}; - -/* SCIFA1 */ -static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xe6c50000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(101)), -}; - -static struct platform_device scif1_device = { - .name = "sh-sci", - .id = 1, - .dev = { - .platform_data = &scif1_platform_data, - }, -}; - -/* SCIFA2 */ -static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xe6c60000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(102)), -}; - -static struct platform_device scif2_device = { - .name = "sh-sci", - .id = 2, - .dev = { - .platform_data = &scif2_platform_data, - }, -}; - -/* SCIFA3 */ -static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xe6c70000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(103)), -}; - -static struct platform_device scif3_device = { - .name = "sh-sci", - .id = 3, - .dev = { - .platform_data = &scif3_platform_data, - }, -}; - -/* SCIFA4 */ -static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xe6c80000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(104)), -}; - -static struct platform_device scif4_device = { - .name = "sh-sci", - .id = 4, - .dev = { - .platform_data = &scif4_platform_data, - }, -}; - -/* SCIFA5 */ -static struct plat_sci_port scif5_platform_data = { - .mapbase = 0xe6cb0000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(105)), -}; - -static struct platform_device scif5_device = { - .name = "sh-sci", - .id = 5, - .dev = { - .platform_data = &scif5_platform_data, - }, -}; - -/* SCIFA6 */ -static struct plat_sci_port scif6_platform_data = { - .mapbase = 0xe6cc0000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(106)), -}; - -static struct platform_device scif6_device = { - .name = "sh-sci", - .id = 6, - .dev = { - .platform_data = &scif6_platform_data, - }, -}; - -/* SCIFA7 */ -static struct plat_sci_port scif7_platform_data = { - .mapbase = 0xe6cd0000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(107)), -}; - -static struct platform_device scif7_device = { - .name = "sh-sci", - .id = 7, - .dev = { - .platform_data = &scif7_platform_data, - }, -}; - -/* SCIFB */ -static struct plat_sci_port scifb_platform_data = { - .mapbase = 0xe6c30000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFB, - .irqs = SCIx_IRQ_MUXED(gic_spi(108)), -}; +/* SCIF */ +#define R8A7740_SCIF(scif_type, index, baseaddr, irq) \ +static struct plat_sci_port scif##index##_platform_data = { \ + .type = scif_type, \ + .flags = UPF_BOOT_AUTOCONF, \ + .scscr = SCSCR_RE | SCSCR_TE, \ +}; \ + \ +static struct resource scif##index##_resources[] = { \ + DEFINE_RES_MEM(baseaddr, 0x100), \ + DEFINE_RES_IRQ(irq), \ +}; \ + \ +static struct platform_device scif##index##_device = { \ + .name = "sh-sci", \ + .id = index, \ + .resource = scif##index##_resources, \ + .num_resources = ARRAY_SIZE(scif##index##_resources), \ + .dev = { \ + .platform_data = &scif##index##_platform_data, \ + }, \ +} -static struct platform_device scifb_device = { - .name = "sh-sci", - .id = 8, - .dev = { - .platform_data = &scifb_platform_data, - }, -}; +R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100)); +R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101)); +R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102)); +R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103)); +R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104)); +R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105)); +R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106)); +R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107)); +R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108)); /* CMT */ static struct sh_timer_config cmt10_platform_data = { @@ -528,7 +399,7 @@ static struct platform_device *r8a7740_devices_dt[] __initdata = { &scif5_device, &scif6_device, &scif7_device, - &scifb_device, + &scif8_device, &cmt10_device, }; @@ -981,7 +852,7 @@ void __init r8a7740_add_standard_devices(void) rmobile_add_device_to_domain("A3SP", &scif5_device); rmobile_add_device_to_domain("A3SP", &scif6_device); rmobile_add_device_to_domain("A3SP", &scif7_device); - rmobile_add_device_to_domain("A3SP", &scifb_device); + rmobile_add_device_to_domain("A3SP", &scif8_device); rmobile_add_device_to_domain("A3SP", &i2c1_device); } diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 03fcc59..6d69452 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -44,24 +44,31 @@ #include <asm/hardware/cache-l2x0.h> /* SCIF */ -#define SCIF_INFO(baseaddr, irq) \ -{ \ - .mapbase = baseaddr, \ +#define R8A7778_SCIF(index, baseaddr, irq) \ +static struct plat_sci_port scif##index##_platform_data = { \ .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ - .scbrr_algo_id = SCBRR_ALGO_2, \ .type = PORT_SCIF, \ - .irqs = SCIx_IRQ_MUXED(irq), \ +}; \ + \ +static struct resource scif##index##_resources[] = { \ + DEFINE_RES_MEM(baseaddr, 0x100), \ + DEFINE_RES_IRQ(irq), \ } -static struct plat_sci_port scif_platform_data[] __initdata = { - SCIF_INFO(0xffe40000, gic_iid(0x66)), - SCIF_INFO(0xffe41000, gic_iid(0x67)), - SCIF_INFO(0xffe42000, gic_iid(0x68)), - SCIF_INFO(0xffe43000, gic_iid(0x69)), - SCIF_INFO(0xffe44000, gic_iid(0x6a)), - SCIF_INFO(0xffe45000, gic_iid(0x6b)), -}; +R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66)); +R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67)); +R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68)); +R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69)); +R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a)); +R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b)); + +#define r8a7778_register_scif(index) \ + platform_device_register_resndata(&platform_bus, "sh-sci", index, \ + scif##index##_resources, \ + ARRAY_SIZE(scif##index##_resources), \ + &scif##index##_platform_data, \ + sizeof(scif##index##_platform_data)) /* TMU */ static struct resource sh_tmu0_resources[] __initdata = { @@ -287,8 +294,6 @@ static void __init r8a7778_register_hspi(int id) void __init r8a7778_add_dt_devices(void) { - int i; - #ifdef CONFIG_CACHE_L2X0 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); if (base) { @@ -300,11 +305,12 @@ void __init r8a7778_add_dt_devices(void) } #endif - for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) - platform_device_register_data(&platform_bus, "sh-sci", i, - &scif_platform_data[i], - sizeof(struct plat_sci_port)); - + r8a7778_register_scif(0); + r8a7778_register_scif(1); + r8a7778_register_scif(2); + r8a7778_register_scif(3); + r8a7778_register_scif(4); + r8a7778_register_scif(5); r8a7778_register_tmu(0); r8a7778_register_tmu(1); } @@ -319,6 +325,52 @@ void __init r8a7778_add_dt_devices(void) #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ +#define HPBDMA_SSI(_id) \ +{ \ + .id = HPBDMA_SLAVE_SSI## _id ##_TX, \ + .addr = 0xffd91008 + (_id * 0x40), \ + .dcr = HPB_DMAE_DCR_CT | \ + HPB_DMAE_DCR_DIP | \ + HPB_DMAE_DCR_SPDS_32BIT | \ + HPB_DMAE_DCR_DMDL | \ + HPB_DMAE_DCR_DPDS_32BIT, \ + .port = _id + (_id << 8), \ + .dma_ch = (28 + _id), \ +}, { \ + .id = HPBDMA_SLAVE_SSI## _id ##_RX, \ + .addr = 0xffd9100c + (_id * 0x40), \ + .dcr = HPB_DMAE_DCR_CT | \ + HPB_DMAE_DCR_DIP | \ + HPB_DMAE_DCR_SMDL | \ + HPB_DMAE_DCR_SPDS_32BIT | \ + HPB_DMAE_DCR_DPDS_32BIT, \ + .port = _id + (_id << 8), \ + .dma_ch = (28 + _id), \ +} + +#define HPBDMA_HPBIF(_id) \ +{ \ + .id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \ + .addr = 0xffda0000 + (_id * 0x1000), \ + .dcr = HPB_DMAE_DCR_CT | \ + HPB_DMAE_DCR_DIP | \ + HPB_DMAE_DCR_SPDS_32BIT | \ + HPB_DMAE_DCR_DMDL | \ + HPB_DMAE_DCR_DPDS_32BIT, \ + .port = 0x1111, \ + .dma_ch = (28 + _id), \ +}, { \ + .id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \ + .addr = 0xffda0000 + (_id * 0x1000), \ + .dcr = HPB_DMAE_DCR_CT | \ + HPB_DMAE_DCR_DIP | \ + HPB_DMAE_DCR_SMDL | \ + HPB_DMAE_DCR_SPDS_32BIT | \ + HPB_DMAE_DCR_DPDS_32BIT, \ + .port = 0x1111, \ + .dma_ch = (28 + _id), \ +} + static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { { .id = HPBDMA_SLAVE_SDHI0_TX, @@ -348,12 +400,86 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { .port = 0x0D0C, .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, .dma_ch = 22, + }, { + .id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */ + .addr = 0xffe60018, + .dcr = HPB_DMAE_DCR_SPDS_32BIT | + HPB_DMAE_DCR_DMDL | + HPB_DMAE_DCR_DPDS_32BIT, + .port = 0x0000, + .dma_ch = 14, + }, { + .id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */ + .addr = 0xffe6001c, + .dcr = HPB_DMAE_DCR_SMDL | + HPB_DMAE_DCR_SPDS_32BIT | + HPB_DMAE_DCR_DPDS_32BIT, + .port = 0x0101, + .dma_ch = 15, }, + + HPBDMA_SSI(0), + HPBDMA_SSI(1), + HPBDMA_SSI(2), + HPBDMA_SSI(3), + HPBDMA_SSI(4), + HPBDMA_SSI(5), + HPBDMA_SSI(6), + HPBDMA_SSI(7), + HPBDMA_SSI(8), + + HPBDMA_HPBIF(0), + HPBDMA_HPBIF(1), + HPBDMA_HPBIF(2), + HPBDMA_HPBIF(3), + HPBDMA_HPBIF(4), + HPBDMA_HPBIF(5), + HPBDMA_HPBIF(6), + HPBDMA_HPBIF(7), + HPBDMA_HPBIF(8), }; static const struct hpb_dmae_channel hpb_dmae_channels[] = { + HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */ + HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */ HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */ + HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */ }; static struct hpb_dmae_pdata dma_platform_data __initdata = { diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 13049e9..8e860b3 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -188,107 +188,35 @@ void __init r8a7779_pinmux_init(void) ARRAY_SIZE(r8a7779_pinctrl_devices)); } -static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xffe40000, - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_2, - .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)), -}; - -static struct platform_device scif0_device = { - .name = "sh-sci", - .id = 0, - .dev = { - .platform_data = &scif0_platform_data, - }, -}; - -static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xffe41000, - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_2, - .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)), -}; - -static struct platform_device scif1_device = { - .name = "sh-sci", - .id = 1, - .dev = { - .platform_data = &scif1_platform_data, - }, -}; - -static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xffe42000, - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_2, - .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)), -}; - -static struct platform_device scif2_device = { - .name = "sh-sci", - .id = 2, - .dev = { - .platform_data = &scif2_platform_data, - }, -}; - -static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xffe43000, - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_2, - .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)), -}; - -static struct platform_device scif3_device = { - .name = "sh-sci", - .id = 3, - .dev = { - .platform_data = &scif3_platform_data, - }, -}; - -static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xffe44000, - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_2, - .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)), -}; - -static struct platform_device scif4_device = { - .name = "sh-sci", - .id = 4, - .dev = { - .platform_data = &scif4_platform_data, - }, -}; - -static struct plat_sci_port scif5_platform_data = { - .mapbase = 0xffe45000, - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_2, - .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)), -}; +/* SCIF */ +#define R8A7779_SCIF(index, baseaddr, irq) \ +static struct plat_sci_port scif##index##_platform_data = { \ + .type = PORT_SCIF, \ + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ +}; \ + \ +static struct resource scif##index##_resources[] = { \ + DEFINE_RES_MEM(baseaddr, 0x100), \ + DEFINE_RES_IRQ(irq), \ +}; \ + \ +static struct platform_device scif##index##_device = { \ + .name = "sh-sci", \ + .id = index, \ + .resource = scif##index##_resources, \ + .num_resources = ARRAY_SIZE(scif##index##_resources), \ + .dev = { \ + .platform_data = &scif##index##_platform_data, \ + }, \ +} -static struct platform_device scif5_device = { - .name = "sh-sci", - .id = 5, - .dev = { - .platform_data = &scif5_platform_data, - }, -}; +R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78)); +R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79)); +R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a)); +R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b)); +R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c)); +R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d)); /* TMU */ static struct sh_timer_config tmu00_platform_data = { @@ -598,45 +526,6 @@ static struct platform_device ohci1_device = { .resource = ohci1_resources, }; -/* Ether */ -static struct resource ether_resources[] __initdata = { - { - .start = 0xfde00000, - .end = 0xfde003ff, - .flags = IORESOURCE_MEM, - }, { - .start = gic_iid(0xb4), - .flags = IORESOURCE_IRQ, - }, -}; - -#define R8A7779_VIN(idx) \ -static struct resource vin##idx##_resources[] __initdata = { \ - DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ - DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \ -}; \ - \ -static struct platform_device_info vin##idx##_info __initdata = { \ - .parent = &platform_bus, \ - .name = "r8a7779-vin", \ - .id = idx, \ - .res = vin##idx##_resources, \ - .num_res = ARRAY_SIZE(vin##idx##_resources), \ - .dma_mask = DMA_BIT_MASK(32), \ -} - -R8A7779_VIN(0); -R8A7779_VIN(1); -R8A7779_VIN(2); -R8A7779_VIN(3); - -static struct platform_device_info *vin_info_table[] __initdata = { - &vin0_info, - &vin1_info, - &vin2_info, - &vin3_info, -}; - /* HPB-DMA */ /* Asynchronous mode register bits */ @@ -825,24 +714,6 @@ void __init r8a7779_add_standard_devices(void) r8a7779_register_hpb_dmae(); } -void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) -{ - platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, - ether_resources, - ARRAY_SIZE(ether_resources), - pdata, sizeof(*pdata)); -} - -void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata) -{ - BUG_ON(id < 0 || id > 3); - - vin_info_table[id]->data = pdata; - vin_info_table[id]->size_data = sizeof(*pdata); - - platform_device_register_full(vin_info_table[id]); -} - /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ void __init __weak r8a7779_register_twd(void) { } diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index c47bcebb..6ab37aa 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -34,6 +34,10 @@ static const struct resource pfc_resources[] __initconst = { DEFINE_RES_MEM(0xe6060000, 0x250), }; +#define r8a7790_register_pfc() \ + platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \ + ARRAY_SIZE(pfc_resources)) + #define R8A7790_GPIO(idx) \ static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \ DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \ @@ -63,73 +67,87 @@ R8A7790_GPIO(5); &r8a7790_gpio##idx##_platform_data, \ sizeof(r8a7790_gpio##idx##_platform_data)) +static struct resource i2c_resources[] __initdata = { + /* I2C0 */ + DEFINE_RES_MEM(0xE6508000, 0x40), + DEFINE_RES_IRQ(gic_spi(287)), + /* I2C1 */ + DEFINE_RES_MEM(0xE6518000, 0x40), + DEFINE_RES_IRQ(gic_spi(288)), + /* I2C2 */ + DEFINE_RES_MEM(0xE6530000, 0x40), + DEFINE_RES_IRQ(gic_spi(286)), + /* I2C3 */ + DEFINE_RES_MEM(0xE6540000, 0x40), + DEFINE_RES_IRQ(gic_spi(290)), + +}; + +#define r8a7790_register_i2c(idx) \ + platform_device_register_simple( \ + "i2c-rcar_gen2", idx, \ + i2c_resources + (2 * idx), 2); \ + void __init r8a7790_pinmux_init(void) { - platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, - ARRAY_SIZE(pfc_resources)); + r8a7790_register_pfc(); r8a7790_register_gpio(0); r8a7790_register_gpio(1); r8a7790_register_gpio(2); r8a7790_register_gpio(3); r8a7790_register_gpio(4); r8a7790_register_gpio(5); + r8a7790_register_i2c(0); + r8a7790_register_i2c(1); + r8a7790_register_i2c(2); + r8a7790_register_i2c(3); } -#define SCIF_COMMON(scif_type, baseaddr, irq) \ - .type = scif_type, \ - .mapbase = baseaddr, \ - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ - .irqs = SCIx_IRQ_MUXED(irq) - -#define SCIFA_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_4, \ - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ -} - -#define SCIFB_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_4, \ - .scscr = SCSCR_RE | SCSCR_TE, \ -} - -#define SCIF_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_2, \ - .scscr = SCSCR_RE | SCSCR_TE, \ -} - -#define HSCIF_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_6, \ - .scscr = SCSCR_RE | SCSCR_TE, \ +#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \ +static struct plat_sci_port scif##index##_platform_data = { \ + .type = scif_type, \ + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ + .scscr = _scscr, \ +}; \ + \ +static struct resource scif##index##_resources[] = { \ + DEFINE_RES_MEM(baseaddr, 0x100), \ + DEFINE_RES_IRQ(irq), \ } -enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, - HSCIF0, HSCIF1 }; - -static const struct plat_sci_port scif[] __initconst = { - SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ - SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ - SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ - SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ - SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ - SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ - SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ - SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ - HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */ - HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */ -}; - -static inline void r8a7790_register_scif(int idx) -{ - platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], - sizeof(struct plat_sci_port)); -} +#define R8A7790_SCIF(index, baseaddr, irq) \ + __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \ + index, baseaddr, irq) + +#define R8A7790_SCIFA(index, baseaddr, irq) \ + __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ + index, baseaddr, irq) + +#define R8A7790_SCIFB(index, baseaddr, irq) \ + __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \ + index, baseaddr, irq) + +#define R8A7790_HSCIF(index, baseaddr, irq) \ + __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \ + index, baseaddr, irq) + +R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ +R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ +R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ +R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ +R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ +R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */ +R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */ +R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */ +R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */ +R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */ + +#define r8a7790_register_scif(index) \ + platform_device_register_resndata(&platform_bus, "sh-sci", index, \ + scif##index##_resources, \ + ARRAY_SIZE(scif##index##_resources), \ + &scif##index##_platform_data, \ + sizeof(scif##index##_platform_data)) static const struct renesas_irqc_config irqc0_data __initconst = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ @@ -182,16 +200,16 @@ static const struct resource cmt00_resources[] __initconst = { void __init r8a7790_add_dt_devices(void) { - r8a7790_register_scif(SCIFA0); - r8a7790_register_scif(SCIFA1); - r8a7790_register_scif(SCIFB0); - r8a7790_register_scif(SCIFB1); - r8a7790_register_scif(SCIFB2); - r8a7790_register_scif(SCIFA2); - r8a7790_register_scif(SCIF0); - r8a7790_register_scif(SCIF1); - r8a7790_register_scif(HSCIF0); - r8a7790_register_scif(HSCIF1); + r8a7790_register_scif(0); + r8a7790_register_scif(1); + r8a7790_register_scif(2); + r8a7790_register_scif(3); + r8a7790_register_scif(4); + r8a7790_register_scif(5); + r8a7790_register_scif(6); + r8a7790_register_scif(7); + r8a7790_register_scif(8); + r8a7790_register_scif(9); r8a7790_register_cmt(00); } diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c index d9393d6..e28404e 100644 --- a/arch/arm/mach-shmobile/setup-r8a7791.c +++ b/arch/arm/mach-shmobile/setup-r8a7791.c @@ -22,6 +22,7 @@ #include <linux/irq.h> #include <linux/kernel.h> #include <linux/of_platform.h> +#include <linux/platform_data/gpio-rcar.h> #include <linux/platform_data/irq-renesas-irqc.h> #include <linux/serial_sci.h> #include <linux/sh_timer.h> @@ -31,66 +32,101 @@ #include <mach/rcar-gen2.h> #include <asm/mach/arch.h> -#define SCIF_COMMON(scif_type, baseaddr, irq) \ - .type = scif_type, \ - .mapbase = baseaddr, \ - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ - .irqs = SCIx_IRQ_MUXED(irq) - -#define SCIFA_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_4, \ - .scscr = SCSCR_RE | SCSCR_TE, \ -} - -#define SCIFB_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_4, \ - .scscr = SCSCR_RE | SCSCR_TE, \ -} +static const struct resource pfc_resources[] __initconst = { + DEFINE_RES_MEM(0xe6060000, 0x250), +}; -#define SCIF_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_2, \ - .scscr = SCSCR_RE | SCSCR_TE, \ +#define r8a7791_register_pfc() \ + platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \ + ARRAY_SIZE(pfc_resources)) + +#define R8A7791_GPIO(idx, base, nr) \ +static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \ + DEFINE_RES_MEM((base), 0x50), \ + DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ +}; \ + \ +static const struct gpio_rcar_config \ +r8a7791_gpio##idx##_platform_data __initconst = { \ + .gpio_base = 32 * (idx), \ + .irq_base = 0, \ + .number_of_pins = (nr), \ + .pctl_name = "pfc-r8a7791", \ + .has_both_edge_trigger = 1, \ +}; \ + +R8A7791_GPIO(0, 0xe6050000, 32); +R8A7791_GPIO(1, 0xe6051000, 32); +R8A7791_GPIO(2, 0xe6052000, 32); +R8A7791_GPIO(3, 0xe6053000, 32); +R8A7791_GPIO(4, 0xe6054000, 32); +R8A7791_GPIO(5, 0xe6055000, 32); +R8A7791_GPIO(6, 0xe6055400, 32); +R8A7791_GPIO(7, 0xe6055800, 26); + +#define r8a7791_register_gpio(idx) \ + platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \ + r8a7791_gpio##idx##_resources, \ + ARRAY_SIZE(r8a7791_gpio##idx##_resources), \ + &r8a7791_gpio##idx##_platform_data, \ + sizeof(r8a7791_gpio##idx##_platform_data)) + +void __init r8a7791_pinmux_init(void) +{ + r8a7791_register_pfc(); + r8a7791_register_gpio(0); + r8a7791_register_gpio(1); + r8a7791_register_gpio(2); + r8a7791_register_gpio(3); + r8a7791_register_gpio(4); + r8a7791_register_gpio(5); + r8a7791_register_gpio(6); + r8a7791_register_gpio(7); } -#define HSCIF_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_6, \ - .scscr = SCSCR_RE | SCSCR_TE, \ +#define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \ +static struct plat_sci_port scif##index##_platform_data = { \ + .type = scif_type, \ + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ + .scscr = SCSCR_RE | SCSCR_TE, \ +}; \ + \ +static struct resource scif##index##_resources[] = { \ + DEFINE_RES_MEM(baseaddr, 0x100), \ + DEFINE_RES_IRQ(irq), \ } -enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, - SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 }; - -static const struct plat_sci_port scif[] __initconst = { - SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ - SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ - SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ - SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ - SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ - SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ - SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ - SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ - SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */ - SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */ - SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */ - SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */ - SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */ - SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */ - SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */ -}; - -static inline void r8a7791_register_scif(int idx) -{ - platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], - sizeof(struct plat_sci_port)); -} +#define R8A7791_SCIF(index, baseaddr, irq) \ + __R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq) + +#define R8A7791_SCIFA(index, baseaddr, irq) \ + __R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq) + +#define R8A7791_SCIFB(index, baseaddr, irq) \ + __R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq) + +R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ +R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ +R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ +R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ +R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ +R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */ +R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */ +R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */ +R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */ +R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */ +R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */ +R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */ +R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */ +R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */ +R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */ + +#define r8a7791_register_scif(index) \ + platform_device_register_resndata(&platform_bus, "sh-sci", index, \ + scif##index##_resources, \ + ARRAY_SIZE(scif##index##_resources), \ + &scif##index##_platform_data, \ + sizeof(scif##index##_platform_data)) static const struct sh_timer_config cmt00_platform_data __initconst = { .name = "CMT00", @@ -136,23 +172,34 @@ static struct resource irqc0_resources[] = { &irqc##idx##_data, \ sizeof(struct renesas_irqc_config)) +static const struct resource thermal_resources[] __initconst = { + DEFINE_RES_MEM(0xe61f0000, 0x14), + DEFINE_RES_MEM(0xe61f0100, 0x38), + DEFINE_RES_IRQ(gic_spi(69)), +}; + +#define r8a7791_register_thermal() \ + platform_device_register_simple("rcar_thermal", -1, \ + thermal_resources, \ + ARRAY_SIZE(thermal_resources)) + void __init r8a7791_add_dt_devices(void) { - r8a7791_register_scif(SCIFA0); - r8a7791_register_scif(SCIFA1); - r8a7791_register_scif(SCIFB0); - r8a7791_register_scif(SCIFB1); - r8a7791_register_scif(SCIFB2); - r8a7791_register_scif(SCIFA2); - r8a7791_register_scif(SCIF0); - r8a7791_register_scif(SCIF1); - r8a7791_register_scif(SCIF2); - r8a7791_register_scif(SCIF3); - r8a7791_register_scif(SCIF4); - r8a7791_register_scif(SCIF5); - r8a7791_register_scif(SCIFA3); - r8a7791_register_scif(SCIFA4); - r8a7791_register_scif(SCIFA5); + r8a7791_register_scif(0); + r8a7791_register_scif(1); + r8a7791_register_scif(2); + r8a7791_register_scif(3); + r8a7791_register_scif(4); + r8a7791_register_scif(5); + r8a7791_register_scif(6); + r8a7791_register_scif(7); + r8a7791_register_scif(8); + r8a7791_register_scif(9); + r8a7791_register_scif(10); + r8a7791_register_scif(11); + r8a7791_register_scif(12); + r8a7791_register_scif(13); + r8a7791_register_scif(14); r8a7791_register_cmt(00); } @@ -160,6 +207,7 @@ void __init r8a7791_add_standard_devices(void) { r8a7791_add_dt_devices(); r8a7791_register_irqc(0); + r8a7791_register_thermal(); } void __init r8a7791_init_early(void) diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 5734c24..69ccc6c6 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/clk/shmobile.h> #include <linux/clocksource.h> #include <linux/io.h> #include <linux/kernel.h> @@ -44,8 +45,10 @@ u32 __init rcar_gen2_read_mode_pins(void) void __init rcar_gen2_timer_init(void) { -#ifdef CONFIG_ARM_ARCH_TIMER +#if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK) u32 mode = rcar_gen2_read_mode_pins(); +#endif +#ifdef CONFIG_ARM_ARCH_TIMER void __iomem *base; int extal_mhz = 0; u32 freq; @@ -78,14 +81,28 @@ void __init rcar_gen2_timer_init(void) /* Remap "armgcnt address map" space */ base = ioremap(0xe6080000, PAGE_SIZE); - /* Update registers with correct frequency */ - iowrite32(freq, base + CNTFID0); - asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); + /* + * Update the timer if it is either not running, or is not at the + * right frequency. The timer is only configurable in secure mode + * so this avoids an abort if the loader started the timer and + * entered the kernel in non-secure mode. + */ + + if ((ioread32(base + CNTCR) & 1) == 0 || + ioread32(base + CNTFID0) != freq) { + /* Update registers with correct frequency */ + iowrite32(freq, base + CNTFID0); + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); + + /* make sure arch timer is started by setting bit 0 of CNTCR */ + iowrite32(1, base + CNTCR); + } - /* make sure arch timer is started by setting bit 0 of CNTCR */ - iowrite32(1, base + CNTCR); iounmap(base); #endif /* CONFIG_ARM_ARCH_TIMER */ +#ifdef CONFIG_COMMON_CLK + rcar_gen2_clocks_init(mode); +#endif clocksource_of_init(); } diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 3118783..2730127 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -86,138 +86,36 @@ void __init sh7372_pinmux_init(void) platform_device_register(&sh7372_pfc_device); } -/* SCIFA0 */ -static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xe6c40000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { evt2irq(0x0c00), evt2irq(0x0c00), - evt2irq(0x0c00), evt2irq(0x0c00) }, -}; - -static struct platform_device scif0_device = { - .name = "sh-sci", - .id = 0, - .dev = { - .platform_data = &scif0_platform_data, - }, -}; - -/* SCIFA1 */ -static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xe6c50000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { evt2irq(0x0c20), evt2irq(0x0c20), - evt2irq(0x0c20), evt2irq(0x0c20) }, -}; - -static struct platform_device scif1_device = { - .name = "sh-sci", - .id = 1, - .dev = { - .platform_data = &scif1_platform_data, - }, -}; - -/* SCIFA2 */ -static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xe6c60000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { evt2irq(0x0c40), evt2irq(0x0c40), - evt2irq(0x0c40), evt2irq(0x0c40) }, -}; - -static struct platform_device scif2_device = { - .name = "sh-sci", - .id = 2, - .dev = { - .platform_data = &scif2_platform_data, - }, -}; - -/* SCIFA3 */ -static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xe6c70000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { evt2irq(0x0c60), evt2irq(0x0c60), - evt2irq(0x0c60), evt2irq(0x0c60) }, -}; - -static struct platform_device scif3_device = { - .name = "sh-sci", - .id = 3, - .dev = { - .platform_data = &scif3_platform_data, - }, -}; - -/* SCIFA4 */ -static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xe6c80000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { evt2irq(0x0d20), evt2irq(0x0d20), - evt2irq(0x0d20), evt2irq(0x0d20) }, -}; - -static struct platform_device scif4_device = { - .name = "sh-sci", - .id = 4, - .dev = { - .platform_data = &scif4_platform_data, - }, -}; - -/* SCIFA5 */ -static struct plat_sci_port scif5_platform_data = { - .mapbase = 0xe6cb0000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { evt2irq(0x0d40), evt2irq(0x0d40), - evt2irq(0x0d40), evt2irq(0x0d40) }, -}; - -static struct platform_device scif5_device = { - .name = "sh-sci", - .id = 5, - .dev = { - .platform_data = &scif5_platform_data, - }, -}; - -/* SCIFB */ -static struct plat_sci_port scif6_platform_data = { - .mapbase = 0xe6c30000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFB, - .irqs = { evt2irq(0x0d60), evt2irq(0x0d60), - evt2irq(0x0d60), evt2irq(0x0d60) }, -}; +/* SCIF */ +#define SH7372_SCIF(scif_type, index, baseaddr, irq) \ +static struct plat_sci_port scif##index##_platform_data = { \ + .type = scif_type, \ + .flags = UPF_BOOT_AUTOCONF, \ + .scscr = SCSCR_RE | SCSCR_TE, \ +}; \ + \ +static struct resource scif##index##_resources[] = { \ + DEFINE_RES_MEM(baseaddr, 0x100), \ + DEFINE_RES_IRQ(irq), \ +}; \ + \ +static struct platform_device scif##index##_device = { \ + .name = "sh-sci", \ + .id = index, \ + .resource = scif##index##_resources, \ + .num_resources = ARRAY_SIZE(scif##index##_resources), \ + .dev = { \ + .platform_data = &scif##index##_platform_data, \ + }, \ +} -static struct platform_device scif6_device = { - .name = "sh-sci", - .id = 6, - .dev = { - .platform_data = &scif6_platform_data, - }, -}; +SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00)); +SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20)); +SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40)); +SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60)); +SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20)); +SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40)); +SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60)); /* CMT */ static struct sh_timer_config cmt2_platform_data = { diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 22de174..f74ab53 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -71,167 +71,38 @@ void __init sh73a0_pinmux_init(void) ARRAY_SIZE(pfc_resources)); } -static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xe6c40000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { gic_spi(72), gic_spi(72), - gic_spi(72), gic_spi(72) }, -}; - -static struct platform_device scif0_device = { - .name = "sh-sci", - .id = 0, - .dev = { - .platform_data = &scif0_platform_data, - }, -}; - -static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xe6c50000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { gic_spi(73), gic_spi(73), - gic_spi(73), gic_spi(73) }, -}; - -static struct platform_device scif1_device = { - .name = "sh-sci", - .id = 1, - .dev = { - .platform_data = &scif1_platform_data, - }, -}; - -static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xe6c60000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { gic_spi(74), gic_spi(74), - gic_spi(74), gic_spi(74) }, -}; - -static struct platform_device scif2_device = { - .name = "sh-sci", - .id = 2, - .dev = { - .platform_data = &scif2_platform_data, - }, -}; - -static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xe6c70000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { gic_spi(75), gic_spi(75), - gic_spi(75), gic_spi(75) }, -}; - -static struct platform_device scif3_device = { - .name = "sh-sci", - .id = 3, - .dev = { - .platform_data = &scif3_platform_data, - }, -}; - -static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xe6c80000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { gic_spi(78), gic_spi(78), - gic_spi(78), gic_spi(78) }, -}; - -static struct platform_device scif4_device = { - .name = "sh-sci", - .id = 4, - .dev = { - .platform_data = &scif4_platform_data, - }, -}; - -static struct plat_sci_port scif5_platform_data = { - .mapbase = 0xe6cb0000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { gic_spi(79), gic_spi(79), - gic_spi(79), gic_spi(79) }, -}; - -static struct platform_device scif5_device = { - .name = "sh-sci", - .id = 5, - .dev = { - .platform_data = &scif5_platform_data, - }, -}; - -static struct plat_sci_port scif6_platform_data = { - .mapbase = 0xe6cc0000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { gic_spi(156), gic_spi(156), - gic_spi(156), gic_spi(156) }, -}; - -static struct platform_device scif6_device = { - .name = "sh-sci", - .id = 6, - .dev = { - .platform_data = &scif6_platform_data, - }, -}; - -static struct plat_sci_port scif7_platform_data = { - .mapbase = 0xe6cd0000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFA, - .irqs = { gic_spi(143), gic_spi(143), - gic_spi(143), gic_spi(143) }, -}; - -static struct platform_device scif7_device = { - .name = "sh-sci", - .id = 7, - .dev = { - .platform_data = &scif7_platform_data, - }, -}; - -static struct plat_sci_port scif8_platform_data = { - .mapbase = 0xe6c30000, - .flags = UPF_BOOT_AUTOCONF, - .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIFB, - .irqs = { gic_spi(80), gic_spi(80), - gic_spi(80), gic_spi(80) }, -}; +/* SCIF */ +#define SH73A0_SCIF(scif_type, index, baseaddr, irq) \ +static struct plat_sci_port scif##index##_platform_data = { \ + .type = scif_type, \ + .flags = UPF_BOOT_AUTOCONF, \ + .scscr = SCSCR_RE | SCSCR_TE, \ +}; \ + \ +static struct resource scif##index##_resources[] = { \ + DEFINE_RES_MEM(baseaddr, 0x100), \ + DEFINE_RES_IRQ(irq), \ +}; \ + \ +static struct platform_device scif##index##_device = { \ + .name = "sh-sci", \ + .id = index, \ + .resource = scif##index##_resources, \ + .num_resources = ARRAY_SIZE(scif##index##_resources), \ + .dev = { \ + .platform_data = &scif##index##_platform_data, \ + }, \ +} -static struct platform_device scif8_device = { - .name = "sh-sci", - .id = 8, - .dev = { - .platform_data = &scif8_platform_data, - }, -}; +SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72)); +SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73)); +SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74)); +SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75)); +SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78)); +SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79)); +SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156)); +SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143)); +SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80)); static struct sh_timer_config cmt10_platform_data = { .name = "CMT10", @@ -273,7 +144,7 @@ static struct sh_timer_config tmu00_platform_data = { }; static struct resource tmu00_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"), + [0] = DEFINE_RES_MEM(0xfff60008, 0xc), [1] = { .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ .flags = IORESOURCE_IRQ, @@ -298,7 +169,7 @@ static struct sh_timer_config tmu01_platform_data = { }; static struct resource tmu01_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"), + [0] = DEFINE_RES_MEM(0xfff60014, 0xc), [1] = { .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ .flags = IORESOURCE_IRQ, @@ -316,7 +187,7 @@ static struct platform_device tmu01_device = { }; static struct resource i2c0_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"), + [0] = DEFINE_RES_MEM(0xe6820000, 0x426), [1] = { .start = gic_spi(167), .end = gic_spi(170), @@ -325,7 +196,7 @@ static struct resource i2c0_resources[] = { }; static struct resource i2c1_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"), + [0] = DEFINE_RES_MEM(0xe6822000, 0x426), [1] = { .start = gic_spi(51), .end = gic_spi(54), @@ -334,7 +205,7 @@ static struct resource i2c1_resources[] = { }; static struct resource i2c2_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"), + [0] = DEFINE_RES_MEM(0xe6824000, 0x426), [1] = { .start = gic_spi(171), .end = gic_spi(174), @@ -343,7 +214,7 @@ static struct resource i2c2_resources[] = { }; static struct resource i2c3_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"), + [0] = DEFINE_RES_MEM(0xe6826000, 0x426), [1] = { .start = gic_spi(183), .end = gic_spi(186), @@ -352,7 +223,7 @@ static struct resource i2c3_resources[] = { }; static struct resource i2c4_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"), + [0] = DEFINE_RES_MEM(0xe6828000, 0x426), [1] = { .start = gic_spi(187), .end = gic_spi(190), @@ -722,7 +593,7 @@ static struct platform_device pmu_device = { /* an IPMMU module for ICB */ static struct resource ipmmu_resources[] = { - DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"), + DEFINE_RES_MEM(0xfe951000, 0x100), }; static const char * const ipmmu_dev_names[] = { diff --git a/arch/arm/mach-shmobile/sh-gpio.h b/arch/arm/mach-shmobile/sh-gpio.h index e834763..2c41414 100644 --- a/arch/arm/mach-shmobile/sh-gpio.h +++ b/arch/arm/mach-shmobile/sh-gpio.h @@ -26,23 +26,4 @@ static inline void __init gpio_direction_none(void __iomem * addr) __raw_writeb(0x00, addr); } -static inline void __init gpio_request_pullup(void __iomem * addr) -{ - u8 data = __raw_readb(addr); - - data &= 0x0F; - data |= 0xC0; - __raw_writeb(data, addr); -} - -static inline void __init gpio_request_pulldown(void __iomem * addr) -{ - u8 data = __raw_readb(addr); - - data &= 0x0F; - data |= 0xA0; - - __raw_writeb(data, addr); -} - #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c index dce50d9..fa2c33f 100644 --- a/arch/arm/mach-sti/platsmp.c +++ b/arch/arm/mach-sti/platsmp.c @@ -31,8 +31,7 @@ static void write_pen_release(int val) { pen_release = val; smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + sync_cache_w(&pen_release); } static DEFINE_SPINLOCK(boot_lock); diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index bce0d42..b9d6cad 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,7 +1,9 @@ config ARCH_SUNXI bool "Allwinner A1X SOCs" if ARCH_MULTI_V7 + select ARCH_HAS_RESET_CONTROLLER select ARCH_REQUIRE_GPIOLIB select ARM_GIC + select ARM_PSCI select CLKSRC_MMIO select CLKSRC_OF select COMMON_CLK @@ -10,6 +12,7 @@ config ARCH_SUNXI select HAVE_SMP select PINCTRL select PINCTRL_SUNXI + select RESET_CONTROLLER select SPARSE_IRQ select SUN4I_TIMER select SUN5I_HSTIMER diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 93bebfc..d939720 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi.o +obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-sunxi/common.h b/arch/arm/mach-sunxi/common.h new file mode 100644 index 0000000..9e5ac47 --- /dev/null +++ b/arch/arm/mach-sunxi/common.h @@ -0,0 +1,19 @@ +/* + * Core functions for Allwinner SoCs + * + * Copyright (C) 2013 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARCH_SUNXI_COMMON_H_ +#define __ARCH_SUNXI_COMMON_H_ + +void sun6i_secondary_startup(void); +extern struct smp_operations sun6i_smp_ops; + +#endif /* __ARCH_SUNXI_COMMON_H_ */ diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S new file mode 100644 index 0000000..a10d494 --- /dev/null +++ b/arch/arm/mach-sunxi/headsmp.S @@ -0,0 +1,9 @@ +#include <linux/linkage.h> +#include <linux/init.h> + + .section ".text.head", "ax" + +ENTRY(sun6i_secondary_startup) + msr cpsr_fsxc, #0xd3 + b secondary_startup +ENDPROC(sun6i_secondary_startup) diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c new file mode 100644 index 0000000..7b141d8 --- /dev/null +++ b/arch/arm/mach-sunxi/platsmp.c @@ -0,0 +1,124 @@ +/* + * SMP support for Allwinner SoCs + * + * Copyright (C) 2013 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * Based on code + * Copyright (C) 2012-2013 Allwinner Ltd. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/memory.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/smp.h> + +#include "common.h" + +#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64) +#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40) +#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04) +#define CPUCFG_CPU_STATUS_REG(cpu) (((cpu) + 1) * 0x40 + 0x08) +#define CPUCFG_GEN_CTRL_REG 0x184 +#define CPUCFG_PRIVATE0_REG 0x1a4 +#define CPUCFG_PRIVATE1_REG 0x1a8 +#define CPUCFG_DBG_CTL0_REG 0x1e0 +#define CPUCFG_DBG_CTL1_REG 0x1e4 + +#define PRCM_CPU_PWROFF_REG 0x100 +#define PRCM_CPU_PWR_CLAMP_REG(cpu) (((cpu) * 4) + 0x140) + +static void __iomem *cpucfg_membase; +static void __iomem *prcm_membase; + +static DEFINE_SPINLOCK(cpu_lock); + +static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm"); + if (!node) { + pr_err("Missing A31 PRCM node in the device tree\n"); + return; + } + + prcm_membase = of_iomap(node, 0); + if (!prcm_membase) { + pr_err("Couldn't map A31 PRCM registers\n"); + return; + } + + node = of_find_compatible_node(NULL, NULL, + "allwinner,sun6i-a31-cpuconfig"); + if (!node) { + pr_err("Missing A31 CPU config node in the device tree\n"); + return; + } + + cpucfg_membase = of_iomap(node, 0); + if (!cpucfg_membase) + pr_err("Couldn't map A31 CPU config registers\n"); + +} + +static int sun6i_smp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + u32 reg; + int i; + + if (!(prcm_membase && cpucfg_membase)) + return -EFAULT; + + spin_lock(&cpu_lock); + + /* Set CPU boot address */ + writel(virt_to_phys(sun6i_secondary_startup), + cpucfg_membase + CPUCFG_PRIVATE0_REG); + + /* Assert the CPU core in reset */ + writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); + + /* Assert the L1 cache in reset */ + reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG); + writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); + + /* Disable external debug access */ + reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); + writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); + + /* Power up the CPU */ + for (i = 0; i <= 8; i++) + writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu)); + mdelay(10); + + /* Clear CPU power-off gating */ + reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG); + writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); + mdelay(1); + + /* Deassert the CPU core reset */ + writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); + + /* Enable back the external debug accesses */ + reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); + writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); + + spin_unlock(&cpu_lock); + + return 0; +} + +struct smp_operations sun6i_smp_ops __initdata = { + .smp_prepare_cpus = sun6i_smp_prepare_cpus, + .smp_boot_secondary = sun6i_smp_boot_secondary, +}; diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 61d3a38..aeea6ce 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -10,6 +10,8 @@ * warranty of any kind, whether express or implied. */ +#include <linux/clk-provider.h> +#include <linux/clocksource.h> #include <linux/delay.h> #include <linux/kernel.h> #include <linux/init.h> @@ -23,6 +25,8 @@ #include <asm/mach/map.h> #include <asm/system_misc.h> +#include "common.h" + #define SUN4I_WATCHDOG_CTRL_REG 0x00 #define SUN4I_WATCHDOG_CTRL_RESTART BIT(0) #define SUN4I_WATCHDOG_MODE_REG 0x04 @@ -132,10 +136,20 @@ static const char * const sun6i_board_dt_compat[] = { NULL, }; +extern void __init sun6i_reset_init(void); +static void __init sun6i_timer_init(void) +{ + of_clk_init(NULL); + sun6i_reset_init(); + clocksource_of_init(); +} + DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family") .init_machine = sunxi_dt_init, + .init_time = sun6i_timer_init, .dt_compat = sun6i_board_dt_compat, .restart = sun6i_restart, + .smp = smp_ops(sun6i_smp_ops), MACHINE_END static const char * const sun7i_board_dt_compat[] = { diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 09e740f..b1232d8 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -2,6 +2,7 @@ config ARCH_TEGRA bool "NVIDIA Tegra" if ARCH_MULTI_V7 select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB + select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS select ARM_GIC select CLKSRC_MMIO select CLKSRC_OF @@ -14,6 +15,8 @@ config ARCH_TEGRA select MIGHT_HAVE_CACHE_L2X0 select MIGHT_HAVE_PCI select PINCTRL + select ARCH_HAS_RESET_CONTROLLER + select RESET_CONTROLLER select SOC_BUS select SPARSE_IRQ select USB_ARCH_HAS_EHCI if USB_SUPPORT @@ -63,6 +66,7 @@ config ARCH_TEGRA_124_SOC bool "Enable support for Tegra124 family" select ARM_L1_CACHE_SHIFT_6 select HAVE_ARM_ARCH_TIMER + select PINCTRL_TEGRA124 help Support for NVIDIA Tegra T124 processor family, based on the ARM CortexA15MP CPU diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index 3a9c1f1..c9ac23b 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <linux/export.h> #include <linux/random.h> +#include <linux/clk.h> #include <linux/tegra-soc.h> #include "fuse.h" @@ -54,6 +55,7 @@ int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */ int tegra_soc_speedo_id; enum tegra_revision tegra_revision; +static struct clk *fuse_clk; static int tegra_fuse_spare_bit; static void (*tegra_init_speedo_data)(void); @@ -77,6 +79,22 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { [TEGRA_REVISION_A04] = "A04", }; +static void tegra_fuse_enable_clk(void) +{ + if (IS_ERR(fuse_clk)) + fuse_clk = clk_get_sys(NULL, "fuse"); + if (IS_ERR(fuse_clk)) + return; + clk_prepare_enable(fuse_clk); +} + +static void tegra_fuse_disable_clk(void) +{ + if (IS_ERR(fuse_clk)) + return; + clk_disable_unprepare(fuse_clk); +} + u32 tegra_fuse_readl(unsigned long offset) { return tegra_apb_readl(TEGRA_FUSE_BASE + offset); @@ -84,7 +102,15 @@ u32 tegra_fuse_readl(unsigned long offset) bool tegra_spare_fuse(int bit) { - return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4); + bool ret; + + tegra_fuse_enable_clk(); + + ret = tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4); + + tegra_fuse_disable_clk(); + + return ret; } static enum tegra_revision tegra_get_revision(u32 id) @@ -113,10 +139,14 @@ static void tegra_get_process_id(void) { u32 reg; + tegra_fuse_enable_clk(); + reg = tegra_fuse_readl(tegra_fuse_spare_bit); tegra_cpu_process_id = (reg >> 6) & 3; reg = tegra_fuse_readl(tegra_fuse_spare_bit); tegra_core_process_id = (reg >> 12) & 3; + + tegra_fuse_disable_clk(); } u32 tegra_read_chipid(void) @@ -159,6 +189,15 @@ void __init tegra_init_fuse(void) reg |= 1 << 28; writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); + /* + * Enable FUSE clock. This needs to be hardcoded because the clock + * subsystem is not active during early boot. + */ + reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14)); + reg |= 1 << 7; + writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14)); + fuse_clk = ERR_PTR(-EINVAL); + reg = tegra_fuse_readl(FUSE_SKU_INFO); randomness[0] = reg; tegra_sku_id = reg & 0xFF; diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h index 26b1c2a..ee79808 100644 --- a/arch/arm/mach-tegra/iomap.h +++ b/arch/arm/mach-tegra/iomap.h @@ -19,6 +19,7 @@ #ifndef __MACH_TEGRA_IOMAP_H #define __MACH_TEGRA_IOMAP_H +#include <asm/pgtable.h> #include <asm/sizes.h> #define TEGRA_IRAM_BASE 0x40000000 @@ -115,27 +116,26 @@ * two 256MB io windows (that actually only use about 64KB * at the start of each). * - * We will just map the first 1MB of each window (to minimize + * We will just map the first MMU section of each window (to minimize * pt entries needed) and provide a macro to transform physical * io addresses to an appropriate void __iomem *. - * */ #define IO_IRAM_PHYS 0x40000000 #define IO_IRAM_VIRT IOMEM(0xFE400000) #define IO_IRAM_SIZE SZ_256K -#define IO_CPU_PHYS 0x50040000 -#define IO_CPU_VIRT IOMEM(0xFE000000) +#define IO_CPU_PHYS 0x50040000 +#define IO_CPU_VIRT IOMEM(0xFE440000) #define IO_CPU_SIZE SZ_16K #define IO_PPSB_PHYS 0x60000000 #define IO_PPSB_VIRT IOMEM(0xFE200000) -#define IO_PPSB_SIZE SZ_1M +#define IO_PPSB_SIZE SECTION_SIZE #define IO_APB_PHYS 0x70000000 -#define IO_APB_VIRT IOMEM(0xFE300000) -#define IO_APB_SIZE SZ_1M +#define IO_APB_VIRT IOMEM(0xFE000000) +#define IO_APB_SIZE SECTION_SIZE #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) #define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 85d28e7..3d0c537 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -25,6 +25,7 @@ #include <linux/export.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/reset.h> #include <linux/seq_file.h> #include <linux/spinlock.h> #include <linux/clk/tegra.h> @@ -33,6 +34,10 @@ #include "fuse.h" #include "iomap.h" +#define DPD_SAMPLE 0x020 +#define DPD_SAMPLE_ENABLE (1 << 0) +#define DPD_SAMPLE_DISABLE (0 << 0) + #define PWRGATE_TOGGLE 0x30 #define PWRGATE_TOGGLE_START (1 << 8) @@ -40,6 +45,19 @@ #define PWRGATE_STATUS 0x38 +#define IO_DPD_REQ 0x1b8 +#define IO_DPD_REQ_CODE_IDLE (0 << 30) +#define IO_DPD_REQ_CODE_OFF (1 << 30) +#define IO_DPD_REQ_CODE_ON (2 << 30) +#define IO_DPD_REQ_CODE_MASK (3 << 30) + +#define IO_DPD_STATUS 0x1bc +#define IO_DPD2_REQ 0x1c0 +#define IO_DPD2_STATUS 0x1c4 +#define SEL_DPD_TIM 0x1c8 + +#define GPU_RG_CNTRL 0x2d4 + static int tegra_num_powerdomains; static int tegra_num_cpu_domains; static const u8 *tegra_cpu_domains; @@ -58,6 +76,13 @@ static const u8 tegra114_cpu_domains[] = { TEGRA_POWERGATE_CPU3, }; +static const u8 tegra124_cpu_domains[] = { + TEGRA_POWERGATE_CPU0, + TEGRA_POWERGATE_CPU1, + TEGRA_POWERGATE_CPU2, + TEGRA_POWERGATE_CPU3, +}; + static DEFINE_SPINLOCK(tegra_powergate_lock); static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); @@ -108,6 +133,7 @@ int tegra_powergate_power_off(int id) return tegra_powergate_set(id, false); } +EXPORT_SYMBOL(tegra_powergate_power_off); int tegra_powergate_is_powered(int id) { @@ -128,12 +154,23 @@ int tegra_powergate_remove_clamping(int id) return -EINVAL; /* + * The Tegra124 GPU has a separate register (with different semantics) + * to remove clamps. + */ + if (tegra_chip_id == TEGRA124) { + if (id == TEGRA_POWERGATE_3D) { + pmc_write(0, GPU_RG_CNTRL); + return 0; + } + } + + /* * Tegra 2 has a bug where PCIE and VDE clamping masks are * swapped relatively to the partition ids */ - if (id == TEGRA_POWERGATE_VDEC) + if (id == TEGRA_POWERGATE_VDEC) mask = (1 << TEGRA_POWERGATE_PCIE); - else if (id == TEGRA_POWERGATE_PCIE) + else if (id == TEGRA_POWERGATE_PCIE) mask = (1 << TEGRA_POWERGATE_VDEC); else mask = (1 << id); @@ -142,13 +179,15 @@ int tegra_powergate_remove_clamping(int id) return 0; } +EXPORT_SYMBOL(tegra_powergate_remove_clamping); /* Must be called with clk disabled, and returns with clk enabled */ -int tegra_powergate_sequence_power_up(int id, struct clk *clk) +int tegra_powergate_sequence_power_up(int id, struct clk *clk, + struct reset_control *rst) { int ret; - tegra_periph_reset_assert(clk); + reset_control_assert(rst); ret = tegra_powergate_power_on(id); if (ret) @@ -165,7 +204,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk) goto err_clamp; udelay(10); - tegra_periph_reset_deassert(clk); + reset_control_deassert(rst); return 0; @@ -202,6 +241,11 @@ int __init tegra_powergate_init(void) tegra_num_cpu_domains = 4; tegra_cpu_domains = tegra114_cpu_domains; break; + case TEGRA124: + tegra_num_powerdomains = 25; + tegra_num_cpu_domains = 4; + tegra_cpu_domains = tegra124_cpu_domains; + break; default: /* Unknown Tegra variant. Disable powergating */ tegra_num_powerdomains = 0; @@ -243,12 +287,36 @@ static const char * const powergate_name_t30[] = { }; static const char * const powergate_name_t114[] = { - [TEGRA_POWERGATE_CPU] = "cpu0", + [TEGRA_POWERGATE_CPU] = "crail", + [TEGRA_POWERGATE_3D] = "3d", + [TEGRA_POWERGATE_VENC] = "venc", + [TEGRA_POWERGATE_VDEC] = "vdec", + [TEGRA_POWERGATE_MPE] = "mpe", + [TEGRA_POWERGATE_HEG] = "heg", + [TEGRA_POWERGATE_CPU1] = "cpu1", + [TEGRA_POWERGATE_CPU2] = "cpu2", + [TEGRA_POWERGATE_CPU3] = "cpu3", + [TEGRA_POWERGATE_CELP] = "celp", + [TEGRA_POWERGATE_CPU0] = "cpu0", + [TEGRA_POWERGATE_C0NC] = "c0nc", + [TEGRA_POWERGATE_C1NC] = "c1nc", + [TEGRA_POWERGATE_DIS] = "dis", + [TEGRA_POWERGATE_DISB] = "disb", + [TEGRA_POWERGATE_XUSBA] = "xusba", + [TEGRA_POWERGATE_XUSBB] = "xusbb", + [TEGRA_POWERGATE_XUSBC] = "xusbc", +}; + +static const char * const powergate_name_t124[] = { + [TEGRA_POWERGATE_CPU] = "crail", [TEGRA_POWERGATE_3D] = "3d", [TEGRA_POWERGATE_VENC] = "venc", + [TEGRA_POWERGATE_PCIE] = "pcie", [TEGRA_POWERGATE_VDEC] = "vdec", + [TEGRA_POWERGATE_L2] = "l2", [TEGRA_POWERGATE_MPE] = "mpe", [TEGRA_POWERGATE_HEG] = "heg", + [TEGRA_POWERGATE_SATA] = "sata", [TEGRA_POWERGATE_CPU1] = "cpu1", [TEGRA_POWERGATE_CPU2] = "cpu2", [TEGRA_POWERGATE_CPU3] = "cpu3", @@ -256,11 +324,14 @@ static const char * const powergate_name_t114[] = { [TEGRA_POWERGATE_CPU0] = "cpu0", [TEGRA_POWERGATE_C0NC] = "c0nc", [TEGRA_POWERGATE_C1NC] = "c1nc", + [TEGRA_POWERGATE_SOR] = "sor", [TEGRA_POWERGATE_DIS] = "dis", [TEGRA_POWERGATE_DISB] = "disb", [TEGRA_POWERGATE_XUSBA] = "xusba", [TEGRA_POWERGATE_XUSBB] = "xusbb", [TEGRA_POWERGATE_XUSBC] = "xusbc", + [TEGRA_POWERGATE_VIC] = "vic", + [TEGRA_POWERGATE_IRAM] = "iram", }; static int powergate_show(struct seq_file *s, void *data) @@ -307,6 +378,9 @@ int __init tegra_powergate_debugfs_init(void) case TEGRA114: powergate_name = powergate_name_t114; break; + case TEGRA124: + powergate_name = powergate_name_t124; + break; } if (powergate_name) { @@ -320,3 +394,120 @@ int __init tegra_powergate_debugfs_init(void) } #endif + +static int tegra_io_rail_prepare(int id, unsigned long *request, + unsigned long *status, unsigned int *bit) +{ + unsigned long rate, value; + struct clk *clk; + + *bit = id % 32; + + /* + * There are two sets of 30 bits to select IO rails, but bits 30 and + * 31 are control bits rather than IO rail selection bits. + */ + if (id > 63 || *bit == 30 || *bit == 31) + return -EINVAL; + + if (id < 32) { + *status = IO_DPD_STATUS; + *request = IO_DPD_REQ; + } else { + *status = IO_DPD2_STATUS; + *request = IO_DPD2_REQ; + } + + clk = clk_get_sys(NULL, "pclk"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + rate = clk_get_rate(clk); + clk_put(clk); + + pmc_write(DPD_SAMPLE_ENABLE, DPD_SAMPLE); + + /* must be at least 200 ns, in APB (PCLK) clock cycles */ + value = DIV_ROUND_UP(1000000000, rate); + value = DIV_ROUND_UP(200, value); + pmc_write(value, SEL_DPD_TIM); + + return 0; +} + +static int tegra_io_rail_poll(unsigned long offset, unsigned long mask, + unsigned long val, unsigned long timeout) +{ + unsigned long value; + + timeout = jiffies + msecs_to_jiffies(timeout); + + while (time_after(timeout, jiffies)) { + value = pmc_read(offset); + if ((value & mask) == val) + return 0; + + usleep_range(250, 1000); + } + + return -ETIMEDOUT; +} + +static void tegra_io_rail_unprepare(void) +{ + pmc_write(DPD_SAMPLE_DISABLE, DPD_SAMPLE); +} + +int tegra_io_rail_power_on(int id) +{ + unsigned long request, status, value; + unsigned int bit, mask; + int err; + + err = tegra_io_rail_prepare(id, &request, &status, &bit); + if (err < 0) + return err; + + mask = 1 << bit; + + value = pmc_read(request); + value |= mask; + value &= ~IO_DPD_REQ_CODE_MASK; + value |= IO_DPD_REQ_CODE_OFF; + pmc_write(value, request); + + err = tegra_io_rail_poll(status, mask, 0, 250); + if (err < 0) + return err; + + tegra_io_rail_unprepare(); + + return 0; +} + +int tegra_io_rail_power_off(int id) +{ + unsigned long request, status, value; + unsigned int bit, mask; + int err; + + err = tegra_io_rail_prepare(id, &request, &status, &bit); + if (err < 0) + return err; + + mask = 1 << bit; + + value = pmc_read(request); + value |= mask; + value &= ~IO_DPD_REQ_CODE_MASK; + value |= IO_DPD_REQ_CODE_ON; + pmc_write(value, request); + + err = tegra_io_rail_poll(status, mask, mask, 250); + if (err < 0) + return err; + + tegra_io_rail_unprepare(); + + return 0; +} diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 568f5bb..146fe8e 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -21,6 +21,7 @@ #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h> +#include <asm/firmware.h> #include "iomap.h" #include "irammap.h" @@ -33,26 +34,18 @@ static bool is_enabled; -static void __init tegra_cpu_reset_handler_enable(void) +static void __init tegra_cpu_reset_handler_set(const u32 reset_address) { - void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); void __iomem *evp_cpu_reset = IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); u32 reg; - BUG_ON(is_enabled); - BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); - - memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, - tegra_cpu_reset_handler_size); - /* * NOTE: This must be the one and only write to the EVP CPU reset * vector in the entire system. */ - writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset, - evp_cpu_reset); + writel(reset_address, evp_cpu_reset); wmb(); reg = readl(evp_cpu_reset); @@ -66,8 +59,33 @@ static void __init tegra_cpu_reset_handler_enable(void) writel(reg, sb_ctrl); wmb(); } +} + +static void __init tegra_cpu_reset_handler_enable(void) +{ + void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); + const u32 reset_address = TEGRA_IRAM_RESET_BASE + + tegra_cpu_reset_handler_offset; + int err; + + BUG_ON(is_enabled); + BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); - is_enabled = true; + memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, + tegra_cpu_reset_handler_size); + + err = call_firmware_op(set_cpu_boot_addr, 0, reset_address); + switch (err) { + case -ENOSYS: + tegra_cpu_reset_handler_set(reset_address); + /* pass-through */ + case 0: + is_enabled = true; + break; + default: + pr_crit("Cannot set CPU reset handler: %d\n", err); + BUG(); + } } void __init tegra_cpu_reset_handler_init(void) diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 7336817..303a285 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -40,6 +40,7 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/setup.h> +#include <asm/trusted_foundations.h> #include "apbio.h" #include "board.h" @@ -60,15 +61,13 @@ * kernel is loaded. The data is declared here rather than debug-macro.S so * that multiple inclusions of debug-macro.S point at the same data. */ -u32 tegra_uart_config[4] = { +u32 tegra_uart_config[3] = { /* Debug UART initialization required */ 1, /* Debug UART physical address */ 0, /* Debug UART virtual address */ 0, - /* Scratch space for debug macro */ - 0, }; static void __init tegra_init_cache(void) @@ -90,6 +89,7 @@ static void __init tegra_init_cache(void) static void __init tegra_init_early(void) { + of_register_trusted_foundations(); tegra_apb_io_init(); tegra_init_fuse(); tegra_cpu_reset_handler_init(); diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c index bf40cd4..0493a84 100644 --- a/arch/arm/mach-u300/regulator.c +++ b/arch/arm/mach-u300/regulator.c @@ -69,9 +69,9 @@ static int __init __u300_init_boardpower(struct platform_device *pdev) return -ENODEV; } regmap = syscon_node_to_regmap(syscon_np); - if (!regmap) { + if (IS_ERR(regmap)) { pr_crit("U300: could not locate syscon regmap\n"); - return -ENODEV; + return PTR_ERR(regmap); } main_power_15 = regulator_get(&pdev->dev, "vana15"); diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index 9a5f9fb..fe08fd3 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c @@ -184,11 +184,13 @@ #define U300_TIMER_APP_CRC (0x100) #define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001) -#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ) -#define US_PER_TICK ((1000000 + (HZ/2)) / HZ) - static void __iomem *u300_timer_base; +struct u300_clockevent_data { + struct clock_event_device cevd; + unsigned ticks_per_jiffy; +}; + /* * The u300_set_mode() function is always called first, if we * have oneshot timer active, the oneshot scheduling function @@ -197,6 +199,9 @@ static void __iomem *u300_timer_base; static void u300_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { + struct u300_clockevent_data *cevdata = + container_of(evt, struct u300_clockevent_data, cevd); + switch (mode) { case CLOCK_EVT_MODE_PERIODIC: /* Disable interrupts on GPT1 */ @@ -209,7 +214,7 @@ static void u300_set_mode(enum clock_event_mode mode, * Set the periodic mode to a certain number of ticks per * jiffy. */ - writel(TICKS_PER_JIFFY, + writel(cevdata->ticks_per_jiffy, u300_timer_base + U300_TIMER_APP_GPT1TC); /* * Set continuous mode, so the timer keeps triggering @@ -305,20 +310,23 @@ static int u300_set_next_event(unsigned long cycles, return 0; } - -/* Use general purpose timer 1 as clock event */ -static struct clock_event_device clockevent_u300_1mhz = { - .name = "GPT1", - .rating = 300, /* Reasonably fast and accurate clock event */ - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = u300_set_next_event, - .set_mode = u300_set_mode, +static struct u300_clockevent_data u300_clockevent_data = { + /* Use general purpose timer 1 as clock event */ + .cevd = { + .name = "GPT1", + /* Reasonably fast and accurate clock event */ + .rating = 300, + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = u300_set_next_event, + .set_mode = u300_set_mode, + }, }; /* Clock event timer interrupt handler */ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id) { - struct clock_event_device *evt = &clockevent_u300_1mhz; + struct clock_event_device *evt = &u300_clockevent_data.cevd; /* ACK/Clear timer IRQ for the APP GPT1 Timer */ writel(U300_TIMER_APP_GPT1IA_IRQ_ACK, @@ -341,7 +349,7 @@ static struct irqaction u300_timer_irq = { * stamp. (Inspired by OMAP implementation.) */ -static u32 notrace u300_read_sched_clock(void) +static u64 notrace u300_read_sched_clock(void) { return readl(u300_timer_base + U300_TIMER_APP_GPT2CC); } @@ -379,7 +387,9 @@ static void __init u300_timer_init_of(struct device_node *np) clk_prepare_enable(clk); rate = clk_get_rate(clk); - setup_sched_clock(u300_read_sched_clock, 32, rate); + u300_clockevent_data.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ); + + sched_clock_register(u300_read_sched_clock, 32, rate); u300_delay_timer.read_current_timer = &u300_read_current_timer; u300_delay_timer.freq = rate; @@ -428,7 +438,7 @@ static void __init u300_timer_init_of(struct device_node *np) pr_err("timer: failed to initialize U300 clock source\n"); /* Configure and register the clockevent */ - clockevents_config_and_register(&clockevent_u300_1mhz, rate, + clockevents_config_and_register(&u300_clockevent_data.cevd, rate, 1, 0xffffffff); /* diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 616b96e..d05ba75 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -2,10 +2,10 @@ # Makefile for the linux kernel, U8500 machine. # -obj-y := cpu.o devices.o id.o timer.o pm.o +obj-y := cpu.o id.o timer.o pm.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o -obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o -obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ +obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o +obj-$(CONFIG_MACH_MOP500) += board-mop500-sdi.o \ board-mop500-regulators.o \ board-mop500-pins.o \ board-mop500-audio.o diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c index 43d6cb8..9309ad4 100644 --- a/arch/arm/mach-ux500/board-mop500-audio.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c @@ -7,16 +7,13 @@ #include <linux/platform_device.h> #include <linux/init.h> #include <linux/gpio.h> -#include <linux/platform_data/pinctrl-nomadik.h> #include <linux/platform_data/dma-ste-dma40.h> -#include "devices.h" #include "irqs.h" #include <linux/platform_data/asoc-ux500-msp.h> #include "ste-dma40-db8500.h" #include "board-mop500.h" -#include "devices-db8500.h" static struct stedma40_chan_cfg msp0_dma_rx = { .high_priority = true, diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 0efb156..f63619b 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -10,94 +10,18 @@ #include <linux/string.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf-generic.h> -#include <linux/platform_data/pinctrl-nomadik.h> #include <asm/mach-types.h> #include "board-mop500.h" -enum custom_pin_cfg_t { - PINS_FOR_DEFAULT, - PINS_FOR_U9500, -}; - -static enum custom_pin_cfg_t pinsfor; - /* These simply sets bias for pins */ #define BIAS(a,b) static unsigned long a[] = { b } -BIAS(pd, PIN_PULL_DOWN); -BIAS(in_nopull, PIN_INPUT_NOPULL); -BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE); -BIAS(in_pu, PIN_INPUT_PULLUP); -BIAS(in_pd, PIN_INPUT_PULLDOWN); -BIAS(out_hi, PIN_OUTPUT_HIGH); -BIAS(out_lo, PIN_OUTPUT_LOW); -BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE); - BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0)); BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1)); BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0)); -/* These also force them into GPIO mode */ -BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED); -BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED); -BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL); -BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL); -BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED); -BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED); -/* Sleep modes */ -BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); -BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); -BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH| - PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP| - PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); -BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW| - PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE| - PIN_SLPM_PDIS_ENABLED); -BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE| - PIN_SLPM_PDIS_DISABLED); -BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE| - PIN_SLPM_PDIS_DISABLED); - -/* We use these to define hog settings that are always done on boot */ -#define DB8500_MUX_HOG(group,func) \ - PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func) -#define DB8500_PIN_HOG(pin,conf) \ - PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf) - -/* These are default states associated with device and changed runtime */ -#define DB8500_MUX(group,func,dev) \ - PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func) -#define DB8500_PIN(pin,conf,dev) \ - PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf) -#define DB8500_PIN_IDLE(pin, conf, dev) \ - PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500", \ - pin, conf) -#define DB8500_PIN_SLEEP(pin, conf, dev) \ - PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \ - pin, conf) -#define DB8500_MUX_STATE(group, func, dev, state) \ - PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func) -#define DB8500_PIN_STATE(pin, conf, dev, state) \ - PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf) - #define AB8500_MUX_HOG(group, func) \ PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func) #define AB8500_PIN_HOG(pin, conf) \ @@ -344,725 +268,8 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = { AB8505_PIN_HOG("GPIO53_D15", in_pd), }; -/* Pin control settings */ -static struct pinctrl_map __initdata mop500_family_pinmap[] = { - /* - * uMSP0, mux in 4 pins, regular placement of RX/TX - * explicitly set the pins to no pull - */ - DB8500_MUX_HOG("msp0txrx_a_1", "msp0"), - DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"), - DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */ - DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */ - DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */ - DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */ - /* MSP2 for HDMI, pull down TXD, TCK, TFS */ - DB8500_MUX_HOG("msp2_a_1", "msp2"), - DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */ - DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */ - DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */ - DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */ - /* - * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to - * pull-up - * TODO: is this really correct? Snowball doesn't have a LCD. - */ - DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"), - DB8500_PIN_HOG("GPIO68_E1", in_pu), - DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu), - /* - * STMPE1601/tc35893 keypad IRQ GPIO 218 - * TODO: set for snowball and HREF really?? - */ - DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu), - /* - * UART0, we do not mux in u0 here. - * uart-0 pins gpio configuration should be kept intact to prevent - * a glitch in tx line when the tty dev is opened. Later these pins - * are configured by uart driver - */ - DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */ - DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */ - DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */ - DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */ - /* - * Mux in UART2 on altfunction C and set pull-ups. - * TODO: is this used on U8500 variants and Snowball really? - * The setting on GPIO31 conflicts with magnetometer use on hrefv60 - */ - /* default state for UART2 */ - DB8500_MUX("u2rxtx_c_1", "u2", "uart2"), - DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */ - DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */ - /* Sleep state for UART2 */ - DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"), - DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"), - /* - * The following pin sets were known as "runtime pins" before being - * converted to the pinctrl model. Here we model them as "default" - * states. - */ - /* Mux in UART0 after initialization */ - DB8500_MUX("u0_a_1", "u0", "uart0"), - DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */ - DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */ - DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */ - DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */ - /* Sleep state for UART0 */ - DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"), - DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"), - DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"), - DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"), - /* Mux in UART1 after initialization */ - DB8500_MUX("u1rxtx_a_1", "u1", "uart1"), - DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */ - DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */ - /* Sleep state for UART1 */ - DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"), - DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"), - /* MSP1 for ALSA codec */ - DB8500_MUX_HOG("msp1txrx_a_1", "msp1"), - DB8500_MUX_HOG("msp1_a_1", "msp1"), - DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup), - DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup), - DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup), - DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup), - /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */ - DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"), - DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"), - /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */ - DB8500_MUX("lcdvsi1_a_1", "lcd", "0-0070"), - DB8500_PIN("GPIO69_E2", in_pu, "0-0070"), - /* LCD VSI1 sleep state */ - DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"), - /* Mux in i2c0 block, default state */ - DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"), - /* i2c0 sleep state */ - DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */ - DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */ - /* Mux in i2c1 block, default state */ - DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"), - /* i2c1 sleep state */ - DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */ - DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */ - /* Mux in i2c2 block, default state */ - DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"), - /* i2c2 sleep state */ - DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */ - DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */ - /* Mux in i2c3 block, default state */ - DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"), - /* i2c3 sleep state */ - DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */ - DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */ - /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */ - DB8500_MUX("mc0_a_1", "mc0", "sdi0"), - DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */ - DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */ - DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */ - DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */ - DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */ - DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */ - DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */ - DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */ - DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */ - DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */ - /* SDI0 sleep state */ - DB8500_PIN_SLEEP("GPIO18_AC2", slpm_out_hi_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO19_AC1", slpm_out_hi_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO20_AB4", slpm_out_hi_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO22_AA3", slpm_in_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO23_AA4", slpm_out_lo_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO24_AB2", slpm_in_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO25_Y4", slpm_in_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO26_Y2", slpm_in_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO27_AA2", slpm_in_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO28_AA1", slpm_in_wkup_pdis, "sdi0"), - - /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */ - DB8500_MUX("mc1_a_1", "mc1", "sdi1"), - DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */ - DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */ - DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */ - DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */ - DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */ - DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */ - DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */ - /* SDI1 sleep state */ - DB8500_PIN_SLEEP("GPIO208_AH16", slpm_out_lo_wkup_pdis, "sdi1"), /* CLK */ - DB8500_PIN_SLEEP("GPIO209_AG15", slpm_in_wkup_pdis, "sdi1"), /* FBCLK */ - DB8500_PIN_SLEEP("GPIO210_AJ15", slpm_in_wkup_pdis, "sdi1"), /* CMD */ - DB8500_PIN_SLEEP("GPIO211_AG14", slpm_in_wkup_pdis, "sdi1"), /* DAT0 */ - DB8500_PIN_SLEEP("GPIO212_AF13", slpm_in_wkup_pdis, "sdi1"), /* DAT1 */ - DB8500_PIN_SLEEP("GPIO213_AG13", slpm_in_wkup_pdis, "sdi1"), /* DAT2 */ - DB8500_PIN_SLEEP("GPIO214_AH15", slpm_in_wkup_pdis, "sdi1"), /* DAT3 */ - - /* Mux in SDI2 (here called MC2) used for for PoP eMMC */ - DB8500_MUX("mc2_a_1", "mc2", "sdi2"), - DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */ - DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */ - DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */ - DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */ - DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */ - DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */ - DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */ - DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */ - DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */ - DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */ - DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */ - /* SDI2 sleep state */ - DB8500_PIN_SLEEP("GPIO128_A5", out_lo_wkup_pdis, "sdi2"), /* CLK */ - DB8500_PIN_SLEEP("GPIO129_B4", in_wkup_pdis_en, "sdi2"), /* CMD */ - DB8500_PIN_SLEEP("GPIO130_C8", in_wkup_pdis_en, "sdi2"), /* FBCLK */ - DB8500_PIN_SLEEP("GPIO131_A12", in_wkup_pdis, "sdi2"), /* DAT0 */ - DB8500_PIN_SLEEP("GPIO132_C10", in_wkup_pdis, "sdi2"), /* DAT1 */ - DB8500_PIN_SLEEP("GPIO133_B10", in_wkup_pdis, "sdi2"), /* DAT2 */ - DB8500_PIN_SLEEP("GPIO134_B9", in_wkup_pdis, "sdi2"), /* DAT3 */ - DB8500_PIN_SLEEP("GPIO135_A9", in_wkup_pdis, "sdi2"), /* DAT4 */ - DB8500_PIN_SLEEP("GPIO136_C7", in_wkup_pdis, "sdi2"), /* DAT5 */ - DB8500_PIN_SLEEP("GPIO137_A7", in_wkup_pdis, "sdi2"), /* DAT6 */ - DB8500_PIN_SLEEP("GPIO138_C5", in_wkup_pdis, "sdi2"), /* DAT7 */ - - /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */ - DB8500_MUX("mc4_a_1", "mc4", "sdi4"), - DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */ - DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */ - DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */ - DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */ - DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */ - DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */ - DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */ - DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */ - DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */ - DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */ - DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */ - /*SDI4 sleep state */ - DB8500_PIN_SLEEP("GPIO197_AH24", slpm_in_wkup_pdis, "sdi4"), /* DAT3 */ - DB8500_PIN_SLEEP("GPIO198_AG25", slpm_in_wkup_pdis, "sdi4"), /* DAT2 */ - DB8500_PIN_SLEEP("GPIO199_AH23", slpm_in_wkup_pdis, "sdi4"), /* DAT1 */ - DB8500_PIN_SLEEP("GPIO200_AH26", slpm_in_wkup_pdis, "sdi4"), /* DAT0 */ - DB8500_PIN_SLEEP("GPIO201_AF24", slpm_in_wkup_pdis, "sdi4"), /* CMD */ - DB8500_PIN_SLEEP("GPIO202_AF25", slpm_in_wkup_pdis, "sdi4"), /* FBCLK */ - DB8500_PIN_SLEEP("GPIO203_AE23", slpm_out_lo_wkup_pdis, "sdi4"), /* CLK */ - DB8500_PIN_SLEEP("GPIO204_AF23", slpm_in_wkup_pdis, "sdi4"), /* DAT7 */ - DB8500_PIN_SLEEP("GPIO205_AG23", slpm_in_wkup_pdis, "sdi4"), /* DAT6 */ - DB8500_PIN_SLEEP("GPIO206_AG24", slpm_in_wkup_pdis, "sdi4"), /* DAT5 */ - DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */ - - /* Mux in USB pins, drive STP high */ - /* USB default state */ - DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"), - DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */ - /* USB sleep state */ - DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */ - DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */ - DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */ - DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */ - DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */ - DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */ - DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */ - DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */ - DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */ - DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */ - DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */ - DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */ - - /* Mux in SPI2 pins on the "other C1" altfunction */ - DB8500_MUX("spi2_oc1_2", "spi2", "spi2"), - DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */ - DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */ - DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */ - DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */ - /* SPI2 idle state */ - DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */ - DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */ - DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */ - /* SPI2 sleep state */ - DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */ - DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */ - DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */ - DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */ - - /* ske default state */ - DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"), - DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */ - DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */ - DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */ - DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */ - DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */ - DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */ - DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */ - DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */ - DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */ - DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */ - DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */ - DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */ - DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */ - DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */ - DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */ - DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */ - /* ske sleep state */ - DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */ - DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */ - DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */ - DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */ - DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */ - DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */ - DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */ - DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */ - DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */ - DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */ - DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */ - DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */ - DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */ - DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */ - DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */ - DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */ - - /* STM APE pins states */ - DB8500_MUX_STATE("stmape_c_1", "stmape", - "stm", "ape_mipi34"), - DB8500_PIN_STATE("GPIO70_G5", in_nopull, - "stm", "ape_mipi34"), /* clk */ - DB8500_PIN_STATE("GPIO71_G4", in_nopull, - "stm", "ape_mipi34"), /* dat3 */ - DB8500_PIN_STATE("GPIO72_H4", in_nopull, - "stm", "ape_mipi34"), /* dat2 */ - DB8500_PIN_STATE("GPIO73_H3", in_nopull, - "stm", "ape_mipi34"), /* dat1 */ - DB8500_PIN_STATE("GPIO74_J3", in_nopull, - "stm", "ape_mipi34"), /* dat0 */ - - DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis, - "stm", "ape_mipi34_sleep"), /* clk */ - DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis, - "stm", "ape_mipi34_sleep"), /* dat3 */ - DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis, - "stm", "ape_mipi34_sleep"), /* dat2 */ - DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis, - "stm", "ape_mipi34_sleep"), /* dat1 */ - DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis, - "stm", "ape_mipi34_sleep"), /* dat0 */ - - DB8500_MUX_STATE("stmape_oc1_1", "stmape", - "stm", "ape_microsd"), - DB8500_PIN_STATE("GPIO23_AA4", in_nopull, - "stm", "ape_microsd"), /* clk */ - DB8500_PIN_STATE("GPIO25_Y4", in_nopull, - "stm", "ape_microsd"), /* dat0 */ - DB8500_PIN_STATE("GPIO26_Y2", in_nopull, - "stm", "ape_microsd"), /* dat1 */ - DB8500_PIN_STATE("GPIO27_AA2", in_nopull, - "stm", "ape_microsd"), /* dat2 */ - DB8500_PIN_STATE("GPIO28_AA1", in_nopull, - "stm", "ape_microsd"), /* dat3 */ - - DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis, - "stm", "ape_microsd_sleep"), /* clk */ - DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis, - "stm", "ape_microsd_sleep"), /* dat0 */ - DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis, - "stm", "ape_microsd_sleep"), /* dat1 */ - DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis, - "stm", "ape_microsd_sleep"), /* dat2 */ - DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis, - "stm", "ape_microsd_sleep"), /* dat3 */ - - /* STM Modem pins states */ - DB8500_MUX_STATE("stmmod_oc3_2", "stmmod", - "stm", "mod_mipi34"), - DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod", - "stm", "mod_mipi34"), - DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod", - "stm", "mod_mipi34"), - DB8500_PIN_STATE("GPIO70_G5", in_nopull, - "stm", "mod_mipi34"), /* clk */ - DB8500_PIN_STATE("GPIO71_G4", in_nopull, - "stm", "mod_mipi34"), /* dat3 */ - DB8500_PIN_STATE("GPIO72_H4", in_nopull, - "stm", "mod_mipi34"), /* dat2 */ - DB8500_PIN_STATE("GPIO73_H3", in_nopull, - "stm", "mod_mipi34"), /* dat1 */ - DB8500_PIN_STATE("GPIO74_J3", in_nopull, - "stm", "mod_mipi34"), /* dat0 */ - DB8500_PIN_STATE("GPIO75_H2", in_pu, - "stm", "mod_mipi34"), /* uartmod rx */ - DB8500_PIN_STATE("GPIO76_J2", out_lo, - "stm", "mod_mipi34"), /* uartmod tx */ - - DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis, - "stm", "mod_mipi34_sleep"), /* clk */ - DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis, - "stm", "mod_mipi34_sleep"), /* dat3 */ - DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis, - "stm", "mod_mipi34_sleep"), /* dat2 */ - DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis, - "stm", "mod_mipi34_sleep"), /* dat1 */ - DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis, - "stm", "mod_mipi34_sleep"), /* dat0 */ - DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis, - "stm", "mod_mipi34_sleep"), /* uartmod rx */ - DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis, - "stm", "mod_mipi34_sleep"), /* uartmod tx */ - - DB8500_MUX_STATE("stmmod_b_1", "stmmod", - "stm", "mod_microsd"), - DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod", - "stm", "mod_microsd"), - DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod", - "stm", "mod_microsd"), - DB8500_PIN_STATE("GPIO23_AA4", in_nopull, - "stm", "mod_microsd"), /* clk */ - DB8500_PIN_STATE("GPIO25_Y4", in_nopull, - "stm", "mod_microsd"), /* dat0 */ - DB8500_PIN_STATE("GPIO26_Y2", in_nopull, - "stm", "mod_microsd"), /* dat1 */ - DB8500_PIN_STATE("GPIO27_AA2", in_nopull, - "stm", "mod_microsd"), /* dat2 */ - DB8500_PIN_STATE("GPIO28_AA1", in_nopull, - "stm", "mod_microsd"), /* dat3 */ - DB8500_PIN_STATE("GPIO75_H2", in_pu, - "stm", "mod_microsd"), /* uartmod rx */ - DB8500_PIN_STATE("GPIO76_J2", out_lo, - "stm", "mod_microsd"), /* uartmod tx */ - - DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis, - "stm", "mod_microsd_sleep"), /* clk */ - DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis, - "stm", "mod_microsd_sleep"), /* dat0 */ - DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis, - "stm", "mod_microsd_sleep"), /* dat1 */ - DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis, - "stm", "mod_microsd_sleep"), /* dat2 */ - DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis, - "stm", "mod_microsd_sleep"), /* dat3 */ - DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis, - "stm", "mod_microsd_sleep"), /* uartmod rx */ - DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis, - "stm", "mod_microsd_sleep"), /* uartmod tx */ - - /* STM dual Modem/APE pins state */ - DB8500_MUX_STATE("stmmod_oc3_2", "stmmod", - "stm", "mod_mipi34_ape_mipi60"), - DB8500_MUX_STATE("stmape_c_2", "stmape", - "stm", "mod_mipi34_ape_mipi60"), - DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod", - "stm", "mod_mipi34_ape_mipi60"), - DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod", - "stm", "mod_mipi34_ape_mipi60"), - DB8500_PIN_STATE("GPIO70_G5", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* clk */ - DB8500_PIN_STATE("GPIO71_G4", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat3 */ - DB8500_PIN_STATE("GPIO72_H4", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat2 */ - DB8500_PIN_STATE("GPIO73_H3", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat1 */ - DB8500_PIN_STATE("GPIO74_J3", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat0 */ - DB8500_PIN_STATE("GPIO75_H2", in_pu, - "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */ - DB8500_PIN_STATE("GPIO76_J2", out_lo, - "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */ - DB8500_PIN_STATE("GPIO155_C19", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* clk */ - DB8500_PIN_STATE("GPIO156_C17", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat3 */ - DB8500_PIN_STATE("GPIO157_A18", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat2 */ - DB8500_PIN_STATE("GPIO158_C18", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat1 */ - DB8500_PIN_STATE("GPIO159_B19", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat0 */ - - DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */ - DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */ - DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */ - DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */ - DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */ - DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */ - DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */ - DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */ - DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */ - DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */ - DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */ - DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */ -}; - -/* - * These are specifically for the MOP500 and HREFP (pre-v60) version of the - * board, which utilized a TC35892 GPIO expander instead of using a lot of - * on-chip pins as the HREFv60 and later does. - */ -static struct pinctrl_map __initdata mop500_pinmap[] = { - /* Mux in SSP0, pull down RXD pin */ - DB8500_MUX_HOG("ssp0_a_1", "ssp0"), - DB8500_PIN_HOG("GPIO145_C13", pd), - /* - * XENON Flashgun on image processor GPIO (controlled from image - * processor firmware), mux in these image processor GPIO lines 0 - * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up - * the pins. - */ - DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"), - DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"), - DB8500_PIN_HOG("GPIO6_AF6", in_pu), - DB8500_PIN_HOG("GPIO7_AG5", in_pu), - /* TC35892 IRQ, pull up the line, let the driver mux in the pin */ - DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu), - /* Mux in UART1 and set the pull-ups */ - DB8500_MUX_HOG("u1rxtx_a_1", "u1"), - DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */ - DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */ - /* - * Runtime stuff: make it possible to mux in the SKE keypad - * and bias the pins - */ - /* ske default state */ - DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"), - DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */ - DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */ - DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */ - DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */ - DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */ - DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */ - DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */ - DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */ - DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */ - DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */ - DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */ - DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */ - DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */ - DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */ - DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */ - DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */ - /* ske sleep state */ - DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */ - DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */ - DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */ - DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */ - DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */ - DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */ - DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */ - DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */ - DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */ - DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */ - DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */ - DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */ - DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */ - DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */ - DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */ - DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */ - - /* Mux in and drive the SDI0 DAT31DIR line high at runtime */ - DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"), - DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"), -}; - -/* - * The HREFv60 series of platforms is using available pins on the DB8500 - * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0 - * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines. - */ -static struct pinctrl_map __initdata hrefv60_pinmap[] = { - /* Drive WLAN_ENA low */ - DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */ - /* - * XENON Flashgun on image processor GPIO (controlled from image - * processor firmware), mux in these image processor GPIO lines 0 - * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant - * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias - * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output. - */ - DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"), - DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"), - DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"), - DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */ - DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */ - DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */ - DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */ - /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ - DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */ - DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */ - /* - * Display Interface 1 uses GPIO 65 for RST (reset). - * Display Interface 2 uses GPIO 66 for RST (reset). - * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) - */ - DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */ - DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */ - /* - * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and - * GPIO 67 for interrupts. Pull-up the IRQ line and drive both - * reset signals low. - */ - DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */ - DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */ - DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */ - /* - * Drive D19-D23 for the ETM PTM trace interface low, - * (presumably pins are unconnected therefore grounded here, - * the "other alt C1" setting enables these pins) - */ - DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo), - DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo), - DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo), - DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo), - DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo), - /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */ - DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */ - DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */ - /* NFC ENA and RESET to low, pulldown IRQ line */ - DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */ - DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */ - DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */ - /* - * SKE keyboard partly on alt A and partly on "Other alt C1" - * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three - * rows of 6 keys, then pull up force sensing interrup and - * drive reset and force sensing WU low. - */ - DB8500_MUX_HOG("kp_a_1", "kp"), - DB8500_MUX_HOG("kp_oc1_1", "kp"), - DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */ - DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */ - DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */ - DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */ - DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */ - DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */ - DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */ - DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */ - DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */ - DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */ - DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */ - /* DiPro Sensor interrupt */ - DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */ - /* Audio Amplifier HF enable */ - DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */ - /* GBF interface, pull low to reset state */ - DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */ - /* MSP : HDTV INTERFACE GPIO line */ - DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd), - /* Accelerometer interrupt lines */ - DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */ - DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */ - /* SD card detect GPIO pin */ - DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu), - /* - * Runtime stuff - * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor - * etc. - */ - DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"), - DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"), - DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"), -}; - -static struct pinctrl_map __initdata u9500_pinmap[] = { - /* Mux in UART1 (just RX/TX) and set the pull-ups */ - DB8500_MUX_HOG("u1rxtx_a_1", "u1"), - DB8500_PIN_HOG("GPIO4_AH6", in_pu), - DB8500_PIN_HOG("GPIO5_AG6", out_hi), - /* WLAN_IRQ line */ - DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu), - /* HSI */ - DB8500_MUX_HOG("hsir_a_1", "hsi"), - DB8500_MUX_HOG("hsit_a_2", "hsi"), - DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */ - DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */ - DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */ - DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */ - DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */ - DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */ - DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */ - DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */ -}; - -static struct pinctrl_map __initdata u8500_pinmap[] = { - DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */ - DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */ -}; - -static struct pinctrl_map __initdata snowball_pinmap[] = { - /* Mux in SSP0 connected to AB8500, pull down RXD pin */ - DB8500_MUX_HOG("ssp0_a_1", "ssp0"), - DB8500_PIN_HOG("GPIO145_C13", pd), - /* Always drive the MC0 DAT31DIR line high on these boards */ - DB8500_PIN_HOG("GPIO21_AB3", out_hi), - /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */ - DB8500_MUX_HOG("sm_b_1", "sm"), - /* User LED */ - DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi), - /* Drive RSTn_LAN high */ - DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi), - /* Accelerometer/Magnetometer */ - DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */ - DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */ - DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */ - /* WLAN/GBF */ - DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */ - DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */ - DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */ - DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */ -}; - -/* - * passing "pinsfor=" in kernel cmdline allows for custom - * configuration of GPIOs on u8500 derived boards. - */ -static int __init early_pinsfor(char *p) -{ - pinsfor = PINS_FOR_DEFAULT; - - if (strcmp(p, "u9500-21") == 0) - pinsfor = PINS_FOR_U9500; - - return 0; -} -early_param("pinsfor", early_pinsfor); - -int pins_for_u9500(void) -{ - if (pinsfor == PINS_FOR_U9500) - return 1; - - return 0; -} - -static void __init mop500_href_family_pinmaps_init(void) -{ - switch (pinsfor) { - case PINS_FOR_U9500: - pinctrl_register_mappings(u9500_pinmap, - ARRAY_SIZE(u9500_pinmap)); - break; - case PINS_FOR_DEFAULT: - pinctrl_register_mappings(u8500_pinmap, - ARRAY_SIZE(u8500_pinmap)); - default: - break; - } -} - void __init mop500_pinmaps_init(void) { - pinctrl_register_mappings(mop500_family_pinmap, - ARRAY_SIZE(mop500_family_pinmap)); - pinctrl_register_mappings(mop500_pinmap, - ARRAY_SIZE(mop500_pinmap)); - mop500_href_family_pinmaps_init(); if (machine_is_u8520()) pinctrl_register_mappings(ab8505_pinmap, ARRAY_SIZE(ab8505_pinmap)); @@ -1073,23 +280,12 @@ void __init mop500_pinmaps_init(void) void __init snowball_pinmaps_init(void) { - pinctrl_register_mappings(mop500_family_pinmap, - ARRAY_SIZE(mop500_family_pinmap)); - pinctrl_register_mappings(snowball_pinmap, - ARRAY_SIZE(snowball_pinmap)); - pinctrl_register_mappings(u8500_pinmap, - ARRAY_SIZE(u8500_pinmap)); pinctrl_register_mappings(ab8500_pinmap, ARRAY_SIZE(ab8500_pinmap)); } void __init hrefv60_pinmaps_init(void) { - pinctrl_register_mappings(mop500_family_pinmap, - ARRAY_SIZE(mop500_family_pinmap)); - pinctrl_register_mappings(hrefv60_pinmap, - ARRAY_SIZE(hrefv60_pinmap)); - mop500_href_family_pinmaps_init(); pinctrl_register_mappings(ab8500_pinmap, ARRAY_SIZE(ab8500_pinmap)); } diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c index 0dc44c6..a4e139a 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ b/arch/arm/mach-ux500/board-mop500-regulators.c @@ -30,20 +30,6 @@ struct regulator_init_data gpio_en_3v3_regulator = { .consumer_supplies = gpio_en_3v3_consumers, }; -static struct regulator_consumer_supply sdi0_reg_consumers[] = { - REGULATOR_SUPPLY("vqmmc", "sdi0"), -}; - -struct regulator_init_data sdi0_reg_init_data = { - .constraints = { - .min_uV = 1800000, - .max_uV = 2900000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(sdi0_reg_consumers), - .consumer_supplies = sdi0_reg_consumers, -}; - /* * TPS61052 regulator */ diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h index 039f513..9bece38 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.h +++ b/arch/arm/mach-ux500/board-mop500-regulators.h @@ -18,7 +18,6 @@ extern struct ab8500_regulator_platform_data ab8500_regulator_plat_data; extern struct ab8500_regulator_platform_data ab8505_regulator_plat_data; extern struct regulator_init_data tps61052_regulator; extern struct regulator_init_data gpio_en_3v3_regulator; -extern struct regulator_init_data sdi0_reg_init_data; void mop500_regulator_init(void); diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 26600a1..fcbf3a1 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -14,10 +14,8 @@ #include <linux/platform_data/dma-ste-dma40.h> #include <asm/mach-types.h> -#include "devices.h" #include "db8500-regs.h" -#include "devices-db8500.h" #include "board-mop500.h" #include "ste-dma40-db8500.h" diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c deleted file mode 100644 index 514d40b..0000000 --- a/arch/arm/mach-ux500/board-mop500.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (C) 2008-2012 ST-Ericsson - * - * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2, as - * published by the Free Software Foundation. - * - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/platform_data/db8500_thermal.h> -#include <linux/amba/bus.h> -#include <linux/amba/pl022.h> -#include <linux/mfd/abx500/ab8500.h> -#include <linux/regulator/ab8500.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/driver.h> -#include <linux/mfd/tps6105x.h> -#include <linux/platform_data/leds-lp55xx.h> -#include <linux/input.h> -#include <linux/delay.h> -#include <linux/leds.h> -#include <linux/pinctrl/consumer.h> -#include <linux/platform_data/pinctrl-nomadik.h> -#include <linux/platform_data/dma-ste-dma40.h> - -#include <asm/mach-types.h> - -#include "setup.h" -#include "devices.h" -#include "irqs.h" - -#include "ste-dma40-db8500.h" -#include "db8500-regs.h" -#include "devices-db8500.h" -#include "board-mop500.h" -#include "board-mop500-regulators.h" - -struct ab8500_platform_data ab8500_platdata = { - .irq_base = MOP500_AB8500_IRQ_BASE, - .regulator = &ab8500_regulator_plat_data, -}; - -#ifdef CONFIG_STE_DMA40 -static struct stedma40_chan_cfg ssp0_dma_cfg_rx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = DMA_DEV_TO_MEM, - .dev_type = DB8500_DMA_DEV8_SSP0, -}; - -static struct stedma40_chan_cfg ssp0_dma_cfg_tx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = DMA_MEM_TO_DEV, - .dev_type = DB8500_DMA_DEV8_SSP0, -}; -#endif - -struct pl022_ssp_controller ssp0_plat = { - .bus_id = 0, -#ifdef CONFIG_STE_DMA40 - .enable_dma = 1, - .dma_filter = stedma40_filter, - .dma_rx_param = &ssp0_dma_cfg_rx, - .dma_tx_param = &ssp0_dma_cfg_tx, -#else - .enable_dma = 0, -#endif - /* on this platform, gpio 31,142,144,214 & - * 224 are connected as chip selects - */ - .num_chipselect = 5, -}; diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index 511d6fe..d48e866 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -87,7 +87,6 @@ extern struct msp_i2s_platform_data msp0_platform_data; extern struct msp_i2s_platform_data msp1_platform_data; extern struct msp_i2s_platform_data msp2_platform_data; extern struct msp_i2s_platform_data msp3_platform_data; -extern struct pl022_ssp_controller ssp0_plat; void __init mop500_pinmaps_init(void); void __init snowball_pinmaps_init(void); diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 12c7e5c..bc8a618 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -21,21 +21,32 @@ #include <linux/of.h> #include <linux/of_platform.h> #include <linux/regulator/machine.h> -#include <linux/platform_data/pinctrl-nomadik.h> #include <linux/random.h> #include <asm/pmu.h> #include <asm/mach/map.h> #include "setup.h" -#include "devices.h" #include "irqs.h" -#include "devices-db8500.h" -#include "db8500-regs.h" +#include "board-mop500-regulators.h" #include "board-mop500.h" +#include "db8500-regs.h" #include "id.h" +struct ab8500_platform_data ab8500_platdata = { + .irq_base = MOP500_AB8500_IRQ_BASE, + .regulator = &ab8500_regulator_plat_data, +}; + +struct prcmu_pdata db8500_prcmu_pdata = { + .ab_platdata = &ab8500_platdata, + .ab_irq = IRQ_DB8500_AB8500, + .irq_base = IRQ_PRCMU_BASE, + .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET, + .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, +}; + /* minimum static i/o mapping required to boot U8500 platforms */ static struct map_desc u8500_uart_io_desc[] __initdata = { __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), @@ -159,17 +170,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL), OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0", NULL), - /* Requires device name bindings. */ - OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE, - "pinctrl-db8500", NULL), {}, }; static struct of_dev_auxdata u8540_auxdata_lookup[] __initdata = { - /* Requires DMA bindings. */ - OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL), - OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL), - OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL), OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", &db8500_prcmu_pdata), {}, diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index f84d439..d11ac4b 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -25,7 +25,6 @@ #include <asm/mach/map.h> #include "setup.h" -#include "devices.h" #include "board-mop500.h" #include "db8500-regs.h" @@ -64,12 +63,7 @@ void __init ux500_init_irq(void) } else ux500_unknown_soc(); -#ifdef CONFIG_OF - if (of_have_populated_dt()) - irqchip_init(); - else -#endif - gic_init(0, 29, dist_base, cpu_base); + irqchip_init(); /* * Init clocks here so that they are available for system timer @@ -79,16 +73,11 @@ void __init ux500_init_irq(void) prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); - if (of_have_populated_dt()) - u8500_of_clk_init(U8500_CLKRST1_BASE, - U8500_CLKRST2_BASE, - U8500_CLKRST3_BASE, - U8500_CLKRST5_BASE, - U8500_CLKRST6_BASE); - else - u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, - U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, - U8500_CLKRST6_BASE); + u8500_of_clk_init(U8500_CLKRST1_BASE, + U8500_CLKRST2_BASE, + U8500_CLKRST3_BASE, + U8500_CLKRST5_BASE, + U8500_CLKRST6_BASE); } else if (cpu_is_u9540()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c deleted file mode 100644 index c59f89d..0000000 --- a/arch/arm/mach-ux500/devices-db8500.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/amba/bus.h> -#include <linux/amba/pl022.h> -#include <linux/mfd/dbx500-prcmu.h> - -#include "setup.h" -#include "irqs.h" - -#include "db8500-regs.h" -#include "devices-db8500.h" - -struct prcmu_pdata db8500_prcmu_pdata = { - .ab_platdata = &ab8500_platdata, - .ab_irq = IRQ_DB8500_AB8500, - .irq_base = IRQ_PRCMU_BASE, - .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET, - .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, -}; diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h deleted file mode 100644 index b8ffc99..0000000 --- a/arch/arm/mach-ux500/devices-db8500.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL), version 2. - */ - -#ifndef __DEVICES_DB8500_H -#define __DEVICES_DB8500_H - -#include "irqs.h" -#include "db8500-regs.h" - -struct platform_device; - -extern struct ab8500_platform_data ab8500_platdata; -extern struct prcmu_pdata db8500_prcmu_pdata; - -#endif diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c deleted file mode 100644 index 0f9e52b..0000000 --- a/arch/arm/mach-ux500/devices.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/amba/bus.h> - -#include "setup.h" - -#include "db8500-regs.h" - -void __init amba_add_devices(struct amba_device *devs[], int num) -{ - int i; - - for (i = 0; i < num; i++) { - struct amba_device *d = devs[i]; - amba_device_register(d, &iomem_resource); - } -} diff --git a/arch/arm/mach-ux500/devices.h b/arch/arm/mach-ux500/devices.h deleted file mode 100644 index 5bca7c6..0000000 --- a/arch/arm/mach-ux500/devices.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __ASM_ARCH_DEVICES_H__ -#define __ASM_ARCH_DEVICES_H__ - -struct platform_device; -struct amba_device; - -extern struct amba_device ux500_pl031_device; - -#endif diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 1f296e7..a44967f 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -38,8 +38,7 @@ static void write_pen_release(int val) { pen_release = val; smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + sync_cache_w(&pen_release); } static void __iomem *scu_base_addr(void) diff --git a/arch/arm/mach-ux500/pm.c b/arch/arm/mach-ux500/pm.c index 1a468f0..b80a9a2 100644 --- a/arch/arm/mach-ux500/pm.c +++ b/arch/arm/mach-ux500/pm.c @@ -3,6 +3,8 @@ * Author: Rickard Andersson <rickard.andersson@stericsson.com> for * ST-Ericsson. * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro. + * Author: Ulf Hansson <ulf.hansson@linaro.org> for Linaro. + * * License terms: GNU General Public License (GPL) version 2 * */ @@ -11,6 +13,7 @@ #include <linux/irqchip/arm-gic.h> #include <linux/delay.h> #include <linux/io.h> +#include <linux/suspend.h> #include <linux/platform_data/arm-ux500-pm.h> #include "db8500-regs.h" @@ -152,6 +155,27 @@ int prcmu_copy_gic_settings(void) return 0; } +#ifdef CONFIG_SUSPEND +static int ux500_suspend_enter(suspend_state_t state) +{ + cpu_do_idle(); + return 0; +} + +static int ux500_suspend_valid(suspend_state_t state) +{ + return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; +} + +static const struct platform_suspend_ops ux500_suspend_ops = { + .enter = ux500_suspend_enter, + .valid = ux500_suspend_valid, +}; +#define UX500_SUSPEND_OPS (&ux500_suspend_ops) +#else +#define UX500_SUSPEND_OPS NULL +#endif + void __init ux500_pm_init(u32 phy_base, u32 size) { prcmu_base = ioremap(phy_base, size); @@ -164,4 +188,7 @@ void __init ux500_pm_init(u32 phy_base, u32 size) * This will make sure that the GIC is correctly configured. */ prcmu_gic_recouple(); + + /* Set up ux500 suspend callbacks. */ + suspend_set_ops(UX500_SUSPEND_OPS); } diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h index bdb3564..2dea8b5 100644 --- a/arch/arm/mach-ux500/setup.h +++ b/arch/arm/mach-ux500/setup.h @@ -19,17 +19,11 @@ void ux500_restart(enum reboot_mode mode, const char *cmd); void __init ux500_map_io(void); -extern void __init u8500_map_io(void); - -extern struct device * __init u8500_init_devices(void); extern void __init ux500_init_irq(void); extern struct device *ux500_soc_device_init(const char *soc_id); -struct amba_device; -extern void __init amba_add_devices(struct amba_device *devs[], int num); - extern void ux500_timer_init(void); #define __IO_DEV_DESC(x, sz) { \ @@ -43,7 +37,7 @@ extern void ux500_timer_init(void); .virtual = IO_ADDRESS(x), \ .pfn = __phys_to_pfn(x), \ .length = sz, \ - .type = MT_MEMORY, \ + .type = MT_MEMORY_RWX, \ } extern struct smp_operations ux500_smp_ops; diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index 05a4ff7..87efda0 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -10,40 +10,12 @@ #include <linux/clocksource.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/platform_data/clocksource-nomadik-mtu.h> - -#include <asm/smp_twd.h> #include "setup.h" -#include "irqs.h" #include "db8500-regs.h" #include "id.h" -#ifdef CONFIG_HAVE_ARM_TWD -static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer, - U8500_TWD_BASE, IRQ_LOCALTIMER); - -static void __init ux500_twd_init(void) -{ - struct twd_local_timer *twd_local_timer; - int err; - - /* Use this to switch local timer base if changed in new ASICs */ - twd_local_timer = &u8500_twd_local_timer; - - if (of_have_populated_dt()) - clocksource_of_init(); - else { - err = twd_local_timer_register(twd_local_timer); - if (err) - pr_err("twd_local_timer_register failed %d\n", err); - } -} -#else -#define ux500_twd_init() do { } while(0) -#endif - const static struct of_device_id prcmu_timer_of_match[] __initconst = { { .compatible = "stericsson,db8500-prcmu-timer-4", }, { }, @@ -51,54 +23,26 @@ const static struct of_device_id prcmu_timer_of_match[] __initconst = { void __init ux500_timer_init(void) { - void __iomem *mtu_timer_base; void __iomem *prcmu_timer_base; void __iomem *tmp_base; struct device_node *np; - if (cpu_is_u8500_family() || cpu_is_ux540_family()) { - mtu_timer_base = __io_address(U8500_MTU0_BASE); + if (cpu_is_u8500_family() || cpu_is_ux540_family()) prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); - } else { + else ux500_unknown_soc(); - } - /* TODO: Once MTU has been DT:ed place code above into else. */ - if (of_have_populated_dt()) { -#ifdef CONFIG_OF - np = of_find_matching_node(NULL, prcmu_timer_of_match); - if (!np) -#endif - goto dt_fail; + np = of_find_matching_node(NULL, prcmu_timer_of_match); + if (!np) + goto dt_fail; - tmp_base = of_iomap(np, 0); - if (!tmp_base) - goto dt_fail; + tmp_base = of_iomap(np, 0); + if (!tmp_base) + goto dt_fail; - prcmu_timer_base = tmp_base; - } + prcmu_timer_base = tmp_base; dt_fail: - /* Doing it the old fashioned way. */ - - /* - * Here we register the timerblocks active in the system. - * Localtimers (twd) is started when both cpu is up and running. - * MTU register a clocksource, clockevent and sched_clock. - * Since the MTU is located in the VAPE power domain - * it will be cleared in sleep which makes it unsuitable. - * We however need it as a timer tick (clockevent) - * during boot to calibrate delay until twd is started. - * RTC-RTT have problems as timer tick during boot since it is - * depending on delay which is not yet calibrated. RTC-RTT is in the - * always-on powerdomain and is used as clockevent instead of twd when - * sleeping. - * The PRCMU timer 4 register a clocksource and - * sched_clock with higher rating then MTU since is always-on. - * - */ - if (!of_have_populated_dt()) - nmdk_timer_init(mtu_timer_base, IRQ_MTU0); clksrc_dbx500_prcmu_init(prcmu_timer_base); - ux500_twd_init(); + clocksource_of_init(); } diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 3b0572f..a335126 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -570,6 +570,16 @@ static struct pl061_platform_data gpio1_plat_data = { .irq_base = IRQ_GPIO1_START, }; +static struct pl061_platform_data gpio2_plat_data = { + .gpio_base = 16, + .irq_base = IRQ_GPIO2_START, +}; + +static struct pl061_platform_data gpio3_plat_data = { + .gpio_base = 24, + .irq_base = IRQ_GPIO3_START, +}; + static struct pl022_ssp_controller ssp0_plat_data = { .bus_id = 0, .enable_dma = 0, @@ -596,6 +606,8 @@ static struct pl022_ssp_controller ssp0_plat_data = { #define WATCHDOG_IRQ { IRQ_WDOGINT } #define GPIO0_IRQ { IRQ_GPIOINT0 } #define GPIO1_IRQ { IRQ_GPIOINT1 } +#define GPIO2_IRQ { IRQ_GPIOINT2 } +#define GPIO3_IRQ { IRQ_GPIOINT3 } #define RTC_IRQ { IRQ_RTCINT } /* @@ -622,6 +634,8 @@ APB_DEVICE(sctl, "dev:e0", SCTL, NULL); APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL); APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data); APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data); +APB_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data); +APB_DEVICE(gpio3, "dev:e7", GPIO3, &gpio3_plat_data); APB_DEVICE(rtc, "dev:e8", RTC, NULL); APB_DEVICE(sci0, "dev:f0", SCI, NULL); APB_DEVICE(uart0, "dev:f1", UART0, NULL); @@ -641,6 +655,8 @@ static struct amba_device *amba_devs[] __initdata = { &wdog_device, &gpio0_device, &gpio1_device, + &gpio2_device, + &gpio3_device, &rtc_device, &sci0_device, &ssp0_device, diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c index 611d140..9a53d0bd 100644 --- a/arch/arm/mach-versatile/versatile_pb.c +++ b/arch/arm/mach-versatile/versatile_pb.c @@ -47,27 +47,11 @@ static struct mmci_platform_data mmc1_plat_data = { .gpio_cd = -1, }; -static struct pl061_platform_data gpio2_plat_data = { - .gpio_base = 16, - .irq_base = IRQ_GPIO2_START, -}; - -static struct pl061_platform_data gpio3_plat_data = { - .gpio_base = 24, - .irq_base = IRQ_GPIO3_START, -}; - #define UART3_IRQ { IRQ_SIC_UART3 } #define SCI1_IRQ { IRQ_SIC_SCI3 } #define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B } /* - * These devices are connected via the core APB bridge - */ -#define GPIO2_IRQ { IRQ_GPIOINT2 } -#define GPIO3_IRQ { IRQ_GPIOINT3 } - -/* * These devices are connected via the DMA APB bridge */ @@ -76,14 +60,9 @@ APB_DEVICE(uart3, "fpga:09", UART3, NULL); APB_DEVICE(sci1, "fpga:0a", SCI1, NULL); APB_DEVICE(mmc1, "fpga:0b", MMCI1, &mmc1_plat_data); -/* DevChip Primecells */ -APB_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data); -APB_DEVICE(gpio3, "dev:e7", GPIO3, &gpio3_plat_data); static struct amba_device *amba_devs[] __initdata = { &uart3_device, - &gpio2_device, - &gpio3_device, &sci1_device, &mmc1_device, }; diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 9a7bd13..1db2a5ca 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -25,6 +25,8 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/of.h> +#include <linux/irqchip.h> +#include <linux/irqchip/arm-gic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -39,11 +41,6 @@ void __iomem *zynq_scu_base; -static struct of_device_id zynq_of_bus_ids[] __initdata = { - { .compatible = "simple-bus", }, - {} -}; - static struct platform_device zynq_cpuidle_device = { .name = "cpuidle-zynq", }; @@ -59,7 +56,7 @@ static void __init zynq_init_machine(void) */ l2x0_of_init(0x02060000, 0xF0F0FFFF); - of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); platform_device_register(&zynq_cpuidle_device); } @@ -97,6 +94,12 @@ static void __init zynq_map_io(void) zynq_scu_map_io(); } +static void __init zynq_irq_init(void) +{ + gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; + irqchip_init(); +} + static void zynq_system_reset(enum reboot_mode mode, const char *cmd) { zynq_slcr_system_reset(); @@ -110,6 +113,7 @@ static const char * const zynq_dt_match[] = { DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") .smp = smp_ops(zynq_smp_ops), .map_io = zynq_map_io, + .init_irq = zynq_irq_init, .init_machine = zynq_init_machine, .init_time = zynq_timer_init, .dt_compat = zynq_dt_match, diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index 3040d21..c22c92c 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -17,6 +17,8 @@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ +void zynq_secondary_startup(void); + extern int zynq_slcr_init(void); extern void zynq_slcr_system_reset(void); extern void zynq_slcr_cpu_stop(int cpu); diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S index d4cd5f3..57a3286 100644 --- a/arch/arm/mach-zynq/headsmp.S +++ b/arch/arm/mach-zynq/headsmp.S @@ -18,5 +18,9 @@ zynq_secondary_trampoline_jump: .word /* cpu 1 */ .globl zynq_secondary_trampoline_end zynq_secondary_trampoline_end: - ENDPROC(zynq_secondary_trampoline) + +ENTRY(zynq_secondary_startup) + bl v7_invalidate_l1 + b secondary_startup +ENDPROC(zynq_secondary_startup) diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c index 689fbbc..abc82ef 100644 --- a/arch/arm/mach-zynq/platsmp.c +++ b/arch/arm/mach-zynq/platsmp.c @@ -39,11 +39,6 @@ int zynq_cpun_start(u32 address, int cpu) u32 trampoline_code_size = &zynq_secondary_trampoline_end - &zynq_secondary_trampoline; - if (cpu > ncores) { - pr_warn("CPU No. is not available in the system\n"); - return -1; - } - /* MS: Expectation that SLCR are directly map and accessible */ /* Not possible to jump to non aligned address */ if (!(address & 3) && (!address || (address >= trampoline_code_size))) { @@ -95,7 +90,7 @@ EXPORT_SYMBOL(zynq_cpun_start); static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle) { - return zynq_cpun_start(virt_to_phys(secondary_startup), cpu); + return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu); } /* @@ -114,23 +109,23 @@ static void __init zynq_smp_init_cpus(void) static void __init zynq_smp_prepare_cpus(unsigned int max_cpus) { - int i; - - /* - * Initialise the present map, which describes the set of CPUs - * actually populated at the present time. - */ - for (i = 0; i < max_cpus; i++) - set_cpu_present(i, true); - scu_enable(zynq_scu_base); } +#ifdef CONFIG_HOTPLUG_CPU +static int zynq_cpu_kill(unsigned cpu) +{ + zynq_slcr_cpu_stop(cpu); + return 1; +} +#endif + struct smp_operations zynq_smp_ops __initdata = { .smp_init_cpus = zynq_smp_init_cpus, .smp_prepare_cpus = zynq_smp_prepare_cpus, .smp_boot_secondary = zynq_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = zynq_platform_cpu_die, + .cpu_kill = zynq_cpu_kill, #endif }; diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index ecfe6e5..7f39ce2 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -12,6 +12,7 @@ ifneq ($(CONFIG_MMU),y) obj-y += nommu.o endif +obj-$(CONFIG_ARM_PTDUMP) += dump.o obj-$(CONFIG_MODULES) += proc-syms.o obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 447da6f..7abde2c 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -25,6 +25,7 @@ #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h> +#include "cache-tauros3.h" #include "cache-aurora-l2.h" #define CACHE_LINE_SIZE 32 @@ -767,6 +768,14 @@ static void aurora_save(void) l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); } +static void __init tauros3_save(void) +{ + l2x0_saved_regs.aux2_ctrl = + readl_relaxed(l2x0_base + TAUROS3_AUX2_CTRL); + l2x0_saved_regs.prefetch_ctrl = + readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); +} + static void l2x0_resume(void) { if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { @@ -821,6 +830,18 @@ static void aurora_resume(void) } } +static void tauros3_resume(void) +{ + if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { + writel_relaxed(l2x0_saved_regs.aux2_ctrl, + l2x0_base + TAUROS3_AUX2_CTRL); + writel_relaxed(l2x0_saved_regs.prefetch_ctrl, + l2x0_base + L2X0_PREFETCH_CTRL); + } + + l2x0_resume(); +} + static void __init aurora_broadcast_l2_commands(void) { __u32 u; @@ -906,6 +927,15 @@ static const struct l2x0_of_data aurora_no_outer_data = { }, }; +static const struct l2x0_of_data tauros3_data = { + .setup = NULL, + .save = tauros3_save, + /* Tauros3 broadcasts L1 cache operations to L2 */ + .outer_cache = { + .resume = tauros3_resume, + }, +}; + static const struct l2x0_of_data bcm_l2x0_data = { .setup = pl310_of_setup, .save = pl310_save, @@ -922,17 +952,19 @@ static const struct l2x0_of_data bcm_l2x0_data = { }; static const struct of_device_id l2x0_ids[] __initconst = { - { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data }, - { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data }, { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data }, - { .compatible = "marvell,aurora-system-cache", - .data = (void *)&aurora_no_outer_data}, - { .compatible = "marvell,aurora-outer-cache", - .data = (void *)&aurora_with_outer_data}, - { .compatible = "brcm,bcm11351-a2-pl310-cache", - .data = (void *)&bcm_l2x0_data}, + { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data }, + { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data }, { .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */ .data = (void *)&bcm_l2x0_data}, + { .compatible = "brcm,bcm11351-a2-pl310-cache", + .data = (void *)&bcm_l2x0_data}, + { .compatible = "marvell,aurora-outer-cache", + .data = (void *)&aurora_with_outer_data}, + { .compatible = "marvell,aurora-system-cache", + .data = (void *)&aurora_no_outer_data}, + { .compatible = "marvell,tauros3-cache", + .data = (void *)&tauros3_data }, {} }; diff --git a/arch/arm/mm/cache-tauros3.h b/arch/arm/mm/cache-tauros3.h new file mode 100644 index 0000000..02c0a97 --- /dev/null +++ b/arch/arm/mm/cache-tauros3.h @@ -0,0 +1,41 @@ +/* + * Marvell Tauros3 cache controller includes + * + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * + * based on GPL'ed 2.6 kernel sources + * (c) Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_HARDWARE_TAUROS3_H +#define __ASM_ARM_HARDWARE_TAUROS3_H + +/* + * Marvell Tauros3 L2CC is compatible with PL310 r0p0 + * but with PREFETCH_CTRL (r2p0) and an additional event counter. + * Also, there is AUX2_CTRL for some Marvell specific control. + */ + +#define TAUROS3_EVENT_CNT2_CFG 0x224 +#define TAUROS3_EVENT_CNT2_VAL 0x228 +#define TAUROS3_INV_ALL 0x780 +#define TAUROS3_CLEAN_ALL 0x784 +#define TAUROS3_AUX2_CTRL 0x820 + +/* Registers shifts and masks */ +#define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN (1 << 2) + +#endif diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index b5c467a..778bcf8 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -146,18 +146,18 @@ flush_levels: ldr r7, =0x7fff ands r7, r7, r1, lsr #13 @ extract max number of the index size loop1: - mov r9, r4 @ create working copy of max way size + mov r9, r7 @ create working copy of max index loop2: - ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 - THUMB( lsl r6, r9, r5 ) + ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11 + THUMB( lsl r6, r4, r5 ) THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 - ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 - THUMB( lsl r6, r7, r2 ) + ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11 + THUMB( lsl r6, r9, r2 ) THUMB( orr r11, r11, r6 ) @ factor index number into r11 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way - subs r9, r9, #1 @ decrement the way + subs r9, r9, #1 @ decrement the index bge loop2 - subs r7, r7, #1 @ decrement the index + subs r4, r4, #1 @ decrement the way bge loop1 skip: add r10, r10, #2 @ increment cache number diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index 84e6f77..6eb97b3 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -36,8 +36,8 @@ * The context ID is used by debuggers and trace logic, and * should be unique within all running processes. * - * In big endian operation, the two 32 bit words are swapped if accesed by - * non 64-bit operations. + * In big endian operation, the two 32 bit words are swapped if accessed + * by non-64-bit operations. */ #define ASID_FIRST_VERSION (1ULL << ASID_BITS) #define NUM_USER_ASIDS ASID_FIRST_VERSION @@ -78,20 +78,21 @@ void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm, #endif #ifdef CONFIG_ARM_LPAE -static void cpu_set_reserved_ttbr0(void) -{ - /* - * Set TTBR0 to swapper_pg_dir which contains only global entries. The - * ASID is set to 0. - */ - cpu_set_ttbr(0, __pa(swapper_pg_dir)); - isb(); -} +/* + * With LPAE, the ASID and page tables are updated atomicly, so there is + * no need for a reserved set of tables (the active ASID tracking prevents + * any issues across a rollover). + */ +#define cpu_set_reserved_ttbr0() #else static void cpu_set_reserved_ttbr0(void) { u32 ttb; - /* Copy TTBR1 into TTBR0 */ + /* + * Copy TTBR1 into TTBR0. + * This points at swapper_pg_dir, which contains only global + * entries so any speculative walks are perfectly safe. + */ asm volatile( " mrc p15, 0, %0, c2, c0, 1 @ read TTBR1\n" " mcr p15, 0, %0, c2, c0, 0 @ set TTBR0\n" @@ -179,6 +180,7 @@ static int is_reserved_asid(u64 asid) static u64 new_context(struct mm_struct *mm, unsigned int cpu) { + static u32 cur_idx = 1; u64 asid = atomic64_read(&mm->context.id); u64 generation = atomic64_read(&asid_generation); @@ -193,10 +195,13 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu) * Allocate a free ASID. If we can't find one, take a * note of the currently active ASIDs and mark the TLBs * as requiring flushes. We always count from ASID #1, - * as we reserve ASID #0 to switch via TTBR0 and indicate - * rollover events. + * as we reserve ASID #0 to switch via TTBR0 and to + * avoid speculative page table walks from hitting in + * any partial walk caches, which could be populated + * from overlapping level-1 descriptors used to map both + * the module area and the userspace stack. */ - asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1); + asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx); if (asid == NUM_USER_ASIDS) { generation = atomic64_add_return(ASID_FIRST_VERSION, &asid_generation); @@ -204,6 +209,7 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu) asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1); } __set_bit(asid, asid_map); + cur_idx = asid; asid |= generation; cpumask_clear(mm_cpumask(mm)); } @@ -221,8 +227,9 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk) __check_vmalloc_seq(mm); /* - * Required during context switch to avoid speculative page table - * walking with the wrong TTBR. + * We cannot update the pgd and the ASID atomicly with classic + * MMU, so switch exclusively to global mappings to avoid + * speculative page table walking with the wrong TTBR. */ cpu_set_reserved_ttbr0(); diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index f61a570..1a77450 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -376,7 +376,7 @@ void __init init_dma_coherent_pool_size(unsigned long size) static int __init atomic_pool_init(void) { struct dma_pool *pool = &atomic_pool; - pgprot_t prot = pgprot_dmacoherent(pgprot_kernel); + pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL); gfp_t gfp = GFP_KERNEL | GFP_DMA; unsigned long nr_pages = pool->size >> PAGE_SHIFT; unsigned long *bitmap; @@ -624,7 +624,7 @@ static void __free_from_contiguous(struct device *dev, struct page *page, if (PageHighMem(page)) __dma_free_remap(cpu_addr, size); else - __dma_remap(page, size, pgprot_kernel); + __dma_remap(page, size, PAGE_KERNEL); dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); } @@ -1351,7 +1351,7 @@ static void __iommu_free_atomic(struct device *dev, void *cpu_addr, static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) { - pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); + pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); struct page **pages; void *addr = NULL; diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c new file mode 100644 index 0000000..2b3a564 --- /dev/null +++ b/arch/arm/mm/dump.c @@ -0,0 +1,345 @@ +/* + * Debug helper to dump the current kernel pagetables of the system + * so that we can see what the various memory ranges are set to. + * + * Derived from x86 implementation: + * (C) Copyright 2008 Intel Corporation + * + * Author: Arjan van de Ven <arjan@linux.intel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ +#include <linux/debugfs.h> +#include <linux/fs.h> +#include <linux/mm.h> +#include <linux/seq_file.h> + +#include <asm/fixmap.h> +#include <asm/pgtable.h> + +struct addr_marker { + unsigned long start_address; + const char *name; +}; + +static struct addr_marker address_markers[] = { + { MODULES_VADDR, "Modules" }, + { PAGE_OFFSET, "Kernel Mapping" }, + { 0, "vmalloc() Area" }, + { VMALLOC_END, "vmalloc() End" }, + { FIXADDR_START, "Fixmap Area" }, + { CONFIG_VECTORS_BASE, "Vectors" }, + { CONFIG_VECTORS_BASE + PAGE_SIZE * 2, "Vectors End" }, + { -1, NULL }, +}; + +struct pg_state { + struct seq_file *seq; + const struct addr_marker *marker; + unsigned long start_address; + unsigned level; + u64 current_prot; +}; + +struct prot_bits { + u64 mask; + u64 val; + const char *set; + const char *clear; +}; + +static const struct prot_bits pte_bits[] = { + { + .mask = L_PTE_USER, + .val = L_PTE_USER, + .set = "USR", + .clear = " ", + }, { + .mask = L_PTE_RDONLY, + .val = L_PTE_RDONLY, + .set = "ro", + .clear = "RW", + }, { + .mask = L_PTE_XN, + .val = L_PTE_XN, + .set = "NX", + .clear = "x ", + }, { + .mask = L_PTE_SHARED, + .val = L_PTE_SHARED, + .set = "SHD", + .clear = " ", + }, { + .mask = L_PTE_MT_MASK, + .val = L_PTE_MT_UNCACHED, + .set = "SO/UNCACHED", + }, { + .mask = L_PTE_MT_MASK, + .val = L_PTE_MT_BUFFERABLE, + .set = "MEM/BUFFERABLE/WC", + }, { + .mask = L_PTE_MT_MASK, + .val = L_PTE_MT_WRITETHROUGH, + .set = "MEM/CACHED/WT", + }, { + .mask = L_PTE_MT_MASK, + .val = L_PTE_MT_WRITEBACK, + .set = "MEM/CACHED/WBRA", +#ifndef CONFIG_ARM_LPAE + }, { + .mask = L_PTE_MT_MASK, + .val = L_PTE_MT_MINICACHE, + .set = "MEM/MINICACHE", +#endif + }, { + .mask = L_PTE_MT_MASK, + .val = L_PTE_MT_WRITEALLOC, + .set = "MEM/CACHED/WBWA", + }, { + .mask = L_PTE_MT_MASK, + .val = L_PTE_MT_DEV_SHARED, + .set = "DEV/SHARED", +#ifndef CONFIG_ARM_LPAE + }, { + .mask = L_PTE_MT_MASK, + .val = L_PTE_MT_DEV_NONSHARED, + .set = "DEV/NONSHARED", +#endif + }, { + .mask = L_PTE_MT_MASK, + .val = L_PTE_MT_DEV_WC, + .set = "DEV/WC", + }, { + .mask = L_PTE_MT_MASK, + .val = L_PTE_MT_DEV_CACHED, + .set = "DEV/CACHED", + }, +}; + +static const struct prot_bits section_bits[] = { +#ifndef CONFIG_ARM_LPAE + /* These are approximate */ + { + .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, + .val = 0, + .set = " ro", + }, { + .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, + .val = PMD_SECT_AP_WRITE, + .set = " RW", + }, { + .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, + .val = PMD_SECT_AP_READ, + .set = "USR ro", + }, { + .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, + .val = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, + .set = "USR RW", +#else + { + .mask = PMD_SECT_USER, + .val = PMD_SECT_USER, + .set = "USR", + }, { + .mask = PMD_SECT_RDONLY, + .val = PMD_SECT_RDONLY, + .set = "ro", + .clear = "RW", +#endif + }, { + .mask = PMD_SECT_XN, + .val = PMD_SECT_XN, + .set = "NX", + .clear = "x ", + }, { + .mask = PMD_SECT_S, + .val = PMD_SECT_S, + .set = "SHD", + .clear = " ", + }, +}; + +struct pg_level { + const struct prot_bits *bits; + size_t num; + u64 mask; +}; + +static struct pg_level pg_level[] = { + { + }, { /* pgd */ + }, { /* pud */ + }, { /* pmd */ + .bits = section_bits, + .num = ARRAY_SIZE(section_bits), + }, { /* pte */ + .bits = pte_bits, + .num = ARRAY_SIZE(pte_bits), + }, +}; + +static void dump_prot(struct pg_state *st, const struct prot_bits *bits, size_t num) +{ + unsigned i; + + for (i = 0; i < num; i++, bits++) { + const char *s; + + if ((st->current_prot & bits->mask) == bits->val) + s = bits->set; + else + s = bits->clear; + + if (s) + seq_printf(st->seq, " %s", s); + } +} + +static void note_page(struct pg_state *st, unsigned long addr, unsigned level, u64 val) +{ + static const char units[] = "KMGTPE"; + u64 prot = val & pg_level[level].mask; + + if (addr < USER_PGTABLES_CEILING) + return; + + if (!st->level) { + st->level = level; + st->current_prot = prot; + seq_printf(st->seq, "---[ %s ]---\n", st->marker->name); + } else if (prot != st->current_prot || level != st->level || + addr >= st->marker[1].start_address) { + const char *unit = units; + unsigned long delta; + + if (st->current_prot) { + seq_printf(st->seq, "0x%08lx-0x%08lx ", + st->start_address, addr); + + delta = (addr - st->start_address) >> 10; + while (!(delta & 1023) && unit[1]) { + delta >>= 10; + unit++; + } + seq_printf(st->seq, "%9lu%c", delta, *unit); + if (pg_level[st->level].bits) + dump_prot(st, pg_level[st->level].bits, pg_level[st->level].num); + seq_printf(st->seq, "\n"); + } + + if (addr >= st->marker[1].start_address) { + st->marker++; + seq_printf(st->seq, "---[ %s ]---\n", st->marker->name); + } + st->start_address = addr; + st->current_prot = prot; + st->level = level; + } +} + +static void walk_pte(struct pg_state *st, pmd_t *pmd, unsigned long start) +{ + pte_t *pte = pte_offset_kernel(pmd, 0); + unsigned long addr; + unsigned i; + + for (i = 0; i < PTRS_PER_PTE; i++, pte++) { + addr = start + i * PAGE_SIZE; + note_page(st, addr, 4, pte_val(*pte)); + } +} + +static void walk_pmd(struct pg_state *st, pud_t *pud, unsigned long start) +{ + pmd_t *pmd = pmd_offset(pud, 0); + unsigned long addr; + unsigned i; + + for (i = 0; i < PTRS_PER_PMD; i++, pmd++) { + addr = start + i * PMD_SIZE; + if (pmd_none(*pmd) || pmd_large(*pmd) || !pmd_present(*pmd)) + note_page(st, addr, 3, pmd_val(*pmd)); + else + walk_pte(st, pmd, addr); + } +} + +static void walk_pud(struct pg_state *st, pgd_t *pgd, unsigned long start) +{ + pud_t *pud = pud_offset(pgd, 0); + unsigned long addr; + unsigned i; + + for (i = 0; i < PTRS_PER_PUD; i++, pud++) { + addr = start + i * PUD_SIZE; + if (!pud_none(*pud)) { + walk_pmd(st, pud, addr); + } else { + note_page(st, addr, 2, pud_val(*pud)); + } + } +} + +static void walk_pgd(struct seq_file *m) +{ + pgd_t *pgd = swapper_pg_dir; + struct pg_state st; + unsigned long addr; + unsigned i, pgdoff = USER_PGTABLES_CEILING / PGDIR_SIZE; + + memset(&st, 0, sizeof(st)); + st.seq = m; + st.marker = address_markers; + + pgd += pgdoff; + + for (i = pgdoff; i < PTRS_PER_PGD; i++, pgd++) { + addr = i * PGDIR_SIZE; + if (!pgd_none(*pgd)) { + walk_pud(&st, pgd, addr); + } else { + note_page(&st, addr, 1, pgd_val(*pgd)); + } + } + + note_page(&st, 0, 0, 0); +} + +static int ptdump_show(struct seq_file *m, void *v) +{ + walk_pgd(m); + return 0; +} + +static int ptdump_open(struct inode *inode, struct file *file) +{ + return single_open(file, ptdump_show, NULL); +} + +static const struct file_operations ptdump_fops = { + .open = ptdump_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int ptdump_init(void) +{ + struct dentry *pe; + unsigned i, j; + + for (i = 0; i < ARRAY_SIZE(pg_level); i++) + if (pg_level[i].bits) + for (j = 0; j < pg_level[i].num; j++) + pg_level[i].mask |= pg_level[i].bits[j].mask; + + address_markers[2].start_address = VMALLOC_START; + + pe = debugfs_create_file("kernel_page_tables", 0400, NULL, NULL, + &ptdump_fops); + return pe ? 0 : -ENOMEM; +} +__initcall(ptdump_init); diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 11eb8ad..f57fb33 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -142,58 +142,6 @@ static void __init find_limits(unsigned long *min, unsigned long *max_low, *max_high = bank_pfn_end(&mi->bank[mi->nr_banks - 1]); } -static void __init arm_bootmem_init(unsigned long start_pfn, - unsigned long end_pfn) -{ - struct memblock_region *reg; - unsigned int boot_pages; - phys_addr_t bitmap; - pg_data_t *pgdat; - - /* - * Allocate the bootmem bitmap page. This must be in a region - * of memory which has already been mapped. - */ - boot_pages = bootmem_bootmap_pages(end_pfn - start_pfn); - bitmap = memblock_alloc_base(boot_pages << PAGE_SHIFT, L1_CACHE_BYTES, - __pfn_to_phys(end_pfn)); - - /* - * Initialise the bootmem allocator, handing the - * memory banks over to bootmem. - */ - node_set_online(0); - pgdat = NODE_DATA(0); - init_bootmem_node(pgdat, __phys_to_pfn(bitmap), start_pfn, end_pfn); - - /* Free the lowmem regions from memblock into bootmem. */ - for_each_memblock(memory, reg) { - unsigned long start = memblock_region_memory_base_pfn(reg); - unsigned long end = memblock_region_memory_end_pfn(reg); - - if (end >= end_pfn) - end = end_pfn; - if (start >= end) - break; - - free_bootmem(__pfn_to_phys(start), (end - start) << PAGE_SHIFT); - } - - /* Reserve the lowmem memblock reserved regions in bootmem. */ - for_each_memblock(reserved, reg) { - unsigned long start = memblock_region_reserved_base_pfn(reg); - unsigned long end = memblock_region_reserved_end_pfn(reg); - - if (end >= end_pfn) - end = end_pfn; - if (start >= end) - break; - - reserve_bootmem(__pfn_to_phys(start), - (end - start) << PAGE_SHIFT, BOOTMEM_DEFAULT); - } -} - #ifdef CONFIG_ZONE_DMA phys_addr_t arm_dma_zone_size __read_mostly; @@ -233,7 +181,7 @@ void __init setup_dma_zone(const struct machine_desc *mdesc) #endif } -static void __init arm_bootmem_free(unsigned long min, unsigned long max_low, +static void __init zone_sizes_init(unsigned long min, unsigned long max_low, unsigned long max_high) { unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES]; @@ -381,7 +329,6 @@ void __init arm_memblock_init(struct meminfo *mi, dma_contiguous_reserve(min(arm_dma_limit, arm_lowmem_limit)); arm_memblock_steal_permitted = false; - memblock_allow_resize(); memblock_dump_all(); } @@ -389,12 +336,11 @@ void __init bootmem_init(void) { unsigned long min, max_low, max_high; + memblock_allow_resize(); max_low = max_high = 0; find_limits(&min, &max_low, &max_high); - arm_bootmem_init(min, max_low); - /* * Sparsemem tries to allocate bootmem in memory_present(), * so must be done after the fixed reservations @@ -411,7 +357,7 @@ void __init bootmem_init(void) * the sparse mem_map arrays initialized by sparse_init() * for memmap_init_zone(), otherwise all PFNs are invalid. */ - arm_bootmem_free(min, max_low, max_high); + zone_sizes_init(min, max_low, max_high); /* * This doesn't seem to be used by the Linux memory manager any @@ -584,7 +530,7 @@ void __init mem_init(void) extern u32 itcm_end; #endif - max_mapnr = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map; + set_max_mapnr(pfn_to_page(max_pfn) - mem_map); /* this will put all unused low memory onto the freelists */ free_unused_memmap(&meminfo); diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index f123d6e..f9c32ba 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -392,9 +392,9 @@ __arm_ioremap_exec(phys_addr_t phys_addr, size_t size, bool cached) unsigned int mtype; if (cached) - mtype = MT_MEMORY; + mtype = MT_MEMORY_RWX; else - mtype = MT_MEMORY_NONCACHED; + mtype = MT_MEMORY_RWX_NONCACHED; return __arm_ioremap_caller(phys_addr, size, mtype, __builtin_return_address(0)); diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 580ef2d..4f08c13 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -22,6 +22,7 @@ #include <asm/cputype.h> #include <asm/sections.h> #include <asm/cachetype.h> +#include <asm/sections.h> #include <asm/setup.h> #include <asm/smp_plat.h> #include <asm/tlb.h> @@ -287,36 +288,43 @@ static struct mem_type mem_types[] = { .prot_l1 = PMD_TYPE_TABLE, .domain = DOMAIN_USER, }, - [MT_MEMORY] = { + [MT_MEMORY_RWX] = { .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, .prot_l1 = PMD_TYPE_TABLE, .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, .domain = DOMAIN_KERNEL, }, + [MT_MEMORY_RW] = { + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | + L_PTE_XN, + .prot_l1 = PMD_TYPE_TABLE, + .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, + .domain = DOMAIN_KERNEL, + }, [MT_ROM] = { .prot_sect = PMD_TYPE_SECT, .domain = DOMAIN_KERNEL, }, - [MT_MEMORY_NONCACHED] = { + [MT_MEMORY_RWX_NONCACHED] = { .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_MT_BUFFERABLE, .prot_l1 = PMD_TYPE_TABLE, .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, .domain = DOMAIN_KERNEL, }, - [MT_MEMORY_DTCM] = { + [MT_MEMORY_RW_DTCM] = { .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_XN, .prot_l1 = PMD_TYPE_TABLE, .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, .domain = DOMAIN_KERNEL, }, - [MT_MEMORY_ITCM] = { + [MT_MEMORY_RWX_ITCM] = { .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, .prot_l1 = PMD_TYPE_TABLE, .domain = DOMAIN_KERNEL, }, - [MT_MEMORY_SO] = { + [MT_MEMORY_RW_SO] = { .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_MT_UNCACHED | L_PTE_XN, .prot_l1 = PMD_TYPE_TABLE, @@ -325,7 +333,8 @@ static struct mem_type mem_types[] = { .domain = DOMAIN_KERNEL, }, [MT_MEMORY_DMA_READY] = { - .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | + L_PTE_XN, .prot_l1 = PMD_TYPE_TABLE, .domain = DOMAIN_KERNEL, }, @@ -337,6 +346,44 @@ const struct mem_type *get_mem_type(unsigned int type) } EXPORT_SYMBOL(get_mem_type); +#define PTE_SET_FN(_name, pteop) \ +static int pte_set_##_name(pte_t *ptep, pgtable_t token, unsigned long addr, \ + void *data) \ +{ \ + pte_t pte = pteop(*ptep); \ +\ + set_pte_ext(ptep, pte, 0); \ + return 0; \ +} \ + +#define SET_MEMORY_FN(_name, callback) \ +int set_memory_##_name(unsigned long addr, int numpages) \ +{ \ + unsigned long start = addr; \ + unsigned long size = PAGE_SIZE*numpages; \ + unsigned end = start + size; \ +\ + if (start < MODULES_VADDR || start >= MODULES_END) \ + return -EINVAL;\ +\ + if (end < MODULES_VADDR || end >= MODULES_END) \ + return -EINVAL; \ +\ + apply_to_page_range(&init_mm, start, size, callback, NULL); \ + flush_tlb_kernel_range(start, end); \ + return 0;\ +} + +PTE_SET_FN(ro, pte_wrprotect) +PTE_SET_FN(rw, pte_mkwrite) +PTE_SET_FN(x, pte_mkexec) +PTE_SET_FN(nx, pte_mknexec) + +SET_MEMORY_FN(ro, pte_set_ro) +SET_MEMORY_FN(rw, pte_set_rw) +SET_MEMORY_FN(x, pte_set_x) +SET_MEMORY_FN(nx, pte_set_nx) + /* * Adjust the PMD section entries according to the CPU in use. */ @@ -410,6 +457,9 @@ static void __init build_mem_type_table(void) mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; + + /* Also setup NX memory mapping */ + mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN; } if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { /* @@ -487,11 +537,13 @@ static void __init build_mem_type_table(void) mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; - mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; - mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; + mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S; + mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED; + mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S; + mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED; mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; - mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; - mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; + mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S; + mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED; } } @@ -502,15 +554,15 @@ static void __init build_mem_type_table(void) if (cpu_arch >= CPU_ARCH_ARMv6) { if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { /* Non-cacheable Normal is XCB = 001 */ - mem_types[MT_MEMORY_NONCACHED].prot_sect |= + mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERED; } else { /* For both ARMv6 and non-TEX-remapping ARMv7 */ - mem_types[MT_MEMORY_NONCACHED].prot_sect |= + mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_TEX(1); } } else { - mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; + mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; } #ifdef CONFIG_ARM_LPAE @@ -543,10 +595,12 @@ static void __init build_mem_type_table(void) mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; - mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; - mem_types[MT_MEMORY].prot_pte |= kern_pgprot; + mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd; + mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; + mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; + mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; - mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; + mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; mem_types[MT_ROM].prot_sect |= cp->pmd; switch (cp->pmd) { @@ -1296,6 +1350,8 @@ static void __init kmap_init(void) static void __init map_lowmem(void) { struct memblock_region *reg; + unsigned long kernel_x_start = round_down(__pa(_stext), SECTION_SIZE); + unsigned long kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); /* Map all the lowmem memory banks. */ for_each_memblock(memory, reg) { @@ -1308,12 +1364,40 @@ static void __init map_lowmem(void) if (start >= end) break; - map.pfn = __phys_to_pfn(start); - map.virtual = __phys_to_virt(start); - map.length = end - start; - map.type = MT_MEMORY; + if (end < kernel_x_start || start >= kernel_x_end) { + map.pfn = __phys_to_pfn(start); + map.virtual = __phys_to_virt(start); + map.length = end - start; + map.type = MT_MEMORY_RWX; - create_mapping(&map); + create_mapping(&map); + } else { + /* This better cover the entire kernel */ + if (start < kernel_x_start) { + map.pfn = __phys_to_pfn(start); + map.virtual = __phys_to_virt(start); + map.length = kernel_x_start - start; + map.type = MT_MEMORY_RW; + + create_mapping(&map); + } + + map.pfn = __phys_to_pfn(kernel_x_start); + map.virtual = __phys_to_virt(kernel_x_start); + map.length = kernel_x_end - kernel_x_start; + map.type = MT_MEMORY_RWX; + + create_mapping(&map); + + if (kernel_x_end < end) { + map.pfn = __phys_to_pfn(kernel_x_end); + map.virtual = __phys_to_virt(kernel_x_end); + map.length = end - kernel_x_end; + map.type = MT_MEMORY_RW; + + create_mapping(&map); + } + } } } diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index 1046b37..2493795 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -23,7 +23,7 @@ #define __pgd_alloc() kmalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL) #define __pgd_free(pgd) kfree(pgd) #else -#define __pgd_alloc() (pgd_t *)__get_free_pages(GFP_KERNEL, 2) +#define __pgd_alloc() (pgd_t *)__get_free_pages(GFP_KERNEL | __GFP_REPEAT, 2) #define __pgd_free(pgd) free_pages((unsigned long)pgd, 2) #endif diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index 29606bd7..d70b733 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -54,7 +54,7 @@ static struct clocksource iop_clocksource = { /* * IOP sched_clock() implementation via its clocksource. */ -static u32 notrace iop_read_sched_clock(void) +static u64 notrace iop_read_sched_clock(void) { return 0xffffffffu - read_tcr1(); } @@ -142,7 +142,7 @@ void __init iop_init_time(unsigned long tick_rate) { u32 timer_ctl; - setup_sched_clock(iop_read_sched_clock, 32, tick_rate); + sched_clock_register(iop_read_sched_clock, 32, tick_rate); ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); iop_tick_rate = tick_rate; diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c index d9bc98e..384a776d 100644 --- a/arch/arm/plat-omap/counter_32k.c +++ b/arch/arm/plat-omap/counter_32k.c @@ -38,7 +38,7 @@ */ static void __iomem *sync32k_cnt_reg; -static u32 notrace omap_32k_read_sched_clock(void) +static u64 notrace omap_32k_read_sched_clock(void) { return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0; } @@ -115,7 +115,7 @@ int __init omap_init_clocksource_32k(void __iomem *vbase) return ret; } - setup_sched_clock(omap_32k_read_sched_clock, 32, 32768); + sched_clock_register(omap_32k_read_sched_clock, 32, 32768); register_persistent_clock(NULL, omap_read_persistent_clock); pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n"); diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index c66d163..830ff07 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -22,6 +22,7 @@ #include <linux/platform_data/dma-mv_xor.h> #include <linux/platform_data/usb-ehci-orion.h> #include <mach/bridge-regs.h> +#include <plat/common.h> /* Create a clkdev entry for a given device/clk */ void __init orion_clkdev_add(const char *con_id, const char *dev_id, @@ -256,7 +257,7 @@ static __init void ge_complete( /***************************************************************************** * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data orion_ge00_shared_data; +static struct mv643xx_eth_shared_platform_data orion_ge00_shared_data; static struct resource orion_ge00_shared_resources[] = { { @@ -322,7 +323,7 @@ void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, /***************************************************************************** * GE01 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data orion_ge01_shared_data; +static struct mv643xx_eth_shared_platform_data orion_ge01_shared_data; static struct resource orion_ge01_shared_resources[] = { { @@ -373,7 +374,7 @@ void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, /***************************************************************************** * GE10 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data orion_ge10_shared_data; +static struct mv643xx_eth_shared_platform_data orion_ge10_shared_data; static struct resource orion_ge10_shared_resources[] = { { @@ -422,7 +423,7 @@ void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, /***************************************************************************** * GE11 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data orion_ge11_shared_data; +static struct mv643xx_eth_shared_platform_data orion_ge11_shared_data; static struct resource orion_ge11_shared_resources[] = { { diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 9d2b2ac..261258f 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -17,6 +17,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/sched_clock.h> +#include <plat/time.h> /* * MBus bridge block registers. @@ -60,7 +61,7 @@ static u32 ticks_per_jiffy; * at least 7.5ns (133MHz TCLK). */ -static u32 notrace orion_read_sched_clock(void) +static u64 notrace orion_read_sched_clock(void) { return ~readl(timer_base + TIMER0_VAL_OFF); } @@ -174,7 +175,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) static struct irqaction orion_timer_irq = { .name = "orion_tick", - .flags = IRQF_DISABLED | IRQF_TIMER, + .flags = IRQF_TIMER, .handler = orion_timer_interrupt }; @@ -201,7 +202,7 @@ orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask, /* * Set scale and timer for sched_clock. */ - setup_sched_clock(orion_read_sched_clock, 32, tclk); + sched_clock_register(orion_read_sched_clock, 32, tclk); /* * Setup free-running clocksource timer (interrupts diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c index 79ef102..054fc5a 100644 --- a/arch/arm/plat-pxa/dma.c +++ b/arch/arm/plat-pxa/dma.c @@ -377,7 +377,7 @@ int __init pxa_init_dma(int irq, int num_ch) spin_lock_init(&dma_channels[i].lock); } - ret = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "DMA", NULL); + ret = request_irq(irq, dma_irq_handler, 0, "DMA", NULL); if (ret) { printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n"); kfree(dma_channels); diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 6d95d60..58645a5 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -24,7 +24,6 @@ config PLAT_S5P select S3C_GPIO_TRACK select S5P_GPIO_DRVSTR select SAMSUNG_CLKSRC if !COMMON_CLK - select SAMSUNG_GPIOLIB_4BIT help Base platform code for Samsung's S5P series SoC. @@ -115,13 +114,6 @@ config S5P_GPIO_INT # options for gpio configuration support -config SAMSUNG_GPIOLIB_4BIT - bool - help - GPIOlib file contains the 4 bit modification functions for gpio - configuration. GPIOlib shall be compiled only for S3C64XX and S5P - series of processors. - config S5P_GPIO_DRVSTR bool help diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index 6bc1a8f..ff6063f 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -101,8 +101,8 @@ struct pm_uart_save { /* helper functions to save/restore lists of registers. */ extern void s3c_pm_do_save(struct sleep_save *ptr, int count); -extern void s3c_pm_do_restore(struct sleep_save *ptr, int count); -extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); +extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count); +extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count); #ifdef CONFIG_SAMSUNG_PM extern int s3c_irq_wake(struct irq_data *data, unsigned int state); diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h index 4afc32f..f48dc0a 100644 --- a/arch/arm/plat-samsung/include/plat/uncompress.h +++ b/arch/arm/plat-samsung/include/plat/uncompress.h @@ -145,6 +145,8 @@ static inline void arch_enable_uart_fifo(void) if (!(fifocon & S3C2410_UFCON_RESETBOTH)) break; } + + uart_wr(S3C2410_UFCON, S3C2410_UFCON_FIFOMODE); } } #else diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index d0c2301..e5b0f2c 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -28,8 +28,10 @@ #ifdef CONFIG_SAMSUNG_ATAGS #include <mach/hardware.h> #include <mach/map.h> +#ifndef CONFIG_ARCH_EXYNOS #include <mach/regs-clock.h> #include <mach/regs-irq.h> +#endif #include <mach/irqs.h> #endif @@ -182,7 +184,7 @@ void s3c_pm_do_save(struct sleep_save *ptr, int count) * restore the UARTs state yet */ -void s3c_pm_do_restore(struct sleep_save *ptr, int count) +void s3c_pm_do_restore(const struct sleep_save *ptr, int count) { for (; count > 0; count--, ptr++) { printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", @@ -203,7 +205,7 @@ void s3c_pm_do_restore(struct sleep_save *ptr, int count) * peripherals, as things may be changing! */ -void s3c_pm_do_restore_core(struct sleep_save *ptr, int count) +void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count) { for (; count > 0; count--, ptr++) __raw_writel(ptr->val, ptr->reg); diff --git a/arch/arm/plat-samsung/s5p-irq-eint.c b/arch/arm/plat-samsung/s5p-irq-eint.c index faa6516..ebee4dc 100644 --- a/arch/arm/plat-samsung/s5p-irq-eint.c +++ b/arch/arm/plat-samsung/s5p-irq-eint.c @@ -16,6 +16,7 @@ #include <linux/device.h> #include <linux/gpio.h> #include <linux/irqchip/arm-vic.h> +#include <linux/of.h> #include <plat/regs-irqtype.h> @@ -202,6 +203,9 @@ static int __init s5p_init_irq_eint(void) { int irq; + if (of_have_populated_dt()) + return -ENODEV; + for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) irq_set_chip(irq, &s5p_irq_vic_eint); diff --git a/arch/arm/plat-samsung/s5p-irq-pm.c b/arch/arm/plat-samsung/s5p-irq-pm.c index 7c1e3b7..5914980 100644 --- a/arch/arm/plat-samsung/s5p-irq-pm.c +++ b/arch/arm/plat-samsung/s5p-irq-pm.c @@ -22,7 +22,10 @@ #include <mach/map.h> #include <mach/regs-gpio.h> + +#ifndef CONFIG_ARCH_EXYNOS #include <mach/regs-irq.h> +#endif /* state for IRQs over sleep */ diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c index 39895d8..53feb90 100644 --- a/arch/arm/plat-versatile/platsmp.c +++ b/arch/arm/plat-versatile/platsmp.c @@ -27,8 +27,7 @@ static void write_pen_release(int val) { pen_release = val; smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + sync_cache_w(&pen_release); } static DEFINE_SPINLOCK(boot_lock); diff --git a/arch/arm/plat-versatile/sched-clock.c b/arch/arm/plat-versatile/sched-clock.c index 51b109e..c966ae9 100644 --- a/arch/arm/plat-versatile/sched-clock.c +++ b/arch/arm/plat-versatile/sched-clock.c @@ -26,7 +26,7 @@ static void __iomem *ctr; -static u32 notrace versatile_read_sched_clock(void) +static u64 notrace versatile_read_sched_clock(void) { if (ctr) return readl(ctr); @@ -37,5 +37,5 @@ static u32 notrace versatile_read_sched_clock(void) void __init versatile_sched_clock_init(void __iomem *reg, unsigned long rate) { ctr = reg; - setup_sched_clock(versatile_read_sched_clock, 32, rate); + sched_clock_register(versatile_read_sched_clock, 32, rate); } diff --git a/arch/blackfin/include/asm/clkdev.h b/arch/blackfin/include/asm/clkdev.h index 9053bed..7ac2436 100644 --- a/arch/blackfin/include/asm/clkdev.h +++ b/arch/blackfin/include/asm/clkdev.h @@ -8,7 +8,9 @@ static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) return kzalloc(size, GFP_KERNEL); } +#ifndef CONFIG_COMMON_CLK #define __clk_put(clk) #define __clk_get(clk) ({ 1; }) +#endif #endif diff --git a/arch/mips/include/asm/clkdev.h b/arch/mips/include/asm/clkdev.h index 2624754..1b3ad7b 100644 --- a/arch/mips/include/asm/clkdev.h +++ b/arch/mips/include/asm/clkdev.h @@ -14,8 +14,10 @@ #include <linux/slab.h> +#ifndef CONFIG_COMMON_CLK #define __clk_get(clk) ({ 1; }) #define __clk_put(clk) do { } while (0) +#endif static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) { diff --git a/arch/s390/crypto/des_s390.c b/arch/s390/crypto/des_s390.c index bcca01c..200f2a1 100644 --- a/arch/s390/crypto/des_s390.c +++ b/arch/s390/crypto/des_s390.c @@ -237,9 +237,9 @@ static int des3_setkey(struct crypto_tfm *tfm, const u8 *key, struct s390_des_ctx *ctx = crypto_tfm_ctx(tfm); u32 *flags = &tfm->crt_flags; - if (!(memcmp(key, &key[DES_KEY_SIZE], DES_KEY_SIZE) && - memcmp(&key[DES_KEY_SIZE], &key[DES_KEY_SIZE * 2], - DES_KEY_SIZE)) && + if (!(crypto_memneq(key, &key[DES_KEY_SIZE], DES_KEY_SIZE) && + crypto_memneq(&key[DES_KEY_SIZE], &key[DES_KEY_SIZE * 2], + DES_KEY_SIZE)) && (*flags & CRYPTO_TFM_REQ_WEAK_KEY)) { *flags |= CRYPTO_TFM_RES_WEAK_KEY; return -EINVAL; diff --git a/arch/sh/include/asm/clkdev.h b/arch/sh/include/asm/clkdev.h index 6ba9186..c419014 100644 --- a/arch/sh/include/asm/clkdev.h +++ b/arch/sh/include/asm/clkdev.h @@ -25,7 +25,9 @@ static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) return kzalloc(size, GFP_KERNEL); } +#ifndef CONFIG_COMMON_CLK #define __clk_put(clk) #define __clk_get(clk) ({ 1; }) +#endif #endif /* __CLKDEV_H__ */ diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c index 4df4d4f..3860b0b 100644 --- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c +++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c @@ -61,51 +61,63 @@ static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL, NULL, prio_registers, NULL); static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xf8400000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(88), +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xf8400000, 0x100), + DEFINE_RES_IRQ(88), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xf8410000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(92), +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xf8410000, 0x100), + DEFINE_RES_IRQ(92), }; static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xf8420000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(96), +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xf8420000, 0x100), + DEFINE_RES_IRQ(96), }; static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c index f7f1cf2..63e996f 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c +++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c @@ -199,17 +199,21 @@ static struct platform_device mtu2_2_device = { }; static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xff804000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(220), +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xff804000, 0x100), + DEFINE_RES_IRQ(220), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c index 7b84785..2c68744 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c @@ -178,136 +178,168 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups, mask_registers, prio_registers, NULL); static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xfffe8000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(180), +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xfffe8000, 0x100), + DEFINE_RES_IRQ(180), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xfffe8800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(184), +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xfffe8800, 0x100), + DEFINE_RES_IRQ(184), }; static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xfffe9000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(188), +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xfffe9000, 0x100), + DEFINE_RES_IRQ(188), }; static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xfffe9800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(192), +}; + +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xfffe9800, 0x100), + DEFINE_RES_IRQ(192), }; static struct platform_device scif3_device = { .name = "sh-sci", .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, }; static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xfffea000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(196), +}; + +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xfffea000, 0x100), + DEFINE_RES_IRQ(196), }; static struct platform_device scif4_device = { .name = "sh-sci", .id = 4, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), .dev = { .platform_data = &scif4_platform_data, }, }; static struct plat_sci_port scif5_platform_data = { - .mapbase = 0xfffea800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(200), +}; + +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xfffea800, 0x100), + DEFINE_RES_IRQ(200), }; static struct platform_device scif5_device = { .name = "sh-sci", .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), .dev = { .platform_data = &scif5_platform_data, }, }; static struct plat_sci_port scif6_platform_data = { - .mapbase = 0xfffeb000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(204), +}; + +static struct resource scif6_resources[] = { + DEFINE_RES_MEM(0xfffeb000, 0x100), + DEFINE_RES_IRQ(204), }; static struct platform_device scif6_device = { .name = "sh-sci", .id = 6, + .resource = scif6_resources, + .num_resources = ARRAY_SIZE(scif6_resources), .dev = { .platform_data = &scif6_platform_data, }, }; static struct plat_sci_port scif7_platform_data = { - .mapbase = 0xfffeb800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(208), +}; + +static struct resource scif7_resources[] = { + DEFINE_RES_MEM(0xfffeb800, 0x100), + DEFINE_RES_IRQ(208), }; static struct platform_device scif7_device = { .name = "sh-sci", .id = 7, + .resource = scif7_resources, + .num_resources = ARRAY_SIZE(scif7_resources), .dev = { .platform_data = &scif7_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c index bfc33f6..d55a0f3 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c @@ -174,76 +174,92 @@ static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups, mask_registers, prio_registers, NULL); static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xfffe8000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(192), .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xfffe8000, 0x100), + DEFINE_RES_IRQ(192), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xfffe8800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(196), .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xfffe8800, 0x100), + DEFINE_RES_IRQ(196), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xfffe9000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(200), .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xfffe9000, 0x100), + DEFINE_RES_IRQ(200), +}; + static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xfffe9800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(204), .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xfffe9800, 0x100), + DEFINE_RES_IRQ(204), +}; + static struct platform_device scif3_device = { .name = "sh-sci", .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c index a501074..241e745 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c @@ -134,68 +134,84 @@ static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups, mask_registers, prio_registers, NULL); static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xfffe8000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(240), +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xfffe8000, 0x100), + DEFINE_RES_IRQ(240), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xfffe8800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(244), +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xfffe8800, 0x100), + DEFINE_RES_IRQ(244), }; static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xfffe9000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(248), +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xfffe9000, 0x100), + DEFINE_RES_IRQ(248), }; static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xfffe9800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(252), +}; + +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xfffe9800, 0x100), + DEFINE_RES_IRQ(252), }; static struct platform_device scif3_device = { .name = "sh-sci", .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c index ce5c1b5..ad5b0f4 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c @@ -226,152 +226,208 @@ static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups, mask_registers, prio_registers, NULL); static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xfffe8000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 233, 234, 235, 232 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xfffe8000, 0x100), + DEFINE_RES_IRQ(233), + DEFINE_RES_IRQ(234), + DEFINE_RES_IRQ(235), + DEFINE_RES_IRQ(232), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xfffe8800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 237, 238, 239, 236 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xfffe8800, 0x100), + DEFINE_RES_IRQ(237), + DEFINE_RES_IRQ(238), + DEFINE_RES_IRQ(239), + DEFINE_RES_IRQ(236), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xfffe9000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 241, 242, 243, 240 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xfffe9000, 0x100), + DEFINE_RES_IRQ(241), + DEFINE_RES_IRQ(242), + DEFINE_RES_IRQ(243), + DEFINE_RES_IRQ(240), +}; + static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xfffe9800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 245, 246, 247, 244 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xfffe9800, 0x100), + DEFINE_RES_IRQ(245), + DEFINE_RES_IRQ(246), + DEFINE_RES_IRQ(247), + DEFINE_RES_IRQ(244), +}; + static struct platform_device scif3_device = { .name = "sh-sci", .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, }; static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xfffea000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 249, 250, 251, 248 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xfffea000, 0x100), + DEFINE_RES_IRQ(249), + DEFINE_RES_IRQ(250), + DEFINE_RES_IRQ(251), + DEFINE_RES_IRQ(248), +}; + static struct platform_device scif4_device = { .name = "sh-sci", .id = 4, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), .dev = { .platform_data = &scif4_platform_data, }, }; static struct plat_sci_port scif5_platform_data = { - .mapbase = 0xfffea800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 253, 254, 255, 252 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xfffea800, 0x100), + DEFINE_RES_IRQ(253), + DEFINE_RES_IRQ(254), + DEFINE_RES_IRQ(255), + DEFINE_RES_IRQ(252), +}; + static struct platform_device scif5_device = { .name = "sh-sci", .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), .dev = { .platform_data = &scif5_platform_data, }, }; static struct plat_sci_port scif6_platform_data = { - .mapbase = 0xfffeb000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 257, 258, 259, 256 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif6_resources[] = { + DEFINE_RES_MEM(0xfffeb000, 0x100), + DEFINE_RES_IRQ(257), + DEFINE_RES_IRQ(258), + DEFINE_RES_IRQ(259), + DEFINE_RES_IRQ(256), +}; + static struct platform_device scif6_device = { .name = "sh-sci", .id = 6, + .resource = scif6_resources, + .num_resources = ARRAY_SIZE(scif6_resources), .dev = { .platform_data = &scif6_platform_data, }, }; static struct plat_sci_port scif7_platform_data = { - .mapbase = 0xfffeb800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 261, 262, 263, 260 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif7_resources[] = { + DEFINE_RES_MEM(0xfffeb800, 0x100), + DEFINE_RES_IRQ(261), + DEFINE_RES_IRQ(262), + DEFINE_RES_IRQ(263), + DEFINE_RES_IRQ(260), +}; + static struct platform_device scif7_device = { .name = "sh-sci", .id = 7, + .resource = scif7_resources, + .num_resources = ARRAY_SIZE(scif7_resources), .dev = { .platform_data = &scif7_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c index e82ae9d..3995119 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c @@ -248,152 +248,208 @@ static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups, mask_registers, prio_registers, NULL); static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xe8007000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 259, 260, 261, 258 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xe8007000, 0x100), + DEFINE_RES_IRQ(259), + DEFINE_RES_IRQ(260), + DEFINE_RES_IRQ(261), + DEFINE_RES_IRQ(258), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xe8007800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 263, 264, 265, 262 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xe8007800, 0x100), + DEFINE_RES_IRQ(263), + DEFINE_RES_IRQ(264), + DEFINE_RES_IRQ(265), + DEFINE_RES_IRQ(262), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xe8008000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 267, 268, 269, 266 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xe8008000, 0x100), + DEFINE_RES_IRQ(267), + DEFINE_RES_IRQ(268), + DEFINE_RES_IRQ(269), + DEFINE_RES_IRQ(266), +}; + static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xe8008800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 271, 272, 273, 270 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xe8008800, 0x100), + DEFINE_RES_IRQ(271), + DEFINE_RES_IRQ(272), + DEFINE_RES_IRQ(273), + DEFINE_RES_IRQ(270), +}; + static struct platform_device scif3_device = { .name = "sh-sci", .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, }; static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xe8009000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 275, 276, 277, 274 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xe8009000, 0x100), + DEFINE_RES_IRQ(275), + DEFINE_RES_IRQ(276), + DEFINE_RES_IRQ(277), + DEFINE_RES_IRQ(274), +}; + static struct platform_device scif4_device = { .name = "sh-sci", .id = 4, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), .dev = { .platform_data = &scif4_platform_data, }, }; static struct plat_sci_port scif5_platform_data = { - .mapbase = 0xe8009800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 279, 280, 281, 278 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xe8009800, 0x100), + DEFINE_RES_IRQ(279), + DEFINE_RES_IRQ(280), + DEFINE_RES_IRQ(281), + DEFINE_RES_IRQ(278), +}; + static struct platform_device scif5_device = { .name = "sh-sci", .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), .dev = { .platform_data = &scif5_platform_data, }, }; static struct plat_sci_port scif6_platform_data = { - .mapbase = 0xe800a000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 283, 284, 285, 282 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif6_resources[] = { + DEFINE_RES_MEM(0xe800a000, 0x100), + DEFINE_RES_IRQ(283), + DEFINE_RES_IRQ(284), + DEFINE_RES_IRQ(285), + DEFINE_RES_IRQ(282), +}; + static struct platform_device scif6_device = { .name = "sh-sci", .id = 6, + .resource = scif6_resources, + .num_resources = ARRAY_SIZE(scif6_resources), .dev = { .platform_data = &scif6_platform_data, }, }; static struct plat_sci_port scif7_platform_data = { - .mapbase = 0xe800a800, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 287, 288, 289, 286 }, .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif7_resources[] = { + DEFINE_RES_MEM(0xe800a800, 0x100), + DEFINE_RES_IRQ(287), + DEFINE_RES_IRQ(288), + DEFINE_RES_IRQ(289), + DEFINE_RES_IRQ(286), +}; + static struct platform_device scif7_device = { .name = "sh-sci", .id = 7, + .resource = scif7_resources, + .num_resources = ARRAY_SIZE(scif7_resources), .dev = { .platform_data = &scif7_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c index 03e4c96..c76b254 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c @@ -70,39 +70,47 @@ static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL, NULL, prio_registers, NULL); static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xa4410000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, - .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), .ops = &sh770x_sci_port_ops, .regtype = SCIx_SH7705_SCIF_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xa4410000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x900)), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xa4400000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, - .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), .ops = &sh770x_sci_port_ops, .regtype = SCIx_SH7705_SCIF_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xa4400000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x880)), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c index ba26cd9..ff1465c 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c @@ -109,20 +109,24 @@ static struct platform_device rtc_device = { }; static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xfffffe80, .port_reg = 0xa4000136, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_TE | SCSCR_RE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCI, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)), .ops = &sh770x_sci_port_ops, .regshift = 1, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xfffffe80, 0x100), + DEFINE_RES_IRQ(evt2irq(0x4e0)), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, @@ -131,19 +135,23 @@ static struct platform_device scif0_device = { defined(CONFIG_CPU_SUBTYPE_SH7707) || \ defined(CONFIG_CPU_SUBTYPE_SH7709) static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xa4000150, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_TE | SCSCR_RE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), .ops = &sh770x_sci_port_ops, .regtype = SCIx_SH3_SCIF_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xa4000150, 0x100), + DEFINE_RES_IRQ(evt2irq(0x900)), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, @@ -152,20 +160,24 @@ static struct platform_device scif1_device = { #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ defined(CONFIG_CPU_SUBTYPE_SH7709) static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xa4000140, .port_reg = SCIx_NOT_SUPPORTED, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_TE | SCSCR_RE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_IRDA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), .ops = &sh770x_sci_port_ops, .regshift = 1, }; +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xa4000140, 0x100), + DEFINE_RES_IRQ(evt2irq(0x880)), +}; + static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c index 93c9c5e..e2ce936 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c @@ -98,36 +98,44 @@ static struct platform_device rtc_device = { }; static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xa4400000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | SCSCR_CKE1 | SCSCR_CKE0, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xa4400000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x880)), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xa4410000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | SCSCR_CKE1 | SCSCR_CKE0, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xa4410000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x900)), }; static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c index 42d991f..1d5729d 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c @@ -52,38 +52,46 @@ static struct platform_device rtc_device = { }; static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xa4430000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), .ops = &sh7720_sci_port_ops, .regtype = SCIx_SH7705_SCIF_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xa4430000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc00)), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xa4438000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), .ops = &sh7720_sci_port_ops, .regtype = SCIx_SH7705_SCIF_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xa4438000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc20)), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c index 2a5320a..a8bd778 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c @@ -17,20 +17,24 @@ #include <linux/io.h> static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xffe80000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { evt2irq(0x700), - evt2irq(0x720), - evt2irq(0x760), - evt2irq(0x740) }, +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe80000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x700)), + DEFINE_RES_IRQ(evt2irq(0x720)), + DEFINE_RES_IRQ(evt2irq(0x760)), + DEFINE_RES_IRQ(evt2irq(0x740)), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c index 04a4551..a447a24 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c @@ -38,36 +38,44 @@ static struct platform_device rtc_device = { }; static struct plat_sci_port sci_platform_data = { - .mapbase = 0xffe00000, .port_reg = 0xffe0001C, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_TE | SCSCR_RE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCI, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)), .regshift = 2, }; +static struct resource sci_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x4e0)), +}; + static struct platform_device sci_device = { .name = "sh-sci", .id = 0, + .resource = sci_resources, + .num_resources = ARRAY_SIZE(sci_resources), .dev = { .platform_data = &sci_platform_data, }, }; static struct plat_sci_port scif_platform_data = { - .mapbase = 0xffe80000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), +}; + +static struct resource scif_resources[] = { + DEFINE_RES_MEM(0xffe80000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x700)), }; static struct platform_device scif_device = { .name = "sh-sci", .id = 1, + .resource = scif_resources, + .num_resources = ARRAY_SIZE(scif_resources), .dev = { .platform_data = &scif_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c index 98e075a..1abd9fb 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c @@ -128,83 +128,99 @@ static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups, mask_registers, prio_registers, NULL); static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xfe600000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { evt2irq(0x880), - evt2irq(0x8a0), - evt2irq(0x8e0), - evt2irq(0x8c0) }, .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xfe600000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x880)), + DEFINE_RES_IRQ(evt2irq(0x8a0)), + DEFINE_RES_IRQ(evt2irq(0x8e0)), + DEFINE_RES_IRQ(evt2irq(0x8c0)), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xfe610000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, - .irqs = { evt2irq(0xb00), - evt2irq(0xb20), - evt2irq(0xb60), - evt2irq(0xb40) }, .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xfe610000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xb00)), + DEFINE_RES_IRQ(evt2irq(0xb20)), + DEFINE_RES_IRQ(evt2irq(0xb60)), + DEFINE_RES_IRQ(evt2irq(0xb40)), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xfe620000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { evt2irq(0xb80), - evt2irq(0xba0), - evt2irq(0xbe0), - evt2irq(0xbc0) }, .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xfe620000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xb80)), + DEFINE_RES_IRQ(evt2irq(0xba0)), + DEFINE_RES_IRQ(evt2irq(0xbe0)), + DEFINE_RES_IRQ(evt2irq(0xbc0)), +}; + static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xfe480000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCI, - .irqs = { evt2irq(0xc00), - evt2irq(0xc20), - evt2irq(0xc40), }, .regshift = 2, }; +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xfe480000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc00)), + DEFINE_RES_IRQ(evt2irq(0xc20)), + DEFINE_RES_IRQ(evt2irq(0xc40)), +}; + static struct platform_device scif3_device = { .name = "sh-sci", .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c index b91ea83..245d192 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c @@ -18,68 +18,84 @@ /* Serial */ static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xffe00000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc00)), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xffe10000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe10000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc20)), }; static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xffe20000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffe20000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc40)), }; static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xffe30000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc60)), +}; + +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xffe30000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc60)), }; static struct platform_device scif3_device = { .name = "sh-sci", .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c index 0bd09d5..6f56cbd 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c @@ -20,18 +20,22 @@ #include <asm/clock.h> static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xffe00000, .port_reg = 0xa405013e, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc00)), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index 6a868b0..5a94efc 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c @@ -179,57 +179,69 @@ struct platform_device dma_device = { /* Serial */ static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xffe00000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), .ops = &sh7722_sci_port_ops, .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc00)), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xffe10000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), .ops = &sh7722_sci_port_ops, .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe10000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc20)), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xffe20000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), .ops = &sh7722_sci_port_ops, .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffe20000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc40)), +}; + static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index 28d6fd8..3c5eb09 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c @@ -23,111 +23,138 @@ /* Serial */ static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xffe00000, .port_reg = 0xa4050160, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc00)), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xffe10000, .port_reg = SCIx_NOT_SUPPORTED, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe10000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc20)), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xffe20000, .port_reg = SCIx_NOT_SUPPORTED, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffe20000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc40)), +}; + static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xa4e30000, .flags = UPF_BOOT_AUTOCONF, .port_reg = SCIx_NOT_SUPPORTED, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_3, + .sampling_rate = 8, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), +}; + +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xa4e30000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x900)), }; static struct platform_device scif3_device = { .name = "sh-sci", .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, }; static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xa4e40000, .port_reg = SCIx_NOT_SUPPORTED, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_3, + .sampling_rate = 8, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), +}; + +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xa4e40000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xd00)), }; static struct platform_device scif4_device = { .name = "sh-sci", .id = 4, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), .dev = { .platform_data = &scif4_platform_data, }, }; static struct plat_sci_port scif5_platform_data = { - .mapbase = 0xa4e50000, .port_reg = SCIx_NOT_SUPPORTED, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_3, + .sampling_rate = 8, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), +}; + +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xa4e50000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xfa0)), }; static struct platform_device scif5_device = { .name = "sh-sci", .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), .dev = { .platform_data = &scif5_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 26b74c2..60ebbc6 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c @@ -290,111 +290,138 @@ static struct platform_device dma1_device = { /* Serial */ static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xffe00000, .port_reg = SCIx_NOT_SUPPORTED, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc00)), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xffe10000, .port_reg = SCIx_NOT_SUPPORTED, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe10000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc20)), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xffe20000, .port_reg = SCIx_NOT_SUPPORTED, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffe20000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xc40)), +}; + static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xa4e30000, .port_reg = SCIx_NOT_SUPPORTED, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_3, + .sampling_rate = 8, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), +}; + +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xa4e30000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x900)), }; static struct platform_device scif3_device = { .name = "sh-sci", .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, }; static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xa4e40000, .port_reg = SCIx_NOT_SUPPORTED, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_3, + .sampling_rate = 8, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), +}; + +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xa4e40000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xd00)), }; static struct platform_device scif4_device = { .name = "sh-sci", .id = 4, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), .dev = { .platform_data = &scif4_platform_data, }, }; static struct plat_sci_port scif5_platform_data = { - .mapbase = 0xa4e50000, .port_reg = SCIx_NOT_SUPPORTED, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE, - .scbrr_algo_id = SCBRR_ALGO_3, + .sampling_rate = 8, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), +}; + +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xa4e50000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xfa0)), }; static struct platform_device scif5_device = { .name = "sh-sci", .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), .dev = { .platform_data = &scif5_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c index f799971d..dad4ed1 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c @@ -25,108 +25,132 @@ /* SCIF */ static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xFFE40000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x8C0)), .regtype = SCIx_SH4_SCIF_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe40000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x8c0)), +}; + static struct platform_device scif0_device = { .name = "sh-sci", - .id = 0, + .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xFFE41000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x8E0)), .regtype = SCIx_SH4_SCIF_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe41000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x8e0)), +}; + static struct platform_device scif1_device = { .name = "sh-sci", - .id = 1, + .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xFFE42000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), .regtype = SCIx_SH4_SCIF_REGTYPE, }; +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffe42000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x900)), +}; + static struct platform_device scif2_device = { .name = "sh-sci", - .id = 2, + .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xFFE43000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x920)), .regtype = SCIx_SH4_SCIF_REGTYPE, }; +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xffe43000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x920)), +}; + static struct platform_device scif3_device = { .name = "sh-sci", - .id = 3, + .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, }; static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xFFE44000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x940)), .regtype = SCIx_SH4_SCIF_REGTYPE, }; +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xffe44000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x940)), +}; + static struct platform_device scif4_device = { .name = "sh-sci", - .id = 4, + .id = 4, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), .dev = { .platform_data = &scif4_platform_data, }, }; static struct plat_sci_port scif5_platform_data = { - .mapbase = 0xFFE43000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x960)), .regtype = SCIx_SH4_SCIF_REGTYPE, }; +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xffe43000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x960)), +}; + static struct platform_device scif5_device = { .name = "sh-sci", - .id = 5, + .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), .dev = { .platform_data = &scif5_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c index 9079a0f..e43e5db 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c @@ -24,51 +24,63 @@ #include <cpu/sh7757.h> static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xfe4b0000, /* SCIF2 */ .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */ + DEFINE_RES_IRQ(evt2irq(0x700)), }; static struct platform_device scif2_device = { .name = "sh-sci", .id = 0, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xfe4c0000, /* SCIF3 */ .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), +}; + +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */ + DEFINE_RES_IRQ(evt2irq(0xb80)), }; static struct platform_device scif3_device = { .name = "sh-sci", .id = 1, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, }; static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xfe4d0000, /* SCIF4 */ .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)), +}; + +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */ + DEFINE_RES_IRQ(evt2irq(0xf00)), }; static struct platform_device scif4_device = { .name = "sh-sci", .id = 2, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), .dev = { .platform_data = &scif4_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c index 1686aca..5eebbd7 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c @@ -19,54 +19,66 @@ #include <linux/usb/ohci_pdriver.h> static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xffe00000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x700)), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xffe08000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe08000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xb80)), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xffe10000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xf00)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffe10000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xf00)), +}; + static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c index 256ea7a..e1ba8cb7 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c @@ -16,170 +16,210 @@ #include <linux/io.h> static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xff923000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)), +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xff923000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x9a0)), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xff924000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)), +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xff924000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x9c0)), }; static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xff925000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)), +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xff925000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x9e0)), }; static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xff926000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xa00)), +}; + +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xff926000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xa00)), }; static struct platform_device scif3_device = { .name = "sh-sci", .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, }; static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xff927000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xa20)), +}; + +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xff927000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xa20)), }; static struct platform_device scif4_device = { .name = "sh-sci", .id = 4, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), .dev = { .platform_data = &scif4_platform_data, }, }; static struct plat_sci_port scif5_platform_data = { - .mapbase = 0xff928000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xa40)), +}; + +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xff928000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xa40)), }; static struct platform_device scif5_device = { .name = "sh-sci", .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), .dev = { .platform_data = &scif5_platform_data, }, }; static struct plat_sci_port scif6_platform_data = { - .mapbase = 0xff929000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xa60)), +}; + +static struct resource scif6_resources[] = { + DEFINE_RES_MEM(0xff929000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xa60)), }; static struct platform_device scif6_device = { .name = "sh-sci", .id = 6, + .resource = scif6_resources, + .num_resources = ARRAY_SIZE(scif6_resources), .dev = { .platform_data = &scif6_platform_data, }, }; static struct plat_sci_port scif7_platform_data = { - .mapbase = 0xff92a000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xa80)), +}; + +static struct resource scif7_resources[] = { + DEFINE_RES_MEM(0xff92a000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xa80)), }; static struct platform_device scif7_device = { .name = "sh-sci", .id = 7, + .resource = scif7_resources, + .num_resources = ARRAY_SIZE(scif7_resources), .dev = { .platform_data = &scif7_platform_data, }, }; static struct plat_sci_port scif8_platform_data = { - .mapbase = 0xff92b000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xaa0)), +}; + +static struct resource scif8_resources[] = { + DEFINE_RES_MEM(0xff92b000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xaa0)), }; static struct platform_device scif8_device = { .name = "sh-sci", .id = 8, + .resource = scif8_resources, + .num_resources = ARRAY_SIZE(scif8_resources), .dev = { .platform_data = &scif8_platform_data, }, }; static struct plat_sci_port scif9_platform_data = { - .mapbase = 0xff92c000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xac0)), +}; + +static struct resource scif9_resources[] = { + DEFINE_RES_MEM(0xff92c000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xac0)), }; static struct platform_device scif9_device = { .name = "sh-sci", .id = 9, + .resource = scif9_resources, + .num_resources = ARRAY_SIZE(scif9_resources), .dev = { .platform_data = &scif9_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c index de45b704..668e54b 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c @@ -18,36 +18,44 @@ #include <cpu/dma-register.h> static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xffe00000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffe00000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x700)), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xffe10000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffe10000, 0x100), + DEFINE_RES_IRQ(evt2irq(0xb80)), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, @@ -409,9 +417,7 @@ void __init plat_early_device_setup(void) { if (mach_is_sh2007()) { scif0_platform_data.scscr &= ~SCSCR_CKE1; - scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2; scif1_platform_data.scscr &= ~SCSCR_CKE1; - scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2; } early_platform_add_devices(sh7780_early_devices, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index 0968ecb..4aa6791 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c @@ -20,108 +20,132 @@ #include <cpu/dma-register.h> static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xffea0000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffea0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x700)), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xffeb0000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffeb0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x780)), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xffec0000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x980)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffec0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x980)), +}; + static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xffed0000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xffed0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x9a0)), +}; + static struct platform_device scif3_device = { .name = "sh-sci", .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, }; static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xffee0000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xffee0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x9c0)), +}; + static struct platform_device scif4_device = { .name = "sh-sci", .id = 4, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), .dev = { .platform_data = &scif4_platform_data, }, }; static struct plat_sci_port scif5_platform_data = { - .mapbase = 0xffef0000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xffef0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x9e0)), +}; + static struct platform_device scif5_device = { .name = "sh-sci", .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), .dev = { .platform_data = &scif5_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index ab52d4d4..5d619a5 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c @@ -28,21 +28,25 @@ #include <asm/mmzone.h> static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xffea0000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = { evt2irq(0x700), - evt2irq(0x720), - evt2irq(0x760), - evt2irq(0x740) }, .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffea0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x700)), + DEFINE_RES_IRQ(evt2irq(0x720)), + DEFINE_RES_IRQ(evt2irq(0x760)), + DEFINE_RES_IRQ(evt2irq(0x740)), +}; + static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, @@ -52,90 +56,119 @@ static struct platform_device scif0_device = { * The rest of these all have multiplexed IRQs */ static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xffeb0000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffeb0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x780)), +}; + +static struct resource scif1_demux_resources[] = { + DEFINE_RES_MEM(0xffeb0000, 0x100), + /* Placeholders, see sh7786_devices_setup() */ + DEFINE_RES_IRQ(0), + DEFINE_RES_IRQ(0), + DEFINE_RES_IRQ(0), + DEFINE_RES_IRQ(0), +}; + static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xffec0000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x840)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffec0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x840)), +}; + static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, }; static struct plat_sci_port scif3_platform_data = { - .mapbase = 0xffed0000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x860)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif3_resources[] = { + DEFINE_RES_MEM(0xffed0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x860)), +}; + static struct platform_device scif3_device = { .name = "sh-sci", .id = 3, + .resource = scif3_resources, + .num_resources = ARRAY_SIZE(scif3_resources), .dev = { .platform_data = &scif3_platform_data, }, }; static struct plat_sci_port scif4_platform_data = { - .mapbase = 0xffee0000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif4_resources[] = { + DEFINE_RES_MEM(0xffee0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x880)), +}; + static struct platform_device scif4_device = { .name = "sh-sci", .id = 4, + .resource = scif4_resources, + .num_resources = ARRAY_SIZE(scif4_resources), .dev = { .platform_data = &scif4_platform_data, }, }; static struct plat_sci_port scif5_platform_data = { - .mapbase = 0xffef0000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, - .scbrr_algo_id = SCBRR_ALGO_1, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x8a0)), .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; +static struct resource scif5_resources[] = { + DEFINE_RES_MEM(0xffef0000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x8a0)), +}; + static struct platform_device scif5_device = { .name = "sh-sci", .id = 5, + .resource = scif5_resources, + .num_resources = ARRAY_SIZE(scif5_resources), .dev = { .platform_data = &scif5_platform_data, }, @@ -1037,13 +1070,16 @@ static int __init sh7786_devices_setup(void) */ irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1); if (irq > 0) { - scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq; - scif1_platform_data.irqs[SCIx_ERI_IRQ] = + scif1_demux_resources[1].start = intc_irq_lookup(sh7786_intc_desc.name, ERI1); - scif1_platform_data.irqs[SCIx_BRI_IRQ] = - intc_irq_lookup(sh7786_intc_desc.name, BRI1); - scif1_platform_data.irqs[SCIx_RXI_IRQ] = + scif1_demux_resources[2].start = intc_irq_lookup(sh7786_intc_desc.name, RXI1); + scif1_demux_resources[3].start = irq; + scif1_demux_resources[4].start = + intc_irq_lookup(sh7786_intc_desc.name, BRI1); + + scif1_device.resource = scif1_demux_resources; + scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources); } ret = platform_add_devices(sh7786_early_devices, diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index 688f7ed..0856bcb 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c @@ -28,60 +28,72 @@ * all rather than adding infrastructure to hack around it. */ static struct plat_sci_port scif0_platform_data = { - .mapbase = 0xffc30000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { evt2irq(0x700), - evt2irq(0x720), - evt2irq(0x760), - evt2irq(0x740) }, +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(0xffc30000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x700)), + DEFINE_RES_IRQ(evt2irq(0x720)), + DEFINE_RES_IRQ(evt2irq(0x760)), + DEFINE_RES_IRQ(evt2irq(0x740)), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { - .mapbase = 0xffc40000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { evt2irq(0x780), - evt2irq(0x7a0), - evt2irq(0x7e0), - evt2irq(0x7c0) }, +}; + +static struct resource scif1_resources[] = { + DEFINE_RES_MEM(0xffc40000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x780)), + DEFINE_RES_IRQ(evt2irq(0x7a0)), + DEFINE_RES_IRQ(evt2irq(0x7e0)), + DEFINE_RES_IRQ(evt2irq(0x7c0)), }; static struct platform_device scif1_device = { .name = "sh-sci", .id = 1, + .resource = scif1_resources, + .num_resources = ARRAY_SIZE(scif1_resources), .dev = { .platform_data = &scif1_platform_data, }, }; static struct plat_sci_port scif2_platform_data = { - .mapbase = 0xffc60000, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { evt2irq(0x880), - evt2irq(0x8a0), - evt2irq(0x8e0), - evt2irq(0x8c0) }, +}; + +static struct resource scif2_resources[] = { + DEFINE_RES_MEM(0xffc60000, 0x100), + DEFINE_RES_IRQ(evt2irq(0x880)), + DEFINE_RES_IRQ(evt2irq(0x8a0)), + DEFINE_RES_IRQ(evt2irq(0x8e0)), + DEFINE_RES_IRQ(evt2irq(0x8c0)), }; static struct platform_device scif2_device = { .name = "sh-sci", .id = 2, + .resource = scif2_resources, + .num_resources = ARRAY_SIZE(scif2_resources), .dev = { .platform_data = &scif2_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c index 18419f1..14d6821 100644 --- a/arch/sh/kernel/cpu/sh5/setup-sh5.c +++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c @@ -17,17 +17,23 @@ #include <asm/addrspace.h> static struct plat_sci_port scif0_platform_data = { - .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000, .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, - .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = { 39, 40, 42, 0 }, +}; + +static struct resource scif0_resources[] = { + DEFINE_RES_MEM(PHYS_PERIPHERAL_BLOCK + 0x01030000, 0x100), + DEFINE_RES_IRQ(39), + DEFINE_RES_IRQ(40), + DEFINE_RES_IRQ(42), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, + .resource = scif0_resources, + .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile index e0fc24d..6ba54d6 100644 --- a/arch/x86/crypto/Makefile +++ b/arch/x86/crypto/Makefile @@ -76,6 +76,7 @@ ifeq ($(avx2_supported),yes) endif aesni-intel-y := aesni-intel_asm.o aesni-intel_glue.o fpu.o +aesni-intel-$(CONFIG_64BIT) += aesni-intel_avx-x86_64.o ghash-clmulni-intel-y := ghash-clmulni-intel_asm.o ghash-clmulni-intel_glue.o sha1-ssse3-y := sha1_ssse3_asm.o sha1_ssse3_glue.o crc32c-intel-y := crc32c-intel_glue.o diff --git a/arch/x86/crypto/aesni-intel_avx-x86_64.S b/arch/x86/crypto/aesni-intel_avx-x86_64.S new file mode 100644 index 0000000..522ab68 --- /dev/null +++ b/arch/x86/crypto/aesni-intel_avx-x86_64.S @@ -0,0 +1,2811 @@ +######################################################################## +# Copyright (c) 2013, Intel Corporation +# +# This software is available to you under a choice of one of two +# licenses. You may choose to be licensed under the terms of the GNU +# General Public License (GPL) Version 2, available from the file +# COPYING in the main directory of this source tree, or the +# OpenIB.org BSD license below: +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the +# distribution. +# +# * Neither the name of the Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# +# THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION ""AS IS"" AND ANY +# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES# LOSS OF USE, DATA, OR +# PROFITS# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +######################################################################## +## +## Authors: +## Erdinc Ozturk <erdinc.ozturk@intel.com> +## Vinodh Gopal <vinodh.gopal@intel.com> +## James Guilford <james.guilford@intel.com> +## Tim Chen <tim.c.chen@linux.intel.com> +## +## References: +## This code was derived and highly optimized from the code described in paper: +## Vinodh Gopal et. al. Optimized Galois-Counter-Mode Implementation +## on Intel Architecture Processors. August, 2010 +## The details of the implementation is explained in: +## Erdinc Ozturk et. al. Enabling High-Performance Galois-Counter-Mode +## on Intel Architecture Processors. October, 2012. +## +## Assumptions: +## +## +## +## iv: +## 0 1 2 3 +## 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 +## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +## | Salt (From the SA) | +## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +## | Initialization Vector | +## | (This is the sequence number from IPSec header) | +## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +## | 0x1 | +## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +## +## +## +## AAD: +## AAD padded to 128 bits with 0 +## for example, assume AAD is a u32 vector +## +## if AAD is 8 bytes: +## AAD[3] = {A0, A1}# +## padded AAD in xmm register = {A1 A0 0 0} +## +## 0 1 2 3 +## 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 +## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +## | SPI (A1) | +## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +## | 32-bit Sequence Number (A0) | +## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +## | 0x0 | +## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +## +## AAD Format with 32-bit Sequence Number +## +## if AAD is 12 bytes: +## AAD[3] = {A0, A1, A2}# +## padded AAD in xmm register = {A2 A1 A0 0} +## +## 0 1 2 3 +## 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 +## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +## | SPI (A2) | +## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +## | 64-bit Extended Sequence Number {A1,A0} | +## | | +## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +## | 0x0 | +## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +## +## AAD Format with 64-bit Extended Sequence Number +## +## +## aadLen: +## from the definition of the spec, aadLen can only be 8 or 12 bytes. +## The code additionally supports aadLen of length 16 bytes. +## +## TLen: +## from the definition of the spec, TLen can only be 8, 12 or 16 bytes. +## +## poly = x^128 + x^127 + x^126 + x^121 + 1 +## throughout the code, one tab and two tab indentations are used. one tab is +## for GHASH part, two tabs is for AES part. +## + +#include <linux/linkage.h> +#include <asm/inst.h> + +.data +.align 16 + +POLY: .octa 0xC2000000000000000000000000000001 +POLY2: .octa 0xC20000000000000000000001C2000000 +TWOONE: .octa 0x00000001000000000000000000000001 + +# order of these constants should not change. +# more specifically, ALL_F should follow SHIFT_MASK, and ZERO should follow ALL_F + +SHUF_MASK: .octa 0x000102030405060708090A0B0C0D0E0F +SHIFT_MASK: .octa 0x0f0e0d0c0b0a09080706050403020100 +ALL_F: .octa 0xffffffffffffffffffffffffffffffff +ZERO: .octa 0x00000000000000000000000000000000 +ONE: .octa 0x00000000000000000000000000000001 +ONEf: .octa 0x01000000000000000000000000000000 + +.text + + +##define the fields of the gcm aes context +#{ +# u8 expanded_keys[16*11] store expanded keys +# u8 shifted_hkey_1[16] store HashKey <<1 mod poly here +# u8 shifted_hkey_2[16] store HashKey^2 <<1 mod poly here +# u8 shifted_hkey_3[16] store HashKey^3 <<1 mod poly here +# u8 shifted_hkey_4[16] store HashKey^4 <<1 mod poly here +# u8 shifted_hkey_5[16] store HashKey^5 <<1 mod poly here +# u8 shifted_hkey_6[16] store HashKey^6 <<1 mod poly here +# u8 shifted_hkey_7[16] store HashKey^7 <<1 mod poly here +# u8 shifted_hkey_8[16] store HashKey^8 <<1 mod poly here +# u8 shifted_hkey_1_k[16] store XOR HashKey <<1 mod poly here (for Karatsuba purposes) +# u8 shifted_hkey_2_k[16] store XOR HashKey^2 <<1 mod poly here (for Karatsuba purposes) +# u8 shifted_hkey_3_k[16] store XOR HashKey^3 <<1 mod poly here (for Karatsuba purposes) +# u8 shifted_hkey_4_k[16] store XOR HashKey^4 <<1 mod poly here (for Karatsuba purposes) +# u8 shifted_hkey_5_k[16] store XOR HashKey^5 <<1 mod poly here (for Karatsuba purposes) +# u8 shifted_hkey_6_k[16] store XOR HashKey^6 <<1 mod poly here (for Karatsuba purposes) +# u8 shifted_hkey_7_k[16] store XOR HashKey^7 <<1 mod poly here (for Karatsuba purposes) +# u8 shifted_hkey_8_k[16] store XOR HashKey^8 <<1 mod poly here (for Karatsuba purposes) +#} gcm_ctx# + +HashKey = 16*11 # store HashKey <<1 mod poly here +HashKey_2 = 16*12 # store HashKey^2 <<1 mod poly here +HashKey_3 = 16*13 # store HashKey^3 <<1 mod poly here +HashKey_4 = 16*14 # store HashKey^4 <<1 mod poly here +HashKey_5 = 16*15 # store HashKey^5 <<1 mod poly here +HashKey_6 = 16*16 # store HashKey^6 <<1 mod poly here +HashKey_7 = 16*17 # store HashKey^7 <<1 mod poly here +HashKey_8 = 16*18 # store HashKey^8 <<1 mod poly here +HashKey_k = 16*19 # store XOR of HashKey <<1 mod poly here (for Karatsuba purposes) +HashKey_2_k = 16*20 # store XOR of HashKey^2 <<1 mod poly here (for Karatsuba purposes) +HashKey_3_k = 16*21 # store XOR of HashKey^3 <<1 mod poly here (for Karatsuba purposes) +HashKey_4_k = 16*22 # store XOR of HashKey^4 <<1 mod poly here (for Karatsuba purposes) +HashKey_5_k = 16*23 # store XOR of HashKey^5 <<1 mod poly here (for Karatsuba purposes) +HashKey_6_k = 16*24 # store XOR of HashKey^6 <<1 mod poly here (for Karatsuba purposes) +HashKey_7_k = 16*25 # store XOR of HashKey^7 <<1 mod poly here (for Karatsuba purposes) +HashKey_8_k = 16*26 # store XOR of HashKey^8 <<1 mod poly here (for Karatsuba purposes) + +#define arg1 %rdi +#define arg2 %rsi +#define arg3 %rdx +#define arg4 %rcx +#define arg5 %r8 +#define arg6 %r9 +#define arg7 STACK_OFFSET+8*1(%r14) +#define arg8 STACK_OFFSET+8*2(%r14) +#define arg9 STACK_OFFSET+8*3(%r14) + +i = 0 +j = 0 + +out_order = 0 +in_order = 1 +DEC = 0 +ENC = 1 + +.macro define_reg r n +reg_\r = %xmm\n +.endm + +.macro setreg +.altmacro +define_reg i %i +define_reg j %j +.noaltmacro +.endm + +# need to push 4 registers into stack to maintain +STACK_OFFSET = 8*4 + +TMP1 = 16*0 # Temporary storage for AAD +TMP2 = 16*1 # Temporary storage for AES State 2 (State 1 is stored in an XMM register) +TMP3 = 16*2 # Temporary storage for AES State 3 +TMP4 = 16*3 # Temporary storage for AES State 4 +TMP5 = 16*4 # Temporary storage for AES State 5 +TMP6 = 16*5 # Temporary storage for AES State 6 +TMP7 = 16*6 # Temporary storage for AES State 7 +TMP8 = 16*7 # Temporary storage for AES State 8 + +VARIABLE_OFFSET = 16*8 + +################################ +# Utility Macros +################################ + +# Encryption of a single block +.macro ENCRYPT_SINGLE_BLOCK XMM0 + vpxor (arg1), \XMM0, \XMM0 + i = 1 + setreg +.rep 9 + vaesenc 16*i(arg1), \XMM0, \XMM0 + i = (i+1) + setreg +.endr + vaesenclast 16*10(arg1), \XMM0, \XMM0 +.endm + +#ifdef CONFIG_AS_AVX +############################################################################### +# GHASH_MUL MACRO to implement: Data*HashKey mod (128,127,126,121,0) +# Input: A and B (128-bits each, bit-reflected) +# Output: C = A*B*x mod poly, (i.e. >>1 ) +# To compute GH = GH*HashKey mod poly, give HK = HashKey<<1 mod poly as input +# GH = GH * HK * x mod poly which is equivalent to GH*HashKey mod poly. +############################################################################### +.macro GHASH_MUL_AVX GH HK T1 T2 T3 T4 T5 + + vpshufd $0b01001110, \GH, \T2 + vpshufd $0b01001110, \HK, \T3 + vpxor \GH , \T2, \T2 # T2 = (a1+a0) + vpxor \HK , \T3, \T3 # T3 = (b1+b0) + + vpclmulqdq $0x11, \HK, \GH, \T1 # T1 = a1*b1 + vpclmulqdq $0x00, \HK, \GH, \GH # GH = a0*b0 + vpclmulqdq $0x00, \T3, \T2, \T2 # T2 = (a1+a0)*(b1+b0) + vpxor \GH, \T2,\T2 + vpxor \T1, \T2,\T2 # T2 = a0*b1+a1*b0 + + vpslldq $8, \T2,\T3 # shift-L T3 2 DWs + vpsrldq $8, \T2,\T2 # shift-R T2 2 DWs + vpxor \T3, \GH, \GH + vpxor \T2, \T1, \T1 # <T1:GH> = GH x HK + + #first phase of the reduction + vpslld $31, \GH, \T2 # packed right shifting << 31 + vpslld $30, \GH, \T3 # packed right shifting shift << 30 + vpslld $25, \GH, \T4 # packed right shifting shift << 25 + + vpxor \T3, \T2, \T2 # xor the shifted versions + vpxor \T4, \T2, \T2 + + vpsrldq $4, \T2, \T5 # shift-R T5 1 DW + + vpslldq $12, \T2, \T2 # shift-L T2 3 DWs + vpxor \T2, \GH, \GH # first phase of the reduction complete + + #second phase of the reduction + + vpsrld $1,\GH, \T2 # packed left shifting >> 1 + vpsrld $2,\GH, \T3 # packed left shifting >> 2 + vpsrld $7,\GH, \T4 # packed left shifting >> 7 + vpxor \T3, \T2, \T2 # xor the shifted versions + vpxor \T4, \T2, \T2 + + vpxor \T5, \T2, \T2 + vpxor \T2, \GH, \GH + vpxor \T1, \GH, \GH # the result is in GH + + +.endm + +.macro PRECOMPUTE_AVX HK T1 T2 T3 T4 T5 T6 + + # Haskey_i_k holds XORed values of the low and high parts of the Haskey_i + vmovdqa \HK, \T5 + + vpshufd $0b01001110, \T5, \T1 + vpxor \T5, \T1, \T1 + vmovdqa \T1, HashKey_k(arg1) + + GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^2<<1 mod poly + vmovdqa \T5, HashKey_2(arg1) # [HashKey_2] = HashKey^2<<1 mod poly + vpshufd $0b01001110, \T5, \T1 + vpxor \T5, \T1, \T1 + vmovdqa \T1, HashKey_2_k(arg1) + + GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^3<<1 mod poly + vmovdqa \T5, HashKey_3(arg1) + vpshufd $0b01001110, \T5, \T1 + vpxor \T5, \T1, \T1 + vmovdqa \T1, HashKey_3_k(arg1) + + GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^4<<1 mod poly + vmovdqa \T5, HashKey_4(arg1) + vpshufd $0b01001110, \T5, \T1 + vpxor \T5, \T1, \T1 + vmovdqa \T1, HashKey_4_k(arg1) + + GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^5<<1 mod poly + vmovdqa \T5, HashKey_5(arg1) + vpshufd $0b01001110, \T5, \T1 + vpxor \T5, \T1, \T1 + vmovdqa \T1, HashKey_5_k(arg1) + + GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^6<<1 mod poly + vmovdqa \T5, HashKey_6(arg1) + vpshufd $0b01001110, \T5, \T1 + vpxor \T5, \T1, \T1 + vmovdqa \T1, HashKey_6_k(arg1) + + GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^7<<1 mod poly + vmovdqa \T5, HashKey_7(arg1) + vpshufd $0b01001110, \T5, \T1 + vpxor \T5, \T1, \T1 + vmovdqa \T1, HashKey_7_k(arg1) + + GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^8<<1 mod poly + vmovdqa \T5, HashKey_8(arg1) + vpshufd $0b01001110, \T5, \T1 + vpxor \T5, \T1, \T1 + vmovdqa \T1, HashKey_8_k(arg1) + +.endm + +## if a = number of total plaintext bytes +## b = floor(a/16) +## num_initial_blocks = b mod 4# +## encrypt the initial num_initial_blocks blocks and apply ghash on the ciphertext +## r10, r11, r12, rax are clobbered +## arg1, arg2, arg3, r14 are used as a pointer only, not modified + +.macro INITIAL_BLOCKS_AVX num_initial_blocks T1 T2 T3 T4 T5 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 T6 T_key ENC_DEC + i = (8-\num_initial_blocks) + setreg + + mov arg6, %r10 # r10 = AAD + mov arg7, %r12 # r12 = aadLen + + + mov %r12, %r11 + + vpxor reg_i, reg_i, reg_i +_get_AAD_loop\@: + vmovd (%r10), \T1 + vpslldq $12, \T1, \T1 + vpsrldq $4, reg_i, reg_i + vpxor \T1, reg_i, reg_i + + add $4, %r10 + sub $4, %r12 + jg _get_AAD_loop\@ + + + cmp $16, %r11 + je _get_AAD_loop2_done\@ + mov $16, %r12 + +_get_AAD_loop2\@: + vpsrldq $4, reg_i, reg_i + sub $4, %r12 + cmp %r11, %r12 + jg _get_AAD_loop2\@ + +_get_AAD_loop2_done\@: + + #byte-reflect the AAD data + vpshufb SHUF_MASK(%rip), reg_i, reg_i + + # initialize the data pointer offset as zero + xor %r11, %r11 + + # start AES for num_initial_blocks blocks + mov arg5, %rax # rax = *Y0 + vmovdqu (%rax), \CTR # CTR = Y0 + vpshufb SHUF_MASK(%rip), \CTR, \CTR + + + i = (9-\num_initial_blocks) + setreg +.rep \num_initial_blocks + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, reg_i + vpshufb SHUF_MASK(%rip), reg_i, reg_i # perform a 16Byte swap + i = (i+1) + setreg +.endr + + vmovdqa (arg1), \T_key + i = (9-\num_initial_blocks) + setreg +.rep \num_initial_blocks + vpxor \T_key, reg_i, reg_i + i = (i+1) + setreg +.endr + + j = 1 + setreg +.rep 9 + vmovdqa 16*j(arg1), \T_key + i = (9-\num_initial_blocks) + setreg +.rep \num_initial_blocks + vaesenc \T_key, reg_i, reg_i + i = (i+1) + setreg +.endr + + j = (j+1) + setreg +.endr + + + vmovdqa 16*10(arg1), \T_key + i = (9-\num_initial_blocks) + setreg +.rep \num_initial_blocks + vaesenclast \T_key, reg_i, reg_i + i = (i+1) + setreg +.endr + + i = (9-\num_initial_blocks) + setreg +.rep \num_initial_blocks + vmovdqu (arg3, %r11), \T1 + vpxor \T1, reg_i, reg_i + vmovdqu reg_i, (arg2 , %r11) # write back ciphertext for num_initial_blocks blocks + add $16, %r11 +.if \ENC_DEC == DEC + vmovdqa \T1, reg_i +.endif + vpshufb SHUF_MASK(%rip), reg_i, reg_i # prepare ciphertext for GHASH computations + i = (i+1) + setreg +.endr + + + i = (8-\num_initial_blocks) + j = (9-\num_initial_blocks) + setreg + GHASH_MUL_AVX reg_i, \T2, \T1, \T3, \T4, \T5, \T6 + +.rep \num_initial_blocks + vpxor reg_i, reg_j, reg_j + GHASH_MUL_AVX reg_j, \T2, \T1, \T3, \T4, \T5, \T6 # apply GHASH on num_initial_blocks blocks + i = (i+1) + j = (j+1) + setreg +.endr + # XMM8 has the combined result here + + vmovdqa \XMM8, TMP1(%rsp) + vmovdqa \XMM8, \T3 + + cmp $128, %r13 + jl _initial_blocks_done\@ # no need for precomputed constants + +############################################################################### +# Haskey_i_k holds XORed values of the low and high parts of the Haskey_i + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM1 + vpshufb SHUF_MASK(%rip), \XMM1, \XMM1 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM2 + vpshufb SHUF_MASK(%rip), \XMM2, \XMM2 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM3 + vpshufb SHUF_MASK(%rip), \XMM3, \XMM3 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM4 + vpshufb SHUF_MASK(%rip), \XMM4, \XMM4 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM5 + vpshufb SHUF_MASK(%rip), \XMM5, \XMM5 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM6 + vpshufb SHUF_MASK(%rip), \XMM6, \XMM6 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM7 + vpshufb SHUF_MASK(%rip), \XMM7, \XMM7 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM8 + vpshufb SHUF_MASK(%rip), \XMM8, \XMM8 # perform a 16Byte swap + + vmovdqa (arg1), \T_key + vpxor \T_key, \XMM1, \XMM1 + vpxor \T_key, \XMM2, \XMM2 + vpxor \T_key, \XMM3, \XMM3 + vpxor \T_key, \XMM4, \XMM4 + vpxor \T_key, \XMM5, \XMM5 + vpxor \T_key, \XMM6, \XMM6 + vpxor \T_key, \XMM7, \XMM7 + vpxor \T_key, \XMM8, \XMM8 + + i = 1 + setreg +.rep 9 # do 9 rounds + vmovdqa 16*i(arg1), \T_key + vaesenc \T_key, \XMM1, \XMM1 + vaesenc \T_key, \XMM2, \XMM2 + vaesenc \T_key, \XMM3, \XMM3 + vaesenc \T_key, \XMM4, \XMM4 + vaesenc \T_key, \XMM5, \XMM5 + vaesenc \T_key, \XMM6, \XMM6 + vaesenc \T_key, \XMM7, \XMM7 + vaesenc \T_key, \XMM8, \XMM8 + i = (i+1) + setreg +.endr + + + vmovdqa 16*i(arg1), \T_key + vaesenclast \T_key, \XMM1, \XMM1 + vaesenclast \T_key, \XMM2, \XMM2 + vaesenclast \T_key, \XMM3, \XMM3 + vaesenclast \T_key, \XMM4, \XMM4 + vaesenclast \T_key, \XMM5, \XMM5 + vaesenclast \T_key, \XMM6, \XMM6 + vaesenclast \T_key, \XMM7, \XMM7 + vaesenclast \T_key, \XMM8, \XMM8 + + vmovdqu (arg3, %r11), \T1 + vpxor \T1, \XMM1, \XMM1 + vmovdqu \XMM1, (arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM1 + .endif + + vmovdqu 16*1(arg3, %r11), \T1 + vpxor \T1, \XMM2, \XMM2 + vmovdqu \XMM2, 16*1(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM2 + .endif + + vmovdqu 16*2(arg3, %r11), \T1 + vpxor \T1, \XMM3, \XMM3 + vmovdqu \XMM3, 16*2(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM3 + .endif + + vmovdqu 16*3(arg3, %r11), \T1 + vpxor \T1, \XMM4, \XMM4 + vmovdqu \XMM4, 16*3(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM4 + .endif + + vmovdqu 16*4(arg3, %r11), \T1 + vpxor \T1, \XMM5, \XMM5 + vmovdqu \XMM5, 16*4(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM5 + .endif + + vmovdqu 16*5(arg3, %r11), \T1 + vpxor \T1, \XMM6, \XMM6 + vmovdqu \XMM6, 16*5(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM6 + .endif + + vmovdqu 16*6(arg3, %r11), \T1 + vpxor \T1, \XMM7, \XMM7 + vmovdqu \XMM7, 16*6(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM7 + .endif + + vmovdqu 16*7(arg3, %r11), \T1 + vpxor \T1, \XMM8, \XMM8 + vmovdqu \XMM8, 16*7(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM8 + .endif + + add $128, %r11 + + vpshufb SHUF_MASK(%rip), \XMM1, \XMM1 # perform a 16Byte swap + vpxor TMP1(%rsp), \XMM1, \XMM1 # combine GHASHed value with the corresponding ciphertext + vpshufb SHUF_MASK(%rip), \XMM2, \XMM2 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM3, \XMM3 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM4, \XMM4 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM5, \XMM5 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM6, \XMM6 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM7, \XMM7 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM8, \XMM8 # perform a 16Byte swap + +############################################################################### + +_initial_blocks_done\@: + +.endm + +# encrypt 8 blocks at a time +# ghash the 8 previously encrypted ciphertext blocks +# arg1, arg2, arg3 are used as pointers only, not modified +# r11 is the data offset value +.macro GHASH_8_ENCRYPT_8_PARALLEL_AVX T1 T2 T3 T4 T5 T6 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 T7 loop_idx ENC_DEC + + vmovdqa \XMM1, \T2 + vmovdqa \XMM2, TMP2(%rsp) + vmovdqa \XMM3, TMP3(%rsp) + vmovdqa \XMM4, TMP4(%rsp) + vmovdqa \XMM5, TMP5(%rsp) + vmovdqa \XMM6, TMP6(%rsp) + vmovdqa \XMM7, TMP7(%rsp) + vmovdqa \XMM8, TMP8(%rsp) + +.if \loop_idx == in_order + vpaddd ONE(%rip), \CTR, \XMM1 # INCR CNT + vpaddd ONE(%rip), \XMM1, \XMM2 + vpaddd ONE(%rip), \XMM2, \XMM3 + vpaddd ONE(%rip), \XMM3, \XMM4 + vpaddd ONE(%rip), \XMM4, \XMM5 + vpaddd ONE(%rip), \XMM5, \XMM6 + vpaddd ONE(%rip), \XMM6, \XMM7 + vpaddd ONE(%rip), \XMM7, \XMM8 + vmovdqa \XMM8, \CTR + + vpshufb SHUF_MASK(%rip), \XMM1, \XMM1 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM2, \XMM2 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM3, \XMM3 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM4, \XMM4 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM5, \XMM5 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM6, \XMM6 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM7, \XMM7 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM8, \XMM8 # perform a 16Byte swap +.else + vpaddd ONEf(%rip), \CTR, \XMM1 # INCR CNT + vpaddd ONEf(%rip), \XMM1, \XMM2 + vpaddd ONEf(%rip), \XMM2, \XMM3 + vpaddd ONEf(%rip), \XMM3, \XMM4 + vpaddd ONEf(%rip), \XMM4, \XMM5 + vpaddd ONEf(%rip), \XMM5, \XMM6 + vpaddd ONEf(%rip), \XMM6, \XMM7 + vpaddd ONEf(%rip), \XMM7, \XMM8 + vmovdqa \XMM8, \CTR +.endif + + + ####################################################################### + + vmovdqu (arg1), \T1 + vpxor \T1, \XMM1, \XMM1 + vpxor \T1, \XMM2, \XMM2 + vpxor \T1, \XMM3, \XMM3 + vpxor \T1, \XMM4, \XMM4 + vpxor \T1, \XMM5, \XMM5 + vpxor \T1, \XMM6, \XMM6 + vpxor \T1, \XMM7, \XMM7 + vpxor \T1, \XMM8, \XMM8 + + ####################################################################### + + + + + + vmovdqu 16*1(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + vmovdqu 16*2(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + + ####################################################################### + + vmovdqa HashKey_8(arg1), \T5 + vpclmulqdq $0x11, \T5, \T2, \T4 # T4 = a1*b1 + vpclmulqdq $0x00, \T5, \T2, \T7 # T7 = a0*b0 + + vpshufd $0b01001110, \T2, \T6 + vpxor \T2, \T6, \T6 + + vmovdqa HashKey_8_k(arg1), \T5 + vpclmulqdq $0x00, \T5, \T6, \T6 + + vmovdqu 16*3(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + vmovdqa TMP2(%rsp), \T1 + vmovdqa HashKey_7(arg1), \T5 + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T4 + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpshufd $0b01001110, \T1, \T3 + vpxor \T1, \T3, \T3 + vmovdqa HashKey_7_k(arg1), \T5 + vpclmulqdq $0x10, \T5, \T3, \T3 + vpxor \T3, \T6, \T6 + + vmovdqu 16*4(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + ####################################################################### + + vmovdqa TMP3(%rsp), \T1 + vmovdqa HashKey_6(arg1), \T5 + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T4 + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpshufd $0b01001110, \T1, \T3 + vpxor \T1, \T3, \T3 + vmovdqa HashKey_6_k(arg1), \T5 + vpclmulqdq $0x10, \T5, \T3, \T3 + vpxor \T3, \T6, \T6 + + vmovdqu 16*5(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + vmovdqa TMP4(%rsp), \T1 + vmovdqa HashKey_5(arg1), \T5 + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T4 + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpshufd $0b01001110, \T1, \T3 + vpxor \T1, \T3, \T3 + vmovdqa HashKey_5_k(arg1), \T5 + vpclmulqdq $0x10, \T5, \T3, \T3 + vpxor \T3, \T6, \T6 + + vmovdqu 16*6(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + + vmovdqa TMP5(%rsp), \T1 + vmovdqa HashKey_4(arg1), \T5 + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T4 + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpshufd $0b01001110, \T1, \T3 + vpxor \T1, \T3, \T3 + vmovdqa HashKey_4_k(arg1), \T5 + vpclmulqdq $0x10, \T5, \T3, \T3 + vpxor \T3, \T6, \T6 + + vmovdqu 16*7(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + vmovdqa TMP6(%rsp), \T1 + vmovdqa HashKey_3(arg1), \T5 + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T4 + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpshufd $0b01001110, \T1, \T3 + vpxor \T1, \T3, \T3 + vmovdqa HashKey_3_k(arg1), \T5 + vpclmulqdq $0x10, \T5, \T3, \T3 + vpxor \T3, \T6, \T6 + + + vmovdqu 16*8(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + vmovdqa TMP7(%rsp), \T1 + vmovdqa HashKey_2(arg1), \T5 + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T4 + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpshufd $0b01001110, \T1, \T3 + vpxor \T1, \T3, \T3 + vmovdqa HashKey_2_k(arg1), \T5 + vpclmulqdq $0x10, \T5, \T3, \T3 + vpxor \T3, \T6, \T6 + + ####################################################################### + + vmovdqu 16*9(arg1), \T5 + vaesenc \T5, \XMM1, \XMM1 + vaesenc \T5, \XMM2, \XMM2 + vaesenc \T5, \XMM3, \XMM3 + vaesenc \T5, \XMM4, \XMM4 + vaesenc \T5, \XMM5, \XMM5 + vaesenc \T5, \XMM6, \XMM6 + vaesenc \T5, \XMM7, \XMM7 + vaesenc \T5, \XMM8, \XMM8 + + vmovdqa TMP8(%rsp), \T1 + vmovdqa HashKey(arg1), \T5 + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T4 + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpshufd $0b01001110, \T1, \T3 + vpxor \T1, \T3, \T3 + vmovdqa HashKey_k(arg1), \T5 + vpclmulqdq $0x10, \T5, \T3, \T3 + vpxor \T3, \T6, \T6 + + vpxor \T4, \T6, \T6 + vpxor \T7, \T6, \T6 + + vmovdqu 16*10(arg1), \T5 + + i = 0 + j = 1 + setreg +.rep 8 + vpxor 16*i(arg3, %r11), \T5, \T2 + .if \ENC_DEC == ENC + vaesenclast \T2, reg_j, reg_j + .else + vaesenclast \T2, reg_j, \T3 + vmovdqu 16*i(arg3, %r11), reg_j + vmovdqu \T3, 16*i(arg2, %r11) + .endif + i = (i+1) + j = (j+1) + setreg +.endr + ####################################################################### + + + vpslldq $8, \T6, \T3 # shift-L T3 2 DWs + vpsrldq $8, \T6, \T6 # shift-R T2 2 DWs + vpxor \T3, \T7, \T7 + vpxor \T4, \T6, \T6 # accumulate the results in T6:T7 + + + + ####################################################################### + #first phase of the reduction + ####################################################################### + vpslld $31, \T7, \T2 # packed right shifting << 31 + vpslld $30, \T7, \T3 # packed right shifting shift << 30 + vpslld $25, \T7, \T4 # packed right shifting shift << 25 + + vpxor \T3, \T2, \T2 # xor the shifted versions + vpxor \T4, \T2, \T2 + + vpsrldq $4, \T2, \T1 # shift-R T1 1 DW + + vpslldq $12, \T2, \T2 # shift-L T2 3 DWs + vpxor \T2, \T7, \T7 # first phase of the reduction complete + ####################################################################### + .if \ENC_DEC == ENC + vmovdqu \XMM1, 16*0(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM2, 16*1(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM3, 16*2(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM4, 16*3(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM5, 16*4(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM6, 16*5(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM7, 16*6(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM8, 16*7(arg2,%r11) # Write to the Ciphertext buffer + .endif + + ####################################################################### + #second phase of the reduction + vpsrld $1, \T7, \T2 # packed left shifting >> 1 + vpsrld $2, \T7, \T3 # packed left shifting >> 2 + vpsrld $7, \T7, \T4 # packed left shifting >> 7 + vpxor \T3, \T2, \T2 # xor the shifted versions + vpxor \T4, \T2, \T2 + + vpxor \T1, \T2, \T2 + vpxor \T2, \T7, \T7 + vpxor \T7, \T6, \T6 # the result is in T6 + ####################################################################### + + vpshufb SHUF_MASK(%rip), \XMM1, \XMM1 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM2, \XMM2 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM3, \XMM3 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM4, \XMM4 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM5, \XMM5 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM6, \XMM6 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM7, \XMM7 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM8, \XMM8 # perform a 16Byte swap + + + vpxor \T6, \XMM1, \XMM1 + + + +.endm + + +# GHASH the last 4 ciphertext blocks. +.macro GHASH_LAST_8_AVX T1 T2 T3 T4 T5 T6 T7 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 + + ## Karatsuba Method + + + vpshufd $0b01001110, \XMM1, \T2 + vpxor \XMM1, \T2, \T2 + vmovdqa HashKey_8(arg1), \T5 + vpclmulqdq $0x11, \T5, \XMM1, \T6 + vpclmulqdq $0x00, \T5, \XMM1, \T7 + + vmovdqa HashKey_8_k(arg1), \T3 + vpclmulqdq $0x00, \T3, \T2, \XMM1 + + ###################### + + vpshufd $0b01001110, \XMM2, \T2 + vpxor \XMM2, \T2, \T2 + vmovdqa HashKey_7(arg1), \T5 + vpclmulqdq $0x11, \T5, \XMM2, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM2, \T4 + vpxor \T4, \T7, \T7 + + vmovdqa HashKey_7_k(arg1), \T3 + vpclmulqdq $0x00, \T3, \T2, \T2 + vpxor \T2, \XMM1, \XMM1 + + ###################### + + vpshufd $0b01001110, \XMM3, \T2 + vpxor \XMM3, \T2, \T2 + vmovdqa HashKey_6(arg1), \T5 + vpclmulqdq $0x11, \T5, \XMM3, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM3, \T4 + vpxor \T4, \T7, \T7 + + vmovdqa HashKey_6_k(arg1), \T3 + vpclmulqdq $0x00, \T3, \T2, \T2 + vpxor \T2, \XMM1, \XMM1 + + ###################### + + vpshufd $0b01001110, \XMM4, \T2 + vpxor \XMM4, \T2, \T2 + vmovdqa HashKey_5(arg1), \T5 + vpclmulqdq $0x11, \T5, \XMM4, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM4, \T4 + vpxor \T4, \T7, \T7 + + vmovdqa HashKey_5_k(arg1), \T3 + vpclmulqdq $0x00, \T3, \T2, \T2 + vpxor \T2, \XMM1, \XMM1 + + ###################### + + vpshufd $0b01001110, \XMM5, \T2 + vpxor \XMM5, \T2, \T2 + vmovdqa HashKey_4(arg1), \T5 + vpclmulqdq $0x11, \T5, \XMM5, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM5, \T4 + vpxor \T4, \T7, \T7 + + vmovdqa HashKey_4_k(arg1), \T3 + vpclmulqdq $0x00, \T3, \T2, \T2 + vpxor \T2, \XMM1, \XMM1 + + ###################### + + vpshufd $0b01001110, \XMM6, \T2 + vpxor \XMM6, \T2, \T2 + vmovdqa HashKey_3(arg1), \T5 + vpclmulqdq $0x11, \T5, \XMM6, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM6, \T4 + vpxor \T4, \T7, \T7 + + vmovdqa HashKey_3_k(arg1), \T3 + vpclmulqdq $0x00, \T3, \T2, \T2 + vpxor \T2, \XMM1, \XMM1 + + ###################### + + vpshufd $0b01001110, \XMM7, \T2 + vpxor \XMM7, \T2, \T2 + vmovdqa HashKey_2(arg1), \T5 + vpclmulqdq $0x11, \T5, \XMM7, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM7, \T4 + vpxor \T4, \T7, \T7 + + vmovdqa HashKey_2_k(arg1), \T3 + vpclmulqdq $0x00, \T3, \T2, \T2 + vpxor \T2, \XMM1, \XMM1 + + ###################### + + vpshufd $0b01001110, \XMM8, \T2 + vpxor \XMM8, \T2, \T2 + vmovdqa HashKey(arg1), \T5 + vpclmulqdq $0x11, \T5, \XMM8, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM8, \T4 + vpxor \T4, \T7, \T7 + + vmovdqa HashKey_k(arg1), \T3 + vpclmulqdq $0x00, \T3, \T2, \T2 + + vpxor \T2, \XMM1, \XMM1 + vpxor \T6, \XMM1, \XMM1 + vpxor \T7, \XMM1, \T2 + + + + + vpslldq $8, \T2, \T4 + vpsrldq $8, \T2, \T2 + + vpxor \T4, \T7, \T7 + vpxor \T2, \T6, \T6 # <T6:T7> holds the result of + # the accumulated carry-less multiplications + + ####################################################################### + #first phase of the reduction + vpslld $31, \T7, \T2 # packed right shifting << 31 + vpslld $30, \T7, \T3 # packed right shifting shift << 30 + vpslld $25, \T7, \T4 # packed right shifting shift << 25 + + vpxor \T3, \T2, \T2 # xor the shifted versions + vpxor \T4, \T2, \T2 + + vpsrldq $4, \T2, \T1 # shift-R T1 1 DW + + vpslldq $12, \T2, \T2 # shift-L T2 3 DWs + vpxor \T2, \T7, \T7 # first phase of the reduction complete + ####################################################################### + + + #second phase of the reduction + vpsrld $1, \T7, \T2 # packed left shifting >> 1 + vpsrld $2, \T7, \T3 # packed left shifting >> 2 + vpsrld $7, \T7, \T4 # packed left shifting >> 7 + vpxor \T3, \T2, \T2 # xor the shifted versions + vpxor \T4, \T2, \T2 + + vpxor \T1, \T2, \T2 + vpxor \T2, \T7, \T7 + vpxor \T7, \T6, \T6 # the result is in T6 + +.endm + + +# combined for GCM encrypt and decrypt functions +# clobbering all xmm registers +# clobbering r10, r11, r12, r13, r14, r15 +.macro GCM_ENC_DEC_AVX ENC_DEC + + #the number of pushes must equal STACK_OFFSET + push %r12 + push %r13 + push %r14 + push %r15 + + mov %rsp, %r14 + + + + + sub $VARIABLE_OFFSET, %rsp + and $~63, %rsp # align rsp to 64 bytes + + + vmovdqu HashKey(arg1), %xmm13 # xmm13 = HashKey + + mov arg4, %r13 # save the number of bytes of plaintext/ciphertext + and $-16, %r13 # r13 = r13 - (r13 mod 16) + + mov %r13, %r12 + shr $4, %r12 + and $7, %r12 + jz _initial_num_blocks_is_0\@ + + cmp $7, %r12 + je _initial_num_blocks_is_7\@ + cmp $6, %r12 + je _initial_num_blocks_is_6\@ + cmp $5, %r12 + je _initial_num_blocks_is_5\@ + cmp $4, %r12 + je _initial_num_blocks_is_4\@ + cmp $3, %r12 + je _initial_num_blocks_is_3\@ + cmp $2, %r12 + je _initial_num_blocks_is_2\@ + + jmp _initial_num_blocks_is_1\@ + +_initial_num_blocks_is_7\@: + INITIAL_BLOCKS_AVX 7, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*7, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_6\@: + INITIAL_BLOCKS_AVX 6, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*6, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_5\@: + INITIAL_BLOCKS_AVX 5, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*5, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_4\@: + INITIAL_BLOCKS_AVX 4, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*4, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_3\@: + INITIAL_BLOCKS_AVX 3, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*3, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_2\@: + INITIAL_BLOCKS_AVX 2, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*2, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_1\@: + INITIAL_BLOCKS_AVX 1, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*1, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_0\@: + INITIAL_BLOCKS_AVX 0, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + + +_initial_blocks_encrypted\@: + cmp $0, %r13 + je _zero_cipher_left\@ + + sub $128, %r13 + je _eight_cipher_left\@ + + + + + vmovd %xmm9, %r15d + and $255, %r15d + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + + +_encrypt_by_8_new\@: + cmp $(255-8), %r15d + jg _encrypt_by_8\@ + + + + add $8, %r15b + GHASH_8_ENCRYPT_8_PARALLEL_AVX %xmm0, %xmm10, %xmm11, %xmm12, %xmm13, %xmm14, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm15, out_order, \ENC_DEC + add $128, %r11 + sub $128, %r13 + jne _encrypt_by_8_new\@ + + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + jmp _eight_cipher_left\@ + +_encrypt_by_8\@: + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + add $8, %r15b + GHASH_8_ENCRYPT_8_PARALLEL_AVX %xmm0, %xmm10, %xmm11, %xmm12, %xmm13, %xmm14, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm15, in_order, \ENC_DEC + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + add $128, %r11 + sub $128, %r13 + jne _encrypt_by_8_new\@ + + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + + + + +_eight_cipher_left\@: + GHASH_LAST_8_AVX %xmm0, %xmm10, %xmm11, %xmm12, %xmm13, %xmm14, %xmm15, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8 + + +_zero_cipher_left\@: + cmp $16, arg4 + jl _only_less_than_16\@ + + mov arg4, %r13 + and $15, %r13 # r13 = (arg4 mod 16) + + je _multiple_of_16_bytes\@ + + # handle the last <16 Byte block seperately + + + vpaddd ONE(%rip), %xmm9, %xmm9 # INCR CNT to get Yn + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + ENCRYPT_SINGLE_BLOCK %xmm9 # E(K, Yn) + + sub $16, %r11 + add %r13, %r11 + vmovdqu (arg3, %r11), %xmm1 # receive the last <16 Byte block + + lea SHIFT_MASK+16(%rip), %r12 + sub %r13, %r12 # adjust the shuffle mask pointer to be + # able to shift 16-r13 bytes (r13 is the + # number of bytes in plaintext mod 16) + vmovdqu (%r12), %xmm2 # get the appropriate shuffle mask + vpshufb %xmm2, %xmm1, %xmm1 # shift right 16-r13 bytes + jmp _final_ghash_mul\@ + +_only_less_than_16\@: + # check for 0 length + mov arg4, %r13 + and $15, %r13 # r13 = (arg4 mod 16) + + je _multiple_of_16_bytes\@ + + # handle the last <16 Byte block seperately + + + vpaddd ONE(%rip), %xmm9, %xmm9 # INCR CNT to get Yn + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + ENCRYPT_SINGLE_BLOCK %xmm9 # E(K, Yn) + + + lea SHIFT_MASK+16(%rip), %r12 + sub %r13, %r12 # adjust the shuffle mask pointer to be + # able to shift 16-r13 bytes (r13 is the + # number of bytes in plaintext mod 16) + +_get_last_16_byte_loop\@: + movb (arg3, %r11), %al + movb %al, TMP1 (%rsp , %r11) + add $1, %r11 + cmp %r13, %r11 + jne _get_last_16_byte_loop\@ + + vmovdqu TMP1(%rsp), %xmm1 + + sub $16, %r11 + +_final_ghash_mul\@: + .if \ENC_DEC == DEC + vmovdqa %xmm1, %xmm2 + vpxor %xmm1, %xmm9, %xmm9 # Plaintext XOR E(K, Yn) + vmovdqu ALL_F-SHIFT_MASK(%r12), %xmm1 # get the appropriate mask to + # mask out top 16-r13 bytes of xmm9 + vpand %xmm1, %xmm9, %xmm9 # mask out top 16-r13 bytes of xmm9 + vpand %xmm1, %xmm2, %xmm2 + vpshufb SHUF_MASK(%rip), %xmm2, %xmm2 + vpxor %xmm2, %xmm14, %xmm14 + #GHASH computation for the last <16 Byte block + GHASH_MUL_AVX %xmm14, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6 + sub %r13, %r11 + add $16, %r11 + .else + vpxor %xmm1, %xmm9, %xmm9 # Plaintext XOR E(K, Yn) + vmovdqu ALL_F-SHIFT_MASK(%r12), %xmm1 # get the appropriate mask to + # mask out top 16-r13 bytes of xmm9 + vpand %xmm1, %xmm9, %xmm9 # mask out top 16-r13 bytes of xmm9 + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + vpxor %xmm9, %xmm14, %xmm14 + #GHASH computation for the last <16 Byte block + GHASH_MUL_AVX %xmm14, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6 + sub %r13, %r11 + add $16, %r11 + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 # shuffle xmm9 back to output as ciphertext + .endif + + + ############################# + # output r13 Bytes + vmovq %xmm9, %rax + cmp $8, %r13 + jle _less_than_8_bytes_left\@ + + mov %rax, (arg2 , %r11) + add $8, %r11 + vpsrldq $8, %xmm9, %xmm9 + vmovq %xmm9, %rax + sub $8, %r13 + +_less_than_8_bytes_left\@: + movb %al, (arg2 , %r11) + add $1, %r11 + shr $8, %rax + sub $1, %r13 + jne _less_than_8_bytes_left\@ + ############################# + +_multiple_of_16_bytes\@: + mov arg7, %r12 # r12 = aadLen (number of bytes) + shl $3, %r12 # convert into number of bits + vmovd %r12d, %xmm15 # len(A) in xmm15 + + shl $3, arg4 # len(C) in bits (*128) + vmovq arg4, %xmm1 + vpslldq $8, %xmm15, %xmm15 # xmm15 = len(A)|| 0x0000000000000000 + vpxor %xmm1, %xmm15, %xmm15 # xmm15 = len(A)||len(C) + + vpxor %xmm15, %xmm14, %xmm14 + GHASH_MUL_AVX %xmm14, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6 # final GHASH computation + vpshufb SHUF_MASK(%rip), %xmm14, %xmm14 # perform a 16Byte swap + + mov arg5, %rax # rax = *Y0 + vmovdqu (%rax), %xmm9 # xmm9 = Y0 + + ENCRYPT_SINGLE_BLOCK %xmm9 # E(K, Y0) + + vpxor %xmm14, %xmm9, %xmm9 + + + +_return_T\@: + mov arg8, %r10 # r10 = authTag + mov arg9, %r11 # r11 = auth_tag_len + + cmp $16, %r11 + je _T_16\@ + + cmp $12, %r11 + je _T_12\@ + +_T_8\@: + vmovq %xmm9, %rax + mov %rax, (%r10) + jmp _return_T_done\@ +_T_12\@: + vmovq %xmm9, %rax + mov %rax, (%r10) + vpsrldq $8, %xmm9, %xmm9 + vmovd %xmm9, %eax + mov %eax, 8(%r10) + jmp _return_T_done\@ + +_T_16\@: + vmovdqu %xmm9, (%r10) + +_return_T_done\@: + mov %r14, %rsp + + pop %r15 + pop %r14 + pop %r13 + pop %r12 +.endm + + +############################################################# +#void aesni_gcm_precomp_avx_gen2 +# (gcm_data *my_ctx_data, +# u8 *hash_subkey)# /* H, the Hash sub key input. Data starts on a 16-byte boundary. */ +############################################################# +ENTRY(aesni_gcm_precomp_avx_gen2) + #the number of pushes must equal STACK_OFFSET + push %r12 + push %r13 + push %r14 + push %r15 + + mov %rsp, %r14 + + + + sub $VARIABLE_OFFSET, %rsp + and $~63, %rsp # align rsp to 64 bytes + + vmovdqu (arg2), %xmm6 # xmm6 = HashKey + + vpshufb SHUF_MASK(%rip), %xmm6, %xmm6 + ############### PRECOMPUTATION of HashKey<<1 mod poly from the HashKey + vmovdqa %xmm6, %xmm2 + vpsllq $1, %xmm6, %xmm6 + vpsrlq $63, %xmm2, %xmm2 + vmovdqa %xmm2, %xmm1 + vpslldq $8, %xmm2, %xmm2 + vpsrldq $8, %xmm1, %xmm1 + vpor %xmm2, %xmm6, %xmm6 + #reduction + vpshufd $0b00100100, %xmm1, %xmm2 + vpcmpeqd TWOONE(%rip), %xmm2, %xmm2 + vpand POLY(%rip), %xmm2, %xmm2 + vpxor %xmm2, %xmm6, %xmm6 # xmm6 holds the HashKey<<1 mod poly + ####################################################################### + vmovdqa %xmm6, HashKey(arg1) # store HashKey<<1 mod poly + + + PRECOMPUTE_AVX %xmm6, %xmm0, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5 + + mov %r14, %rsp + + pop %r15 + pop %r14 + pop %r13 + pop %r12 + ret +ENDPROC(aesni_gcm_precomp_avx_gen2) + +############################################################################### +#void aesni_gcm_enc_avx_gen2( +# gcm_data *my_ctx_data, /* aligned to 16 Bytes */ +# u8 *out, /* Ciphertext output. Encrypt in-place is allowed. */ +# const u8 *in, /* Plaintext input */ +# u64 plaintext_len, /* Length of data in Bytes for encryption. */ +# u8 *iv, /* Pre-counter block j0: 4 byte salt +# (from Security Association) concatenated with 8 byte +# Initialisation Vector (from IPSec ESP Payload) +# concatenated with 0x00000001. 16-byte aligned pointer. */ +# const u8 *aad, /* Additional Authentication Data (AAD)*/ +# u64 aad_len, /* Length of AAD in bytes. With RFC4106 this is going to be 8 or 12 Bytes */ +# u8 *auth_tag, /* Authenticated Tag output. */ +# u64 auth_tag_len)# /* Authenticated Tag Length in bytes. +# Valid values are 16 (most likely), 12 or 8. */ +############################################################################### +ENTRY(aesni_gcm_enc_avx_gen2) + GCM_ENC_DEC_AVX ENC + ret +ENDPROC(aesni_gcm_enc_avx_gen2) + +############################################################################### +#void aesni_gcm_dec_avx_gen2( +# gcm_data *my_ctx_data, /* aligned to 16 Bytes */ +# u8 *out, /* Plaintext output. Decrypt in-place is allowed. */ +# const u8 *in, /* Ciphertext input */ +# u64 plaintext_len, /* Length of data in Bytes for encryption. */ +# u8 *iv, /* Pre-counter block j0: 4 byte salt +# (from Security Association) concatenated with 8 byte +# Initialisation Vector (from IPSec ESP Payload) +# concatenated with 0x00000001. 16-byte aligned pointer. */ +# const u8 *aad, /* Additional Authentication Data (AAD)*/ +# u64 aad_len, /* Length of AAD in bytes. With RFC4106 this is going to be 8 or 12 Bytes */ +# u8 *auth_tag, /* Authenticated Tag output. */ +# u64 auth_tag_len)# /* Authenticated Tag Length in bytes. +# Valid values are 16 (most likely), 12 or 8. */ +############################################################################### +ENTRY(aesni_gcm_dec_avx_gen2) + GCM_ENC_DEC_AVX DEC + ret +ENDPROC(aesni_gcm_dec_avx_gen2) +#endif /* CONFIG_AS_AVX */ + +#ifdef CONFIG_AS_AVX2 +############################################################################### +# GHASH_MUL MACRO to implement: Data*HashKey mod (128,127,126,121,0) +# Input: A and B (128-bits each, bit-reflected) +# Output: C = A*B*x mod poly, (i.e. >>1 ) +# To compute GH = GH*HashKey mod poly, give HK = HashKey<<1 mod poly as input +# GH = GH * HK * x mod poly which is equivalent to GH*HashKey mod poly. +############################################################################### +.macro GHASH_MUL_AVX2 GH HK T1 T2 T3 T4 T5 + + vpclmulqdq $0x11,\HK,\GH,\T1 # T1 = a1*b1 + vpclmulqdq $0x00,\HK,\GH,\T2 # T2 = a0*b0 + vpclmulqdq $0x01,\HK,\GH,\T3 # T3 = a1*b0 + vpclmulqdq $0x10,\HK,\GH,\GH # GH = a0*b1 + vpxor \T3, \GH, \GH + + + vpsrldq $8 , \GH, \T3 # shift-R GH 2 DWs + vpslldq $8 , \GH, \GH # shift-L GH 2 DWs + + vpxor \T3, \T1, \T1 + vpxor \T2, \GH, \GH + + ####################################################################### + #first phase of the reduction + vmovdqa POLY2(%rip), \T3 + + vpclmulqdq $0x01, \GH, \T3, \T2 + vpslldq $8, \T2, \T2 # shift-L T2 2 DWs + + vpxor \T2, \GH, \GH # first phase of the reduction complete + ####################################################################### + #second phase of the reduction + vpclmulqdq $0x00, \GH, \T3, \T2 + vpsrldq $4, \T2, \T2 # shift-R T2 1 DW (Shift-R only 1-DW to obtain 2-DWs shift-R) + + vpclmulqdq $0x10, \GH, \T3, \GH + vpslldq $4, \GH, \GH # shift-L GH 1 DW (Shift-L 1-DW to obtain result with no shifts) + + vpxor \T2, \GH, \GH # second phase of the reduction complete + ####################################################################### + vpxor \T1, \GH, \GH # the result is in GH + + +.endm + +.macro PRECOMPUTE_AVX2 HK T1 T2 T3 T4 T5 T6 + + # Haskey_i_k holds XORed values of the low and high parts of the Haskey_i + vmovdqa \HK, \T5 + GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^2<<1 mod poly + vmovdqa \T5, HashKey_2(arg1) # [HashKey_2] = HashKey^2<<1 mod poly + + GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^3<<1 mod poly + vmovdqa \T5, HashKey_3(arg1) + + GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^4<<1 mod poly + vmovdqa \T5, HashKey_4(arg1) + + GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^5<<1 mod poly + vmovdqa \T5, HashKey_5(arg1) + + GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^6<<1 mod poly + vmovdqa \T5, HashKey_6(arg1) + + GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^7<<1 mod poly + vmovdqa \T5, HashKey_7(arg1) + + GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2 # T5 = HashKey^8<<1 mod poly + vmovdqa \T5, HashKey_8(arg1) + +.endm + + +## if a = number of total plaintext bytes +## b = floor(a/16) +## num_initial_blocks = b mod 4# +## encrypt the initial num_initial_blocks blocks and apply ghash on the ciphertext +## r10, r11, r12, rax are clobbered +## arg1, arg2, arg3, r14 are used as a pointer only, not modified + +.macro INITIAL_BLOCKS_AVX2 num_initial_blocks T1 T2 T3 T4 T5 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 T6 T_key ENC_DEC VER + i = (8-\num_initial_blocks) + setreg + + mov arg6, %r10 # r10 = AAD + mov arg7, %r12 # r12 = aadLen + + + mov %r12, %r11 + + vpxor reg_i, reg_i, reg_i +_get_AAD_loop\@: + vmovd (%r10), \T1 + vpslldq $12, \T1, \T1 + vpsrldq $4, reg_i, reg_i + vpxor \T1, reg_i, reg_i + + add $4, %r10 + sub $4, %r12 + jg _get_AAD_loop\@ + + + cmp $16, %r11 + je _get_AAD_loop2_done\@ + mov $16, %r12 + +_get_AAD_loop2\@: + vpsrldq $4, reg_i, reg_i + sub $4, %r12 + cmp %r11, %r12 + jg _get_AAD_loop2\@ + +_get_AAD_loop2_done\@: + + #byte-reflect the AAD data + vpshufb SHUF_MASK(%rip), reg_i, reg_i + + # initialize the data pointer offset as zero + xor %r11, %r11 + + # start AES for num_initial_blocks blocks + mov arg5, %rax # rax = *Y0 + vmovdqu (%rax), \CTR # CTR = Y0 + vpshufb SHUF_MASK(%rip), \CTR, \CTR + + + i = (9-\num_initial_blocks) + setreg +.rep \num_initial_blocks + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, reg_i + vpshufb SHUF_MASK(%rip), reg_i, reg_i # perform a 16Byte swap + i = (i+1) + setreg +.endr + + vmovdqa (arg1), \T_key + i = (9-\num_initial_blocks) + setreg +.rep \num_initial_blocks + vpxor \T_key, reg_i, reg_i + i = (i+1) + setreg +.endr + + j = 1 + setreg +.rep 9 + vmovdqa 16*j(arg1), \T_key + i = (9-\num_initial_blocks) + setreg +.rep \num_initial_blocks + vaesenc \T_key, reg_i, reg_i + i = (i+1) + setreg +.endr + + j = (j+1) + setreg +.endr + + + vmovdqa 16*10(arg1), \T_key + i = (9-\num_initial_blocks) + setreg +.rep \num_initial_blocks + vaesenclast \T_key, reg_i, reg_i + i = (i+1) + setreg +.endr + + i = (9-\num_initial_blocks) + setreg +.rep \num_initial_blocks + vmovdqu (arg3, %r11), \T1 + vpxor \T1, reg_i, reg_i + vmovdqu reg_i, (arg2 , %r11) # write back ciphertext for + # num_initial_blocks blocks + add $16, %r11 +.if \ENC_DEC == DEC + vmovdqa \T1, reg_i +.endif + vpshufb SHUF_MASK(%rip), reg_i, reg_i # prepare ciphertext for GHASH computations + i = (i+1) + setreg +.endr + + + i = (8-\num_initial_blocks) + j = (9-\num_initial_blocks) + setreg + GHASH_MUL_AVX2 reg_i, \T2, \T1, \T3, \T4, \T5, \T6 + +.rep \num_initial_blocks + vpxor reg_i, reg_j, reg_j + GHASH_MUL_AVX2 reg_j, \T2, \T1, \T3, \T4, \T5, \T6 # apply GHASH on num_initial_blocks blocks + i = (i+1) + j = (j+1) + setreg +.endr + # XMM8 has the combined result here + + vmovdqa \XMM8, TMP1(%rsp) + vmovdqa \XMM8, \T3 + + cmp $128, %r13 + jl _initial_blocks_done\@ # no need for precomputed constants + +############################################################################### +# Haskey_i_k holds XORed values of the low and high parts of the Haskey_i + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM1 + vpshufb SHUF_MASK(%rip), \XMM1, \XMM1 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM2 + vpshufb SHUF_MASK(%rip), \XMM2, \XMM2 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM3 + vpshufb SHUF_MASK(%rip), \XMM3, \XMM3 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM4 + vpshufb SHUF_MASK(%rip), \XMM4, \XMM4 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM5 + vpshufb SHUF_MASK(%rip), \XMM5, \XMM5 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM6 + vpshufb SHUF_MASK(%rip), \XMM6, \XMM6 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM7 + vpshufb SHUF_MASK(%rip), \XMM7, \XMM7 # perform a 16Byte swap + + vpaddd ONE(%rip), \CTR, \CTR # INCR Y0 + vmovdqa \CTR, \XMM8 + vpshufb SHUF_MASK(%rip), \XMM8, \XMM8 # perform a 16Byte swap + + vmovdqa (arg1), \T_key + vpxor \T_key, \XMM1, \XMM1 + vpxor \T_key, \XMM2, \XMM2 + vpxor \T_key, \XMM3, \XMM3 + vpxor \T_key, \XMM4, \XMM4 + vpxor \T_key, \XMM5, \XMM5 + vpxor \T_key, \XMM6, \XMM6 + vpxor \T_key, \XMM7, \XMM7 + vpxor \T_key, \XMM8, \XMM8 + + i = 1 + setreg +.rep 9 # do 9 rounds + vmovdqa 16*i(arg1), \T_key + vaesenc \T_key, \XMM1, \XMM1 + vaesenc \T_key, \XMM2, \XMM2 + vaesenc \T_key, \XMM3, \XMM3 + vaesenc \T_key, \XMM4, \XMM4 + vaesenc \T_key, \XMM5, \XMM5 + vaesenc \T_key, \XMM6, \XMM6 + vaesenc \T_key, \XMM7, \XMM7 + vaesenc \T_key, \XMM8, \XMM8 + i = (i+1) + setreg +.endr + + + vmovdqa 16*i(arg1), \T_key + vaesenclast \T_key, \XMM1, \XMM1 + vaesenclast \T_key, \XMM2, \XMM2 + vaesenclast \T_key, \XMM3, \XMM3 + vaesenclast \T_key, \XMM4, \XMM4 + vaesenclast \T_key, \XMM5, \XMM5 + vaesenclast \T_key, \XMM6, \XMM6 + vaesenclast \T_key, \XMM7, \XMM7 + vaesenclast \T_key, \XMM8, \XMM8 + + vmovdqu (arg3, %r11), \T1 + vpxor \T1, \XMM1, \XMM1 + vmovdqu \XMM1, (arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM1 + .endif + + vmovdqu 16*1(arg3, %r11), \T1 + vpxor \T1, \XMM2, \XMM2 + vmovdqu \XMM2, 16*1(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM2 + .endif + + vmovdqu 16*2(arg3, %r11), \T1 + vpxor \T1, \XMM3, \XMM3 + vmovdqu \XMM3, 16*2(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM3 + .endif + + vmovdqu 16*3(arg3, %r11), \T1 + vpxor \T1, \XMM4, \XMM4 + vmovdqu \XMM4, 16*3(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM4 + .endif + + vmovdqu 16*4(arg3, %r11), \T1 + vpxor \T1, \XMM5, \XMM5 + vmovdqu \XMM5, 16*4(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM5 + .endif + + vmovdqu 16*5(arg3, %r11), \T1 + vpxor \T1, \XMM6, \XMM6 + vmovdqu \XMM6, 16*5(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM6 + .endif + + vmovdqu 16*6(arg3, %r11), \T1 + vpxor \T1, \XMM7, \XMM7 + vmovdqu \XMM7, 16*6(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM7 + .endif + + vmovdqu 16*7(arg3, %r11), \T1 + vpxor \T1, \XMM8, \XMM8 + vmovdqu \XMM8, 16*7(arg2 , %r11) + .if \ENC_DEC == DEC + vmovdqa \T1, \XMM8 + .endif + + add $128, %r11 + + vpshufb SHUF_MASK(%rip), \XMM1, \XMM1 # perform a 16Byte swap + vpxor TMP1(%rsp), \XMM1, \XMM1 # combine GHASHed value with + # the corresponding ciphertext + vpshufb SHUF_MASK(%rip), \XMM2, \XMM2 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM3, \XMM3 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM4, \XMM4 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM5, \XMM5 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM6, \XMM6 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM7, \XMM7 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM8, \XMM8 # perform a 16Byte swap + +############################################################################### + +_initial_blocks_done\@: + + +.endm + + + +# encrypt 8 blocks at a time +# ghash the 8 previously encrypted ciphertext blocks +# arg1, arg2, arg3 are used as pointers only, not modified +# r11 is the data offset value +.macro GHASH_8_ENCRYPT_8_PARALLEL_AVX2 T1 T2 T3 T4 T5 T6 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 T7 loop_idx ENC_DEC + + vmovdqa \XMM1, \T2 + vmovdqa \XMM2, TMP2(%rsp) + vmovdqa \XMM3, TMP3(%rsp) + vmovdqa \XMM4, TMP4(%rsp) + vmovdqa \XMM5, TMP5(%rsp) + vmovdqa \XMM6, TMP6(%rsp) + vmovdqa \XMM7, TMP7(%rsp) + vmovdqa \XMM8, TMP8(%rsp) + +.if \loop_idx == in_order + vpaddd ONE(%rip), \CTR, \XMM1 # INCR CNT + vpaddd ONE(%rip), \XMM1, \XMM2 + vpaddd ONE(%rip), \XMM2, \XMM3 + vpaddd ONE(%rip), \XMM3, \XMM4 + vpaddd ONE(%rip), \XMM4, \XMM5 + vpaddd ONE(%rip), \XMM5, \XMM6 + vpaddd ONE(%rip), \XMM6, \XMM7 + vpaddd ONE(%rip), \XMM7, \XMM8 + vmovdqa \XMM8, \CTR + + vpshufb SHUF_MASK(%rip), \XMM1, \XMM1 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM2, \XMM2 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM3, \XMM3 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM4, \XMM4 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM5, \XMM5 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM6, \XMM6 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM7, \XMM7 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM8, \XMM8 # perform a 16Byte swap +.else + vpaddd ONEf(%rip), \CTR, \XMM1 # INCR CNT + vpaddd ONEf(%rip), \XMM1, \XMM2 + vpaddd ONEf(%rip), \XMM2, \XMM3 + vpaddd ONEf(%rip), \XMM3, \XMM4 + vpaddd ONEf(%rip), \XMM4, \XMM5 + vpaddd ONEf(%rip), \XMM5, \XMM6 + vpaddd ONEf(%rip), \XMM6, \XMM7 + vpaddd ONEf(%rip), \XMM7, \XMM8 + vmovdqa \XMM8, \CTR +.endif + + + ####################################################################### + + vmovdqu (arg1), \T1 + vpxor \T1, \XMM1, \XMM1 + vpxor \T1, \XMM2, \XMM2 + vpxor \T1, \XMM3, \XMM3 + vpxor \T1, \XMM4, \XMM4 + vpxor \T1, \XMM5, \XMM5 + vpxor \T1, \XMM6, \XMM6 + vpxor \T1, \XMM7, \XMM7 + vpxor \T1, \XMM8, \XMM8 + + ####################################################################### + + + + + + vmovdqu 16*1(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + vmovdqu 16*2(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + + ####################################################################### + + vmovdqa HashKey_8(arg1), \T5 + vpclmulqdq $0x11, \T5, \T2, \T4 # T4 = a1*b1 + vpclmulqdq $0x00, \T5, \T2, \T7 # T7 = a0*b0 + vpclmulqdq $0x01, \T5, \T2, \T6 # T6 = a1*b0 + vpclmulqdq $0x10, \T5, \T2, \T5 # T5 = a0*b1 + vpxor \T5, \T6, \T6 + + vmovdqu 16*3(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + vmovdqa TMP2(%rsp), \T1 + vmovdqa HashKey_7(arg1), \T5 + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T4 + + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpclmulqdq $0x01, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + vpclmulqdq $0x10, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + vmovdqu 16*4(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + ####################################################################### + + vmovdqa TMP3(%rsp), \T1 + vmovdqa HashKey_6(arg1), \T5 + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T4 + + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpclmulqdq $0x01, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + vpclmulqdq $0x10, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + vmovdqu 16*5(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + vmovdqa TMP4(%rsp), \T1 + vmovdqa HashKey_5(arg1), \T5 + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T4 + + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpclmulqdq $0x01, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + vpclmulqdq $0x10, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + vmovdqu 16*6(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + + vmovdqa TMP5(%rsp), \T1 + vmovdqa HashKey_4(arg1), \T5 + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T4 + + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpclmulqdq $0x01, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + vpclmulqdq $0x10, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + vmovdqu 16*7(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + vmovdqa TMP6(%rsp), \T1 + vmovdqa HashKey_3(arg1), \T5 + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T4 + + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpclmulqdq $0x01, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + vpclmulqdq $0x10, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + vmovdqu 16*8(arg1), \T1 + vaesenc \T1, \XMM1, \XMM1 + vaesenc \T1, \XMM2, \XMM2 + vaesenc \T1, \XMM3, \XMM3 + vaesenc \T1, \XMM4, \XMM4 + vaesenc \T1, \XMM5, \XMM5 + vaesenc \T1, \XMM6, \XMM6 + vaesenc \T1, \XMM7, \XMM7 + vaesenc \T1, \XMM8, \XMM8 + + vmovdqa TMP7(%rsp), \T1 + vmovdqa HashKey_2(arg1), \T5 + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T4 + + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpclmulqdq $0x01, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + vpclmulqdq $0x10, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + + ####################################################################### + + vmovdqu 16*9(arg1), \T5 + vaesenc \T5, \XMM1, \XMM1 + vaesenc \T5, \XMM2, \XMM2 + vaesenc \T5, \XMM3, \XMM3 + vaesenc \T5, \XMM4, \XMM4 + vaesenc \T5, \XMM5, \XMM5 + vaesenc \T5, \XMM6, \XMM6 + vaesenc \T5, \XMM7, \XMM7 + vaesenc \T5, \XMM8, \XMM8 + + vmovdqa TMP8(%rsp), \T1 + vmovdqa HashKey(arg1), \T5 + + vpclmulqdq $0x00, \T5, \T1, \T3 + vpxor \T3, \T7, \T7 + + vpclmulqdq $0x01, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + vpclmulqdq $0x10, \T5, \T1, \T3 + vpxor \T3, \T6, \T6 + + vpclmulqdq $0x11, \T5, \T1, \T3 + vpxor \T3, \T4, \T1 + + + vmovdqu 16*10(arg1), \T5 + + i = 0 + j = 1 + setreg +.rep 8 + vpxor 16*i(arg3, %r11), \T5, \T2 + .if \ENC_DEC == ENC + vaesenclast \T2, reg_j, reg_j + .else + vaesenclast \T2, reg_j, \T3 + vmovdqu 16*i(arg3, %r11), reg_j + vmovdqu \T3, 16*i(arg2, %r11) + .endif + i = (i+1) + j = (j+1) + setreg +.endr + ####################################################################### + + + vpslldq $8, \T6, \T3 # shift-L T3 2 DWs + vpsrldq $8, \T6, \T6 # shift-R T2 2 DWs + vpxor \T3, \T7, \T7 + vpxor \T6, \T1, \T1 # accumulate the results in T1:T7 + + + + ####################################################################### + #first phase of the reduction + vmovdqa POLY2(%rip), \T3 + + vpclmulqdq $0x01, \T7, \T3, \T2 + vpslldq $8, \T2, \T2 # shift-L xmm2 2 DWs + + vpxor \T2, \T7, \T7 # first phase of the reduction complete + ####################################################################### + .if \ENC_DEC == ENC + vmovdqu \XMM1, 16*0(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM2, 16*1(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM3, 16*2(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM4, 16*3(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM5, 16*4(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM6, 16*5(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM7, 16*6(arg2,%r11) # Write to the Ciphertext buffer + vmovdqu \XMM8, 16*7(arg2,%r11) # Write to the Ciphertext buffer + .endif + + ####################################################################### + #second phase of the reduction + vpclmulqdq $0x00, \T7, \T3, \T2 + vpsrldq $4, \T2, \T2 # shift-R xmm2 1 DW (Shift-R only 1-DW to obtain 2-DWs shift-R) + + vpclmulqdq $0x10, \T7, \T3, \T4 + vpslldq $4, \T4, \T4 # shift-L xmm0 1 DW (Shift-L 1-DW to obtain result with no shifts) + + vpxor \T2, \T4, \T4 # second phase of the reduction complete + ####################################################################### + vpxor \T4, \T1, \T1 # the result is in T1 + + vpshufb SHUF_MASK(%rip), \XMM1, \XMM1 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM2, \XMM2 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM3, \XMM3 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM4, \XMM4 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM5, \XMM5 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM6, \XMM6 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM7, \XMM7 # perform a 16Byte swap + vpshufb SHUF_MASK(%rip), \XMM8, \XMM8 # perform a 16Byte swap + + + vpxor \T1, \XMM1, \XMM1 + + + +.endm + + +# GHASH the last 4 ciphertext blocks. +.macro GHASH_LAST_8_AVX2 T1 T2 T3 T4 T5 T6 T7 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 + + ## Karatsuba Method + + vmovdqa HashKey_8(arg1), \T5 + + vpshufd $0b01001110, \XMM1, \T2 + vpshufd $0b01001110, \T5, \T3 + vpxor \XMM1, \T2, \T2 + vpxor \T5, \T3, \T3 + + vpclmulqdq $0x11, \T5, \XMM1, \T6 + vpclmulqdq $0x00, \T5, \XMM1, \T7 + + vpclmulqdq $0x00, \T3, \T2, \XMM1 + + ###################### + + vmovdqa HashKey_7(arg1), \T5 + vpshufd $0b01001110, \XMM2, \T2 + vpshufd $0b01001110, \T5, \T3 + vpxor \XMM2, \T2, \T2 + vpxor \T5, \T3, \T3 + + vpclmulqdq $0x11, \T5, \XMM2, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM2, \T4 + vpxor \T4, \T7, \T7 + + vpclmulqdq $0x00, \T3, \T2, \T2 + + vpxor \T2, \XMM1, \XMM1 + + ###################### + + vmovdqa HashKey_6(arg1), \T5 + vpshufd $0b01001110, \XMM3, \T2 + vpshufd $0b01001110, \T5, \T3 + vpxor \XMM3, \T2, \T2 + vpxor \T5, \T3, \T3 + + vpclmulqdq $0x11, \T5, \XMM3, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM3, \T4 + vpxor \T4, \T7, \T7 + + vpclmulqdq $0x00, \T3, \T2, \T2 + + vpxor \T2, \XMM1, \XMM1 + + ###################### + + vmovdqa HashKey_5(arg1), \T5 + vpshufd $0b01001110, \XMM4, \T2 + vpshufd $0b01001110, \T5, \T3 + vpxor \XMM4, \T2, \T2 + vpxor \T5, \T3, \T3 + + vpclmulqdq $0x11, \T5, \XMM4, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM4, \T4 + vpxor \T4, \T7, \T7 + + vpclmulqdq $0x00, \T3, \T2, \T2 + + vpxor \T2, \XMM1, \XMM1 + + ###################### + + vmovdqa HashKey_4(arg1), \T5 + vpshufd $0b01001110, \XMM5, \T2 + vpshufd $0b01001110, \T5, \T3 + vpxor \XMM5, \T2, \T2 + vpxor \T5, \T3, \T3 + + vpclmulqdq $0x11, \T5, \XMM5, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM5, \T4 + vpxor \T4, \T7, \T7 + + vpclmulqdq $0x00, \T3, \T2, \T2 + + vpxor \T2, \XMM1, \XMM1 + + ###################### + + vmovdqa HashKey_3(arg1), \T5 + vpshufd $0b01001110, \XMM6, \T2 + vpshufd $0b01001110, \T5, \T3 + vpxor \XMM6, \T2, \T2 + vpxor \T5, \T3, \T3 + + vpclmulqdq $0x11, \T5, \XMM6, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM6, \T4 + vpxor \T4, \T7, \T7 + + vpclmulqdq $0x00, \T3, \T2, \T2 + + vpxor \T2, \XMM1, \XMM1 + + ###################### + + vmovdqa HashKey_2(arg1), \T5 + vpshufd $0b01001110, \XMM7, \T2 + vpshufd $0b01001110, \T5, \T3 + vpxor \XMM7, \T2, \T2 + vpxor \T5, \T3, \T3 + + vpclmulqdq $0x11, \T5, \XMM7, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM7, \T4 + vpxor \T4, \T7, \T7 + + vpclmulqdq $0x00, \T3, \T2, \T2 + + vpxor \T2, \XMM1, \XMM1 + + ###################### + + vmovdqa HashKey(arg1), \T5 + vpshufd $0b01001110, \XMM8, \T2 + vpshufd $0b01001110, \T5, \T3 + vpxor \XMM8, \T2, \T2 + vpxor \T5, \T3, \T3 + + vpclmulqdq $0x11, \T5, \XMM8, \T4 + vpxor \T4, \T6, \T6 + + vpclmulqdq $0x00, \T5, \XMM8, \T4 + vpxor \T4, \T7, \T7 + + vpclmulqdq $0x00, \T3, \T2, \T2 + + vpxor \T2, \XMM1, \XMM1 + vpxor \T6, \XMM1, \XMM1 + vpxor \T7, \XMM1, \T2 + + + + + vpslldq $8, \T2, \T4 + vpsrldq $8, \T2, \T2 + + vpxor \T4, \T7, \T7 + vpxor \T2, \T6, \T6 # <T6:T7> holds the result of the + # accumulated carry-less multiplications + + ####################################################################### + #first phase of the reduction + vmovdqa POLY2(%rip), \T3 + + vpclmulqdq $0x01, \T7, \T3, \T2 + vpslldq $8, \T2, \T2 # shift-L xmm2 2 DWs + + vpxor \T2, \T7, \T7 # first phase of the reduction complete + ####################################################################### + + + #second phase of the reduction + vpclmulqdq $0x00, \T7, \T3, \T2 + vpsrldq $4, \T2, \T2 # shift-R T2 1 DW (Shift-R only 1-DW to obtain 2-DWs shift-R) + + vpclmulqdq $0x10, \T7, \T3, \T4 + vpslldq $4, \T4, \T4 # shift-L T4 1 DW (Shift-L 1-DW to obtain result with no shifts) + + vpxor \T2, \T4, \T4 # second phase of the reduction complete + ####################################################################### + vpxor \T4, \T6, \T6 # the result is in T6 +.endm + + + +# combined for GCM encrypt and decrypt functions +# clobbering all xmm registers +# clobbering r10, r11, r12, r13, r14, r15 +.macro GCM_ENC_DEC_AVX2 ENC_DEC + + #the number of pushes must equal STACK_OFFSET + push %r12 + push %r13 + push %r14 + push %r15 + + mov %rsp, %r14 + + + + + sub $VARIABLE_OFFSET, %rsp + and $~63, %rsp # align rsp to 64 bytes + + + vmovdqu HashKey(arg1), %xmm13 # xmm13 = HashKey + + mov arg4, %r13 # save the number of bytes of plaintext/ciphertext + and $-16, %r13 # r13 = r13 - (r13 mod 16) + + mov %r13, %r12 + shr $4, %r12 + and $7, %r12 + jz _initial_num_blocks_is_0\@ + + cmp $7, %r12 + je _initial_num_blocks_is_7\@ + cmp $6, %r12 + je _initial_num_blocks_is_6\@ + cmp $5, %r12 + je _initial_num_blocks_is_5\@ + cmp $4, %r12 + je _initial_num_blocks_is_4\@ + cmp $3, %r12 + je _initial_num_blocks_is_3\@ + cmp $2, %r12 + je _initial_num_blocks_is_2\@ + + jmp _initial_num_blocks_is_1\@ + +_initial_num_blocks_is_7\@: + INITIAL_BLOCKS_AVX2 7, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*7, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_6\@: + INITIAL_BLOCKS_AVX2 6, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*6, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_5\@: + INITIAL_BLOCKS_AVX2 5, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*5, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_4\@: + INITIAL_BLOCKS_AVX2 4, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*4, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_3\@: + INITIAL_BLOCKS_AVX2 3, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*3, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_2\@: + INITIAL_BLOCKS_AVX2 2, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*2, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_1\@: + INITIAL_BLOCKS_AVX2 1, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + sub $16*1, %r13 + jmp _initial_blocks_encrypted\@ + +_initial_num_blocks_is_0\@: + INITIAL_BLOCKS_AVX2 0, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC + + +_initial_blocks_encrypted\@: + cmp $0, %r13 + je _zero_cipher_left\@ + + sub $128, %r13 + je _eight_cipher_left\@ + + + + + vmovd %xmm9, %r15d + and $255, %r15d + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + + +_encrypt_by_8_new\@: + cmp $(255-8), %r15d + jg _encrypt_by_8\@ + + + + add $8, %r15b + GHASH_8_ENCRYPT_8_PARALLEL_AVX2 %xmm0, %xmm10, %xmm11, %xmm12, %xmm13, %xmm14, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm15, out_order, \ENC_DEC + add $128, %r11 + sub $128, %r13 + jne _encrypt_by_8_new\@ + + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + jmp _eight_cipher_left\@ + +_encrypt_by_8\@: + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + add $8, %r15b + GHASH_8_ENCRYPT_8_PARALLEL_AVX2 %xmm0, %xmm10, %xmm11, %xmm12, %xmm13, %xmm14, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm15, in_order, \ENC_DEC + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + add $128, %r11 + sub $128, %r13 + jne _encrypt_by_8_new\@ + + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + + + + +_eight_cipher_left\@: + GHASH_LAST_8_AVX2 %xmm0, %xmm10, %xmm11, %xmm12, %xmm13, %xmm14, %xmm15, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8 + + +_zero_cipher_left\@: + cmp $16, arg4 + jl _only_less_than_16\@ + + mov arg4, %r13 + and $15, %r13 # r13 = (arg4 mod 16) + + je _multiple_of_16_bytes\@ + + # handle the last <16 Byte block seperately + + + vpaddd ONE(%rip), %xmm9, %xmm9 # INCR CNT to get Yn + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + ENCRYPT_SINGLE_BLOCK %xmm9 # E(K, Yn) + + sub $16, %r11 + add %r13, %r11 + vmovdqu (arg3, %r11), %xmm1 # receive the last <16 Byte block + + lea SHIFT_MASK+16(%rip), %r12 + sub %r13, %r12 # adjust the shuffle mask pointer + # to be able to shift 16-r13 bytes + # (r13 is the number of bytes in plaintext mod 16) + vmovdqu (%r12), %xmm2 # get the appropriate shuffle mask + vpshufb %xmm2, %xmm1, %xmm1 # shift right 16-r13 bytes + jmp _final_ghash_mul\@ + +_only_less_than_16\@: + # check for 0 length + mov arg4, %r13 + and $15, %r13 # r13 = (arg4 mod 16) + + je _multiple_of_16_bytes\@ + + # handle the last <16 Byte block seperately + + + vpaddd ONE(%rip), %xmm9, %xmm9 # INCR CNT to get Yn + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + ENCRYPT_SINGLE_BLOCK %xmm9 # E(K, Yn) + + + lea SHIFT_MASK+16(%rip), %r12 + sub %r13, %r12 # adjust the shuffle mask pointer to be + # able to shift 16-r13 bytes (r13 is the + # number of bytes in plaintext mod 16) + +_get_last_16_byte_loop\@: + movb (arg3, %r11), %al + movb %al, TMP1 (%rsp , %r11) + add $1, %r11 + cmp %r13, %r11 + jne _get_last_16_byte_loop\@ + + vmovdqu TMP1(%rsp), %xmm1 + + sub $16, %r11 + +_final_ghash_mul\@: + .if \ENC_DEC == DEC + vmovdqa %xmm1, %xmm2 + vpxor %xmm1, %xmm9, %xmm9 # Plaintext XOR E(K, Yn) + vmovdqu ALL_F-SHIFT_MASK(%r12), %xmm1 # get the appropriate mask to mask out top 16-r13 bytes of xmm9 + vpand %xmm1, %xmm9, %xmm9 # mask out top 16-r13 bytes of xmm9 + vpand %xmm1, %xmm2, %xmm2 + vpshufb SHUF_MASK(%rip), %xmm2, %xmm2 + vpxor %xmm2, %xmm14, %xmm14 + #GHASH computation for the last <16 Byte block + GHASH_MUL_AVX2 %xmm14, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6 + sub %r13, %r11 + add $16, %r11 + .else + vpxor %xmm1, %xmm9, %xmm9 # Plaintext XOR E(K, Yn) + vmovdqu ALL_F-SHIFT_MASK(%r12), %xmm1 # get the appropriate mask to mask out top 16-r13 bytes of xmm9 + vpand %xmm1, %xmm9, %xmm9 # mask out top 16-r13 bytes of xmm9 + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 + vpxor %xmm9, %xmm14, %xmm14 + #GHASH computation for the last <16 Byte block + GHASH_MUL_AVX2 %xmm14, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6 + sub %r13, %r11 + add $16, %r11 + vpshufb SHUF_MASK(%rip), %xmm9, %xmm9 # shuffle xmm9 back to output as ciphertext + .endif + + + ############################# + # output r13 Bytes + vmovq %xmm9, %rax + cmp $8, %r13 + jle _less_than_8_bytes_left\@ + + mov %rax, (arg2 , %r11) + add $8, %r11 + vpsrldq $8, %xmm9, %xmm9 + vmovq %xmm9, %rax + sub $8, %r13 + +_less_than_8_bytes_left\@: + movb %al, (arg2 , %r11) + add $1, %r11 + shr $8, %rax + sub $1, %r13 + jne _less_than_8_bytes_left\@ + ############################# + +_multiple_of_16_bytes\@: + mov arg7, %r12 # r12 = aadLen (number of bytes) + shl $3, %r12 # convert into number of bits + vmovd %r12d, %xmm15 # len(A) in xmm15 + + shl $3, arg4 # len(C) in bits (*128) + vmovq arg4, %xmm1 + vpslldq $8, %xmm15, %xmm15 # xmm15 = len(A)|| 0x0000000000000000 + vpxor %xmm1, %xmm15, %xmm15 # xmm15 = len(A)||len(C) + + vpxor %xmm15, %xmm14, %xmm14 + GHASH_MUL_AVX2 %xmm14, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6 # final GHASH computation + vpshufb SHUF_MASK(%rip), %xmm14, %xmm14 # perform a 16Byte swap + + mov arg5, %rax # rax = *Y0 + vmovdqu (%rax), %xmm9 # xmm9 = Y0 + + ENCRYPT_SINGLE_BLOCK %xmm9 # E(K, Y0) + + vpxor %xmm14, %xmm9, %xmm9 + + + +_return_T\@: + mov arg8, %r10 # r10 = authTag + mov arg9, %r11 # r11 = auth_tag_len + + cmp $16, %r11 + je _T_16\@ + + cmp $12, %r11 + je _T_12\@ + +_T_8\@: + vmovq %xmm9, %rax + mov %rax, (%r10) + jmp _return_T_done\@ +_T_12\@: + vmovq %xmm9, %rax + mov %rax, (%r10) + vpsrldq $8, %xmm9, %xmm9 + vmovd %xmm9, %eax + mov %eax, 8(%r10) + jmp _return_T_done\@ + +_T_16\@: + vmovdqu %xmm9, (%r10) + +_return_T_done\@: + mov %r14, %rsp + + pop %r15 + pop %r14 + pop %r13 + pop %r12 +.endm + + +############################################################# +#void aesni_gcm_precomp_avx_gen4 +# (gcm_data *my_ctx_data, +# u8 *hash_subkey)# /* H, the Hash sub key input. +# Data starts on a 16-byte boundary. */ +############################################################# +ENTRY(aesni_gcm_precomp_avx_gen4) + #the number of pushes must equal STACK_OFFSET + push %r12 + push %r13 + push %r14 + push %r15 + + mov %rsp, %r14 + + + + sub $VARIABLE_OFFSET, %rsp + and $~63, %rsp # align rsp to 64 bytes + + vmovdqu (arg2), %xmm6 # xmm6 = HashKey + + vpshufb SHUF_MASK(%rip), %xmm6, %xmm6 + ############### PRECOMPUTATION of HashKey<<1 mod poly from the HashKey + vmovdqa %xmm6, %xmm2 + vpsllq $1, %xmm6, %xmm6 + vpsrlq $63, %xmm2, %xmm2 + vmovdqa %xmm2, %xmm1 + vpslldq $8, %xmm2, %xmm2 + vpsrldq $8, %xmm1, %xmm1 + vpor %xmm2, %xmm6, %xmm6 + #reduction + vpshufd $0b00100100, %xmm1, %xmm2 + vpcmpeqd TWOONE(%rip), %xmm2, %xmm2 + vpand POLY(%rip), %xmm2, %xmm2 + vpxor %xmm2, %xmm6, %xmm6 # xmm6 holds the HashKey<<1 mod poly + ####################################################################### + vmovdqa %xmm6, HashKey(arg1) # store HashKey<<1 mod poly + + + PRECOMPUTE_AVX2 %xmm6, %xmm0, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5 + + mov %r14, %rsp + + pop %r15 + pop %r14 + pop %r13 + pop %r12 + ret +ENDPROC(aesni_gcm_precomp_avx_gen4) + + +############################################################################### +#void aesni_gcm_enc_avx_gen4( +# gcm_data *my_ctx_data, /* aligned to 16 Bytes */ +# u8 *out, /* Ciphertext output. Encrypt in-place is allowed. */ +# const u8 *in, /* Plaintext input */ +# u64 plaintext_len, /* Length of data in Bytes for encryption. */ +# u8 *iv, /* Pre-counter block j0: 4 byte salt +# (from Security Association) concatenated with 8 byte +# Initialisation Vector (from IPSec ESP Payload) +# concatenated with 0x00000001. 16-byte aligned pointer. */ +# const u8 *aad, /* Additional Authentication Data (AAD)*/ +# u64 aad_len, /* Length of AAD in bytes. With RFC4106 this is going to be 8 or 12 Bytes */ +# u8 *auth_tag, /* Authenticated Tag output. */ +# u64 auth_tag_len)# /* Authenticated Tag Length in bytes. +# Valid values are 16 (most likely), 12 or 8. */ +############################################################################### +ENTRY(aesni_gcm_enc_avx_gen4) + GCM_ENC_DEC_AVX2 ENC + ret +ENDPROC(aesni_gcm_enc_avx_gen4) + +############################################################################### +#void aesni_gcm_dec_avx_gen4( +# gcm_data *my_ctx_data, /* aligned to 16 Bytes */ +# u8 *out, /* Plaintext output. Decrypt in-place is allowed. */ +# const u8 *in, /* Ciphertext input */ +# u64 plaintext_len, /* Length of data in Bytes for encryption. */ +# u8 *iv, /* Pre-counter block j0: 4 byte salt +# (from Security Association) concatenated with 8 byte +# Initialisation Vector (from IPSec ESP Payload) +# concatenated with 0x00000001. 16-byte aligned pointer. */ +# const u8 *aad, /* Additional Authentication Data (AAD)*/ +# u64 aad_len, /* Length of AAD in bytes. With RFC4106 this is going to be 8 or 12 Bytes */ +# u8 *auth_tag, /* Authenticated Tag output. */ +# u64 auth_tag_len)# /* Authenticated Tag Length in bytes. +# Valid values are 16 (most likely), 12 or 8. */ +############################################################################### +ENTRY(aesni_gcm_dec_avx_gen4) + GCM_ENC_DEC_AVX2 DEC + ret +ENDPROC(aesni_gcm_dec_avx_gen4) + +#endif /* CONFIG_AS_AVX2 */ diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c index 835488b..948ad0e 100644 --- a/arch/x86/crypto/aesni-intel_glue.c +++ b/arch/x86/crypto/aesni-intel_glue.c @@ -101,6 +101,9 @@ asmlinkage void aesni_cbc_dec(struct crypto_aes_ctx *ctx, u8 *out, int crypto_fpu_init(void); void crypto_fpu_exit(void); +#define AVX_GEN2_OPTSIZE 640 +#define AVX_GEN4_OPTSIZE 4096 + #ifdef CONFIG_X86_64 asmlinkage void aesni_ctr_enc(struct crypto_aes_ctx *ctx, u8 *out, const u8 *in, unsigned int len, u8 *iv); @@ -150,6 +153,123 @@ asmlinkage void aesni_gcm_dec(void *ctx, u8 *out, u8 *hash_subkey, const u8 *aad, unsigned long aad_len, u8 *auth_tag, unsigned long auth_tag_len); + +#ifdef CONFIG_AS_AVX +/* + * asmlinkage void aesni_gcm_precomp_avx_gen2() + * gcm_data *my_ctx_data, context data + * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary. + */ +asmlinkage void aesni_gcm_precomp_avx_gen2(void *my_ctx_data, u8 *hash_subkey); + +asmlinkage void aesni_gcm_enc_avx_gen2(void *ctx, u8 *out, + const u8 *in, unsigned long plaintext_len, u8 *iv, + const u8 *aad, unsigned long aad_len, + u8 *auth_tag, unsigned long auth_tag_len); + +asmlinkage void aesni_gcm_dec_avx_gen2(void *ctx, u8 *out, + const u8 *in, unsigned long ciphertext_len, u8 *iv, + const u8 *aad, unsigned long aad_len, + u8 *auth_tag, unsigned long auth_tag_len); + +static void aesni_gcm_enc_avx(void *ctx, u8 *out, + const u8 *in, unsigned long plaintext_len, u8 *iv, + u8 *hash_subkey, const u8 *aad, unsigned long aad_len, + u8 *auth_tag, unsigned long auth_tag_len) +{ + if (plaintext_len < AVX_GEN2_OPTSIZE) { + aesni_gcm_enc(ctx, out, in, plaintext_len, iv, hash_subkey, aad, + aad_len, auth_tag, auth_tag_len); + } else { + aesni_gcm_precomp_avx_gen2(ctx, hash_subkey); + aesni_gcm_enc_avx_gen2(ctx, out, in, plaintext_len, iv, aad, + aad_len, auth_tag, auth_tag_len); + } +} + +static void aesni_gcm_dec_avx(void *ctx, u8 *out, + const u8 *in, unsigned long ciphertext_len, u8 *iv, + u8 *hash_subkey, const u8 *aad, unsigned long aad_len, + u8 *auth_tag, unsigned long auth_tag_len) +{ + if (ciphertext_len < AVX_GEN2_OPTSIZE) { + aesni_gcm_dec(ctx, out, in, ciphertext_len, iv, hash_subkey, aad, + aad_len, auth_tag, auth_tag_len); + } else { + aesni_gcm_precomp_avx_gen2(ctx, hash_subkey); + aesni_gcm_dec_avx_gen2(ctx, out, in, ciphertext_len, iv, aad, + aad_len, auth_tag, auth_tag_len); + } +} +#endif + +#ifdef CONFIG_AS_AVX2 +/* + * asmlinkage void aesni_gcm_precomp_avx_gen4() + * gcm_data *my_ctx_data, context data + * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary. + */ +asmlinkage void aesni_gcm_precomp_avx_gen4(void *my_ctx_data, u8 *hash_subkey); + +asmlinkage void aesni_gcm_enc_avx_gen4(void *ctx, u8 *out, + const u8 *in, unsigned long plaintext_len, u8 *iv, + const u8 *aad, unsigned long aad_len, + u8 *auth_tag, unsigned long auth_tag_len); + +asmlinkage void aesni_gcm_dec_avx_gen4(void *ctx, u8 *out, + const u8 *in, unsigned long ciphertext_len, u8 *iv, + const u8 *aad, unsigned long aad_len, + u8 *auth_tag, unsigned long auth_tag_len); + +static void aesni_gcm_enc_avx2(void *ctx, u8 *out, + const u8 *in, unsigned long plaintext_len, u8 *iv, + u8 *hash_subkey, const u8 *aad, unsigned long aad_len, + u8 *auth_tag, unsigned long auth_tag_len) +{ + if (plaintext_len < AVX_GEN2_OPTSIZE) { + aesni_gcm_enc(ctx, out, in, plaintext_len, iv, hash_subkey, aad, + aad_len, auth_tag, auth_tag_len); + } else if (plaintext_len < AVX_GEN4_OPTSIZE) { + aesni_gcm_precomp_avx_gen2(ctx, hash_subkey); + aesni_gcm_enc_avx_gen2(ctx, out, in, plaintext_len, iv, aad, + aad_len, auth_tag, auth_tag_len); + } else { + aesni_gcm_precomp_avx_gen4(ctx, hash_subkey); + aesni_gcm_enc_avx_gen4(ctx, out, in, plaintext_len, iv, aad, + aad_len, auth_tag, auth_tag_len); + } +} + +static void aesni_gcm_dec_avx2(void *ctx, u8 *out, + const u8 *in, unsigned long ciphertext_len, u8 *iv, + u8 *hash_subkey, const u8 *aad, unsigned long aad_len, + u8 *auth_tag, unsigned long auth_tag_len) +{ + if (ciphertext_len < AVX_GEN2_OPTSIZE) { + aesni_gcm_dec(ctx, out, in, ciphertext_len, iv, hash_subkey, + aad, aad_len, auth_tag, auth_tag_len); + } else if (ciphertext_len < AVX_GEN4_OPTSIZE) { + aesni_gcm_precomp_avx_gen2(ctx, hash_subkey); + aesni_gcm_dec_avx_gen2(ctx, out, in, ciphertext_len, iv, aad, + aad_len, auth_tag, auth_tag_len); + } else { + aesni_gcm_precomp_avx_gen4(ctx, hash_subkey); + aesni_gcm_dec_avx_gen4(ctx, out, in, ciphertext_len, iv, aad, + aad_len, auth_tag, auth_tag_len); + } +} +#endif + +static void (*aesni_gcm_enc_tfm)(void *ctx, u8 *out, + const u8 *in, unsigned long plaintext_len, u8 *iv, + u8 *hash_subkey, const u8 *aad, unsigned long aad_len, + u8 *auth_tag, unsigned long auth_tag_len); + +static void (*aesni_gcm_dec_tfm)(void *ctx, u8 *out, + const u8 *in, unsigned long ciphertext_len, u8 *iv, + u8 *hash_subkey, const u8 *aad, unsigned long aad_len, + u8 *auth_tag, unsigned long auth_tag_len); + static inline struct aesni_rfc4106_gcm_ctx *aesni_rfc4106_gcm_ctx_get(struct crypto_aead *tfm) { @@ -915,7 +1035,7 @@ static int __driver_rfc4106_encrypt(struct aead_request *req) dst = src; } - aesni_gcm_enc(aes_ctx, dst, src, (unsigned long)req->cryptlen, iv, + aesni_gcm_enc_tfm(aes_ctx, dst, src, (unsigned long)req->cryptlen, iv, ctx->hash_subkey, assoc, (unsigned long)req->assoclen, dst + ((unsigned long)req->cryptlen), auth_tag_len); @@ -996,12 +1116,12 @@ static int __driver_rfc4106_decrypt(struct aead_request *req) dst = src; } - aesni_gcm_dec(aes_ctx, dst, src, tempCipherLen, iv, + aesni_gcm_dec_tfm(aes_ctx, dst, src, tempCipherLen, iv, ctx->hash_subkey, assoc, (unsigned long)req->assoclen, authTag, auth_tag_len); /* Compare generated tag with passed in tag. */ - retval = memcmp(src + tempCipherLen, authTag, auth_tag_len) ? + retval = crypto_memneq(src + tempCipherLen, authTag, auth_tag_len) ? -EBADMSG : 0; if (one_entry_in_sg) { @@ -1353,6 +1473,27 @@ static int __init aesni_init(void) if (!x86_match_cpu(aesni_cpu_id)) return -ENODEV; +#ifdef CONFIG_X86_64 +#ifdef CONFIG_AS_AVX2 + if (boot_cpu_has(X86_FEATURE_AVX2)) { + pr_info("AVX2 version of gcm_enc/dec engaged.\n"); + aesni_gcm_enc_tfm = aesni_gcm_enc_avx2; + aesni_gcm_dec_tfm = aesni_gcm_dec_avx2; + } else +#endif +#ifdef CONFIG_AS_AVX + if (boot_cpu_has(X86_FEATURE_AVX)) { + pr_info("AVX version of gcm_enc/dec engaged.\n"); + aesni_gcm_enc_tfm = aesni_gcm_enc_avx; + aesni_gcm_dec_tfm = aesni_gcm_dec_avx; + } else +#endif + { + pr_info("SSE version of gcm_enc/dec engaged.\n"); + aesni_gcm_enc_tfm = aesni_gcm_enc; + aesni_gcm_dec_tfm = aesni_gcm_dec; + } +#endif err = crypto_fpu_init(); if (err) |
