diff options
Diffstat (limited to 'arch')
153 files changed, 1154 insertions, 3394 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1ad6fb6..e98261c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -358,7 +358,6 @@ config ARCH_AT91 bool "Atmel AT91" select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP - select HAVE_CLK select IRQ_DOMAIN select NEED_MACH_GPIO_H select NEED_MACH_IO_H if PCCARD @@ -372,7 +371,6 @@ config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" select ARCH_REQUIRE_GPIOLIB select AUTO_ZRELADDR - select CLKDEV_LOOKUP select CLKSRC_MMIO select COMMON_CLK select CPU_ARM720T @@ -386,8 +384,9 @@ config ARCH_CLPS711X config ARCH_GEMINI bool "Cortina Systems Gemini" select ARCH_REQUIRE_GPIOLIB - select ARCH_USES_GETTIMEOFFSET + select CLKSRC_MMIO select CPU_FA526 + select GENERIC_CLOCKEVENTS select NEED_MACH_GPIO_H help Support for the Cortina Systems Gemini family SoCs @@ -631,7 +630,6 @@ config ARCH_PXA config ARCH_MSM bool "Qualcomm MSM" select ARCH_REQUIRE_GPIOLIB - select CLKDEV_LOOKUP select CLKSRC_OF if OF select COMMON_CLK select GENERIC_CLOCKEVENTS @@ -649,7 +647,6 @@ config ARCH_SHMOBILE select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP - select HAVE_CLK select HAVE_MACH_CLKDEV select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 @@ -706,7 +703,6 @@ config ARCH_S3C24XX select CLKSRC_SAMSUNG_PWM select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG - select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -730,18 +726,19 @@ config ARCH_S3C64XX select CPU_V6 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG - select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_TCM select NEED_MACH_GPIO_H select NO_IOPORT select PLAT_SAMSUNG + select PM_GENERIC_DOMAINS select S3C_DEV_NAND select S3C_GPIO_TRACK select SAMSUNG_ATAGS select SAMSUNG_CLKSRC select SAMSUNG_GPIOLIB_4BIT + select SAMSUNG_WAKEMASK select SAMSUNG_WDT_RESET select USB_ARCH_HAS_OHCI help @@ -754,7 +751,6 @@ config ARCH_S5P64X0 select CPU_V6 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG - select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -773,7 +769,6 @@ config ARCH_S5PC100 select CPU_V7 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG - select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -793,7 +788,6 @@ config ARCH_S5PV210 select CPU_V7 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG - select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -810,11 +804,9 @@ config ARCH_EXYNOS select ARCH_REQUIRE_GPIOLIB select ARCH_SPARSEMEM_ENABLE select ARM_GIC - select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS - select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -824,20 +816,6 @@ config ARCH_EXYNOS help Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) -config ARCH_SHARK - bool "Shark" - select ARCH_USES_GETTIMEOFFSET - select CPU_SA110 - select ISA - select ISA_DMA - select NEED_MACH_MEMORY_H - select PCI - select VIRT_TO_BUS - select ZONE_DMA - help - Support for the StrongARM based Digital DNARD machine, also known - as "Shark" (<http://www.shark-linux.de/shark.html>). - config ARCH_DAVINCI bool "TI DaVinci" select ARCH_HAS_HOLES_MEMORYMODEL @@ -865,7 +843,6 @@ config ARCH_OMAP1 select CLKSRC_MMIO select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP - select HAVE_CLK select HAVE_IDE select IRQ_DOMAIN select NEED_MACH_IO_H if PCCARD @@ -1009,9 +986,7 @@ source "arch/arm/mach-sti/Kconfig" source "arch/arm/mach-s3c24xx/Kconfig" -if ARCH_S3C64XX source "arch/arm/mach-s3c64xx/Kconfig" -endif source "arch/arm/mach-s5p64x0/Kconfig" @@ -1431,12 +1406,6 @@ config PCI_NANOENGINE config PCI_SYSCALL def_bool PCI -# Select the host bridge type -config PCI_HOST_VIA82C505 - bool - depends on PCI && ARCH_SHARK - default y - config PCI_HOST_ITE8152 bool depends on PCI && MACH_ARMCORE diff --git a/arch/arm/Makefile b/arch/arm/Makefile index db50b62..8b66713 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -188,7 +188,6 @@ machine-$(CONFIG_ARCH_S5P64X0) += s5p64x0 machine-$(CONFIG_ARCH_S5PC100) += s5pc100 machine-$(CONFIG_ARCH_S5PV210) += s5pv210 machine-$(CONFIG_ARCH_SA1100) += sa1100 -machine-$(CONFIG_ARCH_SHARK) += shark machine-$(CONFIG_ARCH_SHMOBILE) += shmobile machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile machine-$(CONFIG_ARCH_SIRF) += prima2 diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 7ac1610..e7190bb 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -44,10 +44,6 @@ ifeq ($(CONFIG_ARCH_ACORN),y) OBJS += ll_char_wr.o font.o endif -ifeq ($(CONFIG_ARCH_SHARK),y) -OBJS += head-shark.o ofw-shark.o -endif - ifeq ($(CONFIG_ARCH_SA1100),y) OBJS += head-sa1100.o endif diff --git a/arch/arm/boot/compressed/head-shark.S b/arch/arm/boot/compressed/head-shark.S deleted file mode 100644 index 92b5689..0000000 --- a/arch/arm/boot/compressed/head-shark.S +++ /dev/null @@ -1,140 +0,0 @@ -/* The head-file for the Shark - * by Alexander Schulz - * - * Does the following: - * - get the memory layout from firmware. This can only be done as long as the mmu - * is still on. - * - switch the mmu off, so we have physical addresses - * - copy the kernel to 0x08508000. This is done to have a fixed address where the - * C-parts (misc.c) are executed. This address must be known at compile-time, - * but the load-address of the kernel depends on how much memory is installed. - * - Jump to this location. - * - Set r8 with 0, r7 with the architecture ID for head.S - */ - -#include <linux/linkage.h> - -#include <asm/assembler.h> - - .section ".start", "ax" - - .arch armv4 - b __beginning - -__ofw_data: .long 0 @ the number of memory blocks - .space 128 @ (startaddr,size) ... - .space 128 @ bootargs - .align - -__beginning: mov r4, r0 @ save the entry to the firmware - - mov r0, #0xC0 @ disable irq and fiq - mov r1, r0 - mrs r3, cpsr - bic r2, r3, r0 - eor r2, r2, r1 - msr cpsr_c, r2 - - mov r0, r4 @ get the Memory layout from firmware - adr r1, __ofw_data - add r2, r1, #4 - mov lr, pc - b ofw_init - mov r1, #0 - - adr r2, __mmu_off @ calculate physical address - sub r2, r2, #0xf0000000 @ openprom maps us at f000 virt, 0e50 phys - adr r0, __ofw_data - ldr r0, [r0, #4] - add r2, r2, r0 - add r2, r2, #0x00500000 - - mrc p15, 0, r3, c1, c0 - bic r3, r3, #0xC @ Write Buffer and DCache - bic r3, r3, #0x1000 @ ICache - mcr p15, 0, r3, c1, c0 @ disabled - - mov r0, #0 - mcr p15, 0, r0, c7, c7 @ flush I,D caches on v4 - mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 - mcr p15, 0, r0, c8, c7 @ flush I,D TLBs on v4 - - bic r3, r3, #0x1 @ MMU - mcr p15, 0, r3, c1, c0 @ disabled - - mov pc, r2 - -__copy_target: .long 0x08507FFC -__copy_end: .long 0x08607FFC - - .word _start - .word __bss_start - - .align -__temp_stack: .space 128 - -__mmu_off: - adr r0, __ofw_data @ read the 1. entry of the memory map - ldr r0, [r0, #4] - orr r0, r0, #0x00600000 - sub r0, r0, #4 - - ldr r1, __copy_end - ldr r3, __copy_target - -/* r0 = 0x0e600000 (current end of kernelcode) - * r3 = 0x08508000 (where it should begin) - * r1 = 0x08608000 (end of copying area, 1MB) - * The kernel is compressed, so 1 MB should be enough. - * copy the kernel to the beginning of physical memory - * We start from the highest address, so we can copy - * from 0x08500000 to 0x08508000 if we have only 8MB - */ - -/* As we get more 2.6-kernels it gets more and more - * uncomfortable to be bound to kernel images of 1MB only. - * So we add a loop here, to be able to copy some more. - * Alexander Schulz 2005-07-17 - */ - - mov r4, #3 @ How many megabytes to copy - - -__MoveCode: sub r4, r4, #1 - -__Copy: ldr r2, [r0], #-4 - str r2, [r1], #-4 - teq r1, r3 - bne __Copy - - /* The firmware maps us in blocks of 1 MB, the next block is - _below_ the last one. So our decrementing source pointer - ist right here, but the destination pointer must be increased - by 2 MB */ - add r1, r1, #0x00200000 - add r3, r3, #0x00100000 - - teq r4, #0 - bne __MoveCode - - - /* and jump to it */ - adr r2, __go_on @ where we want to jump - adr r0, __ofw_data @ read the 1. entry of the memory map - ldr r0, [r0, #4] - sub r2, r2, r0 @ we are mapped add 0e50 now, sub that (-0e00) - sub r2, r2, #0x00500000 @ -0050 - ldr r0, __copy_target @ and add 0850 8000 instead - add r0, r0, #4 - add r2, r2, r0 - mov pc, r2 @ and jump there - -__go_on: - adr sp, __temp_stack - add sp, sp, #128 - adr r0, __ofw_data - mov lr, pc - b create_params - - mov r8, #0 - mov r7, #15 diff --git a/arch/arm/boot/compressed/ofw-shark.c b/arch/arm/boot/compressed/ofw-shark.c deleted file mode 100644 index 465c54b..0000000 --- a/arch/arm/boot/compressed/ofw-shark.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * linux/arch/arm/boot/compressed/ofw-shark.c - * - * by Alexander Schulz - * - * This file is used to get some basic information - * about the memory layout of the shark we are running - * on. Memory is usually divided in blocks a 8 MB. - * And bootargs are copied from OpenFirmware. - */ - - -#include <linux/kernel.h> -#include <linux/types.h> -#include <asm/setup.h> -#include <asm/page.h> - - -asmlinkage void -create_params (unsigned long *buffer) -{ - /* Is there a better address? Also change in mach-shark/core.c */ - struct tag *tag = (struct tag *) 0x08003000; - int j,i,m,k,nr_banks,size; - unsigned char *c; - - k = 0; - - /* Head of the taglist */ - tag->hdr.tag = ATAG_CORE; - tag->hdr.size = tag_size(tag_core); - tag->u.core.flags = 1; - tag->u.core.pagesize = PAGE_SIZE; - tag->u.core.rootdev = 0; - - /* Build up one tagged block for each memory region */ - size=0; - nr_banks=(unsigned int) buffer[0]; - for (j=0;j<nr_banks;j++){ - /* search the lowest address and put it into the next entry */ - /* not a fast sort algorithm, but there are at most 8 entries */ - /* and this is used only once anyway */ - m=0xffffffff; - for (i=0;i<(unsigned int) buffer[0];i++){ - if (buffer[2*i+1]<m) { - m=buffer[2*i+1]; - k=i; - } - } - - tag = tag_next(tag); - tag->hdr.tag = ATAG_MEM; - tag->hdr.size = tag_size(tag_mem32); - tag->u.mem.size = buffer[2*k+2]; - tag->u.mem.start = buffer[2*k+1]; - - size += buffer[2*k+2]; - - buffer[2*k+1]=0xffffffff; /* mark as copied */ - } - - /* The command line */ - tag = tag_next(tag); - tag->hdr.tag = ATAG_CMDLINE; - - c=(unsigned char *)(&buffer[34]); - j=0; - while (*c) tag->u.cmdline.cmdline[j++]=*c++; - - tag->u.cmdline.cmdline[j]=0; - tag->hdr.size = (j + 7 + sizeof(struct tag_header)) >> 2; - - /* Hardware revision */ - tag = tag_next(tag); - tag->hdr.tag = ATAG_REVISION; - tag->hdr.size = tag_size(tag_revision); - tag->u.revision.rev = ((unsigned char) buffer[33])-'0'; - - /* End of the taglist */ - tag = tag_next(tag); - tag->hdr.tag = 0; - tag->hdr.size = 0; -} - - -typedef int (*ofw_handle_t)(void *); - -/* Everything below is called with a wrong MMU setting. - * This means: no string constants, no initialization of - * arrays, no global variables! This is ugly but I didn't - * want to write this in assembler :-) - */ - -int -of_decode_int(const unsigned char *p) -{ - unsigned int i = *p++ << 8; - i = (i + *p++) << 8; - i = (i + *p++) << 8; - return (i + *p); -} - -int -OF_finddevice(ofw_handle_t openfirmware, char *name) -{ - unsigned int args[8]; - char service[12]; - - service[0]='f'; - service[1]='i'; - service[2]='n'; - service[3]='d'; - service[4]='d'; - service[5]='e'; - service[6]='v'; - service[7]='i'; - service[8]='c'; - service[9]='e'; - service[10]='\0'; - - args[0]=(unsigned int)service; - args[1]=1; - args[2]=1; - args[3]=(unsigned int)name; - - if (openfirmware(args) == -1) - return -1; - return args[4]; -} - -int -OF_getproplen(ofw_handle_t openfirmware, int handle, char *prop) -{ - unsigned int args[8]; - char service[12]; - - service[0]='g'; - service[1]='e'; - service[2]='t'; - service[3]='p'; - service[4]='r'; - service[5]='o'; - service[6]='p'; - service[7]='l'; - service[8]='e'; - service[9]='n'; - service[10]='\0'; - - args[0] = (unsigned int)service; - args[1] = 2; - args[2] = 1; - args[3] = (unsigned int)handle; - args[4] = (unsigned int)prop; - - if (openfirmware(args) == -1) - return -1; - return args[5]; -} - -int -OF_getprop(ofw_handle_t openfirmware, int handle, char *prop, void *buf, unsigned int buflen) -{ - unsigned int args[8]; - char service[8]; - - service[0]='g'; - service[1]='e'; - service[2]='t'; - service[3]='p'; - service[4]='r'; - service[5]='o'; - service[6]='p'; - service[7]='\0'; - - args[0] = (unsigned int)service; - args[1] = 4; - args[2] = 1; - args[3] = (unsigned int)handle; - args[4] = (unsigned int)prop; - args[5] = (unsigned int)buf; - args[6] = buflen; - - if (openfirmware(args) == -1) - return -1; - return args[7]; -} - -asmlinkage void ofw_init(ofw_handle_t o, int *nomr, int *pointer) -{ - int phandle,i,mem_len,buffer[32]; - char temp[15]; - - temp[0]='/'; - temp[1]='m'; - temp[2]='e'; - temp[3]='m'; - temp[4]='o'; - temp[5]='r'; - temp[6]='y'; - temp[7]='\0'; - - phandle=OF_finddevice(o,temp); - - temp[0]='r'; - temp[1]='e'; - temp[2]='g'; - temp[3]='\0'; - - mem_len = OF_getproplen(o,phandle, temp); - OF_getprop(o,phandle, temp, buffer, mem_len); - *nomr=mem_len >> 3; - - for (i=0; i<=mem_len/4; i++) pointer[i]=of_decode_int((const unsigned char *)&buffer[i]); - - temp[0]='/'; - temp[1]='c'; - temp[2]='h'; - temp[3]='o'; - temp[4]='s'; - temp[5]='e'; - temp[6]='n'; - temp[7]='\0'; - - phandle=OF_finddevice(o,temp); - - temp[0]='b'; - temp[1]='o'; - temp[2]='o'; - temp[3]='t'; - temp[4]='a'; - temp[5]='r'; - temp[6]='g'; - temp[7]='s'; - temp[8]='\0'; - - mem_len = OF_getproplen(o,phandle, temp); - OF_getprop(o,phandle, temp, buffer, mem_len); - if (mem_len > 128) mem_len=128; - for (i=0; i<=mem_len/4; i++) pointer[i+33]=buffer[i]; - pointer[i+33]=0; - - temp[0]='/'; - temp[1]='\0'; - phandle=OF_finddevice(o,temp); - temp[0]='b'; - temp[1]='a'; - temp[2]='n'; - temp[3]='n'; - temp[4]='e'; - temp[5]='r'; - temp[6]='-'; - temp[7]='n'; - temp[8]='a'; - temp[9]='m'; - temp[10]='e'; - temp[11]='\0'; - mem_len = OF_getproplen(o,phandle, temp); - OF_getprop(o,phandle, temp, buffer, mem_len); - * ((unsigned char *) &pointer[32]) = ((unsigned char *) buffer)[mem_len-2]; -} diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 802720e..c485157 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -103,8 +103,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ kirkwood-ts219-6282.dtb \ kirkwood-openblocks_a6.dtb dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb -dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ - msm8960-cdp.dtb +dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \ + qcom-msm8960-cdp.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ armada-370-mirabox.dtb \ armada-370-netgear-rn102.dtb \ diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi index b4ec6fe..17b8799 100644 --- a/arch/arm/boot/dts/at91sam9g25.dtsi +++ b/arch/arm/boot/dts/at91sam9g25.dtsi @@ -7,6 +7,8 @@ */ #include "at91sam9x5.dtsi" +#include "at91sam9x5_usart3.dtsi" +#include "at91sam9x5_macb0.dtsi" / { model = "Atmel AT91SAM9G25 SoC"; diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi index bebf9f5..e35c2fc 100644 --- a/arch/arm/boot/dts/at91sam9g35.dtsi +++ b/arch/arm/boot/dts/at91sam9g35.dtsi @@ -7,6 +7,7 @@ */ #include "at91sam9x5.dtsi" +#include "at91sam9x5_macb0.dtsi" / { model = "Atmel AT91SAM9G35 SoC"; diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi index 49e94ab..c255421 100644 --- a/arch/arm/boot/dts/at91sam9x25.dtsi +++ b/arch/arm/boot/dts/at91sam9x25.dtsi @@ -7,6 +7,9 @@ */ #include "at91sam9x5.dtsi" +#include "at91sam9x5_usart3.dtsi" +#include "at91sam9x5_macb0.dtsi" +#include "at91sam9x5_macb1.dtsi" / { model = "Atmel AT91SAM9X25 SoC"; @@ -22,27 +25,6 @@ 0x80000000 0xfffd0000 0xb83fffff /* pioC */ 0x003fffff 0x003f8000 0x00000000 /* pioD */ >; - - macb1 { - pinctrl_macb1_rmii: macb1_rmii-0 { - atmel,pins = - <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */ - AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */ - AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */ - AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ - AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ - AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ - AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */ - AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */ - AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */ - AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */ - }; - }; - }; - - macb1: ethernet@f8030000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb1_rmii>; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi index 1a3d525..8eac66c 100644 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ b/arch/arm/boot/dts/at91sam9x35.dtsi @@ -7,6 +7,7 @@ */ #include "at91sam9x5.dtsi" +#include "at91sam9x5_macb0.dtsi" / { model = "Atmel AT91SAM9X35 SoC"; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index e74dc15..40267a1 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -206,29 +206,6 @@ }; }; - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */ - AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */ - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ - }; - - pinctrl_usart3_sck: usart3_sck-0 { - atmel,pins = - <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */ - }; - }; - uart0 { pinctrl_uart0: uart0-0 { atmel,pins = @@ -277,34 +254,6 @@ }; }; - macb0 { - pinctrl_macb0_rmii: macb0_rmii-0 { - atmel,pins = - <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ - AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ - AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ - AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ - AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ - AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ - AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ - AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ - AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ - AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ - }; - - pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { - atmel,pins = - <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */ - AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */ - AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ - AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ - AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ - AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ - AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ - AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ - }; - }; - mmc0 { pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { atmel,pins = @@ -610,22 +559,6 @@ status = "disabled"; }; - macb0: ethernet@f802c000 { - compatible = "cdns,at32ap7000-macb", "cdns,macb"; - reg = <0xf802c000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii>; - status = "disabled"; - }; - - macb1: ethernet@f8030000 { - compatible = "cdns,at32ap7000-macb", "cdns,macb"; - reg = <0xf8030000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; - status = "disabled"; - }; - i2c0: i2c@f8010000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8010000 0x100>; diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi new file mode 100644 index 0000000..55731ff --- /dev/null +++ b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi @@ -0,0 +1,56 @@ +/* + * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 + * Ethernet interface. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff400 { + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ + }; + + pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { + atmel,pins = + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */ + AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ + }; + }; + }; + + macb0: ethernet@f802c000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi new file mode 100644 index 0000000..77425a6 --- /dev/null +++ b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi @@ -0,0 +1,44 @@ +/* + * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2 + * Ethernet interfaces. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff400 { + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */ + AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */ + AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */ + AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ + AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ + AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ + AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */ + AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */ + AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */ + AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */ + }; + }; + }; + + macb1: ethernet@f8030000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xf8030000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file mode 100644 index 0000000..2347e95 --- /dev/null +++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi @@ -0,0 +1,51 @@ +/* + * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * 4 USART. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff400 { + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */ + AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */ + }; + + pinctrl_usart3_rts: usart3_rts-0 { + atmel,pins = + <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ + }; + + pinctrl_usart3_cts: usart3_cts-0 { + atmel,pins = + <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ + }; + + pinctrl_usart3_sck: usart3_sck-0 { + atmel,pins = + <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */ + }; + }; + }; + + usart3: serial@f8028000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8028000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts index 386d428..386d428 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 93e9f7e..93e9f7e 100644 --- a/arch/arm/boot/dts/msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index b7f4961..5cdaba4 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -31,7 +31,6 @@ gpio3 = &pioD; gpio4 = &pioE; tcb0 = &tcb0; - tcb1 = &tcb1; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -105,15 +104,6 @@ status = "disabled"; }; - can0: can@f000c000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf000c000 0x300>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_rx_tx>; - status = "disabled"; - }; - tcb0: timer@f0010000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf0010000 0x100>; @@ -166,15 +156,6 @@ status = "disabled"; }; - macb0: ethernet@f0028000 { - compatible = "cdns,pc302-gem", "cdns,gem"; - reg = <0xf0028000 0x100>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; - status = "disabled"; - }; - isi: isi@f0034000 { compatible = "atmel,at91sam9g45-isi"; reg = <0xf0034000 0x4000>; @@ -195,19 +176,6 @@ #size-cells = <0>; }; - mmc2: mmc@f8004000 { - compatible = "atmel,hsmci"; - reg = <0xf8004000 0x600>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - spi1: spi@f8008000 { #address-cells = <1>; #size-cells = <0>; @@ -231,20 +199,6 @@ status = "disabled"; }; - can1: can@f8010000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf8010000 0x300>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_rx_tx>; - }; - - tcb1: timer@f8014000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xf8014000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - }; - adc0: adc@f8018000 { compatible = "atmel,at91sam9260-adc"; reg = <0xf8018000 0x100>; @@ -341,15 +295,6 @@ status = "disabled"; }; - macb1: ethernet@f802c000 { - compatible = "cdns,at32ap7000-macb", "cdns,macb"; - reg = <0xf802c000 0x100>; - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb1_rmii>; - status = "disabled"; - }; - sha@f8034000 { compatible = "atmel,sam9g46-sha"; reg = <0xf8034000 0x100>; @@ -474,22 +419,6 @@ }; }; - can0 { - pinctrl_can0_rx_tx: can0_rx_tx { - atmel,pins = - <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ - AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ - }; - }; - - can1 { - pinctrl_can1_rx_tx: can1_rx_tx { - atmel,pins = - <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */ - AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */ - }; - }; - dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = @@ -537,107 +466,6 @@ }; }; - lcd { - pinctrl_lcd: lcd-0 { - atmel,pins = - <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */ - AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */ - AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */ - AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */ - AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */ - AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */ - AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */ - AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */ - AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */ - AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */ - AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */ - AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */ - AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */ - AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */ - AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */ - AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */ - AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */ - AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */ - AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */ - AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */ - AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */ - AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */ - AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */ - AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */ - AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */ - AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */ - AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */ - AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */ - AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */ - AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */ - }; - }; - - macb0 { - pinctrl_macb0_data_rgmii: macb0_data_rgmii { - atmel,pins = - <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */ - AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */ - AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */ - AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */ - AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */ - AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */ - AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */ - AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */ - }; - pinctrl_macb0_data_gmii: macb0_data_gmii { - atmel,pins = - <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */ - AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ - AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ - AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ - AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ - AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */ - AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */ - AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */ - }; - pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { - atmel,pins = - <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */ - AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ - AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ - AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ - AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ - AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ - AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */ - }; - pinctrl_macb0_signal_gmii: macb0_signal_gmii { - atmel,pins = - <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ - AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */ - AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ - AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */ - AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ - AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */ - AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */ - AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ - AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ - AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */ - }; - - }; - - macb1 { - pinctrl_macb1_rmii: macb1_rmii-0 { - atmel,pins = - <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */ - AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */ - AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */ - AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */ - AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */ - AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */ - AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */ - AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */ - AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */ - AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */ - }; - }; - mmc0 { pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { atmel,pins = @@ -675,21 +503,6 @@ }; }; - mmc2 { - pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { - atmel,pins = - <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */ - AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */ - AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */ - }; - pinctrl_mmc2_dat1_3: mmc2_dat1_3 { - atmel,pins = - <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ - AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ - AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ - }; - }; - nand0 { pinctrl_nand0_ale_cle: nand0_ale_cle-0 { atmel,pins = @@ -748,22 +561,6 @@ }; }; - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ - AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ - AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ - }; - }; - usart0 { pinctrl_usart0: usart0-0 { atmel,pins = diff --git a/arch/arm/boot/dts/sama5d31.dtsi b/arch/arm/boot/dts/sama5d31.dtsi new file mode 100644 index 0000000..7997dc9 --- /dev/null +++ b/arch/arm/boot/dts/sama5d31.dtsi @@ -0,0 +1,16 @@ +/* + * sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_emac.dtsi" +#include "sama5d3_mci2.dtsi" +#include "sama5d3_uart.dtsi" + +/ { + compatible = "atmel,samad31", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts index 027bac7..04eec0d 100644 --- a/arch/arm/boot/dts/sama5d31ek.dts +++ b/arch/arm/boot/dts/sama5d31ek.dts @@ -7,12 +7,13 @@ * Licensed under GPLv2 or later. */ /dts-v1/; +#include "sama5d31.dtsi" #include "sama5d3xmb.dtsi" #include "sama5d3xdm.dtsi" / { model = "Atmel SAMA5D31-EK"; - compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; ahb { apb { diff --git a/arch/arm/boot/dts/sama5d33.dtsi b/arch/arm/boot/dts/sama5d33.dtsi new file mode 100644 index 0000000..39f8322 --- /dev/null +++ b/arch/arm/boot/dts/sama5d33.dtsi @@ -0,0 +1,14 @@ +/* + * sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_gmac.dtsi" + +/ { + compatible = "atmel,samad33", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts index 99bd0c8..cbd6a3f 100644 --- a/arch/arm/boot/dts/sama5d33ek.dts +++ b/arch/arm/boot/dts/sama5d33ek.dts @@ -7,12 +7,13 @@ * Licensed under GPLv2 or later. */ /dts-v1/; +#include "sama5d33.dtsi" #include "sama5d3xmb.dtsi" #include "sama5d3xdm.dtsi" / { model = "Atmel SAMA5D33-EK"; - compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; ahb { apb { diff --git a/arch/arm/boot/dts/sama5d34.dtsi b/arch/arm/boot/dts/sama5d34.dtsi new file mode 100644 index 0000000..89cda2c --- /dev/null +++ b/arch/arm/boot/dts/sama5d34.dtsi @@ -0,0 +1,16 @@ +/* + * sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_gmac.dtsi" +#include "sama5d3_can.dtsi" +#include "sama5d3_mci2.dtsi" + +/ { + compatible = "atmel,samad34", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts index fb8ee11..878aa16 100644 --- a/arch/arm/boot/dts/sama5d34ek.dts +++ b/arch/arm/boot/dts/sama5d34ek.dts @@ -7,12 +7,13 @@ * Licensed under GPLv2 or later. */ /dts-v1/; +#include "sama5d34.dtsi" #include "sama5d3xmb.dtsi" #include "sama5d3xdm.dtsi" / { model = "Atmel SAMA5D34-EK"; - compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; ahb { apb { diff --git a/arch/arm/boot/dts/sama5d35.dtsi b/arch/arm/boot/dts/sama5d35.dtsi new file mode 100644 index 0000000..d20cd71 --- /dev/null +++ b/arch/arm/boot/dts/sama5d35.dtsi @@ -0,0 +1,18 @@ +/* + * sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_gmac.dtsi" +#include "sama5d3_emac.dtsi" +#include "sama5d3_can.dtsi" +#include "sama5d3_mci2.dtsi" +#include "sama5d3_uart.dtsi" +#include "sama5d3_tcb1.dtsi" + +/ { + compatible = "atmel,samad35", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts index 509a53d..9089c7c 100644 --- a/arch/arm/boot/dts/sama5d35ek.dts +++ b/arch/arm/boot/dts/sama5d35ek.dts @@ -7,11 +7,12 @@ * Licensed under GPLv2 or later. */ /dts-v1/; +#include "sama5d35.dtsi" #include "sama5d3xmb.dtsi" / { model = "Atmel SAMA5D35-EK"; - compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; ahb { apb { diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi new file mode 100644 index 0000000..8ed3260 --- /dev/null +++ b/arch/arm/boot/dts/sama5d3_can.dtsi @@ -0,0 +1,54 @@ +/* + * at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * CAN support + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff200 { + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ + AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */ + AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */ + }; + }; + + }; + + can0: can@f000c000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf000c000 0x300>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + status = "disabled"; + }; + + can1: can@f8010000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8010000 0x300>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi new file mode 100644 index 0000000..4d4f351 --- /dev/null +++ b/arch/arm/boot/dts/sama5d3_emac.dtsi @@ -0,0 +1,44 @@ +/* + * at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * Ethernet. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff200 { + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */ + }; + }; + }; + + macb1: ethernet@f802c000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi new file mode 100644 index 0000000..0ba8be3 --- /dev/null +++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi @@ -0,0 +1,77 @@ +/* + * at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * Gigabit Ethernet. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff200 { + macb0 { + pinctrl_macb0_data_rgmii: macb0_data_rgmii { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */ + }; + pinctrl_macb0_data_gmii: macb0_data_gmii { + atmel,pins = + <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */ + AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ + AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ + AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ + AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ + AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */ + AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */ + AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */ + }; + pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { + atmel,pins = + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ + AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */ + }; + pinctrl_macb0_signal_gmii: macb0_signal_gmii { + atmel,pins = + <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ + AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ + AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */ + }; + + }; + }; + + macb0: ethernet@f0028000 { + compatible = "cdns,pc302-gem", "cdns,gem"; + reg = <0xf0028000 0x100>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi new file mode 100644 index 0000000..01f52a7 --- /dev/null +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi @@ -0,0 +1,55 @@ +/* + * at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * LCD support + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff200 { + lcd { + pinctrl_lcd: lcd-0 { + atmel,pins = + <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */ + AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */ + AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */ + AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */ + AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */ + AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */ + AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */ + AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */ + AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */ + AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */ + AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */ + AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */ + AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */ + AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */ + AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */ + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi new file mode 100644 index 0000000..38e88e3 --- /dev/null +++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi @@ -0,0 +1,47 @@ +/* + * at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * 3 MMC ports + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff200 { + mmc2 { + pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { + atmel,pins = + <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */ + }; + pinctrl_mmc2_dat1_3: mmc2_dat1_3 { + atmel,pins = + <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ + AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ + }; + }; + }; + + mmc2: mmc@f8004000 { + compatible = "atmel,hsmci"; + reg = <0xf8004000 0x600>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi new file mode 100644 index 0000000..5264bb4 --- /dev/null +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi @@ -0,0 +1,27 @@ +/* + * at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * 2 TC blocks. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + aliases { + tcb1 = &tcb1; + }; + + ahb { + apb { + tcb1: timer@f8014000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8014000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi new file mode 100644 index 0000000..98fcb2d --- /dev/null +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi @@ -0,0 +1,53 @@ +/* + * at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * UART support + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff200 { + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ + AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ + AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ + }; + }; + }; + + uart0: serial@f0024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf0024000 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "disabled"; + }; + + uart1: serial@f8028000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8028000 0x200>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 31ed9e3..726a0f3 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -6,7 +6,6 @@ * * Licensed under GPLv2 or later. */ -#include "sama5d3.dtsi" / { compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 9169d30..79425e3 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -653,6 +653,7 @@ reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; clocks = <&hclksmc>; status = "okay"; + timings = /bits/ 8 <0 0 0 0x10 0x0a 0>; partition@0 { label = "X-Loader(NAND)"; @@ -707,8 +708,14 @@ pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; stw4811@2d { - compatible = "st,stw4811"; - reg = <0x2d>; + compatible = "st,stw4811"; + reg = <0x2d>; + vmmc_regulator: vmmc { + compatible = "st,stw481x-vmmc"; + regulator-name = "VMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; }; }; @@ -839,6 +846,7 @@ cd-inverted; pinctrl-names = "default"; pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; + vmmc-supply = <&vmmc_regulator>; }; }; }; diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 8c60f47..eaa9cf4 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -6,7 +6,6 @@ obj-y += firmware.o obj-$(CONFIG_ICST) += icst.o obj-$(CONFIG_SA1111) += sa1111.o -obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o obj-$(CONFIG_DMABOUNCE) += dmabounce.o obj-$(CONFIG_SHARP_LOCOMO) += locomo.o obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o diff --git a/arch/arm/common/via82c505.c b/arch/arm/common/via82c505.c deleted file mode 100644 index 6cb362e5..0000000 --- a/arch/arm/common/via82c505.c +++ /dev/null @@ -1,83 +0,0 @@ -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/interrupt.h> -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/ioport.h> -#include <linux/io.h> - - -#include <asm/mach/pci.h> - -#define MAX_SLOTS 7 - -#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) - -static int -via82c505_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - outl(CONFIG_CMD(bus,devfn,where),0xCF8); - switch (size) { - case 1: - *value=inb(0xCFC + (where&3)); - break; - case 2: - *value=inw(0xCFC + (where&2)); - break; - case 4: - *value=inl(0xCFC); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -static int -via82c505_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 value) -{ - outl(CONFIG_CMD(bus,devfn,where),0xCF8); - switch (size) { - case 1: - outb(value, 0xCFC + (where&3)); - break; - case 2: - outw(value, 0xCFC + (where&2)); - break; - case 4: - outl(value, 0xCFC); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops via82c505_ops = { - .read = via82c505_read_config, - .write = via82c505_write_config, -}; - -void __init via82c505_preinit(void) -{ - printk(KERN_DEBUG "PCI: VIA 82c505\n"); - if (!request_region(0xA8,2,"via config")) { - printk(KERN_WARNING"VIA 82c505: Unable to request region 0xA8\n"); - return; - } - if (!request_region(0xCF8,8,"pci config")) { - printk(KERN_WARNING"VIA 82c505: Unable to request region 0xCF8\n"); - release_region(0xA8, 2); - return; - } - - /* Enable compatible Mode */ - outb(0x96,0xA8); - outb(0x18,0xA9); - outb(0x93,0xA8); - outb(0xd0,0xA9); - -} - -int __init via82c505_setup(int nr, struct pci_sys_data *sys) -{ - return (nr == 0); -} diff --git a/arch/arm/configs/shark_defconfig b/arch/arm/configs/shark_defconfig deleted file mode 100644 index e319b2c..0000000 --- a/arch/arm/configs/shark_defconfig +++ /dev/null @@ -1,80 +0,0 @@ -CONFIG_EXPERIMENTAL=y -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_SHARK=y -CONFIG_LEDS=y -CONFIG_LEDS_TIMER=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_FPE_NWFPE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_STANDALONE is not set -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_PARPORT=m -CONFIG_PARPORT_PC=m -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECD=m -CONFIG_SCSI=m -CONFIG_BLK_DEV_SD=m -CONFIG_CHR_DEV_ST=m -CONFIG_BLK_DEV_SR=m -CONFIG_CHR_DEV_SG=m -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_NET_PCI=y -CONFIG_CS89x0=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_PRINTER=m -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_FB_CYBER2000=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=m -CONFIG_SOUND_PRIME=m -CONFIG_SOUND_OSS=m -CONFIG_SOUND_SB=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_CMOS=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFSD=m -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_ISO8859_1=m -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_USER=y diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 454d642..7fc4278 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -106,8 +106,4 @@ extern int dc21285_setup(int nr, struct pci_sys_data *); extern void dc21285_preinit(void); extern void dc21285_postinit(void); -extern struct pci_ops via82c505_ops; -extern int via82c505_setup(int nr, struct pci_sys_data *); -extern void via82c505_init(void *sysdata); - #endif /* __ASM_MACH_PCI_H */ diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sched_clock.h deleted file mode 100644 index 2389b71..0000000 --- a/arch/arm/include/asm/sched_clock.h +++ /dev/null @@ -1,4 +0,0 @@ -/* You shouldn't include this file. Use linux/sched_clock.h instead. - * Temporary file until all asm/sched_clock.h users are gone - */ -#include <linux/sched_clock.h> diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 98aee32..829a96d 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -11,25 +11,26 @@ * This file contains the ARM-specific time handling details: * reading the RTC at bootup, etc... */ +#include <linux/clk-provider.h> +#include <linux/clocksource.h> +#include <linux/errno.h> #include <linux/export.h> -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/time.h> #include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/kernel.h> +#include <linux/profile.h> #include <linux/sched.h> +#include <linux/sched_clock.h> #include <linux/smp.h> +#include <linux/time.h> #include <linux/timex.h> -#include <linux/errno.h> -#include <linux/profile.h> #include <linux/timer.h> -#include <linux/clocksource.h> -#include <linux/irq.h> -#include <linux/sched_clock.h> -#include <asm/thread_info.h> -#include <asm/stacktrace.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> +#include <asm/stacktrace.h> +#include <asm/thread_info.h> #if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE) || \ defined(CONFIG_NVRAM) || defined(CONFIG_NVRAM_MODULE) @@ -116,8 +117,12 @@ int __init register_persistent_clock(clock_access_fn read_boot, void __init time_init(void) { - if (machine_desc->init_time) + if (machine_desc->init_time) { machine_desc->init_time(); - else + } else { +#ifdef CONFIG_COMMON_CLK + of_clk_init(NULL); +#endif clocksource_of_init(); + } } diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index bd454b0..47d7338 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -41,7 +41,6 @@ else endif lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o -lib-$(CONFIG_ARCH_SHARK) += io-shark.o $(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S $(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S diff --git a/arch/arm/lib/io-shark.c b/arch/arm/lib/io-shark.c deleted file mode 100644 index 8242539..0000000 --- a/arch/arm/lib/io-shark.c +++ /dev/null @@ -1,13 +0,0 @@ -/* - * linux/arch/arm/lib/io-shark.c - * - * by Alexander Schulz - * - * derived from: - * linux/arch/arm/lib/io-ebsa.S - * Copyright (C) 1995, 1996 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c index ade948b..112e867 100644 --- a/arch/arm/mach-at91/board-cam60.c +++ b/arch/arm/mach-at91/board-cam60.c @@ -112,7 +112,7 @@ static struct spi_board_info cam60_spi_devices[] __initdata = { /* * MACB Ethernet device */ -static struct __initdata macb_platform_data cam60_macb_data = { +static struct macb_platform_data cam60_macb_data __initdata = { .phy_irq_pin = AT91_PIN_PB5, .is_rmii = 0, }; diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c index 3fcb662..3a185fa 100644 --- a/arch/arm/mach-at91/board-dt-rm9200.c +++ b/arch/arm/mach-at91/board-dt-rm9200.c @@ -14,7 +14,6 @@ #include <linux/gpio.h> #include <linux/of.h> #include <linux/of_irq.h> -#include <linux/of_platform.h> #include <asm/setup.h> #include <asm/irq.h> @@ -36,11 +35,6 @@ static void __init at91rm9200_dt_init_irq(void) of_irq_init(irq_of_match); } -static void __init at91rm9200_dt_device_init(void) -{ - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - static const char *at91rm9200_dt_board_compat[] __initdata = { "atmel,at91rm9200", NULL @@ -52,6 +46,5 @@ DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)") .handle_irq = at91_aic_handle_irq, .init_early = at91rm9200_dt_initialize, .init_irq = at91rm9200_dt_init_irq, - .init_machine = at91rm9200_dt_device_init, .dt_compat = at91rm9200_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c index 8db3013..3dab868 100644 --- a/arch/arm/mach-at91/board-dt-sam9.c +++ b/arch/arm/mach-at91/board-dt-sam9.c @@ -13,7 +13,6 @@ #include <linux/gpio.h> #include <linux/of.h> #include <linux/of_irq.h> -#include <linux/of_platform.h> #include <asm/setup.h> #include <asm/irq.h> @@ -37,11 +36,6 @@ static void __init at91_dt_init_irq(void) of_irq_init(irq_of_match); } -static void __init at91_dt_device_init(void) -{ - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - static const char *at91_dt_board_compat[] __initdata = { "atmel,at91sam9", NULL @@ -54,6 +48,5 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)") .handle_irq = at91_aic_handle_irq, .init_early = at91_dt_initialize, .init_irq = at91_dt_init_irq, - .init_machine = at91_dt_device_init, .dt_compat = at91_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-bcm/board_bcm281xx.c b/arch/arm/mach-bcm/board_bcm281xx.c index 8d9f931..26b2390 100644 --- a/arch/arm/mach-bcm/board_bcm281xx.c +++ b/arch/arm/mach-bcm/board_bcm281xx.c @@ -68,7 +68,6 @@ static void __init board_init(void) static const char * const bcm11351_dt_compat[] = { "brcm,bcm11351", NULL, }; DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor") - .init_time = clocksource_of_init, .init_machine = board_init, .restart = bcm_kona_restart, .dt_compat = bcm11351_dt_compat, diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c index 40686d7..d50135b 100644 --- a/arch/arm/mach-bcm2835/bcm2835.c +++ b/arch/arm/mach-bcm2835/bcm2835.c @@ -18,7 +18,6 @@ #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/clk/bcm2835.h> -#include <linux/clocksource.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -134,7 +133,6 @@ DT_MACHINE_START(BCM2835, "BCM2835") .init_irq = bcm2835_init_irq, .handle_irq = bcm2835_handle_irq, .init_machine = bcm2835_init, - .init_time = clocksource_of_init, .restart = bcm2835_restart, .dt_compat = bcm2835_compat MACHINE_END diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index 4ca2f3c..134641d 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c @@ -29,12 +29,12 @@ #include <linux/clockchips.h> #include <linux/clocksource.h> #include <linux/clk-provider.h> +#include <linux/sched_clock.h> #include <asm/exception.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <asm/sched_clock.h> #include <asm/system_misc.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c index 49f72a8..ddb8663 100644 --- a/arch/arm/mach-dove/board-dt.c +++ b/arch/arm/mach-dove/board-dt.c @@ -10,17 +10,13 @@ #include <linux/init.h> #include <linux/clk-provider.h> -#include <linux/clocksource.h> -#include <linux/irqchip.h> #include <linux/of.h> #include <linux/of_platform.h> -#include <linux/platform_data/usb-ehci-orion.h> #include <asm/hardware/cache-tauros2.h> #include <asm/mach/arch.h> #include <mach/dove.h> #include <mach/pm.h> #include <plat/common.h> -#include <plat/irq.h> #include "common.h" /* @@ -45,12 +41,6 @@ static void __init dove_legacy_clk_init(void) of_clk_get_from_provider(&clkspec)); } -static void __init dove_dt_time_init(void) -{ - of_clk_init(NULL); - clocksource_of_init(); -} - static void __init dove_dt_init_early(void) { mvebu_mbus_init("marvell,dove-mbus", @@ -84,7 +74,6 @@ static const char * const dove_dt_board_compat[] = { DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)") .map_io = dove_map_io, .init_early = dove_dt_init_early, - .init_time = dove_dt_time_init, .init_machine = dove_dt_init, .restart = dove_restart, .dt_compat = dove_dt_board_compat, diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 56fe819..f9d67a0 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -14,19 +14,28 @@ menu "SAMSUNG EXYNOS SoCs Support" config ARCH_EXYNOS4 bool "SAMSUNG EXYNOS4" default y + select ARM_AMBA + select CLKSRC_OF + select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 + select CPU_EXYNOS4210 select GIC_NON_BANKED + select KEYBOARD_SAMSUNG if INPUT_KEYBOARD select HAVE_ARM_SCU if SMP select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL + select S5P_DEV_MFC help Samsung EXYNOS4 SoCs based systems config ARCH_EXYNOS5 bool "SAMSUNG EXYNOS5" + select ARM_AMBA + select CLKSRC_OF select HAVE_ARM_SCU if SMP select HAVE_SMP select PINCTRL + select USB_ARCH_HAS_XHCI help Samsung EXYNOS5 (Cortex-A15) SoC based systems @@ -110,35 +119,6 @@ config SOC_EXYNOS5440 help Enable EXYNOS5440 SoC support -comment "Flattened Device Tree based board for EXYNOS SoCs" - -config MACH_EXYNOS4_DT - bool "Samsung Exynos4 Machine using device tree" - default y - depends on ARCH_EXYNOS4 - select ARM_AMBA - select CLKSRC_OF - select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 - select CPU_EXYNOS4210 - select KEYBOARD_SAMSUNG if INPUT_KEYBOARD - select S5P_DEV_MFC - help - Machine support for Samsung Exynos4 machine with device tree enabled. - Select this if a fdt blob is available for the Exynos4 SoC based board. - Note: This is under development and not all peripherals can be supported - with this machine file. - -config MACH_EXYNOS5_DT - bool "SAMSUNG EXYNOS5 Machine using device tree" - default y - depends on ARCH_EXYNOS5 - select ARM_AMBA - select CLKSRC_OF - select USB_ARCH_HAS_XHCI - help - Machine support for Samsung EXYNOS5 machine with device tree enabled. - Select this if a fdt blob is available for the EXYNOS5 SoC based board. - endmenu endif diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 5369615..8930b66 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -32,5 +32,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec) # machine support -obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o -obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o +obj-$(CONFIG_ARCH_EXYNOS4) += mach-exynos4-dt.o +obj-$(CONFIG_ARCH_EXYNOS5) += mach-exynos5-dt.o diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index ba95e5d..a4e7ba8 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -26,8 +26,6 @@ #include <linux/export.h> #include <linux/irqdomain.h> #include <linux/of_address.h> -#include <linux/clocksource.h> -#include <linux/clk-provider.h> #include <linux/irqchip/arm-gic.h> #include <linux/irqchip/chained_irq.h> @@ -367,12 +365,6 @@ static void __init exynos5_map_io(void) iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); } -void __init exynos_init_time(void) -{ - of_clk_init(NULL); - clocksource_of_init(); -} - struct bus_type exynos_subsys = { .name = "exynos-core", .dev_name = "exynos-core", diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 8646a14..f0fa205 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -16,7 +16,6 @@ #include <linux/of.h> void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); -void exynos_init_time(void); struct map_desc; void exynos_init_io(void); diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index 0099c6c..4b8f6e2 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -11,12 +11,8 @@ * published by the Free Software Foundation. */ -#include <linux/kernel.h> #include <linux/of_platform.h> #include <linux/of_fdt.h> -#include <linux/serial_core.h> -#include <linux/memblock.h> -#include <linux/clocksource.h> #include <asm/mach/arch.h> #include <plat/mfc.h> @@ -54,7 +50,6 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") .init_early = exynos_firmware_init, .init_machine = exynos4_dt_machine_init, .init_late = exynos_init_late, - .init_time = exynos_init_time, .dt_compat = exynos4_dt_compat, .restart = exynos4_restart, .reserve = exynos4_reserve, diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index f874b77..7976ab3 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -11,14 +11,10 @@ #include <linux/of_platform.h> #include <linux/of_fdt.h> -#include <linux/memblock.h> #include <linux/io.h> -#include <linux/clocksource.h> #include <asm/mach/arch.h> #include <mach/regs-pmu.h> - -#include <plat/cpu.h> #include <plat/mfc.h> #include "common.h" @@ -76,7 +72,6 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") .map_io = exynos_init_io, .init_machine = exynos5_dt_machine_init, .init_late = exynos_init_late, - .init_time = exynos_init_time, .dt_compat = exynos5_dt_compat, .restart = exynos5_restart, .reserve = exynos5_reserve, diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c index 21dc5a8..0a63c4d2 100644 --- a/arch/arm/mach-gemini/time.c +++ b/arch/arm/mach-gemini/time.c @@ -13,6 +13,8 @@ #include <mach/hardware.h> #include <mach/global_reg.h> #include <asm/mach/time.h> +#include <linux/clockchips.h> +#include <linux/clocksource.h> /* * Register definitions for the timers @@ -33,19 +35,89 @@ #define TIMER_3_CR_CLOCK (1 << 7) #define TIMER_3_CR_INT (1 << 8) +static unsigned int tick_rate; + +static int gemini_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + u32 cr; + + cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + + /* This may be overdoing it, feel free to test without this */ + cr &= ~TIMER_2_CR_ENABLE; + cr &= ~TIMER_2_CR_INT; + writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + + /* Set next event */ + writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); + writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); + cr |= TIMER_2_CR_ENABLE; + cr |= TIMER_2_CR_INT; + writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + + return 0; +} + +static void gemini_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ); + u32 cr; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* Start the timer */ + writel(period, + TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); + writel(period, + TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); + cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + cr |= TIMER_2_CR_ENABLE; + cr |= TIMER_2_CR_INT; + writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + break; + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: + /* + * Disable also for oneshot: the set_next() call will + * arm the timer instead. + */ + cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + cr &= ~TIMER_2_CR_ENABLE; + cr &= ~TIMER_2_CR_INT; + writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + break; + default: + break; + } +} + +/* Use TIMER2 as clock event */ +static struct clock_event_device gemini_clockevent = { + .name = "TIMER2", + .rating = 300, /* Reasonably fast and accurate clock event */ + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = gemini_timer_set_next_event, + .set_mode = gemini_timer_set_mode, +}; + /* * IRQ handler for the timer */ static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id) { - timer_tick(); + struct clock_event_device *evt = &gemini_clockevent; + evt->event_handler(evt); return IRQ_HANDLED; } static struct irqaction gemini_timer_irq = { .name = "Gemini Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER, + .flags = IRQF_TIMER, .handler = gemini_timer_interrupt, }; @@ -54,9 +126,9 @@ static struct irqaction gemini_timer_irq = { */ void __init gemini_timer_init(void) { - unsigned int tick_rate, reg_v; + u32 reg_v; - reg_v = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS)); + reg_v = readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS)); tick_rate = REG_TO_AHB_SPEED(reg_v) * 1000000; printk(KERN_INFO "Bus: %dMHz", tick_rate / 1000000); @@ -82,8 +154,17 @@ void __init gemini_timer_init(void) * Make irqs happen for the system timer */ setup_irq(IRQ_TIMER2, &gemini_timer_irq); - /* Start the timer */ - __raw_writel(tick_rate / HZ, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); - __raw_writel(tick_rate / HZ, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); - __raw_writel(TIMER_2_CR_ENABLE | TIMER_2_CR_INT, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + + /* Enable and use TIMER1 as clock source */ + writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE))); + writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE))); + writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)), + "TIMER1", tick_rate, 300, 32, + clocksource_mmio_readl_up)) + pr_err("timer: failed to initialize gemini clock source\n"); + + /* Configure and register the clockevent */ + clockevents_config_and_register(&gemini_clockevent, tick_rate, + 1, 0xffffffff); } diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig index 8e8437d..616408d 100644 --- a/arch/arm/mach-highbank/Kconfig +++ b/arch/arm/mach-highbank/Kconfig @@ -12,7 +12,6 @@ config ARCH_HIGHBANK select ARM_GIC select ARM_TIMER_SP804 select CACHE_L2X0 - select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index 8e63ccd..e6d6eac 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c @@ -24,7 +24,6 @@ #include <linux/of_platform.h> #include <linux/of_address.h> #include <linux/amba/bus.h> -#include <linux/clk-provider.h> #include <asm/cacheflush.h> #include <asm/cputype.h> @@ -83,20 +82,6 @@ static void __init highbank_init_irq(void) } } -static void __init highbank_timer_init(void) -{ - struct device_node *np; - - /* Map system registers */ - np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); - sregs_base = of_iomap(np, 0); - WARN_ON(!sregs_base); - - of_clk_init(NULL); - - clocksource_of_init(); -} - static void highbank_power_off(void) { highbank_set_pwr_shutdown(); @@ -155,6 +140,13 @@ static struct notifier_block highbank_platform_nb = { static void __init highbank_init(void) { + struct device_node *np; + + /* Map system registers */ + np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); + sregs_base = of_iomap(np, 0); + WARN_ON(!sregs_base); + pm_power_off = highbank_power_off; highbank_pm_init(); @@ -176,7 +168,6 @@ DT_MACHINE_START(HIGHBANK, "Highbank") #endif .smp = smp_ops(highbank_smp_ops), .init_irq = highbank_init_irq, - .init_time = highbank_timer_init, .init_machine = highbank_init, .dt_compat = highbank_match, .restart = highbank_restart, diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 29a8af6..a91909b 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -4,8 +4,8 @@ config ARCH_MXC select ARM_CPU_SUSPEND if PM select ARM_PATCH_PHYS_VIRT select AUTO_ZRELADDR if !ZBOOT_ROM - select CLKDEV_LOOKUP select CLKSRC_MMIO + select COMMON_CLK select GENERIC_ALLOCATOR select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP @@ -92,14 +92,12 @@ config MACH_MX27 config SOC_IMX1 bool select ARCH_MX1 - select COMMON_CLK select CPU_ARM920T select IMX_HAVE_IOMUX_V1 select MXC_AVIC config SOC_IMX21 bool - select COMMON_CLK select CPU_ARM926T select IMX_HAVE_IOMUX_V1 select MXC_AVIC @@ -108,7 +106,6 @@ config SOC_IMX25 bool select ARCH_MX25 select ARCH_MXC_IOMUX_V3 - select COMMON_CLK select CPU_ARM926T select MXC_AVIC @@ -116,7 +113,6 @@ config SOC_IMX27 bool select ARCH_HAS_CPUFREQ select ARCH_HAS_OPP - select COMMON_CLK select CPU_ARM926T select IMX_HAVE_IOMUX_V1 select MACH_MX27 @@ -124,7 +120,6 @@ config SOC_IMX27 config SOC_IMX31 bool - select COMMON_CLK select CPU_V6 select IMX_HAVE_PLATFORM_MXC_RNGA select MXC_AVIC @@ -133,7 +128,6 @@ config SOC_IMX31 config SOC_IMX35 bool select ARCH_MXC_IOMUX_V3 - select COMMON_CLK select CPU_V6K select HAVE_EPIT select MXC_AVIC @@ -144,7 +138,6 @@ config SOC_IMX5 select ARCH_HAS_CPUFREQ select ARCH_HAS_OPP select ARCH_MXC_IOMUX_V3 - select COMMON_CLK select CPU_V7 select MXC_TZIC @@ -791,7 +784,6 @@ config SOC_IMX6Q select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 select ARM_GIC - select COMMON_CLK select CPU_V7 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 7c0dc45..ceaac9c 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -11,6 +11,7 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/clkdev.h> +#include <linux/clk-provider.h> #include <linux/of.h> #include <linux/err.h> @@ -131,8 +132,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, { int i; - of_clk_init(NULL); - clk[dummy] = imx_clk_fixed("dummy", 0); clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil); clk[osc] = imx_obtain_fixed_clock("osc", rate_osc); @@ -465,12 +464,16 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, return 0; } -int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, - unsigned long rate_ckih1, unsigned long rate_ckih2) +static void __init mx51_clocks_init_dt(struct device_node *np) +{ + mx51_clocks_init(0, 0, 0, 0); +} +CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt); + +static void __init mx53_clocks_init(struct device_node *np) { int i; unsigned long r; - struct device_node *np; clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); @@ -529,12 +532,11 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, pr_err("i.MX53 clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); - np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm"); clk_data.clks = clk; clk_data.clk_num = ARRAY_SIZE(clk); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); + mx5_clocks_common_init(0, 0, 0, 0); clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0"); clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); @@ -566,16 +568,5 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, r = clk_round_rate(clk[usboh3_per_gate], 54000000); clk_set_rate(clk[usboh3_per_gate], r); - - return 0; -} - -int __init mx51_clocks_init_dt(void) -{ - return mx51_clocks_init(0, 0, 0, 0); -} - -int __init mx53_clocks_init_dt(void) -{ - return mx53_clocks_init(0, 0, 0, 0); } +CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 4517fd7..28e8ca0 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -63,13 +63,9 @@ extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); -extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, - unsigned long ckih1, unsigned long ckih2); extern int mx25_clocks_init_dt(void); extern int mx27_clocks_init_dt(void); extern int mx31_clocks_init_dt(void); -extern int mx51_clocks_init_dt(void); -extern int mx53_clocks_init_dt(void); extern struct platform_device *mxc_register_gpio(char *name, int id, resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); extern void mxc_set_cpu_type(unsigned int type); diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c index 53e43e5..bece8a6 100644 --- a/arch/arm/mach-imx/imx51-dt.c +++ b/arch/arm/mach-imx/imx51-dt.c @@ -34,17 +34,11 @@ static const char *imx51_dt_board_compat[] __initdata = { NULL }; -static void __init imx51_timer_init(void) -{ - mx51_clocks_init_dt(); -} - DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)") .map_io = mx51_map_io, .init_early = imx51_init_early, .init_irq = mx51_init_irq, .handle_irq = imx51_handle_irq, - .init_time = imx51_timer_init, .init_machine = imx51_dt_init, .init_late = imx51_init_late, .dt_compat = imx51_dt_board_compat, diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index 98c5894..c9c4d8d 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -36,17 +36,11 @@ static const char *imx53_dt_board_compat[] __initdata = { NULL }; -static void __init imx53_timer_init(void) -{ - mx53_clocks_init_dt(); -} - DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)") .map_io = mx53_map_io, .init_early = imx53_init_early, .init_irq = mx53_init_irq, .handle_irq = imx53_handle_irq, - .init_time = imx53_timer_init, .init_machine = imx53_dt_init, .init_late = imx53_init_late, .dt_compat = imx53_dt_board_compat, diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 90372a2..3be0fa0 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -11,9 +11,7 @@ */ #include <linux/clk.h> -#include <linux/clk-provider.h> #include <linux/clkdev.h> -#include <linux/clocksource.h> #include <linux/cpu.h> #include <linux/delay.h> #include <linux/export.h> @@ -192,6 +190,9 @@ static void __init imx6q_1588_init(void) static void __init imx6q_init_machine(void) { + imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", + imx6q_revision()); + imx6q_enet_phy_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); @@ -293,14 +294,6 @@ static void __init imx6q_init_irq(void) irqchip_init(); } -static void __init imx6q_timer_init(void) -{ - of_clk_init(NULL); - clocksource_of_init(); - imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", - imx6q_revision()); -} - static const char *imx6q_dt_compat[] __initdata = { "fsl,imx6dl", "fsl,imx6q", @@ -311,7 +304,6 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") .smp = smp_ops(imx_smp_ops), .map_io = imx6q_map_io, .init_irq = imx6q_init_irq, - .init_time = imx6q_timer_init, .init_machine = imx6q_init_machine, .init_late = imx6q_init_late, .dt_compat = imx6q_dt_compat, diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 0d75dc5..c70bd7c 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -7,7 +7,6 @@ * */ -#include <linux/clk-provider.h> #include <linux/irqchip.h> #include <linux/of.h> #include <linux/of_platform.h> @@ -31,11 +30,6 @@ static void __init imx6sl_init_irq(void) irqchip_init(); } -static void __init imx6sl_timer_init(void) -{ - of_clk_init(NULL); -} - static const char *imx6sl_dt_compat[] __initdata = { "fsl,imx6sl", NULL, @@ -44,7 +38,6 @@ static const char *imx6sl_dt_compat[] __initdata = { DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)") .map_io = debug_ll_io_init, .init_irq = imx6sl_init_irq, - .init_time = imx6sl_timer_init, .init_machine = imx6sl_init_machine, .dt_compat = imx6sl_dt_compat, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c index 816991d..af0cb8a 100644 --- a/arch/arm/mach-imx/mach-vf610.c +++ b/arch/arm/mach-imx/mach-vf610.c @@ -8,9 +8,7 @@ */ #include <linux/of_platform.h> -#include <linux/clocksource.h> #include <linux/irqchip.h> -#include <linux/clk-provider.h> #include <asm/mach/arch.h> #include <asm/hardware/cache-l2x0.h> @@ -28,12 +26,6 @@ static void __init vf610_init_irq(void) irqchip_init(); } -static void __init vf610_init_time(void) -{ - of_clk_init(NULL); - clocksource_of_init(); -} - static const char *vf610_dt_compat[] __initdata = { "fsl,vf610", NULL, @@ -41,7 +33,6 @@ static const char *vf610_dt_compat[] __initdata = { DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)") .init_irq = vf610_init_irq, - .init_time = vf610_init_time, .init_machine = vf610_init_machine, .dt_compat = vf610_dt_compat, .restart = mxc_restart, diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 82d3ad8..a32a3e5 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -15,7 +15,6 @@ #include <linux/of.h> #include <linux/of_platform.h> #include <linux/clk-provider.h> -#include <linux/clocksource.h> #include <linux/dma-mapping.h> #include <linux/irqchip.h> #include <linux/kexec.h> @@ -66,12 +65,6 @@ static void __init kirkwood_legacy_clk_init(void) clk_prepare_enable(clk); } -static void __init kirkwood_dt_time_init(void) -{ - of_clk_init(NULL); - clocksource_of_init(); -} - static void __init kirkwood_dt_init_early(void) { mvebu_mbus_init("marvell,kirkwood-mbus", @@ -122,7 +115,6 @@ DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)") /* Maintainer: Jason Cooper <jason@lakedaemon.net> */ .map_io = kirkwood_map_io, .init_early = kirkwood_dt_init_early, - .init_time = kirkwood_dt_time_init, .init_machine = kirkwood_dt_init, .restart = kirkwood_restart, .dt_compat = kirkwood_dt_board_compat, diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 905efc8..2586c28 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -1,12 +1,12 @@ if ARCH_MSM comment "Qualcomm MSM SoC Type" - depends on (ARCH_MSM8X60 || ARCH_MSM8960) + depends on ARCH_MSM_DT choice prompt "Qualcomm MSM SoC Type" default ARCH_MSM7X00A - depends on !(ARCH_MSM8X60 || ARCH_MSM8960) + depends on !ARCH_MSM_DT config ARCH_MSM7X00A bool "MSM7x00A / MSM7x01A" @@ -49,7 +49,6 @@ config ARCH_MSM8X60 select GPIO_MSM_V2 select HAVE_SMP select MSM_SCM if SMP - select USE_OF config ARCH_MSM8960 bool "MSM8960" @@ -58,6 +57,11 @@ config ARCH_MSM8960 select HAVE_SMP select GPIO_MSM_V2 select MSM_SCM if SMP + +config ARCH_MSM_DT + def_bool y + depends on (ARCH_MSM8X60 || ARCH_MSM8960) + select SPARSE_IRQ select USE_OF config MSM_HAS_DEBUG_UART_HS @@ -68,6 +72,7 @@ config MSM_SOC_REV_A config ARCH_MSM_ARM11 bool + config ARCH_MSM_SCORPION bool @@ -75,6 +80,7 @@ config MSM_VIC bool menu "Qualcomm MSM Board Type" + depends on !ARCH_MSM_DT config MACH_HALIBUT depends on ARCH_MSM @@ -122,6 +128,7 @@ config MSM_SMD config MSM_GPIOMUX bool + depends on !ARCH_MSM_DT help Support for MSM V1 TLMM GPIOMUX architecture. diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index d872634..7ed4c1b 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -26,7 +26,6 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o b obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o -obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o -obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o +obj-$(CONFIG_ARCH_MSM_DT) += board-dt.o obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c deleted file mode 100644 index c294689..0000000 --- a/arch/arm/mach-msm/board-dt-8660.c +++ /dev/null @@ -1,48 +0,0 @@ -/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/init.h> -#include <linux/of.h> -#include <linux/of_platform.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include "common.h" - -static void __init msm8x60_init_late(void) -{ - smd_debugfs_init(); -} - -static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = { - {} -}; - -static void __init msm8x60_dt_init(void) -{ - of_platform_populate(NULL, of_default_bus_match_table, - msm_auxdata_lookup, NULL); -} - -static const char *msm8x60_fluid_match[] __initdata = { - "qcom,msm8660-fluid", - "qcom,msm8660-surf", - NULL -}; - -DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") - .smp = smp_ops(msm_smp_ops), - .init_machine = msm8x60_dt_init, - .init_late = msm8x60_init_late, - .dt_compat = msm8x60_fluid_match, -MACHINE_END diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt.c index d4ca52c..16e6183 100644 --- a/arch/arm/mach-msm/board-dt-8960.c +++ b/arch/arm/mach-msm/board-dt.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012, The Linux Foundation. All rights reserved. +/* Copyright (c) 2010-2012,2013 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -11,6 +11,7 @@ */ #include <linux/init.h> +#include <linux/of.h> #include <linux/of_platform.h> #include <asm/mach/arch.h> @@ -18,18 +19,14 @@ #include "common.h" -static void __init msm_dt_init(void) -{ - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - -static const char * const msm8960_dt_match[] __initconst = { +static const char * const msm_dt_match[] __initconst = { + "qcom,msm8660-fluid", + "qcom,msm8660-surf", "qcom,msm8960-cdp", NULL }; -DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") +DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") .smp = smp_ops(msm_smp_ops), - .init_machine = msm_dt_init, - .dt_compat = msm8960_dt_match, + .dt_compat = msm_dt_match, MACHINE_END diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h deleted file mode 100644 index 81ab2a6..0000000 --- a/arch/arm/mach-msm/include/mach/irqs-8960.h +++ /dev/null @@ -1,277 +0,0 @@ -/* Copyright (c) 2011 Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_MSM_IRQS_8960_H -#define __ASM_ARCH_MSM_IRQS_8960_H - -/* MSM ACPU Interrupt Numbers */ - -/* 0-15: STI/SGI (software triggered/generated interrupts) - 16-31: PPI (private peripheral interrupts) - 32+: SPI (shared peripheral interrupts) */ - -#define GIC_PPI_START 16 -#define GIC_SPI_START 32 - -#define INT_VGIC (GIC_PPI_START + 0) -#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1) -#define INT_GP_TIMER_EXP (GIC_PPI_START + 2) -#define INT_GP_TIMER2_EXP (GIC_PPI_START + 3) -#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4) -#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5) -#define AVS_SVICINT (GIC_PPI_START + 6) -#define AVS_SVICINTSWDONE (GIC_PPI_START + 7) -#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8) -#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9) -#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 10) -#define SC_AVSCPUXDOWN (GIC_PPI_START + 11) -#define SC_AVSCPUXUP (GIC_PPI_START + 12) -#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13) -#define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14) -/* PPI 15 is unused */ - -#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0) -#define SC_SICL2IRPTREQ (GIC_SPI_START + 1) -#define SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 2) -#define SC_SICAGCIRPTREQ (GIC_SPI_START + 3) -#define TLMM_APCC_DIR_CONN_IRQ_0 (GIC_SPI_START + 4) -#define TLMM_APCC_DIR_CONN_IRQ_1 (GIC_SPI_START + 5) -#define TLMM_APCC_DIR_CONN_IRQ_2 (GIC_SPI_START + 6) -#define TLMM_APCC_DIR_CONN_IRQ_3 (GIC_SPI_START + 7) -#define TLMM_APCC_DIR_CONN_IRQ_4 (GIC_SPI_START + 8) -#define TLMM_APCC_DIR_CONN_IRQ_5 (GIC_SPI_START + 9) -#define TLMM_APCC_DIR_CONN_IRQ_6 (GIC_SPI_START + 10) -#define TLMM_APCC_DIR_CONN_IRQ_7 (GIC_SPI_START + 11) -#define TLMM_APCC_DIR_CONN_IRQ_8 (GIC_SPI_START + 12) -#define TLMM_APCC_DIR_CONN_IRQ_9 (GIC_SPI_START + 13) -#define PM8921_SEC_IRQ_103 (GIC_SPI_START + 14) -#define PM8018_SEC_IRQ_106 (GIC_SPI_START + 15) -#define TLMM_APCC_SUMMARY_IRQ (GIC_SPI_START + 16) -#define SPDM_RT_1_IRQ (GIC_SPI_START + 17) -#define SPDM_DIAG_IRQ (GIC_SPI_START + 18) -#define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19) -#define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20) -#define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21) -#define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22) -#define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23) -#define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24) -#define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25) -#define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26) -#define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27) -#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28) -#define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29) -#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30) -#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31) -#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32) -#define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33) -#define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34) -#define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35) -#define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36) -#define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37) -#define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38) -#define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39) -#define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40) -#define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41) -#define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42) -#define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43) -#define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44) -#define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45) -#define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46) -#define VPE_IRQ (GIC_SPI_START + 47) -#define VFE_IRQ (GIC_SPI_START + 48) -#define VCODEC_IRQ (GIC_SPI_START + 49) -#define TV_ENC_IRQ (GIC_SPI_START + 50) -#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51) -#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52) -#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53) -#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54) -#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55) -#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56) -#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57) -#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58) -#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59) -#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60) -#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61) -#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62) -#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63) -#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64) -#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65) -#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66) -#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67) -#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68) -#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69) -#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70) -#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71) -#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72) -#define ROT_IRQ (GIC_SPI_START + 73) -#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74) -#define MDP_IRQ (GIC_SPI_START + 75) -#define JPEGD_IRQ (GIC_SPI_START + 76) -#define JPEG_IRQ (GIC_SPI_START + 77) -#define MMSS_IMEM_IRQ (GIC_SPI_START + 78) -#define HDMI_IRQ (GIC_SPI_START + 79) -#define GFX3D_IRQ (GIC_SPI_START + 80) -#define GFX2D0_IRQ (GIC_SPI_START + 81) -#define DSI1_IRQ (GIC_SPI_START + 82) -#define CSI_1_IRQ (GIC_SPI_START + 83) -#define CSI_0_IRQ (GIC_SPI_START + 84) -#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85) -#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86) -#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87) -#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88) -#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89) -#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90) -#define TOP_IMEM_IRQ (GIC_SPI_START + 91) -#define FABRIC_SYS_IRQ (GIC_SPI_START + 92) -#define FABRIC_APPS_IRQ (GIC_SPI_START + 93) -#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94) -#define SDC4_BAM_IRQ (GIC_SPI_START + 95) -#define SDC3_BAM_IRQ (GIC_SPI_START + 96) -#define SDC2_BAM_IRQ (GIC_SPI_START + 97) -#define SDC1_BAM_IRQ (GIC_SPI_START + 98) -#define FABRIC_SPS_IRQ (GIC_SPI_START + 99) -#define USB1_HS_IRQ (GIC_SPI_START + 100) -#define SDC4_IRQ_0 (GIC_SPI_START + 101) -#define SDC3_IRQ_0 (GIC_SPI_START + 102) -#define SDC2_IRQ_0 (GIC_SPI_START + 103) -#define SDC1_IRQ_0 (GIC_SPI_START + 104) -#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105) -#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106) -#define SPS_MTI_0 (GIC_SPI_START + 107) -#define SPS_MTI_1 (GIC_SPI_START + 108) -#define SPS_MTI_2 (GIC_SPI_START + 109) -#define SPS_MTI_3 (GIC_SPI_START + 110) -#define SPS_MTI_4 (GIC_SPI_START + 111) -#define SPS_MTI_5 (GIC_SPI_START + 112) -#define SPS_MTI_6 (GIC_SPI_START + 113) -#define SPS_MTI_7 (GIC_SPI_START + 114) -#define SPS_MTI_8 (GIC_SPI_START + 115) -#define SPS_MTI_9 (GIC_SPI_START + 116) -#define SPS_MTI_10 (GIC_SPI_START + 117) -#define SPS_MTI_11 (GIC_SPI_START + 118) -#define SPS_MTI_12 (GIC_SPI_START + 119) -#define SPS_MTI_13 (GIC_SPI_START + 120) -#define SPS_MTI_14 (GIC_SPI_START + 121) -#define SPS_MTI_15 (GIC_SPI_START + 122) -#define SPS_MTI_16 (GIC_SPI_START + 123) -#define SPS_MTI_17 (GIC_SPI_START + 124) -#define SPS_MTI_18 (GIC_SPI_START + 125) -#define SPS_MTI_19 (GIC_SPI_START + 126) -#define SPS_MTI_20 (GIC_SPI_START + 127) -#define SPS_MTI_21 (GIC_SPI_START + 128) -#define SPS_MTI_22 (GIC_SPI_START + 129) -#define SPS_MTI_23 (GIC_SPI_START + 130) -#define SPS_MTI_24 (GIC_SPI_START + 131) -#define SPS_MTI_25 (GIC_SPI_START + 132) -#define SPS_MTI_26 (GIC_SPI_START + 133) -#define SPS_MTI_27 (GIC_SPI_START + 134) -#define SPS_MTI_28 (GIC_SPI_START + 135) -#define SPS_MTI_29 (GIC_SPI_START + 136) -#define SPS_MTI_30 (GIC_SPI_START + 137) -#define SPS_MTI_31 (GIC_SPI_START + 138) -#define CSIPHY_4LN_IRQ (GIC_SPI_START + 139) -#define CSIPHY_2LN_IRQ (GIC_SPI_START + 140) -#define USB2_IRQ (GIC_SPI_START + 141) -#define USB1_IRQ (GIC_SPI_START + 142) -#define TSSC_SSBI_IRQ (GIC_SPI_START + 143) -#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144) -#define TSSC_PENUP_IRQ (GIC_SPI_START + 145) -#define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146) -#define GSBI1_QUP_IRQ (GIC_SPI_START + 147) -#define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148) -#define GSBI2_QUP_IRQ (GIC_SPI_START + 149) -#define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150) -#define GSBI3_QUP_IRQ (GIC_SPI_START + 151) -#define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152) -#define GSBI4_QUP_IRQ (GIC_SPI_START + 153) -#define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154) -#define GSBI5_QUP_IRQ (GIC_SPI_START + 155) -#define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156) -#define GSBI6_QUP_IRQ (GIC_SPI_START + 157) -#define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158) -#define GSBI7_QUP_IRQ (GIC_SPI_START + 159) -#define GSBI8_UARTDM_IRQ (GIC_SPI_START + 160) -#define GSBI8_QUP_IRQ (GIC_SPI_START + 161) -#define TSIF_TSPP_IRQ (GIC_SPI_START + 162) -#define TSIF_BAM_IRQ (GIC_SPI_START + 163) -#define TSIF2_IRQ (GIC_SPI_START + 164) -#define TSIF1_IRQ (GIC_SPI_START + 165) -#define DSI2_IRQ (GIC_SPI_START + 166) -#define ISPIF_IRQ (GIC_SPI_START + 167) -#define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168) -#define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169) -#define INT_ADM0_SCSS_0_IRQ (GIC_SPI_START + 170) -#define INT_ADM0_SCSS_1_IRQ (GIC_SPI_START + 171) -#define INT_ADM0_SCSS_2_IRQ (GIC_SPI_START + 172) -#define INT_ADM0_SCSS_3_IRQ (GIC_SPI_START + 173) -#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174) -#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175) -#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176) -#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177) -#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178) -#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179) -#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180) -#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181) -#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182) -#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183) -#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184) -#define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185) -#define HSDDRX_EBI1CH1_IRQ (GIC_SPI_START + 186) -#define SDC5_BAM_IRQ (GIC_SPI_START + 187) -#define SDC5_IRQ_0 (GIC_SPI_START + 188) -#define GSBI9_UARTDM_IRQ (GIC_SPI_START + 189) -#define GSBI9_QUP_IRQ (GIC_SPI_START + 190) -#define GSBI10_UARTDM_IRQ (GIC_SPI_START + 191) -#define GSBI10_QUP_IRQ (GIC_SPI_START + 192) -#define GSBI11_UARTDM_IRQ (GIC_SPI_START + 193) -#define GSBI11_QUP_IRQ (GIC_SPI_START + 194) -#define GSBI12_UARTDM_IRQ (GIC_SPI_START + 195) -#define GSBI12_QUP_IRQ (GIC_SPI_START + 196) -#define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197) -#define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198) -#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199) -#define RIVA_ASS_RESET_DONE_IRQ (GIC_SPI_START + 200) -#define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201) -#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202) -#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203) -#define RIVA_APPS_WLAM_SMSM_IRQ (GIC_SPI_START + 204) -#define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205) -#define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206) -#define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207) -#define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208) -#define A2_BAM_IRQ (GIC_SPI_START + 209) -#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) -#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) -#define GFX2D1_IRQ (GIC_SPI_START + 212) -#define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213) -#define SPS_SLIMBUS_CORE_EE0_IRQ (GIC_SPI_START + 214) -#define SPS_SLIMBUS_BAM_EE0_IRQ (GIC_SPI_START + 215) -#define QDSS_ETB_IRQ (GIC_SPI_START + 216) -#define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217) -#define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218) -#define TLMM_APCC_DIR_CONN_IRQ_16 (GIC_SPI_START + 219) -#define TLMM_APCC_DIR_CONN_IRQ_17 (GIC_SPI_START + 220) -#define TLMM_APCC_DIR_CONN_IRQ_18 (GIC_SPI_START + 221) -#define TLMM_APCC_DIR_CONN_IRQ_19 (GIC_SPI_START + 222) -#define TLMM_APCC_DIR_CONN_IRQ_20 (GIC_SPI_START + 223) -#define TLMM_APCC_DIR_CONN_IRQ_21 (GIC_SPI_START + 224) -#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225) -#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226) - -/* For now, use the maximum number of interrupts until a pending GIC issue - * is sorted out */ -#define NR_MSM_IRQS 1020 -#define NR_BOARD_IRQS 0 -#define NR_GPIO_IRQS 0 - -#endif - diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h deleted file mode 100644 index f65841c..0000000 --- a/arch/arm/mach-msm/include/mach/irqs-8x60.h +++ /dev/null @@ -1,258 +0,0 @@ -/* Copyright (c) 2010 Code Aurora Forum. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_MSM_IRQS_8X60_H -#define __ASM_ARCH_MSM_IRQS_8X60_H - -/* MSM ACPU Interrupt Numbers */ - -/* 0-15: STI/SGI (software triggered/generated interrupts) - * 16-31: PPI (private peripheral interrupts) - * 32+: SPI (shared peripheral interrupts) - */ - -#define GIC_PPI_START 16 -#define GIC_SPI_START 32 - -#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 0) -#define INT_GP_TIMER_EXP (GIC_PPI_START + 1) -#define INT_GP_TIMER2_EXP (GIC_PPI_START + 2) -#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 3) -#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 4) -#define AVS_SVICINT (GIC_PPI_START + 5) -#define AVS_SVICINTSWDONE (GIC_PPI_START + 6) -#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 7) -#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 8) -#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 9) -#define SC_AVSCPUXDOWN (GIC_PPI_START + 10) -#define SC_AVSCPUXUP (GIC_PPI_START + 11) -#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 12) -/* PPI 13 to 15 are unused */ - - -#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0) -#define SC_SICL2IRPTREQ (GIC_SPI_START + 1) -#define SC_SICL2ACGIRPTREQ (GIC_SPI_START + 2) -#define NC (GIC_SPI_START + 3) -#define TLMM_SCSS_DIR_CONN_IRQ_0 (GIC_SPI_START + 4) -#define TLMM_SCSS_DIR_CONN_IRQ_1 (GIC_SPI_START + 5) -#define TLMM_SCSS_DIR_CONN_IRQ_2 (GIC_SPI_START + 6) -#define TLMM_SCSS_DIR_CONN_IRQ_3 (GIC_SPI_START + 7) -#define TLMM_SCSS_DIR_CONN_IRQ_4 (GIC_SPI_START + 8) -#define TLMM_SCSS_DIR_CONN_IRQ_5 (GIC_SPI_START + 9) -#define TLMM_SCSS_DIR_CONN_IRQ_6 (GIC_SPI_START + 10) -#define TLMM_SCSS_DIR_CONN_IRQ_7 (GIC_SPI_START + 11) -#define TLMM_SCSS_DIR_CONN_IRQ_8 (GIC_SPI_START + 12) -#define TLMM_SCSS_DIR_CONN_IRQ_9 (GIC_SPI_START + 13) -#define PM8058_SEC_IRQ_N (GIC_SPI_START + 14) -#define PM8901_SEC_IRQ_N (GIC_SPI_START + 15) -#define TLMM_SCSS_SUMMARY_IRQ (GIC_SPI_START + 16) -#define SPDM_RT_1_IRQ (GIC_SPI_START + 17) -#define SPDM_DIAG_IRQ (GIC_SPI_START + 18) -#define RPM_SCSS_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19) -#define RPM_SCSS_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20) -#define RPM_SCSS_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21) -#define RPM_SCSS_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22) -#define RPM_SCSS_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23) -#define RPM_SCSS_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24) -#define RPM_SCSS_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25) -#define RPM_SCSS_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26) -#define SSBI2_2_SC_CPU0_SECURE_INT (GIC_SPI_START + 27) -#define SSBI2_2_SC_CPU0_NON_SECURE_INT (GIC_SPI_START + 28) -#define SSBI2_1_SC_CPU0_SECURE_INT (GIC_SPI_START + 29) -#define SSBI2_1_SC_CPU0_NON_SECURE_INT (GIC_SPI_START + 30) -#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31) -#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32) -#define MARM_FIQ (GIC_SPI_START + 33) -#define MARM_IRQ (GIC_SPI_START + 34) -#define MARM_L2CC_IRQ (GIC_SPI_START + 35) -#define MARM_WDOG_EXPIRED (GIC_SPI_START + 36) -#define MARM_SCSS_GP_IRQ_0 (GIC_SPI_START + 37) -#define MARM_SCSS_GP_IRQ_1 (GIC_SPI_START + 38) -#define MARM_SCSS_GP_IRQ_2 (GIC_SPI_START + 39) -#define MARM_SCSS_GP_IRQ_3 (GIC_SPI_START + 40) -#define MARM_SCSS_GP_IRQ_4 (GIC_SPI_START + 41) -#define MARM_SCSS_GP_IRQ_5 (GIC_SPI_START + 42) -#define MARM_SCSS_GP_IRQ_6 (GIC_SPI_START + 43) -#define MARM_SCSS_GP_IRQ_7 (GIC_SPI_START + 44) -#define MARM_SCSS_GP_IRQ_8 (GIC_SPI_START + 45) -#define MARM_SCSS_GP_IRQ_9 (GIC_SPI_START + 46) -#define VPE_IRQ (GIC_SPI_START + 47) -#define VFE_IRQ (GIC_SPI_START + 48) -#define VCODEC_IRQ (GIC_SPI_START + 49) -#define TV_ENC_IRQ (GIC_SPI_START + 50) -#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51) -#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52) -#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53) -#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54) -#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55) -#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56) -#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57) -#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58) -#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59) -#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60) -#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61) -#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62) -#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63) -#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64) -#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65) -#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66) -#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67) -#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68) -#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69) -#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70) -#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71) -#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72) -#define ROT_IRQ (GIC_SPI_START + 73) -#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74) -#define MDP_IRQ (GIC_SPI_START + 75) -#define JPEGD_IRQ (GIC_SPI_START + 76) -#define JPEG_IRQ (GIC_SPI_START + 77) -#define MMSS_IMEM_IRQ (GIC_SPI_START + 78) -#define HDMI_IRQ (GIC_SPI_START + 79) -#define GFX3D_IRQ (GIC_SPI_START + 80) -#define GFX2D0_IRQ (GIC_SPI_START + 81) -#define DSI_IRQ (GIC_SPI_START + 82) -#define CSI_1_IRQ (GIC_SPI_START + 83) -#define CSI_0_IRQ (GIC_SPI_START + 84) -#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85) -#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86) -#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87) -#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88) -#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89) -#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90) -#define TOP_IMEM_IRQ (GIC_SPI_START + 91) -#define FABRIC_SYS_IRQ (GIC_SPI_START + 92) -#define FABRIC_APPS_IRQ (GIC_SPI_START + 93) -#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94) -#define SDC4_BAM_IRQ (GIC_SPI_START + 95) -#define SDC3_BAM_IRQ (GIC_SPI_START + 96) -#define SDC2_BAM_IRQ (GIC_SPI_START + 97) -#define SDC1_BAM_IRQ (GIC_SPI_START + 98) -#define FABRIC_SPS_IRQ (GIC_SPI_START + 99) -#define USB1_HS_IRQ (GIC_SPI_START + 100) -#define SDC4_IRQ_0 (GIC_SPI_START + 101) -#define SDC3_IRQ_0 (GIC_SPI_START + 102) -#define SDC2_IRQ_0 (GIC_SPI_START + 103) -#define SDC1_IRQ_0 (GIC_SPI_START + 104) -#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105) -#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106) -#define SPS_MTI_0 (GIC_SPI_START + 107) -#define SPS_MTI_1 (GIC_SPI_START + 108) -#define SPS_MTI_2 (GIC_SPI_START + 109) -#define SPS_MTI_3 (GIC_SPI_START + 110) -#define SPS_MTI_4 (GIC_SPI_START + 111) -#define SPS_MTI_5 (GIC_SPI_START + 112) -#define SPS_MTI_6 (GIC_SPI_START + 113) -#define SPS_MTI_7 (GIC_SPI_START + 114) -#define SPS_MTI_8 (GIC_SPI_START + 115) -#define SPS_MTI_9 (GIC_SPI_START + 116) -#define SPS_MTI_10 (GIC_SPI_START + 117) -#define SPS_MTI_11 (GIC_SPI_START + 118) -#define SPS_MTI_12 (GIC_SPI_START + 119) -#define SPS_MTI_13 (GIC_SPI_START + 120) -#define SPS_MTI_14 (GIC_SPI_START + 121) -#define SPS_MTI_15 (GIC_SPI_START + 122) -#define SPS_MTI_16 (GIC_SPI_START + 123) -#define SPS_MTI_17 (GIC_SPI_START + 124) -#define SPS_MTI_18 (GIC_SPI_START + 125) -#define SPS_MTI_19 (GIC_SPI_START + 126) -#define SPS_MTI_20 (GIC_SPI_START + 127) -#define SPS_MTI_21 (GIC_SPI_START + 128) -#define SPS_MTI_22 (GIC_SPI_START + 129) -#define SPS_MTI_23 (GIC_SPI_START + 130) -#define SPS_MTI_24 (GIC_SPI_START + 131) -#define SPS_MTI_25 (GIC_SPI_START + 132) -#define SPS_MTI_26 (GIC_SPI_START + 133) -#define SPS_MTI_27 (GIC_SPI_START + 134) -#define SPS_MTI_28 (GIC_SPI_START + 135) -#define SPS_MTI_29 (GIC_SPI_START + 136) -#define SPS_MTI_30 (GIC_SPI_START + 137) -#define SPS_MTI_31 (GIC_SPI_START + 138) -#define UXMC_EBI2_WR_ER_DONE_IRQ (GIC_SPI_START + 139) -#define UXMC_EBI2_OP_DONE_IRQ (GIC_SPI_START + 140) -#define USB2_IRQ (GIC_SPI_START + 141) -#define USB1_IRQ (GIC_SPI_START + 142) -#define TSSC_SSBI_IRQ (GIC_SPI_START + 143) -#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144) -#define TSSC_PENUP_IRQ (GIC_SPI_START + 145) -#define INT_UART1DM_IRQ (GIC_SPI_START + 146) -#define GSBI1_QUP_IRQ (GIC_SPI_START + 147) -#define INT_UART2DM_IRQ (GIC_SPI_START + 148) -#define GSBI2_QUP_IRQ (GIC_SPI_START + 149) -#define INT_UART3DM_IRQ (GIC_SPI_START + 150) -#define GSBI3_QUP_IRQ (GIC_SPI_START + 151) -#define INT_UART4DM_IRQ (GIC_SPI_START + 152) -#define GSBI4_QUP_IRQ (GIC_SPI_START + 153) -#define INT_UART5DM_IRQ (GIC_SPI_START + 154) -#define GSBI5_QUP_IRQ (GIC_SPI_START + 155) -#define INT_UART6DM_IRQ (GIC_SPI_START + 156) -#define GSBI6_QUP_IRQ (GIC_SPI_START + 157) -#define INT_UART7DM_IRQ (GIC_SPI_START + 158) -#define GSBI7_QUP_IRQ (GIC_SPI_START + 159) -#define INT_UART8DM_IRQ (GIC_SPI_START + 160) -#define GSBI8_QUP_IRQ (GIC_SPI_START + 161) -#define TSIF_TSPP_IRQ (GIC_SPI_START + 162) -#define TSIF_BAM_IRQ (GIC_SPI_START + 163) -#define TSIF2_IRQ (GIC_SPI_START + 164) -#define TSIF1_IRQ (GIC_SPI_START + 165) -#define INT_ADM1_MASTER (GIC_SPI_START + 166) -#define INT_ADM1_AARM (GIC_SPI_START + 167) -#define INT_ADM1_SD2 (GIC_SPI_START + 168) -#define INT_ADM1_SD3 (GIC_SPI_START + 169) -#define INT_ADM0_MASTER (GIC_SPI_START + 170) -#define INT_ADM0_AARM (GIC_SPI_START + 171) -#define INT_ADM0_SD2 (GIC_SPI_START + 172) -#define INT_ADM0_SD3 (GIC_SPI_START + 173) -#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174) -#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175) -#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176) -#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177) -#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178) -#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179) -#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180) -#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181) -#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182) -#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183) -#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184) -#define HSDDRX_SMICH0_IRQ (GIC_SPI_START + 185) -#define HSDDRX_EBI1_IRQ (GIC_SPI_START + 186) -#define SDC5_BAM_IRQ (GIC_SPI_START + 187) -#define SDC5_IRQ_0 (GIC_SPI_START + 188) -#define INT_UART9DM_IRQ (GIC_SPI_START + 189) -#define GSBI9_QUP_IRQ (GIC_SPI_START + 190) -#define INT_UART10DM_IRQ (GIC_SPI_START + 191) -#define GSBI10_QUP_IRQ (GIC_SPI_START + 192) -#define INT_UART11DM_IRQ (GIC_SPI_START + 193) -#define GSBI11_QUP_IRQ (GIC_SPI_START + 194) -#define INT_UART12DM_IRQ (GIC_SPI_START + 195) -#define GSBI12_QUP_IRQ (GIC_SPI_START + 196) - -/*SPI 197 to 209 arent used in 8x60*/ -#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) -#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) - -/*SPI 212 to 216 arent used in 8x60*/ -#define SMPSS_SPARE_1 (GIC_SPI_START + 217) -#define SMPSS_SPARE_2 (GIC_SPI_START + 218) -#define SMPSS_SPARE_3 (GIC_SPI_START + 219) -#define SMPSS_SPARE_4 (GIC_SPI_START + 220) -#define SMPSS_SPARE_5 (GIC_SPI_START + 221) -#define SMPSS_SPARE_6 (GIC_SPI_START + 222) -#define SMPSS_SPARE_7 (GIC_SPI_START + 223) - -#define NR_GPIO_IRQS 173 -#define NR_MSM_IRQS 256 -#define NR_BOARD_IRQS 0 - -#endif diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h index 3cd78b1..164d355 100644 --- a/arch/arm/mach-msm/include/mach/irqs.h +++ b/arch/arm/mach-msm/include/mach/irqs.h @@ -24,11 +24,6 @@ #elif defined(CONFIG_ARCH_QSD8X50) #include "irqs-8x50.h" #include "sirc.h" -#elif defined(CONFIG_ARCH_MSM8X60) -#include "irqs-8x60.h" -#elif defined(CONFIG_ARCH_MSM8960) -/* TODO: Make these not generic. */ -#include "irqs-8960.h" #elif defined(CONFIG_ARCH_MSM_ARM11) #include "irqs-7x00.h" #else diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 98f6e2a..cc511a4 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -13,8 +13,6 @@ #include <linux/clk.h> #include <linux/clk/mxs.h> #include <linux/clkdev.h> -#include <linux/clocksource.h> -#include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/gpio.h> @@ -490,16 +488,6 @@ static void mxs_restart(enum reboot_mode mode, const char *cmd) soft_restart(0); } -static void __init mxs_timer_init(void) -{ - if (of_machine_is_compatible("fsl,imx23")) - mx23_clocks_init(); - else - mx28_clocks_init(); - of_clk_init(NULL); - clocksource_of_init(); -} - static const char *mxs_dt_compat[] __initdata = { "fsl,imx28", "fsl,imx23", @@ -508,7 +496,6 @@ static const char *mxs_dt_compat[] __initdata = { DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)") .handle_irq = icoll_handle_irq, - .init_time = mxs_timer_init, .init_machine = mxs_machine_init, .init_late = mxs_pm_init, .dt_compat = mxs_dt_compat, diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index 13e0df9..cce2c9d 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@ -25,15 +25,11 @@ #include <linux/slab.h> #include <linux/irq.h> #include <linux/dma-mapping.h> -#include <linux/platform_data/clk-nomadik.h> -#include <linux/clocksource.h> #include <linux/of_irq.h> #include <linux/of_gpio.h> #include <linux/of_address.h> #include <linux/of_platform.h> -#include <linux/mtd/fsmc.h> #include <linux/gpio.h> -#include <linux/amba/mmci.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -113,50 +109,6 @@ static void cpu8815_restart(enum reboot_mode mode, const char *cmd) writel(1, srcbase + 0x18); } -/* Initial value for SRC control register: all timers use MXTAL/8 source */ -#define SRC_CR_INIT_MASK 0x00007fff -#define SRC_CR_INIT_VAL 0x2aaa8000 - -static void __init cpu8815_timer_init_of(void) -{ - struct device_node *mtu; - void __iomem *base; - int irq; - u32 src_cr; - - /* We need this to be up now */ - nomadik_clk_init(); - - mtu = of_find_node_by_path("/mtu@101e2000"); - if (!mtu) - return; - base = of_iomap(mtu, 0); - if (WARN_ON(!base)) - return; - irq = irq_of_parse_and_map(mtu, 0); - - pr_info("Remapped MTU @ %p, irq: %d\n", base, irq); - - /* Configure timer sources in "system reset controller" ctrl reg */ - src_cr = readl(base); - src_cr &= SRC_CR_INIT_MASK; - src_cr |= SRC_CR_INIT_VAL; - writel(src_cr, base); - - clocksource_of_init(); -} - -static struct fsmc_nand_timings cpu8815_nand_timings = { - .thiz = 0, - .thold = 0x10, - .twait = 0x0A, - .tset = 0, -}; - -static struct fsmc_nand_platform_data cpu8815_nand_data = { - .nand_timings = &cpu8815_nand_timings, -}; - /* * The SMSC911x IRQ is connected to a GPIO pin, but the driver expects * to simply request an IRQ passed as a resource. So the GPIO pin needs @@ -190,15 +142,6 @@ static int __init cpu8815_eth_init(void) device_initcall(cpu8815_eth_init); /* - * TODO: - * cannot be set from device tree, convert to a proper DT - * binding. - */ -static struct mmci_platform_data mmcsd_plat_data = { - .ocr_mask = MMC_VDD_29_30, -}; - -/* * This GPIO pin turns on a line that is used to detect card insertion * on this board. */ @@ -232,24 +175,13 @@ static int __init cpu8815_mmcsd_init(void) } device_initcall(cpu8815_mmcsd_init); - -/* These are mostly to get the right device names for the clock lookups */ -static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("stericsson,fsmc-nand", NOMADIK_FSMC_BASE, - NULL, &cpu8815_nand_data), - OF_DEV_AUXDATA("arm,primecell", NOMADIK_SDI_BASE, - NULL, &mmcsd_plat_data), - { /* sentinel */ }, -}; - static void __init cpu8815_init_of(void) { #ifdef CONFIG_CACHE_L2X0 /* At full speed latency must be >=2, so 0x249 in low bits */ l2x0_of_init(0x00730249, 0xfe000fff); #endif - of_platform_populate(NULL, of_default_bus_match_table, - cpu8815_auxdata_lookup, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char * cpu8815_board_compat[] = { @@ -259,7 +191,6 @@ static const char * cpu8815_board_compat[] = { DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815") .map_io = cpu8815_map_io, - .init_time = cpu8815_timer_init_of, .init_machine = cpu8815_init_of, .restart = cpu8815_restart, .dt_compat = cpu8815_board_compat, diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c index 99e2609..4b2ed2e 100644 --- a/arch/arm/mach-nspire/nspire.c +++ b/arch/arm/mach-nspire/nspire.c @@ -14,11 +14,9 @@ #include <linux/of_platform.h> #include <linux/irqchip.h> #include <linux/irqchip/arm-vic.h> -#include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/amba/bus.h> #include <linux/amba/clcd.h> -#include <linux/clocksource.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -65,12 +63,6 @@ static void __init nspire_init(void) nspire_auxdata, NULL); } -static void __init nspire_init_time(void) -{ - of_clk_init(NULL); - clocksource_of_init(); -} - static void nspire_restart(char mode, const char *cmd) { void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K); @@ -83,7 +75,6 @@ static void nspire_restart(char mode, const char *cmd) DT_MACHINE_START(NSPIRE, "TI-NSPIRE") .dt_compat = nspire_dt_match, .map_io = nspire_map_io, - .init_time = nspire_init_time, .init_machine = nspire_init, .restart = nspire_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index b5fb5f7..c946244 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -8,7 +8,6 @@ config ARCH_OMAP2 select CPU_V6 select MULTI_IRQ_HANDLER select SOC_HAS_OMAP2_SDRC - select COMMON_CLK config ARCH_OMAP3 bool "TI OMAP3" @@ -22,7 +21,6 @@ config ARCH_OMAP3 select PM_OPP if PM select PM_RUNTIME if CPU_IDLE select SOC_HAS_OMAP2_SDRC - select COMMON_CLK select USB_ARCH_HAS_EHCI if USB_SUPPORT config ARCH_OMAP4 @@ -45,7 +43,6 @@ config ARCH_OMAP4 select PM_OPP if PM select PM_RUNTIME if CPU_IDLE select USB_ARCH_HAS_EHCI if USB_SUPPORT - select COMMON_CLK select ARM_ERRATA_754322 select ARM_ERRATA_775420 @@ -59,7 +56,6 @@ config SOC_OMAP5 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_SMP - select COMMON_CLK select HAVE_ARM_ARCH_TIMER select ARM_ERRATA_798181 if SMP @@ -70,7 +66,6 @@ config SOC_AM33XX select ARM_CPU_SUSPEND if PM select CPU_V7 select MULTI_IRQ_HANDLER - select COMMON_CLK config SOC_AM43XX bool "TI AM43x" @@ -79,7 +74,6 @@ config SOC_AM43XX select ARCH_OMAP2PLUS select MULTI_IRQ_HANDLER select ARM_GIC - select COMMON_CLK select MACH_OMAP_GENERIC config ARCH_OMAP2PLUS @@ -89,11 +83,10 @@ config ARCH_OMAP2PLUS select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_OMAP select ARCH_REQUIRE_GPIOLIB - select CLKDEV_LOOKUP select CLKSRC_MMIO + select COMMON_CLK select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP - select HAVE_CLK select OMAP_DM_TIMER select PINCTRL select PROC_DEVICETREE if PROC_FS diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index 25b1fee..c78e893 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -52,7 +52,7 @@ static bool omap2xxx_clk_apll_locked(struct clk_hw *hw) apll_mask = EN_APLL_LOCKED << clk->enable_bit; - r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); + r = omap2xxx_cm_get_pll_status(); return ((r & apll_mask) == apll_mask) ? true : false; } @@ -126,7 +126,7 @@ u32 omap2xxx_get_apll_clkin(void) { u32 aplls, srate = 0; - aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); + aplls = omap2xxx_cm_get_pll_config(); aplls &= OMAP24XX_APLLS_CLKIN_MASK; aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index d862010..3ff3254 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -60,8 +60,7 @@ unsigned long omap2xxx_clk_get_core_rate(void) core_clk = omap2_get_dpll_rate(dpll_core_ck); - v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); - v &= OMAP24XX_CORE_CLK_SRC_MASK; + v = omap2xxx_cm_get_core_clk_src(); if (v == CORE_CLK_SRC_32K) core_clk = 32768; @@ -79,8 +78,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) { u32 high, low, core_clk_src; - core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); - core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; + core_clk_src = omap2xxx_cm_get_core_clk_src(); if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ high = curr_prcm_set->dpll_speed * 2; @@ -120,8 +118,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, const struct dpll_data *dd; cur_rate = omap2xxx_clk_get_core_rate(); - mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); - mult &= OMAP24XX_CORE_CLK_SRC_MASK; + mult = omap2xxx_cm_get_core_clk_src(); if ((rate == (cur_rate / 2)) && (mult == 2)) { omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); @@ -145,7 +142,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, tmpset.cm_clksel1_pll &= ~(dd->mult_mask | dd->div1_mask); div = ((curr_prcm_set->xtal_speed / 1000000) - 1); - tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config(); tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; if (rate > low) { tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index ae2b35e..b935ed2 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -98,7 +98,7 @@ long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - u32 cur_rate, done_rate, bypass = 0, tmp; + u32 cur_rate, done_rate, bypass = 0; const struct prcm_config *prcm; unsigned long found_speed = 0; unsigned long flags; @@ -141,23 +141,11 @@ int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, else done_rate = CORE_CLK_SRC_DPLL; - /* MPU divider */ - omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); - - /* dsp + iva1 div(2420), iva2.1(2430) */ - omap2_cm_write_mod_reg(prcm->cm_clksel_dsp, - OMAP24XX_DSP_MOD, CM_CLKSEL); - - omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); - - /* Major subsystem dividers */ - tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; - omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, - CM_CLKSEL1); - - if (cpu_is_omap2430()) - omap2_cm_write_mod_reg(prcm->cm_clksel_mdm, - OMAP2430_MDM_MOD, CM_CLKSEL); + omap2xxx_cm_set_mod_dividers(prcm->cm_clksel_mpu, + prcm->cm_clksel_dsp, + prcm->cm_clksel_gfx, + prcm->cm_clksel1_core, + prcm->cm_clksel_mdm); /* x2 to enter omap2xxx_sdrc_init_params() */ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 0c38ca9..c7c5d31 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -543,6 +543,44 @@ int omap2_clk_disable_autoidle_all(void) } /** + * omap2_clk_deny_idle - disable autoidle on an OMAP clock + * @clk: struct clk * to disable autoidle for + * + * Disable autoidle on an OMAP clock. + */ +int omap2_clk_deny_idle(struct clk *clk) +{ + struct clk_hw_omap *c; + + if (__clk_get_flags(clk) & CLK_IS_BASIC) + return -EINVAL; + + c = to_clk_hw_omap(__clk_get_hw(clk)); + if (c->ops && c->ops->deny_idle) + c->ops->deny_idle(c); + return 0; +} + +/** + * omap2_clk_allow_idle - enable autoidle on an OMAP clock + * @clk: struct clk * to enable autoidle for + * + * Enable autoidle on an OMAP clock. + */ +int omap2_clk_allow_idle(struct clk *clk) +{ + struct clk_hw_omap *c; + + if (__clk_get_flags(clk) & CLK_IS_BASIC) + return -EINVAL; + + c = to_clk_hw_omap(__clk_get_hw(clk)); + if (c->ops && c->ops->allow_idle) + c->ops->allow_idle(c); + return 0; +} + +/** * omap2_clk_enable_init_clocks - prepare & enable a list of clocks * @clk_names: ptr to an array of strings of clock names to enable * @num_clocks: number of clock names in @clk_names diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 7aa32cd..82916cc 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -411,6 +411,8 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void omap2_init_clk_hw_omap_clocks(struct clk *clk); int omap2_clk_enable_autoidle_all(void); int omap2_clk_disable_autoidle_all(void); +int omap2_clk_allow_idle(struct clk *clk); +int omap2_clk_deny_idle(struct clk *clk); void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c index 6774a53..ce25abb 100644 --- a/arch/arm/mach-omap2/cm2xxx.c +++ b/arch/arm/mach-omap2/cm2xxx.c @@ -327,6 +327,73 @@ struct clkdm_ops omap2_clkdm_operations = { .clkdm_clk_disable = omap2xxx_clkdm_clk_disable, }; +int omap2xxx_cm_fclks_active(void) +{ + u32 f1, f2; + + f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + + return (f1 | f2) ? 1 : 0; +} + +int omap2xxx_cm_mpu_retention_allowed(void) +{ + u32 l; + + /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ + l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | + OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | + OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) + return 0; + /* Check for UART3. */ + l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + if (l & OMAP24XX_EN_UART3_MASK) + return 0; + + return 1; +} + +u32 omap2xxx_cm_get_core_clk_src(void) +{ + u32 v; + + v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + v &= OMAP24XX_CORE_CLK_SRC_MASK; + + return v; +} + +u32 omap2xxx_cm_get_core_pll_config(void) +{ + return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); +} + +u32 omap2xxx_cm_get_pll_config(void) +{ + return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); +} + +u32 omap2xxx_cm_get_pll_status(void) +{ + return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); +} + +void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm) +{ + u32 tmp; + + omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL); + omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL); + omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL); + tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & + OMAP24XX_CLKSEL_DSS2_MASK; + omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1); + if (cpu_is_omap2430()) + omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL); +} + /* * */ diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h index 4cbb39b..891d81c 100644 --- a/arch/arm/mach-omap2/cm2xxx.h +++ b/arch/arm/mach-omap2/cm2xxx.h @@ -62,6 +62,14 @@ extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift); extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst, u8 *idlest_reg_id); +extern int omap2xxx_cm_fclks_active(void); +extern int omap2xxx_cm_mpu_retention_allowed(void); +extern u32 omap2xxx_cm_get_core_clk_src(void); +extern u32 omap2xxx_cm_get_core_pll_config(void); +extern u32 omap2xxx_cm_get_pll_config(void); +extern u32 omap2xxx_cm_get_pll_status(void); +extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, + u32 mdm); extern int __init omap2xxx_cm_init(void); diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c index 9061c30..f6f0288 100644 --- a/arch/arm/mach-omap2/cm3xxx.c +++ b/arch/arm/mach-omap2/cm3xxx.c @@ -636,6 +636,28 @@ void omap3_cm_restore_context(void) OMAP3_CM_CLKOUT_CTRL_OFFSET); } +void omap3_cm_save_scratchpad_contents(u32 *ptr) +{ + *ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); + *ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); + *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); + + /* + * As per erratum i671, ROM code does not respect the PER DPLL + * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1. + * Then, in anycase, clear these bits to avoid extra latencies. + */ + *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) & + ~OMAP3430_AUTO_PERIPH_DPLL_MASK; + *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); + *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); + *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); + *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); + *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); + *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); + *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); +} + /* * */ diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h index e8e146f..8224c91 100644 --- a/arch/arm/mach-omap2/cm3xxx.h +++ b/arch/arm/mach-omap2/cm3xxx.h @@ -83,6 +83,7 @@ extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg, extern void omap3_cm_save_context(void); extern void omap3_cm_restore_context(void); +extern void omap3_cm_save_scratchpad_contents(u32 *ptr); extern int __init omap3xxx_cm_init(void); diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 31e0dfe..44bb4d5 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -46,17 +46,7 @@ struct omap3_scratchpad { struct omap3_scratchpad_prcm_block { u32 prm_clksrc_ctrl; u32 prm_clksel; - u32 cm_clksel_core; - u32 cm_clksel_wkup; - u32 cm_clken_pll; - u32 cm_autoidle_pll; - u32 cm_clksel1_pll; - u32 cm_clksel2_pll; - u32 cm_clksel3_pll; - u32 cm_clken_pll_mpu; - u32 cm_autoidle_pll_mpu; - u32 cm_clksel1_pll_mpu; - u32 cm_clksel2_pll_mpu; + u32 cm_contents[11]; u32 prcm_block_size; }; @@ -347,34 +337,9 @@ void omap3_save_scratchpad_contents(void) prcm_block_contents.prm_clksel = omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET); - prcm_block_contents.cm_clksel_core = - omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); - prcm_block_contents.cm_clksel_wkup = - omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); - prcm_block_contents.cm_clken_pll = - omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); - /* - * As per erratum i671, ROM code does not respect the PER DPLL - * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1. - * Then, in anycase, clear these bits to avoid extra latencies. - */ - prcm_block_contents.cm_autoidle_pll = - omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) & - ~OMAP3430_AUTO_PERIPH_DPLL_MASK; - prcm_block_contents.cm_clksel1_pll = - omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); - prcm_block_contents.cm_clksel2_pll = - omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); - prcm_block_contents.cm_clksel3_pll = - omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); - prcm_block_contents.cm_clken_pll_mpu = - omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); - prcm_block_contents.cm_autoidle_pll_mpu = - omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); - prcm_block_contents.cm_clksel1_pll_mpu = - omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); - prcm_block_contents.cm_clksel2_pll_mpu = - omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); + + omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); + prcm_block_contents.prcm_block_size = 0x0; /* Populate the SDRC block contents */ @@ -604,4 +569,15 @@ int omap3_ctrl_save_padconf(void) return 0; } +/** + * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle + * + * Sets the bootmode for IVA2 to idle. This is needed by the PM code to + * force disable IVA2 so that it does not prevent any low-power states. + */ +void omap3_ctrl_set_iva_bootmode_idle(void) +{ + omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, + OMAP343X_CONTROL_IVA2_BOOTMOD); +} #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index f7d7c2e..da05480 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -427,6 +427,7 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); extern void omap3630_ctrl_disable_rta(void); extern int omap3_ctrl_save_padconf(void); +extern void omap3_ctrl_set_iva_bootmode_idle(void); extern void omap2_set_globals_control(void __iomem *ctrl, void __iomem *ctrl_pad); #else diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 5d87680..b4ac3af 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -25,6 +25,7 @@ #include "soc.h" #include "omap_device.h" +#include "clock.h" /* * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle. @@ -33,22 +34,18 @@ #include "cm3xxx.h" #include "cm-regbits-34xx.h" +static struct clk *mcbsp_iclks[5]; + static int omap3_enable_st_clock(unsigned int id, bool enable) { - unsigned int w; - /* * Sidetone uses McBSP ICLK - which must not idle when sidetones * are enabled or sidetones start sounding ugly. */ - w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); if (enable) - w &= ~(1 << (id - 2)); + return omap2_clk_deny_idle(mcbsp_iclks[id]); else - w |= 1 << (id - 2); - omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); - - return 0; + return omap2_clk_allow_idle(mcbsp_iclks[id]); } static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) @@ -58,6 +55,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) struct omap_hwmod *oh_device[2]; struct omap_mcbsp_platform_data *pdata = NULL; struct platform_device *pdev; + char clk_name[11]; sscanf(oh->name, "mcbsp%d", &id); @@ -99,6 +97,8 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) oh_device[1] = omap_hwmod_lookup(( (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); pdata->enable_st_clock = omap3_enable_st_clock; + sprintf(clk_name, "mcbsp%d_ick", id); + mcbsp_iclks[id] = clk_get(NULL, clk_name); count++; } pdev = omap_device_build_ss(name, id, oh_device, count, pdata, diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index ce956b0..8c07594 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -62,16 +62,6 @@ static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; static struct clk *osc_ck, *emul_ck; -static int omap2_fclks_active(void) -{ - u32 f1, f2; - - f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); - - return (f1 | f2) ? 1 : 0; -} - static int omap2_enter_full_retention(void) { u32 l; @@ -142,17 +132,7 @@ static int sti_console_enabled; static int omap2_allow_mpu_retention(void) { - u32 l; - - /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ - l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | - OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | - OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) - return 0; - /* Check for UART3. */ - l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); - if (l & OMAP24XX_EN_UART3_MASK) + if (!omap2xxx_cm_mpu_retention_allowed()) return 0; if (sti_console_enabled) return 0; @@ -188,7 +168,7 @@ static void omap2_enter_mpu_retention(void) static int omap2_can_sleep(void) { - if (omap2_fclks_active()) + if (omap2xxx_cm_fclks_active()) return 0; if (__clk_is_enabled(osc_ck)) return 0; diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 5a2d803..93b80e5 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -430,8 +430,7 @@ static void __init omap3_iva_idle(void) OMAP3430_IVA2_MOD, CM_FCLKEN); /* Set IVA2 boot mode to 'idle' */ - omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, - OMAP343X_CONTROL_IVA2_BOOTMOD); + omap3_ctrl_set_iva_bootmode_idle(); /* Un-reset IVA2 */ omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index e110b6d..d49aff7 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -6,7 +6,6 @@ * Licensed under GPLv2 or later. */ -#include <linux/clocksource.h> #include <linux/init.h> #include <linux/kernel.h> #include <asm/sizes.h> @@ -21,13 +20,6 @@ void __init sirfsoc_init_late(void) sirfsoc_pm_init(); } -static __init void sirfsoc_init_time(void) -{ - /* initialize clocking early, we want to set the OS timer */ - sirfsoc_of_clk_init(); - clocksource_of_init(); -} - static __init void sirfsoc_map_io(void) { sirfsoc_map_lluart(); @@ -43,7 +35,6 @@ static const char *atlas6_dt_match[] __initdata = { DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ .map_io = sirfsoc_map_io, - .init_time = sirfsoc_init_time, .init_late = sirfsoc_init_late, .dt_compat = atlas6_dt_match, .restart = sirfsoc_restart, @@ -59,7 +50,6 @@ static const char *prima2_dt_match[] __initdata = { DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ .map_io = sirfsoc_map_io, - .init_time = sirfsoc_init_time, .dma_zone_size = SZ_256M, .init_late = sirfsoc_init_late, .dt_compat = prima2_dt_match, @@ -77,7 +67,6 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ .smp = smp_ops(sirfsoc_smp_ops), .map_io = sirfsoc_map_io, - .init_time = sirfsoc_init_time, .init_late = sirfsoc_init_late, .dt_compat = marco_dt_match, .restart = sirfsoc_restart, diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h index a630485..4b76806 100644 --- a/arch/arm/mach-prima2/common.h +++ b/arch/arm/mach-prima2/common.h @@ -23,7 +23,6 @@ extern void sirfsoc_secondary_startup(void); extern void sirfsoc_cpu_die(unsigned int cpu); extern void __init sirfsoc_of_irq_init(void); -extern void __init sirfsoc_of_clk_init(void); extern void sirfsoc_restart(enum reboot_mode, const char *); extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs); diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index 724d2d8..82c0b07 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -19,18 +19,10 @@ #include <linux/init.h> #include <linux/of_platform.h> #include <linux/irqchip.h> -#include <linux/dw_apb_timer.h> -#include <linux/clk-provider.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/hardware/cache-l2x0.h> -static void __init rockchip_timer_init(void) -{ - of_clk_init(NULL); - clocksource_of_init(); -} - static void __init rockchip_dt_init(void) { l2x0_of_init(0, ~0UL); @@ -47,6 +39,5 @@ static const char * const rockchip_board_dt_compat[] = { DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)") .init_machine = rockchip_dt_init, - .init_time = rockchip_timer_init, .dt_compat = rockchip_board_dt_compat, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 041da51..a2d5bb3 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -3,16 +3,7 @@ # # Licensed under GPLv2 -# temporary until we can eliminate all drivers using it. -config PLAT_S3C64XX - bool - depends on ARCH_S3C64XX - default y - select PM_GENERIC_DOMAINS - select SAMSUNG_WAKEMASK - help - Base platform code for any Samsung S3C64XX device - +if ARCH_S3C64XX # Configuration options for the S3C6410 CPU @@ -306,3 +297,5 @@ config MACH_WLF_CRAGG_6410 select SAMSUNG_GPIO_EXTRA128 help Machine support for the Wolfson Cragganmore S3C6410 variant. + +endif diff --git a/arch/arm/mach-shark/Makefile b/arch/arm/mach-shark/Makefile deleted file mode 100644 index 2965718..0000000 --- a/arch/arm/mach-shark/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y := core.o dma.o irq.o pci.o leds.o -obj-m := -obj-n := -obj- := diff --git a/arch/arm/mach-shark/Makefile.boot b/arch/arm/mach-shark/Makefile.boot deleted file mode 100644 index e40e24e..0000000 --- a/arch/arm/mach-shark/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ - zreladdr-y += 0x08008000 - diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c deleted file mode 100644 index 1d32c5e..0000000 --- a/arch/arm/mach-shark/core.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * linux/arch/arm/mach-shark/arch.c - * - * Architecture specific stuff. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/sched.h> -#include <linux/serial_8250.h> -#include <linux/io.h> -#include <linux/cpu.h> -#include <linux/reboot.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/param.h> -#include <asm/system_misc.h> - -#include <asm/mach/map.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#define ROMCARD_SIZE 0x08000000 -#define ROMCARD_START 0x10000000 - -static void shark_restart(enum reboot_mode mode, const char *cmd) -{ - short temp; - /* Reset the Machine via pc[3] of the sequoia chipset */ - outw(0x09,0x24); - temp=inw(0x26); - temp = temp | (1<<3) | (1<<10); - outw(0x09,0x24); - outw(temp,0x26); -} - -static struct plat_serial8250_port serial_platform_data[] = { - { - .iobase = 0x3f8, - .irq = 4, - .uartclk = 1843200, - .regshift = 0, - .iotype = UPIO_PORT, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - { - .iobase = 0x2f8, - .irq = 3, - .uartclk = 1843200, - .regshift = 0, - .iotype = UPIO_PORT, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - { }, -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data, - }, -}; - -static struct resource rtc_resources[] = { - [0] = { - .start = 0x70, - .end = 0x73, - .flags = IORESOURCE_IO, - }, - [1] = { - .start = IRQ_ISA_RTC_ALARM, - .end = IRQ_ISA_RTC_ALARM, - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device rtc_device = { - .name = "rtc_cmos", - .id = -1, - .resource = rtc_resources, - .num_resources = ARRAY_SIZE(rtc_resources), -}; - -static int __init shark_init(void) -{ - int ret; - - if (machine_is_shark()) - { - ret = platform_device_register(&rtc_device); - if (ret) printk(KERN_ERR "Unable to register RTC device: %d\n", ret); - ret = platform_device_register(&serial_device); - if (ret) printk(KERN_ERR "Unable to register Serial device: %d\n", ret); - } - return 0; -} - -arch_initcall(shark_init); - -extern void shark_init_irq(void); - -#define IRQ_TIMER 0 -#define HZ_TIME ((1193180 + HZ/2) / HZ) - -static irqreturn_t -shark_timer_interrupt(int irq, void *dev_id) -{ - timer_tick(); - return IRQ_HANDLED; -} - -static struct irqaction shark_timer_irq = { - .name = "Shark Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = shark_timer_interrupt, -}; - -/* - * Set up timer interrupt, and return the current time in seconds. - */ -static void __init shark_timer_init(void) -{ - outb(0x34, 0x43); /* binary, mode 0, LSB/MSB, Ch 0 */ - outb(HZ_TIME & 0xff, 0x40); /* LSB of count */ - outb(HZ_TIME >> 8, 0x40); - - setup_irq(IRQ_TIMER, &shark_timer_irq); -} - -static void shark_init_early(void) -{ - cpu_idle_poll_ctrl(true); -} - -MACHINE_START(SHARK, "Shark") - /* Maintainer: Alexander Schulz */ - .atag_offset = 0x3000, - .init_early = shark_init_early, - .init_irq = shark_init_irq, - .init_time = shark_timer_init, - .dma_zone_size = SZ_4M, - .restart = shark_restart, -MACHINE_END diff --git a/arch/arm/mach-shark/dma.c b/arch/arm/mach-shark/dma.c deleted file mode 100644 index 10b5b8b..0000000 --- a/arch/arm/mach-shark/dma.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-shark/dma.c - * - * by Alexander Schulz - * - * derived from: - * arch/arm/kernel/dma-ebsa285.c - * Copyright (C) 1998 Phil Blundell - */ - -#include <linux/init.h> - -#include <asm/dma.h> -#include <asm/mach/dma.h> - -static int __init shark_dma_init(void) -{ -#ifdef CONFIG_ISA_DMA - isa_init_dma(); -#endif - return 0; -} -core_initcall(shark_dma_init); diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S deleted file mode 100644 index d129119..0000000 --- a/arch/arm/mach-shark/include/mach/debug-macro.S +++ /dev/null @@ -1,34 +0,0 @@ -/* arch/arm/mach-shark/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart, rp, rv, tmp - mov \rp, #0x3f8 - orr \rv, \rp, #0xfe000000 - orr \rv, \rv, #0x00e00000 - orr \rp, \rp, #0x40000000 - .endm - - .macro senduart,rd,rx - strb \rd, [\rx] - .endm - - .macro waituart,rd,rx - .endm - - .macro busyuart,rd,rx - mov \rd, #0 -1001: add \rd, \rd, #1 - teq \rd, #0x10000 - bne 1001b - .endm - diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S deleted file mode 100644 index c9e49f0..0000000 --- a/arch/arm/mach-shark/include/mach/entry-macro.S +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/mach-shark/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for Shark platform - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - .macro get_irqnr_preamble, base, tmp - mov \base, #0xfe000000 - orr \base, \base, #0x00e00000 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \irqstat, #0x0C - strb \irqstat, [\base, #0x20] @outb(0x0C, 0x20) /* Poll command */ - ldrb \irqnr, [\base, #0x20] @irq = inb(0x20) & 7 - and \irqstat, \irqnr, #0x80 - teq \irqstat, #0 - beq 43f - and \irqnr, \irqnr, #7 - teq \irqnr, #2 - bne 44f -43: mov \irqstat, #0x0C - strb \irqstat, [\base, #0xa0] @outb(0x0C, 0xA0) /* Poll command */ - ldrb \irqnr, [\base, #0xa0] @irq = (inb(0xA0) & 7) + 8 - and \irqstat, \irqnr, #0x80 - teq \irqstat, #0 - beq 44f - and \irqnr, \irqnr, #7 - add \irqnr, \irqnr, #8 -44: teq \irqstat, #0 - .endm - diff --git a/arch/arm/mach-shark/include/mach/framebuffer.h b/arch/arm/mach-shark/include/mach/framebuffer.h deleted file mode 100644 index 84a5bf6..0000000 --- a/arch/arm/mach-shark/include/mach/framebuffer.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * arch/arm/mach-shark/include/mach/framebuffer.h - * - * by Alexander Schulz - * - */ - -#ifndef __ASM_ARCH_FRAMEBUFFER_H -#define __ASM_ARCH_FRAMEBUFFER_H - -/* defines for the Framebuffer */ -#define FB_START 0x06000000 -#define FB_SIZE 0x01000000 - -#endif - diff --git a/arch/arm/mach-shark/include/mach/hardware.h b/arch/arm/mach-shark/include/mach/hardware.h deleted file mode 100644 index 663f952..0000000 --- a/arch/arm/mach-shark/include/mach/hardware.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * arch/arm/mach-shark/include/mach/hardware.h - * - * by Alexander Schulz - * - * derived from: - * arch/arm/mach-ebsa110/include/mach/hardware.h - * Copyright (C) 1996-1999 Russell King. - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#define UNCACHEABLE_ADDR 0xdf010000 - -#endif - diff --git a/arch/arm/mach-shark/include/mach/irqs.h b/arch/arm/mach-shark/include/mach/irqs.h deleted file mode 100644 index c8e8a4e..0000000 --- a/arch/arm/mach-shark/include/mach/irqs.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * arch/arm/mach-shark/include/mach/irqs.h - * - * by Alexander Schulz - */ - -#define NR_IRQS 16 - -#define IRQ_ISA_KEYBOARD 1 -#define IRQ_ISA_RTC_ALARM 8 -#define I8042_KBD_IRQ 1 -#define I8042_AUX_IRQ 12 -#define IRQ_HARDDISK 14 diff --git a/arch/arm/mach-shark/include/mach/isa-dma.h b/arch/arm/mach-shark/include/mach/isa-dma.h deleted file mode 100644 index 96c43b8..0000000 --- a/arch/arm/mach-shark/include/mach/isa-dma.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * arch/arm/mach-shark/include/mach/isa-dma.h - * - * by Alexander Schulz - */ -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H - -#define MAX_DMA_CHANNELS 8 -#define DMA_ISA_CASCADE 4 - -#endif /* _ASM_ARCH_DMA_H */ - diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h deleted file mode 100644 index 1cf8d69..0000000 --- a/arch/arm/mach-shark/include/mach/memory.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * arch/arm/mach-shark/include/mach/memory.h - * - * by Alexander Schulz - * - * derived from: - * arch/arm/mach-ebsa110/include/mach/memory.h - * Copyright (c) 1996-1999 Russell King. - */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#include <asm/sizes.h> - -/* - * Physical DRAM offset. - */ -#define PLAT_PHYS_OFFSET UL(0x08000000) - -/* - * Cache flushing area - */ -#define FLUSH_BASE_PHYS 0x80000000 -#define FLUSH_BASE 0xdf000000 - -#endif diff --git a/arch/arm/mach-shark/include/mach/timex.h b/arch/arm/mach-shark/include/mach/timex.h deleted file mode 100644 index bb6eeae..0000000 --- a/arch/arm/mach-shark/include/mach/timex.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * arch/arm/mach-shark/include/mach/timex.h - * - * by Alexander Schulz - */ - -#define CLOCK_TICK_RATE 1193180 diff --git a/arch/arm/mach-shark/include/mach/uncompress.h b/arch/arm/mach-shark/include/mach/uncompress.h deleted file mode 100644 index a168435..0000000 --- a/arch/arm/mach-shark/include/mach/uncompress.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * arch/arm/mach-shark/include/mach/uncompress.h - * by Alexander Schulz - * - * derived from: - * arch/arm/mach-footbridge/include/mach/uncompress.h - * Copyright (C) 1996,1997,1998 Russell King - */ - -#define SERIAL_BASE ((volatile unsigned char *)0x400003f8) - -static inline void putc(int c) -{ - volatile int t; - - SERIAL_BASE[0] = c; - t=0x10000; - while (t--); -} - -static inline void flush(void) -{ -} - -#ifdef DEBUG -static void putn(unsigned long z) -{ - int i; - char x; - - putc('0'); - putc('x'); - for (i=0;i<8;i++) { - x='0'+((z>>((7-i)*4))&0xf); - if (x>'9') x=x-'0'+'A'-10; - putc(x); - } -} - -static void putr() -{ - putc('\n'); - putc('\r'); -} -#endif - -/* - * nothing to do - */ -#define arch_decomp_setup() diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c deleted file mode 100644 index 5dce13e..0000000 --- a/arch/arm/mach-shark/irq.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * linux/arch/arm/mach-shark/irq.c - * - * by Alexander Schulz - * - * derived from linux/arch/ppc/kernel/i8259.c and: - * arch/arm/mach-ebsa110/include/mach/irq.h - * Copyright (C) 1996-1998 Russell King - */ - -#include <linux/init.h> -#include <linux/fs.h> -#include <linux/interrupt.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/mach/irq.h> - -/* - * 8259A PIC functions to handle ISA devices: - */ - -/* - * This contains the irq mask for both 8259A irq controllers, - * Let through the cascade-interrupt no. 2 (ff-(1<<2)==fb) - */ -static unsigned char cached_irq_mask[2] = { 0xfb, 0xff }; - -/* - * These have to be protected by the irq controller spinlock - * before being called. - */ -static void shark_disable_8259A_irq(struct irq_data *d) -{ - unsigned int mask; - if (d->irq<8) { - mask = 1 << d->irq; - cached_irq_mask[0] |= mask; - outb(cached_irq_mask[1],0xA1); - } else { - mask = 1 << (d->irq-8); - cached_irq_mask[1] |= mask; - outb(cached_irq_mask[0],0x21); - } -} - -static void shark_enable_8259A_irq(struct irq_data *d) -{ - unsigned int mask; - if (d->irq<8) { - mask = ~(1 << d->irq); - cached_irq_mask[0] &= mask; - outb(cached_irq_mask[0],0x21); - } else { - mask = ~(1 << (d->irq-8)); - cached_irq_mask[1] &= mask; - outb(cached_irq_mask[1],0xA1); - } -} - -static void shark_ack_8259A_irq(struct irq_data *d){} - -static irqreturn_t bogus_int(int irq, void *dev_id) -{ - printk("Got interrupt %i!\n",irq); - return IRQ_NONE; -} - -static struct irqaction cascade; - -static struct irq_chip fb_chip = { - .name = "XT-PIC", - .irq_ack = shark_ack_8259A_irq, - .irq_mask = shark_disable_8259A_irq, - .irq_unmask = shark_enable_8259A_irq, -}; - -void __init shark_init_irq(void) -{ - int irq; - - for (irq = 0; irq < NR_IRQS; irq++) { - irq_set_chip_and_handler(irq, &fb_chip, handle_edge_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - - /* init master interrupt controller */ - outb(0x11, 0x20); /* Start init sequence, edge triggered (level: 0x19)*/ - outb(0x00, 0x21); /* Vector base */ - outb(0x04, 0x21); /* Cascade (slave) on IRQ2 */ - outb(0x03, 0x21); /* Select 8086 mode , auto eoi*/ - outb(0x0A, 0x20); - /* init slave interrupt controller */ - outb(0x11, 0xA0); /* Start init sequence, edge triggered */ - outb(0x08, 0xA1); /* Vector base */ - outb(0x02, 0xA1); /* Cascade (slave) on IRQ2 */ - outb(0x03, 0xA1); /* Select 8086 mode, auto eoi */ - outb(0x0A, 0xA0); - outb(cached_irq_mask[1],0xA1); - outb(cached_irq_mask[0],0x21); - //request_region(0x20,0x2,"pic1"); - //request_region(0xA0,0x2,"pic2"); - - cascade.handler = bogus_int; - cascade.name = "cascade"; - setup_irq(2,&cascade); -} - diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c deleted file mode 100644 index 081c778..0000000 --- a/arch/arm/mach-shark/leds.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * DIGITAL Shark LED control routines. - * - * Driver for the 3 user LEDs found on the Shark - * Based on Versatile and RealView machine LED code - * - * License terms: GNU General Public License (GPL) version 2 - * Author: Bryan Wu <bryan.wu@canonical.com> - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <linux/slab.h> -#include <linux/leds.h> - -#include <asm/mach-types.h> - -#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS) -struct shark_led { - struct led_classdev cdev; - u8 mask; -}; - -/* - * The triggers lines up below will only be used if the - * LED triggers are compiled in. - */ -static const struct { - const char *name; - const char *trigger; -} shark_leds[] = { - { "shark:amber0", "default-on", }, /* Bit 5 */ - { "shark:green", "heartbeat", }, /* Bit 6 */ - { "shark:amber1", "cpu0" }, /* Bit 7 */ -}; - -static u16 led_reg_read(void) -{ - outw(0x09, 0x24); - return inw(0x26); -} - -static void led_reg_write(u16 value) -{ - outw(0x09, 0x24); - outw(value, 0x26); -} - -static void shark_led_set(struct led_classdev *cdev, - enum led_brightness b) -{ - struct shark_led *led = container_of(cdev, - struct shark_led, cdev); - u16 reg = led_reg_read(); - - if (b != LED_OFF) - reg |= led->mask; - else - reg &= ~led->mask; - - led_reg_write(reg); -} - -static enum led_brightness shark_led_get(struct led_classdev *cdev) -{ - struct shark_led *led = container_of(cdev, - struct shark_led, cdev); - u16 reg = led_reg_read(); - - return (reg & led->mask) ? LED_FULL : LED_OFF; -} - -static int __init shark_leds_init(void) -{ - int i; - u16 reg; - - if (!machine_is_shark()) - return -ENODEV; - - for (i = 0; i < ARRAY_SIZE(shark_leds); i++) { - struct shark_led *led; - - led = kzalloc(sizeof(*led), GFP_KERNEL); - if (!led) - break; - - led->cdev.name = shark_leds[i].name; - led->cdev.brightness_set = shark_led_set; - led->cdev.brightness_get = shark_led_get; - led->cdev.default_trigger = shark_leds[i].trigger; - - /* Count in 5 bits offset */ - led->mask = BIT(i + 5); - - if (led_classdev_register(NULL, &led->cdev) < 0) { - kfree(led); - break; - } - } - - /* Make LEDs independent of power-state */ - request_region(0x24, 4, "led_reg"); - reg = led_reg_read(); - reg |= 1 << 10; - led_reg_write(reg); - - return 0; -} - -/* - * Since we may have triggers on any subsystem, defer registration - * until after subsystem_init. - */ -fs_initcall(shark_leds_init); -#endif diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c deleted file mode 100644 index 6d91a91..0000000 --- a/arch/arm/mach-shark/pci.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * linux/arch/arm/mach-shark/pci.c - * - * PCI bios-type initialisation for PCI machines - * - * Bits taken from various places. - */ -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/init.h> -#include <linux/io.h> -#include <video/vga.h> - -#include <asm/irq.h> -#include <asm/mach/pci.h> -#include <asm/mach-types.h> - -#define IO_START 0x40000000 - -static int __init shark_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - if (dev->bus->number == 0) - if (dev->devfn == 0) - return 255; - else - return 11; - else - return 255; -} - -extern void __init via82c505_preinit(void); - -static struct hw_pci shark_pci __initdata = { - .setup = via82c505_setup, - .map_irq = shark_map_irq, - .nr_controllers = 1, - .ops = &via82c505_ops, - .preinit = via82c505_preinit, -}; - -static int __init shark_pci_init(void) -{ - if (!machine_is_shark()) - return -ENODEV; - - pcibios_min_io = 0x6000; - pcibios_min_mem = 0x50000000; - vga_base = 0xe8000000; - - pci_ioremap_io(0, IO_START); - - pci_common_init(&shark_pci); - - return 0; -} - -subsys_initcall(shark_pci_init); diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c index a23fa71..3276afc 100644 --- a/arch/arm/mach-shmobile/board-ape6evm-reference.c +++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c @@ -57,7 +57,7 @@ static const char *ape6evm_boards_compat_dt[] __initdata = { }; DT_MACHINE_START(APE6EVM_DT, "ape6evm") - .init_early = r8a73a4_init_delay, + .init_early = r8a73a4_init_early, .init_machine = ape6evm_add_standard_devices, .dt_compat = ape6evm_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c index 24b87eea..1e9313a 100644 --- a/arch/arm/mach-shmobile/board-ape6evm.c +++ b/arch/arm/mach-shmobile/board-ape6evm.c @@ -86,7 +86,7 @@ static struct gpio_keys_button gpio_buttons[] = { GPIO_KEY(KEY_VOLUMEDOWN, 329, "S21"), }; -static struct __initdata gpio_keys_platform_data ape6evm_keys_pdata = { +static struct gpio_keys_platform_data ape6evm_keys_pdata __initdata = { .buttons = gpio_buttons, .nbuttons = ARRAY_SIZE(gpio_buttons), }; @@ -240,7 +240,7 @@ static const char *ape6evm_boards_compat_dt[] __initdata = { }; DT_MACHINE_START(APE6EVM_DT, "ape6evm") - .init_early = r8a73a4_init_delay, + .init_early = r8a73a4_init_early, .init_machine = ape6evm_add_standard_devices, .dt_compat = ape6evm_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index 6b9faf3..f2bf61b 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c @@ -101,6 +101,12 @@ static struct resource sdhi0_resources[] __initdata = { DEFINE_RES_IRQ(gic_iid(0x77)), }; +/* Ether */ +static struct resource ether_resources[] __initdata = { + DEFINE_RES_MEM(0xfde00000, 0x400), + DEFINE_RES_IRQ(gic_iid(0x89)), +}; + static struct sh_eth_plat_data ether_platform_data __initdata = { .phy = 0x01, .edmac_endian = EDMAC_LITTLE_ENDIAN, @@ -162,10 +168,6 @@ static struct sh_mmcif_plat_data sh_mmcif_plat __initdata = { MMC_CAP_NEEDS_POLL, }; -static struct rcar_vin_platform_data vin_platform_data __initdata = { - .flags = RCAR_VIN_BT656, -}; - /* In the default configuration both decoders reside on I2C bus 0 */ #define BOCKW_CAMERA(idx) \ static struct i2c_board_info camera##idx##_info = { \ @@ -181,6 +183,30 @@ static struct soc_camera_link iclink##idx##_ml86v7667 __initdata = { \ BOCKW_CAMERA(0); BOCKW_CAMERA(1); +/* VIN */ +static struct rcar_vin_platform_data vin_platform_data __initdata = { + .flags = RCAR_VIN_BT656, +}; + +#define R8A7778_VIN(idx) \ +static struct resource vin##idx##_resources[] __initdata = { \ + DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ + DEFINE_RES_IRQ(gic_iid(0x5a)), \ +}; \ + \ +static struct platform_device_info vin##idx##_info __initdata = { \ + .parent = &platform_bus, \ + .name = "r8a7778-vin", \ + .id = idx, \ + .res = vin##idx##_resources, \ + .num_res = ARRAY_SIZE(vin##idx##_resources), \ + .dma_mask = DMA_BIT_MASK(32), \ + .data = &vin_platform_data, \ + .size_data = sizeof(vin_platform_data), \ +} +R8A7778_VIN(0); +R8A7778_VIN(1); + static const struct pinctrl_map bockw_pinctrl_map[] = { /* Ether */ PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778", @@ -235,11 +261,17 @@ static void __init bockw_init(void) r8a7778_clock_init(); r8a7778_init_irq_extpin(1); r8a7778_add_standard_devices(); - r8a7778_add_ether_device(ðer_platform_data); - r8a7778_add_vin_device(0, &vin_platform_data); + + platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, + ether_resources, + ARRAY_SIZE(ether_resources), + ðer_platform_data, + sizeof(ether_platform_data)); + + platform_device_register_full(&vin0_info); /* VIN1 has a pin conflict with Ether */ if (!IS_ENABLED(CONFIG_SH_ETH)) - r8a7778_add_vin_device(1, &vin_platform_data); + platform_device_register_full(&vin1_info); platform_device_register_data(&platform_bus, "soc-camera-pdrv", 0, &iclink0_ml86v7667, sizeof(iclink0_ml86v7667)); diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c index 9c316a1..2856f51 100644 --- a/arch/arm/mach-shmobile/board-lager-reference.c +++ b/arch/arm/mach-shmobile/board-lager-reference.c @@ -38,7 +38,7 @@ static const char *lager_boards_compat_dt[] __initdata = { }; DT_MACHINE_START(LAGER_DT, "lager") - .init_early = r8a7790_init_delay, + .init_early = r8a7790_init_early, .init_machine = lager_add_standard_devices, .init_time = r8a7790_timer_init, .dt_compat = lager_boards_compat_dt, diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index 5930af8..66edb7e 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -56,7 +56,7 @@ static struct gpio_led lager_leds[] = { }, }; -static __initdata struct gpio_led_platform_data lager_leds_pdata = { +static const struct gpio_led_platform_data lager_leds_pdata __initconst = { .leds = lager_leds, .num_leds = ARRAY_SIZE(lager_leds), }; @@ -72,7 +72,7 @@ static struct gpio_keys_button gpio_buttons[] = { GPIO_KEY(KEY_1, RCAR_GP_PIN(1, 14), "SW2-pin1"), }; -static __initdata struct gpio_keys_platform_data lager_keys_pdata = { +static const struct gpio_keys_platform_data lager_keys_pdata __initconst = { .buttons = gpio_buttons, .nbuttons = ARRAY_SIZE(gpio_buttons), }; @@ -84,24 +84,24 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] = }; /* MMCIF */ -static struct sh_mmcif_plat_data mmcif1_pdata __initdata = { +static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = { .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, }; -static struct resource mmcif1_resources[] __initdata = { +static const struct resource mmcif1_resources[] __initconst = { DEFINE_RES_MEM_NAMED(0xee220000, 0x80, "MMCIF1"), DEFINE_RES_IRQ(gic_spi(170)), }; /* Ether */ -static struct sh_eth_plat_data ether_pdata __initdata = { +static const struct sh_eth_plat_data ether_pdata __initconst = { .phy = 0x1, .edmac_endian = EDMAC_LITTLE_ENDIAN, .phy_interface = PHY_INTERFACE_MODE_RMII, .ether_link_active_low = 1, }; -static struct resource ether_resources[] __initdata = { +static const struct resource ether_resources[] __initconst = { DEFINE_RES_MEM(0xee700000, 0x400), DEFINE_RES_IRQ(gic_spi(162)), }; @@ -180,13 +180,13 @@ static void __init lager_init(void) phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup); } -static const char *lager_boards_compat_dt[] __initdata = { +static const char * const lager_boards_compat_dt[] __initconst = { "renesas,lager", NULL, }; DT_MACHINE_START(LAGER_DT, "lager") - .init_early = r8a7790_init_delay, + .init_early = r8a7790_init_early, .init_time = r8a7790_timer_init, .init_machine = lager_init, .dt_compat = lager_boards_compat_dt, diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h index f3a9b70..5214338 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h @@ -5,6 +5,6 @@ void r8a73a4_add_standard_devices(void); void r8a73a4_add_dt_devices(void); void r8a73a4_clock_init(void); void r8a73a4_pinmux_init(void); -void r8a73a4_init_delay(void); +void r8a73a4_init_early(void); #endif /* __ASM_R8A73A4_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h index adfcf51..48933def 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7778.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h @@ -23,9 +23,6 @@ extern void r8a7778_add_standard_devices(void); extern void r8a7778_add_standard_devices_dt(void); -extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); -extern void r8a7778_add_vin_device(int id, - struct rcar_vin_platform_data *pdata); extern void r8a7778_add_dt_devices(void); extern void r8a7778_init_late(void); diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h index 788d559..177a837 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h @@ -5,7 +5,7 @@ void r8a7790_add_standard_devices(void); void r8a7790_add_dt_devices(void); void r8a7790_clock_init(void); void r8a7790_pinmux_init(void); -void r8a7790_init_delay(void); +void r8a7790_init_early(void); void r8a7790_timer_init(void); #define MD(nr) BIT(nr) diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index 89491700..53a89627 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -207,7 +207,7 @@ void __init r8a73a4_add_standard_devices(void) r8a73a4_register_thermal(); } -void __init r8a73a4_init_delay(void) +void __init r8a73a4_init_early(void) { #ifndef CONFIG_ARM_ARCH_TIMER shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */ @@ -222,7 +222,7 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = { }; DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") - .init_early = r8a73a4_init_delay, + .init_early = r8a73a4_init_early, .dt_compat = r8a73a4_boards_compat_dt, MACHINE_END #endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 6a2657e..468ee65 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -174,20 +174,6 @@ static struct platform_device_info hci##_info __initdata = { \ USB_PLATFORM_INFO(ehci); USB_PLATFORM_INFO(ohci); -/* Ether */ -static struct resource ether_resources[] __initdata = { - DEFINE_RES_MEM(0xfde00000, 0x400), - DEFINE_RES_IRQ(gic_iid(0x89)), -}; - -void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) -{ - platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, - ether_resources, - ARRAY_SIZE(ether_resources), - pdata, sizeof(*pdata)); -} - /* PFC/GPIO */ static struct resource pfc_resources[] __initdata = { DEFINE_RES_MEM(0xfffc0000, 0x118), @@ -272,7 +258,7 @@ static struct resource hspi_resources[] __initdata = { DEFINE_RES_IRQ(gic_iid(0x75)), }; -void __init r8a7778_register_hspi(int id) +static void __init r8a7778_register_hspi(int id) { BUG_ON(id < 0 || id > 2); @@ -281,40 +267,6 @@ void __init r8a7778_register_hspi(int id) hspi_resources + (2 * id), 2); } -/* VIN */ -#define R8A7778_VIN(idx) \ -static struct resource vin##idx##_resources[] __initdata = { \ - DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ - DEFINE_RES_IRQ(gic_iid(0x5a)), \ -}; \ - \ -static struct platform_device_info vin##idx##_info __initdata = { \ - .parent = &platform_bus, \ - .name = "r8a7778-vin", \ - .id = idx, \ - .res = vin##idx##_resources, \ - .num_res = ARRAY_SIZE(vin##idx##_resources), \ - .dma_mask = DMA_BIT_MASK(32), \ -} - -R8A7778_VIN(0); -R8A7778_VIN(1); - -static struct platform_device_info *vin_info_table[] __initdata = { - &vin0_info, - &vin1_info, -}; - -void __init r8a7778_add_vin_device(int id, struct rcar_vin_platform_data *pdata) -{ - BUG_ON(id < 0 || id > 1); - - vin_info_table[id]->data = pdata; - vin_info_table[id]->size_data = sizeof(*pdata); - - platform_device_register_full(vin_info_table[id]); -} - void __init r8a7778_add_dt_devices(void) { int i; diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index d0f5c9f..e0d29a2 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -31,17 +31,18 @@ #include <mach/r8a7790.h> #include <asm/mach/arch.h> -static struct resource pfc_resources[] __initdata = { +static const struct resource pfc_resources[] __initconst = { DEFINE_RES_MEM(0xe6060000, 0x250), }; #define R8A7790_GPIO(idx) \ -static struct resource r8a7790_gpio##idx##_resources[] __initdata = { \ +static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \ DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \ DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ }; \ \ -static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \ +static const struct gpio_rcar_config \ +r8a7790_gpio##idx##_platform_data __initconst = { \ .gpio_base = 32 * (idx), \ .irq_base = 0, \ .number_of_pins = 32, \ @@ -112,7 +113,7 @@ void __init r8a7790_pinmux_init(void) enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, HSCIF0, HSCIF1 }; -static struct plat_sci_port scif[] __initdata = { +static const struct plat_sci_port scif[] __initconst = { SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ @@ -131,11 +132,11 @@ static inline void r8a7790_register_scif(int idx) sizeof(struct plat_sci_port)); } -static struct renesas_irqc_config irqc0_data __initdata = { +static const struct renesas_irqc_config irqc0_data __initconst = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ }; -static struct resource irqc0_resources[] __initdata = { +static const struct resource irqc0_resources[] __initconst = { DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ @@ -150,7 +151,7 @@ static struct resource irqc0_resources[] __initdata = { &irqc##idx##_data, \ sizeof(struct renesas_irqc_config)) -static struct resource thermal_resources[] __initdata = { +static const struct resource thermal_resources[] __initconst = { DEFINE_RES_MEM(0xe61f0000, 0x14), DEFINE_RES_MEM(0xe61f0100, 0x38), DEFINE_RES_IRQ(gic_spi(69)), @@ -161,13 +162,13 @@ static struct resource thermal_resources[] __initdata = { thermal_resources, \ ARRAY_SIZE(thermal_resources)) -static struct sh_timer_config cmt00_platform_data __initdata = { +static const struct sh_timer_config cmt00_platform_data __initconst = { .name = "CMT00", .timer_bit = 0, .clockevent_rating = 80, }; -static struct resource cmt00_resources[] __initdata = { +static const struct resource cmt00_resources[] __initconst = { DEFINE_RES_MEM(0xffca0510, 0x0c), DEFINE_RES_MEM(0xffca0500, 0x04), DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */ @@ -267,7 +268,7 @@ void __init r8a7790_timer_init(void) clocksource_of_init(); } -void __init r8a7790_init_delay(void) +void __init r8a7790_init_early(void) { #ifndef CONFIG_ARM_ARCH_TIMER shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */ @@ -276,13 +277,13 @@ void __init r8a7790_init_delay(void) #ifdef CONFIG_USE_OF -static const char *r8a7790_boards_compat_dt[] __initdata = { +static const char * const r8a7790_boards_compat_dt[] __initconst = { "renesas,r8a7790", NULL, }; DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") - .init_early = r8a7790_init_delay, + .init_early = r8a7790_init_early, .init_time = r8a7790_timer_init, .dt_compat = r8a7790_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index dd86db4..037100a 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -4,7 +4,6 @@ config ARCH_SOCFPGA select ARM_AMBA select ARM_GIC select CACHE_L2X0 - select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 select DW_APB_TIMER_OF diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index bfce964..dd0d49c 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -14,7 +14,6 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#include <linux/clk-provider.h> #include <linux/irqchip.h> #include <linux/of_address.h> #include <linux/of_irq.h> @@ -107,7 +106,6 @@ static void __init socfpga_cyclone5_init(void) { l2x0_of_init(0, ~0UL); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - of_clk_init(NULL); socfpga_init_clocks(); } diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig index df0d59a..ac1710e6 100644 --- a/arch/arm/mach-spear/Kconfig +++ b/arch/arm/mach-spear/Kconfig @@ -7,11 +7,9 @@ menuconfig PLAT_SPEAR default PLAT_SPEAR_SINGLE select ARCH_REQUIRE_GPIOLIB select ARM_AMBA - select CLKDEV_LOOKUP select CLKSRC_MMIO select COMMON_CLK select GENERIC_CLOCKEVENTS - select HAVE_CLK if PLAT_SPEAR diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c index 8fe6f0c..1217fb5 100644 --- a/arch/arm/mach-sti/board-dt.c +++ b/arch/arm/mach-sti/board-dt.c @@ -7,9 +7,8 @@ * published by the Free Software Foundation. */ -#include <linux/clk-provider.h> -#include <linux/clocksource.h> #include <linux/irq.h> +#include <linux/of_platform.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> @@ -28,11 +27,10 @@ void __init stih41x_l2x0_init(void) l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); } -static void __init stih41x_timer_init(void) +static void __init stih41x_machine_init(void) { - of_clk_init(NULL); - clocksource_of_init(); stih41x_l2x0_init(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char *stih41x_dt_match[] __initdata = { @@ -42,7 +40,7 @@ static const char *stih41x_dt_match[] __initdata = { }; DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree") - .init_time = stih41x_timer_init, + .init_machine = stih41x_machine_init, .smp = smp_ops(sti_smp_ops), .dt_compat = stih41x_dt_match, MACHINE_END diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index e79fb34..90dda62 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -10,7 +10,6 @@ * warranty of any kind, whether express or implied. */ -#include <linux/clocksource.h> #include <linux/delay.h> #include <linux/kernel.h> #include <linux/init.h> @@ -20,8 +19,6 @@ #include <linux/io.h> #include <linux/reboot.h> -#include <linux/clk/sunxi.h> - #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/system_misc.h> @@ -116,12 +113,6 @@ static void sunxi_setup_restart(void) arm_pm_restart = of_id->data; } -static void __init sunxi_timer_init(void) -{ - sunxi_init_clocks(); - clocksource_of_init(); -} - static void __init sunxi_dt_init(void) { sunxi_setup_restart(); @@ -140,6 +131,5 @@ static const char * const sunxi_board_dt_compat[] = { DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") .init_machine = sunxi_dt_init, - .init_time = sunxi_timer_init, .dt_compat = sunxi_board_dt_compat, MACHINE_END diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 67a76f2..56bb6c3 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -3,7 +3,6 @@ config ARCH_TEGRA select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select ARM_GIC - select CLKDEV_LOOKUP select CLKSRC_MMIO select CLKSRC_OF select COMMON_CLK @@ -11,7 +10,6 @@ config ARCH_TEGRA select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP - select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select MIGHT_HAVE_PCI @@ -53,9 +51,9 @@ config ARCH_TEGRA_3x_SOC config ARCH_TEGRA_114_SOC bool "Enable support for Tegra114 family" - select HAVE_ARM_ARCH_TIMER select ARM_ERRATA_798181 select ARM_L1_CACHE_SHIFT_6 + select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA114 help Support for NVIDIA Tegra T114 processor family, based on the diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index e7e5f45..97eb48e 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,6 +1,5 @@ asflags-y += -march=armv7-a -obj-y += common.o obj-y += io.o obj-y += irq.o obj-y += fuse.o diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 740e16f..06f0240 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -20,12 +20,11 @@ #include <linux/platform_device.h> #include <linux/rfkill-gpio.h> #include "board.h" -#include "board-paz00.h" static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = { .name = "wifi_rfkill", - .reset_gpio = TEGRA_WIFI_RST, - .shutdown_gpio = TEGRA_WIFI_PWRN, + .reset_gpio = 25, /* PD1 */ + .shutdown_gpio = 85, /* PK5 */ .type = RFKILL_TYPE_WLAN, }; diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h deleted file mode 100644 index 25c08ec..0000000 --- a/arch/arm/mach-tegra/board-paz00.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * arch/arm/mach-tegra/board-paz00.h - * - * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _MACH_TEGRA_BOARD_PAZ00_H -#define _MACH_TEGRA_BOARD_PAZ00_H - -#include "gpio-names.h" - -#define TEGRA_WIFI_PWRN TEGRA_GPIO_PK5 -#define TEGRA_WIFI_RST TEGRA_GPIO_PD1 - -#endif diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index db6810d..bcf5dbf 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -25,20 +25,8 @@ #include <linux/types.h> #include <linux/reboot.h> -void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd); - -void __init tegra_init_early(void); void __init tegra_map_common_io(void); void __init tegra_init_irq(void); -void __init tegra_dt_init_irq(void); - -void tegra_init_late(void); - -#ifdef CONFIG_DEBUG_FS -int tegra_clk_debugfs_init(void); -#else -static inline int tegra_clk_debugfs_init(void) { return 0; } -#endif int __init tegra_powergate_init(void); #if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c deleted file mode 100644 index 94a119a..0000000 --- a/arch/arm/mach-tegra/common.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * arch/arm/mach-tegra/common.c - * - * Copyright (c) 2013 NVIDIA Corporation. All rights reserved. - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross <ccross@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/init.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/reboot.h> -#include <linux/irqchip.h> -#include <linux/clk-provider.h> - -#include <asm/hardware/cache-l2x0.h> - -#include "board.h" -#include "common.h" -#include "cpuidle.h" -#include "fuse.h" -#include "iomap.h" -#include "irq.h" -#include "pmc.h" -#include "apbio.h" -#include "sleep.h" -#include "pm.h" -#include "reset.h" - -/* - * Storage for debug-macro.S's state. - * - * This must be in .data not .bss so that it gets initialized each time the - * kernel is loaded. The data is declared here rather than debug-macro.S so - * that multiple inclusions of debug-macro.S point at the same data. - */ -u32 tegra_uart_config[4] = { - /* Debug UART initialization required */ - 1, - /* Debug UART physical address */ - 0, - /* Debug UART virtual address */ - 0, - /* Scratch space for debug macro */ - 0, -}; - -#ifdef CONFIG_OF -void __init tegra_dt_init_irq(void) -{ - of_clk_init(NULL); - tegra_pmc_init(); - tegra_init_irq(); - irqchip_init(); - tegra_legacy_irq_syscore_init(); -} -#endif - -void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd) -{ - void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0); - u32 reg; - - reg = readl_relaxed(reset); - reg |= 0x10; - writel_relaxed(reg, reset); -} - -static void __init tegra_init_cache(void) -{ -#ifdef CONFIG_CACHE_L2X0 - int ret; - void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; - u32 aux_ctrl, cache_type; - - cache_type = readl(p + L2X0_CACHE_TYPE); - aux_ctrl = (cache_type & 0x700) << (17-8); - aux_ctrl |= 0x7C400001; - - ret = l2x0_of_init(aux_ctrl, 0x8200c3fe); - if (!ret) - l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs); -#endif - -} - -void __init tegra_init_early(void) -{ - tegra_cpu_reset_handler_init(); - tegra_apb_io_init(); - tegra_init_fuse(); - tegra_init_cache(); - tegra_powergate_init(); - tegra_hotplug_init(); -} - -void __init tegra_init_late(void) -{ - tegra_init_suspend(); - tegra_cpuidle_init(); - tegra_powergate_debugfs_init(); -} diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index e035cd2..f3b5d0d 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -112,7 +112,7 @@ u32 tegra_read_chipid(void) return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); } -void tegra_init_fuse(void) +void __init tegra_init_fuse(void) { u32 id; diff --git a/arch/arm/mach-tegra/gpio-names.h b/arch/arm/mach-tegra/gpio-names.h deleted file mode 100644 index f28220a..0000000 --- a/arch/arm/mach-tegra/gpio-names.h +++ /dev/null @@ -1,247 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/gpio-names.h - * - * Copyright (c) 2010 Google, Inc - * - * Author: - * Erik Gilling <konkers@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_TEGRA_GPIO_NAMES_H -#define __MACH_TEGRA_GPIO_NAMES_H - -#define TEGRA_GPIO_PA0 0 -#define TEGRA_GPIO_PA1 1 -#define TEGRA_GPIO_PA2 2 -#define TEGRA_GPIO_PA3 3 -#define TEGRA_GPIO_PA4 4 -#define TEGRA_GPIO_PA5 5 -#define TEGRA_GPIO_PA6 6 -#define TEGRA_GPIO_PA7 7 -#define TEGRA_GPIO_PB0 8 -#define TEGRA_GPIO_PB1 9 -#define TEGRA_GPIO_PB2 10 -#define TEGRA_GPIO_PB3 11 -#define TEGRA_GPIO_PB4 12 -#define TEGRA_GPIO_PB5 13 -#define TEGRA_GPIO_PB6 14 -#define TEGRA_GPIO_PB7 15 -#define TEGRA_GPIO_PC0 16 -#define TEGRA_GPIO_PC1 17 -#define TEGRA_GPIO_PC2 18 -#define TEGRA_GPIO_PC3 19 -#define TEGRA_GPIO_PC4 20 -#define TEGRA_GPIO_PC5 21 -#define TEGRA_GPIO_PC6 22 -#define TEGRA_GPIO_PC7 23 -#define TEGRA_GPIO_PD0 24 -#define TEGRA_GPIO_PD1 25 -#define TEGRA_GPIO_PD2 26 -#define TEGRA_GPIO_PD3 27 -#define TEGRA_GPIO_PD4 28 -#define TEGRA_GPIO_PD5 29 -#define TEGRA_GPIO_PD6 30 -#define TEGRA_GPIO_PD7 31 -#define TEGRA_GPIO_PE0 32 -#define TEGRA_GPIO_PE1 33 -#define TEGRA_GPIO_PE2 34 -#define TEGRA_GPIO_PE3 35 -#define TEGRA_GPIO_PE4 36 -#define TEGRA_GPIO_PE5 37 -#define TEGRA_GPIO_PE6 38 -#define TEGRA_GPIO_PE7 39 -#define TEGRA_GPIO_PF0 40 -#define TEGRA_GPIO_PF1 41 -#define TEGRA_GPIO_PF2 42 -#define TEGRA_GPIO_PF3 43 -#define TEGRA_GPIO_PF4 44 -#define TEGRA_GPIO_PF5 45 -#define TEGRA_GPIO_PF6 46 -#define TEGRA_GPIO_PF7 47 -#define TEGRA_GPIO_PG0 48 -#define TEGRA_GPIO_PG1 49 -#define TEGRA_GPIO_PG2 50 -#define TEGRA_GPIO_PG3 51 -#define TEGRA_GPIO_PG4 52 -#define TEGRA_GPIO_PG5 53 -#define TEGRA_GPIO_PG6 54 -#define TEGRA_GPIO_PG7 55 -#define TEGRA_GPIO_PH0 56 -#define TEGRA_GPIO_PH1 57 -#define TEGRA_GPIO_PH2 58 -#define TEGRA_GPIO_PH3 59 -#define TEGRA_GPIO_PH4 60 -#define TEGRA_GPIO_PH5 61 -#define TEGRA_GPIO_PH6 62 -#define TEGRA_GPIO_PH7 63 -#define TEGRA_GPIO_PI0 64 -#define TEGRA_GPIO_PI1 65 -#define TEGRA_GPIO_PI2 66 -#define TEGRA_GPIO_PI3 67 -#define TEGRA_GPIO_PI4 68 -#define TEGRA_GPIO_PI5 69 -#define TEGRA_GPIO_PI6 70 -#define TEGRA_GPIO_PI7 71 -#define TEGRA_GPIO_PJ0 72 -#define TEGRA_GPIO_PJ1 73 -#define TEGRA_GPIO_PJ2 74 -#define TEGRA_GPIO_PJ3 75 -#define TEGRA_GPIO_PJ4 76 -#define TEGRA_GPIO_PJ5 77 -#define TEGRA_GPIO_PJ6 78 -#define TEGRA_GPIO_PJ7 79 -#define TEGRA_GPIO_PK0 80 -#define TEGRA_GPIO_PK1 81 -#define TEGRA_GPIO_PK2 82 -#define TEGRA_GPIO_PK3 83 -#define TEGRA_GPIO_PK4 84 -#define TEGRA_GPIO_PK5 85 -#define TEGRA_GPIO_PK6 86 -#define TEGRA_GPIO_PK7 87 -#define TEGRA_GPIO_PL0 88 -#define TEGRA_GPIO_PL1 89 -#define TEGRA_GPIO_PL2 90 -#define TEGRA_GPIO_PL3 91 -#define TEGRA_GPIO_PL4 92 -#define TEGRA_GPIO_PL5 93 -#define TEGRA_GPIO_PL6 94 -#define TEGRA_GPIO_PL7 95 -#define TEGRA_GPIO_PM0 96 -#define TEGRA_GPIO_PM1 97 -#define TEGRA_GPIO_PM2 98 -#define TEGRA_GPIO_PM3 99 -#define TEGRA_GPIO_PM4 100 -#define TEGRA_GPIO_PM5 101 -#define TEGRA_GPIO_PM6 102 -#define TEGRA_GPIO_PM7 103 -#define TEGRA_GPIO_PN0 104 -#define TEGRA_GPIO_PN1 105 -#define TEGRA_GPIO_PN2 106 -#define TEGRA_GPIO_PN3 107 -#define TEGRA_GPIO_PN4 108 -#define TEGRA_GPIO_PN5 109 -#define TEGRA_GPIO_PN6 110 -#define TEGRA_GPIO_PN7 111 -#define TEGRA_GPIO_PO0 112 -#define TEGRA_GPIO_PO1 113 -#define TEGRA_GPIO_PO2 114 -#define TEGRA_GPIO_PO3 115 -#define TEGRA_GPIO_PO4 116 -#define TEGRA_GPIO_PO5 117 -#define TEGRA_GPIO_PO6 118 -#define TEGRA_GPIO_PO7 119 -#define TEGRA_GPIO_PP0 120 -#define TEGRA_GPIO_PP1 121 -#define TEGRA_GPIO_PP2 122 -#define TEGRA_GPIO_PP3 123 -#define TEGRA_GPIO_PP4 124 -#define TEGRA_GPIO_PP5 125 -#define TEGRA_GPIO_PP6 126 -#define TEGRA_GPIO_PP7 127 -#define TEGRA_GPIO_PQ0 128 -#define TEGRA_GPIO_PQ1 129 -#define TEGRA_GPIO_PQ2 130 -#define TEGRA_GPIO_PQ3 131 -#define TEGRA_GPIO_PQ4 132 -#define TEGRA_GPIO_PQ5 133 -#define TEGRA_GPIO_PQ6 134 -#define TEGRA_GPIO_PQ7 135 -#define TEGRA_GPIO_PR0 136 -#define TEGRA_GPIO_PR1 137 -#define TEGRA_GPIO_PR2 138 -#define TEGRA_GPIO_PR3 139 -#define TEGRA_GPIO_PR4 140 -#define TEGRA_GPIO_PR5 141 -#define TEGRA_GPIO_PR6 142 -#define TEGRA_GPIO_PR7 143 -#define TEGRA_GPIO_PS0 144 -#define TEGRA_GPIO_PS1 145 -#define TEGRA_GPIO_PS2 146 -#define TEGRA_GPIO_PS3 147 -#define TEGRA_GPIO_PS4 148 -#define TEGRA_GPIO_PS5 149 -#define TEGRA_GPIO_PS6 150 -#define TEGRA_GPIO_PS7 151 -#define TEGRA_GPIO_PT0 152 -#define TEGRA_GPIO_PT1 153 -#define TEGRA_GPIO_PT2 154 -#define TEGRA_GPIO_PT3 155 -#define TEGRA_GPIO_PT4 156 -#define TEGRA_GPIO_PT5 157 -#define TEGRA_GPIO_PT6 158 -#define TEGRA_GPIO_PT7 159 -#define TEGRA_GPIO_PU0 160 -#define TEGRA_GPIO_PU1 161 -#define TEGRA_GPIO_PU2 162 -#define TEGRA_GPIO_PU3 163 -#define TEGRA_GPIO_PU4 164 -#define TEGRA_GPIO_PU5 165 -#define TEGRA_GPIO_PU6 166 -#define TEGRA_GPIO_PU7 167 -#define TEGRA_GPIO_PV0 168 -#define TEGRA_GPIO_PV1 169 -#define TEGRA_GPIO_PV2 170 -#define TEGRA_GPIO_PV3 171 -#define TEGRA_GPIO_PV4 172 -#define TEGRA_GPIO_PV5 173 -#define TEGRA_GPIO_PV6 174 -#define TEGRA_GPIO_PV7 175 -#define TEGRA_GPIO_PW0 176 -#define TEGRA_GPIO_PW1 177 -#define TEGRA_GPIO_PW2 178 -#define TEGRA_GPIO_PW3 179 -#define TEGRA_GPIO_PW4 180 -#define TEGRA_GPIO_PW5 181 -#define TEGRA_GPIO_PW6 182 -#define TEGRA_GPIO_PW7 183 -#define TEGRA_GPIO_PX0 184 -#define TEGRA_GPIO_PX1 185 -#define TEGRA_GPIO_PX2 186 -#define TEGRA_GPIO_PX3 187 -#define TEGRA_GPIO_PX4 188 -#define TEGRA_GPIO_PX5 189 -#define TEGRA_GPIO_PX6 190 -#define TEGRA_GPIO_PX7 191 -#define TEGRA_GPIO_PY0 192 -#define TEGRA_GPIO_PY1 193 -#define TEGRA_GPIO_PY2 194 -#define TEGRA_GPIO_PY3 195 -#define TEGRA_GPIO_PY4 196 -#define TEGRA_GPIO_PY5 197 -#define TEGRA_GPIO_PY6 198 -#define TEGRA_GPIO_PY7 199 -#define TEGRA_GPIO_PZ0 200 -#define TEGRA_GPIO_PZ1 201 -#define TEGRA_GPIO_PZ2 202 -#define TEGRA_GPIO_PZ3 203 -#define TEGRA_GPIO_PZ4 204 -#define TEGRA_GPIO_PZ5 205 -#define TEGRA_GPIO_PZ6 206 -#define TEGRA_GPIO_PZ7 207 -#define TEGRA_GPIO_PAA0 208 -#define TEGRA_GPIO_PAA1 209 -#define TEGRA_GPIO_PAA2 210 -#define TEGRA_GPIO_PAA3 211 -#define TEGRA_GPIO_PAA4 212 -#define TEGRA_GPIO_PAA5 213 -#define TEGRA_GPIO_PAA6 214 -#define TEGRA_GPIO_PAA7 215 -#define TEGRA_GPIO_PBB0 216 -#define TEGRA_GPIO_PBB1 217 -#define TEGRA_GPIO_PBB2 218 -#define TEGRA_GPIO_PBB3 219 -#define TEGRA_GPIO_PBB4 220 -#define TEGRA_GPIO_PBB5 221 -#define TEGRA_GPIO_PBB6 222 -#define TEGRA_GPIO_PBB7 223 - -#endif diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h index 3f5fa07..cbee57f 100644 --- a/arch/arm/mach-tegra/iomap.h +++ b/arch/arm/mach-tegra/iomap.h @@ -24,44 +24,12 @@ #define TEGRA_IRAM_BASE 0x40000000 #define TEGRA_IRAM_SIZE SZ_256K -#define TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) - -#define TEGRA_HOST1X_BASE 0x50000000 -#define TEGRA_HOST1X_SIZE 0x24000 - #define TEGRA_ARM_PERIF_BASE 0x50040000 #define TEGRA_ARM_PERIF_SIZE SZ_8K -#define TEGRA_ARM_PL310_BASE 0x50043000 -#define TEGRA_ARM_PL310_SIZE SZ_4K - #define TEGRA_ARM_INT_DIST_BASE 0x50041000 #define TEGRA_ARM_INT_DIST_SIZE SZ_4K -#define TEGRA_MPE_BASE 0x54040000 -#define TEGRA_MPE_SIZE SZ_256K - -#define TEGRA_VI_BASE 0x54080000 -#define TEGRA_VI_SIZE SZ_256K - -#define TEGRA_ISP_BASE 0x54100000 -#define TEGRA_ISP_SIZE SZ_256K - -#define TEGRA_DISPLAY_BASE 0x54200000 -#define TEGRA_DISPLAY_SIZE SZ_256K - -#define TEGRA_DISPLAY2_BASE 0x54240000 -#define TEGRA_DISPLAY2_SIZE SZ_256K - -#define TEGRA_HDMI_BASE 0x54280000 -#define TEGRA_HDMI_SIZE SZ_256K - -#define TEGRA_GART_BASE 0x58000000 -#define TEGRA_GART_SIZE SZ_32M - -#define TEGRA_RES_SEMA_BASE 0x60001000 -#define TEGRA_RES_SEMA_SIZE SZ_4K - #define TEGRA_PRIMARY_ICTLR_BASE 0x60004000 #define TEGRA_PRIMARY_ICTLR_SIZE SZ_64 @@ -98,51 +66,15 @@ #define TEGRA_FLOW_CTRL_BASE 0x60007000 #define TEGRA_FLOW_CTRL_SIZE 20 -#define TEGRA_AHB_DMA_BASE 0x60008000 -#define TEGRA_AHB_DMA_SIZE SZ_4K - -#define TEGRA_AHB_DMA_CH0_BASE 0x60009000 -#define TEGRA_AHB_DMA_CH0_SIZE 32 - -#define TEGRA_APB_DMA_BASE 0x6000A000 -#define TEGRA_APB_DMA_SIZE SZ_4K - -#define TEGRA_APB_DMA_CH0_BASE 0x6000B000 -#define TEGRA_APB_DMA_CH0_SIZE 32 - -#define TEGRA_AHB_GIZMO_BASE 0x6000C004 -#define TEGRA_AHB_GIZMO_SIZE 0x10C - #define TEGRA_SB_BASE 0x6000C200 #define TEGRA_SB_SIZE 256 -#define TEGRA_STATMON_BASE 0x6000C400 -#define TEGRA_STATMON_SIZE SZ_1K - -#define TEGRA_GPIO_BASE 0x6000D000 -#define TEGRA_GPIO_SIZE SZ_4K - #define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 #define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K #define TEGRA_APB_MISC_BASE 0x70000000 #define TEGRA_APB_MISC_SIZE SZ_4K -#define TEGRA_APB_MISC_DAS_BASE 0x70000c00 -#define TEGRA_APB_MISC_DAS_SIZE SZ_128 - -#define TEGRA_AC97_BASE 0x70002000 -#define TEGRA_AC97_SIZE SZ_512 - -#define TEGRA_SPDIF_BASE 0x70002400 -#define TEGRA_SPDIF_SIZE SZ_512 - -#define TEGRA_I2S1_BASE 0x70002800 -#define TEGRA_I2S1_SIZE SZ_256 - -#define TEGRA_I2S2_BASE 0x70002A00 -#define TEGRA_I2S2_SIZE SZ_256 - #define TEGRA_UARTA_BASE 0x70006000 #define TEGRA_UARTA_SIZE SZ_64 @@ -158,87 +90,15 @@ #define TEGRA_UARTE_BASE 0x70006400 #define TEGRA_UARTE_SIZE SZ_256 -#define TEGRA_NAND_BASE 0x70008000 -#define TEGRA_NAND_SIZE SZ_256 - -#define TEGRA_HSMMC_BASE 0x70008500 -#define TEGRA_HSMMC_SIZE SZ_256 - -#define TEGRA_SNOR_BASE 0x70009000 -#define TEGRA_SNOR_SIZE SZ_4K - -#define TEGRA_PWFM_BASE 0x7000A000 -#define TEGRA_PWFM_SIZE SZ_256 - -#define TEGRA_PWFM0_BASE 0x7000A000 -#define TEGRA_PWFM0_SIZE 4 - -#define TEGRA_PWFM1_BASE 0x7000A010 -#define TEGRA_PWFM1_SIZE 4 - -#define TEGRA_PWFM2_BASE 0x7000A020 -#define TEGRA_PWFM2_SIZE 4 - -#define TEGRA_PWFM3_BASE 0x7000A030 -#define TEGRA_PWFM3_SIZE 4 - -#define TEGRA_MIPI_BASE 0x7000B000 -#define TEGRA_MIPI_SIZE SZ_256 - -#define TEGRA_I2C_BASE 0x7000C000 -#define TEGRA_I2C_SIZE SZ_256 - -#define TEGRA_TWC_BASE 0x7000C100 -#define TEGRA_TWC_SIZE SZ_256 - -#define TEGRA_SPI_BASE 0x7000C380 -#define TEGRA_SPI_SIZE 48 - -#define TEGRA_I2C2_BASE 0x7000C400 -#define TEGRA_I2C2_SIZE SZ_256 - -#define TEGRA_I2C3_BASE 0x7000C500 -#define TEGRA_I2C3_SIZE SZ_256 - -#define TEGRA_OWR_BASE 0x7000C600 -#define TEGRA_OWR_SIZE 80 - -#define TEGRA_DVC_BASE 0x7000D000 -#define TEGRA_DVC_SIZE SZ_512 - -#define TEGRA_SPI1_BASE 0x7000D400 -#define TEGRA_SPI1_SIZE SZ_512 - -#define TEGRA_SPI2_BASE 0x7000D600 -#define TEGRA_SPI2_SIZE SZ_512 - -#define TEGRA_SPI3_BASE 0x7000D800 -#define TEGRA_SPI3_SIZE SZ_512 - -#define TEGRA_SPI4_BASE 0x7000DA00 -#define TEGRA_SPI4_SIZE SZ_512 - -#define TEGRA_RTC_BASE 0x7000E000 -#define TEGRA_RTC_SIZE SZ_256 - -#define TEGRA_KBC_BASE 0x7000E200 -#define TEGRA_KBC_SIZE SZ_256 - #define TEGRA_PMC_BASE 0x7000E400 #define TEGRA_PMC_SIZE SZ_256 -#define TEGRA_MC_BASE 0x7000F000 -#define TEGRA_MC_SIZE SZ_1K - #define TEGRA_EMC_BASE 0x7000F400 #define TEGRA_EMC_SIZE SZ_1K #define TEGRA_FUSE_BASE 0x7000F800 #define TEGRA_FUSE_SIZE SZ_1K -#define TEGRA_KFUSE_BASE 0x7000FC00 -#define TEGRA_KFUSE_SIZE SZ_1K - #define TEGRA_EMC0_BASE 0x7001A000 #define TEGRA_EMC0_SIZE SZ_2K @@ -248,18 +108,6 @@ #define TEGRA_CSITE_BASE 0x70040000 #define TEGRA_CSITE_SIZE SZ_256K -#define TEGRA_SDMMC1_BASE 0xC8000000 -#define TEGRA_SDMMC1_SIZE SZ_512 - -#define TEGRA_SDMMC2_BASE 0xC8000200 -#define TEGRA_SDMMC2_SIZE SZ_512 - -#define TEGRA_SDMMC3_BASE 0xC8000400 -#define TEGRA_SDMMC3_SIZE SZ_512 - -#define TEGRA_SDMMC4_BASE 0xC8000600 -#define TEGRA_SDMMC4_SIZE SZ_512 - /* On TEGRA, many peripherals are very closely packed in * two 256MB io windows (that actually only use about 64KB * at the start of each). diff --git a/arch/arm/mach-tegra/irammap.h b/arch/arm/mach-tegra/irammap.h index 501952a..e32e174 100644 --- a/arch/arm/mach-tegra/irammap.h +++ b/arch/arm/mach-tegra/irammap.h @@ -23,4 +23,10 @@ #define TEGRA_IRAM_RESET_HANDLER_OFFSET 0 #define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K +/* + * This area is used for LPx resume vector, only while LPx power state is + * active. At other times, the AVP may use this area for arbitrary purposes + */ +#define TEGRA_IRAM_LPx_RESUME_AREA (TEGRA_IRAM_BASE + SZ_4K) + #endif diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index ed294a0..36ed88a 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -263,10 +263,10 @@ static void tegra_suspend_enter_lp1(void) tegra_pmc_suspend(); /* copy the reset vector & SDRAM shutdown code into IRAM */ - memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA), - iram_save_size); - memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr, + memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_size); + memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), + tegra_lp1_iram.start_addr, iram_save_size); *((u32 *)tegra_cpu_lp1_mask) = 1; } @@ -276,7 +276,7 @@ static void tegra_suspend_exit_lp1(void) tegra_pmc_resume(); /* restore IRAM */ - memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr, + memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr, iram_save_size); *(u32 *)tegra_cpu_lp1_mask = 0; diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index fe204e5..6e92a7c 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -37,9 +37,6 @@ void tegra30_sleep_core_init(void); extern unsigned long l2x0_saved_regs_addr; -void save_cpu_arch_register(void); -void restore_cpu_arch_register(void); - void tegra_clear_cpu_in_lp2(void); bool tegra_set_cpu_in_lp2(void); diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index 8acb881..93a4dbc 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -166,6 +166,15 @@ int tegra_pmc_cpu_remove_clamping(int cpuid) return tegra_pmc_powergate_remove_clamping(id); } +void tegra_pmc_restart(enum reboot_mode mode, const char *cmd) +{ + u32 val; + + val = tegra_pmc_readl(0); + val |= 0x10; + tegra_pmc_writel(val, 0); +} + #ifdef CONFIG_PM_SLEEP static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate) { @@ -285,13 +294,10 @@ static const struct of_device_id matches[] __initconst = { { } }; -static void __init tegra_pmc_parse_dt(void) +void __init tegra_pmc_init_irq(void) { struct device_node *np; - u32 prop; - enum tegra_suspend_mode suspend_mode; - u32 core_good_time[2] = {0, 0}; - u32 lp0_vec[2] = {0, 0}; + u32 val; np = of_find_matching_node(NULL, matches); BUG_ON(!np); @@ -300,6 +306,26 @@ static void __init tegra_pmc_parse_dt(void) tegra_pmc_invert_interrupt = of_property_read_bool(np, "nvidia,invert-interrupt"); + + val = tegra_pmc_readl(PMC_CTRL); + if (tegra_pmc_invert_interrupt) + val |= PMC_CTRL_INTR_LOW; + else + val &= ~PMC_CTRL_INTR_LOW; + tegra_pmc_writel(val, PMC_CTRL); +} + +void __init tegra_pmc_init(void) +{ + struct device_node *np; + u32 prop; + enum tegra_suspend_mode suspend_mode; + u32 core_good_time[2] = {0, 0}; + u32 lp0_vec[2] = {0, 0}; + + np = of_find_matching_node(NULL, matches); + BUG_ON(!np); + tegra_pclk = of_clk_get_by_name(np, "pclk"); WARN_ON(IS_ERR(tegra_pclk)); @@ -365,17 +391,3 @@ static void __init tegra_pmc_parse_dt(void) pmc_pm_data.suspend_mode = suspend_mode; } - -void __init tegra_pmc_init(void) -{ - u32 val; - - tegra_pmc_parse_dt(); - - val = tegra_pmc_readl(PMC_CTRL); - if (tegra_pmc_invert_interrupt) - val |= PMC_CTRL_INTR_LOW; - else - val &= ~PMC_CTRL_INTR_LOW; - tegra_pmc_writel(val, PMC_CTRL); -} diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h index 549f8c7..59e19c34 100644 --- a/arch/arm/mach-tegra/pmc.h +++ b/arch/arm/mach-tegra/pmc.h @@ -18,6 +18,8 @@ #ifndef __MACH_TEGRA_PMC_H #define __MACH_TEGRA_PMC_H +#include <linux/reboot.h> + enum tegra_suspend_mode { TEGRA_SUSPEND_NONE = 0, TEGRA_SUSPEND_LP2, /* CPU voltage off */ @@ -39,6 +41,9 @@ bool tegra_pmc_cpu_is_powered(int cpuid); int tegra_pmc_cpu_power_on(int cpuid); int tegra_pmc_cpu_remove_clamping(int cpuid); +void tegra_pmc_restart(enum reboot_mode mode, const char *cmd); + +void tegra_pmc_init_irq(void); void tegra_pmc_init(void); #endif diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index fd0bbf8..568f5bb 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -82,7 +82,7 @@ void __init tegra_cpu_reset_handler_init(void) #ifdef CONFIG_PM_SLEEP __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = - TEGRA_IRAM_CODE_AREA; + TEGRA_IRAM_LPx_RESUME_AREA; __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = virt_to_phys((void *)tegra_resume); #endif diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index 5c3bd11..aaaf3ab 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -25,6 +25,7 @@ #include <asm/cp15.h> #include <asm/cache.h> +#include "irammap.h" #include "sleep.h" #include "flowctrl.h" @@ -235,7 +236,7 @@ ENTRY(tegra20_sleep_core_finish) mov32 r0, tegra20_tear_down_core mov32 r1, tegra20_iram_start sub r0, r0, r1 - mov32 r1, TEGRA_IRAM_CODE_AREA + mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA add r0, r0, r1 mov pc, r3 @@ -328,7 +329,7 @@ tegra20_iram_start: * The physical address of tegra_resume expected to be stored in * PMC_SCRATCH41. * - * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA. + * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA. */ ENTRY(tegra20_lp1_reset) /* diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 63fa91b..c6fc15c 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -20,6 +20,7 @@ #include <asm/asm-offsets.h> #include <asm/cache.h> +#include "irammap.h" #include "fuse.h" #include "sleep.h" #include "flowctrl.h" @@ -262,7 +263,7 @@ ENTRY(tegra30_sleep_core_finish) mov32 r0, tegra30_tear_down_core mov32 r1, tegra30_iram_start sub r0, r0, r1 - mov32 r1, TEGRA_IRAM_CODE_AREA + mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA add r0, r0, r1 mov pc, r3 @@ -314,7 +315,7 @@ tegra30_iram_start: * The physical address of tegra_resume expected to be stored in * PMC_SCRATCH41. * - * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA. + * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA. */ ENTRY(tegra30_lp1_reset) /* diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 5b86055..386115a 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -16,7 +16,6 @@ * */ -#include <linux/clocksource.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> @@ -34,16 +33,78 @@ #include <linux/sys_soc.h> #include <linux/usb/tegra_usb_phy.h> #include <linux/clk/tegra.h> +#include <linux/irqchip.h> +#include <asm/hardware/cache-l2x0.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/setup.h> +#include "apbio.h" #include "board.h" #include "common.h" +#include "cpuidle.h" #include "fuse.h" #include "iomap.h" +#include "irq.h" +#include "pmc.h" +#include "pm.h" +#include "reset.h" +#include "sleep.h" + +/* + * Storage for debug-macro.S's state. + * + * This must be in .data not .bss so that it gets initialized each time the + * kernel is loaded. The data is declared here rather than debug-macro.S so + * that multiple inclusions of debug-macro.S point at the same data. + */ +u32 tegra_uart_config[4] = { + /* Debug UART initialization required */ + 1, + /* Debug UART physical address */ + 0, + /* Debug UART virtual address */ + 0, + /* Scratch space for debug macro */ + 0, +}; + +static void __init tegra_init_cache(void) +{ +#ifdef CONFIG_CACHE_L2X0 + int ret; + void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; + u32 aux_ctrl, cache_type; + + cache_type = readl(p + L2X0_CACHE_TYPE); + aux_ctrl = (cache_type & 0x700) << (17-8); + aux_ctrl |= 0x7C400001; + + ret = l2x0_of_init(aux_ctrl, 0x8200c3fe); + if (!ret) + l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs); +#endif +} + +static void __init tegra_init_early(void) +{ + tegra_cpu_reset_handler_init(); + tegra_apb_io_init(); + tegra_init_fuse(); + tegra_init_cache(); + tegra_powergate_init(); + tegra_hotplug_init(); +} + +static void __init tegra_dt_init_irq(void) +{ + tegra_pmc_init_irq(); + tegra_init_irq(); + irqchip_init(); + tegra_legacy_irq_syscore_init(); +} static void __init tegra_dt_init(void) { @@ -51,6 +112,8 @@ static void __init tegra_dt_init(void) struct soc_device *soc_dev; struct device *parent = NULL; + tegra_pmc_init(); + tegra_clocks_apply_init_table(); soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); @@ -97,7 +160,9 @@ static void __init tegra_dt_init_late(void) { int i; - tegra_init_late(); + tegra_init_suspend(); + tegra_cpuidle_init(); + tegra_powergate_debugfs_init(); for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) { if (of_machine_is_compatible(board_init_funcs[i].machine)) { @@ -119,9 +184,8 @@ DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)") .smp = smp_ops(tegra_smp_ops), .init_early = tegra_init_early, .init_irq = tegra_dt_init_irq, - .init_time = clocksource_of_init, .init_machine = tegra_dt_init, .init_late = tegra_dt_init_late, - .restart = tegra_assert_system_reset, + .restart = tegra_pmc_restart, .dt_compat = tegra_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig index a165986..8e23071 100644 --- a/arch/arm/mach-u300/Kconfig +++ b/arch/arm/mach-u300/Kconfig @@ -5,7 +5,6 @@ config ARCH_U300 select ARM_AMBA select ARM_PATCH_PHYS_VIRT select ARM_VIC - select CLKDEV_LOOKUP select CLKSRC_MMIO select CLKSRC_OF select COMMON_CLK diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 99a28d6..c67f8ad 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -1,37 +1,32 @@ config ARCH_U8500 bool "ST-Ericsson U8500 Series" if ARCH_MULTI_V7 depends on MMU + select AB8500_CORE + select ABX500_CORE select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select ARM_AMBA - select CLKDEV_LOOKUP + select ARM_ERRATA_754322 + select ARM_ERRATA_764369 if SMP + select ARM_GIC + select CACHE_L2X0 + select CLKSRC_NOMADIK_MTU + select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 + select PINCTRL + select PINCTRL_ABX500 + select PINCTRL_NOMADIK + select PL310_ERRATA_753970 if CACHE_PL310 help Support for ST-Ericsson's Ux500 architecture if ARCH_U8500 -config UX500_SOC_COMMON - bool - default y - select ABX500_CORE - select AB8500_CORE - select ARM_ERRATA_754322 - select ARM_ERRATA_764369 if SMP - select ARM_GIC - select CACHE_L2X0 - select CLKSRC_NOMADIK_MTU - select COMMON_CLK - select PINCTRL - select PINCTRL_NOMADIK - select PINCTRL_ABX500 - select PL310_ERRATA_753970 if CACHE_PL310 - config UX500_SOC_DB8500 bool select CPU_FREQ_TABLE if CPU_FREQ diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 3657954..d7e7422 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -4,14 +4,12 @@ config ARCH_VEXPRESS select ARM_AMBA select ARM_GIC select ARM_TIMER_SP804 - select CLKDEV_LOOKUP select COMMON_CLK select COMMON_CLK_VERSATILE select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP - select HAVE_CLK select HAVE_PATA_PLATFORM select HAVE_SMP select ICST diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 95a469e..4f8b8cb 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -1,12 +1,10 @@ /* * Versatile Express V2M Motherboard Support */ -#include <linux/clocksource.h> #include <linux/device.h> #include <linux/amba/bus.h> #include <linux/amba/mmci.h> #include <linux/io.h> -#include <linux/clocksource.h> #include <linux/smp.h> #include <linux/init.h> #include <linux/of_address.h> @@ -22,7 +20,6 @@ #include <linux/regulator/fixed.h> #include <linux/regulator/machine.h> #include <linux/vexpress.h> -#include <linux/clk-provider.h> #include <linux/clkdev.h> #include <asm/mach-types.h> @@ -422,16 +419,8 @@ void __init v2m_dt_init_early(void) pr_warning("vexpress: DT HBI (%x) is not matching " "hardware (%x)!\n", dt_hbi, hbi); } -} - -static void __init v2m_dt_timer_init(void) -{ - of_clk_init(NULL); - clocksource_of_init(); - - versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), - 24000000); + versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), 24000000); } static const struct of_device_id v2m_dt_bus_match[] __initconst = { @@ -458,6 +447,5 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express") .smp_init = smp_init_ops(vexpress_smp_init_ops), .map_io = v2m_dt_map_io, .init_early = v2m_dt_init_early, - .init_time = v2m_dt_timer_init, .init_machine = v2m_dt_init, MACHINE_END diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig index 9b25293..927be93 100644 --- a/arch/arm/mach-vt8500/Kconfig +++ b/arch/arm/mach-vt8500/Kconfig @@ -5,7 +5,6 @@ config ARCH_VT8500 select CLKDEV_LOOKUP select CLKSRC_OF select GENERIC_CLOCKEVENTS - select HAVE_CLK select VT8500_TIMER select PINCTRL help diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h deleted file mode 100644 index 087787a..0000000 --- a/arch/arm/mach-vt8500/common.h +++ /dev/null @@ -1,24 +0,0 @@ -/* linux/arch/arm/mach-vt8500/dt_common.h - * - * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ARCH_ARM_MACH_VT8500_DT_COMMON_H -#define __ARCH_ARM_MACH_VT8500_DT_COMMON_H - -#include <linux/of.h> - -/* defined in drivers/clk/clk-vt8500.c */ -void __init vtwm_clk_init(void __iomem *pmc_base); - -#endif diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c index eefaa60..4a73464 100644 --- a/arch/arm/mach-vt8500/vt8500.c +++ b/arch/arm/mach-vt8500/vt8500.c @@ -18,7 +18,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include <linux/clocksource.h> #include <linux/io.h> #include <linux/pm.h> #include <linux/reboot.h> @@ -33,8 +32,6 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> -#include "common.h" - #define LEGACY_GPIO_BASE 0xD8110000 #define LEGACY_PMC_BASE 0xD8130000 @@ -162,8 +159,6 @@ void __init vt8500_init(void) else pr_err("%s: PMC Hibernation register could not be remapped, not enabling power off!\n", __func__); - vtwm_clk_init(pmc_base); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } @@ -180,7 +175,6 @@ DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)") .dt_compat = vt8500_dt_compat, .map_io = vt8500_map_io, .init_machine = vt8500_init, - .init_time = clocksource_of_init, .restart = vt8500_restart, MACHINE_END |
