diff options
Diffstat (limited to 'arch')
505 files changed, 19350 insertions, 5048 deletions
diff --git a/arch/alpha/mm/fault.c b/arch/alpha/mm/fault.c index 4829f96..00a31de 100644 --- a/arch/alpha/mm/fault.c +++ b/arch/alpha/mm/fault.c @@ -146,7 +146,7 @@ do_page_fault(unsigned long address, unsigned long mmcsr, /* If for any reason at all we couldn't handle the fault, make sure we exit gracefully rather than endlessly redo the fault. */ - fault = handle_mm_fault(mm, vma, address, cause > 0); + fault = handle_mm_fault(mm, vma, address, cause > 0 ? FAULT_FLAG_WRITE : 0); up_read(&mm->mmap_sem); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2947510..aef63c8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1241,7 +1241,7 @@ endmenu menu "CPU Power Management" -if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA) +if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA || ARCH_S3C64XX) source "drivers/cpufreq/Kconfig" @@ -1272,6 +1272,10 @@ config CPU_FREQ_PXA default y select CPU_FREQ_DEFAULT_GOV_USERSPACE +config CPU_FREQ_S3C64XX + bool "CPUfreq support for Samsung S3C64XX CPUs" + depends on CPU_FREQ && CPU_S3C6410 + endif source "drivers/cpuidle/Kconfig" diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 01d49be..4515728 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -674,6 +674,15 @@ proc_types: b __armv4_mmu_cache_off b __armv5tej_mmu_cache_flush +#ifdef CONFIG_CPU_FEROCEON_OLD_ID + /* this conflicts with the standard ARMv5TE entry */ + .long 0x41009260 @ Old Feroceon + .long 0xff00fff0 + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv5tej_mmu_cache_flush +#endif + .word 0x66015261 @ FA526 .word 0xff01fff1 b __fa526_cache_on diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 664c7b8..337741f 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -117,7 +117,7 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) u32 val; spin_lock(&irq_controller_lock); - irq_desc[irq].cpu = cpu; + irq_desc[irq].node = cpu; val = readl(reg) & ~(0xff << shift); val |= 1 << (cpu + shift); writel(val, reg); diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index 887c6eb..6ed8983 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -229,14 +229,18 @@ static int vic_set_wake(unsigned int irq, unsigned int on) { struct vic_device *v = vic_from_irq(irq); unsigned int off = irq & 31; + u32 bit = 1 << off; if (!v) return -EINVAL; + if (!(bit & v->resume_sources)) + return -EINVAL; + if (on) - v->resume_irqs |= 1 << off; + v->resume_irqs |= bit; else - v->resume_irqs &= ~(1 << off); + v->resume_irqs &= ~bit; return 0; } diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig new file mode 100644 index 0000000..e49ed40 --- /dev/null +++ b/arch/arm/configs/mini2440_defconfig @@ -0,0 +1,2097 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.30-rc6 +# Wed May 20 12:29:51 2009 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +CONFIG_NO_IOPORT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_STRIP_ASM_SYMS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_BLK_DEV_INTEGRITY=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_FREEZER=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +CONFIG_ARCH_S3C2410=y +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_W90X900 is not set +CONFIG_PLAT_S3C24XX=y +CONFIG_S3C2410_CLOCK=y +CONFIG_CPU_S3C244X=y +CONFIG_S3C24XX_PWM=y +CONFIG_S3C24XX_GPIO_EXTRA=0 +CONFIG_S3C2410_DMA=y +# CONFIG_S3C2410_DMA_DEBUG is not set +CONFIG_S3C24XX_ADC=y +CONFIG_PLAT_S3C=y +CONFIG_CPU_LLSERIAL_S3C2440_ONLY=y +CONFIG_CPU_LLSERIAL_S3C2440=y + +# +# Boot options +# +# CONFIG_S3C_BOOT_WATCHDOG is not set +# CONFIG_S3C_BOOT_ERROR_RESET is not set +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y + +# +# Power management +# +# CONFIG_S3C2410_PM_DEBUG is not set +# CONFIG_S3C2410_PM_CHECK is not set +CONFIG_S3C_LOWLEVEL_UART_PORT=0 +CONFIG_S3C_GPIO_SPACE=0 + +# +# S3C2400 Machines +# +CONFIG_S3C2410_PM=y +CONFIG_S3C2410_GPIO=y + +# +# S3C2410 Machines +# +# CONFIG_ARCH_SMDK2410 is not set +# CONFIG_ARCH_H1940 is not set +# CONFIG_MACH_N30 is not set +# CONFIG_ARCH_BAST is not set +# CONFIG_MACH_OTOM is not set +# CONFIG_MACH_AML_M5900 is not set +# CONFIG_MACH_TCT_HAMMER is not set +# CONFIG_MACH_VR1000 is not set +# CONFIG_MACH_QT2410 is not set + +# +# S3C2412 Machines +# +# CONFIG_MACH_JIVE is not set +# CONFIG_MACH_SMDK2413 is not set +# CONFIG_MACH_SMDK2412 is not set +# CONFIG_MACH_VSTMS is not set +CONFIG_CPU_S3C2440=y +CONFIG_S3C2440_DMA=y + +# +# S3C2440 Machines +# +# CONFIG_MACH_ANUBIS is not set +# CONFIG_MACH_OSIRIS is not set +# CONFIG_MACH_RX3715 is not set +# CONFIG_ARCH_S3C2440 is not set +# CONFIG_MACH_NEXCODER_2440 is not set +# CONFIG_MACH_AT2440EVB is not set +CONFIG_MACH_MINI2440=y + +# +# S3C2442 Machines +# + +# +# S3C2443 Machines +# +# CONFIG_MACH_SMDK2443 is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM920T=y +CONFIG_CPU_32v4T=y +CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_V4WT=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=200 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Power Management +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=m +CONFIG_CFG80211_REG_DEBUG=y +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m + +# +# Rate control algorithm selection +# +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=m +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_FTL=y +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +CONFIG_INFTL=y +CONFIG_RFD_FTL=y +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=y +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_S3C2410=y +# CONFIG_MTD_NAND_S3C2410_DEBUG is not set +# CONFIG_MTD_NAND_S3C2410_HWECC is not set +# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +CONFIG_MTD_LPDDR=y +CONFIG_MTD_QINFO_PROBE=y + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +CONFIG_DM9000=y +CONFIG_DM9000_DEBUGLEVEL=4 +# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +CONFIG_LIBERTAS=m +# CONFIG_LIBERTAS_USB is not set +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_SPI is not set +# CONFIG_LIBERTAS_DEBUG is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8187 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_P54_COMMON is not set +# CONFIG_AR9170_USB is not set +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +CONFIG_ZD1211RW=m +CONFIG_ZD1211RW_DEBUG=y +# CONFIG_RT2X00 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_UARTS=3 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_S3C2440=y +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=128 +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_S3C2410=y +CONFIG_I2C_SIMTEC=y + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_MAX6875 is not set +CONFIG_SENSORS_TSL2550=m +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_S3C24XX=y +# CONFIG_SPI_S3C24XX_GPIO is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IBMAEM is not set +# CONFIG_SENSORS_IBMPEX is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +CONFIG_SENSORS_LM75=y +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_THERMAL=m +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_S3C2410_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +CONFIG_DVB_CORE=m +CONFIG_VIDEO_MEDIA=m + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=m +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L1=m +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_VIDEO_AU0828 is not set +CONFIG_SOC_CAMERA=m +# CONFIG_SOC_CAMERA_MT9M001 is not set +# CONFIG_SOC_CAMERA_MT9M111 is not set +# CONFIG_SOC_CAMERA_MT9T031 is not set +# CONFIG_SOC_CAMERA_MT9V022 is not set +# CONFIG_SOC_CAMERA_TW9910 is not set +CONFIG_SOC_CAMERA_PLATFORM=m +# CONFIG_SOC_CAMERA_OV772X is not set +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +CONFIG_V4L_USB_DRIVERS=y +# CONFIG_USB_VIDEO_CLASS is not set +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +CONFIG_USB_GSPCA_ZC3XX=m +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_USB_VICAM is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_QUICKCAM_MESSENGER is not set +# CONFIG_USB_ET61X251 is not set +# CONFIG_VIDEO_OVCAMCHIP is not set +# CONFIG_USB_OV511 is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_STV680 is not set +# CONFIG_USB_ZC0301 is not set +# CONFIG_USB_PWC is not set +# CONFIG_USB_PWC_INPUT_EVDEV is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_USB_DSBR is not set +# CONFIG_USB_SI470X is not set +# CONFIG_USB_MR800 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_DVB_DYNAMIC_MINORS is not set +CONFIG_DVB_CAPTURE_DRIVERS=y +# CONFIG_TTPCI_EEPROM is not set + +# +# Supported USB Adapters +# +# CONFIG_DVB_USB is not set +# CONFIG_DVB_SIANO_SMS1XXX is not set + +# +# Supported FlexCopII (B2C2) Adapters +# +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_S3C2410=y +# CONFIG_FB_S3C2410_DEBUG is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +CONFIG_FONT_MINI_4x6=y +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_JACK=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_SOC=y +CONFIG_SND_S3C24XX_SOC=y +CONFIG_SND_S3C24XX_SOC_I2S=y +# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set +CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_L3=y +CONFIG_SND_SOC_UDA134X=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +CONFIG_HIDRAW=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +# CONFIG_DRAGONRISE_FF is not set +CONFIG_HID_EZKEY=y +CONFIG_HID_KYE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_GREENASIA_FF is not set +CONFIG_HID_TOPSEED=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=m +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=m +# CONFIG_USB_STORAGE_FREECOM is not set +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +# CONFIG_USB_EZUSB is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +CONFIG_USB_SERIAL_CP210X=m +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +CONFIG_USB_SERIAL_FTDI_SIO=m +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +CONFIG_USB_SERIAL_SPCP8X5=m +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +CONFIG_USB_GADGET_S3C2410=y +CONFIG_USB_S3C2410=y +# CONFIG_USB_S3C2410_DEBUG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +# CONFIG_USB_GADGET_DUALSPEED is not set +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_CDC_COMPOSITE=m + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_SDIO_UART=y +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SPI=y +CONFIG_MMC_S3C=y +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_S3C24XX=y +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_BD2802 is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_S3C=y +CONFIG_DMADEVICES=y + +# +# DMA Devices +# +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_ROMFS_BACKED_BY_BLOCK is not set +# CONFIG_ROMFS_BACKED_BY_MTD is not set +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_ROMFS_ON_MTD=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +CONFIG_DEBUG_S3C_UART=0 + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_FILE_CAPABILITIES=y +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_FIPS=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_ZLIB=m +CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index 94cc58e..0e97b8c 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -389,6 +389,8 @@ #define __NR_inotify_init1 (__NR_SYSCALL_BASE+360) #define __NR_preadv (__NR_SYSCALL_BASE+361) #define __NR_pwritev (__NR_SYSCALL_BASE+362) +#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363) +#define __NR_perf_counter_open (__NR_SYSCALL_BASE+364) /* * The following SWIs are ARM private. diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index 1680e9e..f776e72 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -372,6 +372,8 @@ /* 360 */ CALL(sys_inotify_init1) CALL(sys_preadv) CALL(sys_pwritev) + CALL(sys_rt_tgsigqueueinfo) + CALL(sys_perf_counter_open) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 6874c7d..096f600 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -167,7 +167,7 @@ void __init init_IRQ(void) #ifdef CONFIG_SMP cpumask_setall(bad_irq_desc.affinity); - bad_irq_desc.cpu = smp_processor_id(); + bad_irq_desc.node = smp_processor_id(); #endif init_arch_irq(); } @@ -176,7 +176,7 @@ void __init init_IRQ(void) static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) { - pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu); + pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->node, cpu); spin_lock_irq(&desc->lock); desc->chip->set_affinity(irq, cpumask_of(cpu)); @@ -195,7 +195,7 @@ void migrate_irqs(void) for (i = 0; i < NR_IRQS; i++) { struct irq_desc *desc = irq_desc + i; - if (desc->cpu == cpu) { + if (desc->node == cpu) { unsigned int newcpu = cpumask_any_and(desc->affinity, cpu_online_mask); if (newcpu >= nr_cpu_ids) { diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 1585423..39196df 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -114,9 +114,6 @@ void arm_machine_restart(char mode, const char *cmd) /* * Function pointers to optional machine specific functions */ -void (*pm_idle)(void); -EXPORT_SYMBOL(pm_idle); - void (*pm_power_off)(void); EXPORT_SYMBOL(pm_power_off); @@ -130,20 +127,19 @@ EXPORT_SYMBOL_GPL(arm_pm_restart); */ static void default_idle(void) { - if (hlt_counter) - cpu_relax(); - else { - local_irq_disable(); - if (!need_resched()) - arch_idle(); - local_irq_enable(); - } + if (!need_resched()) + arch_idle(); + local_irq_enable(); } +void (*pm_idle)(void) = default_idle; +EXPORT_SYMBOL(pm_idle); + /* - * The idle thread. We try to conserve power, while trying to keep - * overall latency low. The architecture specific idle is passed - * a value to indicate the level of "idleness" of the system. + * The idle thread, has rather strange semantics for calling pm_idle, + * but this is what x86 does and we need to do the same, so that + * things like cpuidle get called in the same way. The only difference + * is that we always respect 'hlt_counter' to prevent low power idle. */ void cpu_idle(void) { @@ -151,21 +147,31 @@ void cpu_idle(void) /* endless idle loop with no priority at all */ while (1) { - void (*idle)(void) = pm_idle; - + tick_nohz_stop_sched_tick(1); + leds_event(led_idle_start); + while (!need_resched()) { #ifdef CONFIG_HOTPLUG_CPU - if (cpu_is_offline(smp_processor_id())) { - leds_event(led_idle_start); - cpu_die(); - } + if (cpu_is_offline(smp_processor_id())) + cpu_die(); #endif - if (!idle) - idle = default_idle; - leds_event(led_idle_start); - tick_nohz_stop_sched_tick(1); - while (!need_resched()) - idle(); + local_irq_disable(); + if (hlt_counter) { + local_irq_enable(); + cpu_relax(); + } else { + stop_critical_timings(); + pm_idle(); + start_critical_timings(); + /* + * This will eventually be removed - pm_idle + * functions should always return with IRQs + * enabled. + */ + WARN_ON(irqs_disabled()); + local_irq_enable(); + } + } leds_event(led_idle_end); tick_nohz_restart_sched_tick(); preempt_enable_no_resched(); @@ -352,6 +358,23 @@ asm( ".section .text\n" " .size kernel_thread_helper, . - kernel_thread_helper\n" " .previous"); +#ifdef CONFIG_ARM_UNWIND +extern void kernel_thread_exit(long code); +asm( ".section .text\n" +" .align\n" +" .type kernel_thread_exit, #function\n" +"kernel_thread_exit:\n" +" .fnstart\n" +" .cantunwind\n" +" bl do_exit\n" +" nop\n" +" .fnend\n" +" .size kernel_thread_exit, . - kernel_thread_exit\n" +" .previous"); +#else +#define kernel_thread_exit do_exit +#endif + /* * Create a kernel thread. */ @@ -363,7 +386,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) regs.ARM_r1 = (unsigned long)arg; regs.ARM_r2 = (unsigned long)fn; - regs.ARM_r3 = (unsigned long)do_exit; + regs.ARM_r3 = (unsigned long)kernel_thread_exit; regs.ARM_pc = (unsigned long)kernel_thread_helper; regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE; diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c index 1dedc2c..dd56e11 100644 --- a/arch/arm/kernel/unwind.c +++ b/arch/arm/kernel/unwind.c @@ -212,7 +212,8 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) ctrl->vrs[14] = *vsp++; ctrl->vrs[SP] = (unsigned long)vsp; } else if (insn == 0xb0) { - ctrl->vrs[PC] = ctrl->vrs[LR]; + if (ctrl->vrs[PC] == 0) + ctrl->vrs[PC] = ctrl->vrs[LR]; /* no further processing */ ctrl->entries = 0; } else if (insn == 0xb1) { @@ -309,18 +310,20 @@ int unwind_frame(struct stackframe *frame) } while (ctrl.entries > 0) { - int urc; - - if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high) - return -URC_FAILURE; - urc = unwind_exec_insn(&ctrl); + int urc = unwind_exec_insn(&ctrl); if (urc < 0) return urc; + if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high) + return -URC_FAILURE; } if (ctrl.vrs[PC] == 0) ctrl.vrs[PC] = ctrl.vrs[LR]; + /* check for infinite loop */ + if (frame->pc == ctrl.vrs[PC]) + return -URC_FAILURE; + frame->fp = ctrl.vrs[FP]; frame->sp = ctrl.vrs[SP]; frame->lr = ctrl.vrs[LR]; @@ -332,7 +335,6 @@ int unwind_frame(struct stackframe *frame) void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk) { struct stackframe frame; - unsigned long high, low; register unsigned long current_sp asm ("sp"); pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); @@ -362,9 +364,6 @@ void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk) frame.pc = thread_saved_pc(tsk); } - low = frame.sp & ~(THREAD_SIZE - 1); - high = low + THREAD_SIZE; - while (1) { int urc; unsigned long where = frame.pc; diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 6c07797..4340bf3 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -84,6 +84,14 @@ SECTIONS *(.exitcall.exit) *(.ARM.exidx.exit.text) *(.ARM.extab.exit.text) +#ifndef CONFIG_HOTPLUG_CPU + *(.ARM.exidx.cpuexit.text) + *(.ARM.extab.cpuexit.text) +#endif +#ifndef CONFIG_HOTPLUG + *(.ARM.exidx.devexit.text) + *(.ARM.extab.devexit.text) +#endif #ifndef CONFIG_MMU *(.fixup) *(__ex_table) diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h index aa48284..b520c4b 100644 --- a/arch/arm/mach-davinci/include/mach/nand.h +++ b/arch/arm/mach-davinci/include/mach/nand.h @@ -68,10 +68,14 @@ struct davinci_nand_pdata { /* platform_data */ /* none == NAND_ECC_NONE (strongly *not* advised!!) * soft == NAND_ECC_SOFT - * 1-bit == NAND_ECC_HW - * 4-bit == NAND_ECC_HW_SYNDROME (not on all chips) + * else == NAND_ECC_HW, according to ecc_bits + * + * All DaVinci-family chips support 1-bit hardware ECC. + * Newer ones also support 4-bit ECC, but are awkward + * using it with large page chips. */ nand_ecc_modes_t ecc_mode; + u8 ecc_bits; /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ unsigned options; diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h b/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h new file mode 100644 index 0000000..83f31cd --- /dev/null +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h @@ -0,0 +1,42 @@ +/* + * arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h + */ + +#ifndef __ASM_ARCH_EP93XX_KEYPAD_H +#define __ASM_ARCH_EP93XX_KEYPAD_H + +#define MAX_MATRIX_KEY_ROWS (8) +#define MAX_MATRIX_KEY_COLS (8) + +/* flags for the ep93xx_keypad driver */ +#define EP93XX_KEYPAD_DISABLE_3_KEY (1<<0) /* disable 3-key reset */ +#define EP93XX_KEYPAD_DIAG_MODE (1<<1) /* diagnostic mode */ +#define EP93XX_KEYPAD_BACK_DRIVE (1<<2) /* back driving mode */ +#define EP93XX_KEYPAD_TEST_MODE (1<<3) /* scan only column 0 */ +#define EP93XX_KEYPAD_KDIV (1<<4) /* 1/4 clock or 1/16 clock */ +#define EP93XX_KEYPAD_AUTOREPEAT (1<<5) /* enable key autorepeat */ + +/** + * struct ep93xx_keypad_platform_data - platform specific device structure + * @matrix_key_rows: number of rows in the keypad matrix + * @matrix_key_cols: number of columns in the keypad matrix + * @matrix_key_map: array of keycodes defining the keypad matrix + * @matrix_key_map_size: ARRAY_SIZE(matrix_key_map) + * @debounce: debounce start count; terminal count is 0xff + * @prescale: row/column counter pre-scaler load value + * @flags: see above + */ +struct ep93xx_keypad_platform_data { + unsigned int matrix_key_rows; + unsigned int matrix_key_cols; + unsigned int *matrix_key_map; + int matrix_key_map_size; + unsigned int debounce; + unsigned int prescale; + unsigned int flags; +}; + +/* macro for creating the matrix_key_map table */ +#define KEY(row, col, val) (((row) << 28) | ((col) << 24) | (val)) + +#endif /* __ASM_ARCH_EP93XX_KEYPAD_H */ diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index ba528f8..b0665f1 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -302,7 +302,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) udelay(1); } - if (i < MAX_CLOCK_ENABLE_WAIT) + if (i <= MAX_CLOCK_ENABLE_WAIT) pr_debug("Clock %s stable after %d loops\n", name, i); else printk(KERN_ERR "Clock %s didn't enable in %d tries\n", diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 9e43fe5..045da92 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -286,6 +286,20 @@ static struct omap_clk omap34xx_clks[] = { #define MIN_SDRC_DLL_LOCK_FREQ 83000000 +#define CYCLES_PER_MHZ 1000000 + +/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */ +#define SDRC_MPURATE_SCALE 8 + +/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */ +#define SDRC_MPURATE_BASE_SHIFT 9 + +/* + * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at + * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize + */ +#define SDRC_MPURATE_LOOPS 96 + /** * omap3_dpll_recalc - recalculate DPLL rate * @clk: DPLL struct clk @@ -709,7 +723,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) { u32 new_div = 0; u32 unlock_dll = 0; - unsigned long validrate, sdrcrate; + u32 c; + unsigned long validrate, sdrcrate, mpurate; struct omap_sdrc_params *sp; if (!clk || !rate) @@ -718,18 +733,15 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (clk != &dpll3_m2_ck) return -EINVAL; - if (rate == clk->rate) - return 0; - validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); if (validrate != rate) return -EINVAL; sdrcrate = sdrc_ick.rate; if (rate > clk->rate) - sdrcrate <<= ((rate / clk->rate) - 1); + sdrcrate <<= ((rate / clk->rate) >> 1); else - sdrcrate >>= ((clk->rate / rate) - 1); + sdrcrate >>= ((clk->rate / rate) >> 1); sp = omap2_sdrc_get_params(sdrcrate); if (!sp) @@ -740,17 +752,25 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) unlock_dll = 1; } + /* + * XXX This only needs to be done when the CPU frequency changes + */ + mpurate = arm_fck.rate / CYCLES_PER_MHZ; + c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; + c += 1; /* for safety */ + c *= SDRC_MPURATE_LOOPS; + c >>= SDRC_MPURATE_SCALE; + if (c == 0) + c = 1; + pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, validrate); pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); - /* REVISIT: SRAM code doesn't support other M2 divisors yet */ - WARN_ON(new_div != 1 && new_div != 2); - - /* REVISIT: Add SDRC_MR changing to this code also */ omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, - sp->actim_ctrlb, new_div, unlock_dll); + sp->actim_ctrlb, new_div, unlock_dll, c, + sp->mr, rate > clk->rate); return 0; } diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 32afd94..3a86b0f 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -21,6 +21,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/clk.h> #include <asm/tlb.h> @@ -241,6 +242,40 @@ void __init omap2_map_common_io(void) omapfb_reserve_sdram(); } +/* + * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters + * + * Sets the CORE DPLL3 M2 divider to the same value that it's at + * currently. This has the effect of setting the SDRC SDRAM AC timing + * registers to the values currently defined by the kernel. Currently + * only defined for OMAP3; will return 0 if called on OMAP2. Returns + * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, + * or passes along the return value of clk_set_rate(). + */ +static int __init _omap2_init_reprogram_sdrc(void) +{ + struct clk *dpll3_m2_ck; + int v = -EINVAL; + long rate; + + if (!cpu_is_omap34xx()) + return 0; + + dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); + if (!dpll3_m2_ck) + return -EINVAL; + + rate = clk_get_rate(dpll3_m2_ck); + pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); + v = clk_set_rate(dpll3_m2_ck, rate); + if (v) + pr_err("dpll3_m2_clk rate change failed: %d\n", v); + + clk_put(dpll3_m2_ck); + + return v; +} + void __init omap2_init_common_hw(struct omap_sdrc_params *sp) { omap2_mux_init(); @@ -249,6 +284,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sp) clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); omap2_clk_init(); omap2_sdrc_init(sp); + _omap2_init_reprogram_sdrc(); #endif gpmc_init(); } diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 73e2971..983f1cb 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -1099,7 +1099,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm) (c++ < PWRDM_TRANSITION_BAILOUT)) udelay(1); - if (c >= PWRDM_TRANSITION_BAILOUT) { + if (c > PWRDM_TRANSITION_BAILOUT) { printk(KERN_ERR "powerdomain: waited too long for " "powerdomain %s to complete transition\n", pwrdm->name); return -EAGAIN; diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index c080c825..f41f8d9 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -3,13 +3,12 @@ * * Omap3 specific functions that need to be run in internal SRAM * - * (C) Copyright 2007 - * Texas Instruments Inc. - * Rajendra Nayak <rnayak@ti.com> + * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc. + * Copyright (C) 2008 Nokia Corporation * - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> + * Rajendra Nayak <rnayak@ti.com> * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -37,61 +36,112 @@ .text +/* r4 parameters */ +#define SDRC_NO_UNLOCK_DLL 0x0 +#define SDRC_UNLOCK_DLL 0x1 + +/* SDRC_DLLA_CTRL bit settings */ +#define FIXEDDELAY_SHIFT 24 +#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT) +#define DLLIDLE_MASK 0x4 + +/* + * SDRC_DLLA_CTRL default values: TI hardware team indicates that + * FIXEDDELAY should be initialized to 0xf. This apparently was + * empirically determined during process testing, so no derivation + * was provided. + */ +#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT) + +/* SDRC_DLLA_STATUS bit settings */ +#define LOCKSTATUS_MASK 0x4 + +/* SDRC_POWER bit settings */ +#define SRFRONIDLEREQ_MASK 0x40 +#define PWDENA_MASK 0x4 + +/* CM_IDLEST1_CORE bit settings */ +#define ST_SDRC_MASK 0x2 + +/* CM_ICLKEN1_CORE bit settings */ +#define EN_SDRC_MASK 0x2 + +/* CM_CLKSEL1_PLL bit settings */ +#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b + /* - * Change frequency of core dpll - * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2 - * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for + * omap3_sram_configure_core_dpll - change DPLL3 M2 divider + * r0 = new SDRC_RFR_CTRL register contents + * r1 = new SDRC_ACTIM_CTRLA register contents + * r2 = new SDRC_ACTIM_CTRLB register contents + * r3 = new M2 divider setting (only 1 and 2 supported right now) + * r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for * SDRC rates < 83MHz + * r5 = number of MPU cycles to wait for SDRC to stabilize after + * reprogramming the SDRC when switching to a slower MPU speed + * r6 = new SDRC_MR_0 register value + * r7 = increasing SDRC rate? (1 = yes, 0 = no) + * */ ENTRY(omap3_sram_configure_core_dpll) stmfd sp!, {r1-r12, lr} @ store regs to stack ldr r4, [sp, #52] @ pull extra args off the stack + ldr r5, [sp, #56] @ load extra args from the stack + ldr r6, [sp, #60] @ load extra args from the stack + ldr r7, [sp, #64] @ load extra args from the stack dsb @ flush buffered writes to interconnect - cmp r3, #0x2 - blne configure_sdrc - cmp r4, #0x1 + cmp r7, #1 @ if increasing SDRC clk rate, + bleq configure_sdrc @ program the SDRC regs early (for RFR) + cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state bleq unlock_dll blne lock_dll - bl sdram_in_selfrefresh @ put the SDRAM in self refresh - bl configure_core_dpll - bl enable_sdrc - cmp r4, #0x1 + bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC + bl configure_core_dpll @ change the DPLL3 M2 divider + bl enable_sdrc @ take SDRC out of idle + cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change bleq wait_dll_unlock blne wait_dll_lock - cmp r3, #0x1 - blne configure_sdrc + cmp r7, #1 @ if increasing SDRC clk rate, + beq return_to_sdram @ return to SDRAM code, otherwise, + bl configure_sdrc @ reprogram SDRC regs now + mov r12, r5 + bl wait_clk_stable @ wait for SDRC to stabilize +return_to_sdram: isb @ prevent speculative exec past here mov r0, #0 @ return value ldmfd sp!, {r1-r12, pc} @ restore regs and return unlock_dll: ldr r11, omap3_sdrc_dlla_ctrl ldr r12, [r11] - orr r12, r12, #0x4 + and r12, r12, #FIXEDDELAY_MASK + orr r12, r12, #FIXEDDELAY_DEFAULT + orr r12, r12, #DLLIDLE_MASK str r12, [r11] @ (no OCP barrier needed) bx lr lock_dll: ldr r11, omap3_sdrc_dlla_ctrl ldr r12, [r11] - bic r12, r12, #0x4 + bic r12, r12, #DLLIDLE_MASK str r12, [r11] @ (no OCP barrier needed) bx lr sdram_in_selfrefresh: ldr r11, omap3_sdrc_power @ read the SDRC_POWER register ldr r12, [r11] @ read the contents of SDRC_POWER mov r9, r12 @ keep a copy of SDRC_POWER bits - orr r12, r12, #0x40 @ enable self refresh on idle req - bic r12, r12, #0x4 @ clear PWDENA + orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle + bic r12, r12, #PWDENA_MASK @ clear PWDENA str r12, [r11] @ write back to SDRC_POWER register ldr r12, [r11] @ posted-write barrier for SDRC +idle_sdrc: ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg ldr r12, [r11] - bic r12, r12, #0x2 @ disable iclk bit for SDRC + bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC str r12, [r11] wait_sdrc_idle: ldr r11, omap3_cm_idlest1_core ldr r12, [r11] - and r12, r12, #0x2 @ check for SDRC idle - cmp r12, #2 + and r12, r12, #ST_SDRC_MASK @ check for SDRC idle + cmp r12, #ST_SDRC_MASK bne wait_sdrc_idle bx lr configure_core_dpll: @@ -99,36 +149,23 @@ configure_core_dpll: ldr r12, [r11] ldr r10, core_m2_mask_val @ modify m2 for core dpll and r12, r12, r10 - orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val + orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT str r12, [r11] ldr r12, [r11] @ posted-write barrier for CM - mov r12, #0x800 @ wait for the clock to stabilise - cmp r3, #2 - bne wait_clk_stable bx lr wait_clk_stable: subs r12, r12, #1 bne wait_clk_stable - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop bx lr enable_sdrc: ldr r11, omap3_cm_iclken1_core ldr r12, [r11] - orr r12, r12, #0x2 @ enable iclk bit for SDRC + orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC str r12, [r11] wait_sdrc_idle1: ldr r11, omap3_cm_idlest1_core ldr r12, [r11] - and r12, r12, #0x2 + and r12, r12, #ST_SDRC_MASK cmp r12, #0 bne wait_sdrc_idle1 restore_sdrc_power_val: @@ -138,14 +175,14 @@ restore_sdrc_power_val: wait_dll_lock: ldr r11, omap3_sdrc_dlla_status ldr r12, [r11] - and r12, r12, #0x4 - cmp r12, #0x4 + and r12, r12, #LOCKSTATUS_MASK + cmp r12, #LOCKSTATUS_MASK bne wait_dll_lock bx lr wait_dll_unlock: ldr r11, omap3_sdrc_dlla_status ldr r12, [r11] - and r12, r12, #0x4 + and r12, r12, #LOCKSTATUS_MASK cmp r12, #0x0 bne wait_dll_unlock bx lr @@ -156,7 +193,9 @@ configure_sdrc: str r1, [r11] ldr r11, omap3_sdrc_actim_ctrlb str r2, [r11] - ldr r2, [r11] @ posted-write barrier for SDRC + ldr r11, omap3_sdrc_mr_0 + str r6, [r11] + ldr r6, [r11] @ posted-write barrier for SDRC bx lr omap3_sdrc_power: @@ -173,6 +212,8 @@ omap3_sdrc_actim_ctrla: .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) omap3_sdrc_actim_ctrlb: .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) +omap3_sdrc_mr_0: + .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0) omap3_sdrc_dlla_status: .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) omap3_sdrc_dlla_ctrl: diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index 6f3f77d..d78731e 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -200,6 +200,6 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) int __init orion5x_setup_sram_win(void) { - return setup_cpu_win(win_alloc_count, ORION5X_SRAM_PHYS_BASE, + return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index eafcc49..f87fa12 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -562,7 +562,7 @@ static struct platform_device orion5x_crypto_device = { .resource = orion5x_crypto_res, }; -int __init orion5x_crypto_init(void) +static int __init orion5x_crypto_init(void) { int ret; @@ -697,6 +697,14 @@ void __init orion5x_init(void) } /* + * The 5082/5181l/5182/6082/6082l/6183 have crypto + * while 5180n/5181/5281 don't have crypto. + */ + if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || + dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) + orion5x_crypto_init(); + + /* * Register watchdog driver */ orion5x_wdt_init(); diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index de483e8..8f00450 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -38,7 +38,6 @@ void orion5x_spi_init(void); void orion5x_uart0_init(void); void orion5x_uart1_init(void); void orion5x_xor_init(void); -int orion5x_crypto_init(void); /* * PCIe/PCI functions. diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index f4533f8..89c992b 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -401,6 +401,16 @@ config MACH_PALMZ72 Say Y here if you intend to run this kernel on Palm Zire 72 handheld computer. +config MACH_TREO680 + bool "Palm Treo 680" + default y + depends on ARCH_PXA_PALM + select PXA27x + select IWMMXT + help + Say Y here if you intend to run this kernel on Palm Treo 680 + smartphone. + config MACH_PALMLD bool "Palm LifeDrive" default y diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index d18ffef..d4c6122 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_MACH_PALMT5) += palmt5.o obj-$(CONFIG_MACH_PALMTX) += palmtx.o obj-$(CONFIG_MACH_PALMLD) += palmld.o obj-$(CONFIG_MACH_PALMZ72) += palmz72.o +obj-$(CONFIG_MACH_TREO680) += treo680.o obj-$(CONFIG_ARCH_VIPER) += viper.o ifeq ($(CONFIG_MACH_ZYLONITE),y) diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 962dda2..5363e1a 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -23,6 +23,7 @@ #include <linux/pm.h> #include <linux/gpio.h> #include <linux/backlight.h> +#include <linux/i2c.h> #include <linux/io.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> @@ -600,6 +601,10 @@ static struct platform_device *devices[] __initdata = { &sharpsl_rom_device, }; +static struct i2c_board_info __initdata corgi_i2c_devices[] = { + { I2C_BOARD_INFO("wm8731", 0x1b) }, +}; + static void corgi_poweroff(void) { if (!machine_is_corgi()) @@ -634,6 +639,7 @@ static void __init corgi_init(void) pxa_set_mci_info(&corgi_mci_platform_data); pxa_set_ficp_info(&corgi_ficp_platform_data); pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(corgi_i2c_devices)); platform_scoop_config = &corgi_pcmcia_config; diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 243e080..63b10d9 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -30,6 +30,7 @@ #include <linux/apm-emulation.h> #include <linux/i2c.h> #include <linux/i2c/pca953x.h> +#include <linux/regulator/userspace-consumer.h> #include <media/soc_camera.h> @@ -735,6 +736,7 @@ static struct pxa2xx_spi_chip em_x270_libertas_chip = { .rx_threshold = 1, .tx_threshold = 1, .timeout = 1000, + .gpio_cs = 14, }; static unsigned long em_x270_libertas_pin_config[] = { @@ -803,7 +805,6 @@ static int em_x270_libertas_teardown(struct spi_device *spi) struct libertas_spi_platform_data em_x270_libertas_pdata = { .use_dummy_writes = 1, - .gpio_cs = 14, .setup = em_x270_libertas_setup, .teardown = em_x270_libertas_teardown, }; @@ -838,10 +839,14 @@ static void __init em_x270_init_spi(void) static inline void em_x270_init_spi(void) {} #endif -#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE) +#if defined(CONFIG_SND_PXA2XX_LIB_AC97) +static pxa2xx_audio_ops_t em_x270_ac97_info = { + .reset_gpio = 113, +}; + static void __init em_x270_init_ac97(void) { - pxa_set_ac97_info(NULL); + pxa_set_ac97_info(&em_x270_ac97_info); } #else static inline void em_x270_init_ac97(void) {} @@ -1038,6 +1043,52 @@ static void __init em_x270_init_camera(void) static inline void em_x270_init_camera(void) {} #endif +static struct regulator_bulk_data em_x270_gps_consumer_supply = { + .supply = "vcc gps", +}; + +static struct regulator_userspace_consumer_data em_x270_gps_consumer_data = { + .name = "vcc gps", + .num_supplies = 1, + .supplies = &em_x270_gps_consumer_supply, +}; + +static struct platform_device em_x270_gps_userspace_consumer = { + .name = "reg-userspace-consumer", + .id = 0, + .dev = { + .platform_data = &em_x270_gps_consumer_data, + }, +}; + +static struct regulator_bulk_data em_x270_gprs_consumer_supply = { + .supply = "vcc gprs", +}; + +static struct regulator_userspace_consumer_data em_x270_gprs_consumer_data = { + .name = "vcc gprs", + .num_supplies = 1, + .supplies = &em_x270_gprs_consumer_supply +}; + +static struct platform_device em_x270_gprs_userspace_consumer = { + .name = "reg-userspace-consumer", + .id = 1, + .dev = { + .platform_data = &em_x270_gprs_consumer_data, + } +}; + +static struct platform_device *em_x270_userspace_consumers[] = { + &em_x270_gps_userspace_consumer, + &em_x270_gprs_userspace_consumer, +}; + +static void __init em_x270_userspace_consumers_init(void) +{ + platform_add_devices(ARRAY_AND_SIZE(em_x270_userspace_consumers)); +} + /* DA9030 related initializations */ #define REGULATOR_CONSUMER(_name, _dev, _supply) \ static struct regulator_consumer_supply _name##_consumers[] = { \ @@ -1047,11 +1098,11 @@ static inline void em_x270_init_camera(void) {} }, \ } -REGULATOR_CONSUMER(ldo3, NULL, "vcc gps"); +REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps"); REGULATOR_CONSUMER(ldo5, NULL, "vcc cam"); REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio"); REGULATOR_CONSUMER(ldo12, NULL, "vcc usb"); -REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs"); +REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs"); #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) \ static struct regulator_init_data _ldo##_data = { \ @@ -1062,6 +1113,7 @@ REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs"); .enabled = 0, \ }, \ .valid_ops_mask = _ops_mask, \ + .apply_uV = 1, \ }, \ .num_consumer_supplies = ARRAY_SIZE(_ldo##_consumers), \ .consumer_supplies = _ldo##_consumers, \ @@ -1240,6 +1292,7 @@ static void __init em_x270_init(void) em_x270_init_spi(); em_x270_init_i2c(); em_x270_init_camera(); + em_x270_userspace_consumers_init(); } MACHINE_START(EM_X270, "Compulab EM-X270") diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 7fff467..81359d5 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -30,6 +30,7 @@ #include <linux/pwm_backlight.h> #include <linux/regulator/bq24022.h> #include <linux/regulator/machine.h> +#include <linux/regulator/max1586.h> #include <linux/spi/ads7846.h> #include <linux/spi/spi.h> #include <linux/usb/gpio_vbus.h> @@ -775,6 +776,45 @@ static struct platform_device strataflash = { }; /* + * Maxim MAX1587A on PI2C + */ + +static struct regulator_consumer_supply max1587a_consumer = { + .supply = "vcc_core", +}; + +static struct regulator_init_data max1587a_v3_info = { + .constraints = { + .name = "vcc_core range", + .min_uV = 900000, + .max_uV = 1705000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max1587a_consumer, +}; + +static struct max1586_subdev_data max1587a_subdev = { + .name = "vcc_core", + .id = MAX1586_V3, + .platform_data = &max1587a_v3_info, +}; + +static struct max1586_platform_data max1587a_info = { + .num_subdevs = 1, + .subdevs = &max1587a_subdev, + .v3_gain = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */ +}; + +static struct i2c_board_info __initdata pi2c_board_info[] = { + { + I2C_BOARD_INFO("max1586", 0x14), + .platform_data = &max1587a_info, + }, +}; + +/* * PCMCIA */ @@ -828,6 +868,7 @@ static void __init hx4700_init(void) pxa_set_ficp_info(&ficp_info); pxa27x_set_i2c_power_info(NULL); pxa_set_i2c_info(NULL); + i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info)); pxa2xx_set_spi_info(2, &pxa_ssp2_master_info); spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info)); diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h index 5032307..2806ef6 100644 --- a/arch/arm/mach-pxa/include/mach/palmz72.h +++ b/arch/arm/mach-pxa/include/mach/palmz72.h @@ -21,7 +21,7 @@ /* SD/MMC */ #define GPIO_NR_PALMZ72_SD_DETECT_N 14 #define GPIO_NR_PALMZ72_SD_POWER_N 98 -#define GPIO_NR_PALMZ72_SD_RO 115 +#define GPIO_NR_PALMZ72_SD_RO 115 /* Touchscreen */ #define GPIO_NR_PALMZ72_WM9712_IRQ 27 @@ -31,8 +31,7 @@ /* USB */ #define GPIO_NR_PALMZ72_USB_DETECT_N 15 -#define GPIO_NR_PALMZ72_USB_POWER 95 -#define GPIO_NR_PALMZ72_USB_PULLUP 12 +#define GPIO_NR_PALMZ72_USB_PULLUP 95 /* LCD/Backlight */ #define GPIO_NR_PALMZ72_BL_POWER 20 diff --git a/arch/arm/mach-pxa/include/mach/treo680.h b/arch/arm/mach-pxa/include/mach/treo680.h new file mode 100644 index 0000000..af443b2 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/treo680.h @@ -0,0 +1,49 @@ +/* + * GPIOs and interrupts for Palm Treo 680 smartphone + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_TREO680_H_ +#define _INCLUDE_TREO680_H_ + +/* GPIOs */ +#define GPIO_NR_TREO680_POWER_DETECT 0 +#define GPIO_NR_TREO680_AMP_EN 27 +#define GPIO_NR_TREO680_KEYB_BL 24 +#define GPIO_NR_TREO680_VIBRATE_EN 44 +#define GPIO_NR_TREO680_GREEN_LED 20 +#define GPIO_NR_TREO680_RED_LED 79 +#define GPIO_NR_TREO680_SD_DETECT_N 113 +#define GPIO_NR_TREO680_SD_READONLY 33 +#define GPIO_NR_TREO680_EP_DETECT_N 116 +#define GPIO_NR_TREO680_SD_POWER 42 +#define GPIO_NR_TREO680_USB_DETECT 1 +#define GPIO_NR_TREO680_USB_PULLUP 114 +#define GPIO_NR_TREO680_GSM_POWER 40 +#define GPIO_NR_TREO680_GSM_RESET 87 +#define GPIO_NR_TREO680_GSM_WAKE 57 +#define GPIO_NR_TREO680_GSM_HOST_WAKE 14 +#define GPIO_NR_TREO680_GSM_TRIGGER 10 +#define GPIO_NR_TREO680_BT_EN 43 +#define GPIO_NR_TREO680_IR_EN 115 +#define GPIO_NR_TREO680_IR_TXD 47 +#define GPIO_NR_TREO680_BL_POWER 38 +#define GPIO_NR_TREO680_LCD_POWER 25 + +/* Various addresses */ +#define TREO680_PHYS_RAM_START 0xa0000000 +#define TREO680_PHYS_IO_START 0x40000000 +#define TREO680_STR_BASE 0xa2000000 + +/* BACKLIGHT */ +#define TREO680_MAX_INTENSITY 254 +#define TREO680_DEFAULT_INTENSITY 160 +#define TREO680_LIMIT_MASK 0x7F +#define TREO680_PRESCALER 63 +#define TREO680_PERIOD_NS 3500 + +#endif diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 4dc8c2e..2d28132 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -37,6 +37,7 @@ #include <linux/wm97xx_batt.h> #include <linux/mtd/physmap.h> #include <linux/usb/gpio_vbus.h> +#include <linux/regulator/max1586.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -717,6 +718,38 @@ static struct wm97xx_batt_info mioa701_battery_data = { }; /* + * Voltage regulation + */ +static struct regulator_consumer_supply max1586_consumers[] = { + { + .supply = "vcc_core", + } +}; + +static struct regulator_init_data max1586_v3_info = { + .constraints = { + .name = "vcc_core range", + .min_uV = 1000000, + .max_uV = 1705000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(max1586_consumers), + .consumer_supplies = max1586_consumers, +}; + +static struct max1586_subdev_data max1586_subdevs[] = { + { .name = "vcc_core", .id = MAX1586_V3, + .platform_data = &max1586_v3_info }, +}; + +static struct max1586_platform_data max1586_info = { + .subdevs = max1586_subdevs, + .num_subdevs = ARRAY_SIZE(max1586_subdevs), + .v3_gain = MAX1586_GAIN_NO_R24, /* 700..1475 mV */ +}; + +/* * Camera interface */ struct pxacamera_platform_data mioa701_pxacamera_platform_data = { @@ -725,6 +758,13 @@ struct pxacamera_platform_data mioa701_pxacamera_platform_data = { .mclk_10khz = 5000, }; +static struct i2c_board_info __initdata mioa701_pi2c_devices[] = { + { + I2C_BOARD_INFO("max1586", 0x14), + .platform_data = &max1586_info, + }, +}; + static struct soc_camera_link iclink = { .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */ }; @@ -825,7 +865,9 @@ static void __init mioa701_machine_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); gsm_init(); + i2c_register_board_info(1, ARRAY_AND_SIZE(mioa701_pi2c_devices)); pxa_set_i2c_info(&i2c_pdata); + pxa27x_set_i2c_power_info(NULL); pxa_set_camera_info(&mioa701_pxacamera_platform_data); i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices)); } diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index b88eb4d..c3645aa 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -27,7 +27,9 @@ #include <linux/pda_power.h> #include <linux/pwm_backlight.h> #include <linux/gpio.h> +#include <linux/wm97xx_batt.h> #include <linux/power_supply.h> +#include <linux/usb/gpio_vbus.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -41,6 +43,8 @@ #include <mach/irda.h> #include <mach/pxa27x_keypad.h> #include <mach/udc.h> +#include <mach/palmasoc.h> + #include <mach/pm.h> #include "generic.h" @@ -66,6 +70,8 @@ static unsigned long palmz72_pin_config[] __initdata = { GPIO29_AC97_SDATA_IN_0, GPIO30_AC97_SDATA_OUT, GPIO31_AC97_SYNC, + GPIO89_AC97_SYSCLK, + GPIO113_AC97_nRESET, /* IrDA */ GPIO49_GPIO, /* ir disable */ @@ -77,8 +83,7 @@ static unsigned long palmz72_pin_config[] __initdata = { /* USB */ GPIO15_GPIO, /* usb detect */ - GPIO12_GPIO, /* usb pullup */ - GPIO95_GPIO, /* usb power */ + GPIO95_GPIO, /* usb pullup */ /* Matrix keypad */ GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, @@ -355,6 +360,22 @@ static struct platform_device palmz72_leds = { }; /****************************************************************************** + * UDC + ******************************************************************************/ +static struct gpio_vbus_mach_info palmz72_udc_info = { + .gpio_vbus = GPIO_NR_PALMZ72_USB_DETECT_N, + .gpio_pullup = GPIO_NR_PALMZ72_USB_PULLUP, +}; + +static struct platform_device palmz72_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &palmz72_udc_info, + }, +}; + +/****************************************************************************** * Power supply ******************************************************************************/ static int power_supply_init(struct device *dev) @@ -422,6 +443,31 @@ static struct platform_device power_supply = { }; /****************************************************************************** + * WM97xx battery + ******************************************************************************/ +static struct wm97xx_batt_info wm97xx_batt_pdata = { + .batt_aux = WM97XX_AUX_ID3, + .temp_aux = WM97XX_AUX_ID2, + .charge_gpio = -1, + .max_voltage = PALMZ72_BAT_MAX_VOLTAGE, + .min_voltage = PALMZ72_BAT_MIN_VOLTAGE, + .batt_mult = 1000, + .batt_div = 414, + .temp_mult = 1, + .temp_div = 1, + .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO, + .batt_name = "main-batt", +}; + +/****************************************************************************** + * aSoC audio + ******************************************************************************/ +static struct platform_device palmz72_asoc = { + .name = "palm27x-asoc", + .id = -1, +}; + +/****************************************************************************** * Framebuffer ******************************************************************************/ static struct pxafb_mode_info palmz72_lcd_modes[] = { @@ -527,17 +573,32 @@ device_initcall(palmz72_pm_init); static struct platform_device *devices[] __initdata = { &palmz72_backlight, &palmz72_leds, + &palmz72_asoc, &power_supply, + &palmz72_gpio_vbus, }; +/* setup udc GPIOs initial state */ +static void __init palmz72_udc_init(void) +{ + if (!gpio_request(GPIO_NR_PALMZ72_USB_PULLUP, "USB Pullup")) { + gpio_direction_output(GPIO_NR_PALMZ72_USB_PULLUP, 0); + gpio_free(GPIO_NR_PALMZ72_USB_PULLUP); + } +} + static void __init palmz72_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config)); + set_pxa_fb_info(&palmz72_lcd_screen); pxa_set_mci_info(&palmz72_mci_platform_data); + palmz72_udc_init(); pxa_set_ac97_info(NULL); pxa_set_ficp_info(&palmz72_ficp_platform_data); pxa_set_keypad_info(&palmz72_keypad_platform_data); + wm97xx_bat_set_pdata(&wm97xx_batt_pdata); + platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index ac431ed..9352d4a 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -22,6 +22,7 @@ #include <linux/delay.h> #include <linux/mtd/physmap.h> #include <linux/gpio.h> +#include <linux/i2c.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> #include <linux/mtd/sharpsl.h> @@ -486,6 +487,10 @@ static struct platform_device *devices[] __initdata = { &sharpsl_rom_device, }; +static struct i2c_board_info __initdata poodle_i2c_devices[] = { + { I2C_BOARD_INFO("wm8731", 0x1b) }, +}; + static void poodle_poweroff(void) { arm_machine_restart('h', NULL); @@ -519,6 +524,7 @@ static void __init poodle_init(void) pxa_set_mci_info(&poodle_mci_platform_data); pxa_set_ficp_info(&poodle_ficp_platform_data); pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(poodle_i2c_devices)); poodle_init_spi(); } diff --git a/arch/arm/mach-pxa/treo680.c b/arch/arm/mach-pxa/treo680.c new file mode 100644 index 0000000..a06f19e --- /dev/null +++ b/arch/arm/mach-pxa/treo680.c @@ -0,0 +1,612 @@ +/* + * Hardware definitions for Palm Treo 680 + * + * Author: Tomas Cech <sleep_walker@suse.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * (find more info at www.hackndev.com) + * + */ + +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/irq.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/pda_power.h> +#include <linux/pwm_backlight.h> +#include <linux/gpio.h> +#include <linux/wm97xx_batt.h> +#include <linux/power_supply.h> +#include <linux/sysdev.h> +#include <linux/w1-gpio.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <mach/pxa27x.h> +#include <mach/pxa27x-udc.h> +#include <mach/audio.h> +#include <mach/treo680.h> +#include <mach/mmc.h> +#include <mach/pxafb.h> +#include <mach/irda.h> +#include <mach/pxa27x_keypad.h> +#include <mach/udc.h> +#include <mach/ohci.h> +#include <mach/pxa2xx-regs.h> +#include <mach/palmasoc.h> +#include <mach/camera.h> + +#include <sound/pxa2xx-lib.h> + +#include "generic.h" +#include "devices.h" + +/****************************************************************************** + * Pin configuration + ******************************************************************************/ +static unsigned long treo680_pin_config[] __initdata = { + /* MMC */ + GPIO32_MMC_CLK, + GPIO92_MMC_DAT_0, + GPIO109_MMC_DAT_1, + GPIO110_MMC_DAT_2, + GPIO111_MMC_DAT_3, + GPIO112_MMC_CMD, + GPIO33_GPIO, /* SD read only */ + GPIO113_GPIO, /* SD detect */ + + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + GPIO89_AC97_SYSCLK, + GPIO95_AC97_nRESET, + + /* IrDA */ + GPIO46_FICP_RXD, + GPIO47_FICP_TXD, + + /* PWM */ + GPIO16_PWM0_OUT, + + /* USB */ + GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, /* usb detect */ + + /* MATRIX KEYPAD */ + GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, + GPIO101_KP_MKIN_1, + GPIO102_KP_MKIN_2, + GPIO97_KP_MKIN_3, + GPIO98_KP_MKIN_4, + GPIO99_KP_MKIN_5, + GPIO91_KP_MKIN_6, + GPIO13_KP_MKIN_7, + GPIO103_KP_MKOUT_0 | MFP_LPM_DRIVE_HIGH, + GPIO104_KP_MKOUT_1, + GPIO105_KP_MKOUT_2, + GPIO106_KP_MKOUT_3, + GPIO107_KP_MKOUT_4, + GPIO108_KP_MKOUT_5, + GPIO96_KP_MKOUT_6, + GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, /* Hotsync button */ + + /* LCD */ + GPIO58_LCD_LDD_0, + GPIO59_LCD_LDD_1, + GPIO60_LCD_LDD_2, + GPIO61_LCD_LDD_3, + GPIO62_LCD_LDD_4, + GPIO63_LCD_LDD_5, + GPIO64_LCD_LDD_6, + GPIO65_LCD_LDD_7, + GPIO66_LCD_LDD_8, + GPIO67_LCD_LDD_9, + GPIO68_LCD_LDD_10, + GPIO69_LCD_LDD_11, + GPIO70_LCD_LDD_12, + GPIO71_LCD_LDD_13, + GPIO72_LCD_LDD_14, + GPIO73_LCD_LDD_15, + GPIO74_LCD_FCLK, + GPIO75_LCD_LCLK, + GPIO76_LCD_PCLK, + + /* Quick Capture Interface */ + GPIO84_CIF_FV, + GPIO85_CIF_LV, + GPIO53_CIF_MCLK, + GPIO54_CIF_PCLK, + GPIO81_CIF_DD_0, + GPIO55_CIF_DD_1, + GPIO51_CIF_DD_2, + GPIO50_CIF_DD_3, + GPIO52_CIF_DD_4, + GPIO48_CIF_DD_5, + GPIO17_CIF_DD_6, + GPIO12_CIF_DD_7, + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + + /* GSM */ + GPIO14_GPIO | WAKEUP_ON_EDGE_BOTH, /* GSM host wake up */ + GPIO34_FFUART_RXD, + GPIO35_FFUART_CTS, + GPIO39_FFUART_TXD, + GPIO41_FFUART_RTS, + + /* MISC. */ + GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, /* external power detect */ + GPIO15_GPIO | WAKEUP_ON_EDGE_BOTH, /* silent switch */ + GPIO116_GPIO, /* headphone detect */ + GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH, /* bluetooth host wake up */ +}; + +/****************************************************************************** + * SD/MMC card controller + ******************************************************************************/ +static int treo680_mci_init(struct device *dev, + irq_handler_t treo680_detect_int, void *data) +{ + int err = 0; + + /* Setup an interrupt for detecting card insert/remove events */ + err = gpio_request(GPIO_NR_TREO680_SD_DETECT_N, "SD IRQ"); + + if (err) + goto err; + + err = gpio_direction_input(GPIO_NR_TREO680_SD_DETECT_N); + if (err) + goto err2; + + err = request_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N), + treo680_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM | + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "SD/MMC card detect", data); + + if (err) { + dev_err(dev, "%s: cannot request SD/MMC card detect IRQ\n", + __func__); + goto err2; + } + + err = gpio_request(GPIO_NR_TREO680_SD_POWER, "SD_POWER"); + if (err) + goto err3; + + err = gpio_direction_output(GPIO_NR_TREO680_SD_POWER, 1); + if (err) + goto err4; + + err = gpio_request(GPIO_NR_TREO680_SD_READONLY, "SD_READONLY"); + if (err) + goto err4; + + err = gpio_direction_input(GPIO_NR_TREO680_SD_READONLY); + if (err) + goto err5; + + return 0; + +err5: + gpio_free(GPIO_NR_TREO680_SD_READONLY); +err4: + gpio_free(GPIO_NR_TREO680_SD_POWER); +err3: + free_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N), data); +err2: + gpio_free(GPIO_NR_TREO680_SD_DETECT_N); +err: + return err; +} + +static void treo680_mci_exit(struct device *dev, void *data) +{ + gpio_free(GPIO_NR_TREO680_SD_READONLY); + gpio_free(GPIO_NR_TREO680_SD_POWER); + free_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N), data); + gpio_free(GPIO_NR_TREO680_SD_DETECT_N); +} + +static void treo680_mci_power(struct device *dev, unsigned int vdd) +{ + struct pxamci_platform_data *p_d = dev->platform_data; + gpio_set_value(GPIO_NR_TREO680_SD_POWER, p_d->ocr_mask & (1 << vdd)); +} + +static int treo680_mci_get_ro(struct device *dev) +{ + return gpio_get_value(GPIO_NR_TREO680_SD_READONLY); +} + +static struct pxamci_platform_data treo680_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .setpower = treo680_mci_power, + .get_ro = treo680_mci_get_ro, + .init = treo680_mci_init, + .exit = treo680_mci_exit, +}; + +/****************************************************************************** + * GPIO keyboard + ******************************************************************************/ +static unsigned int treo680_matrix_keys[] = { + KEY(0, 0, KEY_F8), /* Red/Off/Power */ + KEY(0, 1, KEY_LEFT), + KEY(0, 2, KEY_LEFTCTRL), /* Alternate */ + KEY(0, 3, KEY_L), + KEY(0, 4, KEY_A), + KEY(0, 5, KEY_Q), + KEY(0, 6, KEY_P), + + KEY(1, 0, KEY_RIGHTCTRL), /* Menu */ + KEY(1, 1, KEY_RIGHT), + KEY(1, 2, KEY_LEFTSHIFT), /* Left shift */ + KEY(1, 3, KEY_Z), + KEY(1, 4, KEY_S), + KEY(1, 5, KEY_W), + + KEY(2, 0, KEY_F1), /* Phone */ + KEY(2, 1, KEY_UP), + KEY(2, 2, KEY_0), + KEY(2, 3, KEY_X), + KEY(2, 4, KEY_D), + KEY(2, 5, KEY_E), + + KEY(3, 0, KEY_F10), /* Calendar */ + KEY(3, 1, KEY_DOWN), + KEY(3, 2, KEY_SPACE), + KEY(3, 3, KEY_C), + KEY(3, 4, KEY_F), + KEY(3, 5, KEY_R), + + KEY(4, 0, KEY_F12), /* Mail */ + KEY(4, 1, KEY_KPENTER), + KEY(4, 2, KEY_RIGHTALT), /* Alt */ + KEY(4, 3, KEY_V), + KEY(4, 4, KEY_G), + KEY(4, 5, KEY_T), + + KEY(5, 0, KEY_F9), /* Home */ + KEY(5, 1, KEY_PAGEUP), /* Side up */ + KEY(5, 2, KEY_DOT), + KEY(5, 3, KEY_B), + KEY(5, 4, KEY_H), + KEY(5, 5, KEY_Y), + + KEY(6, 0, KEY_TAB), /* Side Activate */ + KEY(6, 1, KEY_PAGEDOWN), /* Side down */ + KEY(6, 2, KEY_ENTER), + KEY(6, 3, KEY_N), + KEY(6, 4, KEY_J), + KEY(6, 5, KEY_U), + + KEY(7, 0, KEY_F6), /* Green/Call */ + KEY(7, 1, KEY_O), + KEY(7, 2, KEY_BACKSPACE), + KEY(7, 3, KEY_M), + KEY(7, 4, KEY_K), + KEY(7, 5, KEY_I), +}; + +static struct pxa27x_keypad_platform_data treo680_keypad_platform_data = { + .matrix_key_rows = 8, + .matrix_key_cols = 7, + .matrix_key_map = treo680_matrix_keys, + .matrix_key_map_size = ARRAY_SIZE(treo680_matrix_keys), + .direct_key_map = { KEY_CONNECT }, + .direct_key_num = 1, + + .debounce_interval = 30, +}; + +/****************************************************************************** + * aSoC audio + ******************************************************************************/ + +static pxa2xx_audio_ops_t treo680_ac97_pdata = { + .reset_gpio = 95, +}; + +/****************************************************************************** + * Backlight + ******************************************************************************/ +static int treo680_backlight_init(struct device *dev) +{ + int ret; + + ret = gpio_request(GPIO_NR_TREO680_BL_POWER, "BL POWER"); + if (ret) + goto err; + ret = gpio_direction_output(GPIO_NR_TREO680_BL_POWER, 0); + if (ret) + goto err2; + ret = gpio_request(GPIO_NR_TREO680_LCD_POWER, "LCD POWER"); + if (ret) + goto err2; + ret = gpio_direction_output(GPIO_NR_TREO680_LCD_POWER, 0); + if (ret) + goto err3; + + return 0; +err3: + gpio_free(GPIO_NR_TREO680_LCD_POWER); +err2: + gpio_free(GPIO_NR_TREO680_BL_POWER); +err: + return ret; +} + +static int treo680_backlight_notify(int brightness) +{ + gpio_set_value(GPIO_NR_TREO680_BL_POWER, brightness); + return TREO680_MAX_INTENSITY - brightness; +}; + +static void treo680_backlight_exit(struct device *dev) +{ + gpio_free(GPIO_NR_TREO680_BL_POWER); + gpio_free(GPIO_NR_TREO680_LCD_POWER); +} + +static struct platform_pwm_backlight_data treo680_backlight_data = { + .pwm_id = 0, + .max_brightness = TREO680_MAX_INTENSITY, + .dft_brightness = TREO680_DEFAULT_INTENSITY, + .pwm_period_ns = TREO680_PERIOD_NS, + .init = treo680_backlight_init, + .notify = treo680_backlight_notify, + .exit = treo680_backlight_exit, +}; + +static struct platform_device treo680_backlight = { + .name = "pwm-backlight", + .dev = { + .parent = &pxa27x_device_pwm0.dev, + .platform_data = &treo680_backlight_data, + }, +}; + +/****************************************************************************** + * IrDA + ******************************************************************************/ +static void treo680_transceiver_mode(struct device *dev, int mode) +{ + gpio_set_value(GPIO_NR_TREO680_IR_EN, mode & IR_OFF); + pxa2xx_transceiver_mode(dev, mode); +} + +static int treo680_irda_startup(struct device *dev) +{ + int err; + + err = gpio_request(GPIO_NR_TREO680_IR_EN, "Ir port disable"); + if (err) + goto err1; + + err = gpio_direction_output(GPIO_NR_TREO680_IR_EN, 1); + if (err) + goto err2; + + return 0; + +err2: + dev_err(dev, "treo680_irda: cannot change IR gpio direction\n"); + gpio_free(GPIO_NR_TREO680_IR_EN); +err1: + dev_err(dev, "treo680_irda: cannot allocate IR gpio\n"); + return err; +} + +static void treo680_irda_shutdown(struct device *dev) +{ + gpio_free(GPIO_NR_TREO680_AMP_EN); +} + +static struct pxaficp_platform_data treo680_ficp_info = { + .transceiver_cap = IR_FIRMODE | IR_SIRMODE | IR_OFF, + .startup = treo680_irda_startup, + .shutdown = treo680_irda_shutdown, + .transceiver_mode = treo680_transceiver_mode, +}; + +/****************************************************************************** + * UDC + ******************************************************************************/ +static struct pxa2xx_udc_mach_info treo680_udc_info __initdata = { + .gpio_vbus = GPIO_NR_TREO680_USB_DETECT, + .gpio_vbus_inverted = 1, + .gpio_pullup = GPIO_NR_TREO680_USB_PULLUP, +}; + + +/****************************************************************************** + * USB host + ******************************************************************************/ +static struct pxaohci_platform_data treo680_ohci_info = { + .port_mode = PMM_PERPORT_MODE, + .flags = ENABLE_PORT1 | ENABLE_PORT3, + .power_budget = 0, +}; + +/****************************************************************************** + * Power supply + ******************************************************************************/ +static int power_supply_init(struct device *dev) +{ + int ret; + + ret = gpio_request(GPIO_NR_TREO680_POWER_DETECT, "CABLE_STATE_AC"); + if (ret) + goto err1; + ret = gpio_direction_input(GPIO_NR_TREO680_POWER_DETECT); + if (ret) + goto err2; + + return 0; + +err2: + gpio_free(GPIO_NR_TREO680_POWER_DETECT); +err1: + return ret; +} + +static int treo680_is_ac_online(void) +{ + return gpio_get_value(GPIO_NR_TREO680_POWER_DETECT); +} + +static void power_supply_exit(struct device *dev) +{ + gpio_free(GPIO_NR_TREO680_POWER_DETECT); +} + +static char *treo680_supplicants[] = { + "main-battery", +}; + +static struct pda_power_pdata power_supply_info = { + .init = power_supply_init, + .is_ac_online = treo680_is_ac_online, + .exit = power_supply_exit, + .supplied_to = treo680_supplicants, + .num_supplicants = ARRAY_SIZE(treo680_supplicants), +}; + +static struct platform_device power_supply = { + .name = "pda-power", + .id = -1, + .dev = { + .platform_data = &power_supply_info, + }, +}; + +/****************************************************************************** + * Vibra and LEDs + ******************************************************************************/ +static struct gpio_led gpio_leds[] = { + { + .name = "treo680:vibra:vibra", + .default_trigger = "none", + .gpio = GPIO_NR_TREO680_VIBRATE_EN, + }, + { + .name = "treo680:green:led", + .default_trigger = "mmc0", + .gpio = GPIO_NR_TREO680_GREEN_LED, + }, + { + .name = "treo680:keybbl:keybbl", + .default_trigger = "none", + .gpio = GPIO_NR_TREO680_KEYB_BL, + }, +}; + +static struct gpio_led_platform_data gpio_led_info = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device treo680_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpio_led_info, + } +}; + + +/****************************************************************************** + * Framebuffer + ******************************************************************************/ +/* TODO: add support for 324x324 */ +static struct pxafb_mode_info treo680_lcd_modes[] = { +{ + .pixclock = 86538, + .xres = 320, + .yres = 320, + .bpp = 16, + + .left_margin = 20, + .right_margin = 8, + .upper_margin = 8, + .lower_margin = 5, + + .hsync_len = 4, + .vsync_len = 1, +}, +}; + +static struct pxafb_mach_info treo680_lcd_screen = { + .modes = treo680_lcd_modes, + .num_modes = ARRAY_SIZE(treo680_lcd_modes), + .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, +}; + +/****************************************************************************** + * Power management - standby + ******************************************************************************/ +static void __init treo680_pm_init(void) +{ + static u32 resume[] = { + 0xe3a00101, /* mov r0, #0x40000000 */ + 0xe380060f, /* orr r0, r0, #0x00f00000 */ + 0xe590f008, /* ldr pc, [r0, #0x08] */ + }; + + /* this is where the bootloader jumps */ + memcpy(phys_to_virt(TREO680_STR_BASE), resume, sizeof(resume)); +} + +/****************************************************************************** + * Machine init + ******************************************************************************/ +static struct platform_device *devices[] __initdata = { + &treo680_backlight, + &treo680_leds, + &power_supply, +}; + +/* setup udc GPIOs initial state */ +static void __init treo680_udc_init(void) +{ + if (!gpio_request(GPIO_NR_TREO680_USB_PULLUP, "UDC Vbus")) { + gpio_direction_output(GPIO_NR_TREO680_USB_PULLUP, 1); + gpio_free(GPIO_NR_TREO680_USB_PULLUP); + } +} + +static void __init treo680_init(void) +{ + treo680_pm_init(); + pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config)); + pxa_set_keypad_info(&treo680_keypad_platform_data); + set_pxa_fb_info(&treo680_lcd_screen); + pxa_set_mci_info(&treo680_mci_platform_data); + treo680_udc_init(); + pxa_set_udc_info(&treo680_udc_info); + pxa_set_ac97_info(&treo680_ac97_pdata); + pxa_set_ficp_info(&treo680_ficp_info); + pxa_set_ohci_info(&treo680_ohci_info); + + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +MACHINE_START(TREO680, "Palm Treo 680") + .phys_io = TREO680_PHYS_IO_START, + .io_pg_offst = io_p2v(0x40000000), + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa27x_init_irq, + .timer = &pxa_timer, + .init_machine = treo680_init, +MACHINE_END diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 1fe294d..ede2a57 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -27,6 +27,7 @@ #include <asm/irq.h> #include <asm/leds.h> #include <asm/mach-types.h> +#include <asm/smp_twd.h> #include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c index 6cd9377..50e25fc 100644 --- a/arch/arm/mach-s3c2410/usb-simtec.c +++ b/arch/arm/mach-s3c2410/usb-simtec.c @@ -22,7 +22,6 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/device.h> -#include <linux/gpio.h> #include <linux/io.h> #include <asm/mach/arch.h> diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index 5df73cb..8cfeaec 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig @@ -84,5 +84,15 @@ config MACH_AT2440EVB help Say Y here if you are using the AT2440EVB development board +config MACH_MINI2440 + bool "MINI2440 development board" + select CPU_S3C2440 + select EEPROM_AT24 + select LEDS_TRIGGER_BACKLIGHT + select SND_S3C24XX_SOC_S3C24XX_UDA134X + help + Say Y here to select support for the MINI2440. Is a 10cm x 10cm board + available via various sources. It can come with a 3.5" or 7" touch LCD. + endmenu diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile index 0b4440e..bfadcf6 100644 --- a/arch/arm/mach-s3c2440/Makefile +++ b/arch/arm/mach-s3c2440/Makefile @@ -22,3 +22,4 @@ obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o +obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c new file mode 100644 index 0000000..6a5bc30 --- /dev/null +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -0,0 +1,703 @@ +/* linux/arch/arm/mach-s3c2440/mach-mini2440.c + * + * Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com> + * Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk> + * and modifications by SBZ <sbz@spgui.org> and + * Weibing <http://weibing.blogbus.com> and + * Michel Pollet <buserror@gmail.com> + * + * For product information, visit http://code.google.com/p/mini2440/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/input.h> +#include <linux/io.h> +#include <linux/serial_core.h> +#include <linux/dm9000.h> +#include <linux/i2c/at24.h> +#include <linux/platform_device.h> +#include <linux/gpio_keys.h> +#include <linux/i2c.h> +#include <linux/mmc/host.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/fb.h> +#include <asm/mach-types.h> + +#include <plat/regs-serial.h> +#include <mach/regs-gpio.h> +#include <mach/leds-gpio.h> +#include <mach/regs-mem.h> +#include <mach/regs-lcd.h> +#include <mach/irqs.h> +#include <plat/nand.h> +#include <plat/iic.h> +#include <plat/mci.h> +#include <plat/udc.h> + +#include <plat/regs-serial.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> +#include <linux/mtd/partitions.h> + +#include <plat/clock.h> +#include <plat/devs.h> +#include <plat/cpu.h> + +#include <sound/s3c24xx_uda134x.h> + +#define MACH_MINI2440_DM9K_BASE (S3C2410_CS4 + 0x300) + +static struct map_desc mini2440_iodesc[] __initdata = { + /* nothing to declare, move along */ +}; + +#define UCON S3C2410_UCON_DEFAULT +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE + + +static struct s3c2410_uartcfg mini2440_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, +}; + +/* USB device UDC support */ + +static void mini2440_udc_pullup(enum s3c2410_udc_cmd_e cmd) +{ + pr_debug("udc: pullup(%d)\n", cmd); + + switch (cmd) { + case S3C2410_UDC_P_ENABLE : + s3c2410_gpio_setpin(S3C2410_GPC(5), 1); + break; + case S3C2410_UDC_P_DISABLE : + s3c2410_gpio_setpin(S3C2410_GPC(5), 0); + break; + case S3C2410_UDC_P_RESET : + break; + default: + break; + } +} + +static struct s3c2410_udc_mach_info mini2440_udc_cfg __initdata = { + .udc_command = mini2440_udc_pullup, +}; + + +/* LCD timing and setup */ + +/* + * This macro simplifies the table bellow + */ +#define _LCD_DECLARE(_clock,_xres,margin_left,margin_right,hsync, \ + _yres,margin_top,margin_bottom,vsync, refresh) \ + .width = _xres, \ + .xres = _xres, \ + .height = _yres, \ + .yres = _yres, \ + .left_margin = margin_left, \ + .right_margin = margin_right, \ + .upper_margin = margin_top, \ + .lower_margin = margin_bottom, \ + .hsync_len = hsync, \ + .vsync_len = vsync, \ + .pixclock = ((_clock*100000000000LL) / \ + ((refresh) * \ + (hsync + margin_left + _xres + margin_right) * \ + (vsync + margin_top + _yres + margin_bottom))), \ + .bpp = 16,\ + .type = (S3C2410_LCDCON1_TFT16BPP |\ + S3C2410_LCDCON1_TFT) + +struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = { + [0] = { /* mini2440 + 3.5" TFT + touchscreen */ + _LCD_DECLARE( + 7, /* The 3.5 is quite fast */ + 240, 21, 38, 6, /* x timing */ + 320, 4, 4, 2, /* y timing */ + 60), /* refresh rate */ + .lcdcon5 = (S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_INVVFRAME | + S3C2410_LCDCON5_INVVDEN | + S3C2410_LCDCON5_PWREN), + }, + [1] = { /* mini2440 + 7" TFT + touchscreen */ + _LCD_DECLARE( + 10, /* the 7" runs slower */ + 800, 40, 40, 48, /* x timing */ + 480, 29, 3, 3, /* y timing */ + 50), /* refresh rate */ + .lcdcon5 = (S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_INVVFRAME | + S3C2410_LCDCON5_PWREN), + }, + /* The VGA shield can outout at several resolutions. All share + * the same timings, however, anything smaller than 1024x768 + * will only be displayed in the top left corner of a 1024x768 + * XGA output unless you add optional dip switches to the shield. + * Therefore timings for other resolutions have been ommited here. + */ + [2] = { + _LCD_DECLARE( + 10, + 1024, 1, 2, 2, /* y timing */ + 768, 200, 16, 16, /* x timing */ + 24), /* refresh rate, maximum stable, + tested with the FPGA shield */ + .lcdcon5 = (S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_HWSWP), + }, +}; + +/* todo - put into gpio header */ + +#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2)) +#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2)) + +struct s3c2410fb_mach_info mini2440_fb_info __initdata = { + .displays = &mini2440_lcd_cfg[0], /* not constant! see init */ + .num_displays = 1, + .default_display = 0, + + /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN + * and disable the pull down resistors on pins we are using for LCD + * data. */ + + .gpcup = (0xf << 1) | (0x3f << 10), + + .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE | + S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM | + S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 | + S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 | + S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7), + + .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) | + S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) | + S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) | + S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) | + S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)), + + .gpdup = (0x3f << 2) | (0x3f << 10), + + .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 | + S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 | + S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 | + S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 | + S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 | + S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23), + + .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) | + S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) | + S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) | + S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)| + S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)| + S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)), +}; + +/* MMC/SD */ + +static struct s3c24xx_mci_pdata mini2440_mmc_cfg __initdata = { + .gpio_detect = S3C2410_GPG(8), + .gpio_wprotect = S3C2410_GPH(8), + .set_power = NULL, + .ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34, +}; + +/* NAND Flash on MINI2440 board */ + +static struct mtd_partition mini2440_default_nand_part[] __initdata = { + [0] = { + .name = "u-boot", + .size = SZ_256K, + .offset = 0, + }, + [1] = { + .name = "u-boot-env", + .size = SZ_128K, + .offset = SZ_256K, + }, + [2] = { + .name = "kernel", + /* 5 megabytes, for a kernel with no modules + * or a uImage with a ramdisk attached */ + .size = 0x00500000, + .offset = SZ_256K + SZ_128K, + }, + [3] = { + .name = "root", + .offset = SZ_256K + SZ_128K + 0x00500000, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct s3c2410_nand_set mini2440_nand_sets[] __initdata = { + [0] = { + .name = "nand", + .nr_chips = 1, + .nr_partitions = ARRAY_SIZE(mini2440_default_nand_part), + .partitions = mini2440_default_nand_part, + }, +}; + +static struct s3c2410_platform_nand mini2440_nand_info __initdata = { + .tacls = 0, + .twrph0 = 25, + .twrph1 = 15, + .nr_sets = ARRAY_SIZE(mini2440_nand_sets), + .sets = mini2440_nand_sets, + .ignore_unset_ecc = 1, +}; + +/* DM9000AEP 10/100 ethernet controller */ + +static struct resource mini2440_dm9k_resource[] __initdata = { + [0] = { + .start = MACH_MINI2440_DM9K_BASE, + .end = MACH_MINI2440_DM9K_BASE + 3, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = MACH_MINI2440_DM9K_BASE + 4, + .end = MACH_MINI2440_DM9K_BASE + 7, + .flags = IORESOURCE_MEM + }, + [2] = { + .start = IRQ_EINT7, + .end = IRQ_EINT7, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, + } +}; + +/* + * The DM9000 has no eeprom, and it's MAC address is set by + * the bootloader before starting the kernel. + */ +static struct dm9000_plat_data mini2440_dm9k_pdata __initdata = { + .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM), +}; + +static struct platform_device mini2440_device_eth __initdata = { + .name = "dm9000", + .id = -1, + .num_resources = ARRAY_SIZE(mini2440_dm9k_resource), + .resource = mini2440_dm9k_resource, + .dev = { + .platform_data = &mini2440_dm9k_pdata, + }, +}; + +/* CON5 + * +--+ /-----\ + * | | | | + * | | | BAT | + * | | \_____/ + * | | + * | | +----+ +----+ + * | | | K5 | | K1 | + * | | +----+ +----+ + * | | +----+ +----+ + * | | | K4 | | K2 | + * | | +----+ +----+ + * | | +----+ +----+ + * | | | K6 | | K3 | + * | | +----+ +----+ + * ..... + */ +static struct gpio_keys_button mini2440_buttons[] __initdata = { + { + .gpio = S3C2410_GPG(0), /* K1 */ + .code = KEY_F1, + .desc = "Button 1", + .active_low = 1, + }, + { + .gpio = S3C2410_GPG(3), /* K2 */ + .code = KEY_F2, + .desc = "Button 2", + .active_low = 1, + }, + { + .gpio = S3C2410_GPG(5), /* K3 */ + .code = KEY_F3, + .desc = "Button 3", + .active_low = 1, + }, + { + .gpio = S3C2410_GPG(6), /* K4 */ + .code = KEY_POWER, + .desc = "Power", + .active_low = 1, + }, + { + .gpio = S3C2410_GPG(7), /* K5 */ + .code = KEY_F5, + .desc = "Button 5", + .active_low = 1, + }, +#if 0 + /* this pin is also known as TCLK1 and seems to already + * marked as "in use" somehow in the kernel -- possibly wrongly */ + { + .gpio = S3C2410_GPG(11), /* K6 */ + .code = KEY_F6, + .desc = "Button 6", + .active_low = 1, + }, +#endif +}; + +static struct gpio_keys_platform_data mini2440_button_data __initdata = { + .buttons = mini2440_buttons, + .nbuttons = ARRAY_SIZE(mini2440_buttons), +}; + +static struct platform_device mini2440_button_device __initdata = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &mini2440_button_data, + } +}; + +/* LEDS */ + +static struct s3c24xx_led_platdata mini2440_led1_pdata __initdata = { + .name = "led1", + .gpio = S3C2410_GPB(5), + .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, + .def_trigger = "heartbeat", +}; + +static struct s3c24xx_led_platdata mini2440_led2_pdata __initdata = { + .name = "led2", + .gpio = S3C2410_GPB(6), + .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, + .def_trigger = "nand-disk", +}; + +static struct s3c24xx_led_platdata mini2440_led3_pdata __initdata = { + .name = "led3", + .gpio = S3C2410_GPB(7), + .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, + .def_trigger = "mmc0", +}; + +static struct s3c24xx_led_platdata mini2440_led4_pdata __initdata = { + .name = "led4", + .gpio = S3C2410_GPB(8), + .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, + .def_trigger = "", +}; + +static struct s3c24xx_led_platdata mini2440_led_backlight_pdata __initdata = { + .name = "backlight", + .gpio = S3C2410_GPG(4), + .def_trigger = "backlight", +}; + +static struct platform_device mini2440_led1 __initdata = { + .name = "s3c24xx_led", + .id = 1, + .dev = { + .platform_data = &mini2440_led1_pdata, + }, +}; + +static struct platform_device mini2440_led2 __initdata = { + .name = "s3c24xx_led", + .id = 2, + .dev = { + .platform_data = &mini2440_led2_pdata, + }, +}; + +static struct platform_device mini2440_led3 __initdata = { + .name = "s3c24xx_led", + .id = 3, + .dev = { + .platform_data = &mini2440_led3_pdata, + }, +}; + +static struct platform_device mini2440_led4 __initdata = { + .name = "s3c24xx_led", + .id = 4, + .dev = { + .platform_data = &mini2440_led4_pdata, + }, +}; + +static struct platform_device mini2440_led_backlight __initdata = { + .name = "s3c24xx_led", + .id = 5, + .dev = { + .platform_data = &mini2440_led_backlight_pdata, + }, +}; + +/* AUDIO */ + +static struct s3c24xx_uda134x_platform_data mini2440_audio_pins __initdata = { + .l3_clk = S3C2410_GPB(4), + .l3_mode = S3C2410_GPB(2), + .l3_data = S3C2410_GPB(3), + .model = UDA134X_UDA1341 +}; + +static struct platform_device mini2440_audio __initdata = { + .name = "s3c24xx_uda134x", + .id = 0, + .dev = { + .platform_data = &mini2440_audio_pins, + }, +}; + +/* + * I2C devices + */ +static struct at24_platform_data at24c08 = { + .byte_len = SZ_8K / 8, + .page_size = 16, +}; + +static struct i2c_board_info mini2440_i2c_devs[] __initdata = { + { + I2C_BOARD_INFO("24c08", 0x50), + .platform_data = &at24c08, + }, +}; + +static struct platform_device *mini2440_devices[] __initdata = { + &s3c_device_usb, + &s3c_device_wdt, +/* &s3c_device_adc,*/ /* ADC doesn't like living with touchscreen ! */ + &s3c_device_i2c0, + &s3c_device_rtc, + &s3c_device_usbgadget, + &mini2440_device_eth, + &mini2440_led1, + &mini2440_led2, + &mini2440_led3, + &mini2440_led4, + &mini2440_button_device, + &s3c_device_nand, + &s3c_device_sdi, + &s3c_device_iis, + &mini2440_audio, +/* &s3c_device_timer[0],*/ /* buzzer pwm, no API for it */ + /* remaining devices are optional */ +}; + +static void __init mini2440_map_io(void) +{ + s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); + + s3c_device_nand.dev.platform_data = &mini2440_nand_info; + s3c_device_sdi.dev.platform_data = &mini2440_mmc_cfg; +} + +/* + * mini2440_features string + * + * t = Touchscreen present + * b = backlight control + * c = camera [TODO] + * 0-9 LCD configuration + * + */ +static char mini2440_features_str[12] __initdata = "0tb"; + +static int __init mini2440_features_setup(char *str) +{ + if (str) + strlcpy(mini2440_features_str, str, sizeof(mini2440_features_str)); + return 1; +} + +__setup("mini2440=", mini2440_features_setup); + +#define FEATURE_SCREEN (1 << 0) +#define FEATURE_BACKLIGHT (1 << 1) +#define FEATURE_TOUCH (1 << 2) +#define FEATURE_CAMERA (1 << 3) + +struct mini2440_features_t { + int count; + int done; + int lcd_index; + struct platform_device *optional[8]; +}; + +static void mini2440_parse_features( + struct mini2440_features_t * features, + const char * features_str ) +{ + const char * fp = features_str; + + features->count = 0; + features->done = 0; + features->lcd_index = -1; + + while (*fp) { + char f = *fp++; + + switch (f) { + case '0'...'9': /* tft screen */ + if (features->done & FEATURE_SCREEN) { + printk(KERN_INFO "MINI2440: '%c' ignored, " + "screen type already set\n", f); + } else { + int li = f - '0'; + if (li >= ARRAY_SIZE(mini2440_lcd_cfg)) + printk(KERN_INFO "MINI2440: " + "'%c' out of range LCD mode\n", f); + else { + features->optional[features->count++] = + &s3c_device_lcd; + features->lcd_index = li; + } + } + features->done |= FEATURE_SCREEN; + break; + case 'b': + if (features->done & FEATURE_BACKLIGHT) + printk(KERN_INFO "MINI2440: '%c' ignored, " + "backlight already set\n", f); + else { + features->optional[features->count++] = + &mini2440_led_backlight; + } + features->done |= FEATURE_BACKLIGHT; + break; + case 't': + printk(KERN_INFO "MINI2440: '%c' ignored, " + "touchscreen not compiled in\n", f); + break; + case 'c': + if (features->done & FEATURE_CAMERA) + printk(KERN_INFO "MINI2440: '%c' ignored, " + "camera already registered\n", f); + else + features->optional[features->count++] = + &s3c_device_camif; + features->done |= FEATURE_CAMERA; + break; + } + } +} + +static void __init mini2440_init(void) +{ + struct mini2440_features_t features = { 0 }; + int i; + + printk(KERN_INFO "MINI2440: Option string mini2440=%s\n", + mini2440_features_str); + + /* Parse the feature string */ + mini2440_parse_features(&features, mini2440_features_str); + + /* turn LCD on */ + s3c2410_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND); + + /* Turn the backlight early on */ + s3c2410_gpio_setpin(S3C2410_GPG(4), 1); + s3c2410_gpio_cfgpin(S3C2410_GPG(4), S3C2410_GPIO_OUTPUT); + + /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */ + s3c2410_gpio_pullup(S3C2410_GPB(1), 0); + s3c2410_gpio_setpin(S3C2410_GPB(1), 0); + s3c2410_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT); + + /* Make sure the D+ pullup pin is output */ + s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT); + + /* mark the key as input, without pullups (there is one on the board) */ + for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) { + s3c2410_gpio_pullup(mini2440_buttons[i].gpio, 0); + s3c2410_gpio_cfgpin(mini2440_buttons[i].gpio, + S3C2410_GPIO_INPUT); + } + if (features.lcd_index != -1) { + int li; + + mini2440_fb_info.displays = + &mini2440_lcd_cfg[features.lcd_index]; + + printk(KERN_INFO "MINI2440: LCD"); + for (li = 0; li < ARRAY_SIZE(mini2440_lcd_cfg); li++) + if (li == features.lcd_index) + printk(" [%d:%dx%d]", li, + mini2440_lcd_cfg[li].width, + mini2440_lcd_cfg[li].height); + else + printk(" %d:%dx%d", li, + mini2440_lcd_cfg[li].width, + mini2440_lcd_cfg[li].height); + printk("\n"); + s3c24xx_fb_set_platdata(&mini2440_fb_info); + } + s3c24xx_udc_set_platdata(&mini2440_udc_cfg); + s3c_i2c0_set_platdata(NULL); + i2c_register_board_info(0, mini2440_i2c_devs, + ARRAY_SIZE(mini2440_i2c_devs)); + + platform_add_devices(mini2440_devices, ARRAY_SIZE(mini2440_devices)); + + if (features.count) /* the optional features */ + platform_add_devices(features.optional, features.count); + +} + + +MACHINE_START(MINI2440, "MINI2440") + /* Maintainer: Michel Pollet <buserror@gmail.com> */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + .map_io = mini2440_map_io, + .init_machine = mini2440_init, + .init_irq = s3c24xx_init_irq, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c2442/Kconfig b/arch/arm/mach-s3c2442/Kconfig index b289d19..103e913 100644 --- a/arch/arm/mach-s3c2442/Kconfig +++ b/arch/arm/mach-s3c2442/Kconfig @@ -24,6 +24,18 @@ config SMDK2440_CPU2442 depends on ARCH_S3C2440 select CPU_S3C2442 +config MACH_NEO1973_GTA02 + bool "Openmoko GTA02 / Freerunner phone" + select CPU_S3C2442 + select MFD_PCF50633 + select PCF50633_GPIO + select I2C + select POWER_SUPPLY + select MACH_NEO1973 + select S3C2410_PWM + help + Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone + endmenu diff --git a/arch/arm/mach-s3c2442/Makefile b/arch/arm/mach-s3c2442/Makefile index 2a909c6..2a19113 100644 --- a/arch/arm/mach-s3c2442/Makefile +++ b/arch/arm/mach-s3c2442/Makefile @@ -12,5 +12,7 @@ obj- := obj-$(CONFIG_CPU_S3C2442) += s3c2442.o obj-$(CONFIG_CPU_S3C2442) += clock.o +obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o + # Machine support diff --git a/arch/arm/mach-s3c2442/include/mach/gta02.h b/arch/arm/mach-s3c2442/include/mach/gta02.h new file mode 100644 index 0000000..953331d --- /dev/null +++ b/arch/arm/mach-s3c2442/include/mach/gta02.h @@ -0,0 +1,84 @@ +#ifndef _GTA02_H +#define _GTA02_H + +#include <mach/regs-gpio.h> + +/* Different hardware revisions, passed in ATAG_REVISION by u-boot */ +#define GTA02v1_SYSTEM_REV 0x00000310 +#define GTA02v2_SYSTEM_REV 0x00000320 +#define GTA02v3_SYSTEM_REV 0x00000330 +#define GTA02v4_SYSTEM_REV 0x00000340 +#define GTA02v5_SYSTEM_REV 0x00000350 +/* since A7 is basically same as A6, we use A6 PCB ID */ +#define GTA02v6_SYSTEM_REV 0x00000360 + +#define GTA02_GPIO_n3DL_GSM S3C2410_GPA(13) /* v1 + v2 + v3 only */ + +#define GTA02_GPIO_PWR_LED1 S3C2410_GPB(0) +#define GTA02_GPIO_PWR_LED2 S3C2410_GPB(1) +#define GTA02_GPIO_AUX_LED S3C2410_GPB(2) +#define GTA02_GPIO_VIBRATOR_ON S3C2410_GPB(3) +#define GTA02_GPIO_MODEM_RST S3C2410_GPB(5) +#define GTA02_GPIO_BT_EN S3C2410_GPB(6) +#define GTA02_GPIO_MODEM_ON S3C2410_GPB(7) +#define GTA02_GPIO_EXTINT8 S3C2410_GPB(8) +#define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9) + +#define GTA02_GPIO_PIO5 S3C2410_GPC(5) /* v3 + v4 only */ + +#define GTA02v3_GPIO_nG1_CS S3C2410_GPD(12) /* v3 + v4 only */ +#define GTA02v3_GPIO_nG2_CS S3C2410_GPD(13) /* v3 + v4 only */ +#define GTA02v5_GPIO_HDQ S3C2410_GPD(14) /* v5 + */ + +#define GTA02_GPIO_nG1_INT S3C2410_GPF(0) +#define GTA02_GPIO_IO1 S3C2410_GPF(1) +#define GTA02_GPIO_PIO_2 S3C2410_GPF(2) /* v2 + v3 + v4 only */ +#define GTA02_GPIO_JACK_INSERT S3C2410_GPF(4) +#define GTA02_GPIO_WLAN_GPIO1 S3C2410_GPF(5) /* v2 + v3 + v4 only */ +#define GTA02_GPIO_AUX_KEY S3C2410_GPF(6) +#define GTA02_GPIO_HOLD_KEY S3C2410_GPF(7) + +#define GTA02_GPIO_3D_IRQ S3C2410_GPG(4) +#define GTA02v2_GPIO_nG2_INT S3C2410_GPG(8) /* v2 + v3 + v4 only */ +#define GTA02v3_GPIO_nUSB_OC S3C2410_GPG(9) /* v3 + v4 only */ +#define GTA02v3_GPIO_nUSB_FLT S3C2410_GPG(10) /* v3 + v4 only */ +#define GTA02v3_GPIO_nGSM_OC S3C2410_GPG(11) /* v3 + v4 only */ + +#define GTA02_GPIO_AMP_SHUT S3C2440_GPJ1 /* v2 + v3 + v4 only */ +#define GTA02v1_GPIO_WLAN_GPIO10 S3C2440_GPJ2 +#define GTA02_GPIO_HP_IN S3C2440_GPJ2 /* v2 + v3 + v4 only */ +#define GTA02_GPIO_INT0 S3C2440_GPJ3 /* v2 + v3 + v4 only */ +#define GTA02_GPIO_nGSM_EN S3C2440_GPJ4 +#define GTA02_GPIO_3D_RESET S3C2440_GPJ5 +#define GTA02_GPIO_nDL_GSM S3C2440_GPJ6 /* v4 + v5 only */ +#define GTA02_GPIO_WLAN_GPIO0 S3C2440_GPJ7 +#define GTA02v1_GPIO_BAT_ID S3C2440_GPJ8 +#define GTA02_GPIO_KEEPACT S3C2440_GPJ8 +#define GTA02v1_GPIO_HP_IN S3C2440_GPJ10 +#define GTA02_CHIP_PWD S3C2440_GPJ11 /* v2 + v3 + v4 only */ +#define GTA02_GPIO_nWLAN_RESET S3C2440_GPJ12 /* v2 + v3 + v4 only */ + +#define GTA02_IRQ_GSENSOR_1 IRQ_EINT0 +#define GTA02_IRQ_MODEM IRQ_EINT1 +#define GTA02_IRQ_PIO_2 IRQ_EINT2 /* v2 + v3 + v4 only */ +#define GTA02_IRQ_nJACK_INSERT IRQ_EINT4 +#define GTA02_IRQ_WLAN_GPIO1 IRQ_EINT5 +#define GTA02_IRQ_AUX IRQ_EINT6 +#define GTA02_IRQ_nHOLD IRQ_EINT7 +#define GTA02_IRQ_PCF50633 IRQ_EINT9 +#define GTA02_IRQ_3D IRQ_EINT12 +#define GTA02_IRQ_GSENSOR_2 IRQ_EINT16 /* v2 + v3 + v4 only */ +#define GTA02v3_IRQ_nUSB_OC IRQ_EINT17 /* v3 + v4 only */ +#define GTA02v3_IRQ_nUSB_FLT IRQ_EINT18 /* v3 + v4 only */ +#define GTA02v3_IRQ_nGSM_OC IRQ_EINT19 /* v3 + v4 only */ + +/* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */ +#define GTA02_PCB_ID1_0 S3C2410_GPC(13) +#define GTA02_PCB_ID1_1 S3C2410_GPC(15) +#define GTA02_PCB_ID1_2 S3C2410_GPD(0) +#define GTA02_PCB_ID2_0 S3C2410_GPD(3) +#define GTA02_PCB_ID2_1 S3C2410_GPD(4) + +int gta02_get_pcb_revision(void); + +#endif /* _GTA02_H */ diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c new file mode 100644 index 0000000..e23b581 --- /dev/null +++ b/arch/arm/mach-s3c2442/mach-gta02.c @@ -0,0 +1,646 @@ +/* + * linux/arch/arm/mach-s3c2442/mach-gta02.c + * + * S3C2442 Machine Support for Openmoko GTA02 / FreeRunner. + * + * Copyright (C) 2006-2009 by Openmoko, Inc. + * Authors: Harald Welte <laforge@openmoko.org> + * Andy Green <andy@openmoko.org> + * Werner Almesberger <werner@openmoko.org> + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/delay.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/workqueue.h> +#include <linux/platform_device.h> +#include <linux/serial_core.h> +#include <linux/spi/spi.h> + +#include <linux/mmc/host.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/io.h> + +#include <linux/i2c.h> +#include <linux/backlight.h> +#include <linux/regulator/machine.h> + +#include <linux/mfd/pcf50633/core.h> +#include <linux/mfd/pcf50633/mbc.h> +#include <linux/mfd/pcf50633/adc.h> +#include <linux/mfd/pcf50633/gpio.h> +#include <linux/mfd/pcf50633/pmic.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <asm/irq.h> +#include <asm/mach-types.h> + +#include <mach/regs-irq.h> +#include <mach/regs-gpio.h> +#include <mach/regs-gpioj.h> +#include <mach/fb.h> + +#include <mach/spi.h> +#include <mach/spi-gpio.h> +#include <plat/usb-control.h> +#include <mach/regs-mem.h> +#include <mach/hardware.h> + +#include <mach/gta02.h> + +#include <plat/regs-serial.h> +#include <plat/nand.h> +#include <plat/devs.h> +#include <plat/cpu.h> +#include <plat/pm.h> +#include <plat/udc.h> +#include <plat/gpio-cfg.h> +#include <plat/iic.h> + +static struct pcf50633 *gta02_pcf; + +/* + * This gets called every 1ms when we paniced. + */ + +static long gta02_panic_blink(long count) +{ + long delay = 0; + static long last_blink; + static char led; + + /* Fast blink: 200ms period. */ + if (count - last_blink < 100) + return 0; + + led ^= 1; + gpio_direction_output(GTA02_GPIO_AUX_LED, led); + + last_blink = count; + + return delay; +} + + +static struct map_desc gta02_iodesc[] __initdata = { + { + .virtual = 0xe0000000, + .pfn = __phys_to_pfn(S3C2410_CS3 + 0x01000000), + .length = SZ_1M, + .type = MT_DEVICE + }, +}; + +#define UCON (S3C2410_UCON_DEFAULT | S3C2443_UCON_RXERR_IRQEN) +#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) +#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) + +static struct s3c2410_uartcfg gta02_uartcfgs[] = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, +}; + +#ifdef CONFIG_CHARGER_PCF50633 +/* + * On GTA02 the 1A charger features a 48K resistor to 0V on the ID pin. + * We use this to recognize that we can pull 1A from the USB socket. + * + * These constants are the measured pcf50633 ADC levels with the 1A + * charger / 48K resistor, and with no pulldown resistor. + */ + +#define ADC_NOM_CHG_DETECT_1A 6 +#define ADC_NOM_CHG_DETECT_USB 43 + +static void +gta02_configure_pmu_for_charger(struct pcf50633 *pcf, void *unused, int res) +{ + int ma; + + /* Interpret charger type */ + if (res < ((ADC_NOM_CHG_DETECT_USB + ADC_NOM_CHG_DETECT_1A) / 2)) { + + /* + * Sanity - stop GPO driving out now that we have a 1A charger + * GPO controls USB Host power generation on GTA02 + */ + pcf50633_gpio_set(pcf, PCF50633_GPO, 0); + + ma = 1000; + } else + ma = 100; + + pcf50633_mbc_usb_curlim_set(pcf, ma); +} + +static struct delayed_work gta02_charger_work; +static int gta02_usb_vbus_draw; + +static void gta02_charger_worker(struct work_struct *work) +{ + if (gta02_usb_vbus_draw) { + pcf50633_mbc_usb_curlim_set(gta02_pcf, gta02_usb_vbus_draw); + return; + } + +#ifdef CONFIG_PCF50633_ADC + pcf50633_adc_async_read(gta02_pcf, + PCF50633_ADCC1_MUX_ADCIN1, + PCF50633_ADCC1_AVERAGE_16, + gta02_configure_pmu_for_charger, + NULL); +#else + /* + * If the PCF50633 ADC is disabled we fallback to a + * 100mA limit for safety. + */ + pcf50633_mbc_usb_curlim_set(pcf, 100); +#endif +} + +#define GTA02_CHARGER_CONFIGURE_TIMEOUT ((3000 * HZ) / 1000) + +static void gta02_pmu_event_callback(struct pcf50633 *pcf, int irq) +{ + if (irq == PCF50633_IRQ_USBINS) { + schedule_delayed_work(>a02_charger_work, + GTA02_CHARGER_CONFIGURE_TIMEOUT); + + return; + } + + if (irq == PCF50633_IRQ_USBREM) { + cancel_delayed_work_sync(>a02_charger_work); + gta02_usb_vbus_draw = 0; + } +} + +static void gta02_udc_vbus_draw(unsigned int ma) +{ + if (!gta02_pcf) + return; + + gta02_usb_vbus_draw = ma; + + schedule_delayed_work(>a02_charger_work, + GTA02_CHARGER_CONFIGURE_TIMEOUT); +} +#else /* !CONFIG_CHARGER_PCF50633 */ +#define gta02_pmu_event_callback NULL +#define gta02_udc_vbus_draw NULL +#endif + +/* + * This is called when pc50633 is probed, unfortunately quite late in the + * day since it is an I2C bus device. Here we can belatedly define some + * platform devices with the advantage that we can mark the pcf50633 as the + * parent. This makes them get suspended and resumed with their parent + * the pcf50633 still around. + */ + +static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf); + + +static char *gta02_batteries[] = { + "battery", +}; + +struct pcf50633_platform_data gta02_pcf_pdata = { + .resumers = { + [0] = PCF50633_INT1_USBINS | + PCF50633_INT1_USBREM | + PCF50633_INT1_ALARM, + [1] = PCF50633_INT2_ONKEYF, + [2] = PCF50633_INT3_ONKEY1S, + [3] = PCF50633_INT4_LOWSYS | + PCF50633_INT4_LOWBAT | + PCF50633_INT4_HIGHTMP, + }, + + .batteries = gta02_batteries, + .num_batteries = ARRAY_SIZE(gta02_batteries), + .reg_init_data = { + [PCF50633_REGULATOR_AUTO] = { + .constraints = { + .min_uV = 3300000, + .max_uV = 3300000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .always_on = 1, + .apply_uV = 1, + .state_mem = { + .enabled = 1, + }, + }, + }, + [PCF50633_REGULATOR_DOWN1] = { + .constraints = { + .min_uV = 1300000, + .max_uV = 1600000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .always_on = 1, + .apply_uV = 1, + }, + }, + [PCF50633_REGULATOR_DOWN2] = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .enabled = 1, + }, + }, + }, + [PCF50633_REGULATOR_HCLDO] = { + .constraints = { + .min_uV = 2000000, + .max_uV = 3300000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + }, + }, + [PCF50633_REGULATOR_LDO1] = { + .constraints = { + .min_uV = 3300000, + .max_uV = 3300000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .apply_uV = 1, + .state_mem = { + .enabled = 0, + }, + }, + }, + [PCF50633_REGULATOR_LDO2] = { + .constraints = { + .min_uV = 3300000, + .max_uV = 3300000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .apply_uV = 1, + }, + }, + [PCF50633_REGULATOR_LDO3] = { + .constraints = { + .min_uV = 3000000, + .max_uV = 3000000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .apply_uV = 1, + }, + }, + [PCF50633_REGULATOR_LDO4] = { + .constraints = { + .min_uV = 3200000, + .max_uV = 3200000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .apply_uV = 1, + }, + }, + [PCF50633_REGULATOR_LDO5] = { + .constraints = { + .min_uV = 3000000, + .max_uV = 3000000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .apply_uV = 1, + .state_mem = { + .enabled = 1, + }, + }, + }, + [PCF50633_REGULATOR_LDO6] = { + .constraints = { + .min_uV = 3000000, + .max_uV = 3000000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + }, + }, + [PCF50633_REGULATOR_MEMLDO] = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .state_mem = { + .enabled = 1, + }, + }, + }, + + }, + .probe_done = gta02_pmu_attach_child_devices, + .mbc_event_callback = gta02_pmu_event_callback, +}; + + +/* NOR Flash. */ + +#define GTA02_FLASH_BASE 0x18000000 /* GCS3 */ +#define GTA02_FLASH_SIZE 0x200000 /* 2MBytes */ + +static struct physmap_flash_data gta02_nor_flash_data = { + .width = 2, +}; + +static struct resource gta02_nor_flash_resource = { + .start = GTA02_FLASH_BASE, + .end = GTA02_FLASH_BASE + GTA02_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device gta02_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = >a02_nor_flash_data, + }, + .resource = >a02_nor_flash_resource, + .num_resources = 1, +}; + + +struct platform_device s3c24xx_pwm_device = { + .name = "s3c24xx_pwm", + .num_resources = 0, +}; + +static struct i2c_board_info gta02_i2c_devs[] __initdata = { + { + I2C_BOARD_INFO("pcf50633", 0x73), + .irq = GTA02_IRQ_PCF50633, + .platform_data = >a02_pcf_pdata, + }, + { + I2C_BOARD_INFO("wm8753", 0x1a), + }, +}; + +static struct s3c2410_nand_set gta02_nand_sets[] = { + [0] = { + /* + * This name is also hard-coded in the boot loaders, so + * changing it would would require all users to upgrade + * their boot loaders, some of which are stored in a NOR + * that is considered to be immutable. + */ + .name = "neo1973-nand", + .nr_chips = 1, + .use_bbt = 1, + .force_soft_ecc = 1, + }, +}; + +/* + * Choose a set of timings derived from S3C@2442B MCP54 + * data sheet (K5D2G13ACM-D075 MCP Memory). + */ + +static struct s3c2410_platform_nand gta02_nand_info = { + .tacls = 0, + .twrph0 = 25, + .twrph1 = 15, + .nr_sets = ARRAY_SIZE(gta02_nand_sets), + .sets = gta02_nand_sets, +}; + + +static void gta02_udc_command(enum s3c2410_udc_cmd_e cmd) +{ + switch (cmd) { + case S3C2410_UDC_P_ENABLE: + pr_debug("%s S3C2410_UDC_P_ENABLE\n", __func__); + gpio_direction_output(GTA02_GPIO_USB_PULLUP, 1); + break; + case S3C2410_UDC_P_DISABLE: + pr_debug("%s S3C2410_UDC_P_DISABLE\n", __func__); + gpio_direction_output(GTA02_GPIO_USB_PULLUP, 0); + break; + case S3C2410_UDC_P_RESET: + pr_debug("%s S3C2410_UDC_P_RESET\n", __func__); + /* FIXME: Do something here. */ + } +} + +/* Get PMU to set USB current limit accordingly. */ +static struct s3c2410_udc_mach_info gta02_udc_cfg = { + .vbus_draw = gta02_udc_vbus_draw, + .udc_command = gta02_udc_command, + +}; + + + +static void gta02_bl_set_intensity(int intensity) +{ + struct pcf50633 *pcf = gta02_pcf; + int old_intensity = pcf50633_reg_read(pcf, PCF50633_REG_LEDOUT); + + /* We map 8-bit intensity to 6-bit intensity in hardware. */ + intensity >>= 2; + + /* + * This can happen during, eg, print of panic on blanked console, + * but we can't service i2c without interrupts active, so abort. + */ + if (in_atomic()) { + printk(KERN_ERR "gta02_bl_set_intensity called while atomic\n"); + return; + } + + old_intensity = pcf50633_reg_read(pcf, PCF50633_REG_LEDOUT); + if (intensity == old_intensity) + return; + + /* We can't do this anywhere else. */ + pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 5); + + if (!(pcf50633_reg_read(pcf, PCF50633_REG_LEDENA) & 3)) + old_intensity = 0; + + /* + * The PCF50633 cannot handle LEDOUT = 0 (datasheet p60) + * if seen, you have to re-enable the LED unit. + */ + if (!intensity || !old_intensity) + pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0); + + /* Illegal to set LEDOUT to 0. */ + if (!intensity) + pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f, 2); + else + pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f, + intensity); + + if (intensity) + pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 2); + +} + +static struct generic_bl_info gta02_bl_info = { + .name = "gta02-bl", + .max_intensity = 0xff, + .default_intensity = 0xff, + .set_bl_intensity = gta02_bl_set_intensity, +}; + +static struct platform_device gta02_bl_dev = { + .name = "generic-bl", + .id = 1, + .dev = { + .platform_data = >a02_bl_info, + }, +}; + + + +/* USB */ +static struct s3c2410_hcd_info gta02_usb_info = { + .port[0] = { + .flags = S3C_HCDFLG_USED, + }, + .port[1] = { + .flags = 0, + }, +}; + + +static void __init gta02_map_io(void) +{ + s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc)); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs)); +} + + +/* These are the guys that don't need to be children of PMU. */ + +static struct platform_device *gta02_devices[] __initdata = { + &s3c_device_usb, + &s3c_device_wdt, + &s3c_device_sdi, + &s3c_device_usbgadget, + &s3c_device_nand, + >a02_nor_flash, + &s3c24xx_pwm_device, + &s3c_device_iis, + &s3c_device_i2c0, +}; + +/* These guys DO need to be children of PMU. */ + +static struct platform_device *gta02_devices_pmu_children[] = { + >a02_bl_dev, +}; + + +/* + * This is called when pc50633 is probed, quite late in the day since it is an + * I2C bus device. Here we can define platform devices with the advantage that + * we can mark the pcf50633 as the parent. This makes them get suspended and + * resumed with their parent the pcf50633 still around. All devices whose + * operation depends on something from pcf50633 must have this relationship + * made explicit like this, or suspend and resume will become an unreliable + * hellworld. + */ + +static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf) +{ + int n; + + /* Grab a copy of the now probed PMU pointer. */ + gta02_pcf = pcf; + + for (n = 0; n < ARRAY_SIZE(gta02_devices_pmu_children); n++) + gta02_devices_pmu_children[n]->dev.parent = pcf->dev; + + platform_add_devices(gta02_devices_pmu_children, + ARRAY_SIZE(gta02_devices_pmu_children)); +} + +static void gta02_poweroff(void) +{ + pcf50633_reg_set_bit_mask(gta02_pcf, PCF50633_REG_OOCSHDWN, 1, 1); +} + +static void __init gta02_machine_init(void) +{ + /* Set the panic callback to make AUX LED blink at ~5Hz. */ + panic_blink = gta02_panic_blink; + + s3c_pm_init(); + +#ifdef CONFIG_CHARGER_PCF50633 + INIT_DELAYED_WORK(>a02_charger_work, gta02_charger_worker); +#endif + + s3c_device_usb.dev.platform_data = >a02_usb_info; + s3c_device_nand.dev.platform_data = >a02_nand_info; + + s3c24xx_udc_set_platdata(>a02_udc_cfg); + s3c_i2c0_set_platdata(NULL); + + i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs)); + + platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices)); + pm_power_off = gta02_poweroff; +} + + +MACHINE_START(NEO1973_GTA02, "GTA02") + /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + .map_io = gta02_map_io, + .init_irq = s3c24xx_init_irq, + .init_machine = gta02_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 3a398be..03cd27d 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -62,6 +62,12 @@ #define SHIFT_ASR 0x40 #define SHIFT_RORRRX 0x60 +#define BAD_INSTR 0xdeadc0de + +/* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */ +#define IS_T32(hi16) \ + (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800)) + static unsigned long ai_user; static unsigned long ai_sys; static unsigned long ai_skipped; @@ -332,38 +338,48 @@ do_alignment_ldrdstrd(unsigned long addr, unsigned long instr, struct pt_regs *regs) { unsigned int rd = RD_BITS(instr); - - if (((rd & 1) == 1) || (rd == 14)) + unsigned int rd2; + int load; + + if ((instr & 0xfe000000) == 0xe8000000) { + /* ARMv7 Thumb-2 32-bit LDRD/STRD */ + rd2 = (instr >> 8) & 0xf; + load = !!(LDST_L_BIT(instr)); + } else if (((rd & 1) == 1) || (rd == 14)) goto bad; + else { + load = ((instr & 0xf0) == 0xd0); + rd2 = rd + 1; + } ai_dword += 1; if (user_mode(regs)) goto user; - if ((instr & 0xf0) == 0xd0) { + if (load) { unsigned long val; get32_unaligned_check(val, addr); regs->uregs[rd] = val; get32_unaligned_check(val, addr + 4); - regs->uregs[rd + 1] = val; + regs->uregs[rd2] = val; } else { put32_unaligned_check(regs->uregs[rd], addr); - put32_unaligned_check(regs->uregs[rd + 1], addr + 4); + put32_unaligned_check(regs->uregs[rd2], addr + 4); } return TYPE_LDST; user: - if ((instr & 0xf0) == 0xd0) { + if (load) { unsigned long val; get32t_unaligned_check(val, addr); regs->uregs[rd] = val; get32t_unaligned_check(val, addr + 4); - regs->uregs[rd + 1] = val; + regs->uregs[rd2] = val; } else { put32t_unaligned_check(regs->uregs[rd], addr); - put32t_unaligned_check(regs->uregs[rd + 1], addr + 4); + put32t_unaligned_check(regs->uregs[rd2], addr + 4); } return TYPE_LDST; @@ -616,8 +632,72 @@ thumb2arm(u16 tinstr) /* Else fall through for illegal instruction case */ default: - return 0xdeadc0de; + return BAD_INSTR; + } +} + +/* + * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction + * handlable by ARM alignment handler, also find the corresponding handler, + * so that we can reuse ARM userland alignment fault fixups for Thumb. + * + * @pinstr: original Thumb-2 instruction; returns new handlable instruction + * @regs: register context. + * @poffset: return offset from faulted addr for later writeback + * + * NOTES: + * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections. + * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt) + */ +static void * +do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs, + union offset_union *poffset) +{ + unsigned long instr = *pinstr; + u16 tinst1 = (instr >> 16) & 0xffff; + u16 tinst2 = instr & 0xffff; + poffset->un = 0; + + switch (tinst1 & 0xffe0) { + /* A6.3.5 Load/Store multiple */ + case 0xe880: /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */ + case 0xe8a0: /* ...above writeback version */ + case 0xe900: /* STMDB/STMFD, LDMDB/LDMEA */ + case 0xe920: /* ...above writeback version */ + /* no need offset decision since handler calculates it */ + return do_alignment_ldmstm; + + case 0xf840: /* POP/PUSH T3 (single register) */ + if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) { + u32 L = !!(LDST_L_BIT(instr)); + const u32 subset[2] = { + 0xe92d0000, /* STMDB sp!,{registers} */ + 0xe8bd0000, /* LDMIA sp!,{registers} */ + }; + *pinstr = subset[L] | (1<<RD_BITS(instr)); + return do_alignment_ldmstm; + } + /* Else fall through for illegal instruction case */ + break; + + /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */ + case 0xe860: + case 0xe960: + case 0xe8e0: + case 0xe9e0: + poffset->un = (tinst2 & 0xff) << 2; + case 0xe940: + case 0xe9c0: + return do_alignment_ldrdstrd; + + /* + * No need to handle load/store instructions up to word size + * since ARMv6 and later CPUs can perform unaligned accesses. + */ + default: + break; } + return NULL; } static int @@ -630,6 +710,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) mm_segment_t fs; unsigned int fault; u16 tinstr = 0; + int isize = 4; + int thumb2_32b = 0; instrptr = instruction_pointer(regs); @@ -637,8 +719,19 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) set_fs(KERNEL_DS); if (thumb_mode(regs)) { fault = __get_user(tinstr, (u16 *)(instrptr & ~1)); - if (!(fault)) - instr = thumb2arm(tinstr); + if (!fault) { + if (cpu_architecture() >= CPU_ARCH_ARMv7 && + IS_T32(tinstr)) { + /* Thumb-2 32-bit */ + u16 tinst2 = 0; + fault = __get_user(tinst2, (u16 *)(instrptr+2)); + instr = (tinstr << 16) | tinst2; + thumb2_32b = 1; + } else { + isize = 2; + instr = thumb2arm(tinstr); + } + } } else fault = __get_user(instr, (u32 *)instrptr); set_fs(fs); @@ -655,7 +748,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) fixup: - regs->ARM_pc += thumb_mode(regs) ? 2 : 4; + regs->ARM_pc += isize; switch (CODING_BITS(instr)) { case 0x00000000: /* 3.13.4 load/store instruction extensions */ @@ -714,18 +807,25 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) handler = do_alignment_ldrstr; break; - case 0x08000000: /* ldm or stm */ - handler = do_alignment_ldmstm; + case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */ + if (thumb2_32b) + handler = do_alignment_t32_to_handler(&instr, regs, &offset); + else + handler = do_alignment_ldmstm; break; default: goto bad; } + if (!handler) + goto bad; type = handler(addr, instr, regs); - if (type == TYPE_ERROR || type == TYPE_FAULT) + if (type == TYPE_ERROR || type == TYPE_FAULT) { + regs->ARM_pc -= isize; goto bad_or_fault; + } if (type == TYPE_LDST) do_alignment_finish_ldst(addr, instr, regs, offset); @@ -735,7 +835,6 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) bad_or_fault: if (type == TYPE_ERROR) goto bad; - regs->ARM_pc -= thumb_mode(regs) ? 2 : 4; /* * We got a fault - fix it up, or die. */ @@ -751,8 +850,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) */ printk(KERN_ERR "Alignment trap: not handling instruction " "%0*lx at [<%08lx>]\n", - thumb_mode(regs) ? 4 : 8, - thumb_mode(regs) ? tinstr : instr, instrptr); + isize << 1, + isize == 2 ? tinstr : instr, instrptr); ai_skipped += 1; return 1; @@ -763,8 +862,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx " "Address=0x%08lx FSR 0x%03x\n", current->comm, task_pid_nr(current), instrptr, - thumb_mode(regs) ? 4 : 8, - thumb_mode(regs) ? tinstr : instr, + isize << 1, + isize == 2 ? tinstr : instr, addr, fsr); if (ai_usermode & UM_FIXUP) diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 0455557..6fdcbb7 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -208,7 +208,7 @@ good_area: * than endlessly redo the fault. */ survive: - fault = handle_mm_fault(mm, vma, addr & PAGE_MASK, fsr & (1 << 11)); + fault = handle_mm_fault(mm, vma, addr & PAGE_MASK, (fsr & (1 << 11)) ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index fdaa9bb..4722582 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -836,6 +836,13 @@ void __init reserve_node_zero(pg_data_t *pgdat) BOOTMEM_EXCLUSIVE); } + if (machine_is_treo680()) { + reserve_bootmem_node(pgdat, 0xa0000000, 0x1000, + BOOTMEM_EXCLUSIVE); + reserve_bootmem_node(pgdat, 0xa2000000, 0x1000, + BOOTMEM_EXCLUSIVE); + } + if (machine_is_palmt5()) reserve_bootmem_node(pgdat, 0xa0200000, 0x1000, BOOTMEM_EXCLUSIVE); diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h index dca7c16..4d53cc5 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/mach/sram.h @@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll); + u32 unlock_dll, u32 f, u32 sdrc_mr, + u32 inc); /* Do not use these */ extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); @@ -62,7 +63,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll); + u32 unlock_dll, u32 f, u32 sdrc_mr, + u32 inc); extern unsigned long omap3_sram_configure_core_dpll_sz; #endif diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index a5b9bcd..65006df 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -371,15 +371,17 @@ static inline int omap243x_sram_init(void) static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, - u32 m2, u32 unlock_dll); + u32 m2, u32 unlock_dll, + u32 f, u32 sdrc_mr, u32 inc); u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, - u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll) + u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, + u32 f, u32 sdrc_mr, u32 inc) { BUG_ON(!_omap3_sram_configure_core_dpll); return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, sdrc_actim_ctrla, sdrc_actim_ctrlb, m2, - unlock_dll); + unlock_dll, f, sdrc_mr, inc); } /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 6106514..74bb7cb 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o obj-y += dev-i2c0.o obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o +obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o diff --git a/arch/arm/plat-s3c/dev-audio.c b/arch/arm/plat-s3c/dev-audio.c new file mode 100644 index 0000000..1322beb --- /dev/null +++ b/arch/arm/plat-s3c/dev-audio.c @@ -0,0 +1,68 @@ +/* linux/arch/arm/plat-s3c/dev-audio.c + * + * Copyright 2009 Wolfson Microelectronics + * Mark Brown <broonie@opensource.wolfsonmicro.com> + * + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/map.h> + +#include <plat/devs.h> + + +static struct resource s3c64xx_iis0_resource[] = { + [0] = { + .start = S3C64XX_PA_IIS0, + .end = S3C64XX_PA_IIS0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device s3c64xx_device_iis0 = { + .name = "s3c64xx-iis", + .id = 0, + .num_resources = ARRAY_SIZE(s3c64xx_iis0_resource), + .resource = s3c64xx_iis0_resource, +}; +EXPORT_SYMBOL(s3c64xx_device_iis0); + +static struct resource s3c64xx_iis1_resource[] = { + [0] = { + .start = S3C64XX_PA_IIS1, + .end = S3C64XX_PA_IIS1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device s3c64xx_device_iis1 = { + .name = "s3c64xx-iis", + .id = 1, + .num_resources = ARRAY_SIZE(s3c64xx_iis1_resource), + .resource = s3c64xx_iis1_resource, +}; +EXPORT_SYMBOL(s3c64xx_device_iis1); + +static struct resource s3c64xx_iisv4_resource[] = { + [0] = { + .start = S3C64XX_PA_IISV4, + .end = S3C64XX_PA_IISV4 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device s3c64xx_device_iisv4 = { + .name = "s3c64xx-iis-v4", + .id = -1, + .num_resources = ARRAY_SIZE(s3c64xx_iisv4_resource), + .resource = s3c64xx_iisv4_resource, +}; +EXPORT_SYMBOL(s3c64xx_device_iisv4); diff --git a/arch/arm/plat-s3c/gpio-config.c b/arch/arm/plat-s3c/gpio-config.c index 08044de..456969b 100644 --- a/arch/arm/plat-s3c/gpio-config.c +++ b/arch/arm/plat-s3c/gpio-config.c @@ -119,7 +119,7 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, unsigned int shift = (off & 7) * 4; u32 con; - if (off < 8 && chip->chip.ngpio >= 8) + if (off < 8 && chip->chip.ngpio > 8) reg -= 4; if (s3c_gpio_is_cfg_special(cfg)) { diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index a0b6768..b5b9c4d 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -24,13 +24,16 @@ extern struct platform_device *s3c24xx_uart_src[]; extern struct platform_device s3c_device_timer[]; +extern struct platform_device s3c64xx_device_iis0; +extern struct platform_device s3c64xx_device_iis1; +extern struct platform_device s3c64xx_device_iisv4; + extern struct platform_device s3c_device_fb; extern struct platform_device s3c_device_usb; extern struct platform_device s3c_device_lcd; extern struct platform_device s3c_device_wdt; extern struct platform_device s3c_device_i2c0; extern struct platform_device s3c_device_i2c1; -extern struct platform_device s3c_device_iis; extern struct platform_device s3c_device_rtc; extern struct platform_device s3c_device_adc; extern struct platform_device s3c_device_sdi; diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h index f4dcd14..18f9588 100644 --- a/arch/arm/plat-s3c/include/plat/nand.h +++ b/arch/arm/plat-s3c/include/plat/nand.h @@ -10,19 +10,26 @@ * published by the Free Software Foundation. */ -/* struct s3c2410_nand_set +/** + * struct s3c2410_nand_set - define a set of one or more nand chips + * @disable_ecc: Entirely disable ECC - Dangerous + * @flash_bbt: Openmoko u-boot can create a Bad Block Table + * Setting this flag will allow the kernel to + * look for it at boot time and also skip the NAND + * scan. + * @nr_chips: Number of chips in this set + * @nr_partitions: Number of partitions pointed to by @partitions + * @name: Name of set (optional) + * @nr_map: Map for low-layer logical to physical chip numbers (option) + * @partitions: The mtd partition list * - * define an set of one or more nand chips registered with an unique mtd - * - * nr_chips = number of chips in this set - * nr_partitions = number of partitions pointed to be partitoons (or zero) - * name = name of set (optional) - * nr_map = map for low-layer logical to physical chip numbers (option) - * partitions = mtd partition list -*/ - + * define a set of one or more nand chips registered with an unique mtd. Also + * allows to pass flag to the underlying NAND layer. 'disable_ecc' will trigger + * a warning at boot time. + */ struct s3c2410_nand_set { - unsigned int disable_ecc : 1; + unsigned int disable_ecc:1; + unsigned int flash_bbt:1; int nr_chips; int nr_partitions; @@ -39,7 +46,7 @@ struct s3c2410_platform_nand { int twrph0; /* active time for nWE/nOE */ int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */ - unsigned int ignore_unset_ecc : 1; + unsigned int ignore_unset_ecc:1; int nr_sets; struct s3c2410_nand_set *sets; diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index 2ed5df3..3c8882c 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -23,6 +23,7 @@ obj-y += gpiolib.o obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o +obj-$(CONFIG_CPU_FREQ_S3C64XX) += cpufreq.o # PM support diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c index 0bc2fa1..7a36e89 100644 --- a/arch/arm/plat-s3c64xx/clock.c +++ b/arch/arm/plat-s3c64xx/clock.c @@ -191,7 +191,7 @@ static struct clk init_clocks[] = { .id = -1, .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_UHOST, + .ctrlbit = S3C_CLKCON_HCLK_UHOST, }, { .name = "hsmmc", .id = 0, diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c new file mode 100644 index 0000000..e6e0843 --- /dev/null +++ b/arch/arm/plat-s3c64xx/cpufreq.c @@ -0,0 +1,262 @@ +/* linux/arch/arm/plat-s3c64xx/cpufreq.c + * + * Copyright 2009 Wolfson Microelectronics plc + * + * S3C64xx CPUfreq Support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/cpufreq.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/regulator/consumer.h> + +static struct clk *armclk; +static struct regulator *vddarm; + +#ifdef CONFIG_CPU_S3C6410 +struct s3c64xx_dvfs { + unsigned int vddarm_min; + unsigned int vddarm_max; +}; + +static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { + [0] = { 1000000, 1000000 }, + [1] = { 1000000, 1050000 }, + [2] = { 1050000, 1100000 }, + [3] = { 1050000, 1150000 }, + [4] = { 1250000, 1350000 }, +}; + +static struct cpufreq_frequency_table s3c64xx_freq_table[] = { + { 0, 66000 }, + { 0, 133000 }, + { 1, 222000 }, + { 1, 266000 }, + { 2, 333000 }, + { 2, 400000 }, + { 3, 532000 }, + { 3, 533000 }, + { 4, 667000 }, + { 0, CPUFREQ_TABLE_END }, +}; +#endif + +static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -EINVAL; + + return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table); +} + +static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu) +{ + if (cpu != 0) + return 0; + + return clk_get_rate(armclk) / 1000; +} + +static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + int ret; + unsigned int i; + struct cpufreq_freqs freqs; + struct s3c64xx_dvfs *dvfs; + + ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table, + target_freq, relation, &i); + if (ret != 0) + return ret; + + freqs.cpu = 0; + freqs.old = clk_get_rate(armclk) / 1000; + freqs.new = s3c64xx_freq_table[i].frequency; + freqs.flags = 0; + dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index]; + + if (freqs.old == freqs.new) + return 0; + + pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new); + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + +#ifdef CONFIG_REGULATOR + if (vddarm && freqs.new > freqs.old) { + ret = regulator_set_voltage(vddarm, + dvfs->vddarm_min, + dvfs->vddarm_max); + if (ret != 0) { + pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n", + freqs.new, ret); + goto err; + } + } +#endif + + ret = clk_set_rate(armclk, freqs.new * 1000); + if (ret < 0) { + pr_err("cpufreq: Failed to set rate %dkHz: %d\n", + freqs.new, ret); + goto err; + } + +#ifdef CONFIG_REGULATOR + if (vddarm && freqs.new < freqs.old) { + ret = regulator_set_voltage(vddarm, + dvfs->vddarm_min, + dvfs->vddarm_max); + if (ret != 0) { + pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n", + freqs.new, ret); + goto err_clk; + } + } +#endif + + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + pr_debug("cpufreq: Set actual frequency %lukHz\n", + clk_get_rate(armclk) / 1000); + + return 0; + +err_clk: + if (clk_set_rate(armclk, freqs.old * 1000) < 0) + pr_err("Failed to restore original clock rate\n"); +err: + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return ret; +} + +#ifdef CONFIG_REGULATOR +static void __init s3c64xx_cpufreq_constrain_voltages(void) +{ + int count, v, i, found; + struct cpufreq_frequency_table *freq; + struct s3c64xx_dvfs *dvfs; + + count = regulator_count_voltages(vddarm); + if (count < 0) { + pr_err("cpufreq: Unable to check supported voltages\n"); + return; + } + + freq = s3c64xx_freq_table; + while (freq->frequency != CPUFREQ_TABLE_END) { + if (freq->frequency == CPUFREQ_ENTRY_INVALID) + continue; + + dvfs = &s3c64xx_dvfs_table[freq->index]; + found = 0; + + for (i = 0; i < count; i++) { + v = regulator_list_voltage(vddarm, i); + if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max) + found = 1; + } + + if (!found) { + pr_debug("cpufreq: %dkHz unsupported by regulator\n", + freq->frequency); + freq->frequency = CPUFREQ_ENTRY_INVALID; + } + + freq++; + } +} +#endif + +static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) +{ + int ret; + struct cpufreq_frequency_table *freq; + + if (policy->cpu != 0) + return -EINVAL; + + if (s3c64xx_freq_table == NULL) { + pr_err("cpufreq: No frequency information for this CPU\n"); + return -ENODEV; + } + + armclk = clk_get(NULL, "armclk"); + if (IS_ERR(armclk)) { + pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n", + PTR_ERR(armclk)); + return PTR_ERR(armclk); + } + +#ifdef CONFIG_REGULATOR + vddarm = regulator_get(NULL, "vddarm"); + if (IS_ERR(vddarm)) { + ret = PTR_ERR(vddarm); + pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret); + pr_err("cpufreq: Only frequency scaling available\n"); + vddarm = NULL; + } else { + s3c64xx_cpufreq_constrain_voltages(); + } +#endif + + freq = s3c64xx_freq_table; + while (freq->frequency != CPUFREQ_TABLE_END) { + unsigned long r; + + /* Check for frequencies we can generate */ + r = clk_round_rate(armclk, freq->frequency * 1000); + r /= 1000; + if (r != freq->frequency) + freq->frequency = CPUFREQ_ENTRY_INVALID; + + /* If we have no regulator then assume startup + * frequency is the maximum we can support. */ + if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0)) + freq->frequency = CPUFREQ_ENTRY_INVALID; + + freq++; + } + + policy->cur = clk_get_rate(armclk) / 1000; + + /* Pick a conservative guess in ns: we'll need ~1 I2C/SPI + * write plus clock reprogramming. */ + policy->cpuinfo.transition_latency = 2 * 1000 * 1000; + + ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table); + if (ret != 0) { + pr_err("cpufreq: Failed to configure frequency table: %d\n", + ret); + regulator_put(vddarm); + clk_put(armclk); + } + + return ret; +} + +static struct cpufreq_driver s3c64xx_cpufreq_driver = { + .owner = THIS_MODULE, + .flags = 0, + .verify = s3c64xx_cpufreq_verify_speed, + .target = s3c64xx_cpufreq_set_target, + .get = s3c64xx_cpufreq_get_speed, + .init = s3c64xx_cpufreq_driver_init, + .name = "s3c", +}; + +static int __init s3c64xx_cpufreq_init(void) +{ + return cpufreq_register_driver(&s3c64xx_cpufreq_driver); +} +module_init(s3c64xx_cpufreq_init); diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c index da7b60e..9285929 100644 --- a/arch/arm/plat-s3c64xx/gpiolib.c +++ b/arch/arm/plat-s3c64xx/gpiolib.c @@ -321,6 +321,11 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { .get_pull = s3c_gpio_getpull_updown, }; +int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin) +{ + return IRQ_EINT(0) + pin; +} + static struct s3c_gpio_chip gpio_2bit[] = { { .base = S3C64XX_GPF_BASE, @@ -353,6 +358,7 @@ static struct s3c_gpio_chip gpio_2bit[] = { .base = S3C64XX_GPN(0), .ngpio = S3C64XX_GPIO_N_NR, .label = "GPN", + .to_irq = s3c64xx_gpio2int_gpn, }, }, { .base = S3C64XX_GPO_BASE, diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index 52836d4..a8777a75 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -88,11 +88,11 @@ #define S3C6400_CLKDIV2_SPI0_SHIFT (0) /* HCLK GATE Registers */ -#define S3C_CLKCON_HCLK_BUS (1<<30) -#define S3C_CLKCON_HCLK_SECUR (1<<29) -#define S3C_CLKCON_HCLK_SDMA1 (1<<28) -#define S3C_CLKCON_HCLK_SDMA2 (1<<27) -#define S3C_CLKCON_HCLK_UHOST (1<<26) +#define S3C_CLKCON_HCLK_3DSE (1<<31) +#define S3C_CLKCON_HCLK_UHOST (1<<29) +#define S3C_CLKCON_HCLK_SECUR (1<<28) +#define S3C_CLKCON_HCLK_SDMA1 (1<<27) +#define S3C_CLKCON_HCLK_SDMA0 (1<<26) #define S3C_CLKCON_HCLK_IROM (1<<25) #define S3C_CLKCON_HCLK_DDR1 (1<<24) #define S3C_CLKCON_HCLK_DDR0 (1<<23) diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index fec6467..33026ef 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -12,7 +12,7 @@ # # http://www.arm.linux.org.uk/developer/machines/?action=new # -# Last update: Fri May 29 10:14:20 2009 +# Last update: Sat Jun 20 22:28:39 2009 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -1455,7 +1455,7 @@ gba MACH_GBA GBA 1457 h6044 MACH_H6044 H6044 1458 app MACH_APP APP 1459 tct_hammer MACH_TCT_HAMMER TCT_HAMMER 1460 -herald MACH_HERMES HERMES 1461 +herald MACH_HERALD HERALD 1461 artemis MACH_ARTEMIS ARTEMIS 1462 htctitan MACH_HTCTITAN HTCTITAN 1463 qranium MACH_QRANIUM QRANIUM 1464 @@ -2245,3 +2245,38 @@ str9 MACH_STR9 STR9 2257 omap3_wl_ff MACH_OMAP3_WL_FF OMAP3_WL_FF 2258 simcom MACH_SIMCOM SIMCOM 2259 mcwebio MACH_MCWEBIO MCWEBIO 2260 +omap3_phrazer MACH_OMAP3_PHRAZER OMAP3_PHRAZER 2261 +darwin MACH_DARWIN DARWIN 2262 +oratiscomu MACH_ORATISCOMU ORATISCOMU 2263 +rtsbc20 MACH_RTSBC20 RTSBC20 2264 +i780 MACH_I780 I780 2265 +gemini324 MACH_GEMINI324 GEMINI324 2266 +oratislan MACH_ORATISLAN ORATISLAN 2267 +oratisalog MACH_ORATISALOG ORATISALOG 2268 +oratismadi MACH_ORATISMADI ORATISMADI 2269 +oratisot16 MACH_ORATISOT16 ORATISOT16 2270 +oratisdesk MACH_ORATISDESK ORATISDESK 2271 +v2p_ca9 MACH_V2P_CA9 V2P_CA9 2272 +sintexo MACH_SINTEXO SINTEXO 2273 +cm3389 MACH_CM3389 CM3389 2274 +omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275 +sgh_i900 MACH_SGH_I900 SGH_I900 2276 +bst100 MACH_BST100 BST100 2277 +passion MACH_PASSION PASSION 2278 +indesign_at91sam MACH_INDESIGN_AT91SAM INDESIGN_AT91SAM 2279 +c4_badger MACH_C4_BADGER C4_BADGER 2280 +c4_viper MACH_C4_VIPER C4_VIPER 2281 +d2net MACH_D2NET D2NET 2282 +bigdisk MACH_BIGDISK BIGDISK 2283 +notalvision MACH_NOTALVISION NOTALVISION 2284 +omap3_kboc MACH_OMAP3_KBOC OMAP3_KBOC 2285 +cyclone MACH_CYCLONE CYCLONE 2286 +ninja MACH_NINJA NINJA 2287 +at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288 +bcmring MACH_BCMRING BCMRING 2289 +resol_dl2 MACH_RESOL_DL2 RESOL_DL2 2290 +ifosw MACH_IFOSW IFOSW 2291 +htcrhodium MACH_HTCRHODIUM HTCRHODIUM 2292 +htctopaz MACH_HTCTOPAZ HTCTOPAZ 2293 +matrix504 MACH_MATRIX504 MATRIX504 2294 +mrfsa MACH_MRFSA MRFSA 2295 diff --git a/arch/avr32/mm/fault.c b/arch/avr32/mm/fault.c index 62d4abb..b61d86d 100644 --- a/arch/avr32/mm/fault.c +++ b/arch/avr32/mm/fault.c @@ -133,7 +133,7 @@ good_area: * fault. */ survive: - fault = handle_mm_fault(mm, vma, address, writeaccess); + fault = handle_mm_fault(mm, vma, address, writeaccess ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 8ea0d94..7faa2f5 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -274,7 +274,7 @@ config BF_REV_0_0 config BF_REV_0_1 bool "0.1" - depends on (BF52x || (BF54x && !BF54xM)) + depends on (BF51x || BF52x || (BF54x && !BF54xM)) config BF_REV_0_2 bool "0.2" @@ -358,7 +358,7 @@ config MEM_MT48LC8M32B2B5_7 config MEM_MT48LC32M16A2TG_75 bool - depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) + depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP) default y config MEM_MT48LC32M8A2_75 @@ -366,6 +366,11 @@ config MEM_MT48LC32M8A2_75 depends on (BFIN518F_EZBRD) default y +config MEM_MT48H32M16LFCJ_75 + bool + depends on (BFIN526_EZBRD) + default y + source "arch/blackfin/mach-bf518/Kconfig" source "arch/blackfin/mach-bf527/Kconfig" source "arch/blackfin/mach-bf533/Kconfig" @@ -623,7 +628,6 @@ choice config TICKSOURCE_GPTMR0 bool "Gptimer0 (SCLK domain)" select BFIN_GPTIMERS - depends on !IPIPE config TICKSOURCE_CORETMR bool "Core timer (CCLK domain)" @@ -644,6 +648,7 @@ config CYCLES_CLOCKSOURCE config GPTMR0_CLOCKSOURCE bool "Use GPTimer0 as a clocksource (higher rating)" + select BFIN_GPTIMERS depends on GENERIC_CLOCKEVENTS depends on !TICKSOURCE_GPTMR0 @@ -908,23 +913,41 @@ endchoice comment "Cache Support" + config BFIN_ICACHE bool "Enable ICACHE" + default y +config BFIN_ICACHE_LOCK + bool "Enable Instruction Cache Locking" + depends on BFIN_ICACHE + default n +config BFIN_EXTMEM_ICACHEABLE + bool "Enable ICACHE for external memory" + depends on BFIN_ICACHE + default y +config BFIN_L2_ICACHEABLE + bool "Enable ICACHE for L2 SRAM" + depends on BFIN_ICACHE + depends on BF54x || BF561 + default n + config BFIN_DCACHE bool "Enable DCACHE" + default y config BFIN_DCACHE_BANKA bool "Enable only 16k BankA DCACHE - BankB is SRAM" depends on BFIN_DCACHE && !BF531 default n -config BFIN_ICACHE_LOCK - bool "Enable Instruction Cache Locking" - -choice - prompt "External memory cache policy" +config BFIN_EXTMEM_DCACHEABLE + bool "Enable DCACHE for external memory" depends on BFIN_DCACHE - default BFIN_WB if !SMP - default BFIN_WT if SMP -config BFIN_WB + default y +choice + prompt "External memory DCACHE policy" + depends on BFIN_EXTMEM_DCACHEABLE + default BFIN_EXTMEM_WRITEBACK if !SMP + default BFIN_EXTMEM_WRITETHROUGH if SMP +config BFIN_EXTMEM_WRITEBACK bool "Write back" depends on !SMP help @@ -942,7 +965,7 @@ config BFIN_WB If you are unsure of the options and you want to be safe, then go with Write Through. -config BFIN_WT +config BFIN_EXTMEM_WRITETHROUGH bool "Write through" help Write Back Policy: @@ -961,23 +984,26 @@ config BFIN_WT endchoice +config BFIN_L2_DCACHEABLE + bool "Enable DCACHE for L2 SRAM" + depends on BFIN_DCACHE + depends on BF54x || BF561 + default n choice - prompt "L2 SRAM cache policy" - depends on (BF54x || BF561) - default BFIN_L2_WT -config BFIN_L2_WB + prompt "L2 SRAM DCACHE policy" + depends on BFIN_L2_DCACHEABLE + default BFIN_L2_WRITEBACK +config BFIN_L2_WRITEBACK bool "Write back" depends on !SMP -config BFIN_L2_WT +config BFIN_L2_WRITETHROUGH bool "Write through" depends on !SMP - -config BFIN_L2_NOT_CACHED - bool "Not cached" - endchoice + +comment "Memory Protection Unit" config MPU bool "Enable the memory protection unit (EXPERIMENTAL)" default n diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile index 3ab6f23..fd9ccc5 100644 --- a/arch/blackfin/boot/Makefile +++ b/arch/blackfin/boot/Makefile @@ -13,7 +13,7 @@ extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma quiet_cmd_uimage = UIMAGE $@ cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \ - -C $(2) -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \ + -C $(2) -n '$(MACHINE)-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \ -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \ -d $< $@ diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig index baec133..dcfb488 100644 --- a/arch/blackfin/configs/BF518F-EZBRD_defconfig +++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig @@ -326,11 +326,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -413,11 +419,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -916,7 +922,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y # CONFIG_MMC_SDHCI is not set CONFIG_SDH_BFIN=m CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y -CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ=y +# CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ is not set # CONFIG_MMC_SPI is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1147,7 +1153,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig index c06262e..48a3a7a 100644 --- a/arch/blackfin/configs/BF526-EZBRD_defconfig +++ b/arch/blackfin/configs/BF526-EZBRD_defconfig @@ -331,16 +331,18 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -# CONFIG_MPU is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set # -# Asynchonous Memory Configuration +# Memory Protection Unit # +# CONFIG_MPU is not set # # EBIU_AMGCTL Global Control @@ -418,11 +420,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1424,7 +1426,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig index e9175c6..dd83527 100644 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT_defconfig @@ -331,11 +331,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -418,11 +424,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1505,7 +1511,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig index 5aa63ba..4c04480 100644 --- a/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/arch/blackfin/configs/BF533-EZKIT_defconfig @@ -292,12 +292,21 @@ CONFIG_DMA_UNCACHED_1M=y # # Cache Support # +# +# Cache Support +# CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -391,11 +400,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1052,7 +1061,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig index fed2532..c99bbcd 100644 --- a/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/arch/blackfin/configs/BF533-STAMP_defconfig @@ -293,11 +293,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -391,11 +397,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1216,7 +1222,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig index f9ac20d..092ffda 100644 --- a/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/arch/blackfin/configs/BF537-STAMP_defconfig @@ -300,11 +300,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -399,11 +405,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1269,7 +1275,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig index ee98e22..fa698a8 100644 --- a/arch/blackfin/configs/BF538-EZKIT_defconfig +++ b/arch/blackfin/configs/BF538-EZKIT_defconfig @@ -311,11 +311,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -398,11 +404,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1203,7 +1209,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index deeabef..b3d3cab 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig @@ -366,14 +366,19 @@ CONFIG_DMA_UNCACHED_2M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -# CONFIG_BFIN_L2_WB is not set -CONFIG_BFIN_L2_WT=y -# CONFIG_BFIN_L2_NOT_CACHED is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_L2_DCACHEABLE is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -459,11 +464,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1606,7 +1611,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig index dcfbe2e..0313cd1 100644 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT_defconfig @@ -331,14 +331,19 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -# CONFIG_BFIN_L2_WB is not set -CONFIG_BFIN_L2_WT=y -# CONFIG_BFIN_L2_NOT_CACHED is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_L2_DCACHEABLE is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -425,11 +430,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1044,7 +1049,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig index 174c578..5d944ff 100644 --- a/arch/blackfin/configs/BlackStamp_defconfig +++ b/arch/blackfin/configs/BlackStamp_defconfig @@ -285,11 +285,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig index e17875e..648a31d 100644 --- a/arch/blackfin/configs/CM-BF527_defconfig +++ b/arch/blackfin/configs/CM-BF527_defconfig @@ -329,11 +329,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -417,11 +423,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1246,7 +1252,7 @@ CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig index fafd95e..ae665b9 100644 --- a/arch/blackfin/configs/CM-BF533_defconfig +++ b/arch/blackfin/configs/CM-BF533_defconfig @@ -262,12 +262,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -CONFIG_L1_MAX_PIECE=16 +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -353,10 +358,10 @@ CONFIG_IP_FIB_HASH=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_DIAG=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -873,7 +878,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig index e73aa5a..d74b6f4 100644 --- a/arch/blackfin/configs/CM-BF537E_defconfig +++ b/arch/blackfin/configs/CM-BF537E_defconfig @@ -297,11 +297,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -383,11 +389,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -861,7 +867,7 @@ CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig index 8021130..7fc8dfa1 100644 --- a/arch/blackfin/configs/CM-BF537U_defconfig +++ b/arch/blackfin/configs/CM-BF537U_defconfig @@ -270,12 +270,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -CONFIG_L1_MAX_PIECE=16 +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -361,10 +366,10 @@ CONFIG_IP_FIB_HASH=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_DIAG=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -901,7 +906,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig index dd815f0..acca4e5 100644 --- a/arch/blackfin/configs/CM-BF548_defconfig +++ b/arch/blackfin/configs/CM-BF548_defconfig @@ -333,12 +333,19 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -CONFIG_L1_MAX_PIECE=16 +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_L2_DCACHEABLE is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -428,11 +435,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -1334,7 +1341,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_SAMPLES is not set CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HUNT_FOR_ZERO=y diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig index 16c198b..bae4ee6 100644 --- a/arch/blackfin/configs/CM-BF561_defconfig +++ b/arch/blackfin/configs/CM-BF561_defconfig @@ -308,12 +308,19 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -CONFIG_L1_MAX_PIECE=16 +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_L2_DCACHEABLE is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -395,11 +402,11 @@ CONFIG_IP_FIB_HASH=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -837,7 +844,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_SAMPLES is not set CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HUNT_FOR_ZERO=y diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig index 6b4c1a9..a6a7c8e 100644 --- a/arch/blackfin/configs/H8606_defconfig +++ b/arch/blackfin/configs/H8606_defconfig @@ -258,12 +258,18 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -CONFIG_BFIN_ICACHE_LOCK=y -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -CONFIG_L1_MAX_PIECE=16 +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# +# CONFIG_MPU is not set # # Asynchonous Memory Configuration diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig index 09701f9..ff377fa 100644 --- a/arch/blackfin/configs/PNAV-10_defconfig +++ b/arch/blackfin/configs/PNAV-10_defconfig @@ -295,11 +295,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -382,11 +388,11 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG is not set CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig index ec84a53..814f9ca 100644 --- a/arch/blackfin/configs/SRV1_defconfig +++ b/arch/blackfin/configs/SRV1_defconfig @@ -279,12 +279,18 @@ CONFIG_DMA_UNCACHED_2M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set -CONFIG_L1_MAX_PIECE=16 +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# +# CONFIG_MPU is not set # # Asynchonous Memory Configuration diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig index 6e27962..375e75a 100644 --- a/arch/blackfin/configs/TCM-BF537_defconfig +++ b/arch/blackfin/configs/TCM-BF537_defconfig @@ -287,11 +287,17 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set -# CONFIG_BFIN_ICACHE_LOCK is not set -CONFIG_BFIN_WB=y -# CONFIG_BFIN_WT is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y +CONFIG_BFIN_EXTMEM_DCACHEABLE=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set + +# +# Memory Protection Unit +# # CONFIG_MPU is not set # @@ -709,7 +715,7 @@ CONFIG_FRAME_WARN=1024 CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_SYSCTL_SYSCALL_CHECK is not set diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h index b1d92f1..88f36d5 100644 --- a/arch/blackfin/include/asm/atomic.h +++ b/arch/blackfin/include/asm/atomic.h @@ -1,24 +1,21 @@ #ifndef __ARCH_BLACKFIN_ATOMIC__ #define __ARCH_BLACKFIN_ATOMIC__ +#ifndef CONFIG_SMP +# include <asm-generic/atomic.h> +#else + #include <linux/types.h> #include <asm/system.h> /* local_irq_XXX() */ /* * Atomic operations that C can't guarantee us. Useful for * resource counting etc.. - * - * Generally we do not concern about SMP BFIN systems, so we don't have - * to deal with that. - * - * Tony Kou (tonyko@lineo.ca) Lineo Inc. 2001 */ #define ATOMIC_INIT(i) { (i) } #define atomic_set(v, i) (((v)->counter) = i) -#ifdef CONFIG_SMP - #define atomic_read(v) __raw_uncached_fetch_asm(&(v)->counter) asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr); @@ -84,100 +81,6 @@ static inline int atomic_test_mask(int mask, atomic_t *v) #define smp_mb__before_atomic_inc() barrier() #define smp_mb__after_atomic_inc() barrier() -#else /* !CONFIG_SMP */ - -#define atomic_read(v) ((v)->counter) - -static inline void atomic_add(int i, atomic_t *v) -{ - unsigned long flags; - - local_irq_save_hw(flags); - v->counter += i; - local_irq_restore_hw(flags); -} - -static inline void atomic_sub(int i, atomic_t *v) -{ - unsigned long flags; - - local_irq_save_hw(flags); - v->counter -= i; - local_irq_restore_hw(flags); - -} - -static inline int atomic_add_return(int i, atomic_t *v) -{ - int __temp = 0; - unsigned long flags; - - local_irq_save_hw(flags); - v->counter += i; - __temp = v->counter; - local_irq_restore_hw(flags); - - - return __temp; -} - -static inline int atomic_sub_return(int i, atomic_t *v) -{ - int __temp = 0; - unsigned long flags; - - local_irq_save_hw(flags); - v->counter -= i; - __temp = v->counter; - local_irq_restore_hw(flags); - - return __temp; -} - -static inline void atomic_inc(volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save_hw(flags); - v->counter++; - local_irq_restore_hw(flags); -} - -static inline void atomic_dec(volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save_hw(flags); - v->counter--; - local_irq_restore_hw(flags); -} - -static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) -{ - unsigned long flags; - - local_irq_save_hw(flags); - v->counter &= ~mask; - local_irq_restore_hw(flags); -} - -static inline void atomic_set_mask(unsigned int mask, atomic_t *v) -{ - unsigned long flags; - - local_irq_save_hw(flags); - v->counter |= mask; - local_irq_restore_hw(flags); -} - -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - -#endif /* !CONFIG_SMP */ - #define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) #define atomic_dec_return(v) atomic_sub_return(1,(v)) #define atomic_inc_return(v) atomic_add_return(1,(v)) @@ -210,4 +113,6 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v) #include <asm-generic/atomic-long.h> -#endif /* __ARCH_BLACKFIN_ATOMIC __ */ +#endif + +#endif diff --git a/arch/blackfin/include/asm/auxvec.h b/arch/blackfin/include/asm/auxvec.h index 215506c..41fa68b 100644 --- a/arch/blackfin/include/asm/auxvec.h +++ b/arch/blackfin/include/asm/auxvec.h @@ -1,4 +1 @@ -#ifndef __ASMBFIN_AUXVEC_H -#define __ASMBFIN_AUXVEC_H - -#endif +#include <asm-generic/auxvec.h> diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index 75fee2f..daffa71 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h @@ -1,26 +1,22 @@ #ifndef _BLACKFIN_BITOPS_H #define _BLACKFIN_BITOPS_H -/* - * Copyright 1992, Linus Torvalds. - */ - -#include <linux/compiler.h> -#include <asm/byteorder.h> /* swab32 */ - -#ifdef __KERNEL__ +#ifndef CONFIG_SMP +# include <asm-generic/bitops.h> +#else #ifndef _LINUX_BITOPS_H #error only <linux/bitops.h> can be included directly #endif +#include <linux/compiler.h> +#include <asm/byteorder.h> /* swab32 */ + #include <asm-generic/bitops/ffs.h> #include <asm-generic/bitops/__ffs.h> #include <asm-generic/bitops/sched.h> #include <asm-generic/bitops/ffz.h> -#ifdef CONFIG_SMP - #include <linux/linkage.h> asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr); @@ -79,189 +75,13 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr) return __raw_bit_test_toggle_asm(a, nr & 0x1f); } -#else /* !CONFIG_SMP */ - -#include <asm/system.h> /* save_flags */ - -static inline void set_bit(int nr, volatile unsigned long *addr) -{ - int *a = (int *)addr; - int mask; - unsigned long flags; - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save_hw(flags); - *a |= mask; - local_irq_restore_hw(flags); -} - -static inline void clear_bit(int nr, volatile unsigned long *addr) -{ - int *a = (int *)addr; - int mask; - unsigned long flags; - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save_hw(flags); - *a &= ~mask; - local_irq_restore_hw(flags); -} - -static inline void change_bit(int nr, volatile unsigned long *addr) -{ - int mask; - unsigned long flags; - unsigned long *ADDR = (unsigned long *)addr; - - ADDR += nr >> 5; - mask = 1 << (nr & 31); - local_irq_save_hw(flags); - *ADDR ^= mask; - local_irq_restore_hw(flags); -} - -static inline int test_and_set_bit(int nr, volatile unsigned long *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save_hw(flags); - retval = (mask & *a) != 0; - *a |= mask; - local_irq_restore_hw(flags); - - return retval; -} - -static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save_hw(flags); - retval = (mask & *a) != 0; - *a &= ~mask; - local_irq_restore_hw(flags); - - return retval; -} - -static inline int test_and_change_bit(int nr, volatile unsigned long *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save_hw(flags); - retval = (mask & *a) != 0; - *a ^= mask; - local_irq_restore_hw(flags); - return retval; -} - -#endif /* CONFIG_SMP */ - /* * clear_bit() doesn't provide any barrier for the compiler. */ #define smp_mb__before_clear_bit() barrier() #define smp_mb__after_clear_bit() barrier() -static inline void __set_bit(int nr, volatile unsigned long *addr) -{ - int *a = (int *)addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - *a |= mask; -} - -static inline void __clear_bit(int nr, volatile unsigned long *addr) -{ - int *a = (int *)addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - *a &= ~mask; -} - -static inline void __change_bit(int nr, volatile unsigned long *addr) -{ - int mask; - unsigned long *ADDR = (unsigned long *)addr; - - ADDR += nr >> 5; - mask = 1 << (nr & 31); - *ADDR ^= mask; -} - -static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a |= mask; - return retval; -} - -static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a &= ~mask; - return retval; -} - -static inline int __test_and_change_bit(int nr, - volatile unsigned long *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a ^= mask; - return retval; -} - -static inline int __test_bit(int nr, const void *addr) -{ - int *a = (int *)addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - return ((mask & *a) != 0); -} - -#ifndef CONFIG_SMP -/* - * This routine doesn't need irq save and restore ops in UP - * context. - */ -static inline int test_bit(int nr, const void *addr) -{ - return __test_bit(nr, addr); -} -#endif +#include <asm-generic/bitops/non-atomic.h> #include <asm-generic/bitops/find.h> #include <asm-generic/bitops/hweight.h> @@ -272,10 +92,10 @@ static inline int test_bit(int nr, const void *addr) #include <asm-generic/bitops/minix.h> -#endif /* __KERNEL__ */ - #include <asm-generic/bitops/fls.h> #include <asm-generic/bitops/__fls.h> #include <asm-generic/bitops/fls64.h> +#endif /* CONFIG_SMP */ + #endif /* _BLACKFIN_BITOPS_H */ diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h index 8bb2cb1..4d44395 100644 --- a/arch/blackfin/include/asm/blackfin.h +++ b/arch/blackfin/include/asm/blackfin.h @@ -86,6 +86,7 @@ static inline void CSYNC(void) #endif /* __ASSEMBLY__ */ +#include <asm/mem_map.h> #include <mach/blackfin.h> #include <asm/bfin-global.h> diff --git a/arch/blackfin/include/asm/bugs.h b/arch/blackfin/include/asm/bugs.h index 9093c9c..61791e1 100644 --- a/arch/blackfin/include/asm/bugs.h +++ b/arch/blackfin/include/asm/bugs.h @@ -1,16 +1 @@ -/* - * include/asm-blackfin/bugs.h - * - * Copyright (C) 1994 Linus Torvalds - */ - -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ - -static void check_bugs(void) -{ -} +#include <asm-generic/bugs.h> diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h index 2ef669e..477050a 100644 --- a/arch/blackfin/include/asm/cache.h +++ b/arch/blackfin/include/asm/cache.h @@ -35,10 +35,10 @@ #if defined(CONFIG_SMP) && \ !defined(CONFIG_BFIN_CACHE_COHERENT) -# if defined(CONFIG_BFIN_ICACHE) +# if defined(CONFIG_BFIN_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE) # define __ARCH_SYNC_CORE_ICACHE # endif -# if defined(CONFIG_BFIN_DCACHE) +# if defined(CONFIG_BFIN_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE) # define __ARCH_SYNC_CORE_DCACHE # endif #ifndef __ASSEMBLY__ diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h index 5c17dee..7e55549e 100644 --- a/arch/blackfin/include/asm/cacheflush.h +++ b/arch/blackfin/include/asm/cacheflush.h @@ -56,7 +56,7 @@ extern void blackfin_invalidate_entire_icache(void); static inline void flush_icache_range(unsigned start, unsigned end) { -#if defined(CONFIG_BFIN_WB) +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) blackfin_dcache_flush_range(start, end); #endif @@ -87,9 +87,9 @@ do { memcpy(dst, src, len); \ #else # define invalidate_dcache_range(start,end) do { } while (0) #endif -#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB) +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) # define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) -# define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) +# define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) #else # define flush_dcache_range(start,end) do { } while (0) # define flush_dcache_page(page) do { } while (0) @@ -100,7 +100,7 @@ extern unsigned long reserved_mem_icache_on; static inline int bfin_addr_dcacheable(unsigned long addr) { -#ifdef CONFIG_BFIN_DCACHE +#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE if (addr < (_ramend - DMA_UNCACHED_REGION)) return 1; #endif @@ -109,7 +109,7 @@ static inline int bfin_addr_dcacheable(unsigned long addr) addr >= _ramend && addr < physical_mem_end) return 1; -#ifndef CONFIG_BFIN_L2_NOT_CACHED +#ifdef CONFIG_BFIN_L2_DCACHEABLE if (addr >= L2_START && addr < L2_START + L2_LENGTH) return 1; #endif diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index a75a6a9..c5dacf8 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -37,8 +37,6 @@ #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) -/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/ - #if ANOMALY_05000158 #define ANOMALY_05000158_WORKAROUND 0x200 #else @@ -47,10 +45,12 @@ #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#ifdef CONFIG_BFIN_WB /*Write Back Policy */ +#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON) -#else /*Write Through */ +#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) +#else +#define SDRAM_DGENERIC (CPLB_COMMON) #endif #define SDRAM_DNON_CHBL (CPLB_COMMON) @@ -61,21 +61,23 @@ #ifdef CONFIG_SMP #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) -#define L2_IMEMORY (CPLB_COMMON) -#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON) +#define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) +#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB) #else #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) -#define L2_IMEMORY (SDRAM_IGENERIC) - -# if defined(CONFIG_BFIN_L2_WB) -# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON) -# elif defined(CONFIG_BFIN_L2_WT) -# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) -# elif defined(CONFIG_BFIN_L2_NOT_CACHED) -# define L2_DMEMORY (CPLB_COMMON) +# if defined(CONFIG_BFIN_L2_ICACHEABLE) +# define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) +# else +# define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) +# endif + +# if defined(CONFIG_BFIN_L2_WRITEBACK) +# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB) +# elif defined(CONFIG_BFIN_L2_WRITETHROUGH) +# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB) # else -# define L2_DMEMORY (0) +# define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) # endif #endif /* CONFIG_SMP */ diff --git a/arch/blackfin/include/asm/cputime.h b/arch/blackfin/include/asm/cputime.h index 2b19705..6d68ad7 100644 --- a/arch/blackfin/include/asm/cputime.h +++ b/arch/blackfin/include/asm/cputime.h @@ -1,6 +1 @@ -#ifndef __BLACKFIN_CPUTIME_H -#define __BLACKFIN_CPUTIME_H - #include <asm-generic/cputime.h> - -#endif /* __BLACKFIN_CPUTIME_H */ diff --git a/arch/blackfin/include/asm/current.h b/arch/blackfin/include/asm/current.h index 31918d2..4c51401 100644 --- a/arch/blackfin/include/asm/current.h +++ b/arch/blackfin/include/asm/current.h @@ -1,23 +1 @@ -#ifndef _BLACKFIN_CURRENT_H -#define _BLACKFIN_CURRENT_H -/* - * current.h - * (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com> - * - * rather than dedicate a register (as the m68k source does), we - * just keep a global, we should probably just change it all to be - * current and lose _current_task. - */ -#include <linux/thread_info.h> - -struct task_struct; - -static inline struct task_struct *get_current(void) __attribute__ ((__const__)); -static inline struct task_struct *get_current(void) -{ - return (current_thread_info()->task); -} - -#define current (get_current()) - -#endif /* _BLACKFIN_CURRENT_H */ +#include <asm-generic/current.h> diff --git a/arch/blackfin/include/asm/device.h b/arch/blackfin/include/asm/device.h index d8f9872..f0a4c25 100644 --- a/arch/blackfin/include/asm/device.h +++ b/arch/blackfin/include/asm/device.h @@ -1,7 +1 @@ -/* - * Arch specific extensions to struct device - * - * This file is released under the GPLv2 - */ #include <asm-generic/device.h> - diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h index d7d9148..ed6b1f3 100644 --- a/arch/blackfin/include/asm/dma-mapping.h +++ b/arch/blackfin/include/asm/dma-mapping.h @@ -95,4 +95,17 @@ static inline void dma_sync_single_for_device(struct device *dev, enum dma_data_direction dir) { } + +static inline void dma_sync_sg_for_cpu(struct device *dev, + struct scatterlist *sg, + int nents, enum dma_data_direction dir) +{ +} + +static inline void dma_sync_sg_for_device(struct device *dev, + struct scatterlist *sg, + int nents, enum dma_data_direction dir) +{ +} + #endif /* _BLACKFIN_DMA_MAPPING_H */ diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h index 230e160..5a87baf 100644 --- a/arch/blackfin/include/asm/elf.h +++ b/arch/blackfin/include/asm/elf.h @@ -20,7 +20,7 @@ typedef unsigned long elf_greg_t; -#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) +#define ELF_NGREG 40 /* (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) */ typedef elf_greg_t elf_gregset_t[ELF_NGREG]; typedef struct user_bfinfp_struct elf_fpregset_t; diff --git a/arch/blackfin/include/asm/emergency-restart.h b/arch/blackfin/include/asm/emergency-restart.h index 27f6c78..3711bd9 100644 --- a/arch/blackfin/include/asm/emergency-restart.h +++ b/arch/blackfin/include/asm/emergency-restart.h @@ -1,6 +1 @@ -#ifndef _ASM_EMERGENCY_RESTART_H -#define _ASM_EMERGENCY_RESTART_H - #include <asm-generic/emergency-restart.h> - -#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/arch/blackfin/include/asm/errno.h b/arch/blackfin/include/asm/errno.h index 164e4f3..4c82b50 100644 --- a/arch/blackfin/include/asm/errno.h +++ b/arch/blackfin/include/asm/errno.h @@ -1,6 +1 @@ -#ifndef _BFIN_ERRNO_H -#define _BFIN_ERRNO_H - -#include<asm-generic/errno.h> - -#endif /* _BFIN_ERRNO_H */ +#include <asm-generic/errno.h> diff --git a/arch/blackfin/include/asm/fb.h b/arch/blackfin/include/asm/fb.h index c7df380..3a4988e 100644 --- a/arch/blackfin/include/asm/fb.h +++ b/arch/blackfin/include/asm/fb.h @@ -1,12 +1 @@ -#ifndef _ASM_FB_H_ -#define _ASM_FB_H_ -#include <linux/fb.h> - -#define fb_pgprotect(...) do {} while (0) - -static inline int fb_is_primary_device(struct fb_info *info) -{ - return 0; -} - -#endif /* _ASM_FB_H_ */ +#include <asm-generic/fb.h> diff --git a/arch/blackfin/include/asm/futex.h b/arch/blackfin/include/asm/futex.h index 6a332a9..0b74582 100644 --- a/arch/blackfin/include/asm/futex.h +++ b/arch/blackfin/include/asm/futex.h @@ -1,6 +1 @@ -#ifndef _ASM_FUTEX_H -#define _ASM_FUTEX_H - #include <asm-generic/futex.h> - -#endif diff --git a/arch/blackfin/include/asm/hardirq.h b/arch/blackfin/include/asm/hardirq.h index 717181a..cbd52f8 100644 --- a/arch/blackfin/include/asm/hardirq.h +++ b/arch/blackfin/include/asm/hardirq.h @@ -1,47 +1,11 @@ #ifndef __BFIN_HARDIRQ_H #define __BFIN_HARDIRQ_H -#include <linux/cache.h> -#include <linux/threads.h> -#include <asm/irq.h> - -typedef struct { - unsigned int __softirq_pending; - unsigned int __syscall_count; - struct task_struct *__ksoftirqd_task; -} ____cacheline_aligned irq_cpustat_t; - -#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ - -/* - * We put the hardirq and softirq counter into the preemption - * counter. The bitmask has the following meaning: - * - * - bits 0-7 are the preemption count (max preemption depth: 256) - * - bits 8-15 are the softirq count (max # of softirqs: 256) - * - bits 16-23 are the hardirq count (max # of hardirqs: 256) - * - * - ( bit 26 is the PREEMPT_ACTIVE flag. ) - * - * PREEMPT_MASK: 0x000000ff - * HARDIRQ_MASK: 0x0000ff00 - * SOFTIRQ_MASK: 0x00ff0000 - */ - -#if NR_IRQS > 256 -#define HARDIRQ_BITS 9 -#else -#define HARDIRQ_BITS 8 -#endif - -#ifdef NR_IRQS -# if (1 << HARDIRQ_BITS) < NR_IRQS -# error HARDIRQ_BITS is too low! -# endif -#endif - #define __ARCH_IRQ_EXIT_IRQS_DISABLED 1 extern void ack_bad_irq(unsigned int irq); +#define ack_bad_irq ack_bad_irq + +#include <asm-generic/hardirq.h> #endif diff --git a/arch/blackfin/include/asm/hw_irq.h b/arch/blackfin/include/asm/hw_irq.h index 5b51eae..1f5ef7d 100644 --- a/arch/blackfin/include/asm/hw_irq.h +++ b/arch/blackfin/include/asm/hw_irq.h @@ -1,6 +1 @@ -#ifndef __ASM_BFIN_HW_IRQ_H -#define __ASM_BFIN_HW_IRQ_H - -/* Dummy include. */ - -#endif +#include <asm-generic/hw_irq.h> diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h index 3022b5c..37053ec 100644 --- a/arch/blackfin/include/asm/io.h +++ b/arch/blackfin/include/asm/io.h @@ -222,7 +222,6 @@ extern void blkfin_inv_cache_all(void); #define ioport_unmap(addr) /* Pages to physical address... */ -#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) #define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT) #define phys_to_virt(vaddr) ((void *) (vaddr)) diff --git a/arch/blackfin/include/asm/ioctls.h b/arch/blackfin/include/asm/ioctls.h index 895e317..eca8d75 100644 --- a/arch/blackfin/include/asm/ioctls.h +++ b/arch/blackfin/include/asm/ioctls.h @@ -1,87 +1,7 @@ #ifndef __ARCH_BFIN_IOCTLS_H__ #define __ARCH_BFIN_IOCTLS_H__ -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -#define TIOCTTYGSTRUCT 0x5426 /* For debugging only */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T', 0x2A, struct termios2) -#define TCSETS2 _IOW('T', 0x2B, struct termios2) -#define TCSETSW2 _IOW('T', 0x2C, struct termios2) -#define TCSETSF2 _IOW('T', 0x2D, struct termios2) -/* Get Pty Number (of pty-mux device) */ -#define TIOCGPTN _IOR('T', 0x30, unsigned int) -#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ - -#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ - #define FIOQSIZE 0x545E +#include <asm-generic/ioctls.h> -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ - -#endif /* __ARCH_BFIN_IOCTLS_H__ */ +#endif diff --git a/arch/blackfin/include/asm/ipcbuf.h b/arch/blackfin/include/asm/ipcbuf.h index 8f0899c..84c7e51 100644 --- a/arch/blackfin/include/asm/ipcbuf.h +++ b/arch/blackfin/include/asm/ipcbuf.h @@ -1,30 +1 @@ -/* Changes origined from m68k version. Lineo Inc. May 2001 */ - -#ifndef __BFIN_IPCBUF_H__ -#define __BFIN_IPCBUF_H__ - -/* - * The user_ipc_perm structure for m68k architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 32-bit mode_t and seq - * - 2 miscellaneous 32-bit values - */ - -struct ipc64_perm { - __kernel_key_t key; - __kernel_uid32_t uid; - __kernel_gid32_t gid; - __kernel_uid32_t cuid; - __kernel_gid32_t cgid; - __kernel_mode_t mode; - unsigned short __pad1; - unsigned short seq; - unsigned short __pad2; - unsigned long __unused1; - unsigned long __unused2; -}; - -#endif /* __BFIN_IPCBUF_H__ */ +#include <asm-generic/ipcbuf.h> diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h index bbe1c37..87ba9ad 100644 --- a/arch/blackfin/include/asm/ipipe.h +++ b/arch/blackfin/include/asm/ipipe.h @@ -35,9 +35,9 @@ #include <asm/atomic.h> #include <asm/traps.h> -#define IPIPE_ARCH_STRING "1.10-00" +#define IPIPE_ARCH_STRING "1.11-00" #define IPIPE_MAJOR_NUMBER 1 -#define IPIPE_MINOR_NUMBER 10 +#define IPIPE_MINOR_NUMBER 11 #define IPIPE_PATCH_NUMBER 0 #ifdef CONFIG_SMP @@ -207,7 +207,7 @@ void ipipe_init_irq_threads(void); int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); -#ifdef CONFIG_GENERIC_CLOCKEVENTS +#ifdef CONFIG_TICKSOURCE_CORETMR #define IRQ_SYSTMR IRQ_CORETMR #define IRQ_PRIOTMR IRQ_CORETMR #else @@ -240,8 +240,13 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); #define ipipe_init_irq_threads() do { } while (0) #define ipipe_start_irq_thread(irq, desc) 0 +#ifndef CONFIG_TICKSOURCE_GPTMR0 #define IRQ_SYSTMR IRQ_CORETMR #define IRQ_PRIOTMR IRQ_CORETMR +#else +#define IRQ_SYSTMR IRQ_TIMER0 +#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 +#endif #define __ipipe_root_tick_p(regs) 1 diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h index 3e8acbd..490098f 100644 --- a/arch/blackfin/include/asm/ipipe_base.h +++ b/arch/blackfin/include/asm/ipipe_base.h @@ -51,23 +51,23 @@ extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ -static inline void __ipipe_stall_root(void) -{ - volatile unsigned long *p = &__ipipe_root_status; - set_bit(0, p); -} +#define __ipipe_stall_root() \ + do { \ + volatile unsigned long *p = &__ipipe_root_status; \ + set_bit(0, p); \ + } while (0) -static inline unsigned long __ipipe_test_and_stall_root(void) -{ - volatile unsigned long *p = &__ipipe_root_status; - return test_and_set_bit(0, p); -} +#define __ipipe_test_and_stall_root() \ + ({ \ + volatile unsigned long *p = &__ipipe_root_status; \ + test_and_set_bit(0, p); \ + }) -static inline unsigned long __ipipe_test_root(void) -{ - const unsigned long *p = &__ipipe_root_status; - return test_bit(0, p); -} +#define __ipipe_test_root() \ + ({ \ + const unsigned long *p = &__ipipe_root_status; \ + test_bit(0, p); \ + }) #endif /* !__ASSEMBLY__ */ diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h index 400bdd5..42a15f5 100644 --- a/arch/blackfin/include/asm/irq.h +++ b/arch/blackfin/include/asm/irq.h @@ -22,13 +22,6 @@ /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */ #include <mach/irq.h> -/* Xenomai IPIPE helpers */ -#define local_irq_restore_hw(x) local_irq_restore(x) -#define local_irq_save_hw(x) local_irq_save(x) -#define local_irq_enable_hw(x) local_irq_enable(x) -#define local_irq_disable_hw(x) local_irq_disable(x) -#define irqs_disabled_hw(x) irqs_disabled(x) - #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) # define NOP_PAD_ANOMALY_05000244 "nop; nop;" #else @@ -45,9 +38,6 @@ : "d" (bfin_irq_flags) \ ) -static inline int irq_canonicalize(int irq) -{ - return irq; -} +#include <asm-generic/irq.h> #endif /* _BFIN_IRQ_H_ */ diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h index 139cba4..9b19a19 100644 --- a/arch/blackfin/include/asm/irqflags.h +++ b/arch/blackfin/include/asm/irqflags.h @@ -31,6 +31,150 @@ static inline unsigned long bfin_cli(void) return flags; } +#ifdef CONFIG_IPIPE + +#include <linux/ipipe_base.h> +#include <linux/ipipe_trace.h> + +#ifdef CONFIG_DEBUG_HWERR +# define bfin_no_irqs 0x3f +#else +# define bfin_no_irqs 0x1f +#endif + +#define raw_local_irq_disable() \ + do { \ + ipipe_check_context(ipipe_root_domain); \ + __ipipe_stall_root(); \ + barrier(); \ + } while (0) + +static inline void raw_local_irq_enable(void) +{ + barrier(); + ipipe_check_context(ipipe_root_domain); + __ipipe_unstall_root(); +} + +#define raw_local_save_flags_ptr(x) \ + do { \ + *(x) = __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; \ + } while (0) + +#define raw_local_save_flags(x) raw_local_save_flags_ptr(&(x)) + +#define raw_irqs_disabled_flags(x) ((x) == bfin_no_irqs) + +#define raw_local_irq_save_ptr(x) \ + do { \ + *(x) = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; \ + barrier(); \ + } while (0) + +#define raw_local_irq_save(x) \ + do { \ + ipipe_check_context(ipipe_root_domain); \ + raw_local_irq_save_ptr(&(x)); \ + } while (0) + +static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real) +{ + /* + * Merge virtual and real interrupt mask bits into a single + * 32bit word. + */ + return (real & ~(1 << 31)) | ((virt != 0) << 31); +} + +static inline int raw_demangle_irq_bits(unsigned long *x) +{ + int virt = (*x & (1 << 31)) != 0; + *x &= ~(1L << 31); + return virt; +} + +static inline void local_irq_disable_hw_notrace(void) +{ + bfin_cli(); +} + +static inline void local_irq_enable_hw_notrace(void) +{ + bfin_sti(bfin_irq_flags); +} + +#define local_save_flags_hw(flags) \ + do { \ + (flags) = bfin_read_IMASK(); \ + } while (0) + +#define irqs_disabled_flags_hw(flags) (((flags) & ~0x3f) == 0) + +#define irqs_disabled_hw() \ + ({ \ + unsigned long flags; \ + local_save_flags_hw(flags); \ + irqs_disabled_flags_hw(flags); \ + }) + +static inline void local_irq_save_ptr_hw(unsigned long *flags) +{ + *flags = bfin_cli(); +#ifdef CONFIG_DEBUG_HWERR + bfin_sti(0x3f); +#endif +} + +#define local_irq_save_hw_notrace(flags) \ + do { \ + local_irq_save_ptr_hw(&(flags)); \ + } while (0) + +static inline void local_irq_restore_hw_notrace(unsigned long flags) +{ + if (!irqs_disabled_flags_hw(flags)) + local_irq_enable_hw_notrace(); +} + +#ifdef CONFIG_IPIPE_TRACE_IRQSOFF +# define local_irq_disable_hw() \ + do { \ + if (!irqs_disabled_hw()) { \ + local_irq_disable_hw_notrace(); \ + ipipe_trace_begin(0x80000000); \ + } \ + } while (0) +# define local_irq_enable_hw() \ + do { \ + if (irqs_disabled_hw()) { \ + ipipe_trace_end(0x80000000); \ + local_irq_enable_hw_notrace(); \ + } \ + } while (0) +# define local_irq_save_hw(flags) \ + do { \ + local_save_flags_hw(flags); \ + if (!irqs_disabled_flags_hw(flags)) { \ + local_irq_disable_hw_notrace(); \ + ipipe_trace_begin(0x80000001); \ + } \ + } while (0) +# define local_irq_restore_hw(flags) \ + do { \ + if (!irqs_disabled_flags_hw(flags)) { \ + ipipe_trace_end(0x80000001); \ + local_irq_enable_hw_notrace(); \ + } \ + } while (0) +#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */ +# define local_irq_disable_hw() local_irq_disable_hw_notrace() +# define local_irq_enable_hw() local_irq_enable_hw_notrace() +# define local_irq_save_hw(flags) local_irq_save_hw_notrace(flags) +# define local_irq_restore_hw(flags) local_irq_restore_hw_notrace(flags) +#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */ + +#else /* CONFIG_IPIPE */ + static inline void raw_local_irq_disable(void) { bfin_cli(); @@ -44,12 +188,6 @@ static inline void raw_local_irq_enable(void) #define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0) -static inline void raw_local_irq_restore(unsigned long flags) -{ - if (!raw_irqs_disabled_flags(flags)) - raw_local_irq_enable(); -} - static inline unsigned long __raw_local_irq_save(void) { unsigned long flags = bfin_cli(); @@ -60,4 +198,18 @@ static inline unsigned long __raw_local_irq_save(void) } #define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0) +#define local_irq_save_hw(flags) raw_local_irq_save(flags) +#define local_irq_restore_hw(flags) raw_local_irq_restore(flags) +#define local_irq_enable_hw() raw_local_irq_enable() +#define local_irq_disable_hw() raw_local_irq_disable() +#define irqs_disabled_hw() irqs_disabled() + +#endif /* !CONFIG_IPIPE */ + +static inline void raw_local_irq_restore(unsigned long flags) +{ + if (!raw_irqs_disabled_flags(flags)) + raw_local_irq_enable(); +} + #endif diff --git a/arch/blackfin/include/asm/kmap_types.h b/arch/blackfin/include/asm/kmap_types.h index 0a88622..3575c64 100644 --- a/arch/blackfin/include/asm/kmap_types.h +++ b/arch/blackfin/include/asm/kmap_types.h @@ -1,6 +1 @@ -#ifndef _ASM_KMAP_TYPES_H -#define _ASM_KMAP_TYPES_H - #include <asm-generic/kmap_types.h> - -#endif diff --git a/arch/blackfin/include/asm/local.h b/arch/blackfin/include/asm/local.h index 75afffb..c11c530 100644 --- a/arch/blackfin/include/asm/local.h +++ b/arch/blackfin/include/asm/local.h @@ -1,6 +1 @@ -#ifndef __BLACKFIN_LOCAL_H -#define __BLACKFIN_LOCAL_H - #include <asm-generic/local.h> - -#endif /* __BLACKFIN_LOCAL_H */ diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h index 61f7487..4179e32 100644 --- a/arch/blackfin/include/asm/mem_init.h +++ b/arch/blackfin/include/asm/mem_init.h @@ -59,7 +59,7 @@ #define SDRAM_tRP TRP_1 #define SDRAM_tRP_num 1 #define SDRAM_tRAS TRAS_4 -#define SDRAM_tRAS_num 3 +#define SDRAM_tRAS_num 4 #define SDRAM_tRCD TRCD_1 #define SDRAM_tWR TWR_2 #endif @@ -89,6 +89,85 @@ #endif #endif +/* + * The BF526-EZ-Board changed SDRAM chips between revisions, + * so we use below timings to accommodate both. + */ +#if defined(CONFIG_MEM_MT48H32M16LFCJ_75) +#if (CONFIG_SCLK_HZ > 119402985) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_8 +#define SDRAM_tRAS_num 8 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_7 +#define SDRAM_tRAS_num 7 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_6 +#define SDRAM_tRAS_num 6 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_5 +#define SDRAM_tRAS_num 5 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_4 +#define SDRAM_tRAS_num 4 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_4 +#define SDRAM_tRAS_num 4 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_3 +#define SDRAM_tRAS_num 3 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) +#define SDRAM_tRP TRP_1 +#define SDRAM_tRP_num 1 +#define SDRAM_tRAS TRAS_3 +#define SDRAM_tRAS_num 3 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ <= 29850746) +#define SDRAM_tRP TRP_1 +#define SDRAM_tRP_num 1 +#define SDRAM_tRAS TRAS_2 +#define SDRAM_tRAS_num 2 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#endif + #if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ defined(CONFIG_MEM_MT48LC8M32B2B5_7) /*SDRAM INFORMATION: */ @@ -109,6 +188,13 @@ #define SDRAM_CL CL_3 #endif +#if defined(CONFIG_MEM_MT48H32M16LFCJ_75) + /*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ +#define SDRAM_CL CL_2 +#endif + #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC /* Equation from section 17 (p17-46) of BF533 HRM */ diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h index e92b310..5e21627 100644 --- a/arch/blackfin/include/asm/mem_map.h +++ b/arch/blackfin/include/asm/mem_map.h @@ -1,87 +1,84 @@ /* - * mem_map.h - * Common header file for blackfin family of processors. + * Common Blackfin memory map * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_H_ -#define _MEM_MAP_H_ +#ifndef __BFIN_MEM_MAP_H__ +#define __BFIN_MEM_MAP_H__ #include <mach/mem_map.h> -#ifndef __ASSEMBLY__ +/* Every Blackfin so far has MMRs like this */ +#ifndef COREMMR_BASE +# define COREMMR_BASE 0xFFE00000 +#endif +#ifndef SYSMMR_BASE +# define SYSMMR_BASE 0xFFC00000 +#endif -#ifdef CONFIG_SMP -static inline ulong get_l1_scratch_start_cpu(int cpu) -{ - return (cpu) ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; -} -static inline ulong get_l1_code_start_cpu(int cpu) -{ - return (cpu) ? COREB_L1_CODE_START : COREA_L1_CODE_START; -} -static inline ulong get_l1_data_a_start_cpu(int cpu) -{ - return (cpu) ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START; -} -static inline ulong get_l1_data_b_start_cpu(int cpu) -{ - return (cpu) ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START; -} +/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */ +#ifndef L1_SCRATCH_START +# define L1_SCRATCH_START 0xFFB00000 +# define L1_SCRATCH_LENGTH 0x1000 +#endif -static inline ulong get_l1_scratch_start(void) -{ - return get_l1_scratch_start_cpu(blackfin_core_id()); -} -static inline ulong get_l1_code_start(void) -{ - return get_l1_code_start_cpu(blackfin_core_id()); -} -static inline ulong get_l1_data_a_start(void) -{ - return get_l1_data_a_start_cpu(blackfin_core_id()); -} -static inline ulong get_l1_data_b_start(void) -{ - return get_l1_data_b_start_cpu(blackfin_core_id()); -} +/* Most parts lack on-chip L2 SRAM */ +#ifndef L2_START +# define L2_START 0 +# define L2_LENGTH 0 +#endif + +/* Most parts lack on-chip L1 ROM */ +#ifndef L1_ROM_START +# define L1_ROM_START 0 +# define L1_ROM_LENGTH 0 +#endif + +/* Allow wonky SMP ports to override this */ +#ifndef GET_PDA_SAFE +# define GET_PDA_SAFE(preg) \ + preg.l = _cpu_pda; \ + preg.h = _cpu_pda; +# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) -#else /* !CONFIG_SMP */ +# ifndef __ASSEMBLY__ -static inline ulong get_l1_scratch_start_cpu(int cpu) +static inline unsigned long get_l1_scratch_start_cpu(int cpu) { return L1_SCRATCH_START; } -static inline ulong get_l1_code_start_cpu(int cpu) +static inline unsigned long get_l1_code_start_cpu(int cpu) { return L1_CODE_START; } -static inline ulong get_l1_data_a_start_cpu(int cpu) +static inline unsigned long get_l1_data_a_start_cpu(int cpu) { return L1_DATA_A_START; } -static inline ulong get_l1_data_b_start_cpu(int cpu) +static inline unsigned long get_l1_data_b_start_cpu(int cpu) { return L1_DATA_B_START; } -static inline ulong get_l1_scratch_start(void) +static inline unsigned long get_l1_scratch_start(void) { return get_l1_scratch_start_cpu(0); } -static inline ulong get_l1_code_start(void) +static inline unsigned long get_l1_code_start(void) { return get_l1_code_start_cpu(0); } -static inline ulong get_l1_data_a_start(void) +static inline unsigned long get_l1_data_a_start(void) { return get_l1_data_a_start_cpu(0); } -static inline ulong get_l1_data_b_start(void) +static inline unsigned long get_l1_data_b_start(void) { return get_l1_data_b_start_cpu(0); } -#endif /* CONFIG_SMP */ -#endif /* __ASSEMBLY__ */ +# endif /* __ASSEMBLY__ */ +#endif /* !GET_PDA_SAFE */ -#endif /* _MEM_MAP_H_ */ +#endif diff --git a/arch/blackfin/include/asm/mman.h b/arch/blackfin/include/asm/mman.h index b58f5ad..8eebf89 100644 --- a/arch/blackfin/include/asm/mman.h +++ b/arch/blackfin/include/asm/mman.h @@ -1,43 +1 @@ -#ifndef __BFIN_MMAN_H__ -#define __BFIN_MMAN_H__ - -#define PROT_READ 0x1 /* page can be read */ -#define PROT_WRITE 0x2 /* page can be written */ -#define PROT_EXEC 0x4 /* page can be executed */ -#define PROT_SEM 0x8 /* page may be used for atomic ops */ -#define PROT_NONE 0x0 /* page can not be accessed */ -#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */ -#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */ - -#define MAP_SHARED 0x01 /* Share changes */ -#define MAP_PRIVATE 0x02 /* Changes are private */ -#define MAP_TYPE 0x0f /* Mask for type of mapping */ -#define MAP_FIXED 0x10 /* Interpret addr exactly */ -#define MAP_ANONYMOUS 0x20 /* don't use a file */ - -#define MAP_GROWSDOWN 0x0100 /* stack-like segment */ -#define MAP_DENYWRITE 0x0800 /* ETXTBSY */ -#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ -#define MAP_LOCKED 0x2000 /* pages are locked */ -#define MAP_NORESERVE 0x4000 /* don't check for reservations */ -#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ -#define MAP_NONBLOCK 0x10000 /* do not block on IO */ - -#define MS_ASYNC 1 /* sync memory asynchronously */ -#define MS_INVALIDATE 2 /* invalidate the caches */ -#define MS_SYNC 4 /* synchronous memory sync */ - -#define MCL_CURRENT 1 /* lock all current mappings */ -#define MCL_FUTURE 2 /* lock all future mappings */ - -#define MADV_NORMAL 0x0 /* default page-in behavior */ -#define MADV_RANDOM 0x1 /* page-in minimum required */ -#define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */ -#define MADV_WILLNEED 0x3 /* pre-fault pages */ -#define MADV_DONTNEED 0x4 /* discard these pages */ - -/* compatibility flags */ -#define MAP_ANON MAP_ANONYMOUS -#define MAP_FILE 0 - -#endif /* __BFIN_MMAN_H__ */ +#include <asm-generic/mman.h> diff --git a/arch/blackfin/include/asm/msgbuf.h b/arch/blackfin/include/asm/msgbuf.h index 6fcbe8c..809134c 100644 --- a/arch/blackfin/include/asm/msgbuf.h +++ b/arch/blackfin/include/asm/msgbuf.h @@ -1,31 +1 @@ -#ifndef _BFIN_MSGBUF_H -#define _BFIN_MSGBUF_H - -/* - * The msqid64_ds structure for bfin architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct msqid64_ds { - struct ipc64_perm msg_perm; - __kernel_time_t msg_stime; /* last msgsnd time */ - unsigned long __unused1; - __kernel_time_t msg_rtime; /* last msgrcv time */ - unsigned long __unused2; - __kernel_time_t msg_ctime; /* last change time */ - unsigned long __unused3; - unsigned long msg_cbytes; /* current number of bytes on queue */ - unsigned long msg_qnum; /* number of messages in queue */ - unsigned long msg_qbytes; /* max number of bytes on queue */ - __kernel_pid_t msg_lspid; /* pid of last msgsnd */ - __kernel_pid_t msg_lrpid; /* last receive pid */ - unsigned long __unused4; - unsigned long __unused5; -}; - -#endif /* _BFIN_MSGBUF_H */ +#include <asm-generic/msgbuf.h> diff --git a/arch/blackfin/include/asm/mutex.h b/arch/blackfin/include/asm/mutex.h index 5d39925..5cc641c 100644 --- a/arch/blackfin/include/asm/mutex.h +++ b/arch/blackfin/include/asm/mutex.h @@ -10,7 +10,7 @@ #define _ASM_MUTEX_H #ifndef CONFIG_SMP -#include <asm-generic/mutex-dec.h> +#include <asm-generic/mutex.h> #else static inline void diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h index 3ea2016..29dcf75 100644 --- a/arch/blackfin/include/asm/page.h +++ b/arch/blackfin/include/asm/page.h @@ -1,88 +1,7 @@ #ifndef _BLACKFIN_PAGE_H #define _BLACKFIN_PAGE_H -/* PAGE_SHIFT determines the page size */ +#include <asm-generic/page.h> +#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) -#define PAGE_SHIFT 12 -#ifdef __ASSEMBLY__ -#define PAGE_SIZE (1 << PAGE_SHIFT) -#else -#define PAGE_SIZE (1UL << PAGE_SHIFT) #endif -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#include <asm/setup.h> - -#ifndef __ASSEMBLY__ - -#define get_user_page(vaddr) __get_free_page(GFP_KERNEL) -#define free_user_page(page, addr) free_page(addr) - -#define clear_page(page) memset((page), 0, PAGE_SIZE) -#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) - -#define clear_user_page(page, vaddr,pg) clear_page(page) -#define copy_user_page(to, from, vaddr,pg) copy_page(to, from) - -/* - * These are used to make use of C type-checking.. - */ -typedef struct { - unsigned long pte; -} pte_t; -typedef struct { - unsigned long pmd[16]; -} pmd_t; -typedef struct { - unsigned long pgd; -} pgd_t; -typedef struct { - unsigned long pgprot; -} pgprot_t; -typedef struct page *pgtable_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((&x)->pmd[0]) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -extern unsigned long memory_start; -extern unsigned long memory_end; - -#endif /* !__ASSEMBLY__ */ - -#include <asm/page_offset.h> -#include <asm/io.h> - -#define PAGE_OFFSET (PAGE_OFFSET_RAW) - -#ifndef __ASSEMBLY__ - -#define __pa(vaddr) virt_to_phys((void *)(vaddr)) -#define __va(paddr) phys_to_virt((unsigned long)(paddr)) - -#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) - -#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT) -#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT) -#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) -#define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) -#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) - -#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn)) -#define page_to_pfn(page) virt_to_pfn(page_to_virt(page)) -#define pfn_valid(pfn) ((pfn) < max_mapnr) - -#define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \ - ((void *)(kaddr) < (void *)memory_end)) - -#include <asm-generic/getorder.h> - -#endif /* __ASSEMBLY__ */ - -#endif /* _BLACKFIN_PAGE_H */ diff --git a/arch/blackfin/include/asm/param.h b/arch/blackfin/include/asm/param.h index 41564a6..965d454 100644 --- a/arch/blackfin/include/asm/param.h +++ b/arch/blackfin/include/asm/param.h @@ -1,22 +1 @@ -#ifndef _BLACKFIN_PARAM_H -#define _BLACKFIN_PARAM_H - -#ifdef __KERNEL__ -#define HZ CONFIG_HZ -#define USER_HZ 100 -#define CLOCKS_PER_SEC (USER_HZ) -#endif - -#ifndef HZ -#define HZ 100 -#endif - -#define EXEC_PAGESIZE 4096 - -#ifndef NOGROUP -#define NOGROUP (-1) -#endif - -#define MAXHOSTNAMELEN 64 /* max length of hostname */ - -#endif /* _BLACKFIN_PARAM_H */ +#include <asm-generic/param.h> diff --git a/arch/blackfin/include/asm/percpu.h b/arch/blackfin/include/asm/percpu.h index c94c7bc..06a959d 100644 --- a/arch/blackfin/include/asm/percpu.h +++ b/arch/blackfin/include/asm/percpu.h @@ -1,6 +1 @@ -#ifndef __ARCH_BLACKFIN_PERCPU__ -#define __ARCH_BLACKFIN_PERCPU__ - #include <asm-generic/percpu.h> - -#endif /* __ARCH_BLACKFIN_PERCPU__ */ diff --git a/arch/blackfin/include/asm/pgalloc.h b/arch/blackfin/include/asm/pgalloc.h index c686e05..f261cb7 100644 --- a/arch/blackfin/include/asm/pgalloc.h +++ b/arch/blackfin/include/asm/pgalloc.h @@ -1,8 +1 @@ -#ifndef _BLACKFIN_PGALLOC_H -#define _BLACKFIN_PGALLOC_H - -#include <asm/setup.h> - -#define check_pgt_cache() do { } while (0) - -#endif /* _BLACKFIN_PGALLOC_H */ +#include <asm-generic/pgalloc.h> diff --git a/arch/blackfin/include/asm/poll.h b/arch/blackfin/include/asm/poll.h index 94cc263..a055667 100644 --- a/arch/blackfin/include/asm/poll.h +++ b/arch/blackfin/include/asm/poll.h @@ -1,24 +1,9 @@ #ifndef __BFIN_POLL_H #define __BFIN_POLL_H -#define POLLIN 1 -#define POLLPRI 2 -#define POLLOUT 4 -#define POLLERR 8 -#define POLLHUP 16 -#define POLLNVAL 32 -#define POLLRDNORM 64 -#define POLLWRNORM POLLOUT -#define POLLRDBAND 128 +#define POLLWRNORM 4 /* POLLOUT */ #define POLLWRBAND 256 -#define POLLMSG 0x0400 -#define POLLREMOVE 0x1000 -#define POLLRDHUP 0x2000 -struct pollfd { - int fd; - short events; - short revents; -}; +#include <asm-generic/poll.h> -#endif /* __BFIN_POLL_H */ +#endif diff --git a/arch/blackfin/include/asm/posix_types.h b/arch/blackfin/include/asm/posix_types.h index 23aa1f8..80c9d64 100644 --- a/arch/blackfin/include/asm/posix_types.h +++ b/arch/blackfin/include/asm/posix_types.h @@ -1,61 +1,27 @@ #ifndef __ARCH_BFIN_POSIX_TYPES_H #define __ARCH_BFIN_POSIX_TYPES_H -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned long __kernel_ino_t; typedef unsigned short __kernel_mode_t; +#define __kernel_mode_t __kernel_mode_t + typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; +#define __kernel_nlink_t __kernel_nlink_t + typedef unsigned int __kernel_ipc_pid_t; -typedef unsigned int __kernel_uid_t; -typedef unsigned int __kernel_gid_t; +#define __kernel_ipc_pid_t __kernel_ipc_pid_t + typedef unsigned long __kernel_size_t; typedef long __kernel_ssize_t; typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_timer_t; -typedef int __kernel_clockid_t; -typedef int __kernel_daddr_t; -typedef char *__kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; +#define __kernel_size_t __kernel_size_t typedef unsigned short __kernel_old_uid_t; typedef unsigned short __kernel_old_gid_t; -typedef unsigned short __kernel_old_dev_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif +#define __kernel_old_uid_t __kernel_old_uid_t -typedef struct { - int val[2]; -} __kernel_fsid_t; - -#if defined(__KERNEL__) - -#undef __FD_SET -#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) - -#undef __FD_CLR -#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) - -#undef __FD_ISSET -#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) +typedef unsigned short __kernel_old_dev_t; +#define __kernel_old_dev_t __kernel_old_dev_t -#endif /* defined(__KERNEL__) */ +#include <asm-generic/posix_types.h> #endif diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h index 3040415..d0be99b 100644 --- a/arch/blackfin/include/asm/processor.h +++ b/arch/blackfin/include/asm/processor.h @@ -7,9 +7,8 @@ */ #define current_text_addr() ({ __label__ _l; _l: &&_l;}) +#include <asm/ptrace.h> #include <asm/blackfin.h> -#include <asm/segment.h> -#include <linux/compiler.h> static inline unsigned long rdusp(void) { @@ -59,36 +58,8 @@ struct thread_struct { PS_S, 0, 0 \ } -/* - * Do necessary setup to start up a newly executed thread. - * - * pass the data segment into user programs if it exists, - * it can't hurt anything as far as I can tell - */ -#ifndef CONFIG_SMP -#define start_thread(_regs, _pc, _usp) \ -do { \ - set_fs(USER_DS); \ - (_regs)->pc = (_pc); \ - if (current->mm) \ - (_regs)->p5 = current->mm->start_data; \ - task_thread_info(current)->l1_task_info.stack_start \ - = (void *)current->mm->context.stack_start; \ - task_thread_info(current)->l1_task_info.lowest_sp = (void *)(_usp); \ - memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info, \ - sizeof(*L1_SCRATCH_TASK_INFO)); \ - wrusp(_usp); \ -} while(0) -#else -#define start_thread(_regs, _pc, _usp) \ -do { \ - set_fs(USER_DS); \ - (_regs)->pc = (_pc); \ - if (current->mm) \ - (_regs)->p5 = current->mm->start_data; \ - wrusp(_usp); \ -} while (0) -#endif +extern void start_thread(struct pt_regs *regs, unsigned long new_ip, + unsigned long new_sp); /* Forward declaration, a strange C thing */ struct task_struct; diff --git a/arch/blackfin/include/asm/resource.h b/arch/blackfin/include/asm/resource.h index 091355a..04bc4db 100644 --- a/arch/blackfin/include/asm/resource.h +++ b/arch/blackfin/include/asm/resource.h @@ -1,6 +1 @@ -#ifndef _BFIN_RESOURCE_H -#define _BFIN_RESOURCE_H - #include <asm-generic/resource.h> - -#endif /* _BFIN_RESOURCE_H */ diff --git a/arch/blackfin/include/asm/sembuf.h b/arch/blackfin/include/asm/sembuf.h index 18deb5c..7673b83 100644 --- a/arch/blackfin/include/asm/sembuf.h +++ b/arch/blackfin/include/asm/sembuf.h @@ -1,25 +1 @@ -#ifndef _BFIN_SEMBUF_H -#define _BFIN_SEMBUF_H - -/* - * The semid64_ds structure for bfin architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct semid64_ds { - struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ - __kernel_time_t sem_otime; /* last semop time */ - unsigned long __unused1; - __kernel_time_t sem_ctime; /* last change time */ - unsigned long __unused2; - unsigned long sem_nsems; /* no. of semaphores in array */ - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _BFIN_SEMBUF_H */ +#include <asm-generic/sembuf.h> diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h index 3a47606..94a4a12 100644 --- a/arch/blackfin/include/asm/serial.h +++ b/arch/blackfin/include/asm/serial.h @@ -1,6 +1,2 @@ -/* - * include/asm-blackfin/serial.h - */ - +#include <asm-generic/serial.h> #define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH -#define BASE_BAUD (1843200 / 16) diff --git a/arch/blackfin/include/asm/setup.h b/arch/blackfin/include/asm/setup.h index 01c8c6c..552df83 100644 --- a/arch/blackfin/include/asm/setup.h +++ b/arch/blackfin/include/asm/setup.h @@ -1,17 +1 @@ -/* -** asm/setup.h -- Definition of the Linux/bfin setup information -** -** This file is subject to the terms and conditions of the GNU General Public -** License. See the file COPYING in the main directory of this archive -** for more details. -** -** Copyright Lineo, Inc 2001 Tony Kou -** -*/ - -#ifndef _BFIN_SETUP_H -#define _BFIN_SETUP_H - -#define COMMAND_LINE_SIZE 512 - -#endif /* _BFIN_SETUP_H */ +#include <asm-generic/setup.h> diff --git a/arch/blackfin/include/asm/shmbuf.h b/arch/blackfin/include/asm/shmbuf.h index 6124363..83c05fc 100644 --- a/arch/blackfin/include/asm/shmbuf.h +++ b/arch/blackfin/include/asm/shmbuf.h @@ -1,42 +1 @@ -#ifndef _BFIN_SHMBUF_H -#define _BFIN_SHMBUF_H - -/* - * The shmid64_ds structure for bfin architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct shmid64_ds { - struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ - __kernel_time_t shm_atime; /* last attach time */ - unsigned long __unused1; - __kernel_time_t shm_dtime; /* last detach time */ - unsigned long __unused2; - __kernel_time_t shm_ctime; /* last change time */ - unsigned long __unused3; - __kernel_pid_t shm_cpid; /* pid of creator */ - __kernel_pid_t shm_lpid; /* pid of last operator */ - unsigned long shm_nattch; /* no. of current attaches */ - unsigned long __unused4; - unsigned long __unused5; -}; - -struct shminfo64 { - unsigned long shmmax; - unsigned long shmmin; - unsigned long shmmni; - unsigned long shmseg; - unsigned long shmall; - unsigned long __unused1; - unsigned long __unused2; - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _BFIN_SHMBUF_H */ +#include <asm-generic/shmbuf.h> diff --git a/arch/blackfin/include/asm/shmparam.h b/arch/blackfin/include/asm/shmparam.h index 3c03906..93f30de 100644 --- a/arch/blackfin/include/asm/shmparam.h +++ b/arch/blackfin/include/asm/shmparam.h @@ -1,6 +1 @@ -#ifndef _BFIN_SHMPARAM_H -#define _BFIN_SHMPARAM_H - -#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ - -#endif /* _BFIN_SHMPARAM_H */ +#include <asm-generic/shmparam.h> diff --git a/arch/blackfin/include/asm/signal.h b/arch/blackfin/include/asm/signal.h index 2eea907..77a3bf3 100644 --- a/arch/blackfin/include/asm/signal.h +++ b/arch/blackfin/include/asm/signal.h @@ -1,160 +1,7 @@ #ifndef _BLACKFIN_SIGNAL_H #define _BLACKFIN_SIGNAL_H -#include <linux/types.h> +#define SA_RESTORER 0x04000000 +#include <asm-generic/signal.h> -/* Avoid too many header ordering problems. */ -struct siginfo; - -#ifdef __KERNEL__ -/* Most things should be clean enough to redefine this at will, if care - is taken to make libc match. */ - -#define _NSIG 64 -#define _NSIG_BPW 32 -#define _NSIG_WORDS (_NSIG / _NSIG_BPW) - -typedef unsigned long old_sigset_t; /* at least 32 bits */ - -typedef struct { - unsigned long sig[_NSIG_WORDS]; -} sigset_t; - -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -#define NSIG 32 -typedef unsigned long sigset_t; - -#endif /* __KERNEL__ */ - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX _NSIG - -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 /* not supported yet */ -#define SA_SIGINFO 0x00000004 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - -/* - * sigaltstack controls - */ -#define SS_ONSTACK 1 -#define SS_DISABLE 2 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#include <asm-generic/signal-defs.h> - -#ifdef __KERNEL__ -struct old_sigaction { - __sighandler_t sa_handler; - old_sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer) (void); -}; - -struct sigaction { - __sighandler_t sa_handler; - unsigned long sa_flags; - void (*sa_restorer) (void); - sigset_t sa_mask; /* mask last for extensibility */ -}; - -struct k_sigaction { - struct sigaction sa; -}; -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -struct sigaction { - union { - __sighandler_t _sa_handler; - void (*_sa_sigaction) (int, struct siginfo *, void *); - } _u; - sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer) (void); -}; - -#define sa_handler _u._sa_handler -#define sa_sigaction _u._sa_sigaction - -#endif /* __KERNEL__ */ - -typedef struct sigaltstack { - void __user *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - -#ifdef __KERNEL__ - -#include <asm/sigcontext.h> -#undef __HAVE_ARCH_SIG_BITOPS - -#define ptrace_signal_deliver(regs, cookie) do { } while (0) - -#endif /* __KERNEL__ */ - -#endif /* _BLACKFIN_SIGNAL_H */ +#endif diff --git a/arch/blackfin/include/asm/socket.h b/arch/blackfin/include/asm/socket.h index fac7fe9..6b71384 100644 --- a/arch/blackfin/include/asm/socket.h +++ b/arch/blackfin/include/asm/socket.h @@ -1,59 +1 @@ -#ifndef _ASM_SOCKET_H -#define _ASM_SOCKET_H - -#include <asm/sockios.h> - -/* For setsockoptions(2) */ -#define SOL_SOCKET 1 - -#define SO_DEBUG 1 -#define SO_REUSEADDR 2 -#define SO_TYPE 3 -#define SO_ERROR 4 -#define SO_DONTROUTE 5 -#define SO_BROADCAST 6 -#define SO_SNDBUF 7 -#define SO_RCVBUF 8 -#define SO_SNDBUFFORCE 32 -#define SO_RCVBUFFORCE 33 -#define SO_KEEPALIVE 9 -#define SO_OOBINLINE 10 -#define SO_NO_CHECK 11 -#define SO_PRIORITY 12 -#define SO_LINGER 13 -#define SO_BSDCOMPAT 14 -/* To add :#define SO_REUSEPORT 15 */ -#define SO_PASSCRED 16 -#define SO_PEERCRED 17 -#define SO_RCVLOWAT 18 -#define SO_SNDLOWAT 19 -#define SO_RCVTIMEO 20 -#define SO_SNDTIMEO 21 - -/* Security levels - as per NRL IPv6 - don't actually do anything */ -#define SO_SECURITY_AUTHENTICATION 22 -#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 -#define SO_SECURITY_ENCRYPTION_NETWORK 24 - -#define SO_BINDTODEVICE 25 - -/* Socket filtering */ -#define SO_ATTACH_FILTER 26 -#define SO_DETACH_FILTER 27 - -#define SO_PEERNAME 28 -#define SO_TIMESTAMP 29 -#define SCM_TIMESTAMP SO_TIMESTAMP - -#define SO_ACCEPTCONN 30 -#define SO_PEERSEC 31 -#define SO_PASSSEC 34 -#define SO_TIMESTAMPNS 35 -#define SCM_TIMESTAMPNS SO_TIMESTAMPNS - -#define SO_MARK 36 - -#define SO_TIMESTAMPING 37 -#define SCM_TIMESTAMPING SO_TIMESTAMPING - -#endif /* _ASM_SOCKET_H */ +#include <asm-generic/socket.h> diff --git a/arch/blackfin/include/asm/sockios.h b/arch/blackfin/include/asm/sockios.h index 426b89b..def6d47 100644 --- a/arch/blackfin/include/asm/sockios.h +++ b/arch/blackfin/include/asm/sockios.h @@ -1,13 +1 @@ -#ifndef __ARCH_BFIN_SOCKIOS__ -#define __ARCH_BFIN_SOCKIOS__ - -/* Socket-level I/O control calls. */ -#define FIOSETOWN 0x8901 -#define SIOCSPGRP 0x8902 -#define FIOGETOWN 0x8903 -#define SIOCGPGRP 0x8904 -#define SIOCATMARK 0x8905 -#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ -#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ - -#endif /* __ARCH_BFIN_SOCKIOS__ */ +#include <asm-generic/sockios.h> diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h index 0249ac3..d6ff4b5 100644 --- a/arch/blackfin/include/asm/spinlock.h +++ b/arch/blackfin/include/asm/spinlock.h @@ -1,6 +1,10 @@ #ifndef __BFIN_SPINLOCK_H #define __BFIN_SPINLOCK_H +#ifndef CONFIG_SMP +# include <asm-generic/spinlock.h> +#else + #include <asm/atomic.h> asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr); @@ -86,4 +90,6 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw) #define _raw_read_relax(lock) cpu_relax() #define _raw_write_relax(lock) cpu_relax() +#endif + #endif /* !__BFIN_SPINLOCK_H */ diff --git a/arch/blackfin/include/asm/statfs.h b/arch/blackfin/include/asm/statfs.h index 3506720..0b91fe1 100644 --- a/arch/blackfin/include/asm/statfs.h +++ b/arch/blackfin/include/asm/statfs.h @@ -1,6 +1 @@ -#ifndef _BFIN_STATFS_H -#define _BFIN_STATFS_H - #include <asm-generic/statfs.h> - -#endif /* _BFIN_STATFS_H */ diff --git a/arch/blackfin/include/asm/swab.h b/arch/blackfin/include/asm/swab.h index 6403ad2..d442113 100644 --- a/arch/blackfin/include/asm/swab.h +++ b/arch/blackfin/include/asm/swab.h @@ -2,11 +2,7 @@ #define _BLACKFIN_SWAB_H #include <linux/types.h> -#include <linux/compiler.h> - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __SWAB_64_THRU_32__ -#endif +#include <asm-generic/swab.h> #ifdef __GNUC__ diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h index 294dbda..85e8f16 100644 --- a/arch/blackfin/include/asm/system.h +++ b/arch/blackfin/include/asm/system.h @@ -135,11 +135,13 @@ struct __xchg_dummy { }; #define __xg(x) ((volatile struct __xchg_dummy *)(x)) +#include <mach/blackfin.h> + static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) { unsigned long tmp = 0; - unsigned long flags = 0; + unsigned long flags; local_irq_save_hw(flags); diff --git a/arch/blackfin/include/asm/termbits.h b/arch/blackfin/include/asm/termbits.h index f37feb7..3935b10 100644 --- a/arch/blackfin/include/asm/termbits.h +++ b/arch/blackfin/include/asm/termbits.h @@ -1,198 +1 @@ -#ifndef __ARCH_BFIN_TERMBITS_H__ -#define __ARCH_BFIN_TERMBITS_H__ - -#include <linux/posix_types.h> - -typedef unsigned char cc_t; -typedef unsigned int speed_t; -typedef unsigned int tcflag_t; - -#define NCCS 19 -struct termios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ -}; - -struct termios2 { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -struct ktermios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -/* c_cc characters */ -#define VINTR 0 -#define VQUIT 1 -#define VERASE 2 -#define VKILL 3 -#define VEOF 4 -#define VTIME 5 -#define VMIN 6 -#define VSWTC 7 -#define VSTART 8 -#define VSTOP 9 -#define VSUSP 10 -#define VEOL 11 -#define VREPRINT 12 -#define VDISCARD 13 -#define VWERASE 14 -#define VLNEXT 15 -#define VEOL2 16 - -/* c_iflag bits */ -#define IGNBRK 0000001 -#define BRKINT 0000002 -#define IGNPAR 0000004 -#define PARMRK 0000010 -#define INPCK 0000020 -#define ISTRIP 0000040 -#define INLCR 0000100 -#define IGNCR 0000200 -#define ICRNL 0000400 -#define IUCLC 0001000 -#define IXON 0002000 -#define IXANY 0004000 -#define IXOFF 0010000 -#define IMAXBEL 0020000 -#define IUTF8 0040000 - -/* c_oflag bits */ -#define OPOST 0000001 -#define OLCUC 0000002 -#define ONLCR 0000004 -#define OCRNL 0000010 -#define ONOCR 0000020 -#define ONLRET 0000040 -#define OFILL 0000100 -#define OFDEL 0000200 -#define NLDLY 0000400 -#define NL0 0000000 -#define NL1 0000400 -#define CRDLY 0003000 -#define CR0 0000000 -#define CR1 0001000 -#define CR2 0002000 -#define CR3 0003000 -#define TABDLY 0014000 -#define TAB0 0000000 -#define TAB1 0004000 -#define TAB2 0010000 -#define TAB3 0014000 -#define XTABS 0014000 -#define BSDLY 0020000 -#define BS0 0000000 -#define BS1 0020000 -#define VTDLY 0040000 -#define VT0 0000000 -#define VT1 0040000 -#define FFDLY 0100000 -#define FF0 0000000 -#define FF1 0100000 - -/* c_cflag bit meaning */ -#define CBAUD 0010017 -#define B0 0000000 /* hang up */ -#define B50 0000001 -#define B75 0000002 -#define B110 0000003 -#define B134 0000004 -#define B150 0000005 -#define B200 0000006 -#define B300 0000007 -#define B600 0000010 -#define B1200 0000011 -#define B1800 0000012 -#define B2400 0000013 -#define B4800 0000014 -#define B9600 0000015 -#define B19200 0000016 -#define B38400 0000017 -#define EXTA B19200 -#define EXTB B38400 -#define CSIZE 0000060 -#define CS5 0000000 -#define CS6 0000020 -#define CS7 0000040 -#define CS8 0000060 -#define CSTOPB 0000100 -#define CREAD 0000200 -#define PARENB 0000400 -#define PARODD 0001000 -#define HUPCL 0002000 -#define CLOCAL 0004000 -#define CBAUDEX 0010000 -#define BOTHER 0010000 -#define B57600 0010001 -#define B115200 0010002 -#define B230400 0010003 -#define B460800 0010004 -#define B500000 0010005 -#define B576000 0010006 -#define B921600 0010007 -#define B1000000 0010010 -#define B1152000 0010011 -#define B1500000 0010012 -#define B2000000 0010013 -#define B2500000 0010014 -#define B3000000 0010015 -#define B3500000 0010016 -#define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate */ -#define CMSPAR 010000000000 /* mark or space (stick) parity */ -#define CRTSCTS 020000000000 /* flow control */ - -#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ - -/* c_lflag bits */ -#define ISIG 0000001 -#define ICANON 0000002 -#define XCASE 0000004 -#define ECHO 0000010 -#define ECHOE 0000020 -#define ECHOK 0000040 -#define ECHONL 0000100 -#define NOFLSH 0000200 -#define TOSTOP 0000400 -#define ECHOCTL 0001000 -#define ECHOPRT 0002000 -#define ECHOKE 0004000 -#define FLUSHO 0010000 -#define PENDIN 0040000 -#define IEXTEN 0100000 - -/* tcflow() and TCXONC use these */ -#define TCOOFF 0 -#define TCOON 1 -#define TCIOFF 2 -#define TCION 3 - -/* tcflush() and TCFLSH use these */ -#define TCIFLUSH 0 -#define TCOFLUSH 1 -#define TCIOFLUSH 2 - -/* tcsetattr uses these */ -#define TCSANOW 0 -#define TCSADRAIN 1 -#define TCSAFLUSH 2 - -#endif /* __ARCH_BFIN_TERMBITS_H__ */ +#include <asm-generic/termbits.h> diff --git a/arch/blackfin/include/asm/termios.h b/arch/blackfin/include/asm/termios.h index d50d063..280d78a 100644 --- a/arch/blackfin/include/asm/termios.h +++ b/arch/blackfin/include/asm/termios.h @@ -1,94 +1 @@ -#ifndef __BFIN_TERMIOS_H__ -#define __BFIN_TERMIOS_H__ - -#include <asm/termbits.h> -#include <asm/ioctls.h> - -struct winsize { - unsigned short ws_row; - unsigned short ws_col; - unsigned short ws_xpixel; - unsigned short ws_ypixel; -}; - -#define NCC 8 -struct termio { - unsigned short c_iflag; /* input mode flags */ - unsigned short c_oflag; /* output mode flags */ - unsigned short c_cflag; /* control mode flags */ - unsigned short c_lflag; /* local mode flags */ - unsigned char c_line; /* line discipline */ - unsigned char c_cc[NCC]; /* control characters */ -}; - -/* modem lines */ -#define TIOCM_LE 0x001 -#define TIOCM_DTR 0x002 -#define TIOCM_RTS 0x004 -#define TIOCM_ST 0x008 -#define TIOCM_SR 0x010 -#define TIOCM_CTS 0x020 -#define TIOCM_CAR 0x040 -#define TIOCM_RNG 0x080 -#define TIOCM_DSR 0x100 -#define TIOCM_CD TIOCM_CAR -#define TIOCM_RI TIOCM_RNG -#define TIOCM_OUT1 0x2000 -#define TIOCM_OUT2 0x4000 -#define TIOCM_LOOP 0x8000 - -/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ - -#ifdef __KERNEL__ - -/* intr=^C quit=^\ erase=del kill=^U - eof=^D vtime=\0 vmin=\1 sxtc=\0 - start=^Q stop=^S susp=^Z eol=\0 - reprint=^R discard=^U werase=^W lnext=^V - eol2=\0 -*/ -#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" - -/* - * Translate a "termio" structure into a "termios". Ugh. - */ -#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ - unsigned short __tmp; \ - get_user(__tmp,&(termio)->x); \ - *(unsigned short *) &(termios)->x = __tmp; \ -} - -#define user_termio_to_kernel_termios(termios, termio) \ -({ \ - SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ - copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ -}) - -/* - * Translate a "termios" structure into a "termio". Ugh. - */ -#define kernel_termios_to_user_termio(termio, termios) \ -({ \ - put_user((termios)->c_iflag, &(termio)->c_iflag); \ - put_user((termios)->c_oflag, &(termio)->c_oflag); \ - put_user((termios)->c_cflag, &(termio)->c_cflag); \ - put_user((termios)->c_lflag, &(termio)->c_lflag); \ - put_user((termios)->c_line, &(termio)->c_line); \ - copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ -}) - -#define user_termios_to_kernel_termios(k, u) \ - copy_from_user(k, u, sizeof(struct termios2)) -#define kernel_termios_to_user_termios(u, k) \ - copy_to_user(u, k, sizeof(struct termios2)) -#define user_termios_to_kernel_termios_1(k, u) \ - copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios_1(u, k) \ - copy_to_user(u, k, sizeof(struct termios)) - -#endif /* __KERNEL__ */ - -#endif /* __BFIN_TERMIOS_H__ */ +#include <asm-generic/termios.h> diff --git a/arch/blackfin/include/asm/tlbflush.h b/arch/blackfin/include/asm/tlbflush.h index 277b400..f1a06c0 100644 --- a/arch/blackfin/include/asm/tlbflush.h +++ b/arch/blackfin/include/asm/tlbflush.h @@ -1,56 +1 @@ -#ifndef _BLACKFIN_TLBFLUSH_H -#define _BLACKFIN_TLBFLUSH_H - -/* - * Copyright (C) 2000 Lineo, David McCullough <davidm@uclinux.org> - * Copyright (C) 2000-2002, Greg Ungerer <gerg@snapgear.com> - */ - -#include <asm/setup.h> - -/* - * flush all user-space atc entries. - */ -static inline void __flush_tlb(void) -{ - BUG(); -} - -static inline void __flush_tlb_one(unsigned long addr) -{ - BUG(); -} - -#define flush_tlb() __flush_tlb() - -/* - * flush all atc entries (both kernel and user-space entries). - */ -static inline void flush_tlb_all(void) -{ - BUG(); -} - -static inline void flush_tlb_mm(struct mm_struct *mm) -{ - BUG(); -} - -static inline void flush_tlb_page(struct vm_area_struct *vma, - unsigned long addr) -{ - BUG(); -} - -static inline void flush_tlb_range(struct mm_struct *mm, - unsigned long start, unsigned long end) -{ - BUG(); -} - -static inline void flush_tlb_kernel_page(unsigned long addr) -{ - BUG(); -} - -#endif +#include <asm-generic/tlbflush.h> diff --git a/arch/blackfin/include/asm/topology.h b/arch/blackfin/include/asm/topology.h index acee239..5428f33 100644 --- a/arch/blackfin/include/asm/topology.h +++ b/arch/blackfin/include/asm/topology.h @@ -1,6 +1 @@ -#ifndef _ASM_BLACKFIN_TOPOLOGY_H -#define _ASM_BLACKFIN_TOPOLOGY_H - #include <asm-generic/topology.h> - -#endif /* _ASM_BLACKFIN_TOPOLOGY_H */ diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h index 34f7295..3cdc454 100644 --- a/arch/blackfin/include/asm/traps.h +++ b/arch/blackfin/include/asm/traps.h @@ -111,9 +111,7 @@ level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" #define EXC_0x2A(level) \ "Instruction fetch misaligned address violation\n" \ - level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ - level " exception, the return address provided in RETX is the destination address which is\n" \ - level " misaligned, rather than the address of the offending instruction.\n" + level " - Attempted misaligned instruction cache fetch.\n" #define EXC_0x2B(level) \ "CPLB protection violation\n" \ level " - Illegal instruction fetch access (memory protection violation).\n" diff --git a/arch/blackfin/include/asm/types.h b/arch/blackfin/include/asm/types.h index 8441cbc..b9e79bc 100644 --- a/arch/blackfin/include/asm/types.h +++ b/arch/blackfin/include/asm/types.h @@ -1,36 +1 @@ -#ifndef _BFIN_TYPES_H -#define _BFIN_TYPES_H - -/* - * This file is never included by application software unless - * explicitly requested (e.g., via linux/types.h) in which case the - * application is Linux specific so (user-) name space pollution is - * not a major issue. However, for interoperability, libraries still - * need to be careful to avoid a name clashes. - */ -#include <asm-generic/int-ll64.h> - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -#endif /* __ASSEMBLY__ */ -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG 32 - -#ifndef __ASSEMBLY__ - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; -typedef u64 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* _BFIN_TYPES_H */ +#include <asm-generic/types.h> diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h index 8894e9f..2f469a1 100644 --- a/arch/blackfin/include/asm/uaccess.h +++ b/arch/blackfin/include/asm/uaccess.h @@ -265,4 +265,26 @@ __clear_user(void *to, unsigned long n) #define clear_user(to, n) __clear_user(to, n) +/* How to interpret these return values: + * CORE: can be accessed by core load or dma memcpy + * CORE_ONLY: can only be accessed by core load + * DMA: can only be accessed by dma memcpy + * IDMA: can only be accessed by interprocessor dma memcpy (BF561) + * ITEST: can be accessed by isram memcpy or dma memcpy + */ +enum { + BFIN_MEM_ACCESS_CORE = 0, + BFIN_MEM_ACCESS_CORE_ONLY, + BFIN_MEM_ACCESS_DMA, + BFIN_MEM_ACCESS_IDMA, + BFIN_MEM_ACCESS_ITEST, +}; +/** + * bfin_mem_access_type() - what kind of memory access is required + * @addr: the address to check + * @size: number of bytes needed + * @return: <0 is error, >=0 is BFIN_MEM_ACCESS_xxx enum (see above) + */ +int bfin_mem_access_type(unsigned long addr, unsigned long size); + #endif /* _BLACKFIN_UACCESS_H */ diff --git a/arch/blackfin/include/asm/ucontext.h b/arch/blackfin/include/asm/ucontext.h index 4a4e385..9bc07b9 100644 --- a/arch/blackfin/include/asm/ucontext.h +++ b/arch/blackfin/include/asm/ucontext.h @@ -1,17 +1 @@ -/** Changes made by Tony Kou Lineo Inc. May 2001 - * - * Based on: include/m68knommu/ucontext.h - */ - -#ifndef _BLACKFIN_UCONTEXT_H -#define _BLACKFIN_UCONTEXT_H - -struct ucontext { - unsigned long uc_flags; /* the others are necessary */ - struct ucontext *uc_link; - stack_t uc_stack; - struct sigcontext uc_mcontext; - sigset_t uc_sigmask; /* mask last for extensibility */ -}; - -#endif /* _BLACKFIN_UCONTEXT_H */ +#include <asm-generic/ucontext.h> diff --git a/arch/blackfin/include/asm/unaligned.h b/arch/blackfin/include/asm/unaligned.h index fd8a1d6..6cecbbb 100644 --- a/arch/blackfin/include/asm/unaligned.h +++ b/arch/blackfin/include/asm/unaligned.h @@ -1,11 +1 @@ -#ifndef _ASM_BLACKFIN_UNALIGNED_H -#define _ASM_BLACKFIN_UNALIGNED_H - -#include <linux/unaligned/le_struct.h> -#include <linux/unaligned/be_byteshift.h> -#include <linux/unaligned/generic.h> - -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le - -#endif /* _ASM_BLACKFIN_UNALIGNED_H */ +#include <asm-generic/unaligned.h> diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h index da35133..c8e7ee4 100644 --- a/arch/blackfin/include/asm/unistd.h +++ b/arch/blackfin/include/asm/unistd.h @@ -381,8 +381,9 @@ #define __NR_preadv 366 #define __NR_pwritev 367 #define __NR_rt_tgsigqueueinfo 368 +#define __NR_perf_counter_open 369 -#define __NR_syscall 369 +#define __NR_syscall 370 #define NR_syscalls __NR_syscall /* Old optional stuff no one actually uses */ diff --git a/arch/blackfin/include/asm/user.h b/arch/blackfin/include/asm/user.h index afe6a0e..4792a60 100644 --- a/arch/blackfin/include/asm/user.h +++ b/arch/blackfin/include/asm/user.h @@ -1,89 +1 @@ -#ifndef _BFIN_USER_H -#define _BFIN_USER_H - -/* Changes by Tony Kou Lineo, Inc. July, 2001 - * - * Based include/asm-m68knommu/user.h - * - */ - -/* Core file format: The core file is written in such a way that gdb - can understand it and provide useful information to the user (under - linux we use the 'trad-core' bfd). There are quite a number of - obstacles to being able to view the contents of the floating point - registers, and until these are solved you will not be able to view the - contents of them. Actually, you can read in the core file and look at - the contents of the user struct to find out what the floating point - registers contain. - The actual file contents are as follows: - UPAGE: 1 page consisting of a user struct that tells gdb what is present - in the file. Directly after this is a copy of the task_struct, which - is currently not used by gdb, but it may come in useful at some point. - All of the registers are stored as part of the upage. The upage should - always be only one page. - DATA: The data area is stored. We use current->end_text to - current->brk to pick up all of the user variables, plus any memory - that may have been malloced. No attempt is made to determine if a page - is demand-zero or if a page is totally unused, we just cover the entire - range. All of the addresses are rounded in such a way that an integral - number of pages is written. - STACK: We need the stack information in order to get a meaningful - backtrace. We need to write the data from (esp) to - current->start_stack, so we round each of these off in order to be able - to write an integer number of pages. - The minimum core file size is 3 pages, or 12288 bytes. -*/ -struct user_bfinfp_struct { -}; - -/* This is the old layout of "struct pt_regs" as of Linux 1.x, and - is still the layout used by user (the new pt_regs doesn't have - all registers). */ -struct user_regs_struct { - long r0, r1, r2, r3, r4, r5, r6, r7; - long p0, p1, p2, p3, p4, p5, usp, fp; - long i0, i1, i2, i3; - long l0, l1, l2, l3; - long b0, b1, b2, b3; - long m0, m1, m2, m3; - long a0w, a1w; - long a0x, a1x; - unsigned long rets; - unsigned long astat; - unsigned long pc; - unsigned long orig_p0; -}; - -/* When the kernel dumps core, it starts by dumping the user struct - - this will be used by gdb to figure out where the data and stack segments - are within the file, and what virtual addresses to use. */ - -struct user { -/* We start with the registers, to mimic the way that "memory" is returned - from the ptrace(3,...) function. */ - - struct user_regs_struct regs; /* Where the registers are actually stored */ - -/* The rest of this junk is to help gdb figure out what goes where */ - unsigned long int u_tsize; /* Text segment size (pages). */ - unsigned long int u_dsize; /* Data segment size (pages). */ - unsigned long int u_ssize; /* Stack segment size (pages). */ - unsigned long start_code; /* Starting virtual address of text. */ - unsigned long start_stack; /* Starting virtual address of stack area. - This is actually the bottom of the stack, - the top of the stack is always found in the - esp register. */ - long int signal; /* Signal that caused the core dump. */ - int reserved; /* No longer used */ - unsigned long u_ar0; - /* Used by gdb to help find the values for */ - /* the registers. */ - unsigned long magic; /* To uniquely identify a core file */ - char u_comm[32]; /* User command that was responsible */ -}; -#define NBPG PAGE_SIZE -#define UPAGES 1 -#define HOST_TEXT_START_ADDR (u.start_code) -#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) - -#endif +#include <asm-generic/user.h> diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index 3731088..141d928 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile @@ -20,7 +20,6 @@ obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o CFLAGS_REMOVE_ftrace.o = -pg obj-$(CONFIG_IPIPE) += ipipe.o -obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o obj-$(CONFIG_CPLB_INFO) += cplbinfo.o obj-$(CONFIG_MODULES) += module.o diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c index aa05e63..ed8392c 100644 --- a/arch/blackfin/kernel/bfin_ksyms.c +++ b/arch/blackfin/kernel/bfin_ksyms.c @@ -10,6 +10,7 @@ #include <linux/uaccess.h> #include <asm/cacheflush.h> +#include <asm/io.h> /* Allow people to have their own Blackfin exception handler in a module */ EXPORT_SYMBOL(bfin_return_from_exception); diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c index c006a44..36193ee 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c @@ -46,13 +46,13 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n"); -#ifdef CONFIG_BFIN_ICACHE +#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; #endif -#ifdef CONFIG_BFIN_DCACHE +#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE d_cache = CPLB_L1_CHBL; -#ifdef CONFIG_BFIN_WT +#ifdef CONFIG_BFIN_EXTMEM_WRITETROUGH d_cache |= CPLB_L1_AOW | CPLB_WT; #endif #endif @@ -91,9 +91,9 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) /* Cover L2 memory */ #if L2_LENGTH > 0 dcplb_tbl[cpu][i_d].addr = L2_START; - dcplb_tbl[cpu][i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB; + dcplb_tbl[cpu][i_d++].data = L2_DMEMORY; icplb_tbl[cpu][i_i].addr = L2_START; - icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB; + icplb_tbl[cpu][i_i++].data = L2_IMEMORY; #endif first_mask_dcplb = i_d; diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index 784923e..bcdfe9b 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -150,15 +150,19 @@ static noinline int dcplb_miss(unsigned int cpu) nr_dcplb_miss[cpu]++; d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; -#ifdef CONFIG_BFIN_DCACHE +#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE if (bfin_addr_dcacheable(addr)) { d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; -#ifdef CONFIG_BFIN_WT +# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH d_data |= CPLB_L1_AOW | CPLB_WT; -#endif +# endif } #endif - if (addr >= physical_mem_end) { + + if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { + addr = L2_START; + d_data = L2_DMEMORY; + } else if (addr >= physical_mem_end) { if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && (status & FAULT_USERSUPV)) { addr &= ~0x3fffff; @@ -235,7 +239,7 @@ static noinline int icplb_miss(unsigned int cpu) i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB; -#ifdef CONFIG_BFIN_ICACHE +#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE /* * Normal RAM, and possibly the reserved memory area, are * cacheable. @@ -245,7 +249,10 @@ static noinline int icplb_miss(unsigned int cpu) i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; #endif - if (addr >= physical_mem_end) { + if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { + addr = L2_START; + i_data = L2_IMEMORY; + } else if (addr >= physical_mem_end) { if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH && (status & FAULT_USERSUPV)) { addr &= ~(1 * 1024 * 1024 - 1); @@ -365,13 +372,18 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu) local_irq_save_hw(flags); current_rwx_mask[cpu] = masks; - d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; -#ifdef CONFIG_BFIN_DCACHE - d_data |= CPLB_L1_CHBL; -#ifdef CONFIG_BFIN_WT - d_data |= CPLB_L1_AOW | CPLB_WT; -#endif + if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { + addr = L2_START; + d_data = L2_DMEMORY; + } else { + d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; +#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE + d_data |= CPLB_L1_CHBL; +# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH + d_data |= CPLB_L1_AOW | CPLB_WT; +# endif #endif + } disable_dcplb(); for (i = first_mask_dcplb; i < first_switched_dcplb; i++) { diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c index d8cde1f..b8d2203 100644 --- a/arch/blackfin/kernel/ipipe.c +++ b/arch/blackfin/kernel/ipipe.c @@ -52,7 +52,7 @@ EXPORT_SYMBOL(__ipipe_freq_scale); atomic_t __ipipe_irq_lvdepth[IVG15 + 1]; -unsigned long __ipipe_irq_lvmask = __all_masked_irq_flags; +unsigned long __ipipe_irq_lvmask = bfin_no_irqs; EXPORT_SYMBOL(__ipipe_irq_lvmask); static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc) @@ -342,8 +342,3 @@ void ___ipipe_sync_pipeline(unsigned long syncmask) } EXPORT_SYMBOL(show_stack); - -#ifdef CONFIG_IPIPE_TRACE_MCOUNT -void notrace _mcount(void); -EXPORT_SYMBOL(_mcount); -#endif /* CONFIG_IPIPE_TRACE_MCOUNT */ diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c index 6e31e93..4b5fd36 100644 --- a/arch/blackfin/kernel/irqchip.c +++ b/arch/blackfin/kernel/irqchip.c @@ -38,38 +38,15 @@ #include <asm/pda.h> static atomic_t irq_err_count; -static spinlock_t irq_controller_lock; - -/* - * Dummy mask/unmask handler - */ -void dummy_mask_unmask_irq(unsigned int irq) -{ -} - void ack_bad_irq(unsigned int irq) { atomic_inc(&irq_err_count); printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq); } -static struct irq_chip bad_chip = { - .ack = dummy_mask_unmask_irq, - .mask = dummy_mask_unmask_irq, - .unmask = dummy_mask_unmask_irq, -}; - -static int bad_stats; static struct irq_desc bad_irq_desc = { - .status = IRQ_DISABLED, - .chip = &bad_chip, .handle_irq = handle_bad_irq, - .depth = 1, .lock = __SPIN_LOCK_UNLOCKED(irq_desc->lock), - .kstat_irqs = &bad_stats, -#ifdef CONFIG_SMP - .affinity = CPU_MASK_ALL -#endif }; #ifdef CONFIG_CPUMASK_OFFSTACK @@ -77,6 +54,7 @@ static struct irq_desc bad_irq_desc = { #error "Blackfin architecture does not support CONFIG_CPUMASK_OFFSTACK." #endif +#ifdef CONFIG_PROC_FS int show_interrupts(struct seq_file *p, void *v) { int i = *(loff_t *) v, j; @@ -108,50 +86,29 @@ int show_interrupts(struct seq_file *p, void *v) } return 0; } - -/* - * do_IRQ handles all hardware IRQs. Decoded IRQs should not - * come via this function. Instead, they should provide their - * own 'handler' - */ -#ifdef CONFIG_DO_IRQ_L1 -__attribute__((l1_text)) -#endif -asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) -{ - struct pt_regs *old_regs; - struct irq_desc *desc = irq_desc + irq; -#ifndef CONFIG_IPIPE - unsigned short pending, other_ints; #endif - old_regs = set_irq_regs(regs); - /* - * Some hardware gives randomly wrong interrupts. Rather - * than crashing, do something sensible. - */ - if (irq >= NR_IRQS) - desc = &bad_irq_desc; - - irq_enter(); #ifdef CONFIG_DEBUG_STACKOVERFLOW +static void check_stack_overflow(int irq) +{ /* Debugging check for stack overflow: is there less than STACK_WARN free? */ - { - long sp; - - sp = __get_SP() & (THREAD_SIZE-1); + long sp = __get_SP() & (THREAD_SIZE - 1); - if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) { - dump_stack(); - printk(KERN_EMERG "%s: possible stack overflow while handling irq %i " - " only %ld bytes free\n", - __func__, irq, sp - sizeof(struct thread_info)); - } + if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) { + dump_stack(); + pr_emerg("irq%i: possible stack overflow only %ld bytes free\n", + irq, sp - sizeof(struct thread_info)); } +} +#else +static inline void check_stack_overflow(int irq) { } #endif - generic_handle_irq(irq); #ifndef CONFIG_IPIPE +static void maybe_lower_to_irq14(void) +{ + unsigned short pending, other_ints; + /* * If we're the only interrupt running (ignoring IRQ15 which * is for syscalls), lower our priority to IRQ14 so that @@ -165,7 +122,38 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) other_ints = pending & (pending - 1); if (other_ints == 0) lower_to_irq14(); -#endif /* !CONFIG_IPIPE */ +} +#else +static inline void maybe_lower_to_irq14(void) { } +#endif + +/* + * do_IRQ handles all hardware IRQs. Decoded IRQs should not + * come via this function. Instead, they should provide their + * own 'handler' + */ +#ifdef CONFIG_DO_IRQ_L1 +__attribute__((l1_text)) +#endif +asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) +{ + struct pt_regs *old_regs = set_irq_regs(regs); + + irq_enter(); + + check_stack_overflow(irq); + + /* + * Some hardware gives randomly wrong interrupts. Rather + * than crashing, do something sensible. + */ + if (irq >= NR_IRQS) + handle_bad_irq(irq, &bad_irq_desc); + else + generic_handle_irq(irq); + + maybe_lower_to_irq14(); + irq_exit(); set_irq_regs(old_regs); @@ -173,14 +161,6 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) void __init init_IRQ(void) { - struct irq_desc *desc; - int irq; - - spin_lock_init(&irq_controller_lock); - for (irq = 0, desc = irq_desc; irq < NR_IRQS; irq++, desc++) { - *desc = bad_irq_desc; - } - init_arch_irq(); #ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c index da28f79..cce79d0 100644 --- a/arch/blackfin/kernel/kgdb.c +++ b/arch/blackfin/kernel/kgdb.c @@ -34,15 +34,6 @@ int gdb_bfin_vector = -1; #error change the definition of slavecpulocks #endif -#define IN_MEM(addr, size, l1_addr, l1_size) \ -({ \ - unsigned long __addr = (unsigned long)(addr); \ - (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \ -}) -#define ASYNC_BANK_SIZE \ - (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ - ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) - void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) { gdb_regs[BFIN_R0] = regs->r0; @@ -463,41 +454,88 @@ static int hex(char ch) static int validate_memory_access_address(unsigned long addr, int size) { - int cpu = raw_smp_processor_id(); - - if (size < 0) + if (size < 0 || addr == 0) return -EFAULT; - if (addr >= 0x1000 && (addr + size) <= physical_mem_end) - return 0; - if (addr >= SYSMMR_BASE) - return 0; - if (IN_MEM(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE)) - return 0; - if (cpu == 0) { - if (IN_MEM(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH)) - return 0; - if (IN_MEM(addr, size, L1_CODE_START, L1_CODE_LENGTH)) - return 0; - if (IN_MEM(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH)) - return 0; - if (IN_MEM(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH)) - return 0; -#ifdef CONFIG_SMP - } else if (cpu == 1) { - if (IN_MEM(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) + return bfin_mem_access_type(addr, size); +} + +static int bfin_probe_kernel_read(char *dst, char *src, int size) +{ + unsigned long lsrc = (unsigned long)src; + int mem_type; + + mem_type = validate_memory_access_address(lsrc, size); + if (mem_type < 0) + return mem_type; + + if (lsrc >= SYSMMR_BASE) { + if (size == 2 && lsrc % 2 == 0) { + u16 mmr = bfin_read16(src); + memcpy(dst, &mmr, sizeof(mmr)); return 0; - if (IN_MEM(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) + } else if (size == 4 && lsrc % 4 == 0) { + u32 mmr = bfin_read32(src); + memcpy(dst, &mmr, sizeof(mmr)); return 0; - if (IN_MEM(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) + } + } else { + switch (mem_type) { + case BFIN_MEM_ACCESS_CORE: + case BFIN_MEM_ACCESS_CORE_ONLY: + return probe_kernel_read(dst, src, size); + /* XXX: should support IDMA here with SMP */ + case BFIN_MEM_ACCESS_DMA: + if (dma_memcpy(dst, src, size)) + return 0; + break; + case BFIN_MEM_ACCESS_ITEST: + if (isram_memcpy(dst, src, size)) + return 0; + break; + } + } + + return -EFAULT; +} + +static int bfin_probe_kernel_write(char *dst, char *src, int size) +{ + unsigned long ldst = (unsigned long)dst; + int mem_type; + + mem_type = validate_memory_access_address(ldst, size); + if (mem_type < 0) + return mem_type; + + if (ldst >= SYSMMR_BASE) { + if (size == 2 && ldst % 2 == 0) { + u16 mmr; + memcpy(&mmr, src, sizeof(mmr)); + bfin_write16(dst, mmr); return 0; - if (IN_MEM(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) + } else if (size == 4 && ldst % 4 == 0) { + u32 mmr; + memcpy(&mmr, src, sizeof(mmr)); + bfin_write32(dst, mmr); return 0; -#endif + } + } else { + switch (mem_type) { + case BFIN_MEM_ACCESS_CORE: + case BFIN_MEM_ACCESS_CORE_ONLY: + return probe_kernel_write(dst, src, size); + /* XXX: should support IDMA here with SMP */ + case BFIN_MEM_ACCESS_DMA: + if (dma_memcpy(dst, src, size)) + return 0; + break; + case BFIN_MEM_ACCESS_ITEST: + if (isram_memcpy(dst, src, size)) + return 0; + break; + } } - if (IN_MEM(addr, size, L2_START, L2_LENGTH)) - return 0; - return -EFAULT; } @@ -509,14 +547,6 @@ int kgdb_mem2hex(char *mem, char *buf, int count) { char *tmp; int err; - unsigned char *pch; - unsigned short mmr16; - unsigned long mmr32; - int cpu = raw_smp_processor_id(); - - err = validate_memory_access_address((unsigned long)mem, count); - if (err) - return err; /* * We use the upper half of buf as an intermediate buffer for the @@ -524,44 +554,7 @@ int kgdb_mem2hex(char *mem, char *buf, int count) */ tmp = buf + count; - if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/ - switch (count) { - case 2: - if ((unsigned int)mem % 2 == 0) { - mmr16 = *(unsigned short *)mem; - pch = (unsigned char *)&mmr16; - *tmp++ = *pch++; - *tmp++ = *pch++; - tmp -= 2; - } else - err = -EFAULT; - break; - case 4: - if ((unsigned int)mem % 4 == 0) { - mmr32 = *(unsigned long *)mem; - pch = (unsigned char *)&mmr32; - *tmp++ = *pch++; - *tmp++ = *pch++; - *tmp++ = *pch++; - *tmp++ = *pch++; - tmp -= 4; - } else - err = -EFAULT; - break; - default: - err = -EFAULT; - } - } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) -#ifdef CONFIG_SMP - || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH)) -#endif - ) { - /* access L1 instruction SRAM*/ - if (dma_memcpy(tmp, mem, count) == NULL) - err = -EFAULT; - } else - err = probe_kernel_read(tmp, mem, count); - + err = bfin_probe_kernel_read(tmp, mem, count); if (!err) { while (count > 0) { buf = pack_hex_byte(buf, *tmp); @@ -582,13 +575,8 @@ int kgdb_mem2hex(char *mem, char *buf, int count) */ int kgdb_ebin2mem(char *buf, char *mem, int count) { - char *tmp_old; - char *tmp_new; - unsigned short *mmr16; - unsigned long *mmr32; - int err; + char *tmp_old, *tmp_new; int size; - int cpu = raw_smp_processor_id(); tmp_old = tmp_new = buf; @@ -601,41 +589,7 @@ int kgdb_ebin2mem(char *buf, char *mem, int count) tmp_old++; } - err = validate_memory_access_address((unsigned long)mem, size); - if (err) - return err; - - if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/ - switch (size) { - case 2: - if ((unsigned int)mem % 2 == 0) { - mmr16 = (unsigned short *)buf; - *(unsigned short *)mem = *mmr16; - } else - err = -EFAULT; - break; - case 4: - if ((unsigned int)mem % 4 == 0) { - mmr32 = (unsigned long *)buf; - *(unsigned long *)mem = *mmr32; - } else - err = -EFAULT; - break; - default: - err = -EFAULT; - } - } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) -#ifdef CONFIG_SMP - || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH)) -#endif - ) { - /* access L1 instruction SRAM */ - if (dma_memcpy(mem, buf, size) == NULL) - err = -EFAULT; - } else - err = probe_kernel_write(mem, buf, size); - - return err; + return bfin_probe_kernel_write(mem, buf, count); } /* @@ -645,16 +599,7 @@ int kgdb_ebin2mem(char *buf, char *mem, int count) */ int kgdb_hex2mem(char *buf, char *mem, int count) { - char *tmp_raw; - char *tmp_hex; - unsigned short *mmr16; - unsigned long *mmr32; - int err; - int cpu = raw_smp_processor_id(); - - err = validate_memory_access_address((unsigned long)mem, count); - if (err) - return err; + char *tmp_raw, *tmp_hex; /* * We use the upper half of buf as an intermediate buffer for the @@ -669,39 +614,18 @@ int kgdb_hex2mem(char *buf, char *mem, int count) *tmp_raw |= hex(*tmp_hex--) << 4; } - if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/ - switch (count) { - case 2: - if ((unsigned int)mem % 2 == 0) { - mmr16 = (unsigned short *)tmp_raw; - *(unsigned short *)mem = *mmr16; - } else - err = -EFAULT; - break; - case 4: - if ((unsigned int)mem % 4 == 0) { - mmr32 = (unsigned long *)tmp_raw; - *(unsigned long *)mem = *mmr32; - } else - err = -EFAULT; - break; - default: - err = -EFAULT; - } - } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) -#ifdef CONFIG_SMP - || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH)) -#endif - ) { - /* access L1 instruction SRAM */ - if (dma_memcpy(mem, tmp_raw, count) == NULL) - err = -EFAULT; - } else - err = probe_kernel_write(mem, tmp_raw, count); - - return err; + return bfin_probe_kernel_write(mem, tmp_raw, count); } +#define IN_MEM(addr, size, l1_addr, l1_size) \ +({ \ + unsigned long __addr = (unsigned long)(addr); \ + (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \ +}) +#define ASYNC_BANK_SIZE \ + (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ + ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) + int kgdb_validate_break_address(unsigned long addr) { int cpu = raw_smp_processor_id(); @@ -724,46 +648,17 @@ int kgdb_validate_break_address(unsigned long addr) int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr) { - int err; - int cpu = raw_smp_processor_id(); - - if ((cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) -#ifdef CONFIG_SMP - || (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH)) -#endif - ) { - /* access L1 instruction SRAM */ - if (dma_memcpy(saved_instr, (void *)addr, BREAK_INSTR_SIZE) - == NULL) - return -EFAULT; - - if (dma_memcpy((void *)addr, arch_kgdb_ops.gdb_bpt_instr, - BREAK_INSTR_SIZE) == NULL) - return -EFAULT; - - return 0; - } else { - err = probe_kernel_read(saved_instr, (char *)addr, - BREAK_INSTR_SIZE); - if (err) - return err; - - return probe_kernel_write((char *)addr, - arch_kgdb_ops.gdb_bpt_instr, BREAK_INSTR_SIZE); - } + int err = bfin_probe_kernel_read(saved_instr, (char *)addr, + BREAK_INSTR_SIZE); + if (err) + return err; + return bfin_probe_kernel_write((char *)addr, arch_kgdb_ops.gdb_bpt_instr, + BREAK_INSTR_SIZE); } int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle) { - if (IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) { - /* access L1 instruction SRAM */ - if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL) - return -EFAULT; - - return 0; - } else - return probe_kernel_write((char *)addr, - (char *)bundle, BREAK_INSTR_SIZE); + return bfin_probe_kernel_write((char *)addr, bundle, BREAK_INSTR_SIZE); } int kgdb_arch_init(void) diff --git a/arch/blackfin/kernel/mcount.S b/arch/blackfin/kernel/mcount.S deleted file mode 100644 index edcfb38..0000000 --- a/arch/blackfin/kernel/mcount.S +++ /dev/null @@ -1,70 +0,0 @@ -/* - * linux/arch/blackfin/mcount.S - * - * Copyright (C) 2006 Analog Devices Inc. - * - * 2007/04/12 Save index, length, modify and base registers. --rpm - */ - -#include <linux/linkage.h> -#include <asm/blackfin.h> - -.text - -.align 4 /* just in case */ - -ENTRY(__mcount) - [--sp] = i0; - [--sp] = i1; - [--sp] = i2; - [--sp] = i3; - [--sp] = l0; - [--sp] = l1; - [--sp] = l2; - [--sp] = l3; - [--sp] = m0; - [--sp] = m1; - [--sp] = m2; - [--sp] = m3; - [--sp] = b0; - [--sp] = b1; - [--sp] = b2; - [--sp] = b3; - [--sp] = ( r7:0, p5:0 ); - [--sp] = ASTAT; - - p1.L = _ipipe_trace_enable; - p1.H = _ipipe_trace_enable; - r7 = [p1]; - CC = r7 == 0; - if CC jump out; - link 0x10; - r0 = 0x0; - [sp + 0xc] = r0; /* v */ - r0 = 0x0; /* type: IPIPE_TRACE_FN */ - r1 = rets; - p0 = [fp]; /* p0: Prior FP */ - r2 = [p0 + 4]; /* r2: Prior RETS */ - call ___ipipe_trace; - unlink; -out: - ASTAT = [sp++]; - ( r7:0, p5:0 ) = [sp++]; - b3 = [sp++]; - b2 = [sp++]; - b1 = [sp++]; - b0 = [sp++]; - m3 = [sp++]; - m2 = [sp++]; - m1 = [sp++]; - m0 = [sp++]; - l3 = [sp++]; - l2 = [sp++]; - l1 = [sp++]; - l0 = [sp++]; - i3 = [sp++]; - i2 = [sp++]; - i1 = [sp++]; - i0 = [sp++]; - rts; -ENDPROC(__mcount) diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 30d0843..79cad0a 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -160,6 +160,29 @@ pid_t kernel_thread(int (*fn) (void *), void *arg, unsigned long flags) } EXPORT_SYMBOL(kernel_thread); +/* + * Do necessary setup to start up a newly executed thread. + * + * pass the data segment into user programs if it exists, + * it can't hurt anything as far as I can tell + */ +void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp) +{ + set_fs(USER_DS); + regs->pc = new_ip; + if (current->mm) + regs->p5 = current->mm->start_data; +#ifdef CONFIG_SMP + task_thread_info(current)->l1_task_info.stack_start = + (void *)current->mm->context.stack_start; + task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp; + memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info, + sizeof(*L1_SCRATCH_TASK_INFO)); +#endif + wrusp(new_sp); +} +EXPORT_SYMBOL_GPL(start_thread); + void flush_thread(void) { } @@ -321,6 +344,87 @@ void finish_atomic_sections (struct pt_regs *regs) } } +static inline +int in_mem(unsigned long addr, unsigned long size, + unsigned long start, unsigned long end) +{ + return addr >= start && addr + size <= end; +} +static inline +int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off, + unsigned long const_addr, unsigned long const_size) +{ + return const_size && + in_mem(addr, size, const_addr + off, const_addr + const_size); +} +static inline +int in_mem_const(unsigned long addr, unsigned long size, + unsigned long const_addr, unsigned long const_size) +{ + return in_mem_const_off(addr, 0, size, const_addr, const_size); +} +#define IN_ASYNC(bnum, bctlnum) \ +({ \ + (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? -EFAULT : \ + bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? -EFAULT : \ + BFIN_MEM_ACCESS_CORE; \ +}) + +int bfin_mem_access_type(unsigned long addr, unsigned long size) +{ + int cpu = raw_smp_processor_id(); + + /* Check that things do not wrap around */ + if (addr > ULONG_MAX - size) + return -EFAULT; + + if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end)) + return BFIN_MEM_ACCESS_CORE; + + if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH)) + return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA; + if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH)) + return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT; + if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH)) + return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; + if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH)) + return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; +#ifdef COREB_L1_CODE_START + if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) + return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA; + if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) + return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT; + if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) + return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; + if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) + return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; +#endif + if (in_mem_const(addr, size, L2_START, L2_LENGTH)) + return BFIN_MEM_ACCESS_CORE; + + if (addr >= SYSMMR_BASE) + return BFIN_MEM_ACCESS_CORE_ONLY; + + /* We can't read EBIU banks that aren't enabled or we end up hanging + * on the access to the async space. + */ + if (in_mem_const(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK0_SIZE)) + return IN_ASYNC(0, 0); + if (in_mem_const(addr, size, ASYNC_BANK1_BASE, ASYNC_BANK1_SIZE)) + return IN_ASYNC(1, 0); + if (in_mem_const(addr, size, ASYNC_BANK2_BASE, ASYNC_BANK2_SIZE)) + return IN_ASYNC(2, 1); + if (in_mem_const(addr, size, ASYNC_BANK3_BASE, ASYNC_BANK3_SIZE)) + return IN_ASYNC(3, 1); + + if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH)) + return BFIN_MEM_ACCESS_CORE; + if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH)) + return BFIN_MEM_ACCESS_DMA; + + return -EFAULT; +} + #if defined(CONFIG_ACCESS_CHECK) #ifdef CONFIG_ACCESS_OK_L1 __attribute__((l1_text)) @@ -330,51 +434,61 @@ int _access_ok(unsigned long addr, unsigned long size) { if (size == 0) return 1; - if (addr > (addr + size)) + /* Check that things do not wrap around */ + if (addr > ULONG_MAX - size) return 0; if (segment_eq(get_fs(), KERNEL_DS)) return 1; #ifdef CONFIG_MTD_UCLINUX - if (addr >= memory_start && (addr + size) <= memory_end) - return 1; - if (addr >= memory_mtd_end && (addr + size) <= physical_mem_end) + if (1) +#else + if (0) +#endif + { + if (in_mem(addr, size, memory_start, memory_end)) + return 1; + if (in_mem(addr, size, memory_mtd_end, physical_mem_end)) + return 1; +# ifndef CONFIG_ROMFS_ON_MTD + if (0) +# endif + /* For XIP, allow user space to use pointers within the ROMFS. */ + if (in_mem(addr, size, memory_mtd_start, memory_mtd_end)) + return 1; + } else { + if (in_mem(addr, size, memory_start, physical_mem_end)) + return 1; + } + + if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end)) return 1; -#ifdef CONFIG_ROMFS_ON_MTD - /* For XIP, allow user space to use pointers within the ROMFS. */ - if (addr >= memory_mtd_start && (addr + size) <= memory_mtd_end) + if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH)) return 1; -#endif -#else - if (addr >= memory_start && (addr + size) <= physical_mem_end) + if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH)) return 1; -#endif - if (addr >= (unsigned long)__init_begin && - addr + size <= (unsigned long)__init_end) + if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH)) return 1; - if (addr >= get_l1_scratch_start() - && addr + size <= get_l1_scratch_start() + L1_SCRATCH_LENGTH) + if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH)) return 1; -#if L1_CODE_LENGTH != 0 - if (addr >= get_l1_code_start() + (_etext_l1 - _stext_l1) - && addr + size <= get_l1_code_start() + L1_CODE_LENGTH) +#ifdef COREB_L1_CODE_START + if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) return 1; -#endif -#if L1_DATA_A_LENGTH != 0 - if (addr >= get_l1_data_a_start() + (_ebss_l1 - _sdata_l1) - && addr + size <= get_l1_data_a_start() + L1_DATA_A_LENGTH) + if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) return 1; -#endif -#if L1_DATA_B_LENGTH != 0 - if (addr >= get_l1_data_b_start() + (_ebss_b_l1 - _sdata_b_l1) - && addr + size <= get_l1_data_b_start() + L1_DATA_B_LENGTH) + if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) return 1; -#endif -#if L2_LENGTH != 0 - if (addr >= L2_START + (_ebss_l2 - _stext_l2) - && addr + size <= L2_START + L2_LENGTH) + if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) return 1; #endif + if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH)) + return 1; + + if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH)) + return 1; + if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH)) + return 1; + return 0; } EXPORT_SYMBOL(_access_ok); diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 6454bab..298f023 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -117,15 +117,49 @@ void __cpuinit bfin_setup_caches(unsigned int cpu) */ #ifdef CONFIG_BFIN_ICACHE printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); + printk(KERN_INFO " External memory:" +# ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE + " cacheable" +# else + " uncacheable" +# endif + " in instruction cache\n"); + if (L2_LENGTH) + printk(KERN_INFO " L2 SRAM :" +# ifdef CONFIG_BFIN_L2_ICACHEABLE + " cacheable" +# else + " uncacheable" +# endif + " in instruction cache\n"); + +#else + printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu); #endif + #ifdef CONFIG_BFIN_DCACHE - printk(KERN_INFO "Data Cache Enabled for CPU%u" -# if defined CONFIG_BFIN_WB - " (write-back)" -# elif defined CONFIG_BFIN_WT - " (write-through)" + printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu); + printk(KERN_INFO " External memory:" +# if defined CONFIG_BFIN_EXTMEM_WRITEBACK + " cacheable (write-back)" +# elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH + " cacheable (write-through)" +# else + " uncacheable" # endif - "\n", cpu); + " in data cache\n"); + if (L2_LENGTH) + printk(KERN_INFO " L2 SRAM :" +# if defined CONFIG_BFIN_L2_WRITEBACK + " cacheable (write-back)" +# elif defined CONFIG_BFIN_L2_WRITETHROUGH + " cacheable (write-through)" +# else + " uncacheable" +# endif + " in data cache\n"); +#else + printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu); #endif } @@ -443,9 +477,11 @@ static __init void parse_cmdline_early(char *cmdline_p) } else if (!memcmp(to, "clkin_hz=", 9)) { to += 9; early_init_clkin_hz(to); +#ifdef CONFIG_EARLY_PRINTK } else if (!memcmp(to, "earlyprintk=", 12)) { to += 12; setup_early_printk(to); +#endif } else if (!memcmp(to, "memmap=", 7)) { to += 7; parse_memmap(to); @@ -516,7 +552,7 @@ static __init void memory_setup(void) && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) mtd_size = PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); -# if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) +# if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) /* Due to a Hardware Anomaly we need to limit the size of usable * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on * 05000263 - Hardware loop corrupted when taking an ICPLB exception @@ -544,7 +580,7 @@ static __init void memory_setup(void) dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); #endif /* CONFIG_MTD_UCLINUX */ -#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) +#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) /* Due to a Hardware Anomaly we need to limit the size of usable * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on * 05000263 - Hardware loop corrupted when taking an ICPLB exception @@ -764,6 +800,11 @@ void __init setup_arch(char **cmdline_p) { unsigned long sclk, cclk; + /* Check to make sure we are running on the right processor */ + if (unlikely(CPUID != bfin_cpuid())) + printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", + CPU, bfin_cpuid(), bfin_revid()); + #ifdef CONFIG_DUMMY_CONSOLE conswitchp = &dummy_con; #endif @@ -778,14 +819,17 @@ void __init setup_arch(char **cmdline_p) memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); boot_command_line[COMMAND_LINE_SIZE - 1] = '\0'; - /* setup memory defaults from the user config */ - physical_mem_end = 0; - _ramend = get_mem_size() * 1024 * 1024; - memset(&bfin_memmap, 0, sizeof(bfin_memmap)); + /* If the user does not specify things on the command line, use + * what the bootloader set things up as + */ + physical_mem_end = 0; parse_cmdline_early(&command_line[0]); + if (_ramend == 0) + _ramend = get_mem_size() * 1024 * 1024; + if (physical_mem_end == 0) physical_mem_end = _ramend; @@ -837,7 +881,8 @@ void __init setup_arch(char **cmdline_p) defined(CONFIG_BF538) || defined(CONFIG_BF539) _bfin_swrst = bfin_read_SWRST(); #else - _bfin_swrst = bfin_read_SYSCR(); + /* Clear boot mode field */ + _bfin_swrst = bfin_read_SYSCR() & ~0xf; #endif #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT @@ -875,10 +920,7 @@ void __init setup_arch(char **cmdline_p) else printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid()); - if (unlikely(CPUID != bfin_cpuid())) - printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", - CPU, bfin_cpuid(), bfin_revid()); - else { + if (likely(CPUID == bfin_cpuid())) { if (bfin_revid() != bfin_compiled_revid()) { if (bfin_compiled_revid() == -1) printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", @@ -1157,16 +1199,25 @@ static int show_cpuinfo(struct seq_file *m, void *v) icache_size = 0; seq_printf(m, "cache size\t: %d KB(L1 icache) " - "%d KB(L1 dcache%s) %d KB(L2 cache)\n", - icache_size, dcache_size, -#if defined CONFIG_BFIN_WB - "-wb" -#elif defined CONFIG_BFIN_WT - "-wt" -#endif - "", 0); - + "%d KB(L1 dcache) %d KB(L2 cache)\n", + icache_size, dcache_size, 0); seq_printf(m, "%s\n", cache); + seq_printf(m, "external memory\t: " +#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) + "cacheable" +#else + "uncacheable" +#endif + " in instruction cache\n"); + seq_printf(m, "external memory\t: " +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) + "cacheable (write-back)" +#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) + "cacheable (write-through)" +#else + "uncacheable" +#endif + " in data cache\n"); if (icache_size) seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n", @@ -1239,8 +1290,25 @@ static int show_cpuinfo(struct seq_file *m, void *v) if (cpu_num != num_possible_cpus() - 1) return 0; - if (L2_LENGTH) + if (L2_LENGTH) { seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); + seq_printf(m, "L2 SRAM\t\t: " +#if defined(CONFIG_BFIN_L2_ICACHEABLE) + "cacheable" +#else + "uncacheable" +#endif + " in instruction cache\n"); + seq_printf(m, "L2 SRAM\t\t: " +#if defined(CONFIG_BFIN_L2_WRITEBACK) + "cacheable (write-back)" +#elif defined(CONFIG_BFIN_L2_WRITETHROUGH) + "cacheable (write-through)" +#else + "uncacheable" +#endif + " in data cache\n"); + } seq_printf(m, "board name\t: %s\n", bfin_board_name); seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index d279552..8eeb457 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -37,6 +37,7 @@ #include <asm/traps.h> #include <asm/cacheflush.h> #include <asm/cplb.h> +#include <asm/dma.h> #include <asm/blackfin.h> #include <asm/irq_handler.h> #include <linux/irq.h> @@ -636,57 +637,30 @@ asmlinkage void trap_c(struct pt_regs *fp) */ static bool get_instruction(unsigned short *val, unsigned short *address) { - - unsigned long addr; - - addr = (unsigned long)address; + unsigned long addr = (unsigned long)address; /* Check for odd addresses */ if (addr & 0x1) return false; - /* Check that things do not wrap around */ - if (addr > (addr + 2)) + /* MMR region will never have instructions */ + if (addr >= SYSMMR_BASE) return false; - /* - * Since we are in exception context, we need to do a little address checking - * We need to make sure we are only accessing valid memory, and - * we don't read something in the async space that can hang forever - */ - if ((addr >= FIXED_CODE_START && (addr + 2) <= physical_mem_end) || -#if L2_LENGTH != 0 - (addr >= L2_START && (addr + 2) <= (L2_START + L2_LENGTH)) || -#endif - (addr >= BOOT_ROM_START && (addr + 2) <= (BOOT_ROM_START + BOOT_ROM_LENGTH)) || -#if L1_DATA_A_LENGTH != 0 - (addr >= L1_DATA_A_START && (addr + 2) <= (L1_DATA_A_START + L1_DATA_A_LENGTH)) || -#endif -#if L1_DATA_B_LENGTH != 0 - (addr >= L1_DATA_B_START && (addr + 2) <= (L1_DATA_B_START + L1_DATA_B_LENGTH)) || -#endif - (addr >= L1_SCRATCH_START && (addr + 2) <= (L1_SCRATCH_START + L1_SCRATCH_LENGTH)) || - (!(bfin_read_EBIU_AMBCTL0() & B0RDYEN) && - addr >= ASYNC_BANK0_BASE && (addr + 2) <= (ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)) || - (!(bfin_read_EBIU_AMBCTL0() & B1RDYEN) && - addr >= ASYNC_BANK1_BASE && (addr + 2) <= (ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)) || - (!(bfin_read_EBIU_AMBCTL1() & B2RDYEN) && - addr >= ASYNC_BANK2_BASE && (addr + 2) <= (ASYNC_BANK2_BASE + ASYNC_BANK1_SIZE)) || - (!(bfin_read_EBIU_AMBCTL1() & B3RDYEN) && - addr >= ASYNC_BANK3_BASE && (addr + 2) <= (ASYNC_BANK3_BASE + ASYNC_BANK1_SIZE))) { - *val = *address; - return true; + switch (bfin_mem_access_type(addr, 2)) { + case BFIN_MEM_ACCESS_CORE: + case BFIN_MEM_ACCESS_CORE_ONLY: + *val = *address; + return true; + case BFIN_MEM_ACCESS_DMA: + dma_memcpy(val, address, 2); + return true; + case BFIN_MEM_ACCESS_ITEST: + isram_memcpy(val, address, 2); + return true; + default: /* invalid access */ + return false; } - -#if L1_CODE_LENGTH != 0 - if (addr >= L1_CODE_START && (addr + 2) <= (L1_CODE_START + L1_CODE_LENGTH)) { - isram_memcpy(val, address, 2); - return true; - } -#endif - - - return false; } /* diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c index 1382f03..d979110 100644 --- a/arch/blackfin/mach-bf518/boards/ezbrd.c +++ b/arch/blackfin/mach-bf518/boards/ezbrd.c @@ -119,13 +119,19 @@ static struct platform_device bfin_mac_device = { }; #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) -static struct dsa_platform_data ksz8893m_switch_data = { +static struct dsa_chip_data ksz8893m_switch_chip_data = { .mii_bus = &bfin_mii_bus.dev, + .port_names = { + NULL, + "eth%d", + "eth%d", + "cpu", + }, +}; +static struct dsa_platform_data ksz8893m_switch_data = { + .nr_chips = 1, .netdev = &bfin_mac_device.dev, - .port_names[0] = NULL, - .port_names[1] = "eth%d", - .port_names[2] = "eth%d", - .port_names[3] = "cpu", + .chip = &ksz8893m_switch_chip_data, }; static struct platform_device ksz8893m_switch_device = { diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h index b69bd9a..426e064 100644 --- a/arch/blackfin/mach-bf518/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h @@ -7,7 +7,7 @@ */ /* This file should be up to date with: - * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List + * - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List */ /* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ @@ -18,7 +18,7 @@ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) @@ -45,29 +45,31 @@ /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ #define ANOMALY_05000426 (1) /* Software System Reset Corrupts PLL_LOCKCNT Register */ -#define ANOMALY_05000430 (1) +#define ANOMALY_05000430 (__SILICON_REVISION__ < 1) /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ #define ANOMALY_05000431 (1) /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ -#define ANOMALY_05000435 (1) +#define ANOMALY_05000435 (__SILICON_REVISION__ < 1) /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ -#define ANOMALY_05000438 (1) +#define ANOMALY_05000438 (__SILICON_REVISION__ < 1) /* Preboot Cannot be Used to Alter the PLL_DIV Register */ -#define ANOMALY_05000439 (1) +#define ANOMALY_05000439 (__SILICON_REVISION__ < 1) /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ -#define ANOMALY_05000440 (1) +#define ANOMALY_05000440 (__SILICON_REVISION__ < 1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) /* Incorrect L1 Instruction Bank B Memory Map Location */ -#define ANOMALY_05000444 (1) +#define ANOMALY_05000444 (__SILICON_REVISION__ < 1) /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ -#define ANOMALY_05000452 (1) +#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) /* PWM_TRIPB Signal Not Available on PG10 */ -#define ANOMALY_05000453 (1) +#define ANOMALY_05000453 (__SILICON_REVISION__ < 1) /* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ -#define ANOMALY_05000455 (1) -/* False Hardware Error when RETI points to invalid memory */ +#define ANOMALY_05000455 (__SILICON_REVISION__ < 1) +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) +/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ +#define ANOMALY_05000462 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -78,24 +80,30 @@ #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) #define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) #define ANOMALY_05000215 (0) #define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) #define ANOMALY_05000231 (0) #define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000244 (0) #define ANOMALY_05000248 (0) #define ANOMALY_05000250 (0) +#define ANOMALY_05000257 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000274 (0) #define ANOMALY_05000278 (0) +#define ANOMALY_05000281 (0) +#define ANOMALY_05000283 (0) #define ANOMALY_05000285 (0) #define ANOMALY_05000287 (0) #define ANOMALY_05000301 (0) @@ -103,10 +111,13 @@ #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000312 (0) +#define ANOMALY_05000315 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000353 (0) +#define ANOMALY_05000357 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000371 (0) #define ANOMALY_05000380 (0) #define ANOMALY_05000386 (0) #define ANOMALY_05000389 (0) @@ -117,5 +128,7 @@ #define ANOMALY_05000448 (0) #define ANOMALY_05000456 (0) #define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) #endif diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h index 267bb7c..e8e14c2 100644 --- a/arch/blackfin/mach-bf518/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h @@ -33,7 +33,6 @@ #define _MACH_BLACKFIN_H_ #include "bf518.h" -#include "mem_map.h" #include "defBF512.h" #include "anomaly.h" diff --git a/arch/blackfin/mach-bf518/include/mach/mem_map.h b/arch/blackfin/mach-bf518/include/mach/mem_map.h index 62bcc78..3c6777c 100644 --- a/arch/blackfin/mach-bf518/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf518/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * file: include/asm-blackfin/mach-bf518/mem_map.h - * based on: include/asm-blackfin/mach-bf527/mem_map.h - * author: Bryan Wu <cooloney@kernel.org> + * BF51x memory map * - * created: - * description: - * Memory MAP Common header file for blackfin BF518/6/4/2 of processors. - * rev: - * - * modified: - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_518_H_ -#define _MEM_MAP_518_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ @@ -89,20 +67,4 @@ #define BFIN_DSUPBANKS 0 #endif /*CONFIG_BFIN_DCACHE */ -/* Level 2 Memory - none */ - -#define L2_START 0 -#define L2_LENGTH 0 - -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif /* _MEM_MAP_518_H_ */ +#endif diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c index 1eaf27f..f4867ce 100644 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c @@ -78,7 +78,6 @@ static struct resource bfin_isp1760_resources[] = { static struct isp1760_platform_data isp1760_priv = { .is_isp1761 = 0, - .port1_disable = 0, .bus_width_16 = 1, .port1_otg = 0, .analog_oc = 0, diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c index 9f9c000..b2f30f0 100644 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ b/arch/blackfin/mach-bf527/boards/ezbrd.c @@ -237,10 +237,10 @@ static struct flash_platform_data bfin_spi_flash_data = { .name = "m25p80", .parts = bfin_spi_flash_partitions, .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p16", + .type = "sst25wf040", }; -/* SPI flash chip (m25p64) */ +/* SPI flash chip (sst25wf040) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ .bits_per_word = 8, diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index 3e5b7db..799a1d1 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -77,7 +77,6 @@ static struct resource bfin_isp1760_resources[] = { static struct isp1760_platform_data isp1760_priv = { .is_isp1761 = 0, - .port1_disable = 0, .bus_width_16 = 1, .port1_otg = 0, .analog_oc = 0, diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index c84ddea..0d63f74 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h @@ -34,7 +34,7 @@ #define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) #define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ @@ -184,8 +184,12 @@ #define ANOMALY_05000456 (1) /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ #define ANOMALY_05000457 (1) -/* False Hardware Error when RETI points to invalid memory */ +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) +/* USB Rx DMA hang */ +#define ANOMALY_05000465 (1) +/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ +#define ANOMALY_05000467 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -195,24 +199,30 @@ #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) #define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) #define ANOMALY_05000215 (0) #define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) #define ANOMALY_05000231 (0) #define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000244 (0) #define ANOMALY_05000248 (0) #define ANOMALY_05000250 (0) +#define ANOMALY_05000257 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000274 (0) #define ANOMALY_05000278 (0) +#define ANOMALY_05000281 (0) +#define ANOMALY_05000283 (0) #define ANOMALY_05000285 (0) #define ANOMALY_05000287 (0) #define ANOMALY_05000301 (0) @@ -220,6 +230,7 @@ #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000312 (0) +#define ANOMALY_05000315 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h index 417abcd..03665a8 100644 --- a/arch/blackfin/mach-bf527/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h @@ -33,7 +33,6 @@ #define _MACH_BLACKFIN_H_ #include "bf527.h" -#include "mem_map.h" #include "defBF522.h" #include "anomaly.h" diff --git a/arch/blackfin/mach-bf527/include/mach/mem_map.h b/arch/blackfin/mach-bf527/include/mach/mem_map.h index 019e001..d96e894 100644 --- a/arch/blackfin/mach-bf527/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf527/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * file: include/asm-blackfin/mach-bf527/mem_map.h - * based on: include/asm-blackfin/mach-bf537/mem_map.h - * author: Michael Hennerich (michael.hennerich@analog.com) + * BF52x memory map * - * created: - * description: - * Memory MAP Common header file for blackfin BF527/5/2 of processors. - * rev: - * - * modified: - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_527_H_ -#define _MEM_MAP_527_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ @@ -89,20 +67,4 @@ #define BFIN_DSUPBANKS 0 #endif /*CONFIG_BFIN_DCACHE */ -/* Level 2 Memory - none */ - -#define L2_START 0 -#define L2_LENGTH 0 - -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif /* _MEM_MAP_527_H_ */ +#endif diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index 89a5ec4..4e3e511 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c @@ -32,6 +32,7 @@ #include <linux/platform_device.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/plat-ram.h> #include <linux/spi/spi.h> #include <linux/spi/flash.h> #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) @@ -86,6 +87,101 @@ static struct platform_device smc91x_device = { }; #endif +#if defined(CONFIG_MTD_PSD4256G) || defined(CONFIG_MTD_PSD4256G_MODULE) +static const char *map_probes[] = { + "stm_flash", + NULL, +}; + +static struct platdata_mtd_ram stm_pri_data_a = { + .mapname = "Flash A Primary", + .map_probes = map_probes, + .bankwidth = 2, +}; + +static struct resource stm_pri_resource_a = { + .start = 0x20000000, + .end = 0x200fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device stm_pri_device_a = { + .name = "mtd-ram", + .id = 0, + .dev = { + .platform_data = &stm_pri_data_a, + }, + .num_resources = 1, + .resource = &stm_pri_resource_a, +}; + +static struct platdata_mtd_ram stm_pri_data_b = { + .mapname = "Flash B Primary", + .map_probes = map_probes, + .bankwidth = 2, +}; + +static struct resource stm_pri_resource_b = { + .start = 0x20100000, + .end = 0x201fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device stm_pri_device_b = { + .name = "mtd-ram", + .id = 4, + .dev = { + .platform_data = &stm_pri_data_b, + }, + .num_resources = 1, + .resource = &stm_pri_resource_b, +}; +#endif + +#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE) +static struct platdata_mtd_ram sram_data_a = { + .mapname = "Flash A SRAM", + .bankwidth = 2, +}; + +static struct resource sram_resource_a = { + .start = 0x20240000, + .end = 0x2024ffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device sram_device_a = { + .name = "mtd-ram", + .id = 8, + .dev = { + .platform_data = &sram_data_a, + }, + .num_resources = 1, + .resource = &sram_resource_a, +}; + +static struct platdata_mtd_ram sram_data_b = { + .mapname = "Flash B SRAM", + .bankwidth = 2, +}; + +static struct resource sram_resource_b = { + .start = 0x202c0000, + .end = 0x202cffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device sram_device_b = { + .name = "mtd-ram", + .id = 9, + .dev = { + .platform_data = &sram_data_b, + }, + .num_resources = 1, + .resource = &sram_resource_b, +}; +#endif + #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) static struct mtd_partition bfin_spi_flash_partitions[] = { { @@ -357,6 +453,16 @@ static struct platform_device *ezkit_devices[] __initdata = { &bfin_dpmc, +#if defined(CONFIG_MTD_PSD4256G) || defined(CONFIG_MTD_PSD4256G_MODULE) + &stm_pri_device_a, + &stm_pri_device_b, +#endif + +#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE) + &sram_device_a, + &sram_device_b, +#endif + #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) &smc91x_device, #endif diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h index 31145b5..70a0ad6 100644 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h @@ -34,7 +34,7 @@ # define ANOMALY_BF533 0 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) @@ -46,7 +46,7 @@ #define ANOMALY_05000122 (1) /* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ #define ANOMALY_05000158 (__SILICON_REVISION__ < 5) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) @@ -56,13 +56,13 @@ #define ANOMALY_05000180 (1) /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ #define ANOMALY_05000183 (__SILICON_REVISION__ < 4) -/* False Protection Exceptions */ +/* False Protection Exceptions when Speculative Fetch Is Cancelled */ #define ANOMALY_05000189 (__SILICON_REVISION__ < 4) /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ #define ANOMALY_05000193 (__SILICON_REVISION__ < 4) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ #define ANOMALY_05000194 (__SILICON_REVISION__ < 4) -/* Failing MMR Accesses When Stalled by Preceding Memory Read */ +/* Failing MMR Accesses when Preceding Memory Read Stalls */ #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) /* Current DMA Address Shows Wrong Value During Carry Fix */ #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) @@ -74,7 +74,7 @@ #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) /* Specific Sequence That Can Cause DMA Error or DMA Stopping */ #define ANOMALY_05000203 (__SILICON_REVISION__ < 4) -/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ +/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ #define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) /* Recovery from "Brown-Out" Condition */ #define ANOMALY_05000207 (__SILICON_REVISION__ < 4) @@ -106,7 +106,7 @@ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* Data CPLBs Should Prevent Spurious Hardware Errors */ +/* Data CPLBs Should Prevent False Hardware Errors */ #define ANOMALY_05000246 (__SILICON_REVISION__ < 5) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ == 4) @@ -148,21 +148,21 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 6) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 6) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 6) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 6) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 6) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 6) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ #define ANOMALY_05000301 (__SILICON_REVISION__ < 6) -/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ +/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) -/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ +/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */ #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) /* SCKELOW Bit Does Not Maintain State Through Hibernate */ #define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ @@ -170,11 +170,11 @@ #define ANOMALY_05000310 (1) /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ #define ANOMALY_05000311 (__SILICON_REVISION__ < 6) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 6) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (__SILICON_REVISION__ < 6) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 6) /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ #define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) @@ -200,7 +200,7 @@ #define ANOMALY_05000426 (1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) -/* False Hardware Error when RETI points to invalid memory */ +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* These anomalies have been "phased" out of analog.com anomaly sheets and are @@ -215,17 +215,17 @@ #define ANOMALY_05000070 (__SILICON_REVISION__ < 2) /* Writing FIO_DIR can corrupt a programmable flag's data */ #define ANOMALY_05000079 (__SILICON_REVISION__ < 2) -/* Timer Auto-Baud Mode requires the UART clock to be enabled */ +/* Timer Auto-Baud Mode requires the UART clock to be enabled. */ #define ANOMALY_05000086 (__SILICON_REVISION__ < 2) /* Internal Clocking Modes on SPORT0 not supported */ #define ANOMALY_05000088 (__SILICON_REVISION__ < 2) /* Internal voltage regulator does not wake up from an RTC wakeup */ #define ANOMALY_05000092 (__SILICON_REVISION__ < 2) -/* The IFLUSH instruction must be preceded by a CSYNC instruction */ +/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */ #define ANOMALY_05000093 (__SILICON_REVISION__ < 2) -/* Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior */ +/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */ #define ANOMALY_05000095 (__SILICON_REVISION__ < 2) -/* PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC */ +/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */ #define ANOMALY_05000096 (__SILICON_REVISION__ < 2) /* Performance Monitor 0 and 1 are swapped when monitoring memory events */ #define ANOMALY_05000097 (__SILICON_REVISION__ < 2) @@ -235,45 +235,45 @@ #define ANOMALY_05000100 (__SILICON_REVISION__ < 2) /* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ #define ANOMALY_05000101 (__SILICON_REVISION__ < 2) -/* Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ +/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ #define ANOMALY_05000102 (__SILICON_REVISION__ < 2) -/* Incorrect value written to the cycle counters */ +/* Incorrect Value Written to the Cycle Counters */ #define ANOMALY_05000103 (__SILICON_REVISION__ < 2) -/* Stores to L1 Data memory incorrect when a specific sequence is followed */ +/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */ #define ANOMALY_05000104 (__SILICON_REVISION__ < 2) /* Programmable Flag (PF3) functionality not supported in all PPI modes */ #define ANOMALY_05000106 (__SILICON_REVISION__ < 2) /* Data store can be lost when targeting a cache line fill */ #define ANOMALY_05000107 (__SILICON_REVISION__ < 2) -/* Reserved bits in SYSCFG register not set at power on */ +/* Reserved Bits in SYSCFG Register Not Set at Power-On */ #define ANOMALY_05000109 (__SILICON_REVISION__ < 3) /* Infinite Core Stall */ #define ANOMALY_05000114 (__SILICON_REVISION__ < 2) -/* PPI_FSx may glitch when generated by the on chip Timers */ +/* PPI_FSx may glitch when generated by the on chip Timers. */ #define ANOMALY_05000115 (__SILICON_REVISION__ < 2) -/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) /* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ #define ANOMALY_05000117 (__SILICON_REVISION__ < 2) /* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ #define ANOMALY_05000118 (__SILICON_REVISION__ < 2) -/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ +/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */ #define ANOMALY_05000123 (__SILICON_REVISION__ < 3) /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ #define ANOMALY_05000124 (__SILICON_REVISION__ < 3) -/* Erroneous exception when enabling cache */ +/* Erroneous Exception when Enabling Cache */ #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) /* SPI clock polarity and phase bits incorrect during booting */ #define ANOMALY_05000126 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL is not set on Reset */ +/* DMEM_CONTROL<12> Is Not Set on Reset */ #define ANOMALY_05000137 (__SILICON_REVISION__ < 3) /* SPI boot will not complete if there is a zero fill block in the loader file */ #define ANOMALY_05000138 (__SILICON_REVISION__ == 2) -/* Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs */ +/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */ #define ANOMALY_05000139 (__SILICON_REVISION__ < 2) /* Allowing the SPORT RX FIFO to fill will cause an overflow */ #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) @@ -287,7 +287,7 @@ #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ +/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */ #define ANOMALY_05000148 (__SILICON_REVISION__ < 3) /* Frame Delay in SPORT Multichannel Mode */ #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) @@ -295,13 +295,13 @@ #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ #define ANOMALY_05000155 (__SILICON_REVISION__ < 3) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* SPORT transmit data is not gated by external frame sync in certain conditions */ +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* SDRAM auto-refresh and subsequent Power Ups */ +/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ #define ANOMALY_05000168 (__SILICON_REVISION__ < 3) -/* DATA CPLB page miss can result in lost write-through cache data writes */ +/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ #define ANOMALY_05000169 (__SILICON_REVISION__ < 3) /* DMA vs Core accesses to external memory */ #define ANOMALY_05000173 (__SILICON_REVISION__ < 3) @@ -309,15 +309,15 @@ #define ANOMALY_05000174 (__SILICON_REVISION__ < 3) /* Overlapping Sequencer and Memory Stalls */ #define ANOMALY_05000175 (__SILICON_REVISION__ < 3) -/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ +/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ #define ANOMALY_05000176 (__SILICON_REVISION__ < 3) -/* Disabling the PPI resets the PPI configuration registers */ +/* Disabling the PPI Resets the PPI Configuration Registers */ #define ANOMALY_05000181 (__SILICON_REVISION__ < 3) -/* PPI TX Mode with 2 External Frame Syncs */ +/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ #define ANOMALY_05000185 (__SILICON_REVISION__ < 3) /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) -/* In PPI Transmit Modes with External Frame Syncs POLC */ +/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */ #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) /* Internal Voltage Regulator may not start up */ #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) @@ -326,6 +326,7 @@ #define ANOMALY_05000120 (0) #define ANOMALY_05000149 (0) #define ANOMALY_05000171 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000220 (0) #define ANOMALY_05000248 (0) #define ANOMALY_05000266 (0) @@ -345,5 +346,7 @@ #define ANOMALY_05000448 (0) #define ANOMALY_05000456 (0) #define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) #endif diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h index 045184f..39aa175 100644 --- a/arch/blackfin/mach-bf533/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h @@ -34,7 +34,6 @@ #define BF533_FAMILY #include "bf533.h" -#include "mem_map.h" #include "defBF532.h" #include "anomaly.h" diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h index fc33b7c..197af1a 100644 --- a/arch/blackfin/mach-bf533/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf533/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * File: include/asm-blackfin/mach-bf533/mem_map.h - * Based on: - * Author: + * BF533 memory map * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_533_H_ -#define _MEM_MAP_533_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ @@ -158,20 +136,4 @@ #endif -/* Level 2 Memory - none */ - -#define L2_START 0 -#define L2_LENGTH 0 - -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif /* _MEM_MAP_533_H_ */ +#endif diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index ff7228c..c1f76dd 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -79,7 +79,6 @@ static struct resource bfin_isp1760_resources[] = { static struct isp1760_platform_data isp1760_priv = { .is_isp1761 = 0, - .port1_disable = 0, .bus_width_16 = 1, .port1_otg = 0, .analog_oc = 0, diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h index fc96634..57c128c 100644 --- a/arch/blackfin/mach-bf537/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h @@ -34,13 +34,13 @@ # define ANOMALY_BF537 0 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 2) /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) @@ -50,11 +50,11 @@ #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* CLKIN Buffer Output Enable Reset Behavior Is Changed */ +/* Buffered CLKIN Output Is Disabled by Default */ #define ANOMALY_05000247 (1) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ < 3) -/* EMAC Tx DMA error after an early frame abort */ +/* EMAC TX DMA Error After an Early Frame Abort */ #define ANOMALY_05000252 (__SILICON_REVISION__ < 3) /* Maximum External Clock Speed for Timers */ #define ANOMALY_05000253 (__SILICON_REVISION__ < 3) @@ -62,7 +62,7 @@ #define ANOMALY_05000254 (__SILICON_REVISION__ > 2) /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ #define ANOMALY_05000255 (__SILICON_REVISION__ < 3) -/* EMAC MDIO input latched on wrong MDC edge */ +/* EMAC MDIO Input Latched on Wrong MDC Edge */ #define ANOMALY_05000256 (__SILICON_REVISION__ < 3) /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ #define ANOMALY_05000257 (__SILICON_REVISION__ < 3) @@ -80,7 +80,7 @@ #define ANOMALY_05000264 (__SILICON_REVISION__ < 3) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) -/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ +/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */ #define ANOMALY_05000268 (__SILICON_REVISION__ < 3) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ #define ANOMALY_05000270 (__SILICON_REVISION__ < 3) @@ -92,15 +92,15 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) -/* SPI Master boot mode does not work well with Atmel Data flash devices */ +/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */ #define ANOMALY_05000280 (1) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 3) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 3) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 3) -/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ +/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */ #define ANOMALY_05000285 (__SILICON_REVISION__ < 3) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 3) @@ -112,25 +112,25 @@ #define ANOMALY_05000305 (__SILICON_REVISION__ < 3) /* SCKELOW Bit Does Not Maintain State Through Hibernate */ #define ANOMALY_05000307 (__SILICON_REVISION__ < 3) -/* Writing UART_THR while UART clock is disabled sends erroneous start bit */ +/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */ #define ANOMALY_05000309 (__SILICON_REVISION__ < 3) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode: collisions occur in Full Duplex mode */ +/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */ #define ANOMALY_05000316 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */ +/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */ #define ANOMALY_05000321 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ +/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */ #define ANOMALY_05000322 (1) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) -/* New Feature: UART Remains Enabled after UART Boot */ +/* UART Gets Disabled after UART Boot */ #define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (1) @@ -154,7 +154,7 @@ #define ANOMALY_05000426 (1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) -/* False Hardware Error when RETI points to invalid memory */ +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* Anomalies that don't exist on this proc */ @@ -165,14 +165,17 @@ #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) #define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) #define ANOMALY_05000215 (0) #define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) #define ANOMALY_05000231 (0) #define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000248 (0) #define ANOMALY_05000266 (0) @@ -195,5 +198,7 @@ #define ANOMALY_05000448 (0) #define ANOMALY_05000456 (0) #define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) #endif diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h index 7d6069c..f5e5015 100644 --- a/arch/blackfin/mach-bf537/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h @@ -35,7 +35,6 @@ #define BF537_FAMILY #include "bf537.h" -#include "mem_map.h" #include "defBF534.h" #include "anomaly.h" diff --git a/arch/blackfin/mach-bf537/include/mach/mem_map.h b/arch/blackfin/mach-bf537/include/mach/mem_map.h index f9010c4b4..942f08d 100644 --- a/arch/blackfin/mach-bf537/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf537/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * file: include/asm-blackfin/mach-bf537/mem_map.h - * based on: - * author: + * BF537 memory map * - * created: - * description: - * Memory MAP Common header file for blackfin BF537/6/4 of processors. - * rev: - * - * modified: - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_537_H_ -#define _MEM_MAP_537_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ @@ -166,20 +144,4 @@ #endif -/* Level 2 Memory - none */ - -#define L2_START 0 -#define L2_LENGTH 0 - -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif /* _MEM_MAP_537_H_ */ +#endif diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h index 175ca9e..c97acdf 100644 --- a/arch/blackfin/mach-bf538/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h @@ -30,13 +30,13 @@ # define ANOMALY_BF539 0 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ #define ANOMALY_05000179 (1) @@ -70,11 +70,11 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 4) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 4) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 4) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 4) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 4) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 4) @@ -92,11 +92,11 @@ #define ANOMALY_05000307 (__SILICON_REVISION__ < 4) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 5) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (__SILICON_REVISION__ < 4) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 4) /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ #define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) @@ -110,7 +110,7 @@ #define ANOMALY_05000371 (__SILICON_REVISION__ < 5) /* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */ #define ANOMALY_05000374 (__SILICON_REVISION__ == 4) -/* New Feature: Open-Drain GPIO Outputs on PC1 and PC4 (Not Available on Older Silicon) */ +/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */ #define ANOMALY_05000375 (__SILICON_REVISION__ < 4) /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ #define ANOMALY_05000402 (__SILICON_REVISION__ < 4) @@ -126,26 +126,32 @@ #define ANOMALY_05000436 (__SILICON_REVISION__ > 3) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) -/* False Hardware Error when RETI points to invalid memory */ +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) #define ANOMALY_05000120 (0) +#define ANOMALY_05000125 (0) #define ANOMALY_05000149 (0) #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) #define ANOMALY_05000215 (0) #define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) #define ANOMALY_05000231 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000248 (0) #define ANOMALY_05000250 (0) #define ANOMALY_05000254 (0) +#define ANOMALY_05000257 (0) #define ANOMALY_05000263 (0) +#define ANOMALY_05000266 (0) #define ANOMALY_05000274 (0) #define ANOMALY_05000287 (0) #define ANOMALY_05000305 (0) @@ -166,5 +172,7 @@ #define ANOMALY_05000448 (0) #define ANOMALY_05000456 (0) #define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) #endif diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h index 6f62835..9496196 100644 --- a/arch/blackfin/mach-bf538/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h @@ -35,7 +35,6 @@ #define BF538_FAMILY #include "bf538.h" -#include "mem_map.h" #include "defBF539.h" #include "anomaly.h" diff --git a/arch/blackfin/mach-bf538/include/mach/mem_map.h b/arch/blackfin/mach-bf538/include/mach/mem_map.h index 7681196..aff00f4 100644 --- a/arch/blackfin/mach-bf538/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf538/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * File: include/asm-blackfin/mach-bf538/mem_map.h - * Based on: - * Author: + * BF538 memory map * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_538_H_ -#define _MEM_MAP_538_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ @@ -93,21 +71,4 @@ #define BFIN_DSUPBANKS 0 #endif /*CONFIG_BFIN_DCACHE*/ - -/* Level 2 Memory - none */ - -#define L2_START 0 -#define L2_LENGTH 0 - -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif /* _MEM_MAP_538_H_ */ +#endif diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 805a57b..81f5b95 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -76,7 +76,6 @@ static struct resource bfin_isp1760_resources[] = { static struct isp1760_platform_data isp1760_priv = { .is_isp1761 = 0, - .port1_disable = 0, .bus_width_16 = 1, .port1_otg = 0, .analog_oc = 0, diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index c510ae6..18a4cd24 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h @@ -18,7 +18,7 @@ # error will not work on BF548 silicon version 0.0, or 0.1 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) @@ -30,17 +30,17 @@ #define ANOMALY_05000265 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 1) /* TWI Slave Boot Mode Is Not Functional */ #define ANOMALY_05000324 (__SILICON_REVISION__ < 1) -/* External FIFO Boot Mode Is Not Functional */ +/* FIFO Boot Mode Not Functional */ #define ANOMALY_05000325 (__SILICON_REVISION__ < 2) /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ #define ANOMALY_05000327 (__SILICON_REVISION__ < 1) @@ -178,8 +178,12 @@ #define ANOMALY_05000450 (1) /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ #define ANOMALY_05000456 (__SILICON_REVISION__ < 3) -/* False Hardware Error when RETI points to invalid memory */ +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) +/* USB Rx DMA hang */ +#define ANOMALY_05000465 (1) +/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ +#define ANOMALY_05000467 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -189,30 +193,36 @@ #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) #define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) #define ANOMALY_05000215 (0) #define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) #define ANOMALY_05000231 (0) #define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000244 (0) #define ANOMALY_05000248 (0) #define ANOMALY_05000250 (0) #define ANOMALY_05000254 (0) +#define ANOMALY_05000257 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000274 (0) #define ANOMALY_05000278 (0) +#define ANOMALY_05000283 (0) #define ANOMALY_05000287 (0) #define ANOMALY_05000301 (0) #define ANOMALY_05000305 (0) #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) +#define ANOMALY_05000315 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h index cf6c150..6b97396 100644 --- a/arch/blackfin/mach-bf548/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h @@ -33,7 +33,6 @@ #define _MACH_BLACKFIN_H_ #include "bf548.h" -#include "mem_map.h" #include "anomaly.h" #ifdef CONFIG_BF542 diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h index 70b9c11..caac2df 100644 --- a/arch/blackfin/mach-bf548/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf548/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * file: include/asm-blackfin/mach-bf548/mem_map.h - * based on: - * author: + * BF548 memory map * - * created: - * description: - * Memory MAP Common header file for blackfin BF537/6/4 of processors. - * rev: - * - * modified: - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_548_H_ -#define _MEM_MAP_548_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ @@ -103,15 +81,4 @@ # define L2_LENGTH 0x20000 #endif -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif/* _MEM_MAP_548_H_ */ +#endif diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index b5ef7ff..4df904f 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -62,7 +62,6 @@ static struct resource bfin_isp1760_resources[] = { static struct isp1760_platform_data isp1760_priv = { .is_isp1761 = 0, - .port1_disable = 0, .bus_width_16 = 1, .port1_otg = 0, .analog_oc = 0, diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index dccd396c..94b8e27 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h @@ -18,19 +18,19 @@ # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) -/* Testset instructions restricted to 32-bit aligned memory locations */ +/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ #define ANOMALY_05000120 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Erroneous exception when enabling cache */ +/* Erroneous Exception when Enabling Cache */ #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) -/* Signbits instruction not functional under certain conditions */ +/* SIGNBITS Instruction Not Functional under Certain Conditions */ #define ANOMALY_05000127 (1) /* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ #define ANOMALY_05000134 (__SILICON_REVISION__ < 3) @@ -40,7 +40,7 @@ #define ANOMALY_05000136 (__SILICON_REVISION__ < 3) /* Allowing the SPORT RX FIFO to fill will cause an overflow */ #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) @@ -52,7 +52,7 @@ #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* IMDMA S1/D1 channel may stall */ +/* IMDMA S1/D1 Channel May Stall */ #define ANOMALY_05000149 (1) /* DMA engine may lose data due to incorrect handshaking */ #define ANOMALY_05000150 (__SILICON_REVISION__ < 3) @@ -66,7 +66,7 @@ #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ #define ANOMALY_05000156 (__SILICON_REVISION__ < 4) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ #define ANOMALY_05000159 (__SILICON_REVISION__ < 3) @@ -76,17 +76,17 @@ #define ANOMALY_05000161 (__SILICON_REVISION__ < 3) /* DMEM_CONTROL<12> is not set on Reset */ #define ANOMALY_05000162 (__SILICON_REVISION__ < 3) -/* SPORT transmit data is not gated by external frame sync in certain conditions */ +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) -/* SDRAM auto-refresh and subsequent Power Ups */ +/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ #define ANOMALY_05000168 (__SILICON_REVISION__ < 5) -/* DATA CPLB page miss can result in lost write-through cache data writes */ +/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ #define ANOMALY_05000169 (__SILICON_REVISION__ < 5) -/* Boot-ROM code modifies SICA_IWRx wakeup registers */ +/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ #define ANOMALY_05000171 (__SILICON_REVISION__ < 5) /* DSPID register values incorrect */ #define ANOMALY_05000172 (__SILICON_REVISION__ < 3) @@ -96,29 +96,29 @@ #define ANOMALY_05000174 (__SILICON_REVISION__ < 5) /* Overlapping Sequencer and Memory Stalls */ #define ANOMALY_05000175 (__SILICON_REVISION__ < 5) -/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ +/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ #define ANOMALY_05000176 (__SILICON_REVISION__ < 5) /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) -/* Disabling the PPI resets the PPI configuration registers */ +/* Disabling the PPI Resets the PPI Configuration Registers */ #define ANOMALY_05000181 (__SILICON_REVISION__ < 5) -/* IMDMA does not operate to full speed for 600MHz and higher devices */ +/* Internal Memory DMA Does Not Operate at Full Speed */ #define ANOMALY_05000182 (1) -/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */ +/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ #define ANOMALY_05000184 (__SILICON_REVISION__ < 5) -/* PPI TX Mode with 2 External Frame Syncs */ +/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ #define ANOMALY_05000185 (__SILICON_REVISION__ < 5) -/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */ +/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */ #define ANOMALY_05000186 (__SILICON_REVISION__ < 5) /* IMDMA Corrupted Data after a Halt */ #define ANOMALY_05000187 (1) /* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ #define ANOMALY_05000188 (__SILICON_REVISION__ < 5) -/* False Protection Exceptions */ +/* False Protection Exceptions when Speculative Fetch Is Cancelled */ #define ANOMALY_05000189 (__SILICON_REVISION__ < 5) -/* PPI not functional at core voltage < 1Volt */ +/* PPI Not Functional at Core Voltage < 1Volt */ #define ANOMALY_05000190 (1) /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) @@ -126,7 +126,7 @@ #define ANOMALY_05000193 (__SILICON_REVISION__ < 5) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ #define ANOMALY_05000194 (__SILICON_REVISION__ < 5) -/* Failing MMR Accesses When Stalled by Preceding Memory Read */ +/* Failing MMR Accesses when Preceding Memory Read Stalls */ #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) /* Current DMA Address Shows Wrong Value During Carry Fix */ #define ANOMALY_05000199 (__SILICON_REVISION__ < 5) @@ -134,9 +134,9 @@ #define ANOMALY_05000200 (__SILICON_REVISION__ < 5) /* Possible Infinite Stall with Specific Dual-DAG Situation */ #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) -/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ +/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ #define ANOMALY_05000204 (__SILICON_REVISION__ < 5) -/* Specific sequence that can cause DMA error or DMA stopping */ +/* Specific Sequence that Can Cause DMA Error or DMA Stopping */ #define ANOMALY_05000205 (__SILICON_REVISION__ < 5) /* Recovery from "Brown-Out" Condition */ #define ANOMALY_05000207 (__SILICON_REVISION__ < 5) @@ -158,7 +158,7 @@ #define ANOMALY_05000230 (__SILICON_REVISION__ < 5) /* UART STB Bit Incorrectly Affects Receiver Setting */ #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) -/* SPORT data transmit lines are incorrectly driven in multichannel mode */ +/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */ #define ANOMALY_05000232 (__SILICON_REVISION__ < 5) /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) @@ -166,7 +166,7 @@ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (__SILICON_REVISION__ < 5) -/* TESTSET operation forces stall on the other core */ +/* TESTSET Operation Forces Stall on the Other Core */ #define ANOMALY_05000248 (__SILICON_REVISION__ < 5) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) @@ -192,9 +192,9 @@ #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (__SILICON_REVISION__ < 5) -/* IMDMA destination IRQ status must be read prior to using IMDMA */ +/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */ #define ANOMALY_05000266 (__SILICON_REVISION__ > 3) -/* IMDMA may corrupt data under certain conditions */ +/* IMDMA May Corrupt Data under Certain Conditions */ #define ANOMALY_05000267 (1) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ #define ANOMALY_05000269 (1) @@ -202,7 +202,7 @@ #define ANOMALY_05000270 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* Data cache write back to external synchronous memory may be lost */ +/* Data Cache Write Back to External Synchronous Memory May Be Lost */ #define ANOMALY_05000274 (1) /* PPI Timing and Sampling Information Updates */ #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) @@ -212,17 +212,17 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 5) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (1) -/* A read will receive incorrect data under certain conditions */ +/* Reads Will Receive Incorrect Data under Certain Conditions */ #define ANOMALY_05000287 (__SILICON_REVISION__ < 5) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 5) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ #define ANOMALY_05000301 (1) -/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ +/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (1) /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) @@ -230,25 +230,25 @@ #define ANOMALY_05000307 (__SILICON_REVISION__ < 5) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (1) -/* PF2 Output Remains Asserted After SPI Master Boot */ +/* PF2 Output Remains Asserted after SPI Master Boot */ #define ANOMALY_05000320 (__SILICON_REVISION__ > 3) -/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */ +/* Erroneous GPIO Flag Pin Operations under Specific Sequences */ #define ANOMALY_05000323 (1) -/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */ +/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */ #define ANOMALY_05000326 (__SILICON_REVISION__ > 3) -/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */ +/* 24-Bit SPI Boot Mode Is Not Functional */ #define ANOMALY_05000331 (__SILICON_REVISION__ < 5) -/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */ +/* Slave SPI Boot Mode Is Not Functional */ #define ANOMALY_05000332 (__SILICON_REVISION__ < 5) -/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ +/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */ #define ANOMALY_05000333 (__SILICON_REVISION__ < 5) -/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */ +/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000339 (__SILICON_REVISION__ < 5) /* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ #define ANOMALY_05000343 (__SILICON_REVISION__ < 5) @@ -276,7 +276,7 @@ #define ANOMALY_05000428 (__SILICON_REVISION__ > 3) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) -/* False Hardware Error when RETI points to invalid memory */ +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* Anomalies that don't exist on this proc */ @@ -284,6 +284,7 @@ #define ANOMALY_05000158 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000353 (1) @@ -298,5 +299,7 @@ #define ANOMALY_05000448 (0) #define ANOMALY_05000456 (0) #define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) #endif diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h index f79f6626..8be3135 100644 --- a/arch/blackfin/mach-bf561/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h @@ -34,7 +34,6 @@ #define BF561_FAMILY #include "bf561.h" -#include "mem_map.h" #include "defBF561.h" #include "anomaly.h" diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h index 419dffd..a63e15c 100644 --- a/arch/blackfin/mach-bf561/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h @@ -1,13 +1,16 @@ /* - * Memory MAP - * Common header file for blackfin BF561 of processors. + * BF561 memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_561_H_ -#define _MEM_MAP_561_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ @@ -82,9 +85,6 @@ #define COREA_L1_SCRATCH_START 0xFFB00000 #define COREB_L1_SCRATCH_START 0xFF700000 -#define L1_SCRATCH_START COREA_L1_SCRATCH_START -#define L1_SCRATCH_LENGTH 0x1000 - #ifdef __ASSEMBLY__ /* @@ -155,14 +155,42 @@ dreg = ROT dreg BY -1; \ dreg = CC; -#else -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; +static inline unsigned long get_l1_scratch_start_cpu(int cpu) +{ + return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; +} +static inline unsigned long get_l1_code_start_cpu(int cpu) +{ + return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START; +} +static inline unsigned long get_l1_data_a_start_cpu(int cpu) +{ + return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START; +} +static inline unsigned long get_l1_data_b_start_cpu(int cpu) +{ + return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START; +} + +static inline unsigned long get_l1_scratch_start(void) +{ + return get_l1_scratch_start_cpu(blackfin_core_id()); +} +static inline unsigned long get_l1_code_start(void) +{ + return get_l1_code_start_cpu(blackfin_core_id()); +} +static inline unsigned long get_l1_data_a_start(void) +{ + return get_l1_data_a_start_cpu(blackfin_core_id()); +} +static inline unsigned long get_l1_data_b_start(void) +{ + return get_l1_data_b_start_cpu(blackfin_core_id()); +} -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) #endif /* CONFIG_SMP */ #endif /* __ASSEMBLY__ */ -#endif /* _MEM_MAP_533_H_ */ +#endif diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile index 1f3228e..dd8b2dc 100644 --- a/arch/blackfin/mach-common/Makefile +++ b/arch/blackfin/mach-common/Makefile @@ -4,7 +4,7 @@ obj-y := \ cache.o cache-c.o entry.o head.o \ - interrupt.o irqpanic.o arch_checks.o ints-priority.o + interrupt.o arch_checks.o ints-priority.o obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o obj-$(CONFIG_PM) += pm.o dpmc_modes.o @@ -12,3 +12,4 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq.o obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o +obj-$(CONFIG_DEBUG_ICACHE_CHECK) += irqpanic.o diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c index da93d92..5998d86 100644 --- a/arch/blackfin/mach-common/arch_checks.c +++ b/arch/blackfin/mach-common/arch_checks.c @@ -74,7 +74,7 @@ /* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ #if ANOMALY_05000220 && \ - ((defined(CONFIG_BFIN_WB) && defined(CONFIG_BFIN_L2_NOT_CACHED)) || \ - (!defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_L2_WB))) + ((defined(CONFIG_BFIN_EXTMEM_WRITEBACK) && !defined(CONFIG_BFIN_L2_DCACHEABLE)) || \ + (!defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) && defined(CONFIG_BFIN_L2_WRITEBACK))) # error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB. #endif diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c index 70e3411..85c6580 100644 --- a/arch/blackfin/mach-common/cpufreq.c +++ b/arch/blackfin/mach-common/cpufreq.c @@ -141,7 +141,7 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy) sclk = get_sclk() / 1000; #if ANOMALY_05000273 || ANOMALY_05000274 || \ - (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE)) + (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE)) min_cclk = sclk * 2; #else min_cclk = sclk; diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 31fa313..5a4e7c7 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -1609,6 +1609,7 @@ ENTRY(_sys_call_table) .long _sys_preadv .long _sys_pwritev .long _sys_rt_tgsigqueueinfo + .long _sys_perf_counter_open .rept NR_syscalls-(.-_sys_call_table)/4 .long _sys_ni_syscall diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 351afd0..b421501 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -472,7 +472,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) if (type == IRQ_TYPE_PROBE) { /* only probe unenabled GPIO interrupt lines */ - if (__test_bit(gpionr, gpio_enabled)) + if (test_bit(gpionr, gpio_enabled)) return 0; type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; } @@ -782,7 +782,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) if (type == IRQ_TYPE_PROBE) { /* only probe unenabled GPIO interrupt lines */ - if (__test_bit(gpionr, gpio_enabled)) + if (test_bit(gpionr, gpio_enabled)) return 0; type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; } @@ -1052,35 +1052,34 @@ int __init init_arch_irq(void) set_irq_chained_handler(irq, bfin_demux_error_irq); break; #endif -#if defined(CONFIG_TICKSOURCE_GPTMR0) - case IRQ_TIMER0: - set_irq_handler(irq, handle_percpu_irq); - break; -#endif #ifdef CONFIG_SMP case IRQ_SUPPLE_0: case IRQ_SUPPLE_1: set_irq_handler(irq, handle_percpu_irq); break; #endif - default: #ifdef CONFIG_IPIPE - /* - * We want internal interrupt sources to be - * masked, because ISRs may trigger interrupts - * recursively (e.g. DMA), but interrupts are - * _not_ masked at CPU level. So let's handle - * most of them as level interrupts, except - * the timer interrupt which is special. - */ - if (irq == IRQ_SYSTMR || irq == IRQ_CORETMR) - set_irq_handler(irq, handle_simple_irq); - else - set_irq_handler(irq, handle_level_irq); +#ifndef CONFIG_TICKSOURCE_CORETMR + case IRQ_TIMER0: + set_irq_handler(irq, handle_simple_irq); + break; +#endif /* !CONFIG_TICKSOURCE_CORETMR */ + case IRQ_CORETMR: + set_irq_handler(irq, handle_simple_irq); + break; + default: + set_irq_handler(irq, handle_level_irq); + break; #else /* !CONFIG_IPIPE */ +#ifdef CONFIG_TICKSOURCE_GPTMR0 + case IRQ_TIMER0: + set_irq_handler(irq, handle_percpu_irq); + break; +#endif /* CONFIG_TICKSOURCE_GPTMR0 */ + default: set_irq_handler(irq, handle_simple_irq); -#endif /* !CONFIG_IPIPE */ break; +#endif /* !CONFIG_IPIPE */ } } @@ -1224,15 +1223,14 @@ __attribute__((l1_text)) asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) { struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); - struct ipipe_domain *this_domain = ipipe_current_domain; + struct ipipe_domain *this_domain = __ipipe_current_domain; struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; int irq, s; - if (likely(vec == EVT_IVTMR_P)) { + if (likely(vec == EVT_IVTMR_P)) irq = IRQ_CORETMR; - - } else { + else { #if defined(SIC_ISR0) || defined(SICA_ISR0) unsigned long sic_status[3]; @@ -1262,12 +1260,11 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) break; } #endif - irq = ivg->irqno; } if (irq == IRQ_SYSTMR) { -#ifndef CONFIG_GENERIC_CLOCKEVENTS +#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0) bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ #endif /* This is basically what we need from the register frame. */ diff --git a/arch/blackfin/mach-common/irqpanic.c b/arch/blackfin/mach-common/irqpanic.c index 05004df..883e324 100644 --- a/arch/blackfin/mach-common/irqpanic.c +++ b/arch/blackfin/mach-common/irqpanic.c @@ -30,21 +30,17 @@ #include <linux/module.h> #include <linux/kernel_stat.h> #include <linux/sched.h> -#include <asm/traps.h> #include <asm/blackfin.h> -#ifdef CONFIG_DEBUG_ICACHE_CHECK #define L1_ICACHE_START 0xffa10000 #define L1_ICACHE_END 0xffa13fff -void irq_panic(int reason, struct pt_regs *regs) __attribute__ ((l1_text)); -#endif /* * irq_panic - calls panic with string setup */ +__attribute__ ((l1_text)) asmlinkage void irq_panic(int reason, struct pt_regs *regs) { -#ifdef CONFIG_DEBUG_ICACHE_CHECK unsigned int cmd, tag, ca, cache_hi, cache_lo, *pa; unsigned short i, j, die; unsigned int bad[10][6]; @@ -126,9 +122,6 @@ asmlinkage void irq_panic(int reason, struct pt_regs *regs) bad[j][3], bad[j][4], bad[j][5]); } panic("icache coherency error"); - } else { + } else printk(KERN_EMERG "icache checked, and OK\n"); - } -#endif - } diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index bce5a84..9e7e27b 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c @@ -132,7 +132,7 @@ int bf53x_resume_l1_mem(unsigned char *memptr) return 0; } -#ifdef CONFIG_BFIN_WB +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) static void flushinv_all_dcache(void) { u32 way, bank, subbank, set; @@ -175,7 +175,7 @@ static inline void dcache_disable(void) #ifdef CONFIG_BFIN_DCACHE unsigned long ctrl; -#ifdef CONFIG_BFIN_WB +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) flushinv_all_dcache(); #endif SSYNC(); diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index 014a55a..68bd0bd6 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c @@ -160,7 +160,7 @@ void __init mem_init(void) /* do not count in kernel image between _rambase and _ramstart */ reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT; -#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) +#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT; #endif diff --git a/arch/cris/arch-v10/kernel/dma.c b/arch/cris/arch-v10/kernel/dma.c index 929e686..d31504b 100644 --- a/arch/cris/arch-v10/kernel/dma.c +++ b/arch/cris/arch-v10/kernel/dma.c @@ -24,7 +24,7 @@ int cris_request_dma(unsigned int dmanr, const char * device_id, unsigned long int gens; int fail = -EINVAL; - if ((dmanr < 0) || (dmanr >= MAX_DMA_CHANNELS)) { + if (dmanr >= MAX_DMA_CHANNELS) { printk(KERN_CRIT "cris_request_dma: invalid DMA channel %u\n", dmanr); return -EINVAL; } @@ -213,7 +213,7 @@ int cris_request_dma(unsigned int dmanr, const char * device_id, void cris_free_dma(unsigned int dmanr, const char * device_id) { unsigned long flags; - if ((dmanr < 0) || (dmanr >= MAX_DMA_CHANNELS)) { + if (dmanr >= MAX_DMA_CHANNELS) { printk(KERN_CRIT "cris_free_dma: invalid DMA channel %u\n", dmanr); return; } diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c index 67c61ea..fd529a0 100644 --- a/arch/cris/arch-v32/drivers/cryptocop.c +++ b/arch/cris/arch-v32/drivers/cryptocop.c @@ -1395,7 +1395,7 @@ static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char if (padlen < MD5_MIN_PAD_LENGTH) padlen += MD5_BLOCK_LENGTH; p = kmalloc(padlen, alloc_flag); - if (!pad) return -ENOMEM; + if (!p) return -ENOMEM; *p = 0x80; memset(p+1, 0, padlen - 1); @@ -1427,7 +1427,7 @@ static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, cha if (padlen < SHA1_MIN_PAD_LENGTH) padlen += SHA1_BLOCK_LENGTH; p = kmalloc(padlen, alloc_flag); - if (!pad) return -ENOMEM; + if (!p) return -ENOMEM; *p = 0x80; memset(p+1, 0, padlen - 1); diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c index d70b445..57668db 100644 --- a/arch/cris/arch-v32/kernel/irq.c +++ b/arch/cris/arch-v32/kernel/irq.c @@ -430,8 +430,8 @@ crisv32_do_multiple(struct pt_regs* regs) masked[i] &= ~TIMER_MASK; do_IRQ(TIMER0_INTR_VECT, regs); } - } #endif + } #ifdef IGNORE_MASK /* Remove IRQs that can't be handled as multiple. */ diff --git a/arch/cris/arch-v32/lib/Makefile b/arch/cris/arch-v32/lib/Makefile index eb4aad1..dd296b9 100644 --- a/arch/cris/arch-v32/lib/Makefile +++ b/arch/cris/arch-v32/lib/Makefile @@ -3,5 +3,5 @@ # lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o \ - csumcpfruser.o spinlock.o delay.o + csumcpfruser.o spinlock.o delay.o strcmp.o diff --git a/arch/cris/arch-v32/lib/strcmp.S b/arch/cris/arch-v32/lib/strcmp.S new file mode 100644 index 0000000..8f7a1ee --- /dev/null +++ b/arch/cris/arch-v32/lib/strcmp.S @@ -0,0 +1,21 @@ +; strcmp.S -- CRISv32 version. +; Copyright (C) 2008 AXIS Communications AB +; Written by Edgar E. Iglesias +; +; This source code is licensed under the GNU General Public License, +; Version 2. See the file COPYING for more details. + + .global strcmp + .type strcmp,@function +strcmp: +1: + move.b [$r10+], $r12 + seq $r13 + sub.b [$r11+], $r12 + or.b $r12, $r13 + beq 1b + nop + + ret + movs.b $r12, $r10 + .size strcmp, . - strcmp diff --git a/arch/cris/include/arch-v32/arch/spinlock.h b/arch/cris/include/arch-v32/arch/spinlock.h index 129756b..367a53e 100644 --- a/arch/cris/include/arch-v32/arch/spinlock.h +++ b/arch/cris/include/arch-v32/arch/spinlock.h @@ -78,7 +78,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) { __raw_spin_lock(&rw->slock); while (rw->lock != RW_LOCK_BIAS); - rw->lock == 0; + rw->lock = 0; __raw_spin_unlock(&rw->slock); } @@ -93,7 +93,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw) { __raw_spin_lock(&rw->slock); while (rw->lock != RW_LOCK_BIAS); - rw->lock == RW_LOCK_BIAS; + rw->lock = RW_LOCK_BIAS; __raw_spin_unlock(&rw->slock); } @@ -114,7 +114,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) int ret = 0; __raw_spin_lock(&rw->slock); if (rw->lock == RW_LOCK_BIAS) { - rw->lock == 0; + rw->lock = 0; ret = 1; } __raw_spin_unlock(&rw->slock); diff --git a/arch/cris/include/asm/string.h b/arch/cris/include/asm/string.h index 691190e..d5db39f 100644 --- a/arch/cris/include/asm/string.h +++ b/arch/cris/include/asm/string.h @@ -11,4 +11,10 @@ extern void *memcpy(void *, const void *, size_t); #define __HAVE_ARCH_MEMSET extern void *memset(void *, int, size_t); +#ifdef CONFIG_ETRAX_ARCH_V32 +/* For v32 we provide strcmp. */ +#define __HAVE_ARCH_STRCMP +extern int strcmp(const char *s1, const char *s2); +#endif + #endif diff --git a/arch/cris/mm/fault.c b/arch/cris/mm/fault.c index c4c76db..f925115 100644 --- a/arch/cris/mm/fault.c +++ b/arch/cris/mm/fault.c @@ -163,7 +163,7 @@ do_page_fault(unsigned long address, struct pt_regs *regs, * the fault. */ - fault = handle_mm_fault(mm, vma, address, writeaccess & 1); + fault = handle_mm_fault(mm, vma, address, (writeaccess & 1) ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/frv/mm/fault.c b/arch/frv/mm/fault.c index 05093d4..30f5d10 100644 --- a/arch/frv/mm/fault.c +++ b/arch/frv/mm/fault.c @@ -163,7 +163,7 @@ asmlinkage void do_page_fault(int datammu, unsigned long esr0, unsigned long ear * make sure we exit gracefully rather than endlessly redo * the fault. */ - fault = handle_mm_fault(mm, vma, ear0, write); + fault = handle_mm_fault(mm, vma, ear0, write ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/h8300/Kconfig.cpu b/arch/h8300/Kconfig.cpu index b65dcfe..6e2ecff 100644 --- a/arch/h8300/Kconfig.cpu +++ b/arch/h8300/Kconfig.cpu @@ -13,7 +13,7 @@ config H8300H_GENERIC config H8300H_AKI3068NET bool "AE-3068/69" - select CONFIG_H83068 + select H83068 help AKI-H8/3068F / AKI-H8/3069F Flashmicom LAN Board Support More Information. (Japanese Only) @@ -24,7 +24,7 @@ config H8300H_AKI3068NET config H8300H_H8MAX bool "H8MAX" - select CONFIG_H83068 + select H83068 help H8MAX Evaluation Board Support More Information. (Japanese Only) @@ -32,7 +32,7 @@ config H8300H_H8MAX config H8300H_SIM bool "H8/300H Simulator" - select CONFIG_H83007 + select H83007 help GDB Simulator Support More Information. @@ -45,7 +45,7 @@ config H8S_GENERIC config H8S_EDOSK2674 bool "EDOSK-2674" - select CONFIG_H8S2768 + select H8S2678 help Renesas EDOSK-2674 Evaluation Board Support More Information. diff --git a/arch/ia64/include/asm/iommu.h b/arch/ia64/include/asm/iommu.h index 0490794..745e095 100644 --- a/arch/ia64/include/asm/iommu.h +++ b/arch/ia64/include/asm/iommu.h @@ -9,6 +9,11 @@ extern void pci_iommu_shutdown(void); extern void no_iommu_init(void); extern int force_iommu, no_iommu; extern int iommu_detected; +#ifdef CONFIG_DMAR +extern int iommu_pass_through; +#else +#define iommu_pass_through (0) +#endif extern void iommu_dma_init(void); extern void machvec_init(const char *name); diff --git a/arch/ia64/kernel/acpi-processor.c b/arch/ia64/kernel/acpi-processor.c index cbe6cee..dbda7bd 100644 --- a/arch/ia64/kernel/acpi-processor.c +++ b/arch/ia64/kernel/acpi-processor.c @@ -71,3 +71,15 @@ void arch_acpi_processor_init_pdc(struct acpi_processor *pr) } EXPORT_SYMBOL(arch_acpi_processor_init_pdc); + +void arch_acpi_processor_cleanup_pdc(struct acpi_processor *pr) +{ + if (pr->pdc) { + kfree(pr->pdc->pointer->buffer.pointer); + kfree(pr->pdc->pointer); + kfree(pr->pdc); + pr->pdc = NULL; + } +} + +EXPORT_SYMBOL(arch_acpi_processor_cleanup_pdc); diff --git a/arch/ia64/kernel/pci-dma.c b/arch/ia64/kernel/pci-dma.c index 1376da4..0569596 100644 --- a/arch/ia64/kernel/pci-dma.c +++ b/arch/ia64/kernel/pci-dma.c @@ -32,6 +32,8 @@ int force_iommu __read_mostly = 1; int force_iommu __read_mostly; #endif +int iommu_pass_through; + /* Dummy device used for NULL arguments (normally ISA). Better would be probably a smaller DMA mask, but this is bug-to-bug compatible to i386. */ diff --git a/arch/ia64/kernel/pci-swiotlb.c b/arch/ia64/kernel/pci-swiotlb.c index 285aae8..223abb1 100644 --- a/arch/ia64/kernel/pci-swiotlb.c +++ b/arch/ia64/kernel/pci-swiotlb.c @@ -46,7 +46,7 @@ void __init swiotlb_dma_init(void) void __init pci_swiotlb_init(void) { - if (!iommu_detected) { + if (!iommu_detected || iommu_pass_through) { #ifdef CONFIG_IA64_GENERIC swiotlb = 1; printk(KERN_INFO "PCI-DMA: Re-initialize machine vector.\n"); diff --git a/arch/ia64/kvm/kvm_lib.c b/arch/ia64/kvm/kvm_lib.c index a85cb61..f1268b8 100644 --- a/arch/ia64/kvm/kvm_lib.c +++ b/arch/ia64/kvm/kvm_lib.c @@ -11,5 +11,11 @@ * */ #undef CONFIG_MODULES +#include <linux/module.h> +#undef CONFIG_KALLSYMS +#undef EXPORT_SYMBOL +#undef EXPORT_SYMBOL_GPL +#define EXPORT_SYMBOL(sym) +#define EXPORT_SYMBOL_GPL(sym) #include "../../../lib/vsprintf.c" #include "../../../lib/ctype.c" diff --git a/arch/ia64/mm/fault.c b/arch/ia64/mm/fault.c index 23088be..19261a9 100644 --- a/arch/ia64/mm/fault.c +++ b/arch/ia64/mm/fault.c @@ -154,7 +154,7 @@ ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *re * sure we exit gracefully rather than endlessly redo the * fault. */ - fault = handle_mm_fault(mm, vma, address, (mask & VM_WRITE) != 0); + fault = handle_mm_fault(mm, vma, address, (mask & VM_WRITE) ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { /* * We ran out of memory, or some other thing happened diff --git a/arch/m32r/mm/fault.c b/arch/m32r/mm/fault.c index 4a71df4..7274b47 100644 --- a/arch/m32r/mm/fault.c +++ b/arch/m32r/mm/fault.c @@ -196,7 +196,7 @@ survive: */ addr = (address & PAGE_MASK); set_thread_fault_code(error_code); - fault = handle_mm_fault(mm, vma, addr, write); + fault = handle_mm_fault(mm, vma, addr, write ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/m68k/mm/fault.c b/arch/m68k/mm/fault.c index f493f03..d0e35cf 100644 --- a/arch/m68k/mm/fault.c +++ b/arch/m68k/mm/fault.c @@ -155,7 +155,7 @@ good_area: */ survive: - fault = handle_mm_fault(mm, vma, address, write); + fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0); #ifdef DEBUG printk("handle_mm_fault returns %d\n",fault); #endif diff --git a/arch/microblaze/kernel/init_task.c b/arch/microblaze/kernel/init_task.c index 48eb9fb..67da225 100644 --- a/arch/microblaze/kernel/init_task.c +++ b/arch/microblaze/kernel/init_task.c @@ -18,8 +18,6 @@ static struct signal_struct init_signals = INIT_SIGNALS(init_signals); static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); -struct mm_struct init_mm = INIT_MM(init_mm); -EXPORT_SYMBOL(init_mm); union thread_union init_thread_union __attribute__((__section__(".data.init_task"))) = diff --git a/arch/microblaze/kernel/vmlinux.lds.S b/arch/microblaze/kernel/vmlinux.lds.S index 8ae807a..d34d38d 100644 --- a/arch/microblaze/kernel/vmlinux.lds.S +++ b/arch/microblaze/kernel/vmlinux.lds.S @@ -62,7 +62,8 @@ SECTIONS { _sdata = . ; .data ALIGN (4096) : { /* page aligned when MMU used - origin 0x4 */ - *(.data) + DATA_DATA + CONSTRUCTORS } . = ALIGN(32); .data.cacheline_aligned : { *(.data.cacheline_aligned) } @@ -98,13 +99,13 @@ SECTIONS { . = ALIGN(4096); .init.text : { _sinittext = . ; - *(.init.text) - *(.exit.text) - *(.exit.data) + INIT_TEXT _einittext = .; } - .init.data : { *(.init.data) } + .init.data : { + INIT_DATA + } . = ALIGN(4); .init.ivt : { diff --git a/arch/microblaze/mm/fault.c b/arch/microblaze/mm/fault.c index 5e67cd1..956607a 100644 --- a/arch/microblaze/mm/fault.c +++ b/arch/microblaze/mm/fault.c @@ -232,7 +232,7 @@ good_area: * the fault. */ survive: - fault = handle_mm_fault(mm, vma, address, is_write); + fault = handle_mm_fault(mm, vma, address, is_write ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b29f028..8c4be1f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -601,6 +601,7 @@ config CAVIUM_OCTEON_SIMULATOR select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_HOTPLUG_CPU select SYS_HAS_CPU_CAVIUM_OCTEON help The Octeon simulator is software performance model of the Cavium @@ -615,6 +616,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_HOTPLUG_CPU select SYS_HAS_EARLY_PRINTK select SYS_HAS_CPU_CAVIUM_OCTEON select SWAP_IO_SPACE @@ -784,8 +786,17 @@ config SYS_HAS_EARLY_PRINTK bool config HOTPLUG_CPU + bool "Support for hot-pluggable CPUs" + depends on SMP && HOTPLUG && SYS_SUPPORTS_HOTPLUG_CPU + help + Say Y here to allow turning CPUs off and on. CPUs can be + controlled through /sys/devices/system/cpu. + (Note: power management support will enable this option + automatically on SMP systems. ) + Say N if you want to disable CPU hotplug. + +config SYS_SUPPORTS_HOTPLUG_CPU bool - default n config I8259 bool @@ -2136,11 +2147,11 @@ menu "Power management options" config ARCH_HIBERNATION_POSSIBLE def_bool y - depends on !SMP + depends on SYS_SUPPORTS_HOTPLUG_CPU config ARCH_SUSPEND_POSSIBLE def_bool y - depends on !SMP + depends on SYS_SUPPORTS_HOTPLUG_CPU source "kernel/power/Kconfig" diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 8dfa009..384f184 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -7,7 +7,7 @@ */ #include <linux/irq.h> #include <linux/interrupt.h> -#include <linux/hardirq.h> +#include <linux/smp.h> #include <asm/octeon/octeon.h> #include <asm/octeon/cvmx-pexp-defs.h> @@ -501,3 +501,62 @@ asmlinkage void plat_irq_dispatch(void) } } } + +#ifdef CONFIG_HOTPLUG_CPU +static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu) +{ + unsigned int isset; +#ifdef CONFIG_SMP + int coreid = cpu_logical_map(cpu); +#else + int coreid = cvmx_get_core_num(); +#endif + int bit = (irq < OCTEON_IRQ_WDOG0) ? + irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0; + if (irq < 64) { + isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) & + (1ull << bit)) >> bit; + } else { + isset = (cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)) & + (1ull << bit)) >> bit; + } + return isset; +} + +void fixup_irqs(void) +{ + int irq; + + for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) + octeon_irq_core_disable_local(irq); + + for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_GPIO15; irq++) { + if (is_irq_enabled_on_cpu(irq, smp_processor_id())) { + /* ciu irq migrates to next cpu */ + octeon_irq_chip_ciu0.disable(irq); + octeon_irq_ciu0_set_affinity(irq, &cpu_online_map); + } + } + +#if 0 + for (irq = OCTEON_IRQ_MBOX0; irq <= OCTEON_IRQ_MBOX1; irq++) + octeon_irq_mailbox_mask(irq); +#endif + for (irq = OCTEON_IRQ_UART0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { + if (is_irq_enabled_on_cpu(irq, smp_processor_id())) { + /* ciu irq migrates to next cpu */ + octeon_irq_chip_ciu0.disable(irq); + octeon_irq_ciu0_set_affinity(irq, &cpu_online_map); + } + } + + for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED135; irq++) { + if (is_irq_enabled_on_cpu(irq, smp_processor_id())) { + /* ciu irq migrates to next cpu */ + octeon_irq_chip_ciu1.disable(irq); + octeon_irq_ciu1_set_affinity(irq, &cpu_online_map); + } + } +} + +#endif /* CONFIG_HOTPLUG_CPU */ diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h new file mode 100644 index 0000000..0f7f84a --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_boot.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2004, 2005 Cavium Networks + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __OCTEON_BOOT_H__ +#define __OCTEON_BOOT_H__ + +#include <linux/types.h> + +struct boot_init_vector { + uint32_t stack_addr; + uint32_t code_addr; + uint32_t app_start_func_addr; + uint32_t k0_val; + uint32_t flags; + uint32_t boot_info_addr; + uint32_t pad; + uint32_t pad2; +}; + +/* similar to bootloader's linux_app_boot_info but without global data */ +struct linux_app_boot_info { + uint32_t labi_signature; + uint32_t start_core0_addr; + uint32_t avail_coremask; + uint32_t pci_console_active; + uint32_t icache_prefetch_disable; + uint32_t InitTLBStart_addr; + uint32_t start_app_addr; + uint32_t cur_exception_base; + uint32_t no_mark_private_data; + uint32_t compact_flash_common_base_addr; + uint32_t compact_flash_attribute_base_addr; + uint32_t led_display_base_addr; +}; + +/* If not to copy a lot of bootloader's structures + here is only offset of requested member */ +#define AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK 0x765c + +/* hardcoded in bootloader */ +#define LABI_ADDR_IN_BOOTLOADER 0x700 + +#define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot" + +#define LABI_SIGNATURE 0xAABBCCDD + +/* from uboot-headers/octeon_mem_map.h */ +#define EXCEPTION_BASE_INCR (4 * 1024) + /* Increment size for exception base addresses (4k minimum) */ +#define EXCEPTION_BASE_BASE 0 +#define BOOTLOADER_PRIV_DATA_BASE (EXCEPTION_BASE_BASE + 0x800) +#define BOOTLOADER_BOOT_VECTOR (BOOTLOADER_PRIV_DATA_BASE) + +#endif /* __OCTEON_BOOT_H__ */ diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 5f4e49b..da55924 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -13,6 +13,7 @@ #include <linux/io.h> #include <linux/irq.h> #include <linux/serial.h> +#include <linux/smp.h> #include <linux/types.h> #include <linux/string.h> /* for memset */ #include <linux/tty.h> diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 24e0ad6..0b891a9 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -5,6 +5,7 @@ * * Copyright (C) 2004-2008 Cavium Networks */ +#include <linux/cpu.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/smp.h> @@ -19,10 +20,16 @@ #include <asm/octeon/octeon.h> +#include "octeon_boot.h" + volatile unsigned long octeon_processor_boot = 0xff; volatile unsigned long octeon_processor_sp; volatile unsigned long octeon_processor_gp; +#ifdef CONFIG_HOTPLUG_CPU +static unsigned int InitTLBStart_addr; +#endif + static irqreturn_t mailbox_interrupt(int irq, void *dev_id) { const int coreid = cvmx_get_core_num(); @@ -67,8 +74,28 @@ static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action) } /** - * Detect available CPUs, populate phys_cpu_present_map + * Detect available CPUs, populate cpu_possible_map */ +static void octeon_smp_hotplug_setup(void) +{ +#ifdef CONFIG_HOTPLUG_CPU + uint32_t labi_signature; + + labi_signature = + cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + LABI_ADDR_IN_BOOTLOADER + + offsetof(struct linux_app_boot_info, + labi_signature))); + if (labi_signature != LABI_SIGNATURE) + pr_err("The bootloader version on this board is incorrect\n"); + InitTLBStart_addr = + cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + LABI_ADDR_IN_BOOTLOADER + + offsetof(struct linux_app_boot_info, + InitTLBStart_addr))); +#endif +} + static void octeon_smp_setup(void) { const int coreid = cvmx_get_core_num(); @@ -91,6 +118,9 @@ static void octeon_smp_setup(void) cpus++; } } + cpu_present_map = cpu_possible_map; + + octeon_smp_hotplug_setup(); } /** @@ -128,6 +158,17 @@ static void octeon_init_secondary(void) const int coreid = cvmx_get_core_num(); union cvmx_ciu_intx_sum0 interrupt_enable; +#ifdef CONFIG_HOTPLUG_CPU + unsigned int cur_exception_base; + + cur_exception_base = cvmx_read64_uint32( + CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + LABI_ADDR_IN_BOOTLOADER + + offsetof(struct linux_app_boot_info, + cur_exception_base))); + /* cur_exception_base is incremented in bootloader after setting */ + write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR)); +#endif octeon_check_cpu_bist(); octeon_init_cvmcount(); /* @@ -199,6 +240,193 @@ static void octeon_cpus_done(void) #endif } +#ifdef CONFIG_HOTPLUG_CPU + +/* State of each CPU. */ +DEFINE_PER_CPU(int, cpu_state); + +extern void fixup_irqs(void); + +static DEFINE_SPINLOCK(smp_reserve_lock); + +static int octeon_cpu_disable(void) +{ + unsigned int cpu = smp_processor_id(); + + if (cpu == 0) + return -EBUSY; + + spin_lock(&smp_reserve_lock); + + cpu_clear(cpu, cpu_online_map); + cpu_clear(cpu, cpu_callin_map); + local_irq_disable(); + fixup_irqs(); + local_irq_enable(); + + flush_cache_all(); + local_flush_tlb_all(); + + spin_unlock(&smp_reserve_lock); + + return 0; +} + +static void octeon_cpu_die(unsigned int cpu) +{ + int coreid = cpu_logical_map(cpu); + uint32_t avail_coremask; + struct cvmx_bootmem_named_block_desc *block_desc; + +#ifdef CONFIG_CAVIUM_OCTEON_WATCHDOG + /* Disable the watchdog */ + cvmx_ciu_wdogx_t ciu_wdog; + ciu_wdog.u64 = cvmx_read_csr(CVMX_CIU_WDOGX(cpu)); + ciu_wdog.s.mode = 0; + cvmx_write_csr(CVMX_CIU_WDOGX(cpu), ciu_wdog.u64); +#endif + + while (per_cpu(cpu_state, cpu) != CPU_DEAD) + cpu_relax(); + + /* + * This is a bit complicated strategics of getting/settig available + * cores mask, copied from bootloader + */ + /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */ + block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); + + if (!block_desc) { + avail_coremask = + cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + LABI_ADDR_IN_BOOTLOADER + + offsetof + (struct linux_app_boot_info, + avail_coremask))); + } else { /* alternative, already initialized */ + avail_coremask = + cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + block_desc->base_addr + + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK)); + } + + avail_coremask |= 1 << coreid; + + /* Setting avail_coremask for bootoct binary */ + if (!block_desc) { + cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + LABI_ADDR_IN_BOOTLOADER + + offsetof(struct linux_app_boot_info, + avail_coremask)), + avail_coremask); + } else { + cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + block_desc->base_addr + + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK), + avail_coremask); + } + + pr_info("Reset core %d. Available Coremask = %x \n", coreid, + avail_coremask); + cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); + cvmx_write_csr(CVMX_CIU_PP_RST, 0); +} + +void play_dead(void) +{ + int coreid = cvmx_get_core_num(); + + idle_task_exit(); + octeon_processor_boot = 0xff; + per_cpu(cpu_state, coreid) = CPU_DEAD; + + while (1) /* core will be reset here */ + ; +} + +extern void kernel_entry(unsigned long arg1, ...); + +static void start_after_reset(void) +{ + kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */ +} + +int octeon_update_boot_vector(unsigned int cpu) +{ + + int coreid = cpu_logical_map(cpu); + unsigned int avail_coremask; + struct cvmx_bootmem_named_block_desc *block_desc; + struct boot_init_vector *boot_vect = + (struct boot_init_vector *) cvmx_phys_to_ptr(0x0 + + BOOTLOADER_BOOT_VECTOR); + + block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); + + if (!block_desc) { + avail_coremask = + cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + LABI_ADDR_IN_BOOTLOADER + + offsetof(struct linux_app_boot_info, + avail_coremask))); + } else { /* alternative, already initialized */ + avail_coremask = + cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + block_desc->base_addr + + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK)); + } + + if (!(avail_coremask & (1 << coreid))) { + /* core not available, assume, that catched by simple-executive */ + cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); + cvmx_write_csr(CVMX_CIU_PP_RST, 0); + } + + boot_vect[coreid].app_start_func_addr = + (uint32_t) (unsigned long) start_after_reset; + boot_vect[coreid].code_addr = InitTLBStart_addr; + + CVMX_SYNC; + + cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); + + return 0; +} + +static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb, + unsigned long action, void *hcpu) +{ + unsigned int cpu = (unsigned long)hcpu; + + switch (action) { + case CPU_UP_PREPARE: + octeon_update_boot_vector(cpu); + break; + case CPU_ONLINE: + pr_info("Cpu %d online\n", cpu); + break; + case CPU_DEAD: + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block __cpuinitdata octeon_cpu_notifier = { + .notifier_call = octeon_cpu_callback, +}; + +static int __cpuinit register_cavium_notifier(void) +{ + register_hotcpu_notifier(&octeon_cpu_notifier); + + return 0; +} + +late_initcall(register_cavium_notifier); + +#endif /* CONFIG_HOTPLUG_CPU */ + struct plat_smp_ops octeon_smp_ops = { .send_ipi_single = octeon_send_ipi_single, .send_ipi_mask = octeon_send_ipi_mask, @@ -208,4 +436,8 @@ struct plat_smp_ops octeon_smp_ops = { .boot_secondary = octeon_boot_secondary, .smp_setup = octeon_smp_setup, .prepare_cpus = octeon_prepare_cpus, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_disable = octeon_cpu_disable, + .cpu_die = octeon_cpu_die, +#endif }; diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h index 08ea468..6cf29c2 100644 --- a/arch/mips/include/asm/bug.h +++ b/arch/mips/include/asm/bug.h @@ -1,6 +1,7 @@ #ifndef __ASM_BUG_H #define __ASM_BUG_H +#include <linux/compiler.h> #include <asm/sgidefs.h> #ifdef CONFIG_BUG diff --git a/arch/mips/include/asm/bugs.h b/arch/mips/include/asm/bugs.h index 9dc10df..b160a70 100644 --- a/arch/mips/include/asm/bugs.h +++ b/arch/mips/include/asm/bugs.h @@ -11,6 +11,7 @@ #include <linux/bug.h> #include <linux/delay.h> +#include <linux/smp.h> #include <asm/cpu.h> #include <asm/cpu-info.h> diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index 4f1eed1..09b08d0 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -10,6 +10,7 @@ #define _ASM_IRQ_H #include <linux/linkage.h> +#include <linux/smp.h> #include <asm/mipsmtregs.h> diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index d7f3eb0..d3bea88 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -13,6 +13,7 @@ #include <linux/errno.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/slab.h> #include <asm/cacheflush.h> #include <asm/tlbflush.h> diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h index 64ffc02..fd54554 100644 --- a/arch/mips/include/asm/smp-ops.h +++ b/arch/mips/include/asm/smp-ops.h @@ -26,6 +26,10 @@ struct plat_smp_ops { void (*boot_secondary)(int cpu, struct task_struct *idle); void (*smp_setup)(void); void (*prepare_cpus)(unsigned int max_cpus); +#ifdef CONFIG_HOTPLUG_CPU + int (*cpu_disable)(void); + void (*cpu_die)(unsigned int cpu); +#endif }; extern void register_smp_ops(struct plat_smp_ops *ops); diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index 40e5ef1..aaa2d4a 100644 --- a/arch/mips/include/asm/smp.h +++ b/arch/mips/include/asm/smp.h @@ -13,6 +13,7 @@ #include <linux/bitops.h> #include <linux/linkage.h> +#include <linux/smp.h> #include <linux/threads.h> #include <linux/cpumask.h> @@ -40,6 +41,7 @@ extern int __cpu_logical_map[NR_CPUS]; /* Octeon - Tell another core to flush its icache */ #define SMP_ICACHE_FLUSH 0x4 +extern volatile cpumask_t cpu_callin_map; extern void asmlinkage smp_bootstrap(void); @@ -55,6 +57,24 @@ static inline void smp_send_reschedule(int cpu) mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF); } +#ifdef CONFIG_HOTPLUG_CPU +static inline int __cpu_disable(void) +{ + extern struct plat_smp_ops *mp_ops; /* private */ + + return mp_ops->cpu_disable(); +} + +static inline void __cpu_die(unsigned int cpu) +{ + extern struct plat_smp_ops *mp_ops; /* private */ + + mp_ops->cpu_die(cpu); +} + +extern void play_dead(void); +#endif + extern asmlinkage void smp_call_function_interrupt(void); extern void arch_send_call_function_single_ipi(int cpu); diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h index 3a56d90..2367b56 100644 --- a/arch/mips/include/asm/sn/addrs.h +++ b/arch/mips/include/asm/sn/addrs.h @@ -11,6 +11,7 @@ #ifndef __ASSEMBLY__ +#include <linux/smp.h> #include <linux/types.h> #endif /* !__ASSEMBLY__ */ diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index d9b6a5b..7fd170d 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -10,6 +10,7 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/kernel.h> +#include <linux/smp.h> #include <linux/spinlock.h> #include <asm/irq_cpu.h> diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c index a5182a2..e02f79b 100644 --- a/arch/mips/kernel/cevt-bcm1480.c +++ b/arch/mips/kernel/cevt-bcm1480.c @@ -18,6 +18,7 @@ #include <linux/clockchips.h> #include <linux/interrupt.h> #include <linux/percpu.h> +#include <linux/smp.h> #include <asm/addrspace.h> #include <asm/io.h> diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 0015e44..2652362 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -9,6 +9,7 @@ #include <linux/clockchips.h> #include <linux/interrupt.h> #include <linux/percpu.h> +#include <linux/smp.h> #include <asm/smtc_ipi.h> #include <asm/time.h> diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c index 340f53e..ac5903d 100644 --- a/arch/mips/kernel/cevt-sb1250.c +++ b/arch/mips/kernel/cevt-sb1250.c @@ -18,6 +18,7 @@ #include <linux/clockchips.h> #include <linux/interrupt.h> #include <linux/percpu.h> +#include <linux/smp.h> #include <asm/addrspace.h> #include <asm/io.h> diff --git a/arch/mips/kernel/cevt-smtc.c b/arch/mips/kernel/cevt-smtc.c index df6f5bc..98bd7de 100644 --- a/arch/mips/kernel/cevt-smtc.c +++ b/arch/mips/kernel/cevt-smtc.c @@ -10,6 +10,7 @@ #include <linux/clockchips.h> #include <linux/interrupt.h> #include <linux/percpu.h> +#include <linux/smp.h> #include <asm/smtc_ipi.h> #include <asm/time.h> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index b13b8eb..1abe990 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -14,6 +14,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/ptrace.h> +#include <linux/smp.h> #include <linux/stddef.h> #include <asm/bugs.h> diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c index ed20e7f..f7d8d5d 100644 --- a/arch/mips/kernel/i8253.c +++ b/arch/mips/kernel/i8253.c @@ -7,6 +7,7 @@ #include <linux/interrupt.h> #include <linux/jiffies.h> #include <linux/module.h> +#include <linux/smp.h> #include <linux/spinlock.h> #include <asm/delay.h> diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index 3f43c2e..39000f1 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -2,6 +2,7 @@ #include <linux/bitmap.h> #include <linux/init.h> +#include <linux/smp.h> #include <asm/io.h> #include <asm/gic.h> diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c index 6e152c8..50c9bb8 100644 --- a/arch/mips/kernel/kgdb.c +++ b/arch/mips/kernel/kgdb.c @@ -26,6 +26,7 @@ #include <linux/kgdb.h> #include <linux/kdebug.h> #include <linux/sched.h> +#include <linux/smp.h> #include <asm/inst.h> #include <asm/fpu.h> #include <asm/cacheflush.h> diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 1eaaa45..c09d681 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -50,10 +50,15 @@ */ void __noreturn cpu_idle(void) { + int cpu; + + /* CPU is going idle. */ + cpu = smp_processor_id(); + /* endless idle loop with no priority at all */ while (1) { tick_nohz_stop_sched_tick(1); - while (!need_resched()) { + while (!need_resched() && cpu_online(cpu)) { #ifdef CONFIG_MIPS_MT_SMTC extern void smtc_idle_loop_hook(void); @@ -62,6 +67,12 @@ void __noreturn cpu_idle(void) if (cpu_wait) (*cpu_wait)(); } +#ifdef CONFIG_HOTPLUG_CPU + if (!cpu_online(cpu) && !cpu_isset(cpu, cpu_callin_map) && + (system_state == SYSTEM_RUNNING || + system_state == SYSTEM_BOOTING)) + play_dead(); +#endif tick_nohz_restart_sched_tick(); preempt_enable_no_resched(); schedule(); diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index f27beca..653be06 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -20,6 +20,7 @@ #include <linux/kernel.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/cpumask.h> #include <linux/interrupt.h> #include <linux/compiler.h> diff --git a/arch/mips/kernel/smp-up.c b/arch/mips/kernel/smp-up.c index 878e373..2508d55 100644 --- a/arch/mips/kernel/smp-up.c +++ b/arch/mips/kernel/smp-up.c @@ -55,6 +55,18 @@ static void __init up_prepare_cpus(unsigned int max_cpus) { } +#ifdef CONFIG_HOTPLUG_CPU +static int up_cpu_disable(void) +{ + return -ENOSYS; +} + +static void up_cpu_die(unsigned int cpu) +{ + BUG(); +} +#endif + struct plat_smp_ops up_smp_ops = { .send_ipi_single = up_send_ipi_single, .send_ipi_mask = up_send_ipi_mask, @@ -64,4 +76,8 @@ struct plat_smp_ops up_smp_ops = { .boot_secondary = up_boot_secondary, .smp_setup = up_smp_setup, .prepare_cpus = up_prepare_cpus, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_disable = up_cpu_disable, + .cpu_die = up_cpu_die, +#endif }; diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index c937506..bc7d9b0 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -22,6 +22,7 @@ #include <linux/delay.h> #include <linux/init.h> #include <linux/interrupt.h> +#include <linux/smp.h> #include <linux/spinlock.h> #include <linux/threads.h> #include <linux/module.h> @@ -44,7 +45,7 @@ #include <asm/mipsmtregs.h> #endif /* CONFIG_MIPS_MT_SMTC */ -static volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ +volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ @@ -200,6 +201,8 @@ void __devinit smp_prepare_boot_cpu(void) * and keep control until "cpu_online(cpu)" is set. Note: cpu is * physical, not logical. */ +static struct task_struct *cpu_idle_thread[NR_CPUS]; + int __cpuinit __cpu_up(unsigned int cpu) { struct task_struct *idle; @@ -209,9 +212,16 @@ int __cpuinit __cpu_up(unsigned int cpu) * The following code is purely to make sure * Linux can schedule processes on this slave. */ - idle = fork_idle(cpu); - if (IS_ERR(idle)) - panic(KERN_ERR "Fork failed for CPU %d", cpu); + if (!cpu_idle_thread[cpu]) { + idle = fork_idle(cpu); + cpu_idle_thread[cpu] = idle; + + if (IS_ERR(idle)) + panic(KERN_ERR "Fork failed for CPU %d", cpu); + } else { + idle = cpu_idle_thread[cpu]; + init_idle(idle, cpu); + } mp_ops->boot_secondary(cpu, idle); diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 37d51cd..8a0626c 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -20,6 +20,7 @@ #include <linux/clockchips.h> #include <linux/kernel.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/cpumask.h> #include <linux/interrupt.h> #include <linux/kernel_stat.h> diff --git a/arch/mips/kernel/topology.c b/arch/mips/kernel/topology.c index 660e44e..cf3eb61 100644 --- a/arch/mips/kernel/topology.c +++ b/arch/mips/kernel/topology.c @@ -17,7 +17,10 @@ static int __init topology_init(void) #endif /* CONFIG_NUMA */ for_each_present_cpu(i) { - ret = register_cpu(&per_cpu(cpu_devices, i), i); + struct cpu *c = &per_cpu(cpu_devices, i); + + c->hotpluggable = 1; + ret = register_cpu(c, i); if (ret) printk(KERN_WARNING "topology_init: register_cpu %d " "failed (%d)\n", i, ret); diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c index 881ecbc..0cea932 100644 --- a/arch/mips/mipssim/sim_time.c +++ b/arch/mips/mipssim/sim_time.c @@ -91,6 +91,7 @@ unsigned __cpuinit get_c0_compare_int(void) mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; } else { #endif + { if (cpu_has_vint) set_vi_handler(cp0_compare_irq, mips_timer_dispatch); mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index 44d01a0..b165cdc 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -8,6 +8,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/mm.h> #include <linux/bitops.h> #include <linux/cpu.h> diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c index 5500c20..54e5f7b 100644 --- a/arch/mips/mm/c-r3k.c +++ b/arch/mips/mm/c-r3k.c @@ -12,6 +12,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/mm.h> #include <asm/page.h> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 71fe4cb..6721ee2b1 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -13,6 +13,7 @@ #include <linux/kernel.h> #include <linux/linkage.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/mm.h> #include <linux/module.h> #include <linux/bitops.h> diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index f7c8f9c..6515b44 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -11,6 +11,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/mm.h> #include <asm/cacheops.h> diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index 55767ad..6751ce9 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -102,7 +102,7 @@ good_area: * make sure we exit gracefully rather than endlessly redo * the fault. */ - fault = handle_mm_fault(mm, vma, address, write); + fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c index 2b1309b..e274fda 100644 --- a/arch/mips/mm/highmem.c +++ b/arch/mips/mm/highmem.c @@ -1,5 +1,6 @@ #include <linux/module.h> #include <linux/highmem.h> +#include <linux/smp.h> #include <asm/fixmap.h> #include <asm/tlbflush.h> diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index c551129..0e82050 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -13,6 +13,7 @@ #include <linux/module.h> #include <linux/signal.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/kernel.h> #include <linux/errno.h> #include <linux/string.h> diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 48060c6..f5c7375 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -10,6 +10,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/mm.h> #include <linux/module.h> #include <linux/proc_fs.h> diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c index 1c0048a..0f5ab23 100644 --- a/arch/mips/mm/tlb-r3k.c +++ b/arch/mips/mm/tlb-r3k.c @@ -13,6 +13,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/mm.h> #include <asm/page.h> diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index f60fe51..cee502c 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -10,6 +10,7 @@ */ #include <linux/init.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/mm.h> #include <linux/hugetlb.h> diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c index 4ec95cc..2b82f23 100644 --- a/arch/mips/mm/tlb-r8k.c +++ b/arch/mips/mm/tlb-r8k.c @@ -10,6 +10,7 @@ */ #include <linux/init.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/mm.h> #include <asm/cpu.h> diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 8f606ea..9a17bf8 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -23,6 +23,7 @@ #include <linux/bug.h> #include <linux/kernel.h> #include <linux/types.h> +#include <linux/smp.h> #include <linux/string.h> #include <linux/init.h> diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index ea17611..b4eaf13 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -24,6 +24,7 @@ #include <linux/init.h> #include <linux/irq.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/io.h> diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index dda6f20..a0e726e 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -10,6 +10,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/pci.h> +#include <linux/smp.h> #include <asm/sn/arch.h> #include <asm/pci/bridge.h> #include <asm/paccess.h> diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c index f78c29b..8ace277 100644 --- a/arch/mips/pmc-sierra/yosemite/smp.c +++ b/arch/mips/pmc-sierra/yosemite/smp.c @@ -1,5 +1,6 @@ #include <linux/linkage.h> #include <linux/sched.h> +#include <linux/smp.h> #include <asm/pmon.h> #include <asm/titan_dep.h> diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S index 486bd3f..4b8174b 100644 --- a/arch/mips/power/hibernate.S +++ b/arch/mips/power/hibernate.S @@ -43,15 +43,6 @@ LEAF(swsusp_arch_resume) bne t1, t3, 1b PTR_L t0, PBE_NEXT(t0) bnez t0, 0b - /* flush caches to make sure context is in memory */ - PTR_L t0, __flush_cache_all - jalr t0 - /* flush tlb entries */ -#ifdef CONFIG_SMP - jal flush_tlb_all -#else - jal local_flush_tlb_all -#endif PTR_LA t0, saved_regs PTR_L ra, PT_R31(t0) PTR_L sp, PT_R29(t0) diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c index 4a500e8..51d3a4f 100644 --- a/arch/mips/sgi-ip27/ip27-init.c +++ b/arch/mips/sgi-ip27/ip27-init.c @@ -9,6 +9,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/sched.h> +#include <linux/smp.h> #include <linux/mm.h> #include <linux/module.h> #include <linux/cpumask.h> diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 1bb692a..c1c8e40 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -18,6 +18,7 @@ #include <linux/ioport.h> #include <linux/timex.h> #include <linux/slab.h> +#include <linux/smp.h> #include <linux/random.h> #include <linux/kernel.h> #include <linux/kernel_stat.h> diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index f10a7cd..6d0e59f 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -10,6 +10,7 @@ #include <linux/interrupt.h> #include <linux/kernel_stat.h> #include <linux/param.h> +#include <linux/smp.h> #include <linux/time.h> #include <linux/timex.h> #include <linux/mm.h> diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c index 6ae64e8..5e871e7 100644 --- a/arch/mips/sgi-ip27/ip27-xtalk.c +++ b/arch/mips/sgi-ip27/ip27-xtalk.c @@ -9,6 +9,7 @@ #include <linux/init.h> #include <linux/kernel.h> +#include <linux/smp.h> #include <asm/sn/types.h> #include <asm/sn/klconfig.h> #include <asm/sn/hub.h> diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index 690de06..ba59839 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -19,6 +19,7 @@ #include <linux/init.h> #include <linux/linkage.h> #include <linux/interrupt.h> +#include <linux/smp.h> #include <linux/spinlock.h> #include <linux/mm.h> #include <linux/slab.h> diff --git a/arch/mips/sibyte/common/cfe_console.c b/arch/mips/sibyte/common/cfe_console.c index 81e3d54..1ad2da1 100644 --- a/arch/mips/sibyte/common/cfe_console.c +++ b/arch/mips/sibyte/common/cfe_console.c @@ -51,12 +51,13 @@ static int cfe_console_setup(struct console *cons, char *str) setleds("u0cn"); } else if (!strcmp(consdev, "uart1")) { setleds("u1cn"); + } else #endif #ifdef CONFIG_VGA_CONSOLE - } else if (!strcmp(consdev, "pcconsole0")) { - setleds("pccn"); -#endif + if (!strcmp(consdev, "pcconsole0")) { + setleds("pccn"); } else +#endif return -ENODEV; } return 0; diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c index 69f5f88..0d9ec1a 100644 --- a/arch/mips/sni/time.c +++ b/arch/mips/sni/time.c @@ -1,5 +1,6 @@ #include <linux/types.h> #include <linux/interrupt.h> +#include <linux/smp.h> #include <linux/time.h> #include <linux/clockchips.h> diff --git a/arch/mn10300/kernel/vmlinux.lds.S b/arch/mn10300/kernel/vmlinux.lds.S index 24de6b9..bcebcef 100644 --- a/arch/mn10300/kernel/vmlinux.lds.S +++ b/arch/mn10300/kernel/vmlinux.lds.S @@ -38,14 +38,10 @@ SECTIONS _etext = .; /* End of text section */ - . = ALIGN(16); /* Exception table */ - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - + EXCEPTION_TABLE(16) BUG_TABLE - RODATA + RO_DATA(PAGE_SIZE) /* writeable */ .data : { /* Data */ @@ -53,27 +49,19 @@ SECTIONS CONSTRUCTORS } - . = ALIGN(PAGE_SIZE); - __nosave_begin = .; - .data_nosave : { *(.data.nosave) } - . = ALIGN(PAGE_SIZE); - __nosave_end = .; - - . = ALIGN(PAGE_SIZE); - .data.page_aligned : { *(.data.idt) } + .data_nosave : { NOSAVE_DATA; } - . = ALIGN(32); - .data.cacheline_aligned : { *(.data.cacheline_aligned) } + .data.page_aligned : { PAGE_ALIGNED_DATA(PAGE_SIZE); } + .data.cacheline_aligned : { CACHELINE_ALIGNED_DATA(32); } /* rarely changed data like cpu maps */ . = ALIGN(32); .data.read_mostly : AT(ADDR(.data.read_mostly)) { - *(.data.read_mostly) + READ_MOSTLY_DATA(32); _edata = .; /* End of data section */ } - . = ALIGN(THREAD_SIZE); /* init_task */ - .data.init_task : { *(.data.init_task) } + .data.init_task : { INIT_TASK(THREAD_SIZE); } /* might get freed after init */ . = ALIGN(PAGE_SIZE); @@ -88,23 +76,18 @@ SECTIONS __init_begin = .; .init.text : { _sinittext = .; - *(.init.text) + INIT_TEXT; _einittext = .; } - .init.data : { *(.init.data) } - . = ALIGN(16); - __setup_start = .; - .setup.init : { KEEP(*(.init.setup)) } - __setup_end = .; + .init.data : { INIT_DATA; } + .setup.init : { INIT_SETUP(16); } __initcall_start = .; .initcall.init : { INITCALLS } __initcall_end = .; - __con_initcall_start = .; - .con_initcall.init : { *(.con_initcall.init) } - __con_initcall_end = .; + .con_initcall.init : { CON_INITCALL; } SECURITY_INIT . = ALIGN(4); @@ -114,28 +97,17 @@ SECTIONS .altinstr_replacement : { *(.altinstr_replacement) } /* .exit.text is discard at runtime, not link time, to deal with references from .altinstructions and .eh_frame */ - .exit.text : { *(.exit.text) } - .exit.data : { *(.exit.data) } + .exit.text : { EXIT_TEXT; } + .exit.data : { EXIT_DATA; } -#ifdef CONFIG_BLK_DEV_INITRD - . = ALIGN(PAGE_SIZE); - __initramfs_start = .; - .init.ramfs : { *(.init.ramfs) } - __initramfs_end = .; -#endif + .init.ramfs : { INIT_RAM_FS; } PERCPU(32) . = ALIGN(PAGE_SIZE); __init_end = .; /* freed after init ends here */ - __bss_start = .; /* BSS */ - .bss : { - *(.bss.page_aligned) - *(.bss) - } - . = ALIGN(4); - __bss_stop = .; + BSS(4) _end = . ; @@ -145,7 +117,7 @@ SECTIONS /* Sections to be discarded */ /DISCARD/ : { - *(.exitcall.exit) + EXIT_CALL } STABS_DEBUG diff --git a/arch/mn10300/mm/fault.c b/arch/mn10300/mm/fault.c index 33cf250..a62e1e1 100644 --- a/arch/mn10300/mm/fault.c +++ b/arch/mn10300/mm/fault.c @@ -258,7 +258,7 @@ good_area: * make sure we exit gracefully rather than endlessly redo * the fault. */ - fault = handle_mm_fault(mm, vma, address, write); + fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/parisc/mm/fault.c b/arch/parisc/mm/fault.c index 92c7fa4..bfb6dd6 100644 --- a/arch/parisc/mm/fault.c +++ b/arch/parisc/mm/fault.c @@ -202,7 +202,7 @@ good_area: * fault. */ - fault = handle_mm_fault(mm, vma, address, (acc_type & VM_WRITE) != 0); + fault = handle_mm_fault(mm, vma, address, (acc_type & VM_WRITE) ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { /* * We hit a shared mapping outside of the file, or some diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 9fb344d..d00131c 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -62,7 +62,6 @@ config HAVE_LATENCYTOP_SUPPORT config TRACE_IRQFLAGS_SUPPORT bool - depends on PPC64 default y config LOCKDEP_SUPPORT @@ -126,6 +125,7 @@ config PPC select HAVE_OPROFILE select HAVE_SYSCALL_WRAPPERS if PPC64 select GENERIC_ATOMIC64 if PPC32 + select HAVE_PERF_COUNTERS config EARLY_PRINTK bool diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug index d79a902..3b10051 100644 --- a/arch/powerpc/Kconfig.debug +++ b/arch/powerpc/Kconfig.debug @@ -2,6 +2,23 @@ menu "Kernel hacking" source "lib/Kconfig.debug" +config PPC_DISABLE_WERROR + bool "Don't build arch/powerpc code with -Werror" + default n + help + This option tells the compiler NOT to build the code under + arch/powerpc with the -Werror flag (which means warnings + are treated as errors). + + Only enable this if you are hitting a build failure in the + arch/powerpc code caused by a warning, and you don't feel + inclined to fix it. + +config PPC_WERROR + bool + depends on !PPC_DISABLE_WERROR + default y + config PRINT_STACK_DEPTH int "Stack depth to print" if DEBUG_KERNEL default 64 diff --git a/arch/powerpc/boot/.gitignore b/arch/powerpc/boot/.gitignore index 2f50acd..3d80c3e 100644 --- a/arch/powerpc/boot/.gitignore +++ b/arch/powerpc/boot/.gitignore @@ -36,3 +36,13 @@ zImage.pseries zconf.h zlib.h zutil.h +fdt.c +fdt.h +fdt_ro.c +fdt_rw.c +fdt_strerror.c +fdt_sw.c +fdt_wip.c +libfdt.h +libfdt_internal.h + diff --git a/arch/powerpc/boot/cuboot-85xx.c b/arch/powerpc/boot/cuboot-85xx.c index 6776a1a..277ba4a 100644 --- a/arch/powerpc/boot/cuboot-85xx.c +++ b/arch/powerpc/boot/cuboot-85xx.c @@ -15,6 +15,7 @@ #include "cuboot.h" #define TARGET_85xx +#define TARGET_HAS_ETH3 #include "ppcboot.h" static bd_t bd; @@ -27,6 +28,7 @@ static void platform_fixups(void) dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr); dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr); dt_fixup_mac_address_by_alias("ethernet2", bd.bi_enet2addr); + dt_fixup_mac_address_by_alias("ethernet3", bd.bi_enet3addr); dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 8, bd.bi_busfreq); /* Unfortunately, the specific model number is encoded in the diff --git a/arch/powerpc/boot/dts/amigaone.dts b/arch/powerpc/boot/dts/amigaone.dts index 26549fc..49ac36b 100644 --- a/arch/powerpc/boot/dts/amigaone.dts +++ b/arch/powerpc/boot/dts/amigaone.dts @@ -70,8 +70,8 @@ devsel-speed = <0x00000001>; min-grant = <0>; max-latency = <0>; - /* First 64k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */ - ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00010000>; + /* First 4k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */ + ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00001000>; interrupt-parent = <&i8259>; #interrupt-cells = <2>; #address-cells = <2>; diff --git a/arch/powerpc/boot/dts/asp834x-redboot.dts b/arch/powerpc/boot/dts/asp834x-redboot.dts index 7da84fd..261d10c 100644 --- a/arch/powerpc/boot/dts/asp834x-redboot.dts +++ b/arch/powerpc/boot/dts/asp834x-redboot.dts @@ -167,7 +167,7 @@ interrupt-parent = <&ipic>; interrupts = <39 0x8>; phy_type = "ulpi"; - port1; + port0; }; /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ usb@23000 { diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts index 217f8aa..35a6318 100644 --- a/arch/powerpc/boot/dts/gef_sbc610.dts +++ b/arch/powerpc/boot/dts/gef_sbc610.dts @@ -152,6 +152,16 @@ interrupt-parent = <&mpic>; dfsrr; + hwmon@48 { + compatible = "national,lm92"; + reg = <0x48>; + }; + + hwmon@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + rtc@51 { compatible = "epson,rx8581"; reg = <0x00000051>; diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts new file mode 100644 index 0000000..167044f --- /dev/null +++ b/arch/powerpc/boot/dts/kmeter1.dts @@ -0,0 +1,520 @@ +/* + * Keymile KMETER1 Device Tree Source + * + * 2008 DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "KMETER1"; + compatible = "keymile,KMETER1"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + ethernet1 = &enet_estar1; + ethernet2 = &enet_estar2; + ethernet3 = &enet_eth1; + ethernet4 = &enet_eth2; + ethernet5 = &enet_eth3; + ethernet6 = &enet_eth4; + serial0 = &serial0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8360@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <32768>; // L1, 32K + i-cache-size = <32768>; // L1, 32K + timebase-frequency = <0>; /* Filled in by U-Boot */ + bus-frequency = <0>; /* Filled in by U-Boot */ + clock-frequency = <0>; /* Filled in by U-Boot */ + }; + }; + + memory { + device_type = "memory"; + reg = <0 0>; /* Filled in by U-Boot */ + }; + + soc8360@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8360-immr", "simple-bus"; + ranges = <0x0 0xe0000000 0x00200000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <0>; /* Filled in by U-Boot */ + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <264000000>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + + ipic: pic@700 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "fsl,pq2pro-pic", "fsl,ipic"; + interrupt-controller; + reg = <0x700 0x100>; + }; + + par_io@1400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1400 0x100>; + compatible = "fsl,mpc8360-par_io"; + num-ports = <7>; + + pio_ucc1: ucc_pin@0 { + reg = <0>; + + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 0 3 1 0 1 0 /* TxD0 */ + 0 4 1 0 1 0 /* TxD1 */ + 0 5 1 0 1 0 /* TxD2 */ + 0 6 1 0 1 0 /* TxD3 */ + 0 9 2 0 1 0 /* RxD0 */ + 0 10 2 0 1 0 /* RxD1 */ + 0 11 2 0 1 0 /* RxD2 */ + 0 12 2 0 1 0 /* RxD3 */ + 0 7 1 0 1 0 /* TX_EN */ + 0 8 1 0 1 0 /* TX_ER */ + 0 15 2 0 1 0 /* RX_DV */ + 0 16 2 0 1 0 /* RX_ER */ + 0 0 2 0 1 0 /* RX_CLK */ + 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ + 2 8 2 0 1 0 /* GTX125 - CLK9 */ + >; + }; + + pio_ucc2: ucc_pin@1 { + reg = <1>; + + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 0 17 1 0 1 0 /* TxD0 */ + 0 18 1 0 1 0 /* TxD1 */ + 0 19 1 0 1 0 /* TxD2 */ + 0 20 1 0 1 0 /* TxD3 */ + 0 23 2 0 1 0 /* RxD0 */ + 0 24 2 0 1 0 /* RxD1 */ + 0 25 2 0 1 0 /* RxD2 */ + 0 26 2 0 1 0 /* RxD3 */ + 0 21 1 0 1 0 /* TX_EN */ + 0 22 1 0 1 0 /* TX_ER */ + 0 29 2 0 1 0 /* RX_DV */ + 0 30 2 0 1 0 /* RX_ER */ + 0 31 2 0 1 0 /* RX_CLK */ + 2 2 1 0 2 0 /* GTX_CLK - CLK3 */ + 2 3 2 0 1 0 /* GTX125 - CLK4 */ + >; + }; + + pio_ucc4: ucc_pin@3 { + reg = <3>; + + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ + 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ + 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ + 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ + 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ + 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ + 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ + + 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_ucc5: ucc_pin@4 { + reg = <4>; + + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ + 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ + 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ + 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ + 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ + 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ + 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ + >; + }; + + pio_ucc6: ucc_pin@5 { + reg = <5>; + + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */ + 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */ + 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */ + 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */ + 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */ + 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ + 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */ + >; + }; + + pio_ucc7: ucc_pin@6 { + reg = <6>; + + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */ + 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */ + 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */ + 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */ + 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */ + 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ + 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */ + >; + }; + + pio_ucc8: ucc_pin@7 { + reg = <7>; + + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */ + 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */ + 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */ + 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */ + 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */ + 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */ + 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */ + + 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ + >; + }; + + }; + + qe@100000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe"; + ranges = <0x0 0x100000 0x100000>; + reg = <0x100000 0x480>; + clock-frequency = <0>; /* Filled in by U-Boot */ + brg-frequency = <0>; /* Filled in by U-Boot */ + bus-frequency = <0>; /* Filled in by U-Boot */ + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x00010000 0x0000c000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0xc000>; + }; + }; + + /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ + enet_estar1: ucc@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk9"; + phy-handle = <&phy_estar1>; + phy-connection-type = "rgmii-id"; + pio-handle = <&pio_ucc1>; + }; + + /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ + enet_estar2: ucc@3000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <2>; + reg = <0x3000 0x200>; + interrupts = <33>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk4"; + phy-handle = <&phy_estar2>; + phy-connection-type = "rgmii-id"; + pio-handle = <&pio_ucc2>; + }; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + enet_piggy2: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + phy-handle = <&phy_piggy2>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc4>; + }; + + /* Eth-1 (UCC5, MDIO 0x08, RMII) */ + enet_eth1: ucc@2400 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <5>; + reg = <0x2400 0x200>; + interrupts = <40>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth1>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc5>; + }; + + /* Eth-2 (UCC6, MDIO 0x09, RMII) */ + enet_eth2: ucc@3400 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <6>; + reg = <0x3400 0x200>; + interrupts = <41>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth2>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc6>; + }; + + /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ + enet_eth3: ucc@2600 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <7>; + reg = <0x2600 0x200>; + interrupts = <42>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth3>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc7>; + }; + + /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ + enet_eth4: ucc@3600 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <8>; + reg = <0x3600 0x200>; + interrupts = <43>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth4>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc8>; + }; + + mdio@3320 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3320 0x18>; + compatible = "fsl,ucc-mdio"; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + phy_piggy2: ethernet-phy@00 { + reg = <0x0>; + }; + + /* Eth-1 (UCC5, MDIO 0x08, RMII) */ + phy_eth1: ethernet-phy@08 { + reg = <0x08>; + }; + + /* Eth-2 (UCC6, MDIO 0x09, RMII) */ + phy_eth2: ethernet-phy@09 { + reg = <0x09>; + }; + + /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ + phy_eth3: ethernet-phy@0a { + reg = <0x0a>; + }; + + /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ + phy_eth4: ethernet-phy@0b { + reg = <0x0b>; + }; + + /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ + phy_estar1: ethernet-phy@10 { + interrupt-parent = <&ipic>; + interrupts = <17 0x8>; + reg = <0x10>; + }; + + /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ + phy_estar2: ethernet-phy@11 { + interrupt-parent = <&ipic>; + interrupts = <18 0x8>; + reg = <0x11>; + }; + }; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + interrupts = <32 8 33 8>; + interrupt-parent = <&ipic>; + }; + }; + }; + + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xe0005000 0xd8>; + ranges = <0 0 0xf0000000 0x04000000>; /* Filled in by U-Boot */ + + flash@f0000000,0 { + compatible = "cfi-flash"; + /* + * The Intel P30 chip has 2 non-identical chips on + * one die, so we need to define 2 seperate regions + * that are scanned by physmap_of independantly. + */ + reg = <0 0x00000000 0x02000000 + 0 0x02000000 0x02000000>; /* Filled in by U-Boot */ + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "u-boot"; + reg = <0 0x40000>; + }; + partition@40000 { + label = "env"; + reg = <0x40000 0x40000>; + }; + partition@80000 { + label = "dtb"; + reg = <0x80000 0x20000>; + }; + partition@a0000 { + label = "kernel"; + reg = <0xa0000 0x300000>; + }; + partition@3a0000 { + label = "ramdisk"; + reg = <0x3a0000 0x800000>; + }; + partition@ba0000 { + label = "user"; + reg = <0xba0000 0x3460000>; + }; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts index 2a1929a..60f3327 100644 --- a/arch/powerpc/boot/dts/mpc8272ads.dts +++ b/arch/powerpc/boot/dts/mpc8272ads.dts @@ -17,6 +17,13 @@ #address-cells = <1>; #size-cells = <1>; + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + serial0 = &scc1; + serial1 = &scc4; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -46,13 +53,13 @@ #size-cells = <1>; reg = <0xf0010100 0x40>; - ranges = <0x0 0x0 0xfe000000 0x2000000 + ranges = <0x0 0x0 0xff800000 0x00800000 0x1 0x0 0xf4500000 0x8000 0x3 0x0 0xf8200000 0x8000>; flash@0,0 { compatible = "jedec-flash"; - reg = <0x0 0x0 0x2000000>; + reg = <0x0 0x0 0x00800000>; bank-width = <4>; device-width = <1>; }; @@ -144,7 +151,7 @@ reg = <0x119f0 0x10 0x115f0 0x10>; }; - serial@11a00 { + scc1: serial@11a00 { device_type = "serial"; compatible = "fsl,mpc8272-scc-uart", "fsl,cpm2-scc-uart"; @@ -155,7 +162,7 @@ fsl,cpm-command = <0x800000>; }; - serial@11a60 { + scc4: serial@11a60 { device_type = "serial"; compatible = "fsl,mpc8272-scc-uart", "fsl,cpm2-scc-uart"; @@ -192,7 +199,7 @@ }; }; - ethernet@11300 { + eth0: ethernet@11300 { device_type = "network"; compatible = "fsl,mpc8272-fcc-enet", "fsl,cpm2-fcc-enet"; @@ -205,7 +212,7 @@ fsl,cpm-command = <0x12000300>; }; - ethernet@11320 { + eth1: ethernet@11320 { device_type = "network"; compatible = "fsl,mpc8272-fcc-enet", "fsl,cpm2-fcc-enet"; diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts index 3f4c5fb..32e10f5 100644 --- a/arch/powerpc/boot/dts/mpc8315erdb.dts +++ b/arch/powerpc/boot/dts/mpc8315erdb.dts @@ -322,6 +322,21 @@ reg = <0x700 0x100>; device_type = "ipic"; }; + + ipic-msi@7c0 { + compatible = "fsl,ipic-msi"; + reg = <0x7c0 0x40>; + msi-available-ranges = <0 0x100>; + interrupts = <0x43 0x8 + 0x4 0x8 + 0x51 0x8 + 0x52 0x8 + 0x56 0x8 + 0x57 0x8 + 0x58 0x8 + 0x59 0x8>; + interrupt-parent = < &ipic >; + }; }; pci0: pci@e0008500 { diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts index e3eeaed..feeeb7f 100644 --- a/arch/powerpc/boot/dts/mpc8349emitx.dts +++ b/arch/powerpc/boot/dts/mpc8349emitx.dts @@ -156,7 +156,7 @@ interrupt-parent = <&ipic>; interrupts = <39 0x8>; phy_type = "ulpi"; - port1; + port0; }; usb@23000 { diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts index a2553a6..230febb 100644 --- a/arch/powerpc/boot/dts/mpc834x_mds.dts +++ b/arch/powerpc/boot/dts/mpc834x_mds.dts @@ -153,7 +153,7 @@ interrupt-parent = <&ipic>; interrupts = <39 0x8>; phy_type = "ulpi"; - port1; + port0; }; /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ usb@23000 { diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts index 67bb372..f32c281 100644 --- a/arch/powerpc/boot/dts/mpc8377_mds.dts +++ b/arch/powerpc/boot/dts/mpc8377_mds.dts @@ -155,7 +155,7 @@ }; sdhci@2e000 { - compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc"; + compatible = "fsl,mpc8377-esdhc", "fsl,esdhc"; reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts index 0533393..224b4f0 100644 --- a/arch/powerpc/boot/dts/mpc8377_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts @@ -169,7 +169,7 @@ }; sdhci@2e000 { - compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc"; + compatible = "fsl,mpc8377-esdhc", "fsl,esdhc"; reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts index a955a57..f720ab9 100644 --- a/arch/powerpc/boot/dts/mpc8378_mds.dts +++ b/arch/powerpc/boot/dts/mpc8378_mds.dts @@ -155,7 +155,7 @@ }; sdhci@2e000 { - compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc"; + compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts index 5d90e85..474ea2f 100644 --- a/arch/powerpc/boot/dts/mpc8378_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts @@ -169,7 +169,7 @@ }; sdhci@2e000 { - compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc"; + compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts index d266ddb..4fa221f 100644 --- a/arch/powerpc/boot/dts/mpc8379_mds.dts +++ b/arch/powerpc/boot/dts/mpc8379_mds.dts @@ -153,7 +153,7 @@ }; sdhci@2e000 { - compatible = "fsl,mpc8379-esdhc"; + compatible = "fsl,mpc8379-esdhc", "fsl,esdhc"; reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts index 98ae95b..d4838af 100644 --- a/arch/powerpc/boot/dts/mpc8379_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts @@ -167,7 +167,7 @@ }; sdhci@2e000 { - compatible = "fsl,mpc8379-esdhc"; + compatible = "fsl,mpc8379-esdhc", "fsl,esdhc"; reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts index 39c2927..a680165 100644 --- a/arch/powerpc/boot/dts/mpc8569mds.dts +++ b/arch/powerpc/boot/dts/mpc8569mds.dts @@ -24,6 +24,8 @@ ethernet1 = &enet1; ethernet2 = &enet2; ethernet3 = &enet3; + ethernet5 = &enet5; + ethernet7 = &enet7; pci1 = &pci1; rapidio0 = &rio0; }; @@ -70,8 +72,30 @@ #size-cells = <1>; compatible = "cfi-flash"; reg = <0x0 0x0 0x02000000>; - bank-width = <2>; + bank-width = <1>; device-width = <1>; + partition@0 { + label = "ramdisk"; + reg = <0x00000000 0x01c00000>; + }; + partition@1c00000 { + label = "kernel"; + reg = <0x01c00000 0x002e0000>; + }; + partiton@1ee0000 { + label = "dtb"; + reg = <0x01ee0000 0x00020000>; + }; + partition@1f00000 { + label = "firmware"; + reg = <0x01f00000 0x00080000>; + read-only; + }; + partition@1f80000 { + label = "u-boot"; + reg = <0x01f80000 0x00080000>; + read-only; + }; }; bcsr@1,0 { @@ -229,6 +253,7 @@ /* Filled in by U-Boot */ clock-frequency = <0>; status = "disabled"; + sdhci,1-bit-only; }; crypto@30000 { @@ -466,6 +491,37 @@ reg = <0x3>; device_type = "ethernet-phy"; }; + qe_phy5: ethernet-phy@04 { + interrupt-parent = <&mpic>; + reg = <0x04>; + device_type = "ethernet-phy"; + }; + qe_phy7: ethernet-phy@06 { + interrupt-parent = <&mpic>; + reg = <0x6>; + device_type = "ethernet-phy"; + }; + }; + mdio@3520 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3520 0x18>; + compatible = "fsl,ucc-mdio"; + + tbi0: tbi-phy@15 { + reg = <0x15>; + device_type = "tbi-phy"; + }; + }; + mdio@3720 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3720 0x38>; + compatible = "fsl,ucc-mdio"; + tbi1: tbi-phy@17 { + reg = <0x17>; + device_type = "tbi-phy"; + }; }; enet2: ucc@2200 { @@ -513,6 +569,36 @@ phy-connection-type = "rgmii-id"; }; + enet5: ucc@3400 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <6>; + reg = <0x3400 0x200>; + interrupts = <41>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "none"; + tbi-handle = <&tbi0>; + phy-handle = <&qe_phy5>; + phy-connection-type = "sgmii"; + }; + + enet7: ucc@3600 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <8>; + reg = <0x3600 0x200>; + interrupts = <43>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "none"; + tbi-handle = <&tbi1>; + phy-handle = <&qe_phy7>; + phy-connection-type = "sgmii"; + }; + muram@10000 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts index cfc2c60..f468d21 100644 --- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts +++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts @@ -100,8 +100,18 @@ }; board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,fpga-pixis"; reg = <3 0 0x20>; + ranges = <0 3 0 0x20>; + + sdcsr_pio: gpio-controller@a { + #gpio-cells = <2>; + compatible = "fsl,fpga-pixis-gpio-bank"; + reg = <0xa 1>; + gpio-controller; + }; }; }; @@ -176,6 +186,28 @@ interrupt-parent = <&mpic>; }; + spi@7000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc8610-spi", "fsl,spi"; + reg = <0x7000 0x40>; + cell-index = <0>; + interrupts = <59 2>; + interrupt-parent = <&mpic>; + mode = "cpu"; + gpios = <&sdcsr_pio 7 0>; + + mmc-slot@0 { + compatible = "fsl,mpc8610hpcd-mmc-slot", + "mmc-spi-slot"; + reg = <0>; + gpios = <&sdcsr_pio 0 1 /* nCD */ + &sdcsr_pio 1 0>; /* WP */ + voltage-ranges = <3300 3300>; + spi-max-frequency = <50000000>; + }; + }; + display@2c000 { compatible = "fsl,diu"; reg = <0x2c000 100>; diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts index 8958347..30bfdc0 100644 --- a/arch/powerpc/boot/dts/pcm030.dts +++ b/arch/powerpc/boot/dts/pcm030.dts @@ -258,34 +258,16 @@ compatible = "nxp,pcf8563"; reg = <0x51>; }; - /* FIXME: EEPROM */ + eeprom@52 { + compatible = "catalyst,24c32"; + reg = <0x52>; + }; }; sram@8000 { compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; reg = <0x8000 0x4000>; }; - - /* This is only an example device to show the usage of gpios. It maps all available - * gpios to the "gpio-provider" device. - */ - gpio { - compatible = "gpio-provider"; - - /* mpc52xx exp.con patchfield */ - gpios = <&gpio_wkup 0 0 /* GPIO_WKUP_7 11d jp13-3 */ - &gpio_wkup 1 0 /* GPIO_WKUP_6 14c */ - &gpio_wkup 6 0 /* PSC2_4 43c x5-11 */ - &gpio_simple 2 0 /* IRDA_1 24c x7-6 set GPS_PORT_CONFIG[IRDA] = 0 */ - &gpio_simple 3 0 /* IRDA_0 x8-5 set GPS_PORT_CONFIG[IRDA] = 0 */ - &gpt2 0 0 /* timer2 12d x4-4 */ - &gpt3 0 0 /* timer3 13d x6-4 */ - &gpt4 0 0 /* timer4 61c x2-16 */ - &gpt5 0 0 /* timer5 44c x7-11 */ - &gpt6 0 0 /* timer6 60c x8-15 */ - &gpt7 0 0 /* timer7 36a x17-9 */ - >; - }; }; pci@f0000d00 { diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts index 5fb6f66..2d9fa68 100644 --- a/arch/powerpc/boot/dts/sbc8349.dts +++ b/arch/powerpc/boot/dts/sbc8349.dts @@ -144,7 +144,7 @@ interrupt-parent = <&ipic>; interrupts = <39 0x8>; phy_type = "ulpi"; - port1; + port0; }; /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ usb@23000 { diff --git a/arch/powerpc/boot/dts/xcalibur1501.dts b/arch/powerpc/boot/dts/xcalibur1501.dts new file mode 100644 index 0000000..ac0a617 --- /dev/null +++ b/arch/powerpc/boot/dts/xcalibur1501.dts @@ -0,0 +1,696 @@ +/* + * Copyright (C) 2008 Extreme Engineering Solutions, Inc. + * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. + * + * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +/ { + model = "xes,xcalibur1501"; + compatible = "xes,xcalibur1501", "xes,MPC8572"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + serial0 = &serial0; + serial1 = &serial1; + pci2 = &pci2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8572@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + next-level-cache = <&L2>; + }; + + PowerPC,8572@1 { + device_type = "cpu"; + reg = <0x1>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot + }; + + localbus@ef005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; + reg = <0 0xef005000 0 0x1000>; + interrupts = <19 2>; + interrupt-parent = <&mpic>; + /* Local bus region mappings */ + ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */ + 1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */ + 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ + 3 0 0 0xef840000 0x40000 /* CS3: NAND CE2 */ + 4 0 0 0xe9000000 0x100000>; /* CS4: USB */ + + nor-boot@0,0 { + compatible = "amd,s29gl01gp", "cfi-flash"; + bank-width = <2>; + reg = <0 0 0x8000000>; /* 128MB */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "Primary user space"; + reg = <0x00000000 0x6f00000>; /* 111 MB */ + }; + partition@6f00000 { + label = "Primary kernel"; + reg = <0x6f00000 0x1000000>; /* 16 MB */ + }; + partition@7f00000 { + label = "Primary DTB"; + reg = <0x7f00000 0x40000>; /* 256 KB */ + }; + partition@7f40000 { + label = "Primary U-Boot environment"; + reg = <0x7f40000 0x40000>; /* 256 KB */ + }; + partition@7f80000 { + label = "Primary U-Boot"; + reg = <0x7f80000 0x80000>; /* 512 KB */ + read-only; + }; + }; + + nor-alternate@1,0 { + compatible = "amd,s29gl01gp", "cfi-flash"; + bank-width = <2>; + //reg = <0xf0000000 0x08000000>; /* 128MB */ + reg = <1 0 0x8000000>; /* 128MB */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "Secondary user space"; + reg = <0x00000000 0x6f00000>; /* 111 MB */ + }; + partition@6f00000 { + label = "Secondary kernel"; + reg = <0x6f00000 0x1000000>; /* 16 MB */ + }; + partition@7f00000 { + label = "Secondary DTB"; + reg = <0x7f00000 0x40000>; /* 256 KB */ + }; + partition@7f40000 { + label = "Secondary U-Boot environment"; + reg = <0x7f40000 0x40000>; /* 256 KB */ + }; + partition@7f80000 { + label = "Secondary U-Boot"; + reg = <0x7f80000 0x80000>; /* 512 KB */ + read-only; + }; + }; + + nand@2,0 { + #address-cells = <1>; + #size-cells = <1>; + /* + * Actual part could be ST Micro NAND08GW3B2A (1 GB), + * Micron MT29F8G08DAA (2x 512 MB), or Micron + * MT29F16G08FAA (2x 1 GB), depending on the build + * configuration + */ + compatible = "fsl,mpc8572-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <2 0 0x40000>; + /* U-Boot should fix this up if chip size > 1 GB */ + partition@0 { + label = "NAND Filesystem"; + reg = <0 0x40000000>; + }; + }; + + usb@4,0 { + compatible = "nxp,usb-isp1761"; + reg = <4 0 0x100000>; + bus-width = <32>; + interrupt-parent = <&mpic>; + interrupts = <10 1>; + }; + }; + + soc8572@ef000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8572-immr", "simple-bus"; + ranges = <0x0 0 0xef000000 0x100000>; + bus-frequency = <0>; // Filled out by uboot. + + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8572-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + + memory-controller@2000 { + compatible = "fsl,mpc8572-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + memory-controller@6000 { + compatible = "fsl,mpc8572-memory-controller"; + reg = <0x6000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8572-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x100000>; // L2, 1M + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + + temp-sensor@48 { + compatible = "dallas,ds1631", "dallas,ds1621"; + reg = <0x48>; + }; + + temp-sensor@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + + cpu-supervisor@51 { + compatible = "dallas,ds4510"; + reg = <0x51>; + }; + + eeprom@54 { + compatible = "atmel,at24c128b"; + reg = <0x54>; + }; + + rtc@68 { + compatible = "stm,m41t00", + "dallas,ds1338"; + reg = <0x68>; + }; + + pcie-switch@6a { + compatible = "plx,pex8648"; + reg = <0x6a>; + }; + + /* On-board signals for VID, flash, serial */ + gpio1: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + /* PMC0/XMC0 signals */ + gpio2: gpio@1c { + compatible = "nxp,pca9557"; + reg = <0x1c>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + /* PMC1/XMC1 signals */ + gpio3: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + /* CompactPCI signals (sysen, GA[4:0]) */ + gpio4: gpio@1e { + compatible = "nxp,pca9557"; + reg = <0x1e>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + /* CompactPCI J5 GPIO and FAL/DEG/PRST */ + gpio5: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + dma@c300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; + reg = <0xc300 0x4>; + ranges = <0x0 0xc100 0x200>; + cell-index = <1>; + dma-channel@0 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <76 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <77 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <78 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <79 2>; + }; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + /* eTSEC 1 front panel 0 */ + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi0>; + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + + phy0: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <4 1>; + reg = <0x1>; + }; + phy1: ethernet-phy@2 { + interrupt-parent = <&mpic>; + interrupts = <4 1>; + reg = <0x2>; + }; + phy2: ethernet-phy@3 { + interrupt-parent = <&mpic>; + interrupts = <5 1>; + reg = <0x3>; + }; + phy3: ethernet-phy@4 { + interrupt-parent = <&mpic>; + interrupts = <5 1>; + reg = <0x4>; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* eTSEC 2 front panel 1 */ + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi1>; + phy-handle = <&phy1>; + phy-connection-type = "sgmii"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* eTSEC 3 PICMG2.16 backplane port 0 */ + enet2: ethernet@26000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <2>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + ranges = <0x0 0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi2>; + phy-handle = <&phy2>; + phy-connection-type = "sgmii"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi2: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* eTSEC 4 PICMG2.16 backplane port 1 */ + enet3: ethernet@27000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <3>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + ranges = <0x0 0x27000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 38 2 39 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi3>; + phy-handle = <&phy3>; + phy-connection-type = "sgmii"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi3: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* UART0 */ + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + /* UART1 */ + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { //global utilities block + compatible = "fsl,mpc8572-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + msi@41600 { + compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + + crypto@30000 { + compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", + "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2 58 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x9fe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + + gpio0: gpio@f000 { + compatible = "fsl,mpc8572-gpio"; + reg = <0xf000 0x1000>; + interrupts = <47 2>; + interrupt-parent = <&mpic>; + #gpio-cells = <2>; + gpio-controller; + }; + + gpio-leds { + compatible = "gpio-leds"; + + heartbeat { + label = "Heartbeat"; + gpios = <&gpio0 4 1>; + linux,default-trigger = "heartbeat"; + }; + + yellow { + label = "Yellow"; + gpios = <&gpio0 5 1>; + }; + + red { + label = "Red"; + gpios = <&gpio0 6 1>; + }; + + green { + label = "Green"; + gpios = <&gpio0 7 1>; + }; + }; + + /* PME (pattern-matcher) */ + pme@10000 { + compatible = "fsl,mpc8572-pme", "pme8572"; + reg = <0x10000 0x5000>; + interrupts = <57 2 64 2 65 2 66 2 67 2>; + interrupt-parent = <&mpic>; + }; + + tlu@2f000 { + compatible = "fsl,mpc8572-tlu", "fsl_tlu"; + reg = <0x2f000 0x1000>; + interupts = <61 2 >; + interrupt-parent = <&mpic>; + }; + + tlu@15000 { + compatible = "fsl,mpc8572-tlu", "fsl_tlu"; + reg = <0x15000 0x1000>; + interupts = <75 2>; + interrupt-parent = <&mpic>; + }; + }; + + /* + * PCI Express controller 3 @ ef008000 is not used. + * This would have been pci0 on other mpc85xx platforms. + * + * PCI Express controller 2 @ ef009000 is not used. + * This would have been pci1 on other mpc85xx platforms. + */ + + /* PCI Express controller 1, wired to PEX8648 PCIe switch */ + pci2: pcie@ef00a000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xef00a000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 + 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <26 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 + >; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x40000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/xpedite5200.dts b/arch/powerpc/boot/dts/xpedite5200.dts new file mode 100644 index 0000000..a0cf53f --- /dev/null +++ b/arch/powerpc/boot/dts/xpedite5200.dts @@ -0,0 +1,466 @@ +/* + * Copyright (C) 2009 Extreme Engineering Solutions, Inc. + * Based on TQM8548 device tree + * + * XPedite5200 PrPMC/XMC module based on MPC8548E + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +/ { + model = "xes,xpedite5200"; + compatible = "xes,xpedite5200", "xes,MPC8548"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8548@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; // Filled in by U-Boot + }; + + soc@ef000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <0x0 0xef000000 0x100000>; + bus-frequency = <0>; + compatible = "fsl,mpc8548-immr", "simple-bus"; + + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8548-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + + memory-controller@2000 { + compatible = "fsl,mpc8548-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8548-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x80000>; // L2, 512K + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + /* On-card I2C */ + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + + /* + * Board GPIO: + * 0: BRD_CFG0 (1: P14 IO present) + * 1: BRD_CFG1 (1: FP ethernet present) + * 2: BRD_CFG2 (1: XMC IO present) + * 3: XMC root complex indicator + * 4: Flash boot device indicator + * 5: Flash write protect enable + * 6: PMC monarch indicator + * 7: PMC EREADY + */ + gpio1: gpio@18 { + compatible = "nxp,pca9556"; + reg = <0x18>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + /* P14 GPIO */ + gpio2: gpio@19 { + compatible = "nxp,pca9556"; + reg = <0x19>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + eeprom@50 { + compatible = "atmel,at24c16"; + reg = <0x50>; + }; + + rtc@68 { + compatible = "stm,m41t00", + "dallas,ds1338"; + reg = <0x68>; + }; + + dtt@48 { + compatible = "maxim,max1237"; + reg = <0x34>; + }; + }; + + /* Off-card I2C */ + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + /* eTSEC1: Front panel port 0 */ + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi0>; + phy-handle = <&phy0>; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + + phy0: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x1>; + }; + phy1: ethernet-phy@2 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x2>; + }; + phy2: ethernet-phy@3 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x3>; + }; + phy3: ethernet-phy@4 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x4>; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* eTSEC2: Front panel port 1 */ + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi1>; + phy-handle = <&phy1>; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* eTSEC3: Rear panel port 2 */ + enet2: ethernet@26000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <2>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + ranges = <0x0 0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi2>; + phy-handle = <&phy2>; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi2: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* eTSEC4: Rear panel port 3 */ + enet3: ethernet@27000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <3>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + ranges = <0x0 0x27000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 38 2 39 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi3>; + phy-handle = <&phy3>; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi3: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + current-speed = <115200>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + current-speed = <115200>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { // global utilities reg + compatible = "fsl,mpc8548-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + }; + + localbus@ef005000 { + compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xef005000 0x100>; // BRx, ORx, etc. + + ranges = < + 0 0x0 0xfc000000 0x04000000 // NOR boot flash + 1 0x0 0xf8000000 0x04000000 // NOR expansion flash + 2 0x0 0xef800000 0x00010000 // NAND CE1 + 3 0x0 0xef840000 0x00010000 // NAND CE2 + >; + + nor-boot@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0 0x0 0x4000000>; + bank-width = <2>; + + partition@0 { + label = "Primary OS"; + reg = <0x00000000 0x180000>; + }; + partition@180000 { + label = "Secondary OS"; + reg = <0x00180000 0x180000>; + }; + partition@300000 { + label = "User"; + reg = <0x00300000 0x3c80000>; + }; + partition@3f80000 { + label = "Boot firmware"; + reg = <0x03f80000 0x80000>; + }; + }; + + nor-alternate@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <1 0x0 0x4000000>; + bank-width = <2>; + + partition@0 { + label = "Filesystem"; + reg = <0x00000000 0x3f80000>; + }; + partition@3f80000 { + label = "Alternate boot firmware"; + reg = <0x03f80000 0x80000>; + }; + }; + + nand@2,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xes,address-ctl-nand"; + reg = <2 0x0 0x10000>; + cle-line = <0x8>; /* CLE tied to A3 */ + ale-line = <0x10>; /* ALE tied to A4 */ + + /* U-Boot should fix this up */ + partition@0 { + label = "NAND Filesystem"; + reg = <0 0x40000000>; + }; + }; + }; + + /* PMC interface */ + pci0: pci@ef008000 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; + device_type = "pci"; + reg = <0xef008000 0x1000>; + clock-frequency = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL */ + 0xe000 0 0 1 &mpic 2 1 + 0xe000 0 0 2 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <24 2>; + bus-range = <0 0>; + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000 + 0x01000000 0 0x00000000 0xe8000000 0 0x00800000>; + }; + + /* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */ +}; diff --git a/arch/powerpc/boot/dts/xpedite5200_xmon.dts b/arch/powerpc/boot/dts/xpedite5200_xmon.dts new file mode 100644 index 0000000..c5b2975 --- /dev/null +++ b/arch/powerpc/boot/dts/xpedite5200_xmon.dts @@ -0,0 +1,506 @@ +/* + * Copyright (C) 2009 Extreme Engineering Solutions, Inc. + * Based on TQM8548 device tree + * + * XPedite5200 PrPMC/XMC module based on MPC8548E. This dts is for the + * xMon boot loader memory map which differs from U-Boot's. + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +/ { + model = "xes,xpedite5200"; + compatible = "xes,xpedite5200", "xes,MPC8548"; + #address-cells = <1>; + #size-cells = <1>; + form-factor = "PMC/XMC"; + boot-bank = <0x0>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8548@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; // Filled in by boot loader + }; + + soc@ef000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <0x0 0xef000000 0x100000>; + bus-frequency = <0>; + compatible = "fsl,mpc8548-immr", "simple-bus"; + + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8548-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + + memory-controller@2000 { + compatible = "fsl,mpc8548-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8548-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x80000>; // L2, 512K + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + /* On-card I2C */ + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + + /* + * Board GPIO: + * 0: BRD_CFG0 (1: P14 IO present) + * 1: BRD_CFG1 (1: FP ethernet present) + * 2: BRD_CFG2 (1: XMC IO present) + * 3: XMC root complex indicator + * 4: Flash boot device indicator + * 5: Flash write protect enable + * 6: PMC monarch indicator + * 7: PMC EREADY + */ + gpio1: gpio@18 { + compatible = "nxp,pca9556"; + reg = <0x18>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + /* P14 GPIO */ + gpio2: gpio@19 { + compatible = "nxp,pca9556"; + reg = <0x19>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + eeprom@50 { + compatible = "atmel,at24c16"; + reg = <0x50>; + }; + + rtc@68 { + compatible = "stm,m41t00", + "dallas,ds1338"; + reg = <0x68>; + }; + + dtt@48 { + compatible = "maxim,max1237"; + reg = <0x34>; + }; + }; + + /* Off-card I2C */ + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + /* eTSEC1: Front panel port 0 */ + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi0>; + phy-handle = <&phy0>; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + + phy0: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x1>; + }; + phy1: ethernet-phy@2 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x2>; + }; + phy2: ethernet-phy@3 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x3>; + }; + phy3: ethernet-phy@4 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x4>; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* eTSEC2: Front panel port 1 */ + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi1>; + phy-handle = <&phy1>; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* eTSEC3: Rear panel port 2 */ + enet2: ethernet@26000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <2>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + ranges = <0x0 0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi2>; + phy-handle = <&phy2>; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi2: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* eTSEC4: Rear panel port 3 */ + enet3: ethernet@27000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <3>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + ranges = <0x0 0x27000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 38 2 39 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi3>; + phy-handle = <&phy3>; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi3: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + current-speed = <9600>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + current-speed = <9600>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { // global utilities reg + compatible = "fsl,mpc8548-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + }; + + localbus@ef005000 { + compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xef005000 0x100>; // BRx, ORx, etc. + + ranges = < + 0 0x0 0xf8000000 0x08000000 // NOR boot flash + 1 0x0 0xf0000000 0x08000000 // NOR expansion flash + 2 0x0 0xe8000000 0x00010000 // NAND CE1 + 3 0x0 0xe8010000 0x00010000 // NAND CE2 + >; + + nor-boot@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0 0x0 0x4000000>; + bank-width = <2>; + + partition@0 { + label = "Primary OS"; + reg = <0x00000000 0x180000>; + }; + partition@180000 { + label = "Secondary OS"; + reg = <0x00180000 0x180000>; + }; + partition@300000 { + label = "User"; + reg = <0x00300000 0x3c80000>; + }; + partition@3f80000 { + label = "Boot firmware"; + reg = <0x03f80000 0x80000>; + }; + }; + + nor-alternate@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <1 0x0 0x4000000>; + bank-width = <2>; + + partition@0 { + label = "Filesystem"; + reg = <0x00000000 0x3f80000>; + }; + partition@3f80000 { + label = "Alternate boot firmware"; + reg = <0x03f80000 0x80000>; + }; + }; + + nand@2,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xes,address-ctl-nand"; + reg = <2 0x0 0x10000>; + cle-line = <0x8>; /* CLE tied to A3 */ + ale-line = <0x10>; /* ALE tied to A4 */ + + partition@0 { + label = "NAND Filesystem"; + reg = <0 0x40000000>; + }; + }; + }; + + /* PMC interface */ + pci0: pci@ef008000 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; + device_type = "pci"; + reg = <0xef008000 0x1000>; + clock-frequency = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL */ + 0xe000 0 0 1 &mpic 2 1 + 0xe000 0 0 2 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <24 2>; + bus-range = <0 0>; + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 + 0x01000000 0 0x00000000 0xd0000000 0 0x01000000>; + }; + + /* XMC PCIe */ + pci1: pcie@ef00a000 { + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0x00000 0 0 1 &mpic 0 1 + 0x00000 0 0 2 &mpic 1 1 + 0x00000 0 0 3 &mpic 2 1 + 0x00000 0 0 4 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <26 2>; + bus-range = <0 0xff>; + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000 + 0x01000000 0 0x00000000 0xd1000000 0 0x01000000>; + clock-frequency = <33333333>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xef00a000 0x1000>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0 0xc0000000 0x02000000 0 + 0xc0000000 0 0x20000000 + 0x01000000 0 0x00000000 0x01000000 0 + 0x00000000 0 0x08000000>; + }; + }; + + /* Needed for dtbImage boot wrapper compatibility */ + chosen { + linux,stdout-path = &serial0; + }; +}; diff --git a/arch/powerpc/boot/dts/xpedite5301.dts b/arch/powerpc/boot/dts/xpedite5301.dts new file mode 100644 index 0000000..db7faf5 --- /dev/null +++ b/arch/powerpc/boot/dts/xpedite5301.dts @@ -0,0 +1,640 @@ +/* + * Copyright (C) 2008 Extreme Engineering Solutions, Inc. + * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. + * + * XPedite5301 PMC/XMC module based on MPC8572E + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +/ { + model = "xes,xpedite5301"; + compatible = "xes,xpedite5301", "xes,MPC8572"; + #address-cells = <2>; + #size-cells = <2>; + form-factor = "PMC/XMC"; + boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */ + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + pci1 = &pci1; + pci2 = &pci2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8572@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + next-level-cache = <&L2>; + }; + + PowerPC,8572@1 { + device_type = "cpu"; + reg = <0x1>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot + }; + + localbus@ef005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; + reg = <0 0xef005000 0 0x1000>; + interrupts = <19 2>; + interrupt-parent = <&mpic>; + /* Local bus region mappings */ + ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */ + 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */ + 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ + 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */ + + nor-boot@0,0 { + compatible = "amd,s29gl01gp", "cfi-flash"; + bank-width = <2>; + reg = <0 0 0x8000000>; /* 128MB */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "Primary user space"; + reg = <0x00000000 0x6f00000>; /* 111 MB */ + }; + partition@6f00000 { + label = "Primary kernel"; + reg = <0x6f00000 0x1000000>; /* 16 MB */ + }; + partition@7f00000 { + label = "Primary DTB"; + reg = <0x7f00000 0x40000>; /* 256 KB */ + }; + partition@7f40000 { + label = "Primary U-Boot environment"; + reg = <0x7f40000 0x40000>; /* 256 KB */ + }; + partition@7f80000 { + label = "Primary U-Boot"; + reg = <0x7f80000 0x80000>; /* 512 KB */ + read-only; + }; + }; + + nor-alternate@1,0 { + compatible = "amd,s29gl01gp", "cfi-flash"; + bank-width = <2>; + //reg = <0xf0000000 0x08000000>; /* 128MB */ + reg = <1 0 0x8000000>; /* 128MB */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "Secondary user space"; + reg = <0x00000000 0x6f00000>; /* 111 MB */ + }; + partition@6f00000 { + label = "Secondary kernel"; + reg = <0x6f00000 0x1000000>; /* 16 MB */ + }; + partition@7f00000 { + label = "Secondary DTB"; + reg = <0x7f00000 0x40000>; /* 256 KB */ + }; + partition@7f40000 { + label = "Secondary U-Boot environment"; + reg = <0x7f40000 0x40000>; /* 256 KB */ + }; + partition@7f80000 { + label = "Secondary U-Boot"; + reg = <0x7f80000 0x80000>; /* 512 KB */ + read-only; + }; + }; + + nand@2,0 { + #address-cells = <1>; + #size-cells = <1>; + /* + * Actual part could be ST Micro NAND08GW3B2A (1 GB), + * Micron MT29F8G08DAA (2x 512 MB), or Micron + * MT29F16G08FAA (2x 1 GB), depending on the build + * configuration + */ + compatible = "fsl,mpc8572-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <2 0 0x40000>; + /* U-Boot should fix this up if chip size > 1 GB */ + partition@0 { + label = "NAND Filesystem"; + reg = <0 0x40000000>; + }; + }; + + }; + + soc8572@ef000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8572-immr", "simple-bus"; + ranges = <0x0 0 0xef000000 0x100000>; + bus-frequency = <0>; // Filled out by uboot. + + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8572-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + + memory-controller@2000 { + compatible = "fsl,mpc8572-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + memory-controller@6000 { + compatible = "fsl,mpc8572-memory-controller"; + reg = <0x6000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8572-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x100000>; // L2, 1M + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + + temp-sensor@48 { + compatible = "dallas,ds1631", "dallas,ds1621"; + reg = <0x48>; + }; + + temp-sensor@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + + cpu-supervisor@51 { + compatible = "dallas,ds4510"; + reg = <0x51>; + }; + + eeprom@54 { + compatible = "atmel,at24c128b"; + reg = <0x54>; + }; + + rtc@68 { + compatible = "stm,m41t00", + "dallas,ds1338"; + reg = <0x68>; + }; + + pcie-switch@70 { + compatible = "plx,pex8518"; + reg = <0x70>; + }; + + gpio1: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + gpio2: gpio@1c { + compatible = "nxp,pca9557"; + reg = <0x1c>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + gpio3: gpio@1e { + compatible = "nxp,pca9557"; + reg = <0x1e>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + gpio4: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + dma@c300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; + reg = <0xc300 0x4>; + ranges = <0x0 0xc100 0x200>; + cell-index = <1>; + dma-channel@0 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <76 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <77 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <78 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <79 2>; + }; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + /* eTSEC 1 */ + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi0>; + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + + phy0: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x1>; + }; + phy1: ethernet-phy@2 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x2>; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* eTSEC 2 */ + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi1>; + phy-handle = <&phy1>; + phy-connection-type = "sgmii"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* UART0 */ + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + /* UART1 */ + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { //global utilities block + compatible = "fsl,mpc8572-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + msi@41600 { + compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + + crypto@30000 { + compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", + "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2 58 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x9fe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + + gpio0: gpio@f000 { + compatible = "fsl,mpc8572-gpio"; + reg = <0xf000 0x1000>; + interrupts = <47 2>; + interrupt-parent = <&mpic>; + #gpio-cells = <2>; + gpio-controller; + }; + + gpio-leds { + compatible = "gpio-leds"; + + heartbeat { + label = "Heartbeat"; + gpios = <&gpio0 4 1>; + linux,default-trigger = "heartbeat"; + }; + + yellow { + label = "Yellow"; + gpios = <&gpio0 5 1>; + }; + + red { + label = "Red"; + gpios = <&gpio0 6 1>; + }; + + green { + label = "Green"; + gpios = <&gpio0 7 1>; + }; + }; + + /* PME (pattern-matcher) */ + pme@10000 { + compatible = "fsl,mpc8572-pme", "pme8572"; + reg = <0x10000 0x5000>; + interrupts = <57 2 64 2 65 2 66 2 67 2>; + interrupt-parent = <&mpic>; + }; + + tlu@2f000 { + compatible = "fsl,mpc8572-tlu", "fsl_tlu"; + reg = <0x2f000 0x1000>; + interupts = <61 2 >; + interrupt-parent = <&mpic>; + }; + + tlu@15000 { + compatible = "fsl,mpc8572-tlu", "fsl_tlu"; + reg = <0x15000 0x1000>; + interupts = <75 2>; + interrupt-parent = <&mpic>; + }; + }; + + /* + * PCI Express controller 3 @ ef008000 is not used. + * This would have been pci0 on other mpc85xx platforms. + */ + + /* PCI Express controller 2, wired to XMC P15 connector */ + pci1: pcie@ef009000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xef009000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000 + 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <25 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0x0 0x0 0x0 0x1 &mpic 0x4 0x1 + 0x0 0x0 0x0 0x2 &mpic 0x5 0x1 + 0x0 0x0 0x0 0x3 &mpic 0x6 0x1 + 0x0 0x0 0x0 0x4 &mpic 0x7 0x1 + >; + pcie@0 { + reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0xc0000000 + 0x2000000 0x0 0xc0000000 + 0x0 0x10000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + /* PCI Express controller 1, wired to PEX8112 for PMC interface */ + pci2: pcie@ef00a000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xef00a000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 + 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <26 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 + >; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x40000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/xpedite5330.dts b/arch/powerpc/boot/dts/xpedite5330.dts new file mode 100644 index 0000000..c364ca6 --- /dev/null +++ b/arch/powerpc/boot/dts/xpedite5330.dts @@ -0,0 +1,707 @@ +/* + * Copyright (C) 2008 Extreme Engineering Solutions, Inc. + * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. + * + * XPedite5330 3U CompactPCI module based on MPC8572E + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +/ { + model = "xes,xpedite5330"; + compatible = "xes,xpedite5330", "xes,MPC8572"; + #address-cells = <2>; + #size-cells = <2>; + form-factor = "3U CompactPCI"; + boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */ + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; + }; + + pmcslots { + #address-cells = <1>; + #size-cells = <0>; + + pmcslot@0 { + cell-index = <0>; + /* + * boolean properties (true if defined): + * monarch; + * module-present; + */ + }; + }; + + xmcslots { + #address-cells = <1>; + #size-cells = <0>; + + xmcslot@0 { + cell-index = <0>; + /* + * boolean properties (true if defined): + * module-present; + */ + }; + }; + + cpci { + /* + * boolean properties (true if defined): + * system-controller; + */ + system-controller; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8572@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + next-level-cache = <&L2>; + }; + + PowerPC,8572@1 { + device_type = "cpu"; + reg = <0x1>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot + }; + + localbus@ef005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; + reg = <0 0xef005000 0 0x1000>; + interrupts = <19 2>; + interrupt-parent = <&mpic>; + /* Local bus region mappings */ + ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */ + 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */ + 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ + 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */ + + nor-boot@0,0 { + compatible = "amd,s29gl01gp", "cfi-flash"; + bank-width = <2>; + reg = <0 0 0x8000000>; /* 128MB */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "Primary user space"; + reg = <0x00000000 0x6f00000>; /* 111 MB */ + }; + partition@6f00000 { + label = "Primary kernel"; + reg = <0x6f00000 0x1000000>; /* 16 MB */ + }; + partition@7f00000 { + label = "Primary DTB"; + reg = <0x7f00000 0x40000>; /* 256 KB */ + }; + partition@7f40000 { + label = "Primary U-Boot environment"; + reg = <0x7f40000 0x40000>; /* 256 KB */ + }; + partition@7f80000 { + label = "Primary U-Boot"; + reg = <0x7f80000 0x80000>; /* 512 KB */ + read-only; + }; + }; + + nor-alternate@1,0 { + compatible = "amd,s29gl01gp", "cfi-flash"; + bank-width = <2>; + //reg = <0xf0000000 0x08000000>; /* 128MB */ + reg = <1 0 0x8000000>; /* 128MB */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "Secondary user space"; + reg = <0x00000000 0x6f00000>; /* 111 MB */ + }; + partition@6f00000 { + label = "Secondary kernel"; + reg = <0x6f00000 0x1000000>; /* 16 MB */ + }; + partition@7f00000 { + label = "Secondary DTB"; + reg = <0x7f00000 0x40000>; /* 256 KB */ + }; + partition@7f40000 { + label = "Secondary U-Boot environment"; + reg = <0x7f40000 0x40000>; /* 256 KB */ + }; + partition@7f80000 { + label = "Secondary U-Boot"; + reg = <0x7f80000 0x80000>; /* 512 KB */ + read-only; + }; + }; + + nand@2,0 { + #address-cells = <1>; + #size-cells = <1>; + /* + * Actual part could be ST Micro NAND08GW3B2A (1 GB), + * Micron MT29F8G08DAA (2x 512 MB), or Micron + * MT29F16G08FAA (2x 1 GB), depending on the build + * configuration + */ + compatible = "fsl,mpc8572-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <2 0 0x40000>; + /* U-Boot should fix this up if chip size > 1 GB */ + partition@0 { + label = "NAND Filesystem"; + reg = <0 0x40000000>; + }; + }; + + }; + + soc8572@ef000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8572-immr", "simple-bus"; + ranges = <0x0 0 0xef000000 0x100000>; + bus-frequency = <0>; // Filled out by uboot. + + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8572-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + + memory-controller@2000 { + compatible = "fsl,mpc8572-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + memory-controller@6000 { + compatible = "fsl,mpc8572-memory-controller"; + reg = <0x6000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8572-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x100000>; // L2, 1M + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + + temp-sensor@48 { + compatible = "dallas,ds1631", "dallas,ds1621"; + reg = <0x48>; + }; + + temp-sensor@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + + cpu-supervisor@51 { + compatible = "dallas,ds4510"; + reg = <0x51>; + }; + + eeprom@54 { + compatible = "atmel,at24c128b"; + reg = <0x54>; + }; + + rtc@68 { + compatible = "stm,m41t00", + "dallas,ds1338"; + reg = <0x68>; + }; + + pcie-switch@70 { + compatible = "plx,pex8518"; + reg = <0x70>; + }; + + gpio1: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + gpio2: gpio@1c { + compatible = "nxp,pca9557"; + reg = <0x1c>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + gpio3: gpio@1e { + compatible = "nxp,pca9557"; + reg = <0x1e>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + gpio4: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + dma@c300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; + reg = <0xc300 0x4>; + ranges = <0x0 0xc100 0x200>; + cell-index = <1>; + dma-channel@0 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <76 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <77 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <78 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <79 2>; + }; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + /* eTSEC 1 */ + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi0>; + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + + phy0: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x1>; + }; + phy1: ethernet-phy@2 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x2>; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* eTSEC 2 */ + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi1>; + phy-handle = <&phy1>; + phy-connection-type = "sgmii"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* UART0 */ + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + /* UART1 */ + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { //global utilities block + compatible = "fsl,mpc8572-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + msi@41600 { + compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + + crypto@30000 { + compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", + "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2 58 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x9fe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + + gpio0: gpio@f000 { + compatible = "fsl,mpc8572-gpio"; + reg = <0xf000 0x1000>; + interrupts = <47 2>; + interrupt-parent = <&mpic>; + #gpio-cells = <2>; + gpio-controller; + }; + + gpio-leds { + compatible = "gpio-leds"; + + heartbeat { + label = "Heartbeat"; + gpios = <&gpio0 4 1>; + linux,default-trigger = "heartbeat"; + }; + + yellow { + label = "Yellow"; + gpios = <&gpio0 5 1>; + }; + + red { + label = "Red"; + gpios = <&gpio0 6 1>; + }; + + green { + label = "Green"; + gpios = <&gpio0 7 1>; + }; + }; + + /* PME (pattern-matcher) */ + pme@10000 { + compatible = "fsl,mpc8572-pme", "pme8572"; + reg = <0x10000 0x5000>; + interrupts = <57 2 64 2 65 2 66 2 67 2>; + interrupt-parent = <&mpic>; + }; + + tlu@2f000 { + compatible = "fsl,mpc8572-tlu", "fsl_tlu"; + reg = <0x2f000 0x1000>; + interupts = <61 2 >; + interrupt-parent = <&mpic>; + }; + + tlu@15000 { + compatible = "fsl,mpc8572-tlu", "fsl_tlu"; + reg = <0x15000 0x1000>; + interupts = <75 2>; + interrupt-parent = <&mpic>; + }; + }; + + /* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */ + pci0: pcie@ef008000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xef008000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000 + 0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <24 2>; + interrupt-map-mask = <0xff00 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 + >; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0x0 0xe0000000 + 0x02000000 0x0 0xe0000000 + 0x0 0x10000000 + + 0x01000000 0x0 0x0 + 0x01000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + /* PCI Express controller 2, PMC module via PEX8112 bridge */ + pci1: pcie@ef009000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xef009000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000 + 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <25 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0x0 0x0 0x0 0x1 &mpic 0x4 0x1 + 0x0 0x0 0x0 0x2 &mpic 0x5 0x1 + 0x0 0x0 0x0 0x3 &mpic 0x6 0x1 + 0x0 0x0 0x0 0x4 &mpic 0x7 0x1 + >; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0xc0000000 + 0x2000000 0x0 0xc0000000 + 0x0 0x10000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + /* PCI Express controller 1, XMC P15 */ + pci2: pcie@ef00a000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xef00a000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 + 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <26 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 + >; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x40000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/xpedite5370.dts b/arch/powerpc/boot/dts/xpedite5370.dts new file mode 100644 index 0000000..7a8a4afd --- /dev/null +++ b/arch/powerpc/boot/dts/xpedite5370.dts @@ -0,0 +1,638 @@ +/* + * Copyright (C) 2008 Extreme Engineering Solutions, Inc. + * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. + * + * XPedite5370 3U VPX single-board computer based on MPC8572E + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +/ { + model = "xes,xpedite5370"; + compatible = "xes,xpedite5370", "xes,MPC8572"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + pci1 = &pci1; + pci2 = &pci2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8572@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + next-level-cache = <&L2>; + }; + + PowerPC,8572@1 { + device_type = "cpu"; + reg = <0x1>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot + }; + + localbus@ef005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; + reg = <0 0xef005000 0 0x1000>; + interrupts = <19 2>; + interrupt-parent = <&mpic>; + /* Local bus region mappings */ + ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */ + 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */ + 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ + 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */ + + nor-boot@0,0 { + compatible = "amd,s29gl01gp", "cfi-flash"; + bank-width = <2>; + reg = <0 0 0x8000000>; /* 128MB */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "Primary user space"; + reg = <0x00000000 0x6f00000>; /* 111 MB */ + }; + partition@6f00000 { + label = "Primary kernel"; + reg = <0x6f00000 0x1000000>; /* 16 MB */ + }; + partition@7f00000 { + label = "Primary DTB"; + reg = <0x7f00000 0x40000>; /* 256 KB */ + }; + partition@7f40000 { + label = "Primary U-Boot environment"; + reg = <0x7f40000 0x40000>; /* 256 KB */ + }; + partition@7f80000 { + label = "Primary U-Boot"; + reg = <0x7f80000 0x80000>; /* 512 KB */ + read-only; + }; + }; + + nor-alternate@1,0 { + compatible = "amd,s29gl01gp", "cfi-flash"; + bank-width = <2>; + //reg = <0xf0000000 0x08000000>; /* 128MB */ + reg = <1 0 0x8000000>; /* 128MB */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "Secondary user space"; + reg = <0x00000000 0x6f00000>; /* 111 MB */ + }; + partition@6f00000 { + label = "Secondary kernel"; + reg = <0x6f00000 0x1000000>; /* 16 MB */ + }; + partition@7f00000 { + label = "Secondary DTB"; + reg = <0x7f00000 0x40000>; /* 256 KB */ + }; + partition@7f40000 { + label = "Secondary U-Boot environment"; + reg = <0x7f40000 0x40000>; /* 256 KB */ + }; + partition@7f80000 { + label = "Secondary U-Boot"; + reg = <0x7f80000 0x80000>; /* 512 KB */ + read-only; + }; + }; + + nand@2,0 { + #address-cells = <1>; + #size-cells = <1>; + /* + * Actual part could be ST Micro NAND08GW3B2A (1 GB), + * Micron MT29F8G08DAA (2x 512 MB), or Micron + * MT29F16G08FAA (2x 1 GB), depending on the build + * configuration + */ + compatible = "fsl,mpc8572-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <2 0 0x40000>; + /* U-Boot should fix this up if chip size > 1 GB */ + partition@0 { + label = "NAND Filesystem"; + reg = <0 0x40000000>; + }; + }; + + }; + + soc8572@ef000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8572-immr", "simple-bus"; + ranges = <0x0 0 0xef000000 0x100000>; + bus-frequency = <0>; // Filled out by uboot. + + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8572-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + + memory-controller@2000 { + compatible = "fsl,mpc8572-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + memory-controller@6000 { + compatible = "fsl,mpc8572-memory-controller"; + reg = <0x6000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8572-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x100000>; // L2, 1M + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + + temp-sensor@48 { + compatible = "dallas,ds1631", "dallas,ds1621"; + reg = <0x48>; + }; + + temp-sensor@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + + cpu-supervisor@51 { + compatible = "dallas,ds4510"; + reg = <0x51>; + }; + + eeprom@54 { + compatible = "atmel,at24c128b"; + reg = <0x54>; + }; + + rtc@68 { + compatible = "stm,m41t00", + "dallas,ds1338"; + reg = <0x68>; + }; + + pcie-switch@70 { + compatible = "plx,pex8518"; + reg = <0x70>; + }; + + gpio1: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + gpio2: gpio@1c { + compatible = "nxp,pca9557"; + reg = <0x1c>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + gpio3: gpio@1e { + compatible = "nxp,pca9557"; + reg = <0x1e>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + gpio4: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + dma@c300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; + reg = <0xc300 0x4>; + ranges = <0x0 0xc100 0x200>; + cell-index = <1>; + dma-channel@0 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <76 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <77 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <78 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <79 2>; + }; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + /* eTSEC 1 */ + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi0>; + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + + phy0: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x1>; + }; + phy1: ethernet-phy@2 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x2>; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* eTSEC 2 */ + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi1>; + phy-handle = <&phy1>; + phy-connection-type = "sgmii"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + /* UART0 */ + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + /* UART1 */ + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { //global utilities block + compatible = "fsl,mpc8572-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + msi@41600 { + compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + + crypto@30000 { + compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", + "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2 58 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x9fe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + + gpio0: gpio@f000 { + compatible = "fsl,mpc8572-gpio"; + reg = <0xf000 0x1000>; + interrupts = <47 2>; + interrupt-parent = <&mpic>; + #gpio-cells = <2>; + gpio-controller; + }; + + gpio-leds { + compatible = "gpio-leds"; + + heartbeat { + label = "Heartbeat"; + gpios = <&gpio0 4 1>; + linux,default-trigger = "heartbeat"; + }; + + yellow { + label = "Yellow"; + gpios = <&gpio0 5 1>; + }; + + red { + label = "Red"; + gpios = <&gpio0 6 1>; + }; + + green { + label = "Green"; + gpios = <&gpio0 7 1>; + }; + }; + + /* PME (pattern-matcher) */ + pme@10000 { + compatible = "fsl,mpc8572-pme", "pme8572"; + reg = <0x10000 0x5000>; + interrupts = <57 2 64 2 65 2 66 2 67 2>; + interrupt-parent = <&mpic>; + }; + + tlu@2f000 { + compatible = "fsl,mpc8572-tlu", "fsl_tlu"; + reg = <0x2f000 0x1000>; + interupts = <61 2 >; + interrupt-parent = <&mpic>; + }; + + tlu@15000 { + compatible = "fsl,mpc8572-tlu", "fsl_tlu"; + reg = <0x15000 0x1000>; + interupts = <75 2>; + interrupt-parent = <&mpic>; + }; + }; + + /* + * PCI Express controller 3 @ ef008000 is not used. + * This would have been pci0 on other mpc85xx platforms. + */ + + /* PCI Express controller 2, wired to VPX P1,P2 backplane */ + pci1: pcie@ef009000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xef009000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000 + 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <25 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0x0 0x0 0x0 0x1 &mpic 0x4 0x1 + 0x0 0x0 0x0 0x2 &mpic 0x5 0x1 + 0x0 0x0 0x0 0x3 &mpic 0x6 0x1 + 0x0 0x0 0x0 0x4 &mpic 0x7 0x1 + >; + pcie@0 { + reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0xc0000000 + 0x2000000 0x0 0xc0000000 + 0x0 0x10000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + /* PCI Express controller 1, wired to PEX8518 PCIe switch */ + pci2: pcie@ef00a000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xef00a000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 + 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <26 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 + >; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x40000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; +}; diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index 3ac75ae..4db487d 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -225,6 +225,10 @@ asp834x-redboot) platformo="$object/fixed-head.o $object/redboot-83xx.o" binary=y ;; +xpedite52*) + link_address='0x1400000' + platformo=$object/cuboot-85xx.o + ;; esac vmz="$tmpdir/`basename \"$kernel\"`.$ext" diff --git a/arch/powerpc/configs/83xx/kmeter1_defconfig b/arch/powerpc/configs/83xx/kmeter1_defconfig new file mode 100644 index 0000000..bf0853f --- /dev/null +++ b/arch/powerpc/configs/83xx/kmeter1_defconfig @@ -0,0 +1,908 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28 +# Fri Apr 3 10:34:33 2009 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +CONFIG_6xx=y +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +# CONFIG_FSL_EMB_PERFMON is not set +# CONFIG_ALTIVEC is not set +CONFIG_PPC_STD_MMU=y +CONFIG_PPC_STD_MMU_32=y +# CONFIG_PPC_MM_SLICES is not set +# CONFIG_SMP is not set +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +# CONFIG_GENERIC_TBSYNC is not set +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFAULT_UIMAGE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PPC_DCR_NATIVE is not set +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set + +# +# Platform support +# +CONFIG_PPC_MULTIPLATFORM=y +CONFIG_CLASSIC32=y +# CONFIG_PPC_CHRP is not set +# CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set +# CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PPC_82xx is not set +# CONFIG_PQ2ADS is not set +CONFIG_PPC_83xx=y +# CONFIG_MPC831x_RDB is not set +# CONFIG_MPC832x_MDS is not set +# CONFIG_MPC832x_RDB is not set +# CONFIG_MPC834x_MDS is not set +# CONFIG_MPC834x_ITX is not set +# CONFIG_MPC836x_MDS is not set +# CONFIG_MPC836x_RDK is not set +# CONFIG_MPC837x_MDS is not set +# CONFIG_MPC837x_RDB is not set +# CONFIG_SBC834x is not set +# CONFIG_ASP834x is not set +CONFIG_KMETER1=y +# CONFIG_PPC_86xx is not set +# CONFIG_EMBEDDED6xx is not set +CONFIG_IPIC=y +# CONFIG_MPIC is not set +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_TAU is not set +CONFIG_QUICC_ENGINE=y +# CONFIG_QE_GPIO is not set +# CONFIG_FSL_ULI1575 is not set + +# +# Kernel options +# +# CONFIG_HIGHMEM is not set +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_SCHED_HRTICK=y +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_IOMMU_HELPER is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +# CONFIG_KEXEC is not set +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_PROC_DEVICETREE=y +# CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="" +# CONFIG_PM is not set +# CONFIG_SECCOMP is not set +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_FSL_SOC=y +CONFIG_PPC_PCI_CHOICE=y +# CONFIG_PCI is not set +# CONFIG_PCI_DOMAINS is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_HAS_RAPIDIO is not set + +# +# Advanced setup +# +# CONFIG_ADVANCED_OPTIONS is not set + +# +# Default settings for advanced configuration options are used +# +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_KERNEL_START=0xc0000000 +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +CONFIG_MTD_PHRAM=y +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +CONFIG_MTD_UBI_GLUEBI=y + +# +# UBI debugging options +# +CONFIG_MTD_UBI_DEBUG=y +# CONFIG_MTD_UBI_DEBUG_MSG is not set +# CONFIG_MTD_UBI_DEBUG_PARANOID is not set +# CONFIG_MTD_UBI_DEBUG_DISABLE_BGT is not set +# CONFIG_MTD_UBI_DEBUG_USERSPACE_IO is not set +# CONFIG_MTD_UBI_DEBUG_EMULATE_BITFLIPS is not set +# CONFIG_MTD_UBI_DEBUG_EMULATE_WRITE_FAILURES is not set +# CONFIG_MTD_UBI_DEBUG_EMULATE_ERASE_FAILURES is not set + +# +# Additional UBI debugging messages +# +# CONFIG_MTD_UBI_DEBUG_MSG_BLD is not set +# CONFIG_MTD_UBI_DEBUG_MSG_EBA is not set +# CONFIG_MTD_UBI_DEBUG_MSG_WL is not set +# CONFIG_MTD_UBI_DEBUG_MSG_IO is not set +CONFIG_OF_DEVICE=y +CONFIG_OF_I2C=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=y +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +CONFIG_NETDEV_1000=y +# CONFIG_GIANFAR is not set +CONFIG_UCC_GETH=y +# CONFIG_UGETH_MAGIC_PACKET is not set +# CONFIG_UGETH_FILTERING is not set +# CONFIG_UGETH_TX_ON_DEMAND is not set +# CONFIG_MV643XX_ETH is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set +CONFIG_WAN=y +CONFIG_HDLC=y +# CONFIG_HDLC_RAW is not set +# CONFIG_HDLC_RAW_ETH is not set +# CONFIG_HDLC_CISCO is not set +# CONFIG_HDLC_FR is not set +# CONFIG_HDLC_PPP is not set + +# +# X.25/LAPB support is disabled +# +CONFIG_HDLC_KM=y +CONFIG_FS_UCC_HDLC=y +# CONFIG_DLCI is not set +CONFIG_PPP=y +CONFIG_PPP_MULTILINK=y +# CONFIG_PPP_FILTER is not set +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_MPPE is not set +CONFIG_PPPOE=y +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_OF_PLATFORM is not set +# CONFIG_SERIAL_QE is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_BOOTCOUNT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_MPC=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_AT24 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_SOUND is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +CONFIG_UIO=y +# CONFIG_UIO_PDRV is not set +# CONFIG_UIO_PDRV_GENIRQ is not set +# CONFIG_UIO_SMX is not set +# CONFIG_UIO_SERCOS3 is not set +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +# CONFIG_MSDOS_PARTITION is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_NLS is not set +# CONFIG_DLM is not set +CONFIG_UCC_FAST=y +CONFIG_UCC=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_HAVE_LMB=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_IRQSTACKS is not set +# CONFIG_VIRQ_DEBUG is not set +# CONFIG_BOOTX_TEXT is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set +# CONFIG_PPC_CLOCK is not set +CONFIG_PPC_LIB_RHEAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig b/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig new file mode 100644 index 0000000..2552cbe --- /dev/null +++ b/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig @@ -0,0 +1,1821 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.30-rc6 +# Thu Jun 11 11:25:17 2009 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_6xx is not set +CONFIG_PPC_85xx=y +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_E500=y +# CONFIG_PPC_E500MC is not set +CONFIG_BOOKE=y +CONFIG_FSL_BOOKE=y +CONFIG_FSL_EMB_PERFMON=y +# CONFIG_PHYS_64BIT is not set +CONFIG_SPE=y +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_BOOK3E_MMU=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DTC=y +CONFIG_DEFAULT_UIMAGE=y +# CONFIG_PPC_DCR_NATIVE is not set +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_EXTRA_PASS=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set +CONFIG_PPC_MSI_BITMAP=y + +# +# Platform support +# +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +CONFIG_MPC85xx=y +# CONFIG_MPC8540_ADS is not set +# CONFIG_MPC8560_ADS is not set +# CONFIG_MPC85xx_CDS is not set +# CONFIG_MPC85xx_MDS is not set +# CONFIG_MPC8536_DS is not set +# CONFIG_MPC85xx_DS is not set +# CONFIG_SOCRATES is not set +# CONFIG_KSI8560 is not set +CONFIG_XES_MPC85xx=y +# CONFIG_STX_GP3 is not set +# CONFIG_TQM8540 is not set +# CONFIG_TQM8541 is not set +# CONFIG_TQM8548 is not set +# CONFIG_TQM8555 is not set +# CONFIG_TQM8560 is not set +# CONFIG_SBC8548 is not set +# CONFIG_SBC8560 is not set +# CONFIG_IPIC is not set +CONFIG_MPIC=y +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set +# CONFIG_CPM2 is not set +# CONFIG_FSL_ULI1575 is not set +CONFIG_MPC8xxx_GPIO=y +# CONFIG_SIMPLE_GPIO is not set + +# +# Kernel options +# +CONFIG_HIGHMEM=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +# CONFIG_SCHED_HRTICK is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_MATH_EMULATION=y +# CONFIG_IOMMU_HELPER is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +# CONFIG_IRQ_ALL_CPUS is not set +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_64K_PAGES is not set +# CONFIG_PPC_256K_PAGES is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_PROC_DEVICETREE=y +# CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="" +# CONFIG_PM is not set +CONFIG_SECCOMP=y +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_FSL_SOC=y +CONFIG_FSL_PCI=y +CONFIG_FSL_LBC=y +CONFIG_PPC_PCI_CHOICE=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEAER=y +# CONFIG_PCIEASPM is not set +CONFIG_ARCH_SUPPORTS_MSI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_HAS_RAPIDIO is not set + +# +# Advanced setup +# +CONFIG_ADVANCED_OPTIONS=y +CONFIG_LOWMEM_SIZE_BOOL=y +CONFIG_LOWMEM_SIZE=0x40000000 +# CONFIG_LOWMEM_CAM_NUM_BOOL is not set +CONFIG_LOWMEM_CAM_NUM=3 +# CONFIG_RELOCATABLE is not set +CONFIG_PAGE_OFFSET_BOOL=y +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_KERNEL_START_BOOL=y +CONFIG_KERNEL_START=0x80000000 +# CONFIG_PHYSICAL_START_BOOL is not set +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_PHYSICAL_ALIGN=0x04000000 +CONFIG_TASK_SIZE_BOOL=y +CONFIG_TASK_SIZE=0x80000000 +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +CONFIG_NET_IPGRE=y +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_ARPD=y +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_NAND_FSL_ELBC=y +CONFIG_MTD_NAND_FSL_UPM=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +CONFIG_OF_DEVICE=y +CONFIG_OF_GPIO=y +CONFIG_OF_I2C=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=y +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=131072 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=y +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y +CONFIG_SATA_AHCI=y +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_FSL is not set +CONFIG_ATA_SFF=y +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +CONFIG_PATA_ALI=y +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_SCH is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# Enable only one of the two stacks, unless you know what you are doing +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +CONFIG_BROADCOM_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_ATL2 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +CONFIG_FSL_PQ_MDIO=y +CONFIG_GIANFAR=y +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_XILINX_XPS_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_OF_PLATFORM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_HVC_UDBG is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NVRAM=y +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_MPC=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Graphics adapter I2C/DDC channel drivers +# +# CONFIG_I2C_VOODOO3 is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_XILINX is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_PCA953X=y +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ATXP1 is not set +CONFIG_SENSORS_DS1621=y +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +CONFIG_SENSORS_LM90=y +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_BOOKE_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +# CONFIG_VGACON_SOFT_SCROLLBACK is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_GREENASIA_FF is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_ISP1760_HCD=y +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +CONFIG_LEDS_GPIO_OF=y +# CONFIG_LEDS_LP5521 is not set +CONFIG_LEDS_PCA955X=y +# CONFIG_LEDS_BD2802 is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +CONFIG_LEDS_TRIGGER_GPIO=y +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC=y + +# +# Reporting subsystems +# +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_MM_EDAC=y +CONFIG_EDAC_MPC85XX=y +# CONFIG_EDAC_AMD8131 is not set +# CONFIG_EDAC_AMD8111 is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_DS1307=y +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_GENERIC is not set +CONFIG_DMADEVICES=y + +# +# DMA Devices +# +CONFIG_FSL_DMA=y +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_HAVE_LMB=y +CONFIG_NLATTR=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_XMON is not set +# CONFIG_IRQSTACKS is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_CRYPTO_DEV_TALITOS is not set +# CONFIG_PPC_CLOCK is not set +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/include/asm/cpm1.h b/arch/powerpc/include/asm/cpm1.h index 2ff79874..7685ffd 100644 --- a/arch/powerpc/include/asm/cpm1.h +++ b/arch/powerpc/include/asm/cpm1.h @@ -598,8 +598,6 @@ typedef struct risc_timer_pram { #define CICR_IEN ((uint)0x00000080) /* Int. enable */ #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ -#define IMAP_ADDR (get_immrbase()) - #define CPM_PIN_INPUT 0 #define CPM_PIN_OUTPUT 1 #define CPM_PIN_PRIMARY 0 diff --git a/arch/powerpc/include/asm/delay.h b/arch/powerpc/include/asm/delay.h index f9200a6..1e2eb41 100644 --- a/arch/powerpc/include/asm/delay.h +++ b/arch/powerpc/include/asm/delay.h @@ -2,8 +2,11 @@ #define _ASM_POWERPC_DELAY_H #ifdef __KERNEL__ +#include <asm/time.h> + /* * Copyright 1996, Paul Mackerras. + * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -30,5 +33,38 @@ extern void udelay(unsigned long usecs); #define mdelay(n) udelay((n) * 1000) #endif +/** + * spin_event_timeout - spin until a condition gets true or a timeout elapses + * @condition: a C expression to evalate + * @timeout: timeout, in microseconds + * @delay: the number of microseconds to delay between each evaluation of + * @condition + * + * The process spins until the condition evaluates to true (non-zero) or the + * timeout elapses. The return value of this macro is the value of + * @condition when the loop terminates. This allows you to determine the cause + * of the loop terminates. If the return value is zero, then you know a + * timeout has occurred. + * + * This primary purpose of this macro is to poll on a hardware register + * until a status bit changes. The timeout ensures that the loop still + * terminates even if the bit never changes. The delay is for devices that + * need a delay in between successive reads. + * + * gcc will optimize out the if-statement if @delay is a constant. + */ +#define spin_event_timeout(condition, timeout, delay) \ +({ \ + typeof(condition) __ret; \ + unsigned long __loops = tb_ticks_per_usec * timeout; \ + unsigned long __start = get_tbl(); \ + while (!(__ret = (condition)) && (tb_ticks_since(__start) <= __loops)) \ + if (delay) \ + udelay(delay); \ + else \ + cpu_relax(); \ + __ret; \ +}) + #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_DELAY_H */ diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h index 3d9e887..b44aaab 100644 --- a/arch/powerpc/include/asm/dma-mapping.h +++ b/arch/powerpc/include/asm/dma-mapping.h @@ -309,7 +309,9 @@ static inline void dma_sync_single_for_cpu(struct device *dev, struct dma_mapping_ops *dma_ops = get_dma_ops(dev); BUG_ON(!dma_ops); - dma_ops->sync_single_range_for_cpu(dev, dma_handle, 0, + + if (dma_ops->sync_single_range_for_cpu) + dma_ops->sync_single_range_for_cpu(dev, dma_handle, 0, size, direction); } @@ -320,7 +322,9 @@ static inline void dma_sync_single_for_device(struct device *dev, struct dma_mapping_ops *dma_ops = get_dma_ops(dev); BUG_ON(!dma_ops); - dma_ops->sync_single_range_for_device(dev, dma_handle, + + if (dma_ops->sync_single_range_for_device) + dma_ops->sync_single_range_for_device(dev, dma_handle, 0, size, direction); } @@ -331,7 +335,9 @@ static inline void dma_sync_sg_for_cpu(struct device *dev, struct dma_mapping_ops *dma_ops = get_dma_ops(dev); BUG_ON(!dma_ops); - dma_ops->sync_sg_for_cpu(dev, sgl, nents, direction); + + if (dma_ops->sync_sg_for_cpu) + dma_ops->sync_sg_for_cpu(dev, sgl, nents, direction); } static inline void dma_sync_sg_for_device(struct device *dev, @@ -341,7 +347,9 @@ static inline void dma_sync_sg_for_device(struct device *dev, struct dma_mapping_ops *dma_ops = get_dma_ops(dev); BUG_ON(!dma_ops); - dma_ops->sync_sg_for_device(dev, sgl, nents, direction); + + if (dma_ops->sync_sg_for_device) + dma_ops->sync_sg_for_device(dev, sgl, nents, direction); } static inline void dma_sync_single_range_for_cpu(struct device *dev, @@ -351,7 +359,9 @@ static inline void dma_sync_single_range_for_cpu(struct device *dev, struct dma_mapping_ops *dma_ops = get_dma_ops(dev); BUG_ON(!dma_ops); - dma_ops->sync_single_range_for_cpu(dev, dma_handle, + + if (dma_ops->sync_single_range_for_cpu) + dma_ops->sync_single_range_for_cpu(dev, dma_handle, offset, size, direction); } @@ -362,7 +372,9 @@ static inline void dma_sync_single_range_for_device(struct device *dev, struct dma_mapping_ops *dma_ops = get_dma_ops(dev); BUG_ON(!dma_ops); - dma_ops->sync_single_range_for_device(dev, dma_handle, offset, + + if (dma_ops->sync_single_range_for_device) + dma_ops->sync_single_range_for_device(dev, dma_handle, offset, size, direction); } #else /* CONFIG_PPC_NEED_DMA_SYNC_OPS */ diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 63a4f77..1b5a210 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -95,8 +95,8 @@ struct fsl_lbc_bank { }; struct fsl_lbc_regs { - struct fsl_lbc_bank bank[8]; - u8 res0[0x28]; + struct fsl_lbc_bank bank[12]; + u8 res0[0x8]; __be32 mar; /**< UPM Address Register */ u8 res1[0x4]; __be32 mamr; /**< UPMA Mode Register */ diff --git a/arch/powerpc/include/asm/highmem.h b/arch/powerpc/include/asm/highmem.h index 684a73f..a74c4ee 100644 --- a/arch/powerpc/include/asm/highmem.h +++ b/arch/powerpc/include/asm/highmem.h @@ -22,9 +22,7 @@ #ifdef __KERNEL__ -#include <linux/init.h> #include <linux/interrupt.h> -#include <linux/highmem.h> #include <asm/kmap_types.h> #include <asm/tlbflush.h> #include <asm/page.h> @@ -62,6 +60,9 @@ extern pte_t *pkmap_page_table; extern void *kmap_high(struct page *page); extern void kunmap_high(struct page *page); +extern void *kmap_atomic_prot(struct page *page, enum km_type type, + pgprot_t prot); +extern void kunmap_atomic(void *kvaddr, enum km_type type); static inline void *kmap(struct page *page) { @@ -79,62 +80,11 @@ static inline void kunmap(struct page *page) kunmap_high(page); } -/* - * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap - * gives a more generic (and caching) interface. But kmap_atomic can - * be used in IRQ contexts, so in some (very limited) cases we need - * it. - */ -static inline void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot) -{ - unsigned int idx; - unsigned long vaddr; - - /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ - pagefault_disable(); - if (!PageHighMem(page)) - return page_address(page); - - debug_kmap_atomic(type); - idx = type + KM_TYPE_NR*smp_processor_id(); - vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); -#ifdef CONFIG_DEBUG_HIGHMEM - BUG_ON(!pte_none(*(kmap_pte-idx))); -#endif - __set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot), 1); - local_flush_tlb_page(NULL, vaddr); - - return (void*) vaddr; -} - static inline void *kmap_atomic(struct page *page, enum km_type type) { return kmap_atomic_prot(page, type, kmap_prot); } -static inline void kunmap_atomic(void *kvaddr, enum km_type type) -{ -#ifdef CONFIG_DEBUG_HIGHMEM - unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; - enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id(); - - if (vaddr < __fix_to_virt(FIX_KMAP_END)) { - pagefault_enable(); - return; - } - - BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)); - - /* - * force other mappings to Oops if they'll try to access - * this pte without first remap it - */ - pte_clear(&init_mm, vaddr, kmap_pte-idx); - local_flush_tlb_page(NULL, vaddr); -#endif - pagefault_enable(); -} - static inline struct page *kmap_atomic_to_page(void *ptr) { unsigned long idx, vaddr = (unsigned long) ptr; @@ -148,6 +98,7 @@ static inline struct page *kmap_atomic_to_page(void *ptr) return pte_page(*pte); } + #define flush_cache_kmaps() flush_cache_all() #endif /* __KERNEL__ */ diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h index b7f8f4a..8b505ea 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h @@ -68,13 +68,13 @@ static inline int irqs_disabled_flags(unsigned long flags) #if defined(CONFIG_BOOKE) #define SET_MSR_EE(x) mtmsr(x) -#define local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory") +#define raw_local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory") #else #define SET_MSR_EE(x) mtmsr(x) -#define local_irq_restore(flags) mtmsr(flags) +#define raw_local_irq_restore(flags) mtmsr(flags) #endif -static inline void local_irq_disable(void) +static inline void raw_local_irq_disable(void) { #ifdef CONFIG_BOOKE __asm__ __volatile__("wrteei 0": : :"memory"); @@ -86,7 +86,7 @@ static inline void local_irq_disable(void) #endif } -static inline void local_irq_enable(void) +static inline void raw_local_irq_enable(void) { #ifdef CONFIG_BOOKE __asm__ __volatile__("wrteei 1": : :"memory"); @@ -98,7 +98,7 @@ static inline void local_irq_enable(void) #endif } -static inline void local_irq_save_ptr(unsigned long *flags) +static inline void raw_local_irq_save_ptr(unsigned long *flags) { unsigned long msr; msr = mfmsr(); @@ -110,12 +110,12 @@ static inline void local_irq_save_ptr(unsigned long *flags) #endif } -#define local_save_flags(flags) ((flags) = mfmsr()) -#define local_irq_save(flags) local_irq_save_ptr(&flags) -#define irqs_disabled() ((mfmsr() & MSR_EE) == 0) +#define raw_local_save_flags(flags) ((flags) = mfmsr()) +#define raw_local_irq_save(flags) raw_local_irq_save_ptr(&flags) +#define raw_irqs_disabled() ((mfmsr() & MSR_EE) == 0) +#define raw_irqs_disabled_flags(flags) (((flags) & MSR_EE) == 0) -#define hard_irq_enable() local_irq_enable() -#define hard_irq_disable() local_irq_disable() +#define hard_irq_disable() raw_local_irq_disable() static inline int irqs_disabled_flags(unsigned long flags) { @@ -131,6 +131,8 @@ static inline int irqs_disabled_flags(unsigned long flags) struct irq_chip; #ifdef CONFIG_PERF_COUNTERS + +#ifdef CONFIG_PPC64 static inline unsigned long test_perf_counter_pending(void) { unsigned long x; @@ -154,15 +156,15 @@ static inline void clear_perf_counter_pending(void) "r" (0), "i" (offsetof(struct paca_struct, perf_counter_pending))); } +#endif /* CONFIG_PPC64 */ -#else +#else /* CONFIG_PERF_COUNTERS */ static inline unsigned long test_perf_counter_pending(void) { return 0; } -static inline void set_perf_counter_pending(void) {} static inline void clear_perf_counter_pending(void) {} #endif /* CONFIG_PERF_COUNTERS */ diff --git a/arch/powerpc/include/asm/mpc52xx.h b/arch/powerpc/include/asm/mpc52xx.h index 52e049c..1b4f697 100644 --- a/arch/powerpc/include/asm/mpc52xx.h +++ b/arch/powerpc/include/asm/mpc52xx.h @@ -16,6 +16,7 @@ #ifndef __ASSEMBLY__ #include <asm/types.h> #include <asm/prom.h> +#include <asm/mpc5xxx.h> #endif /* __ASSEMBLY__ */ #include <linux/suspend.h> @@ -268,7 +269,6 @@ struct mpc52xx_intr { #ifndef __ASSEMBLY__ /* mpc52xx_common.c */ -extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node); extern void mpc5200_setup_xlb_arbiter(void); extern void mpc52xx_declare_of_platform_devices(void); extern void mpc52xx_map_common_devices(void); diff --git a/arch/powerpc/include/asm/mpc512x.h b/arch/powerpc/include/asm/mpc5xxx.h index c48a165..5ce9c5f 100644 --- a/arch/powerpc/include/asm/mpc512x.h +++ b/arch/powerpc/include/asm/mpc5xxx.h @@ -4,7 +4,7 @@ * Author: John Rigby, <jrigby@freescale.com>, Friday Apr 13 2007 * * Description: - * MPC5121 Prototypes and definitions + * MPC5xxx Prototypes and definitions * * This is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by @@ -13,10 +13,10 @@ * */ -#ifndef __ASM_POWERPC_MPC512x_H__ -#define __ASM_POWERPC_MPC512x_H__ +#ifndef __ASM_POWERPC_MPC5xxx_H__ +#define __ASM_POWERPC_MPC5xxx_H__ -extern unsigned long mpc512x_find_ips_freq(struct device_node *node); +extern unsigned long mpc5xxx_get_bus_frequency(struct device_node *node); -#endif /* __ASM_POWERPC_MPC512x_H__ */ +#endif /* __ASM_POWERPC_MPC5xxx_H__ */ diff --git a/arch/powerpc/include/asm/perf_counter.h b/arch/powerpc/include/asm/perf_counter.h index cc7c887..8ccd4e1 100644 --- a/arch/powerpc/include/asm/perf_counter.h +++ b/arch/powerpc/include/asm/perf_counter.h @@ -10,6 +10,8 @@ */ #include <linux/types.h> +#include <asm/hw_irq.h> + #define MAX_HWCOUNTERS 8 #define MAX_EVENT_ALTERNATIVES 8 #define MAX_LIMITED_HWCOUNTERS 2 @@ -19,27 +21,27 @@ * describe the PMU on a particular POWER-family CPU. */ struct power_pmu { - int n_counter; - int max_alternatives; - u64 add_fields; - u64 test_adder; - int (*compute_mmcr)(u64 events[], int n_ev, - unsigned int hwc[], u64 mmcr[]); - int (*get_constraint)(u64 event, u64 *mskp, u64 *valp); - int (*get_alternatives)(u64 event, unsigned int flags, - u64 alt[]); - void (*disable_pmc)(unsigned int pmc, u64 mmcr[]); - int (*limited_pmc_event)(u64 event); - u32 flags; - int n_generic; - int *generic_events; - int (*cache_events)[PERF_COUNT_HW_CACHE_MAX] + const char *name; + int n_counter; + int max_alternatives; + unsigned long add_fields; + unsigned long test_adder; + int (*compute_mmcr)(u64 events[], int n_ev, + unsigned int hwc[], unsigned long mmcr[]); + int (*get_constraint)(u64 event, unsigned long *mskp, + unsigned long *valp); + int (*get_alternatives)(u64 event, unsigned int flags, + u64 alt[]); + void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]); + int (*limited_pmc_event)(u64 event); + u32 flags; + int n_generic; + int *generic_events; + int (*cache_events)[PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX]; }; -extern struct power_pmu *ppmu; - /* * Values for power_pmu.flags */ @@ -53,15 +55,23 @@ extern struct power_pmu *ppmu; #define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */ #define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */ +extern int register_power_pmu(struct power_pmu *); + struct pt_regs; extern unsigned long perf_misc_flags(struct pt_regs *regs); -#define perf_misc_flags(regs) perf_misc_flags(regs) - extern unsigned long perf_instruction_pointer(struct pt_regs *regs); /* - * The power_pmu.get_constraint function returns a 64-bit value and - * a 64-bit mask that express the constraints between this event and + * Only override the default definitions in include/linux/perf_counter.h + * if we have hardware PMU support. + */ +#ifdef CONFIG_PPC_PERF_CTRS +#define perf_misc_flags(regs) perf_misc_flags(regs) +#endif + +/* + * The power_pmu.get_constraint function returns a 32/64-bit value and + * a 32/64-bit mask that express the constraints between this event and * other events. * * The value and mask are divided up into (non-overlapping) bitfields diff --git a/arch/powerpc/include/asm/pte-hash64-64k.h b/arch/powerpc/include/asm/pte-hash64-64k.h index e05d26f..82b7220 100644 --- a/arch/powerpc/include/asm/pte-hash64-64k.h +++ b/arch/powerpc/include/asm/pte-hash64-64k.h @@ -47,7 +47,8 @@ * generic accessors and iterators here */ #define __real_pte(e,p) ((real_pte_t) { \ - (e), pte_val(*((p) + PTRS_PER_PTE)) }) + (e), ((e) & _PAGE_COMBO) ? \ + (pte_val(*((p) + PTRS_PER_PTE))) : 0 }) #define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \ (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf)) #define __rpte_to_pte(r) ((r).pte) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index a3c28e4..1170267 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -755,7 +755,8 @@ #define mfspr(rn) ({unsigned long rval; \ asm volatile("mfspr %0," __stringify(rn) \ : "=r" (rval)); rval;}) -#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)) +#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)\ + : "memory") #ifdef __powerpc64__ #ifdef CONFIG_PPC_CELL diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 601ddbc..6bcf364 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -389,12 +389,14 @@ #define ICCR_CACHE 1 /* Cacheable */ /* Bit definitions for L1CSR0. */ +#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ #define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ #define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ /* Bit definitions for L1CSR1. */ +#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h index 01c1233..168fce7 100644 --- a/arch/powerpc/include/asm/rtas.h +++ b/arch/powerpc/include/asm/rtas.h @@ -58,7 +58,7 @@ struct rtas_t { unsigned long entry; /* physical address pointer */ unsigned long base; /* physical address pointer */ unsigned long size; - spinlock_t lock; + raw_spinlock_t lock; struct rtas_args args; struct device_node *dev; /* virtual address pointer */ }; @@ -245,5 +245,8 @@ static inline u32 rtas_config_addr(int busno, int devfn, int reg) (devfn << 8) | (reg & 0xff); } +extern void __cpuinit rtas_give_timebase(void); +extern void __cpuinit rtas_take_timebase(void); + #endif /* __KERNEL__ */ #endif /* _POWERPC_RTAS_H */ diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index 612b0c4..b73396b 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -4,6 +4,8 @@ CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"' +subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror + ifeq ($(CONFIG_PPC64),y) CFLAGS_prom_init.o += -mno-minimal-toc endif @@ -95,9 +97,10 @@ obj64-$(CONFIG_AUDIT) += compat_audit.o obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o -obj-$(CONFIG_PERF_COUNTERS) += perf_counter.o power4-pmu.o ppc970-pmu.o \ - power5-pmu.o power5+-pmu.o power6-pmu.o \ - power7-pmu.o +obj-$(CONFIG_PPC_PERF_CTRS) += perf_counter.o +obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \ + power5+-pmu.o power6-pmu.o power7-pmu.o +obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o @@ -106,6 +109,7 @@ obj-y += iomap.o endif obj-$(CONFIG_PPC64) += $(obj64-y) +obj-$(CONFIG_PPC32) += $(obj32-y) ifneq ($(CONFIG_XMON)$(CONFIG_KEXEC),) obj-y += ppc_save_regs.o diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S index 54f767e..1e9949e 100644 --- a/arch/powerpc/kernel/cpu_setup_6xx.S +++ b/arch/powerpc/kernel/cpu_setup_6xx.S @@ -239,6 +239,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_L3CR) ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE ori r11,r11,HID0_LRSTK | HID0_BTIC oris r11,r11,HID0_DPM@h +BEGIN_MMU_FTR_SECTION + oris r11,r11,HID0_HIGH_BAT@h +END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) BEGIN_FTR_SECTION xori r11,r11,HID0_BTIC END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC) diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index eb4b9ad..0adb50a 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -17,6 +17,40 @@ #include <asm/cputable.h> #include <asm/ppc_asm.h> +_GLOBAL(__e500_icache_setup) + mfspr r0, SPRN_L1CSR1 + andi. r3, r0, L1CSR1_ICE + bnelr /* Already enabled */ + oris r0, r0, L1CSR1_CPE@h + ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE) + mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */ + isync + blr + +_GLOBAL(__e500_dcache_setup) + mfspr r0, SPRN_L1CSR0 + andi. r3, r0, L1CSR0_DCE + bnelr /* Already enabled */ + msync + isync + li r0, 0 + mtspr SPRN_L1CSR0, r0 /* Disable */ + msync + isync + li r0, (L1CSR0_DCFI | L1CSR0_CLFC) + mtspr SPRN_L1CSR0, r0 /* Invalidate */ + isync +1: mfspr r0, SPRN_L1CSR0 + andi. r3, r0, L1CSR0_CLFC + bne+ 1b /* Wait for lock bits reset */ + oris r0, r0, L1CSR0_CPE@h + ori r0, r0, L1CSR0_DCE + msync + isync + mtspr SPRN_L1CSR0, r0 /* Enable */ + isync + blr + _GLOBAL(__setup_cpu_e200) /* enable dedicated debug exception handling resources (Debug APU) */ mfspr r3,SPRN_HID0 @@ -25,7 +59,16 @@ _GLOBAL(__setup_cpu_e200) b __setup_e200_ivors _GLOBAL(__setup_cpu_e500v1) _GLOBAL(__setup_cpu_e500v2) - b __setup_e500_ivors + mflr r4 + bl __e500_icache_setup + bl __e500_dcache_setup + bl __setup_e500_ivors + mtlr r4 + blr _GLOBAL(__setup_cpu_e500mc) - b __setup_e500mc_ivors - + mflr r4 + bl __e500_icache_setup + bl __e500_dcache_setup + bl __setup_e500mc_ivors + mtlr r4 + blr diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 4dd38f1..3cadba6 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -191,11 +191,49 @@ transfer_to_handler_cont: mflr r9 lwz r11,0(r9) /* virtual address of handler */ lwz r9,4(r9) /* where to go when done */ +#ifdef CONFIG_TRACE_IRQFLAGS + lis r12,reenable_mmu@h + ori r12,r12,reenable_mmu@l + mtspr SPRN_SRR0,r12 + mtspr SPRN_SRR1,r10 + SYNC + RFI +reenable_mmu: /* re-enable mmu so we can */ + mfmsr r10 + lwz r12,_MSR(r1) + xor r10,r10,r12 + andi. r10,r10,MSR_EE /* Did EE change? */ + beq 1f + + /* Save handler and return address into the 2 unused words + * of the STACK_FRAME_OVERHEAD (sneak sneak sneak). Everything + * else can be recovered from the pt_regs except r3 which for + * normal interrupts has been set to pt_regs and for syscalls + * is an argument, so we temporarily use ORIG_GPR3 to save it + */ + stw r9,8(r1) + stw r11,12(r1) + stw r3,ORIG_GPR3(r1) + bl trace_hardirqs_off + lwz r0,GPR0(r1) + lwz r3,ORIG_GPR3(r1) + lwz r4,GPR4(r1) + lwz r5,GPR5(r1) + lwz r6,GPR6(r1) + lwz r7,GPR7(r1) + lwz r8,GPR8(r1) + lwz r9,8(r1) + lwz r11,12(r1) +1: mtctr r11 + mtlr r9 + bctr /* jump to handler */ +#else /* CONFIG_TRACE_IRQFLAGS */ mtspr SPRN_SRR0,r11 mtspr SPRN_SRR1,r10 mtlr r9 SYNC RFI /* jump to handler, enable MMU */ +#endif /* CONFIG_TRACE_IRQFLAGS */ #if defined (CONFIG_6xx) || defined(CONFIG_E500) 4: rlwinm r12,r12,0,~_TLF_NAPPING @@ -251,6 +289,31 @@ _GLOBAL(DoSyscall) #ifdef SHOW_SYSCALLS bl do_show_syscall #endif /* SHOW_SYSCALLS */ +#ifdef CONFIG_TRACE_IRQFLAGS + /* Return from syscalls can (and generally will) hard enable + * interrupts. You aren't supposed to call a syscall with + * interrupts disabled in the first place. However, to ensure + * that we get it right vs. lockdep if it happens, we force + * that hard enable here with appropriate tracing if we see + * that we have been called with interrupts off + */ + mfmsr r11 + andi. r12,r11,MSR_EE + bne+ 1f + /* We came in with interrupts disabled, we enable them now */ + bl trace_hardirqs_on + mfmsr r11 + lwz r0,GPR0(r1) + lwz r3,GPR3(r1) + lwz r4,GPR4(r1) + ori r11,r11,MSR_EE + lwz r5,GPR5(r1) + lwz r6,GPR6(r1) + lwz r7,GPR7(r1) + lwz r8,GPR8(r1) + mtmsr r11 +1: +#endif /* CONFIG_TRACE_IRQFLAGS */ rlwinm r10,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */ lwz r11,TI_FLAGS(r10) andi. r11,r11,_TIF_SYSCALL_T_OR_A @@ -275,6 +338,7 @@ ret_from_syscall: rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */ /* disable interrupts so current_thread_info()->flags can't change */ LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */ + /* Note: We don't bother telling lockdep about it */ SYNC MTMSRD(r10) lwz r9,TI_FLAGS(r12) @@ -288,6 +352,19 @@ ret_from_syscall: oris r11,r11,0x1000 /* Set SO bit in CR */ stw r11,_CCR(r1) syscall_exit_cont: + lwz r8,_MSR(r1) +#ifdef CONFIG_TRACE_IRQFLAGS + /* If we are going to return from the syscall with interrupts + * off, we trace that here. It shouldn't happen though but we + * want to catch the bugger if it does right ? + */ + andi. r10,r8,MSR_EE + bne+ 1f + stw r3,GPR3(r1) + bl trace_hardirqs_off + lwz r3,GPR3(r1) +1: +#endif /* CONFIG_TRACE_IRQFLAGS */ #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) /* If the process has its own DBCR0 value, load it up. The internal debug mode bit tells us that dbcr0 should be loaded. */ @@ -311,7 +388,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) mtlr r4 mtcr r5 lwz r7,_NIP(r1) - lwz r8,_MSR(r1) FIX_SRR1(r8, r0) lwz r2,GPR2(r1) lwz r1,GPR1(r1) @@ -394,7 +470,9 @@ syscall_exit_work: andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP) beq ret_from_except - /* Re-enable interrupts */ + /* Re-enable interrupts. There is no need to trace that with + * lockdep as we are supposed to have IRQs on at this point + */ ori r10,r10,MSR_EE SYNC MTMSRD(r10) @@ -705,6 +783,7 @@ ret_from_except: /* Hard-disable interrupts so that current_thread_info()->flags * can't change between when we test it and when we return * from the interrupt. */ + /* Note: We don't bother telling lockdep about it */ LOAD_MSR_KERNEL(r10,MSR_KERNEL) SYNC /* Some chip revs have problems here... */ MTMSRD(r10) /* disable interrupts */ @@ -744,11 +823,24 @@ resume_kernel: beq+ restore andi. r0,r3,MSR_EE /* interrupts off? */ beq restore /* don't schedule if so */ +#ifdef CONFIG_TRACE_IRQFLAGS + /* Lockdep thinks irqs are enabled, we need to call + * preempt_schedule_irq with IRQs off, so we inform lockdep + * now that we -did- turn them off already + */ + bl trace_hardirqs_off +#endif 1: bl preempt_schedule_irq rlwinm r9,r1,0,0,(31-THREAD_SHIFT) lwz r3,TI_FLAGS(r9) andi. r0,r3,_TIF_NEED_RESCHED bne- 1b +#ifdef CONFIG_TRACE_IRQFLAGS + /* And now, to properly rebalance the above, we tell lockdep they + * are being turned back on, which will happen when we return + */ + bl trace_hardirqs_on +#endif #else resume_kernel: #endif /* CONFIG_PREEMPT */ @@ -765,6 +857,28 @@ restore: stw r6,icache_44x_need_flush@l(r4) 1: #endif /* CONFIG_44x */ + + lwz r9,_MSR(r1) +#ifdef CONFIG_TRACE_IRQFLAGS + /* Lockdep doesn't know about the fact that IRQs are temporarily turned + * off in this assembly code while peeking at TI_FLAGS() and such. However + * we need to inform it if the exception turned interrupts off, and we + * are about to trun them back on. + * + * The problem here sadly is that we don't know whether the exceptions was + * one that turned interrupts off or not. So we always tell lockdep about + * turning them on here when we go back to wherever we came from with EE + * on, even if that may meen some redudant calls being tracked. Maybe later + * we could encode what the exception did somewhere or test the exception + * type in the pt_regs but that sounds overkill + */ + andi. r10,r9,MSR_EE + beq 1f + bl trace_hardirqs_on + lwz r9,_MSR(r1) +1: +#endif /* CONFIG_TRACE_IRQFLAGS */ + lwz r0,GPR0(r1) lwz r2,GPR2(r1) REST_4GPRS(3, r1) @@ -782,7 +896,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) stwcx. r0,0,r1 /* to clear the reservation */ #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) - lwz r9,_MSR(r1) andi. r10,r9,MSR_RI /* check if this exception occurred */ beql nonrecoverable /* at a bad place (MSR:RI = 0) */ @@ -805,7 +918,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) MTMSRD(r10) /* clear the RI bit */ .globl exc_exit_restart exc_exit_restart: - lwz r9,_MSR(r1) lwz r12,_NIP(r1) FIX_SRR1(r9,r10) mtspr SPRN_SRR0,r12 @@ -1035,11 +1147,18 @@ do_work: /* r10 contains MSR_KERNEL here */ beq do_user_signal do_resched: /* r10 contains MSR_KERNEL here */ + /* Note: We don't need to inform lockdep that we are enabling + * interrupts here. As far as it knows, they are already enabled + */ ori r10,r10,MSR_EE SYNC MTMSRD(r10) /* hard-enable interrupts */ bl schedule recheck: + /* Note: And we don't tell it we are disabling them again + * neither. Those disable/enable cycles used to peek at + * TI_FLAGS aren't advertised. + */ LOAD_MSR_KERNEL(r10,MSR_KERNEL) SYNC MTMSRD(r10) /* disable interrupts */ diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c index 1b12696..ce1f3e44 100644 --- a/arch/powerpc/kernel/ftrace.c +++ b/arch/powerpc/kernel/ftrace.c @@ -586,7 +586,7 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr) return; } - if (ftrace_push_return_trace(old, self_addr, &trace.depth) == -EBUSY) { + if (ftrace_push_return_trace(old, self_addr, &trace.depth, 0) == -EBUSY) { *parent = old; return; } diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index 4846946..fc21329 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -1124,9 +1124,8 @@ mmu_off: RFI /* - * Use the first pair of BAT registers to map the 1st 16MB - * of RAM to PAGE_OFFSET. From this point on we can't safely - * call OF any more. + * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET + * (we keep one for debugging) and on others, we use one 256M BAT. */ initial_bats: lis r11,PAGE_OFFSET@h @@ -1136,12 +1135,16 @@ initial_bats: bne 4f ori r11,r11,4 /* set up BAT registers for 601 */ li r8,0x7f /* valid, block length = 8MB */ - oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */ - oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */ mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */ mtspr SPRN_IBAT0L,r8 /* lower BAT register */ - mtspr SPRN_IBAT1U,r9 - mtspr SPRN_IBAT1L,r10 + addis r11,r11,0x800000@h + addis r8,r8,0x800000@h + mtspr SPRN_IBAT1U,r11 + mtspr SPRN_IBAT1L,r8 + addis r11,r11,0x800000@h + addis r8,r8,0x800000@h + mtspr SPRN_IBAT2U,r11 + mtspr SPRN_IBAT2L,r8 isync blr diff --git a/arch/powerpc/kernel/mpc7450-pmu.c b/arch/powerpc/kernel/mpc7450-pmu.c new file mode 100644 index 0000000..75ff47f --- /dev/null +++ b/arch/powerpc/kernel/mpc7450-pmu.c @@ -0,0 +1,417 @@ +/* + * Performance counter support for MPC7450-family processors. + * + * Copyright 2008-2009 Paul Mackerras, IBM Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include <linux/string.h> +#include <linux/perf_counter.h> +#include <linux/string.h> +#include <asm/reg.h> +#include <asm/cputable.h> + +#define N_COUNTER 6 /* Number of hardware counters */ +#define MAX_ALT 3 /* Maximum number of event alternative codes */ + +/* + * Bits in event code for MPC7450 family + */ +#define PM_THRMULT_MSKS 0x40000 +#define PM_THRESH_SH 12 +#define PM_THRESH_MSK 0x3f +#define PM_PMC_SH 8 +#define PM_PMC_MSK 7 +#define PM_PMCSEL_MSK 0x7f + +/* + * Classify events according to how specific their PMC requirements are. + * Result is: + * 0: can go on any PMC + * 1: can go on PMCs 1-4 + * 2: can go on PMCs 1,2,4 + * 3: can go on PMCs 1 or 2 + * 4: can only go on one PMC + * -1: event code is invalid + */ +#define N_CLASSES 5 + +static int mpc7450_classify_event(u32 event) +{ + int pmc; + + pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; + if (pmc) { + if (pmc > N_COUNTER) + return -1; + return 4; + } + event &= PM_PMCSEL_MSK; + if (event <= 1) + return 0; + if (event <= 7) + return 1; + if (event <= 13) + return 2; + if (event <= 22) + return 3; + return -1; +} + +/* + * Events using threshold and possible threshold scale: + * code scale? name + * 11e N PM_INSTQ_EXCEED_CYC + * 11f N PM_ALTV_IQ_EXCEED_CYC + * 128 Y PM_DTLB_SEARCH_EXCEED_CYC + * 12b Y PM_LD_MISS_EXCEED_L1_CYC + * 220 N PM_CQ_EXCEED_CYC + * 30c N PM_GPR_RB_EXCEED_CYC + * 30d ? PM_FPR_IQ_EXCEED_CYC ? + * 311 Y PM_ITLB_SEARCH_EXCEED + * 410 N PM_GPR_IQ_EXCEED_CYC + */ + +/* + * Return use of threshold and threshold scale bits: + * 0 = uses neither, 1 = uses threshold, 2 = uses both + */ +static int mpc7450_threshold_use(u32 event) +{ + int pmc, sel; + + pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; + sel = event & PM_PMCSEL_MSK; + switch (pmc) { + case 1: + if (sel == 0x1e || sel == 0x1f) + return 1; + if (sel == 0x28 || sel == 0x2b) + return 2; + break; + case 2: + if (sel == 0x20) + return 1; + break; + case 3: + if (sel == 0xc || sel == 0xd) + return 1; + if (sel == 0x11) + return 2; + break; + case 4: + if (sel == 0x10) + return 1; + break; + } + return 0; +} + +/* + * Layout of constraint bits: + * 33222222222211111111110000000000 + * 10987654321098765432109876543210 + * |< >< > < > < ><><><><><><> + * TS TV G4 G3 G2P6P5P4P3P2P1 + * + * P1 - P6 + * 0 - 11: Count of events needing PMC1 .. PMC6 + * + * G2 + * 12 - 14: Count of events needing PMC1 or PMC2 + * + * G3 + * 16 - 18: Count of events needing PMC1, PMC2 or PMC4 + * + * G4 + * 20 - 23: Count of events needing PMC1, PMC2, PMC3 or PMC4 + * + * TV + * 24 - 29: Threshold value requested + * + * TS + * 30: Threshold scale value requested + */ + +static u32 pmcbits[N_COUNTER][2] = { + { 0x00844002, 0x00111001 }, /* PMC1 mask, value: P1,G2,G3,G4 */ + { 0x00844008, 0x00111004 }, /* PMC2: P2,G2,G3,G4 */ + { 0x00800020, 0x00100010 }, /* PMC3: P3,G4 */ + { 0x00840080, 0x00110040 }, /* PMC4: P4,G3,G4 */ + { 0x00000200, 0x00000100 }, /* PMC5: P5 */ + { 0x00000800, 0x00000400 } /* PMC6: P6 */ +}; + +static u32 classbits[N_CLASSES - 1][2] = { + { 0x00000000, 0x00000000 }, /* class 0: no constraint */ + { 0x00800000, 0x00100000 }, /* class 1: G4 */ + { 0x00040000, 0x00010000 }, /* class 2: G3 */ + { 0x00004000, 0x00001000 }, /* class 3: G2 */ +}; + +static int mpc7450_get_constraint(u64 event, unsigned long *maskp, + unsigned long *valp) +{ + int pmc, class; + u32 mask, value; + int thresh, tuse; + + class = mpc7450_classify_event(event); + if (class < 0) + return -1; + if (class == 4) { + pmc = ((unsigned int)event >> PM_PMC_SH) & PM_PMC_MSK; + mask = pmcbits[pmc - 1][0]; + value = pmcbits[pmc - 1][1]; + } else { + mask = classbits[class][0]; + value = classbits[class][1]; + } + + tuse = mpc7450_threshold_use(event); + if (tuse) { + thresh = ((unsigned int)event >> PM_THRESH_SH) & PM_THRESH_MSK; + mask |= 0x3f << 24; + value |= thresh << 24; + if (tuse == 2) { + mask |= 0x40000000; + if ((unsigned int)event & PM_THRMULT_MSKS) + value |= 0x40000000; + } + } + + *maskp = mask; + *valp = value; + return 0; +} + +static const unsigned int event_alternatives[][MAX_ALT] = { + { 0x217, 0x317 }, /* PM_L1_DCACHE_MISS */ + { 0x418, 0x50f, 0x60f }, /* PM_SNOOP_RETRY */ + { 0x502, 0x602 }, /* PM_L2_HIT */ + { 0x503, 0x603 }, /* PM_L3_HIT */ + { 0x504, 0x604 }, /* PM_L2_ICACHE_MISS */ + { 0x505, 0x605 }, /* PM_L3_ICACHE_MISS */ + { 0x506, 0x606 }, /* PM_L2_DCACHE_MISS */ + { 0x507, 0x607 }, /* PM_L3_DCACHE_MISS */ + { 0x50a, 0x623 }, /* PM_LD_HIT_L3 */ + { 0x50b, 0x624 }, /* PM_ST_HIT_L3 */ + { 0x50d, 0x60d }, /* PM_L2_TOUCH_HIT */ + { 0x50e, 0x60e }, /* PM_L3_TOUCH_HIT */ + { 0x512, 0x612 }, /* PM_INT_LOCAL */ + { 0x513, 0x61d }, /* PM_L2_MISS */ + { 0x514, 0x61e }, /* PM_L3_MISS */ +}; + +/* + * Scan the alternatives table for a match and return the + * index into the alternatives table if found, else -1. + */ +static int find_alternative(u32 event) +{ + int i, j; + + for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { + if (event < event_alternatives[i][0]) + break; + for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j) + if (event == event_alternatives[i][j]) + return i; + } + return -1; +} + +static int mpc7450_get_alternatives(u64 event, unsigned int flags, u64 alt[]) +{ + int i, j, nalt = 1; + u32 ae; + + alt[0] = event; + nalt = 1; + i = find_alternative((u32)event); + if (i >= 0) { + for (j = 0; j < MAX_ALT; ++j) { + ae = event_alternatives[i][j]; + if (ae && ae != (u32)event) + alt[nalt++] = ae; + } + } + return nalt; +} + +/* + * Bitmaps of which PMCs each class can use for classes 0 - 3. + * Bit i is set if PMC i+1 is usable. + */ +static const u8 classmap[N_CLASSES] = { + 0x3f, 0x0f, 0x0b, 0x03, 0 +}; + +/* Bit position and width of each PMCSEL field */ +static const int pmcsel_shift[N_COUNTER] = { + 6, 0, 27, 22, 17, 11 +}; +static const u32 pmcsel_mask[N_COUNTER] = { + 0x7f, 0x3f, 0x1f, 0x1f, 0x1f, 0x3f +}; + +/* + * Compute MMCR0/1/2 values for a set of events. + */ +static int mpc7450_compute_mmcr(u64 event[], int n_ev, + unsigned int hwc[], unsigned long mmcr[]) +{ + u8 event_index[N_CLASSES][N_COUNTER]; + int n_classevent[N_CLASSES]; + int i, j, class, tuse; + u32 pmc_inuse = 0, pmc_avail; + u32 mmcr0 = 0, mmcr1 = 0, mmcr2 = 0; + u32 ev, pmc, thresh; + + if (n_ev > N_COUNTER) + return -1; + + /* First pass: count usage in each class */ + for (i = 0; i < N_CLASSES; ++i) + n_classevent[i] = 0; + for (i = 0; i < n_ev; ++i) { + class = mpc7450_classify_event(event[i]); + if (class < 0) + return -1; + j = n_classevent[class]++; + event_index[class][j] = i; + } + + /* Second pass: allocate PMCs from most specific event to least */ + for (class = N_CLASSES - 1; class >= 0; --class) { + for (i = 0; i < n_classevent[class]; ++i) { + ev = event[event_index[class][i]]; + if (class == 4) { + pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK; + if (pmc_inuse & (1 << (pmc - 1))) + return -1; + } else { + /* Find a suitable PMC */ + pmc_avail = classmap[class] & ~pmc_inuse; + if (!pmc_avail) + return -1; + pmc = ffs(pmc_avail); + } + pmc_inuse |= 1 << (pmc - 1); + + tuse = mpc7450_threshold_use(ev); + if (tuse) { + thresh = (ev >> PM_THRESH_SH) & PM_THRESH_MSK; + mmcr0 |= thresh << 16; + if (tuse == 2 && (ev & PM_THRMULT_MSKS)) + mmcr2 = 0x80000000; + } + ev &= pmcsel_mask[pmc - 1]; + ev <<= pmcsel_shift[pmc - 1]; + if (pmc <= 2) + mmcr0 |= ev; + else + mmcr1 |= ev; + hwc[event_index[class][i]] = pmc - 1; + } + } + + if (pmc_inuse & 1) + mmcr0 |= MMCR0_PMC1CE; + if (pmc_inuse & 0x3e) + mmcr0 |= MMCR0_PMCnCE; + + /* Return MMCRx values */ + mmcr[0] = mmcr0; + mmcr[1] = mmcr1; + mmcr[2] = mmcr2; + return 0; +} + +/* + * Disable counting by a PMC. + * Note that the pmc argument is 0-based here, not 1-based. + */ +static void mpc7450_disable_pmc(unsigned int pmc, unsigned long mmcr[]) +{ + if (pmc <= 1) + mmcr[0] &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]); + else + mmcr[1] &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]); +} + +static int mpc7450_generic_events[] = { + [PERF_COUNT_HW_CPU_CYCLES] = 1, + [PERF_COUNT_HW_INSTRUCTIONS] = 2, + [PERF_COUNT_HW_CACHE_MISSES] = 0x217, /* PM_L1_DCACHE_MISS */ + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x122, /* PM_BR_CMPL */ + [PERF_COUNT_HW_BRANCH_MISSES] = 0x41c, /* PM_BR_MPRED */ +}; + +#define C(x) PERF_COUNT_HW_CACHE_##x + +/* + * Table of generalized cache-related events. + * 0 means not supported, -1 means nonsensical, other values + * are event codes. + */ +static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { + [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ + [C(OP_READ)] = { 0, 0x225 }, + [C(OP_WRITE)] = { 0, 0x227 }, + [C(OP_PREFETCH)] = { 0, 0 }, + }, + [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ + [C(OP_READ)] = { 0x129, 0x115 }, + [C(OP_WRITE)] = { -1, -1 }, + [C(OP_PREFETCH)] = { 0x634, 0 }, + }, + [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ + [C(OP_READ)] = { 0, 0 }, + [C(OP_WRITE)] = { 0, 0 }, + [C(OP_PREFETCH)] = { 0, 0 }, + }, + [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ + [C(OP_READ)] = { 0, 0x312 }, + [C(OP_WRITE)] = { -1, -1 }, + [C(OP_PREFETCH)] = { -1, -1 }, + }, + [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ + [C(OP_READ)] = { 0, 0x223 }, + [C(OP_WRITE)] = { -1, -1 }, + [C(OP_PREFETCH)] = { -1, -1 }, + }, + [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ + [C(OP_READ)] = { 0x122, 0x41c }, + [C(OP_WRITE)] = { -1, -1 }, + [C(OP_PREFETCH)] = { -1, -1 }, + }, +}; + +struct power_pmu mpc7450_pmu = { + .name = "MPC7450 family", + .n_counter = N_COUNTER, + .max_alternatives = MAX_ALT, + .add_fields = 0x00111555ul, + .test_adder = 0x00301000ul, + .compute_mmcr = mpc7450_compute_mmcr, + .get_constraint = mpc7450_get_constraint, + .get_alternatives = mpc7450_get_alternatives, + .disable_pmc = mpc7450_disable_pmc, + .n_generic = ARRAY_SIZE(mpc7450_generic_events), + .generic_events = mpc7450_generic_events, + .cache_events = &mpc7450_cache_events, +}; + +static int init_mpc7450_pmu(void) +{ + if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/7450")) + return -ENODEV; + + return register_power_pmu(&mpc7450_pmu); +} + +arch_initcall(init_mpc7450_pmu); diff --git a/arch/powerpc/kernel/of_device.c b/arch/powerpc/kernel/of_device.c index fa983a5..a359cb0 100644 --- a/arch/powerpc/kernel/of_device.c +++ b/arch/powerpc/kernel/of_device.c @@ -76,7 +76,7 @@ struct of_device *of_device_alloc(struct device_node *np, dev->dev.archdata.of_node = np; if (bus_id) - dev_set_name(&dev->dev, bus_id); + dev_set_name(&dev->dev, "%s", bus_id); else of_device_make_bus_id(dev); diff --git a/arch/powerpc/kernel/perf_counter.c b/arch/powerpc/kernel/perf_counter.c index bb20238..809fdf9 100644 --- a/arch/powerpc/kernel/perf_counter.c +++ b/arch/powerpc/kernel/perf_counter.c @@ -29,7 +29,7 @@ struct cpu_hw_counters { struct perf_counter *counter[MAX_HWCOUNTERS]; u64 events[MAX_HWCOUNTERS]; unsigned int flags[MAX_HWCOUNTERS]; - u64 mmcr[3]; + unsigned long mmcr[3]; struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS]; u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; }; @@ -46,6 +46,115 @@ struct power_pmu *ppmu; */ static unsigned int freeze_counters_kernel = MMCR0_FCS; +/* + * 32-bit doesn't have MMCRA but does have an MMCR2, + * and a few other names are different. + */ +#ifdef CONFIG_PPC32 + +#define MMCR0_FCHV 0 +#define MMCR0_PMCjCE MMCR0_PMCnCE + +#define SPRN_MMCRA SPRN_MMCR2 +#define MMCRA_SAMPLE_ENABLE 0 + +static inline unsigned long perf_ip_adjust(struct pt_regs *regs) +{ + return 0; +} +static inline void perf_set_pmu_inuse(int inuse) { } +static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } +static inline u32 perf_get_misc_flags(struct pt_regs *regs) +{ + return 0; +} +static inline void perf_read_regs(struct pt_regs *regs) { } +static inline int perf_intr_is_nmi(struct pt_regs *regs) +{ + return 0; +} + +#endif /* CONFIG_PPC32 */ + +/* + * Things that are specific to 64-bit implementations. + */ +#ifdef CONFIG_PPC64 + +static inline unsigned long perf_ip_adjust(struct pt_regs *regs) +{ + unsigned long mmcra = regs->dsisr; + + if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) { + unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; + if (slot > 1) + return 4 * (slot - 1); + } + return 0; +} + +static inline void perf_set_pmu_inuse(int inuse) +{ + get_lppaca()->pmcregs_in_use = inuse; +} + +/* + * The user wants a data address recorded. + * If we're not doing instruction sampling, give them the SDAR + * (sampled data address). If we are doing instruction sampling, then + * only give them the SDAR if it corresponds to the instruction + * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC + * bit in MMCRA. + */ +static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) +{ + unsigned long mmcra = regs->dsisr; + unsigned long sdsync = (ppmu->flags & PPMU_ALT_SIPR) ? + POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC; + + if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) + *addrp = mfspr(SPRN_SDAR); +} + +static inline u32 perf_get_misc_flags(struct pt_regs *regs) +{ + unsigned long mmcra = regs->dsisr; + + if (TRAP(regs) != 0xf00) + return 0; /* not a PMU interrupt */ + + if (ppmu->flags & PPMU_ALT_SIPR) { + if (mmcra & POWER6_MMCRA_SIHV) + return PERF_EVENT_MISC_HYPERVISOR; + return (mmcra & POWER6_MMCRA_SIPR) ? + PERF_EVENT_MISC_USER : PERF_EVENT_MISC_KERNEL; + } + if (mmcra & MMCRA_SIHV) + return PERF_EVENT_MISC_HYPERVISOR; + return (mmcra & MMCRA_SIPR) ? PERF_EVENT_MISC_USER : + PERF_EVENT_MISC_KERNEL; +} + +/* + * Overload regs->dsisr to store MMCRA so we only need to read it once + * on each interrupt. + */ +static inline void perf_read_regs(struct pt_regs *regs) +{ + regs->dsisr = mfspr(SPRN_MMCRA); +} + +/* + * If interrupts were soft-disabled when a PMU interrupt occurs, treat + * it as an NMI. + */ +static inline int perf_intr_is_nmi(struct pt_regs *regs) +{ + return !regs->softe; +} + +#endif /* CONFIG_PPC64 */ + static void perf_counter_interrupt(struct pt_regs *regs); void perf_counter_print_debug(void) @@ -78,12 +187,14 @@ static unsigned long read_pmc(int idx) case 6: val = mfspr(SPRN_PMC6); break; +#ifdef CONFIG_PPC64 case 7: val = mfspr(SPRN_PMC7); break; case 8: val = mfspr(SPRN_PMC8); break; +#endif /* CONFIG_PPC64 */ default: printk(KERN_ERR "oops trying to read PMC%d\n", idx); val = 0; @@ -115,12 +226,14 @@ static void write_pmc(int idx, unsigned long val) case 6: mtspr(SPRN_PMC6, val); break; +#ifdef CONFIG_PPC64 case 7: mtspr(SPRN_PMC7, val); break; case 8: mtspr(SPRN_PMC8, val); break; +#endif /* CONFIG_PPC64 */ default: printk(KERN_ERR "oops trying to write PMC%d\n", idx); } @@ -135,15 +248,15 @@ static void write_pmc(int idx, unsigned long val) static int power_check_constraints(u64 event[], unsigned int cflags[], int n_ev) { - u64 mask, value, nv; + unsigned long mask, value, nv; u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; - u64 amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; - u64 avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; - u64 smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS]; + unsigned long amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; + unsigned long avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; + unsigned long smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS]; int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS]; int i, j; - u64 addf = ppmu->add_fields; - u64 tadd = ppmu->test_adder; + unsigned long addf = ppmu->add_fields; + unsigned long tadd = ppmu->test_adder; if (n_ev > ppmu->n_counter) return -1; @@ -283,7 +396,7 @@ static int check_excludes(struct perf_counter **ctrs, unsigned int cflags[], static void power_pmu_read(struct perf_counter *counter) { - long val, delta, prev; + s64 val, delta, prev; if (!counter->hw.idx) return; @@ -403,14 +516,12 @@ static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0) void hw_perf_disable(void) { struct cpu_hw_counters *cpuhw; - unsigned long ret; unsigned long flags; local_irq_save(flags); cpuhw = &__get_cpu_var(cpu_hw_counters); - ret = cpuhw->disabled; - if (!ret) { + if (!cpuhw->disabled) { cpuhw->disabled = 1; cpuhw->n_added = 0; @@ -479,7 +590,7 @@ void hw_perf_enable(void) mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); if (cpuhw->n_counters == 0) - get_lppaca()->pmcregs_in_use = 0; + perf_set_pmu_inuse(0); goto out_enable; } @@ -512,7 +623,7 @@ void hw_perf_enable(void) * bit set and set the hardware counters to their initial values. * Then unfreeze the counters. */ - get_lppaca()->pmcregs_in_use = 1; + perf_set_pmu_inuse(1); mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) @@ -913,6 +1024,8 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter) case PERF_TYPE_RAW: ev = counter->attr.config; break; + default: + return ERR_PTR(-EINVAL); } counter->hw.config_base = ev; counter->hw.idx = 0; @@ -1007,13 +1120,12 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter) * things if requested. Note that interrupts are hard-disabled * here so there is no possibility of being interrupted. */ -static void record_and_restart(struct perf_counter *counter, long val, +static void record_and_restart(struct perf_counter *counter, unsigned long val, struct pt_regs *regs, int nmi) { u64 period = counter->hw.sample_period; s64 prev, delta, left; int record = 0; - u64 addr, mmcra, sdsync; /* we don't have to worry about interrupts here */ prev = atomic64_read(&counter->hw.prev_count); @@ -1033,8 +1145,8 @@ static void record_and_restart(struct perf_counter *counter, long val, left = period; record = 1; } - if (left < 0x80000000L) - val = 0x80000000L - left; + if (left < 0x80000000LL) + val = 0x80000000LL - left; } /* @@ -1047,22 +1159,9 @@ static void record_and_restart(struct perf_counter *counter, long val, .period = counter->hw.last_period, }; - if (counter->attr.sample_type & PERF_SAMPLE_ADDR) { - /* - * The user wants a data address recorded. - * If we're not doing instruction sampling, - * give them the SDAR (sampled data address). - * If we are doing instruction sampling, then only - * give them the SDAR if it corresponds to the - * instruction pointed to by SIAR; this is indicated - * by the [POWER6_]MMCRA_SDSYNC bit in MMCRA. - */ - mmcra = regs->dsisr; - sdsync = (ppmu->flags & PPMU_ALT_SIPR) ? - POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC; - if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) - data.addr = mfspr(SPRN_SDAR); - } + if (counter->attr.sample_type & PERF_SAMPLE_ADDR) + perf_get_data_addr(regs, &data.addr); + if (perf_counter_overflow(counter, nmi, &data)) { /* * Interrupts are coming too fast - throttle them @@ -1088,25 +1187,12 @@ static void record_and_restart(struct perf_counter *counter, long val, */ unsigned long perf_misc_flags(struct pt_regs *regs) { - unsigned long mmcra; - - if (TRAP(regs) != 0xf00) { - /* not a PMU interrupt */ - return user_mode(regs) ? PERF_EVENT_MISC_USER : - PERF_EVENT_MISC_KERNEL; - } + u32 flags = perf_get_misc_flags(regs); - mmcra = regs->dsisr; - if (ppmu->flags & PPMU_ALT_SIPR) { - if (mmcra & POWER6_MMCRA_SIHV) - return PERF_EVENT_MISC_HYPERVISOR; - return (mmcra & POWER6_MMCRA_SIPR) ? PERF_EVENT_MISC_USER : - PERF_EVENT_MISC_KERNEL; - } - if (mmcra & MMCRA_SIHV) - return PERF_EVENT_MISC_HYPERVISOR; - return (mmcra & MMCRA_SIPR) ? PERF_EVENT_MISC_USER : - PERF_EVENT_MISC_KERNEL; + if (flags) + return flags; + return user_mode(regs) ? PERF_EVENT_MISC_USER : + PERF_EVENT_MISC_KERNEL; } /* @@ -1115,20 +1201,12 @@ unsigned long perf_misc_flags(struct pt_regs *regs) */ unsigned long perf_instruction_pointer(struct pt_regs *regs) { - unsigned long mmcra; unsigned long ip; - unsigned long slot; if (TRAP(regs) != 0xf00) return regs->nip; /* not a PMU interrupt */ - ip = mfspr(SPRN_SIAR); - mmcra = regs->dsisr; - if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) { - slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; - if (slot > 1) - ip += 4 * (slot - 1); - } + ip = mfspr(SPRN_SIAR) + perf_ip_adjust(regs); return ip; } @@ -1140,7 +1218,7 @@ static void perf_counter_interrupt(struct pt_regs *regs) int i; struct cpu_hw_counters *cpuhw = &__get_cpu_var(cpu_hw_counters); struct perf_counter *counter; - long val; + unsigned long val; int found = 0; int nmi; @@ -1148,16 +1226,9 @@ static void perf_counter_interrupt(struct pt_regs *regs) freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), mfspr(SPRN_PMC6)); - /* - * Overload regs->dsisr to store MMCRA so we only need to read it once. - */ - regs->dsisr = mfspr(SPRN_MMCRA); + perf_read_regs(regs); - /* - * If interrupts were soft-disabled when this PMU interrupt - * occurred, treat it as an NMI. - */ - nmi = !regs->softe; + nmi = perf_intr_is_nmi(regs); if (nmi) nmi_enter(); else @@ -1214,50 +1285,22 @@ void hw_perf_counter_setup(int cpu) cpuhw->mmcr[0] = MMCR0_FC; } -extern struct power_pmu power4_pmu; -extern struct power_pmu ppc970_pmu; -extern struct power_pmu power5_pmu; -extern struct power_pmu power5p_pmu; -extern struct power_pmu power6_pmu; -extern struct power_pmu power7_pmu; - -static int init_perf_counters(void) +int register_power_pmu(struct power_pmu *pmu) { - unsigned long pvr; - - /* XXX should get this from cputable */ - pvr = mfspr(SPRN_PVR); - switch (PVR_VER(pvr)) { - case PV_POWER4: - case PV_POWER4p: - ppmu = &power4_pmu; - break; - case PV_970: - case PV_970FX: - case PV_970MP: - ppmu = &ppc970_pmu; - break; - case PV_POWER5: - ppmu = &power5_pmu; - break; - case PV_POWER5p: - ppmu = &power5p_pmu; - break; - case 0x3e: - ppmu = &power6_pmu; - break; - case 0x3f: - ppmu = &power7_pmu; - break; - } + if (ppmu) + return -EBUSY; /* something's already registered */ + + ppmu = pmu; + pr_info("%s performance monitor hardware support registered\n", + pmu->name); +#ifdef MSR_HV /* * Use FCHV to ignore kernel events if MSR.HV is set. */ if (mfmsr() & MSR_HV) freeze_counters_kernel = MMCR0_FCHV; +#endif /* CONFIG_PPC64 */ return 0; } - -arch_initcall(init_perf_counters); diff --git a/arch/powerpc/kernel/power4-pmu.c b/arch/powerpc/kernel/power4-pmu.c index 07bd308..db90b0c 100644 --- a/arch/powerpc/kernel/power4-pmu.c +++ b/arch/powerpc/kernel/power4-pmu.c @@ -10,7 +10,9 @@ */ #include <linux/kernel.h> #include <linux/perf_counter.h> +#include <linux/string.h> #include <asm/reg.h> +#include <asm/cputable.h> /* * Bits in event code for POWER4 @@ -179,22 +181,22 @@ static short mmcr1_adder_bits[8] = { */ static struct unitinfo { - u64 value, mask; - int unit; - int lowerbit; + unsigned long value, mask; + int unit; + int lowerbit; } p4_unitinfo[16] = { - [PM_FPU] = { 0x44000000000000ull, 0x88000000000000ull, PM_FPU, 0 }, - [PM_ISU1] = { 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 }, + [PM_FPU] = { 0x44000000000000ul, 0x88000000000000ul, PM_FPU, 0 }, + [PM_ISU1] = { 0x20080000000000ul, 0x88000000000000ul, PM_ISU1, 0 }, [PM_ISU1_ALT] = - { 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 }, - [PM_IFU] = { 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 }, + { 0x20080000000000ul, 0x88000000000000ul, PM_ISU1, 0 }, + [PM_IFU] = { 0x02200000000000ul, 0x08820000000000ul, PM_IFU, 41 }, [PM_IFU_ALT] = - { 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 }, - [PM_IDU0] = { 0x10100000000000ull, 0x80840000000000ull, PM_IDU0, 1 }, - [PM_ISU2] = { 0x10140000000000ull, 0x80840000000000ull, PM_ISU2, 0 }, - [PM_LSU0] = { 0x01400000000000ull, 0x08800000000000ull, PM_LSU0, 0 }, - [PM_LSU1] = { 0x00000000000000ull, 0x00010000000000ull, PM_LSU1, 40 }, - [PM_GPS] = { 0x00000000000000ull, 0x00000000000000ull, PM_GPS, 0 } + { 0x02200000000000ul, 0x08820000000000ul, PM_IFU, 41 }, + [PM_IDU0] = { 0x10100000000000ul, 0x80840000000000ul, PM_IDU0, 1 }, + [PM_ISU2] = { 0x10140000000000ul, 0x80840000000000ul, PM_ISU2, 0 }, + [PM_LSU0] = { 0x01400000000000ul, 0x08800000000000ul, PM_LSU0, 0 }, + [PM_LSU1] = { 0x00000000000000ul, 0x00010000000000ul, PM_LSU1, 40 }, + [PM_GPS] = { 0x00000000000000ul, 0x00000000000000ul, PM_GPS, 0 } }; static unsigned char direct_marked_event[8] = { @@ -249,10 +251,11 @@ static int p4_marked_instr_event(u64 event) return (mask >> (byte * 8 + bit)) & 1; } -static int p4_get_constraint(u64 event, u64 *maskp, u64 *valp) +static int p4_get_constraint(u64 event, unsigned long *maskp, + unsigned long *valp) { int pmc, byte, unit, lower, sh; - u64 mask = 0, value = 0; + unsigned long mask = 0, value = 0; int grp = -1; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; @@ -282,14 +285,14 @@ static int p4_get_constraint(u64 event, u64 *maskp, u64 *valp) value |= p4_unitinfo[unit].value; sh = p4_unitinfo[unit].lowerbit; if (sh > 1) - value |= (u64)lower << sh; + value |= (unsigned long)lower << sh; else if (lower != sh) return -1; unit = p4_unitinfo[unit].unit; /* Set byte lane select field */ mask |= 0xfULL << (28 - 4 * byte); - value |= (u64)unit << (28 - 4 * byte); + value |= (unsigned long)unit << (28 - 4 * byte); } if (grp == 0) { /* increment PMC1/2/5/6 field */ @@ -353,9 +356,9 @@ static int p4_get_alternatives(u64 event, unsigned int flags, u64 alt[]) } static int p4_compute_mmcr(u64 event[], int n_ev, - unsigned int hwc[], u64 mmcr[]) + unsigned int hwc[], unsigned long mmcr[]) { - u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0; + unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0; unsigned int pmc, unit, byte, psel, lower; unsigned int ttm, grp; unsigned int pmc_inuse = 0; @@ -429,9 +432,11 @@ static int p4_compute_mmcr(u64 event[], int n_ev, return -1; /* Set TTMxSEL fields. Note, units 1-3 => TTM0SEL codes 0-2 */ - mmcr1 |= (u64)(unituse[3] * 2 + unituse[2]) << MMCR1_TTM0SEL_SH; - mmcr1 |= (u64)(unituse[7] * 3 + unituse[6] * 2) << MMCR1_TTM1SEL_SH; - mmcr1 |= (u64)unituse[9] << MMCR1_TTM2SEL_SH; + mmcr1 |= (unsigned long)(unituse[3] * 2 + unituse[2]) + << MMCR1_TTM0SEL_SH; + mmcr1 |= (unsigned long)(unituse[7] * 3 + unituse[6] * 2) + << MMCR1_TTM1SEL_SH; + mmcr1 |= (unsigned long)unituse[9] << MMCR1_TTM2SEL_SH; /* Set TTCxSEL fields. */ if (unitlower & 0xe) @@ -456,7 +461,8 @@ static int p4_compute_mmcr(u64 event[], int n_ev, ttm = unit - 1; /* 2->1, 3->2 */ else ttm = unit >> 2; - mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2*byte); + mmcr1 |= (unsigned long)ttm + << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); } } @@ -519,7 +525,7 @@ static int p4_compute_mmcr(u64 event[], int n_ev, return 0; } -static void p4_disable_pmc(unsigned int pmc, u64 mmcr[]) +static void p4_disable_pmc(unsigned int pmc, unsigned long mmcr[]) { /* * Setting the PMCxSEL field to 0 disables PMC x. @@ -583,16 +589,27 @@ static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { }, }; -struct power_pmu power4_pmu = { - .n_counter = 8, - .max_alternatives = 5, - .add_fields = 0x0000001100005555ull, - .test_adder = 0x0011083300000000ull, - .compute_mmcr = p4_compute_mmcr, - .get_constraint = p4_get_constraint, - .get_alternatives = p4_get_alternatives, - .disable_pmc = p4_disable_pmc, - .n_generic = ARRAY_SIZE(p4_generic_events), - .generic_events = p4_generic_events, - .cache_events = &power4_cache_events, +static struct power_pmu power4_pmu = { + .name = "POWER4/4+", + .n_counter = 8, + .max_alternatives = 5, + .add_fields = 0x0000001100005555ul, + .test_adder = 0x0011083300000000ul, + .compute_mmcr = p4_compute_mmcr, + .get_constraint = p4_get_constraint, + .get_alternatives = p4_get_alternatives, + .disable_pmc = p4_disable_pmc, + .n_generic = ARRAY_SIZE(p4_generic_events), + .generic_events = p4_generic_events, + .cache_events = &power4_cache_events, }; + +static int init_power4_pmu(void) +{ + if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power4")) + return -ENODEV; + + return register_power_pmu(&power4_pmu); +} + +arch_initcall(init_power4_pmu); diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/kernel/power5+-pmu.c index 41e5d2d..f4adca8 100644 --- a/arch/powerpc/kernel/power5+-pmu.c +++ b/arch/powerpc/kernel/power5+-pmu.c @@ -10,7 +10,9 @@ */ #include <linux/kernel.h> #include <linux/perf_counter.h> +#include <linux/string.h> #include <asm/reg.h> +#include <asm/cputable.h> /* * Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3) @@ -126,20 +128,21 @@ static const int grsel_shift[8] = { }; /* Masks and values for using events from the various units */ -static u64 unit_cons[PM_LASTUNIT+1][2] = { - [PM_FPU] = { 0x3200000000ull, 0x0100000000ull }, - [PM_ISU0] = { 0x0200000000ull, 0x0080000000ull }, - [PM_ISU1] = { 0x3200000000ull, 0x3100000000ull }, - [PM_IFU] = { 0x3200000000ull, 0x2100000000ull }, - [PM_IDU] = { 0x0e00000000ull, 0x0040000000ull }, - [PM_GRS] = { 0x0e00000000ull, 0x0c40000000ull }, +static unsigned long unit_cons[PM_LASTUNIT+1][2] = { + [PM_FPU] = { 0x3200000000ul, 0x0100000000ul }, + [PM_ISU0] = { 0x0200000000ul, 0x0080000000ul }, + [PM_ISU1] = { 0x3200000000ul, 0x3100000000ul }, + [PM_IFU] = { 0x3200000000ul, 0x2100000000ul }, + [PM_IDU] = { 0x0e00000000ul, 0x0040000000ul }, + [PM_GRS] = { 0x0e00000000ul, 0x0c40000000ul }, }; -static int power5p_get_constraint(u64 event, u64 *maskp, u64 *valp) +static int power5p_get_constraint(u64 event, unsigned long *maskp, + unsigned long *valp) { int pmc, byte, unit, sh; int bit, fmask; - u64 mask = 0, value = 0; + unsigned long mask = 0, value = 0; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; if (pmc) { @@ -171,17 +174,18 @@ static int power5p_get_constraint(u64 event, u64 *maskp, u64 *valp) bit = event & 7; fmask = (bit == 6)? 7: 3; sh = grsel_shift[bit]; - mask |= (u64)fmask << sh; - value |= (u64)((event >> PM_GRS_SH) & fmask) << sh; + mask |= (unsigned long)fmask << sh; + value |= (unsigned long)((event >> PM_GRS_SH) & fmask) + << sh; } /* Set byte lane select field */ - mask |= 0xfULL << (24 - 4 * byte); - value |= (u64)unit << (24 - 4 * byte); + mask |= 0xfUL << (24 - 4 * byte); + value |= (unsigned long)unit << (24 - 4 * byte); } if (pmc < 5) { /* need a counter from PMC1-4 set */ - mask |= 0x8000000000000ull; - value |= 0x1000000000000ull; + mask |= 0x8000000000000ul; + value |= 0x1000000000000ul; } *maskp = mask; *valp = value; @@ -452,10 +456,10 @@ static int power5p_marked_instr_event(u64 event) } static int power5p_compute_mmcr(u64 event[], int n_ev, - unsigned int hwc[], u64 mmcr[]) + unsigned int hwc[], unsigned long mmcr[]) { - u64 mmcr1 = 0; - u64 mmcra = 0; + unsigned long mmcr1 = 0; + unsigned long mmcra = 0; unsigned int pmc, unit, byte, psel; unsigned int ttm; int i, isbus, bit, grsel; @@ -517,7 +521,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, continue; if (ttmuse++) return -1; - mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH; + mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH; } ttmuse = 0; for (; i <= PM_GRS; ++i) { @@ -525,7 +529,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, continue; if (ttmuse++) return -1; - mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH; + mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH; } if (ttmuse > 1) return -1; @@ -540,10 +544,11 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, unit = PM_ISU0_ALT; } else if (unit == PM_LSU1 + 1) { /* select lower word of LSU1 for this byte */ - mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte); + mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte); } ttm = unit >> 2; - mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); + mmcr1 |= (unsigned long)ttm + << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); } /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ @@ -568,7 +573,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, if (isbus && (byte & 2) && (psel == 8 || psel == 0x10 || psel == 0x28)) /* add events on higher-numbered bus */ - mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc); + mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc); } else { /* Instructions or run cycles on PMC5/6 */ --pmc; @@ -576,7 +581,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, if (isbus && unit == PM_GRS) { bit = psel & 7; grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK; - mmcr1 |= (u64)grsel << grsel_shift[bit]; + mmcr1 |= (unsigned long)grsel << grsel_shift[bit]; } if (power5p_marked_instr_event(event[i])) mmcra |= MMCRA_SAMPLE_ENABLE; @@ -599,7 +604,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, return 0; } -static void power5p_disable_pmc(unsigned int pmc, u64 mmcr[]) +static void power5p_disable_pmc(unsigned int pmc, unsigned long mmcr[]) { if (pmc <= 3) mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc)); @@ -654,18 +659,30 @@ static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { }, }; -struct power_pmu power5p_pmu = { - .n_counter = 6, - .max_alternatives = MAX_ALT, - .add_fields = 0x7000000000055ull, - .test_adder = 0x3000040000000ull, - .compute_mmcr = power5p_compute_mmcr, - .get_constraint = power5p_get_constraint, - .get_alternatives = power5p_get_alternatives, - .disable_pmc = power5p_disable_pmc, - .limited_pmc_event = power5p_limited_pmc_event, - .flags = PPMU_LIMITED_PMC5_6, - .n_generic = ARRAY_SIZE(power5p_generic_events), - .generic_events = power5p_generic_events, - .cache_events = &power5p_cache_events, +static struct power_pmu power5p_pmu = { + .name = "POWER5+/++", + .n_counter = 6, + .max_alternatives = MAX_ALT, + .add_fields = 0x7000000000055ul, + .test_adder = 0x3000040000000ul, + .compute_mmcr = power5p_compute_mmcr, + .get_constraint = power5p_get_constraint, + .get_alternatives = power5p_get_alternatives, + .disable_pmc = power5p_disable_pmc, + .limited_pmc_event = power5p_limited_pmc_event, + .flags = PPMU_LIMITED_PMC5_6, + .n_generic = ARRAY_SIZE(power5p_generic_events), + .generic_events = power5p_generic_events, + .cache_events = &power5p_cache_events, }; + +static int init_power5p_pmu(void) +{ + if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5+") + && strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5++")) + return -ENODEV; + + return register_power_pmu(&power5p_pmu); +} + +arch_initcall(init_power5p_pmu); diff --git a/arch/powerpc/kernel/power5-pmu.c b/arch/powerpc/kernel/power5-pmu.c index 05600b6..29b2c6c 100644 --- a/arch/powerpc/kernel/power5-pmu.c +++ b/arch/powerpc/kernel/power5-pmu.c @@ -10,7 +10,9 @@ */ #include <linux/kernel.h> #include <linux/perf_counter.h> +#include <linux/string.h> #include <asm/reg.h> +#include <asm/cputable.h> /* * Bits in event code for POWER5 (not POWER5++) @@ -130,20 +132,21 @@ static const int grsel_shift[8] = { }; /* Masks and values for using events from the various units */ -static u64 unit_cons[PM_LASTUNIT+1][2] = { - [PM_FPU] = { 0xc0002000000000ull, 0x00001000000000ull }, - [PM_ISU0] = { 0x00002000000000ull, 0x00000800000000ull }, - [PM_ISU1] = { 0xc0002000000000ull, 0xc0001000000000ull }, - [PM_IFU] = { 0xc0002000000000ull, 0x80001000000000ull }, - [PM_IDU] = { 0x30002000000000ull, 0x00000400000000ull }, - [PM_GRS] = { 0x30002000000000ull, 0x30000400000000ull }, +static unsigned long unit_cons[PM_LASTUNIT+1][2] = { + [PM_FPU] = { 0xc0002000000000ul, 0x00001000000000ul }, + [PM_ISU0] = { 0x00002000000000ul, 0x00000800000000ul }, + [PM_ISU1] = { 0xc0002000000000ul, 0xc0001000000000ul }, + [PM_IFU] = { 0xc0002000000000ul, 0x80001000000000ul }, + [PM_IDU] = { 0x30002000000000ul, 0x00000400000000ul }, + [PM_GRS] = { 0x30002000000000ul, 0x30000400000000ul }, }; -static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp) +static int power5_get_constraint(u64 event, unsigned long *maskp, + unsigned long *valp) { int pmc, byte, unit, sh; int bit, fmask; - u64 mask = 0, value = 0; + unsigned long mask = 0, value = 0; int grp = -1; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; @@ -178,8 +181,9 @@ static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp) bit = event & 7; fmask = (bit == 6)? 7: 3; sh = grsel_shift[bit]; - mask |= (u64)fmask << sh; - value |= (u64)((event >> PM_GRS_SH) & fmask) << sh; + mask |= (unsigned long)fmask << sh; + value |= (unsigned long)((event >> PM_GRS_SH) & fmask) + << sh; } /* * Bus events on bytes 0 and 2 can be counted @@ -188,22 +192,22 @@ static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp) if (!pmc) grp = byte & 1; /* Set byte lane select field */ - mask |= 0xfULL << (24 - 4 * byte); - value |= (u64)unit << (24 - 4 * byte); + mask |= 0xfUL << (24 - 4 * byte); + value |= (unsigned long)unit << (24 - 4 * byte); } if (grp == 0) { /* increment PMC1/2 field */ - mask |= 0x200000000ull; - value |= 0x080000000ull; + mask |= 0x200000000ul; + value |= 0x080000000ul; } else if (grp == 1) { /* increment PMC3/4 field */ - mask |= 0x40000000ull; - value |= 0x10000000ull; + mask |= 0x40000000ul; + value |= 0x10000000ul; } if (pmc < 5) { /* need a counter from PMC1-4 set */ - mask |= 0x8000000000000ull; - value |= 0x1000000000000ull; + mask |= 0x8000000000000ul; + value |= 0x1000000000000ul; } *maskp = mask; *valp = value; @@ -383,10 +387,10 @@ static int power5_marked_instr_event(u64 event) } static int power5_compute_mmcr(u64 event[], int n_ev, - unsigned int hwc[], u64 mmcr[]) + unsigned int hwc[], unsigned long mmcr[]) { - u64 mmcr1 = 0; - u64 mmcra = 0; + unsigned long mmcr1 = 0; + unsigned long mmcra = 0; unsigned int pmc, unit, byte, psel; unsigned int ttm, grp; int i, isbus, bit, grsel; @@ -457,7 +461,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, continue; if (ttmuse++) return -1; - mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH; + mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH; } ttmuse = 0; for (; i <= PM_GRS; ++i) { @@ -465,7 +469,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, continue; if (ttmuse++) return -1; - mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH; + mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH; } if (ttmuse > 1) return -1; @@ -480,10 +484,11 @@ static int power5_compute_mmcr(u64 event[], int n_ev, unit = PM_ISU0_ALT; } else if (unit == PM_LSU1 + 1) { /* select lower word of LSU1 for this byte */ - mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte); + mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte); } ttm = unit >> 2; - mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); + mmcr1 |= (unsigned long)ttm + << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); } /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ @@ -513,7 +518,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, --pmc; if ((psel == 8 || psel == 0x10) && isbus && (byte & 2)) /* add events on higher-numbered bus */ - mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc); + mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc); } else { /* Instructions or run cycles on PMC5/6 */ --pmc; @@ -521,7 +526,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, if (isbus && unit == PM_GRS) { bit = psel & 7; grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK; - mmcr1 |= (u64)grsel << grsel_shift[bit]; + mmcr1 |= (unsigned long)grsel << grsel_shift[bit]; } if (power5_marked_instr_event(event[i])) mmcra |= MMCRA_SAMPLE_ENABLE; @@ -541,7 +546,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, return 0; } -static void power5_disable_pmc(unsigned int pmc, u64 mmcr[]) +static void power5_disable_pmc(unsigned int pmc, unsigned long mmcr[]) { if (pmc <= 3) mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc)); @@ -596,16 +601,27 @@ static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { }, }; -struct power_pmu power5_pmu = { - .n_counter = 6, - .max_alternatives = MAX_ALT, - .add_fields = 0x7000090000555ull, - .test_adder = 0x3000490000000ull, - .compute_mmcr = power5_compute_mmcr, - .get_constraint = power5_get_constraint, - .get_alternatives = power5_get_alternatives, - .disable_pmc = power5_disable_pmc, - .n_generic = ARRAY_SIZE(power5_generic_events), - .generic_events = power5_generic_events, - .cache_events = &power5_cache_events, +static struct power_pmu power5_pmu = { + .name = "POWER5", + .n_counter = 6, + .max_alternatives = MAX_ALT, + .add_fields = 0x7000090000555ul, + .test_adder = 0x3000490000000ul, + .compute_mmcr = power5_compute_mmcr, + .get_constraint = power5_get_constraint, + .get_alternatives = power5_get_alternatives, + .disable_pmc = power5_disable_pmc, + .n_generic = ARRAY_SIZE(power5_generic_events), + .generic_events = power5_generic_events, + .cache_events = &power5_cache_events, }; + +static int init_power5_pmu(void) +{ + if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5")) + return -ENODEV; + + return register_power_pmu(&power5_pmu); +} + +arch_initcall(init_power5_pmu); diff --git a/arch/powerpc/kernel/power6-pmu.c b/arch/powerpc/kernel/power6-pmu.c index 46f74be..09ae5bf 100644 --- a/arch/powerpc/kernel/power6-pmu.c +++ b/arch/powerpc/kernel/power6-pmu.c @@ -10,7 +10,9 @@ */ #include <linux/kernel.h> #include <linux/perf_counter.h> +#include <linux/string.h> #include <asm/reg.h> +#include <asm/cputable.h> /* * Bits in event code for POWER6 @@ -41,9 +43,9 @@ #define MMCR1_NESTSEL_SH 45 #define MMCR1_NESTSEL_MSK 0x7 #define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK) -#define MMCR1_PMC1_LLA ((u64)1 << 44) -#define MMCR1_PMC1_LLA_VALUE ((u64)1 << 39) -#define MMCR1_PMC1_ADDR_SEL ((u64)1 << 35) +#define MMCR1_PMC1_LLA (1ul << 44) +#define MMCR1_PMC1_LLA_VALUE (1ul << 39) +#define MMCR1_PMC1_ADDR_SEL (1ul << 35) #define MMCR1_PMC1SEL_SH 24 #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8) #define MMCR1_PMCSEL_MSK 0xff @@ -173,10 +175,10 @@ static int power6_marked_instr_event(u64 event) * Assign PMC numbers and compute MMCR1 value for a set of events */ static int p6_compute_mmcr(u64 event[], int n_ev, - unsigned int hwc[], u64 mmcr[]) + unsigned int hwc[], unsigned long mmcr[]) { - u64 mmcr1 = 0; - u64 mmcra = 0; + unsigned long mmcr1 = 0; + unsigned long mmcra = 0; int i; unsigned int pmc, ev, b, u, s, psel; unsigned int ttmset = 0; @@ -215,7 +217,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev, /* check for conflict on this byte of event bus */ if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u) return -1; - mmcr1 |= (u64)u << MMCR1_TTMSEL_SH(b); + mmcr1 |= (unsigned long)u << MMCR1_TTMSEL_SH(b); ttmset |= 1 << b; if (u == 5) { /* Nest events have a further mux */ @@ -224,7 +226,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev, MMCR1_NESTSEL(mmcr1) != s) return -1; ttmset |= 0x10; - mmcr1 |= (u64)s << MMCR1_NESTSEL_SH; + mmcr1 |= (unsigned long)s << MMCR1_NESTSEL_SH; } if (0x30 <= psel && psel <= 0x3d) { /* these need the PMCx_ADDR_SEL bits */ @@ -243,7 +245,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev, if (power6_marked_instr_event(event[i])) mmcra |= MMCRA_SAMPLE_ENABLE; if (pmc < 4) - mmcr1 |= (u64)psel << MMCR1_PMCSEL_SH(pmc); + mmcr1 |= (unsigned long)psel << MMCR1_PMCSEL_SH(pmc); } mmcr[0] = 0; if (pmc_inuse & 1) @@ -265,10 +267,11 @@ static int p6_compute_mmcr(u64 event[], int n_ev, * 20-23, 24-27, 28-31 ditto for bytes 1, 2, 3 * 32-34 select field: nest (subunit) event selector */ -static int p6_get_constraint(u64 event, u64 *maskp, u64 *valp) +static int p6_get_constraint(u64 event, unsigned long *maskp, + unsigned long *valp) { int pmc, byte, sh, subunit; - u64 mask = 0, value = 0; + unsigned long mask = 0, value = 0; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; if (pmc) { @@ -282,11 +285,11 @@ static int p6_get_constraint(u64 event, u64 *maskp, u64 *valp) byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; sh = byte * 4 + (16 - PM_UNIT_SH); mask |= PM_UNIT_MSKS << sh; - value |= (u64)(event & PM_UNIT_MSKS) << sh; + value |= (unsigned long)(event & PM_UNIT_MSKS) << sh; if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) { subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK; - mask |= (u64)PM_SUBUNIT_MSK << 32; - value |= (u64)subunit << 32; + mask |= (unsigned long)PM_SUBUNIT_MSK << 32; + value |= (unsigned long)subunit << 32; } } if (pmc <= 4) { @@ -458,7 +461,7 @@ static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[]) return nalt; } -static void p6_disable_pmc(unsigned int pmc, u64 mmcr[]) +static void p6_disable_pmc(unsigned int pmc, unsigned long mmcr[]) { /* Set PMCxSEL to 0 to disable PMCx */ if (pmc <= 3) @@ -515,18 +518,29 @@ static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { }, }; -struct power_pmu power6_pmu = { - .n_counter = 6, - .max_alternatives = MAX_ALT, - .add_fields = 0x1555, - .test_adder = 0x3000, - .compute_mmcr = p6_compute_mmcr, - .get_constraint = p6_get_constraint, - .get_alternatives = p6_get_alternatives, - .disable_pmc = p6_disable_pmc, - .limited_pmc_event = p6_limited_pmc_event, - .flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR, - .n_generic = ARRAY_SIZE(power6_generic_events), - .generic_events = power6_generic_events, - .cache_events = &power6_cache_events, +static struct power_pmu power6_pmu = { + .name = "POWER6", + .n_counter = 6, + .max_alternatives = MAX_ALT, + .add_fields = 0x1555, + .test_adder = 0x3000, + .compute_mmcr = p6_compute_mmcr, + .get_constraint = p6_get_constraint, + .get_alternatives = p6_get_alternatives, + .disable_pmc = p6_disable_pmc, + .limited_pmc_event = p6_limited_pmc_event, + .flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR, + .n_generic = ARRAY_SIZE(power6_generic_events), + .generic_events = power6_generic_events, + .cache_events = &power6_cache_events, }; + +static int init_power6_pmu(void) +{ + if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6")) + return -ENODEV; + + return register_power_pmu(&power6_pmu); +} + +arch_initcall(init_power6_pmu); diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c index b72e7a1..5d755ef 100644 --- a/arch/powerpc/kernel/power7-pmu.c +++ b/arch/powerpc/kernel/power7-pmu.c @@ -10,7 +10,9 @@ */ #include <linux/kernel.h> #include <linux/perf_counter.h> +#include <linux/string.h> #include <asm/reg.h> +#include <asm/cputable.h> /* * Bits in event code for POWER7 @@ -71,10 +73,11 @@ * 0-9: Count of events needing PMC1..PMC5 */ -static int power7_get_constraint(u64 event, u64 *maskp, u64 *valp) +static int power7_get_constraint(u64 event, unsigned long *maskp, + unsigned long *valp) { int pmc, sh; - u64 mask = 0, value = 0; + unsigned long mask = 0, value = 0; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; if (pmc) { @@ -224,10 +227,10 @@ static int power7_marked_instr_event(u64 event) } static int power7_compute_mmcr(u64 event[], int n_ev, - unsigned int hwc[], u64 mmcr[]) + unsigned int hwc[], unsigned long mmcr[]) { - u64 mmcr1 = 0; - u64 mmcra = 0; + unsigned long mmcr1 = 0; + unsigned long mmcra = 0; unsigned int pmc, unit, combine, l2sel, psel; unsigned int pmc_inuse = 0; int i; @@ -265,11 +268,14 @@ static int power7_compute_mmcr(u64 event[], int n_ev, --pmc; } if (pmc <= 3) { - mmcr1 |= (u64) unit << (MMCR1_TTM0SEL_SH - 4 * pmc); - mmcr1 |= (u64) combine << (MMCR1_PMC1_COMBINE_SH - pmc); + mmcr1 |= (unsigned long) unit + << (MMCR1_TTM0SEL_SH - 4 * pmc); + mmcr1 |= (unsigned long) combine + << (MMCR1_PMC1_COMBINE_SH - pmc); mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc); if (unit == 6) /* L2 events */ - mmcr1 |= (u64) l2sel << MMCR1_L2SEL_SH; + mmcr1 |= (unsigned long) l2sel + << MMCR1_L2SEL_SH; } if (power7_marked_instr_event(event[i])) mmcra |= MMCRA_SAMPLE_ENABLE; @@ -287,10 +293,10 @@ static int power7_compute_mmcr(u64 event[], int n_ev, return 0; } -static void power7_disable_pmc(unsigned int pmc, u64 mmcr[]) +static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) { if (pmc <= 3) - mmcr[1] &= ~(0xffULL << MMCR1_PMCSEL_SH(pmc)); + mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc)); } static int power7_generic_events[] = { @@ -342,16 +348,27 @@ static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { }, }; -struct power_pmu power7_pmu = { - .n_counter = 6, - .max_alternatives = MAX_ALT + 1, - .add_fields = 0x1555ull, - .test_adder = 0x3000ull, - .compute_mmcr = power7_compute_mmcr, - .get_constraint = power7_get_constraint, - .get_alternatives = power7_get_alternatives, - .disable_pmc = power7_disable_pmc, - .n_generic = ARRAY_SIZE(power7_generic_events), - .generic_events = power7_generic_events, - .cache_events = &power7_cache_events, +static struct power_pmu power7_pmu = { + .name = "POWER7", + .n_counter = 6, + .max_alternatives = MAX_ALT + 1, + .add_fields = 0x1555ul, + .test_adder = 0x3000ul, + .compute_mmcr = power7_compute_mmcr, + .get_constraint = power7_get_constraint, + .get_alternatives = power7_get_alternatives, + .disable_pmc = power7_disable_pmc, + .n_generic = ARRAY_SIZE(power7_generic_events), + .generic_events = power7_generic_events, + .cache_events = &power7_cache_events, }; + +static int init_power7_pmu(void) +{ + if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7")) + return -ENODEV; + + return register_power_pmu(&power7_pmu); +} + +arch_initcall(init_power7_pmu); diff --git a/arch/powerpc/kernel/ppc970-pmu.c b/arch/powerpc/kernel/ppc970-pmu.c index ba0a357..6637c87f 100644 --- a/arch/powerpc/kernel/ppc970-pmu.c +++ b/arch/powerpc/kernel/ppc970-pmu.c @@ -10,7 +10,9 @@ */ #include <linux/string.h> #include <linux/perf_counter.h> +#include <linux/string.h> #include <asm/reg.h> +#include <asm/cputable.h> /* * Bits in event code for PPC970 @@ -183,7 +185,7 @@ static int p970_marked_instr_event(u64 event) } /* Masks and values for using events from the various units */ -static u64 unit_cons[PM_LASTUNIT+1][2] = { +static unsigned long unit_cons[PM_LASTUNIT+1][2] = { [PM_FPU] = { 0xc80000000000ull, 0x040000000000ull }, [PM_VPU] = { 0xc80000000000ull, 0xc40000000000ull }, [PM_ISU] = { 0x080000000000ull, 0x020000000000ull }, @@ -192,10 +194,11 @@ static u64 unit_cons[PM_LASTUNIT+1][2] = { [PM_STS] = { 0x380000000000ull, 0x310000000000ull }, }; -static int p970_get_constraint(u64 event, u64 *maskp, u64 *valp) +static int p970_get_constraint(u64 event, unsigned long *maskp, + unsigned long *valp) { int pmc, byte, unit, sh, spcsel; - u64 mask = 0, value = 0; + unsigned long mask = 0, value = 0; int grp = -1; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; @@ -222,7 +225,7 @@ static int p970_get_constraint(u64 event, u64 *maskp, u64 *valp) grp = byte & 1; /* Set byte lane select field */ mask |= 0xfULL << (28 - 4 * byte); - value |= (u64)unit << (28 - 4 * byte); + value |= (unsigned long)unit << (28 - 4 * byte); } if (grp == 0) { /* increment PMC1/2/5/6 field */ @@ -236,7 +239,7 @@ static int p970_get_constraint(u64 event, u64 *maskp, u64 *valp) spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK; if (spcsel) { mask |= 3ull << 48; - value |= (u64)spcsel << 48; + value |= (unsigned long)spcsel << 48; } *maskp = mask; *valp = value; @@ -257,9 +260,9 @@ static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[]) } static int p970_compute_mmcr(u64 event[], int n_ev, - unsigned int hwc[], u64 mmcr[]) + unsigned int hwc[], unsigned long mmcr[]) { - u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0; + unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0; unsigned int pmc, unit, byte, psel; unsigned int ttm, grp; unsigned int pmc_inuse = 0; @@ -320,7 +323,7 @@ static int p970_compute_mmcr(u64 event[], int n_ev, continue; ttm = unitmap[i]; ++ttmuse[(ttm >> 2) & 1]; - mmcr1 |= (u64)(ttm & ~4) << MMCR1_TTM1SEL_SH; + mmcr1 |= (unsigned long)(ttm & ~4) << MMCR1_TTM1SEL_SH; } /* Check only one unit per TTMx */ if (ttmuse[0] > 1 || ttmuse[1] > 1) @@ -340,7 +343,8 @@ static int p970_compute_mmcr(u64 event[], int n_ev, if (unit == PM_LSU1L && byte >= 2) mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte); } - mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); + mmcr1 |= (unsigned long)ttm + << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); } /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ @@ -386,7 +390,8 @@ static int p970_compute_mmcr(u64 event[], int n_ev, for (pmc = 0; pmc < 2; ++pmc) mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc); for (; pmc < 8; ++pmc) - mmcr1 |= (u64)pmcsel[pmc] << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2)); + mmcr1 |= (unsigned long)pmcsel[pmc] + << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2)); if (pmc_inuse & 1) mmcr0 |= MMCR0_PMC1CE; if (pmc_inuse & 0xfe) @@ -401,7 +406,7 @@ static int p970_compute_mmcr(u64 event[], int n_ev, return 0; } -static void p970_disable_pmc(unsigned int pmc, u64 mmcr[]) +static void p970_disable_pmc(unsigned int pmc, unsigned long mmcr[]) { int shift, i; @@ -467,16 +472,28 @@ static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { }, }; -struct power_pmu ppc970_pmu = { - .n_counter = 8, - .max_alternatives = 2, - .add_fields = 0x001100005555ull, - .test_adder = 0x013300000000ull, - .compute_mmcr = p970_compute_mmcr, - .get_constraint = p970_get_constraint, - .get_alternatives = p970_get_alternatives, - .disable_pmc = p970_disable_pmc, - .n_generic = ARRAY_SIZE(ppc970_generic_events), - .generic_events = ppc970_generic_events, - .cache_events = &ppc970_cache_events, +static struct power_pmu ppc970_pmu = { + .name = "PPC970/FX/MP", + .n_counter = 8, + .max_alternatives = 2, + .add_fields = 0x001100005555ull, + .test_adder = 0x013300000000ull, + .compute_mmcr = p970_compute_mmcr, + .get_constraint = p970_get_constraint, + .get_alternatives = p970_get_alternatives, + .disable_pmc = p970_disable_pmc, + .n_generic = ARRAY_SIZE(ppc970_generic_events), + .generic_events = ppc970_generic_events, + .cache_events = &ppc970_cache_events, }; + +static int init_ppc970_pmu(void) +{ + if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970") + && strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970MP")) + return -ENODEV; + + return register_power_pmu(&ppc970_pmu); +} + +arch_initcall(init_ppc970_pmu); diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 3e7135bb..892a9f2 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -528,7 +528,7 @@ void show_regs(struct pt_regs * regs) for (i = 0; i < 32; i++) { if ((i % REGS_PER_LINE) == 0) - printk("\n" KERN_INFO "GPR%02d: ", i); + printk("\nGPR%02d: ", i); printk(REG " ", regs->gpr[i]); if (i == LAST_VOLATILE && !FULL_REGS(regs)) break; diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c index ee4c760..c434823 100644 --- a/arch/powerpc/kernel/rtas.c +++ b/arch/powerpc/kernel/rtas.c @@ -38,9 +38,10 @@ #include <asm/syscalls.h> #include <asm/smp.h> #include <asm/atomic.h> +#include <asm/time.h> struct rtas_t rtas = { - .lock = SPIN_LOCK_UNLOCKED + .lock = __RAW_SPIN_LOCK_UNLOCKED }; EXPORT_SYMBOL(rtas); @@ -67,6 +68,28 @@ unsigned long rtas_rmo_buf; void (*rtas_flash_term_hook)(int); EXPORT_SYMBOL(rtas_flash_term_hook); +/* RTAS use home made raw locking instead of spin_lock_irqsave + * because those can be called from within really nasty contexts + * such as having the timebase stopped which would lockup with + * normal locks and spinlock debugging enabled + */ +static unsigned long lock_rtas(void) +{ + unsigned long flags; + + local_irq_save(flags); + preempt_disable(); + __raw_spin_lock_flags(&rtas.lock, flags); + return flags; +} + +static void unlock_rtas(unsigned long flags) +{ + __raw_spin_unlock(&rtas.lock); + local_irq_restore(flags); + preempt_enable(); +} + /* * call_rtas_display_status and call_rtas_display_status_delay * are designed only for very early low-level debugging, which @@ -79,7 +102,7 @@ static void call_rtas_display_status(char c) if (!rtas.base) return; - spin_lock_irqsave(&rtas.lock, s); + s = lock_rtas(); args->token = 10; args->nargs = 1; @@ -89,7 +112,7 @@ static void call_rtas_display_status(char c) enter_rtas(__pa(args)); - spin_unlock_irqrestore(&rtas.lock, s); + unlock_rtas(s); } static void call_rtas_display_status_delay(char c) @@ -411,8 +434,7 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...) if (!rtas.entry || token == RTAS_UNKNOWN_SERVICE) return -1; - /* Gotta do something different here, use global lock for now... */ - spin_lock_irqsave(&rtas.lock, s); + s = lock_rtas(); rtas_args = &rtas.args; rtas_args->token = token; @@ -439,8 +461,7 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...) outputs[i] = rtas_args->rets[i+1]; ret = (nret > 0)? rtas_args->rets[0]: 0; - /* Gotta do something different here, use global lock for now... */ - spin_unlock_irqrestore(&rtas.lock, s); + unlock_rtas(s); if (buff_copy) { log_error(buff_copy, ERR_TYPE_RTAS_LOG, 0); @@ -837,7 +858,7 @@ asmlinkage int ppc_rtas(struct rtas_args __user *uargs) buff_copy = get_errorlog_buffer(); - spin_lock_irqsave(&rtas.lock, flags); + flags = lock_rtas(); rtas.args = args; enter_rtas(__pa(&rtas.args)); @@ -848,7 +869,7 @@ asmlinkage int ppc_rtas(struct rtas_args __user *uargs) if (args.rets[0] == -1) errbuf = __fetch_rtas_last_error(buff_copy); - spin_unlock_irqrestore(&rtas.lock, flags); + unlock_rtas(flags); if (buff_copy) { if (errbuf) @@ -951,3 +972,33 @@ int __init early_init_dt_scan_rtas(unsigned long node, /* break now */ return 1; } + +static raw_spinlock_t timebase_lock; +static u64 timebase = 0; + +void __cpuinit rtas_give_timebase(void) +{ + unsigned long flags; + + local_irq_save(flags); + hard_irq_disable(); + __raw_spin_lock(&timebase_lock); + rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); + timebase = get_tb(); + __raw_spin_unlock(&timebase_lock); + + while (timebase) + barrier(); + rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); + local_irq_restore(flags); +} + +void __cpuinit rtas_take_timebase(void) +{ + while (!timebase) + barrier(); + __raw_spin_lock(&timebase_lock); + set_tb(timebase >> 32, timebase & 0xffffffff); + timebase = 0; + __raw_spin_unlock(&timebase_lock); +} diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c index 1d15424..e1e3059 100644 --- a/arch/powerpc/kernel/setup_32.c +++ b/arch/powerpc/kernel/setup_32.c @@ -119,6 +119,8 @@ notrace unsigned long __init early_init(unsigned long dt_ptr) */ notrace void __init machine_init(unsigned long dt_ptr) { + lockdep_init(); + /* Enable early debugging if any specified (see udbg.h) */ udbg_early_init(); diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 65484b2..0b47de0 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -68,7 +68,8 @@ EXPORT_PER_CPU_SYMBOL(cpu_core_map); /* SMP operations for this machine */ struct smp_ops_t *smp_ops; -static volatile unsigned int cpu_callin_map[NR_CPUS]; +/* Can't be static due to PowerMac hackery */ +volatile unsigned int cpu_callin_map[NR_CPUS]; int smt_enabled_at_boot = 1; diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index 15391c2..eae4511 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c @@ -53,6 +53,7 @@ #include <linux/posix-timers.h> #include <linux/irq.h> #include <linux/delay.h> +#include <linux/perf_counter.h> #include <asm/io.h> #include <asm/processor.h> @@ -525,6 +526,26 @@ void __init iSeries_time_init_early(void) } #endif /* CONFIG_PPC_ISERIES */ +#if defined(CONFIG_PERF_COUNTERS) && defined(CONFIG_PPC32) +DEFINE_PER_CPU(u8, perf_counter_pending); + +void set_perf_counter_pending(void) +{ + get_cpu_var(perf_counter_pending) = 1; + set_dec(1); + put_cpu_var(perf_counter_pending); +} + +#define test_perf_counter_pending() __get_cpu_var(perf_counter_pending) +#define clear_perf_counter_pending() __get_cpu_var(perf_counter_pending) = 0 + +#else /* CONFIG_PERF_COUNTERS && CONFIG_PPC32 */ + +#define test_perf_counter_pending() 0 +#define clear_perf_counter_pending() + +#endif /* CONFIG_PERF_COUNTERS && CONFIG_PPC32 */ + /* * For iSeries shared processors, we have to let the hypervisor * set the hardware decrementer. We set a virtual decrementer @@ -551,6 +572,10 @@ void timer_interrupt(struct pt_regs * regs) set_dec(DECREMENTER_MAX); #ifdef CONFIG_PPC32 + if (test_perf_counter_pending()) { + clear_perf_counter_pending(); + perf_counter_do_pending(); + } if (atomic_read(&ppc_n_lost_interrupts) != 0) do_IRQ(regs); #endif diff --git a/arch/powerpc/kernel/udbg_16550.c b/arch/powerpc/kernel/udbg_16550.c index 0362a89..acb74a1 100644 --- a/arch/powerpc/kernel/udbg_16550.c +++ b/arch/powerpc/kernel/udbg_16550.c @@ -219,7 +219,7 @@ void udbg_init_pas_realmode(void) #ifdef CONFIG_PPC_EARLY_DEBUG_44x #include <platforms/44x/44x.h> -static int udbg_44x_as1_flush(void) +static void udbg_44x_as1_flush(void) { if (udbg_comport) { while ((as1_readb(&udbg_comport->lsr) & LSR_THRE) == 0) diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile index 4b2df66..459c7ee 100644 --- a/arch/powerpc/kvm/Makefile +++ b/arch/powerpc/kvm/Makefile @@ -2,6 +2,8 @@ # Makefile for Kernel-based Virtual Machine module # +subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror + EXTRA_CFLAGS += -Ivirt/kvm -Iarch/powerpc/kvm common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o) diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 29b742b..3040dac 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -2,6 +2,8 @@ # Makefile for ppc-specific library files.. # +subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror + ifeq ($(CONFIG_PPC64),y) EXTRA_CFLAGS += -mno-minimal-toc endif diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile index c4bcf07..3e68363 100644 --- a/arch/powerpc/mm/Makefile +++ b/arch/powerpc/mm/Makefile @@ -2,6 +2,8 @@ # Makefile for the linux ppc-specific parts of the memory manager. # +subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror + ifeq ($(CONFIG_PPC64),y) EXTRA_CFLAGS += -mno-minimal-toc endif @@ -28,3 +30,4 @@ obj-$(CONFIG_PPC_MM_SLICES) += slice.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o obj-$(CONFIG_PPC_SUBPAGE_PROT) += subpage-prot.o obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o +obj-$(CONFIG_HIGHMEM) += highmem.o diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c index 5beffc8..830bef0 100644 --- a/arch/powerpc/mm/fault.c +++ b/arch/powerpc/mm/fault.c @@ -302,7 +302,7 @@ good_area: * the fault. */ survive: - ret = handle_mm_fault(mm, vma, address, is_write); + ret = handle_mm_fault(mm, vma, address, is_write ? FAULT_FLAG_WRITE : 0); if (unlikely(ret & VM_FAULT_ERROR)) { if (ret & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/powerpc/mm/highmem.c b/arch/powerpc/mm/highmem.c new file mode 100644 index 0000000..c2186c7 --- /dev/null +++ b/arch/powerpc/mm/highmem.c @@ -0,0 +1,77 @@ +/* + * highmem.c: virtual kernel memory mappings for high memory + * + * PowerPC version, stolen from the i386 version. + * + * Used in CONFIG_HIGHMEM systems for memory pages which + * are not addressable by direct kernel virtual addresses. + * + * Copyright (C) 1999 Gerhard Wichert, Siemens AG + * Gerhard.Wichert@pdb.siemens.de + * + * + * Redesigned the x86 32-bit VM architecture to deal with + * up to 16 Terrabyte physical memory. With current x86 CPUs + * we now support up to 64 Gigabytes physical RAM. + * + * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> + * + * Reworked for PowerPC by various contributors. Moved from + * highmem.h by Benjamin Herrenschmidt (c) 2009 IBM Corp. + */ + +#include <linux/highmem.h> +#include <linux/module.h> + +/* + * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap + * gives a more generic (and caching) interface. But kmap_atomic can + * be used in IRQ contexts, so in some (very limited) cases we need + * it. + */ +void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot) +{ + unsigned int idx; + unsigned long vaddr; + + /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ + pagefault_disable(); + if (!PageHighMem(page)) + return page_address(page); + + debug_kmap_atomic(type); + idx = type + KM_TYPE_NR*smp_processor_id(); + vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); +#ifdef CONFIG_DEBUG_HIGHMEM + BUG_ON(!pte_none(*(kmap_pte-idx))); +#endif + __set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot), 1); + local_flush_tlb_page(NULL, vaddr); + + return (void*) vaddr; +} +EXPORT_SYMBOL(kmap_atomic_prot); + +void kunmap_atomic(void *kvaddr, enum km_type type) +{ +#ifdef CONFIG_DEBUG_HIGHMEM + unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; + enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id(); + + if (vaddr < __fix_to_virt(FIX_KMAP_END)) { + pagefault_enable(); + return; + } + + BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)); + + /* + * force other mappings to Oops if they'll try to access + * this pte without first remap it + */ + pte_clear(&init_mm, vaddr, kmap_pte-idx); + local_flush_tlb_page(NULL, vaddr); +#endif + pagefault_enable(); +} +EXPORT_SYMBOL(kunmap_atomic); diff --git a/arch/powerpc/oprofile/Makefile b/arch/powerpc/oprofile/Makefile index 2ef6b0d..73e1c2c 100644 --- a/arch/powerpc/oprofile/Makefile +++ b/arch/powerpc/oprofile/Makefile @@ -1,3 +1,5 @@ +subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror + ifeq ($(CONFIG_PPC64),y) EXTRA_CFLAGS += -mno-minimal-toc endif diff --git a/arch/powerpc/platforms/44x/warp.c b/arch/powerpc/platforms/44x/warp.c index c511880..0362c88 100644 --- a/arch/powerpc/platforms/44x/warp.c +++ b/arch/powerpc/platforms/44x/warp.c @@ -16,6 +16,7 @@ #include <linux/interrupt.h> #include <linux/delay.h> #include <linux/of_gpio.h> +#include <linux/of_i2c.h> #include <asm/machdep.h> #include <asm/prom.h> @@ -43,7 +44,13 @@ static int __init warp_probe(void) { unsigned long root = of_get_flat_dt_root(); - return of_flat_dt_is_compatible(root, "pika,warp"); + if (!of_flat_dt_is_compatible(root, "pika,warp")) + return 0; + + /* For __dma_alloc_coherent */ + ISA_DMA_THRESHOLD = ~0L; + + return 1; } define_machine(warp) { @@ -59,7 +66,6 @@ define_machine(warp) { static u32 post_info; -/* I am not sure this is the best place for this... */ static int __init warp_post_info(void) { struct device_node *np; @@ -188,9 +194,9 @@ static int pika_setup_leds(void) return 0; } -static void pika_setup_critical_temp(struct i2c_client *client) +static void pika_setup_critical_temp(struct device_node *np, + struct i2c_client *client) { - struct device_node *np; int irq, rc; /* Do this before enabling critical temp interrupt since we @@ -202,14 +208,7 @@ static void pika_setup_critical_temp(struct i2c_client *client) i2c_smbus_write_byte_data(client, 2, 65); /* Thigh */ i2c_smbus_write_byte_data(client, 3, 0); /* Tlow */ - np = of_find_compatible_node(NULL, NULL, "adi,ad7414"); - if (np == NULL) { - printk(KERN_ERR __FILE__ ": Unable to find ad7414\n"); - return; - } - irq = irq_of_parse_and_map(np, 0); - of_node_put(np); if (irq == NO_IRQ) { printk(KERN_ERR __FILE__ ": Unable to get ad7414 irq\n"); return; @@ -238,32 +237,24 @@ static inline void pika_dtm_check_fan(void __iomem *fpga) static int pika_dtm_thread(void __iomem *fpga) { - struct i2c_adapter *adap; + struct device_node *np; struct i2c_client *client; - /* We loop in case either driver was compiled as a module and - * has not been insmoded yet. - */ - while (!(adap = i2c_get_adapter(0))) { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(HZ); - } - - while (1) { - list_for_each_entry(client, &adap->clients, list) - if (client->addr == 0x4a) - goto found_it; + np = of_find_compatible_node(NULL, NULL, "adi,ad7414"); + if (np == NULL) + return -ENOENT; - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(HZ); + client = of_find_i2c_device_by_node(np); + if (client == NULL) { + of_node_put(np); + return -ENOENT; } -found_it: - pika_setup_critical_temp(client); + pika_setup_critical_temp(np, client); - i2c_put_adapter(adap); + of_node_put(np); - printk(KERN_INFO "PIKA DTM thread running.\n"); + printk(KERN_INFO "Warp DTM thread running.\n"); while (!kthread_should_stop()) { int val; @@ -285,7 +276,6 @@ found_it: return 0; } - static int __init pika_dtm_start(void) { struct task_struct *dtm_thread; diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c index 1bcff94..84544d0 100644 --- a/arch/powerpc/platforms/512x/clock.c +++ b/arch/powerpc/platforms/512x/clock.c @@ -24,7 +24,7 @@ #include <linux/io.h> #include <linux/of_platform.h> -#include <asm/mpc512x.h> +#include <asm/mpc5xxx.h> #include <asm/clk_interface.h> #undef CLK_DEBUG @@ -83,13 +83,13 @@ static void dump_clocks(void) mutex_lock(&clocks_mutex); printk(KERN_INFO "CLOCKS:\n"); list_for_each_entry(p, &clocks, node) { - printk(KERN_INFO " %s %ld", p->name, p->rate); + pr_info(" %s=%ld", p->name, p->rate); if (p->parent) - printk(KERN_INFO " %s %ld", p->parent->name, + pr_cont(" %s=%ld", p->parent->name, p->parent->rate); if (p->flags & CLK_HAS_CTRL) - printk(KERN_INFO " reg/bit %d/%d", p->reg, p->bit); - printk("\n"); + pr_cont(" reg/bit=%d/%d", p->reg, p->bit); + pr_cont("\n"); } mutex_unlock(&clocks_mutex); } diff --git a/arch/powerpc/platforms/512x/mpc512x.h b/arch/powerpc/platforms/512x/mpc512x.h index 9c03693..22a5352 100644 --- a/arch/powerpc/platforms/512x/mpc512x.h +++ b/arch/powerpc/platforms/512x/mpc512x.h @@ -11,7 +11,6 @@ #ifndef __MPC512X_H__ #define __MPC512X_H__ -extern unsigned long mpc512x_find_ips_freq(struct device_node *node); extern void __init mpc512x_init_IRQ(void); void __init mpc512x_declare_of_platform_devices(void); #endif /* __MPC512X_H__ */ diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c index d8cd579..434d683 100644 --- a/arch/powerpc/platforms/512x/mpc512x_shared.c +++ b/arch/powerpc/platforms/512x/mpc512x_shared.c @@ -24,29 +24,6 @@ #include "mpc512x.h" -unsigned long -mpc512x_find_ips_freq(struct device_node *node) -{ - struct device_node *np; - const unsigned int *p_ips_freq = NULL; - - of_node_get(node); - while (node) { - p_ips_freq = of_get_property(node, "bus-frequency", NULL); - if (p_ips_freq) - break; - - np = of_get_parent(node); - of_node_put(node); - node = np; - } - if (node) - of_node_put(node); - - return p_ips_freq ? *p_ips_freq : 0; -} -EXPORT_SYMBOL(mpc512x_find_ips_freq); - void __init mpc512x_init_IRQ(void) { struct device_node *np; diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c index 8e3dd5a..a46bad0 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_common.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c @@ -47,36 +47,6 @@ static DEFINE_SPINLOCK(mpc52xx_lock); static struct mpc52xx_gpt __iomem *mpc52xx_wdt; static struct mpc52xx_cdm __iomem *mpc52xx_cdm; -/** - * mpc52xx_find_ipb_freq - Find the IPB bus frequency for a device - * @node: device node - * - * Returns IPB bus frequency, or 0 if the bus frequency cannot be found. - */ -unsigned int -mpc52xx_find_ipb_freq(struct device_node *node) -{ - struct device_node *np; - const unsigned int *p_ipb_freq = NULL; - - of_node_get(node); - while (node) { - p_ipb_freq = of_get_property(node, "bus-frequency", NULL); - if (p_ipb_freq) - break; - - np = of_get_parent(node); - of_node_put(node); - node = np; - } - if (node) - of_node_put(node); - - return p_ipb_freq ? *p_ipb_freq : 0; -} -EXPORT_SYMBOL(mpc52xx_find_ipb_freq); - - /* * Configure the XLB arbiter settings to match what Linux expects. */ @@ -221,7 +191,7 @@ unsigned int mpc52xx_get_xtal_freq(struct device_node *node) if (!mpc52xx_cdm) return 0; - freq = mpc52xx_find_ipb_freq(node); + freq = mpc5xxx_get_bus_frequency(node); if (!freq) return 0; diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig index 437d29a..083ebee 100644 --- a/arch/powerpc/platforms/83xx/Kconfig +++ b/arch/powerpc/platforms/83xx/Kconfig @@ -96,6 +96,13 @@ config ASP834x This enables support for the Analogue & Micro ASP 83xx board. +config KMETER1 + bool "Keymile KMETER1" + select DEFAULT_UIMAGE + select QUICC_ENGINE + help + This enables support for the Keymile KMETER1 board. + endif diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile index 051777c..e139c36 100644 --- a/arch/powerpc/platforms/83xx/Makefile +++ b/arch/powerpc/platforms/83xx/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_MPC837x_MDS) += mpc837x_mds.o obj-$(CONFIG_SBC834x) += sbc834x.o obj-$(CONFIG_MPC837x_RDB) += mpc837x_rdb.o obj-$(CONFIG_ASP834x) += asp834x.o +obj-$(CONFIG_KMETER1) += kmeter1.o diff --git a/arch/powerpc/platforms/83xx/kmeter1.c b/arch/powerpc/platforms/83xx/kmeter1.c new file mode 100644 index 0000000..903acfd --- /dev/null +++ b/arch/powerpc/platforms/83xx/kmeter1.c @@ -0,0 +1,191 @@ +/* + * Copyright 2008 DENX Software Engineering GmbH + * Author: Heiko Schocher <hs@denx.de> + * + * Description: + * Keymile KMETER1 board specific routines. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/stddef.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/reboot.h> +#include <linux/pci.h> +#include <linux/kdev_t.h> +#include <linux/major.h> +#include <linux/console.h> +#include <linux/delay.h> +#include <linux/seq_file.h> +#include <linux/root_dev.h> +#include <linux/initrd.h> +#include <linux/of_platform.h> +#include <linux/of_device.h> + +#include <asm/system.h> +#include <asm/atomic.h> +#include <asm/time.h> +#include <asm/io.h> +#include <asm/machdep.h> +#include <asm/ipic.h> +#include <asm/irq.h> +#include <asm/prom.h> +#include <asm/udbg.h> +#include <sysdev/fsl_soc.h> +#include <sysdev/fsl_pci.h> +#include <asm/qe.h> +#include <asm/qe_ic.h> + +#include "mpc83xx.h" + +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ +/* ************************************************************************ + * + * Setup the architecture + * + */ +static void __init kmeter1_setup_arch(void) +{ + struct device_node *np; + + if (ppc_md.progress) + ppc_md.progress("kmeter1_setup_arch()", 0); + +#ifdef CONFIG_PCI + for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") + mpc83xx_add_bridge(np); +#endif + +#ifdef CONFIG_QUICC_ENGINE + qe_reset(); + + np = of_find_node_by_name(NULL, "par_io"); + if (np != NULL) { + par_io_init(np); + of_node_put(np); + + for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) + par_io_of_config(np); + } + + np = of_find_compatible_node(NULL, "network", "ucc_geth"); + if (np != NULL) { + uint svid; + + /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */ + svid = mfspr(SPRN_SVR); + if (SVR_REV(svid) == 0x0021) { + struct device_node *np_par; + struct resource res; + void __iomem *base; + int ret; + + np_par = of_find_node_by_name(NULL, "par_io"); + if (np_par == NULL) { + printk(KERN_WARNING "%s couldn;t find par_io node\n", + __func__); + return; + } + /* Map Parallel I/O ports registers */ + ret = of_address_to_resource(np_par, 0, &res); + if (ret) { + printk(KERN_WARNING "%s couldn;t map par_io registers\n", + __func__); + return; + } + base = ioremap(res.start, res.end - res.start + 1); + + /* + * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) + * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) + */ + setbits32((base + 0xa8), 0x0c003000); + + /* + * IMMR + 0x14AC[20:27] = 10101010 + * (data delay for both UCC's) + */ + clrsetbits_be32((base + 0xac), 0xff0, 0xaa0); + iounmap(base); + of_node_put(np_par); + } + of_node_put(np); + } +#endif /* CONFIG_QUICC_ENGINE */ +} + +static struct of_device_id kmeter_ids[] = { + { .type = "soc", }, + { .compatible = "soc", }, + { .compatible = "simple-bus", }, + { .type = "qe", }, + { .compatible = "fsl,qe", }, + {}, +}; + +static int __init kmeter_declare_of_platform_devices(void) +{ + /* Publish the QE devices */ + of_platform_bus_probe(NULL, kmeter_ids, NULL); + + return 0; +} +machine_device_initcall(kmeter1, kmeter_declare_of_platform_devices); + +static void __init kmeter1_init_IRQ(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,pq2pro-pic"); + if (!np) { + np = of_find_node_by_type(NULL, "ipic"); + if (!np) + return; + } + + ipic_init(np, 0); + + /* Initialize the default interrupt mapping priorities, + * in case the boot rom changed something on us. + */ + ipic_set_default_priority(); + of_node_put(np); + +#ifdef CONFIG_QUICC_ENGINE + np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); + if (!np) { + np = of_find_node_by_type(NULL, "qeic"); + if (!np) + return; + } + qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic); + of_node_put(np); +#endif /* CONFIG_QUICC_ENGINE */ +} + +/* + * Called very early, MMU is off, device-tree isn't unflattened + */ +static int __init kmeter1_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + return of_flat_dt_is_compatible(root, "keymile,KMETER1"); +} + +define_machine(kmeter1) { + .name = "KMETER1", + .probe = kmeter1_probe, + .setup_arch = kmeter1_setup_arch, + .init_IRQ = kmeter1_init_IRQ, + .get_irq = ipic_get_irq, + .restart = mpc83xx_restart, + .time_init = mpc83xx_time_init, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +}; diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h index 83cfe51..d1dc5b0 100644 --- a/arch/powerpc/platforms/83xx/mpc83xx.h +++ b/arch/powerpc/platforms/83xx/mpc83xx.h @@ -22,8 +22,8 @@ /* system i/o configuration register low */ #define MPC83XX_SICRL_OFFS 0x114 #define MPC834X_SICRL_USB_MASK 0x60000000 -#define MPC834X_SICRL_USB0 0x40000000 -#define MPC834X_SICRL_USB1 0x20000000 +#define MPC834X_SICRL_USB0 0x20000000 +#define MPC834X_SICRL_USB1 0x40000000 #define MPC831X_SICRL_USB_MASK 0x00000c00 #define MPC831X_SICRL_USB_ULPI 0x00000800 #define MPC8315_SICRL_USB_MASK 0x000000fc diff --git a/arch/powerpc/platforms/83xx/usb.c b/arch/powerpc/platforms/83xx/usb.c index 11e1fac..3ba4bb7 100644 --- a/arch/powerpc/platforms/83xx/usb.c +++ b/arch/powerpc/platforms/83xx/usb.c @@ -47,25 +47,25 @@ int mpc834x_usb_cfg(void) sccr |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */ prop = of_get_property(np, "phy_type", NULL); + port1_is_dr = 1; if (prop && (!strcmp(prop, "utmi") || !strcmp(prop, "utmi_wide"))) { sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1; sicrh |= MPC834X_SICRH_USB_UTMI; - port1_is_dr = 1; + port0_is_dr = 1; } else if (prop && !strcmp(prop, "serial")) { dr_mode = of_get_property(np, "dr_mode", NULL); if (dr_mode && !strcmp(dr_mode, "otg")) { sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1; - port1_is_dr = 1; + port0_is_dr = 1; } else { - sicrl |= MPC834X_SICRL_USB0; + sicrl |= MPC834X_SICRL_USB1; } } else if (prop && !strcmp(prop, "ulpi")) { - sicrl |= MPC834X_SICRL_USB0; + sicrl |= MPC834X_SICRL_USB1; } else { printk(KERN_WARNING "834x USB PHY type not supported\n"); } - port0_is_dr = 1; of_node_put(np); } np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph"); diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 43d385c..a9b4166 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -35,12 +35,14 @@ config MPC85xx_MDS select DEFAULT_UIMAGE select PHYLIB select HAS_RAPIDIO + select SWIOTLB help This option enables support for the MPC85xx MDS board config MPC8536_DS bool "Freescale MPC8536 DS" select DEFAULT_UIMAGE + select SWIOTLB help This option enables support for the MPC8536 DS board @@ -49,6 +51,7 @@ config MPC85xx_DS select PPC_I8259 select DEFAULT_UIMAGE select FSL_ULI1575 + select SWIOTLB help This option enables support for the MPC85xx DS (MPC8544 DS) board @@ -64,6 +67,16 @@ config KSI8560 help This option enables support for the Emerson KSI8560 board +config XES_MPC85xx + bool "X-ES single-board computer" + select DEFAULT_UIMAGE + help + This option enables support for the various single-board + computers from Extreme Engineering Solutions (X-ES) based on + Freescale MPC85xx processors. + Manufacturer: Extreme Engineering Solutions, Inc. + URL: <http://www.xes-inc.com/> + config STX_GP3 bool "Silicon Turnkey Express GP3" help diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index a857b35..835733f 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_SBC8560) += sbc8560.o obj-$(CONFIG_SBC8548) += sbc8548.o obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o obj-$(CONFIG_KSI8560) += ksi8560.o +obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
\ No newline at end of file diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c index 63efca2..055ff41 100644 --- a/arch/powerpc/platforms/85xx/mpc8536_ds.c +++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c @@ -17,6 +17,7 @@ #include <linux/seq_file.h> #include <linux/interrupt.h> #include <linux/of_platform.h> +#include <linux/lmb.h> #include <asm/system.h> #include <asm/time.h> @@ -26,6 +27,7 @@ #include <asm/prom.h> #include <asm/udbg.h> #include <asm/mpic.h> +#include <asm/swiotlb.h> #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> @@ -65,7 +67,9 @@ static void __init mpc8536_ds_setup_arch(void) { #ifdef CONFIG_PCI struct device_node *np; + struct pci_controller *hose; #endif + dma_addr_t max = 0xffffffff; if (ppc_md.progress) ppc_md.progress("mpc8536_ds_setup_arch()", 0); @@ -80,11 +84,22 @@ static void __init mpc8536_ds_setup_arch(void) fsl_add_bridge(np, 1); else fsl_add_bridge(np, 0); + + hose = pci_find_hose_for_OF_device(np); + max = min(max, hose->dma_window_base_cur + + hose->dma_window_size); } } #endif +#ifdef CONFIG_SWIOTLB + if (lmb_end_of_DRAM() > max) { + ppc_swiotlb_enable = 1; + set_pci_dma_ops(&swiotlb_pci_dma_ops); + } +#endif + printk("MPC8536 DS board from Freescale Semiconductor\n"); } @@ -102,6 +117,8 @@ static int __init mpc8536_ds_publish_devices(void) } machine_device_initcall(mpc8536_ds, mpc8536_ds_publish_devices); +machine_arch_initcall(mpc8536_ds, swiotlb_setup_bus_notifier); + /* * Called very early, device-tree isn't unflattened */ diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c index 53d5851..849c0ac 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c @@ -20,6 +20,7 @@ #include <linux/seq_file.h> #include <linux/interrupt.h> #include <linux/of_platform.h> +#include <linux/lmb.h> #include <asm/system.h> #include <asm/time.h> @@ -30,6 +31,7 @@ #include <asm/udbg.h> #include <asm/mpic.h> #include <asm/i8259.h> +#include <asm/swiotlb.h> #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> @@ -155,7 +157,9 @@ static void __init mpc85xx_ds_setup_arch(void) { #ifdef CONFIG_PCI struct device_node *np; + struct pci_controller *hose; #endif + dma_addr_t max = 0xffffffff; if (ppc_md.progress) ppc_md.progress("mpc85xx_ds_setup_arch()", 0); @@ -171,6 +175,10 @@ static void __init mpc85xx_ds_setup_arch(void) fsl_add_bridge(np, 1); else fsl_add_bridge(np, 0); + + hose = pci_find_hose_for_OF_device(np); + max = min(max, hose->dma_window_base_cur + + hose->dma_window_size); } } @@ -181,6 +189,13 @@ static void __init mpc85xx_ds_setup_arch(void) mpc85xx_smp_init(); #endif +#ifdef CONFIG_SWIOTLB + if (lmb_end_of_DRAM() > max) { + ppc_swiotlb_enable = 1; + set_pci_dma_ops(&swiotlb_pci_dma_ops); + } +#endif + printk("MPC85xx DS board from Freescale Semiconductor\n"); } @@ -217,6 +232,10 @@ machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices); machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices); machine_device_initcall(p2020_ds, mpc85xxds_publish_devices); +machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier); +machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier); +machine_arch_initcall(p2020_ds, swiotlb_setup_bus_notifier); + /* * Called very early, device-tree isn't unflattened */ diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index b2c0a43..60ed9c0 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -33,6 +33,7 @@ #include <linux/of_platform.h> #include <linux/of_device.h> #include <linux/phy.h> +#include <linux/lmb.h> #include <asm/system.h> #include <asm/atomic.h> @@ -49,6 +50,7 @@ #include <asm/qe.h> #include <asm/qe_ic.h> #include <asm/mpic.h> +#include <asm/swiotlb.h> #undef DEBUG #ifdef DEBUG @@ -155,6 +157,10 @@ static void __init mpc85xx_mds_setup_arch(void) { struct device_node *np; static u8 __iomem *bcsr_regs = NULL; +#ifdef CONFIG_PCI + struct pci_controller *hose; +#endif + dma_addr_t max = 0xffffffff; if (ppc_md.progress) ppc_md.progress("mpc85xx_mds_setup_arch()", 0); @@ -179,6 +185,10 @@ static void __init mpc85xx_mds_setup_arch(void) fsl_add_bridge(np, 1); else fsl_add_bridge(np, 0); + + hose = pci_find_hose_for_OF_device(np); + max = min(max, hose->dma_window_base_cur + + hose->dma_window_size); } } #endif @@ -227,6 +237,13 @@ static void __init mpc85xx_mds_setup_arch(void) iounmap(bcsr_regs); } #endif /* CONFIG_QUICC_ENGINE */ + +#ifdef CONFIG_SWIOTLB + if (lmb_end_of_DRAM() > max) { + ppc_swiotlb_enable = 1; + set_pci_dma_ops(&swiotlb_pci_dma_ops); + } +#endif } @@ -268,6 +285,7 @@ static struct of_device_id mpc85xx_ids[] = { { .type = "qe", }, { .compatible = "fsl,qe", }, { .compatible = "gianfar", }, + { .compatible = "fsl,rapidio-delta", }, {}, }; @@ -281,6 +299,9 @@ static int __init mpc85xx_publish_devices(void) machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices); +machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier); +machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier); + static void __init mpc85xx_mds_pic_init(void) { struct mpic *mpic; diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c index cc0b0db..62c592ede6 100644 --- a/arch/powerpc/platforms/85xx/smp.c +++ b/arch/powerpc/platforms/85xx/smp.c @@ -52,20 +52,19 @@ smp_85xx_kick_cpu(int nr) pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr); - local_irq_save(flags); - np = of_get_cpu_node(nr, NULL); cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL); if (cpu_rel_addr == NULL) { printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr); - local_irq_restore(flags); return; } /* Map the spin table */ bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY); + local_irq_save(flags); + out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr); out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start)); @@ -73,10 +72,10 @@ smp_85xx_kick_cpu(int nr) while ((__secondary_hold_acknowledge != nr) && (++n < 1000)) mdelay(1); - iounmap(bptr_vaddr); - local_irq_restore(flags); + iounmap(bptr_vaddr); + pr_debug("waited %d msecs for CPU #%d.\n", n, nr); } diff --git a/arch/powerpc/platforms/85xx/socrates.c b/arch/powerpc/platforms/85xx/socrates.c index d0e8443..747d8fb 100644 --- a/arch/powerpc/platforms/85xx/socrates.c +++ b/arch/powerpc/platforms/85xx/socrates.c @@ -102,10 +102,11 @@ static struct of_device_id __initdata socrates_of_bus_ids[] = { {}, }; -static void __init socrates_init(void) +static int __init socrates_publish_devices(void) { - of_platform_bus_probe(NULL, socrates_of_bus_ids, NULL); + return of_platform_bus_probe(NULL, socrates_of_bus_ids, NULL); } +machine_device_initcall(socrates, socrates_publish_devices); /* * Called very early, device-tree isn't unflattened @@ -124,7 +125,6 @@ define_machine(socrates) { .name = "Socrates", .probe = socrates_probe, .setup_arch = socrates_setup_arch, - .init = socrates_init, .init_IRQ = socrates_pic_init, .get_irq = mpic_get_irq, .restart = fsl_rstcr_restart, diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c new file mode 100644 index 0000000..1b42605 --- /dev/null +++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c @@ -0,0 +1,281 @@ +/* + * Copyright (C) 2009 Extreme Engineering Solutions, Inc. + * + * X-ES board-specific functionality + * + * Based on mpc85xx_ds code from Freescale Semiconductor, Inc. + * + * Author: Nate Case <ncase@xes-inc.com> + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/stddef.h> +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/kdev_t.h> +#include <linux/delay.h> +#include <linux/seq_file.h> +#include <linux/interrupt.h> +#include <linux/of_platform.h> + +#include <asm/system.h> +#include <asm/time.h> +#include <asm/machdep.h> +#include <asm/pci-bridge.h> +#include <mm/mmu_decl.h> +#include <asm/prom.h> +#include <asm/udbg.h> +#include <asm/mpic.h> + +#include <sysdev/fsl_soc.h> +#include <sysdev/fsl_pci.h> + +/* A few bit definitions needed for fixups on some boards */ +#define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */ +#define MPC85xx_L2CTL_L2I 0x40000000 /* L2 flash invalidate */ +#define MPC85xx_L2CTL_L2SIZ_MASK 0x30000000 /* L2 SRAM size (R/O) */ + +void __init xes_mpc85xx_pic_init(void) +{ + struct mpic *mpic; + struct resource r; + struct device_node *np; + + np = of_find_node_by_type(NULL, "open-pic"); + if (np == NULL) { + printk(KERN_ERR "Could not find open-pic node\n"); + return; + } + + if (of_address_to_resource(np, 0, &r)) { + printk(KERN_ERR "Failed to map mpic register space\n"); + of_node_put(np); + return; + } + + mpic = mpic_alloc(np, r.start, + MPIC_PRIMARY | MPIC_WANTS_RESET | + MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS, + 0, 256, " OpenPIC "); + BUG_ON(mpic == NULL); + of_node_put(np); + + mpic_init(mpic); +} + +static void xes_mpc85xx_configure_l2(void __iomem *l2_base) +{ + volatile uint32_t ctl, tmp; + + asm volatile("msync; isync"); + tmp = in_be32(l2_base); + + /* + * xMon may have enabled part of L2 as SRAM, so we need to set it + * up for all cache mode just to be safe. + */ + printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n"); + + ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I; + if (machine_is_compatible("MPC8540") || + machine_is_compatible("MPC8560")) + /* + * Assume L2 SRAM is used fully for cache, so set + * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3). + */ + ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2; + + asm volatile("msync; isync"); + out_be32(l2_base, ctl); + asm volatile("msync; isync"); +} + +static void xes_mpc85xx_fixups(void) +{ + struct device_node *np; + int err; + + /* + * Legacy xMon firmware on some X-ES boards does not enable L2 + * as cache. We must ensure that they get enabled here. + */ + for_each_node_by_name(np, "l2-cache-controller") { + struct resource r[2]; + void __iomem *l2_base; + + /* Only MPC8548, MPC8540, and MPC8560 boards are affected */ + if (!of_device_is_compatible(np, + "fsl,mpc8548-l2-cache-controller") && + !of_device_is_compatible(np, + "fsl,mpc8540-l2-cache-controller") && + !of_device_is_compatible(np, + "fsl,mpc8560-l2-cache-controller")) + continue; + + err = of_address_to_resource(np, 0, &r[0]); + if (err) { + printk(KERN_WARNING "xes_mpc85xx: Could not get " + "resource for device tree node '%s'", + np->full_name); + continue; + } + + l2_base = ioremap(r[0].start, r[0].end - r[0].start + 1); + + xes_mpc85xx_configure_l2(l2_base); + } +} + +#ifdef CONFIG_PCI +static int primary_phb_addr; +#endif + +/* + * Setup the architecture + */ +#ifdef CONFIG_SMP +extern void __init mpc85xx_smp_init(void); +#endif +static void __init xes_mpc85xx_setup_arch(void) +{ +#ifdef CONFIG_PCI + struct device_node *np; +#endif + struct device_node *root; + const char *model = "Unknown"; + + root = of_find_node_by_path("/"); + if (root == NULL) + return; + + model = of_get_property(root, "model", NULL); + + printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n", + model + strlen("xes,")); + + xes_mpc85xx_fixups(); + +#ifdef CONFIG_PCI + for_each_node_by_type(np, "pci") { + if (of_device_is_compatible(np, "fsl,mpc8540-pci") || + of_device_is_compatible(np, "fsl,mpc8548-pcie")) { + struct resource rsrc; + of_address_to_resource(np, 0, &rsrc); + if ((rsrc.start & 0xfffff) == primary_phb_addr) + fsl_add_bridge(np, 1); + else + fsl_add_bridge(np, 0); + } + } +#endif + +#ifdef CONFIG_SMP + mpc85xx_smp_init(); +#endif +} + +static struct of_device_id __initdata xes_mpc85xx_ids[] = { + { .type = "soc", }, + { .compatible = "soc", }, + { .compatible = "simple-bus", }, + { .compatible = "gianfar", }, + {}, +}; + +static int __init xes_mpc85xx_publish_devices(void) +{ + return of_platform_bus_probe(NULL, xes_mpc85xx_ids, NULL); +} +machine_device_initcall(xes_mpc8572, xes_mpc85xx_publish_devices); +machine_device_initcall(xes_mpc8548, xes_mpc85xx_publish_devices); +machine_device_initcall(xes_mpc8540, xes_mpc85xx_publish_devices); + +/* + * Called very early, device-tree isn't unflattened + */ +static int __init xes_mpc8572_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + if (of_flat_dt_is_compatible(root, "xes,MPC8572")) { +#ifdef CONFIG_PCI + primary_phb_addr = 0x8000; +#endif + return 1; + } else { + return 0; + } +} + +static int __init xes_mpc8548_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + if (of_flat_dt_is_compatible(root, "xes,MPC8548")) { +#ifdef CONFIG_PCI + primary_phb_addr = 0xb000; +#endif + return 1; + } else { + return 0; + } +} + +static int __init xes_mpc8540_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + if (of_flat_dt_is_compatible(root, "xes,MPC8540")) { +#ifdef CONFIG_PCI + primary_phb_addr = 0xb000; +#endif + return 1; + } else { + return 0; + } +} + +define_machine(xes_mpc8572) { + .name = "X-ES MPC8572", + .probe = xes_mpc8572_probe, + .setup_arch = xes_mpc85xx_setup_arch, + .init_IRQ = xes_mpc85xx_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif + .get_irq = mpic_get_irq, + .restart = fsl_rstcr_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +}; + +define_machine(xes_mpc8548) { + .name = "X-ES MPC8548", + .probe = xes_mpc8548_probe, + .setup_arch = xes_mpc85xx_setup_arch, + .init_IRQ = xes_mpc85xx_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif + .get_irq = mpic_get_irq, + .restart = fsl_rstcr_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +}; + +define_machine(xes_mpc8540) { + .name = "X-ES MPC8540", + .probe = xes_mpc8540_probe, + .setup_arch = xes_mpc85xx_setup_arch, + .init_IRQ = xes_mpc85xx_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif + .get_irq = mpic_get_irq, + .restart = fsl_rstcr_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +}; diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig index fdaf4dd..9c7b64a 100644 --- a/arch/powerpc/platforms/86xx/Kconfig +++ b/arch/powerpc/platforms/86xx/Kconfig @@ -15,6 +15,7 @@ config MPC8641_HPCN select DEFAULT_UIMAGE select FSL_ULI1575 select HAS_RAPIDIO + select SWIOTLB help This option enables support for the MPC8641 HPCN board. diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c index 51eec0c..627908a 100644 --- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c +++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c @@ -37,6 +37,7 @@ #include <linux/of_platform.h> #include <sysdev/fsl_pci.h> #include <sysdev/fsl_soc.h> +#include <sysdev/simple_gpio.h> #include "mpc86xx.h" @@ -51,6 +52,9 @@ static struct of_device_id __initdata mpc8610_ids[] = { static int __init mpc8610_declare_of_platform_devices(void) { + /* Firstly, register PIXIS GPIOs. */ + simple_gpiochip_init("fsl,fpga-pixis-gpio-bank"); + /* Without this call, the SSI device driver won't get probed. */ of_platform_bus_probe(NULL, mpc8610_ids, NULL); diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c index 7e9e83c..6632702 100644 --- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c +++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c @@ -19,6 +19,7 @@ #include <linux/delay.h> #include <linux/seq_file.h> #include <linux/of_platform.h> +#include <linux/lmb.h> #include <asm/system.h> #include <asm/time.h> @@ -27,6 +28,7 @@ #include <asm/prom.h> #include <mm/mmu_decl.h> #include <asm/udbg.h> +#include <asm/swiotlb.h> #include <asm/mpic.h> @@ -70,7 +72,9 @@ mpc86xx_hpcn_setup_arch(void) { #ifdef CONFIG_PCI struct device_node *np; + struct pci_controller *hose; #endif + dma_addr_t max = 0xffffffff; if (ppc_md.progress) ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0); @@ -83,6 +87,9 @@ mpc86xx_hpcn_setup_arch(void) fsl_add_bridge(np, 1); else fsl_add_bridge(np, 0); + hose = pci_find_hose_for_OF_device(np); + max = min(max, hose->dma_window_base_cur + + hose->dma_window_size); } ppc_md.pci_exclude_device = mpc86xx_exclude_device; @@ -94,6 +101,13 @@ mpc86xx_hpcn_setup_arch(void) #ifdef CONFIG_SMP mpc86xx_smp_init(); #endif + +#ifdef CONFIG_SWIOTLB + if (lmb_end_of_DRAM() > max) { + ppc_swiotlb_enable = 1; + set_pci_dma_ops(&swiotlb_pci_dma_ops); + } +#endif } @@ -158,6 +172,7 @@ static int __init declare_of_platform_devices(void) return 0; } machine_device_initcall(mpc86xx_hpcn, declare_of_platform_devices); +machine_arch_initcall(mpc86xx_hpcn, swiotlb_setup_bus_notifier); define_machine(mpc86xx_hpcn) { .name = "MPC86xx HPCN", diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype index cca6b4f..61187be 100644 --- a/arch/powerpc/platforms/Kconfig.cputype +++ b/arch/powerpc/platforms/Kconfig.cputype @@ -1,7 +1,7 @@ config PPC64 bool "64-bit kernel" default n - select HAVE_PERF_COUNTERS + select PPC_HAVE_PMU_SUPPORT help This option selects whether a 32-bit or a 64-bit kernel will be built. @@ -21,7 +21,7 @@ choice If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx. -config PPC_BOOK3S +config PPC_BOOK3S_32 bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx" select PPC_FPU @@ -57,11 +57,14 @@ config E200 endchoice -config PPC_BOOK3S - default y +config PPC_BOOK3S_64 + def_bool y depends on PPC64 select PPC_FPU +config PPC_BOOK3S + def_bool y + depends on PPC_BOOK3S_32 || PPC_BOOK3S_64 config POWER4_ONLY bool "Optimize for POWER4" @@ -75,6 +78,7 @@ config POWER4_ONLY config 6xx def_bool y depends on PPC32 && PPC_BOOK3S + select PPC_HAVE_PMU_SUPPORT config POWER3 bool @@ -243,6 +247,15 @@ config VIRT_CPU_ACCOUNTING If in doubt, say Y here. +config PPC_HAVE_PMU_SUPPORT + bool + +config PPC_PERF_CTRS + def_bool y + depends on PERF_COUNTERS && PPC_HAVE_PMU_SUPPORT + help + This enables the powerpc-specific perf_counter back-end. + config SMP depends on PPC_STD_MMU || FSL_BOOKE bool "Symmetric multi-processing support" diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile index f741919..a6812ee 100644 --- a/arch/powerpc/platforms/Makefile +++ b/arch/powerpc/platforms/Makefile @@ -1,4 +1,6 @@ +subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror + obj-$(CONFIG_FSL_ULI1575) += fsl_uli1575.o obj-$(CONFIG_PPC_PMAC) += powermac/ diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c index 9046803..bc97fad 100644 --- a/arch/powerpc/platforms/cell/smp.c +++ b/arch/powerpc/platforms/cell/smp.c @@ -36,7 +36,6 @@ #include <asm/prom.h> #include <asm/smp.h> #include <asm/paca.h> -#include <asm/time.h> #include <asm/machdep.h> #include <asm/cputable.h> #include <asm/firmware.h> @@ -140,31 +139,6 @@ static void __devinit smp_cell_setup_cpu(int cpu) mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER); } -static DEFINE_SPINLOCK(timebase_lock); -static unsigned long timebase = 0; - -static void __devinit cell_give_timebase(void) -{ - spin_lock(&timebase_lock); - rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); - timebase = get_tb(); - spin_unlock(&timebase_lock); - - while (timebase) - barrier(); - rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); -} - -static void __devinit cell_take_timebase(void) -{ - while (!timebase) - barrier(); - spin_lock(&timebase_lock); - set_tb(timebase >> 32, timebase & 0xffffffff); - timebase = 0; - spin_unlock(&timebase_lock); -} - static void __devinit smp_cell_kick_cpu(int nr) { BUG_ON(nr < 0 || nr >= NR_CPUS); @@ -224,8 +198,8 @@ void __init smp_init_cell(void) /* Non-lpar has additional take/give timebase */ if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { - smp_ops->give_timebase = cell_give_timebase; - smp_ops->take_timebase = cell_take_timebase; + smp_ops->give_timebase = rtas_give_timebase; + smp_ops->take_timebase = rtas_take_timebase; } DBG(" <- smp_init_cell()\n"); diff --git a/arch/powerpc/platforms/cell/spu_fault.c b/arch/powerpc/platforms/cell/spu_fault.c index 95d8dad..d06ba87 100644 --- a/arch/powerpc/platforms/cell/spu_fault.c +++ b/arch/powerpc/platforms/cell/spu_fault.c @@ -70,7 +70,7 @@ int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea, } ret = 0; - *flt = handle_mm_fault(mm, vma, ea, is_write); + *flt = handle_mm_fault(mm, vma, ea, is_write ? FAULT_FLAG_WRITE : 0); if (unlikely(*flt & VM_FAULT_ERROR)) { if (*flt & VM_FAULT_OOM) { ret = -ENOMEM; diff --git a/arch/powerpc/platforms/chrp/smp.c b/arch/powerpc/platforms/chrp/smp.c index 10a4a4d..02cafec 100644 --- a/arch/powerpc/platforms/chrp/smp.c +++ b/arch/powerpc/platforms/chrp/smp.c @@ -26,7 +26,6 @@ #include <asm/io.h> #include <asm/prom.h> #include <asm/smp.h> -#include <asm/time.h> #include <asm/machdep.h> #include <asm/mpic.h> #include <asm/rtas.h> @@ -42,40 +41,12 @@ static void __devinit smp_chrp_setup_cpu(int cpu_nr) mpic_setup_this_cpu(); } -static DEFINE_SPINLOCK(timebase_lock); -static unsigned int timebase_upper = 0, timebase_lower = 0; - -void __devinit smp_chrp_give_timebase(void) -{ - spin_lock(&timebase_lock); - rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); - timebase_upper = get_tbu(); - timebase_lower = get_tbl(); - spin_unlock(&timebase_lock); - - while (timebase_upper || timebase_lower) - barrier(); - rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); -} - -void __devinit smp_chrp_take_timebase(void) -{ - while (!(timebase_upper || timebase_lower)) - barrier(); - spin_lock(&timebase_lock); - set_tb(timebase_upper, timebase_lower); - timebase_upper = 0; - timebase_lower = 0; - spin_unlock(&timebase_lock); - printk("CPU %i taken timebase\n", smp_processor_id()); -} - /* CHRP with openpic */ struct smp_ops_t chrp_smp_ops = { .message_pass = smp_mpic_message_pass, .probe = smp_mpic_probe, .kick_cpu = smp_chrp_kick_cpu, .setup_cpu = smp_chrp_setup_cpu, - .give_timebase = smp_chrp_give_timebase, - .take_timebase = smp_chrp_take_timebase, + .give_timebase = rtas_give_timebase, + .take_timebase = rtas_take_timebase, }; diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c index 153051e..a461934 100644 --- a/arch/powerpc/platforms/pasemi/setup.c +++ b/arch/powerpc/platforms/pasemi/setup.c @@ -71,20 +71,25 @@ static void pas_restart(char *cmd) } #ifdef CONFIG_SMP -static DEFINE_SPINLOCK(timebase_lock); +static raw_spinlock_t timebase_lock; static unsigned long timebase; static void __devinit pas_give_timebase(void) { - spin_lock(&timebase_lock); + unsigned long flags; + + local_irq_save(flags); + hard_irq_disable(); + __raw_spin_lock(&timebase_lock); mtspr(SPRN_TBCTL, TBCTL_FREEZE); isync(); timebase = get_tb(); - spin_unlock(&timebase_lock); + __raw_spin_unlock(&timebase_lock); while (timebase) barrier(); mtspr(SPRN_TBCTL, TBCTL_RESTART); + local_irq_restore(flags); } static void __devinit pas_take_timebase(void) @@ -92,10 +97,10 @@ static void __devinit pas_take_timebase(void) while (!timebase) smp_rmb(); - spin_lock(&timebase_lock); + __raw_spin_lock(&timebase_lock); set_tb(timebase >> 32, timebase & 0xffffffff); timebase = 0; - spin_unlock(&timebase_lock); + __raw_spin_unlock(&timebase_lock); } struct smp_ops_t pas_smp_ops = { diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c index 86f69a4..c205226 100644 --- a/arch/powerpc/platforms/powermac/setup.c +++ b/arch/powerpc/platforms/powermac/setup.c @@ -103,11 +103,6 @@ unsigned long smu_cmdbuf_abs; EXPORT_SYMBOL(smu_cmdbuf_abs); #endif -#ifdef CONFIG_SMP -extern struct smp_ops_t psurge_smp_ops; -extern struct smp_ops_t core99_smp_ops; -#endif /* CONFIG_SMP */ - static void pmac_show_cpuinfo(struct seq_file *m) { struct device_node *np; @@ -341,34 +336,6 @@ static void __init pmac_setup_arch(void) ROOT_DEV = DEFAULT_ROOT_DEVICE; #endif -#ifdef CONFIG_SMP - /* Check for Core99 */ - ic = of_find_node_by_name(NULL, "uni-n"); - if (!ic) - ic = of_find_node_by_name(NULL, "u3"); - if (!ic) - ic = of_find_node_by_name(NULL, "u4"); - if (ic) { - of_node_put(ic); - smp_ops = &core99_smp_ops; - } -#ifdef CONFIG_PPC32 - else { - /* - * We have to set bits in cpu_possible_map here since the - * secondary CPU(s) aren't in the device tree, and - * setup_per_cpu_areas only allocates per-cpu data for - * CPUs in the cpu_possible_map. - */ - int cpu; - - for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu) - cpu_set(cpu, cpu_possible_map); - smp_ops = &psurge_smp_ops; - } -#endif -#endif /* CONFIG_SMP */ - #ifdef CONFIG_ADB if (strstr(cmd_line, "adb_sync")) { extern int __adb_probe_sync; @@ -512,6 +479,14 @@ static void __init pmac_init_early(void) #ifdef CONFIG_PPC64 iommu_init_early_dart(); #endif + + /* SMP Init has to be done early as we need to patch up + * cpu_possible_map before interrupt stacks are allocated + * or kaboom... + */ +#ifdef CONFIG_SMP + pmac_setup_smp(); +#endif } static int __init pmac_declare_of_platform_devices(void) diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c index cf1dbe7..6d4da7b 100644 --- a/arch/powerpc/platforms/powermac/smp.c +++ b/arch/powerpc/platforms/powermac/smp.c @@ -64,10 +64,11 @@ extern void __secondary_start_pmac_0(void); extern int pmac_pfunc_base_install(void); -#ifdef CONFIG_PPC32 +static void (*pmac_tb_freeze)(int freeze); +static u64 timebase; +static int tb_req; -/* Sync flag for HW tb sync */ -static volatile int sec_tb_reset = 0; +#ifdef CONFIG_PPC32 /* * Powersurge (old powermac SMP) support. @@ -294,6 +295,9 @@ static int __init smp_psurge_probe(void) psurge_quad_init(); /* All released cards using this HW design have 4 CPUs */ ncpus = 4; + /* No sure how timebase sync works on those, let's use SW */ + smp_ops->give_timebase = smp_generic_give_timebase; + smp_ops->take_timebase = smp_generic_take_timebase; } else { iounmap(quad_base); if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { @@ -308,18 +312,15 @@ static int __init smp_psurge_probe(void) psurge_start = ioremap(PSURGE_START, 4); psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); - /* - * This is necessary because OF doesn't know about the + /* This is necessary because OF doesn't know about the * secondary cpu(s), and thus there aren't nodes in the * device tree for them, and smp_setup_cpu_maps hasn't - * set their bits in cpu_possible_map and cpu_present_map. + * set their bits in cpu_present_map. */ if (ncpus > NR_CPUS) ncpus = NR_CPUS; - for (i = 1; i < ncpus ; ++i) { + for (i = 1; i < ncpus ; ++i) cpu_set(i, cpu_present_map); - set_hard_smp_processor_id(i, i); - } if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); @@ -329,8 +330,14 @@ static int __init smp_psurge_probe(void) static void __init smp_psurge_kick_cpu(int nr) { unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; - unsigned long a; - int i; + unsigned long a, flags; + int i, j; + + /* Defining this here is evil ... but I prefer hiding that + * crap to avoid giving people ideas that they can do the + * same. + */ + extern volatile unsigned int cpu_callin_map[NR_CPUS]; /* may need to flush here if secondary bats aren't setup */ for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) @@ -339,47 +346,52 @@ static void __init smp_psurge_kick_cpu(int nr) if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); + /* This is going to freeze the timeebase, we disable interrupts */ + local_irq_save(flags); + out_be32(psurge_start, start); mb(); psurge_set_ipi(nr); + /* * We can't use udelay here because the timebase is now frozen. */ for (i = 0; i < 2000; ++i) - barrier(); + asm volatile("nop" : : : "memory"); psurge_clr_ipi(nr); - if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); -} - -/* - * With the dual-cpu powersurge board, the decrementers and timebases - * of both cpus are frozen after the secondary cpu is started up, - * until we give the secondary cpu another interrupt. This routine - * uses this to get the timebases synchronized. - * -- paulus. - */ -static void __init psurge_dual_sync_tb(int cpu_nr) -{ - int t; - - set_dec(tb_ticks_per_jiffy); - /* XXX fixme */ - set_tb(0, 0); - - if (cpu_nr > 0) { + /* + * Also, because the timebase is frozen, we must not return to the + * caller which will try to do udelay's etc... Instead, we wait -here- + * for the CPU to callin. + */ + for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) { + for (j = 1; j < 10000; j++) + asm volatile("nop" : : : "memory"); + asm volatile("sync" : : : "memory"); + } + if (!cpu_callin_map[nr]) + goto stuck; + + /* And we do the TB sync here too for standard dual CPU cards */ + if (psurge_type == PSURGE_DUAL) { + while(!tb_req) + barrier(); + tb_req = 0; + mb(); + timebase = get_tb(); + mb(); + while (timebase) + barrier(); mb(); - sec_tb_reset = 1; - return; } + stuck: + /* now interrupt the secondary, restarting both TBs */ + if (psurge_type == PSURGE_DUAL) + psurge_set_ipi(1); - /* wait for the secondary to have reset its TB before proceeding */ - for (t = 10000000; t > 0 && !sec_tb_reset; --t) - ; - - /* now interrupt the secondary, starting both TBs */ - psurge_set_ipi(1); + if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); } static struct irqaction psurge_irqaction = { @@ -390,36 +402,35 @@ static struct irqaction psurge_irqaction = { static void __init smp_psurge_setup_cpu(int cpu_nr) { + if (cpu_nr != 0) + return; - if (cpu_nr == 0) { - /* If we failed to start the second CPU, we should still - * send it an IPI to start the timebase & DEC or we might - * have them stuck. - */ - if (num_online_cpus() < 2) { - if (psurge_type == PSURGE_DUAL) - psurge_set_ipi(1); - return; - } - /* reset the entry point so if we get another intr we won't - * try to startup again */ - out_be32(psurge_start, 0x100); - if (setup_irq(30, &psurge_irqaction)) - printk(KERN_ERR "Couldn't get primary IPI interrupt"); - } - - if (psurge_type == PSURGE_DUAL) - psurge_dual_sync_tb(cpu_nr); + /* reset the entry point so if we get another intr we won't + * try to startup again */ + out_be32(psurge_start, 0x100); + if (setup_irq(30, &psurge_irqaction)) + printk(KERN_ERR "Couldn't get primary IPI interrupt"); } void __init smp_psurge_take_timebase(void) { - /* Dummy implementation */ + if (psurge_type != PSURGE_DUAL) + return; + + tb_req = 1; + mb(); + while (!timebase) + barrier(); + mb(); + set_tb(timebase >> 32, timebase & 0xffffffff); + timebase = 0; + mb(); + set_dec(tb_ticks_per_jiffy/2); } void __init smp_psurge_give_timebase(void) { - /* Dummy implementation */ + /* Nothing to do here */ } /* PowerSurge-style Macs */ @@ -437,9 +448,6 @@ struct smp_ops_t psurge_smp_ops = { * Core 99 and later support */ -static void (*pmac_tb_freeze)(int freeze); -static u64 timebase; -static int tb_req; static void smp_core99_give_timebase(void) { @@ -478,7 +486,6 @@ static void __devinit smp_core99_take_timebase(void) set_tb(timebase >> 32, timebase & 0xffffffff); timebase = 0; mb(); - set_dec(tb_ticks_per_jiffy/2); local_irq_restore(flags); } @@ -920,3 +927,34 @@ struct smp_ops_t core99_smp_ops = { # endif #endif }; + +void __init pmac_setup_smp(void) +{ + struct device_node *np; + + /* Check for Core99 */ + np = of_find_node_by_name(NULL, "uni-n"); + if (!np) + np = of_find_node_by_name(NULL, "u3"); + if (!np) + np = of_find_node_by_name(NULL, "u4"); + if (np) { + of_node_put(np); + smp_ops = &core99_smp_ops; + } +#ifdef CONFIG_PPC32 + else { + /* We have to set bits in cpu_possible_map here since the + * secondary CPU(s) aren't in the device tree. Various + * things won't be initialized for CPUs not in the possible + * map, so we really need to fix it up here. + */ + int cpu; + + for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu) + cpu_set(cpu, cpu_possible_map); + smp_ops = &psurge_smp_ops; + } +#endif /* CONFIG_PPC32 */ +} + diff --git a/arch/powerpc/platforms/pseries/eeh_driver.c b/arch/powerpc/platforms/pseries/eeh_driver.c index 9a2a6e3..0e8db67 100644 --- a/arch/powerpc/platforms/pseries/eeh_driver.c +++ b/arch/powerpc/platforms/pseries/eeh_driver.c @@ -122,7 +122,7 @@ static void eeh_enable_irq(struct pci_dev *dev) * passed back in "userdata". */ -static void eeh_report_error(struct pci_dev *dev, void *userdata) +static int eeh_report_error(struct pci_dev *dev, void *userdata) { enum pci_ers_result rc, *res = userdata; struct pci_driver *driver = dev->driver; @@ -130,19 +130,21 @@ static void eeh_report_error(struct pci_dev *dev, void *userdata) dev->error_state = pci_channel_io_frozen; if (!driver) - return; + return 0; eeh_disable_irq(dev); if (!driver->err_handler || !driver->err_handler->error_detected) - return; + return 0; rc = driver->err_handler->error_detected (dev, pci_channel_io_frozen); /* A driver that needs a reset trumps all others */ if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; if (*res == PCI_ERS_RESULT_NONE) *res = rc; + + return 0; } /** @@ -153,7 +155,7 @@ static void eeh_report_error(struct pci_dev *dev, void *userdata) * Cumulative response passed back in "userdata". */ -static void eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata) +static int eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata) { enum pci_ers_result rc, *res = userdata; struct pci_driver *driver = dev->driver; @@ -161,26 +163,28 @@ static void eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata) if (!driver || !driver->err_handler || !driver->err_handler->mmio_enabled) - return; + return 0; rc = driver->err_handler->mmio_enabled (dev); /* A driver that needs a reset trumps all others */ if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; if (*res == PCI_ERS_RESULT_NONE) *res = rc; + + return 0; } /** * eeh_report_reset - tell device that slot has been reset */ -static void eeh_report_reset(struct pci_dev *dev, void *userdata) +static int eeh_report_reset(struct pci_dev *dev, void *userdata) { enum pci_ers_result rc, *res = userdata; struct pci_driver *driver = dev->driver; if (!driver) - return; + return 0; dev->error_state = pci_channel_io_normal; @@ -188,35 +192,39 @@ static void eeh_report_reset(struct pci_dev *dev, void *userdata) if (!driver->err_handler || !driver->err_handler->slot_reset) - return; + return 0; rc = driver->err_handler->slot_reset(dev); if ((*res == PCI_ERS_RESULT_NONE) || (*res == PCI_ERS_RESULT_RECOVERED)) *res = rc; if (*res == PCI_ERS_RESULT_DISCONNECT && rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; + + return 0; } /** * eeh_report_resume - tell device to resume normal operations */ -static void eeh_report_resume(struct pci_dev *dev, void *userdata) +static int eeh_report_resume(struct pci_dev *dev, void *userdata) { struct pci_driver *driver = dev->driver; dev->error_state = pci_channel_io_normal; if (!driver) - return; + return 0; eeh_enable_irq(dev); if (!driver->err_handler || !driver->err_handler->resume) - return; + return 0; driver->err_handler->resume(dev); + + return 0; } /** @@ -226,22 +234,24 @@ static void eeh_report_resume(struct pci_dev *dev, void *userdata) * dead, and that no further recovery attempts will be made on it. */ -static void eeh_report_failure(struct pci_dev *dev, void *userdata) +static int eeh_report_failure(struct pci_dev *dev, void *userdata) { struct pci_driver *driver = dev->driver; dev->error_state = pci_channel_io_perm_failure; if (!driver) - return; + return 0; eeh_disable_irq(dev); if (!driver->err_handler || !driver->err_handler->error_detected) - return; + return 0; driver->err_handler->error_detected(dev, pci_channel_io_perm_failure); + + return 0; } /* ------------------------------------------------------- */ diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c index 1a231c3..1f8f6cf 100644 --- a/arch/powerpc/platforms/pseries/smp.c +++ b/arch/powerpc/platforms/pseries/smp.c @@ -35,7 +35,6 @@ #include <asm/prom.h> #include <asm/smp.h> #include <asm/paca.h> -#include <asm/time.h> #include <asm/machdep.h> #include <asm/cputable.h> #include <asm/firmware.h> @@ -118,31 +117,6 @@ static void __devinit smp_xics_setup_cpu(int cpu) } #endif /* CONFIG_XICS */ -static DEFINE_SPINLOCK(timebase_lock); -static unsigned long timebase = 0; - -static void __devinit pSeries_give_timebase(void) -{ - spin_lock(&timebase_lock); - rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); - timebase = get_tb(); - spin_unlock(&timebase_lock); - - while (timebase) - barrier(); - rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); -} - -static void __devinit pSeries_take_timebase(void) -{ - while (!timebase) - barrier(); - spin_lock(&timebase_lock); - set_tb(timebase >> 32, timebase & 0xffffffff); - timebase = 0; - spin_unlock(&timebase_lock); -} - static void __devinit smp_pSeries_kick_cpu(int nr) { BUG_ON(nr < 0 || nr >= NR_CPUS); @@ -209,8 +183,8 @@ static void __init smp_init_pseries(void) /* Non-lpar has additional take/give timebase */ if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { - smp_ops->give_timebase = pSeries_give_timebase; - smp_ops->take_timebase = pSeries_take_timebase; + smp_ops->give_timebase = rtas_give_timebase; + smp_ops->take_timebase = rtas_take_timebase; } pr_debug(" <- smp_init_pSeries()\n"); diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile index 2d1c87d..9d4b174 100644 --- a/arch/powerpc/sysdev/Makefile +++ b/arch/powerpc/sysdev/Makefile @@ -1,3 +1,5 @@ +subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror + ifeq ($(CONFIG_PPC64),y) EXTRA_CFLAGS += -mno-minimal-toc endif @@ -48,6 +50,9 @@ obj-$(CONFIG_PPC_DCR) += dcr.o obj-$(CONFIG_8xx) += mpc8xx_pic.o cpm1.o obj-$(CONFIG_UCODE_PATCH) += micropatch.o +obj-$(CONFIG_PPC_MPC512x) += mpc5xxx_clocks.o +obj-$(CONFIG_PPC_MPC52xx) += mpc5xxx_clocks.o + ifeq ($(CONFIG_SUSPEND),y) obj-$(CONFIG_6xx) += 6xx-suspend.o endif diff --git a/arch/powerpc/sysdev/mpc5xxx_clocks.c b/arch/powerpc/sysdev/mpc5xxx_clocks.c new file mode 100644 index 0000000..34e12f9 --- /dev/null +++ b/arch/powerpc/sysdev/mpc5xxx_clocks.c @@ -0,0 +1,33 @@ +/** + * mpc5xxx_get_bus_frequency - Find the bus frequency for a device + * @node: device node + * + * Returns bus frequency (IPS on MPC512x, IPB on MPC52xx), + * or 0 if the bus frequency cannot be found. + */ + +#include <linux/kernel.h> +#include <linux/of_platform.h> + +unsigned int +mpc5xxx_get_bus_frequency(struct device_node *node) +{ + struct device_node *np; + const unsigned int *p_bus_freq = NULL; + + of_node_get(node); + while (node) { + p_bus_freq = of_get_property(node, "bus-frequency", NULL); + if (p_bus_freq) + break; + + np = of_get_parent(node); + of_node_put(node); + node = np; + } + if (node) + of_node_put(node); + + return p_bus_freq ? *p_bus_freq : 0; +} +EXPORT_SYMBOL(mpc5xxx_get_bus_frequency); diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 9c3af50..d46de1f 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -279,28 +279,29 @@ static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, } #ifdef CONFIG_PPC_DCR -static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, +static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, + struct mpic_reg_bank *rb, unsigned int offset, unsigned int size) { const u32 *dbasep; - dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL); + dbasep = of_get_property(node, "dcr-reg", NULL); - rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size); + rb->dhost = dcr_map(node, *dbasep + offset, size); BUG_ON(!DCR_MAP_OK(rb->dhost)); } -static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr, - struct mpic_reg_bank *rb, unsigned int offset, - unsigned int size) +static inline void mpic_map(struct mpic *mpic, struct device_node *node, + phys_addr_t phys_addr, struct mpic_reg_bank *rb, + unsigned int offset, unsigned int size) { if (mpic->flags & MPIC_USES_DCR) - _mpic_map_dcr(mpic, rb, offset, size); + _mpic_map_dcr(mpic, node, rb, offset, size); else _mpic_map_mmio(mpic, phys_addr, rb, offset, size); } #else /* CONFIG_PPC_DCR */ -#define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) +#define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) #endif /* !CONFIG_PPC_DCR */ @@ -1052,11 +1053,10 @@ struct mpic * __init mpic_alloc(struct device_node *node, int intvec_top; u64 paddr = phys_addr; - mpic = alloc_bootmem(sizeof(struct mpic)); + mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); if (mpic == NULL) return NULL; - - memset(mpic, 0, sizeof(struct mpic)); + mpic->name = name; mpic->hc_irq = mpic_irq_chip; @@ -1152,8 +1152,8 @@ struct mpic * __init mpic_alloc(struct device_node *node, } /* Map the global registers */ - mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); - mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); + mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); + mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); /* Reset */ if (flags & MPIC_WANTS_RESET) { @@ -1194,7 +1194,7 @@ struct mpic * __init mpic_alloc(struct device_node *node, /* Map the per-CPU registers */ for (i = 0; i < mpic->num_cpus; i++) { - mpic_map(mpic, paddr, &mpic->cpuregs[i], + mpic_map(mpic, node, paddr, &mpic->cpuregs[i], MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), 0x1000); } @@ -1202,7 +1202,7 @@ struct mpic * __init mpic_alloc(struct device_node *node, /* Initialize main ISU if none provided */ if (mpic->isu_size == 0) { mpic->isu_size = mpic->num_sources; - mpic_map(mpic, paddr, &mpic->isus[0], + mpic_map(mpic, node, paddr, &mpic->isus[0], MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); } mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); @@ -1256,8 +1256,10 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, BUG_ON(isu_num >= MPIC_MAX_ISU); - mpic_map(mpic, paddr, &mpic->isus[isu_num], 0, + mpic_map(mpic, mpic->irqhost->of_node, + paddr, &mpic->isus[isu_num], 0, MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); + if ((isu_first + mpic->isu_size) > mpic->num_sources) mpic->num_sources = isu_first + mpic->isu_size; } diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index b28b0e5..237e365 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c @@ -112,6 +112,7 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input) { unsigned long flags; u8 mcn_shift = 0, dev_shift = 0; + u32 ret; spin_lock_irqsave(&qe_lock, flags); if (cmd == QE_RESET) { @@ -139,11 +140,13 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input) } /* wait for the QE_CR_FLG to clear */ - while(in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) - cpu_relax(); + ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0, + 100, 0); + /* On timeout (e.g. failure), the expression will be false (ret == 0), + otherwise it will be true (ret == 1). */ spin_unlock_irqrestore(&qe_lock, flags); - return 0; + return ret == 1; } EXPORT_SYMBOL(qe_issue_cmd); diff --git a/arch/powerpc/xmon/Makefile b/arch/powerpc/xmon/Makefile index 9cb03b7..85ab97a 100644 --- a/arch/powerpc/xmon/Makefile +++ b/arch/powerpc/xmon/Makefile @@ -1,5 +1,7 @@ # Makefile for xmon +subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror + ifdef CONFIG_PPC64 EXTRA_CFLAGS += -mno-minimal-toc endif diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index a14dba0..e577839 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -94,6 +94,7 @@ config S390 select HAVE_KVM if 64BIT select HAVE_ARCH_TRACEHOOK select INIT_ALL_POSSIBLE + select HAVE_PERF_COUNTERS source "init/Kconfig" diff --git a/arch/s390/defconfig b/arch/s390/defconfig index d401d56..fcba206 100644 --- a/arch/s390/defconfig +++ b/arch/s390/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30-rc3 -# Thu Apr 23 09:29:52 2009 +# Linux kernel version: 2.6.30 +# Mon Jun 22 11:08:16 2009 # CONFIG_SCHED_MC=y CONFIG_MMU=y @@ -25,6 +25,7 @@ CONFIG_VIRT_CPU_ACCOUNTING=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_S390=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -90,7 +91,6 @@ CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y @@ -103,7 +103,14 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_COUNTERS=y + +# +# Performance Counters +# +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y # CONFIG_SLUB is not set @@ -119,6 +126,11 @@ CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_USE_GENERIC_SMP_HELPERS=y CONFIG_HAVE_DEFAULT_NO_SPIN_MUTEXES=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set # CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y @@ -150,7 +162,7 @@ CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" CONFIG_PREEMPT_NOTIFIERS=y -# CONFIG_FREEZER is not set +CONFIG_FREEZER=y # # Base setup @@ -199,6 +211,7 @@ CONFIG_ARCH_SPARSEMEM_DEFAULT=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_FLATMEM_MANUAL is not set # CONFIG_DISCONTIGMEM_MANUAL is not set @@ -218,9 +231,9 @@ CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y CONFIG_HAVE_MLOCK=y CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 # # I/O subsystem configuration @@ -257,6 +270,16 @@ CONFIG_KEXEC=y # CONFIG_ZFCPDUMP is not set CONFIG_S390_GUEST=y CONFIG_SECCOMP=y + +# +# Power Management +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_SLEEP=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="" CONFIG_NET=y # @@ -384,6 +407,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y # @@ -446,6 +470,7 @@ CONFIG_CAN_BCM=m # CAN Device Drivers # CONFIG_CAN_VCAN=m +# CONFIG_CAN_DEV is not set # CONFIG_CAN_DEBUG_DEVICES is not set # CONFIG_AF_RXRPC is not set # CONFIG_WIMAX is not set @@ -524,10 +549,6 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y @@ -578,7 +599,6 @@ CONFIG_DM_MULTIPATH=m # CONFIG_DM_DELAY is not set # CONFIG_DM_UEVENT is not set CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_IFB is not set CONFIG_DUMMY=m CONFIG_BONDING=m @@ -595,6 +615,7 @@ CONFIG_NET_ETHERNET=y # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_KS8842 is not set CONFIG_NETDEV_1000=y CONFIG_NETDEV_10000=y # CONFIG_TR is not set @@ -674,6 +695,11 @@ CONFIG_S390_TAPE_34XX=m # CONFIG_MONREADER is not set CONFIG_MONWRITER=m CONFIG_S390_VMUR=m + +# +# PPS support +# +# CONFIG_PPS is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set @@ -683,6 +709,10 @@ CONFIG_S390_VMUR=m # CONFIG_NEW_LEDS is not set CONFIG_ACCESSIBILITY=y # CONFIG_AUXDISPLAY is not set + +# +# TI VLYNQ +# # CONFIG_STAGING is not set # @@ -703,11 +733,12 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y -CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -865,19 +896,23 @@ CONFIG_DEBUG_MEMORY_INIT=y CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_DEBUG_PAGEALLOC is not set CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FTRACE_SYSCALLS=y CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# +CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_PREEMPT_TRACER is not set # CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set # CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set # CONFIG_STACK_TRACER is not set # CONFIG_KMEMTRACE is not set # CONFIG_WORKQUEUE_TRACER is not set @@ -886,6 +921,7 @@ CONFIG_TRACING_SUPPORT=y CONFIG_SAMPLES=y # CONFIG_SAMPLE_KOBJECT is not set # CONFIG_SAMPLE_KPROBES is not set +# CONFIG_KMEMCHECK is not set # # Security options diff --git a/arch/s390/include/asm/cputime.h b/arch/s390/include/asm/cputime.h index ec917d4..7a3817a 100644 --- a/arch/s390/include/asm/cputime.h +++ b/arch/s390/include/asm/cputime.h @@ -178,7 +178,7 @@ cputime64_to_clock_t(cputime64_t cputime) } struct s390_idle_data { - spinlock_t lock; + unsigned int sequence; unsigned long long idle_count; unsigned long long idle_enter; unsigned long long idle_time; diff --git a/arch/s390/include/asm/debug.h b/arch/s390/include/asm/debug.h index 9450ce6..31ed568 100644 --- a/arch/s390/include/asm/debug.h +++ b/arch/s390/include/asm/debug.h @@ -248,14 +248,5 @@ int debug_unregister_view(debug_info_t* id, struct debug_view* view); #define PRINT_FATAL(x...) printk ( KERN_DEBUG PRINTK_HEADER x ) #endif /* DASD_DEBUG */ -#undef DEBUG_MALLOC -#ifdef DEBUG_MALLOC -void *b; -#define kmalloc(x...) (PRINT_INFO(" kmalloc %p\n",b=kmalloc(x)),b) -#define kfree(x) PRINT_INFO(" kfree %p\n",x);kfree(x) -#define get_zeroed_page(x...) (PRINT_INFO(" gfp %p\n",b=get_zeroed_page(x)),b) -#define __get_free_pages(x...) (PRINT_INFO(" gfps %p\n",b=__get_free_pages(x)),b) -#endif /* DEBUG_MALLOC */ - #endif /* __KERNEL__ */ #endif /* DEBUG_H */ diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index a27d0d5..1cd02f6 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -99,7 +99,9 @@ struct kvm_s390_sie_block { __u8 reservedd0[48]; /* 0x00d0 */ __u64 gcr[16]; /* 0x0100 */ __u64 gbea; /* 0x0180 */ - __u8 reserved188[120]; /* 0x0188 */ + __u8 reserved188[24]; /* 0x0188 */ + __u32 fac; /* 0x01a0 */ + __u8 reserved1a4[92]; /* 0x01a4 */ } __attribute__((packed)); struct kvm_vcpu_stat { diff --git a/arch/s390/include/asm/perf_counter.h b/arch/s390/include/asm/perf_counter.h new file mode 100644 index 0000000..a7205a3 --- /dev/null +++ b/arch/s390/include/asm/perf_counter.h @@ -0,0 +1,8 @@ +/* + * Performance counter support - s390 specific definitions. + * + * Copyright 2009 Martin Schwidefsky, IBM Corporation. + */ + +static inline void set_perf_counter_pending(void) {} +static inline void clear_perf_counter_pending(void) {} diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h index 402d6dc..79d849f 100644 --- a/arch/s390/include/asm/qdio.h +++ b/arch/s390/include/asm/qdio.h @@ -380,7 +380,7 @@ extern int qdio_establish(struct qdio_initialize *); extern int qdio_activate(struct ccw_device *); extern int do_QDIO(struct ccw_device *cdev, unsigned int callflags, - int q_nr, int bufnr, int count); + int q_nr, unsigned int bufnr, unsigned int count); extern int qdio_cleanup(struct ccw_device*, int); extern int qdio_shutdown(struct ccw_device*, int); extern int qdio_free(struct ccw_device *); diff --git a/arch/s390/kernel/ftrace.c b/arch/s390/kernel/ftrace.c index 82ddfd3..3e298e6 100644 --- a/arch/s390/kernel/ftrace.c +++ b/arch/s390/kernel/ftrace.c @@ -190,7 +190,7 @@ unsigned long prepare_ftrace_return(unsigned long ip, unsigned long parent) goto out; if (unlikely(atomic_read(¤t->tracing_graph_pause))) goto out; - if (ftrace_push_return_trace(parent, ip, &trace.depth) == -EBUSY) + if (ftrace_push_return_trace(parent, ip, &trace.depth, 0) == -EBUSY) goto out; trace.func = ftrace_mcount_call_adjust(ip) & PSW_ADDR_INSN; /* Only trace if the calling function expects to. */ diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c index 9bb2f62..86783ef 100644 --- a/arch/s390/kernel/kprobes.c +++ b/arch/s390/kernel/kprobes.c @@ -154,39 +154,35 @@ void __kprobes get_instruction_type(struct arch_specific_insn *ainsn) static int __kprobes swap_instruction(void *aref) { + struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + unsigned long status = kcb->kprobe_status; struct ins_replace_args *args = aref; + int rc; - return probe_kernel_write(args->ptr, &args->new, sizeof(args->new)); + kcb->kprobe_status = KPROBE_SWAP_INST; + rc = probe_kernel_write(args->ptr, &args->new, sizeof(args->new)); + kcb->kprobe_status = status; + return rc; } void __kprobes arch_arm_kprobe(struct kprobe *p) { - struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); - unsigned long status = kcb->kprobe_status; struct ins_replace_args args; args.ptr = p->addr; args.old = p->opcode; args.new = BREAKPOINT_INSTRUCTION; - - kcb->kprobe_status = KPROBE_SWAP_INST; stop_machine(swap_instruction, &args, NULL); - kcb->kprobe_status = status; } void __kprobes arch_disarm_kprobe(struct kprobe *p) { - struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); - unsigned long status = kcb->kprobe_status; struct ins_replace_args args; args.ptr = p->addr; args.old = BREAKPOINT_INSTRUCTION; args.new = p->opcode; - - kcb->kprobe_status = KPROBE_SWAP_INST; stop_machine(swap_instruction, &args, NULL); - kcb->kprobe_status = status; } void __kprobes arch_remove_kprobe(struct kprobe *p) diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index fd8e311..2270730 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -856,13 +856,20 @@ static ssize_t show_idle_count(struct sys_device *dev, { struct s390_idle_data *idle; unsigned long long idle_count; + unsigned int sequence; idle = &per_cpu(s390_idle, dev->id); - spin_lock(&idle->lock); +repeat: + sequence = idle->sequence; + smp_rmb(); + if (sequence & 1) + goto repeat; idle_count = idle->idle_count; if (idle->idle_enter) idle_count++; - spin_unlock(&idle->lock); + smp_rmb(); + if (idle->sequence != sequence) + goto repeat; return sprintf(buf, "%llu\n", idle_count); } static SYSDEV_ATTR(idle_count, 0444, show_idle_count, NULL); @@ -872,15 +879,22 @@ static ssize_t show_idle_time(struct sys_device *dev, { struct s390_idle_data *idle; unsigned long long now, idle_time, idle_enter; + unsigned int sequence; idle = &per_cpu(s390_idle, dev->id); - spin_lock(&idle->lock); now = get_clock(); +repeat: + sequence = idle->sequence; + smp_rmb(); + if (sequence & 1) + goto repeat; idle_time = idle->idle_time; idle_enter = idle->idle_enter; if (idle_enter != 0ULL && idle_enter < now) idle_time += now - idle_enter; - spin_unlock(&idle->lock); + smp_rmb(); + if (idle->sequence != sequence) + goto repeat; return sprintf(buf, "%llu\n", idle_time >> 12); } static SYSDEV_ATTR(idle_time_us, 0444, show_idle_time, NULL); @@ -908,11 +922,7 @@ static int __cpuinit smp_cpu_notify(struct notifier_block *self, case CPU_ONLINE: case CPU_ONLINE_FROZEN: idle = &per_cpu(s390_idle, cpu); - spin_lock_irq(&idle->lock); - idle->idle_enter = 0; - idle->idle_time = 0; - idle->idle_count = 0; - spin_unlock_irq(&idle->lock); + memset(idle, 0, sizeof(struct s390_idle_data)); if (sysfs_create_group(&s->kobj, &cpu_online_attr_group)) return NOTIFY_BAD; break; diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c index 215330a..d4c8e9c 100644 --- a/arch/s390/kernel/time.c +++ b/arch/s390/kernel/time.c @@ -36,7 +36,6 @@ #include <linux/notifier.h> #include <linux/clocksource.h> #include <linux/clockchips.h> -#include <linux/bootmem.h> #include <asm/uaccess.h> #include <asm/delay.h> #include <asm/s390_ext.h> @@ -62,9 +61,6 @@ u64 sched_clock_base_cc = -1; /* Force to data section. */ -static ext_int_info_t ext_int_info_cc; -static ext_int_info_t ext_int_etr_cc; - static DEFINE_PER_CPU(struct clock_event_device, comparators); /* @@ -255,15 +251,11 @@ void __init time_init(void) stp_reset(); /* request the clock comparator external interrupt */ - if (register_early_external_interrupt(0x1004, - clock_comparator_interrupt, - &ext_int_info_cc) != 0) + if (register_external_interrupt(0x1004, clock_comparator_interrupt)) panic("Couldn't request external interrupt 0x1004"); /* request the timing alert external interrupt */ - if (register_early_external_interrupt(0x1406, - timing_alert_interrupt, - &ext_int_etr_cc) != 0) + if (register_external_interrupt(0x1406, timing_alert_interrupt)) panic("Couldn't request external interrupt 0x1406"); if (clocksource_register(&clocksource_tod) != 0) @@ -1445,14 +1437,14 @@ static void __init stp_reset(void) { int rc; - stp_page = alloc_bootmem_pages(PAGE_SIZE); + stp_page = (void *) get_zeroed_page(GFP_ATOMIC); rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); if (rc == 0) set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags); else if (stp_online) { pr_warning("The real or virtual hardware system does " "not provide an STP interface\n"); - free_bootmem((unsigned long) stp_page, PAGE_SIZE); + free_page((unsigned long) stp_page); stp_page = NULL; stp_online = 0; } diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c index c8eb725..c41bb0d 100644 --- a/arch/s390/kernel/vtime.c +++ b/arch/s390/kernel/vtime.c @@ -25,13 +25,9 @@ #include <asm/irq_regs.h> #include <asm/cputime.h> -static ext_int_info_t ext_int_info_timer; - static DEFINE_PER_CPU(struct vtimer_queue, virt_cpu_timer); -DEFINE_PER_CPU(struct s390_idle_data, s390_idle) = { - .lock = __SPIN_LOCK_UNLOCKED(s390_idle.lock) -}; +DEFINE_PER_CPU(struct s390_idle_data, s390_idle); static inline __u64 get_vtimer(void) { @@ -153,11 +149,13 @@ void vtime_start_cpu(void) vq->elapsed -= vq->idle - S390_lowcore.async_enter_timer; } - spin_lock(&idle->lock); + idle->sequence++; + smp_wmb(); idle->idle_time += idle_time; idle->idle_enter = 0ULL; idle->idle_count++; - spin_unlock(&idle->lock); + smp_wmb(); + idle->sequence++; } void vtime_stop_cpu(void) @@ -244,15 +242,23 @@ cputime64_t s390_get_idle_time(int cpu) { struct s390_idle_data *idle; unsigned long long now, idle_time, idle_enter; + unsigned int sequence; idle = &per_cpu(s390_idle, cpu); - spin_lock(&idle->lock); + now = get_clock(); +repeat: + sequence = idle->sequence; + smp_rmb(); + if (sequence & 1) + goto repeat; idle_time = 0; idle_enter = idle->idle_enter; if (idle_enter != 0ULL && idle_enter < now) idle_time = now - idle_enter; - spin_unlock(&idle->lock); + smp_rmb(); + if (idle->sequence != sequence) + goto repeat; return idle_time; } @@ -557,8 +563,7 @@ void init_cpu_vtimer(void) void __init vtime_init(void) { /* request the cpu timer external interrupt */ - if (register_early_external_interrupt(0x1005, do_cpu_timer_interrupt, - &ext_int_info_timer) != 0) + if (register_external_interrupt(0x1005, do_cpu_timer_interrupt)) panic("Couldn't request external interrupt 0x1005"); /* Enable cpu timer interrupts on the boot cpu. */ diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index c18b21d..90d9d1b 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -25,6 +25,7 @@ #include <asm/lowcore.h> #include <asm/pgtable.h> #include <asm/nmi.h> +#include <asm/system.h> #include "kvm-s390.h" #include "gaccess.h" @@ -69,6 +70,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = { { NULL } }; +static unsigned long long *facilities; /* Section: not file related */ void kvm_arch_hardware_enable(void *garbage) @@ -288,6 +290,7 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) vcpu->arch.sie_block->gmsor = vcpu->kvm->arch.guest_origin; vcpu->arch.sie_block->ecb = 2; vcpu->arch.sie_block->eca = 0xC1002001U; + vcpu->arch.sie_block->fac = (int) (long) facilities; hrtimer_init(&vcpu->arch.ckc_timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); tasklet_init(&vcpu->arch.tasklet, kvm_s390_tasklet, (unsigned long) vcpu); @@ -739,11 +742,29 @@ gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn) static int __init kvm_s390_init(void) { - return kvm_init(NULL, sizeof(struct kvm_vcpu), THIS_MODULE); + int ret; + ret = kvm_init(NULL, sizeof(struct kvm_vcpu), THIS_MODULE); + if (ret) + return ret; + + /* + * guests can ask for up to 255+1 double words, we need a full page + * to hold the maximum amount of facilites. On the other hand, we + * only set facilities that are known to work in KVM. + */ + facilities = (unsigned long long *) get_zeroed_page(GFP_DMA); + if (!facilities) { + kvm_exit(); + return -ENOMEM; + } + stfle(facilities, 1); + facilities[0] &= 0xff00fff3f0700000ULL; + return 0; } static void __exit kvm_s390_exit(void) { + free_page((unsigned long) facilities); kvm_exit(); } diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 93ecd06..d426aac 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -158,7 +158,7 @@ static int handle_stfl(struct kvm_vcpu *vcpu) vcpu->stat.instruction_stfl++; /* only pass the facility bits, which we can handle */ - facility_list &= 0xfe00fff3; + facility_list &= 0xff00fff3; rc = copy_to_guest(vcpu, offsetof(struct _lowcore, stfl_fac_list), &facility_list, sizeof(facility_list)); diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c index b0b84c3..cb5d59e 100644 --- a/arch/s390/lib/uaccess_pt.c +++ b/arch/s390/lib/uaccess_pt.c @@ -66,7 +66,7 @@ static int __handle_fault(struct mm_struct *mm, unsigned long address, } survive: - fault = handle_mm_fault(mm, vma, address, write_access); + fault = handle_mm_fault(mm, vma, address, write_access ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c index 220a152..74eb26b 100644 --- a/arch/s390/mm/fault.c +++ b/arch/s390/mm/fault.c @@ -352,7 +352,7 @@ good_area: * make sure we exit gracefully rather than endlessly redo * the fault. */ - fault = handle_mm_fault(mm, vma, address, write); + fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) { up_read(&mm->mmap_sem); diff --git a/arch/s390/power/swsusp_asm64.S b/arch/s390/power/swsusp_asm64.S index 3c74e7d..76d688d 100644 --- a/arch/s390/power/swsusp_asm64.S +++ b/arch/s390/power/swsusp_asm64.S @@ -109,10 +109,11 @@ swsusp_arch_resume: aghi %r15,-STACK_FRAME_OVERHEAD stg %r1,__SF_BACKCHAIN(%r15) +#ifdef CONFIG_SMP /* Save boot cpu number */ brasl %r14,smp_get_phys_cpu_id lgr %r10,%r2 - +#endif /* Deactivate DAT */ stnsm __SF_EMPTY(%r15),0xfb @@ -177,11 +178,12 @@ swsusp_arch_resume: /* Pointer to save arae */ lghi %r13,0x1000 +#ifdef CONFIG_SMP /* Switch CPUs */ lgr %r2,%r10 /* get cpu id */ llgf %r3,0x318(%r13) brasl %r14,smp_switch_boot_cpu_in_resume - +#endif /* Restore prefix register */ spx 0x318(%r13) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index ac1c620..e2bdd7b 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -15,7 +15,7 @@ config SUPERH select HAVE_IOREMAP_PROT if MMU select HAVE_ARCH_TRACEHOOK select HAVE_DMA_API_DEBUG - select HAVE_PERF_COUNTER + select HAVE_PERF_COUNTERS select RTC_LIB select GENERIC_ATOMIC64 help @@ -71,6 +71,9 @@ config GENERIC_HARDIRQS_NO__DO_IRQ config GENERIC_IRQ_PROBE def_bool y +config IRQ_PER_CPU + def_bool y + config GENERIC_GPIO def_bool n @@ -151,6 +154,9 @@ config ARCH_NO_VIRT_TO_BUS config ARCH_HAS_DEFAULT_IDLE def_bool y +config ARCH_HAS_CPU_IDLE_WAIT + def_bool y + config IO_TRAPPED bool @@ -411,6 +417,8 @@ config CPU_SUBTYPE_SH7786 select CPU_HAS_PTEAEX select ARCH_SPARSEMEM_ENABLE select SYS_SUPPORTS_NUMA + select SYS_SUPPORTS_SMP + select GENERIC_CLOCKEVENTS_BROADCAST if SMP config CPU_SUBTYPE_SHX3 bool "Support SH-X3 processor" @@ -648,7 +656,7 @@ config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 depends on SMP - default "4" if CPU_SHX3 + default "4" if CPU_SUBTYPE_SHX3 default "2" help This allows you to specify the maximum number of CPUs which this diff --git a/arch/sh/include/asm/dma-mapping.h b/arch/sh/include/asm/dma-mapping.h index ea9d4f4..69d56dd 100644 --- a/arch/sh/include/asm/dma-mapping.h +++ b/arch/sh/include/asm/dma-mapping.h @@ -97,7 +97,7 @@ static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, dma_unmap_single(dev, dma_address, size, dir); } -static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle, +static inline void __dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) { #if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT) @@ -119,7 +119,7 @@ static inline void dma_sync_single_range(struct device *dev, dma_cache_sync(dev, phys_to_virt(dma_handle) + offset, size, dir); } -static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg, +static inline void __dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction dir) { int i; @@ -137,7 +137,7 @@ static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) { - dma_sync_single(dev, dma_handle, size, dir); + __dma_sync_single(dev, dma_handle, size, dir); debug_dma_sync_single_for_cpu(dev, dma_handle, size, dir); } @@ -146,7 +146,7 @@ static inline void dma_sync_single_for_device(struct device *dev, size_t size, enum dma_data_direction dir) { - dma_sync_single(dev, dma_handle, size, dir); + __dma_sync_single(dev, dma_handle, size, dir); debug_dma_sync_single_for_device(dev, dma_handle, size, dir); } @@ -177,7 +177,7 @@ static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction dir) { - dma_sync_sg(dev, sg, nelems, dir); + __dma_sync_sg(dev, sg, nelems, dir); debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir); } @@ -185,7 +185,7 @@ static inline void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction dir) { - dma_sync_sg(dev, sg, nelems, dir); + __dma_sync_sg(dev, sg, nelems, dir); debug_dma_sync_sg_for_device(dev, sg, nelems, dir); } diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h index a88895e..ab79e1f 100644 --- a/arch/sh/include/asm/system.h +++ b/arch/sh/include/asm/system.h @@ -154,6 +154,7 @@ extern struct dentry *sh_debugfs_root; void per_cpu_trap_init(void); void default_idle(void); +void cpu_idle_wait(void); asmlinkage void break_point_trap(void); diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile index 96ea09c..ebdd391 100644 --- a/arch/sh/kernel/cpu/sh4a/Makefile +++ b/arch/sh/kernel/cpu/sh4a/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o # SMP setup -smp-$(CONFIG_CPU_SUBTYPE_SHX3) := smp-shx3.o +smp-$(CONFIG_CPU_SHX3) := smp-shx3.o # Primary on-chip clocks (common) clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o @@ -38,6 +38,6 @@ pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o -obj-y += $(clock-y) -obj-$(CONFIG_SMP) += $(smp-y) +obj-y += $(clock-y) +obj-$(CONFIG_SMP) += $(smp-y) obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index 93e0d2c..b700494 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c @@ -595,9 +595,8 @@ enum { HSPI, GPIO0, GPIO1, Thermal, - INTC0, INTC1, INTC2, INTC3, INTC4, INTC5, INTC6, INTC7, - - /* interrupt groups */ + INTICI0, INTICI1, INTICI2, INTICI3, + INTICI4, INTICI5, INTICI6, INTICI7, }; static struct intc_vect vectors[] __initdata = { @@ -638,10 +637,12 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(HSPI, 0xe80), INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0), INTC_VECT(Thermal, 0xee0), + INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20), + INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60), + INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0), + INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0), }; -/* FIXME: Main CPU support only now */ -#if 1 /* Main CPU */ #define CnINTMSK0 0xfe410030 #define CnINTMSK1 0xfe410040 #define CnINTMSKCLR0 0xfe410050 @@ -654,21 +655,6 @@ static struct intc_vect vectors[] __initdata = { #define CnINT2MSKCR1 0xfe410a34 #define CnINT2MSKCR2 0xfe410a38 #define CnINT2MSKCR3 0xfe410a3c -#else /* Sub CPU */ -#define CnINTMSK0 0xfe410034 -#define CnINTMSK1 0xfe410044 -#define CnINTMSKCLR0 0xfe410054 -#define CnINTMSKCLR1 0xfe410064 -#define CnINT2MSKR0 0xfe410b20 -#define CnINT2MSKR1 0xfe410b24 -#define CnINT2MSKR2 0xfe410b28 -#define CnINT2MSKR3 0xfe410b2c -#define CnINT2MSKCR0 0xfe410b30 -#define CnINT2MSKCR1 0xfe410b34 -#define CnINT2MSKCR2 0xfe410b38 -#define CnINT2MSKCR3 0xfe410b3c -#endif - #define INTMSK2 0xfe410068 #define INTMSKCLR2 0xfe41006c @@ -753,6 +739,9 @@ static struct intc_prio_reg prio_registers[] __initdata = { GPIO1, Thermal } }, { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } }, { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } }, + { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */ + { INTICI7, INTICI6, INTICI5, INTICI4, + INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) }, }; static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL, diff --git a/arch/sh/kernel/idle.c b/arch/sh/kernel/idle.c index f35ed03..27ff2dc 100644 --- a/arch/sh/kernel/idle.c +++ b/arch/sh/kernel/idle.c @@ -1,7 +1,7 @@ /* * The idle loop for all SuperH platforms. * - * Copyright (C) 2002 - 2008 Paul Mundt + * Copyright (C) 2002 - 2009 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -15,6 +15,7 @@ #include <linux/preempt.h> #include <linux/thread_info.h> #include <linux/irqflags.h> +#include <linux/smp.h> #include <asm/pgalloc.h> #include <asm/system.h> #include <asm/atomic.h> @@ -79,3 +80,23 @@ void cpu_idle(void) check_pgt_cache(); } } + +static void do_nothing(void *unused) +{ +} + +/* + * cpu_idle_wait - Used to ensure that all the CPUs discard old value of + * pm_idle and update to new pm_idle value. Required while changing pm_idle + * handler on SMP systems. + * + * Caller must have changed pm_idle to the new value before the call. Old + * pm_idle value will not be used by any CPU after the return of this function. + */ +void cpu_idle_wait(void) +{ + smp_mb(); + /* kick all the CPUs so that they exit out of pm_idle */ + smp_call_function(do_nothing, NULL, 1); +} +EXPORT_SYMBOL_GPL(cpu_idle_wait); diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c index 2c50f80..cc8ddbd 100644 --- a/arch/sh/mm/fault_32.c +++ b/arch/sh/mm/fault_32.c @@ -133,7 +133,7 @@ good_area: * the fault. */ survive: - fault = handle_mm_fault(mm, vma, address, writeaccess); + fault = handle_mm_fault(mm, vma, address, writeaccess ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c index ee8e6bb..fe532ae 100644 --- a/arch/sh/mm/init.c +++ b/arch/sh/mm/init.c @@ -70,7 +70,7 @@ static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot) } set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, prot)); - flush_tlb_one(get_asid(), addr); + local_flush_tlb_one(get_asid(), addr); } /* @@ -177,10 +177,8 @@ void __init paging_init(void) free_area_init_nodes(max_zone_pfns); -#ifdef CONFIG_SUPERH32 /* Set up the uncached fixmap */ set_fixmap_nocache(FIX_UNCACHED, __pa(&__uncached_start)); -#endif } static struct kcore_list kcore_mem, kcore_vmalloc; diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c index 7876997..fcbb6e1 100644 --- a/arch/sh/mm/tlbflush_64.c +++ b/arch/sh/mm/tlbflush_64.c @@ -187,7 +187,7 @@ good_area: * the fault. */ survive: - fault = handle_mm_fault(mm, vma, address, writeaccess); + fault = handle_mm_fault(mm, vma, address, writeaccess ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/sparc/boot/Makefile b/arch/sparc/boot/Makefile index 96041a8..1ff0fd9 100644 --- a/arch/sparc/boot/Makefile +++ b/arch/sparc/boot/Makefile @@ -15,7 +15,7 @@ quiet_cmd_elftoaout = ELFTOAOUT $@ ifeq ($(CONFIG_SPARC32),y) quiet_cmd_piggy = PIGGY $@ - cmd_piggy = $(obj)/piggyback_32 $@ $(obj)/System.map $(ROOT_IMG) + cmd_piggy = $(obj)/piggyback_32 $@ System.map $(ROOT_IMG) quiet_cmd_btfix = BTFIX $@ cmd_btfix = $(OBJDUMP) -x vmlinux | $(obj)/btfixupprep > $@ quiet_cmd_sysmap = SYSMAP $(obj)/System.map @@ -58,7 +58,7 @@ $(obj)/image: $(obj)/btfix.o FORCE $(obj)/zImage: $(obj)/image $(call if_changed,strip) -$(obj)/tftpboot.img: $(obj)/piggyback $(obj)/System.map $(obj)/image FORCE +$(obj)/tftpboot.img: $(obj)/image $(obj)/piggyback_32 System.map $(ROOT_IMG) FORCE $(call if_changed,elftoaout) $(call if_changed,piggy) @@ -79,7 +79,7 @@ $(obj)/image: vmlinux FORCE $(call if_changed,strip) @echo ' kernel: $@ is ready' -$(obj)/tftpboot.img: vmlinux $(obj)/piggyback_64 System.map $(ROOT_IMG) FORCE +$(obj)/tftpboot.img: $(obj)/image $(obj)/piggyback_64 System.map $(ROOT_IMG) FORCE $(call if_changed,elftoaout) $(call if_changed,piggy) @echo ' kernel: $@ is ready' diff --git a/arch/sparc/boot/piggyback_32.c b/arch/sparc/boot/piggyback_32.c index c9f500c..e8dc9ad 100644 --- a/arch/sparc/boot/piggyback_32.c +++ b/arch/sparc/boot/piggyback_32.c @@ -70,7 +70,7 @@ void die(char *str) int main(int argc,char **argv) { static char aout_magic[] = { 0x01, 0x03, 0x01, 0x07 }; - unsigned char buffer[1024], *q, *r; + char buffer[1024], *q, *r; unsigned int i, j, k, start, end, offset; FILE *map; struct stat s; @@ -84,7 +84,7 @@ int main(int argc,char **argv) while (fgets (buffer, 1024, map)) { if (!strcmp (buffer + 8, " T start\n") || !strcmp (buffer + 16, " T start\n")) start = strtoul (buffer, NULL, 16); - else if (!strcmp (buffer + 8, " A end\n") || !strcmp (buffer + 16, " A end\n")) + else if (!strcmp (buffer + 8, " A _end\n") || !strcmp (buffer + 16, " A _end\n")) end = strtoul (buffer, NULL, 16); } fclose (map); diff --git a/arch/sparc/boot/piggyback_64.c b/arch/sparc/boot/piggyback_64.c index de364bf..c63fd1b 100644 --- a/arch/sparc/boot/piggyback_64.c +++ b/arch/sparc/boot/piggyback_64.c @@ -46,6 +46,7 @@ int main(int argc,char **argv) struct stat s; int image, tail; + start = end = 0; if (stat (argv[3], &s) < 0) die (argv[3]); map = fopen (argv[2], "r"); if (!map) die(argv[2]); diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c index bd07505..f0ee790 100644 --- a/arch/sparc/kernel/irq_64.c +++ b/arch/sparc/kernel/irq_64.c @@ -20,7 +20,6 @@ #include <linux/delay.h> #include <linux/proc_fs.h> #include <linux/seq_file.h> -#include <linux/bootmem.h> #include <linux/irq.h> #include <asm/ptrace.h> @@ -914,25 +913,19 @@ void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu) tb->nonresum_qmask); } -static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask) -{ - unsigned long size = PAGE_ALIGN(qmask + 1); - void *p = __alloc_bootmem(size, size, 0); - if (!p) { - prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); - prom_halt(); - } - - *pa_ptr = __pa(p); -} - -static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask) +/* Each queue region must be a power of 2 multiple of 64 bytes in + * size. The base real address must be aligned to the size of the + * region. Thus, an 8KB queue must be 8KB aligned, for example. + */ +static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask) { unsigned long size = PAGE_ALIGN(qmask + 1); - void *p = __alloc_bootmem(size, size, 0); + unsigned long order = get_order(size); + unsigned long p; + p = __get_free_pages(GFP_KERNEL, order); if (!p) { - prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); + prom_printf("SUN4V: Error, cannot allocate queue.\n"); prom_halt(); } @@ -942,11 +935,11 @@ static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask) static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb) { #ifdef CONFIG_SMP - void *page; + unsigned long page; BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); - page = alloc_bootmem_pages(PAGE_SIZE); + page = get_zeroed_page(GFP_KERNEL); if (!page) { prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); prom_halt(); @@ -965,13 +958,13 @@ static void __init sun4v_init_mondo_queues(void) for_each_possible_cpu(cpu) { struct trap_per_cpu *tb = &trap_block[cpu]; - alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); - alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask); - alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask); - alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask); - alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask); - alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, - tb->nonresum_qmask); + alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); + alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask); + alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask); + alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask); + alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask); + alloc_one_queue(&tb->nonresum_kernel_buf_pa, + tb->nonresum_qmask); } } @@ -999,7 +992,7 @@ void __init init_IRQ(void) kill_prom_timer(); size = sizeof(struct ino_bucket) * NUM_IVECS; - ivector_table = alloc_bootmem(size); + ivector_table = kzalloc(size, GFP_KERNEL); if (!ivector_table) { prom_printf("Fatal error, cannot allocate ivector_table\n"); prom_halt(); diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c index 12e447f..a5e30c6 100644 --- a/arch/sparc/mm/fault_32.c +++ b/arch/sparc/mm/fault_32.c @@ -241,7 +241,7 @@ good_area: * make sure we exit gracefully rather than endlessly redo * the fault. */ - fault = handle_mm_fault(mm, vma, address, write); + fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; @@ -484,7 +484,7 @@ good_area: if(!(vma->vm_flags & (VM_READ | VM_EXEC))) goto bad_area; } - switch (handle_mm_fault(mm, vma, address, write)) { + switch (handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0)) { case VM_FAULT_SIGBUS: case VM_FAULT_OOM: goto do_sigbus; diff --git a/arch/sparc/mm/fault_64.c b/arch/sparc/mm/fault_64.c index 4ab8993..e5620b2 100644 --- a/arch/sparc/mm/fault_64.c +++ b/arch/sparc/mm/fault_64.c @@ -398,7 +398,7 @@ good_area: goto bad_area; } - fault = handle_mm_fault(mm, vma, address, (fault_code & FAULT_CODE_WRITE)); + fault = handle_mm_fault(mm, vma, address, (fault_code & FAULT_CODE_WRITE) ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c index ca92e2f..ed6be6b 100644 --- a/arch/sparc/mm/init_64.c +++ b/arch/sparc/mm/init_64.c @@ -1796,10 +1796,16 @@ void __init paging_init(void) prom_build_devicetree(); of_populate_present_mask(); +#ifndef CONFIG_SMP + of_fill_in_cpu_data(); +#endif if (tlb_type == hypervisor) { sun4v_mdesc_init(); mdesc_populate_present_mask(cpu_all_mask); +#ifndef CONFIG_SMP + mdesc_fill_in_cpu_data(cpu_all_mask); +#endif } /* Once the OF device tree and MDESC have been setup, we know diff --git a/arch/um/drivers/slip_kern.c b/arch/um/drivers/slip_kern.c index 5ec1756..dd2aadc 100644 --- a/arch/um/drivers/slip_kern.c +++ b/arch/um/drivers/slip_kern.c @@ -30,7 +30,6 @@ static void slip_init(struct net_device *dev, void *data) slip_proto_init(&spri->slip); - dev->init = NULL; dev->hard_header_len = 0; dev->header_ops = NULL; dev->addr_len = 0; diff --git a/arch/um/drivers/slirp_kern.c b/arch/um/drivers/slirp_kern.c index f15a6e7..e376284 100644 --- a/arch/um/drivers/slirp_kern.c +++ b/arch/um/drivers/slirp_kern.c @@ -32,7 +32,6 @@ void slirp_init(struct net_device *dev, void *data) slip_proto_init(&spri->slip); - dev->init = NULL; dev->hard_header_len = 0; dev->header_ops = NULL; dev->addr_len = 0; diff --git a/arch/um/include/asm/dma-mapping.h b/arch/um/include/asm/dma-mapping.h index 90fc708..378de4b 100644 --- a/arch/um/include/asm/dma-mapping.h +++ b/arch/um/include/asm/dma-mapping.h @@ -79,14 +79,14 @@ dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, } static inline void -dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size, +dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { BUG(); } static inline void -dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, +dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction) { BUG(); diff --git a/arch/um/kernel/trap.c b/arch/um/kernel/trap.c index 7384d8a..637c650 100644 --- a/arch/um/kernel/trap.c +++ b/arch/um/kernel/trap.c @@ -65,7 +65,7 @@ good_area: do { int fault; - fault = handle_mm_fault(mm, vma, address, is_write); + fault = handle_mm_fault(mm, vma, address, is_write ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) { goto out_of_memory; diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 73c0bda..d1430ef 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -34,6 +34,7 @@ config X86 select HAVE_DYNAMIC_FTRACE select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_GRAPH_TRACER + select HAVE_FUNCTION_GRAPH_FP_TEST select HAVE_FUNCTION_TRACE_MCOUNT_TEST select HAVE_FTRACE_NMI_ENTER if DYNAMIC_FTRACE select HAVE_FTRACE_SYSCALLS diff --git a/arch/x86/boot/bioscall.S b/arch/x86/boot/bioscall.S index 5077937..1dfbf64 100644 --- a/arch/x86/boot/bioscall.S +++ b/arch/x86/boot/bioscall.S @@ -13,7 +13,7 @@ * touching registers they shouldn't be. */ - .code16 + .code16gcc .text .globl intcall .type intcall, @function diff --git a/arch/x86/crypto/aesni-intel_asm.S b/arch/x86/crypto/aesni-intel_asm.S index caba996..eb0566e 100644 --- a/arch/x86/crypto/aesni-intel_asm.S +++ b/arch/x86/crypto/aesni-intel_asm.S @@ -845,7 +845,7 @@ ENTRY(aesni_cbc_enc) */ ENTRY(aesni_cbc_dec) cmp $16, LEN - jb .Lcbc_dec_ret + jb .Lcbc_dec_just_ret mov 480(KEYP), KLEN add $240, KEYP movups (IVP), IV @@ -891,6 +891,7 @@ ENTRY(aesni_cbc_dec) add $16, OUTP cmp $16, LEN jge .Lcbc_dec_loop1 - movups IV, (IVP) .Lcbc_dec_ret: + movups IV, (IVP) +.Lcbc_dec_just_ret: ret diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c index 4e66339..c580c5e 100644 --- a/arch/x86/crypto/aesni-intel_glue.c +++ b/arch/x86/crypto/aesni-intel_glue.c @@ -198,6 +198,7 @@ static int ecb_encrypt(struct blkcipher_desc *desc, blkcipher_walk_init(&walk, dst, src, nbytes); err = blkcipher_walk_virt(desc, &walk); + desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; kernel_fpu_begin(); while ((nbytes = walk.nbytes)) { @@ -221,6 +222,7 @@ static int ecb_decrypt(struct blkcipher_desc *desc, blkcipher_walk_init(&walk, dst, src, nbytes); err = blkcipher_walk_virt(desc, &walk); + desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; kernel_fpu_begin(); while ((nbytes = walk.nbytes)) { @@ -266,6 +268,7 @@ static int cbc_encrypt(struct blkcipher_desc *desc, blkcipher_walk_init(&walk, dst, src, nbytes); err = blkcipher_walk_virt(desc, &walk); + desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; kernel_fpu_begin(); while ((nbytes = walk.nbytes)) { @@ -289,6 +292,7 @@ static int cbc_decrypt(struct blkcipher_desc *desc, blkcipher_walk_init(&walk, dst, src, nbytes); err = blkcipher_walk_virt(desc, &walk); + desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; kernel_fpu_begin(); while ((nbytes = walk.nbytes)) { diff --git a/arch/x86/crypto/fpu.c b/arch/x86/crypto/fpu.c index 5f9781a..daef6cd 100644 --- a/arch/x86/crypto/fpu.c +++ b/arch/x86/crypto/fpu.c @@ -48,7 +48,7 @@ static int crypto_fpu_encrypt(struct blkcipher_desc *desc_in, struct blkcipher_desc desc = { .tfm = child, .info = desc_in->info, - .flags = desc_in->flags, + .flags = desc_in->flags & ~CRYPTO_TFM_REQ_MAY_SLEEP, }; kernel_fpu_begin(); @@ -67,7 +67,7 @@ static int crypto_fpu_decrypt(struct blkcipher_desc *desc_in, struct blkcipher_desc desc = { .tfm = child, .info = desc_in->info, - .flags = desc_in->flags, + .flags = desc_in->flags & ~CRYPTO_TFM_REQ_MAY_SLEEP, }; kernel_fpu_begin(); diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 4518dc5..20d1465 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -144,6 +144,7 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) #else /* !CONFIG_ACPI */ +#define acpi_disabled 1 #define acpi_lapic 0 #define acpi_ioapic 0 static inline void acpi_noirq_set(void) { } diff --git a/arch/x86/include/asm/amd_iommu.h b/arch/x86/include/asm/amd_iommu.h index 262e028..bdf96f1 100644 --- a/arch/x86/include/asm/amd_iommu.h +++ b/arch/x86/include/asm/amd_iommu.h @@ -29,9 +29,11 @@ extern void amd_iommu_detect(void); extern irqreturn_t amd_iommu_int_handler(int irq, void *data); extern void amd_iommu_flush_all_domains(void); extern void amd_iommu_flush_all_devices(void); +extern void amd_iommu_shutdown(void); #else static inline int amd_iommu_init(void) { return -ENODEV; } static inline void amd_iommu_detect(void) { } +static inline void amd_iommu_shutdown(void) { } #endif #endif /* _ASM_X86_AMD_IOMMU_H */ diff --git a/arch/x86/include/asm/atomic_32.h b/arch/x86/include/asm/atomic_32.h index 8cb9c81..2503d4e 100644 --- a/arch/x86/include/asm/atomic_32.h +++ b/arch/x86/include/asm/atomic_32.h @@ -257,7 +257,7 @@ typedef struct { /** * atomic64_read - read atomic64 variable - * @v: pointer of type atomic64_t + * @ptr: pointer of type atomic64_t * * Atomically reads the value of @v. * Doesn't imply a read memory barrier. @@ -294,7 +294,6 @@ atomic64_cmpxchg(atomic64_t *ptr, unsigned long long old_val, * atomic64_xchg - xchg atomic64 variable * @ptr: pointer to type atomic64_t * @new_val: value to assign - * @old_val: old value that was there * * Atomically xchgs the value of @ptr to @new_val and returns * the old value. diff --git a/arch/x86/include/asm/boot.h b/arch/x86/include/asm/boot.h index 418e632..7a10659 100644 --- a/arch/x86/include/asm/boot.h +++ b/arch/x86/include/asm/boot.h @@ -8,7 +8,7 @@ #ifdef __KERNEL__ -#include <asm/page_types.h> +#include <asm/pgtable_types.h> /* Physical address where kernel should be loaded. */ #define LOAD_PHYSICAL_ADDR ((CONFIG_PHYSICAL_START \ @@ -16,10 +16,10 @@ & ~(CONFIG_PHYSICAL_ALIGN - 1)) /* Minimum kernel alignment, as a power of two */ -#ifdef CONFIG_x86_64 +#ifdef CONFIG_X86_64 #define MIN_KERNEL_ALIGN_LG2 PMD_SHIFT #else -#define MIN_KERNEL_ALIGN_LG2 (PAGE_SHIFT+1) +#define MIN_KERNEL_ALIGN_LG2 (PAGE_SHIFT + THREAD_ORDER) #endif #define MIN_KERNEL_ALIGN (_AC(1, UL) << MIN_KERNEL_ALIGN_LG2) diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h index c45f415..c993e9e 100644 --- a/arch/x86/include/asm/desc.h +++ b/arch/x86/include/asm/desc.h @@ -1,7 +1,6 @@ #ifndef _ASM_X86_DESC_H #define _ASM_X86_DESC_H -#ifndef __ASSEMBLY__ #include <asm/desc_defs.h> #include <asm/ldt.h> #include <asm/mmu.h> @@ -380,29 +379,4 @@ static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist) _set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS); } -#else -/* - * GET_DESC_BASE reads the descriptor base of the specified segment. - * - * Args: - * idx - descriptor index - * gdt - GDT pointer - * base - 32bit register to which the base will be written - * lo_w - lo word of the "base" register - * lo_b - lo byte of the "base" register - * hi_b - hi byte of the low word of the "base" register - * - * Example: - * GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah) - * Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax. - */ -#define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \ - movb idx * 8 + 4(gdt), lo_b; \ - movb idx * 8 + 7(gdt), hi_b; \ - shll $16, base; \ - movw idx * 8 + 2(gdt), lo_w; - - -#endif /* __ASSEMBLY__ */ - #endif /* _ASM_X86_DESC_H */ diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h index af326a2..fd6d21b 100644 --- a/arch/x86/include/asm/iommu.h +++ b/arch/x86/include/asm/iommu.h @@ -6,6 +6,7 @@ extern void no_iommu_init(void); extern struct dma_map_ops nommu_dma_ops; extern int force_iommu, no_iommu; extern int iommu_detected; +extern int iommu_pass_through; /* 10 seconds */ #define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 540a466..5cdd8d1 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -102,15 +102,39 @@ struct mce_log { #ifdef __KERNEL__ +#include <linux/percpu.h> +#include <linux/init.h> +#include <asm/atomic.h> + extern int mce_disabled; +extern int mce_p5_enabled; -#include <asm/atomic.h> -#include <linux/percpu.h> +#ifdef CONFIG_X86_MCE +void mcheck_init(struct cpuinfo_x86 *c); +#else +static inline void mcheck_init(struct cpuinfo_x86 *c) {} +#endif + +#ifdef CONFIG_X86_OLD_MCE +extern int nr_mce_banks; +void amd_mcheck_init(struct cpuinfo_x86 *c); +void intel_p4_mcheck_init(struct cpuinfo_x86 *c); +void intel_p6_mcheck_init(struct cpuinfo_x86 *c); +#endif + +#ifdef CONFIG_X86_ANCIENT_MCE +void intel_p5_mcheck_init(struct cpuinfo_x86 *c); +void winchip_mcheck_init(struct cpuinfo_x86 *c); +static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } +#else +static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} +static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} +static inline void enable_p5_mce(void) {} +#endif void mce_setup(struct mce *m); void mce_log(struct mce *m); DECLARE_PER_CPU(struct sys_device, mce_dev); -extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); /* * To support more than 128 would need to escape the predefined @@ -145,12 +169,8 @@ int mce_available(struct cpuinfo_x86 *c); DECLARE_PER_CPU(unsigned, mce_exception_count); DECLARE_PER_CPU(unsigned, mce_poll_count); -void mce_log_therm_throt_event(__u64 status); - extern atomic_t mce_entry; -void do_machine_check(struct pt_regs *, long); - typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); @@ -167,13 +187,32 @@ void mce_notify_process(void); DECLARE_PER_CPU(struct mce, injectm); extern struct file_operations mce_chrdev_ops; -#ifdef CONFIG_X86_MCE -void mcheck_init(struct cpuinfo_x86 *c); -#else -#define mcheck_init(c) do { } while (0) -#endif +/* + * Exception handler + */ + +/* Call the installed machine check handler for this CPU setup. */ +extern void (*machine_check_vector)(struct pt_regs *, long error_code); +void do_machine_check(struct pt_regs *, long); + +/* + * Threshold handler + */ extern void (*mce_threshold_vector)(void); +extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); + +/* + * Thermal handler + */ + +void intel_init_thermal(struct cpuinfo_x86 *c); + +#ifdef CONFIG_X86_NEW_MCE +void mce_log_therm_throt_event(__u64 status); +#else +static inline void mce_log_therm_throt_event(__u64 status) {} +#endif #endif /* __KERNEL__ */ #endif /* _ASM_X86_MCE_H */ diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 2260376..48ad9d2 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -3,13 +3,10 @@ #include <asm/msr-index.h> -#ifndef __ASSEMBLY__ -# include <linux/types.h> -#endif - #ifdef __KERNEL__ #ifndef __ASSEMBLY__ +#include <linux/types.h> #include <asm/asm.h> #include <asm/errno.h> #include <asm/cpumask.h> @@ -264,6 +261,4 @@ static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) #endif /* CONFIG_SMP */ #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ - - #endif /* _ASM_X86_MSR_H */ diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h index 8d382d3..7639dbf 100644 --- a/arch/x86/include/asm/page_64_types.h +++ b/arch/x86/include/asm/page_64_types.h @@ -41,7 +41,7 @@ /* See Documentation/x86/x86_64/mm.txt for a description of the memory map. */ #define __PHYSICAL_MASK_SHIFT 46 -#define __VIRTUAL_MASK_SHIFT 48 +#define __VIRTUAL_MASK_SHIFT 47 /* * Kernel image size is limited to 512 MB (see level2_kernel_pgt in diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index b51a1e8..927958d 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -130,6 +130,7 @@ extern void pci_iommu_alloc(void); /* generic pci stuff */ #include <asm-generic/pci.h> +#define PCIBIOS_MAX_MEM_32 0xffffffff #ifdef CONFIG_NUMA /* Returns the node based on pci bus */ diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index e60fd3e..b399988 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -121,6 +121,9 @@ extern int __init pcibios_init(void); extern int __init pci_mmcfg_arch_init(void); extern void __init pci_mmcfg_arch_free(void); +extern struct acpi_mcfg_allocation *pci_mmcfg_config; +extern int pci_mmcfg_config_num; + /* * AMD Fam10h CPUs are buggy, and cannot access MMIO config space * on their northbrige except through the * %eax register. As such, you MUST diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h index 02ecb30..103f1dd 100644 --- a/arch/x86/include/asm/percpu.h +++ b/arch/x86/include/asm/percpu.h @@ -42,6 +42,7 @@ #else /* ...!ASSEMBLY */ +#include <linux/kernel.h> #include <linux/stringify.h> #ifdef CONFIG_SMP @@ -155,6 +156,15 @@ do { \ /* We can use this directly for local CPU (faster). */ DECLARE_PER_CPU(unsigned long, this_cpu_off); +#ifdef CONFIG_NEED_MULTIPLE_NODES +void *pcpu_lpage_remapped(void *kaddr); +#else +static inline void *pcpu_lpage_remapped(void *kaddr) +{ + return NULL; +} +#endif + #endif /* !__ASSEMBLY__ */ #ifdef CONFIG_SMP diff --git a/arch/x86/include/asm/perf_counter.h b/arch/x86/include/asm/perf_counter.h index 876ed97..5fb33e1 100644 --- a/arch/x86/include/asm/perf_counter.h +++ b/arch/x86/include/asm/perf_counter.h @@ -84,11 +84,6 @@ union cpuid10_edx { #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b #define X86_PMC_IDX_FIXED_BUS_CYCLES (X86_PMC_IDX_FIXED + 2) -extern void set_perf_counter_pending(void); - -#define clear_perf_counter_pending() do { } while (0) -#define test_perf_counter_pending() (0) - #ifdef CONFIG_PERF_COUNTERS extern void init_hw_perf_counters(void); extern void perf_counters_lapic_init(void); diff --git a/arch/x86/include/asm/pgtable_32.h b/arch/x86/include/asm/pgtable_32.h index 31bd120..01fd946 100644 --- a/arch/x86/include/asm/pgtable_32.h +++ b/arch/x86/include/asm/pgtable_32.h @@ -49,13 +49,17 @@ extern void set_pmd_pfn(unsigned long, unsigned long, pgprot_t); #endif #if defined(CONFIG_HIGHPTE) +#define __KM_PTE \ + (in_nmi() ? KM_NMI_PTE : \ + in_irq() ? KM_IRQ_PTE : \ + KM_PTE0) #define pte_offset_map(dir, address) \ - ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)), KM_PTE0) + \ + ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)), __KM_PTE) + \ pte_index((address))) #define pte_offset_map_nested(dir, address) \ ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)), KM_PTE1) + \ pte_index((address))) -#define pte_unmap(pte) kunmap_atomic((pte), KM_PTE0) +#define pte_unmap(pte) kunmap_atomic((pte), __KM_PTE) #define pte_unmap_nested(pte) kunmap_atomic((pte), KM_PTE1) #else #define pte_offset_map(dir, address) \ diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h index abde308..c57a301 100644 --- a/arch/x86/include/asm/pgtable_64.h +++ b/arch/x86/include/asm/pgtable_64.h @@ -165,10 +165,7 @@ extern void cleanup_highmap(void); /* fs/proc/kcore.c */ #define kc_vaddr_to_offset(v) ((v) & __VIRTUAL_MASK) -#define kc_offset_to_vaddr(o) \ - (((o) & (1UL << (__VIRTUAL_MASK_SHIFT - 1))) \ - ? ((o) | ~__VIRTUAL_MASK) \ - : (o)) +#define kc_offset_to_vaddr(o) ((o) | ~__VIRTUAL_MASK) #define __HAVE_ARCH_PTE_SAME #endif /* !__ASSEMBLY__ */ diff --git a/arch/x86/include/asm/therm_throt.h b/arch/x86/include/asm/therm_throt.h deleted file mode 100644 index c62349e..0000000 --- a/arch/x86/include/asm/therm_throt.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _ASM_X86_THERM_THROT_H -#define _ASM_X86_THERM_THROT_H - -#include <asm/atomic.h> - -extern atomic_t therm_throt_en; -int therm_throt_process(int curr); - -#endif /* _ASM_X86_THERM_THROT_H */ diff --git a/arch/x86/include/asm/timer.h b/arch/x86/include/asm/timer.h index bd37ed4..20ca9c4 100644 --- a/arch/x86/include/asm/timer.h +++ b/arch/x86/include/asm/timer.h @@ -45,12 +45,16 @@ extern int no_timer_check; */ DECLARE_PER_CPU(unsigned long, cyc2ns); +DECLARE_PER_CPU(unsigned long long, cyc2ns_offset); #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ static inline unsigned long long __cycles_2_ns(unsigned long long cyc) { - return cyc * per_cpu(cyc2ns, smp_processor_id()) >> CYC2NS_SCALE_FACTOR; + int cpu = smp_processor_id(); + unsigned long long ns = per_cpu(cyc2ns_offset, cpu); + ns += cyc * per_cpu(cyc2ns, cpu) >> CYC2NS_SCALE_FACTOR; + return ns; } static inline unsigned long long cycles_2_ns(unsigned long long cyc) diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h index b685ece..20e6a79 100644 --- a/arch/x86/include/asm/uaccess.h +++ b/arch/x86/include/asm/uaccess.h @@ -25,7 +25,7 @@ #define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) #define KERNEL_DS MAKE_MM_SEG(-1UL) -#define USER_DS MAKE_MM_SEG(PAGE_OFFSET) +#define USER_DS MAKE_MM_SEG(TASK_SIZE_MAX) #define get_ds() (KERNEL_DS) #define get_fs() (current_thread_info()->addr_limit) diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 6310861..6b8ca3a 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -44,11 +44,7 @@ static int __initdata acpi_force = 0; u32 acpi_rsdt_forced; -#ifdef CONFIG_ACPI -int acpi_disabled = 0; -#else -int acpi_disabled = 1; -#endif +int acpi_disabled; EXPORT_SYMBOL(acpi_disabled); #ifdef CONFIG_X86_64 @@ -122,72 +118,6 @@ void __init __acpi_unmap_table(char *map, unsigned long size) early_iounmap(map, size); } -#ifdef CONFIG_PCI_MMCONFIG - -static int acpi_mcfg_64bit_base_addr __initdata = FALSE; - -/* The physical address of the MMCONFIG aperture. Set from ACPI tables. */ -struct acpi_mcfg_allocation *pci_mmcfg_config; -int pci_mmcfg_config_num; - -static int __init acpi_mcfg_oem_check(struct acpi_table_mcfg *mcfg) -{ - if (!strcmp(mcfg->header.oem_id, "SGI")) - acpi_mcfg_64bit_base_addr = TRUE; - - return 0; -} - -int __init acpi_parse_mcfg(struct acpi_table_header *header) -{ - struct acpi_table_mcfg *mcfg; - unsigned long i; - int config_size; - - if (!header) - return -EINVAL; - - mcfg = (struct acpi_table_mcfg *)header; - - /* how many config structures do we have */ - pci_mmcfg_config_num = 0; - i = header->length - sizeof(struct acpi_table_mcfg); - while (i >= sizeof(struct acpi_mcfg_allocation)) { - ++pci_mmcfg_config_num; - i -= sizeof(struct acpi_mcfg_allocation); - }; - if (pci_mmcfg_config_num == 0) { - printk(KERN_ERR PREFIX "MMCONFIG has no entries\n"); - return -ENODEV; - } - - config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config); - pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL); - if (!pci_mmcfg_config) { - printk(KERN_WARNING PREFIX - "No memory for MCFG config tables\n"); - return -ENOMEM; - } - - memcpy(pci_mmcfg_config, &mcfg[1], config_size); - - acpi_mcfg_oem_check(mcfg); - - for (i = 0; i < pci_mmcfg_config_num; ++i) { - if ((pci_mmcfg_config[i].address > 0xFFFFFFFF) && - !acpi_mcfg_64bit_base_addr) { - printk(KERN_ERR PREFIX - "MMCONFIG not in low 4GB of memory\n"); - kfree(pci_mmcfg_config); - pci_mmcfg_config_num = 0; - return -ENODEV; - } - } - - return 0; -} -#endif /* CONFIG_PCI_MMCONFIG */ - #ifdef CONFIG_X86_LOCAL_APIC static int __init acpi_parse_madt(struct acpi_table_header *table) { @@ -1519,14 +1449,6 @@ static struct dmi_system_id __initdata acpi_dmi_table[] = { }, { .callback = force_acpi_ht, - .ident = "ASUS P4B266", - .matches = { - DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), - DMI_MATCH(DMI_BOARD_NAME, "P4B266"), - }, - }, - { - .callback = force_acpi_ht, .ident = "ASUS P2B-DS", .matches = { DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c index bbbe4bb..8c44c23 100644 --- a/arch/x86/kernel/acpi/cstate.c +++ b/arch/x86/kernel/acpi/cstate.c @@ -34,12 +34,22 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, flags->bm_check = 1; else if (c->x86_vendor == X86_VENDOR_INTEL) { /* - * Today all CPUs that support C3 share cache. - * TBD: This needs to look at cache shared map, once - * multi-core detection patch makes to the base. + * Today all MP CPUs that support C3 share cache. + * And caches should not be flushed by software while + * entering C3 type state. */ flags->bm_check = 1; } + + /* + * On all recent Intel platforms, ARB_DISABLE is a nop. + * So, set bm_control to zero to indicate that ARB_DISABLE + * is not required while entering C3 type state on + * P4, Core and beyond CPUs + */ + if (c->x86_vendor == X86_VENDOR_INTEL && + (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 14))) + flags->bm_control = 0; } EXPORT_SYMBOL(acpi_processor_power_init_bm_check); diff --git a/arch/x86/kernel/acpi/processor.c b/arch/x86/kernel/acpi/processor.c index 7c074ee..d296f4a 100644 --- a/arch/x86/kernel/acpi/processor.c +++ b/arch/x86/kernel/acpi/processor.c @@ -72,6 +72,7 @@ static void init_intel_pdc(struct acpi_processor *pr, struct cpuinfo_x86 *c) return; } + /* Initialize _PDC data based on the CPU vendor */ void arch_acpi_processor_init_pdc(struct acpi_processor *pr) { @@ -85,3 +86,15 @@ void arch_acpi_processor_init_pdc(struct acpi_processor *pr) } EXPORT_SYMBOL(arch_acpi_processor_init_pdc); + +void arch_acpi_processor_cleanup_pdc(struct acpi_processor *pr) +{ + if (pr->pdc) { + kfree(pr->pdc->pointer->buffer.pointer); + kfree(pr->pdc->pointer); + kfree(pr->pdc); + pr->pdc = NULL; + } +} + +EXPORT_SYMBOL(arch_acpi_processor_cleanup_pdc); diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c index 1c60554..9372f04 100644 --- a/arch/x86/kernel/amd_iommu.c +++ b/arch/x86/kernel/amd_iommu.c @@ -434,6 +434,16 @@ static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); } +/* Flush the whole IO/TLB for a given protection domain - including PDE */ +static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid) +{ + u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; + + INC_STATS_COUNTER(domain_flush_single); + + iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1); +} + /* * This function is used to flush the IO/TLB for a given protection domain * on every IOMMU in the system @@ -1078,7 +1088,13 @@ static void attach_device(struct amd_iommu *iommu, amd_iommu_pd_table[devid] = domain; write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); + /* + * We might boot into a crash-kernel here. The crashed kernel + * left the caches in the IOMMU dirty. So we have to flush + * here to evict all dirty stuff. + */ iommu_queue_inv_dev_entry(iommu, devid); + iommu_flush_tlb_pde(iommu, domain->id); } /* diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c index 238989e..10b2acc 100644 --- a/arch/x86/kernel/amd_iommu_init.c +++ b/arch/x86/kernel/amd_iommu_init.c @@ -260,6 +260,14 @@ static void iommu_enable(struct amd_iommu *iommu) static void iommu_disable(struct amd_iommu *iommu) { + /* Disable command buffer */ + iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); + + /* Disable event logging and event interrupts */ + iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); + iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); + + /* Disable IOMMU hardware itself */ iommu_feature_disable(iommu, CONTROL_IOMMU_EN); } @@ -478,6 +486,10 @@ static void iommu_enable_event_buffer(struct amd_iommu *iommu) memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, &entry, sizeof(entry)); + /* set head and tail to zero manually */ + writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); + writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); + iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); } @@ -1042,6 +1054,7 @@ static void enable_iommus(void) struct amd_iommu *iommu; for_each_iommu(iommu) { + iommu_disable(iommu); iommu_set_device_table(iommu); iommu_enable_command_buffer(iommu); iommu_enable_event_buffer(iommu); @@ -1066,12 +1079,6 @@ static void disable_iommus(void) static int amd_iommu_resume(struct sys_device *dev) { - /* - * Disable IOMMUs before reprogramming the hardware registers. - * IOMMU is still enabled from the resume kernel. - */ - disable_iommus(); - /* re-load the hardware */ enable_iommus(); @@ -1079,8 +1086,8 @@ static int amd_iommu_resume(struct sys_device *dev) * we have to flush after the IOMMUs are enabled because a * disabled IOMMU will never execute the commands we send */ - amd_iommu_flush_all_domains(); amd_iommu_flush_all_devices(); + amd_iommu_flush_all_domains(); return 0; } @@ -1273,6 +1280,11 @@ free: goto out; } +void amd_iommu_shutdown(void) +{ + disable_iommus(); +} + /**************************************************************************** * * Early detect code. This code runs at IOMMU detection time in the DMA diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index ef8d929..4d0216f 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -462,7 +462,8 @@ static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) { - union entry_union eu; + union entry_union eu = {{0, 0}}; + eu.entry = e; io_apic_write(apic, 0x11 + 2*pin, eu.w2); io_apic_write(apic, 0x10 + 2*pin, eu.w1); @@ -1413,6 +1414,9 @@ int setup_ioapic_entry(int apic_id, int irq, irte.vector = vector; irte.dest_id = IRTE_DEST(destination); + /* Set source-id of interrupt request */ + set_ioapic_sid(&irte, apic_id); + modify_irte(irq, &irte); ir_entry->index2 = (index >> 15) & 0x1; @@ -2003,7 +2007,9 @@ void disable_IO_APIC(void) /* * Use virtual wire A mode when interrupt remapping is enabled. */ - disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1); + if (cpu_has_apic) + disconnect_bsp_APIC(!intr_remapping_enabled && + ioapic_i8259.pin != -1); } #ifdef CONFIG_X86_32 @@ -3287,6 +3293,9 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms irte.vector = cfg->vector; irte.dest_id = IRTE_DEST(dest); + /* Set source-id of interrupt request */ + set_msi_sid(&irte, pdev); + modify_irte(irq, &irte); msg->address_hi = MSI_ADDR_BASE_HI; @@ -3567,7 +3576,7 @@ static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) #endif /* CONFIG_SMP */ -struct irq_chip dmar_msi_type = { +static struct irq_chip dmar_msi_type = { .name = "DMAR_MSI", .unmask = dmar_msi_unmask, .mask = dmar_msi_mask, diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c index 440a8bc..0c0182c 100644 --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -20,23 +20,12 @@ #include <asm/apic.h> #include <asm/setup.h> -#include <linux/threads.h> -#include <linux/cpumask.h> -#include <asm/mpspec.h> -#include <asm/fixmap.h> -#include <asm/apicdef.h> -#include <linux/kernel.h> -#include <linux/string.h> #include <linux/smp.h> -#include <linux/init.h> #include <asm/ipi.h> -#include <linux/smp.h> -#include <linux/init.h> #include <linux/interrupt.h> #include <asm/acpi.h> #include <asm/e820.h> -#include <asm/setup.h> #ifdef CONFIG_HOTPLUG_CPU #define DEFAULT_SEND_IPI (1) diff --git a/arch/x86/kernel/apic/summit_32.c b/arch/x86/kernel/apic/summit_32.c index 344eee4..eafdfbd1 100644 --- a/arch/x86/kernel/apic/summit_32.c +++ b/arch/x86/kernel/apic/summit_32.c @@ -44,7 +44,6 @@ #include <asm/ipi.h> #include <linux/kernel.h> #include <linux/string.h> -#include <linux/init.h> #include <linux/gfp.h> #include <linux/smp.h> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index e5b27d8..28e5f59 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -258,13 +258,15 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) { #ifdef CONFIG_X86_HT unsigned bits; + int cpu = smp_processor_id(); bits = c->x86_coreid_bits; - /* Low order bits define the core id (index of core in socket) */ c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); /* Convert the initial APIC ID into the socket ID */ c->phys_proc_id = c->initial_apicid >> bits; + /* use socket ID also for last level cache */ + per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; #endif } diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9fa3388..f1961c0 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -108,7 +108,7 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { /* data */ [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, - [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, + [GDT_ENTRY_ESPFIX_SS] = { { { 0x0000ffff, 0x00cf9200 } } }, [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, GDT_STACK_CANARY_INIT #endif diff --git a/arch/x86/kernel/cpu/mcheck/Makefile b/arch/x86/kernel/cpu/mcheck/Makefile index 45004fa..188a1ca 100644 --- a/arch/x86/kernel/cpu/mcheck/Makefile +++ b/arch/x86/kernel/cpu/mcheck/Makefile @@ -1,11 +1,12 @@ -obj-y = mce.o therm_throt.o +obj-y = mce.o obj-$(CONFIG_X86_NEW_MCE) += mce-severity.o obj-$(CONFIG_X86_OLD_MCE) += k7.o p4.o p6.o obj-$(CONFIG_X86_ANCIENT_MCE) += winchip.o p5.o -obj-$(CONFIG_X86_MCE_P4THERMAL) += mce_intel.o -obj-$(CONFIG_X86_MCE_INTEL) += mce_intel_64.o mce_intel.o -obj-$(CONFIG_X86_MCE_AMD) += mce_amd_64.o +obj-$(CONFIG_X86_MCE_INTEL) += mce_intel.o +obj-$(CONFIG_X86_MCE_AMD) += mce_amd.o obj-$(CONFIG_X86_MCE_NONFATAL) += non-fatal.o obj-$(CONFIG_X86_MCE_THRESHOLD) += threshold.o obj-$(CONFIG_X86_MCE_INJECT) += mce-inject.o + +obj-$(CONFIG_X86_THERMAL_VECTOR) += therm_throt.o diff --git a/arch/x86/kernel/cpu/mcheck/k7.c b/arch/x86/kernel/cpu/mcheck/k7.c index 89e5104..b945d5d 100644 --- a/arch/x86/kernel/cpu/mcheck/k7.c +++ b/arch/x86/kernel/cpu/mcheck/k7.c @@ -10,10 +10,9 @@ #include <asm/processor.h> #include <asm/system.h> +#include <asm/mce.h> #include <asm/msr.h> -#include "mce.h" - /* Machine Check Handler For AMD Athlon/Duron: */ static void k7_machine_check(struct pt_regs *regs, long error_code) { diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index fabba15..af425b8 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -44,7 +44,6 @@ #include <asm/msr.h> #include "mce-internal.h" -#include "mce.h" /* Handle unconfigured int18 (should never happen) */ static void unexpected_machine_check(struct pt_regs *regs, long error_code) @@ -57,7 +56,7 @@ static void unexpected_machine_check(struct pt_regs *regs, long error_code) void (*machine_check_vector)(struct pt_regs *, long error_code) = unexpected_machine_check; -int mce_disabled; +int mce_disabled __read_mostly; #ifdef CONFIG_X86_NEW_MCE @@ -76,21 +75,22 @@ DEFINE_PER_CPU(unsigned, mce_exception_count); * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors * 3: never panic or SIGBUS, log all errors (for testing only) */ -static int tolerant = 1; -static int banks; -static u64 *bank; -static unsigned long notify_user; -static int rip_msr; -static int mce_bootlog = -1; -static int monarch_timeout = -1; -static int mce_panic_timeout; -static int mce_dont_log_ce; -int mce_cmci_disabled; -int mce_ignore_ce; -int mce_ser; - -static char trigger[128]; -static char *trigger_argv[2] = { trigger, NULL }; +static int tolerant __read_mostly = 1; +static int banks __read_mostly; +static u64 *bank __read_mostly; +static int rip_msr __read_mostly; +static int mce_bootlog __read_mostly = -1; +static int monarch_timeout __read_mostly = -1; +static int mce_panic_timeout __read_mostly; +static int mce_dont_log_ce __read_mostly; +int mce_cmci_disabled __read_mostly; +int mce_ignore_ce __read_mostly; +int mce_ser __read_mostly; + +/* User mode helper program triggered by machine check event */ +static unsigned long mce_need_notify; +static char mce_helper[128]; +static char *mce_helper_argv[2] = { mce_helper, NULL }; static unsigned long dont_init_banks; @@ -180,7 +180,7 @@ void mce_log(struct mce *mce) wmb(); mce->finished = 1; - set_bit(0, ¬ify_user); + set_bit(0, &mce_need_notify); } static void print_mce(struct mce *m) @@ -691,18 +691,21 @@ static atomic_t global_nwo; * in the entry order. * TBD double check parallel CPU hotunplug */ -static int mce_start(int no_way_out, int *order) +static int mce_start(int *no_way_out) { - int nwo; + int order; int cpus = num_online_cpus(); u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; - if (!timeout) { - *order = -1; - return no_way_out; - } + if (!timeout) + return -1; - atomic_add(no_way_out, &global_nwo); + atomic_add(*no_way_out, &global_nwo); + /* + * global_nwo should be updated before mce_callin + */ + smp_wmb(); + order = atomic_add_return(1, &mce_callin); /* * Wait for everyone. @@ -710,40 +713,43 @@ static int mce_start(int no_way_out, int *order) while (atomic_read(&mce_callin) != cpus) { if (mce_timed_out(&timeout)) { atomic_set(&global_nwo, 0); - *order = -1; - return no_way_out; + return -1; } ndelay(SPINUNIT); } /* - * Cache the global no_way_out state. + * mce_callin should be read before global_nwo */ - nwo = atomic_read(&global_nwo); + smp_rmb(); - /* - * Monarch starts executing now, the others wait. - */ - if (*order == 1) { + if (order == 1) { + /* + * Monarch: Starts executing now, the others wait. + */ atomic_set(&mce_executing, 1); - return nwo; + } else { + /* + * Subject: Now start the scanning loop one by one in + * the original callin order. + * This way when there are any shared banks it will be + * only seen by one CPU before cleared, avoiding duplicates. + */ + while (atomic_read(&mce_executing) < order) { + if (mce_timed_out(&timeout)) { + atomic_set(&global_nwo, 0); + return -1; + } + ndelay(SPINUNIT); + } } /* - * Now start the scanning loop one by one - * in the original callin order. - * This way when there are any shared banks it will - * be only seen by one CPU before cleared, avoiding duplicates. + * Cache the global no_way_out state. */ - while (atomic_read(&mce_executing) < *order) { - if (mce_timed_out(&timeout)) { - atomic_set(&global_nwo, 0); - *order = -1; - return no_way_out; - } - ndelay(SPINUNIT); - } - return nwo; + *no_way_out = atomic_read(&global_nwo); + + return order; } /* @@ -863,7 +869,6 @@ void do_machine_check(struct pt_regs *regs, long error_code) * check handler. */ int order; - /* * If no_way_out gets set, there is no safe way to recover from this * MCE. If tolerant is cranked up, we'll try anyway. @@ -887,7 +892,6 @@ void do_machine_check(struct pt_regs *regs, long error_code) if (!banks) goto out; - order = atomic_add_return(1, &mce_callin); mce_setup(&m); m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); @@ -909,7 +913,7 @@ void do_machine_check(struct pt_regs *regs, long error_code) * This way we don't report duplicated events on shared banks * because the first one to see it will clear it. */ - no_way_out = mce_start(no_way_out, &order); + order = mce_start(&no_way_out); for (i = 0; i < banks; i++) { __clear_bit(i, toclear); if (!bank[i]) @@ -1113,12 +1117,12 @@ static void mcheck_timer(unsigned long data) *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); t->expires = jiffies + *n; - add_timer(t); + add_timer_on(t, smp_processor_id()); } static void mce_do_trigger(struct work_struct *work) { - call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT); + call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); } static DECLARE_WORK(mce_trigger_work, mce_do_trigger); @@ -1135,7 +1139,7 @@ int mce_notify_irq(void) clear_thread_flag(TIF_MCE_NOTIFY); - if (test_and_clear_bit(0, ¬ify_user)) { + if (test_and_clear_bit(0, &mce_need_notify)) { wake_up_interruptible(&mce_wait); /* @@ -1143,7 +1147,7 @@ int mce_notify_irq(void) * work_pending is always cleared before the function is * executed. */ - if (trigger[0] && !work_pending(&mce_trigger_work)) + if (mce_helper[0] && !work_pending(&mce_trigger_work)) schedule_work(&mce_trigger_work); if (__ratelimit(&ratelimit)) @@ -1245,7 +1249,7 @@ static void mce_cpu_quirks(struct cpuinfo_x86 *c) * Various K7s with broken bank 0 around. Always disable * by default. */ - if (c->x86 == 6) + if (c->x86 == 6 && banks > 0) bank[0] = 0; } @@ -1282,8 +1286,7 @@ static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) return; switch (c->x86_vendor) { case X86_VENDOR_INTEL: - if (mce_p5_enabled()) - intel_p5_mcheck_init(c); + intel_p5_mcheck_init(c); break; case X86_VENDOR_CENTAUR: winchip_mcheck_init(c); @@ -1318,7 +1321,7 @@ static void mce_init_timer(void) return; setup_timer(t, mcheck_timer, smp_processor_id()); t->expires = round_jiffies(jiffies + *n); - add_timer(t); + add_timer_on(t, smp_processor_id()); } /* @@ -1609,8 +1612,9 @@ static int mce_resume(struct sys_device *dev) static void mce_cpu_restart(void *data) { del_timer_sync(&__get_cpu_var(mce_timer)); - if (mce_available(¤t_cpu_data)) - mce_init(); + if (!mce_available(¤t_cpu_data)) + return; + mce_init(); mce_init_timer(); } @@ -1620,6 +1624,26 @@ static void mce_restart(void) on_each_cpu(mce_cpu_restart, NULL, 1); } +/* Toggle features for corrected errors */ +static void mce_disable_ce(void *all) +{ + if (!mce_available(¤t_cpu_data)) + return; + if (all) + del_timer_sync(&__get_cpu_var(mce_timer)); + cmci_clear(); +} + +static void mce_enable_ce(void *all) +{ + if (!mce_available(¤t_cpu_data)) + return; + cmci_reenable(); + cmci_recheck(); + if (all) + mce_init_timer(); +} + static struct sysdev_class mce_sysclass = { .suspend = mce_suspend, .shutdown = mce_shutdown, @@ -1659,9 +1683,9 @@ static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, static ssize_t show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) { - strcpy(buf, trigger); + strcpy(buf, mce_helper); strcat(buf, "\n"); - return strlen(trigger) + 1; + return strlen(mce_helper) + 1; } static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, @@ -1670,10 +1694,10 @@ static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *p; int len; - strncpy(trigger, buf, sizeof(trigger)); - trigger[sizeof(trigger)-1] = 0; - len = strlen(trigger); - p = strchr(trigger, '\n'); + strncpy(mce_helper, buf, sizeof(mce_helper)); + mce_helper[sizeof(mce_helper)-1] = 0; + len = strlen(mce_helper); + p = strchr(mce_helper, '\n'); if (*p) *p = 0; @@ -1681,6 +1705,52 @@ static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, return len; } +static ssize_t set_ignore_ce(struct sys_device *s, + struct sysdev_attribute *attr, + const char *buf, size_t size) +{ + u64 new; + + if (strict_strtoull(buf, 0, &new) < 0) + return -EINVAL; + + if (mce_ignore_ce ^ !!new) { + if (new) { + /* disable ce features */ + on_each_cpu(mce_disable_ce, (void *)1, 1); + mce_ignore_ce = 1; + } else { + /* enable ce features */ + mce_ignore_ce = 0; + on_each_cpu(mce_enable_ce, (void *)1, 1); + } + } + return size; +} + +static ssize_t set_cmci_disabled(struct sys_device *s, + struct sysdev_attribute *attr, + const char *buf, size_t size) +{ + u64 new; + + if (strict_strtoull(buf, 0, &new) < 0) + return -EINVAL; + + if (mce_cmci_disabled ^ !!new) { + if (new) { + /* disable cmci */ + on_each_cpu(mce_disable_ce, NULL, 1); + mce_cmci_disabled = 1; + } else { + /* enable cmci */ + mce_cmci_disabled = 0; + on_each_cpu(mce_enable_ce, NULL, 1); + } + } + return size; +} + static ssize_t store_int_with_restart(struct sys_device *s, struct sysdev_attribute *attr, const char *buf, size_t size) @@ -1693,6 +1763,7 @@ static ssize_t store_int_with_restart(struct sys_device *s, static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); +static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); static struct sysdev_ext_attribute attr_check_interval = { _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, @@ -1700,9 +1771,24 @@ static struct sysdev_ext_attribute attr_check_interval = { &check_interval }; +static struct sysdev_ext_attribute attr_ignore_ce = { + _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), + &mce_ignore_ce +}; + +static struct sysdev_ext_attribute attr_cmci_disabled = { + _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), + &mce_cmci_disabled +}; + static struct sysdev_attribute *mce_attrs[] = { - &attr_tolerant.attr, &attr_check_interval.attr, &attr_trigger, + &attr_tolerant.attr, + &attr_check_interval.attr, + &attr_trigger, &attr_monarch_timeout.attr, + &attr_dont_log_ce.attr, + &attr_ignore_ce.attr, + &attr_cmci_disabled.attr, NULL }; @@ -1712,7 +1798,7 @@ static cpumask_var_t mce_dev_initialized; static __cpuinit int mce_create_device(unsigned int cpu) { int err; - int i; + int i, j; if (!mce_available(&boot_cpu_data)) return -EIO; @@ -1730,9 +1816,9 @@ static __cpuinit int mce_create_device(unsigned int cpu) if (err) goto error; } - for (i = 0; i < banks; i++) { + for (j = 0; j < banks; j++) { err = sysdev_create_file(&per_cpu(mce_dev, cpu), - &bank_attrs[i]); + &bank_attrs[j]); if (err) goto error2; } @@ -1740,8 +1826,8 @@ static __cpuinit int mce_create_device(unsigned int cpu) return 0; error2: - while (--i >= 0) - sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); + while (--j >= 0) + sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[j]); error: while (--i >= 0) sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); @@ -1883,7 +1969,7 @@ static __init int mce_init_device(void) if (!mce_available(&boot_cpu_data)) return -EIO; - alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); + zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); err = mce_init_banks(); if (err) @@ -1915,7 +2001,7 @@ EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ /* This has to be run for each processor */ void mcheck_init(struct cpuinfo_x86 *c) { - if (mce_disabled == 1) + if (mce_disabled) return; switch (c->x86_vendor) { @@ -1945,10 +2031,9 @@ void mcheck_init(struct cpuinfo_x86 *c) static int __init mcheck_enable(char *str) { - mce_disabled = -1; + mce_p5_enabled = 1; return 1; } - __setup("mce", mcheck_enable); #endif /* CONFIG_X86_OLD_MCE */ diff --git a/arch/x86/kernel/cpu/mcheck/mce.h b/arch/x86/kernel/cpu/mcheck/mce.h deleted file mode 100644 index 84a552b..0000000 --- a/arch/x86/kernel/cpu/mcheck/mce.h +++ /dev/null @@ -1,38 +0,0 @@ -#include <linux/init.h> -#include <asm/mce.h> - -#ifdef CONFIG_X86_OLD_MCE -void amd_mcheck_init(struct cpuinfo_x86 *c); -void intel_p4_mcheck_init(struct cpuinfo_x86 *c); -void intel_p6_mcheck_init(struct cpuinfo_x86 *c); -#endif - -#ifdef CONFIG_X86_ANCIENT_MCE -void intel_p5_mcheck_init(struct cpuinfo_x86 *c); -void winchip_mcheck_init(struct cpuinfo_x86 *c); -extern int mce_p5_enable; -static inline int mce_p5_enabled(void) { return mce_p5_enable; } -static inline void enable_p5_mce(void) { mce_p5_enable = 1; } -#else -static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} -static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} -static inline int mce_p5_enabled(void) { return 0; } -static inline void enable_p5_mce(void) { } -#endif - -/* Call the installed machine check handler for this CPU setup. */ -extern void (*machine_check_vector)(struct pt_regs *, long error_code); - -#ifdef CONFIG_X86_OLD_MCE - -extern int nr_mce_banks; - -void intel_set_thermal_handler(void); - -#else - -static inline void intel_set_thermal_handler(void) { } - -#endif - -void intel_init_thermal(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index ddae216..ddae216 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c index 2b011d2..e1acec0f 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c @@ -1,74 +1,226 @@ /* - * Common code for Intel machine checks + * Intel specific MCE features. + * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca> + * Copyright (C) 2008, 2009 Intel Corporation + * Author: Andi Kleen */ -#include <linux/interrupt.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/smp.h> -#include <asm/therm_throt.h> -#include <asm/processor.h> -#include <asm/system.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/percpu.h> #include <asm/apic.h> +#include <asm/processor.h> #include <asm/msr.h> +#include <asm/mce.h> + +/* + * Support for Intel Correct Machine Check Interrupts. This allows + * the CPU to raise an interrupt when a corrected machine check happened. + * Normally we pick those up using a regular polling timer. + * Also supports reliable discovery of shared banks. + */ -#include "mce.h" +static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned); -void intel_init_thermal(struct cpuinfo_x86 *c) +/* + * cmci_discover_lock protects against parallel discovery attempts + * which could race against each other. + */ +static DEFINE_SPINLOCK(cmci_discover_lock); + +#define CMCI_THRESHOLD 1 + +static int cmci_supported(int *banks) { - unsigned int cpu = smp_processor_id(); - int tm2 = 0; - u32 l, h; + u64 cap; - /* Thermal monitoring depends on ACPI and clock modulation*/ - if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC)) - return; + if (mce_cmci_disabled || mce_ignore_ce) + return 0; /* - * First check if its enabled already, in which case there might - * be some SMM goo which handles it, so we can't even put a handler - * since it might be delivered via SMI already: + * Vendor check is not strictly needed, but the initial + * initialization is vendor keyed and this + * makes sure none of the backdoors are entered otherwise. */ - rdmsr(MSR_IA32_MISC_ENABLE, l, h); - h = apic_read(APIC_LVTTHMR); - if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) { - printk(KERN_DEBUG - "CPU%d: Thermal monitoring handled by SMI\n", cpu); - return; + if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) + return 0; + if (!cpu_has_apic || lapic_get_maxlvt() < 6) + return 0; + rdmsrl(MSR_IA32_MCG_CAP, cap); + *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff); + return !!(cap & MCG_CMCI_P); +} + +/* + * The interrupt handler. This is called on every event. + * Just call the poller directly to log any events. + * This could in theory increase the threshold under high load, + * but doesn't for now. + */ +static void intel_threshold_interrupt(void) +{ + machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); + mce_notify_irq(); +} + +static void print_update(char *type, int *hdr, int num) +{ + if (*hdr == 0) + printk(KERN_INFO "CPU %d MCA banks", smp_processor_id()); + *hdr = 1; + printk(KERN_CONT " %s:%d", type, num); +} + +/* + * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks + * on this CPU. Use the algorithm recommended in the SDM to discover shared + * banks. + */ +static void cmci_discover(int banks, int boot) +{ + unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned); + unsigned long flags; + int hdr = 0; + int i; + + spin_lock_irqsave(&cmci_discover_lock, flags); + for (i = 0; i < banks; i++) { + u64 val; + + if (test_bit(i, owned)) + continue; + + rdmsrl(MSR_IA32_MC0_CTL2 + i, val); + + /* Already owned by someone else? */ + if (val & CMCI_EN) { + if (test_and_clear_bit(i, owned) || boot) + print_update("SHD", &hdr, i); + __clear_bit(i, __get_cpu_var(mce_poll_banks)); + continue; + } + + val |= CMCI_EN | CMCI_THRESHOLD; + wrmsrl(MSR_IA32_MC0_CTL2 + i, val); + rdmsrl(MSR_IA32_MC0_CTL2 + i, val); + + /* Did the enable bit stick? -- the bank supports CMCI */ + if (val & CMCI_EN) { + if (!test_and_set_bit(i, owned) || boot) + print_update("CMCI", &hdr, i); + __clear_bit(i, __get_cpu_var(mce_poll_banks)); + } else { + WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks))); + } } + spin_unlock_irqrestore(&cmci_discover_lock, flags); + if (hdr) + printk(KERN_CONT "\n"); +} + +/* + * Just in case we missed an event during initialization check + * all the CMCI owned banks. + */ +void cmci_recheck(void) +{ + unsigned long flags; + int banks; + + if (!mce_available(¤t_cpu_data) || !cmci_supported(&banks)) + return; + local_irq_save(flags); + machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); + local_irq_restore(flags); +} - if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2)) - tm2 = 1; +/* + * Disable CMCI on this CPU for all banks it owns when it goes down. + * This allows other CPUs to claim the banks on rediscovery. + */ +void cmci_clear(void) +{ + unsigned long flags; + int i; + int banks; + u64 val; - /* Check whether a vector already exists */ - if (h & APIC_VECTOR_MASK) { - printk(KERN_DEBUG - "CPU%d: Thermal LVT vector (%#x) already installed\n", - cpu, (h & APIC_VECTOR_MASK)); + if (!cmci_supported(&banks)) return; + spin_lock_irqsave(&cmci_discover_lock, flags); + for (i = 0; i < banks; i++) { + if (!test_bit(i, __get_cpu_var(mce_banks_owned))) + continue; + /* Disable CMCI */ + rdmsrl(MSR_IA32_MC0_CTL2 + i, val); + val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK); + wrmsrl(MSR_IA32_MC0_CTL2 + i, val); + __clear_bit(i, __get_cpu_var(mce_banks_owned)); } + spin_unlock_irqrestore(&cmci_discover_lock, flags); +} + +/* + * After a CPU went down cycle through all the others and rediscover + * Must run in process context. + */ +void cmci_rediscover(int dying) +{ + int banks; + int cpu; + cpumask_var_t old; + + if (!cmci_supported(&banks)) + return; + if (!alloc_cpumask_var(&old, GFP_KERNEL)) + return; + cpumask_copy(old, ¤t->cpus_allowed); - /* We'll mask the thermal vector in the lapic till we're ready: */ - h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED; - apic_write(APIC_LVTTHMR, h); + for_each_online_cpu(cpu) { + if (cpu == dying) + continue; + if (set_cpus_allowed_ptr(current, cpumask_of(cpu))) + continue; + /* Recheck banks in case CPUs don't all have the same */ + if (cmci_supported(&banks)) + cmci_discover(banks, 0); + } - rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); - wrmsr(MSR_IA32_THERM_INTERRUPT, - l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h); + set_cpus_allowed_ptr(current, old); + free_cpumask_var(old); +} - intel_set_thermal_handler(); +/* + * Reenable CMCI on this CPU in case a CPU down failed. + */ +void cmci_reenable(void) +{ + int banks; + if (cmci_supported(&banks)) + cmci_discover(banks, 0); +} - rdmsr(MSR_IA32_MISC_ENABLE, l, h); - wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); +static void intel_init_cmci(void) +{ + int banks; - /* Unmask the thermal vector: */ - l = apic_read(APIC_LVTTHMR); - apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED); + if (!cmci_supported(&banks)) + return; - printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n", - cpu, tm2 ? "TM2" : "TM1"); + mce_threshold_vector = intel_threshold_interrupt; + cmci_discover(banks, 1); + /* + * For CPU #0 this runs with still disabled APIC, but that's + * ok because only the vector is set up. We still do another + * check for the banks later for CPU #0 just to make sure + * to not miss any events. + */ + apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED); + cmci_recheck(); +} - /* enable thermal throttle processing */ - atomic_set(&therm_throt_en, 1); +void mce_intel_feature_init(struct cpuinfo_x86 *c) +{ + intel_init_thermal(c); + intel_init_cmci(); } diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c deleted file mode 100644 index f2ef695..0000000 --- a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * Intel specific MCE features. - * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca> - * Copyright (C) 2008, 2009 Intel Corporation - * Author: Andi Kleen - */ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/percpu.h> -#include <asm/processor.h> -#include <asm/apic.h> -#include <asm/msr.h> -#include <asm/mce.h> -#include <asm/hw_irq.h> -#include <asm/idle.h> -#include <asm/therm_throt.h> - -#include "mce.h" - -asmlinkage void smp_thermal_interrupt(void) -{ - __u64 msr_val; - - ack_APIC_irq(); - - exit_idle(); - irq_enter(); - - rdmsrl(MSR_IA32_THERM_STATUS, msr_val); - if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT)) - mce_log_therm_throt_event(msr_val); - - inc_irq_stat(irq_thermal_count); - irq_exit(); -} - -/* - * Support for Intel Correct Machine Check Interrupts. This allows - * the CPU to raise an interrupt when a corrected machine check happened. - * Normally we pick those up using a regular polling timer. - * Also supports reliable discovery of shared banks. - */ - -static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned); - -/* - * cmci_discover_lock protects against parallel discovery attempts - * which could race against each other. - */ -static DEFINE_SPINLOCK(cmci_discover_lock); - -#define CMCI_THRESHOLD 1 - -static int cmci_supported(int *banks) -{ - u64 cap; - - if (mce_cmci_disabled || mce_ignore_ce) - return 0; - - /* - * Vendor check is not strictly needed, but the initial - * initialization is vendor keyed and this - * makes sure none of the backdoors are entered otherwise. - */ - if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) - return 0; - if (!cpu_has_apic || lapic_get_maxlvt() < 6) - return 0; - rdmsrl(MSR_IA32_MCG_CAP, cap); - *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff); - return !!(cap & MCG_CMCI_P); -} - -/* - * The interrupt handler. This is called on every event. - * Just call the poller directly to log any events. - * This could in theory increase the threshold under high load, - * but doesn't for now. - */ -static void intel_threshold_interrupt(void) -{ - machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); - mce_notify_irq(); -} - -static void print_update(char *type, int *hdr, int num) -{ - if (*hdr == 0) - printk(KERN_INFO "CPU %d MCA banks", smp_processor_id()); - *hdr = 1; - printk(KERN_CONT " %s:%d", type, num); -} - -/* - * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks - * on this CPU. Use the algorithm recommended in the SDM to discover shared - * banks. - */ -static void cmci_discover(int banks, int boot) -{ - unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned); - unsigned long flags; - int hdr = 0; - int i; - - spin_lock_irqsave(&cmci_discover_lock, flags); - for (i = 0; i < banks; i++) { - u64 val; - - if (test_bit(i, owned)) - continue; - - rdmsrl(MSR_IA32_MC0_CTL2 + i, val); - - /* Already owned by someone else? */ - if (val & CMCI_EN) { - if (test_and_clear_bit(i, owned) || boot) - print_update("SHD", &hdr, i); - __clear_bit(i, __get_cpu_var(mce_poll_banks)); - continue; - } - - val |= CMCI_EN | CMCI_THRESHOLD; - wrmsrl(MSR_IA32_MC0_CTL2 + i, val); - rdmsrl(MSR_IA32_MC0_CTL2 + i, val); - - /* Did the enable bit stick? -- the bank supports CMCI */ - if (val & CMCI_EN) { - if (!test_and_set_bit(i, owned) || boot) - print_update("CMCI", &hdr, i); - __clear_bit(i, __get_cpu_var(mce_poll_banks)); - } else { - WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks))); - } - } - spin_unlock_irqrestore(&cmci_discover_lock, flags); - if (hdr) - printk(KERN_CONT "\n"); -} - -/* - * Just in case we missed an event during initialization check - * all the CMCI owned banks. - */ -void cmci_recheck(void) -{ - unsigned long flags; - int banks; - - if (!mce_available(¤t_cpu_data) || !cmci_supported(&banks)) - return; - local_irq_save(flags); - machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); - local_irq_restore(flags); -} - -/* - * Disable CMCI on this CPU for all banks it owns when it goes down. - * This allows other CPUs to claim the banks on rediscovery. - */ -void cmci_clear(void) -{ - unsigned long flags; - int i; - int banks; - u64 val; - - if (!cmci_supported(&banks)) - return; - spin_lock_irqsave(&cmci_discover_lock, flags); - for (i = 0; i < banks; i++) { - if (!test_bit(i, __get_cpu_var(mce_banks_owned))) - continue; - /* Disable CMCI */ - rdmsrl(MSR_IA32_MC0_CTL2 + i, val); - val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK); - wrmsrl(MSR_IA32_MC0_CTL2 + i, val); - __clear_bit(i, __get_cpu_var(mce_banks_owned)); - } - spin_unlock_irqrestore(&cmci_discover_lock, flags); -} - -/* - * After a CPU went down cycle through all the others and rediscover - * Must run in process context. - */ -void cmci_rediscover(int dying) -{ - int banks; - int cpu; - cpumask_var_t old; - - if (!cmci_supported(&banks)) - return; - if (!alloc_cpumask_var(&old, GFP_KERNEL)) - return; - cpumask_copy(old, ¤t->cpus_allowed); - - for_each_online_cpu(cpu) { - if (cpu == dying) - continue; - if (set_cpus_allowed_ptr(current, cpumask_of(cpu))) - continue; - /* Recheck banks in case CPUs don't all have the same */ - if (cmci_supported(&banks)) - cmci_discover(banks, 0); - } - - set_cpus_allowed_ptr(current, old); - free_cpumask_var(old); -} - -/* - * Reenable CMCI on this CPU in case a CPU down failed. - */ -void cmci_reenable(void) -{ - int banks; - if (cmci_supported(&banks)) - cmci_discover(banks, 0); -} - -static void intel_init_cmci(void) -{ - int banks; - - if (!cmci_supported(&banks)) - return; - - mce_threshold_vector = intel_threshold_interrupt; - cmci_discover(banks, 1); - /* - * For CPU #0 this runs with still disabled APIC, but that's - * ok because only the vector is set up. We still do another - * check for the banks later for CPU #0 just to make sure - * to not miss any events. - */ - apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED); - cmci_recheck(); -} - -void mce_intel_feature_init(struct cpuinfo_x86 *c) -{ - intel_init_thermal(c); - intel_init_cmci(); -} diff --git a/arch/x86/kernel/cpu/mcheck/non-fatal.c b/arch/x86/kernel/cpu/mcheck/non-fatal.c index 70b7104..f5f2d6f 100644 --- a/arch/x86/kernel/cpu/mcheck/non-fatal.c +++ b/arch/x86/kernel/cpu/mcheck/non-fatal.c @@ -17,10 +17,9 @@ #include <asm/processor.h> #include <asm/system.h> +#include <asm/mce.h> #include <asm/msr.h> -#include "mce.h" - static int firstbank; #define MCE_RATE (15*HZ) /* timer rate is 15s */ diff --git a/arch/x86/kernel/cpu/mcheck/p4.c b/arch/x86/kernel/cpu/mcheck/p4.c index 82cee10..4482aea 100644 --- a/arch/x86/kernel/cpu/mcheck/p4.c +++ b/arch/x86/kernel/cpu/mcheck/p4.c @@ -1,21 +1,15 @@ /* * P4 specific Machine Check Exception Reporting */ - -#include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/init.h> #include <linux/smp.h> -#include <asm/therm_throt.h> #include <asm/processor.h> -#include <asm/system.h> -#include <asm/apic.h> +#include <asm/mce.h> #include <asm/msr.h> -#include "mce.h" - /* as supported by the P4/Xeon family */ struct intel_mce_extended_msrs { u32 eax; @@ -33,46 +27,6 @@ struct intel_mce_extended_msrs { static int mce_num_extended_msrs; - -#ifdef CONFIG_X86_MCE_P4THERMAL - -static void unexpected_thermal_interrupt(struct pt_regs *regs) -{ - printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n", - smp_processor_id()); - add_taint(TAINT_MACHINE_CHECK); -} - -/* P4/Xeon Thermal transition interrupt handler: */ -static void intel_thermal_interrupt(struct pt_regs *regs) -{ - __u64 msr_val; - - ack_APIC_irq(); - - rdmsrl(MSR_IA32_THERM_STATUS, msr_val); - therm_throt_process(msr_val & THERM_STATUS_PROCHOT); -} - -/* Thermal interrupt handler for this CPU setup: */ -static void (*vendor_thermal_interrupt)(struct pt_regs *regs) = - unexpected_thermal_interrupt; - -void smp_thermal_interrupt(struct pt_regs *regs) -{ - irq_enter(); - vendor_thermal_interrupt(regs); - __get_cpu_var(irq_stat).irq_thermal_count++; - irq_exit(); -} - -void intel_set_thermal_handler(void) -{ - vendor_thermal_interrupt = intel_thermal_interrupt; -} - -#endif /* CONFIG_X86_MCE_P4THERMAL */ - /* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */ static void intel_get_extended_msrs(struct intel_mce_extended_msrs *r) { diff --git a/arch/x86/kernel/cpu/mcheck/p5.c b/arch/x86/kernel/cpu/mcheck/p5.c index 015f481..5c0e653 100644 --- a/arch/x86/kernel/cpu/mcheck/p5.c +++ b/arch/x86/kernel/cpu/mcheck/p5.c @@ -10,12 +10,11 @@ #include <asm/processor.h> #include <asm/system.h> +#include <asm/mce.h> #include <asm/msr.h> -#include "mce.h" - /* By default disabled */ -int mce_p5_enable; +int mce_p5_enabled __read_mostly; /* Machine check handler for Pentium class Intel CPUs: */ static void pentium_machine_check(struct pt_regs *regs, long error_code) @@ -43,15 +42,13 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c) { u32 l, h; - /* Check for MCE support: */ - if (!cpu_has(c, X86_FEATURE_MCE)) + /* Default P5 to off as its often misconnected: */ + if (!mce_p5_enabled) return; -#ifdef CONFIG_X86_OLD_MCE - /* Default P5 to off as its often misconnected: */ - if (mce_disabled != -1) + /* Check for MCE support: */ + if (!cpu_has(c, X86_FEATURE_MCE)) return; -#endif machine_check_vector = pentium_machine_check; /* Make sure the vector pointer is visible before we enable MCEs: */ diff --git a/arch/x86/kernel/cpu/mcheck/p6.c b/arch/x86/kernel/cpu/mcheck/p6.c index 43c24e6..01e4f81 100644 --- a/arch/x86/kernel/cpu/mcheck/p6.c +++ b/arch/x86/kernel/cpu/mcheck/p6.c @@ -10,10 +10,9 @@ #include <asm/processor.h> #include <asm/system.h> +#include <asm/mce.h> #include <asm/msr.h> -#include "mce.h" - /* Machine Check Handler For PII/PIII */ static void intel_machine_check(struct pt_regs *regs, long error_code) { diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c index 7b1ae2e..bff8dd1 100644 --- a/arch/x86/kernel/cpu/mcheck/therm_throt.c +++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c @@ -13,13 +13,23 @@ * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c. * Inspired by Ross Biro's and Al Borchers' counter code. */ +#include <linux/interrupt.h> #include <linux/notifier.h> #include <linux/jiffies.h> +#include <linux/kernel.h> #include <linux/percpu.h> #include <linux/sysdev.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/smp.h> #include <linux/cpu.h> -#include <asm/therm_throt.h> +#include <asm/processor.h> +#include <asm/system.h> +#include <asm/apic.h> +#include <asm/idle.h> +#include <asm/mce.h> +#include <asm/msr.h> /* How long to wait between reporting thermal events */ #define CHECK_INTERVAL (300 * HZ) @@ -27,7 +37,7 @@ static DEFINE_PER_CPU(__u64, next_check) = INITIAL_JIFFIES; static DEFINE_PER_CPU(unsigned long, thermal_throttle_count); -atomic_t therm_throt_en = ATOMIC_INIT(0); +static atomic_t therm_throt_en = ATOMIC_INIT(0); #ifdef CONFIG_SYSFS #define define_therm_throt_sysdev_one_ro(_name) \ @@ -82,7 +92,7 @@ static struct attribute_group thermal_throttle_attr_group = { * 1 : Event should be logged further, and a message has been * printed to the syslog. */ -int therm_throt_process(int curr) +static int therm_throt_process(int curr) { unsigned int cpu = smp_processor_id(); __u64 tmp_jiffs = get_jiffies_64(); @@ -186,6 +196,94 @@ static __init int thermal_throttle_init_device(void) return 0; } - device_initcall(thermal_throttle_init_device); + #endif /* CONFIG_SYSFS */ + +/* Thermal transition interrupt handler */ +static void intel_thermal_interrupt(void) +{ + __u64 msr_val; + + rdmsrl(MSR_IA32_THERM_STATUS, msr_val); + if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT)) + mce_log_therm_throt_event(msr_val); +} + +static void unexpected_thermal_interrupt(void) +{ + printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n", + smp_processor_id()); + add_taint(TAINT_MACHINE_CHECK); +} + +static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt; + +asmlinkage void smp_thermal_interrupt(struct pt_regs *regs) +{ + exit_idle(); + irq_enter(); + inc_irq_stat(irq_thermal_count); + smp_thermal_vector(); + irq_exit(); + /* Ack only at the end to avoid potential reentry */ + ack_APIC_irq(); +} + +void intel_init_thermal(struct cpuinfo_x86 *c) +{ + unsigned int cpu = smp_processor_id(); + int tm2 = 0; + u32 l, h; + + /* Thermal monitoring depends on ACPI and clock modulation*/ + if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC)) + return; + + /* + * First check if its enabled already, in which case there might + * be some SMM goo which handles it, so we can't even put a handler + * since it might be delivered via SMI already: + */ + rdmsr(MSR_IA32_MISC_ENABLE, l, h); + h = apic_read(APIC_LVTTHMR); + if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) { + printk(KERN_DEBUG + "CPU%d: Thermal monitoring handled by SMI\n", cpu); + return; + } + + if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2)) + tm2 = 1; + + /* Check whether a vector already exists */ + if (h & APIC_VECTOR_MASK) { + printk(KERN_DEBUG + "CPU%d: Thermal LVT vector (%#x) already installed\n", + cpu, (h & APIC_VECTOR_MASK)); + return; + } + + /* We'll mask the thermal vector in the lapic till we're ready: */ + h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED; + apic_write(APIC_LVTTHMR, h); + + rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); + wrmsr(MSR_IA32_THERM_INTERRUPT, + l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h); + + smp_thermal_vector = intel_thermal_interrupt; + + rdmsr(MSR_IA32_MISC_ENABLE, l, h); + wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); + + /* Unmask the thermal vector: */ + l = apic_read(APIC_LVTTHMR); + apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED); + + printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n", + cpu, tm2 ? "TM2" : "TM1"); + + /* enable thermal throttle processing */ + atomic_set(&therm_throt_en, 1); +} diff --git a/arch/x86/kernel/cpu/mcheck/winchip.c b/arch/x86/kernel/cpu/mcheck/winchip.c index 81b0248..54060f5 100644 --- a/arch/x86/kernel/cpu/mcheck/winchip.c +++ b/arch/x86/kernel/cpu/mcheck/winchip.c @@ -9,10 +9,9 @@ #include <asm/processor.h> #include <asm/system.h> +#include <asm/mce.h> #include <asm/msr.h> -#include "mce.h" - /* Machine check handler for WinChip C6: */ static void winchip_machine_check(struct pt_regs *regs, long error_code) { diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index 275bc14..76dfef2 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c @@ -19,6 +19,7 @@ #include <linux/kdebug.h> #include <linux/sched.h> #include <linux/uaccess.h> +#include <linux/highmem.h> #include <asm/apic.h> #include <asm/stacktrace.h> @@ -389,23 +390,23 @@ static u64 intel_pmu_raw_event(u64 event) return event & CORE_EVNTSEL_MASK; } -static const u64 amd_0f_hw_cache_event_ids +static const u64 amd_hw_cache_event_ids [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX] = { [ C(L1D) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ + [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ }, [ C(OP_WRITE) ] = { - [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */ [ C(RESULT_MISS) ] = 0, }, [ C(OP_PREFETCH) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */ + [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */ }, }, [ C(L1I ) ] = { @@ -418,17 +419,17 @@ static const u64 amd_0f_hw_cache_event_ids [ C(RESULT_MISS) ] = -1, }, [ C(OP_PREFETCH) ] = { - [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */ [ C(RESULT_MISS) ] = 0, }, }, [ C(LL ) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */ + [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */ }, [ C(OP_WRITE) ] = { - [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */ [ C(RESULT_MISS) ] = 0, }, [ C(OP_PREFETCH) ] = { @@ -438,8 +439,8 @@ static const u64 amd_0f_hw_cache_event_ids }, [ C(DTLB) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ + [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */ }, [ C(OP_WRITE) ] = { [ C(RESULT_ACCESS) ] = 0, @@ -1223,6 +1224,8 @@ again: if (!intel_pmu_save_and_restart(counter)) continue; + data.period = counter->hw.last_period; + if (perf_counter_overflow(counter, 1, &data)) intel_pmu_disable_counter(&counter->hw, bit); } @@ -1459,18 +1462,16 @@ static int intel_pmu_init(void) static int amd_pmu_init(void) { + /* Performance-monitoring supported from K7 and later: */ + if (boot_cpu_data.x86 < 6) + return -ENODEV; + x86_pmu = amd_pmu; - switch (boot_cpu_data.x86) { - case 0x0f: - case 0x10: - case 0x11: - memcpy(hw_cache_event_ids, amd_0f_hw_cache_event_ids, - sizeof(hw_cache_event_ids)); + /* Events are common for all AMDs */ + memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, + sizeof(hw_cache_event_ids)); - pr_cont("AMD Family 0f/10/11 events, "); - break; - } return 0; } @@ -1554,9 +1555,9 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter) */ static inline -void callchain_store(struct perf_callchain_entry *entry, unsigned long ip) +void callchain_store(struct perf_callchain_entry *entry, u64 ip) { - if (entry->nr < MAX_STACK_DEPTH) + if (entry->nr < PERF_MAX_STACK_DEPTH) entry->ip[entry->nr++] = ip; } @@ -1577,8 +1578,8 @@ static void backtrace_warning(void *data, char *msg) static int backtrace_stack(void *data, char *name) { - /* Don't bother with IRQ stacks for now */ - return -1; + /* Process all stacks: */ + return 0; } static void backtrace_address(void *data, unsigned long addr, int reliable) @@ -1596,47 +1597,59 @@ static const struct stacktrace_ops backtrace_ops = { .address = backtrace_address, }; +#include "../dumpstack.h" + static void perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) { - unsigned long bp; - char *stack; - int nr = entry->nr; + callchain_store(entry, PERF_CONTEXT_KERNEL); + callchain_store(entry, regs->ip); - callchain_store(entry, instruction_pointer(regs)); + dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); +} - stack = ((char *)regs + sizeof(struct pt_regs)); -#ifdef CONFIG_FRAME_POINTER - bp = frame_pointer(regs); -#else - bp = 0; -#endif +/* + * best effort, GUP based copy_from_user() that assumes IRQ or NMI context + */ +static unsigned long +copy_from_user_nmi(void *to, const void __user *from, unsigned long n) +{ + unsigned long offset, addr = (unsigned long)from; + int type = in_nmi() ? KM_NMI : KM_IRQ0; + unsigned long size, len = 0; + struct page *page; + void *map; + int ret; - dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry); + do { + ret = __get_user_pages_fast(addr, 1, 0, &page); + if (!ret) + break; - entry->kernel = entry->nr - nr; -} + offset = addr & (PAGE_SIZE - 1); + size = min(PAGE_SIZE - offset, n - len); + map = kmap_atomic(page, type); + memcpy(to, map+offset, size); + kunmap_atomic(map, type); + put_page(page); -struct stack_frame { - const void __user *next_fp; - unsigned long return_address; -}; + len += size; + to += size; + addr += size; + + } while (len < n); + + return len; +} static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) { - int ret; + unsigned long bytes; - if (!access_ok(VERIFY_READ, fp, sizeof(*frame))) - return 0; + bytes = copy_from_user_nmi(frame, fp, sizeof(*frame)); - ret = 1; - pagefault_disable(); - if (__copy_from_user_inatomic(frame, fp, sizeof(*frame))) - ret = 0; - pagefault_enable(); - - return ret; + return bytes == sizeof(*frame); } static void @@ -1644,28 +1657,28 @@ perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) { struct stack_frame frame; const void __user *fp; - int nr = entry->nr; - regs = (struct pt_regs *)current->thread.sp0 - 1; - fp = (void __user *)regs->bp; + if (!user_mode(regs)) + regs = task_pt_regs(current); + fp = (void __user *)regs->bp; + + callchain_store(entry, PERF_CONTEXT_USER); callchain_store(entry, regs->ip); - while (entry->nr < MAX_STACK_DEPTH) { - frame.next_fp = NULL; + while (entry->nr < PERF_MAX_STACK_DEPTH) { + frame.next_frame = NULL; frame.return_address = 0; if (!copy_stack_frame(fp, &frame)) break; - if ((unsigned long)fp < user_stack_pointer(regs)) + if ((unsigned long)fp < regs->sp) break; callchain_store(entry, frame.return_address); - fp = frame.next_fp; + fp = frame.next_frame; } - - entry->user = entry->nr - nr; } static void @@ -1701,9 +1714,6 @@ struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) entry = &__get_cpu_var(irq_entry); entry->nr = 0; - entry->hv = 0; - entry->kernel = 0; - entry->user = 0; perf_do_callchain(regs, entry); diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c index d6f5b9f..5c481f6 100644 --- a/arch/x86/kernel/cpu/perfctr-watchdog.c +++ b/arch/x86/kernel/cpu/perfctr-watchdog.c @@ -716,11 +716,15 @@ static void probe_nmi_watchdog(void) wd_ops = &k7_wd_ops; break; case X86_VENDOR_INTEL: - /* - * Work around Core Duo (Yonah) errata AE49 where perfctr1 - * doesn't have a working enable bit. + /* Work around where perfctr1 doesn't have a working enable + * bit as described in the following errata: + * AE49 Core Duo and Intel Core Solo 65 nm + * AN49 Intel Pentium Dual-Core + * AF49 Dual-Core Intel Xeon Processor LV */ - if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 14) { + if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 14) || + ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 15 && + boot_cpu_data.x86_mask == 4))) { intel_arch_wd_ops.perfctr = MSR_ARCH_PERFMON_PERFCTR0; intel_arch_wd_ops.evntsel = MSR_ARCH_PERFMON_EVENTSEL0; } diff --git a/arch/x86/kernel/crash.c b/arch/x86/kernel/crash.c index ff95824..5e409dc 100644 --- a/arch/x86/kernel/crash.c +++ b/arch/x86/kernel/crash.c @@ -27,6 +27,7 @@ #include <asm/cpu.h> #include <asm/reboot.h> #include <asm/virtext.h> +#include <asm/iommu.h> #if defined(CONFIG_SMP) && defined(CONFIG_X86_LOCAL_APIC) @@ -103,5 +104,10 @@ void native_machine_crash_shutdown(struct pt_regs *regs) #ifdef CONFIG_HPET_TIMER hpet_disable(); #endif + +#ifdef CONFIG_X86_64 + pci_iommu_shutdown(); +#endif + crash_save_cpu(regs, safe_smp_processor_id()); } diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index 95ea5fa..c8405718 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -22,6 +22,7 @@ #include "dumpstack.h" int panic_on_unrecovered_nmi; +int panic_on_io_nmi; unsigned int code_bytes = 64; int kstack_depth_to_print = 3 * STACKSLOTS_PER_LINE; static int die_counter; diff --git a/arch/x86/kernel/efi.c b/arch/x86/kernel/efi.c index 1736acc..96f7ac0 100644 --- a/arch/x86/kernel/efi.c +++ b/arch/x86/kernel/efi.c @@ -240,10 +240,35 @@ static void __init do_add_efi_memmap(void) unsigned long long size = md->num_pages << EFI_PAGE_SHIFT; int e820_type; - if (md->attribute & EFI_MEMORY_WB) - e820_type = E820_RAM; - else + switch (md->type) { + case EFI_LOADER_CODE: + case EFI_LOADER_DATA: + case EFI_BOOT_SERVICES_CODE: + case EFI_BOOT_SERVICES_DATA: + case EFI_CONVENTIONAL_MEMORY: + if (md->attribute & EFI_MEMORY_WB) + e820_type = E820_RAM; + else + e820_type = E820_RESERVED; + break; + case EFI_ACPI_RECLAIM_MEMORY: + e820_type = E820_ACPI; + break; + case EFI_ACPI_MEMORY_NVS: + e820_type = E820_NVS; + break; + case EFI_UNUSABLE_MEMORY: + e820_type = E820_UNUSABLE; + break; + default: + /* + * EFI_RESERVED_TYPE EFI_RUNTIME_SERVICES_CODE + * EFI_RUNTIME_SERVICES_DATA EFI_MEMORY_MAPPED_IO + * EFI_MEMORY_MAPPED_IO_PORT_SPACE EFI_PAL_CODE + */ e820_type = E820_RESERVED; + break; + } e820_add_region(start, size, e820_type); } sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map); diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S index c929add..c097e7d 100644 --- a/arch/x86/kernel/entry_32.S +++ b/arch/x86/kernel/entry_32.S @@ -48,7 +48,6 @@ #include <asm/segment.h> #include <asm/smp.h> #include <asm/page_types.h> -#include <asm/desc.h> #include <asm/percpu.h> #include <asm/dwarf2.h> #include <asm/processor-flags.h> @@ -84,7 +83,7 @@ #define preempt_stop(clobbers) DISABLE_INTERRUPTS(clobbers); TRACE_IRQS_OFF #else #define preempt_stop(clobbers) -#define resume_kernel restore_nocheck +#define resume_kernel restore_all #endif .macro TRACE_IRQS_IRET @@ -372,7 +371,7 @@ END(ret_from_exception) ENTRY(resume_kernel) DISABLE_INTERRUPTS(CLBR_ANY) cmpl $0,TI_preempt_count(%ebp) # non-zero preempt_count ? - jnz restore_nocheck + jnz restore_all need_resched: movl TI_flags(%ebp), %ecx # need_resched set ? testb $_TIF_NEED_RESCHED, %cl @@ -540,6 +539,8 @@ syscall_exit: jne syscall_exit_work restore_all: + TRACE_IRQS_IRET +restore_all_notrace: movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS # Warning: PT_OLDSS(%esp) contains the wrong/random values if we # are returning to the kernel. @@ -551,8 +552,6 @@ restore_all: CFI_REMEMBER_STATE je ldt_ss # returning to user-space with LDT SS restore_nocheck: - TRACE_IRQS_IRET -restore_nocheck_notrace: RESTORE_REGS 4 # skip orig_eax/error_code CFI_ADJUST_CFA_OFFSET -4 irq_return: @@ -588,22 +587,34 @@ ldt_ss: jne restore_nocheck #endif - /* If returning to userspace with 16bit stack, - * try to fix the higher word of ESP, as the CPU - * won't restore it. - * This is an "official" bug of all the x86-compatible - * CPUs, which we can try to work around to make - * dosemu and wine happy. */ - movl PT_OLDESP(%esp), %eax - movl %esp, %edx - call patch_espfix_desc +/* + * Setup and switch to ESPFIX stack + * + * We're returning to userspace with a 16 bit stack. The CPU will not + * restore the high word of ESP for us on executing iret... This is an + * "official" bug of all the x86-compatible CPUs, which we can work + * around to make dosemu and wine happy. We do this by preloading the + * high word of ESP with the high word of the userspace ESP while + * compensating for the offset by changing to the ESPFIX segment with + * a base address that matches for the difference. + */ + mov %esp, %edx /* load kernel esp */ + mov PT_OLDESP(%esp), %eax /* load userspace esp */ + mov %dx, %ax /* eax: new kernel esp */ + sub %eax, %edx /* offset (low word is 0) */ + PER_CPU(gdt_page, %ebx) + shr $16, %edx + mov %dl, GDT_ENTRY_ESPFIX_SS * 8 + 4(%ebx) /* bits 16..23 */ + mov %dh, GDT_ENTRY_ESPFIX_SS * 8 + 7(%ebx) /* bits 24..31 */ pushl $__ESPFIX_SS CFI_ADJUST_CFA_OFFSET 4 - pushl %eax + push %eax /* new kernel esp */ CFI_ADJUST_CFA_OFFSET 4 + /* Disable interrupts, but do not irqtrace this section: we + * will soon execute iret and the tracer was already set to + * the irqstate after the iret */ DISABLE_INTERRUPTS(CLBR_EAX) - TRACE_IRQS_OFF - lss (%esp), %esp + lss (%esp), %esp /* switch to espfix segment */ CFI_ADJUST_CFA_OFFSET -8 jmp restore_nocheck CFI_ENDPROC @@ -716,15 +727,24 @@ PTREGSCALL(vm86) PTREGSCALL(vm86old) .macro FIXUP_ESPFIX_STACK - /* since we are on a wrong stack, we cant make it a C code :( */ +/* + * Switch back for ESPFIX stack to the normal zerobased stack + * + * We can't call C functions using the ESPFIX stack. This code reads + * the high word of the segment base from the GDT and swiches to the + * normal stack and adjusts ESP with the matching offset. + */ + /* fixup the stack */ PER_CPU(gdt_page, %ebx) - GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah) - addl %esp, %eax + mov GDT_ENTRY_ESPFIX_SS * 8 + 4(%ebx), %al /* bits 16..23 */ + mov GDT_ENTRY_ESPFIX_SS * 8 + 7(%ebx), %ah /* bits 24..31 */ + shl $16, %eax + addl %esp, %eax /* the adjusted stack pointer */ pushl $__KERNEL_DS CFI_ADJUST_CFA_OFFSET 4 pushl %eax CFI_ADJUST_CFA_OFFSET 4 - lss (%esp), %esp + lss (%esp), %esp /* switch to the normal stack segment */ CFI_ADJUST_CFA_OFFSET -8 .endm .macro UNWIND_ESPFIX_STACK @@ -1154,6 +1174,7 @@ ENTRY(ftrace_graph_caller) pushl %edx movl 0xc(%esp), %edx lea 0x4(%ebp), %eax + movl (%ebp), %ecx subl $MCOUNT_INSN_SIZE, %edx call prepare_ftrace_return popl %edx @@ -1168,6 +1189,7 @@ return_to_handler: pushl %eax pushl %ecx pushl %edx + movl %ebp, %eax call ftrace_return_to_handler movl %eax, 0xc(%esp) popl %edx @@ -1329,7 +1351,7 @@ nmi_stack_correct: xorl %edx,%edx # zero error code movl %esp,%eax # pt_regs pointer call do_nmi - jmp restore_nocheck_notrace + jmp restore_all_notrace CFI_ENDPROC nmi_stack_fixup: diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S index de74f0a..c251be7 100644 --- a/arch/x86/kernel/entry_64.S +++ b/arch/x86/kernel/entry_64.S @@ -135,6 +135,7 @@ ENTRY(ftrace_graph_caller) leaq 8(%rbp), %rdi movq 0x38(%rsp), %rsi + movq (%rbp), %rdx subq $MCOUNT_INSN_SIZE, %rsi call prepare_ftrace_return @@ -150,6 +151,7 @@ GLOBAL(return_to_handler) /* Save the return values */ movq %rax, (%rsp) movq %rdx, 8(%rsp) + movq %rbp, %rdi call ftrace_return_to_handler diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c index b79c553..d94e1ea 100644 --- a/arch/x86/kernel/ftrace.c +++ b/arch/x86/kernel/ftrace.c @@ -408,7 +408,8 @@ int ftrace_disable_ftrace_graph_caller(void) * Hook the return address and push it in the stack of return addrs * in current thread info. */ -void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr) +void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, + unsigned long frame_pointer) { unsigned long old; int faulted; @@ -453,7 +454,8 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr) return; } - if (ftrace_push_return_trace(old, self_addr, &trace.depth) == -EBUSY) { + if (ftrace_push_return_trace(old, self_addr, &trace.depth, + frame_pointer) == -EBUSY) { *parent = old; return; } diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S index dc5ed4b..8663afb 100644 --- a/arch/x86/kernel/head_32.S +++ b/arch/x86/kernel/head_32.S @@ -13,7 +13,6 @@ #include <asm/segment.h> #include <asm/page_types.h> #include <asm/pgtable_types.h> -#include <asm/desc.h> #include <asm/cache.h> #include <asm/thread_info.h> #include <asm/asm-offsets.h> diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 54b29bb..fa54f78 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -12,7 +12,6 @@ #include <linux/linkage.h> #include <linux/threads.h> #include <linux/init.h> -#include <asm/desc.h> #include <asm/segment.h> #include <asm/pgtable.h> #include <asm/page.h> diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 81408b9..dedc2bd 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -510,7 +510,8 @@ static int hpet_setup_irq(struct hpet_dev *dev) { if (request_irq(dev->irq, hpet_interrupt_handler, - IRQF_DISABLED|IRQF_NOBALANCING, dev->name, dev)) + IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, + dev->name, dev)) return -1; disable_irq(dev->irq); diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c index 745579b..4763047 100644 --- a/arch/x86/kernel/pci-dma.c +++ b/arch/x86/kernel/pci-dma.c @@ -32,6 +32,8 @@ int no_iommu __read_mostly; /* Set this to 1 if there is a HW IOMMU in the system */ int iommu_detected __read_mostly = 0; +int iommu_pass_through; + dma_addr_t bad_dma_address __read_mostly = 0; EXPORT_SYMBOL(bad_dma_address); @@ -209,6 +211,10 @@ static __init int iommu_setup(char *p) #ifdef CONFIG_SWIOTLB if (!strncmp(p, "soft", 4)) swiotlb = 1; + if (!strncmp(p, "pt", 2)) { + iommu_pass_through = 1; + return 1; + } #endif gart_parse_options(p); @@ -290,6 +296,8 @@ static int __init pci_iommu_init(void) void pci_iommu_shutdown(void) { gart_iommu_shutdown(); + + amd_iommu_shutdown(); } /* Must execute after PCI subsystem */ fs_initcall(pci_iommu_init); diff --git a/arch/x86/kernel/pci-swiotlb.c b/arch/x86/kernel/pci-swiotlb.c index a1712f2..6af96ee 100644 --- a/arch/x86/kernel/pci-swiotlb.c +++ b/arch/x86/kernel/pci-swiotlb.c @@ -71,7 +71,8 @@ void __init pci_swiotlb_init(void) { /* don't initialize swiotlb if iommu=off (no_iommu=1) */ #ifdef CONFIG_X86_64 - if (!iommu_detected && !no_iommu && max_pfn > MAX_DMA32_PFN) + if ((!iommu_detected && !no_iommu && max_pfn > MAX_DMA32_PFN) || + iommu_pass_through) swiotlb = 1; #endif if (swiotlb_force) diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index be5ae80..de2cab1 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -289,6 +289,20 @@ void * __init extend_brk(size_t size, size_t align) return ret; } +#ifdef CONFIG_X86_64 +static void __init init_gbpages(void) +{ + if (direct_gbpages && cpu_has_gbpages) + printk(KERN_INFO "Using GB pages for direct mapping\n"); + else + direct_gbpages = 0; +} +#else +static inline void init_gbpages(void) +{ +} +#endif + static void __init reserve_brk(void) { if (_brk_end > _brk_start) @@ -871,6 +885,8 @@ void __init setup_arch(char **cmdline_p) reserve_brk(); + init_gbpages(); + /* max_pfn_mapped is updated here */ max_low_pfn_mapped = init_memory_mapping(0, max_low_pfn<<PAGE_SHIFT); max_pfn_mapped = max_low_pfn_mapped; diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c index 9c3f082..29a3eef 100644 --- a/arch/x86/kernel/setup_percpu.c +++ b/arch/x86/kernel/setup_percpu.c @@ -124,7 +124,7 @@ static void * __init pcpu_alloc_bootmem(unsigned int cpu, unsigned long size, } /* - * Remap allocator + * Large page remap allocator * * This allocator uses PMD page as unit. A PMD page is allocated for * each cpu and each is remapped into vmalloc area using PMD mapping. @@ -137,105 +137,185 @@ static void * __init pcpu_alloc_bootmem(unsigned int cpu, unsigned long size, * better than only using 4k mappings while still being NUMA friendly. */ #ifdef CONFIG_NEED_MULTIPLE_NODES -static size_t pcpur_size __initdata; -static void **pcpur_ptrs __initdata; +struct pcpul_ent { + unsigned int cpu; + void *ptr; +}; + +static size_t pcpul_size; +static struct pcpul_ent *pcpul_map; +static struct vm_struct pcpul_vm; -static struct page * __init pcpur_get_page(unsigned int cpu, int pageno) +static struct page * __init pcpul_get_page(unsigned int cpu, int pageno) { size_t off = (size_t)pageno << PAGE_SHIFT; - if (off >= pcpur_size) + if (off >= pcpul_size) return NULL; - return virt_to_page(pcpur_ptrs[cpu] + off); + return virt_to_page(pcpul_map[cpu].ptr + off); } -static ssize_t __init setup_pcpu_remap(size_t static_size) +static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen) { - static struct vm_struct vm; - size_t ptrs_size, dyn_size; + size_t map_size, dyn_size; unsigned int cpu; + int i, j; ssize_t ret; - /* - * If large page isn't supported, there's no benefit in doing - * this. Also, on non-NUMA, embedding is better. - * - * NOTE: disabled for now. - */ - if (true || !cpu_has_pse || !pcpu_need_numa()) + if (!chosen) { + size_t vm_size = VMALLOC_END - VMALLOC_START; + size_t tot_size = num_possible_cpus() * PMD_SIZE; + + /* on non-NUMA, embedding is better */ + if (!pcpu_need_numa()) + return -EINVAL; + + /* don't consume more than 20% of vmalloc area */ + if (tot_size > vm_size / 5) { + pr_info("PERCPU: too large chunk size %zuMB for " + "large page remap\n", tot_size >> 20); + return -EINVAL; + } + } + + /* need PSE */ + if (!cpu_has_pse) { + pr_warning("PERCPU: lpage allocator requires PSE\n"); return -EINVAL; + } /* * Currently supports only single page. Supporting multiple * pages won't be too difficult if it ever becomes necessary. */ - pcpur_size = PFN_ALIGN(static_size + PERCPU_MODULE_RESERVE + + pcpul_size = PFN_ALIGN(static_size + PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE); - if (pcpur_size > PMD_SIZE) { + if (pcpul_size > PMD_SIZE) { pr_warning("PERCPU: static data is larger than large page, " "can't use large page\n"); return -EINVAL; } - dyn_size = pcpur_size - static_size - PERCPU_FIRST_CHUNK_RESERVE; + dyn_size = pcpul_size - static_size - PERCPU_FIRST_CHUNK_RESERVE; /* allocate pointer array and alloc large pages */ - ptrs_size = PFN_ALIGN(num_possible_cpus() * sizeof(pcpur_ptrs[0])); - pcpur_ptrs = alloc_bootmem(ptrs_size); + map_size = PFN_ALIGN(num_possible_cpus() * sizeof(pcpul_map[0])); + pcpul_map = alloc_bootmem(map_size); for_each_possible_cpu(cpu) { - pcpur_ptrs[cpu] = pcpu_alloc_bootmem(cpu, PMD_SIZE, PMD_SIZE); - if (!pcpur_ptrs[cpu]) + pcpul_map[cpu].cpu = cpu; + pcpul_map[cpu].ptr = pcpu_alloc_bootmem(cpu, PMD_SIZE, + PMD_SIZE); + if (!pcpul_map[cpu].ptr) { + pr_warning("PERCPU: failed to allocate large page " + "for cpu%u\n", cpu); goto enomem; + } /* - * Only use pcpur_size bytes and give back the rest. + * Only use pcpul_size bytes and give back the rest. * * Ingo: The 2MB up-rounding bootmem is needed to make * sure the partial 2MB page is still fully RAM - it's * not well-specified to have a PAT-incompatible area * (unmapped RAM, device memory, etc.) in that hole. */ - free_bootmem(__pa(pcpur_ptrs[cpu] + pcpur_size), - PMD_SIZE - pcpur_size); + free_bootmem(__pa(pcpul_map[cpu].ptr + pcpul_size), + PMD_SIZE - pcpul_size); - memcpy(pcpur_ptrs[cpu], __per_cpu_load, static_size); + memcpy(pcpul_map[cpu].ptr, __per_cpu_load, static_size); } /* allocate address and map */ - vm.flags = VM_ALLOC; - vm.size = num_possible_cpus() * PMD_SIZE; - vm_area_register_early(&vm, PMD_SIZE); + pcpul_vm.flags = VM_ALLOC; + pcpul_vm.size = num_possible_cpus() * PMD_SIZE; + vm_area_register_early(&pcpul_vm, PMD_SIZE); for_each_possible_cpu(cpu) { - pmd_t *pmd; + pmd_t *pmd, pmd_v; - pmd = populate_extra_pmd((unsigned long)vm.addr - + cpu * PMD_SIZE); - set_pmd(pmd, pfn_pmd(page_to_pfn(virt_to_page(pcpur_ptrs[cpu])), - PAGE_KERNEL_LARGE)); + pmd = populate_extra_pmd((unsigned long)pcpul_vm.addr + + cpu * PMD_SIZE); + pmd_v = pfn_pmd(page_to_pfn(virt_to_page(pcpul_map[cpu].ptr)), + PAGE_KERNEL_LARGE); + set_pmd(pmd, pmd_v); } /* we're ready, commit */ pr_info("PERCPU: Remapped at %p with large pages, static data " - "%zu bytes\n", vm.addr, static_size); + "%zu bytes\n", pcpul_vm.addr, static_size); - ret = pcpu_setup_first_chunk(pcpur_get_page, static_size, + ret = pcpu_setup_first_chunk(pcpul_get_page, static_size, PERCPU_FIRST_CHUNK_RESERVE, dyn_size, - PMD_SIZE, vm.addr, NULL); - goto out_free_ar; + PMD_SIZE, pcpul_vm.addr, NULL); + + /* sort pcpul_map array for pcpu_lpage_remapped() */ + for (i = 0; i < num_possible_cpus() - 1; i++) + for (j = i + 1; j < num_possible_cpus(); j++) + if (pcpul_map[i].ptr > pcpul_map[j].ptr) { + struct pcpul_ent tmp = pcpul_map[i]; + pcpul_map[i] = pcpul_map[j]; + pcpul_map[j] = tmp; + } + + return ret; enomem: for_each_possible_cpu(cpu) - if (pcpur_ptrs[cpu]) - free_bootmem(__pa(pcpur_ptrs[cpu]), PMD_SIZE); - ret = -ENOMEM; -out_free_ar: - free_bootmem(__pa(pcpur_ptrs), ptrs_size); - return ret; + if (pcpul_map[cpu].ptr) + free_bootmem(__pa(pcpul_map[cpu].ptr), pcpul_size); + free_bootmem(__pa(pcpul_map), map_size); + return -ENOMEM; +} + +/** + * pcpu_lpage_remapped - determine whether a kaddr is in pcpul recycled area + * @kaddr: the kernel address in question + * + * Determine whether @kaddr falls in the pcpul recycled area. This is + * used by pageattr to detect VM aliases and break up the pcpu PMD + * mapping such that the same physical page is not mapped under + * different attributes. + * + * The recycled area is always at the tail of a partially used PMD + * page. + * + * RETURNS: + * Address of corresponding remapped pcpu address if match is found; + * otherwise, NULL. + */ +void *pcpu_lpage_remapped(void *kaddr) +{ + void *pmd_addr = (void *)((unsigned long)kaddr & PMD_MASK); + unsigned long offset = (unsigned long)kaddr & ~PMD_MASK; + int left = 0, right = num_possible_cpus() - 1; + int pos; + + /* pcpul in use at all? */ + if (!pcpul_map) + return NULL; + + /* okay, perform binary search */ + while (left <= right) { + pos = (left + right) / 2; + + if (pcpul_map[pos].ptr < pmd_addr) + left = pos + 1; + else if (pcpul_map[pos].ptr > pmd_addr) + right = pos - 1; + else { + /* it shouldn't be in the area for the first chunk */ + WARN_ON(offset < pcpul_size); + + return pcpul_vm.addr + + pcpul_map[pos].cpu * PMD_SIZE + offset; + } + } + + return NULL; } #else -static ssize_t __init setup_pcpu_remap(size_t static_size) +static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen) { return -EINVAL; } @@ -249,7 +329,7 @@ static ssize_t __init setup_pcpu_remap(size_t static_size) * mapping so that it can use PMD mapping without additional TLB * pressure. */ -static ssize_t __init setup_pcpu_embed(size_t static_size) +static ssize_t __init setup_pcpu_embed(size_t static_size, bool chosen) { size_t reserve = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; @@ -258,7 +338,7 @@ static ssize_t __init setup_pcpu_embed(size_t static_size) * this. Also, embedding allocation doesn't play well with * NUMA. */ - if (!cpu_has_pse || pcpu_need_numa()) + if (!chosen && (!cpu_has_pse || pcpu_need_numa())) return -EINVAL; return pcpu_embed_first_chunk(static_size, PERCPU_FIRST_CHUNK_RESERVE, @@ -308,8 +388,11 @@ static ssize_t __init setup_pcpu_4k(size_t static_size) void *ptr; ptr = pcpu_alloc_bootmem(cpu, PAGE_SIZE, PAGE_SIZE); - if (!ptr) + if (!ptr) { + pr_warning("PERCPU: failed to allocate " + "4k page for cpu%u\n", cpu); goto enomem; + } memcpy(ptr, __per_cpu_load + i * PAGE_SIZE, PAGE_SIZE); pcpu4k_pages[j++] = virt_to_page(ptr); @@ -333,6 +416,16 @@ out_free_ar: return ret; } +/* for explicit first chunk allocator selection */ +static char pcpu_chosen_alloc[16] __initdata; + +static int __init percpu_alloc_setup(char *str) +{ + strncpy(pcpu_chosen_alloc, str, sizeof(pcpu_chosen_alloc) - 1); + return 0; +} +early_param("percpu_alloc", percpu_alloc_setup); + static inline void setup_percpu_segment(int cpu) { #ifdef CONFIG_X86_32 @@ -346,11 +439,6 @@ static inline void setup_percpu_segment(int cpu) #endif } -/* - * Great future plan: - * Declare PDA itself and support (irqstack,tss,pgd) as per cpu data. - * Always point %gs to its beginning - */ void __init setup_per_cpu_areas(void) { size_t static_size = __per_cpu_end - __per_cpu_start; @@ -367,9 +455,26 @@ void __init setup_per_cpu_areas(void) * of large page mappings. Please read comments on top of * each allocator for details. */ - ret = setup_pcpu_remap(static_size); - if (ret < 0) - ret = setup_pcpu_embed(static_size); + ret = -EINVAL; + if (strlen(pcpu_chosen_alloc)) { + if (strcmp(pcpu_chosen_alloc, "4k")) { + if (!strcmp(pcpu_chosen_alloc, "lpage")) + ret = setup_pcpu_lpage(static_size, true); + else if (!strcmp(pcpu_chosen_alloc, "embed")) + ret = setup_pcpu_embed(static_size, true); + else + pr_warning("PERCPU: unknown allocator %s " + "specified\n", pcpu_chosen_alloc); + if (ret < 0) + pr_warning("PERCPU: %s allocator failed (%zd), " + "falling back to 4k\n", + pcpu_chosen_alloc, ret); + } + } else { + ret = setup_pcpu_lpage(static_size, false); + if (ret < 0) + ret = setup_pcpu_embed(static_size, false); + } if (ret < 0) ret = setup_pcpu_4k(static_size); if (ret < 0) diff --git a/arch/x86/kernel/tlb_uv.c b/arch/x86/kernel/tlb_uv.c index 124d40c..8ccabb8 100644 --- a/arch/x86/kernel/tlb_uv.c +++ b/arch/x86/kernel/tlb_uv.c @@ -711,7 +711,6 @@ uv_activation_descriptor_init(int node, int pnode) unsigned long pa; unsigned long m; unsigned long n; - unsigned long mmr_image; struct bau_desc *adp; struct bau_desc *ad2; @@ -727,12 +726,8 @@ uv_activation_descriptor_init(int node, int pnode) n = pa >> uv_nshift; m = pa & uv_mmask; - mmr_image = uv_read_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE); - if (mmr_image) { - uv_write_global_mmr64(pnode, (unsigned long) - UVH_LB_BAU_SB_DESCRIPTOR_BASE, - (n << UV_DESC_BASE_PNODE_SHIFT | m)); - } + uv_write_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, + (n << UV_DESC_BASE_PNODE_SHIFT | m)); /* * initializing all 8 (UV_ITEMS_PER_DESCRIPTOR) descriptors for each diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 5f935f0..5204332 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -54,6 +54,7 @@ #include <asm/traps.h> #include <asm/desc.h> #include <asm/i387.h> +#include <asm/mce.h> #include <asm/mach_traps.h> @@ -65,8 +66,6 @@ #include <asm/setup.h> #include <asm/traps.h> -#include "cpu/mcheck/mce.h" - asmlinkage int system_call(void); /* Do we ignore FPU interrupts ? */ @@ -347,6 +346,9 @@ io_check_error(unsigned char reason, struct pt_regs *regs) printk(KERN_EMERG "NMI: IOCK error (debug interrupt?)\n"); show_registers(regs); + if (panic_on_io_nmi) + panic("NMI IOCK error: Not continuing"); + /* Re-enable the IOCK line, wait for a few seconds */ reason = (reason & 0xf) | 8; outb(reason, 0x61); diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index b0597ad..6e1a368 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -590,22 +590,26 @@ EXPORT_SYMBOL(recalibrate_cpu_khz); */ DEFINE_PER_CPU(unsigned long, cyc2ns); +DEFINE_PER_CPU(unsigned long long, cyc2ns_offset); static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu) { - unsigned long long tsc_now, ns_now; + unsigned long long tsc_now, ns_now, *offset; unsigned long flags, *scale; local_irq_save(flags); sched_clock_idle_sleep_event(); scale = &per_cpu(cyc2ns, cpu); + offset = &per_cpu(cyc2ns_offset, cpu); rdtscll(tsc_now); ns_now = __cycles_2_ns(tsc_now); - if (cpu_khz) + if (cpu_khz) { *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz; + *offset = ns_now - (tsc_now * *scale >> CYC2NS_SCALE_FACTOR); + } sched_clock_idle_wakeup_event(0); local_irq_restore(flags); diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 5c3d6e8..7030b5f 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -2157,7 +2157,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) else /* 32 bits PSE 4MB page */ context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); - context->rsvd_bits_mask[1][0] = ~0ull; + context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0]; break; case PT32E_ROOT_LEVEL: context->rsvd_bits_mask[0][2] = @@ -2170,7 +2170,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) context->rsvd_bits_mask[1][1] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 62) | rsvd_bits(13, 20); /* large page */ - context->rsvd_bits_mask[1][0] = ~0ull; + context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0]; break; case PT64_ROOT_LEVEL: context->rsvd_bits_mask[0][3] = exb_bit_rsvd | @@ -2186,7 +2186,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) context->rsvd_bits_mask[1][1] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 51) | rsvd_bits(13, 20); /* large page */ - context->rsvd_bits_mask[1][0] = ~0ull; + context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0]; break; } } diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h index 258e459..67785f6 100644 --- a/arch/x86/kvm/paging_tmpl.h +++ b/arch/x86/kvm/paging_tmpl.h @@ -281,7 +281,7 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, { unsigned access = gw->pt_access; struct kvm_mmu_page *shadow_page; - u64 spte, *sptep; + u64 spte, *sptep = NULL; int direct; gfn_t table_gfn; int r; diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index e770bf3..356a0ce 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -3012,6 +3012,12 @@ static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) return 1; } +static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) +{ + kvm_queue_exception(vcpu, UD_VECTOR); + return 1; +} + static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) { unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); @@ -3198,6 +3204,15 @@ static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, [EXIT_REASON_HLT] = handle_halt, [EXIT_REASON_INVLPG] = handle_invlpg, [EXIT_REASON_VMCALL] = handle_vmcall, + [EXIT_REASON_VMCLEAR] = handle_vmx_insn, + [EXIT_REASON_VMLAUNCH] = handle_vmx_insn, + [EXIT_REASON_VMPTRLD] = handle_vmx_insn, + [EXIT_REASON_VMPTRST] = handle_vmx_insn, + [EXIT_REASON_VMREAD] = handle_vmx_insn, + [EXIT_REASON_VMRESUME] = handle_vmx_insn, + [EXIT_REASON_VMWRITE] = handle_vmx_insn, + [EXIT_REASON_VMOFF] = handle_vmx_insn, + [EXIT_REASON_VMON] = handle_vmx_insn, [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, [EXIT_REASON_APIC_ACCESS] = handle_apic_access, [EXIT_REASON_WBINVD] = handle_wbinvd, diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 249540f..fe5474a 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -898,6 +898,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) case MSR_VM_HSAVE_PA: case MSR_P6_EVNTSEL0: case MSR_P6_EVNTSEL1: + case MSR_K7_EVNTSEL0: data = 0; break; case MSR_MTRRcap: diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86/kvm/x86_emulate.c index c1b6c23..616de46 100644 --- a/arch/x86/kvm/x86_emulate.c +++ b/arch/x86/kvm/x86_emulate.c @@ -1361,7 +1361,7 @@ static inline int writeback(struct x86_emulate_ctxt *ctxt, return 0; } -void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask) +static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask) { u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask); /* diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c index f456860..ff485d3 100644 --- a/arch/x86/lib/delay.c +++ b/arch/x86/lib/delay.c @@ -55,8 +55,10 @@ static void delay_tsc(unsigned long loops) preempt_disable(); cpu = smp_processor_id(); + rdtsc_barrier(); rdtscl(bclock); for (;;) { + rdtsc_barrier(); rdtscl(now); if ((now - bclock) >= loops) break; @@ -78,6 +80,7 @@ static void delay_tsc(unsigned long loops) if (unlikely(cpu != smp_processor_id())) { loops -= (now - bclock); cpu = smp_processor_id(); + rdtsc_barrier(); rdtscl(bclock); } } diff --git a/arch/x86/lib/usercopy_64.c b/arch/x86/lib/usercopy_64.c index ec13cb5..b7c2849 100644 --- a/arch/x86/lib/usercopy_64.c +++ b/arch/x86/lib/usercopy_64.c @@ -127,7 +127,7 @@ EXPORT_SYMBOL(__strnlen_user); long strnlen_user(const char __user *s, long n) { - if (!access_ok(VERIFY_READ, s, n)) + if (!access_ok(VERIFY_READ, s, 1)) return 0; return __strnlen_user(s, n); } diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index baa0e86..78a5fff 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -952,8 +952,6 @@ do_page_fault(struct pt_regs *regs, unsigned long error_code) tsk = current; mm = tsk->mm; - prefetchw(&mm->mmap_sem); - /* Get the faulting address: */ address = read_cr2(); @@ -963,6 +961,7 @@ do_page_fault(struct pt_regs *regs, unsigned long error_code) */ if (kmemcheck_active(regs)) kmemcheck_hide(regs); + prefetchw(&mm->mmap_sem); if (unlikely(kmmio_fault(regs, address))) return; @@ -1114,7 +1113,7 @@ good_area: * make sure we exit gracefully rather than endlessly redo * the fault: */ - fault = handle_mm_fault(mm, vma, address, write); + fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { mm_fault_error(regs, error_code, address, fault); diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c index 6340cef..71da1bc 100644 --- a/arch/x86/mm/gup.c +++ b/arch/x86/mm/gup.c @@ -14,7 +14,7 @@ static inline pte_t gup_get_pte(pte_t *ptep) { #ifndef CONFIG_X86_PAE - return *ptep; + return ACCESS_ONCE(*ptep); #else /* * With get_user_pages_fast, we walk down the pagetables without taking @@ -219,6 +219,62 @@ static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end, return 1; } +/* + * Like get_user_pages_fast() except its IRQ-safe in that it won't fall + * back to the regular GUP. + */ +int __get_user_pages_fast(unsigned long start, int nr_pages, int write, + struct page **pages) +{ + struct mm_struct *mm = current->mm; + unsigned long addr, len, end; + unsigned long next; + unsigned long flags; + pgd_t *pgdp; + int nr = 0; + + start &= PAGE_MASK; + addr = start; + len = (unsigned long) nr_pages << PAGE_SHIFT; + end = start + len; + if (unlikely(!access_ok(write ? VERIFY_WRITE : VERIFY_READ, + (void __user *)start, len))) + return 0; + + /* + * XXX: batch / limit 'nr', to avoid large irq off latency + * needs some instrumenting to determine the common sizes used by + * important workloads (eg. DB2), and whether limiting the batch size + * will decrease performance. + * + * It seems like we're in the clear for the moment. Direct-IO is + * the main guy that batches up lots of get_user_pages, and even + * they are limited to 64-at-a-time which is not so many. + */ + /* + * This doesn't prevent pagetable teardown, but does prevent + * the pagetables and pages from being freed on x86. + * + * So long as we atomically load page table pointers versus teardown + * (which we do on x86, with the above PAE exception), we can follow the + * address down to the the page and take a ref on it. + */ + local_irq_save(flags); + pgdp = pgd_offset(mm, addr); + do { + pgd_t pgd = *pgdp; + + next = pgd_addr_end(addr, end); + if (pgd_none(pgd)) + break; + if (!gup_pud_range(pgd, addr, next, write, pages, &nr)) + break; + } while (pgdp++, addr = next, addr != end); + local_irq_restore(flags); + + return nr; +} + /** * get_user_pages_fast() - pin user pages in memory * @start: starting user address @@ -247,11 +303,16 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, start &= PAGE_MASK; addr = start; len = (unsigned long) nr_pages << PAGE_SHIFT; + end = start + len; - if (unlikely(!access_ok(write ? VERIFY_WRITE : VERIFY_READ, - (void __user *)start, len))) + if (end < start) goto slow_irqon; +#ifdef CONFIG_X86_64 + if (end >> __VIRTUAL_MASK_SHIFT) + goto slow_irqon; +#endif + /* * XXX: batch / limit 'nr', to avoid large irq off latency * needs some instrumenting to determine the common sizes used by diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index f53b57e..47ce9a2 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -177,20 +177,6 @@ static int __meminit save_mr(struct map_range *mr, int nr_range, return nr_range; } -#ifdef CONFIG_X86_64 -static void __init init_gbpages(void) -{ - if (direct_gbpages && cpu_has_gbpages) - printk(KERN_INFO "Using GB pages for direct mapping\n"); - else - direct_gbpages = 0; -} -#else -static inline void init_gbpages(void) -{ -} -#endif - /* * Setup the direct mapping of the physical memory at PAGE_OFFSET. * This runs before bootmem is initialized and gets pages directly from @@ -210,9 +196,6 @@ unsigned long __init_refok init_memory_mapping(unsigned long start, printk(KERN_INFO "init_memory_mapping: %016lx-%016lx\n", start, end); - if (!after_bootmem) - init_gbpages(); - #if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KMEMCHECK) /* * For CONFIG_DEBUG_PAGEALLOC, identity mapping will use small pages. diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index 9c54329..c4378f4 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -527,7 +527,7 @@ phys_pud_update(pgd_t *pgd, unsigned long addr, unsigned long end, return phys_pud_init(pud, addr, end, page_size_mask); } -unsigned long __init +unsigned long __meminit kernel_physical_mapping_init(unsigned long start, unsigned long end, unsigned long page_size_mask) diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c index 3cfe9ce..1b734d7 100644 --- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c @@ -11,6 +11,7 @@ #include <linux/interrupt.h> #include <linux/seq_file.h> #include <linux/debugfs.h> +#include <linux/pfn.h> #include <asm/e820.h> #include <asm/processor.h> @@ -681,8 +682,9 @@ static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); static int cpa_process_alias(struct cpa_data *cpa) { struct cpa_data alias_cpa; - int ret = 0; - unsigned long temp_cpa_vaddr, vaddr; + unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); + unsigned long vaddr, remapped; + int ret; if (cpa->pfn >= max_pfn_mapped) return 0; @@ -706,42 +708,55 @@ static int cpa_process_alias(struct cpa_data *cpa) PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { alias_cpa = *cpa; - temp_cpa_vaddr = (unsigned long) __va(cpa->pfn << PAGE_SHIFT); - alias_cpa.vaddr = &temp_cpa_vaddr; + alias_cpa.vaddr = &laddr; alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); - ret = __change_page_attr_set_clr(&alias_cpa, 0); + if (ret) + return ret; } #ifdef CONFIG_X86_64 - if (ret) - return ret; /* - * No need to redo, when the primary call touched the high - * mapping already: - */ - if (within(vaddr, (unsigned long) _text, _brk_end)) - return 0; - - /* - * If the physical address is inside the kernel map, we need + * If the primary call didn't touch the high mapping already + * and the physical address is inside the kernel map, we need * to touch the high mapped kernel as well: */ - if (!within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) - return 0; + if (!within(vaddr, (unsigned long)_text, _brk_end) && + within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) { + unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + + __START_KERNEL_map - phys_base; + alias_cpa = *cpa; + alias_cpa.vaddr = &temp_cpa_vaddr; + alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); - alias_cpa = *cpa; - temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + __START_KERNEL_map - phys_base; - alias_cpa.vaddr = &temp_cpa_vaddr; - alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); + /* + * The high mapping range is imprecise, so ignore the + * return value. + */ + __change_page_attr_set_clr(&alias_cpa, 0); + } +#endif /* - * The high mapping range is imprecise, so ignore the return value. + * If the PMD page was partially used for per-cpu remapping, + * the recycled area needs to be split and modified. Because + * the area is always proper subset of a PMD page + * cpa->numpages is guaranteed to be 1 for these areas, so + * there's no need to loop over and check for further remaps. */ - __change_page_attr_set_clr(&alias_cpa, 0); -#endif - return ret; + remapped = (unsigned long)pcpu_lpage_remapped((void *)laddr); + if (remapped) { + WARN_ON(cpa->numpages > 1); + alias_cpa = *cpa; + alias_cpa.vaddr = &remapped; + alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); + ret = __change_page_attr_set_clr(&alias_cpa, 0); + if (ret) + return ret; + } + + return 0; } static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c index c0ecf25..b26626d 100644 --- a/arch/x86/pci/acpi.c +++ b/arch/x86/pci/acpi.c @@ -38,15 +38,26 @@ count_resource(struct acpi_resource *acpi_res, void *data) struct acpi_resource_address64 addr; acpi_status status; - if (info->res_num >= PCI_BUS_NUM_RESOURCES) - return AE_OK; - status = resource_to_addr(acpi_res, &addr); if (ACPI_SUCCESS(status)) info->res_num++; return AE_OK; } +static int +bus_has_transparent_bridge(struct pci_bus *bus) +{ + struct pci_dev *dev; + + list_for_each_entry(dev, &bus->devices, bus_list) { + u16 class = dev->class >> 8; + + if (class == PCI_CLASS_BRIDGE_PCI && dev->transparent) + return true; + } + return false; +} + static acpi_status setup_resource(struct acpi_resource *acpi_res, void *data) { @@ -56,9 +67,7 @@ setup_resource(struct acpi_resource *acpi_res, void *data) acpi_status status; unsigned long flags; struct resource *root; - - if (info->res_num >= PCI_BUS_NUM_RESOURCES) - return AE_OK; + int max_root_bus_resources = PCI_BUS_NUM_RESOURCES; status = resource_to_addr(acpi_res, &addr); if (!ACPI_SUCCESS(status)) @@ -82,6 +91,18 @@ setup_resource(struct acpi_resource *acpi_res, void *data) res->end = res->start + addr.address_length - 1; res->child = NULL; + if (bus_has_transparent_bridge(info->bus)) + max_root_bus_resources -= 3; + if (info->res_num >= max_root_bus_resources) { + printk(KERN_WARNING "PCI: Failed to allocate 0x%lx-0x%lx " + "from %s for %s due to _CRS returning more than " + "%d resource descriptors\n", (unsigned long) res->start, + (unsigned long) res->end, root->name, info->name, + max_root_bus_resources); + info->res_num++; + return AE_OK; + } + if (insert_resource(root, res)) { printk(KERN_ERR "PCI: Failed to allocate 0x%lx-0x%lx " "from %s for %s\n", (unsigned long) res->start, diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index 8766b0e..712443e 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -523,6 +523,69 @@ reject: static int __initdata known_bridge; +static int acpi_mcfg_64bit_base_addr __initdata = FALSE; + +/* The physical address of the MMCONFIG aperture. Set from ACPI tables. */ +struct acpi_mcfg_allocation *pci_mmcfg_config; +int pci_mmcfg_config_num; + +static int __init acpi_mcfg_oem_check(struct acpi_table_mcfg *mcfg) +{ + if (!strcmp(mcfg->header.oem_id, "SGI")) + acpi_mcfg_64bit_base_addr = TRUE; + + return 0; +} + +static int __init pci_parse_mcfg(struct acpi_table_header *header) +{ + struct acpi_table_mcfg *mcfg; + unsigned long i; + int config_size; + + if (!header) + return -EINVAL; + + mcfg = (struct acpi_table_mcfg *)header; + + /* how many config structures do we have */ + pci_mmcfg_config_num = 0; + i = header->length - sizeof(struct acpi_table_mcfg); + while (i >= sizeof(struct acpi_mcfg_allocation)) { + ++pci_mmcfg_config_num; + i -= sizeof(struct acpi_mcfg_allocation); + }; + if (pci_mmcfg_config_num == 0) { + printk(KERN_ERR PREFIX "MMCONFIG has no entries\n"); + return -ENODEV; + } + + config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config); + pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL); + if (!pci_mmcfg_config) { + printk(KERN_WARNING PREFIX + "No memory for MCFG config tables\n"); + return -ENOMEM; + } + + memcpy(pci_mmcfg_config, &mcfg[1], config_size); + + acpi_mcfg_oem_check(mcfg); + + for (i = 0; i < pci_mmcfg_config_num; ++i) { + if ((pci_mmcfg_config[i].address > 0xFFFFFFFF) && + !acpi_mcfg_64bit_base_addr) { + printk(KERN_ERR PREFIX + "MMCONFIG not in low 4GB of memory\n"); + kfree(pci_mmcfg_config); + pci_mmcfg_config_num = 0; + return -ENODEV; + } + } + + return 0; +} + static void __init __pci_mmcfg_init(int early) { /* MMCONFIG disabled */ @@ -543,7 +606,7 @@ static void __init __pci_mmcfg_init(int early) } if (!known_bridge) - acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg); + acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); pci_mmcfg_reject_broken(early); diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index d277ef1..b3d20b9 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -244,7 +244,7 @@ static void __restore_processor_state(struct saved_context *ctxt) do_fpu_end(); mtrr_ap_init(); -#ifdef CONFIG_X86_32 +#ifdef CONFIG_X86_OLD_MCE mcheck_init(&boot_cpu_data); #endif } diff --git a/arch/xtensa/configs/s6105_defconfig b/arch/xtensa/configs/s6105_defconfig index 768bee0..bb84fbc 100644 --- a/arch/xtensa/configs/s6105_defconfig +++ b/arch/xtensa/configs/s6105_defconfig @@ -263,7 +263,54 @@ CONFIG_HAVE_IDE=y # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set # CONFIG_MD is not set -# CONFIG_NETDEVICES is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +CONFIG_SMSC_PHY=y +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +CONFIG_S6GMAC=y +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set @@ -304,8 +351,6 @@ CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set @@ -387,7 +432,59 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set -# CONFIG_RTC_CLASS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +# CONFIG_RTC_INTF_SYSFS is not set +# CONFIG_RTC_INTF_PROC is not set +# CONFIG_RTC_INTF_DEV is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +CONFIG_RTC_DRV_M41T80=y +# CONFIG_RTC_DRV_M41T80_WDT is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set # CONFIG_STAGING is not set diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h index 8fc1c0c..b7b8fbe 100644 --- a/arch/xtensa/include/asm/cacheflush.h +++ b/arch/xtensa/include/asm/cacheflush.h @@ -155,5 +155,100 @@ extern void copy_from_user_page(struct vm_area_struct*, struct page*, #endif +#define XTENSA_CACHEBLK_LOG2 29 +#define XTENSA_CACHEBLK_SIZE (1 << XTENSA_CACHEBLK_LOG2) +#define XTENSA_CACHEBLK_MASK (7 << XTENSA_CACHEBLK_LOG2) + +#if XCHAL_HAVE_CACHEATTR +static inline u32 xtensa_get_cacheattr(void) +{ + u32 r; + asm volatile(" rsr %0, CACHEATTR" : "=a"(r)); + return r; +} + +static inline u32 xtensa_get_dtlb1(u32 addr) +{ + u32 r = addr & XTENSA_CACHEBLK_MASK; + return r | ((xtensa_get_cacheattr() >> (r >> (XTENSA_CACHEBLK_LOG2-2))) + & 0xF); +} +#else +static inline u32 xtensa_get_dtlb1(u32 addr) +{ + u32 r; + asm volatile(" rdtlb1 %0, %1" : "=a"(r) : "a"(addr)); + asm volatile(" dsync"); + return r; +} + +static inline u32 xtensa_get_cacheattr(void) +{ + u32 r = 0; + u32 a = 0; + do { + a -= XTENSA_CACHEBLK_SIZE; + r = (r << 4) | (xtensa_get_dtlb1(a) & 0xF); + } while (a); + return r; +} +#endif + +static inline int xtensa_need_flush_dma_source(u32 addr) +{ + return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) >= 4; +} + +static inline int xtensa_need_invalidate_dma_destination(u32 addr) +{ + return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) != 2; +} + +static inline void flush_dcache_unaligned(u32 addr, u32 size) +{ + u32 cnt; + if (size) { + cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr) + + XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE; + while (cnt--) { + asm volatile(" dhwb %0, 0" : : "a"(addr)); + addr += XCHAL_DCACHE_LINESIZE; + } + asm volatile(" dsync"); + } +} + +static inline void invalidate_dcache_unaligned(u32 addr, u32 size) +{ + int cnt; + if (size) { + asm volatile(" dhwbi %0, 0 ;" : : "a"(addr)); + cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr) + - XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE; + while (cnt-- > 0) { + asm volatile(" dhi %0, %1" : : "a"(addr), + "n"(XCHAL_DCACHE_LINESIZE)); + addr += XCHAL_DCACHE_LINESIZE; + } + asm volatile(" dhwbi %0, %1" : : "a"(addr), + "n"(XCHAL_DCACHE_LINESIZE)); + asm volatile(" dsync"); + } +} + +static inline void flush_invalidate_dcache_unaligned(u32 addr, u32 size) +{ + u32 cnt; + if (size) { + cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr) + + XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE; + while (cnt--) { + asm volatile(" dhwbi %0, 0" : : "a"(addr)); + addr += XCHAL_DCACHE_LINESIZE; + } + asm volatile(" dsync"); + } +} + #endif /* __KERNEL__ */ #endif /* _XTENSA_CACHEFLUSH_H */ diff --git a/arch/xtensa/include/asm/gpio.h b/arch/xtensa/include/asm/gpio.h index 0763b07..a8c9fc4 100644 --- a/arch/xtensa/include/asm/gpio.h +++ b/arch/xtensa/include/asm/gpio.h @@ -38,14 +38,14 @@ static inline int gpio_cansleep(unsigned int gpio) return __gpio_cansleep(gpio); } -/* - * Not implemented, yet. - */ static inline int gpio_to_irq(unsigned int gpio) { - return -ENOSYS; + return __gpio_to_irq(gpio); } +/* + * Not implemented, yet. + */ static inline int irq_to_gpio(unsigned int irq) { return -EINVAL; diff --git a/arch/xtensa/include/asm/irq.h b/arch/xtensa/include/asm/irq.h index dfac82d..4c0ccc9 100644 --- a/arch/xtensa/include/asm/irq.h +++ b/arch/xtensa/include/asm/irq.h @@ -11,6 +11,7 @@ #ifndef _XTENSA_IRQ_H #define _XTENSA_IRQ_H +#include <linux/init.h> #include <platform/hardware.h> #include <variant/core.h> @@ -21,11 +22,20 @@ static inline void variant_irq_enable(unsigned int irq) { } static inline void variant_irq_disable(unsigned int irq) { } #endif +#ifndef VARIANT_NR_IRQS +# define VARIANT_NR_IRQS 0 +#endif #ifndef PLATFORM_NR_IRQS # define PLATFORM_NR_IRQS 0 #endif #define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS -#define NR_IRQS (XTENSA_NR_IRQS + PLATFORM_NR_IRQS) +#define NR_IRQS (XTENSA_NR_IRQS + VARIANT_NR_IRQS + PLATFORM_NR_IRQS) + +#if VARIANT_NR_IRQS == 0 +static inline void variant_init_irq(void) { } +#else +void variant_init_irq(void) __init; +#endif static __inline__ int irq_canonicalize(int irq) { diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c index a36c85ed..a1badb3 100644 --- a/arch/xtensa/kernel/irq.c +++ b/arch/xtensa/kernel/irq.c @@ -197,4 +197,6 @@ void __init init_IRQ(void) } cached_irq_mask = 0; + + variant_init_irq(); } diff --git a/arch/xtensa/mm/fault.c b/arch/xtensa/mm/fault.c index bdd860d..bc07333 100644 --- a/arch/xtensa/mm/fault.c +++ b/arch/xtensa/mm/fault.c @@ -106,7 +106,7 @@ good_area: * the fault. */ survive: - fault = handle_mm_fault(mm, vma, address, is_write); + fault = handle_mm_fault(mm, vma, address, is_write ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; diff --git a/arch/xtensa/platforms/s6105/device.c b/arch/xtensa/platforms/s6105/device.c index 78b08be..65333ff 100644 --- a/arch/xtensa/platforms/s6105/device.c +++ b/arch/xtensa/platforms/s6105/device.c @@ -5,14 +5,27 @@ */ #include <linux/kernel.h> +#include <linux/gpio.h> #include <linux/init.h> +#include <linux/irq.h> +#include <linux/phy.h> #include <linux/platform_device.h> #include <linux/serial.h> #include <linux/serial_8250.h> #include <variant/hardware.h> +#include <variant/dmac.h> +#include <platform/gpio.h> + +#define GPIO3_INTNUM 3 #define UART_INTNUM 4 +#define GMAC_INTNUM 5 + +static const signed char gpio3_irq_mappings[] = { + S6_INTC_GPIO(3), + -1 +}; static const signed char uart_irq_mappings[] = { S6_INTC_UART(0), @@ -20,8 +33,18 @@ static const signed char uart_irq_mappings[] = { -1, }; +static const signed char gmac_irq_mappings[] = { + S6_INTC_GMAC_STAT, + S6_INTC_GMAC_ERR, + S6_INTC_DMA_HOSTTERMCNT(0), + S6_INTC_DMA_HOSTTERMCNT(1), + -1 +}; + const signed char *platform_irq_mappings[NR_IRQS] = { + [GPIO3_INTNUM] = gpio3_irq_mappings, [UART_INTNUM] = uart_irq_mappings, + [GMAC_INTNUM] = gmac_irq_mappings, }; static struct plat_serial8250_port serial_platform_data[] = { @@ -46,6 +69,66 @@ static struct plat_serial8250_port serial_platform_data[] = { { }, }; +static struct resource s6_gmac_resource[] = { + { + .name = "mem", + .start = (resource_size_t)S6_REG_GMAC, + .end = (resource_size_t)S6_REG_GMAC + 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "dma", + .start = (resource_size_t) + DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACTX), + .end = (resource_size_t) + DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACTX) + 0x100 - 1, + .flags = IORESOURCE_DMA, + }, + { + .name = "dma", + .start = (resource_size_t) + DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACRX), + .end = (resource_size_t) + DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACRX) + 0x100 - 1, + .flags = IORESOURCE_DMA, + }, + { + .name = "io", + .start = (resource_size_t)S6_MEM_GMAC, + .end = (resource_size_t)S6_MEM_GMAC + 0x2000000 - 1, + .flags = IORESOURCE_IO, + }, + { + .name = "irq", + .start = (resource_size_t)GMAC_INTNUM, + .flags = IORESOURCE_IRQ, + }, + { + .name = "irq", + .start = (resource_size_t)PHY_POLL, + .flags = IORESOURCE_IRQ, + }, +}; + +static int __init prepare_phy_irq(int pin) +{ + int irq; + if (gpio_request(pin, "s6gmac_phy") < 0) + goto fail; + if (gpio_direction_input(pin) < 0) + goto free; + irq = gpio_to_irq(pin); + if (irq < 0) + goto free; + if (set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0) + goto free; + return irq; +free: + gpio_free(pin); +fail: + return PHY_POLL; +} + static struct platform_device platform_devices[] = { { .name = "serial8250", @@ -54,12 +137,23 @@ static struct platform_device platform_devices[] = { .platform_data = serial_platform_data, }, }, + { + .name = "s6gmac", + .id = 0, + .resource = s6_gmac_resource, + .num_resources = ARRAY_SIZE(s6_gmac_resource), + }, + { + I2C_BOARD_INFO("m41t62", S6I2C_ADDR_M41T62), + }, }; static int __init device_init(void) { int i; + s6_gmac_resource[5].start = prepare_phy_irq(GPIO_PHY_IRQ); + for (i = 0; i < ARRAY_SIZE(platform_devices); i++) platform_device_register(&platform_devices[i]); return 0; diff --git a/arch/xtensa/platforms/s6105/setup.c b/arch/xtensa/platforms/s6105/setup.c index 855ddea..86ce730 100644 --- a/arch/xtensa/platforms/s6105/setup.c +++ b/arch/xtensa/platforms/s6105/setup.c @@ -35,12 +35,21 @@ void __init platform_setup(char **cmdline) { unsigned long reg; + reg = readl(S6_REG_GREG1 + S6_GREG1_PLLSEL); + reg &= ~(S6_GREG1_PLLSEL_GMAC_MASK << S6_GREG1_PLLSEL_GMAC | + S6_GREG1_PLLSEL_GMII_MASK << S6_GREG1_PLLSEL_GMII); + reg |= S6_GREG1_PLLSEL_GMAC_125MHZ << S6_GREG1_PLLSEL_GMAC | + S6_GREG1_PLLSEL_GMII_125MHZ << S6_GREG1_PLLSEL_GMII; + writel(reg, S6_REG_GREG1 + S6_GREG1_PLLSEL); + reg = readl(S6_REG_GREG1 + S6_GREG1_CLKGATE); reg &= ~(1 << S6_GREG1_BLOCK_SB); + reg &= ~(1 << S6_GREG1_BLOCK_GMAC); writel(reg, S6_REG_GREG1 + S6_GREG1_CLKGATE); reg = readl(S6_REG_GREG1 + S6_GREG1_BLOCKENA); reg |= 1 << S6_GREG1_BLOCK_SB; + reg |= 1 << S6_GREG1_BLOCK_GMAC; writel(reg, S6_REG_GREG1 + S6_GREG1_BLOCKENA); printk(KERN_NOTICE "S6105 on Stretch S6000 - " @@ -49,7 +58,7 @@ void __init platform_setup(char **cmdline) void __init platform_init(bp_tag_t *first) { - s6_gpio_init(); + s6_gpio_init(0); gpio_request(GPIO_LED1_NGREEN, "led1_green"); gpio_request(GPIO_LED1_RED, "led1_red"); gpio_direction_output(GPIO_LED1_NGREEN, 1); diff --git a/arch/xtensa/variants/s6000/Makefile b/arch/xtensa/variants/s6000/Makefile index d83f380..3e7ef0a 100644 --- a/arch/xtensa/variants/s6000/Makefile +++ b/arch/xtensa/variants/s6000/Makefile @@ -1,4 +1,4 @@ # s6000 Makefile -obj-y += irq.o gpio.o +obj-y += irq.o gpio.o dmac.o obj-$(CONFIG_XTENSA_CALIBRATE_CCOUNT) += delay.o diff --git a/arch/xtensa/variants/s6000/dmac.c b/arch/xtensa/variants/s6000/dmac.c new file mode 100644 index 0000000..dc7f7c5 --- /dev/null +++ b/arch/xtensa/variants/s6000/dmac.c @@ -0,0 +1,173 @@ +/* + * Authors: Oskar Schirmer <os@emlix.com> + * Daniel Gloeckner <dg@emlix.com> + * (c) 2008 emlix GmbH http://www.emlix.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/spinlock.h> +#include <asm/cacheflush.h> +#include <variant/dmac.h> + +/* DMA engine lookup */ + +struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB]; + + +/* DMA control, per engine */ + +void s6dmac_put_fifo_cache(u32 dmac, int chan, u32 src, u32 dst, u32 size) +{ + if (xtensa_need_flush_dma_source(src)) { + u32 base = src; + u32 span = size; + u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK); + if (chunk && (size > chunk)) { + s32 skip = + readl(DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP); + u32 gaps = (size+chunk-1)/chunk - 1; + if (skip >= 0) { + span += gaps * skip; + } else if (-skip > chunk) { + s32 decr = gaps * (chunk + skip); + base += decr; + span = chunk - decr; + } else { + span = max(span + gaps * skip, + (chunk + skip) * gaps - skip); + } + } + flush_dcache_unaligned(base, span); + } + if (xtensa_need_invalidate_dma_destination(dst)) { + u32 base = dst; + u32 span = size; + u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK); + if (chunk && (size > chunk)) { + s32 skip = + readl(DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP); + u32 gaps = (size+chunk-1)/chunk - 1; + if (skip >= 0) { + span += gaps * skip; + } else if (-skip > chunk) { + s32 decr = gaps * (chunk + skip); + base += decr; + span = chunk - decr; + } else { + span = max(span + gaps * skip, + (chunk + skip) * gaps - skip); + } + } + invalidate_dcache_unaligned(base, span); + } + s6dmac_put_fifo(dmac, chan, src, dst, size); +} + +void s6dmac_disable_error_irqs(u32 dmac, u32 mask) +{ + unsigned long flags; + spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock; + spin_lock_irqsave(spinl, flags); + _s6dmac_disable_error_irqs(dmac, mask); + spin_unlock_irqrestore(spinl, flags); +} + +u32 s6dmac_int_sources(u32 dmac, u32 channel) +{ + u32 mask, ret, tmp; + mask = 1 << channel; + + tmp = readl(dmac + S6_DMA_TERMCNTIRQSTAT); + tmp &= mask; + writel(tmp, dmac + S6_DMA_TERMCNTIRQCLR); + ret = tmp >> channel; + + tmp = readl(dmac + S6_DMA_PENDCNTIRQSTAT); + tmp &= mask; + writel(tmp, dmac + S6_DMA_PENDCNTIRQCLR); + ret |= (tmp >> channel) << 1; + + tmp = readl(dmac + S6_DMA_LOWWMRKIRQSTAT); + tmp &= mask; + writel(tmp, dmac + S6_DMA_LOWWMRKIRQCLR); + ret |= (tmp >> channel) << 2; + + tmp = readl(dmac + S6_DMA_INTRAW0); + tmp &= (mask << S6_DMA_INT0_OVER) | (mask << S6_DMA_INT0_UNDER); + writel(tmp, dmac + S6_DMA_INTCLEAR0); + + if (tmp & (mask << S6_DMA_INT0_UNDER)) + ret |= 1 << 3; + if (tmp & (mask << S6_DMA_INT0_OVER)) + ret |= 1 << 4; + + tmp = readl(dmac + S6_DMA_MASTERERRINFO); + mask <<= S6_DMA_INT1_CHANNEL; + if (((tmp >> S6_DMA_MASTERERR_CHAN(0)) & S6_DMA_MASTERERR_CHAN_MASK) + == channel) + mask |= 1 << S6_DMA_INT1_MASTER; + if (((tmp >> S6_DMA_MASTERERR_CHAN(1)) & S6_DMA_MASTERERR_CHAN_MASK) + == channel) + mask |= 1 << (S6_DMA_INT1_MASTER + 1); + if (((tmp >> S6_DMA_MASTERERR_CHAN(2)) & S6_DMA_MASTERERR_CHAN_MASK) + == channel) + mask |= 1 << (S6_DMA_INT1_MASTER + 2); + + tmp = readl(dmac + S6_DMA_INTRAW1) & mask; + writel(tmp, dmac + S6_DMA_INTCLEAR1); + ret |= ((tmp >> channel) & 1) << 5; + ret |= ((tmp >> S6_DMA_INT1_MASTER) & S6_DMA_INT1_MASTER_MASK) << 6; + + return ret; +} + +void s6dmac_release_chan(u32 dmac, int chan) +{ + if (chan >= 0) + s6dmac_disable_chan(dmac, chan); +} + + +/* global init */ + +static inline void __init dmac_init(u32 dmac, u8 chan_nb) +{ + s6dmac_ctrl[S6_DMAC_INDEX(dmac)].dmac = dmac; + spin_lock_init(&s6dmac_ctrl[S6_DMAC_INDEX(dmac)].lock); + s6dmac_ctrl[S6_DMAC_INDEX(dmac)].chan_nb = chan_nb; + writel(S6_DMA_INT1_MASTER_MASK << S6_DMA_INT1_MASTER, + dmac + S6_DMA_INTCLEAR1); +} + +static inline void __init dmac_master(u32 dmac, + u32 m0start, u32 m0end, u32 m1start, u32 m1end) +{ + writel(m0start, dmac + S6_DMA_MASTER0START); + writel(m0end - 1, dmac + S6_DMA_MASTER0END); + writel(m1start, dmac + S6_DMA_MASTER1START); + writel(m1end - 1, dmac + S6_DMA_MASTER1END); +} + +static void __init s6_dmac_init(void) +{ + dmac_init(S6_REG_LMSDMA, S6_LMSDMA_NB); + dmac_master(S6_REG_LMSDMA, + S6_MEM_DDR, S6_MEM_PCIE_APER, S6_MEM_EFI, S6_MEM_GMAC); + dmac_init(S6_REG_NIDMA, S6_NIDMA_NB); + dmac_init(S6_REG_DPDMA, S6_DPDMA_NB); + dmac_master(S6_REG_DPDMA, + S6_MEM_DDR, S6_MEM_PCIE_APER, S6_REG_DP, S6_REG_DPDMA); + dmac_init(S6_REG_HIFDMA, S6_HIFDMA_NB); + dmac_master(S6_REG_HIFDMA, + S6_MEM_GMAC, S6_MEM_PCIE_CFG, S6_MEM_PCIE_APER, S6_MEM_AUX); +} + +arch_initcall(s6_dmac_init); diff --git a/arch/xtensa/variants/s6000/gpio.c b/arch/xtensa/variants/s6000/gpio.c index 79317fd..380a70f 100644 --- a/arch/xtensa/variants/s6000/gpio.c +++ b/arch/xtensa/variants/s6000/gpio.c @@ -4,15 +4,20 @@ * Copyright (c) 2009 emlix GmbH * Authors: Oskar Schirmer <os@emlix.com> * Johannes Weiner <jw@emlix.com> + * Daniel Gloeckner <dg@emlix.com> */ +#include <linux/bitops.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/irq.h> #include <linux/gpio.h> #include <variant/hardware.h> +#define IRQ_BASE XTENSA_NR_IRQS + #define S6_GPIO_DATA 0x000 #define S6_GPIO_IS 0x404 #define S6_GPIO_IBE 0x408 @@ -52,19 +57,175 @@ static void set(struct gpio_chip *chip, unsigned int off, int val) writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off)); } +static int to_irq(struct gpio_chip *chip, unsigned offset) +{ + if (offset < 8) + return offset + IRQ_BASE; + return -EINVAL; +} + static struct gpio_chip gpiochip = { .owner = THIS_MODULE, .direction_input = direction_input, .get = get, .direction_output = direction_output, .set = set, + .to_irq = to_irq, .base = 0, .ngpio = 24, .can_sleep = 0, /* no blocking io needed */ .exported = 0, /* no exporting to userspace */ }; -int s6_gpio_init(void) +int s6_gpio_init(u32 afsel) { + writeb(afsel, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL); + writeb(afsel >> 8, S6_REG_GPIO + S6_GPIO_BANK(1) + S6_GPIO_AFSEL); + writeb(afsel >> 16, S6_REG_GPIO + S6_GPIO_BANK(2) + S6_GPIO_AFSEL); return gpiochip_add(&gpiochip); } + +static void ack(unsigned int irq) +{ + writeb(1 << (irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC); +} + +static void mask(unsigned int irq) +{ + u8 r = readb(S6_REG_GPIO + S6_GPIO_IE); + r &= ~(1 << (irq - IRQ_BASE)); + writeb(r, S6_REG_GPIO + S6_GPIO_IE); +} + +static void unmask(unsigned int irq) +{ + u8 m = readb(S6_REG_GPIO + S6_GPIO_IE); + m |= 1 << (irq - IRQ_BASE); + writeb(m, S6_REG_GPIO + S6_GPIO_IE); +} + +static int set_type(unsigned int irq, unsigned int type) +{ + const u8 m = 1 << (irq - IRQ_BASE); + irq_flow_handler_t handler; + struct irq_desc *desc; + u8 reg; + + if (type == IRQ_TYPE_PROBE) { + if ((readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL) & m) + || (readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE) & m) + || readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_DIR + + S6_GPIO_MASK(irq - IRQ_BASE))) + return 0; + type = IRQ_TYPE_EDGE_BOTH; + } + + reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS); + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) { + reg |= m; + handler = handle_level_irq; + } else { + reg &= ~m; + handler = handle_edge_irq; + } + writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS); + desc = irq_to_desc(irq); + desc->handle_irq = handler; + + reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV); + if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)) + reg |= m; + else + reg &= ~m; + writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV); + + reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE); + if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) + reg |= m; + else + reg &= ~m; + writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE); + return 0; +} + +static struct irq_chip gpioirqs = { + .name = "GPIO", + .ack = ack, + .mask = mask, + .unmask = unmask, + .set_type = set_type, +}; + +static u8 demux_masks[4]; + +static void demux_irqs(unsigned int irq, struct irq_desc *desc) +{ + u8 *mask = get_irq_desc_data(desc); + u8 pending; + int cirq; + + desc->chip->mask(irq); + desc->chip->ack(irq); + pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask; + cirq = IRQ_BASE - 1; + while (pending) { + int n = ffs(pending); + cirq += n; + pending >>= n; + generic_handle_irq(cirq); + } + desc->chip->unmask(irq); +} + +extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS]; + +void __init variant_init_irq(void) +{ + int irq, n; + writeb(0, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE); + for (irq = n = 0; irq < XTENSA_NR_IRQS; irq++) { + const signed char *mapping = platform_irq_mappings[irq]; + int alone = 1; + u8 mask; + if (!mapping) + continue; + for(mask = 0; *mapping != -1; mapping++) + switch (*mapping) { + case S6_INTC_GPIO(0): + mask |= 1 << 0; + break; + case S6_INTC_GPIO(1): + mask |= 1 << 1; + break; + case S6_INTC_GPIO(2): + mask |= 1 << 2; + break; + case S6_INTC_GPIO(3): + mask |= 0x1f << 3; + break; + default: + alone = 0; + } + if (mask) { + int cirq, i; + if (!alone) { + printk(KERN_ERR "chained irq chips can't share" + " parent irq %i\n", irq); + continue; + } + demux_masks[n] = mask; + cirq = IRQ_BASE - 1; + do { + i = ffs(mask); + cirq += i; + mask >>= i; + set_irq_chip(cirq, &gpioirqs); + set_irq_type(irq, IRQ_TYPE_LEVEL_LOW); + } while (mask); + set_irq_data(irq, demux_masks + n); + set_irq_chained_handler(irq, demux_irqs); + if (++n == ARRAY_SIZE(demux_masks)) + break; + } + } +} diff --git a/arch/xtensa/variants/s6000/include/variant/dmac.h b/arch/xtensa/variants/s6000/include/variant/dmac.h new file mode 100644 index 0000000..89ab948 --- /dev/null +++ b/arch/xtensa/variants/s6000/include/variant/dmac.h @@ -0,0 +1,387 @@ +/* + * include/asm-xtensa/variant-s6000/dmac.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 Tensilica Inc. + * Copyright (C) 2008 Emlix GmbH <info@emlix.com> + * Authors: Fabian Godehardt <fg@emlix.com> + * Oskar Schirmer <os@emlix.com> + * Daniel Gloeckner <dg@emlix.com> + */ + +#ifndef __ASM_XTENSA_S6000_DMAC_H +#define __ASM_XTENSA_S6000_DMAC_H +#include <linux/io.h> +#include <variant/hardware.h> + +/* DMA global */ + +#define S6_DMA_INTSTAT0 0x000 +#define S6_DMA_INTSTAT1 0x004 +#define S6_DMA_INTENABLE0 0x008 +#define S6_DMA_INTENABLE1 0x00C +#define S6_DMA_INTRAW0 0x010 +#define S6_DMA_INTRAW1 0x014 +#define S6_DMA_INTCLEAR0 0x018 +#define S6_DMA_INTCLEAR1 0x01C +#define S6_DMA_INTSET0 0x020 +#define S6_DMA_INTSET1 0x024 +#define S6_DMA_INT0_UNDER 0 +#define S6_DMA_INT0_OVER 16 +#define S6_DMA_INT1_CHANNEL 0 +#define S6_DMA_INT1_MASTER 16 +#define S6_DMA_INT1_MASTER_MASK 7 +#define S6_DMA_TERMCNTIRQSTAT 0x028 +#define S6_DMA_TERMCNTIRQCLR 0x02C +#define S6_DMA_TERMCNTIRQSET 0x030 +#define S6_DMA_PENDCNTIRQSTAT 0x034 +#define S6_DMA_PENDCNTIRQCLR 0x038 +#define S6_DMA_PENDCNTIRQSET 0x03C +#define S6_DMA_LOWWMRKIRQSTAT 0x040 +#define S6_DMA_LOWWMRKIRQCLR 0x044 +#define S6_DMA_LOWWMRKIRQSET 0x048 +#define S6_DMA_MASTERERRINFO 0x04C +#define S6_DMA_MASTERERR_CHAN(n) (4*(n)) +#define S6_DMA_MASTERERR_CHAN_MASK 0xF +#define S6_DMA_DESCRFIFO0 0x050 +#define S6_DMA_DESCRFIFO1 0x054 +#define S6_DMA_DESCRFIFO2 0x058 +#define S6_DMA_DESCRFIFO2_AUTODISABLE 24 +#define S6_DMA_DESCRFIFO3 0x05C +#define S6_DMA_MASTER0START 0x060 +#define S6_DMA_MASTER0END 0x064 +#define S6_DMA_MASTER1START 0x068 +#define S6_DMA_MASTER1END 0x06C +#define S6_DMA_NEXTFREE 0x070 +#define S6_DMA_NEXTFREE_CHAN 0 +#define S6_DMA_NEXTFREE_CHAN_MASK 0x1F +#define S6_DMA_NEXTFREE_ENA 16 +#define S6_DMA_NEXTFREE_ENA_MASK ((1 << 16) - 1) +#define S6_DMA_DPORTCTRLGRP(p) ((p) * 4 + 0x074) +#define S6_DMA_DPORTCTRLGRP_FRAMEREP 0 +#define S6_DMA_DPORTCTRLGRP_NRCHANS 1 +#define S6_DMA_DPORTCTRLGRP_NRCHANS_1 0 +#define S6_DMA_DPORTCTRLGRP_NRCHANS_3 1 +#define S6_DMA_DPORTCTRLGRP_NRCHANS_4 2 +#define S6_DMA_DPORTCTRLGRP_NRCHANS_2 3 +#define S6_DMA_DPORTCTRLGRP_ENA 31 + + +/* DMA per channel */ + +#define DMA_CHNL(dmac, n) ((dmac) + 0x1000 + (n) * 0x100) +#define DMA_INDEX_CHNL(addr) (((addr) >> 8) & 0xF) +#define DMA_MASK_DMAC(addr) ((addr) & 0xFFFF0000) +#define S6_DMA_CHNCTRL 0x000 +#define S6_DMA_CHNCTRL_ENABLE 0 +#define S6_DMA_CHNCTRL_PAUSE 1 +#define S6_DMA_CHNCTRL_PRIO 2 +#define S6_DMA_CHNCTRL_PRIO_MASK 3 +#define S6_DMA_CHNCTRL_PERIPHXFER 4 +#define S6_DMA_CHNCTRL_PERIPHENA 5 +#define S6_DMA_CHNCTRL_SRCINC 6 +#define S6_DMA_CHNCTRL_DSTINC 7 +#define S6_DMA_CHNCTRL_BURSTLOG 8 +#define S6_DMA_CHNCTRL_BURSTLOG_MASK 7 +#define S6_DMA_CHNCTRL_DESCFIFODEPTH 12 +#define S6_DMA_CHNCTRL_DESCFIFODEPTH_MASK 0x1F +#define S6_DMA_CHNCTRL_DESCFIFOFULL 17 +#define S6_DMA_CHNCTRL_BWCONSEL 18 +#define S6_DMA_CHNCTRL_BWCONENA 19 +#define S6_DMA_CHNCTRL_PENDGCNTSTAT 20 +#define S6_DMA_CHNCTRL_PENDGCNTSTAT_MASK 0x3F +#define S6_DMA_CHNCTRL_LOWWMARK 26 +#define S6_DMA_CHNCTRL_LOWWMARK_MASK 0xF +#define S6_DMA_CHNCTRL_TSTAMP 30 +#define S6_DMA_TERMCNTNB 0x004 +#define S6_DMA_TERMCNTNB_MASK 0xFFFF +#define S6_DMA_TERMCNTTMO 0x008 +#define S6_DMA_TERMCNTSTAT 0x00C +#define S6_DMA_TERMCNTSTAT_MASK 0xFF +#define S6_DMA_CMONCHUNK 0x010 +#define S6_DMA_SRCSKIP 0x014 +#define S6_DMA_DSTSKIP 0x018 +#define S6_DMA_CUR_SRC 0x024 +#define S6_DMA_CUR_DST 0x028 +#define S6_DMA_TIMESTAMP 0x030 + +/* DMA channel lists */ + +#define S6_DPDMA_CHAN(stream, channel) (4 * (stream) + (channel)) +#define S6_DPDMA_NB 16 + +#define S6_HIFDMA_GMACTX 0 +#define S6_HIFDMA_GMACRX 1 +#define S6_HIFDMA_I2S0 2 +#define S6_HIFDMA_I2S1 3 +#define S6_HIFDMA_EGIB 4 +#define S6_HIFDMA_PCITX 5 +#define S6_HIFDMA_PCIRX 6 +#define S6_HIFDMA_NB 7 + +#define S6_NIDMA_NB 4 + +#define S6_LMSDMA_NB 12 + +/* controller access */ + +#define S6_DMAC_NB 4 +#define S6_DMAC_INDEX(dmac) (((unsigned)(dmac) >> 18) % S6_DMAC_NB) + +struct s6dmac_ctrl { + u32 dmac; + spinlock_t lock; + u8 chan_nb; +}; + +extern struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB]; + + +/* DMA control, per channel */ + +static inline int s6dmac_fifo_full(u32 dmac, int chan) +{ + return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) + & (1 << S6_DMA_CHNCTRL_DESCFIFOFULL)) && 1; +} + +static inline int s6dmac_termcnt_irq(u32 dmac, int chan) +{ + u32 m = 1 << chan; + int r = (readl(dmac + S6_DMA_TERMCNTIRQSTAT) & m) && 1; + if (r) + writel(m, dmac + S6_DMA_TERMCNTIRQCLR); + return r; +} + +static inline int s6dmac_pendcnt_irq(u32 dmac, int chan) +{ + u32 m = 1 << chan; + int r = (readl(dmac + S6_DMA_PENDCNTIRQSTAT) & m) && 1; + if (r) + writel(m, dmac + S6_DMA_PENDCNTIRQCLR); + return r; +} + +static inline int s6dmac_lowwmark_irq(u32 dmac, int chan) +{ + int r = (readl(dmac + S6_DMA_LOWWMRKIRQSTAT) & (1 << chan)) ? 1 : 0; + if (r) + writel(1 << chan, dmac + S6_DMA_LOWWMRKIRQCLR); + return r; +} + +static inline u32 s6dmac_pending_count(u32 dmac, int chan) +{ + return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) + >> S6_DMA_CHNCTRL_PENDGCNTSTAT) + & S6_DMA_CHNCTRL_PENDGCNTSTAT_MASK; +} + +static inline void s6dmac_set_terminal_count(u32 dmac, int chan, u32 n) +{ + n &= S6_DMA_TERMCNTNB_MASK; + n |= readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB) + & ~S6_DMA_TERMCNTNB_MASK; + writel(n, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB); +} + +static inline u32 s6dmac_get_terminal_count(u32 dmac, int chan) +{ + return (readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB)) + & S6_DMA_TERMCNTNB_MASK; +} + +static inline u32 s6dmac_timestamp(u32 dmac, int chan) +{ + return readl(DMA_CHNL(dmac, chan) + S6_DMA_TIMESTAMP); +} + +static inline u32 s6dmac_cur_src(u32 dmac, int chan) +{ + return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_SRC); +} + +static inline u32 s6dmac_cur_dst(u32 dmac, int chan) +{ + return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_DST); +} + +static inline void s6dmac_disable_chan(u32 dmac, int chan) +{ + u32 ctrl; + writel(readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) + & ~(1 << S6_DMA_CHNCTRL_ENABLE), + DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL); + do + ctrl = readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL); + while (ctrl & (1 << S6_DMA_CHNCTRL_ENABLE)); +} + +static inline void s6dmac_set_stride_skip(u32 dmac, int chan, + int comchunk, /* 0: disable scatter/gather */ + int srcskip, int dstskip) +{ + writel(comchunk, DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK); + writel(srcskip, DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP); + writel(dstskip, DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP); +} + +static inline void s6dmac_enable_chan(u32 dmac, int chan, + int prio, /* 0 (highest) .. 3 (lowest) */ + int periphxfer, /* <0: disable p.req.line, 0..1: mode */ + int srcinc, int dstinc, /* 0: dont increment src/dst address */ + int comchunk, /* 0: disable scatter/gather */ + int srcskip, int dstskip, + int burstsize, /* 4 for I2S, 7 for everything else */ + int bandwidthconserve, /* <0: disable, 0..1: select */ + int lowwmark, /* 0..15 */ + int timestamp, /* 0: disable timestamp */ + int enable) /* 0: disable for now */ +{ + writel(1, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB); + writel(0, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTTMO); + writel(lowwmark << S6_DMA_CHNCTRL_LOWWMARK, + DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL); + s6dmac_set_stride_skip(dmac, chan, comchunk, srcskip, dstskip); + writel(((enable ? 1 : 0) << S6_DMA_CHNCTRL_ENABLE) | + (prio << S6_DMA_CHNCTRL_PRIO) | + (((periphxfer > 0) ? 1 : 0) << S6_DMA_CHNCTRL_PERIPHXFER) | + (((periphxfer < 0) ? 0 : 1) << S6_DMA_CHNCTRL_PERIPHENA) | + ((srcinc ? 1 : 0) << S6_DMA_CHNCTRL_SRCINC) | + ((dstinc ? 1 : 0) << S6_DMA_CHNCTRL_DSTINC) | + (burstsize << S6_DMA_CHNCTRL_BURSTLOG) | + (((bandwidthconserve > 0) ? 1 : 0) << S6_DMA_CHNCTRL_BWCONSEL) | + (((bandwidthconserve < 0) ? 0 : 1) << S6_DMA_CHNCTRL_BWCONENA) | + (lowwmark << S6_DMA_CHNCTRL_LOWWMARK) | + ((timestamp ? 1 : 0) << S6_DMA_CHNCTRL_TSTAMP), + DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL); +} + + +/* DMA control, per engine */ + +static inline unsigned _dmac_addr_index(u32 dmac) +{ + unsigned i = S6_DMAC_INDEX(dmac); + if (s6dmac_ctrl[i].dmac != dmac) + BUG(); + return i; +} + +static inline void _s6dmac_disable_error_irqs(u32 dmac, u32 mask) +{ + writel(mask, dmac + S6_DMA_TERMCNTIRQCLR); + writel(mask, dmac + S6_DMA_PENDCNTIRQCLR); + writel(mask, dmac + S6_DMA_LOWWMRKIRQCLR); + writel(readl(dmac + S6_DMA_INTENABLE0) + & ~((mask << S6_DMA_INT0_UNDER) | (mask << S6_DMA_INT0_OVER)), + dmac + S6_DMA_INTENABLE0); + writel(readl(dmac + S6_DMA_INTENABLE1) & ~(mask << S6_DMA_INT1_CHANNEL), + dmac + S6_DMA_INTENABLE1); + writel((mask << S6_DMA_INT0_UNDER) | (mask << S6_DMA_INT0_OVER), + dmac + S6_DMA_INTCLEAR0); + writel(mask << S6_DMA_INT1_CHANNEL, dmac + S6_DMA_INTCLEAR1); +} + +/* + * request channel from specified engine + * with chan<0, accept any channel + * further parameters see s6dmac_enable_chan + * returns < 0 upon error, channel nb otherwise + */ +static inline int s6dmac_request_chan(u32 dmac, int chan, + int prio, + int periphxfer, + int srcinc, int dstinc, + int comchunk, + int srcskip, int dstskip, + int burstsize, + int bandwidthconserve, + int lowwmark, + int timestamp, + int enable) +{ + int r = chan; + unsigned long flags; + spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock; + spin_lock_irqsave(spinl, flags); + if (r < 0) { + r = (readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_CHAN) + & S6_DMA_NEXTFREE_CHAN_MASK; + } + if (r >= s6dmac_ctrl[_dmac_addr_index(dmac)].chan_nb) { + if (chan < 0) + r = -EBUSY; + else + r = -ENXIO; + } else if (((readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_ENA) + >> r) & 1) { + r = -EBUSY; + } else { + s6dmac_enable_chan(dmac, r, prio, periphxfer, + srcinc, dstinc, comchunk, srcskip, dstskip, burstsize, + bandwidthconserve, lowwmark, timestamp, enable); + } + spin_unlock_irqrestore(spinl, flags); + return r; +} + +static inline void s6dmac_put_fifo(u32 dmac, int chan, + u32 src, u32 dst, u32 size) +{ + unsigned long flags; + spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock; + spin_lock_irqsave(spinl, flags); + writel(src, dmac + S6_DMA_DESCRFIFO0); + writel(dst, dmac + S6_DMA_DESCRFIFO1); + writel(size, dmac + S6_DMA_DESCRFIFO2); + writel(chan, dmac + S6_DMA_DESCRFIFO3); + spin_unlock_irqrestore(spinl, flags); +} + +static inline u32 s6dmac_channel_enabled(u32 dmac, int chan) +{ + return readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) & + (1 << S6_DMA_CHNCTRL_ENABLE); +} + +/* + * group 1-4 data port channels + * with port=0..3, nrch=1-4 channels, + * frrep=0/1 (dis- or enable frame repeat) + */ +static inline void s6dmac_dp_setup_group(u32 dmac, int port, + int nrch, int frrep) +{ + const static u8 mask[4] = {0, 3, 1, 2}; + BUG_ON(dmac != S6_REG_DPDMA); + if ((port < 0) || (port > 3) || (nrch < 1) || (nrch > 4)) + return; + writel((mask[nrch - 1] << S6_DMA_DPORTCTRLGRP_NRCHANS) + | ((frrep ? 1 : 0) << S6_DMA_DPORTCTRLGRP_FRAMEREP), + dmac + S6_DMA_DPORTCTRLGRP(port)); +} + +static inline void s6dmac_dp_switch_group(u32 dmac, int port, int enable) +{ + u32 tmp; + BUG_ON(dmac != S6_REG_DPDMA); + tmp = readl(dmac + S6_DMA_DPORTCTRLGRP(port)); + if (enable) + tmp |= (1 << S6_DMA_DPORTCTRLGRP_ENA); + else + tmp &= ~(1 << S6_DMA_DPORTCTRLGRP_ENA); + writel(tmp, dmac + S6_DMA_DPORTCTRLGRP(port)); +} + +extern void s6dmac_put_fifo_cache(u32 dmac, int chan, + u32 src, u32 dst, u32 size); +extern void s6dmac_disable_error_irqs(u32 dmac, u32 mask); +extern u32 s6dmac_int_sources(u32 dmac, u32 channel); +extern void s6dmac_release_chan(u32 dmac, int chan); + +#endif /* __ASM_XTENSA_S6000_DMAC_H */ diff --git a/arch/xtensa/variants/s6000/include/variant/gpio.h b/arch/xtensa/variants/s6000/include/variant/gpio.h index 8327f62..8484ab0 100644 --- a/arch/xtensa/variants/s6000/include/variant/gpio.h +++ b/arch/xtensa/variants/s6000/include/variant/gpio.h @@ -1,6 +1,6 @@ #ifndef _XTENSA_VARIANT_S6000_GPIO_H #define _XTENSA_VARIANT_S6000_GPIO_H -extern int s6_gpio_init(void); +extern int s6_gpio_init(u32 afsel); #endif /* _XTENSA_VARIANT_S6000_GPIO_H */ diff --git a/arch/xtensa/variants/s6000/include/variant/irq.h b/arch/xtensa/variants/s6000/include/variant/irq.h index fa031cb..97d6fc4 100644 --- a/arch/xtensa/variants/s6000/include/variant/irq.h +++ b/arch/xtensa/variants/s6000/include/variant/irq.h @@ -1,9 +1,9 @@ -#ifndef __XTENSA_S6000_IRQ_H -#define __XTENSA_S6000_IRQ_H +#ifndef _XTENSA_S6000_IRQ_H +#define _XTENSA_S6000_IRQ_H #define NO_IRQ (-1) +#define VARIANT_NR_IRQS 8 /* GPIO interrupts */ extern void variant_irq_enable(unsigned int irq); -extern void variant_irq_disable(unsigned int irq); #endif /* __XTENSA_S6000_IRQ_H */ |
