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Diffstat (limited to 'arch/sh/kernel/cpu/init.c')
-rw-r--r--arch/sh/kernel/cpu/init.c30
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index 6c3c768..4b339a6 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -48,7 +48,7 @@ static void __init cache_init(void)
{
unsigned long ccr, flags;
- if (cpu_data->type == CPU_SH_NONE)
+ if (current_cpu_data.type == CPU_SH_NONE)
panic("Unknown CPU");
jump_to_P2();
@@ -68,7 +68,7 @@ static void __init cache_init(void)
if (ccr & CCR_CACHE_ENABLE) {
unsigned long ways, waysize, addrstart;
- waysize = cpu_data->dcache.sets;
+ waysize = current_cpu_data.dcache.sets;
#ifdef CCR_CACHE_ORA
/*
@@ -79,7 +79,7 @@ static void __init cache_init(void)
waysize >>= 1;
#endif
- waysize <<= cpu_data->dcache.entry_shift;
+ waysize <<= current_cpu_data.dcache.entry_shift;
#ifdef CCR_CACHE_EMODE
/* If EMODE is not set, we only have 1 way to flush. */
@@ -87,7 +87,7 @@ static void __init cache_init(void)
ways = 1;
else
#endif
- ways = cpu_data->dcache.ways;
+ ways = current_cpu_data.dcache.ways;
addrstart = CACHE_OC_ADDRESS_ARRAY;
do {
@@ -95,10 +95,10 @@ static void __init cache_init(void)
for (addr = addrstart;
addr < addrstart + waysize;
- addr += cpu_data->dcache.linesz)
+ addr += current_cpu_data.dcache.linesz)
ctrl_outl(0, addr);
- addrstart += cpu_data->dcache.way_incr;
+ addrstart += current_cpu_data.dcache.way_incr;
} while (--ways);
}
@@ -110,7 +110,7 @@ static void __init cache_init(void)
#ifdef CCR_CACHE_EMODE
/* Force EMODE if possible */
- if (cpu_data->dcache.ways > 1)
+ if (current_cpu_data.dcache.ways > 1)
flags |= CCR_CACHE_EMODE;
else
flags &= ~CCR_CACHE_EMODE;
@@ -127,10 +127,10 @@ static void __init cache_init(void)
#ifdef CONFIG_SH_OCRAM
/* Turn on OCRAM -- halve the OC */
flags |= CCR_CACHE_ORA;
- cpu_data->dcache.sets >>= 1;
+ current_cpu_data.dcache.sets >>= 1;
- cpu_data->dcache.way_size = cpu_data->dcache.sets *
- cpu_data->dcache.linesz;
+ current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
+ current_cpu_data.dcache.linesz;
#endif
ctrl_outl(flags, CCR);
@@ -172,7 +172,7 @@ static void __init dsp_init(void)
/* If the DSP bit is still set, this CPU has a DSP */
if (sr & SR_DSP)
- cpu_data->flags |= CPU_HAS_DSP;
+ current_cpu_data.flags |= CPU_HAS_DSP;
/* Now that we've determined the DSP status, clear the DSP bit. */
release_dsp();
@@ -204,18 +204,18 @@ asmlinkage void __init sh_cpu_init(void)
cache_init();
shm_align_mask = max_t(unsigned long,
- cpu_data->dcache.way_size - 1,
+ current_cpu_data.dcache.way_size - 1,
PAGE_SIZE - 1);
/* Disable the FPU */
if (fpu_disabled) {
printk("FPU Disabled\n");
- cpu_data->flags &= ~CPU_HAS_FPU;
+ current_cpu_data.flags &= ~CPU_HAS_FPU;
disable_fpu();
}
/* FPU initialization */
- if ((cpu_data->flags & CPU_HAS_FPU)) {
+ if ((current_cpu_data.flags & CPU_HAS_FPU)) {
clear_thread_flag(TIF_USEDFPU);
clear_used_math();
}
@@ -233,7 +233,7 @@ asmlinkage void __init sh_cpu_init(void)
/* Disable the DSP */
if (dsp_disabled) {
printk("DSP Disabled\n");
- cpu_data->flags &= ~CPU_HAS_DSP;
+ current_cpu_data.flags &= ~CPU_HAS_DSP;
release_dsp();
}
#endif
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