diff options
Diffstat (limited to 'arch/ppc')
28 files changed, 44 insertions, 55 deletions
diff --git a/arch/ppc/8xx_io/cs4218_tdm.c b/arch/ppc/8xx_io/cs4218_tdm.c index 89fe0ce..2ca9ec7 100644 --- a/arch/ppc/8xx_io/cs4218_tdm.c +++ b/arch/ppc/8xx_io/cs4218_tdm.c @@ -1380,7 +1380,7 @@ static void cs_nosound(unsigned long xx) spin_unlock_irqrestore(&cs4218_lock, flags); } -static struct timer_list beep_timer = TIMER_INITIALIZER(cs_nosound, 0, 0); +static DEFINE_TIMER(beep_timer, cs_nosound, 0, 0); }; static void cs_mksound(unsigned int hz, unsigned int ticks) diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig index 6ab7e5e..e3f1ce3 100644 --- a/arch/ppc/Kconfig +++ b/arch/ppc/Kconfig @@ -499,11 +499,6 @@ config WINCEPT MPC821 PowerPC, introduced in 1998 and designed to be used in thin-client machines. Say Y to support it directly. - Be aware that PCI buses can only function when SYS board is plugged - into the PIB (Platform IO Board) board from Freescale which provide - 3 PCI slots. The PIBs PCI initialization is the bootloader's - responsiblilty. - endchoice choice @@ -680,6 +675,11 @@ config MPC834x_SYS help This option enables support for the MPC 834x SYS evaluation board. + Be aware that PCI buses can only function when SYS board is plugged + into the PIB (Platform IO Board) board from Freescale which provide + 3 PCI slots. The PIBs PCI initialization is the bootloader's + responsiblilty. + config EV64360 bool "Marvell-EV64360BP" help diff --git a/arch/ppc/Makefile b/arch/ppc/Makefile index d1b6e6d..4b3fe39 100644 --- a/arch/ppc/Makefile +++ b/arch/ppc/Makefile @@ -105,13 +105,7 @@ archclean: $(Q)$(MAKE) $(clean)=arch/ppc/boot $(Q)rm -rf include3 -prepare: include/asm-$(ARCH)/offsets.h checkbin - -arch/$(ARCH)/kernel/asm-offsets.s: include/asm include/linux/version.h \ - include/config/MARKER - -include/asm-$(ARCH)/offsets.h: arch/$(ARCH)/kernel/asm-offsets.s - $(call filechk,gen-asm-offsets) +prepare: checkbin # Temporary hack until we have migrated to asm-powerpc include/asm: include3/asm @@ -143,7 +137,5 @@ checkbin: false ; \ fi -CLEAN_FILES += include/asm-$(ARCH)/offsets.h \ - arch/$(ARCH)/kernel/asm-offsets.s \ - $(TOUT) +CLEAN_FILES += $(TOUT) diff --git a/arch/ppc/boot/common/ns16550.c b/arch/ppc/boot/common/ns16550.c index 9017c54..26818bb 100644 --- a/arch/ppc/boot/common/ns16550.c +++ b/arch/ppc/boot/common/ns16550.c @@ -23,7 +23,7 @@ static int shift; unsigned long serial_init(int chan, void *ignored) { - unsigned long com_port; + unsigned long com_port, base_baud; unsigned char lcr, dlm; /* We need to find out which type io we're expecting. If it's @@ -43,6 +43,8 @@ unsigned long serial_init(int chan, void *ignored) /* How far apart the registers are. */ shift = rs_table[chan].iomem_reg_shift; + /* Base baud.. */ + base_baud = rs_table[chan].baud_base; /* save the LCR */ lcr = inb(com_port + (UART_LCR << shift)); @@ -62,9 +64,9 @@ unsigned long serial_init(int chan, void *ignored) else { /* Input clock. */ outb(com_port + (UART_DLL << shift), - (BASE_BAUD / SERIAL_BAUD) & 0xFF); + (base_baud / SERIAL_BAUD) & 0xFF); outb(com_port + (UART_DLM << shift), - (BASE_BAUD / SERIAL_BAUD) >> 8); + (base_baud / SERIAL_BAUD) >> 8); /* 8 data, 1 stop, no parity */ outb(com_port + (UART_LCR << shift), 0x03); /* RTS/DTR */ diff --git a/arch/ppc/boot/common/util.S b/arch/ppc/boot/common/util.S index 47e6414..c96c9f8 100644 --- a/arch/ppc/boot/common/util.S +++ b/arch/ppc/boot/common/util.S @@ -252,7 +252,7 @@ _GLOBAL(flush_instruction_cache) 1: dcbf r0,r3 # Flush the data cache icbi r0,r3 # Invalidate the instruction cache addi r3,r3,0x10 # Increment by one cache line - cmplwi cr0,r3,r4 # Are we at the end yet? + cmplw cr0,r3,r4 # Are we at the end yet? blt 1b # No, keep flushing and invalidating #else /* Enable, invalidate and then disable the L1 icache/dcache. */ diff --git a/arch/ppc/kernel/Makefile b/arch/ppc/kernel/Makefile index b1457a8..1fb92f1 100644 --- a/arch/ppc/kernel/Makefile +++ b/arch/ppc/kernel/Makefile @@ -15,8 +15,9 @@ extra-y += vmlinux.lds obj-y := entry.o traps.o irq.o idle.o time.o misc.o \ process.o signal.o ptrace.o align.o \ semaphore.o syscalls.o setup.o \ - cputable.o ppc_htab.o perfmon.o + cputable.o ppc_htab.o obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o +obj-$(CONFIG_E500) += perfmon.o obj-$(CONFIG_SOFTWARE_SUSPEND) += swsusp.o obj-$(CONFIG_POWER4) += cpu_setup_power4.o obj-$(CONFIG_MODULES) += module.o ppc_ksyms.o diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S index bd037ca..1f37b7e 100644 --- a/arch/ppc/kernel/cpu_setup_6xx.S +++ b/arch/ppc/kernel/cpu_setup_6xx.S @@ -15,7 +15,7 @@ #include <asm/ppc_asm.h> #include <asm/cputable.h> #include <asm/ppc_asm.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> #include <asm/cache.h> _GLOBAL(__setup_cpu_601) diff --git a/arch/ppc/kernel/cpu_setup_power4.S b/arch/ppc/kernel/cpu_setup_power4.S index f2ea1a9..304589a 100644 --- a/arch/ppc/kernel/cpu_setup_power4.S +++ b/arch/ppc/kernel/cpu_setup_power4.S @@ -15,7 +15,7 @@ #include <asm/ppc_asm.h> #include <asm/cputable.h> #include <asm/ppc_asm.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> #include <asm/cache.h> _GLOBAL(__970_cpu_preinit) diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S index cb83045..03d4886 100644 --- a/arch/ppc/kernel/entry.S +++ b/arch/ppc/kernel/entry.S @@ -29,7 +29,7 @@ #include <asm/cputable.h> #include <asm/thread_info.h> #include <asm/ppc_asm.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> #include <asm/unistd.h> #undef SHOW_SYSCALLS diff --git a/arch/ppc/kernel/fpu.S b/arch/ppc/kernel/fpu.S index 6189b26..665d7d3 100644 --- a/arch/ppc/kernel/fpu.S +++ b/arch/ppc/kernel/fpu.S @@ -18,7 +18,7 @@ #include <asm/cache.h> #include <asm/thread_info.h> #include <asm/ppc_asm.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> /* * This task wants to use the FPU now. diff --git a/arch/ppc/kernel/head.S b/arch/ppc/kernel/head.S index a931d77..55daf12 100644 --- a/arch/ppc/kernel/head.S +++ b/arch/ppc/kernel/head.S @@ -31,7 +31,7 @@ #include <asm/cache.h> #include <asm/thread_info.h> #include <asm/ppc_asm.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> #ifdef CONFIG_APUS #include <asm/amigappc.h> diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S index 9e68e32..599245b 100644 --- a/arch/ppc/kernel/head_44x.S +++ b/arch/ppc/kernel/head_44x.S @@ -40,7 +40,7 @@ #include <asm/cputable.h> #include <asm/thread_info.h> #include <asm/ppc_asm.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> #include "head_booke.h" diff --git a/arch/ppc/kernel/head_4xx.S b/arch/ppc/kernel/head_4xx.S index ca9518b..8562b80 100644 --- a/arch/ppc/kernel/head_4xx.S +++ b/arch/ppc/kernel/head_4xx.S @@ -40,7 +40,7 @@ #include <asm/cputable.h> #include <asm/thread_info.h> #include <asm/ppc_asm.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> /* As with the other PowerPC ports, it is expected that when code * execution begins here, the following registers contain valid, yet diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index eb18cad..cb1a3a5 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -30,7 +30,7 @@ #include <asm/cputable.h> #include <asm/thread_info.h> #include <asm/ppc_asm.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> /* Macro to make the code more readable. */ #ifdef CONFIG_8xx_CPU6 diff --git a/arch/ppc/kernel/head_fsl_booke.S b/arch/ppc/kernel/head_fsl_booke.S index 4028f4c..8e52e84 100644 --- a/arch/ppc/kernel/head_fsl_booke.S +++ b/arch/ppc/kernel/head_fsl_booke.S @@ -41,7 +41,7 @@ #include <asm/cputable.h> #include <asm/thread_info.h> #include <asm/ppc_asm.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> #include "head_booke.h" /* As with the other PowerPC ports, it is expected that when code diff --git a/arch/ppc/kernel/idle_6xx.S b/arch/ppc/kernel/idle_6xx.S index 25d009c..1a2194c 100644 --- a/arch/ppc/kernel/idle_6xx.S +++ b/arch/ppc/kernel/idle_6xx.S @@ -20,7 +20,7 @@ #include <asm/cputable.h> #include <asm/thread_info.h> #include <asm/ppc_asm.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> #undef DEBUG diff --git a/arch/ppc/kernel/idle_power4.S b/arch/ppc/kernel/idle_power4.S index 73a58ff..cc0d535 100644 --- a/arch/ppc/kernel/idle_power4.S +++ b/arch/ppc/kernel/idle_power4.S @@ -20,7 +20,7 @@ #include <asm/cputable.h> #include <asm/thread_info.h> #include <asm/ppc_asm.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> #undef DEBUG diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S index ce71b4a..90d917d 100644 --- a/arch/ppc/kernel/misc.S +++ b/arch/ppc/kernel/misc.S @@ -23,7 +23,7 @@ #include <asm/mmu.h> #include <asm/ppc_asm.h> #include <asm/thread_info.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> .text diff --git a/arch/ppc/kernel/swsusp.S b/arch/ppc/kernel/swsusp.S index 55148bb..69773cc 100644 --- a/arch/ppc/kernel/swsusp.S +++ b/arch/ppc/kernel/swsusp.S @@ -5,7 +5,7 @@ #include <asm/cputable.h> #include <asm/thread_info.h> #include <asm/ppc_asm.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> /* diff --git a/arch/ppc/kernel/syscalls.c b/arch/ppc/kernel/syscalls.c index 124313c..127f040 100644 --- a/arch/ppc/kernel/syscalls.c +++ b/arch/ppc/kernel/syscalls.c @@ -41,10 +41,6 @@ #include <asm/ipc.h> #include <asm/semaphore.h> -void -check_bugs(void) -{ -} /* * sys_ipc() is the de-multiplexer for the SysV IPC calls.. diff --git a/arch/ppc/kernel/traps.c b/arch/ppc/kernel/traps.c index d87423d..8356d54 100644 --- a/arch/ppc/kernel/traps.c +++ b/arch/ppc/kernel/traps.c @@ -849,10 +849,12 @@ void AltivecAssistException(struct pt_regs *regs) } #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_E500 void PerformanceMonitorException(struct pt_regs *regs) { perf_irq(regs); } +#endif #ifdef CONFIG_FSL_BOOKE void CacheLockingException(struct pt_regs *regs, unsigned long address, diff --git a/arch/ppc/mm/hashtable.S b/arch/ppc/mm/hashtable.S index ab83132..3ec87c9 100644 --- a/arch/ppc/mm/hashtable.S +++ b/arch/ppc/mm/hashtable.S @@ -30,7 +30,7 @@ #include <asm/cputable.h> #include <asm/ppc_asm.h> #include <asm/thread_info.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> #ifdef CONFIG_SMP .comm mmu_hash_lock,4 diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c index 0fd3442..d6b2b19 100644 --- a/arch/ppc/platforms/4xx/ebony.c +++ b/arch/ppc/platforms/4xx/ebony.c @@ -91,15 +91,10 @@ ebony_calibrate_decr(void) * on Rev. C silicon then errata forces us to * use the internal clock. */ - switch (PVR_REV(mfspr(SPRN_PVR))) { - case PVR_REV(PVR_440GP_RB): - freq = EBONY_440GP_RB_SYSCLK; - break; - case PVR_REV(PVR_440GP_RC1): - default: - freq = EBONY_440GP_RC_SYSCLK; - break; - } + if (strcmp(cur_cpu_spec[0]->cpu_name, "440GP Rev. B") == 0) + freq = EBONY_440GP_RB_SYSCLK; + else + freq = EBONY_440GP_RC_SYSCLK; ibm44x_calibrate_decr(freq); } diff --git a/arch/ppc/platforms/hdpu.c b/arch/ppc/platforms/hdpu.c index b659d7b..ff37968 100644 --- a/arch/ppc/platforms/hdpu.c +++ b/arch/ppc/platforms/hdpu.c @@ -58,7 +58,7 @@ static void parse_bootinfo(unsigned long r3, static void hdpu_set_l1pe(void); static void hdpu_cpustate_set(unsigned char new_state); #ifdef CONFIG_SMP -static spinlock_t timebase_lock = SPIN_LOCK_UNLOCKED; +static DEFINE_SPINLOCK(timebase_lock); static unsigned int timebase_upper = 0, timebase_lower = 0; extern int smp_tb_synchronized; diff --git a/arch/ppc/platforms/pmac_sleep.S b/arch/ppc/platforms/pmac_sleep.S index 016a746..8d67adc 100644 --- a/arch/ppc/platforms/pmac_sleep.S +++ b/arch/ppc/platforms/pmac_sleep.S @@ -17,7 +17,7 @@ #include <asm/cputable.h> #include <asm/cache.h> #include <asm/thread_info.h> -#include <asm/offsets.h> +#include <asm/asm-offsets.h> #define MAGIC 0x4c617273 /* 'Lars' */ diff --git a/arch/ppc/syslib/ibm440gx_common.c b/arch/ppc/syslib/ibm440gx_common.c index d4776af..0bb9198 100644 --- a/arch/ppc/syslib/ibm440gx_common.c +++ b/arch/ppc/syslib/ibm440gx_common.c @@ -236,9 +236,10 @@ void __init ibm440gx_l2c_setup(struct ibm44x_clocks* p) /* Disable L2C on rev.A, rev.B and 800MHz version of rev.C, enable it on all other revisions */ - u32 pvr = mfspr(SPRN_PVR); - if (pvr == PVR_440GX_RA || pvr == PVR_440GX_RB || - (pvr == PVR_440GX_RC && p->cpu > 667000000)) + if (strcmp(cur_cpu_spec[0]->cpu_name, "440GX Rev. A") == 0 || + strcmp(cur_cpu_spec[0]->cpu_name, "440GX Rev. B") == 0 + || (strcmp(cur_cpu_spec[0]->cpu_name, "440GX Rev. C") + == 0 && p->cpu > 667000000)) ibm440gx_l2c_disable(); else ibm440gx_l2c_enable(); diff --git a/arch/ppc/syslib/mv64x60.c b/arch/ppc/syslib/mv64x60.c index 6262b11..839f887 100644 --- a/arch/ppc/syslib/mv64x60.c +++ b/arch/ppc/syslib/mv64x60.c @@ -31,7 +31,7 @@ u8 mv64x60_pci_exclude_bridge = 1; -spinlock_t mv64x60_lock = SPIN_LOCK_UNLOCKED; +DEFINE_SPINLOCK(mv64x60_lock); static phys_addr_t mv64x60_bridge_pbase; static void *mv64x60_bridge_vbase; diff --git a/arch/ppc/syslib/qspan_pci.c b/arch/ppc/syslib/qspan_pci.c index 57f4ed5..0970b5d 100644 --- a/arch/ppc/syslib/qspan_pci.c +++ b/arch/ppc/syslib/qspan_pci.c @@ -94,7 +94,7 @@ #define mk_config_type1(bus, dev, offset) \ mk_config_addr(bus, dev, offset) | 1; -static spinlock_t pcibios_lock = SPIN_LOCK_UNLOCKED; +static DEFINE_SPINLOCK(pcibios_lock); int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned char *val) |
