diff options
Diffstat (limited to 'arch/ppc/platforms')
46 files changed, 1073 insertions, 3534 deletions
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig index 805dd98..76f4476 100644 --- a/arch/ppc/platforms/4xx/Kconfig +++ b/arch/ppc/platforms/4xx/Kconfig @@ -16,11 +16,6 @@ choice depends on 40x default WALNUT -config ASH - bool "Ash" - help - This option enables support for the IBM NP405H evaluation board. - config BUBINGA bool "Bubinga" select WANT_EARLY_SERIAL @@ -37,11 +32,6 @@ config EP405 help This option enables support for the EP405/EP405PC boards. -config OAK - bool "Oak" - help - This option enables support for the IBM 403GCX evaluation board. - config REDWOOD_5 bool "Redwood-5" help @@ -152,13 +142,13 @@ config IBM440EP_ERR42 # All 405-based cores up until the 405GPR and 405EP have this errata. config IBM405_ERR77 bool - depends on 40x && !403GCX && !405GPR + depends on 40x && !403GCX && !405GPR && !405EP default y # All 40x-based cores, up until the 405GPR and 405EP have this errata. config IBM405_ERR51 bool - depends on 40x && !405GPR + depends on 40x && !405GPR && !405EP default y config BOOKE @@ -186,6 +176,7 @@ config BIOS_FIXUP depends on BUBINGA || EP405 || SYCAMORE || WALNUT default y +# OAK doesn't exist but wanted to keep this around for any future 403GCX boards config 403GCX bool depends OAK diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile index 844c3b5..1dd6d7f 100644 --- a/arch/ppc/platforms/4xx/Makefile +++ b/arch/ppc/platforms/4xx/Makefile @@ -1,14 +1,12 @@ # # Makefile for the PowerPC 4xx linux kernel. -obj-$(CONFIG_ASH) += ash.o obj-$(CONFIG_BAMBOO) += bamboo.o obj-$(CONFIG_CPCI405) += cpci405.o obj-$(CONFIG_EBONY) += ebony.o obj-$(CONFIG_EP405) += ep405.o obj-$(CONFIG_BUBINGA) += bubinga.o obj-$(CONFIG_LUAN) += luan.o -obj-$(CONFIG_OAK) += oak.o obj-$(CONFIG_OCOTEA) += ocotea.o obj-$(CONFIG_REDWOOD_5) += redwood5.o obj-$(CONFIG_REDWOOD_6) += redwood6.o diff --git a/arch/ppc/platforms/4xx/ash.c b/arch/ppc/platforms/4xx/ash.c deleted file mode 100644 index ce29117..0000000 --- a/arch/ppc/platforms/4xx/ash.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * arch/ppc/platforms/4xx/ash.c - * - * Support for the IBM NP405H ash eval board - * - * Author: Armin Kuster <akuster@mvista.com> - * - * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include <linux/config.h> -#include <linux/init.h> -#include <linux/pagemap.h> -#include <linux/pci.h> - -#include <asm/machdep.h> -#include <asm/pci-bridge.h> -#include <asm/io.h> -#include <asm/ocp.h> -#include <asm/ibm_ocp_pci.h> -#include <asm/todc.h> - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -void *ash_rtc_base; - -/* Some IRQs unique to Walnut. - * Used by the generic 405 PCI setup functions in ppc4xx_pci.c - */ -int __init -ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {24, 24, 24, 24}, /* IDSEL 1 - PCI slot 1 */ - {25, 25, 25, 25}, /* IDSEL 2 - PCI slot 2 */ - {26, 26, 26, 26}, /* IDSEL 3 - PCI slot 3 */ - {27, 27, 27, 27}, /* IDSEL 4 - PCI slot 4 */ - }; - - const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -void __init -ash_setup_arch(void) -{ - ppc4xx_setup_arch(); - - ibm_ocp_set_emac(0, 3); - -#ifdef CONFIG_DEBUG_BRINGUP - int i; - printk("\n"); - printk("machine\t: %s\n", PPC4xx_MACHINE_NAME); - printk("\n"); - printk("bi_s_version\t %s\n", bip->bi_s_version); - printk("bi_r_version\t %s\n", bip->bi_r_version); - printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize, - bip->bi_memsize / (1024 * 1000)); - for (i = 0; i < EMAC_NUMS; i++) { - printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", i, - bip->bi_enetaddr[i][0], bip->bi_enetaddr[i][1], - bip->bi_enetaddr[i][2], bip->bi_enetaddr[i][3], - bip->bi_enetaddr[i][4], bip->bi_enetaddr[i][5]); - } - printk("bi_pci_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0, - bip->bi_pci_enetaddr[0], bip->bi_pci_enetaddr[1], - bip->bi_pci_enetaddr[2], bip->bi_pci_enetaddr[3], - bip->bi_pci_enetaddr[4], bip->bi_pci_enetaddr[5]); - - printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n", - bip->bi_intfreq, bip->bi_intfreq / 1000000); - - printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n", - bip->bi_busfreq, bip->bi_busfreq / 1000000); - printk("bi_pci_busfreq\t 0x%8.8x\t pci bus clock:\t %dMHz\n", - bip->bi_pci_busfreq, bip->bi_pci_busfreq / 1000000); - - printk("\n"); -#endif - /* RTC step for ash */ - ash_rtc_base = (void *) ASH_RTC_VADDR; - TODC_INIT(TODC_TYPE_DS1743, ash_rtc_base, ash_rtc_base, ash_rtc_base, - 8); -} - -void __init -bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip) -{ - /* - * Expected PCI mapping: - * - * PLB addr PCI memory addr - * --------------------- --------------------- - * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff - * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff - * - * PLB addr PCI io addr - * --------------------- --------------------- - * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000 - * - * The following code is simplified by assuming that the bootrom - * has been well behaved in following this mapping. - */ - -#ifdef DEBUG - int i; - - printk("ioremap PCLIO_BASE = 0x%x\n", pcip); - printk("PCI bridge regs before fixup \n"); - for (i = 0; i <= 2; i++) { - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); - printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); - printk(" pmm%dpcila\t0x%x\n", i, - in_le32(&(pcip->pmm[i].pcila))); - printk(" pmm%dpciha\t0x%x\n", i, - in_le32(&(pcip->pmm[i].pciha))); - } - printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); - printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); - printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); - printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); - for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { - early_read_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - &bar_response); - DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n", - hose->first_busno, PCI_SLOT(hose->first_busno), - PCI_FUNC(hose->first_busno), bar, bar_response); - } - -#endif - if (ppc_md.progress) - ppc_md.progress("bios_fixup(): enter", 0x800); - - /* added for IBM boot rom version 1.15 bios bar changes -AK */ - - /* Disable region first */ - out_le32((void *) &(pcip->pmm[0].ma), 0x00000000); - /* PLB starting addr, PCI: 0x80000000 */ - out_le32((void *) &(pcip->pmm[0].la), 0x80000000); - /* PCI start addr, 0x80000000 */ - out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE); - /* 512MB range of PLB to PCI */ - out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000); - /* Enable no pre-fetch, enable region */ - out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff - - (PPC405_PCI_UPPER_MEM - - PPC405_PCI_MEM_BASE)) | 0x01)); - - /* Disable region one */ - out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); - out_le32((void *) &(pcip->pmm[1].la), 0x00000000); - out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000); - out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000); - out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); - - /* Disable region two */ - out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); - out_le32((void *) &(pcip->pmm[2].la), 0x00000000); - out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000); - out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000); - out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); - - /* Enable PTM1 and PTM2, mapped to PLB address 0. */ - - out_le32((void *) &(pcip->ptm1la), 0x00000000); - out_le32((void *) &(pcip->ptm1ms), 0x00000001); - out_le32((void *) &(pcip->ptm2la), 0x00000000); - out_le32((void *) &(pcip->ptm2ms), 0x00000001); - - /* Write zero to PTM1 BAR. */ - - early_write_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), - PCI_BASE_ADDRESS_1, - 0x00000000); - - /* Disable PTM2 (unused) */ - - out_le32((void *) &(pcip->ptm2la), 0x00000000); - out_le32((void *) &(pcip->ptm2ms), 0x00000000); - - /* end work arround */ - if (ppc_md.progress) - ppc_md.progress("bios_fixup(): done", 0x800); - -#ifdef DEBUG - printk("PCI bridge regs after fixup \n"); - for (i = 0; i <= 2; i++) { - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); - printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); - printk(" pmm%dpcila\t0x%x\n", i, - in_le32(&(pcip->pmm[i].pcila))); - printk(" pmm%dpciha\t0x%x\n", i, - in_le32(&(pcip->pmm[i].pciha))); - } - printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); - printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); - printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); - printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); - - for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { - early_read_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - &bar_response); - DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n", - hose->first_busno, PCI_SLOT(hose->first_busno), - PCI_FUNC(hose->first_busno), bar, bar_response); - } - - -#endif -} - -void __init -ash_map_io(void) -{ - ppc4xx_map_io(); - io_block_mapping(ASH_RTC_VADDR, ASH_RTC_PADDR, ASH_RTC_SIZE, _PAGE_IO); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - ppc4xx_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = ash_setup_arch; - ppc_md.setup_io_mappings = ash_map_io; - -#ifdef CONFIG_PPC_RTC - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; -#endif -} diff --git a/arch/ppc/platforms/4xx/ash.h b/arch/ppc/platforms/4xx/ash.h deleted file mode 100644 index 5f7448e..0000000 --- a/arch/ppc/platforms/4xx/ash.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * arch/ppc/platforms/4xx/ash.h - * - * Macros, definitions, and data structures specific to the IBM PowerPC - * Ash eval board. - * - * Author: Armin Kuster <akuster@mvista.com> - * - * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_ASH_H__ -#define __ASM_ASH_H__ -#include <platforms/4xx/ibmnp405h.h> - -#ifndef __ASSEMBLY__ -/* - * Data structure defining board information maintained by the boot - * ROM on IBM's "Ash" evaluation board. An effort has been made to - * keep the field names consistent with the 8xx 'bd_t' board info - * structures. - */ - -typedef struct board_info { - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[30]; /* Version of the IBM ROM */ - unsigned int bi_memsize; /* DRAM installed, in bytes */ - unsigned char bi_enetaddr[4][6]; /* Local Ethernet MAC address */ - unsigned char bi_pci_enetaddr[6]; - unsigned int bi_intfreq; /* Processor speed, in Hz */ - unsigned int bi_busfreq; /* PLB Bus speed, in Hz */ - unsigned int bi_pci_busfreq; /* PCI speed in Hz */ -} bd_t; - -/* Some 4xx parts use a different timebase frequency from the internal clock. -*/ -#define bi_tbfreq bi_intfreq - -/* Memory map for the IBM "Ash" NP405H evaluation board. - */ - -extern void *ash_rtc_base; -#define ASH_RTC_PADDR ((uint)0xf0000000) -#define ASH_RTC_VADDR ASH_RTC_PADDR -#define ASH_RTC_SIZE ((uint)8*1024) - - -/* Early initialization address mapping for block_io. - * Standard 405GP map. - */ -#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE) -#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR -#define PPC4xx_PCI_IO_SIZE ((uint)64*1024) -#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR) -#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR -#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024) -#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000) -#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR -#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024) -#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000) -#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR -#define PPC4xx_ONB_IO_SIZE ((uint)4*1024) - -#define NR_BOARD_IRQS 32 - -#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK -#define BASE_BAUD 201600 -#else -#define BASE_BAUD 691200 -#endif - -#define PPC4xx_MACHINE_NAME "IBM NP405H Ash" - -extern char pci_irq_table[][4]; - - -#endif /* !__ASSEMBLY__ */ -#endif /* __ASM_ASH_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/bamboo.c b/arch/ppc/platforms/4xx/bamboo.c index f116787..ac391d4 100644 --- a/arch/ppc/platforms/4xx/bamboo.c +++ b/arch/ppc/platforms/4xx/bamboo.c @@ -52,13 +52,6 @@ #include <syslib/gen550.h> #include <syslib/ibm440gx_common.h> -/* - * This is a horrible kludge, we eventually need to abstract this - * generic PHY stuff, so the standard phy mode defines can be - * easily used from arch code. - */ -#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h" - bd_t __res; static struct ibm44x_clocks clocks __initdata; @@ -123,33 +116,69 @@ bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) static void __init bamboo_set_emacdata(void) { - unsigned char * selection1_base; + u8 * base_addr; struct ocp_def *def; struct ocp_func_emac_data *emacdata; - u8 selection1_val; + u8 val; int mode; + u32 excluded = 0; - selection1_base = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16); - selection1_val = readb(selection1_base); - iounmap((void *) selection1_base); - if (BAMBOO_SEL_MII(selection1_val)) + base_addr = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16); + val = readb(base_addr); + iounmap((void *) base_addr); + if (BAMBOO_SEL_MII(val)) mode = PHY_MODE_MII; - else if (BAMBOO_SEL_RMII(selection1_val)) + else if (BAMBOO_SEL_RMII(val)) mode = PHY_MODE_RMII; else mode = PHY_MODE_SMII; - /* Set mac_addr and phy mode for each EMAC */ + /* + * SW2 on the Bamboo is used for ethernet configuration and is accessed + * via the CONFIG2 register in the FPGA. If the ANEG pin is set, + * overwrite the supported features with the settings in SW2. + * + * This is used as a workaround for the improperly biased RJ-45 sockets + * on the Rev. 0 Bamboo. By default only 10baseT is functional. + * Removing inductors L17 and L18 from the board allows 100baseT, but + * disables 10baseT. The Rev. 1 has no such limitations. + */ + + base_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 8); + val = readb(base_addr); + iounmap((void *) base_addr); + if (!BAMBOO_AUTONEGOTIATE(val)) { + excluded |= SUPPORTED_Autoneg; + if (BAMBOO_FORCE_100Mbps(val)) { + excluded |= SUPPORTED_10baseT_Full; + excluded |= SUPPORTED_10baseT_Half; + if (BAMBOO_FULL_DUPLEX_EN(val)) + excluded |= SUPPORTED_100baseT_Half; + else + excluded |= SUPPORTED_100baseT_Full; + } else { + excluded |= SUPPORTED_100baseT_Full; + excluded |= SUPPORTED_100baseT_Half; + if (BAMBOO_FULL_DUPLEX_EN(val)) + excluded |= SUPPORTED_10baseT_Half; + else + excluded |= SUPPORTED_10baseT_Full; + } + } + + /* Set mac_addr, phy mode and unsupported phy features for each EMAC */ def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0); emacdata = def->additions; memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); emacdata->phy_mode = mode; + emacdata->phy_feat_exc = excluded; def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1); emacdata = def->additions; memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6); emacdata->phy_mode = mode; + emacdata->phy_feat_exc = excluded; } static int diff --git a/arch/ppc/platforms/4xx/bamboo.h b/arch/ppc/platforms/4xx/bamboo.h index 63d714504..5c01928 100644 --- a/arch/ppc/platforms/4xx/bamboo.h +++ b/arch/ppc/platforms/4xx/bamboo.h @@ -88,7 +88,7 @@ #define STD_UART_OP(num) \ { 0, BASE_BAUD, 0, UART##num##_INT, \ (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: UART##num##_IO_BASE, \ + iomem_base: (void*)UART##num##_IO_BASE, \ io_type: SERIAL_IO_MEM}, #define SERIAL_PORT_DFNS \ diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c index 509e69a..0fd3442 100644 --- a/arch/ppc/platforms/4xx/ebony.c +++ b/arch/ppc/platforms/4xx/ebony.c @@ -55,13 +55,6 @@ #include <syslib/gen550.h> #include <syslib/ibm440gp_common.h> -/* - * This is a horrible kludge, we eventually need to abstract this - * generic PHY stuff, so the standard phy mode defines can be - * easily used from arch code. - */ -#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h" - bd_t __res; static struct ibm44x_clocks clocks __initdata; diff --git a/arch/ppc/platforms/4xx/ibm405ep.c b/arch/ppc/platforms/4xx/ibm405ep.c index 6d44567..093b28d 100644 --- a/arch/ppc/platforms/4xx/ibm405ep.c +++ b/arch/ppc/platforms/4xx/ibm405ep.c @@ -33,6 +33,7 @@ static struct ocp_func_mal_data ibm405ep_mal0_def = { .txde_irq = 13, /* TX Descriptor Error IRQ */ .rxde_irq = 14, /* RX Descriptor Error IRQ */ .serr_irq = 10, /* MAL System Error IRQ */ + .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ }; OCP_SYSFS_MAL_DATA() diff --git a/arch/ppc/platforms/4xx/ibm405gp.c b/arch/ppc/platforms/4xx/ibm405gp.c index dfd7ef3..e570046 100644 --- a/arch/ppc/platforms/4xx/ibm405gp.c +++ b/arch/ppc/platforms/4xx/ibm405gp.c @@ -46,6 +46,7 @@ static struct ocp_func_mal_data ibm405gp_mal0_def = { .txde_irq = 13, /* TX Descriptor Error IRQ */ .rxde_irq = 14, /* RX Descriptor Error IRQ */ .serr_irq = 10, /* MAL System Error IRQ */ + .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ }; OCP_SYSFS_MAL_DATA() diff --git a/arch/ppc/platforms/4xx/ibm405gpr.c b/arch/ppc/platforms/4xx/ibm405gpr.c index 01c8ccb..cd0d00d 100644 --- a/arch/ppc/platforms/4xx/ibm405gpr.c +++ b/arch/ppc/platforms/4xx/ibm405gpr.c @@ -42,6 +42,7 @@ static struct ocp_func_mal_data ibm405gpr_mal0_def = { .txde_irq = 13, /* TX Descriptor Error IRQ */ .rxde_irq = 14, /* RX Descriptor Error IRQ */ .serr_irq = 10, /* MAL System Error IRQ */ + .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ }; OCP_SYSFS_MAL_DATA() diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c index 284da01..4712de8 100644 --- a/arch/ppc/platforms/4xx/ibm440ep.c +++ b/arch/ppc/platforms/4xx/ibm440ep.c @@ -53,6 +53,7 @@ static struct ocp_func_mal_data ibm440ep_mal0_def = { .txde_irq = 33, /* TX Descriptor Error IRQ */ .rxde_irq = 34, /* RX Descriptor Error IRQ */ .serr_irq = 32, /* MAL System Error IRQ */ + .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ }; OCP_SYSFS_MAL_DATA() diff --git a/arch/ppc/platforms/4xx/ibm440gp.c b/arch/ppc/platforms/4xx/ibm440gp.c index 27615ef..d926245 100644 --- a/arch/ppc/platforms/4xx/ibm440gp.c +++ b/arch/ppc/platforms/4xx/ibm440gp.c @@ -56,6 +56,7 @@ static struct ocp_func_mal_data ibm440gp_mal0_def = { .txde_irq = 33, /* TX Descriptor Error IRQ */ .rxde_irq = 34, /* RX Descriptor Error IRQ */ .serr_irq = 32, /* MAL System Error IRQ */ + .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ }; OCP_SYSFS_MAL_DATA() diff --git a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c index 1f38f42..956f45e 100644 --- a/arch/ppc/platforms/4xx/ibm440gx.c +++ b/arch/ppc/platforms/4xx/ibm440gx.c @@ -84,6 +84,7 @@ static struct ocp_func_mal_data ibm440gx_mal0_def = { .txde_irq = 33, /* TX Descriptor Error IRQ */ .rxde_irq = 34, /* RX Descriptor Error IRQ */ .serr_irq = 32, /* MAL System Error IRQ */ + .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ }; OCP_SYSFS_MAL_DATA() diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c index fa3e003..feb17e4 100644 --- a/arch/ppc/platforms/4xx/ibm440sp.c +++ b/arch/ppc/platforms/4xx/ibm440sp.c @@ -43,6 +43,7 @@ static struct ocp_func_mal_data ibm440sp_mal0_def = { .txde_irq = 34, /* TX Descriptor Error IRQ */ .rxde_irq = 35, /* RX Descriptor Error IRQ */ .serr_irq = 33, /* MAL System Error IRQ */ + .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ }; OCP_SYSFS_MAL_DATA() diff --git a/arch/ppc/platforms/4xx/ibmnp405h.c b/arch/ppc/platforms/4xx/ibmnp405h.c index ecdc5be..a477a78 100644 --- a/arch/ppc/platforms/4xx/ibmnp405h.c +++ b/arch/ppc/platforms/4xx/ibmnp405h.c @@ -34,7 +34,7 @@ static struct ocp_func_emac_data ibmnp405h_emac1_def = { .zmii_mux = 1, /* ZMII input of this EMAC */ .mal_idx = 0, /* MAL device index */ .mal_rx_chan = 1, /* MAL rx channel number */ - .mal_tx_chan = 1, /* MAL tx channel number */ + .mal_tx_chan = 2, /* MAL tx channel number */ .wol_irq = 41, /* WOL interrupt number */ .mdio_idx = -1, /* No shared MDIO */ .tah_idx = -1, /* No TAH */ @@ -46,7 +46,7 @@ static struct ocp_func_emac_data ibmnp405h_emac2_def = { .zmii_mux = 2, /* ZMII input of this EMAC */ .mal_idx = 0, /* MAL device index */ .mal_rx_chan = 2, /* MAL rx channel number */ - .mal_tx_chan = 2, /* MAL tx channel number */ + .mal_tx_chan = 4, /* MAL tx channel number */ .wol_irq = 41, /* WOL interrupt number */ .mdio_idx = -1, /* No shared MDIO */ .tah_idx = -1, /* No TAH */ @@ -58,7 +58,7 @@ static struct ocp_func_emac_data ibmnp405h_emac3_def = { .zmii_mux = 3, /* ZMII input of this EMAC */ .mal_idx = 0, /* MAL device index */ .mal_rx_chan = 3, /* MAL rx channel number */ - .mal_tx_chan = 3, /* MAL tx channel number */ + .mal_tx_chan = 6, /* MAL tx channel number */ .wol_irq = 41, /* WOL interrupt number */ .mdio_idx = -1, /* No shared MDIO */ .tah_idx = -1, /* No TAH */ @@ -73,6 +73,7 @@ static struct ocp_func_mal_data ibmnp405h_mal0_def = { .txde_irq = 46, /* TX Descriptor Error IRQ */ .rxde_irq = 47, /* RX Descriptor Error IRQ */ .serr_irq = 45, /* MAL System Error IRQ */ + .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ }; OCP_SYSFS_MAL_DATA() diff --git a/arch/ppc/platforms/4xx/ibmstb4.c b/arch/ppc/platforms/4xx/ibmstb4.c index 874d16b..d90627b 100644 --- a/arch/ppc/platforms/4xx/ibmstb4.c +++ b/arch/ppc/platforms/4xx/ibmstb4.c @@ -11,6 +11,7 @@ #include <linux/init.h> #include <asm/ocp.h> +#include <asm/ppc4xx_pic.h> #include <platforms/4xx/ibmstb4.h> static struct ocp_func_iic_data ibmstb4_iic0_def = { @@ -72,12 +73,51 @@ struct ocp_def core_ocp[] __initdata = { .irq = IDE0_IRQ, .pm = OCP_CPM_NA, }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_USB, - .paddr = USB0_BASE, - .irq = USB0_IRQ, - .pm = OCP_CPM_NA, - }, { .vendor = OCP_VENDOR_INVALID, } }; + +/* Polarity and triggering settings for internal interrupt sources */ +struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { + { .polarity = 0x7fffff01, + .triggering = 0x00000000, + .ext_irq_mask = 0x0000007e, /* IRQ0 - IRQ5 */ + } +}; + +static struct resource ohci_usb_resources[] = { + [0] = { + .start = USB0_BASE, + .end = USB0_BASE + USB0_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = USB0_IRQ, + .end = USB0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 dma_mask = 0xffffffffULL; + +static struct platform_device ohci_usb_device = { + .name = "ppc-soc-ohci", + .id = 0, + .num_resources = ARRAY_SIZE(ohci_usb_resources), + .resource = ohci_usb_resources, + .dev = { + .dma_mask = &dma_mask, + .coherent_dma_mask = 0xffffffffULL, + } +}; + +static struct platform_device *ibmstb4_devs[] __initdata = { + &ohci_usb_device, +}; + +static int __init +ibmstb4_platform_add_devices(void) +{ + return platform_add_devices(ibmstb4_devs, ARRAY_SIZE(ibmstb4_devs)); +} +arch_initcall(ibmstb4_platform_add_devices); diff --git a/arch/ppc/platforms/4xx/ibmstb4.h b/arch/ppc/platforms/4xx/ibmstb4.h index bcb4b1e..9f21d4c 100644 --- a/arch/ppc/platforms/4xx/ibmstb4.h +++ b/arch/ppc/platforms/4xx/ibmstb4.h @@ -73,9 +73,9 @@ #define OPB0_BASE 0x40000000 #define GPIO0_BASE 0x40060000 +#define USB0_BASE 0x40010000 +#define USB0_SIZE 0xA0 #define USB0_IRQ 18 -#define USB0_BASE STB04xxx_MAP_IO_ADDR(0x40010000) -#define USB0_EXTENT 4096 #define IIC_NUMS 2 #define UART_NUMS 3 diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c index 95359f7..a38e6f9 100644 --- a/arch/ppc/platforms/4xx/luan.c +++ b/arch/ppc/platforms/4xx/luan.c @@ -53,13 +53,6 @@ #include <syslib/ibm440gx_common.h> #include <syslib/ibm440sp_common.h> -/* - * This is a horrible kludge, we eventually need to abstract this - * generic PHY stuff, so the standard phy mode defines can be - * easily used from arch code. - */ -#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h" - bd_t __res; static struct ibm44x_clocks clocks __initdata; diff --git a/arch/ppc/platforms/4xx/luan.h b/arch/ppc/platforms/4xx/luan.h index 09b444c..bbe7d07 100644 --- a/arch/ppc/platforms/4xx/luan.h +++ b/arch/ppc/platforms/4xx/luan.h @@ -55,7 +55,7 @@ #define STD_UART_OP(num) \ { 0, BASE_BAUD, 0, UART##num##_INT, \ (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: UART##num##_IO_BASE, \ + iomem_base: (void*)UART##num##_IO_BASE, \ io_type: SERIAL_IO_MEM}, #define SERIAL_PORT_DFNS \ diff --git a/arch/ppc/platforms/4xx/oak.c b/arch/ppc/platforms/4xx/oak.c deleted file mode 100644 index fa25ee1..0000000 --- a/arch/ppc/platforms/4xx/oak.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * - * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu> - * - * Module name: oak.c - * - * Description: - * Architecture- / platform-specific boot-time initialization code for - * the IBM PowerPC 403GCX "Oak" evaluation board. Adapted from original - * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek - * <dan@net4x.com>. - * - */ - -#include <linux/config.h> -#include <linux/init.h> -#include <linux/smp.h> -#include <linux/threads.h> -#include <linux/param.h> -#include <linux/string.h> -#include <linux/initrd.h> -#include <linux/irq.h> -#include <linux/seq_file.h> - -#include <asm/board.h> -#include <asm/machdep.h> -#include <asm/page.h> -#include <asm/bootinfo.h> -#include <asm/ppc4xx_pic.h> -#include <asm/time.h> - -#include "oak.h" - -/* Function Prototypes */ - -extern void abort(void); - -/* Global Variables */ - -unsigned char __res[sizeof(bd_t)]; - - -/* - * void __init oak_init() - * - * Description: - * This routine... - * - * Input(s): - * r3 - Optional pointer to a board information structure. - * r4 - Optional pointer to the physical starting address of the init RAM - * disk. - * r5 - Optional pointer to the physical ending address of the init RAM - * disk. - * r6 - Optional pointer to the physical starting address of any kernel - * command-line parameters. - * r7 - Optional pointer to the physical ending address of any kernel - * command-line parameters. - * - * Output(s): - * N/A - * - * Returns: - * N/A - * - */ -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - /* - * If we were passed in a board information, copy it into the - * residual data area. - */ - if (r3) { - memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t)); - } - -#if defined(CONFIG_BLK_DEV_INITRD) - /* - * If the init RAM disk has been configured in, and there's a valid - * starting address for it, set it up. - */ - if (r4) { - initrd_start = r4 + KERNELBASE; - initrd_end = r5 + KERNELBASE; - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - /* Copy the kernel command line arguments to a safe place. */ - - if (r6) { - *(char *)(r7 + KERNELBASE) = 0; - strcpy(cmd_line, (char *)(r6 + KERNELBASE)); - } - - /* Initialize machine-dependency vectors */ - - ppc_md.setup_arch = oak_setup_arch; - ppc_md.show_percpuinfo = oak_show_percpuinfo; - ppc_md.irq_canonicalize = NULL; - ppc_md.init_IRQ = ppc4xx_pic_init; - ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ - ppc_md.init = NULL; - - ppc_md.restart = oak_restart; - ppc_md.power_off = oak_power_off; - ppc_md.halt = oak_halt; - - ppc_md.time_init = oak_time_init; - ppc_md.set_rtc_time = oak_set_rtc_time; - ppc_md.get_rtc_time = oak_get_rtc_time; - ppc_md.calibrate_decr = oak_calibrate_decr; -} - -/* - * Document me. - */ -void __init -oak_setup_arch(void) -{ - /* XXX - Implement me */ -} - -/* - * int oak_show_percpuinfo() - * - * Description: - * This routine pretty-prints the platform's internal CPU and bus clock - * frequencies into the buffer for usage in /proc/cpuinfo. - * - * Input(s): - * *buffer - Buffer into which CPU and bus clock frequencies are to be - * printed. - * - * Output(s): - * *buffer - Buffer with the CPU and bus clock frequencies. - * - * Returns: - * The number of bytes copied into 'buffer' if OK, otherwise zero or less - * on error. - */ -int -oak_show_percpuinfo(struct seq_file *m, int i) -{ - bd_t *bp = (bd_t *)__res; - - seq_printf(m, "clock\t\t: %dMHz\n" - "bus clock\t\t: %dMHz\n", - bp->bi_intfreq / 1000000, - bp->bi_busfreq / 1000000); - - return 0; -} - -/* - * Document me. - */ -void -oak_restart(char *cmd) -{ - abort(); -} - -/* - * Document me. - */ -void -oak_power_off(void) -{ - oak_restart(NULL); -} - -/* - * Document me. - */ -void -oak_halt(void) -{ - oak_restart(NULL); -} - -/* - * Document me. - */ -long __init -oak_time_init(void) -{ - /* XXX - Implement me */ - return 0; -} - -/* - * Document me. - */ -int __init -oak_set_rtc_time(unsigned long time) -{ - /* XXX - Implement me */ - - return (0); -} - -/* - * Document me. - */ -unsigned long __init -oak_get_rtc_time(void) -{ - /* XXX - Implement me */ - - return (0); -} - -/* - * void __init oak_calibrate_decr() - * - * Description: - * This routine retrieves the internal processor frequency from the board - * information structure, sets up the kernel timer decrementer based on - * that value, enables the 403 programmable interval timer (PIT) and sets - * it up for auto-reload. - * - * Input(s): - * N/A - * - * Output(s): - * N/A - * - * Returns: - * N/A - * - */ -void __init -oak_calibrate_decr(void) -{ - unsigned int freq; - bd_t *bip = (bd_t *)__res; - - freq = bip->bi_intfreq; - - decrementer_count = freq / HZ; - count_period_num = 1; - count_period_den = freq; - - /* Enable the PIT and set auto-reload of its value */ - - mtspr(SPRN_TCR, TCR_PIE | TCR_ARE); - - /* Clear any pending timer interrupts */ - - mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_PIS | TSR_FIS); -} diff --git a/arch/ppc/platforms/4xx/oak.h b/arch/ppc/platforms/4xx/oak.h deleted file mode 100644 index 1b86a4c..0000000 --- a/arch/ppc/platforms/4xx/oak.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * - * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> - * - * Module name: oak.h - * - * Description: - * Macros, definitions, and data structures specific to the IBM PowerPC - * 403G{A,B,C,CX} "Oak" evaluation board. Anything specific to the pro- - * cessor itself is defined elsewhere. - * - */ - -#ifdef __KERNEL__ -#ifndef __ASM_OAK_H__ -#define __ASM_OAK_H__ - -/* We have an IBM 403G{A,B,C,CX} core */ -#include <asm/ibm403.h> - -#define _IO_BASE 0 -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 - -/* Memory map for the "Oak" evaluation board */ - -#define PPC403SPU_IO_BASE 0x40000000 /* 403 On-chip serial port */ -#define PPC403SPU_IO_SIZE 0x00000008 -#define OAKSERIAL_IO_BASE 0x7E000000 /* NS16550DV serial port */ -#define OAKSERIAL_IO_SIZE 0x00000008 -#define OAKNET_IO_BASE 0xF4000000 /* NS83902AV Ethernet */ -#define OAKNET_IO_SIZE 0x00000040 -#define OAKPROM_IO_BASE 0xFFFE0000 /* AMD 29F010 Flash ROM */ -#define OAKPROM_IO_SIZE 0x00020000 - - -/* Interrupt assignments fixed by the hardware implementation */ - -/* This is annoying kbuild-2.4 problem. -- Tom */ - -#define PPC403SPU_RX_INT 4 /* AIC_INT4 */ -#define PPC403SPU_TX_INT 5 /* AIC_INT5 */ -#define OAKNET_INT 27 /* AIC_INT27 */ -#define OAKSERIAL_INT 28 /* AIC_INT28 */ - -#ifndef __ASSEMBLY__ -/* - * Data structure defining board information maintained by the boot - * ROM on IBM's "Oak" evaluation board. An effort has been made to - * keep the field names consistent with the 8xx 'bd_t' board info - * structures. - */ - -typedef struct board_info { - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[30]; /* Version of the IBM ROM */ - unsigned int bi_memsize; /* DRAM installed, in bytes */ - unsigned char bi_enetaddr[6]; /* Ethernet MAC address */ - unsigned int bi_intfreq; /* Processor speed, in Hz */ - unsigned int bi_busfreq; /* Bus speed, in Hz */ -} bd_t; - -#ifdef __cplusplus -extern "C" { -#endif - -extern void oak_init(unsigned long r3, - unsigned long ird_start, - unsigned long ird_end, - unsigned long cline_start, - unsigned long cline_end); -extern void oak_setup_arch(void); -extern int oak_setup_residual(char *buffer); -extern void oak_init_IRQ(void); -extern int oak_get_irq(struct pt_regs *regs); -extern void oak_restart(char *cmd); -extern void oak_power_off(void); -extern void oak_halt(void); -extern void oak_time_init(void); -extern int oak_set_rtc_time(unsigned long now); -extern unsigned long oak_get_rtc_time(void); -extern void oak_calibrate_decr(void); - -#ifdef __cplusplus -} -#endif - -/* Some 4xx parts use a different timebase frequency from the internal clock. -*/ -#define bi_tbfreq bi_intfreq - -#define PPC4xx_MACHINE_NAME "IBM Oak" - -#endif /* !__ASSEMBLY__ */ -#endif /* __ASM_OAK_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/oak_setup.h b/arch/ppc/platforms/4xx/oak_setup.h deleted file mode 100644 index 8648bd0..0000000 --- a/arch/ppc/platforms/4xx/oak_setup.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * - * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu> - * - * Module name: oak_setup.h - * - * Description: - * Architecture- / platform-specific boot-time initialization code for - * the IBM PowerPC 403GCX "Oak" evaluation board. Adapted from original - * code by Gary Thomas, Cort Dougan <cort@cs.nmt.edu>, and Dan Malek - * <dan@netx4.com>. - * - */ - -#ifndef __OAK_SETUP_H__ -#define __OAK_SETUP_H__ - -#include <asm/ptrace.h> -#include <asm/board.h> - - -#ifdef __cplusplus -extern "C" { -#endif - -extern unsigned char __res[sizeof(bd_t)]; - -extern void oak_init(unsigned long r3, - unsigned long ird_start, - unsigned long ird_end, - unsigned long cline_start, - unsigned long cline_end); -extern void oak_setup_arch(void); -extern int oak_setup_residual(char *buffer); -extern void oak_init_IRQ(void); -extern int oak_get_irq(struct pt_regs *regs); -extern void oak_restart(char *cmd); -extern void oak_power_off(void); -extern void oak_halt(void); -extern void oak_time_init(void); -extern int oak_set_rtc_time(unsigned long now); -extern unsigned long oak_get_rtc_time(void); -extern void oak_calibrate_decr(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* __OAK_SETUP_H__ */ diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c index 8fc34a3..80028df 100644 --- a/arch/ppc/platforms/4xx/ocotea.c +++ b/arch/ppc/platforms/4xx/ocotea.c @@ -53,13 +53,6 @@ #include <syslib/gen550.h> #include <syslib/ibm440gx_common.h> -/* - * This is a horrible kludge, we eventually need to abstract this - * generic PHY stuff, so the standard phy mode defines can be - * easily used from arch code. - */ -#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h" - bd_t __res; static struct ibm44x_clocks clocks __initdata; diff --git a/arch/ppc/platforms/4xx/redwood5.c b/arch/ppc/platforms/4xx/redwood5.c index 2f5e410..bee8b4a 100644 --- a/arch/ppc/platforms/4xx/redwood5.c +++ b/arch/ppc/platforms/4xx/redwood5.c @@ -18,6 +18,19 @@ #include <linux/ioport.h> #include <asm/io.h> #include <asm/machdep.h> +#include <asm/ppc4xx_pic.h> + +/* + * Define external IRQ senses and polarities. + */ +unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = { + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */ +}; static struct resource smc91x_resources[] = { [0] = { diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.c b/arch/ppc/platforms/83xx/mpc834x_sys.c index ddd04d4..b38a851 100644 --- a/arch/ppc/platforms/83xx/mpc834x_sys.c +++ b/arch/ppc/platforms/83xx/mpc834x_sys.c @@ -62,9 +62,29 @@ extern unsigned long total_memory; /* in mm/init */ unsigned char __res[sizeof (bd_t)]; #ifdef CONFIG_PCI -#error "PCI is not supported" -/* NEED mpc83xx_map_irq & mpc83xx_exclude_device - see platforms/85xx/mpc85xx_ads_common.c */ +int +mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) +{ + static char pci_irq_table[][4] = + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + { + {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x11 */ + {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x12 */ + {PIRQD, PIRQA, PIRQB, PIRQC} /* idsel 0x13 */ + }; + + const long min_idsel = 0x11, max_idsel = 0x13, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; +} + +int +mpc83xx_exclude_device(u_char bus, u_char devfn) +{ + return PCIBIOS_SUCCESSFUL; +} #endif /* CONFIG_PCI */ /* ************************************************************************ @@ -88,7 +108,7 @@ mpc834x_sys_setup_arch(void) #ifdef CONFIG_PCI /* setup PCI host bridges */ - mpc83xx_sys_setup_hose(); + mpc83xx_setup_hose(); #endif mpc83xx_early_serial_map(); @@ -175,10 +195,17 @@ mpc834x_sys_init_IRQ(void) IRQ_SENSE_LEVEL, /* EXT 1 */ IRQ_SENSE_LEVEL, /* EXT 2 */ 0, /* EXT 3 */ +#ifdef CONFIG_PCI + IRQ_SENSE_LEVEL, /* EXT 4 */ + IRQ_SENSE_LEVEL, /* EXT 5 */ + IRQ_SENSE_LEVEL, /* EXT 6 */ + IRQ_SENSE_LEVEL, /* EXT 7 */ +#else 0, /* EXT 4 */ 0, /* EXT 5 */ 0, /* EXT 6 */ 0, /* EXT 7 */ +#endif }; ipic_init(binfo->bi_immr_base + 0x00700, 0, MPC83xx_IPIC_IRQ_OFFSET, senses, 8); diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.h b/arch/ppc/platforms/83xx/mpc834x_sys.h index a2f6e49..1584cd7 100644 --- a/arch/ppc/platforms/83xx/mpc834x_sys.h +++ b/arch/ppc/platforms/83xx/mpc834x_sys.h @@ -26,7 +26,7 @@ #define VIRT_IMMRBAR ((uint)0xfe000000) #define BCSR_PHYS_ADDR ((uint)0xf8000000) -#define BCSR_SIZE ((uint)(32 * 1024)) +#define BCSR_SIZE ((uint)(128 * 1024)) #define BCSR_MISC_REG2_OFF 0x07 #define BCSR_MISC_REG2_PORESET 0x01 @@ -34,23 +34,25 @@ #define BCSR_MISC_REG3_OFF 0x08 #define BCSR_MISC_REG3_CNFLOCK 0x80 -#ifdef CONFIG_PCI -/* PCI interrupt controller */ -#define PIRQA MPC83xx_IRQ_IRQ4 -#define PIRQB MPC83xx_IRQ_IRQ5 -#define PIRQC MPC83xx_IRQ_IRQ6 -#define PIRQD MPC83xx_IRQ_IRQ7 - -#define MPC834x_SYS_PCI1_LOWER_IO 0x00000000 -#define MPC834x_SYS_PCI1_UPPER_IO 0x00ffffff - -#define MPC834x_SYS_PCI1_LOWER_MEM 0x80000000 -#define MPC834x_SYS_PCI1_UPPER_MEM 0x9fffffff - -#define MPC834x_SYS_PCI1_IO_BASE 0xe2000000 -#define MPC834x_SYS_PCI1_MEM_OFFSET 0x00000000 - -#define MPC834x_SYS_PCI1_IO_SIZE 0x01000000 -#endif /* CONFIG_PCI */ +#define PIRQA MPC83xx_IRQ_EXT4 +#define PIRQB MPC83xx_IRQ_EXT5 +#define PIRQC MPC83xx_IRQ_EXT6 +#define PIRQD MPC83xx_IRQ_EXT7 + +#define MPC83xx_PCI1_LOWER_IO 0x00000000 +#define MPC83xx_PCI1_UPPER_IO 0x00ffffff +#define MPC83xx_PCI1_LOWER_MEM 0x80000000 +#define MPC83xx_PCI1_UPPER_MEM 0x9fffffff +#define MPC83xx_PCI1_IO_BASE 0xe2000000 +#define MPC83xx_PCI1_MEM_OFFSET 0x00000000 +#define MPC83xx_PCI1_IO_SIZE 0x01000000 + +#define MPC83xx_PCI2_LOWER_IO 0x00000000 +#define MPC83xx_PCI2_UPPER_IO 0x00ffffff +#define MPC83xx_PCI2_LOWER_MEM 0xa0000000 +#define MPC83xx_PCI2_UPPER_MEM 0xbfffffff +#define MPC83xx_PCI2_IO_BASE 0xe3000000 +#define MPC83xx_PCI2_MEM_OFFSET 0x00000000 +#define MPC83xx_PCI2_IO_SIZE 0x01000000 #endif /* __MACH_MPC83XX_SYS_H__ */ diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile index 5488a05..ff7452e 100644 --- a/arch/ppc/platforms/Makefile +++ b/arch/ppc/platforms/Makefile @@ -21,22 +21,17 @@ obj-$(CONFIG_CPU_FREQ_PMAC) += pmac_cpufreq.o endif obj-$(CONFIG_PMAC_BACKLIGHT) += pmac_backlight.o obj-$(CONFIG_PREP_RESIDUAL) += residual.o -obj-$(CONFIG_ADIR) += adir_setup.o adir_pic.o adir_pci.o obj-$(CONFIG_PQ2ADS) += pq2ads.o obj-$(CONFIG_TQM8260) += tqm8260_setup.o obj-$(CONFIG_CPCI690) += cpci690.o obj-$(CONFIG_EV64260) += ev64260.o obj-$(CONFIG_CHESTNUT) += chestnut.o obj-$(CONFIG_GEMINI) += gemini_pci.o gemini_setup.o gemini_prom.o -obj-$(CONFIG_K2) += k2.o obj-$(CONFIG_LOPEC) += lopec.o obj-$(CONFIG_KATANA) += katana.o obj-$(CONFIG_HDPU) += hdpu.o -obj-$(CONFIG_MCPN765) += mcpn765.o -obj-$(CONFIG_MENF1) += menf1_setup.o menf1_pci.o obj-$(CONFIG_MVME5100) += mvme5100.o obj-$(CONFIG_PAL4) += pal4_setup.o pal4_pci.o -obj-$(CONFIG_PCORE) += pcore.o obj-$(CONFIG_POWERPMC250) += powerpmc250.o obj-$(CONFIG_PPLUS) += pplus.o obj-$(CONFIG_PRPMC750) += prpmc750.o @@ -46,6 +41,7 @@ obj-$(CONFIG_SANDPOINT) += sandpoint.o obj-$(CONFIG_SBC82xx) += sbc82xx.o obj-$(CONFIG_SPRUCE) += spruce.o obj-$(CONFIG_LITE5200) += lite5200.o +obj-$(CONFIG_EV64360) += ev64360.o ifeq ($(CONFIG_SMP),y) obj-$(CONFIG_PPC_PMAC) += pmac_smp.o diff --git a/arch/ppc/platforms/adir.h b/arch/ppc/platforms/adir.h deleted file mode 100644 index 13a748b..0000000 --- a/arch/ppc/platforms/adir.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * arch/ppc/platforms/adir.h - * - * Definitions for SBS Adirondack board support - * - * By Michael Sokolov <msokolov@ivan.Harhan.ORG> - */ - -#ifndef __PPC_PLATFORMS_ADIR_H -#define __PPC_PLATFORMS_ADIR_H - -/* - * SBS Adirondack definitions - */ - -/* PPC physical address space layout. We use the one set up by the firmware. */ -#define ADIR_PCI32_MEM_BASE 0x80000000 -#define ADIR_PCI32_MEM_SIZE 0x20000000 -#define ADIR_PCI64_MEM_BASE 0xA0000000 -#define ADIR_PCI64_MEM_SIZE 0x20000000 -#define ADIR_PCI32_IO_BASE 0xC0000000 -#define ADIR_PCI32_IO_SIZE 0x10000000 -#define ADIR_PCI64_IO_BASE 0xD0000000 -#define ADIR_PCI64_IO_SIZE 0x10000000 -#define ADIR_PCI64_PHB 0xFF400000 -#define ADIR_PCI32_PHB 0xFF500000 - -#define ADIR_PCI64_CONFIG_ADDR (ADIR_PCI64_PHB + 0x000f8000) -#define ADIR_PCI64_CONFIG_DATA (ADIR_PCI64_PHB + 0x000f8010) - -#define ADIR_PCI32_CONFIG_ADDR (ADIR_PCI32_PHB + 0x000f8000) -#define ADIR_PCI32_CONFIG_DATA (ADIR_PCI32_PHB + 0x000f8010) - -/* System memory as seen from PCI */ -#define ADIR_PCI_SYS_MEM_BASE 0x80000000 - -/* Static virtual mapping of PCI I/O */ -#define ADIR_PCI32_VIRT_IO_BASE 0xFE000000 -#define ADIR_PCI32_VIRT_IO_SIZE 0x01000000 -#define ADIR_PCI64_VIRT_IO_BASE 0xFF000000 -#define ADIR_PCI64_VIRT_IO_SIZE 0x01000000 - -/* Registers */ -#define ADIR_NVRAM_RTC_ADDR 0x74 -#define ADIR_NVRAM_RTC_DATA 0x75 - -#define ADIR_BOARD_ID_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF0) -#define ADIR_CPLD1REV_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF1) -#define ADIR_CPLD2REV_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF2) -#define ADIR_FLASHCTL_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF3) -#define ADIR_CPC710_STAT_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF4) -#define ADIR_CLOCK_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF5) -#define ADIR_GPIO_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF8) -#define ADIR_MISC_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF9) -#define ADIR_LED_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFFA) - -#define ADIR_CLOCK_REG_PD 0x10 -#define ADIR_CLOCK_REG_SPREAD 0x08 -#define ADIR_CLOCK_REG_SEL133 0x04 -#define ADIR_CLOCK_REG_SEL1 0x02 -#define ADIR_CLOCK_REG_SEL0 0x01 - -#define ADIR_PROCA_INT_MASK (ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF0) -#define ADIR_PROCB_INT_MASK (ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF2) -#define ADIR_PROCA_INT_STAT (ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF4) -#define ADIR_PROCB_INT_STAT (ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF6) - -/* Linux IRQ numbers */ -#define ADIR_IRQ_NONE -1 -#define ADIR_IRQ_SERIAL2 3 -#define ADIR_IRQ_SERIAL1 4 -#define ADIR_IRQ_FDC 6 -#define ADIR_IRQ_PARALLEL 7 -#define ADIR_IRQ_VIA_AUDIO 10 -#define ADIR_IRQ_VIA_USB 11 -#define ADIR_IRQ_IDE0 14 -#define ADIR_IRQ_IDE1 15 -#define ADIR_IRQ_PCI0_INTA 16 -#define ADIR_IRQ_PCI0_INTB 17 -#define ADIR_IRQ_PCI0_INTC 18 -#define ADIR_IRQ_PCI0_INTD 19 -#define ADIR_IRQ_PCI1_INTA 20 -#define ADIR_IRQ_PCI1_INTB 21 -#define ADIR_IRQ_PCI1_INTC 22 -#define ADIR_IRQ_PCI1_INTD 23 -#define ADIR_IRQ_MBSCSI 24 /* motherboard SCSI */ -#define ADIR_IRQ_MBETH1 25 /* motherboard Ethernet 1 */ -#define ADIR_IRQ_MBETH0 26 /* motherboard Ethernet 0 */ -#define ADIR_IRQ_CPC710_INT1 27 -#define ADIR_IRQ_CPC710_INT2 28 -#define ADIR_IRQ_VT82C686_NMI 29 -#define ADIR_IRQ_VT82C686_INTR 30 -#define ADIR_IRQ_INTERPROC 31 - -#endif /* __PPC_PLATFORMS_ADIR_H */ diff --git a/arch/ppc/platforms/adir_pci.c b/arch/ppc/platforms/adir_pci.c deleted file mode 100644 index f94ac53..0000000 --- a/arch/ppc/platforms/adir_pci.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * arch/ppc/platforms/adir_pci.c - * - * PCI support for SBS Adirondack - * - * By Michael Sokolov <msokolov@ivan.Harhan.ORG> - * based on the K2 version by Matt Porter <mporter@mvista.com> - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/slab.h> - -#include <asm/byteorder.h> -#include <asm/io.h> -#include <asm/uaccess.h> -#include <asm/machdep.h> -#include <asm/pci-bridge.h> - -#include <syslib/cpc710.h> -#include "adir.h" - -#undef DEBUG -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif /* DEBUG */ - -static inline int __init -adir_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ -#define PCIIRQ(a,b,c,d) {ADIR_IRQ_##a,ADIR_IRQ_##b,ADIR_IRQ_##c,ADIR_IRQ_##d}, - struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); - /* - * The three PCI devices on the motherboard have dedicated lines to the - * CPLD interrupt controller, bypassing the standard PCI INTA-D and the - * PC interrupt controller. All other PCI devices (slots) have usual - * staggered INTA-D lines, resulting in 8 lines total (PCI0 INTA-D and - * PCI1 INTA-D). All 8 go to the CPLD interrupt controller. PCI0 INTA-D - * also go to the south bridge, so we have the option of taking them - * via the CPLD interrupt controller or via the south bridge 8259 - * 8258 thingy. PCI1 INTA-D can only be taken via the CPLD interrupt - * controller. We take all PCI interrupts via the CPLD interrupt - * controller as recommended by SBS. - * - * We also have some monkey business with the PCI devices within the - * VT82C686B south bridge itself. This chip actually has 7 functions on - * its IDSEL. Function 0 is the actual south bridge, function 1 is IDE, - * and function 4 is some special stuff. The other 4 functions are just - * regular PCI devices bundled in the chip. 2 and 3 are USB UHCIs and 5 - * and 6 are audio (not supported on the Adirondack). - * - * This is where the monkey business begins. PCI devices are supposed - * to signal normal PCI interrupts. But the 4 functions in question are - * located in the south bridge chip, which is designed with the - * assumption that it will be fielding PCI INTA-D interrupts rather - * than generating them. Here's what it does. Each of the functions in - * question routes its interrupt to one of the IRQs on the 8259 thingy. - * Which one? It looks at the Interrupt Line register in the PCI config - * space, even though the PCI spec says it's for BIOS/OS interaction - * only. - * - * How do we deal with this? We take these interrupts via 8259 IRQs as - * we have to. We return the desired IRQ numbers from this routine when - * called for the functions in question. The PCI scan code will then - * stick our return value into the Interrupt Line register in the PCI - * config space, and the interrupt will actually go there. We identify - * these functions within the south bridge IDSEL by their interrupt pin - * numbers, as the VT82C686B has 04 in the Interrupt Pin register for - * USB and 03 for audio. - */ - if (!hose->index) { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - /* south bridge */ PCIIRQ(IDE0, NONE, VIA_AUDIO, VIA_USB) - /* Ethernet 0 */ PCIIRQ(MBETH0, MBETH0, MBETH0, MBETH0) - /* PCI0 slot 1 */ PCIIRQ(PCI0_INTB, PCI0_INTC, PCI0_INTD, PCI0_INTA) - /* PCI0 slot 2 */ PCIIRQ(PCI0_INTC, PCI0_INTD, PCI0_INTA, PCI0_INTB) - /* PCI0 slot 3 */ PCIIRQ(PCI0_INTD, PCI0_INTA, PCI0_INTB, PCI0_INTC) - }; - const long min_idsel = 3, max_idsel = 7, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } else { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - /* Ethernet 1 */ PCIIRQ(MBETH1, MBETH1, MBETH1, MBETH1) - /* SCSI */ PCIIRQ(MBSCSI, MBSCSI, MBSCSI, MBSCSI) - /* PCI1 slot 1 */ PCIIRQ(PCI1_INTB, PCI1_INTC, PCI1_INTD, PCI1_INTA) - /* PCI1 slot 2 */ PCIIRQ(PCI1_INTC, PCI1_INTD, PCI1_INTA, PCI1_INTB) - /* PCI1 slot 3 */ PCIIRQ(PCI1_INTD, PCI1_INTA, PCI1_INTB, PCI1_INTC) - }; - const long min_idsel = 3, max_idsel = 7, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } -#undef PCIIRQ -} - -static void -adir_pcibios_fixup_resources(struct pci_dev *dev) -{ - int i; - - if ((dev->vendor == PCI_VENDOR_ID_IBM) && - (dev->device == PCI_DEVICE_ID_IBM_CPC710_PCI64)) - { - DBG("Fixup CPC710 resources\n"); - for (i=0; i<DEVICE_COUNT_RESOURCE; i++) - { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - } - } -} - -/* - * CPC710 DD3 has an errata causing it to hang the system if a type 0 config - * cycle is attempted on its PCI32 interface with a device number > 21. - * CPC710's PCI bridges map device numbers 1 through 21 to AD11 through AD31. - * Per the PCI spec it MUST accept all other device numbers and do nothing, and - * software MUST scan all device numbers without assuming how IDSELs are - * mapped. However, as the CPC710 DD3's errata causes such correct scanning - * procedure to hang the system, we have no choice but to introduce this hack - * of knowingly avoiding device numbers > 21 on PCI0, - */ -static int -adir_exclude_device(u_char bus, u_char devfn) -{ - if ((bus == 0) && (PCI_SLOT(devfn) > 21)) - return PCIBIOS_DEVICE_NOT_FOUND; - else - return PCIBIOS_SUCCESSFUL; -} - -void adir_find_bridges(void) -{ - struct pci_controller *hose_a, *hose_b; - - /* Setup PCI32 hose */ - hose_a = pcibios_alloc_controller(); - if (!hose_a) - return; - - hose_a->first_busno = 0; - hose_a->last_busno = 0xff; - hose_a->pci_mem_offset = ADIR_PCI32_MEM_BASE; - hose_a->io_space.start = 0; - hose_a->io_space.end = ADIR_PCI32_VIRT_IO_SIZE - 1; - hose_a->mem_space.start = 0; - hose_a->mem_space.end = ADIR_PCI32_MEM_SIZE - 1; - hose_a->io_resource.start = 0; - hose_a->io_resource.end = ADIR_PCI32_VIRT_IO_SIZE - 1; - hose_a->io_resource.flags = IORESOURCE_IO; - hose_a->mem_resources[0].start = ADIR_PCI32_MEM_BASE; - hose_a->mem_resources[0].end = ADIR_PCI32_MEM_BASE + - ADIR_PCI32_MEM_SIZE - 1; - hose_a->mem_resources[0].flags = IORESOURCE_MEM; - hose_a->io_base_phys = ADIR_PCI32_IO_BASE; - hose_a->io_base_virt = (void *) ADIR_PCI32_VIRT_IO_BASE; - - ppc_md.pci_exclude_device = adir_exclude_device; - setup_indirect_pci(hose_a, ADIR_PCI32_CONFIG_ADDR, - ADIR_PCI32_CONFIG_DATA); - - /* Initialize PCI32 bus registers */ - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(0, 0), - CPC710_BUS_NUMBER, - hose_a->first_busno); - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(0, 0), - CPC710_SUB_BUS_NUMBER, - hose_a->last_busno); - - hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno); - - /* Write out correct max subordinate bus number for hose A */ - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(0, 0), - CPC710_SUB_BUS_NUMBER, - hose_a->last_busno); - - /* Setup PCI64 hose */ - hose_b = pcibios_alloc_controller(); - if (!hose_b) - return; - - hose_b->first_busno = hose_a->last_busno + 1; - hose_b->last_busno = 0xff; - hose_b->pci_mem_offset = ADIR_PCI64_MEM_BASE; - hose_b->io_space.start = 0; - hose_b->io_space.end = ADIR_PCI64_VIRT_IO_SIZE - 1; - hose_b->mem_space.start = 0; - hose_b->mem_space.end = ADIR_PCI64_MEM_SIZE - 1; - hose_b->io_resource.start = 0; - hose_b->io_resource.end = ADIR_PCI64_VIRT_IO_SIZE - 1; - hose_b->io_resource.flags = IORESOURCE_IO; - hose_b->mem_resources[0].start = ADIR_PCI64_MEM_BASE; - hose_b->mem_resources[0].end = ADIR_PCI64_MEM_BASE + - ADIR_PCI64_MEM_SIZE - 1; - hose_b->mem_resources[0].flags = IORESOURCE_MEM; - hose_b->io_base_phys = ADIR_PCI64_IO_BASE; - hose_b->io_base_virt = (void *) ADIR_PCI64_VIRT_IO_BASE; - - setup_indirect_pci(hose_b, ADIR_PCI64_CONFIG_ADDR, - ADIR_PCI64_CONFIG_DATA); - - /* Initialize PCI64 bus registers */ - early_write_config_byte(hose_b, - 0, - PCI_DEVFN(0, 0), - CPC710_SUB_BUS_NUMBER, - 0xff); - - early_write_config_byte(hose_b, - 0, - PCI_DEVFN(0, 0), - CPC710_BUS_NUMBER, - hose_b->first_busno); - - hose_b->last_busno = pciauto_bus_scan(hose_b, - hose_b->first_busno); - - /* Write out correct max subordinate bus number for hose B */ - early_write_config_byte(hose_b, - hose_b->first_busno, - PCI_DEVFN(0, 0), - CPC710_SUB_BUS_NUMBER, - hose_b->last_busno); - - ppc_md.pcibios_fixup = NULL; - ppc_md.pcibios_fixup_resources = adir_pcibios_fixup_resources; - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = adir_map_irq; -} diff --git a/arch/ppc/platforms/adir_pic.c b/arch/ppc/platforms/adir_pic.c deleted file mode 100644 index 9947cba..0000000 --- a/arch/ppc/platforms/adir_pic.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * arch/ppc/platforms/adir_pic.c - * - * Interrupt controller support for SBS Adirondack - * - * By Michael Sokolov <msokolov@ivan.Harhan.ORG> - * based on the K2 and SCM versions by Matt Porter <mporter@mvista.com> - */ - -#include <linux/stddef.h> -#include <linux/init.h> -#include <linux/sched.h> -#include <linux/pci.h> -#include <linux/interrupt.h> - -#include <asm/io.h> -#include <asm/i8259.h> -#include "adir.h" - -static void adir_onboard_pic_enable(unsigned int irq); -static void adir_onboard_pic_disable(unsigned int irq); - -__init static void -adir_onboard_pic_init(void) -{ - volatile u_short *maskreg = (volatile u_short *) ADIR_PROCA_INT_MASK; - - /* Disable all Adirondack onboard interrupts */ - out_be16(maskreg, 0xFFFF); -} - -static int -adir_onboard_pic_get_irq(void) -{ - volatile u_short *statreg = (volatile u_short *) ADIR_PROCA_INT_STAT; - int irq; - u_short int_status, int_test; - - int_status = in_be16(statreg); - for (irq = 0, int_test = 1; irq < 16; irq++, int_test <<= 1) { - if (int_status & int_test) - break; - } - - if (irq == 16) - return -1; - - return (irq+16); -} - -static void -adir_onboard_pic_enable(unsigned int irq) -{ - volatile u_short *maskreg = (volatile u_short *) ADIR_PROCA_INT_MASK; - - /* Change irq to Adirondack onboard native value */ - irq -= 16; - - /* Enable requested irq number */ - out_be16(maskreg, in_be16(maskreg) & ~(1 << irq)); -} - -static void -adir_onboard_pic_disable(unsigned int irq) -{ - volatile u_short *maskreg = (volatile u_short *) ADIR_PROCA_INT_MASK; - - /* Change irq to Adirondack onboard native value */ - irq -= 16; - - /* Disable requested irq number */ - out_be16(maskreg, in_be16(maskreg) | (1 << irq)); -} - -static struct hw_interrupt_type adir_onboard_pic = { - " ADIR PIC ", - NULL, - NULL, - adir_onboard_pic_enable, /* unmask */ - adir_onboard_pic_disable, /* mask */ - adir_onboard_pic_disable, /* mask and ack */ - NULL, - NULL -}; - -static struct irqaction noop_action = { - .handler = no_action, - .flags = SA_INTERRUPT, - .mask = CPU_MASK_NONE, - .name = "82c59 primary cascade", -}; - -/* - * Linux interrupt values are assigned as follows: - * - * 0-15 VT82C686 8259 interrupts - * 16-31 Adirondack CPLD interrupts - */ -__init void -adir_init_IRQ(void) -{ - int i; - - /* Initialize the cascaded 8259's on the VT82C686 */ - for (i=0; i<16; i++) - irq_desc[i].handler = &i8259_pic; - i8259_init(NULL); - - /* Initialize Adirondack CPLD PIC and enable 8259 interrupt cascade */ - for (i=16; i<32; i++) - irq_desc[i].handler = &adir_onboard_pic; - adir_onboard_pic_init(); - - /* Enable 8259 interrupt cascade */ - setup_irq(ADIR_IRQ_VT82C686_INTR, &noop_action); -} - -int -adir_get_irq(struct pt_regs *regs) -{ - int irq; - - if ((irq = adir_onboard_pic_get_irq()) < 0) - return irq; - - if (irq == ADIR_IRQ_VT82C686_INTR) - irq = i8259_irq(regs); - - return irq; -} diff --git a/arch/ppc/platforms/adir_setup.c b/arch/ppc/platforms/adir_setup.c deleted file mode 100644 index 6a6754e..0000000 --- a/arch/ppc/platforms/adir_setup.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * arch/ppc/platforms/adir_setup.c - * - * Board setup routines for SBS Adirondack - * - * By Michael Sokolov <msokolov@ivan.Harhan.ORG> - * based on the K2 version by Matt Porter <mporter@mvista.com> - */ - -#include <linux/config.h> -#include <linux/stddef.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/reboot.h> -#include <linux/pci.h> -#include <linux/kdev_t.h> -#include <linux/types.h> -#include <linux/major.h> -#include <linux/initrd.h> -#include <linux/console.h> -#include <linux/delay.h> -#include <linux/ide.h> -#include <linux/seq_file.h> -#include <linux/root_dev.h> - -#include <asm/system.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <asm/dma.h> -#include <asm/io.h> -#include <asm/machdep.h> -#include <asm/time.h> -#include <asm/todc.h> -#include <asm/bootinfo.h> - -#include "adir.h" - -extern void adir_init_IRQ(void); -extern int adir_get_irq(struct pt_regs *); -extern void adir_find_bridges(void); -extern unsigned long loops_per_jiffy; - -static unsigned int cpu_750cx[16] = { - 5, 15, 14, 0, 4, 13, 0, 9, 6, 11, 8, 10, 16, 12, 7, 0 -}; - -static int -adir_get_bus_speed(void) -{ - if (!(*((u_char *) ADIR_CLOCK_REG) & ADIR_CLOCK_REG_SEL133)) - return 100000000; - else - return 133333333; -} - -static int -adir_get_cpu_speed(void) -{ - unsigned long hid1; - int cpu_speed; - - hid1 = mfspr(SPRN_HID1) >> 28; - - hid1 = cpu_750cx[hid1]; - - cpu_speed = adir_get_bus_speed()*hid1/2; - return cpu_speed; -} - -static void __init -adir_calibrate_decr(void) -{ - int freq, divisor = 4; - - /* determine processor bus speed */ - freq = adir_get_bus_speed(); - tb_ticks_per_jiffy = freq / HZ / divisor; - tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000); -} - -static int -adir_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: SBS\n"); - seq_printf(m, "machine\t\t: Adirondack\n"); - seq_printf(m, "cpu speed\t: %dMhz\n", adir_get_cpu_speed()/1000000); - seq_printf(m, "bus speed\t: %dMhz\n", adir_get_bus_speed()/1000000); - seq_printf(m, "memory type\t: SDRAM\n"); - - return 0; -} - -extern char cmd_line[]; - -TODC_ALLOC(); - -static void __init -adir_setup_arch(void) -{ - unsigned int cpu; - - /* Setup TODC access */ - TODC_INIT(TODC_TYPE_MC146818, ADIR_NVRAM_RTC_ADDR, 0, - ADIR_NVRAM_RTC_DATA, 8); - - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000/HZ; - - /* Setup PCI host bridges */ - adir_find_bridges(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA1; -#endif - - /* Identify the system */ - printk("System Identification: SBS Adirondack - PowerPC 750CXe @ %d Mhz\n", adir_get_cpu_speed()/1000000); - printk("SBS Adirondack port (C) 2001 SBS Technologies, Inc.\n"); - - /* Identify the CPU manufacturer */ - cpu = mfspr(SPRN_PVR); - printk("CPU manufacturer: IBM [rev=%04x]\n", (cpu & 0xffff)); -} - -static void -adir_restart(char *cmd) -{ - local_irq_disable(); - /* SRR0 has system reset vector, SRR1 has default MSR value */ - /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ - __asm__ __volatile__ - ("lis 3,0xfff0\n\t" - "ori 3,3,0x0100\n\t" - "mtspr 26,3\n\t" - "li 3,0\n\t" - "mtspr 27,3\n\t" - "rfi\n\t"); - for(;;); -} - -static void -adir_power_off(void) -{ - for(;;); -} - -static void -adir_halt(void) -{ - adir_restart(NULL); -} - -static unsigned long __init -adir_find_end_of_memory(void) -{ - return boot_mem_size; -} - -static void __init -adir_map_io(void) -{ - io_block_mapping(ADIR_PCI32_VIRT_IO_BASE, ADIR_PCI32_IO_BASE, - ADIR_PCI32_VIRT_IO_SIZE, _PAGE_IO); - io_block_mapping(ADIR_PCI64_VIRT_IO_BASE, ADIR_PCI64_IO_BASE, - ADIR_PCI64_VIRT_IO_SIZE, _PAGE_IO); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - /* - * On the Adirondack we use bi_recs and pass the pointer to them in R3. - */ - parse_bootinfo((struct bi_record *) (r3 + KERNELBASE)); - - /* Remember, isa_io_base is virtual but isa_mem_base is physical! */ - isa_io_base = ADIR_PCI32_VIRT_IO_BASE; - isa_mem_base = ADIR_PCI32_MEM_BASE; - pci_dram_offset = ADIR_PCI_SYS_MEM_BASE; - - ppc_md.setup_arch = adir_setup_arch; - ppc_md.show_cpuinfo = adir_show_cpuinfo; - ppc_md.irq_canonicalize = NULL; - ppc_md.init_IRQ = adir_init_IRQ; - ppc_md.get_irq = adir_get_irq; - ppc_md.init = NULL; - - ppc_md.find_end_of_memory = adir_find_end_of_memory; - ppc_md.setup_io_mappings = adir_map_io; - - ppc_md.restart = adir_restart; - ppc_md.power_off = adir_power_off; - ppc_md.halt = adir_halt; - - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.nvram_read_val = todc_mc146818_read_val; - ppc_md.nvram_write_val = todc_mc146818_write_val; - ppc_md.calibrate_decr = adir_calibrate_decr; -} diff --git a/arch/ppc/platforms/cpci690.c b/arch/ppc/platforms/cpci690.c index 507870c..f64ac2a 100644 --- a/arch/ppc/platforms/cpci690.c +++ b/arch/ppc/platforms/cpci690.c @@ -35,11 +35,7 @@ #define SET_PCI_IDE_NATIVE static struct mv64x60_handle bh; -static u32 cpci690_br_base; - -static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */ - 18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0 -}; +static void __iomem *cpci690_br_base; TODC_ALLOC(); @@ -55,7 +51,7 @@ cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) * A B C D */ { - { 90, 91, 88, 89}, /* IDSEL 30/20 - Sentinel */ + { 90, 91, 88, 89 }, /* IDSEL 30/20 - Sentinel */ }; const long min_idsel = 20, max_idsel = 20, irqs_per_slot = 4; @@ -67,9 +63,9 @@ cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) * A B C D */ { - { 93, 94, 95, 92}, /* IDSEL 28/18 - PMC slot 2 */ - { 0, 0, 0, 0}, /* IDSEL 29/19 - Not used */ - { 94, 95, 92, 93}, /* IDSEL 30/20 - PMC slot 1 */ + { 93, 94, 95, 92 }, /* IDSEL 28/18 - PMC slot 2 */ + { 0, 0, 0, 0 }, /* IDSEL 29/19 - Not used */ + { 94, 95, 92, 93 }, /* IDSEL 30/20 - PMC slot 1 */ }; const long min_idsel = 18, max_idsel = 20, irqs_per_slot = 4; @@ -77,68 +73,29 @@ cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) } } -static int -cpci690_get_cpu_speed(void) -{ - unsigned long hid1; +#define GB (1024UL * 1024UL * 1024UL) - hid1 = mfspr(SPRN_HID1) >> 28; - return CPCI690_BUS_FREQ * cpu_7xx[hid1]/2; +static u32 +cpci690_get_bus_freq(void) +{ + if (boot_mem_size >= (1*GB)) /* bus speed based on mem size */ + return 100000000; + else + return 133333333; } -#define KB (1024UL) -#define MB (1024UL * KB) -#define GB (1024UL * MB) +static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */ + 0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/ + 16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/ +}; -unsigned long __init -cpci690_find_end_of_memory(void) +static int +cpci690_get_cpu_freq(void) { - u32 mem_ctlr_size; - static u32 board_size; - static u8 first_time = 1; - - if (first_time) { - /* Using cpci690_set_bat() mapping ==> virt addr == phys addr */ - switch (in_8((u8 *) (cpci690_br_base + - CPCI690_BR_MEM_CTLR)) & 0x07) { - case 0x01: - board_size = 256*MB; - break; - case 0x02: - board_size = 512*MB; - break; - case 0x03: - board_size = 768*MB; - break; - case 0x04: - board_size = 1*GB; - break; - case 0x05: - board_size = 1*GB + 512*MB; - break; - case 0x06: - board_size = 2*GB; - break; - default: - board_size = 0xffffffff; /* use mem ctlr size */ - } /* switch */ - - mem_ctlr_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, - MV64x60_TYPE_GT64260A); - - /* Check that mem ctlr & board reg agree. If not, pick MIN. */ - if (board_size != mem_ctlr_size) { - printk(KERN_WARNING "Board register & memory controller" - "mem size disagree (board reg: 0x%lx, " - "mem ctlr: 0x%lx)\n", - (ulong)board_size, (ulong)mem_ctlr_size); - board_size = min(board_size, mem_ctlr_size); - } - - first_time = 0; - } /* if */ - - return board_size; + unsigned long pll_cfg; + + pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27; + return cpci690_get_bus_freq() * cpu_750xx[pll_cfg]/2; } static void __init @@ -228,7 +185,7 @@ cpci690_setup_peripherals(void) mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CPCI690_BR_BASE, CPCI690_BR_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); - cpci690_br_base = (u32)ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE); + cpci690_br_base = ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CPCI690_TODC_BASE, CPCI690_TODC_SIZE, 0); @@ -329,7 +286,7 @@ cpci690_fixup_mpsc_pdata(struct platform_device *pdev) pdata->max_idle = 40; pdata->default_baud = CPCI690_MPSC_BAUD; pdata->brg_clk_src = CPCI690_MPSC_CLK_SRC; - pdata->brg_clk_freq = CPCI690_BUS_FREQ; + pdata->brg_clk_freq = cpci690_get_bus_freq(); } static int __init @@ -365,7 +322,7 @@ cpci690_reset_board(void) u32 i = 10000; local_irq_disable(); - out_8((u8 *)(cpci690_br_base + CPCI690_BR_SW_RESET), 0x11); + out_8((cpci690_br_base + CPCI690_BR_SW_RESET), 0x11); while (i != 0) i++; panic("restart failed\n"); @@ -394,10 +351,40 @@ cpci690_power_off(void) static int cpci690_show_cpuinfo(struct seq_file *m) { + char *s; + + seq_printf(m, "cpu MHz\t\t: %d\n", + (cpci690_get_cpu_freq() + 500000) / 1000000); + seq_printf(m, "bus MHz\t\t: %d\n", + (cpci690_get_bus_freq() + 500000) / 1000000); seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n"); seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n"); - seq_printf(m, "cpu MHz\t\t: %d\n", cpci690_get_cpu_speed()/1000/1000); - seq_printf(m, "bus MHz\t\t: %d\n", CPCI690_BUS_FREQ/1000/1000); + seq_printf(m, "FPGA Revision\t: %d\n", + in_8(cpci690_br_base + CPCI690_BR_MEM_CTLR) >> 5); + + switch(bh.type) { + case MV64x60_TYPE_GT64260A: + s = "gt64260a"; + break; + case MV64x60_TYPE_GT64260B: + s = "gt64260b"; + break; + case MV64x60_TYPE_MV64360: + s = "mv64360"; + break; + case MV64x60_TYPE_MV64460: + s = "mv64460"; + break; + default: + s = "Unknown"; + } + seq_printf(m, "bridge type\t: %s\n", s); + seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev); +#if defined(CONFIG_NOT_COHERENT_CACHE) + seq_printf(m, "coherency\t: %s\n", "off"); +#else + seq_printf(m, "coherency\t: %s\n", "on"); +#endif return 0; } @@ -407,7 +394,7 @@ cpci690_calibrate_decr(void) { ulong freq; - freq = CPCI690_BUS_FREQ / 4; + freq = cpci690_get_bus_freq() / 4; printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", freq/1000000, freq%1000000); @@ -416,25 +403,12 @@ cpci690_calibrate_decr(void) tb_to_us = mulhwu_scale_factor(freq, 1000000); } -static __inline__ void -cpci690_set_bat(u32 addr, u32 size) -{ - addr &= 0xfffe0000; - size &= 0x1ffe0000; - size = ((size >> 17) - 1) << 2; - - mb(); - mtspr(SPRN_DBAT1U, addr | size | 0x2); /* Vs == 1; Vp == 0 */ - mtspr(SPRN_DBAT1L, addr | 0x2a); /* WIMG bits == 0101; PP == r/w access */ - mb(); -} - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC) static void __init cpci690_map_io(void) { io_block_mapping(CONFIG_MV64X60_NEW_BASE, CONFIG_MV64X60_NEW_BASE, - 128 * KB, _PAGE_IO); + 128 * 1024, _PAGE_IO); } #endif @@ -442,14 +416,15 @@ void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7) { -#ifdef CONFIG_BLK_DEV_INITRD - initrd_start=initrd_end=0; - initrd_below_start_ok=0; -#endif /* CONFIG_BLK_DEV_INITRD */ - parse_bootinfo(find_bootinfo()); - loops_per_jiffy = cpci690_get_cpu_speed() / HZ; +#ifdef CONFIG_BLK_DEV_INITRD + /* take care of initrd if we have one */ + if (r4) { + initrd_start = r4 + KERNELBASE; + initrd_end = r5 + KERNELBASE; + } +#endif /* CONFIG_BLK_DEV_INITRD */ isa_mem_base = 0; @@ -460,7 +435,6 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, ppc_md.restart = cpci690_restart; ppc_md.power_off = cpci690_power_off; ppc_md.halt = cpci690_halt; - ppc_md.find_end_of_memory = cpci690_find_end_of_memory; ppc_md.time_init = todc_time_init; ppc_md.set_rtc_time = todc_set_rtc_time; ppc_md.get_rtc_time = todc_get_rtc_time; @@ -468,22 +442,13 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, ppc_md.nvram_write_val = todc_direct_write_val; ppc_md.calibrate_decr = cpci690_calibrate_decr; - /* - * Need to map in board regs (used by cpci690_find_end_of_memory()) - * and the bridge's regs (used by progress); - */ - cpci690_set_bat(CPCI690_BR_BASE, 32 * MB); - cpci690_br_base = CPCI690_BR_BASE; - -#ifdef CONFIG_SERIAL_TEXT_DEBUG +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC) ppc_md.setup_io_mappings = cpci690_map_io; +#ifdef CONFIG_SERIAL_TEXT_DEBUG ppc_md.progress = mv64x60_mpsc_progress; mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); #endif /* CONFIG_SERIAL_TEXT_DEBUG */ -#ifdef CONFIG_KGDB - ppc_md.setup_io_mappings = cpci690_map_io; - ppc_md.early_serial_map = cpci690_early_serial_map; -#endif /* CONFIG_KGDB */ +#endif /* defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC) */ #if defined(CONFIG_SERIAL_MPSC) platform_notify = cpci690_platform_notify; diff --git a/arch/ppc/platforms/cpci690.h b/arch/ppc/platforms/cpci690.h index 36cd267..49584c9 100644 --- a/arch/ppc/platforms/cpci690.h +++ b/arch/ppc/platforms/cpci690.h @@ -73,6 +73,4 @@ typedef struct board_info { #define CPCI690_MPSC_BAUD 9600 #define CPCI690_MPSC_CLK_SRC 8 /* TCLK */ -#define CPCI690_BUS_FREQ 133333333 - #endif /* __PPC_PLATFORMS_CPCI690_H */ diff --git a/arch/ppc/platforms/ev64360.c b/arch/ppc/platforms/ev64360.c new file mode 100644 index 0000000..9811a8a --- /dev/null +++ b/arch/ppc/platforms/ev64360.c @@ -0,0 +1,510 @@ +/* + * arch/ppc/platforms/ev64360.c + * + * Board setup routines for the Marvell EV-64360-BP Evaluation Board. + * + * Author: Lee Nicks <allinux@gmail.com> + * + * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il + * Based on code done by - Mark A. Greer <mgreer@mvista.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/config.h> +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/kdev_t.h> +#include <linux/console.h> +#include <linux/initrd.h> +#include <linux/root_dev.h> +#include <linux/delay.h> +#include <linux/seq_file.h> +#include <linux/bootmem.h> +#include <linux/mtd/physmap.h> +#include <linux/mv643xx.h> +#ifdef CONFIG_BOOTIMG +#include <linux/bootimg.h> +#endif +#include <asm/page.h> +#include <asm/time.h> +#include <asm/smp.h> +#include <asm/todc.h> +#include <asm/bootinfo.h> +#include <asm/ppcboot.h> +#include <asm/mv64x60.h> +#include <platforms/ev64360.h> + +#define BOARD_VENDOR "Marvell" +#define BOARD_MACHINE "EV-64360-BP" + +static struct mv64x60_handle bh; +static void __iomem *sram_base; + +static u32 ev64360_flash_size_0; +static u32 ev64360_flash_size_1; + +static u32 ev64360_bus_frequency; + +unsigned char __res[sizeof(bd_t)]; + +static int __init +ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) +{ + return 0; +} + +static void __init +ev64360_setup_bridge(void) +{ + struct mv64x60_setup_info si; + int i; + + memset(&si, 0, sizeof(si)); + + si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; + + #ifdef CONFIG_PCI + si.pci_1.enable_bus = 1; + si.pci_1.pci_io.cpu_base = EV64360_PCI1_IO_START_PROC_ADDR; + si.pci_1.pci_io.pci_base_hi = 0; + si.pci_1.pci_io.pci_base_lo = EV64360_PCI1_IO_START_PCI_ADDR; + si.pci_1.pci_io.size = EV64360_PCI1_IO_SIZE; + si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; + si.pci_1.pci_mem[0].cpu_base = EV64360_PCI1_MEM_START_PROC_ADDR; + si.pci_1.pci_mem[0].pci_base_hi = EV64360_PCI1_MEM_START_PCI_HI_ADDR; + si.pci_1.pci_mem[0].pci_base_lo = EV64360_PCI1_MEM_START_PCI_LO_ADDR; + si.pci_1.pci_mem[0].size = EV64360_PCI1_MEM_SIZE; + si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; + si.pci_1.pci_cmd_bits = 0; + si.pci_1.latency_timer = 0x80; + #else + si.pci_0.enable_bus = 0; + si.pci_1.enable_bus = 0; + #endif + + for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) { +#if defined(CONFIG_NOT_COHERENT_CACHE) + si.cpu_prot_options[i] = 0; + si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; + si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; + si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; + + si.pci_1.acc_cntl_options[i] = + MV64360_PCI_ACC_CNTL_SNOOP_NONE | + MV64360_PCI_ACC_CNTL_SWAP_NONE | + MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | + MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; +#else + si.cpu_prot_options[i] = 0; + si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */ + si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */ + si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */ + + si.pci_1.acc_cntl_options[i] = + MV64360_PCI_ACC_CNTL_SNOOP_WB | + MV64360_PCI_ACC_CNTL_SWAP_NONE | + MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | + MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES; +#endif + } + + if (mv64x60_init(&bh, &si)) + printk(KERN_WARNING "Bridge initialization failed.\n"); + + #ifdef CONFIG_PCI + pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */ + ppc_md.pci_swizzle = common_swizzle; + ppc_md.pci_map_irq = ev64360_map_irq; + ppc_md.pci_exclude_device = mv64x60_pci_exclude_device; + + mv64x60_set_bus(&bh, 1, 0); + bh.hose_b->first_busno = 0; + bh.hose_b->last_busno = 0xff; + #endif +} + +/* Bridge & platform setup routines */ +void __init +ev64360_intr_setup(void) +{ + /* MPP 8, 9, and 10 */ + mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff); + + /* + * Define GPP 8,9,and 10 interrupt polarity as active low + * input signal and level triggered + */ + mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700); + mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700); + + /* Config GPP intr ctlr to respond to level trigger */ + mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10)); + + /* Erranum FEr PCI-#8 */ + mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9)); + mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9)); + + /* + * Dismiss and then enable interrupt on GPP interrupt cause + * for CPU #0 + */ + mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700); + mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700); + + /* + * Dismiss and then enable interrupt on CPU #0 high cause reg + * BIT25 summarizes GPP interrupts 8-15 + */ + mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25)); +} + +void __init +ev64360_setup_peripherals(void) +{ + u32 base; + + /* Set up window for boot CS */ + mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, + EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); + + /* We only use the 32-bit flash */ + mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base, + &ev64360_flash_size_0); + ev64360_flash_size_1 = 0; + + mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, + EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); + + mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, + EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0); + bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); + sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE); + + /* Set up Enet->SRAM window */ + mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, + EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2); + bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN); + + /* Give enet r/w access to memory region */ + mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1))); + mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1))); + mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1))); + + mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3)); + mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, + ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24))); + +#if defined(CONFIG_NOT_COHERENT_CACHE) + mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000); +#else + mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2); +#endif + + /* + * Setting the SRAM to 0. Note that this generates parity errors on + * internal data path in SRAM since it's first time accessing it + * while after reset it's not configured. + */ + memset(sram_base, 0, MV64360_SRAM_SIZE); + + /* set up PCI interrupt controller */ + ev64360_intr_setup(); +} + +static void __init +ev64360_setup_arch(void) +{ + if (ppc_md.progress) + ppc_md.progress("ev64360_setup_arch: enter", 0); + + set_tb(0, 0); + +#ifdef CONFIG_BLK_DEV_INITRD + if (initrd_start) + ROOT_DEV = Root_RAM0; + else +#endif +#ifdef CONFIG_ROOT_NFS + ROOT_DEV = Root_NFS; +#else + ROOT_DEV = Root_SDA2; +#endif + + /* + * Set up the L2CR register. + */ + _set_L2CR(L2CR_L2E | L2CR_L2PE); + + if (ppc_md.progress) + ppc_md.progress("ev64360_setup_arch: calling setup_bridge", 0); + + ev64360_setup_bridge(); + ev64360_setup_peripherals(); + ev64360_bus_frequency = ev64360_bus_freq(); + + printk(KERN_INFO "%s %s port (C) 2005 Lee Nicks " + "(allinux@gmail.com)\n", BOARD_VENDOR, BOARD_MACHINE); + if (ppc_md.progress) + ppc_md.progress("ev64360_setup_arch: exit", 0); +} + +/* Platform device data fixup routines. */ +#if defined(CONFIG_SERIAL_MPSC) +static void __init +ev64360_fixup_mpsc_pdata(struct platform_device *pdev) +{ + struct mpsc_pdata *pdata; + + pdata = (struct mpsc_pdata *)pdev->dev.platform_data; + + pdata->max_idle = 40; + pdata->default_baud = EV64360_DEFAULT_BAUD; + pdata->brg_clk_src = EV64360_MPSC_CLK_SRC; + /* + * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts, + * TCLK == SysCLK but on 64460, they are separate pins. + * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz. + */ + pdata->brg_clk_freq = min(ev64360_bus_frequency, MV64x60_TCLK_FREQ_MAX); +} +#endif + +#if defined(CONFIG_MV643XX_ETH) +static void __init +ev64360_fixup_eth_pdata(struct platform_device *pdev) +{ + struct mv643xx_eth_platform_data *eth_pd; + static u16 phy_addr[] = { + EV64360_ETH0_PHY_ADDR, + EV64360_ETH1_PHY_ADDR, + EV64360_ETH2_PHY_ADDR, + }; + + eth_pd = pdev->dev.platform_data; + eth_pd->force_phy_addr = 1; + eth_pd->phy_addr = phy_addr[pdev->id]; + eth_pd->tx_queue_size = EV64360_ETH_TX_QUEUE_SIZE; + eth_pd->rx_queue_size = EV64360_ETH_RX_QUEUE_SIZE; +} +#endif + +static int __init +ev64360_platform_notify(struct device *dev) +{ + static struct { + char *bus_id; + void ((*rtn)(struct platform_device *pdev)); + } dev_map[] = { +#if defined(CONFIG_SERIAL_MPSC) + { MPSC_CTLR_NAME ".0", ev64360_fixup_mpsc_pdata }, + { MPSC_CTLR_NAME ".1", ev64360_fixup_mpsc_pdata }, +#endif +#if defined(CONFIG_MV643XX_ETH) + { MV643XX_ETH_NAME ".0", ev64360_fixup_eth_pdata }, + { MV643XX_ETH_NAME ".1", ev64360_fixup_eth_pdata }, + { MV643XX_ETH_NAME ".2", ev64360_fixup_eth_pdata }, +#endif + }; + struct platform_device *pdev; + int i; + + if (dev && dev->bus_id) + for (i=0; i<ARRAY_SIZE(dev_map); i++) + if (!strncmp(dev->bus_id, dev_map[i].bus_id, + BUS_ID_SIZE)) { + + pdev = container_of(dev, + struct platform_device, dev); + dev_map[i].rtn(pdev); + } + + return 0; +} + +#ifdef CONFIG_MTD_PHYSMAP + +#ifndef MB +#define MB (1 << 20) +#endif + +/* + * MTD Layout. + * + * FLASH Amount: 0xff000000 - 0xffffffff + * ------------- ----------------------- + * Reserved: 0xff000000 - 0xff03ffff + * JFFS2 file system: 0xff040000 - 0xffefffff + * U-boot: 0xfff00000 - 0xffffffff + */ +static int __init +ev64360_setup_mtd(void) +{ + u32 size; + int ptbl_entries; + static struct mtd_partition *ptbl; + + size = ev64360_flash_size_0 + ev64360_flash_size_1; + if (!size) + return -ENOMEM; + + ptbl_entries = 3; + + if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition), + GFP_KERNEL)) == NULL) { + + printk(KERN_WARNING "Can't alloc MTD partition table\n"); + return -ENOMEM; + } + memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition)); + + ptbl[0].name = "reserved"; + ptbl[0].offset = 0; + ptbl[0].size = EV64360_MTD_RESERVED_SIZE; + ptbl[1].name = "jffs2"; + ptbl[1].offset = EV64360_MTD_RESERVED_SIZE; + ptbl[1].size = EV64360_MTD_JFFS2_SIZE; + ptbl[2].name = "U-BOOT"; + ptbl[2].offset = EV64360_MTD_RESERVED_SIZE + EV64360_MTD_JFFS2_SIZE; + ptbl[2].size = EV64360_MTD_UBOOT_SIZE; + + physmap_map.size = size; + physmap_set_partitions(ptbl, ptbl_entries); + return 0; +} + +arch_initcall(ev64360_setup_mtd); +#endif + +static void +ev64360_restart(char *cmd) +{ + ulong i = 0xffffffff; + volatile unsigned char * rtc_base = ioremap(EV64360_RTC_WINDOW_BASE,0x4000); + + /* issue hard reset */ + rtc_base[0xf] = 0x80; + rtc_base[0xc] = 0x00; + rtc_base[0xd] = 0x01; + rtc_base[0xf] = 0x83; + + while (i-- > 0) ; + panic("restart failed\n"); +} + +static void +ev64360_halt(void) +{ + while (1) ; + /* NOTREACHED */ +} + +static void +ev64360_power_off(void) +{ + ev64360_halt(); + /* NOTREACHED */ +} + +static int +ev64360_show_cpuinfo(struct seq_file *m) +{ + seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n"); + seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n"); + seq_printf(m, "bus speed\t: %dMHz\n", ev64360_bus_frequency/1000/1000); + + return 0; +} + +static void __init +ev64360_calibrate_decr(void) +{ + u32 freq; + + freq = ev64360_bus_frequency / 4; + + printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", + (long)freq / 1000000, (long)freq % 1000000); + + tb_ticks_per_jiffy = freq / HZ; + tb_to_us = mulhwu_scale_factor(freq, 1000000); +} + +unsigned long __init +ev64360_find_end_of_memory(void) +{ + return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, + MV64x60_TYPE_MV64360); +} + +static inline void +ev64360_set_bat(void) +{ + mb(); + mtspr(SPRN_DBAT2U, 0xf0001ffe); + mtspr(SPRN_DBAT2L, 0xf000002a); + mb(); +} + +#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) +static void __init +ev64360_map_io(void) +{ + io_block_mapping(CONFIG_MV64X60_NEW_BASE, \ + CONFIG_MV64X60_NEW_BASE, \ + 0x00020000, _PAGE_IO); +} +#endif + +void __init +platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + parse_bootinfo(find_bootinfo()); + + /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer) + * are non-zero, then we should use the board info from the bd_t + * structure and the cmdline pointed to by r6 instead of the + * information from birecs, if any. Otherwise, use the information + * from birecs as discovered by the preceeding call to + * parse_bootinfo(). This rule should work with both PPCBoot, which + * uses a bd_t board info structure, and the kernel boot wrapper, + * which uses birecs. + */ + if (r3 && r6) { + /* copy board info structure */ + memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) ); + /* copy command line */ + *(char *)(r7+KERNELBASE) = 0; + strcpy(cmd_line, (char *)(r6+KERNELBASE)); + } + #ifdef CONFIG_ISA + isa_mem_base = 0; + #endif + + ppc_md.setup_arch = ev64360_setup_arch; + ppc_md.show_cpuinfo = ev64360_show_cpuinfo; + ppc_md.init_IRQ = mv64360_init_irq; + ppc_md.get_irq = mv64360_get_irq; + ppc_md.restart = ev64360_restart; + ppc_md.power_off = ev64360_power_off; + ppc_md.halt = ev64360_halt; + ppc_md.find_end_of_memory = ev64360_find_end_of_memory; + ppc_md.calibrate_decr = ev64360_calibrate_decr; + +#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) + ppc_md.setup_io_mappings = ev64360_map_io; + ppc_md.progress = mv64x60_mpsc_progress; + mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); +#endif + +#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) + platform_notify = ev64360_platform_notify; +#endif + + ev64360_set_bat(); /* Need for ev64360_find_end_of_memory and progress */ +} diff --git a/arch/ppc/platforms/ev64360.h b/arch/ppc/platforms/ev64360.h new file mode 100644 index 0000000..68eabe4 --- /dev/null +++ b/arch/ppc/platforms/ev64360.h @@ -0,0 +1,116 @@ +/* + * arch/ppc/platforms/ev64360.h + * + * Definitions for Marvell EV-64360-BP Evaluation Board. + * + * Author: Lee Nicks <allinux@gmail.com> + * + * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il + * Based on code done by Mark A. Greer <mgreer@mvista.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/* + * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to + * PCI I/O space and 4 windows from the CPU bus to PCI MEM space. + * We'll only use one PCI MEM window on each PCI bus. + * + * This is the CPU physical memory map (windows must be at least 64KB and start + * on a boundary that is a multiple of the window size): + * + * 0x42000000-0x4203ffff - Internal SRAM + * 0xf1000000-0xf100ffff - MV64360 Registers (CONFIG_MV64X60_NEW_BASE) + * 0xfc800000-0xfcffffff - RTC + * 0xff000000-0xffffffff - Boot window, 16 MB flash + * 0xc0000000-0xc3ffffff - PCI I/O (second hose) + * 0x80000000-0xbfffffff - PCI MEM (second hose) + */ + +#ifndef __PPC_PLATFORMS_EV64360_H +#define __PPC_PLATFORMS_EV64360_H + +/* CPU Physical Memory Map setup. */ +#define EV64360_BOOT_WINDOW_BASE 0xff000000 +#define EV64360_BOOT_WINDOW_SIZE 0x01000000 /* 16 MB */ +#define EV64360_INTERNAL_SRAM_BASE 0x42000000 +#define EV64360_RTC_WINDOW_BASE 0xfc800000 +#define EV64360_RTC_WINDOW_SIZE 0x00800000 /* 8 MB */ + +#define EV64360_PCI1_MEM_START_PROC_ADDR 0x80000000 +#define EV64360_PCI1_MEM_START_PCI_HI_ADDR 0x00000000 +#define EV64360_PCI1_MEM_START_PCI_LO_ADDR 0x80000000 +#define EV64360_PCI1_MEM_SIZE 0x40000000 /* 1 GB */ +#define EV64360_PCI1_IO_START_PROC_ADDR 0xc0000000 +#define EV64360_PCI1_IO_START_PCI_ADDR 0x00000000 +#define EV64360_PCI1_IO_SIZE 0x04000000 /* 64 MB */ + +#define EV64360_DEFAULT_BAUD 115200 +#define EV64360_MPSC_CLK_SRC 8 /* TCLK */ +#define EV64360_MPSC_CLK_FREQ 133333333 + +#define EV64360_MTD_RESERVED_SIZE 0x40000 +#define EV64360_MTD_JFFS2_SIZE 0xec0000 +#define EV64360_MTD_UBOOT_SIZE 0x100000 + +#define EV64360_ETH0_PHY_ADDR 8 +#define EV64360_ETH1_PHY_ADDR 9 +#define EV64360_ETH2_PHY_ADDR 10 + +#define EV64360_ETH_TX_QUEUE_SIZE 800 +#define EV64360_ETH_RX_QUEUE_SIZE 400 + +#define EV64360_ETH_PORT_CONFIG_VALUE \ + ETH_UNICAST_NORMAL_MODE | \ + ETH_DEFAULT_RX_QUEUE_0 | \ + ETH_DEFAULT_RX_ARP_QUEUE_0 | \ + ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ + ETH_RECEIVE_BC_IF_IP | \ + ETH_RECEIVE_BC_IF_ARP | \ + ETH_CAPTURE_TCP_FRAMES_DIS | \ + ETH_CAPTURE_UDP_FRAMES_DIS | \ + ETH_DEFAULT_RX_TCP_QUEUE_0 | \ + ETH_DEFAULT_RX_UDP_QUEUE_0 | \ + ETH_DEFAULT_RX_BPDU_QUEUE_0 + +#define EV64360_ETH_PORT_CONFIG_EXTEND_VALUE \ + ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ + ETH_PARTITION_DISABLE + +#define GT_ETH_IPG_INT_RX(value) \ + ((value & 0x3fff) << 8) + +#define EV64360_ETH_PORT_SDMA_CONFIG_VALUE \ + ETH_RX_BURST_SIZE_4_64BIT | \ + GT_ETH_IPG_INT_RX(0) | \ + ETH_TX_BURST_SIZE_4_64BIT + +#define EV64360_ETH_PORT_SERIAL_CONTROL_VALUE \ + ETH_FORCE_LINK_PASS | \ + ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ + ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ + ETH_ADV_SYMMETRIC_FLOW_CTRL | \ + ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + ETH_FORCE_BP_MODE_NO_JAM | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL | \ + ETH_RETRANSMIT_16_ATTEMPTS | \ + ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ + ETH_DTE_ADV_0 | \ + ETH_DISABLE_AUTO_NEG_BYPASS | \ + ETH_AUTO_NEG_NO_CHANGE | \ + ETH_MAX_RX_PACKET_9700BYTE | \ + ETH_CLR_EXT_LOOPBACK | \ + ETH_SET_FULL_DUPLEX_MODE | \ + ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX + +static inline u32 +ev64360_bus_freq(void) +{ + return 133333333; +} + +#endif /* __PPC_PLATFORMS_EV64360_H */ diff --git a/arch/ppc/platforms/k2.c b/arch/ppc/platforms/k2.c deleted file mode 100644 index aacb438..0000000 --- a/arch/ppc/platforms/k2.c +++ /dev/null @@ -1,613 +0,0 @@ -/* - * arch/ppc/platforms/k2.c - * - * Board setup routines for SBS K2 - * - * Author: Matt Porter <mporter@mvista.com> - * - * Updated by: Randy Vinson <rvinson@mvista.com. - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include <linux/config.h> -#include <linux/stddef.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/reboot.h> -#include <linux/pci.h> -#include <linux/kdev_t.h> -#include <linux/types.h> -#include <linux/major.h> -#include <linux/initrd.h> -#include <linux/console.h> -#include <linux/delay.h> -#include <linux/ide.h> -#include <linux/irq.h> -#include <linux/seq_file.h> -#include <linux/root_dev.h> - -#include <asm/system.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <asm/dma.h> -#include <asm/io.h> -#include <asm/machdep.h> -#include <asm/time.h> -#include <asm/i8259.h> -#include <asm/todc.h> -#include <asm/bootinfo.h> - -#include <syslib/cpc710.h> -#include "k2.h" - -extern unsigned long loops_per_jiffy; -extern void gen550_progress(char *, unsigned short); - -static unsigned int cpu_7xx[16] = { - 0, 15, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0 -}; -static unsigned int cpu_6xx[16] = { - 0, 0, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 0, 12, 7, 0 -}; - -static inline int __init -k2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); - /* - * Check our hose index. If we are zero then we are on the - * local PCI hose, otherwise we are on the cPCI hose. - */ - if (!hose->index) { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {1, 0, 0, 0}, /* Ethernet */ - {5, 5, 5, 5}, /* PMC Site 1 */ - {6, 6, 6, 6}, /* PMC Site 2 */ - {0, 0, 0, 0}, /* unused */ - {0, 0, 0, 0}, /* unused */ - {0, 0, 0, 0}, /* PCI-ISA Bridge */ - {0, 0, 0, 0}, /* unused */ - {0, 0, 0, 0}, /* unused */ - {0, 0, 0, 0}, /* unused */ - {0, 0, 0, 0}, /* unused */ - {0, 0, 0, 0}, /* unused */ - {0, 0, 0, 0}, /* unused */ - {0, 0, 0, 0}, /* unused */ - {0, 0, 0, 0}, /* unused */ - {15, 0, 0, 0}, /* M5229 IDE */ - }; - const long min_idsel = 3, max_idsel = 17, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } else { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {10, 11, 12, 9}, /* cPCI slot 8 */ - {11, 12, 9, 10}, /* cPCI slot 7 */ - {12, 9, 10, 11}, /* cPCI slot 6 */ - {9, 10, 11, 12}, /* cPCI slot 5 */ - {10, 11, 12, 9}, /* cPCI slot 4 */ - {11, 12, 9, 10}, /* cPCI slot 3 */ - {12, 9, 10, 11}, /* cPCI slot 2 */ - }; - const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } -} - -void k2_pcibios_fixup(void) -{ -#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) - struct pci_dev *ide_dev; - - /* - * Enable DMA support on hdc - */ - ide_dev = pci_get_device(PCI_VENDOR_ID_AL, - PCI_DEVICE_ID_AL_M5229, NULL); - - if (ide_dev) { - - unsigned long ide_dma_base; - - ide_dma_base = pci_resource_start(ide_dev, 4); - outb(0x00, ide_dma_base + 0x2); - outb(0x20, ide_dma_base + 0xa); - pci_dev_put(ide_dev); - } -#endif -} - -void k2_pcibios_fixup_resources(struct pci_dev *dev) -{ - int i; - - if ((dev->vendor == PCI_VENDOR_ID_IBM) && - (dev->device == PCI_DEVICE_ID_IBM_CPC710_PCI64)) { - pr_debug("Fixup CPC710 resources\n"); - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - } - } -} - -void k2_setup_hoses(void) -{ - struct pci_controller *hose_a, *hose_b; - - /* - * Reconfigure CPC710 memory map so - * we have some more PCI memory space. - */ - - /* Set FPHB mode */ - __raw_writel(0x808000e0, PGCHP); /* Set FPHB mode */ - - /* PCI32 mappings */ - __raw_writel(0x00000000, K2_PCI32_BAR + PIBAR); /* PCI I/O base */ - __raw_writel(0x00000000, K2_PCI32_BAR + PMBAR); /* PCI Mem base */ - __raw_writel(0xf0000000, K2_PCI32_BAR + MSIZE); /* 256MB */ - __raw_writel(0xfff00000, K2_PCI32_BAR + IOSIZE); /* 1MB */ - __raw_writel(0xc0000000, K2_PCI32_BAR + SMBAR); /* Base@0xc0000000 */ - __raw_writel(0x80000000, K2_PCI32_BAR + SIBAR); /* Base@0x80000000 */ - __raw_writel(0x000000c0, K2_PCI32_BAR + PSSIZE); /* 1GB space */ - __raw_writel(0x000000c0, K2_PCI32_BAR + PPSIZE); /* 1GB space */ - __raw_writel(0x00000000, K2_PCI32_BAR + BARPS); /* Base@0x00000000 */ - __raw_writel(0x00000000, K2_PCI32_BAR + BARPP); /* Base@0x00000000 */ - __raw_writel(0x00000080, K2_PCI32_BAR + PSBAR); /* Base@0x80 */ - __raw_writel(0x00000000, K2_PCI32_BAR + PPBAR); - - __raw_writel(0xc0000000, K2_PCI32_BAR + BPMDLK); - __raw_writel(0xd0000000, K2_PCI32_BAR + TPMDLK); - __raw_writel(0x80000000, K2_PCI32_BAR + BIODLK); - __raw_writel(0x80100000, K2_PCI32_BAR + TIODLK); - __raw_writel(0xe0008000, K2_PCI32_BAR + DLKCTRL); - __raw_writel(0xffffffff, K2_PCI32_BAR + DLKDEV); - - /* PCI64 mappings */ - __raw_writel(0x00100000, K2_PCI64_BAR + PIBAR); /* PCI I/O base */ - __raw_writel(0x10000000, K2_PCI64_BAR + PMBAR); /* PCI Mem base */ - __raw_writel(0xf0000000, K2_PCI64_BAR + MSIZE); /* 256MB */ - __raw_writel(0xfff00000, K2_PCI64_BAR + IOSIZE); /* 1MB */ - __raw_writel(0xd0000000, K2_PCI64_BAR + SMBAR); /* Base@0xd0000000 */ - __raw_writel(0x80100000, K2_PCI64_BAR + SIBAR); /* Base@0x80100000 */ - __raw_writel(0x000000c0, K2_PCI64_BAR + PSSIZE); /* 1GB space */ - __raw_writel(0x000000c0, K2_PCI64_BAR + PPSIZE); /* 1GB space */ - __raw_writel(0x00000000, K2_PCI64_BAR + BARPS); /* Base@0x00000000 */ - __raw_writel(0x00000000, K2_PCI64_BAR + BARPP); /* Base@0x00000000 */ - - /* Setup PCI32 hose */ - hose_a = pcibios_alloc_controller(); - if (!hose_a) - return; - - hose_a->first_busno = 0; - hose_a->last_busno = 0xff; - hose_a->pci_mem_offset = K2_PCI32_MEM_BASE; - - pci_init_resource(&hose_a->io_resource, - K2_PCI32_LOWER_IO, - K2_PCI32_UPPER_IO, - IORESOURCE_IO, "PCI32 host bridge"); - - pci_init_resource(&hose_a->mem_resources[0], - K2_PCI32_LOWER_MEM + K2_PCI32_MEM_BASE, - K2_PCI32_UPPER_MEM + K2_PCI32_MEM_BASE, - IORESOURCE_MEM, "PCI32 host bridge"); - - hose_a->io_space.start = K2_PCI32_LOWER_IO; - hose_a->io_space.end = K2_PCI32_UPPER_IO; - hose_a->mem_space.start = K2_PCI32_LOWER_MEM; - hose_a->mem_space.end = K2_PCI32_UPPER_MEM; - hose_a->io_base_virt = (void *)K2_ISA_IO_BASE; - - setup_indirect_pci(hose_a, K2_PCI32_CONFIG_ADDR, K2_PCI32_CONFIG_DATA); - - /* Initialize PCI32 bus registers */ - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(0, 0), - CPC710_BUS_NUMBER, hose_a->first_busno); - - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(0, 0), - CPC710_SUB_BUS_NUMBER, hose_a->last_busno); - - /* Enable PCI interrupt polling */ - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(8, 0), 0x45, 0x80); - - /* Route polled PCI interrupts */ - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(8, 0), 0x48, 0x58); - - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(8, 0), 0x49, 0x07); - - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(8, 0), 0x4a, 0x31); - - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(8, 0), 0x4b, 0xb9); - - /* route secondary IDE channel interrupt to IRQ 15 */ - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(8, 0), 0x75, 0x0f); - - /* enable IDE controller IDSEL */ - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(8, 0), 0x58, 0x48); - - /* Enable IDE function */ - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(17, 0), 0x50, 0x03); - - /* Set M5229 IDE controller to native mode */ - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(17, 0), PCI_CLASS_PROG, 0xdf); - - hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno); - - /* Write out correct max subordinate bus number for hose A */ - early_write_config_byte(hose_a, - hose_a->first_busno, - PCI_DEVFN(0, 0), - CPC710_SUB_BUS_NUMBER, hose_a->last_busno); - - /* Only setup PCI64 hose if we are in the system slot */ - if (!(readb(K2_MISC_REG) & K2_SYS_SLOT_MASK)) { - /* Setup PCI64 hose */ - hose_b = pcibios_alloc_controller(); - if (!hose_b) - return; - - hose_b->first_busno = hose_a->last_busno + 1; - hose_b->last_busno = 0xff; - - /* Reminder: quit changing the following, it is correct. */ - hose_b->pci_mem_offset = K2_PCI32_MEM_BASE; - - pci_init_resource(&hose_b->io_resource, - K2_PCI64_LOWER_IO, - K2_PCI64_UPPER_IO, - IORESOURCE_IO, "PCI64 host bridge"); - - pci_init_resource(&hose_b->mem_resources[0], - K2_PCI64_LOWER_MEM + K2_PCI32_MEM_BASE, - K2_PCI64_UPPER_MEM + K2_PCI32_MEM_BASE, - IORESOURCE_MEM, "PCI64 host bridge"); - - hose_b->io_space.start = K2_PCI64_LOWER_IO; - hose_b->io_space.end = K2_PCI64_UPPER_IO; - hose_b->mem_space.start = K2_PCI64_LOWER_MEM; - hose_b->mem_space.end = K2_PCI64_UPPER_MEM; - hose_b->io_base_virt = (void *)K2_ISA_IO_BASE; - - setup_indirect_pci(hose_b, - K2_PCI64_CONFIG_ADDR, K2_PCI64_CONFIG_DATA); - - /* Initialize PCI64 bus registers */ - early_write_config_byte(hose_b, - 0, - PCI_DEVFN(0, 0), - CPC710_SUB_BUS_NUMBER, 0xff); - - early_write_config_byte(hose_b, - 0, - PCI_DEVFN(0, 0), - CPC710_BUS_NUMBER, hose_b->first_busno); - - hose_b->last_busno = pciauto_bus_scan(hose_b, - hose_b->first_busno); - - /* Write out correct max subordinate bus number for hose B */ - early_write_config_byte(hose_b, - hose_b->first_busno, - PCI_DEVFN(0, 0), - CPC710_SUB_BUS_NUMBER, - hose_b->last_busno); - - /* Configure PCI64 PSBAR */ - early_write_config_dword(hose_b, - hose_b->first_busno, - PCI_DEVFN(0, 0), - PCI_BASE_ADDRESS_0, - K2_PCI64_SYS_MEM_BASE); - } - - /* Configure i8259 level/edge settings */ - outb(0x62, 0x4d0); - outb(0xde, 0x4d1); - -#ifdef CONFIG_CPC710_DATA_GATHERING - { - unsigned int tmp; - tmp = __raw_readl(ABCNTL); - /* Enable data gathering on both PCI interfaces */ - __raw_writel(tmp | 0x05000000, ABCNTL); - } -#endif - - ppc_md.pcibios_fixup = k2_pcibios_fixup; - ppc_md.pcibios_fixup_resources = k2_pcibios_fixup_resources; - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = k2_map_irq; -} - -static int k2_get_bus_speed(void) -{ - int bus_speed; - unsigned char board_id; - - board_id = *(unsigned char *)K2_BOARD_ID_REG; - - switch (K2_BUS_SPD(board_id)) { - - case 0: - default: - bus_speed = 100000000; - break; - - case 1: - bus_speed = 83333333; - break; - - case 2: - bus_speed = 75000000; - break; - - case 3: - bus_speed = 66666666; - break; - } - return bus_speed; -} - -static int k2_get_cpu_speed(void) -{ - unsigned long hid1; - int cpu_speed; - - hid1 = mfspr(SPRN_HID1) >> 28; - - if ((mfspr(SPRN_PVR) >> 16) == 8) - hid1 = cpu_7xx[hid1]; - else - hid1 = cpu_6xx[hid1]; - - cpu_speed = k2_get_bus_speed() * hid1 / 2; - return cpu_speed; -} - -static void __init k2_calibrate_decr(void) -{ - int freq, divisor = 4; - - /* determine processor bus speed */ - freq = k2_get_bus_speed(); - tb_ticks_per_jiffy = freq / HZ / divisor; - tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000); -} - -static int k2_show_cpuinfo(struct seq_file *m) -{ - unsigned char k2_geo_bits, k2_system_slot; - - seq_printf(m, "vendor\t\t: SBS\n"); - seq_printf(m, "machine\t\t: K2\n"); - seq_printf(m, "cpu speed\t: %dMhz\n", k2_get_cpu_speed() / 1000000); - seq_printf(m, "bus speed\t: %dMhz\n", k2_get_bus_speed() / 1000000); - seq_printf(m, "memory type\t: SDRAM\n"); - - k2_geo_bits = readb(K2_MSIZ_GEO_REG) & K2_GEO_ADR_MASK; - k2_system_slot = !(readb(K2_MISC_REG) & K2_SYS_SLOT_MASK); - seq_printf(m, "backplane\t: %s slot board", - k2_system_slot ? "System" : "Non system"); - seq_printf(m, "with geographical address %x\n", k2_geo_bits); - - return 0; -} - -TODC_ALLOC(); - -static void __init k2_setup_arch(void) -{ - unsigned int cpu; - - /* Setup TODC access */ - TODC_INIT(TODC_TYPE_MK48T37, 0, 0, - ioremap(K2_RTC_BASE_ADDRESS, K2_RTC_SIZE), 8); - - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000 / HZ; - - /* make FLASH transactions higher priority than PCI to avoid deadlock */ - __raw_writel(__raw_readl(SIOC1) | 0x80000000, SIOC1); - - /* Set hardware to access FLASH page 2 */ - __raw_writel(1 << 29, GPOUT); - - /* Setup PCI host bridges */ - k2_setup_hoses(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_HDC1; -#endif - - /* Identify the system */ - printk(KERN_INFO "System Identification: SBS K2 - PowerPC 750 @ " - "%d Mhz\n", k2_get_cpu_speed() / 1000000); - printk(KERN_INFO "Port by MontaVista Software, Inc. " - "(source@mvista.com)\n"); - - /* Identify the CPU manufacturer */ - cpu = PVR_REV(mfspr(SPRN_PVR)); - printk(KERN_INFO "CPU manufacturer: %s [rev=%04x]\n", - (cpu & (1 << 15)) ? "IBM" : "Motorola", cpu); -} - -static void k2_restart(char *cmd) -{ - local_irq_disable(); - - /* Flip FLASH back to page 1 to access firmware image */ - __raw_writel(0, GPOUT); - - /* SRR0 has system reset vector, SRR1 has default MSR value */ - /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ - mtspr(SPRN_SRR0, 0xfff00100); - mtspr(SPRN_SRR1, 0); - __asm__ __volatile__("rfi\n\t"); - - /* not reached */ - for (;;) ; -} - -static void k2_power_off(void) -{ - for (;;) ; -} - -static void k2_halt(void) -{ - k2_restart(NULL); -} - -/* - * Set BAT 3 to map PCI32 I/O space. - */ -static __inline__ void k2_set_bat(void) -{ - /* wait for all outstanding memory accesses to complete */ - mb(); - - /* setup DBATs */ - mtspr(SPRN_DBAT2U, 0x80001ffe); - mtspr(SPRN_DBAT2L, 0x8000002a); - mtspr(SPRN_DBAT3U, 0xf0001ffe); - mtspr(SPRN_DBAT3L, 0xf000002a); - - /* wait for updates */ - mb(); -} - -static unsigned long __init k2_find_end_of_memory(void) -{ - unsigned long total; - unsigned char msize = 7; /* Default to 128MB */ - - msize = K2_MEM_SIZE(readb(K2_MSIZ_GEO_REG)); - - switch (msize) { - case 2: - /* - * This will break without a lowered - * KERNELBASE or CONFIG_HIGHMEM on. - * It seems non 1GB builds exist yet, - * though. - */ - total = K2_MEM_SIZE_1GB; - break; - case 3: - case 4: - total = K2_MEM_SIZE_512MB; - break; - case 5: - case 6: - total = K2_MEM_SIZE_256MB; - break; - case 7: - total = K2_MEM_SIZE_128MB; - break; - default: - printk - ("K2: Invalid memory size detected, defaulting to 128MB\n"); - total = K2_MEM_SIZE_128MB; - break; - } - return total; -} - -static void __init k2_map_io(void) -{ - io_block_mapping(K2_PCI32_IO_BASE, - K2_PCI32_IO_BASE, 0x00200000, _PAGE_IO); - io_block_mapping(0xff000000, 0xff000000, 0x01000000, _PAGE_IO); -} - -static void __init k2_init_irq(void) -{ - int i; - - for (i = 0; i < 16; i++) - irq_desc[i].handler = &i8259_pic; - - i8259_init(0); -} - -void __init platform_init(unsigned long r3, unsigned long r4, - unsigned long r5, unsigned long r6, unsigned long r7) -{ - parse_bootinfo((struct bi_record *)(r3 + KERNELBASE)); - - k2_set_bat(); - - isa_io_base = K2_ISA_IO_BASE; - isa_mem_base = K2_ISA_MEM_BASE; - pci_dram_offset = K2_PCI32_SYS_MEM_BASE; - - ppc_md.setup_arch = k2_setup_arch; - ppc_md.show_cpuinfo = k2_show_cpuinfo; - ppc_md.init_IRQ = k2_init_irq; - ppc_md.get_irq = i8259_irq; - - ppc_md.find_end_of_memory = k2_find_end_of_memory; - ppc_md.setup_io_mappings = k2_map_io; - - ppc_md.restart = k2_restart; - ppc_md.power_off = k2_power_off; - ppc_md.halt = k2_halt; - - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.calibrate_decr = k2_calibrate_decr; - - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; - -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = gen550_progress; -#endif -} diff --git a/arch/ppc/platforms/k2.h b/arch/ppc/platforms/k2.h deleted file mode 100644 index 78326ab..0000000 --- a/arch/ppc/platforms/k2.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * arch/ppc/platforms/k2.h - * - * Definitions for SBS K2 board support - * - * Author: Matt Porter <mporter@mvista.com> - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __PPC_PLATFORMS_K2_H -#define __PPC_PLATFORMS_K2_H - -/* - * SBS K2 definitions - */ - -#define K2_PCI64_BAR 0xff400000 -#define K2_PCI32_BAR 0xff500000 - -#define K2_PCI64_CONFIG_ADDR (K2_PCI64_BAR + 0x000f8000) -#define K2_PCI64_CONFIG_DATA (K2_PCI64_BAR + 0x000f8010) - -#define K2_PCI32_CONFIG_ADDR (K2_PCI32_BAR + 0x000f8000) -#define K2_PCI32_CONFIG_DATA (K2_PCI32_BAR + 0x000f8010) - -#define K2_PCI64_MEM_BASE 0xd0000000 -#define K2_PCI64_IO_BASE 0x80100000 - -#define K2_PCI32_MEM_BASE 0xc0000000 -#define K2_PCI32_IO_BASE 0x80000000 - -#define K2_PCI32_SYS_MEM_BASE 0x80000000 -#define K2_PCI64_SYS_MEM_BASE K2_PCI32_SYS_MEM_BASE - -#define K2_PCI32_LOWER_MEM 0x00000000 -#define K2_PCI32_UPPER_MEM 0x0fffffff -#define K2_PCI32_LOWER_IO 0x00000000 -#define K2_PCI32_UPPER_IO 0x000fffff - -#define K2_PCI64_LOWER_MEM 0x10000000 -#define K2_PCI64_UPPER_MEM 0x1fffffff -#define K2_PCI64_LOWER_IO 0x00100000 -#define K2_PCI64_UPPER_IO 0x001fffff - -#define K2_ISA_IO_BASE K2_PCI32_IO_BASE -#define K2_ISA_MEM_BASE K2_PCI32_MEM_BASE - -#define K2_BOARD_ID_REG (K2_ISA_IO_BASE + 0x800) -#define K2_MISC_REG (K2_ISA_IO_BASE + 0x804) -#define K2_MSIZ_GEO_REG (K2_ISA_IO_BASE + 0x808) -#define K2_HOT_SWAP_REG (K2_ISA_IO_BASE + 0x80c) -#define K2_PLD2_REG (K2_ISA_IO_BASE + 0x80e) -#define K2_PLD3_REG (K2_ISA_IO_BASE + 0x80f) - -#define K2_BUS_SPD(board_id) (board_id >> 2) & 3 - -#define K2_RTC_BASE_OFFSET 0x90000 -#define K2_RTC_BASE_ADDRESS (K2_PCI32_MEM_BASE + K2_RTC_BASE_OFFSET) -#define K2_RTC_SIZE 0x8000 - -#define K2_MEM_SIZE_MASK 0xe0 -#define K2_MEM_SIZE(size_reg) (size_reg & K2_MEM_SIZE_MASK) >> 5 -#define K2_MEM_SIZE_1GB 0x40000000 -#define K2_MEM_SIZE_512MB 0x20000000 -#define K2_MEM_SIZE_256MB 0x10000000 -#define K2_MEM_SIZE_128MB 0x08000000 - -#define K2_L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ -#define K2_L2CACHE_512KB 0x00 /* 512KB */ -#define K2_L2CACHE_256KB 0x01 /* 256KB */ -#define K2_L2CACHE_1MB 0x02 /* 1MB */ -#define K2_L2CACHE_NONE 0x03 /* None */ - -#define K2_GEO_ADR_MASK 0x1f - -#define K2_SYS_SLOT_MASK 0x08 - -#endif /* __PPC_PLATFORMS_K2_H */ diff --git a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c index 169dbf6..2b53afa 100644 --- a/arch/ppc/platforms/katana.c +++ b/arch/ppc/platforms/katana.c @@ -33,6 +33,7 @@ #include <linux/bootimg.h> #endif #include <asm/io.h> +#include <asm/unistd.h> #include <asm/page.h> #include <asm/time.h> #include <asm/smp.h> @@ -42,15 +43,14 @@ #include <asm/mv64x60.h> #include <platforms/katana.h> -static struct mv64x60_handle bh; -static katana_id_t katana_id; -static void __iomem *cpld_base; -static void __iomem *sram_base; - -static u32 katana_flash_size_0; -static u32 katana_flash_size_1; - -static u32 katana_bus_frequency; +static struct mv64x60_handle bh; +static katana_id_t katana_id; +static void __iomem *cpld_base; +static void __iomem *sram_base; +static u32 katana_flash_size_0; +static u32 katana_flash_size_1; +static u32 katana_bus_frequency; +static struct pci_controller katana_hose_a; unsigned char __res[sizeof(bd_t)]; @@ -71,8 +71,12 @@ katana_irq_lookup_750i(unsigned char idsel, unsigned char pin) KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i }, /* IDSEL 6 (T8110) */ {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 }, + /* IDSEL 7 (unused) */ + {0, 0, 0, 0 }, + /* IDSEL 8 (Intel 82544) (752i only but doesn't harm 750i) */ + {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 }, }; - const long min_idsel = 4, max_idsel = 6, irqs_per_slot = 4; + const long min_idsel = 4, max_idsel = 8, irqs_per_slot = 4; return PCI_IRQ_TABLE_LOOKUP; } @@ -148,7 +152,7 @@ katana_get_proc_num(void) save_exclude = mv64x60_pci_exclude_bridge; mv64x60_pci_exclude_bridge = 0; - early_read_config_word(bh.hose_a, 0, + early_read_config_word(bh.hose_b, 0, PCI_DEVFN(0,0), PCI_DEVICE_ID, &val); mv64x60_pci_exclude_bridge = save_exclude; @@ -191,7 +195,8 @@ katana_setup_bridge(void) struct mv64x60_setup_info si; void __iomem *vaddr; int i; - u16 val; + u32 v; + u16 val, type; u8 save_exclude; /* @@ -222,6 +227,20 @@ katana_setup_bridge(void) PCI_DEVICE_ID, val); } + /* + * While we're in here, set the hotswap register correctly. + * Turn off blue LED; mask ENUM#, clear insertion & extraction bits. + */ + early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0), + MV64360_PCICFG_CPCI_HOTSWAP, &v); + v &= ~(1<<19); + v |= ((1<<17) | (1<<22) | (1<<23)); + early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0), + MV64360_PCICFG_CPCI_HOTSWAP, v); + + /* While we're at it, grab the bridge type for later */ + early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type); + mv64x60_pci_exclude_bridge = save_exclude; iounmap(vaddr); @@ -251,21 +270,23 @@ katana_setup_bridge(void) si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; si.pci_1.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_NONE | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; + MV64360_PCI_ACC_CNTL_SNOOP_NONE | + MV64360_PCI_ACC_CNTL_SWAP_NONE | + MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | + MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; #else si.cpu_prot_options[i] = 0; - si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */ - si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */ - si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */ + si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; + si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; + si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; si.pci_1.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_WB | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES; + MV64360_PCI_ACC_CNTL_SNOOP_WB | + MV64360_PCI_ACC_CNTL_SWAP_NONE | + MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | + ((type == PCI_DEVICE_ID_MARVELL_MV64360) ? + MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES : + MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES); #endif } @@ -281,12 +302,26 @@ katana_setup_bridge(void) mv64x60_set_bus(&bh, 1, 0); bh.hose_b->first_busno = 0; bh.hose_b->last_busno = 0xff; + + /* + * Need to access hotswap reg which is in the pci config area of the + * bridge's hose 0. Note that pcibios_alloc_controller() can't be used + * to alloc hose_a b/c that would make hose 0 known to the generic + * pci code which we don't want. + */ + bh.hose_a = &katana_hose_a; + setup_indirect_pci_nomap(bh.hose_a, + bh.v_base + MV64x60_PCI0_CONFIG_ADDR, + bh.v_base + MV64x60_PCI0_CONFIG_DATA); } /* Bridge & platform setup routines */ void __init katana_intr_setup(void) { + if (bh.type == MV64x60_TYPE_MV64460) /* As per instns from Marvell */ + mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, 1 << 15); + /* MPP 8, 9, and 10 */ mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff); @@ -309,9 +344,16 @@ katana_intr_setup(void) /* Config GPP intr ctlr to respond to level trigger */ mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10)); - /* Erranum FEr PCI-#8 */ - mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9)); - mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9)); + if (bh.type == MV64x60_TYPE_MV64360) { + /* Erratum FEr PCI-#9 */ + mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, + (1<<4) | (1<<5) | (1<<6) | (1<<7)); + mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, (1<<8) | (1<<9)); + } else { + mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<6) | (1<<7)); + mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, + (1<<4) | (1<<5) | (1<<8) | (1<<9)); + } /* * Dismiss and then enable interrupt on GPP interrupt cause @@ -473,17 +515,46 @@ katana_setup_arch(void) ppc_md.progress("katana_setup_arch: exit", 0); } +void +katana_fixup_resources(struct pci_dev *dev) +{ + u16 v16; + + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, L1_CACHE_LINE_SIZE>>2); + + pci_read_config_word(dev, PCI_COMMAND, &v16); + v16 |= PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK; + pci_write_config_word(dev, PCI_COMMAND, v16); +} + +static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */ + 0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/ + 16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/ +}; + +static int +katana_get_cpu_freq(void) +{ + unsigned long pll_cfg; + + pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27; + return katana_bus_frequency * cpu_750xx[pll_cfg]/2; +} + /* Platform device data fixup routines. */ #if defined(CONFIG_SERIAL_MPSC) static void __init katana_fixup_mpsc_pdata(struct platform_device *pdev) { - struct mpsc_pdata *pdata; + struct mpsc_pdata *pdata = (struct mpsc_pdata *)pdev->dev.platform_data; + bd_t *bdp = (bd_t *)__res; - pdata = (struct mpsc_pdata *)pdev->dev.platform_data; + if (bdp->bi_baudrate) + pdata->default_baud = bdp->bi_baudrate; + else + pdata->default_baud = KATANA_DEFAULT_BAUD; pdata->max_idle = 40; - pdata->default_baud = KATANA_DEFAULT_BAUD; pdata->brg_clk_src = KATANA_MPSC_CLK_SRC; /* * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts, @@ -513,6 +584,18 @@ katana_fixup_eth_pdata(struct platform_device *pdev) } #endif +#if defined(CONFIG_SYSFS) +static void __init +katana_fixup_mv64xxx_pdata(struct platform_device *pdev) +{ + struct mv64xxx_pdata *pdata = (struct mv64xxx_pdata *) + pdev->dev.platform_data; + + /* Katana supports the mv64xxx hotswap register */ + pdata->hs_reg_valid = 1; +} +#endif + static int __init katana_platform_notify(struct device *dev) { @@ -529,6 +612,9 @@ katana_platform_notify(struct device *dev) { MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata }, { MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata }, #endif +#if defined(CONFIG_SYSFS) + { MV64XXX_DEV_NAME ".0", katana_fixup_mv64xxx_pdata }, +#endif }; struct platform_device *pdev; int i; @@ -536,8 +622,7 @@ katana_platform_notify(struct device *dev) if (dev && dev->bus_id) for (i=0; i<ARRAY_SIZE(dev_map); i++) if (!strncmp(dev->bus_id, dev_map[i].bus_id, - BUS_ID_SIZE)) { - + BUS_ID_SIZE)) { pdev = container_of(dev, struct platform_device, dev); dev_map[i].rtn(pdev); @@ -578,8 +663,7 @@ katana_setup_mtd(void) ptbl_entries = (size >= (64*MB)) ? 6 : 4; if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition), - GFP_KERNEL)) == NULL) { - + GFP_KERNEL)) == NULL) { printk(KERN_WARNING "Can't alloc MTD partition table\n"); return -ENOMEM; } @@ -611,7 +695,6 @@ katana_setup_mtd(void) physmap_set_partitions(ptbl, ptbl_entries); return 0; } - arch_initcall(katana_setup_mtd); #endif @@ -632,7 +715,22 @@ katana_halt(void) { u8 v; - if (katana_id == KATANA_ID_752I) { + /* Turn on blue LED to indicate its okay to remove */ + if (katana_id == KATANA_ID_750I) { + u32 v; + u8 save_exclude; + + /* Set LOO bit in cPCI HotSwap reg of hose 0 to turn on LED. */ + save_exclude = mv64x60_pci_exclude_bridge; + mv64x60_pci_exclude_bridge = 0; + early_read_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0), + MV64360_PCICFG_CPCI_HOTSWAP, &v); + v &= 0xff; + v |= (1 << 19); + early_write_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0), + MV64360_PCICFG_CPCI_HOTSWAP, v); + mv64x60_pci_exclude_bridge = save_exclude; + } else if (katana_id == KATANA_ID_752I) { v = in_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF); v |= HSL_PLD_HOT_SWAP_LED_BIT; out_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF, v); @@ -652,37 +750,65 @@ katana_power_off(void) static int katana_show_cpuinfo(struct seq_file *m) { + char *s; + + seq_printf(m, "cpu freq\t: %dMHz\n", + (katana_get_cpu_freq() + 500000) / 1000000); + seq_printf(m, "bus freq\t: %ldMHz\n", + ((long)katana_bus_frequency + 500000) / 1000000); seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n"); seq_printf(m, "board\t\t: "); - switch (katana_id) { case KATANA_ID_3750: - seq_printf(m, "Katana 3750\n"); + seq_printf(m, "Katana 3750"); break; case KATANA_ID_750I: - seq_printf(m, "Katana 750i\n"); + seq_printf(m, "Katana 750i"); break; case KATANA_ID_752I: - seq_printf(m, "Katana 752i\n"); + seq_printf(m, "Katana 752i"); break; default: - seq_printf(m, "Unknown\n"); + seq_printf(m, "Unknown"); break; } - - seq_printf(m, "product ID\t: 0x%x\n", + seq_printf(m, " (product id: 0x%x)\n", in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)); + + seq_printf(m, "pci mode\t: %sMonarch\n", + katana_is_monarch()? "" : "Non-"); seq_printf(m, "hardware rev\t: 0x%x\n", in_8(cpld_base+KATANA_CPLD_HARDWARE_VER)); - seq_printf(m, "PLD rev\t\t: 0x%x\n", + seq_printf(m, "pld rev\t\t: 0x%x\n", in_8(cpld_base + KATANA_CPLD_PLD_VER)); - seq_printf(m, "PLB freq\t: %ldMhz\n", - (long)katana_bus_frequency / 1000000); - seq_printf(m, "PCI\t\t: %sMonarch\n", katana_is_monarch()? "" : "Non-"); + + switch(bh.type) { + case MV64x60_TYPE_GT64260A: + s = "gt64260a"; + break; + case MV64x60_TYPE_GT64260B: + s = "gt64260b"; + break; + case MV64x60_TYPE_MV64360: + s = "mv64360"; + break; + case MV64x60_TYPE_MV64460: + s = "mv64460"; + break; + default: + s = "Unknown"; + } + seq_printf(m, "bridge type\t: %s\n", s); + seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev); +#if defined(CONFIG_NOT_COHERENT_CACHE) + seq_printf(m, "coherency\t: %s\n", "off"); +#else + seq_printf(m, "coherency\t: %s\n", "on"); +#endif return 0; } @@ -701,11 +827,20 @@ katana_calibrate_decr(void) tb_to_us = mulhwu_scale_factor(freq, 1000000); } +/* + * The katana supports both uImage and zImage. If uImage, get the mem size + * from the bd info. If zImage, the bootwrapper adds a BI_MEMSIZE entry in + * the bi_rec data which is sucked out and put into boot_mem_size by + * parse_bootinfo(). MMU_init() will then use the boot_mem_size for the mem + * size and not call this routine. The only way this will fail is when a uImage + * is used but the fw doesn't pass in a valid bi_memsize. This should never + * happen, though. + */ unsigned long __init katana_find_end_of_memory(void) { - return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, - MV64x60_TYPE_MV64360); + bd_t *bdp = (bd_t *)__res; + return bdp->bi_memsize; } #if defined(CONFIG_I2C_MV64XXX) && defined(CONFIG_SENSORS_M41T00) @@ -729,15 +864,6 @@ katana_rtc_hookup(void) late_initcall(katana_rtc_hookup); #endif -static inline void -katana_set_bat(void) -{ - mb(); - mtspr(SPRN_DBAT2U, 0xf0001ffe); - mtspr(SPRN_DBAT2L, 0xf000002a); - mb(); -} - #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) static void __init katana_map_io(void) @@ -763,15 +889,24 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, */ if (r3 && r6) { /* copy board info structure */ - memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) ); + memcpy((void *)__res, (void *)(r3+KERNELBASE), sizeof(bd_t)); /* copy command line */ *(char *)(r7+KERNELBASE) = 0; strcpy(cmd_line, (char *)(r6+KERNELBASE)); } +#ifdef CONFIG_BLK_DEV_INITRD + /* take care of initrd if we have one */ + if (r4) { + initrd_start = r4 + KERNELBASE; + initrd_end = r5 + KERNELBASE; + } +#endif /* CONFIG_BLK_DEV_INITRD */ + isa_mem_base = 0; ppc_md.setup_arch = katana_setup_arch; + ppc_md.pcibios_fixup_resources = katana_fixup_resources; ppc_md.show_cpuinfo = katana_show_cpuinfo; ppc_md.init_IRQ = mv64360_init_irq; ppc_md.get_irq = mv64360_get_irq; @@ -790,6 +925,4 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) platform_notify = katana_platform_notify; #endif - - katana_set_bat(); /* Need for katana_find_end_of_memory and progress */ } diff --git a/arch/ppc/platforms/katana.h b/arch/ppc/platforms/katana.h index b82ed81..597257e 100644 --- a/arch/ppc/platforms/katana.h +++ b/arch/ppc/platforms/katana.h @@ -56,14 +56,14 @@ #define KATANA_PCI1_IO_SIZE 0x04000000 /* 64 MB */ /* Board-specific IRQ info */ -#define KATANA_PCI_INTA_IRQ_3750 64+8 -#define KATANA_PCI_INTB_IRQ_3750 64+9 -#define KATANA_PCI_INTC_IRQ_3750 64+10 - -#define KATANA_PCI_INTA_IRQ_750i 64+8 -#define KATANA_PCI_INTB_IRQ_750i 64+9 -#define KATANA_PCI_INTC_IRQ_750i 64+10 -#define KATANA_PCI_INTD_IRQ_750i 64+14 +#define KATANA_PCI_INTA_IRQ_3750 (64+8) +#define KATANA_PCI_INTB_IRQ_3750 (64+9) +#define KATANA_PCI_INTC_IRQ_3750 (64+10) + +#define KATANA_PCI_INTA_IRQ_750i (64+8) +#define KATANA_PCI_INTB_IRQ_750i (64+9) +#define KATANA_PCI_INTC_IRQ_750i (64+10) +#define KATANA_PCI_INTD_IRQ_750i (64+14) #define KATANA_CPLD_RST_EVENT 0x00000000 #define KATANA_CPLD_RST_CMD 0x00001000 diff --git a/arch/ppc/platforms/mcpn765.c b/arch/ppc/platforms/mcpn765.c deleted file mode 100644 index e88d294..0000000 --- a/arch/ppc/platforms/mcpn765.c +++ /dev/null @@ -1,527 +0,0 @@ -/* - * arch/ppc/platforms/mcpn765.c - * - * Board setup routines for the Motorola MCG MCPN765 cPCI Board. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * Modified by Randy Vinson (rvinson@mvista.com) - * - * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * This file adds support for the Motorola MCG MCPN765. - */ -#include <linux/config.h> -#include <linux/stddef.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/reboot.h> -#include <linux/pci.h> -#include <linux/kdev_t.h> -#include <linux/major.h> -#include <linux/initrd.h> -#include <linux/console.h> -#include <linux/delay.h> -#include <linux/irq.h> -#include <linux/seq_file.h> -#include <linux/root_dev.h> -#include <linux/serial.h> -#include <linux/tty.h> /* for linux/serial_core.h */ -#include <linux/serial_core.h> -#include <linux/slab.h> - -#include <asm/system.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <asm/time.h> -#include <asm/dma.h> -#include <asm/byteorder.h> -#include <asm/io.h> -#include <asm/machdep.h> -#include <asm/prom.h> -#include <asm/smp.h> -#include <asm/open_pic.h> -#include <asm/i8259.h> -#include <asm/todc.h> -#include <asm/pci-bridge.h> -#include <asm/irq.h> -#include <asm/uaccess.h> -#include <asm/bootinfo.h> -#include <asm/hawk.h> -#include <asm/kgdb.h> - -#include "mcpn765.h" - -static u_char mcpn765_openpic_initsenses[] __initdata = { - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE),/* 16: i8259 cascade */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 17: COM1,2,3,4 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 18: Enet 1 (front) */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 19: HAWK WDT XXXX */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 20: 21554 bridge */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 21: cPCI INTA# */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 22: cPCI INTB# */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 23: cPCI INTC# */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 24: cPCI INTD# */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 25: PMC1 INTA#,PMC2 INTB#*/ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 26: PMC1 INTB#,PMC2 INTC#*/ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 27: PMC1 INTC#,PMC2 INTD#*/ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 28: PMC1 INTD#,PMC2 INTA#*/ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 29: Enet 2 (J3) */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 30: Abort Switch */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 31: RTC Alarm */ -}; - -extern void mcpn765_set_VIA_IDE_native(void); - -extern u_int openpic_irq(void); -extern char cmd_line[]; - -extern void gen550_progress(char *, unsigned short); -extern void gen550_init(int, struct uart_port *); - -int use_of_interrupt_tree = 0; - -static void mcpn765_halt(void); - -TODC_ALLOC(); - -/* - * Motorola MCG MCPN765 interrupt routing. - */ -static inline int -mcpn765_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 14, 0, 0, 0 }, /* IDSEL 11 - have to manually set */ - { 0, 0, 0, 0 }, /* IDSEL 12 - unused */ - { 0, 0, 0, 0 }, /* IDSEL 13 - unused */ - { 18, 0, 0, 0 }, /* IDSEL 14 - Enet 0 */ - { 0, 0, 0, 0 }, /* IDSEL 15 - unused */ - { 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */ - { 28, 25, 26, 27 }, /* IDSEL 17 - PMC Slot 2 */ - { 0, 0, 0, 0 }, /* IDSEL 18 - PMC 2B Connector XXXX */ - { 29, 0, 0, 0 }, /* IDSEL 19 - Enet 1 */ - { 20, 0, 0, 0 }, /* IDSEL 20 - 21554 cPCI bridge */ - }; - - const long min_idsel = 11, max_idsel = 20, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -void __init -mcpn765_set_VIA_IDE_legacy(void) -{ - unsigned short vend, dev; - - early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend); - early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev); - - if ((vend == PCI_VENDOR_ID_VIA) && - (dev == PCI_DEVICE_ID_VIA_82C586_1)) { - - unsigned char temp; - - /* put back original "standard" port base addresses */ - early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), - PCI_BASE_ADDRESS_0, 0x1f1); - early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), - PCI_BASE_ADDRESS_1, 0x3f5); - early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), - PCI_BASE_ADDRESS_2, 0x171); - early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), - PCI_BASE_ADDRESS_3, 0x375); - early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), - PCI_BASE_ADDRESS_4, 0xcc01); - - /* put into legacy mode */ - early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG, - &temp); - temp &= ~0x05; - early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG, - temp); - } -} - -void -mcpn765_set_VIA_IDE_native(void) -{ - unsigned short vend, dev; - - early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend); - early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev); - - if ((vend == PCI_VENDOR_ID_VIA) && - (dev == PCI_DEVICE_ID_VIA_82C586_1)) { - - unsigned char temp; - - /* put into native mode */ - early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG, - &temp); - temp |= 0x05; - early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG, - temp); - } -} - -/* - * Initialize the VIA 82c586b. - */ -static void __init -mcpn765_setup_via_82c586b(void) -{ - struct pci_dev *dev; - u_char c; - - if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_82C586_0, - NULL)) == NULL) { - printk("No VIA ISA bridge found\n"); - mcpn765_halt(); - /* NOTREACHED */ - } - - /* - * If the firmware left the EISA 4d0/4d1 ports enabled, make sure - * IRQ 14 is set for edge. - */ - pci_read_config_byte(dev, 0x47, &c); - - if (c & (1<<5)) { - c = inb(0x4d1); - c &= ~(1<<6); - outb(c, 0x4d1); - } - - /* Disable PNP IRQ routing since we use the Hawk's MPIC */ - pci_write_config_dword(dev, 0x54, 0); - pci_write_config_byte(dev, 0x58, 0); - - pci_dev_put(dev); - if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_82C586_1, - NULL)) == NULL) { - printk("No VIA ISA bridge found\n"); - mcpn765_halt(); - /* NOTREACHED */ - } - - /* - * PPCBug doesn't set the enable bits for the IDE device. - * Turn them on now. - */ - pci_read_config_byte(dev, 0x40, &c); - c |= 0x03; - pci_write_config_byte(dev, 0x40, c); - pci_dev_put(dev); - - return; -} - -void __init -mcpn765_pcibios_fixup(void) -{ - /* Do MCPN765 board specific initialization. */ - mcpn765_setup_via_82c586b(); -} - -void __init -mcpn765_find_bridges(void) -{ - struct pci_controller *hose; - - hose = pcibios_alloc_controller(); - - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - hose->pci_mem_offset = MCPN765_PCI_PHY_MEM_OFFSET; - - pci_init_resource(&hose->io_resource, - MCPN765_PCI_IO_START, - MCPN765_PCI_IO_END, - IORESOURCE_IO, - "PCI host bridge"); - - pci_init_resource(&hose->mem_resources[0], - MCPN765_PCI_MEM_START, - MCPN765_PCI_MEM_END, - IORESOURCE_MEM, - "PCI host bridge"); - - hose->io_space.start = MCPN765_PCI_IO_START; - hose->io_space.end = MCPN765_PCI_IO_END; - hose->mem_space.start = MCPN765_PCI_MEM_START; - hose->mem_space.end = MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE; - - if (hawk_init(hose, - MCPN765_HAWK_PPC_REG_BASE, - MCPN765_PROC_PCI_MEM_START, - MCPN765_PROC_PCI_MEM_END - HAWK_MPIC_SIZE, - MCPN765_PROC_PCI_IO_START, - MCPN765_PROC_PCI_IO_END, - MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE + 1) != 0) { - printk("Could not initialize HAWK bridge\n"); - } - - /* VIA IDE BAR decoders are only 16-bits wide. PCI Auto Config - * will reassign the bars outside of 16-bit I/O space, which will - * "break" things. To prevent this, we'll set the IDE chip into - * legacy mode and seed the bars with their legacy addresses (in 16-bit - * I/O space). The Auto Config code will skip the IDE contoller in - * legacy mode, so our bar values will stick. - */ - mcpn765_set_VIA_IDE_legacy(); - - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - /* Now that we've got 16-bit addresses in the bars, we can switch the - * IDE controller back into native mode so we can do "modern" resource - * and interrupt management. - */ - mcpn765_set_VIA_IDE_native(); - - ppc_md.pcibios_fixup = mcpn765_pcibios_fixup; - ppc_md.pcibios_fixup_bus = NULL; - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = mcpn765_map_irq; - - return; -} -static void __init -mcpn765_setup_arch(void) -{ - struct pci_controller *hose; - - if ( ppc_md.progress ) - ppc_md.progress("mcpn765_setup_arch: enter", 0); - - loops_per_jiffy = 50000000 / HZ; - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - - if ( ppc_md.progress ) - ppc_md.progress("mcpn765_setup_arch: find_bridges", 0); - - /* Lookup PCI host bridges */ - mcpn765_find_bridges(); - - hose = pci_bus_to_hose(0); - isa_io_base = (ulong)hose->io_base_virt; - - TODC_INIT(TODC_TYPE_MK48T37, - (MCPN765_PHYS_NVRAM_AS0 - isa_io_base), - (MCPN765_PHYS_NVRAM_AS1 - isa_io_base), - (MCPN765_PHYS_NVRAM_DATA - isa_io_base), - 8); - - OpenPIC_InitSenses = mcpn765_openpic_initsenses; - OpenPIC_NumInitSenses = sizeof(mcpn765_openpic_initsenses); - - printk("Motorola MCG MCPN765 cPCI Non-System Board\n"); - printk("MCPN765 port (MontaVista Software, Inc. (source@mvista.com))\n"); - - if ( ppc_md.progress ) - ppc_md.progress("mcpn765_setup_arch: exit", 0); - - return; -} - -static void __init -mcpn765_init2(void) -{ - - request_region(0x00,0x20,"dma1"); - request_region(0x20,0x20,"pic1"); - request_region(0x40,0x20,"timer"); - request_region(0x80,0x10,"dma page reg"); - request_region(0xa0,0x20,"pic2"); - request_region(0xc0,0x20,"dma2"); - - return; -} - -/* - * Interrupt setup and service. - * Have MPIC on HAWK and cascaded 8259s on VIA 82586 cascaded to MPIC. - */ -static void __init -mcpn765_init_IRQ(void) -{ - int i; - - if ( ppc_md.progress ) - ppc_md.progress("init_irq: enter", 0); - - openpic_init(NUM_8259_INTERRUPTS); - openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade", - i8259_irq); - - for(i=0; i < NUM_8259_INTERRUPTS; i++) - irq_desc[i].handler = &i8259_pic; - - i8259_init(0); - - if ( ppc_md.progress ) - ppc_md.progress("init_irq: exit", 0); - - return; -} - -static u32 -mcpn765_irq_canonicalize(u32 irq) -{ - if (irq == 2) - return 9; - else - return irq; -} - -static unsigned long __init -mcpn765_find_end_of_memory(void) -{ - return hawk_get_mem_size(MCPN765_HAWK_SMC_BASE); -} - -static void __init -mcpn765_map_io(void) -{ - io_block_mapping(0xfe800000, 0xfe800000, 0x00800000, _PAGE_IO); -} - -static void -mcpn765_reset_board(void) -{ - local_irq_disable(); - - /* set VIA IDE controller into native mode */ - mcpn765_set_VIA_IDE_native(); - - /* Set exception prefix high - to the firmware */ - _nmask_and_or_msr(0, MSR_IP); - - out_8((u_char *)MCPN765_BOARD_MODRST_REG, 0x01); - - return; -} - -static void -mcpn765_restart(char *cmd) -{ - volatile ulong i = 10000000; - - mcpn765_reset_board(); - - while (i-- > 0); - panic("restart failed\n"); -} - -static void -mcpn765_power_off(void) -{ - mcpn765_halt(); - /* NOTREACHED */ -} - -static void -mcpn765_halt(void) -{ - local_irq_disable(); - while (1); - /* NOTREACHED */ -} - -static int -mcpn765_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: Motorola MCG\n"); - seq_printf(m, "machine\t\t: MCPN765\n"); - - return 0; -} - -/* - * Set BAT 3 to map 0xf0000000 to end of physical memory space. - */ -static __inline__ void -mcpn765_set_bat(void) -{ - mb(); - mtspr(SPRN_DBAT1U, 0xfe8000fe); - mtspr(SPRN_DBAT1L, 0xfe80002a); - mb(); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - /* Map in board regs, etc. */ - mcpn765_set_bat(); - - isa_mem_base = MCPN765_ISA_MEM_BASE; - pci_dram_offset = MCPN765_PCI_DRAM_OFFSET; - ISA_DMA_THRESHOLD = 0x00ffffff; - DMA_MODE_READ = 0x44; - DMA_MODE_WRITE = 0x48; - - ppc_md.setup_arch = mcpn765_setup_arch; - ppc_md.show_cpuinfo = mcpn765_show_cpuinfo; - ppc_md.irq_canonicalize = mcpn765_irq_canonicalize; - ppc_md.init_IRQ = mcpn765_init_IRQ; - ppc_md.get_irq = openpic_get_irq; - ppc_md.init = mcpn765_init2; - - ppc_md.restart = mcpn765_restart; - ppc_md.power_off = mcpn765_power_off; - ppc_md.halt = mcpn765_halt; - - ppc_md.find_end_of_memory = mcpn765_find_end_of_memory; - ppc_md.setup_io_mappings = mcpn765_map_io; - - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.calibrate_decr = todc_calibrate_decr; - - ppc_md.nvram_read_val = todc_m48txx_read_val; - ppc_md.nvram_write_val = todc_m48txx_write_val; - - ppc_md.heartbeat = NULL; - ppc_md.heartbeat_reset = 0; - ppc_md.heartbeat_count = 0; - -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = gen550_progress; -#endif -#ifdef CONFIG_KGDB - ppc_md.kgdb_map_scc = gen550_kgdb_map_scc; -#endif - - return; -} diff --git a/arch/ppc/platforms/mcpn765.h b/arch/ppc/platforms/mcpn765.h deleted file mode 100644 index 4d35eca..0000000 --- a/arch/ppc/platforms/mcpn765.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * arch/ppc/platforms/mcpn765.h - * - * Definitions for Motorola MCG MCPN765 cPCI Board. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * From Processor to PCI: - * PCI Mem Space: 0x80000000 - 0xc0000000 -> 0x80000000 - 0xc0000000 (1 GB) - * PCI I/O Space: 0xfd800000 - 0xfe000000 -> 0x00000000 - 0x00800000 (8 MB) - * Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area - * MPIC in PCI Mem Space: 0xfe800000 - 0xfe830000 (not all used by MPIC) - * - * From PCI to Processor: - * System Memory: 0x00000000 -> 0x00000000 - */ - -#ifndef __PPC_PLATFORMS_MCPN765_H -#define __PPC_PLATFORMS_MCPN765_H -#include <linux/config.h> - -/* PCI Memory space mapping info */ -#define MCPN765_PCI_MEM_SIZE 0x40000000U -#define MCPN765_PROC_PCI_MEM_START 0x80000000U -#define MCPN765_PROC_PCI_MEM_END (MCPN765_PROC_PCI_MEM_START + \ - MCPN765_PCI_MEM_SIZE - 1) -#define MCPN765_PCI_MEM_START 0x80000000U -#define MCPN765_PCI_MEM_END (MCPN765_PCI_MEM_START + \ - MCPN765_PCI_MEM_SIZE - 1) - -/* PCI I/O space mapping info */ -#define MCPN765_PCI_IO_SIZE 0x00800000U -#define MCPN765_PROC_PCI_IO_START 0xfd800000U -#define MCPN765_PROC_PCI_IO_END (MCPN765_PROC_PCI_IO_START + \ - MCPN765_PCI_IO_SIZE - 1) -#define MCPN765_PCI_IO_START 0x00000000U -#define MCPN765_PCI_IO_END (MCPN765_PCI_IO_START + \ - MCPN765_PCI_IO_SIZE - 1) - -/* System memory mapping info */ -#define MCPN765_PCI_DRAM_OFFSET 0x00000000U -#define MCPN765_PCI_PHY_MEM_OFFSET 0x00000000U - -#define MCPN765_ISA_MEM_BASE 0x00000000U -#define MCPN765_ISA_IO_BASE MCPN765_PROC_PCI_IO_START - -/* Define base addresses for important sets of registers */ -#define MCPN765_HAWK_MPIC_BASE 0xfe800000U -#define MCPN765_HAWK_SMC_BASE 0xfef80000U -#define MCPN765_HAWK_PPC_REG_BASE 0xfeff0000U - -/* Define MCPN765 board register addresses. */ -#define MCPN765_BOARD_STATUS_REG 0xfef88080U -#define MCPN765_BOARD_MODFAIL_REG 0xfef88090U -#define MCPN765_BOARD_MODRST_REG 0xfef880a0U -#define MCPN765_BOARD_TBEN_REG 0xfef880c0U -#define MCPN765_BOARD_GEOGRAPHICAL_REG 0xfef880e8U -#define MCPN765_BOARD_EXT_FEATURE_REG 0xfef880f0U -#define MCPN765_BOARD_LAST_RESET_REG 0xfef880f8U - -/* Defines for UART */ - -/* Define the UART base addresses */ -#define MCPN765_SERIAL_1 0xfef88000 -#define MCPN765_SERIAL_2 0xfef88200 -#define MCPN765_SERIAL_3 0xfef88400 -#define MCPN765_SERIAL_4 0xfef88600 - -#ifdef CONFIG_SERIAL_MANY_PORTS -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE 4 -#endif - -/* Rate for the 1.8432 Mhz clock for the onboard serial chip */ -#define BASE_BAUD ( 1843200 / 16 ) -#define UART_CLK 1843200 - -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST) -#endif - -/* All UART IRQ's are wire-OR'd to IRQ 17 */ -#define STD_SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, MCPN765_SERIAL_1, 17, STD_COM_FLAGS, /* ttyS0 */\ - iomem_base: (u8 *)MCPN765_SERIAL_1, \ - iomem_reg_shift: 4, \ - io_type: SERIAL_IO_MEM }, \ - { 0, BASE_BAUD, MCPN765_SERIAL_2, 17, STD_COM_FLAGS, /* ttyS1 */\ - iomem_base: (u8 *)MCPN765_SERIAL_2, \ - iomem_reg_shift: 4, \ - io_type: SERIAL_IO_MEM }, \ - { 0, BASE_BAUD, MCPN765_SERIAL_3, 17, STD_COM_FLAGS, /* ttyS2 */\ - iomem_base: (u8 *)MCPN765_SERIAL_3, \ - iomem_reg_shift: 4, \ - io_type: SERIAL_IO_MEM }, \ - { 0, BASE_BAUD, MCPN765_SERIAL_4, 17, STD_COM_FLAGS, /* ttyS3 */\ - iomem_base: (u8 *)MCPN765_SERIAL_4, \ - iomem_reg_shift: 4, \ - io_type: SERIAL_IO_MEM }, - -#define SERIAL_PORT_DFNS \ - STD_SERIAL_PORT_DFNS - -/* Define the NVRAM/RTC address strobe & data registers */ -#define MCPN765_PHYS_NVRAM_AS0 0xfef880c8U -#define MCPN765_PHYS_NVRAM_AS1 0xfef880d0U -#define MCPN765_PHYS_NVRAM_DATA 0xfef880d8U - -extern void mcpn765_find_bridges(void); - -#endif /* __PPC_PLATFORMS_MCPN765_H */ diff --git a/arch/ppc/platforms/pcore.c b/arch/ppc/platforms/pcore.c deleted file mode 100644 index d719163..0000000 --- a/arch/ppc/platforms/pcore.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * arch/ppc/platforms/pcore_setup.c - * - * Setup routines for Force PCORE boards - * - * Author: Matt Porter <mporter@mvista.com> - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include <linux/config.h> -#include <linux/stddef.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/reboot.h> -#include <linux/pci.h> -#include <linux/kdev_t.h> -#include <linux/types.h> -#include <linux/major.h> -#include <linux/initrd.h> -#include <linux/console.h> -#include <linux/irq.h> -#include <linux/seq_file.h> -#include <linux/root_dev.h> - -#include <asm/io.h> -#include <asm/machdep.h> -#include <asm/time.h> -#include <asm/i8259.h> -#include <asm/mpc10x.h> -#include <asm/todc.h> -#include <asm/bootinfo.h> -#include <asm/kgdb.h> - -#include "pcore.h" - -extern unsigned long loops_per_jiffy; - -static int board_type; - -static inline int __init -pcore_6750_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {9, 10, 11, 12}, /* IDSEL 24 - DEC 21554 */ - {10, 0, 0, 0}, /* IDSEL 25 - DEC 21143 */ - {11, 12, 9, 10}, /* IDSEL 26 - PMC I */ - {12, 9, 10, 11}, /* IDSEL 27 - PMC II */ - {0, 0, 0, 0}, /* IDSEL 28 - unused */ - {0, 0, 9, 0}, /* IDSEL 29 - unused */ - {0, 0, 0, 0}, /* IDSEL 30 - Winbond */ - }; - const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -}; - -static inline int __init -pcore_680_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {9, 10, 11, 12}, /* IDSEL 24 - Sentinel */ - {10, 0, 0, 0}, /* IDSEL 25 - i82559 #1 */ - {11, 12, 9, 10}, /* IDSEL 26 - PMC I */ - {12, 9, 10, 11}, /* IDSEL 27 - PMC II */ - {9, 0, 0, 0}, /* IDSEL 28 - i82559 #2 */ - {0, 0, 0, 0}, /* IDSEL 29 - unused */ - {0, 0, 0, 0}, /* IDSEL 30 - Winbond */ - }; - const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -}; - -void __init -pcore_pcibios_fixup(void) -{ - struct pci_dev *dev; - - if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND, - PCI_DEVICE_ID_WINBOND_83C553, - 0))) - { - /* Reroute interrupts both IDE channels to 15 */ - pci_write_config_byte(dev, - PCORE_WINBOND_IDE_INT, - 0xff); - - /* Route INTA-D to IRQ9-12, respectively */ - pci_write_config_word(dev, - PCORE_WINBOND_PCI_INT, - 0x9abc); - - /* - * Set up 8259 edge/level triggering - */ - outb(0x00, PCORE_WINBOND_PRI_EDG_LVL); - outb(0x1e, PCORE_WINBOND_SEC_EDG_LVL); - pci_dev_put(dev); - } -} - -int __init -pcore_find_bridges(void) -{ - struct pci_controller* hose; - int host_bridge, board_type; - - hose = pcibios_alloc_controller(); - if (!hose) - return 0; - - mpc10x_bridge_init(hose, - MPC10X_MEM_MAP_B, - MPC10X_MEM_MAP_B, - MPC10X_MAPB_EUMB_BASE); - - /* Determine board type */ - early_read_config_dword(hose, - 0, - PCI_DEVFN(0,0), - PCI_VENDOR_ID, - &host_bridge); - if (host_bridge == MPC10X_BRIDGE_106) - board_type = PCORE_TYPE_6750; - else /* MPC10X_BRIDGE_107 */ - board_type = PCORE_TYPE_680; - - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - ppc_md.pcibios_fixup = pcore_pcibios_fixup; - ppc_md.pci_swizzle = common_swizzle; - - if (board_type == PCORE_TYPE_6750) - ppc_md.pci_map_irq = pcore_6750_map_irq; - else /* PCORE_TYPE_680 */ - ppc_md.pci_map_irq = pcore_680_map_irq; - - return board_type; -} - -/* Dummy variable to satisfy mpc10x_common.o */ -void *OpenPIC_Addr; - -static int -pcore_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: Force Computers\n"); - - if (board_type == PCORE_TYPE_6750) - seq_printf(m, "machine\t\t: PowerCore 6750\n"); - else /* PCORE_TYPE_680 */ - seq_printf(m, "machine\t\t: PowerCore 680\n"); - - seq_printf(m, "L2\t\t: " ); - if (board_type == PCORE_TYPE_6750) - switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK) - { - case PCORE_DCCR_L2_0KB: - seq_printf(m, "nocache"); - break; - case PCORE_DCCR_L2_256KB: - seq_printf(m, "256KB"); - break; - case PCORE_DCCR_L2_1MB: - seq_printf(m, "1MB"); - break; - case PCORE_DCCR_L2_512KB: - seq_printf(m, "512KB"); - break; - default: - seq_printf(m, "error"); - break; - } - else /* PCORE_TYPE_680 */ - switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK) - { - case PCORE_DCCR_L2_2MB: - seq_printf(m, "2MB"); - break; - case PCORE_DCCR_L2_256KB: - seq_printf(m, "reserved"); - break; - case PCORE_DCCR_L2_1MB: - seq_printf(m, "1MB"); - break; - case PCORE_DCCR_L2_512KB: - seq_printf(m, "512KB"); - break; - default: - seq_printf(m, "error"); - break; - } - - seq_printf(m, "\n"); - - return 0; -} - -static void __init -pcore_setup_arch(void) -{ - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000/HZ; - - /* Lookup PCI host bridges */ - board_type = pcore_find_bridges(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - - printk(KERN_INFO "Force PowerCore "); - if (board_type == PCORE_TYPE_6750) - printk("6750\n"); - else - printk("680\n"); - printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n"); - _set_L2CR(L2CR_L2E | _get_L2CR()); - -} - -static void -pcore_restart(char *cmd) -{ - local_irq_disable(); - /* Hard reset */ - writeb(0x11, 0xfe000332); - while(1); -} - -static void -pcore_halt(void) -{ - local_irq_disable(); - /* Turn off user LEDs */ - writeb(0x00, 0xfe000300); - while (1); -} - -static void -pcore_power_off(void) -{ - pcore_halt(); -} - - -static void __init -pcore_init_IRQ(void) -{ - int i; - - for ( i = 0 ; i < 16 ; i++ ) - irq_desc[i].handler = &i8259_pic; - - i8259_init(0); -} - -/* - * Set BAT 3 to map 0xf0000000 to end of physical memory space. - */ -static __inline__ void -pcore_set_bat(void) -{ - mb(); - mtspr(SPRN_DBAT3U, 0xf0001ffe); - mtspr(SPRN_DBAT3L, 0xfe80002a); - mb(); - -} - -static unsigned long __init -pcore_find_end_of_memory(void) -{ - - return mpc10x_get_mem_size(MPC10X_MEM_MAP_B); -} - -static void __init -pcore_map_io(void) -{ - io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO); -} - -TODC_ALLOC(); - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - /* Cover I/O space with a BAT */ - /* yuck, better hope your ram size is a power of 2 -- paulus */ - pcore_set_bat(); - - isa_io_base = MPC10X_MAPB_ISA_IO_BASE; - isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE; - pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET; - - ppc_md.setup_arch = pcore_setup_arch; - ppc_md.show_cpuinfo = pcore_show_cpuinfo; - ppc_md.init_IRQ = pcore_init_IRQ; - ppc_md.get_irq = i8259_irq; - - ppc_md.find_end_of_memory = pcore_find_end_of_memory; - ppc_md.setup_io_mappings = pcore_map_io; - - ppc_md.restart = pcore_restart; - ppc_md.power_off = pcore_power_off; - ppc_md.halt = pcore_halt; - - TODC_INIT(TODC_TYPE_MK48T59, - PCORE_NVRAM_AS0, - PCORE_NVRAM_AS1, - PCORE_NVRAM_DATA, - 8); - - ppc_md.time_init = todc_time_init; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.calibrate_decr = todc_calibrate_decr; - - ppc_md.nvram_read_val = todc_m48txx_read_val; - ppc_md.nvram_write_val = todc_m48txx_write_val; - -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = gen550_progress; -#endif -#ifdef CONFIG_KGDB - ppc_md.kgdb_map_scc = gen550_kgdb_map_scc; -#endif -} diff --git a/arch/ppc/platforms/pcore.h b/arch/ppc/platforms/pcore.h deleted file mode 100644 index c6a26e7..0000000 --- a/arch/ppc/platforms/pcore.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * arch/ppc/platforms/pcore.h - * - * Definitions for Force PowerCore board support - * - * Author: Matt Porter <mporter@mvista.com> - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __PPC_PLATFORMS_PCORE_H -#define __PPC_PLATFORMS_PCORE_H - -#include <asm/mpc10x.h> - -#define PCORE_TYPE_6750 1 -#define PCORE_TYPE_680 2 - -#define PCORE_NVRAM_AS0 0x73 -#define PCORE_NVRAM_AS1 0x75 -#define PCORE_NVRAM_DATA 0x77 - -#define PCORE_DCCR_REG (MPC10X_MAPB_ISA_IO_BASE + 0x308) -#define PCORE_DCCR_L2_MASK 0xc0 -#define PCORE_DCCR_L2_0KB 0x00 -#define PCORE_DCCR_L2_256KB 0x40 -#define PCORE_DCCR_L2_512KB 0xc0 -#define PCORE_DCCR_L2_1MB 0x80 -#define PCORE_DCCR_L2_2MB 0x00 - -#define PCORE_WINBOND_IDE_INT 0x43 -#define PCORE_WINBOND_PCI_INT 0x44 -#define PCORE_WINBOND_PRI_EDG_LVL 0x4d0 -#define PCORE_WINBOND_SEC_EDG_LVL 0x4d1 - -#endif /* __PPC_PLATFORMS_PCORE_H */ diff --git a/arch/ppc/platforms/pmac_pic.c b/arch/ppc/platforms/pmac_pic.c index 9f92e1b..2ce0588 100644 --- a/arch/ppc/platforms/pmac_pic.c +++ b/arch/ppc/platforms/pmac_pic.c @@ -619,7 +619,7 @@ not_found: return viaint; } -static int pmacpic_suspend(struct sys_device *sysdev, u32 state) +static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state) { int viaint = pmacpic_find_viaint(); diff --git a/arch/ppc/platforms/spd8xx.h b/arch/ppc/platforms/spd8xx.h deleted file mode 100644 index ed48d14..0000000 --- a/arch/ppc/platforms/spd8xx.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Speech Design SPD8xxTS board specific definitions - * - * Copyright (c) 2000,2001 Wolfgang Denk (wd@denx.de) - */ - -#ifdef __KERNEL__ -#ifndef __ASM_SPD8XX_H__ -#define __ASM_SPD8XX_H__ - -#include <linux/config.h> - -#include <asm/ppcboot.h> - -#ifndef __ASSEMBLY__ -#define SPD_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */ -#define SPD_IMAP_SIZE (64 * 1024) /* size of mapped area */ - -#define IMAP_ADDR SPD_IMMR_BASE /* physical base address of IMMR area */ -#define IMAP_SIZE SPD_IMAP_SIZE /* mapped size of IMMR area */ - -#define PCMCIA_MEM_ADDR ((uint)0xFE100000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define IDE0_INTERRUPT 10 /* = IRQ5 */ -#define IDE1_INTERRUPT 12 /* = IRQ6 */ -#define CPM_INTERRUPT 13 /* = SIU_LEVEL6 (was: SIU_LEVEL2) */ - -/* override the default number of IDE hardware interfaces */ -#define MAX_HWIFS 2 - -/* - * Definitions for IDE0 Interface - */ -#define IDE0_BASE_OFFSET 0x0000 /* Offset in PCMCIA memory */ -#define IDE0_DATA_REG_OFFSET 0x0000 -#define IDE0_ERROR_REG_OFFSET 0x0081 -#define IDE0_NSECTOR_REG_OFFSET 0x0082 -#define IDE0_SECTOR_REG_OFFSET 0x0083 -#define IDE0_LCYL_REG_OFFSET 0x0084 -#define IDE0_HCYL_REG_OFFSET 0x0085 -#define IDE0_SELECT_REG_OFFSET 0x0086 -#define IDE0_STATUS_REG_OFFSET 0x0087 -#define IDE0_CONTROL_REG_OFFSET 0x0106 -#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */ - -/* - * Definitions for IDE1 Interface - */ -#define IDE1_BASE_OFFSET 0x0C00 /* Offset in PCMCIA memory */ -#define IDE1_DATA_REG_OFFSET 0x0000 -#define IDE1_ERROR_REG_OFFSET 0x0081 -#define IDE1_NSECTOR_REG_OFFSET 0x0082 -#define IDE1_SECTOR_REG_OFFSET 0x0083 -#define IDE1_LCYL_REG_OFFSET 0x0084 -#define IDE1_HCYL_REG_OFFSET 0x0085 -#define IDE1_SELECT_REG_OFFSET 0x0086 -#define IDE1_STATUS_REG_OFFSET 0x0087 -#define IDE1_CONTROL_REG_OFFSET 0x0106 -#define IDE1_IRQ_REG_OFFSET 0x000A /* not used */ - -/* CPM Ethernet through SCCx. - * - * Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */ -#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ -#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002E00) - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif /* !__ASSEMBLY__ */ -#endif /* __ASM_SPD8XX_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/tqm8xx.h b/arch/ppc/platforms/tqm8xx.h index 2150dc8..43ac064 100644 --- a/arch/ppc/platforms/tqm8xx.h +++ b/arch/ppc/platforms/tqm8xx.h @@ -147,29 +147,6 @@ static __inline__ void ide_led(int on) #define SICR_ENET_CLKRT ((uint)0x00002600) #endif /* CONFIG_FPS850L */ -/*** SM850 *********************************************************/ - -/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */ - -#ifdef CONFIG_SM850 -#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */ -#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ -#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ - -#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */ -#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. - */ -#define SICR_ENET_MASK ((uint)0x00FF0000) -#define SICR_ENET_CLKRT ((uint)0x00260000) -#endif /* CONFIG_SM850 */ - /* We don't use the 8259. */ #define NR_8259_INTS 0 |
