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-rw-r--r--arch/mips/pci/ops-bridge.c20
-rw-r--r--arch/mips/pci/pci-ip27.c8
-rw-r--r--arch/mips/pci/pci-sb1250.c8
-rw-r--r--arch/mips/pci/pci-vr41xx.c14
4 files changed, 44 insertions, 6 deletions
diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c
index 1fa0992..b46b3e2 100644
--- a/arch/mips/pci/ops-bridge.c
+++ b/arch/mips/pci/ops-bridge.c
@@ -14,6 +14,22 @@
#include <asm/sn/sn0/hub.h>
/*
+ * Most of the IOC3 PCI config register aren't present
+ * we emulate what is needed for a normal PCI enumeration
+ */
+static u32 emulate_ioc3_cfg(int where, int size)
+{
+ if (size == 1 && where == 0x3d)
+ return 0x01;
+ else if (size == 2 && where == 0x3c)
+ return 0x0100;
+ else if (size == 4 && where == 0x3c)
+ return 0x00000100;
+
+ return 0;
+}
+
+/*
* The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
* not really documented, so right now I can't write code which uses it.
* Therefore we use type 0 accesses for now even though they won't work
@@ -64,7 +80,7 @@ oh_my_gawd:
* generic PCI code a chance to look at the wrong register.
*/
if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
- *value = 0;
+ *value = emulate_ioc3_cfg(where, size);
return PCIBIOS_SUCCESSFUL;
}
@@ -127,7 +143,7 @@ oh_my_gawd:
* generic PCI code a chance to look at the wrong register.
*/
if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
- *value = 0;
+ *value = emulate_ioc3_cfg(where, size);
return PCIBIOS_SUCCESSFUL;
}
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index bb64828..a185169 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -47,6 +47,9 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
static int num_bridges = 0;
bridge_t *bridge;
int slot;
+ extern int pci_probe_only;
+
+ pci_probe_only = 1;
printk("a bridge\n");
@@ -100,6 +103,11 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
*/
bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
BRIDGE_CTRL_MEM_SWAP;
+#ifdef CONFIG_PAGE_SIZE_4KB
+ bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
+#else /* 16kB or larger */
+ bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
+#endif
/*
* Hmm... IRIX sets additional bits in the address which
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index 42e4d2c..2a09ad9 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -207,6 +207,7 @@ struct pci_controller sb1250_controller = {
static int __init sb1250_pcibios_init(void)
{
+ void __iomem *io_map_base;
uint32_t cmdreg;
uint64_t reg;
extern int pci_probe_only;
@@ -253,12 +254,13 @@ static int __init sb1250_pcibios_init(void)
* works correctly with most of Linux's drivers.
* XXX ehs: Should this happen in PCI Device mode?
*/
-
- set_io_port_base((unsigned long)
- ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536));
isa_slot_offset = (unsigned long)
ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024);
+ io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024);
+ sb1250_controller.io_map_base = io_map_base;
+ set_io_port_base((unsigned long)io_map_base);
+
#ifdef CONFIG_SIBYTE_HAS_LDT
/*
* Also check the LDT bridge's enable, just in case we didn't
diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c
index 33c4f68..d1e049b 100644
--- a/arch/mips/pci/pci-vr41xx.c
+++ b/arch/mips/pci/pci-vr41xx.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 2001-2003 MontaVista Software Inc.
* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
- * Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ * Copyright (C) 2004-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
*
* This program is free software; you can redistribute it and/or modify
@@ -300,6 +300,18 @@ static int __init vr41xx_pciu_init(void)
ioport_resource.end = IO_PORT_RESOURCE_END;
}
+ if (setup->master_io) {
+ void __iomem *io_map_base;
+ struct resource *res = vr41xx_pci_controller.io_resource;
+ master = setup->master_io;
+ io_map_base = ioremap(master->bus_base_address,
+ res->end - res->start + 1);
+ if (!io_map_base)
+ return -EBUSY;
+
+ vr41xx_pci_controller.io_map_base = (unsigned long)io_map_base;
+ }
+
register_pci_controller(&vr41xx_pci_controller);
return 0;
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