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-rw-r--r--arch/mips/momentum/jaguar_atx/reset.c2
-rw-r--r--arch/mips/momentum/jaguar_atx/setup.c6
-rw-r--r--arch/mips/momentum/ocelot_3/reset.c2
-rw-r--r--arch/mips/momentum/ocelot_3/setup.c38
-rw-r--r--arch/mips/momentum/ocelot_c/reset.c2
-rw-r--r--arch/mips/momentum/ocelot_c/setup.c4
6 files changed, 26 insertions, 28 deletions
diff --git a/arch/mips/momentum/jaguar_atx/reset.c b/arch/mips/momentum/jaguar_atx/reset.c
index c4236b1..ce9fb2e 100644
--- a/arch/mips/momentum/jaguar_atx/reset.c
+++ b/arch/mips/momentum/jaguar_atx/reset.c
@@ -32,7 +32,7 @@ void momenco_jaguar_restart(char *command)
#else
void *nvram = (void*) 0xfc807000;
#endif
- /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
+ /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
writeb(0x84, nvram + 0xff7);
/* wait for the watchdog to go off */
diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c
index 2699917..91d9637 100644
--- a/arch/mips/momentum/jaguar_atx/setup.c
+++ b/arch/mips/momentum/jaguar_atx/setup.c
@@ -229,8 +229,8 @@ void momenco_time_init(void)
mips_hpt_frequency = cpu_clock / 2;
board_timer_setup = momenco_timer_setup;
- rtc_get_time = m48t37y_get_time;
- rtc_set_time = m48t37y_set_time;
+ rtc_mips_get_time = m48t37y_get_time;
+ rtc_mips_set_time = m48t37y_set_time;
}
static struct resource mv_pci_io_mem0_resource = {
@@ -461,7 +461,7 @@ void __init plat_setup(void)
unsigned int tbControl;
tbControl =
0 << 26 | /* post trigger delay 0 */
- 0x2 << 16 | /* sequential trace mode */
+ 0x2 << 16 | /* sequential trace mode */
// 0x0 << 16 | /* non-sequential trace mode */
// 0xf << 4 | /* watchpoints disabled */
2 << 2 | /* armed */
diff --git a/arch/mips/momentum/ocelot_3/reset.c b/arch/mips/momentum/ocelot_3/reset.c
index 72b4423..9d86d24 100644
--- a/arch/mips/momentum/ocelot_3/reset.c
+++ b/arch/mips/momentum/ocelot_3/reset.c
@@ -34,7 +34,7 @@ void momenco_ocelot_restart(char *command)
/* base address of timekeeper portion of part */
void *nvram = (void *) 0xfc807000L;
- /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
+ /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
writeb(0x84, nvram + 0xff7);
/* wait for the watchdog to go off */
diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c
index f95677f..370e75d 100644
--- a/arch/mips/momentum/ocelot_3/setup.c
+++ b/arch/mips/momentum/ocelot_3/setup.c
@@ -58,6 +58,7 @@
#include <linux/bootmem.h>
#include <linux/mv643xx.h>
#include <linux/pm.h>
+#include <linux/bcd.h>
#include <asm/time.h>
#include <asm/page.h>
@@ -131,9 +132,6 @@ void setup_wired_tlb_entries(void)
add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M);
}
-#define CONV_BCD_TO_BIN(val) (((val) & 0xf) + (((val) >> 4) * 10))
-#define CONV_BIN_TO_BCD(val) (((val) % 10) + (((val) / 10) << 4))
-
unsigned long m48t37y_get_time(void)
{
unsigned int year, month, day, hour, min, sec;
@@ -143,16 +141,16 @@ unsigned long m48t37y_get_time(void)
/* stop the update */
rtc_base[0x7ff8] = 0x40;
- year = CONV_BCD_TO_BIN(rtc_base[0x7fff]);
- year += CONV_BCD_TO_BIN(rtc_base[0x7ff1]) * 100;
+ year = BCD2BIN(rtc_base[0x7fff]);
+ year += BCD2BIN(rtc_base[0x7ff1]) * 100;
- month = CONV_BCD_TO_BIN(rtc_base[0x7ffe]);
+ month = BCD2BIN(rtc_base[0x7ffe]);
- day = CONV_BCD_TO_BIN(rtc_base[0x7ffd]);
+ day = BCD2BIN(rtc_base[0x7ffd]);
- hour = CONV_BCD_TO_BIN(rtc_base[0x7ffb]);
- min = CONV_BCD_TO_BIN(rtc_base[0x7ffa]);
- sec = CONV_BCD_TO_BIN(rtc_base[0x7ff9]);
+ hour = BCD2BIN(rtc_base[0x7ffb]);
+ min = BCD2BIN(rtc_base[0x7ffa]);
+ sec = BCD2BIN(rtc_base[0x7ff9]);
/* start the update */
rtc_base[0x7ff8] = 0x00;
@@ -175,22 +173,22 @@ int m48t37y_set_time(unsigned long sec)
rtc_base[0x7ff8] = 0x80;
/* year */
- rtc_base[0x7fff] = CONV_BIN_TO_BCD(tm.tm_year % 100);
- rtc_base[0x7ff1] = CONV_BIN_TO_BCD(tm.tm_year / 100);
+ rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
+ rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
/* month */
- rtc_base[0x7ffe] = CONV_BIN_TO_BCD(tm.tm_mon);
+ rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
/* day */
- rtc_base[0x7ffd] = CONV_BIN_TO_BCD(tm.tm_mday);
+ rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
/* hour/min/sec */
- rtc_base[0x7ffb] = CONV_BIN_TO_BCD(tm.tm_hour);
- rtc_base[0x7ffa] = CONV_BIN_TO_BCD(tm.tm_min);
- rtc_base[0x7ff9] = CONV_BIN_TO_BCD(tm.tm_sec);
+ rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
+ rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
+ rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
/* day of week -- not really used, but let's keep it up-to-date */
- rtc_base[0x7ffc] = CONV_BIN_TO_BCD(tm.tm_wday + 1);
+ rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
/* disable writing */
rtc_base[0x7ff8] = 0x00;
@@ -215,8 +213,8 @@ void momenco_time_init(void)
mips_hpt_frequency = cpu_clock / 2;
board_timer_setup = momenco_timer_setup;
- rtc_get_time = m48t37y_get_time;
- rtc_set_time = m48t37y_set_time;
+ rtc_mips_get_time = m48t37y_get_time;
+ rtc_mips_set_time = m48t37y_set_time;
}
/*
diff --git a/arch/mips/momentum/ocelot_c/reset.c b/arch/mips/momentum/ocelot_c/reset.c
index 6a2489f..9dcd154 100644
--- a/arch/mips/momentum/ocelot_c/reset.c
+++ b/arch/mips/momentum/ocelot_c/reset.c
@@ -34,7 +34,7 @@ void momenco_ocelot_restart(char *command)
0xfc807000;
#endif
- /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
+ /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
writeb(0x84, nvram + 0xff7);
/* wait for the watchdog to go off */
diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c
index bd02e60..a3e6f55 100644
--- a/arch/mips/momentum/ocelot_c/setup.c
+++ b/arch/mips/momentum/ocelot_c/setup.c
@@ -227,8 +227,8 @@ void momenco_time_init(void)
printk("momenco_time_init cpu_clock=%d\n", cpu_clock);
board_timer_setup = momenco_timer_setup;
- rtc_get_time = m48t37y_get_time;
- rtc_set_time = m48t37y_set_time;
+ rtc_mips_get_time = m48t37y_get_time;
+ rtc_mips_set_time = m48t37y_set_time;
}
void __init plat_setup(void)
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