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Diffstat (limited to 'arch/mips/momentum/ocelot_c/setup.c')
-rw-r--r--arch/mips/momentum/ocelot_c/setup.c27
1 files changed, 14 insertions, 13 deletions
diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c
index 15998d8..bd02e60 100644
--- a/arch/mips/momentum/ocelot_c/setup.c
+++ b/arch/mips/momentum/ocelot_c/setup.c
@@ -54,6 +54,7 @@
#include <linux/pm.h>
#include <linux/timex.h>
#include <linux/vmalloc.h>
+#include <linux/mv643xx.h>
#include <asm/time.h>
#include <asm/bootinfo.h>
@@ -64,9 +65,9 @@
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/reboot.h>
+#include <asm/marvell.h>
#include <linux/bootmem.h>
#include <linux/blkdev.h>
-#include <asm/mv64340.h>
#include "ocelot_c_fpga.h"
unsigned long marvell_base;
@@ -252,22 +253,22 @@ void __init plat_setup(void)
/* shut down ethernet ports, just to be sure our memory doesn't get
* corrupted by random ethernet traffic.
*/
- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
+ MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
+ MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
+ MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
+ MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
do {}
- while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
+ while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
- while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
+ while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
do {}
- while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
+ while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
- while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
- MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
- MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
- MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
- MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
+ while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
+ MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
+ MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
+ MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
+ MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
/* Turn off the Bit-Error LED */
OCELOT_FPGA_WRITE(0x80, CLR);
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