diff options
Diffstat (limited to 'arch/mips/mips-boards')
| -rw-r--r-- | arch/mips/mips-boards/generic/mipsIRQ.S | 2 | ||||
| -rw-r--r-- | arch/mips/mips-boards/sim/sim_IRQ.c | 2 | ||||
| -rw-r--r-- | arch/mips/mips-boards/sim/sim_irq.S | 2 | ||||
| -rw-r--r-- | arch/mips/mips-boards/sim/sim_smp.c | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/mips-boards/generic/mipsIRQ.S b/arch/mips/mips-boards/generic/mipsIRQ.S index a397ecb..ddd5c73 100644 --- a/arch/mips/mips-boards/generic/mipsIRQ.S +++ b/arch/mips/mips-boards/generic/mipsIRQ.S @@ -98,7 +98,7 @@ and s0, s1 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - .set mips32 + .set mips32 clz a0, s0 .set mips0 negu a0 diff --git a/arch/mips/mips-boards/sim/sim_IRQ.c b/arch/mips/mips-boards/sim/sim_IRQ.c index 9987a85..5b84c7f 100644 --- a/arch/mips/mips-boards/sim/sim_IRQ.c +++ b/arch/mips/mips-boards/sim/sim_IRQ.c @@ -96,7 +96,7 @@ andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt #else beq a0, zero, 1f # delay slot, check hw3 interrupt - andi a0, s0, CAUSEF_IP5 + andi a0, s0, CAUSEF_IP5 #endif /* Wheee, combined hardware level zero interrupt. */ diff --git a/arch/mips/mips-boards/sim/sim_irq.S b/arch/mips/mips-boards/sim/sim_irq.S index 835f038..da52297 100644 --- a/arch/mips/mips-boards/sim/sim_irq.S +++ b/arch/mips/mips-boards/sim/sim_irq.S @@ -42,7 +42,7 @@ and s0, s1 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - .set mips32 + .set mips32 clz a0, s0 .set mips0 negu a0 diff --git a/arch/mips/mips-boards/sim/sim_smp.c b/arch/mips/mips-boards/sim/sim_smp.c index 1982435..a9f0c2b 100644 --- a/arch/mips/mips-boards/sim/sim_smp.c +++ b/arch/mips/mips-boards/sim/sim_smp.c @@ -115,7 +115,7 @@ void prom_prepare_cpus(unsigned int max_cpus) #ifdef CONFIG_MIPS_MT_SMTC void mipsmt_prepare_cpus(int c); /* - * As noted above, we can assume a single CPU for now + * As noted above, we can assume a single CPU for now * but it may be multithreaded. */ |
