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-rw-r--r--arch/mips/kernel/traps.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index f548717..08f1edf 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1510,10 +1510,6 @@ void __cpuinit per_cpu_trap_init(void)
write_c0_hwrena(enable);
}
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
- write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
-#endif
-
#ifdef CONFIG_MIPS_MT_SMTC
if (!secondaryTC) {
#endif /* CONFIG_MIPS_MT_SMTC */
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