diff options
Diffstat (limited to 'arch/mips/include/asm/mach-rc32434')
| -rw-r--r-- | arch/mips/include/asm/mach-rc32434/ddr.h | 2 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-rc32434/dma.h | 12 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-rc32434/dma_v.h | 4 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-rc32434/eth.h | 6 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-rc32434/gpio.h | 6 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-rc32434/irq.h | 12 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-rc32434/pci.h | 60 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-rc32434/rb.h | 6 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-rc32434/rc32434.h | 2 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-rc32434/timer.h | 18 |
10 files changed, 64 insertions, 64 deletions
diff --git a/arch/mips/include/asm/mach-rc32434/ddr.h b/arch/mips/include/asm/mach-rc32434/ddr.h index 291e2cf..e1cad0c 100644 --- a/arch/mips/include/asm/mach-rc32434/ddr.h +++ b/arch/mips/include/asm/mach-rc32434/ddr.h @@ -138,4 +138,4 @@ struct ddr_ram { #define RC32434_DLLED_DBE_BIT 0 #define RC32434_DLLED_DTE_BIT 1 -#endif /* _ASM_RC32434_DDR_H_ */ +#endif /* _ASM_RC32434_DDR_H_ */ diff --git a/arch/mips/include/asm/mach-rc32434/dma.h b/arch/mips/include/asm/mach-rc32434/dma.h index 5f898b5..4322191 100644 --- a/arch/mips/include/asm/mach-rc32434/dma.h +++ b/arch/mips/include/asm/mach-rc32434/dma.h @@ -5,7 +5,7 @@ * DMA register definition. * * Author : ryan.holmQVist@idt.com - * Date : 20011005 + * Date : 20011005 */ #ifndef __ASM_RC32434_DMA_H @@ -71,10 +71,10 @@ struct dma_reg { #define DMA_CHAN_DONE_BIT (1 << 1) #define DMA_CHAN_MODE_BIT (1 << 2) #define DMA_CHAN_MODE_MSK 0x0000000c -#define DMA_CHAN_MODE_AUTO 0 -#define DMA_CHAN_MODE_BURST 1 -#define DMA_CHAN_MODE_XFRT 2 -#define DMA_CHAN_MODE_RSVD 3 +#define DMA_CHAN_MODE_AUTO 0 +#define DMA_CHAN_MODE_BURST 1 +#define DMA_CHAN_MODE_XFRT 2 +#define DMA_CHAN_MODE_RSVD 3 #define DMA_CHAN_ACT_BIT (1 << 4) /* DMA status registers */ @@ -100,4 +100,4 @@ struct dma_channel { struct dma_reg ch[DMA_CHAN_COUNT]; }; -#endif /* __ASM_RC32434_DMA_H */ +#endif /* __ASM_RC32434_DMA_H */ diff --git a/arch/mips/include/asm/mach-rc32434/dma_v.h b/arch/mips/include/asm/mach-rc32434/dma_v.h index 173a9f9..28c5406 100644 --- a/arch/mips/include/asm/mach-rc32434/dma_v.h +++ b/arch/mips/include/asm/mach-rc32434/dma_v.h @@ -5,7 +5,7 @@ * DMA register definition. * * Author : ryan.holmQVist@idt.com - * Date : 20011005 + * Date : 20011005 */ #ifndef _ASM_RC32434_DMA_V_H_ @@ -49,4 +49,4 @@ static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr) __raw_writel(dma_addr, &ch->dmandptr); } -#endif /* _ASM_RC32434_DMA_V_H_ */ +#endif /* _ASM_RC32434_DMA_V_H_ */ diff --git a/arch/mips/include/asm/mach-rc32434/eth.h b/arch/mips/include/asm/mach-rc32434/eth.h index a25cbc5..c2645fa 100644 --- a/arch/mips/include/asm/mach-rc32434/eth.h +++ b/arch/mips/include/asm/mach-rc32434/eth.h @@ -26,8 +26,8 @@ * */ -#ifndef __ASM_RC32434_ETH_H -#define __ASM_RC32434_ETH_H +#ifndef __ASM_RC32434_ETH_H +#define __ASM_RC32434_ETH_H #define ETH0_BASE_ADDR 0x18060000 @@ -217,4 +217,4 @@ struct eth_regs { #define ETH_TX_LE (1 << 16) #define ETH_TX_CC 0x001E0000 -#endif /* __ASM_RC32434_ETH_H */ +#endif /* __ASM_RC32434_ETH_H */ diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h index 12ee8d5..4dee0a3 100644 --- a/arch/mips/include/asm/mach-rc32434/gpio.h +++ b/arch/mips/include/asm/mach-rc32434/gpio.h @@ -5,7 +5,7 @@ * GPIO register definition. * * Author : ryan.holmQVist@idt.com - * Date : 20011005 + * Date : 20011005 * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com> * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> */ @@ -26,9 +26,9 @@ #define irq_to_gpio(irq) (irq - (8 + 4 * 32)) struct rb532_gpio_reg { - u32 gpiofunc; /* GPIO Function Register + u32 gpiofunc; /* GPIO Function Register * gpiofunc[x]==0 bit = gpio - * func[x]==1 bit = altfunc + * func[x]==1 bit = altfunc */ u32 gpiocfg; /* GPIO Configuration Register * gpiocfg[x]==0 bit = input diff --git a/arch/mips/include/asm/mach-rc32434/irq.h b/arch/mips/include/asm/mach-rc32434/irq.h index 023a5b10..b76dec9 100644 --- a/arch/mips/include/asm/mach-rc32434/irq.h +++ b/arch/mips/include/asm/mach-rc32434/irq.h @@ -1,7 +1,7 @@ #ifndef __ASM_RC32434_IRQ_H #define __ASM_RC32434_IRQ_H -#define NR_IRQS 256 +#define NR_IRQS 256 #include <asm/mach-generic/irq.h> #include <asm/mach-rc32434/rb.h> @@ -25,12 +25,12 @@ #define UART0_IRQ (GROUP3_IRQ_BASE + 0) -#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0) -#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1) -#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9) -#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10) +#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0) +#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1) +#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9) +#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10) #define GPIO_MAPPED_IRQ_BASE GROUP4_IRQ_BASE #define GPIO_MAPPED_IRQ_GROUP 4 -#endif /* __ASM_RC32434_IRQ_H */ +#endif /* __ASM_RC32434_IRQ_H */ diff --git a/arch/mips/include/asm/mach-rc32434/pci.h b/arch/mips/include/asm/mach-rc32434/pci.h index 410638f..6f40d15 100644 --- a/arch/mips/include/asm/mach-rc32434/pci.h +++ b/arch/mips/include/asm/mach-rc32434/pci.h @@ -151,11 +151,11 @@ struct pci_msu { #define PCI_CFGA_REG_PBA2 (0x18 >> 2) /* use PCIPBA_ */ #define PCI_CFGA_REG_PBA3 (0x1c >> 2) /* use PCIPBA_ */ #define PCI_CFGA_REG_SUBSYS (0x2c >> 2) /* use PCFGSS_ */ -#define PCI_CFGA_REG_3C (0x3C >> 2) /* use PCFG3C_ */ +#define PCI_CFGA_REG_3C (0x3C >> 2) /* use PCFG3C_ */ #define PCI_CFGA_REG_PBBA0C (0x44 >> 2) /* use PCIPBAC_ */ -#define PCI_CFGA_REG_PBA0M (0x48 >> 2) +#define PCI_CFGA_REG_PBA0M (0x48 >> 2) #define PCI_CFGA_REG_PBA1C (0x4c >> 2) /* use PCIPBAC_ */ -#define PCI_CFGA_REG_PBA1M (0x50 >> 2) +#define PCI_CFGA_REG_PBA1M (0x50 >> 2) #define PCI_CFGA_REG_PBA2C (0x54 >> 2) /* use PCIPBAC_ */ #define PCI_CFGA_REG_PBA2M (0x58 >> 2) #define PCI_CFGA_REG_PBA3C (0x5c >> 2) /* use PCIPBAC_ */ @@ -164,9 +164,9 @@ struct pci_msu { #define PCI_CFGA_FUNC_BIT 8 #define PCI_CFGA_FUNC 0x00000700 #define PCI_CFGA_DEV_BIT 11 -#define PCI_CFGA_DEV 0x0000f800 -#define PCI_CFGA_DEV_INTERN 0 -#define PCI_CFGA_BUS_BIT 16 +#define PCI_CFGA_DEV 0x0000f800 +#define PCI_CFGA_DEV_INTERN 0 +#define PCI_CFGA_BUS_BIT 16 #define PCI CFGA_BUS 0x00ff0000 #define PCI_CFGA_BUS_TYPE0 0 #define PCI_CFGA_EN (1 << 31) @@ -201,13 +201,13 @@ struct pci_msu { #define PCI_PBAC_P (1 << 1) #define PCI_PBAC_SIZE_BIT 2 #define PCI_PBAC_SIZE 0x0000007c -#define PCI_PBAC_SB (1 << 7) -#define PCI_PBAC_PP (1 << 8) +#define PCI_PBAC_SB (1 << 7) +#define PCI_PBAC_PP (1 << 8) #define PCI_PBAC_MR_BIT 9 #define PCI_PBAC_MR 0x00000600 #define PCI_PBAC_MR_RD 0 #define PCI_PBAC_MR_RD_LINE 1 -#define PCI_PBAC_MR_RD_MULT 2 +#define PCI_PBAC_MR_RD_MULT 2 #define PCI_PBAC_MRL (1 << 11) #define PCI_PBAC_MRM (1 << 12) #define PCI_PBAC_TRP (1 << 13) @@ -227,14 +227,14 @@ struct pci_msu { */ #define PCI_LBAC_MSI (1 << 0) -#define PCI_LBAC_MSI_MEM 0 -#define PCI_LBAC_MSI_IO 1 +#define PCI_LBAC_MSI_MEM 0 +#define PCI_LBAC_MSI_IO 1 #define PCI_LBAC_SIZE_BIT 2 #define PCI_LBAC_SIZE 0x0000007c #define PCI_LBAC_SB (1 << 7) #define PCI_LBAC_RT (1 << 8) -#define PCI_LBAC_RT_NO_PREF 0 -#define PCI_LBAC_RT_PREF 1 +#define PCI_LBAC_RT_NO_PREF 0 +#define PCI_LBAC_RT_PREF 1 /* * PCI Local Base Address [0|1|2|3] Mapping Register @@ -279,16 +279,16 @@ struct pci_msu { #define PCI_DMAD_PT 0x00c00000 /* preferred transaction field */ /* These are for reads (DMA channel 8) */ #define PCI_DMAD_DEVCMD_MR 0 /* memory read */ -#define PCI_DMAD_DEVCMD_MRL 1 /* memory read line */ -#define PCI_DMAD_DEVCMD_MRM 2 /* memory read multiple */ -#define PCI_DMAD_DEVCMD_IOR 3 /* I/O read */ +#define PCI_DMAD_DEVCMD_MRL 1 /* memory read line */ +#define PCI_DMAD_DEVCMD_MRM 2 /* memory read multiple */ +#define PCI_DMAD_DEVCMD_IOR 3 /* I/O read */ /* These are for writes (DMA channel 9) */ #define PCI_DMAD_DEVCMD_MW 0 /* memory write */ -#define PCI_DMAD_DEVCMD_MWI 1 /* memory write invalidate */ -#define PCI_DMAD_DEVCMD_IOW 3 /* I/O write */ +#define PCI_DMAD_DEVCMD_MWI 1 /* memory write invalidate */ +#define PCI_DMAD_DEVCMD_IOW 3 /* I/O write */ /* Swap byte field applies to both DMA channel 8 and 9 */ -#define PCI_DMAD_SB (1 << 24) /* swap byte field */ +#define PCI_DMAD_SB (1 << 24) /* swap byte field */ /* @@ -309,7 +309,7 @@ struct pci_msu { #define PCI_MSU_M1 (1 << 1) #define PCI_MSU_DB (1 << 2) -#define PCI_MSG_ADDR 0xB8088010 +#define PCI_MSG_ADDR 0xB8088010 #define PCI0_ADDR 0xB8080000 #define rc32434_pci ((struct pci_reg *) PCI0_ADDR) #define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR) @@ -331,9 +331,9 @@ struct pci_msu { #define PCILBA_SIZE_MASK 0x1F #define SIZE_256MB 0x1C #define SIZE_128MB 0x1B -#define SIZE_64MB 0x1A +#define SIZE_64MB 0x1A #define SIZE_32MB 0x19 -#define SIZE_16MB 0x18 +#define SIZE_16MB 0x18 #define SIZE_4MB 0x16 #define SIZE_2MB 0x15 #define SIZE_1MB 0x14 @@ -363,7 +363,7 @@ struct pci_msu { #define KORINA_CONFIG23_ADDR 0x8000005C #define KORINA_CONFIG24_ADDR 0x80000060 #define KORINA_CONFIG25_ADDR 0x80000064 -#define KORINA_CMD (PCI_CFG04_CMD_IO_ENA | \ +#define KORINA_CMD (PCI_CFG04_CMD_IO_ENA | \ PCI_CFG04_CMD_MEM_ENA | \ PCI_CFG04_CMD_BM_ENA | \ PCI_CFG04_CMD_MW_INV | \ @@ -401,8 +401,8 @@ struct pci_msu { #define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */ #define KORINA_CNFG4 KORINA_BAR0 -#define KORINA_CNFG5 KORINA_BAR1 -#define KORINA_CNFG6 KORINA_BAR2 +#define KORINA_CNFG5 KORINA_BAR1 +#define KORINA_CNFG6 KORINA_BAR2 #define KORINA_CNFG7 KORINA_BAR3 #define KORINA_SUBSYS_VENDOR_ID 0x011d @@ -410,20 +410,20 @@ struct pci_msu { #define KORINA_CNFG8 0 #define KORINA_CNFG9 0 #define KORINA_CNFG10 0 -#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \ +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \ KORINA_SUBSYSTEM_ID) #define KORINA_INT_LINE 1 #define KORINA_INT_PIN 1 #define KORINA_MIN_GNT 8 #define KORINA_MAX_LAT 0x38 #define KORINA_CNFG12 0 -#define KORINA_CNFG13 0 +#define KORINA_CNFG13 0 #define KORINA_CNFG14 0 #define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \ (KORINA_MIN_GNT<<16) | \ (KORINA_INT_PIN<<8) | \ KORINA_INT_LINE) -#define KORINA_RETRY_LIMIT 0x80 +#define KORINA_RETRY_LIMIT 0x80 #define KORINA_TRDY_LIMIT 0x80 #define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \ KORINA_TRDY_LIMIT) @@ -475,7 +475,7 @@ struct pci_msu { #define KORINA_PBA3M 0 #define KORINA_CNFG24 KORINA_PBA3M -#define PCITC_DTIMER_VAL 8 +#define PCITC_DTIMER_VAL 8 #define PCITC_RTIMER_VAL 0x10 -#endif /* __ASM_RC32434_PCI_H */ +#endif /* __ASM_RC32434_PCI_H */ diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h index 6dc5f8d..aac8ce8 100644 --- a/arch/mips/include/asm/mach-rc32434/rb.h +++ b/arch/mips/include/asm/mach-rc32434/rb.h @@ -18,7 +18,7 @@ #include <linux/genhd.h> #define REGBASE 0x18000000 -#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE)) +#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE)) #define UART0BASE 0x58000 #define RST (1 << 15) #define DEV0BASE 0x010000 @@ -80,10 +80,10 @@ struct cf_device { struct mpmc_device { unsigned char state; spinlock_t lock; - void __iomem *base; + void __iomem *base; }; extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); extern unsigned char get_latch_u5(void); -#endif /* __ASM_RC32434_RB_H */ +#endif /* __ASM_RC32434_RB_H */ diff --git a/arch/mips/include/asm/mach-rc32434/rc32434.h b/arch/mips/include/asm/mach-rc32434/rc32434.h index fce25d4..02fd32b 100644 --- a/arch/mips/include/asm/mach-rc32434/rc32434.h +++ b/arch/mips/include/asm/mach-rc32434/rc32434.h @@ -16,4 +16,4 @@ static inline void rc32434_sync(void) __asm__ volatile ("sync"); } -#endif /* _ASM_RC32434_RC32434_H_ */ +#endif /* _ASM_RC32434_RC32434_H_ */ diff --git a/arch/mips/include/asm/mach-rc32434/timer.h b/arch/mips/include/asm/mach-rc32434/timer.h index e49b1d5..cda26bb9 100644 --- a/arch/mips/include/asm/mach-rc32434/timer.h +++ b/arch/mips/include/asm/mach-rc32434/timer.h @@ -51,15 +51,15 @@ struct timer { #define RC32434_CTC_TO_BIT 1 /* Real time clock registers */ -#define RC32434_RTC_MSK(x) BIT_TO_MASK(x) -#define RC32434_RTC_CE_BIT 0 -#define RC32434_RTC_TO_BIT 1 -#define RC32434_RTC_RQE_BIT 2 +#define RC32434_RTC_MSK(x) BIT_TO_MASK(x) +#define RC32434_RTC_CE_BIT 0 +#define RC32434_RTC_TO_BIT 1 +#define RC32434_RTC_RQE_BIT 2 /* Counter registers */ -#define RC32434_RCOUNT_BIT 0 -#define RC32434_RCOUNT_MSK 0x0000ffff -#define RC32434_RCOMP_BIT 0 -#define RC32434_RCOMP_MSK 0x0000ffff +#define RC32434_RCOUNT_BIT 0 +#define RC32434_RCOUNT_MSK 0x0000ffff +#define RC32434_RCOMP_BIT 0 +#define RC32434_RCOMP_MSK 0x0000ffff -#endif /* __ASM_RC32434_TIMER_H */ +#endif /* __ASM_RC32434_TIMER_H */ |
