diff options
Diffstat (limited to 'arch/mips/include/asm/io.h')
| -rw-r--r-- | arch/mips/include/asm/io.h | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index ff2e034..1be1372 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -7,7 +7,7 @@ * Copyright (C) 1994 - 2000, 06 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. - * Author: Maciej W. Rozycki <macro@mips.com> + * Author: Maciej W. Rozycki <macro@mips.com> */ #ifndef _ASM_IO_H #define _ASM_IO_H @@ -253,9 +253,9 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, __ioremap_mode((offset), (size), _CACHE_UNCACHED) /* - * ioremap_cachable - map bus memory into CPU space - * @offset: bus address of the memory - * @size: size of the resource to map + * ioremap_cachable - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map * * ioremap_nocache performs a platform specific sequence of operations to * make bus memory CPU accessible via the readb/readw/readl/writeb/ @@ -264,14 +264,14 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, * address. * * This version of ioremap ensures that the memory is marked cachable by - * the CPU. Also enables full write-combining. Useful for some + * the CPU. Also enables full write-combining. Useful for some * memory-like regions on I/O busses. */ #define ioremap_cachable(offset, size) \ __ioremap_mode((offset), (size), _page_cachable_default) /* - * These two are MIPS specific ioremap variant. ioremap_cacheable_cow + * These two are MIPS specific ioremap variant. ioremap_cacheable_cow * requests a cachable mapping, ioremap_uncached_accelerated requests a * mapping using the uncached accelerated mode which isn't supported on * all processors. @@ -298,7 +298,7 @@ static inline void iounmap(const volatile void __iomem *addr) } #ifdef CONFIG_CPU_CAVIUM_OCTEON -#define war_octeon_io_reorder_wmb() wmb() +#define war_octeon_io_reorder_wmb() wmb() #else #define war_octeon_io_reorder_wmb() do { } while (0) #endif @@ -317,7 +317,7 @@ static inline void pfx##write##bwlq(type val, \ \ __val = pfx##ioswab##bwlq(__mem, val); \ \ - if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ + if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ *__mem = __val; \ else if (cpu_has_64bits) { \ unsigned long __flags; \ @@ -327,9 +327,9 @@ static inline void pfx##write##bwlq(type val, \ local_irq_save(__flags); \ __asm__ __volatile__( \ ".set mips3" "\t\t# __writeq""\n\t" \ - "dsll32 %L0, %L0, 0" "\n\t" \ - "dsrl32 %L0, %L0, 0" "\n\t" \ - "dsll32 %M0, %M0, 0" "\n\t" \ + "dsll32 %L0, %L0, 0" "\n\t" \ + "dsrl32 %L0, %L0, 0" "\n\t" \ + "dsll32 %M0, %M0, 0" "\n\t" \ "or %L0, %L0, %M0" "\n\t" \ "sd %L0, %2" "\n\t" \ ".set mips0" "\n" \ @@ -348,7 +348,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ \ __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ \ - if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ + if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ __val = *__mem; \ else if (cpu_has_64bits) { \ unsigned long __flags; \ @@ -356,9 +356,9 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ if (irq) \ local_irq_save(__flags); \ __asm__ __volatile__( \ - ".set mips3" "\t\t# __readq" "\n\t" \ + ".set mips3" "\t\t# __readq" "\n\t" \ "ld %L0, %1" "\n\t" \ - "dsra32 %M0, %L0, 0" "\n\t" \ + "dsra32 %M0, %L0, 0" "\n\t" \ "sll %L0, %L0, 0" "\n\t" \ ".set mips0" "\n" \ : "=r" (__val) \ @@ -586,7 +586,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); #else /* Sane hardware */ -#define dma_cache_wback_inv(start,size) \ +#define dma_cache_wback_inv(start,size) \ do { (void) (start); (void) (size); } while (0) #define dma_cache_wback(start,size) \ do { (void) (start); (void) (size); } while (0) |
