diff options
Diffstat (limited to 'arch/mips/alchemy/common/time.c')
| -rw-r--r-- | arch/mips/alchemy/common/time.c | 35 |
1 files changed, 30 insertions, 5 deletions
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 379a664..2aecb2f 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net> + * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com> * * Previous incarnations were: * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com> @@ -85,7 +85,6 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = { .name = "rtcmatch2", .features = CLOCK_EVT_FEAT_ONESHOT, .rating = 100, - .irq = AU1000_RTC_MATCH2_INT, .set_next_event = au1x_rtcmatch2_set_next_event, .set_mode = au1x_rtcmatch2_set_mode, .cpumask = cpu_all_mask, @@ -98,11 +97,13 @@ static struct irqaction au1x_rtcmatch2_irqaction = { .dev_id = &au1x_rtcmatch2_clockdev, }; -void __init plat_time_init(void) +static int __init alchemy_time_init(unsigned int m2int) { struct clock_event_device *cd = &au1x_rtcmatch2_clockdev; unsigned long t; + au1x_rtcmatch2_clockdev.irq = m2int; + /* Check if firmware (YAMON, ...) has enabled 32kHz and clock * has been detected. If so install the rtcmatch2 clocksource, * otherwise don't bother. Note that both bits being set is by @@ -148,13 +149,18 @@ void __init plat_time_init(void) cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd); cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */ clockevents_register_device(cd); - setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction); + setup_irq(m2int, &au1x_rtcmatch2_irqaction); printk(KERN_INFO "Alchemy clocksource installed\n"); - return; + return 0; cntr_err: + return -1; +} + +static void __init alchemy_setup_c0timer(void) +{ /* * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this * function is called. Because the Alchemy counters are unusable @@ -166,3 +172,22 @@ cntr_err: r4k_clockevent_init(); init_r4k_clocksource(); } + +static int alchemy_m2inttab[] __initdata = { + AU1000_RTC_MATCH2_INT, + AU1500_RTC_MATCH2_INT, + AU1100_RTC_MATCH2_INT, + AU1550_RTC_MATCH2_INT, + AU1200_RTC_MATCH2_INT, +}; + +void __init plat_time_init(void) +{ + int t; + + t = alchemy_get_cputype(); + if (t == ALCHEMY_CPU_UNKNOWN) + alchemy_setup_c0timer(); + else if (alchemy_time_init(alchemy_m2inttab[t])) + alchemy_setup_c0timer(); +} |
