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-rw-r--r--arch/metag/include/asm/cache.h24
1 files changed, 0 insertions, 24 deletions
diff --git a/arch/metag/include/asm/cache.h b/arch/metag/include/asm/cache.h
deleted file mode 100644
index b5df022..0000000
--- a/arch/metag/include/asm/cache.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_CACHE_H
-#define __ASM_METAG_CACHE_H
-
-/* L1 cache line size (64 bytes) */
-#define L1_CACHE_SHIFT 6
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-/* Meta requires large data items to be 8 byte aligned. */
-#define ARCH_SLAB_MINALIGN 8
-
-/*
- * With an L2 cache, we may invalidate dirty lines, so we need to ensure DMA
- * buffers have cache line alignment.
- */
-#ifdef CONFIG_METAG_L2C
-#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-#else
-#define ARCH_DMA_MINALIGN 8
-#endif
-
-#define __read_mostly __attribute__((__section__(".data..read_mostly")))
-
-#endif
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