diff options
Diffstat (limited to 'arch/m68knommu/platform')
80 files changed, 0 insertions, 14714 deletions
diff --git a/arch/m68knommu/platform/5206/Makefile b/arch/m68knommu/platform/5206/Makefile deleted file mode 100644 index b5db056..0000000 --- a/arch/m68knommu/platform/5206/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o - diff --git a/arch/m68knommu/platform/5206/config.c b/arch/m68knommu/platform/5206/config.c deleted file mode 100644 index 9c33546..0000000 --- a/arch/m68knommu/platform/5206/config.c +++ /dev/null @@ -1,121 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/5206/config.c - * - * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) - * Copyright (C) 2000-2001, Lineo Inc. (www.lineo.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/io.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfuart.h> - -/***************************************************************************/ - -static struct mcf_platform_uart m5206_uart_platform[] = { - { - .mapbase = MCF_MBAR + MCFUART_BASE1, - .irq = 73, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE2, - .irq = 74, - }, - { }, -}; - -static struct platform_device m5206_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m5206_uart_platform, -}; - -static struct platform_device *m5206_devices[] __initdata = { - &m5206_uart, -}; - -/***************************************************************************/ - -static void __init m5206_uart_init_line(int line, int irq) -{ - if (line == 0) { - writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); - writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); - mcf_mapirq2imr(irq, MCFINTC_UART0); - } else if (line == 1) { - writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); - writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); - mcf_mapirq2imr(irq, MCFINTC_UART1); - } -} - -static void __init m5206_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m5206_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m5206_uart_init_line(line, m5206_uart_platform[line].irq); -} - -/***************************************************************************/ - -static void __init m5206_timers_init(void) -{ - /* Timer1 is always used as system timer */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, - MCF_MBAR + MCFSIM_TIMER1ICR); - mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1); - -#ifdef CONFIG_HIGHPROFILE - /* Timer2 is to be used as a high speed profile timer */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, - MCF_MBAR + MCFSIM_TIMER2ICR); - mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2); -#endif -} - -/***************************************************************************/ - -void m5206_cpu_reset(void) -{ - local_irq_disable(); - /* Set watchdog to soft reset, and enabled */ - __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR); - for (;;) - /* wait for watchdog to timeout */; -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ - mach_reset = m5206_cpu_reset; - m5206_timers_init(); - m5206_uarts_init(); - - /* Only support the external interrupts on their primary level */ - mcf_mapirq2imr(25, MCFINTC_EINT1); - mcf_mapirq2imr(28, MCFINTC_EINT4); - mcf_mapirq2imr(31, MCFINTC_EINT7); -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/5206/gpio.c b/arch/m68knommu/platform/5206/gpio.c deleted file mode 100644 index b9ab4a1..0000000 --- a/arch/m68knommu/platform/5206/gpio.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PP", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFSIM_PADDR, - .podr = (void __iomem *) MCFSIM_PADAT, - .ppdr = (void __iomem *) MCFSIM_PADAT, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68knommu/platform/5206e/Makefile b/arch/m68knommu/platform/5206e/Makefile deleted file mode 100644 index b5db056..0000000 --- a/arch/m68knommu/platform/5206e/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o - diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c deleted file mode 100644 index 9423979..0000000 --- a/arch/m68knommu/platform/5206e/config.c +++ /dev/null @@ -1,127 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/5206e/config.c - * - * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/io.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfuart.h> -#include <asm/mcfdma.h> - -/***************************************************************************/ - -static struct mcf_platform_uart m5206e_uart_platform[] = { - { - .mapbase = MCF_MBAR + MCFUART_BASE1, - .irq = 73, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE2, - .irq = 74, - }, - { }, -}; - -static struct platform_device m5206e_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m5206e_uart_platform, -}; - -static struct platform_device *m5206e_devices[] __initdata = { - &m5206e_uart, -}; - -/***************************************************************************/ - -static void __init m5206e_uart_init_line(int line, int irq) -{ - if (line == 0) { - writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); - writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); - mcf_mapirq2imr(irq, MCFINTC_UART0); - } else if (line == 1) { - writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); - writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); - mcf_mapirq2imr(irq, MCFINTC_UART1); - } -} - -static void __init m5206e_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m5206e_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m5206e_uart_init_line(line, m5206e_uart_platform[line].irq); -} - -/***************************************************************************/ - -static void __init m5206e_timers_init(void) -{ - /* Timer1 is always used as system timer */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, - MCF_MBAR + MCFSIM_TIMER1ICR); - mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1); - -#ifdef CONFIG_HIGHPROFILE - /* Timer2 is to be used as a high speed profile timer */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, - MCF_MBAR + MCFSIM_TIMER2ICR); - mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2); -#endif -} - -/***************************************************************************/ - -void m5206e_cpu_reset(void) -{ - local_irq_disable(); - /* Set watchdog to soft reset, and enabled */ - __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR); - for (;;) - /* wait for watchdog to timeout */; -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ -#if defined(CONFIG_NETtel) - /* Copy command line from FLASH to local buffer... */ - memcpy(commandp, (char *) 0xf0004000, size); - commandp[size-1] = 0; -#endif /* CONFIG_NETtel */ - - mach_reset = m5206e_cpu_reset; - m5206e_timers_init(); - m5206e_uarts_init(); - - /* Only support the external interrupts on their primary level */ - mcf_mapirq2imr(25, MCFINTC_EINT1); - mcf_mapirq2imr(28, MCFINTC_EINT4); - mcf_mapirq2imr(31, MCFINTC_EINT7); -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - platform_add_devices(m5206e_devices, ARRAY_SIZE(m5206e_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/5206e/gpio.c b/arch/m68knommu/platform/5206e/gpio.c deleted file mode 100644 index b9ab4a1..0000000 --- a/arch/m68knommu/platform/5206e/gpio.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PP", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFSIM_PADDR, - .podr = (void __iomem *) MCFSIM_PADAT, - .ppdr = (void __iomem *) MCFSIM_PADAT, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68knommu/platform/520x/Makefile b/arch/m68knommu/platform/520x/Makefile deleted file mode 100644 index ad3f4e5..0000000 --- a/arch/m68knommu/platform/520x/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# Makefile for the M5208 specific file. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o diff --git a/arch/m68knommu/platform/520x/config.c b/arch/m68knommu/platform/520x/config.c deleted file mode 100644 index 621238f..0000000 --- a/arch/m68knommu/platform/520x/config.c +++ /dev/null @@ -1,311 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/520x/config.c - * - * Copyright (C) 2005, Freescale (www.freescale.com) - * Copyright (C) 2005, Intec Automation (mike@steroidmicros.com) - * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com) - * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/spi/spi.h> -#include <linux/gpio.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfuart.h> -#include <asm/mcfqspi.h> - -/***************************************************************************/ - -static struct mcf_platform_uart m520x_uart_platform[] = { - { - .mapbase = MCFUART_BASE1, - .irq = MCFINT_VECBASE + MCFINT_UART0, - }, - { - .mapbase = MCFUART_BASE2, - .irq = MCFINT_VECBASE + MCFINT_UART1, - }, - { - .mapbase = MCFUART_BASE3, - .irq = MCFINT_VECBASE + MCFINT_UART2, - }, - { }, -}; - -static struct platform_device m520x_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m520x_uart_platform, -}; - -static struct resource m520x_fec_resources[] = { - { - .start = MCFFEC_BASE, - .end = MCFFEC_BASE + MCFFEC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = 64 + 36, - .end = 64 + 36, - .flags = IORESOURCE_IRQ, - }, - { - .start = 64 + 40, - .end = 64 + 40, - .flags = IORESOURCE_IRQ, - }, - { - .start = 64 + 42, - .end = 64 + 42, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device m520x_fec = { - .name = "fec", - .id = 0, - .num_resources = ARRAY_SIZE(m520x_fec_resources), - .resource = m520x_fec_resources, -}; - -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) -static struct resource m520x_qspi_resources[] = { - { - .start = MCFQSPI_IOBASE, - .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MCFINT_VECBASE + MCFINT_QSPI, - .end = MCFINT_VECBASE + MCFINT_QSPI, - .flags = IORESOURCE_IRQ, - }, -}; - -#define MCFQSPI_CS0 62 -#define MCFQSPI_CS1 63 -#define MCFQSPI_CS2 44 - -static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control) -{ - int status; - - status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS0 failed\n"); - goto fail0; - } - status = gpio_direction_output(MCFQSPI_CS0, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n"); - goto fail1; - } - - status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS1 failed\n"); - goto fail1; - } - status = gpio_direction_output(MCFQSPI_CS1, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n"); - goto fail2; - } - - status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS2 failed\n"); - goto fail2; - } - status = gpio_direction_output(MCFQSPI_CS2, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n"); - goto fail3; - } - - return 0; - -fail3: - gpio_free(MCFQSPI_CS2); -fail2: - gpio_free(MCFQSPI_CS1); -fail1: - gpio_free(MCFQSPI_CS0); -fail0: - return status; -} - -static void m520x_cs_teardown(struct mcfqspi_cs_control *cs_control) -{ - gpio_free(MCFQSPI_CS2); - gpio_free(MCFQSPI_CS1); - gpio_free(MCFQSPI_CS0); -} - -static void m520x_cs_select(struct mcfqspi_cs_control *cs_control, - u8 chip_select, bool cs_high) -{ - switch (chip_select) { - case 0: - gpio_set_value(MCFQSPI_CS0, cs_high); - break; - case 1: - gpio_set_value(MCFQSPI_CS1, cs_high); - break; - case 2: - gpio_set_value(MCFQSPI_CS2, cs_high); - break; - } -} - -static void m520x_cs_deselect(struct mcfqspi_cs_control *cs_control, - u8 chip_select, bool cs_high) -{ - switch (chip_select) { - case 0: - gpio_set_value(MCFQSPI_CS0, !cs_high); - break; - case 1: - gpio_set_value(MCFQSPI_CS1, !cs_high); - break; - case 2: - gpio_set_value(MCFQSPI_CS2, !cs_high); - break; - } -} - -static struct mcfqspi_cs_control m520x_cs_control = { - .setup = m520x_cs_setup, - .teardown = m520x_cs_teardown, - .select = m520x_cs_select, - .deselect = m520x_cs_deselect, -}; - -static struct mcfqspi_platform_data m520x_qspi_data = { - .bus_num = 0, - .num_chipselect = 3, - .cs_control = &m520x_cs_control, -}; - -static struct platform_device m520x_qspi = { - .name = "mcfqspi", - .id = 0, - .num_resources = ARRAY_SIZE(m520x_qspi_resources), - .resource = m520x_qspi_resources, - .dev.platform_data = &m520x_qspi_data, -}; - -static void __init m520x_qspi_init(void) -{ - u16 par; - /* setup Port QS for QSPI with gpio CS control */ - writeb(0x3f, MCF_GPIO_PAR_QSPI); - /* make U1CTS and U2RTS gpio for cs_control */ - par = readw(MCF_GPIO_PAR_UART); - par &= 0x00ff; - writew(par, MCF_GPIO_PAR_UART); -} -#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ - - -static struct platform_device *m520x_devices[] __initdata = { - &m520x_uart, - &m520x_fec, -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) - &m520x_qspi, -#endif -}; - -/***************************************************************************/ - -static void __init m520x_uart_init_line(int line, int irq) -{ - u16 par; - u8 par2; - - switch (line) { - case 0: - par = readw(MCF_GPIO_PAR_UART); - par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | - MCF_GPIO_PAR_UART_PAR_URXD0; - writew(par, MCF_GPIO_PAR_UART); - break; - case 1: - par = readw(MCF_GPIO_PAR_UART); - par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | - MCF_GPIO_PAR_UART_PAR_URXD1; - writew(par, MCF_GPIO_PAR_UART); - break; - case 2: - par2 = readb(MCF_GPIO_PAR_FECI2C); - par2 &= ~0x0F; - par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 | - MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2; - writeb(par2, MCF_GPIO_PAR_FECI2C); - break; - } -} - -static void __init m520x_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m520x_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m520x_uart_init_line(line, m520x_uart_platform[line].irq); -} - -/***************************************************************************/ - -static void __init m520x_fec_init(void) -{ - u8 v; - - /* Set multi-function pins to ethernet mode */ - v = readb(MCF_GPIO_PAR_FEC); - writeb(v | 0xf0, MCF_GPIO_PAR_FEC); - - v = readb(MCF_GPIO_PAR_FECI2C); - writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C); -} - -/***************************************************************************/ - -static void m520x_cpu_reset(void) -{ - local_irq_disable(); - __raw_writeb(MCF_RCR_SWRESET, MCF_RCR); -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ - mach_reset = m520x_cpu_reset; - m520x_uarts_init(); - m520x_fec_init(); -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) - m520x_qspi_init(); -#endif -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - platform_add_devices(m520x_devices, ARRAY_SIZE(m520x_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/520x/gpio.c b/arch/m68knommu/platform/520x/gpio.c deleted file mode 100644 index d757328..0000000 --- a/arch/m68knommu/platform/520x/gpio.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PIRQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFEPORT_EPDDR, - .podr = (void __iomem *) MCFEPORT_EPDR, - .ppdr = (void __iomem *) MCFEPORT_EPPDR, - }, - { - .gpio_chip = { - .label = "BUSCTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 8, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, - .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, - }, - { - .gpio_chip = { - .label = "BE", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 16, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BE, - .podr = (void __iomem *) MCFGPIO_PODR_BE, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BE, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BE, - }, - { - .gpio_chip = { - .label = "CS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 25, - .ngpio = 3, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_CS, - .podr = (void __iomem *) MCFGPIO_PODR_CS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, - }, - { - .gpio_chip = { - .label = "FECI2C", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 32, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, - .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, - }, - { - .gpio_chip = { - .label = "QSPI", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 40, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, - .podr = (void __iomem *) MCFGPIO_PODR_QSPI, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, - }, - { - .gpio_chip = { - .label = "TIMER", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 48, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, - .podr = (void __iomem *) MCFGPIO_PODR_TIMER, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER, - }, - { - .gpio_chip = { - .label = "UART", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 56, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UART, - .podr = (void __iomem *) MCFGPIO_PODR_UART, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UART, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UART, - }, - { - .gpio_chip = { - .label = "FECH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 64, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECH, - .podr = (void __iomem *) MCFGPIO_PODR_FECH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH, - }, - { - .gpio_chip = { - .label = "FECL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 72, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECL, - .podr = (void __iomem *) MCFGPIO_PODR_FECL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68knommu/platform/523x/Makefile b/arch/m68knommu/platform/523x/Makefile deleted file mode 100644 index c04b8f7..0000000 --- a/arch/m68knommu/platform/523x/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o diff --git a/arch/m68knommu/platform/523x/config.c b/arch/m68knommu/platform/523x/config.c deleted file mode 100644 index 418a76f..0000000 --- a/arch/m68knommu/platform/523x/config.c +++ /dev/null @@ -1,293 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/523x/config.c - * - * Sub-architcture dependant initialization code for the Freescale - * 523x CPUs. - * - * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com) - * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/spi/spi.h> -#include <linux/gpio.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfuart.h> -#include <asm/mcfqspi.h> - -/***************************************************************************/ - -static struct mcf_platform_uart m523x_uart_platform[] = { - { - .mapbase = MCFUART_BASE1, - .irq = MCFINT_VECBASE + MCFINT_UART0, - }, - { - .mapbase = MCFUART_BASE2, - .irq = MCFINT_VECBASE + MCFINT_UART0 + 1, - }, - { - .mapbase = MCFUART_BASE3, - .irq = MCFINT_VECBASE + MCFINT_UART0 + 2, - }, - { }, -}; - -static struct platform_device m523x_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m523x_uart_platform, -}; - -static struct resource m523x_fec_resources[] = { - { - .start = MCFFEC_BASE, - .end = MCFFEC_BASE + MCFFEC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = 64 + 23, - .end = 64 + 23, - .flags = IORESOURCE_IRQ, - }, - { - .start = 64 + 27, - .end = 64 + 27, - .flags = IORESOURCE_IRQ, - }, - { - .start = 64 + 29, - .end = 64 + 29, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device m523x_fec = { - .name = "fec", - .id = 0, - .num_resources = ARRAY_SIZE(m523x_fec_resources), - .resource = m523x_fec_resources, -}; - -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) -static struct resource m523x_qspi_resources[] = { - { - .start = MCFQSPI_IOBASE, - .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MCFINT_VECBASE + MCFINT_QSPI, - .end = MCFINT_VECBASE + MCFINT_QSPI, - .flags = IORESOURCE_IRQ, - }, -}; - -#define MCFQSPI_CS0 91 -#define MCFQSPI_CS1 92 -#define MCFQSPI_CS2 103 -#define MCFQSPI_CS3 99 - -static int m523x_cs_setup(struct mcfqspi_cs_control *cs_control) -{ - int status; - - status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS0 failed\n"); - goto fail0; - } - status = gpio_direction_output(MCFQSPI_CS0, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n"); - goto fail1; - } - - status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS1 failed\n"); - goto fail1; - } - status = gpio_direction_output(MCFQSPI_CS1, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n"); - goto fail2; - } - - status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS2 failed\n"); - goto fail2; - } - status = gpio_direction_output(MCFQSPI_CS2, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n"); - goto fail3; - } - - status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS3 failed\n"); - goto fail3; - } - status = gpio_direction_output(MCFQSPI_CS3, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n"); - goto fail4; - } - - return 0; - -fail4: - gpio_free(MCFQSPI_CS3); -fail3: - gpio_free(MCFQSPI_CS2); -fail2: - gpio_free(MCFQSPI_CS1); -fail1: - gpio_free(MCFQSPI_CS0); -fail0: - return status; -} - -static void m523x_cs_teardown(struct mcfqspi_cs_control *cs_control) -{ - gpio_free(MCFQSPI_CS3); - gpio_free(MCFQSPI_CS2); - gpio_free(MCFQSPI_CS1); - gpio_free(MCFQSPI_CS0); -} - -static void m523x_cs_select(struct mcfqspi_cs_control *cs_control, - u8 chip_select, bool cs_high) -{ - switch (chip_select) { - case 0: - gpio_set_value(MCFQSPI_CS0, cs_high); - break; - case 1: - gpio_set_value(MCFQSPI_CS1, cs_high); - break; - case 2: - gpio_set_value(MCFQSPI_CS2, cs_high); - break; - case 3: - gpio_set_value(MCFQSPI_CS3, cs_high); - break; - } -} - -static void m523x_cs_deselect(struct mcfqspi_cs_control *cs_control, - u8 chip_select, bool cs_high) -{ - switch (chip_select) { - case 0: - gpio_set_value(MCFQSPI_CS0, !cs_high); - break; - case 1: - gpio_set_value(MCFQSPI_CS1, !cs_high); - break; - case 2: - gpio_set_value(MCFQSPI_CS2, !cs_high); - break; - case 3: - gpio_set_value(MCFQSPI_CS3, !cs_high); - break; - } -} - -static struct mcfqspi_cs_control m523x_cs_control = { - .setup = m523x_cs_setup, - .teardown = m523x_cs_teardown, - .select = m523x_cs_select, - .deselect = m523x_cs_deselect, -}; - -static struct mcfqspi_platform_data m523x_qspi_data = { - .bus_num = 0, - .num_chipselect = 4, - .cs_control = &m523x_cs_control, -}; - -static struct platform_device m523x_qspi = { - .name = "mcfqspi", - .id = 0, - .num_resources = ARRAY_SIZE(m523x_qspi_resources), - .resource = m523x_qspi_resources, - .dev.platform_data = &m523x_qspi_data, -}; - -static void __init m523x_qspi_init(void) -{ - u16 par; - - /* setup QSPS pins for QSPI with gpio CS control */ - writeb(0x1f, MCFGPIO_PAR_QSPI); - /* and CS2 & CS3 as gpio */ - par = readw(MCFGPIO_PAR_TIMER); - par &= 0x3f3f; - writew(par, MCFGPIO_PAR_TIMER); -} -#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ - -static struct platform_device *m523x_devices[] __initdata = { - &m523x_uart, - &m523x_fec, -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) - &m523x_qspi, -#endif -}; - -/***************************************************************************/ - -static void __init m523x_fec_init(void) -{ - u16 par; - u8 v; - - /* Set multi-function pins to ethernet use */ - par = readw(MCF_IPSBAR + 0x100082); - writew(par | 0xf00, MCF_IPSBAR + 0x100082); - v = readb(MCF_IPSBAR + 0x100078); - writeb(v | 0xc0, MCF_IPSBAR + 0x100078); -} - -/***************************************************************************/ - -static void m523x_cpu_reset(void) -{ - local_irq_disable(); - __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR); -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ - mach_reset = m523x_cpu_reset; -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - m523x_fec_init(); -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) - m523x_qspi_init(); -#endif - platform_add_devices(m523x_devices, ARRAY_SIZE(m523x_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/523x/gpio.c b/arch/m68knommu/platform/523x/gpio.c deleted file mode 100644 index 327ebf1..0000000 --- a/arch/m68knommu/platform/523x/gpio.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PIRQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 1, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFEPORT_EPDDR, - .podr = (void __iomem *) MCFEPORT_EPDR, - .ppdr = (void __iomem *) MCFEPORT_EPPDR, - }, - { - .gpio_chip = { - .label = "ADDR", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 13, - .ngpio = 3, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR, - .podr = (void __iomem *) MCFGPIO_PODR_ADDR, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, - .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, - .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR, - }, - { - .gpio_chip = { - .label = "DATAH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 16, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_DATAH, - .podr = (void __iomem *) MCFGPIO_PODR_DATAH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH, - }, - { - .gpio_chip = { - .label = "DATAL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 24, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_DATAL, - .podr = (void __iomem *) MCFGPIO_PODR_DATAL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL, - }, - { - .gpio_chip = { - .label = "BUSCTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 32, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, - .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, - }, - { - .gpio_chip = { - .label = "BS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 40, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BS, - .podr = (void __iomem *) MCFGPIO_PODR_BS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BS, - }, - { - .gpio_chip = { - .label = "CS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 49, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_CS, - .podr = (void __iomem *) MCFGPIO_PODR_CS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, - }, - { - .gpio_chip = { - .label = "SDRAM", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 56, - .ngpio = 6, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM, - .podr = (void __iomem *) MCFGPIO_PODR_SDRAM, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, - .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, - .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM, - }, - { - .gpio_chip = { - .label = "FECI2C", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 64, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, - .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, - }, - { - .gpio_chip = { - .label = "UARTH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 72, - .ngpio = 2, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH, - .podr = (void __iomem *) MCFGPIO_PODR_UARTH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH, - }, - { - .gpio_chip = { - .label = "UARTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 80, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL, - .podr = (void __iomem *) MCFGPIO_PODR_UARTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL, - }, - { - .gpio_chip = { - .label = "QSPI", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 88, - .ngpio = 5, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, - .podr = (void __iomem *) MCFGPIO_PODR_QSPI, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, - }, - { - .gpio_chip = { - .label = "TIMER", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 96, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, - .podr = (void __iomem *) MCFGPIO_PODR_TIMER, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER, - }, - { - .gpio_chip = { - .label = "ETPU", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 104, - .ngpio = 3, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_ETPU, - .podr = (void __iomem *) MCFGPIO_PODR_ETPU, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ETPU, - .setr = (void __iomem *) MCFGPIO_PPDSDR_ETPU, - .clrr = (void __iomem *) MCFGPIO_PCLRR_ETPU, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68knommu/platform/5249/Makefile b/arch/m68knommu/platform/5249/Makefile deleted file mode 100644 index 4bed30f..0000000 --- a/arch/m68knommu/platform/5249/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o intc2.o - diff --git a/arch/m68knommu/platform/5249/config.c b/arch/m68knommu/platform/5249/config.c deleted file mode 100644 index ceb31e5..0000000 --- a/arch/m68knommu/platform/5249/config.c +++ /dev/null @@ -1,330 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/5249/config.c - * - * Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/spi/spi.h> -#include <linux/gpio.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfuart.h> -#include <asm/mcfqspi.h> - -/***************************************************************************/ - -static struct mcf_platform_uart m5249_uart_platform[] = { - { - .mapbase = MCF_MBAR + MCFUART_BASE1, - .irq = 73, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE2, - .irq = 74, - }, - { }, -}; - -static struct platform_device m5249_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m5249_uart_platform, -}; - -#ifdef CONFIG_M5249C3 - -static struct resource m5249_smc91x_resources[] = { - { - .start = 0xe0000300, - .end = 0xe0000300 + 0x100, - .flags = IORESOURCE_MEM, - }, - { - .start = MCFINTC2_GPIOIRQ6, - .end = MCFINTC2_GPIOIRQ6, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device m5249_smc91x = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(m5249_smc91x_resources), - .resource = m5249_smc91x_resources, -}; - -#endif /* CONFIG_M5249C3 */ - -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) -static struct resource m5249_qspi_resources[] = { - { - .start = MCFQSPI_IOBASE, - .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MCF_IRQ_QSPI, - .end = MCF_IRQ_QSPI, - .flags = IORESOURCE_IRQ, - }, -}; - -#define MCFQSPI_CS0 29 -#define MCFQSPI_CS1 24 -#define MCFQSPI_CS2 21 -#define MCFQSPI_CS3 22 - -static int m5249_cs_setup(struct mcfqspi_cs_control *cs_control) -{ - int status; - - status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS0 failed\n"); - goto fail0; - } - status = gpio_direction_output(MCFQSPI_CS0, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n"); - goto fail1; - } - - status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS1 failed\n"); - goto fail1; - } - status = gpio_direction_output(MCFQSPI_CS1, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n"); - goto fail2; - } - - status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS2 failed\n"); - goto fail2; - } - status = gpio_direction_output(MCFQSPI_CS2, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n"); - goto fail3; - } - - status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS3 failed\n"); - goto fail3; - } - status = gpio_direction_output(MCFQSPI_CS3, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n"); - goto fail4; - } - - return 0; - -fail4: - gpio_free(MCFQSPI_CS3); -fail3: - gpio_free(MCFQSPI_CS2); -fail2: - gpio_free(MCFQSPI_CS1); -fail1: - gpio_free(MCFQSPI_CS0); -fail0: - return status; -} - -static void m5249_cs_teardown(struct mcfqspi_cs_control *cs_control) -{ - gpio_free(MCFQSPI_CS3); - gpio_free(MCFQSPI_CS2); - gpio_free(MCFQSPI_CS1); - gpio_free(MCFQSPI_CS0); -} - -static void m5249_cs_select(struct mcfqspi_cs_control *cs_control, - u8 chip_select, bool cs_high) -{ - switch (chip_select) { - case 0: - gpio_set_value(MCFQSPI_CS0, cs_high); - break; - case 1: - gpio_set_value(MCFQSPI_CS1, cs_high); - break; - case 2: - gpio_set_value(MCFQSPI_CS2, cs_high); - break; - case 3: - gpio_set_value(MCFQSPI_CS3, cs_high); - break; - } -} - -static void m5249_cs_deselect(struct mcfqspi_cs_control *cs_control, - u8 chip_select, bool cs_high) -{ - switch (chip_select) { - case 0: - gpio_set_value(MCFQSPI_CS0, !cs_high); - break; - case 1: - gpio_set_value(MCFQSPI_CS1, !cs_high); - break; - case 2: - gpio_set_value(MCFQSPI_CS2, !cs_high); - break; - case 3: - gpio_set_value(MCFQSPI_CS3, !cs_high); - break; - } -} - -static struct mcfqspi_cs_control m5249_cs_control = { - .setup = m5249_cs_setup, - .teardown = m5249_cs_teardown, - .select = m5249_cs_select, - .deselect = m5249_cs_deselect, -}; - -static struct mcfqspi_platform_data m5249_qspi_data = { - .bus_num = 0, - .num_chipselect = 4, - .cs_control = &m5249_cs_control, -}; - -static struct platform_device m5249_qspi = { - .name = "mcfqspi", - .id = 0, - .num_resources = ARRAY_SIZE(m5249_qspi_resources), - .resource = m5249_qspi_resources, - .dev.platform_data = &m5249_qspi_data, -}; - -static void __init m5249_qspi_init(void) -{ - /* QSPI irq setup */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, - MCF_MBAR + MCFSIM_QSPIICR); - mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); -} -#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ - - -static struct platform_device *m5249_devices[] __initdata = { - &m5249_uart, -#ifdef CONFIG_M5249C3 - &m5249_smc91x, -#endif -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) - &m5249_qspi, -#endif -}; - -/***************************************************************************/ - -static void __init m5249_uart_init_line(int line, int irq) -{ - if (line == 0) { - writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); - writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); - mcf_mapirq2imr(irq, MCFINTC_UART0); - } else if (line == 1) { - writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); - writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); - mcf_mapirq2imr(irq, MCFINTC_UART1); - } -} - -static void __init m5249_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m5249_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m5249_uart_init_line(line, m5249_uart_platform[line].irq); -} - -/***************************************************************************/ - -#ifdef CONFIG_M5249C3 - -static void __init m5249_smc91x_init(void) -{ - u32 gpio; - - /* Set the GPIO line as interrupt source for smc91x device */ - gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); - writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); - - gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5); - writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5); -} - -#endif /* CONFIG_M5249C3 */ - -/***************************************************************************/ - -static void __init m5249_timers_init(void) -{ - /* Timer1 is always used as system timer */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, - MCF_MBAR + MCFSIM_TIMER1ICR); - mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1); - -#ifdef CONFIG_HIGHPROFILE - /* Timer2 is to be used as a high speed profile timer */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, - MCF_MBAR + MCFSIM_TIMER2ICR); - mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2); -#endif -} - -/***************************************************************************/ - -void m5249_cpu_reset(void) -{ - local_irq_disable(); - /* Set watchdog to soft reset, and enabled */ - __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR); - for (;;) - /* wait for watchdog to timeout */; -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ - mach_reset = m5249_cpu_reset; - m5249_timers_init(); - m5249_uarts_init(); -#ifdef CONFIG_M5249C3 - m5249_smc91x_init(); -#endif -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) - m5249_qspi_init(); -#endif -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/5249/gpio.c b/arch/m68knommu/platform/5249/gpio.c deleted file mode 100644 index 2b56c6e..0000000 --- a/arch/m68knommu/platform/5249/gpio.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "GPIO0", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 32, - }, - .pddr = (void __iomem *) MCFSIM2_GPIOENABLE, - .podr = (void __iomem *) MCFSIM2_GPIOWRITE, - .ppdr = (void __iomem *) MCFSIM2_GPIOREAD, - }, - { - .gpio_chip = { - .label = "GPIO1", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 32, - .ngpio = 32, - }, - .pddr = (void __iomem *) MCFSIM2_GPIO1ENABLE, - .podr = (void __iomem *) MCFSIM2_GPIO1WRITE, - .ppdr = (void __iomem *) MCFSIM2_GPIO1READ, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68knommu/platform/5249/intc2.c b/arch/m68knommu/platform/5249/intc2.c deleted file mode 100644 index 8f4b63e..0000000 --- a/arch/m68knommu/platform/5249/intc2.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * intc2.c -- support for the 2nd INTC controller of the 5249 - * - * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> - -static void intc2_irq_gpio_mask(struct irq_data *d) -{ - u32 imr; - imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); - imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); - writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); -} - -static void intc2_irq_gpio_unmask(struct irq_data *d) -{ - u32 imr; - imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); - imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); - writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); -} - -static void intc2_irq_gpio_ack(struct irq_data *d) -{ - writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR); -} - -static struct irq_chip intc2_irq_gpio_chip = { - .name = "CF-INTC2", - .irq_mask = intc2_irq_gpio_mask, - .irq_unmask = intc2_irq_gpio_unmask, - .irq_ack = intc2_irq_gpio_ack, -}; - -static int __init mcf_intc2_init(void) -{ - int irq; - - /* GPIO interrupt sources */ - for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) { - set_irq_chip(irq, &intc2_irq_gpio_chip); - set_irq_handler(irq, handle_edge_irq); - } - - return 0; -} - -arch_initcall(mcf_intc2_init); diff --git a/arch/m68knommu/platform/5272/Makefile b/arch/m68knommu/platform/5272/Makefile deleted file mode 100644 index 34110fc..0000000 --- a/arch/m68knommu/platform/5272/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o intc.o - diff --git a/arch/m68knommu/platform/5272/config.c b/arch/m68knommu/platform/5272/config.c deleted file mode 100644 index 65bb582..0000000 --- a/arch/m68knommu/platform/5272/config.c +++ /dev/null @@ -1,176 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/5272/config.c - * - * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) - * Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/phy.h> -#include <linux/phy_fixed.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfuart.h> - -/***************************************************************************/ - -/* - * Some platforms need software versions of the GPIO data registers. - */ -unsigned short ppdata; -unsigned char ledbank = 0xff; - -/***************************************************************************/ - -static struct mcf_platform_uart m5272_uart_platform[] = { - { - .mapbase = MCF_MBAR + MCFUART_BASE1, - .irq = MCF_IRQ_UART1, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE2, - .irq = MCF_IRQ_UART2, - }, - { }, -}; - -static struct platform_device m5272_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m5272_uart_platform, -}; - -static struct resource m5272_fec_resources[] = { - { - .start = MCF_MBAR + 0x840, - .end = MCF_MBAR + 0x840 + 0x1cf, - .flags = IORESOURCE_MEM, - }, - { - .start = MCF_IRQ_ERX, - .end = MCF_IRQ_ERX, - .flags = IORESOURCE_IRQ, - }, - { - .start = MCF_IRQ_ETX, - .end = MCF_IRQ_ETX, - .flags = IORESOURCE_IRQ, - }, - { - .start = MCF_IRQ_ENTC, - .end = MCF_IRQ_ENTC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device m5272_fec = { - .name = "fec", - .id = 0, - .num_resources = ARRAY_SIZE(m5272_fec_resources), - .resource = m5272_fec_resources, -}; - -static struct platform_device *m5272_devices[] __initdata = { - &m5272_uart, - &m5272_fec, -}; - -/***************************************************************************/ - -static void __init m5272_uart_init_line(int line, int irq) -{ - u32 v; - - if ((line >= 0) && (line < 2)) { - /* Enable the output lines for the serial ports */ - v = readl(MCF_MBAR + MCFSIM_PBCNT); - v = (v & ~0x000000ff) | 0x00000055; - writel(v, MCF_MBAR + MCFSIM_PBCNT); - - v = readl(MCF_MBAR + MCFSIM_PDCNT); - v = (v & ~0x000003fc) | 0x000002a8; - writel(v, MCF_MBAR + MCFSIM_PDCNT); - } -} - -static void __init m5272_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m5272_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m5272_uart_init_line(line, m5272_uart_platform[line].irq); -} - -/***************************************************************************/ - -static void m5272_cpu_reset(void) -{ - local_irq_disable(); - /* Set watchdog to reset, and enabled */ - __raw_writew(0, MCF_MBAR + MCFSIM_WIRR); - __raw_writew(1, MCF_MBAR + MCFSIM_WRRR); - __raw_writew(0, MCF_MBAR + MCFSIM_WCR); - for (;;) - /* wait for watchdog to timeout */; -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ -#if defined (CONFIG_MOD5272) - volatile unsigned char *pivrp; - - /* Set base of device vectors to be 64 */ - pivrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_PIVR); - *pivrp = 0x40; -#endif - -#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES) - /* Copy command line from FLASH to local buffer... */ - memcpy(commandp, (char *) 0xf0004000, size); - commandp[size-1] = 0; -#elif defined(CONFIG_CANCam) - /* Copy command line from FLASH to local buffer... */ - memcpy(commandp, (char *) 0xf0010000, size); - commandp[size-1] = 0; -#endif - - mach_reset = m5272_cpu_reset; -} - -/***************************************************************************/ - -/* - * Some 5272 based boards have the FEC ethernet diectly connected to - * an ethernet switch. In this case we need to use the fixed phy type, - * and we need to declare it early in boot. - */ -static struct fixed_phy_status nettel_fixed_phy_status __initdata = { - .link = 1, - .speed = 100, - .duplex = 0, -}; - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - m5272_uarts_init(); - fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status); - platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/5272/gpio.c b/arch/m68knommu/platform/5272/gpio.c deleted file mode 100644 index 57ac10a..0000000 --- a/arch/m68knommu/platform/5272/gpio.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PA", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 16, - }, - .pddr = (void __iomem *) MCFSIM_PADDR, - .podr = (void __iomem *) MCFSIM_PADAT, - .ppdr = (void __iomem *) MCFSIM_PADAT, - }, - { - .gpio_chip = { - .label = "PB", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 16, - .ngpio = 16, - }, - .pddr = (void __iomem *) MCFSIM_PBDDR, - .podr = (void __iomem *) MCFSIM_PBDAT, - .ppdr = (void __iomem *) MCFSIM_PBDAT, - }, - { - .gpio_chip = { - .label = "PC", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 32, - .ngpio = 16, - }, - .pddr = (void __iomem *) MCFSIM_PCDDR, - .podr = (void __iomem *) MCFSIM_PCDAT, - .ppdr = (void __iomem *) MCFSIM_PCDAT, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68knommu/platform/5272/intc.c b/arch/m68knommu/platform/5272/intc.c deleted file mode 100644 index 969ff0a..0000000 --- a/arch/m68knommu/platform/5272/intc.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * intc.c -- interrupt controller or ColdFire 5272 SoC - * - * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/kernel_stat.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/traps.h> - -/* - * The 5272 ColdFire interrupt controller is nothing like any other - * ColdFire interrupt controller - it truly is completely different. - * Given its age it is unlikely to be used on any other ColdFire CPU. - */ - -/* - * The masking and priproty setting of interrupts on the 5272 is done - * via a set of 4 "Interrupt Controller Registers" (ICR). There is a - * loose mapping of vector number to register and internal bits, but - * a table is the easiest and quickest way to map them. - * - * Note that the external interrupts are edge triggered (unlike the - * internal interrupt sources which are level triggered). Which means - * they also need acknowledgeing via acknowledge bits. - */ -struct irqmap { - unsigned char icr; - unsigned char index; - unsigned char ack; -}; - -static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = { - /*MCF_IRQ_SPURIOUS*/ { .icr = 0, .index = 0, .ack = 0, }, - /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, }, - /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, }, - /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, }, - /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, }, - /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, }, - /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, }, - /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, }, - /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, }, - /*MCF_IRQ_UART1*/ { .icr = MCFSIM_ICR2, .index = 28, .ack = 0, }, - /*MCF_IRQ_UART2*/ { .icr = MCFSIM_ICR2, .index = 24, .ack = 0, }, - /*MCF_IRQ_PLIP*/ { .icr = MCFSIM_ICR2, .index = 20, .ack = 0, }, - /*MCF_IRQ_PLIA*/ { .icr = MCFSIM_ICR2, .index = 16, .ack = 0, }, - /*MCF_IRQ_USB0*/ { .icr = MCFSIM_ICR2, .index = 12, .ack = 0, }, - /*MCF_IRQ_USB1*/ { .icr = MCFSIM_ICR2, .index = 8, .ack = 0, }, - /*MCF_IRQ_USB2*/ { .icr = MCFSIM_ICR2, .index = 4, .ack = 0, }, - /*MCF_IRQ_USB3*/ { .icr = MCFSIM_ICR2, .index = 0, .ack = 0, }, - /*MCF_IRQ_USB4*/ { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, }, - /*MCF_IRQ_USB5*/ { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, }, - /*MCF_IRQ_USB6*/ { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, }, - /*MCF_IRQ_USB7*/ { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, }, - /*MCF_IRQ_DMA*/ { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, }, - /*MCF_IRQ_ERX*/ { .icr = MCFSIM_ICR3, .index = 8, .ack = 0, }, - /*MCF_IRQ_ETX*/ { .icr = MCFSIM_ICR3, .index = 4, .ack = 0, }, - /*MCF_IRQ_ENTC*/ { .icr = MCFSIM_ICR3, .index = 0, .ack = 0, }, - /*MCF_IRQ_QSPI*/ { .icr = MCFSIM_ICR4, .index = 28, .ack = 0, }, - /*MCF_IRQ_EINT5*/ { .icr = MCFSIM_ICR4, .index = 24, .ack = 1, }, - /*MCF_IRQ_EINT6*/ { .icr = MCFSIM_ICR4, .index = 20, .ack = 1, }, - /*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, }, -}; - -/* - * The act of masking the interrupt also has a side effect of 'ack'ing - * an interrupt on this irq (for the external irqs). So this mask function - * is also an ack_mask function. - */ -static void intc_irq_mask(struct irq_data *d) -{ - unsigned int irq = d->irq; - - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { - u32 v; - irq -= MCFINT_VECBASE; - v = 0x8 << intc_irqmap[irq].index; - writel(v, MCF_MBAR + intc_irqmap[irq].icr); - } -} - -static void intc_irq_unmask(struct irq_data *d) -{ - unsigned int irq = d->irq; - - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { - u32 v; - irq -= MCFINT_VECBASE; - v = 0xd << intc_irqmap[irq].index; - writel(v, MCF_MBAR + intc_irqmap[irq].icr); - } -} - -static void intc_irq_ack(struct irq_data *d) -{ - unsigned int irq = d->irq; - - /* Only external interrupts are acked */ - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { - irq -= MCFINT_VECBASE; - if (intc_irqmap[irq].ack) { - u32 v; - v = readl(MCF_MBAR + intc_irqmap[irq].icr); - v &= (0x7 << intc_irqmap[irq].index); - v |= (0x8 << intc_irqmap[irq].index); - writel(v, MCF_MBAR + intc_irqmap[irq].icr); - } - } -} - -static int intc_irq_set_type(struct irq_data *d, unsigned int type) -{ - unsigned int irq = d->irq; - - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { - irq -= MCFINT_VECBASE; - if (intc_irqmap[irq].ack) { - u32 v; - v = readl(MCF_MBAR + MCFSIM_PITR); - if (type == IRQ_TYPE_EDGE_FALLING) - v &= ~(0x1 << (32 - irq)); - else - v |= (0x1 << (32 - irq)); - writel(v, MCF_MBAR + MCFSIM_PITR); - } - } - return 0; -} - -/* - * Simple flow handler to deal with the external edge triggered interrupts. - * We need to be careful with the masking/acking due to the side effects - * of masking an interrupt. - */ -static void intc_external_irq(unsigned int irq, struct irq_desc *desc) -{ - get_irq_desc_chip(desc)->irq_ack(&desc->irq_data); - handle_simple_irq(irq, desc); -} - -static struct irq_chip intc_irq_chip = { - .name = "CF-INTC", - .irq_mask = intc_irq_mask, - .irq_unmask = intc_irq_unmask, - .irq_mask_ack = intc_irq_mask, - .irq_ack = intc_irq_ack, - .irq_set_type = intc_irq_set_type, -}; - -void __init init_IRQ(void) -{ - int irq, edge; - - init_vectors(); - - /* Mask all interrupt sources */ - writel(0x88888888, MCF_MBAR + MCFSIM_ICR1); - writel(0x88888888, MCF_MBAR + MCFSIM_ICR2); - writel(0x88888888, MCF_MBAR + MCFSIM_ICR3); - writel(0x88888888, MCF_MBAR + MCFSIM_ICR4); - - for (irq = 0; (irq < NR_IRQS); irq++) { - set_irq_chip(irq, &intc_irq_chip); - edge = 0; - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) - edge = intc_irqmap[irq - MCFINT_VECBASE].ack; - if (edge) { - set_irq_type(irq, IRQ_TYPE_EDGE_RISING); - set_irq_handler(irq, intc_external_irq); - } else { - set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); - set_irq_handler(irq, handle_level_irq); - } - } -} - diff --git a/arch/m68knommu/platform/527x/Makefile b/arch/m68knommu/platform/527x/Makefile deleted file mode 100644 index 6ac4b57..0000000 --- a/arch/m68knommu/platform/527x/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o - diff --git a/arch/m68knommu/platform/527x/config.c b/arch/m68knommu/platform/527x/config.c deleted file mode 100644 index fa35959..0000000 --- a/arch/m68knommu/platform/527x/config.c +++ /dev/null @@ -1,384 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/527x/config.c - * - * Sub-architcture dependant initialization code for the Freescale - * 5270/5271 CPUs. - * - * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com) - * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/spi/spi.h> -#include <linux/gpio.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfuart.h> -#include <asm/mcfqspi.h> - -/***************************************************************************/ - -static struct mcf_platform_uart m527x_uart_platform[] = { - { - .mapbase = MCFUART_BASE1, - .irq = MCFINT_VECBASE + MCFINT_UART0, - }, - { - .mapbase = MCFUART_BASE2, - .irq = MCFINT_VECBASE + MCFINT_UART1, - }, - { - .mapbase = MCFUART_BASE3, - .irq = MCFINT_VECBASE + MCFINT_UART2, - }, - { }, -}; - -static struct platform_device m527x_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m527x_uart_platform, -}; - -static struct resource m527x_fec0_resources[] = { - { - .start = MCFFEC_BASE0, - .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = 64 + 23, - .end = 64 + 23, - .flags = IORESOURCE_IRQ, - }, - { - .start = 64 + 27, - .end = 64 + 27, - .flags = IORESOURCE_IRQ, - }, - { - .start = 64 + 29, - .end = 64 + 29, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource m527x_fec1_resources[] = { - { - .start = MCFFEC_BASE1, - .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = 128 + 23, - .end = 128 + 23, - .flags = IORESOURCE_IRQ, - }, - { - .start = 128 + 27, - .end = 128 + 27, - .flags = IORESOURCE_IRQ, - }, - { - .start = 128 + 29, - .end = 128 + 29, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device m527x_fec[] = { - { - .name = "fec", - .id = 0, - .num_resources = ARRAY_SIZE(m527x_fec0_resources), - .resource = m527x_fec0_resources, - }, - { - .name = "fec", - .id = 1, - .num_resources = ARRAY_SIZE(m527x_fec1_resources), - .resource = m527x_fec1_resources, - }, -}; - -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) -static struct resource m527x_qspi_resources[] = { - { - .start = MCFQSPI_IOBASE, - .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MCFINT_VECBASE + MCFINT_QSPI, - .end = MCFINT_VECBASE + MCFINT_QSPI, - .flags = IORESOURCE_IRQ, - }, -}; - -#if defined(CONFIG_M5271) -#define MCFQSPI_CS0 91 -#define MCFQSPI_CS1 92 -#define MCFQSPI_CS2 99 -#define MCFQSPI_CS3 103 -#elif defined(CONFIG_M5275) -#define MCFQSPI_CS0 59 -#define MCFQSPI_CS1 60 -#define MCFQSPI_CS2 61 -#define MCFQSPI_CS3 62 -#endif - -static int m527x_cs_setup(struct mcfqspi_cs_control *cs_control) -{ - int status; - - status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS0 failed\n"); - goto fail0; - } - status = gpio_direction_output(MCFQSPI_CS0, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n"); - goto fail1; - } - - status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS1 failed\n"); - goto fail1; - } - status = gpio_direction_output(MCFQSPI_CS1, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n"); - goto fail2; - } - - status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS2 failed\n"); - goto fail2; - } - status = gpio_direction_output(MCFQSPI_CS2, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n"); - goto fail3; - } - - status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS3 failed\n"); - goto fail3; - } - status = gpio_direction_output(MCFQSPI_CS3, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n"); - goto fail4; - } - - return 0; - -fail4: - gpio_free(MCFQSPI_CS3); -fail3: - gpio_free(MCFQSPI_CS2); -fail2: - gpio_free(MCFQSPI_CS1); -fail1: - gpio_free(MCFQSPI_CS0); -fail0: - return status; -} - -static void m527x_cs_teardown(struct mcfqspi_cs_control *cs_control) -{ - gpio_free(MCFQSPI_CS3); - gpio_free(MCFQSPI_CS2); - gpio_free(MCFQSPI_CS1); - gpio_free(MCFQSPI_CS0); -} - -static void m527x_cs_select(struct mcfqspi_cs_control *cs_control, - u8 chip_select, bool cs_high) -{ - switch (chip_select) { - case 0: - gpio_set_value(MCFQSPI_CS0, cs_high); - break; - case 1: - gpio_set_value(MCFQSPI_CS1, cs_high); - break; - case 2: - gpio_set_value(MCFQSPI_CS2, cs_high); - break; - case 3: - gpio_set_value(MCFQSPI_CS3, cs_high); - break; - } -} - -static void m527x_cs_deselect(struct mcfqspi_cs_control *cs_control, - u8 chip_select, bool cs_high) -{ - switch (chip_select) { - case 0: - gpio_set_value(MCFQSPI_CS0, !cs_high); - break; - case 1: - gpio_set_value(MCFQSPI_CS1, !cs_high); - break; - case 2: - gpio_set_value(MCFQSPI_CS2, !cs_high); - break; - case 3: - gpio_set_value(MCFQSPI_CS3, !cs_high); - break; - } -} - -static struct mcfqspi_cs_control m527x_cs_control = { - .setup = m527x_cs_setup, - .teardown = m527x_cs_teardown, - .select = m527x_cs_select, - .deselect = m527x_cs_deselect, -}; - -static struct mcfqspi_platform_data m527x_qspi_data = { - .bus_num = 0, - .num_chipselect = 4, - .cs_control = &m527x_cs_control, -}; - -static struct platform_device m527x_qspi = { - .name = "mcfqspi", - .id = 0, - .num_resources = ARRAY_SIZE(m527x_qspi_resources), - .resource = m527x_qspi_resources, - .dev.platform_data = &m527x_qspi_data, -}; - -static void __init m527x_qspi_init(void) -{ -#if defined(CONFIG_M5271) - u16 par; - - /* setup QSPS pins for QSPI with gpio CS control */ - writeb(0x1f, MCFGPIO_PAR_QSPI); - /* and CS2 & CS3 as gpio */ - par = readw(MCFGPIO_PAR_TIMER); - par &= 0x3f3f; - writew(par, MCFGPIO_PAR_TIMER); -#elif defined(CONFIG_M5275) - /* setup QSPS pins for QSPI with gpio CS control */ - writew(0x003e, MCFGPIO_PAR_QSPI); -#endif -} -#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ - -static struct platform_device *m527x_devices[] __initdata = { - &m527x_uart, - &m527x_fec[0], -#ifdef CONFIG_FEC2 - &m527x_fec[1], -#endif -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) - &m527x_qspi, -#endif -}; - -/***************************************************************************/ - -static void __init m527x_uart_init_line(int line, int irq) -{ - u16 sepmask; - - if ((line < 0) || (line > 2)) - return; - - /* - * External Pin Mask Setting & Enable External Pin for Interface - */ - sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); - if (line == 0) - sepmask |= UART0_ENABLE_MASK; - else if (line == 1) - sepmask |= UART1_ENABLE_MASK; - else if (line == 2) - sepmask |= UART2_ENABLE_MASK; - writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART); -} - -static void __init m527x_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m527x_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m527x_uart_init_line(line, m527x_uart_platform[line].irq); -} - -/***************************************************************************/ - -static void __init m527x_fec_init(void) -{ - u16 par; - u8 v; - - /* Set multi-function pins to ethernet mode for fec0 */ -#if defined(CONFIG_M5271) - v = readb(MCF_IPSBAR + 0x100047); - writeb(v | 0xf0, MCF_IPSBAR + 0x100047); -#else - par = readw(MCF_IPSBAR + 0x100082); - writew(par | 0xf00, MCF_IPSBAR + 0x100082); - v = readb(MCF_IPSBAR + 0x100078); - writeb(v | 0xc0, MCF_IPSBAR + 0x100078); -#endif - -#ifdef CONFIG_FEC2 - /* Set multi-function pins to ethernet mode for fec1 */ - par = readw(MCF_IPSBAR + 0x100082); - writew(par | 0xa0, MCF_IPSBAR + 0x100082); - v = readb(MCF_IPSBAR + 0x100079); - writeb(v | 0xc0, MCF_IPSBAR + 0x100079); -#endif -} - -/***************************************************************************/ - -static void m527x_cpu_reset(void) -{ - local_irq_disable(); - __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR); -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ - mach_reset = m527x_cpu_reset; - m527x_uarts_init(); - m527x_fec_init(); -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) - m527x_qspi_init(); -#endif -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/527x/gpio.c b/arch/m68knommu/platform/527x/gpio.c deleted file mode 100644 index 205da0a..0000000 --- a/arch/m68knommu/platform/527x/gpio.c +++ /dev/null @@ -1,609 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { -#if defined(CONFIG_M5271) - { - .gpio_chip = { - .label = "PIRQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 1, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFEPORT_EPDDR, - .podr = (void __iomem *) MCFEPORT_EPDR, - .ppdr = (void __iomem *) MCFEPORT_EPPDR, - }, - { - .gpio_chip = { - .label = "ADDR", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 13, - .ngpio = 3, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR, - .podr = (void __iomem *) MCFGPIO_PODR_ADDR, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, - .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, - .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR, - }, - { - .gpio_chip = { - .label = "DATAH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 16, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_DATAH, - .podr = (void __iomem *) MCFGPIO_PODR_DATAH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH, - }, - { - .gpio_chip = { - .label = "DATAL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 24, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_DATAL, - .podr = (void __iomem *) MCFGPIO_PODR_DATAL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL, - }, - { - .gpio_chip = { - .label = "BUSCTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 32, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, - .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, - }, - { - .gpio_chip = { - .label = "BS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 40, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BS, - .podr = (void __iomem *) MCFGPIO_PODR_BS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BS, - }, - { - .gpio_chip = { - .label = "CS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 49, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_CS, - .podr = (void __iomem *) MCFGPIO_PODR_CS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, - }, - { - .gpio_chip = { - .label = "SDRAM", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 56, - .ngpio = 6, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM, - .podr = (void __iomem *) MCFGPIO_PODR_SDRAM, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, - .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, - .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM, - }, - { - .gpio_chip = { - .label = "FECI2C", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 64, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, - .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, - }, - { - .gpio_chip = { - .label = "UARTH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 72, - .ngpio = 2, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH, - .podr = (void __iomem *) MCFGPIO_PODR_UARTH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH, - }, - { - .gpio_chip = { - .label = "UARTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 80, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL, - .podr = (void __iomem *) MCFGPIO_PODR_UARTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL, - }, - { - .gpio_chip = { - .label = "QSPI", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 88, - .ngpio = 5, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, - .podr = (void __iomem *) MCFGPIO_PODR_QSPI, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, - }, - { - .gpio_chip = { - .label = "TIMER", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 96, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, - .podr = (void __iomem *) MCFGPIO_PODR_TIMER, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER, - }, -#elif defined(CONFIG_M5275) - { - .gpio_chip = { - .label = "PIRQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 1, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFEPORT_EPDDR, - .podr = (void __iomem *) MCFEPORT_EPDR, - .ppdr = (void __iomem *) MCFEPORT_EPPDR, - }, - { - .gpio_chip = { - .label = "BUSCTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 8, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, - .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, - }, - { - .gpio_chip = { - .label = "ADDR", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 21, - .ngpio = 3, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR, - .podr = (void __iomem *) MCFGPIO_PODR_ADDR, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, - .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, - .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR, - }, - { - .gpio_chip = { - .label = "CS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 25, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_CS, - .podr = (void __iomem *) MCFGPIO_PODR_CS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, - }, - { - .gpio_chip = { - .label = "FEC0H", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 32, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0H, - .podr = (void __iomem *) MCFGPIO_PODR_FEC0H, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0H, - }, - { - .gpio_chip = { - .label = "FEC0L", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 40, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0L, - .podr = (void __iomem *) MCFGPIO_PODR_FEC0L, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0L, - }, - { - .gpio_chip = { - .label = "FECI2C", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 48, - .ngpio = 6, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, - .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, - }, - { - .gpio_chip = { - .label = "QSPI", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 56, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, - .podr = (void __iomem *) MCFGPIO_PODR_QSPI, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, - }, - { - .gpio_chip = { - .label = "SDRAM", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 64, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM, - .podr = (void __iomem *) MCFGPIO_PODR_SDRAM, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, - .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, - .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM, - }, - { - .gpio_chip = { - .label = "TIMERH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 72, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERH, - .podr = (void __iomem *) MCFGPIO_PODR_TIMERH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERH, - }, - { - .gpio_chip = { - .label = "TIMERL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 80, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERL, - .podr = (void __iomem *) MCFGPIO_PODR_TIMERL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERL, - }, - { - .gpio_chip = { - .label = "UARTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 88, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL, - .podr = (void __iomem *) MCFGPIO_PODR_UARTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL, - }, - { - .gpio_chip = { - .label = "FEC1H", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 96, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1H, - .podr = (void __iomem *) MCFGPIO_PODR_FEC1H, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1H, - }, - { - .gpio_chip = { - .label = "FEC1L", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 104, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1L, - .podr = (void __iomem *) MCFGPIO_PODR_FEC1L, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1L, - }, - { - .gpio_chip = { - .label = "BS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 114, - .ngpio = 2, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BS, - .podr = (void __iomem *) MCFGPIO_PODR_BS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BS, - }, - { - .gpio_chip = { - .label = "IRQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 121, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_IRQ, - .podr = (void __iomem *) MCFGPIO_PODR_IRQ, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_IRQ, - .setr = (void __iomem *) MCFGPIO_PPDSDR_IRQ, - .clrr = (void __iomem *) MCFGPIO_PCLRR_IRQ, - }, - { - .gpio_chip = { - .label = "USBH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 128, - .ngpio = 1, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_USBH, - .podr = (void __iomem *) MCFGPIO_PODR_USBH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_USBH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_USBH, - }, - { - .gpio_chip = { - .label = "USBL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 136, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_USBL, - .podr = (void __iomem *) MCFGPIO_PODR_USBL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_USBL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_USBL, - }, - { - .gpio_chip = { - .label = "UARTH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 144, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH, - .podr = (void __iomem *) MCFGPIO_PODR_UARTH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH, - }, -#endif -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68knommu/platform/528x/Makefile b/arch/m68knommu/platform/528x/Makefile deleted file mode 100644 index 6ac4b57..0000000 --- a/arch/m68knommu/platform/528x/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o - diff --git a/arch/m68knommu/platform/528x/config.c b/arch/m68knommu/platform/528x/config.c deleted file mode 100644 index ac39fc6..0000000 --- a/arch/m68knommu/platform/528x/config.c +++ /dev/null @@ -1,320 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/528x/config.c - * - * Sub-architcture dependant initialization code for the Freescale - * 5280, 5281 and 5282 CPUs. - * - * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com) - * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/spi/spi.h> -#include <linux/gpio.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfuart.h> -#include <asm/mcfqspi.h> - -/***************************************************************************/ - -static struct mcf_platform_uart m528x_uart_platform[] = { - { - .mapbase = MCFUART_BASE1, - .irq = MCFINT_VECBASE + MCFINT_UART0, - }, - { - .mapbase = MCFUART_BASE2, - .irq = MCFINT_VECBASE + MCFINT_UART0 + 1, - }, - { - .mapbase = MCFUART_BASE3, - .irq = MCFINT_VECBASE + MCFINT_UART0 + 2, - }, - { }, -}; - -static struct platform_device m528x_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m528x_uart_platform, -}; - -static struct resource m528x_fec_resources[] = { - { - .start = MCFFEC_BASE, - .end = MCFFEC_BASE + MCFFEC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = 64 + 23, - .end = 64 + 23, - .flags = IORESOURCE_IRQ, - }, - { - .start = 64 + 27, - .end = 64 + 27, - .flags = IORESOURCE_IRQ, - }, - { - .start = 64 + 29, - .end = 64 + 29, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device m528x_fec = { - .name = "fec", - .id = 0, - .num_resources = ARRAY_SIZE(m528x_fec_resources), - .resource = m528x_fec_resources, -}; - -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) -static struct resource m528x_qspi_resources[] = { - { - .start = MCFQSPI_IOBASE, - .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MCFINT_VECBASE + MCFINT_QSPI, - .end = MCFINT_VECBASE + MCFINT_QSPI, - .flags = IORESOURCE_IRQ, - }, -}; - -#define MCFQSPI_CS0 147 -#define MCFQSPI_CS1 148 -#define MCFQSPI_CS2 149 -#define MCFQSPI_CS3 150 - -static int m528x_cs_setup(struct mcfqspi_cs_control *cs_control) -{ - int status; - - status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS0 failed\n"); - goto fail0; - } - status = gpio_direction_output(MCFQSPI_CS0, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n"); - goto fail1; - } - - status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS1 failed\n"); - goto fail1; - } - status = gpio_direction_output(MCFQSPI_CS1, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n"); - goto fail2; - } - - status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS2 failed\n"); - goto fail2; - } - status = gpio_direction_output(MCFQSPI_CS2, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n"); - goto fail3; - } - - status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS3 failed\n"); - goto fail3; - } - status = gpio_direction_output(MCFQSPI_CS3, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n"); - goto fail4; - } - - return 0; - -fail4: - gpio_free(MCFQSPI_CS3); -fail3: - gpio_free(MCFQSPI_CS2); -fail2: - gpio_free(MCFQSPI_CS1); -fail1: - gpio_free(MCFQSPI_CS0); -fail0: - return status; -} - -static void m528x_cs_teardown(struct mcfqspi_cs_control *cs_control) -{ - gpio_free(MCFQSPI_CS3); - gpio_free(MCFQSPI_CS2); - gpio_free(MCFQSPI_CS1); - gpio_free(MCFQSPI_CS0); -} - -static void m528x_cs_select(struct mcfqspi_cs_control *cs_control, - u8 chip_select, bool cs_high) -{ - gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high); -} - -static void m528x_cs_deselect(struct mcfqspi_cs_control *cs_control, - u8 chip_select, bool cs_high) -{ - gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high); -} - -static struct mcfqspi_cs_control m528x_cs_control = { - .setup = m528x_cs_setup, - .teardown = m528x_cs_teardown, - .select = m528x_cs_select, - .deselect = m528x_cs_deselect, -}; - -static struct mcfqspi_platform_data m528x_qspi_data = { - .bus_num = 0, - .num_chipselect = 4, - .cs_control = &m528x_cs_control, -}; - -static struct platform_device m528x_qspi = { - .name = "mcfqspi", - .id = 0, - .num_resources = ARRAY_SIZE(m528x_qspi_resources), - .resource = m528x_qspi_resources, - .dev.platform_data = &m528x_qspi_data, -}; - -static void __init m528x_qspi_init(void) -{ - /* setup Port QS for QSPI with gpio CS control */ - __raw_writeb(0x07, MCFGPIO_PQSPAR); -} -#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ - -static struct platform_device *m528x_devices[] __initdata = { - &m528x_uart, - &m528x_fec, -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) - &m528x_qspi, -#endif -}; - -/***************************************************************************/ - -static void __init m528x_uart_init_line(int line, int irq) -{ - u8 port; - - if ((line < 0) || (line > 2)) - return; - - /* make sure PUAPAR is set for UART0 and UART1 */ - if (line < 2) { - port = readb(MCF5282_GPIO_PUAPAR); - port |= (0x03 << (line * 2)); - writeb(port, MCF5282_GPIO_PUAPAR); - } -} - -static void __init m528x_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m528x_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m528x_uart_init_line(line, m528x_uart_platform[line].irq); -} - -/***************************************************************************/ - -static void __init m528x_fec_init(void) -{ - u16 v16; - - /* Set multi-function pins to ethernet mode for fec0 */ - v16 = readw(MCF_IPSBAR + 0x100056); - writew(v16 | 0xf00, MCF_IPSBAR + 0x100056); - writeb(0xc0, MCF_IPSBAR + 0x100058); -} - -/***************************************************************************/ - -static void m528x_cpu_reset(void) -{ - local_irq_disable(); - __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR); -} - -/***************************************************************************/ - -#ifdef CONFIG_WILDFIRE -void wildfire_halt(void) -{ - writeb(0, 0x30000007); - writeb(0x2, 0x30000007); -} -#endif - -#ifdef CONFIG_WILDFIREMOD -void wildfiremod_halt(void) -{ - printk(KERN_INFO "WildFireMod hibernating...\n"); - - /* Set portE.5 to Digital IO */ - MCF5282_GPIO_PEPAR &= ~(1 << (5 * 2)); - - /* Make portE.5 an output */ - MCF5282_GPIO_DDRE |= (1 << 5); - - /* Now toggle portE.5 from low to high */ - MCF5282_GPIO_PORTE &= ~(1 << 5); - MCF5282_GPIO_PORTE |= (1 << 5); - - printk(KERN_EMERG "Failed to hibernate. Halting!\n"); -} -#endif - -void __init config_BSP(char *commandp, int size) -{ -#ifdef CONFIG_WILDFIRE - mach_halt = wildfire_halt; -#endif -#ifdef CONFIG_WILDFIREMOD - mach_halt = wildfiremod_halt; -#endif -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - mach_reset = m528x_cpu_reset; - m528x_uarts_init(); - m528x_fec_init(); -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) - m528x_qspi_init(); -#endif - platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/528x/gpio.c b/arch/m68knommu/platform/528x/gpio.c deleted file mode 100644 index 526db66..0000000 --- a/arch/m68knommu/platform/528x/gpio.c +++ /dev/null @@ -1,438 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "NQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 1, - .ngpio = 7, - }, - .pddr = (void __iomem *)MCFEPORT_EPDDR, - .podr = (void __iomem *)MCFEPORT_EPDR, - .ppdr = (void __iomem *)MCFEPORT_EPPDR, - }, - { - .gpio_chip = { - .label = "TA", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 8, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPTA_GPTDDR, - .podr = (void __iomem *)MCFGPTA_GPTPORT, - .ppdr = (void __iomem *)MCFGPTB_GPTPORT, - }, - { - .gpio_chip = { - .label = "TB", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 16, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPTB_GPTDDR, - .podr = (void __iomem *)MCFGPTB_GPTPORT, - .ppdr = (void __iomem *)MCFGPTB_GPTPORT, - }, - { - .gpio_chip = { - .label = "QA", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 24, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFQADC_DDRQA, - .podr = (void __iomem *)MCFQADC_PORTQA, - .ppdr = (void __iomem *)MCFQADC_PORTQA, - }, - { - .gpio_chip = { - .label = "QB", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 32, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFQADC_DDRQB, - .podr = (void __iomem *)MCFQADC_PORTQB, - .ppdr = (void __iomem *)MCFQADC_PORTQB, - }, - { - .gpio_chip = { - .label = "A", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 40, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRA, - .podr = (void __iomem *)MCFGPIO_PORTA, - .ppdr = (void __iomem *)MCFGPIO_PORTAP, - .setr = (void __iomem *)MCFGPIO_SETA, - .clrr = (void __iomem *)MCFGPIO_CLRA, - }, - { - .gpio_chip = { - .label = "B", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 48, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRB, - .podr = (void __iomem *)MCFGPIO_PORTB, - .ppdr = (void __iomem *)MCFGPIO_PORTBP, - .setr = (void __iomem *)MCFGPIO_SETB, - .clrr = (void __iomem *)MCFGPIO_CLRB, - }, - { - .gpio_chip = { - .label = "C", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 56, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRC, - .podr = (void __iomem *)MCFGPIO_PORTC, - .ppdr = (void __iomem *)MCFGPIO_PORTCP, - .setr = (void __iomem *)MCFGPIO_SETC, - .clrr = (void __iomem *)MCFGPIO_CLRC, - }, - { - .gpio_chip = { - .label = "D", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 64, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRD, - .podr = (void __iomem *)MCFGPIO_PORTD, - .ppdr = (void __iomem *)MCFGPIO_PORTDP, - .setr = (void __iomem *)MCFGPIO_SETD, - .clrr = (void __iomem *)MCFGPIO_CLRD, - }, - { - .gpio_chip = { - .label = "E", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 72, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRE, - .podr = (void __iomem *)MCFGPIO_PORTE, - .ppdr = (void __iomem *)MCFGPIO_PORTEP, - .setr = (void __iomem *)MCFGPIO_SETE, - .clrr = (void __iomem *)MCFGPIO_CLRE, - }, - { - .gpio_chip = { - .label = "F", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 80, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRF, - .podr = (void __iomem *)MCFGPIO_PORTF, - .ppdr = (void __iomem *)MCFGPIO_PORTFP, - .setr = (void __iomem *)MCFGPIO_SETF, - .clrr = (void __iomem *)MCFGPIO_CLRF, - }, - { - .gpio_chip = { - .label = "G", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 88, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRG, - .podr = (void __iomem *)MCFGPIO_PORTG, - .ppdr = (void __iomem *)MCFGPIO_PORTGP, - .setr = (void __iomem *)MCFGPIO_SETG, - .clrr = (void __iomem *)MCFGPIO_CLRG, - }, - { - .gpio_chip = { - .label = "H", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 96, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRH, - .podr = (void __iomem *)MCFGPIO_PORTH, - .ppdr = (void __iomem *)MCFGPIO_PORTHP, - .setr = (void __iomem *)MCFGPIO_SETH, - .clrr = (void __iomem *)MCFGPIO_CLRH, - }, - { - .gpio_chip = { - .label = "J", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 104, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRJ, - .podr = (void __iomem *)MCFGPIO_PORTJ, - .ppdr = (void __iomem *)MCFGPIO_PORTJP, - .setr = (void __iomem *)MCFGPIO_SETJ, - .clrr = (void __iomem *)MCFGPIO_CLRJ, - }, - { - .gpio_chip = { - .label = "DD", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 112, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRDD, - .podr = (void __iomem *)MCFGPIO_PORTDD, - .ppdr = (void __iomem *)MCFGPIO_PORTDDP, - .setr = (void __iomem *)MCFGPIO_SETDD, - .clrr = (void __iomem *)MCFGPIO_CLRDD, - }, - { - .gpio_chip = { - .label = "EH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 120, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDREH, - .podr = (void __iomem *)MCFGPIO_PORTEH, - .ppdr = (void __iomem *)MCFGPIO_PORTEHP, - .setr = (void __iomem *)MCFGPIO_SETEH, - .clrr = (void __iomem *)MCFGPIO_CLREH, - }, - { - .gpio_chip = { - .label = "EL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 128, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDREL, - .podr = (void __iomem *)MCFGPIO_PORTEL, - .ppdr = (void __iomem *)MCFGPIO_PORTELP, - .setr = (void __iomem *)MCFGPIO_SETEL, - .clrr = (void __iomem *)MCFGPIO_CLREL, - }, - { - .gpio_chip = { - .label = "AS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 136, - .ngpio = 6, - }, - .pddr = (void __iomem *)MCFGPIO_DDRAS, - .podr = (void __iomem *)MCFGPIO_PORTAS, - .ppdr = (void __iomem *)MCFGPIO_PORTASP, - .setr = (void __iomem *)MCFGPIO_SETAS, - .clrr = (void __iomem *)MCFGPIO_CLRAS, - }, - { - .gpio_chip = { - .label = "QS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 144, - .ngpio = 7, - }, - .pddr = (void __iomem *)MCFGPIO_DDRQS, - .podr = (void __iomem *)MCFGPIO_PORTQS, - .ppdr = (void __iomem *)MCFGPIO_PORTQSP, - .setr = (void __iomem *)MCFGPIO_SETQS, - .clrr = (void __iomem *)MCFGPIO_CLRQS, - }, - { - .gpio_chip = { - .label = "SD", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 152, - .ngpio = 6, - }, - .pddr = (void __iomem *)MCFGPIO_DDRSD, - .podr = (void __iomem *)MCFGPIO_PORTSD, - .ppdr = (void __iomem *)MCFGPIO_PORTSDP, - .setr = (void __iomem *)MCFGPIO_SETSD, - .clrr = (void __iomem *)MCFGPIO_CLRSD, - }, - { - .gpio_chip = { - .label = "TC", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 160, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPIO_DDRTC, - .podr = (void __iomem *)MCFGPIO_PORTTC, - .ppdr = (void __iomem *)MCFGPIO_PORTTCP, - .setr = (void __iomem *)MCFGPIO_SETTC, - .clrr = (void __iomem *)MCFGPIO_CLRTC, - }, - { - .gpio_chip = { - .label = "TD", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 168, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPIO_DDRTD, - .podr = (void __iomem *)MCFGPIO_PORTTD, - .ppdr = (void __iomem *)MCFGPIO_PORTTDP, - .setr = (void __iomem *)MCFGPIO_SETTD, - .clrr = (void __iomem *)MCFGPIO_CLRTD, - }, - { - .gpio_chip = { - .label = "UA", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 176, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPIO_DDRUA, - .podr = (void __iomem *)MCFGPIO_PORTUA, - .ppdr = (void __iomem *)MCFGPIO_PORTUAP, - .setr = (void __iomem *)MCFGPIO_SETUA, - .clrr = (void __iomem *)MCFGPIO_CLRUA, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68knommu/platform/5307/Makefile b/arch/m68knommu/platform/5307/Makefile deleted file mode 100644 index d4293b7..0000000 --- a/arch/m68knommu/platform/5307/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# Makefile for the m68knommu kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y += config.o gpio.o -obj-$(CONFIG_NETtel) += nettel.o -obj-$(CONFIG_CLEOPATRA) += nettel.o - diff --git a/arch/m68knommu/platform/5307/config.c b/arch/m68knommu/platform/5307/config.c deleted file mode 100644 index 00900ac..0000000 --- a/arch/m68knommu/platform/5307/config.c +++ /dev/null @@ -1,147 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/5307/config.c - * - * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) - * Copyright (C) 2000, Lineo (www.lineo.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/io.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfuart.h> -#include <asm/mcfwdebug.h> - -/***************************************************************************/ - -/* - * Some platforms need software versions of the GPIO data registers. - */ -unsigned short ppdata; -unsigned char ledbank = 0xff; - -/***************************************************************************/ - -static struct mcf_platform_uart m5307_uart_platform[] = { - { - .mapbase = MCF_MBAR + MCFUART_BASE1, - .irq = 73, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE2, - .irq = 74, - }, - { }, -}; - -static struct platform_device m5307_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m5307_uart_platform, -}; - -static struct platform_device *m5307_devices[] __initdata = { - &m5307_uart, -}; - -/***************************************************************************/ - -static void __init m5307_uart_init_line(int line, int irq) -{ - if (line == 0) { - writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); - writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); - mcf_mapirq2imr(irq, MCFINTC_UART0); - } else if (line == 1) { - writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); - writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); - mcf_mapirq2imr(irq, MCFINTC_UART1); - } -} - -static void __init m5307_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m5307_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m5307_uart_init_line(line, m5307_uart_platform[line].irq); -} - -/***************************************************************************/ - -static void __init m5307_timers_init(void) -{ - /* Timer1 is always used as system timer */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, - MCF_MBAR + MCFSIM_TIMER1ICR); - mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1); - -#ifdef CONFIG_HIGHPROFILE - /* Timer2 is to be used as a high speed profile timer */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, - MCF_MBAR + MCFSIM_TIMER2ICR); - mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2); -#endif -} - -/***************************************************************************/ - -void m5307_cpu_reset(void) -{ - local_irq_disable(); - /* Set watchdog to soft reset, and enabled */ - __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR); - for (;;) - /* wait for watchdog to timeout */; -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ -#if defined(CONFIG_NETtel) || \ - defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA) - /* Copy command line from FLASH to local buffer... */ - memcpy(commandp, (char *) 0xf0004000, size); - commandp[size-1] = 0; -#endif - - mach_reset = m5307_cpu_reset; - m5307_timers_init(); - m5307_uarts_init(); - - /* Only support the external interrupts on their primary level */ - mcf_mapirq2imr(25, MCFINTC_EINT1); - mcf_mapirq2imr(27, MCFINTC_EINT3); - mcf_mapirq2imr(29, MCFINTC_EINT5); - mcf_mapirq2imr(31, MCFINTC_EINT7); - -#ifdef CONFIG_BDM_DISABLE - /* - * Disable the BDM clocking. This also turns off most of the rest of - * the BDM device. This is good for EMC reasons. This option is not - * incompatible with the memory protection option. - */ - wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK); -#endif -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/5307/gpio.c b/arch/m68knommu/platform/5307/gpio.c deleted file mode 100644 index 5850612..0000000 --- a/arch/m68knommu/platform/5307/gpio.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PP", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 16, - }, - .pddr = (void __iomem *) MCFSIM_PADDR, - .podr = (void __iomem *) MCFSIM_PADAT, - .ppdr = (void __iomem *) MCFSIM_PADAT, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68knommu/platform/5307/nettel.c b/arch/m68knommu/platform/5307/nettel.c deleted file mode 100644 index e925ea4..0000000 --- a/arch/m68knommu/platform/5307/nettel.c +++ /dev/null @@ -1,153 +0,0 @@ -/***************************************************************************/ - -/* - * nettel.c -- startup code support for the NETtel boards - * - * Copyright (C) 2009, Greg Ungerer (gerg@snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/nettel.h> - -/***************************************************************************/ - -/* - * Define the IO and interrupt resources of the 2 SMC9196 interfaces. - */ -#define NETTEL_SMC0_ADDR 0x30600300 -#define NETTEL_SMC0_IRQ 29 - -#define NETTEL_SMC1_ADDR 0x30600000 -#define NETTEL_SMC1_IRQ 27 - -/* - * We need some access into the SMC9196 registers. Define those registers - * we will need here (including the smc91x.h doesn't seem to give us these - * in a simple form). - */ -#define SMC91xx_BANKSELECT 14 -#define SMC91xx_BASEADDR 2 -#define SMC91xx_BASEMAC 4 - -/***************************************************************************/ - -static struct resource nettel_smc91x_0_resources[] = { - { - .start = NETTEL_SMC0_ADDR, - .end = NETTEL_SMC0_ADDR + 0x20, - .flags = IORESOURCE_MEM, - }, - { - .start = NETTEL_SMC0_IRQ, - .end = NETTEL_SMC0_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource nettel_smc91x_1_resources[] = { - { - .start = NETTEL_SMC1_ADDR, - .end = NETTEL_SMC1_ADDR + 0x20, - .flags = IORESOURCE_MEM, - }, - { - .start = NETTEL_SMC1_IRQ, - .end = NETTEL_SMC1_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device nettel_smc91x[] = { - { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(nettel_smc91x_0_resources), - .resource = nettel_smc91x_0_resources, - }, - { - .name = "smc91x", - .id = 1, - .num_resources = ARRAY_SIZE(nettel_smc91x_1_resources), - .resource = nettel_smc91x_1_resources, - }, -}; - -static struct platform_device *nettel_devices[] __initdata = { - &nettel_smc91x[0], - &nettel_smc91x[1], -}; - -/***************************************************************************/ - -static u8 nettel_macdefault[] __initdata = { - 0x00, 0xd0, 0xcf, 0x00, 0x00, 0x01, -}; - -/* - * Set flash contained MAC address into SMC9196 core. Make sure the flash - * MAC address is sane, and not an empty flash. If no good use the Moreton - * Bay default MAC address instead. - */ - -static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flashaddr) -{ - u16 *macp; - - macp = (u16 *) flashaddr; - if ((macp[0] == 0xffff) && (macp[1] == 0xffff) && (macp[2] == 0xffff)) - macp = (u16 *) &nettel_macdefault[0]; - - writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); - writew(macp[0], ioaddr + SMC91xx_BASEMAC); - writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2); - writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4); -} - -/***************************************************************************/ - -/* - * Re-map the address space of at least one of the SMC ethernet - * parts. Both parts power up decoding the same address, so we - * need to move one of them first, before doing anything else. - */ - -static void __init nettel_smc91x_init(void) -{ - writew(0x00ec, MCF_MBAR + MCFSIM_PADDR); - mcf_setppdata(0, 0x0080); - writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); - writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR); - mcf_setppdata(0x0080, 0); - - /* Set correct chip select timing for SMC9196 accesses */ - writew(0x1180, MCF_MBAR + MCFSIM_CSCR3); - - /* Set the SMC interrupts to be auto-vectored */ - mcf_autovector(NETTEL_SMC0_IRQ); - mcf_autovector(NETTEL_SMC1_IRQ); - - /* Set MAC addresses from flash for both interfaces */ - nettel_smc91x_setmac(NETTEL_SMC0_ADDR, 0xf0006000); - nettel_smc91x_setmac(NETTEL_SMC1_ADDR, 0xf0006006); -} - -/***************************************************************************/ - -static int __init init_nettel(void) -{ - nettel_smc91x_init(); - platform_add_devices(nettel_devices, ARRAY_SIZE(nettel_devices)); - return 0; -} - -arch_initcall(init_nettel); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/532x/Makefile b/arch/m68knommu/platform/532x/Makefile deleted file mode 100644 index ce01669..0000000 --- a/arch/m68knommu/platform/532x/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -#obj-y := config.o usb-mcf532x.o spi-mcf532x.o -obj-y := config.o gpio.o diff --git a/arch/m68knommu/platform/532x/config.c b/arch/m68knommu/platform/532x/config.c deleted file mode 100644 index ca51323..0000000 --- a/arch/m68knommu/platform/532x/config.c +++ /dev/null @@ -1,648 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/532x/config.c - * - * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) - * Copyright (C) 2000, Lineo (www.lineo.com) - * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com - * Copyright Freescale Semiconductor, Inc 2006 - * Copyright (c) 2006, emlix, Sebastian Hess <sh@emlix.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/spi/spi.h> -#include <linux/gpio.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfuart.h> -#include <asm/mcfdma.h> -#include <asm/mcfwdebug.h> -#include <asm/mcfqspi.h> - -/***************************************************************************/ - -static struct mcf_platform_uart m532x_uart_platform[] = { - { - .mapbase = MCFUART_BASE1, - .irq = MCFINT_VECBASE + MCFINT_UART0, - }, - { - .mapbase = MCFUART_BASE2, - .irq = MCFINT_VECBASE + MCFINT_UART1, - }, - { - .mapbase = MCFUART_BASE3, - .irq = MCFINT_VECBASE + MCFINT_UART2, - }, - { }, -}; - -static struct platform_device m532x_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m532x_uart_platform, -}; - -static struct resource m532x_fec_resources[] = { - { - .start = 0xfc030000, - .end = 0xfc0307ff, - .flags = IORESOURCE_MEM, - }, - { - .start = 64 + 36, - .end = 64 + 36, - .flags = IORESOURCE_IRQ, - }, - { - .start = 64 + 40, - .end = 64 + 40, - .flags = IORESOURCE_IRQ, - }, - { - .start = 64 + 42, - .end = 64 + 42, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device m532x_fec = { - .name = "fec", - .id = 0, - .num_resources = ARRAY_SIZE(m532x_fec_resources), - .resource = m532x_fec_resources, -}; - -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) -static struct resource m532x_qspi_resources[] = { - { - .start = MCFQSPI_IOBASE, - .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MCFINT_VECBASE + MCFINT_QSPI, - .end = MCFINT_VECBASE + MCFINT_QSPI, - .flags = IORESOURCE_IRQ, - }, -}; - -#define MCFQSPI_CS0 84 -#define MCFQSPI_CS1 85 -#define MCFQSPI_CS2 86 - -static int m532x_cs_setup(struct mcfqspi_cs_control *cs_control) -{ - int status; - - status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS0 failed\n"); - goto fail0; - } - status = gpio_direction_output(MCFQSPI_CS0, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n"); - goto fail1; - } - - status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS1 failed\n"); - goto fail1; - } - status = gpio_direction_output(MCFQSPI_CS1, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n"); - goto fail2; - } - - status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2"); - if (status) { - pr_debug("gpio_request for MCFQSPI_CS2 failed\n"); - goto fail2; - } - status = gpio_direction_output(MCFQSPI_CS2, 1); - if (status) { - pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n"); - goto fail3; - } - - return 0; - -fail3: - gpio_free(MCFQSPI_CS2); -fail2: - gpio_free(MCFQSPI_CS1); -fail1: - gpio_free(MCFQSPI_CS0); -fail0: - return status; -} - -static void m532x_cs_teardown(struct mcfqspi_cs_control *cs_control) -{ - gpio_free(MCFQSPI_CS2); - gpio_free(MCFQSPI_CS1); - gpio_free(MCFQSPI_CS0); -} - -static void m532x_cs_select(struct mcfqspi_cs_control *cs_control, - u8 chip_select, bool cs_high) -{ - gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high); -} - -static void m532x_cs_deselect(struct mcfqspi_cs_control *cs_control, - u8 chip_select, bool cs_high) -{ - gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high); -} - -static struct mcfqspi_cs_control m532x_cs_control = { - .setup = m532x_cs_setup, - .teardown = m532x_cs_teardown, - .select = m532x_cs_select, - .deselect = m532x_cs_deselect, -}; - -static struct mcfqspi_platform_data m532x_qspi_data = { - .bus_num = 0, - .num_chipselect = 3, - .cs_control = &m532x_cs_control, -}; - -static struct platform_device m532x_qspi = { - .name = "mcfqspi", - .id = 0, - .num_resources = ARRAY_SIZE(m532x_qspi_resources), - .resource = m532x_qspi_resources, - .dev.platform_data = &m532x_qspi_data, -}; - -static void __init m532x_qspi_init(void) -{ - /* setup QSPS pins for QSPI with gpio CS control */ - writew(0x01f0, MCF_GPIO_PAR_QSPI); -} -#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ - - -static struct platform_device *m532x_devices[] __initdata = { - &m532x_uart, - &m532x_fec, -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) - &m532x_qspi, -#endif -}; - -/***************************************************************************/ - -static void __init m532x_uart_init_line(int line, int irq) -{ - if (line == 0) { - /* GPIO initialization */ - MCF_GPIO_PAR_UART |= 0x000F; - } else if (line == 1) { - /* GPIO initialization */ - MCF_GPIO_PAR_UART |= 0x0FF0; - } -} - -static void __init m532x_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m532x_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m532x_uart_init_line(line, m532x_uart_platform[line].irq); -} -/***************************************************************************/ - -static void __init m532x_fec_init(void) -{ - /* Set multi-function pins to ethernet mode for fec0 */ - MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC | - MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO); - MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | - MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC); -} - -/***************************************************************************/ - -static void m532x_cpu_reset(void) -{ - local_irq_disable(); - __raw_writeb(MCF_RCR_SWRESET, MCF_RCR); -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ -#if !defined(CONFIG_BOOTPARAM) - /* Copy command line from FLASH to local buffer... */ - memcpy(commandp, (char *) 0x4000, 4); - if(strncmp(commandp, "kcl ", 4) == 0){ - memcpy(commandp, (char *) 0x4004, size); - commandp[size-1] = 0; - } else { - memset(commandp, 0, size); - } -#endif - -#ifdef CONFIG_BDM_DISABLE - /* - * Disable the BDM clocking. This also turns off most of the rest of - * the BDM device. This is good for EMC reasons. This option is not - * incompatible with the memory protection option. - */ - wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK); -#endif -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - m532x_uarts_init(); - m532x_fec_init(); -#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) - m532x_qspi_init(); -#endif - platform_add_devices(m532x_devices, ARRAY_SIZE(m532x_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ -/* Board initialization */ -/***************************************************************************/ -/* - * PLL min/max specifications - */ -#define MAX_FVCO 500000 /* KHz */ -#define MAX_FSYS 80000 /* KHz */ -#define MIN_FSYS 58333 /* KHz */ -#define FREF 16000 /* KHz */ - - -#define MAX_MFD 135 /* Multiplier */ -#define MIN_MFD 88 /* Multiplier */ -#define BUSDIV 6 /* Divider */ - -/* - * Low Power Divider specifications - */ -#define MIN_LPD (1 << 0) /* Divider (not encoded) */ -#define MAX_LPD (1 << 15) /* Divider (not encoded) */ -#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ - -#define SYS_CLK_KHZ 80000 -#define SYSTEM_PERIOD 12.5 -/* - * SDRAM Timing Parameters - */ -#define SDRAM_BL 8 /* # of beats in a burst */ -#define SDRAM_TWR 2 /* in clocks */ -#define SDRAM_CASL 2.5 /* CASL in clocks */ -#define SDRAM_TRCD 2 /* in clocks */ -#define SDRAM_TRP 2 /* in clocks */ -#define SDRAM_TRFC 7 /* in clocks */ -#define SDRAM_TREFI 7800 /* in ns */ - -#define EXT_SRAM_ADDRESS (0xC0000000) -#define FLASH_ADDRESS (0x00000000) -#define SDRAM_ADDRESS (0x40000000) - -#define NAND_FLASH_ADDRESS (0xD0000000) - -int sys_clk_khz = 0; -int sys_clk_mhz = 0; - -void wtm_init(void); -void scm_init(void); -void gpio_init(void); -void fbcs_init(void); -void sdramc_init(void); -int clock_pll (int fsys, int flags); -int clock_limp (int); -int clock_exit_limp (void); -int get_sys_clock (void); - -asmlinkage void __init sysinit(void) -{ - sys_clk_khz = clock_pll(0, 0); - sys_clk_mhz = sys_clk_khz/1000; - - wtm_init(); - scm_init(); - gpio_init(); - fbcs_init(); - sdramc_init(); -} - -void wtm_init(void) -{ - /* Disable watchdog timer */ - MCF_WTM_WCR = 0; -} - -#define MCF_SCM_BCR_GBW (0x00000100) -#define MCF_SCM_BCR_GBR (0x00000200) - -void scm_init(void) -{ - /* All masters are trusted */ - MCF_SCM_MPR = 0x77777777; - - /* Allow supervisor/user, read/write, and trusted/untrusted - access to all slaves */ - MCF_SCM_PACRA = 0; - MCF_SCM_PACRB = 0; - MCF_SCM_PACRC = 0; - MCF_SCM_PACRD = 0; - MCF_SCM_PACRE = 0; - MCF_SCM_PACRF = 0; - - /* Enable bursts */ - MCF_SCM_BCR = (MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW); -} - - -void fbcs_init(void) -{ - MCF_GPIO_PAR_CS = 0x0000003E; - - /* Latch chip select */ - MCF_FBCS1_CSAR = 0x10080000; - - MCF_FBCS1_CSCR = 0x002A3780; - MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V); - - /* Initialize latch to drive signals to inactive states */ - *((u16 *)(0x10080000)) = 0xFFFF; - - /* External SRAM */ - MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS; - MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16 - | MCF_FBCS_CSCR_AA - | MCF_FBCS_CSCR_SBM - | MCF_FBCS_CSCR_WS(1)); - MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K - | MCF_FBCS_CSMR_V); - - /* Boot Flash connected to FBCS0 */ - MCF_FBCS0_CSAR = FLASH_ADDRESS; - MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16 - | MCF_FBCS_CSCR_BEM - | MCF_FBCS_CSCR_AA - | MCF_FBCS_CSCR_SBM - | MCF_FBCS_CSCR_WS(7)); - MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M - | MCF_FBCS_CSMR_V); -} - -void sdramc_init(void) -{ - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ - if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) { - /* SDRAM chip select initialization */ - - /* Initialize SDRAM chip select */ - MCF_SDRAMC_SDCS0 = (0 - | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) - | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE)); - - /* - * Basic configuration and initialization - */ - MCF_SDRAMC_SDCFG1 = (0 - | MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 )) - | MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) - | MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2)) - | MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5)) - | MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5)) - | MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5)) - | MCF_SDRAMC_SDCFG1_WTLAT(3)); - MCF_SDRAMC_SDCFG2 = (0 - | MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1) - | MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR) - | MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5)) - | MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1)); - - - /* - * Precharge and enable write to SDMR - */ - MCF_SDRAMC_SDCR = (0 - | MCF_SDRAMC_SDCR_MODE_EN - | MCF_SDRAMC_SDCR_CKE - | MCF_SDRAMC_SDCR_DDR - | MCF_SDRAMC_SDCR_MUX(1) - | MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5)) - | MCF_SDRAMC_SDCR_PS_16 - | MCF_SDRAMC_SDCR_IPALL); - - /* - * Write extended mode register - */ - MCF_SDRAMC_SDMR = (0 - | MCF_SDRAMC_SDMR_BNKAD_LEMR - | MCF_SDRAMC_SDMR_AD(0x0) - | MCF_SDRAMC_SDMR_CMD); - - /* - * Write mode register and reset DLL - */ - MCF_SDRAMC_SDMR = (0 - | MCF_SDRAMC_SDMR_BNKAD_LMR - | MCF_SDRAMC_SDMR_AD(0x163) - | MCF_SDRAMC_SDMR_CMD); - - /* - * Execute a PALL command - */ - MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL; - - /* - * Perform two REF cycles - */ - MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; - MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; - - /* - * Write mode register and clear reset DLL - */ - MCF_SDRAMC_SDMR = (0 - | MCF_SDRAMC_SDMR_BNKAD_LMR - | MCF_SDRAMC_SDMR_AD(0x063) - | MCF_SDRAMC_SDMR_CMD); - - /* - * Enable auto refresh and lock SDMR - */ - MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN; - MCF_SDRAMC_SDCR |= (0 - | MCF_SDRAMC_SDCR_REF - | MCF_SDRAMC_SDCR_DQS_OE(0xC)); - } -} - -void gpio_init(void) -{ - /* Enable UART0 pins */ - MCF_GPIO_PAR_UART = ( 0 - | MCF_GPIO_PAR_UART_PAR_URXD0 - | MCF_GPIO_PAR_UART_PAR_UTXD0); - - /* Initialize TIN3 as a GPIO output to enable the write - half of the latch */ - MCF_GPIO_PAR_TIMER = 0x00; - __raw_writeb(0x08, MCFGPIO_PDDR_TIMER); - __raw_writeb(0x00, MCFGPIO_PCLRR_TIMER); - -} - -int clock_pll(int fsys, int flags) -{ - int fref, temp, fout, mfd; - u32 i; - - fref = FREF; - - if (fsys == 0) { - /* Return current PLL output */ - mfd = MCF_PLL_PFDR; - - return (fref * mfd / (BUSDIV * 4)); - } - - /* Check bounds of requested system clock */ - if (fsys > MAX_FSYS) - fsys = MAX_FSYS; - if (fsys < MIN_FSYS) - fsys = MIN_FSYS; - - /* Multiplying by 100 when calculating the temp value, - and then dividing by 100 to calculate the mfd allows - for exact values without needing to include floating - point libraries. */ - temp = 100 * fsys / fref; - mfd = 4 * BUSDIV * temp / 100; - - /* Determine the output frequency for selected values */ - fout = (fref * mfd / (BUSDIV * 4)); - - /* - * Check to see if the SDRAM has already been initialized. - * If it has then the SDRAM needs to be put into self refresh - * mode before reprogramming the PLL. - */ - if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) - /* Put SDRAM into self refresh mode */ - MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE; - - /* - * Initialize the PLL to generate the new system clock frequency. - * The device must be put into LIMP mode to reprogram the PLL. - */ - - /* Enter LIMP mode */ - clock_limp(DEFAULT_LPD); - - /* Reprogram PLL for desired fsys */ - MCF_PLL_PODR = (0 - | MCF_PLL_PODR_CPUDIV(BUSDIV/3) - | MCF_PLL_PODR_BUSDIV(BUSDIV)); - - MCF_PLL_PFDR = mfd; - - /* Exit LIMP mode */ - clock_exit_limp(); - - /* - * Return the SDRAM to normal operation if it is in use. - */ - if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) - /* Exit self refresh mode */ - MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE; - - /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */ - MCF_SDRAMC_LIMP_FIX = MCF_SDRAMC_REFRESH; - - /* wait for DQS logic to relock */ - for (i = 0; i < 0x200; i++) - ; - - return fout; -} - -int clock_limp(int div) -{ - u32 temp; - - /* Check bounds of divider */ - if (div < MIN_LPD) - div = MIN_LPD; - if (div > MAX_LPD) - div = MAX_LPD; - - /* Save of the current value of the SSIDIV so we don't - overwrite the value*/ - temp = (MCF_CCM_CDR & MCF_CCM_CDR_SSIDIV(0xF)); - - /* Apply the divider to the system clock */ - MCF_CCM_CDR = ( 0 - | MCF_CCM_CDR_LPDIV(div) - | MCF_CCM_CDR_SSIDIV(temp)); - - MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP; - - return (FREF/(3*(1 << div))); -} - -int clock_exit_limp(void) -{ - int fout; - - /* Exit LIMP mode */ - MCF_CCM_MISCCR = (MCF_CCM_MISCCR & ~ MCF_CCM_MISCCR_LIMP); - - /* Wait for PLL to lock */ - while (!(MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK)) - ; - - fout = get_sys_clock(); - - return fout; -} - -int get_sys_clock(void) -{ - int divider; - - /* Test to see if device is in LIMP mode */ - if (MCF_CCM_MISCCR & MCF_CCM_MISCCR_LIMP) { - divider = MCF_CCM_CDR & MCF_CCM_CDR_LPDIV(0xF); - return (FREF/(2 << divider)); - } - else - return ((FREF * MCF_PLL_PFDR) / (BUSDIV * 4)); -} diff --git a/arch/m68knommu/platform/532x/gpio.c b/arch/m68knommu/platform/532x/gpio.c deleted file mode 100644 index 212a85d..0000000 --- a/arch/m68knommu/platform/532x/gpio.c +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PIRQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFEPORT_EPDDR, - .podr = (void __iomem *) MCFEPORT_EPDR, - .ppdr = (void __iomem *) MCFEPORT_EPPDR, - }, - { - .gpio_chip = { - .label = "FECH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 8, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECH, - .podr = (void __iomem *) MCFGPIO_PODR_FECH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH, - }, - { - .gpio_chip = { - .label = "FECL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 16, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECL, - .podr = (void __iomem *) MCFGPIO_PODR_FECL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL, - }, - { - .gpio_chip = { - .label = "SSI", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 24, - .ngpio = 5, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_SSI, - .podr = (void __iomem *) MCFGPIO_PODR_SSI, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SSI, - .setr = (void __iomem *) MCFGPIO_PPDSDR_SSI, - .clrr = (void __iomem *) MCFGPIO_PCLRR_SSI, - }, - { - .gpio_chip = { - .label = "BUSCTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 32, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, - .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, - }, - { - .gpio_chip = { - .label = "BE", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 40, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BE, - .podr = (void __iomem *) MCFGPIO_PODR_BE, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BE, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BE, - }, - { - .gpio_chip = { - .label = "CS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 49, - .ngpio = 5, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_CS, - .podr = (void __iomem *) MCFGPIO_PODR_CS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, - }, - { - .gpio_chip = { - .label = "PWM", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 58, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_PWM, - .podr = (void __iomem *) MCFGPIO_PODR_PWM, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_PWM, - .setr = (void __iomem *) MCFGPIO_PPDSDR_PWM, - .clrr = (void __iomem *) MCFGPIO_PCLRR_PWM, - }, - { - .gpio_chip = { - .label = "FECI2C", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 64, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, - .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, - }, - { - .gpio_chip = { - .label = "UART", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 72, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UART, - .podr = (void __iomem *) MCFGPIO_PODR_UART, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UART, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UART, - }, - { - .gpio_chip = { - .label = "QSPI", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 80, - .ngpio = 6, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, - .podr = (void __iomem *) MCFGPIO_PODR_QSPI, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, - }, - { - .gpio_chip = { - .label = "TIMER", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 88, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, - .podr = (void __iomem *) MCFGPIO_PODR_TIMER, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER, - }, - { - .gpio_chip = { - .label = "LCDDATAH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 96, - .ngpio = 2, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAH, - .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAH, - }, - { - .gpio_chip = { - .label = "LCDDATAM", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 104, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAM, - .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAM, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM, - .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM, - .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAM, - }, - { - .gpio_chip = { - .label = "LCDDATAL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 112, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAL, - .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAL, - }, - { - .gpio_chip = { - .label = "LCDCTLH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 120, - .ngpio = 1, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLH, - .podr = (void __iomem *) MCFGPIO_PODR_LCDCTLH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLH, - }, - { - .gpio_chip = { - .label = "LCDCTLL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 128, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLL, - .podr = (void __iomem *) MCFGPIO_PODR_LCDCTLL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLL, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68knommu/platform/5407/Makefile b/arch/m68knommu/platform/5407/Makefile deleted file mode 100644 index e83fe14..0000000 --- a/arch/m68knommu/platform/5407/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o - diff --git a/arch/m68knommu/platform/5407/config.c b/arch/m68knommu/platform/5407/config.c deleted file mode 100644 index 70ea789..0000000 --- a/arch/m68knommu/platform/5407/config.c +++ /dev/null @@ -1,122 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/5407/config.c - * - * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) - * Copyright (C) 2000, Lineo (www.lineo.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/io.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfuart.h> - -/***************************************************************************/ - -static struct mcf_platform_uart m5407_uart_platform[] = { - { - .mapbase = MCF_MBAR + MCFUART_BASE1, - .irq = 73, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE2, - .irq = 74, - }, - { }, -}; - -static struct platform_device m5407_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m5407_uart_platform, -}; - -static struct platform_device *m5407_devices[] __initdata = { - &m5407_uart, -}; - -/***************************************************************************/ - -static void __init m5407_uart_init_line(int line, int irq) -{ - if (line == 0) { - writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); - writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); - mcf_mapirq2imr(irq, MCFINTC_UART0); - } else if (line == 1) { - writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); - writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); - mcf_mapirq2imr(irq, MCFINTC_UART1); - } -} - -static void __init m5407_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m5407_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m5407_uart_init_line(line, m5407_uart_platform[line].irq); -} - -/***************************************************************************/ - -static void __init m5407_timers_init(void) -{ - /* Timer1 is always used as system timer */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, - MCF_MBAR + MCFSIM_TIMER1ICR); - mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1); - -#ifdef CONFIG_HIGHPROFILE - /* Timer2 is to be used as a high speed profile timer */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, - MCF_MBAR + MCFSIM_TIMER2ICR); - mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2); -#endif -} - -/***************************************************************************/ - -void m5407_cpu_reset(void) -{ - local_irq_disable(); - /* set watchdog to soft reset, and enabled */ - __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR); - for (;;) - /* wait for watchdog to timeout */; -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ - mach_reset = m5407_cpu_reset; - m5407_timers_init(); - m5407_uarts_init(); - - /* Only support the external interrupts on their primary level */ - mcf_mapirq2imr(25, MCFINTC_EINT1); - mcf_mapirq2imr(27, MCFINTC_EINT3); - mcf_mapirq2imr(29, MCFINTC_EINT5); - mcf_mapirq2imr(31, MCFINTC_EINT7); -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - platform_add_devices(m5407_devices, ARRAY_SIZE(m5407_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/5407/gpio.c b/arch/m68knommu/platform/5407/gpio.c deleted file mode 100644 index 5850612..0000000 --- a/arch/m68knommu/platform/5407/gpio.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PP", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 16, - }, - .pddr = (void __iomem *) MCFSIM_PADDR, - .podr = (void __iomem *) MCFSIM_PADAT, - .ppdr = (void __iomem *) MCFSIM_PADAT, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68knommu/platform/54xx/Makefile b/arch/m68knommu/platform/54xx/Makefile deleted file mode 100644 index 6cfd090..0000000 --- a/arch/m68knommu/platform/54xx/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT -# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o -obj-$(CONFIG_FIREBEE) += firebee.o - diff --git a/arch/m68knommu/platform/54xx/config.c b/arch/m68knommu/platform/54xx/config.c deleted file mode 100644 index 7813098..0000000 --- a/arch/m68knommu/platform/54xx/config.c +++ /dev/null @@ -1,115 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/54xx/config.c - * - * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be> - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/m54xxsim.h> -#include <asm/mcfuart.h> -#include <asm/m54xxgpt.h> - -/***************************************************************************/ - -static struct mcf_platform_uart m54xx_uart_platform[] = { - { - .mapbase = MCF_MBAR + MCFUART_BASE1, - .irq = 64 + 35, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE2, - .irq = 64 + 34, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE3, - .irq = 64 + 33, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE4, - .irq = 64 + 32, - }, -}; - -static struct platform_device m54xx_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m54xx_uart_platform, -}; - -static struct platform_device *m54xx_devices[] __initdata = { - &m54xx_uart, -}; - - -/***************************************************************************/ - -static void __init m54xx_uart_init_line(int line, int irq) -{ - int rts_cts; - - /* enable io pins */ - switch (line) { - case 0: - rts_cts = 0; break; - case 1: - rts_cts = MCF_PAR_PSC_RTS_RTS; break; - case 2: - rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break; - case 3: - rts_cts = 0; break; - } - __raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD, - MCF_MBAR + MCF_PAR_PSC(line)); -} - -static void __init m54xx_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m54xx_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m54xx_uart_init_line(line, m54xx_uart_platform[line].irq); -} - -/***************************************************************************/ - -static void mcf54xx_reset(void) -{ - /* disable interrupts and enable the watchdog */ - asm("movew #0x2700, %sr\n"); - __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0); - __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0); - __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4), - MCF_MBAR + MCF_GPT_GMS0); -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ - mach_reset = mcf54xx_reset; - m54xx_uarts_init(); -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - - platform_add_devices(m54xx_devices, ARRAY_SIZE(m54xx_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/54xx/firebee.c b/arch/m68knommu/platform/54xx/firebee.c deleted file mode 100644 index 46d5053..0000000 --- a/arch/m68knommu/platform/54xx/firebee.c +++ /dev/null @@ -1,86 +0,0 @@ -/***************************************************************************/ - -/* - * firebee.c -- extra startup code support for the FireBee boards - * - * Copyright (C) 2011, Greg Ungerer (gerg@snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> - -/***************************************************************************/ - -/* - * 8MB of NOR flash fitted to the FireBee board. - */ -#define FLASH_PHYS_ADDR 0xe0000000 /* Physical address of flash */ -#define FLASH_PHYS_SIZE 0x00800000 /* Size of flash */ - -#define PART_BOOT_START 0x00000000 /* Start at bottom of flash */ -#define PART_BOOT_SIZE 0x00040000 /* 256k in size */ -#define PART_IMAGE_START 0x00040000 /* Start after boot loader */ -#define PART_IMAGE_SIZE 0x006c0000 /* Most of flash */ -#define PART_FPGA_START 0x00700000 /* Start at offset 7MB */ -#define PART_FPGA_SIZE 0x00100000 /* 1MB in size */ - -static struct mtd_partition firebee_flash_parts[] = { - { - .name = "dBUG", - .offset = PART_BOOT_START, - .size = PART_BOOT_SIZE, - }, - { - .name = "FPGA", - .offset = PART_FPGA_START, - .size = PART_FPGA_SIZE, - }, - { - .name = "image", - .offset = PART_IMAGE_START, - .size = PART_IMAGE_SIZE, - }, -}; - -static struct physmap_flash_data firebee_flash_data = { - .width = 2, - .nr_parts = ARRAY_SIZE(firebee_flash_parts), - .parts = firebee_flash_parts, -}; - -static struct resource firebee_flash_resource = { - .start = FLASH_PHYS_ADDR, - .end = FLASH_PHYS_ADDR + FLASH_PHYS_SIZE, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device firebee_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &firebee_flash_data, - }, - .num_resources = 1, - .resource = &firebee_flash_resource, -}; - -/***************************************************************************/ - -static int __init init_firebee(void) -{ - platform_device_register(&firebee_flash); - return 0; -} - -arch_initcall(init_firebee); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/68328/Makefile b/arch/m68knommu/platform/68328/Makefile deleted file mode 100644 index 5e54355..0000000 --- a/arch/m68knommu/platform/68328/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -# -# Makefile for arch/m68knommu/platform/68328. -# - -head-y = head-$(MODEL).o -head-$(CONFIG_PILOT) = head-pilot.o -head-$(CONFIG_DRAGEN2) = head-de2.o - -obj-y += entry.o ints.o timers.o -obj-$(CONFIG_M68328) += config.o -obj-$(CONFIG_ROM) += romvec.o - -extra-y := head.o -extra-$(CONFIG_M68328) += bootlogo.rh head.o - -$(obj)/bootlogo.rh: $(src)/bootlogo.h - perl $(src)/bootlogo.pl < $(src)/bootlogo.h > $(obj)/bootlogo.rh - -$(obj)/head.o: $(obj)/$(head-y) - ln -sf $(head-y) $(obj)/head.o - -clean-files := $(obj)/bootlogo.rh $(obj)/head.o $(head-y) diff --git a/arch/m68knommu/platform/68328/bootlogo.h b/arch/m68knommu/platform/68328/bootlogo.h deleted file mode 100644 index 67bc2c1..0000000 --- a/arch/m68knommu/platform/68328/bootlogo.h +++ /dev/null @@ -1,270 +0,0 @@ -#define bootlogo_width 160 -#define bootlogo_height 160 -static unsigned char bootlogo_bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x01, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x40, 0x55, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x90, 0x20, 0x02, 0xfc, 0xff, 0x1f, 0x80, 0x22, 0x00, 0x90, 0x24, 0x49, - 0x12, 0x92, 0x40, 0xb2, 0x24, 0x09, 0xc9, 0x49, 0x04, 0x80, 0x90, 0xfc, - 0xff, 0xbf, 0x24, 0x00, 0x00, 0x90, 0x24, 0x49, 0x12, 0x92, 0x40, 0x92, - 0x24, 0x06, 0x49, 0x48, 0x50, 0x0a, 0x02, 0xfe, 0xff, 0x3f, 0x00, 0x05, - 0x00, 0x50, 0xa5, 0x4a, 0x15, 0x92, 0x40, 0x92, 0x24, 0x06, 0x49, 0x48, - 0x80, 0x40, 0x48, 0xfe, 0xff, 0x3f, 0x49, 0x00, 0x00, 0x20, 0x42, 0x84, - 0x88, 0x1a, 0x41, 0x92, 0x34, 0x49, 0x49, 0x68, 0x00, 0x38, 0x10, 0x07, - 0x00, 0x60, 0x80, 0x00, 0x00, 0x20, 0x42, 0x84, 0x88, 0x14, 0x4e, 0x92, - 0x28, 0x49, 0x46, 0x50, 0x00, 0x80, 0x83, 0x01, 0x00, 0xa0, 0x6a, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, - 0x00, 0x00, 0xfc, 0x00, 0x00, 0xc0, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, }; diff --git a/arch/m68knommu/platform/68328/bootlogo.pl b/arch/m68knommu/platform/68328/bootlogo.pl deleted file mode 100644 index b04ae3f..0000000 --- a/arch/m68knommu/platform/68328/bootlogo.pl +++ /dev/null @@ -1,10 +0,0 @@ - -$_ = join("", <>); - -s/(0x[0-9a-f]{2})/sprintf("0x%.2x",ord(pack("b8",unpack("B8",chr(hex($1))))))/gei; - -s/^ / .byte /gm; -s/[,};]+$//gm; -s/^static.*//gm; - -print $_; diff --git a/arch/m68knommu/platform/68328/config.c b/arch/m68knommu/platform/68328/config.c deleted file mode 100644 index a7bd21d..0000000 --- a/arch/m68knommu/platform/68328/config.c +++ /dev/null @@ -1,52 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/68328/config.c - * - * Copyright (C) 1993 Hamish Macdonald - * Copyright (C) 1999 D. Jeff Dionne - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - * VZ Support/Fixes Evan Stawnyczy <e@lineo.ca> - */ - -/***************************************************************************/ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <asm/system.h> -#include <asm/machdep.h> -#include <asm/MC68328.h> - -/***************************************************************************/ - -void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec); - -/***************************************************************************/ - -void m68328_reset (void) -{ - local_irq_disable(); - asm volatile ("moveal #0x10c00000, %a0;\n\t" - "moveb #0, 0xFFFFF300;\n\t" - "moveal 0(%a0), %sp;\n\t" - "moveal 4(%a0), %a0;\n\t" - "jmp (%a0);"); -} - -/***************************************************************************/ - -void config_BSP(char *command, int len) -{ - printk(KERN_INFO "\n68328 support D. Jeff Dionne <jeff@uclinux.org>\n"); - printk(KERN_INFO "68328 support Kenneth Albanowski <kjahds@kjshds.com>\n"); - printk(KERN_INFO "68328/Pilot support Bernhard Kuhn <kuhn@lpr.e-technik.tu-muenchen.de>\n"); - - mach_gettod = m68328_timer_gettod; - mach_reset = m68328_reset; -} - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/68328/entry.S b/arch/m68knommu/platform/68328/entry.S deleted file mode 100644 index 676960c..0000000 --- a/arch/m68knommu/platform/68328/entry.S +++ /dev/null @@ -1,263 +0,0 @@ -/* - * linux/arch/m68knommu/platform/68328/entry.S - * - * Copyright (C) 1991, 1992 Linus Torvalds - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file README.legal in the main directory of this archive - * for more details. - * - * Linux/m68k support by Hamish Macdonald - */ - -#include <linux/sys.h> -#include <linux/linkage.h> -#include <asm/thread_info.h> -#include <asm/unistd.h> -#include <asm/errno.h> -#include <asm/setup.h> -#include <asm/segment.h> -#include <asm/traps.h> -#include <asm/asm-offsets.h> -#include <asm/entry.h> - -.text - -.globl system_call -.globl resume -.globl ret_from_exception -.globl ret_from_signal -.globl sys_call_table -.globl ret_from_interrupt -.globl bad_interrupt -.globl inthandler1 -.globl inthandler2 -.globl inthandler3 -.globl inthandler4 -.globl inthandler5 -.globl inthandler6 -.globl inthandler7 - -badsys: - movel #-ENOSYS,%sp@(PT_OFF_D0) - jra ret_from_exception - -do_trace: - movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/ - subql #4,%sp - SAVE_SWITCH_STACK - jbsr syscall_trace_enter - RESTORE_SWITCH_STACK - addql #4,%sp - movel %sp@(PT_OFF_ORIG_D0),%d1 - movel #-ENOSYS,%d0 - cmpl #NR_syscalls,%d1 - jcc 1f - lsl #2,%d1 - lea sys_call_table, %a0 - jbsr %a0@(%d1) - -1: movel %d0,%sp@(PT_OFF_D0) /* save the return value */ - subql #4,%sp /* dummy return address */ - SAVE_SWITCH_STACK - jbsr syscall_trace_leave - -ret_from_signal: - RESTORE_SWITCH_STACK - addql #4,%sp - jra ret_from_exception - -ENTRY(system_call) - SAVE_ALL - - /* save top of frame*/ - pea %sp@ - jbsr set_esp0 - addql #4,%sp - - movel %sp@(PT_OFF_ORIG_D0),%d0 - - movel %sp,%d1 /* get thread_info pointer */ - andl #-THREAD_SIZE,%d1 - movel %d1,%a2 - btst #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8) - jne do_trace - cmpl #NR_syscalls,%d0 - jcc badsys - lsl #2,%d0 - lea sys_call_table,%a0 - movel %a0@(%d0), %a0 - jbsr %a0@ - movel %d0,%sp@(PT_OFF_D0) /* save the return value*/ - -ret_from_exception: - btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel*/ - jeq Luser_return /* if so, skip resched, signals*/ - -Lkernel_return: - RESTORE_ALL - -Luser_return: - /* only allow interrupts when we are really the last one on the*/ - /* kernel stack, otherwise stack overflow can occur during*/ - /* heavy interrupt load*/ - andw #ALLOWINT,%sr - - movel %sp,%d1 /* get thread_info pointer */ - andl #-THREAD_SIZE,%d1 - movel %d1,%a2 -1: - move %a2@(TI_FLAGS),%d1 /* thread_info->flags */ - jne Lwork_to_do - RESTORE_ALL - -Lwork_to_do: - movel %a2@(TI_FLAGS),%d1 /* thread_info->flags */ - btst #TIF_NEED_RESCHED,%d1 - jne reschedule - -Lsignal_return: - subql #4,%sp /* dummy return address*/ - SAVE_SWITCH_STACK - pea %sp@(SWITCH_STACK_SIZE) - bsrw do_signal - addql #4,%sp - RESTORE_SWITCH_STACK - addql #4,%sp - jra 1b - -/* - * This is the main interrupt handler, responsible for calling process_int() - */ -inthandler1: - SAVE_ALL - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel #65,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_interrupt - -inthandler2: - SAVE_ALL - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel #66,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_interrupt - -inthandler3: - SAVE_ALL - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel #67,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_interrupt - -inthandler4: - SAVE_ALL - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel #68,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_interrupt - -inthandler5: - SAVE_ALL - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel #69,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_interrupt - -inthandler6: - SAVE_ALL - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel #70,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_interrupt - -inthandler7: - SAVE_ALL - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel #71,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_interrupt - -inthandler: - SAVE_ALL - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel %d0,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_interrupt - -ret_from_interrupt: - jeq 1f -2: - RESTORE_ALL -1: - moveb %sp@(PT_OFF_SR), %d0 - and #7, %d0 - jhi 2b - - /* check if we need to do software interrupts */ - jeq ret_from_exception - - pea ret_from_exception - jra do_softirq - - -/* - * Handler for uninitialized and spurious interrupts. - */ -ENTRY(bad_interrupt) - addql #1,num_spurious - rte - -/* - * Beware - when entering resume, prev (the current task) is - * in a0, next (the new task) is in a1,so don't change these - * registers until their contents are no longer needed. - */ -ENTRY(resume) - movel %a0,%d1 /* save prev thread in d1 */ - movew %sr,%a0@(TASK_THREAD+THREAD_SR) /* save sr */ - movel %usp,%a2 /* save usp */ - movel %a2,%a0@(TASK_THREAD+THREAD_USP) - - SAVE_SWITCH_STACK - movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack */ - movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new thread stack */ - RESTORE_SWITCH_STACK - - movel %a1@(TASK_THREAD+THREAD_USP),%a0 /* restore user stack */ - movel %a0,%usp - movew %a1@(TASK_THREAD+THREAD_SR),%sr /* restore thread status reg */ - rts - diff --git a/arch/m68knommu/platform/68328/head-de2.S b/arch/m68knommu/platform/68328/head-de2.S deleted file mode 100644 index f632fdc..0000000 --- a/arch/m68knommu/platform/68328/head-de2.S +++ /dev/null @@ -1,128 +0,0 @@ - -#define MEM_END 0x00800000 /* Memory size 8Mb */ - -#undef CRT_DEBUG - -.macro PUTC CHAR -#ifdef CRT_DEBUG - moveq #\CHAR, %d7 - jsr putc -#endif -.endm - - .global _start - .global _rambase - .global _ramvec - .global _ramstart - .global _ramend - - .data - -/* - * Set up the usable of RAM stuff - */ -_rambase: - .long 0 -_ramvec: - .long 0 -_ramstart: - .long 0 -_ramend: - .long 0 - - .text - -_start: - -/* - * Setup initial stack - */ - /* disable all interrupts */ - movew #0x2700, %sr - movel #-1, 0xfffff304 - movel #MEM_END-4, %sp - - PUTC '\r' - PUTC '\n' - PUTC 'A' - PUTC 'B' - -/* - * Determine end of RAM - */ - - movel #MEM_END, %a0 - movel %a0, _ramend - - PUTC 'C' - -/* - * Move ROM filesystem above bss :-) - */ - - moveal #_sbss, %a0 /* romfs at the start of bss */ - moveal #_ebss, %a1 /* Set up destination */ - movel %a0, %a2 /* Copy of bss start */ - - movel 8(%a0), %d1 /* Get size of ROMFS */ - addql #8, %d1 /* Allow for rounding */ - andl #0xfffffffc, %d1 /* Whole words */ - - addl %d1, %a0 /* Copy from end */ - addl %d1, %a1 /* Copy from end */ - movel %a1, _ramstart /* Set start of ram */ - -1: - movel -(%a0), %d0 /* Copy dword */ - movel %d0, -(%a1) - cmpl %a0, %a2 /* Check if at end */ - bne 1b - - PUTC 'D' - -/* - * Initialize BSS segment to 0 - */ - - lea _sbss, %a0 - lea _ebss, %a1 - - /* Copy 0 to %a0 until %a0 == %a1 */ -2: cmpal %a0, %a1 - beq 1f - clrl (%a0)+ - bra 2b -1: - - PUTC 'E' - -/* - * Load the current task pointer and stack - */ - - lea init_thread_union, %a0 - lea 0x2000(%a0), %sp - - PUTC 'F' - PUTC '\r' - PUTC '\n' - -/* - * Go - */ - - jmp start_kernel - -/* - * Local functions - */ - -#ifdef CRT_DEBUG -putc: - moveb %d7, 0xfffff907 -1: - movew 0xfffff906, %d7 - andw #0x2000, %d7 - beq 1b - rts -#endif diff --git a/arch/m68knommu/platform/68328/head-pilot.S b/arch/m68knommu/platform/68328/head-pilot.S deleted file mode 100644 index aecff53..0000000 --- a/arch/m68knommu/platform/68328/head-pilot.S +++ /dev/null @@ -1,222 +0,0 @@ -/* - * linux/arch/m68knommu/platform/68328/head-pilot.S - * - A startup file for the MC68328 - * - * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, - * Kenneth Albanowski <kjahds@kjahds.com>, - * The Silver Hammer Group, Ltd. - * - * (c) 1995, Dionne & Associates - * (c) 1995, DKG Display Tech. - */ - -#define ASSEMBLY - -#define IMMED # -#define DBG_PUTC(x) moveb IMMED x, 0xfffff907 - - -.global _stext -.global _start - -.global _rambase -.global _ramvec -.global _ramstart -.global _ramend - -.global penguin_bits - -#ifdef CONFIG_PILOT - -#define IMR 0xFFFFF304 - - .data - .align 16 - -penguin_bits: -#include "bootlogo.rh" - -#endif - -/*****************************************************************************/ - -.data - -/* - * Set up the usable of RAM stuff. Size of RAM is determined then - * an initial stack set up at the end. - */ -.align 4 -_ramvec: -.long 0 -_rambase: -.long 0 -_ramstart: -.long 0 -_ramend: -.long 0 - -.text - -_start: -_stext: - - -#ifdef CONFIG_M68328 - -#ifdef CONFIG_PILOT - .byte 0x4e, 0xfa, 0x00, 0x0a /* Jmp +X bytes */ - .byte 'b', 'o', 'o', 't' - .word 10000 - - nop -#endif - - moveq #0, %d0 - movew %d0, 0xfffff618 /* Watchdog off */ - movel #0x00011f07, 0xfffff114 /* CS A1 Mask */ - - movew #0x0800, 0xfffff906 /* Ignore CTS */ - movew #0x010b, 0xfffff902 /* BAUD to 9600 */ - - movew #0x2410, 0xfffff200 /* PLLCR */ - movew #0x123, 0xfffff202 /* PLLFSR */ - -#ifdef CONFIG_PILOT - moveb #0, 0xfffffA27 /* LCKCON */ - movel #_start, 0xfffffA00 /* LSSA */ - moveb #0xa, 0xfffffA05 /* LVPW */ - movew #0x9f, 0xFFFFFa08 /* LXMAX */ - movew #0x9f, 0xFFFFFa0a /* LYMAX */ - moveb #9, 0xfffffa29 /* LBAR */ - moveb #0, 0xfffffa25 /* LPXCD */ - moveb #0x04, 0xFFFFFa20 /* LPICF */ - moveb #0x58, 0xfffffA27 /* LCKCON */ - moveb #0x85, 0xfffff429 /* PFDATA */ - moveb #0xd8, 0xfffffA27 /* LCKCON */ - moveb #0xc5, 0xfffff429 /* PFDATA */ - moveb #0xd5, 0xfffff429 /* PFDATA */ - - moveal #0x00100000, %a3 - moveal #0x100ffc00, %a4 -#endif /* CONFIG_PILOT */ - -#endif /* CONFIG_M68328 */ - - movew #0x2700, %sr - lea %a4@(-4), %sp - - DBG_PUTC('\r') - DBG_PUTC('\n') - DBG_PUTC('A') - - moveq #0,%d0 - movew #16384, %d0 /* PLL settle wait loop */ -L0: - subw #1, %d0 - bne L0 - - DBG_PUTC('B') - - /* Copy command line from beginning of RAM (+16) to end of bss */ - movel #CONFIG_VECTORBASE, %d7 - addl #16, %d7 - moveal %d7, %a0 - moveal #_ebss, %a1 - lea %a1@(512), %a2 - - DBG_PUTC('C') - - /* Copy %a0 to %a1 until %a1 == %a2 */ -L2: - movel %a0@+, %d0 - movel %d0, %a1@+ - cmpal %a1, %a2 - bhi L2 - - /* Copy data+init segment from ROM to RAM */ - moveal #_etext, %a0 - moveal #_sdata, %a1 - moveal #__init_end, %a2 - - DBG_PUTC('D') - - /* Copy %a0 to %a1 until %a1 == %a2 */ -LD1: - movel %a0@+, %d0 - movel %d0, %a1@+ - cmpal %a1, %a2 - bhi LD1 - - DBG_PUTC('E') - - moveal #_sbss, %a0 - moveal #_ebss, %a1 - - /* Copy 0 to %a0 until %a0 == %a1 */ -L1: - movel #0, %a0@+ - cmpal %a0, %a1 - bhi L1 - - DBG_PUTC('F') - - /* Copy command line from end of bss to command line */ - moveal #_ebss, %a0 - moveal #command_line, %a1 - lea %a1@(512), %a2 - - DBG_PUTC('G') - - /* Copy %a0 to %a1 until %a1 == %a2 */ -L3: - movel %a0@+, %d0 - movel %d0, %a1@+ - cmpal %a1, %a2 - bhi L3 - - movel #_sdata, %d0 - movel %d0, _rambase - movel #_ebss, %d0 - movel %d0, _ramstart - - movel %a4, %d0 - subl #4096, %d0 /* Reserve 4K of stack */ - moveq #79, %d7 - movel %d0, _ramend - - movel %a3, %d0 - movel %d0, rom_length - - pea 0 - pea env - pea %sp@(4) - pea 0 - - DBG_PUTC('H') - -#ifdef CONFIG_PILOT - movel #penguin_bits, 0xFFFFFA00 - moveb #10, 0xFFFFFA05 - movew #160, 0xFFFFFA08 - movew #160, 0xFFFFFA0A -#endif /* CONFIG_PILOT */ - - DBG_PUTC('I') - - lea init_thread_union, %a0 - lea 0x2000(%a0), %sp - - DBG_PUTC('J') - DBG_PUTC('\r') - DBG_PUTC('\n') - - jsr start_kernel -_exit: - - jmp _exit - - - .data -env: - .long 0 diff --git a/arch/m68knommu/platform/68328/head-ram.S b/arch/m68knommu/platform/68328/head-ram.S deleted file mode 100644 index 7f1aeea..0000000 --- a/arch/m68knommu/platform/68328/head-ram.S +++ /dev/null @@ -1,141 +0,0 @@ - - .global __main - .global __rom_start - - .global _rambase - .global _ramstart - - .global splash_bits - .global _start - .global _stext - .global _edata - -#define DEBUG -#define ROM_OFFSET 0x10C00000 -#define STACK_GAURD 0x10 - - .text - -_start: -_stext: - movew #0x2700, %sr /* Exceptions off! */ - -#if 0 - /* Init chip registers. uCsimm specific */ - moveb #0x00, 0xfffffb0b /* Watchdog off */ - moveb #0x10, 0xfffff000 /* SCR */ - - movew #0x2400, 0xfffff200 /* PLLCR */ - movew #0x0123, 0xfffff202 /* PLLFSR */ - - moveb #0x00, 0xfffff40b /* enable chip select */ - moveb #0x00, 0xfffff423 /* enable /DWE */ - moveb #0x08, 0xfffffd0d /* disable hardmap */ - moveb #0x07, 0xfffffd0e /* level 7 interrupt clear */ - - movew #0x8600, 0xfffff100 /* FLASH at 0x10c00000 */ - movew #0x018b, 0xfffff110 /* 2Meg, enable, 0ws */ - - movew #0x8f00, 0xfffffc00 /* DRAM configuration */ - movew #0x9667, 0xfffffc02 /* DRAM control */ - movew #0x0000, 0xfffff106 /* DRAM at 0x00000000 */ - movew #0x068f, 0xfffff116 /* 8Meg, enable, 0ws */ - - moveb #0x40, 0xfffff300 /* IVR */ - movel #0x007FFFFF, %d0 /* IMR */ - movel %d0, 0xfffff304 - - moveb 0xfffff42b, %d0 - andb #0xe0, %d0 - moveb %d0, 0xfffff42b - - moveb #0x08, 0xfffff907 /* Ignore CTS */ - movew #0x010b, 0xfffff902 /* BAUD to 9600 */ - movew #0xe100, 0xfffff900 /* enable */ -#endif - - movew #16384, %d0 /* PLL settle wait loop */ -L0: - subw #1, %d0 - bne L0 -#ifdef DEBUG - moveq #70, %d7 /* 'F' */ - moveb %d7,0xfffff907 /* No absolute addresses */ -pclp1: - movew 0xfffff906, %d7 - andw #0x2000, %d7 - beq pclp1 -#endif /* DEBUG */ - -#ifdef DEBUG - moveq #82, %d7 /* 'R' */ - moveb %d7,0xfffff907 /* No absolute addresses */ -pclp3: - movew 0xfffff906, %d7 - andw #0x2000, %d7 - beq pclp3 -#endif /* DEBUG */ - moveal #0x007ffff0, %ssp - moveal #_sbss, %a0 - moveal #_ebss, %a1 - - /* Copy 0 to %a0 until %a0 >= %a1 */ -L1: - movel #0, %a0@+ - cmpal %a0, %a1 - bhi L1 - -#ifdef DEBUG - moveq #67, %d7 /* 'C' */ - jsr putc -#endif /* DEBUG */ - - pea 0 - pea env - pea %sp@(4) - pea 0 - -#ifdef DEBUG - moveq #70, %d7 /* 'F' */ - jsr putc -#endif /* DEBUG */ - -lp: - jsr start_kernel - jmp lp -_exit: - - jmp _exit - -__main: - /* nothing */ - rts - -#ifdef DEBUG -putc: - moveb %d7,0xfffff907 -pclp: - movew 0xfffff906, %d7 - andw #0x2000, %d7 - beq pclp - rts -#endif /* DEBUG */ - - .data - -/* - * Set up the usable of RAM stuff. Size of RAM is determined then - * an initial stack set up at the end. - */ -.align 4 -_ramvec: -.long 0 -_rambase: -.long 0 -_ramstart: -.long 0 -_ramend: -.long 0 - -env: - .long 0 diff --git a/arch/m68knommu/platform/68328/head-rom.S b/arch/m68knommu/platform/68328/head-rom.S deleted file mode 100644 index 6ec77d3..0000000 --- a/arch/m68knommu/platform/68328/head-rom.S +++ /dev/null @@ -1,110 +0,0 @@ - - .global _start - .global _stext - - .global _rambase - .global _ramvec - .global _ramstart - .global _ramend - -#ifdef CONFIG_INIT_LCD - .global splash_bits -#endif - - .data - -/* - * Set up the usable of RAM stuff. Size of RAM is determined then - * an initial stack set up at the end. - */ -.align 4 -_ramvec: -.long 0 -_rambase: -.long 0 -_ramstart: -.long 0 -_ramend: -.long 0 - -#define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE) - -#ifdef CONFIG_INIT_LCD -splash_bits: -#include "bootlogo.rh" -#endif - - .text -_start: -_stext: movew #0x2700,%sr -#ifdef CONFIG_INIT_LCD - movel #splash_bits, 0xfffffA00 /* LSSA */ - moveb #0x28, 0xfffffA05 /* LVPW */ - movew #0x280, 0xFFFFFa08 /* LXMAX */ - movew #0x1df, 0xFFFFFa0a /* LYMAX */ - moveb #0, 0xfffffa29 /* LBAR */ - moveb #0, 0xfffffa25 /* LPXCD */ - moveb #0x08, 0xFFFFFa20 /* LPICF */ - moveb #0x01, 0xFFFFFA21 /* -ve pol */ - moveb #0x81, 0xfffffA27 /* LCKCON */ - movew #0xff00, 0xfffff412 /* LCD pins */ -#endif - moveal #RAMEND-CONFIG_MEMORY_RESERVE*0x100000 - 0x10, %sp - movew #32767, %d0 /* PLL settle wait loop */ -1: subq #1, %d0 - bne 1b - - /* Copy data segment from ROM to RAM */ - moveal #_etext, %a0 - moveal #_sdata, %a1 - moveal #_edata, %a2 - - /* Copy %a0 to %a1 until %a1 == %a2 */ -1: movel %a0@+, %a1@+ - cmpal %a1, %a2 - bhi 1b - - moveal #_sbss, %a0 - moveal #_ebss, %a1 - /* Copy 0 to %a0 until %a0 == %a1 */ - -1: - clrl %a0@+ - cmpal %a0, %a1 - bhi 1b - - movel #_sdata, %d0 - movel %d0, _rambase - movel #_ebss, %d0 - movel %d0, _ramstart - movel #RAMEND-CONFIG_MEMORY_RESERVE*0x100000, %d0 - movel %d0, _ramend - movel #CONFIG_VECTORBASE, %d0 - movel %d0, _ramvec - -/* - * load the current task pointer and stack - */ - lea init_thread_union, %a0 - lea 0x2000(%a0), %sp - -1: jsr start_kernel - bra 1b -_exit: - - jmp _exit - - -putc: - moveb %d7,0xfffff907 -1: - movew 0xfffff906, %d7 - andw #0x2000, %d7 - beq 1b - rts - - .data -env: - .long 0 - .text - diff --git a/arch/m68knommu/platform/68328/ints.c b/arch/m68knommu/platform/68328/ints.c deleted file mode 100644 index e563183..0000000 --- a/arch/m68knommu/platform/68328/ints.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * linux/arch/m68knommu/platform/68328/ints.c - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - * Copyright 1996 Roman Zippel - * Copyright 1999 D. Jeff Dionne <jeff@rt-control.com> - */ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <asm/traps.h> -#include <asm/io.h> -#include <asm/machdep.h> - -#if defined(CONFIG_M68328) -#include <asm/MC68328.h> -#elif defined(CONFIG_M68EZ328) -#include <asm/MC68EZ328.h> -#elif defined(CONFIG_M68VZ328) -#include <asm/MC68VZ328.h> -#endif - -/* assembler routines */ -asmlinkage void system_call(void); -asmlinkage void buserr(void); -asmlinkage void trap(void); -asmlinkage void trap3(void); -asmlinkage void trap4(void); -asmlinkage void trap5(void); -asmlinkage void trap6(void); -asmlinkage void trap7(void); -asmlinkage void trap8(void); -asmlinkage void trap9(void); -asmlinkage void trap10(void); -asmlinkage void trap11(void); -asmlinkage void trap12(void); -asmlinkage void trap13(void); -asmlinkage void trap14(void); -asmlinkage void trap15(void); -asmlinkage void trap33(void); -asmlinkage void trap34(void); -asmlinkage void trap35(void); -asmlinkage void trap36(void); -asmlinkage void trap37(void); -asmlinkage void trap38(void); -asmlinkage void trap39(void); -asmlinkage void trap40(void); -asmlinkage void trap41(void); -asmlinkage void trap42(void); -asmlinkage void trap43(void); -asmlinkage void trap44(void); -asmlinkage void trap45(void); -asmlinkage void trap46(void); -asmlinkage void trap47(void); -asmlinkage irqreturn_t bad_interrupt(int, void *); -asmlinkage irqreturn_t inthandler(void); -asmlinkage irqreturn_t inthandler1(void); -asmlinkage irqreturn_t inthandler2(void); -asmlinkage irqreturn_t inthandler3(void); -asmlinkage irqreturn_t inthandler4(void); -asmlinkage irqreturn_t inthandler5(void); -asmlinkage irqreturn_t inthandler6(void); -asmlinkage irqreturn_t inthandler7(void); - -extern e_vector *_ramvec; - -/* The number of spurious interrupts */ -volatile unsigned int num_spurious; - -/* The 68k family did not have a good way to determine the source - * of interrupts until later in the family. The EC000 core does - * not provide the vector number on the stack, we vector everything - * into one vector and look in the blasted mask register... - * This code is designed to be fast, almost constant time, not clean! - */ -void process_int(int vec, struct pt_regs *fp) -{ - int irq; - int mask; - - unsigned long pend = ISR; - - while (pend) { - if (pend & 0x0000ffff) { - if (pend & 0x000000ff) { - if (pend & 0x0000000f) { - mask = 0x00000001; - irq = 0; - } else { - mask = 0x00000010; - irq = 4; - } - } else { - if (pend & 0x00000f00) { - mask = 0x00000100; - irq = 8; - } else { - mask = 0x00001000; - irq = 12; - } - } - } else { - if (pend & 0x00ff0000) { - if (pend & 0x000f0000) { - mask = 0x00010000; - irq = 16; - } else { - mask = 0x00100000; - irq = 20; - } - } else { - if (pend & 0x0f000000) { - mask = 0x01000000; - irq = 24; - } else { - mask = 0x10000000; - irq = 28; - } - } - } - - while (! (mask & pend)) { - mask <<=1; - irq++; - } - - do_IRQ(irq, fp); - pend &= ~mask; - } -} - -static void intc_irq_unmask(struct irq_data *d) -{ - IMR &= ~(1 << d->irq); -} - -static void intc_irq_mask(struct irq_data *d) -{ - IMR |= (1 << d->irq); -} - -static struct irq_chip intc_irq_chip = { - .name = "M68K-INTC", - .irq_mask = intc_irq_mask, - .irq_unmask = intc_irq_unmask, -}; - -/* - * This function should be called during kernel startup to initialize - * the machine vector table. - */ -void __init init_IRQ(void) -{ - int i; - - /* set up the vectors */ - for (i = 72; i < 256; ++i) - _ramvec[i] = (e_vector) bad_interrupt; - - _ramvec[32] = system_call; - - _ramvec[65] = (e_vector) inthandler1; - _ramvec[66] = (e_vector) inthandler2; - _ramvec[67] = (e_vector) inthandler3; - _ramvec[68] = (e_vector) inthandler4; - _ramvec[69] = (e_vector) inthandler5; - _ramvec[70] = (e_vector) inthandler6; - _ramvec[71] = (e_vector) inthandler7; - - IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */ - - /* turn off all interrupts */ - IMR = ~0; - - for (i = 0; (i < NR_IRQS); i++) { - set_irq_chip(i, &intc_irq_chip); - set_irq_handler(i, handle_level_irq); - } -} - diff --git a/arch/m68knommu/platform/68328/romvec.S b/arch/m68knommu/platform/68328/romvec.S deleted file mode 100644 index 3108446..0000000 --- a/arch/m68knommu/platform/68328/romvec.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * linux/arch/m68knommu/platform/68328/romvec.S - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - * Copyright 1996 Roman Zippel - * Copyright 1999 D. Jeff Dionne <jeff@rt-control.com> - * Copyright 2006 Greg Ungerer <gerg@snapgear.com> - */ - -.global _start -.global _buserr -.global trap -.global system_call - -.section .romvec - -e_vectors: -.long CONFIG_RAMBASE+CONFIG_RAMSIZE-4, _start, buserr, trap -.long trap, trap, trap, trap -.long trap, trap, trap, trap -.long trap, trap, trap, trap -.long trap, trap, trap, trap -.long trap, trap, trap, trap -.long trap, trap, trap, trap -.long trap, trap, trap, trap -/* TRAP #0-15 */ -.long system_call, trap, trap, trap -.long trap, trap, trap, trap -.long trap, trap, trap, trap -.long trap, trap, trap, trap -.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - diff --git a/arch/m68knommu/platform/68328/timers.c b/arch/m68knommu/platform/68328/timers.c deleted file mode 100644 index 309f7259..0000000 --- a/arch/m68knommu/platform/68328/timers.c +++ /dev/null @@ -1,134 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/68328/timers.c - * - * Copyright (C) 1993 Hamish Macdonald - * Copyright (C) 1999 D. Jeff Dionne - * Copyright (C) 2001 Georges Menie, Ken Desmet - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -/***************************************************************************/ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/mm.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/clocksource.h> -#include <asm/setup.h> -#include <asm/system.h> -#include <asm/pgtable.h> -#include <asm/machdep.h> -#include <asm/MC68VZ328.h> - -/***************************************************************************/ - -#if defined(CONFIG_DRAGEN2) -/* with a 33.16 MHz clock, this will give usec resolution to the time functions */ -#define CLOCK_SOURCE TCTL_CLKSOURCE_SYSCLK -#define CLOCK_PRE 7 -#define TICKS_PER_JIFFY 41450 - -#elif defined(CONFIG_XCOPILOT_BUGS) -/* - * The only thing I know is that CLK32 is not available on Xcopilot - * I have little idea about what frequency SYSCLK has on Xcopilot. - * The values for prescaler and compare registers were simply - * taken from the original source - */ -#define CLOCK_SOURCE TCTL_CLKSOURCE_SYSCLK -#define CLOCK_PRE 2 -#define TICKS_PER_JIFFY 0xd7e4 - -#else -/* default to using the 32Khz clock */ -#define CLOCK_SOURCE TCTL_CLKSOURCE_32KHZ -#define CLOCK_PRE 31 -#define TICKS_PER_JIFFY 10 -#endif - -static u32 m68328_tick_cnt; - -/***************************************************************************/ - -static irqreturn_t hw_tick(int irq, void *dummy) -{ - /* Reset Timer1 */ - TSTAT &= 0; - - m68328_tick_cnt += TICKS_PER_JIFFY; - return arch_timer_interrupt(irq, dummy); -} - -/***************************************************************************/ - -static struct irqaction m68328_timer_irq = { - .name = "timer", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = hw_tick, -}; - -/***************************************************************************/ - -static cycle_t m68328_read_clk(struct clocksource *cs) -{ - unsigned long flags; - u32 cycles; - - local_irq_save(flags); - cycles = m68328_tick_cnt + TCN; - local_irq_restore(flags); - - return cycles; -} - -/***************************************************************************/ - -static struct clocksource m68328_clk = { - .name = "timer", - .rating = 250, - .read = m68328_read_clk, - .shift = 20, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -/***************************************************************************/ - -void hw_timer_init(void) -{ - /* disable timer 1 */ - TCTL = 0; - - /* set ISR */ - setup_irq(TMR_IRQ_NUM, &m68328_timer_irq); - - /* Restart mode, Enable int, Set clock source */ - TCTL = TCTL_OM | TCTL_IRQEN | CLOCK_SOURCE; - TPRER = CLOCK_PRE; - TCMP = TICKS_PER_JIFFY; - - /* Enable timer 1 */ - TCTL |= TCTL_TEN; - m68328_clk.mult = clocksource_hz2mult(TICKS_PER_JIFFY*HZ, m68328_clk.shift); - clocksource_register(&m68328_clk); -} - -/***************************************************************************/ - -void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec) -{ - long now = RTCTIME; - - *year = *mon = *day = 1; - *hour = (now >> 24) % 24; - *min = (now >> 16) % 60; - *sec = now % 60; -} - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/68360/Makefile b/arch/m68knommu/platform/68360/Makefile deleted file mode 100644 index cf5af73..0000000 --- a/arch/m68knommu/platform/68360/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# Makefile for arch/m68knommu/platform/68360. -# - -obj-y := config.o commproc.o entry.o ints.o - -extra-y := head.o - -$(obj)/head.o: $(obj)/head-$(MODEL).o - ln -sf head-$(MODEL).o $(obj)/head.o diff --git a/arch/m68knommu/platform/68360/commproc.c b/arch/m68knommu/platform/68360/commproc.c deleted file mode 100644 index 8e4e10c..0000000 --- a/arch/m68knommu/platform/68360/commproc.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * General Purpose functions for the global management of the - * Communication Processor Module. - * - * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * In addition to the individual control of the communication - * channels, there are a few functions that globally affect the - * communication processor. - * - * Buffer descriptors must be allocated from the dual ported memory - * space. The allocator for that is here. When the communication - * process is reset, we reclaim the memory available. There is - * currently no deallocator for this memory. - * The amount of space available is platform dependent. On the - * MBX, the EPPC software loads additional microcode into the - * communication processor, and uses some of the DP ram for this - * purpose. Current, the first 512 bytes and the last 256 bytes of - * memory are used. Right now I am conservative and only use the - * memory that can never be used for microcode. If there are - * applications that require more DP ram, we can expand the boundaries - * but then we have to be careful of any downloaded microcode. - * - */ - -/* - * Michael Leslie <mleslie@lineo.com> - * adapted Dan Malek's ppc8xx drivers to M68360 - * - */ - -#include <linux/errno.h> -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <linux/interrupt.h> -#include <asm/irq.h> -#include <asm/m68360.h> -#include <asm/commproc.h> - -/* #include <asm/page.h> */ -/* #include <asm/pgtable.h> */ -extern void *_quicc_base; -extern unsigned int system_clock; - - -static uint dp_alloc_base; /* Starting offset in DP ram */ -static uint dp_alloc_top; /* Max offset + 1 */ - -#if 0 -static void *host_buffer; /* One page of host buffer */ -static void *host_end; /* end + 1 */ -#endif - -/* struct cpm360_t *cpmp; */ /* Pointer to comm processor space */ - -QUICC *pquicc; -/* QUICC *quicc_dpram; */ /* mleslie - temporary; use extern pquicc elsewhere instead */ - - -/* CPM interrupt vector functions. */ -struct cpm_action { - void (*handler)(void *); - void *dev_id; -}; -static struct cpm_action cpm_vecs[CPMVEC_NR]; -static void cpm_interrupt(int irq, void * dev, struct pt_regs * regs); -static void cpm_error_interrupt(void *); - -/* prototypes: */ -void cpm_install_handler(int vec, void (*handler)(), void *dev_id); -void m360_cpm_reset(void); - - - - -void m360_cpm_reset() -{ -/* pte_t *pte; */ - - pquicc = (struct quicc *)(_quicc_base); /* initialized in crt0_rXm.S */ - - /* Perform a CPM reset. */ - pquicc->cp_cr = (SOFTWARE_RESET | CMD_FLAG); - - /* Wait for CPM to become ready (should be 2 clocks). */ - while (pquicc->cp_cr & CMD_FLAG); - - /* On the recommendation of the 68360 manual, p. 7-60 - * - Set sdma interrupt service mask to 7 - * - Set sdma arbitration ID to 4 - */ - pquicc->sdma_sdcr = 0x0740; - - - /* Claim the DP memory for our use. - */ - dp_alloc_base = CPM_DATAONLY_BASE; - dp_alloc_top = dp_alloc_base + CPM_DATAONLY_SIZE; - - - /* Set the host page for allocation. - */ - /* host_buffer = host_page_addr; */ - /* host_end = host_page_addr + PAGE_SIZE; */ - - /* pte = find_pte(&init_mm, host_page_addr); */ - /* pte_val(*pte) |= _PAGE_NO_CACHE; */ - /* flush_tlb_page(current->mm->mmap, host_buffer); */ - - /* Tell everyone where the comm processor resides. - */ -/* cpmp = (cpm360_t *)commproc; */ -} - - -/* This is called during init_IRQ. We used to do it above, but this - * was too early since init_IRQ was not yet called. - */ -void -cpm_interrupt_init(void) -{ - /* Initialize the CPM interrupt controller. - * NOTE THAT pquicc had better have been initialized! - * reference: MC68360UM p. 7-377 - */ - pquicc->intr_cicr = - (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | - (CPM_INTERRUPT << 13) | - CICR_HP_MASK | - (CPM_VECTOR_BASE << 5) | - CICR_SPS; - - /* mask all CPM interrupts from reaching the cpu32 core: */ - pquicc->intr_cimr = 0; - - - /* mles - If I understand correctly, the 360 just pops over to the CPM - * specific vector, obviating the necessity to vector through the IRQ - * whose priority the CPM is set to. This needs a closer look, though. - */ - - /* Set our interrupt handler with the core CPU. */ -/* if (request_irq(CPM_INTERRUPT, cpm_interrupt, 0, "cpm", NULL) != 0) */ -/* panic("Could not allocate CPM IRQ!"); */ - - /* Install our own error handler. - */ - /* I think we want to hold off on this one for the moment - mles */ - /* cpm_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL); */ - - /* master CPM interrupt enable */ - /* pquicc->intr_cicr |= CICR_IEN; */ /* no such animal for 360 */ -} - - - -/* CPM interrupt controller interrupt. -*/ -static void -cpm_interrupt(int irq, void * dev, struct pt_regs * regs) -{ - /* uint vec; */ - - /* mles: Note that this stuff is currently being performed by - * M68360_do_irq(int vec, struct pt_regs *fp), in ../ints.c */ - - /* figure out the vector */ - /* call that vector's handler */ - /* clear the irq's bit in the service register */ - -#if 0 /* old 860 stuff: */ - /* Get the vector by setting the ACK bit and then reading - * the register. - */ - ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr = 1; - vec = ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr; - vec >>= 11; - - - if (cpm_vecs[vec].handler != 0) - (*cpm_vecs[vec].handler)(cpm_vecs[vec].dev_id); - else - ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << vec); - - /* After servicing the interrupt, we have to remove the status - * indicator. - */ - ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr |= (1 << vec); -#endif - -} - -/* The CPM can generate the error interrupt when there is a race condition - * between generating and masking interrupts. All we have to do is ACK it - * and return. This is a no-op function so we don't need any special - * tests in the interrupt handler. - */ -static void -cpm_error_interrupt(void *dev) -{ -} - -/* Install a CPM interrupt handler. -*/ -void -cpm_install_handler(int vec, void (*handler)(), void *dev_id) -{ - - request_irq(vec, handler, 0, "timer", dev_id); - -/* if (cpm_vecs[vec].handler != 0) */ -/* printk(KERN_INFO "CPM interrupt %x replacing %x\n", */ -/* (uint)handler, (uint)cpm_vecs[vec].handler); */ -/* cpm_vecs[vec].handler = handler; */ -/* cpm_vecs[vec].dev_id = dev_id; */ - - /* ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr |= (1 << vec); */ -/* pquicc->intr_cimr |= (1 << vec); */ - -} - -/* Free a CPM interrupt handler. -*/ -void -cpm_free_handler(int vec) -{ - cpm_vecs[vec].handler = NULL; - cpm_vecs[vec].dev_id = NULL; - /* ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << vec); */ - pquicc->intr_cimr &= ~(1 << vec); -} - - - - -/* Allocate some memory from the dual ported ram. We may want to - * enforce alignment restrictions, but right now everyone is a good - * citizen. - */ -uint -m360_cpm_dpalloc(uint size) -{ - uint retloc; - - if ((dp_alloc_base + size) >= dp_alloc_top) - return(CPM_DP_NOSPACE); - - retloc = dp_alloc_base; - dp_alloc_base += size; - - return(retloc); -} - - -#if 0 /* mleslie - for now these are simply kmalloc'd */ -/* We also own one page of host buffer space for the allocation of - * UART "fifos" and the like. - */ -uint -m360_cpm_hostalloc(uint size) -{ - uint retloc; - - if ((host_buffer + size) >= host_end) - return(0); - - retloc = host_buffer; - host_buffer += size; - - return(retloc); -} -#endif - - -/* Set a baud rate generator. This needs lots of work. There are - * four BRGs, any of which can be wired to any channel. - * The internal baud rate clock is the system clock divided by 16. - * This assumes the baudrate is 16x oversampled by the uart. - */ -/* #define BRG_INT_CLK (((bd_t *)__res)->bi_intfreq * 1000000) */ -#define BRG_INT_CLK system_clock -#define BRG_UART_CLK (BRG_INT_CLK/16) - -void -m360_cpm_setbrg(uint brg, uint rate) -{ - volatile uint *bp; - - /* This is good enough to get SMCs running..... - */ - /* bp = (uint *)&cpmp->cp_brgc1; */ - bp = (volatile uint *)(&pquicc->brgc[0].l); - bp += brg; - *bp = ((BRG_UART_CLK / rate - 1) << 1) | CPM_BRG_EN; -} - - -/* - * Local variables: - * c-indent-level: 4 - * c-basic-offset: 4 - * tab-width: 4 - * End: - */ diff --git a/arch/m68knommu/platform/68360/config.c b/arch/m68knommu/platform/68360/config.c deleted file mode 100644 index 9dd5bca..0000000 --- a/arch/m68knommu/platform/68360/config.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * linux/arch/m68knommu/platform/68360/config.c - * - * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> - * Copyright (C) 1993 Hamish Macdonald - * Copyright (C) 1999 D. Jeff Dionne <jeff@uclinux.org> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include <stdarg.h> -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/mm.h> -#include <linux/interrupt.h> -#include <linux/irq.h> - -#include <asm/setup.h> -#include <asm/system.h> -#include <asm/pgtable.h> -#include <asm/machdep.h> -#include <asm/m68360.h> - -#ifdef CONFIG_UCQUICC -#include <asm/bootstd.h> -#endif - -extern void m360_cpm_reset(void); - -// Mask to select if the PLL prescaler is enabled. -#define MCU_PREEN ((unsigned short)(0x0001 << 13)) - -#if defined(CONFIG_UCQUICC) -#define OSCILLATOR (unsigned long int)33000000 -#endif - -unsigned long int system_clock; - -extern QUICC *pquicc; - -/* TODO DON"T Hard Code this */ -/* calculate properly using the right PLL and prescaller */ -// unsigned int system_clock = 33000000l; -extern unsigned long int system_clock; //In kernel setup.c - - -static irqreturn_t hw_tick(int irq, void *dummy) -{ - /* Reset Timer1 */ - /* TSTAT &= 0; */ - - pquicc->timer_ter1 = 0x0002; /* clear timer event */ - - return arch_timer_interrupt(irq, dummy); -} - -static struct irqaction m68360_timer_irq = { - .name = "timer", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = hw_tick, -}; - -void hw_timer_init(void) -{ - unsigned char prescaler; - unsigned short tgcr_save; - -#if 0 - /* Restart mode, Enable int, 32KHz, Enable timer */ - TCTL = TCTL_OM | TCTL_IRQEN | TCTL_CLKSOURCE_32KHZ | TCTL_TEN; - /* Set prescaler (Divide 32KHz by 32)*/ - TPRER = 31; - /* Set compare register 32Khz / 32 / 10 = 100 */ - TCMP = 10; - - request_irq(IRQ_MACHSPEC | 1, timer_routine, 0, "timer", NULL); -#endif - - /* General purpose quicc timers: MC68360UM p7-20 */ - - /* Set up timer 1 (in [1..4]) to do 100Hz */ - tgcr_save = pquicc->timer_tgcr & 0xfff0; - pquicc->timer_tgcr = tgcr_save; /* stop and reset timer 1 */ - /* pquicc->timer_tgcr |= 0x4444; */ /* halt timers when FREEZE (ie bdm freeze) */ - - prescaler = 8; - pquicc->timer_tmr1 = 0x001a | /* or=1, frr=1, iclk=01b */ - (unsigned short)((prescaler - 1) << 8); - - pquicc->timer_tcn1 = 0x0000; /* initial count */ - /* calculate interval for 100Hz based on the _system_clock: */ - pquicc->timer_trr1 = (system_clock/ prescaler) / HZ; /* reference count */ - - pquicc->timer_ter1 = 0x0003; /* clear timer events */ - - /* enable timer 1 interrupt in CIMR */ - setup_irq(CPMVEC_TIMER1, &m68360_timer_irq); - - /* Start timer 1: */ - tgcr_save = (pquicc->timer_tgcr & 0xfff0) | 0x0001; - pquicc->timer_tgcr = tgcr_save; -} - -void BSP_gettod (int *yearp, int *monp, int *dayp, - int *hourp, int *minp, int *secp) -{ -} - -int BSP_set_clock_mmss(unsigned long nowtime) -{ -#if 0 - short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60; - - tod->second1 = real_seconds / 10; - tod->second2 = real_seconds % 10; - tod->minute1 = real_minutes / 10; - tod->minute2 = real_minutes % 10; -#endif - return 0; -} - -void BSP_reset (void) -{ - local_irq_disable(); - asm volatile ( - "moveal #_start, %a0;\n" - "moveb #0, 0xFFFFF300;\n" - "moveal 0(%a0), %sp;\n" - "moveal 4(%a0), %a0;\n" - "jmp (%a0);\n" - ); -} - -unsigned char *scc1_hwaddr; -static int errno; - -#if defined (CONFIG_UCQUICC) -_bsc0(char *, getserialnum) -_bsc1(unsigned char *, gethwaddr, int, a) -_bsc1(char *, getbenv, char *, a) -#endif - - -void config_BSP(char *command, int len) -{ - unsigned char *p; - - m360_cpm_reset(); - - /* Calculate the real system clock value. */ - { - unsigned int local_pllcr = (unsigned int)(pquicc->sim_pllcr); - if( local_pllcr & MCU_PREEN ) // If the prescaler is dividing by 128 - { - int mf = (int)(pquicc->sim_pllcr & 0x0fff); - system_clock = (OSCILLATOR / 128) * (mf + 1); - } - else - { - int mf = (int)(pquicc->sim_pllcr & 0x0fff); - system_clock = (OSCILLATOR) * (mf + 1); - } - } - - printk(KERN_INFO "\n68360 QUICC support (C) 2000 Lineo Inc.\n"); - -#if defined(CONFIG_UCQUICC) && 0 - printk(KERN_INFO "uCquicc serial string [%s]\n",getserialnum()); - p = scc1_hwaddr = gethwaddr(0); - printk(KERN_INFO "uCquicc hwaddr %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", - p[0], p[1], p[2], p[3], p[4], p[5]); - - p = getbenv("APPEND"); - if (p) - strcpy(p,command); - else - command[0] = 0; -#else - scc1_hwaddr = "\00\01\02\03\04\05"; -#endif - - mach_gettod = BSP_gettod; - mach_reset = BSP_reset; -} diff --git a/arch/m68knommu/platform/68360/entry.S b/arch/m68knommu/platform/68360/entry.S deleted file mode 100644 index 46c1b18..0000000 --- a/arch/m68knommu/platform/68360/entry.S +++ /dev/null @@ -1,184 +0,0 @@ -/* - * linux/arch/m68knommu/platform/68360/entry.S - * - * Copyright (C) 1991, 1992 Linus Torvalds - * Copyright (C) 2001 SED Systems, a Division of Calian Ltd. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file README.legal in the main directory of this archive - * for more details. - * - * Linux/m68k support by Hamish Macdonald - * M68360 Port by SED Systems, and Lineo. - */ - -#include <linux/sys.h> -#include <linux/linkage.h> -#include <asm/thread_info.h> -#include <asm/unistd.h> -#include <asm/errno.h> -#include <asm/setup.h> -#include <asm/segment.h> -#include <asm/traps.h> -#include <asm/asm-offsets.h> -#include <asm/entry.h> - -.text - -.globl system_call -.globl resume -.globl ret_from_exception -.globl ret_from_signal -.globl sys_call_table -.globl ret_from_interrupt -.globl bad_interrupt -.globl inthandler - -badsys: - movel #-ENOSYS,%sp@(PT_OFF_D0) - jra ret_from_exception - -do_trace: - movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/ - subql #4,%sp - SAVE_SWITCH_STACK - jbsr syscall_trace_enter - RESTORE_SWITCH_STACK - addql #4,%sp - movel %sp@(PT_OFF_ORIG_D0),%d1 - movel #-ENOSYS,%d0 - cmpl #NR_syscalls,%d1 - jcc 1f - lsl #2,%d1 - lea sys_call_table, %a0 - jbsr %a0@(%d1) - -1: movel %d0,%sp@(PT_OFF_D0) /* save the return value */ - subql #4,%sp /* dummy return address */ - SAVE_SWITCH_STACK - jbsr syscall_trace_leave - -ret_from_signal: - RESTORE_SWITCH_STACK - addql #4,%sp - jra ret_from_exception - -ENTRY(system_call) - SAVE_ALL - - /* save top of frame*/ - pea %sp@ - jbsr set_esp0 - addql #4,%sp - - movel %sp@(PT_OFF_ORIG_D0),%d0 - - movel %sp,%d1 /* get thread_info pointer */ - andl #-THREAD_SIZE,%d1 - movel %d1,%a2 - btst #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8) - jne do_trace - cmpl #NR_syscalls,%d0 - jcc badsys - lsl #2,%d0 - lea sys_call_table,%a0 - movel %a0@(%d0), %a0 - jbsr %a0@ - movel %d0,%sp@(PT_OFF_D0) /* save the return value*/ - -ret_from_exception: - btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel*/ - jeq Luser_return /* if so, skip resched, signals*/ - -Lkernel_return: - RESTORE_ALL - -Luser_return: - /* only allow interrupts when we are really the last one on the*/ - /* kernel stack, otherwise stack overflow can occur during*/ - /* heavy interrupt load*/ - andw #ALLOWINT,%sr - - movel %sp,%d1 /* get thread_info pointer */ - andl #-THREAD_SIZE,%d1 - movel %d1,%a2 -1: - move %a2@(TI_FLAGS),%d1 /* thread_info->flags */ - jne Lwork_to_do - RESTORE_ALL - -Lwork_to_do: - movel %a2@(TI_FLAGS),%d1 /* thread_info->flags */ - btst #TIF_NEED_RESCHED,%d1 - jne reschedule - -Lsignal_return: - subql #4,%sp /* dummy return address*/ - SAVE_SWITCH_STACK - pea %sp@(SWITCH_STACK_SIZE) - bsrw do_signal - addql #4,%sp - RESTORE_SWITCH_STACK - addql #4,%sp - jra 1b - -/* - * This is the main interrupt handler, responsible for calling do_IRQ() - */ -inthandler: - SAVE_ALL - movew %sp@(PT_OFF_FORMATVEC), %d0 - and.l #0x3ff, %d0 - lsr.l #0x02, %d0 - - movel %sp,%sp@- - movel %d0,%sp@- /* put vector # on stack*/ - jbsr do_IRQ /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_interrupt - -ret_from_interrupt: - jeq 1f -2: - RESTORE_ALL -1: - moveb %sp@(PT_OFF_SR), %d0 - and #7, %d0 - jhi 2b - /* check if we need to do software interrupts */ - - movel irq_stat+CPUSTAT_SOFTIRQ_PENDING,%d0 - jeq ret_from_exception - - pea ret_from_exception - jra do_softirq - - -/* - * Handler for uninitialized and spurious interrupts. - */ -bad_interrupt: - addql #1,num_spurious - rte - -/* - * Beware - when entering resume, prev (the current task) is - * in a0, next (the new task) is in a1,so don't change these - * registers until their contents are no longer needed. - */ -ENTRY(resume) - movel %a0,%d1 /* save prev thread in d1 */ - movew %sr,%a0@(TASK_THREAD+THREAD_SR) /* save sr */ - movel %usp,%a2 /* save usp */ - movel %a2,%a0@(TASK_THREAD+THREAD_USP) - - SAVE_SWITCH_STACK - movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack */ - movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new thread stack */ - RESTORE_SWITCH_STACK - - movel %a1@(TASK_THREAD+THREAD_USP),%a0 /* restore user stack */ - movel %a0,%usp - movew %a1@(TASK_THREAD+THREAD_SR),%sr /* restore thread status reg */ - rts - diff --git a/arch/m68knommu/platform/68360/head-ram.S b/arch/m68knommu/platform/68360/head-ram.S deleted file mode 100644 index 8eb94fb..0000000 --- a/arch/m68knommu/platform/68360/head-ram.S +++ /dev/null @@ -1,403 +0,0 @@ -/* arch/m68knommu/platform/68360/head-ram.S - * - * Startup code for Motorola 68360 - * - * Copyright 2001 (C) SED Systems, a Division of Calian Ltd. - * Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S - * Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7 - * uClinux Kernel - * Copyright (C) Michael Leslie <mleslie@lineo.com> - * Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S - * Copyright (C) 1998 D. Jeff Dionne <jeff@uclinux.org>, - * - */ -#define ASSEMBLY - -.global _stext -.global _start - -.global _rambase -.global _ramvec -.global _ramstart -.global _ramend - -.global _quicc_base -.global _periph_base - -#define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE) -#define ROMEND (CONFIG_ROMBASE + CONFIG_ROMSIZE) - -#define REGB 0x1000 -#define PEPAR (_dprbase + REGB + 0x0016) -#define GMR (_dprbase + REGB + 0x0040) -#define OR0 (_dprbase + REGB + 0x0054) -#define BR0 (_dprbase + REGB + 0x0050) -#define OR1 (_dprbase + REGB + 0x0064) -#define BR1 (_dprbase + REGB + 0x0060) -#define OR4 (_dprbase + REGB + 0x0094) -#define BR4 (_dprbase + REGB + 0x0090) -#define OR6 (_dprbase + REGB + 0x00b4) -#define BR6 (_dprbase + REGB + 0x00b0) -#define OR7 (_dprbase + REGB + 0x00c4) -#define BR7 (_dprbase + REGB + 0x00c0) - -#define MCR (_dprbase + REGB + 0x0000) -#define AVR (_dprbase + REGB + 0x0008) - -#define SYPCR (_dprbase + REGB + 0x0022) - -#define PLLCR (_dprbase + REGB + 0x0010) -#define CLKOCR (_dprbase + REGB + 0x000C) -#define CDVCR (_dprbase + REGB + 0x0014) - -#define BKAR (_dprbase + REGB + 0x0030) -#define BKCR (_dprbase + REGB + 0x0034) -#define SWIV (_dprbase + REGB + 0x0023) -#define PICR (_dprbase + REGB + 0x0026) -#define PITR (_dprbase + REGB + 0x002A) - -/* Define for all memory configuration */ -#define MCU_SIM_GMR 0x00000000 -#define SIM_OR_MASK 0x0fffffff - -/* Defines for chip select zero - the flash */ -#define SIM_OR0_MASK 0x20000002 -#define SIM_BR0_MASK 0x00000001 - - -/* Defines for chip select one - the RAM */ -#define SIM_OR1_MASK 0x10000000 -#define SIM_BR1_MASK 0x00000001 - -#define MCU_SIM_MBAR_ADRS 0x0003ff00 -#define MCU_SIM_MBAR_BA_MASK 0xfffff000 -#define MCU_SIM_MBAR_AS_MASK 0x00000001 - -#define MCU_SIM_PEPAR 0x00B4 - -#define MCU_DISABLE_INTRPTS 0x2700 -#define MCU_SIM_AVR 0x00 - -#define MCU_SIM_MCR 0x00005cff - -#define MCU_SIM_CLKOCR 0x00 -#define MCU_SIM_PLLCR 0x8000 -#define MCU_SIM_CDVCR 0x0000 - -#define MCU_SIM_SYPCR 0x0000 -#define MCU_SIM_SWIV 0x00 -#define MCU_SIM_PICR 0x0000 -#define MCU_SIM_PITR 0x0000 - - -#include <asm/m68360_regs.h> - - -/* - * By the time this RAM specific code begins to execute, DPRAM - * and DRAM should already be mapped and accessible. - */ - - .text -_start: -_stext: - nop - ori.w #MCU_DISABLE_INTRPTS, %sr /* disable interrupts: */ - /* We should not need to setup the boot stack the reset should do it. */ - movea.l #RAMEND, %sp /*set up stack at the end of DRAM:*/ - -set_mbar_register: - moveq.l #0x07, %d1 /* Setup MBAR */ - movec %d1, %dfc - - lea.l MCU_SIM_MBAR_ADRS, %a0 - move.l #_dprbase, %d0 - andi.l #MCU_SIM_MBAR_BA_MASK, %d0 - ori.l #MCU_SIM_MBAR_AS_MASK, %d0 - moves.l %d0, %a0@ - - moveq.l #0x05, %d1 - movec.l %d1, %dfc - - /* Now we can begin to access registers in DPRAM */ - -set_sim_mcr: - /* Set Module Configuration Register */ - move.l #MCU_SIM_MCR, MCR - - /* to do: Determine cause of reset */ - - /* - * configure system clock MC68360 p. 6-40 - * (value +1)*osc/128 = system clock - */ -set_sim_clock: - move.w #MCU_SIM_PLLCR, PLLCR - move.b #MCU_SIM_CLKOCR, CLKOCR - move.w #MCU_SIM_CDVCR, CDVCR - - /* Wait for the PLL to settle */ - move.w #16384, %d0 -pll_settle_wait: - subi.w #1, %d0 - bne pll_settle_wait - - /* Setup the system protection register, and watchdog timer register */ - move.b #MCU_SIM_SWIV, SWIV - move.w #MCU_SIM_PICR, PICR - move.w #MCU_SIM_PITR, PITR - move.w #MCU_SIM_SYPCR, SYPCR - - /* Clear DPRAM - system + parameter */ - movea.l #_dprbase, %a0 - movea.l #_dprbase+0x2000, %a1 - - /* Copy 0 to %a0 until %a0 == %a1 */ -clear_dpram: - movel #0, %a0@+ - cmpal %a0, %a1 - bhi clear_dpram - -configure_memory_controller: - /* Set up Global Memory Register (GMR) */ - move.l #MCU_SIM_GMR, %d0 - move.l %d0, GMR - -configure_chip_select_0: - move.l #RAMEND, %d0 - subi.l #__ramstart, %d0 - subq.l #0x01, %d0 - eori.l #SIM_OR_MASK, %d0 - ori.l #SIM_OR0_MASK, %d0 - move.l %d0, OR0 - - move.l #__ramstart, %d0 - ori.l #SIM_BR0_MASK, %d0 - move.l %d0, BR0 - -configure_chip_select_1: - move.l #ROMEND, %d0 - subi.l #__rom_start, %d0 - subq.l #0x01, %d0 - eori.l #SIM_OR_MASK, %d0 - ori.l #SIM_OR1_MASK, %d0 - move.l %d0, OR1 - - move.l #__rom_start, %d0 - ori.l #SIM_BR1_MASK, %d0 - move.l %d0, BR1 - - move.w #MCU_SIM_PEPAR, PEPAR - - /* point to vector table: */ - move.l #_romvec, %a0 - move.l #_ramvec, %a1 -copy_vectors: - move.l %a0@, %d0 - move.l %d0, %a1@ - move.l %a0@, %a1@ - addq.l #0x04, %a0 - addq.l #0x04, %a1 - cmp.l #_start, %a0 - blt copy_vectors - - move.l #_ramvec, %a1 - movec %a1, %vbr - - - /* Copy data segment from ROM to RAM */ - moveal #_stext, %a0 - moveal #_sdata, %a1 - moveal #_edata, %a2 - - /* Copy %a0 to %a1 until %a1 == %a2 */ -LD1: - move.l %a0@, %d0 - addq.l #0x04, %a0 - move.l %d0, %a1@ - addq.l #0x04, %a1 - cmp.l #_edata, %a1 - blt LD1 - - moveal #_sbss, %a0 - moveal #_ebss, %a1 - - /* Copy 0 to %a0 until %a0 == %a1 */ -L1: - movel #0, %a0@+ - cmpal %a0, %a1 - bhi L1 - -load_quicc: - move.l #_dprbase, _quicc_base - -store_ram_size: - /* Set ram size information */ - move.l #_sdata, _rambase - move.l #_ebss, _ramstart - move.l #RAMEND, %d0 - sub.l #0x1000, %d0 /* Reserve 4K for stack space.*/ - move.l %d0, _ramend /* Different from RAMEND.*/ - - pea 0 - pea env - pea %sp@(4) - pea 0 - - lea init_thread_union, %a2 - lea 0x2000(%a2), %sp - -lp: - jsr start_kernel - -_exit: - jmp _exit - - - .data - .align 4 -env: - .long 0 -_quicc_base: - .long 0 -_periph_base: - .long 0 -_ramvec: - .long 0 -_rambase: - .long 0 -_ramstart: - .long 0 -_ramend: - .long 0 -_dprbase: - .long 0xffffe000 - - .text - - /* - * These are the exception vectors at boot up, they are copied into RAM - * and then overwritten as needed. - */ - -.section ".data..initvect","awx" - .long RAMEND /* Reset: Initial Stack Pointer - 0. */ - .long _start /* Reset: Initial Program Counter - 1. */ - .long buserr /* Bus Error - 2. */ - .long trap /* Address Error - 3. */ - .long trap /* Illegal Instruction - 4. */ - .long trap /* Divide by zero - 5. */ - .long trap /* CHK, CHK2 Instructions - 6. */ - .long trap /* TRAPcc, TRAPV Instructions - 7. */ - .long trap /* Privilege Violation - 8. */ - .long trap /* Trace - 9. */ - .long trap /* Line 1010 Emulator - 10. */ - .long trap /* Line 1111 Emualtor - 11. */ - .long trap /* Harware Breakpoint - 12. */ - .long trap /* (Reserved for Coprocessor Protocol Violation)- 13. */ - .long trap /* Format Error - 14. */ - .long trap /* Uninitialized Interrupt - 15. */ - .long trap /* (Unassigned, Reserver) - 16. */ - .long trap /* (Unassigned, Reserver) - 17. */ - .long trap /* (Unassigned, Reserver) - 18. */ - .long trap /* (Unassigned, Reserver) - 19. */ - .long trap /* (Unassigned, Reserver) - 20. */ - .long trap /* (Unassigned, Reserver) - 21. */ - .long trap /* (Unassigned, Reserver) - 22. */ - .long trap /* (Unassigned, Reserver) - 23. */ - .long trap /* Spurious Interrupt - 24. */ - .long trap /* Level 1 Interrupt Autovector - 25. */ - .long trap /* Level 2 Interrupt Autovector - 26. */ - .long trap /* Level 3 Interrupt Autovector - 27. */ - .long trap /* Level 4 Interrupt Autovector - 28. */ - .long trap /* Level 5 Interrupt Autovector - 29. */ - .long trap /* Level 6 Interrupt Autovector - 30. */ - .long trap /* Level 7 Interrupt Autovector - 31. */ - .long system_call /* Trap Instruction Vectors 0 - 32. */ - .long trap /* Trap Instruction Vectors 1 - 33. */ - .long trap /* Trap Instruction Vectors 2 - 34. */ - .long trap /* Trap Instruction Vectors 3 - 35. */ - .long trap /* Trap Instruction Vectors 4 - 36. */ - .long trap /* Trap Instruction Vectors 5 - 37. */ - .long trap /* Trap Instruction Vectors 6 - 38. */ - .long trap /* Trap Instruction Vectors 7 - 39. */ - .long trap /* Trap Instruction Vectors 8 - 40. */ - .long trap /* Trap Instruction Vectors 9 - 41. */ - .long trap /* Trap Instruction Vectors 10 - 42. */ - .long trap /* Trap Instruction Vectors 11 - 43. */ - .long trap /* Trap Instruction Vectors 12 - 44. */ - .long trap /* Trap Instruction Vectors 13 - 45. */ - .long trap /* Trap Instruction Vectors 14 - 46. */ - .long trap /* Trap Instruction Vectors 15 - 47. */ - .long 0 /* (Reserved for Coprocessor) - 48. */ - .long 0 /* (Reserved for Coprocessor) - 49. */ - .long 0 /* (Reserved for Coprocessor) - 50. */ - .long 0 /* (Reserved for Coprocessor) - 51. */ - .long 0 /* (Reserved for Coprocessor) - 52. */ - .long 0 /* (Reserved for Coprocessor) - 53. */ - .long 0 /* (Reserved for Coprocessor) - 54. */ - .long 0 /* (Reserved for Coprocessor) - 55. */ - .long 0 /* (Reserved for Coprocessor) - 56. */ - .long 0 /* (Reserved for Coprocessor) - 57. */ - .long 0 /* (Reserved for Coprocessor) - 58. */ - .long 0 /* (Unassigned, Reserved) - 59. */ - .long 0 /* (Unassigned, Reserved) - 60. */ - .long 0 /* (Unassigned, Reserved) - 61. */ - .long 0 /* (Unassigned, Reserved) - 62. */ - .long 0 /* (Unassigned, Reserved) - 63. */ - /* The assignment of these vectors to the CPM is */ - /* dependent on the configuration of the CPM vba */ - /* fields. */ - .long 0 /* (User-Defined Vectors 1) CPM Error - 64. */ - .long 0 /* (User-Defined Vectors 2) CPM Parallel IO PC11- 65. */ - .long 0 /* (User-Defined Vectors 3) CPM Parallel IO PC10- 66. */ - .long 0 /* (User-Defined Vectors 4) CPM SMC2 / PIP - 67. */ - .long 0 /* (User-Defined Vectors 5) CPM SMC1 - 68. */ - .long 0 /* (User-Defined Vectors 6) CPM SPI - 69. */ - .long 0 /* (User-Defined Vectors 7) CPM Parallel IO PC9 - 70. */ - .long 0 /* (User-Defined Vectors 8) CPM Timer 4 - 71. */ - .long 0 /* (User-Defined Vectors 9) CPM Reserved - 72. */ - .long 0 /* (User-Defined Vectors 10) CPM Parallel IO PC8- 73. */ - .long 0 /* (User-Defined Vectors 11) CPM Parallel IO PC7- 74. */ - .long 0 /* (User-Defined Vectors 12) CPM Parallel IO PC6- 75. */ - .long 0 /* (User-Defined Vectors 13) CPM Timer 3 - 76. */ - .long 0 /* (User-Defined Vectors 14) CPM Reserved - 77. */ - .long 0 /* (User-Defined Vectors 15) CPM Parallel IO PC5- 78. */ - .long 0 /* (User-Defined Vectors 16) CPM Parallel IO PC4- 79. */ - .long 0 /* (User-Defined Vectors 17) CPM Reserved - 80. */ - .long 0 /* (User-Defined Vectors 18) CPM RISC Timer Tbl - 81. */ - .long 0 /* (User-Defined Vectors 19) CPM Timer 2 - 82. */ - .long 0 /* (User-Defined Vectors 21) CPM Reserved - 83. */ - .long 0 /* (User-Defined Vectors 22) CPM IDMA2 - 84. */ - .long 0 /* (User-Defined Vectors 23) CPM IDMA1 - 85. */ - .long 0 /* (User-Defined Vectors 24) CPM SDMA Bus Err - 86. */ - .long 0 /* (User-Defined Vectors 25) CPM Parallel IO PC3- 87. */ - .long 0 /* (User-Defined Vectors 26) CPM Parallel IO PC2- 88. */ - .long 0 /* (User-Defined Vectors 27) CPM Timer 1 - 89. */ - .long 0 /* (User-Defined Vectors 28) CPM Parallel IO PC1- 90. */ - .long 0 /* (User-Defined Vectors 29) CPM SCC 4 - 91. */ - .long 0 /* (User-Defined Vectors 30) CPM SCC 3 - 92. */ - .long 0 /* (User-Defined Vectors 31) CPM SCC 2 - 93. */ - .long 0 /* (User-Defined Vectors 32) CPM SCC 1 - 94. */ - .long 0 /* (User-Defined Vectors 33) CPM Parallel IO PC0- 95. */ - /* I don't think anything uses the vectors after here. */ - .long 0 /* (User-Defined Vectors 34) - 96. */ - .long 0,0,0,0,0 /* (User-Defined Vectors 35 - 39). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 40 - 49). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 50 - 59). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 60 - 69). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 70 - 79). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 80 - 89). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 90 - 99). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 100 - 109). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 110 - 119). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 120 - 129). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 130 - 139). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 140 - 149). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 150 - 159). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 160 - 169). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 170 - 179). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 180 - 189). */ - .long 0,0,0 /* (User-Defined Vectors 190 - 192). */ -.text -ignore: rte diff --git a/arch/m68knommu/platform/68360/head-rom.S b/arch/m68knommu/platform/68360/head-rom.S deleted file mode 100644 index 97510e5..0000000 --- a/arch/m68knommu/platform/68360/head-rom.S +++ /dev/null @@ -1,414 +0,0 @@ -/* arch/m68knommu/platform/68360/head-rom.S - * - * Startup code for Motorola 68360 - * - * Copyright (C) SED Systems, a Division of Calian Ltd. - * Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S - * Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7 - * uClinux Kernel - * Copyright (C) Michael Leslie <mleslie@lineo.com> - * Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S - * Copyright (C) 1998 D. Jeff Dionne <jeff@uclinux.org>, - * - */ - -.global _stext -.global _sbss -.global _start - -.global _rambase -.global _ramvec -.global _ramstart -.global _ramend - -.global _quicc_base -.global _periph_base - -#define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE) - -#define REGB 0x1000 -#define PEPAR (_dprbase + REGB + 0x0016) -#define GMR (_dprbase + REGB + 0x0040) -#define OR0 (_dprbase + REGB + 0x0054) -#define BR0 (_dprbase + REGB + 0x0050) - -#define OR1 (_dprbase + REGB + 0x0064) -#define BR1 (_dprbase + REGB + 0x0060) - -#define OR2 (_dprbase + REGB + 0x0074) -#define BR2 (_dprbase + REGB + 0x0070) - -#define OR3 (_dprbase + REGB + 0x0084) -#define BR3 (_dprbase + REGB + 0x0080) - -#define OR4 (_dprbase + REGB + 0x0094) -#define BR4 (_dprbase + REGB + 0x0090) - -#define OR5 (_dprbase + REGB + 0x00A4) -#define BR5 (_dprbase + REGB + 0x00A0) - -#define OR6 (_dprbase + REGB + 0x00b4) -#define BR6 (_dprbase + REGB + 0x00b0) - -#define OR7 (_dprbase + REGB + 0x00c4) -#define BR7 (_dprbase + REGB + 0x00c0) - -#define MCR (_dprbase + REGB + 0x0000) -#define AVR (_dprbase + REGB + 0x0008) - -#define SYPCR (_dprbase + REGB + 0x0022) - -#define PLLCR (_dprbase + REGB + 0x0010) -#define CLKOCR (_dprbase + REGB + 0x000C) -#define CDVCR (_dprbase + REGB + 0x0014) - -#define BKAR (_dprbase + REGB + 0x0030) -#define BKCR (_dprbase + REGB + 0x0034) -#define SWIV (_dprbase + REGB + 0x0023) -#define PICR (_dprbase + REGB + 0x0026) -#define PITR (_dprbase + REGB + 0x002A) - -/* Define for all memory configuration */ -#define MCU_SIM_GMR 0x00000000 -#define SIM_OR_MASK 0x0fffffff - -/* Defines for chip select zero - the flash */ -#define SIM_OR0_MASK 0x20000000 -#define SIM_BR0_MASK 0x00000001 - -/* Defines for chip select one - the RAM */ -#define SIM_OR1_MASK 0x10000000 -#define SIM_BR1_MASK 0x00000001 - -#define MCU_SIM_MBAR_ADRS 0x0003ff00 -#define MCU_SIM_MBAR_BA_MASK 0xfffff000 -#define MCU_SIM_MBAR_AS_MASK 0x00000001 - -#define MCU_SIM_PEPAR 0x00B4 - -#define MCU_DISABLE_INTRPTS 0x2700 -#define MCU_SIM_AVR 0x00 - -#define MCU_SIM_MCR 0x00005cff - -#define MCU_SIM_CLKOCR 0x00 -#define MCU_SIM_PLLCR 0x8000 -#define MCU_SIM_CDVCR 0x0000 - -#define MCU_SIM_SYPCR 0x0000 -#define MCU_SIM_SWIV 0x00 -#define MCU_SIM_PICR 0x0000 -#define MCU_SIM_PITR 0x0000 - - -#include <asm/m68360_regs.h> - - -/* - * By the time this RAM specific code begins to execute, DPRAM - * and DRAM should already be mapped and accessible. - */ - - .text -_start: -_stext: - nop - ori.w #MCU_DISABLE_INTRPTS, %sr /* disable interrupts: */ - /* We should not need to setup the boot stack the reset should do it. */ - movea.l #RAMEND, %sp /* set up stack at the end of DRAM:*/ - - -set_mbar_register: - moveq.l #0x07, %d1 /* Setup MBAR */ - movec %d1, %dfc - - lea.l MCU_SIM_MBAR_ADRS, %a0 - move.l #_dprbase, %d0 - andi.l #MCU_SIM_MBAR_BA_MASK, %d0 - ori.l #MCU_SIM_MBAR_AS_MASK, %d0 - moves.l %d0, %a0@ - - moveq.l #0x05, %d1 - movec.l %d1, %dfc - - /* Now we can begin to access registers in DPRAM */ - -set_sim_mcr: - /* Set Module Configuration Register */ - move.l #MCU_SIM_MCR, MCR - - /* to do: Determine cause of reset */ - - /* - * configure system clock MC68360 p. 6-40 - * (value +1)*osc/128 = system clock - * or - * (value + 1)*osc = system clock - * You do not need to divide the oscillator by 128 unless you want to. - */ -set_sim_clock: - move.w #MCU_SIM_PLLCR, PLLCR - move.b #MCU_SIM_CLKOCR, CLKOCR - move.w #MCU_SIM_CDVCR, CDVCR - - /* Wait for the PLL to settle */ - move.w #16384, %d0 -pll_settle_wait: - subi.w #1, %d0 - bne pll_settle_wait - - /* Setup the system protection register, and watchdog timer register */ - move.b #MCU_SIM_SWIV, SWIV - move.w #MCU_SIM_PICR, PICR - move.w #MCU_SIM_PITR, PITR - move.w #MCU_SIM_SYPCR, SYPCR - - /* Clear DPRAM - system + parameter */ - movea.l #_dprbase, %a0 - movea.l #_dprbase+0x2000, %a1 - - /* Copy 0 to %a0 until %a0 == %a1 */ -clear_dpram: - movel #0, %a0@+ - cmpal %a0, %a1 - bhi clear_dpram - -configure_memory_controller: - /* Set up Global Memory Register (GMR) */ - move.l #MCU_SIM_GMR, %d0 - move.l %d0, GMR - -configure_chip_select_0: - move.l #0x00400000, %d0 - subq.l #0x01, %d0 - eori.l #SIM_OR_MASK, %d0 - ori.l #SIM_OR0_MASK, %d0 - move.l %d0, OR0 - - move.l #__rom_start, %d0 - ori.l #SIM_BR0_MASK, %d0 - move.l %d0, BR0 - - move.l #0x0, BR1 - move.l #0x0, BR2 - move.l #0x0, BR3 - move.l #0x0, BR4 - move.l #0x0, BR5 - move.l #0x0, BR6 - move.l #0x0, BR7 - - move.w #MCU_SIM_PEPAR, PEPAR - - /* point to vector table: */ - move.l #_romvec, %a0 - move.l #_ramvec, %a1 -copy_vectors: - move.l %a0@, %d0 - move.l %d0, %a1@ - move.l %a0@, %a1@ - addq.l #0x04, %a0 - addq.l #0x04, %a1 - cmp.l #_start, %a0 - blt copy_vectors - - move.l #_ramvec, %a1 - movec %a1, %vbr - - - /* Copy data segment from ROM to RAM */ - moveal #_etext, %a0 - moveal #_sdata, %a1 - moveal #_edata, %a2 - - /* Copy %a0 to %a1 until %a1 == %a2 */ -LD1: - move.l %a0@, %d0 - addq.l #0x04, %a0 - move.l %d0, %a1@ - addq.l #0x04, %a1 - cmp.l #_edata, %a1 - blt LD1 - - moveal #_sbss, %a0 - moveal #_ebss, %a1 - - /* Copy 0 to %a0 until %a0 == %a1 */ -L1: - movel #0, %a0@+ - cmpal %a0, %a1 - bhi L1 - -load_quicc: - move.l #_dprbase, _quicc_base - -store_ram_size: - /* Set ram size information */ - move.l #_sdata, _rambase - move.l #_ebss, _ramstart - move.l #RAMEND, %d0 - sub.l #0x1000, %d0 /* Reserve 4K for stack space.*/ - move.l %d0, _ramend /* Different from RAMEND.*/ - - pea 0 - pea env - pea %sp@(4) - pea 0 - - lea init_thread_union, %a2 - lea 0x2000(%a2), %sp - -lp: - jsr start_kernel - -_exit: - jmp _exit - - - .data - .align 4 -env: - .long 0 -_quicc_base: - .long 0 -_periph_base: - .long 0 -_ramvec: - .long 0 -_rambase: - .long 0 -_ramstart: - .long 0 -_ramend: - .long 0 -_dprbase: - .long 0xffffe000 - - - .text - - /* - * These are the exception vectors at boot up, they are copied into RAM - * and then overwritten as needed. - */ - -.section ".data..initvect","awx" - .long RAMEND /* Reset: Initial Stack Pointer - 0. */ - .long _start /* Reset: Initial Program Counter - 1. */ - .long buserr /* Bus Error - 2. */ - .long trap /* Address Error - 3. */ - .long trap /* Illegal Instruction - 4. */ - .long trap /* Divide by zero - 5. */ - .long trap /* CHK, CHK2 Instructions - 6. */ - .long trap /* TRAPcc, TRAPV Instructions - 7. */ - .long trap /* Privilege Violation - 8. */ - .long trap /* Trace - 9. */ - .long trap /* Line 1010 Emulator - 10. */ - .long trap /* Line 1111 Emualtor - 11. */ - .long trap /* Harware Breakpoint - 12. */ - .long trap /* (Reserved for Coprocessor Protocol Violation)- 13. */ - .long trap /* Format Error - 14. */ - .long trap /* Uninitialized Interrupt - 15. */ - .long trap /* (Unassigned, Reserver) - 16. */ - .long trap /* (Unassigned, Reserver) - 17. */ - .long trap /* (Unassigned, Reserver) - 18. */ - .long trap /* (Unassigned, Reserver) - 19. */ - .long trap /* (Unassigned, Reserver) - 20. */ - .long trap /* (Unassigned, Reserver) - 21. */ - .long trap /* (Unassigned, Reserver) - 22. */ - .long trap /* (Unassigned, Reserver) - 23. */ - .long trap /* Spurious Interrupt - 24. */ - .long trap /* Level 1 Interrupt Autovector - 25. */ - .long trap /* Level 2 Interrupt Autovector - 26. */ - .long trap /* Level 3 Interrupt Autovector - 27. */ - .long trap /* Level 4 Interrupt Autovector - 28. */ - .long trap /* Level 5 Interrupt Autovector - 29. */ - .long trap /* Level 6 Interrupt Autovector - 30. */ - .long trap /* Level 7 Interrupt Autovector - 31. */ - .long system_call /* Trap Instruction Vectors 0 - 32. */ - .long trap /* Trap Instruction Vectors 1 - 33. */ - .long trap /* Trap Instruction Vectors 2 - 34. */ - .long trap /* Trap Instruction Vectors 3 - 35. */ - .long trap /* Trap Instruction Vectors 4 - 36. */ - .long trap /* Trap Instruction Vectors 5 - 37. */ - .long trap /* Trap Instruction Vectors 6 - 38. */ - .long trap /* Trap Instruction Vectors 7 - 39. */ - .long trap /* Trap Instruction Vectors 8 - 40. */ - .long trap /* Trap Instruction Vectors 9 - 41. */ - .long trap /* Trap Instruction Vectors 10 - 42. */ - .long trap /* Trap Instruction Vectors 11 - 43. */ - .long trap /* Trap Instruction Vectors 12 - 44. */ - .long trap /* Trap Instruction Vectors 13 - 45. */ - .long trap /* Trap Instruction Vectors 14 - 46. */ - .long trap /* Trap Instruction Vectors 15 - 47. */ - .long 0 /* (Reserved for Coprocessor) - 48. */ - .long 0 /* (Reserved for Coprocessor) - 49. */ - .long 0 /* (Reserved for Coprocessor) - 50. */ - .long 0 /* (Reserved for Coprocessor) - 51. */ - .long 0 /* (Reserved for Coprocessor) - 52. */ - .long 0 /* (Reserved for Coprocessor) - 53. */ - .long 0 /* (Reserved for Coprocessor) - 54. */ - .long 0 /* (Reserved for Coprocessor) - 55. */ - .long 0 /* (Reserved for Coprocessor) - 56. */ - .long 0 /* (Reserved for Coprocessor) - 57. */ - .long 0 /* (Reserved for Coprocessor) - 58. */ - .long 0 /* (Unassigned, Reserved) - 59. */ - .long 0 /* (Unassigned, Reserved) - 60. */ - .long 0 /* (Unassigned, Reserved) - 61. */ - .long 0 /* (Unassigned, Reserved) - 62. */ - .long 0 /* (Unassigned, Reserved) - 63. */ - /* The assignment of these vectors to the CPM is */ - /* dependent on the configuration of the CPM vba */ - /* fields. */ - .long 0 /* (User-Defined Vectors 1) CPM Error - 64. */ - .long 0 /* (User-Defined Vectors 2) CPM Parallel IO PC11- 65. */ - .long 0 /* (User-Defined Vectors 3) CPM Parallel IO PC10- 66. */ - .long 0 /* (User-Defined Vectors 4) CPM SMC2 / PIP - 67. */ - .long 0 /* (User-Defined Vectors 5) CPM SMC1 - 68. */ - .long 0 /* (User-Defined Vectors 6) CPM SPI - 69. */ - .long 0 /* (User-Defined Vectors 7) CPM Parallel IO PC9 - 70. */ - .long 0 /* (User-Defined Vectors 8) CPM Timer 4 - 71. */ - .long 0 /* (User-Defined Vectors 9) CPM Reserved - 72. */ - .long 0 /* (User-Defined Vectors 10) CPM Parallel IO PC8- 73. */ - .long 0 /* (User-Defined Vectors 11) CPM Parallel IO PC7- 74. */ - .long 0 /* (User-Defined Vectors 12) CPM Parallel IO PC6- 75. */ - .long 0 /* (User-Defined Vectors 13) CPM Timer 3 - 76. */ - .long 0 /* (User-Defined Vectors 14) CPM Reserved - 77. */ - .long 0 /* (User-Defined Vectors 15) CPM Parallel IO PC5- 78. */ - .long 0 /* (User-Defined Vectors 16) CPM Parallel IO PC4- 79. */ - .long 0 /* (User-Defined Vectors 17) CPM Reserved - 80. */ - .long 0 /* (User-Defined Vectors 18) CPM RISC Timer Tbl - 81. */ - .long 0 /* (User-Defined Vectors 19) CPM Timer 2 - 82. */ - .long 0 /* (User-Defined Vectors 21) CPM Reserved - 83. */ - .long 0 /* (User-Defined Vectors 22) CPM IDMA2 - 84. */ - .long 0 /* (User-Defined Vectors 23) CPM IDMA1 - 85. */ - .long 0 /* (User-Defined Vectors 24) CPM SDMA Bus Err - 86. */ - .long 0 /* (User-Defined Vectors 25) CPM Parallel IO PC3- 87. */ - .long 0 /* (User-Defined Vectors 26) CPM Parallel IO PC2- 88. */ - .long 0 /* (User-Defined Vectors 27) CPM Timer 1 - 89. */ - .long 0 /* (User-Defined Vectors 28) CPM Parallel IO PC1- 90. */ - .long 0 /* (User-Defined Vectors 29) CPM SCC 4 - 91. */ - .long 0 /* (User-Defined Vectors 30) CPM SCC 3 - 92. */ - .long 0 /* (User-Defined Vectors 31) CPM SCC 2 - 93. */ - .long 0 /* (User-Defined Vectors 32) CPM SCC 1 - 94. */ - .long 0 /* (User-Defined Vectors 33) CPM Parallel IO PC0- 95. */ - /* I don't think anything uses the vectors after here. */ - .long 0 /* (User-Defined Vectors 34) - 96. */ - .long 0,0,0,0,0 /* (User-Defined Vectors 35 - 39). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 40 - 49). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 50 - 59). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 60 - 69). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 70 - 79). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 80 - 89). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 90 - 99). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 100 - 109). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 110 - 119). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 120 - 129). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 130 - 139). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 140 - 149). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 150 - 159). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 160 - 169). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 170 - 179). */ - .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 180 - 189). */ - .long 0,0,0 /* (User-Defined Vectors 190 - 192). */ -.text -ignore: rte diff --git a/arch/m68knommu/platform/68360/ints.c b/arch/m68knommu/platform/68360/ints.c deleted file mode 100644 index 8de3feb..0000000 --- a/arch/m68knommu/platform/68360/ints.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * linux/arch/$(ARCH)/platform/$(PLATFORM)/ints.c - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> - * Copyright (c) 1996 Roman Zippel - * Copyright (c) 1999 D. Jeff Dionne <jeff@uclinux.org> - */ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <asm/traps.h> -#include <asm/machdep.h> -#include <asm/m68360.h> - -/* from quicc/commproc.c: */ -extern QUICC *pquicc; -extern void cpm_interrupt_init(void); - -#define INTERNAL_IRQS (96) - -/* assembler routines */ -asmlinkage void system_call(void); -asmlinkage void buserr(void); -asmlinkage void trap(void); -asmlinkage void bad_interrupt(void); -asmlinkage void inthandler(void); - -extern void *_ramvec[]; - -/* The number of spurious interrupts */ -volatile unsigned int num_spurious; - -static void intc_irq_unmask(struct irq_data *d) -{ - pquicc->intr_cimr |= (1 << d->irq); -} - -static void intc_irq_mask(struct irq_data *d) -{ - pquicc->intr_cimr &= ~(1 << d->irq); -} - -static void intc_irq_ack(struct irq_data *d) -{ - pquicc->intr_cisr = (1 << d->irq); -} - -static struct irq_chip intc_irq_chip = { - .name = "M68K-INTC", - .irq_mask = intc_irq_mask, - .irq_unmask = intc_irq_unmask, - .irq_ack = intc_irq_ack, -}; - -/* - * This function should be called during kernel startup to initialize - * the vector table. - */ -void init_IRQ(void) -{ - int i; - int vba = (CPM_VECTOR_BASE<<4); - - /* set up the vectors */ - _ramvec[2] = buserr; - _ramvec[3] = trap; - _ramvec[4] = trap; - _ramvec[5] = trap; - _ramvec[6] = trap; - _ramvec[7] = trap; - _ramvec[8] = trap; - _ramvec[9] = trap; - _ramvec[10] = trap; - _ramvec[11] = trap; - _ramvec[12] = trap; - _ramvec[13] = trap; - _ramvec[14] = trap; - _ramvec[15] = trap; - - _ramvec[32] = system_call; - _ramvec[33] = trap; - - cpm_interrupt_init(); - - /* set up CICR for vector base address and irq level */ - /* irl = 4, hp = 1f - see MC68360UM p 7-377 */ - pquicc->intr_cicr = 0x00e49f00 | vba; - - /* CPM interrupt vectors: (p 7-376) */ - _ramvec[vba+CPMVEC_ERROR] = bad_interrupt; /* Error */ - _ramvec[vba+CPMVEC_PIO_PC11] = inthandler; /* pio - pc11 */ - _ramvec[vba+CPMVEC_PIO_PC10] = inthandler; /* pio - pc10 */ - _ramvec[vba+CPMVEC_SMC2] = inthandler; /* smc2/pip */ - _ramvec[vba+CPMVEC_SMC1] = inthandler; /* smc1 */ - _ramvec[vba+CPMVEC_SPI] = inthandler; /* spi */ - _ramvec[vba+CPMVEC_PIO_PC9] = inthandler; /* pio - pc9 */ - _ramvec[vba+CPMVEC_TIMER4] = inthandler; /* timer 4 */ - _ramvec[vba+CPMVEC_RESERVED1] = inthandler; /* reserved */ - _ramvec[vba+CPMVEC_PIO_PC8] = inthandler; /* pio - pc8 */ - _ramvec[vba+CPMVEC_PIO_PC7] = inthandler; /* pio - pc7 */ - _ramvec[vba+CPMVEC_PIO_PC6] = inthandler; /* pio - pc6 */ - _ramvec[vba+CPMVEC_TIMER3] = inthandler; /* timer 3 */ - _ramvec[vba+CPMVEC_PIO_PC5] = inthandler; /* pio - pc5 */ - _ramvec[vba+CPMVEC_PIO_PC4] = inthandler; /* pio - pc4 */ - _ramvec[vba+CPMVEC_RESERVED2] = inthandler; /* reserved */ - _ramvec[vba+CPMVEC_RISCTIMER] = inthandler; /* timer table */ - _ramvec[vba+CPMVEC_TIMER2] = inthandler; /* timer 2 */ - _ramvec[vba+CPMVEC_RESERVED3] = inthandler; /* reserved */ - _ramvec[vba+CPMVEC_IDMA2] = inthandler; /* idma 2 */ - _ramvec[vba+CPMVEC_IDMA1] = inthandler; /* idma 1 */ - _ramvec[vba+CPMVEC_SDMA_CB_ERR] = inthandler; /* sdma channel bus error */ - _ramvec[vba+CPMVEC_PIO_PC3] = inthandler; /* pio - pc3 */ - _ramvec[vba+CPMVEC_PIO_PC2] = inthandler; /* pio - pc2 */ - /* _ramvec[vba+CPMVEC_TIMER1] = cpm_isr_timer1; */ /* timer 1 */ - _ramvec[vba+CPMVEC_TIMER1] = inthandler; /* timer 1 */ - _ramvec[vba+CPMVEC_PIO_PC1] = inthandler; /* pio - pc1 */ - _ramvec[vba+CPMVEC_SCC4] = inthandler; /* scc 4 */ - _ramvec[vba+CPMVEC_SCC3] = inthandler; /* scc 3 */ - _ramvec[vba+CPMVEC_SCC2] = inthandler; /* scc 2 */ - _ramvec[vba+CPMVEC_SCC1] = inthandler; /* scc 1 */ - _ramvec[vba+CPMVEC_PIO_PC0] = inthandler; /* pio - pc0 */ - - - /* turn off all CPM interrupts */ - pquicc->intr_cimr = 0x00000000; - - for (i = 0; (i < NR_IRQS); i++) { - set_irq_chip(i, &intc_irq_chip); - set_irq_handler(i, handle_level_irq); - } -} - diff --git a/arch/m68knommu/platform/68EZ328/Makefile b/arch/m68knommu/platform/68EZ328/Makefile deleted file mode 100644 index ee97735..0000000 --- a/arch/m68knommu/platform/68EZ328/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Makefile for arch/m68knommu/platform/68EZ328. -# - -obj-y := config.o - -extra-y := bootlogo.rh - -$(obj)/bootlogo.rh: $(src)/bootlogo.h - perl $(src)/../68328/bootlogo.pl < $(src)/bootlogo.h \ - > $(obj)/bootlogo.rh diff --git a/arch/m68knommu/platform/68EZ328/bootlogo.h b/arch/m68knommu/platform/68EZ328/bootlogo.h deleted file mode 100644 index e842bda..0000000 --- a/arch/m68knommu/platform/68EZ328/bootlogo.h +++ /dev/null @@ -1,3204 +0,0 @@ -#define splash_width 640 -#define splash_height 480 -static unsigned char splash_bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - }; diff --git a/arch/m68knommu/platform/68EZ328/config.c b/arch/m68knommu/platform/68EZ328/config.c deleted file mode 100644 index 1be1a16..0000000 --- a/arch/m68knommu/platform/68EZ328/config.c +++ /dev/null @@ -1,76 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/68EZ328/config.c - * - * Copyright (C) 1993 Hamish Macdonald - * Copyright (C) 1999 D. Jeff Dionne - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -/***************************************************************************/ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <asm/system.h> -#include <asm/pgtable.h> -#include <asm/machdep.h> -#include <asm/MC68EZ328.h> -#ifdef CONFIG_UCSIMM -#include <asm/bootstd.h> -#endif - -/***************************************************************************/ - -void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec); - -/***************************************************************************/ - -void m68ez328_reset(void) -{ - local_irq_disable(); - asm volatile ( - "moveal #0x10c00000, %a0;\n" - "moveb #0, 0xFFFFF300;\n" - "moveal 0(%a0), %sp;\n" - "moveal 4(%a0), %a0;\n" - "jmp (%a0);\n" - ); -} - -/***************************************************************************/ - -unsigned char *cs8900a_hwaddr; -static int errno; - -#ifdef CONFIG_UCSIMM -_bsc0(char *, getserialnum) -_bsc1(unsigned char *, gethwaddr, int, a) -_bsc1(char *, getbenv, char *, a) -#endif - -void config_BSP(char *command, int len) -{ - unsigned char *p; - - printk(KERN_INFO "\n68EZ328 DragonBallEZ support (C) 1999 Rt-Control, Inc\n"); - -#ifdef CONFIG_UCSIMM - printk(KERN_INFO "uCsimm serial string [%s]\n",getserialnum()); - p = cs8900a_hwaddr = gethwaddr(0); - printk(KERN_INFO "uCsimm hwaddr %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", - p[0], p[1], p[2], p[3], p[4], p[5]); - - p = getbenv("APPEND"); - if (p) strcpy(p,command); - else command[0] = 0; -#endif - - mach_gettod = m68328_timer_gettod; - mach_reset = m68ez328_reset; -} - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/68VZ328/Makefile b/arch/m68knommu/platform/68VZ328/Makefile deleted file mode 100644 index 447ffa0..0000000 --- a/arch/m68knommu/platform/68VZ328/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# -# Makefile for arch/m68knommu/platform/68VZ328. -# - -obj-y := config.o -logo-$(UCDIMM) := bootlogo.rh -logo-$(DRAGEN2) := screen.h -extra-y := $(logo-y) - -$(obj)/bootlogo.rh: $(src)/../68EZ328/bootlogo.h - perl $(src)/bootlogo.pl < $(src)/../68328/bootlogo.h > $(obj)/bootlogo.rh - -$(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl - perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h - -clean-files := $(obj)/screen.h $(obj)/bootlogo.rh diff --git a/arch/m68knommu/platform/68VZ328/config.c b/arch/m68knommu/platform/68VZ328/config.c deleted file mode 100644 index eabaabe..0000000 --- a/arch/m68knommu/platform/68VZ328/config.c +++ /dev/null @@ -1,188 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/68VZ328/config.c - * - * Copyright (C) 1993 Hamish Macdonald - * Copyright (C) 1999 D. Jeff Dionne - * Copyright (C) 2001 Georges Menie, Ken Desmet - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -/***************************************************************************/ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/kd.h> -#include <linux/netdevice.h> -#include <linux/interrupt.h> -#include <linux/irq.h> - -#include <asm/system.h> -#include <asm/pgtable.h> -#include <asm/machdep.h> -#include <asm/MC68VZ328.h> -#include <asm/bootstd.h> - -#ifdef CONFIG_INIT_LCD -#include "bootlogo.h" -#endif - -/***************************************************************************/ - -void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec); - -/***************************************************************************/ -/* Init Drangon Engine hardware */ -/***************************************************************************/ -#if defined(CONFIG_DRAGEN2) - -static void m68vz328_reset(void) -{ - local_irq_disable(); - -#ifdef CONFIG_INIT_LCD - PBDATA |= 0x20; /* disable CCFL light */ - PKDATA |= 0x4; /* disable LCD controller */ - LCKCON = 0; -#endif - - __asm__ __volatile__( - "reset\n\t" - "moveal #0x04000000, %a0\n\t" - "moveal 0(%a0), %sp\n\t" - "moveal 4(%a0), %a0\n\t" - "jmp (%a0)" - ); -} - -static void init_hardware(char *command, int size) -{ -#ifdef CONFIG_DIRECT_IO_ACCESS - SCR = 0x10; /* allow user access to internal registers */ -#endif - - /* CSGB Init */ - CSGBB = 0x4000; - CSB = 0x1a1; - - /* CS8900 init */ - /* PK3: hardware sleep function pin, active low */ - PKSEL |= PK(3); /* select pin as I/O */ - PKDIR |= PK(3); /* select pin as output */ - PKDATA |= PK(3); /* set pin high */ - - /* PF5: hardware reset function pin, active high */ - PFSEL |= PF(5); /* select pin as I/O */ - PFDIR |= PF(5); /* select pin as output */ - PFDATA &= ~PF(5); /* set pin low */ - - /* cs8900 hardware reset */ - PFDATA |= PF(5); - { int i; for (i = 0; i < 32000; ++i); } - PFDATA &= ~PF(5); - - /* INT1 enable (cs8900 IRQ) */ - PDPOL &= ~PD(1); /* active high signal */ - PDIQEG &= ~PD(1); - PDIRQEN |= PD(1); /* IRQ enabled */ - -#ifdef CONFIG_INIT_LCD - /* initialize LCD controller */ - LSSA = (long) screen_bits; - LVPW = 0x14; - LXMAX = 0x140; - LYMAX = 0xef; - LRRA = 0; - LPXCD = 3; - LPICF = 0x08; - LPOLCF = 0; - LCKCON = 0x80; - PCPDEN = 0xff; - PCSEL = 0; - - /* Enable LCD controller */ - PKDIR |= 0x4; - PKSEL |= 0x4; - PKDATA &= ~0x4; - - /* Enable CCFL backlighting circuit */ - PBDIR |= 0x20; - PBSEL |= 0x20; - PBDATA &= ~0x20; - - /* contrast control register */ - PFDIR |= 0x1; - PFSEL &= ~0x1; - PWMR = 0x037F; -#endif -} - -/***************************************************************************/ -/* Init RT-Control uCdimm hardware */ -/***************************************************************************/ -#elif defined(CONFIG_UCDIMM) - -static void m68vz328_reset(void) -{ - local_irq_disable(); - asm volatile ( - "moveal #0x10c00000, %a0;\n\t" - "moveb #0, 0xFFFFF300;\n\t" - "moveal 0(%a0), %sp;\n\t" - "moveal 4(%a0), %a0;\n\t" - "jmp (%a0);\n" - ); -} - -unsigned char *cs8900a_hwaddr; -static int errno; - -_bsc0(char *, getserialnum) -_bsc1(unsigned char *, gethwaddr, int, a) -_bsc1(char *, getbenv, char *, a) - -static void init_hardware(char *command, int size) -{ - char *p; - - printk(KERN_INFO "uCdimm serial string [%s]\n", getserialnum()); - p = cs8900a_hwaddr = gethwaddr(0); - printk(KERN_INFO "uCdimm hwaddr %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", - p[0], p[1], p[2], p[3], p[4], p[5]); - p = getbenv("APPEND"); - if (p) - strcpy(p, command); - else - command[0] = 0; -} - -/***************************************************************************/ -#else - -static void m68vz328_reset(void) -{ -} - -static void init_hardware(char *command, int size) -{ -} - -/***************************************************************************/ -#endif -/***************************************************************************/ - -void config_BSP(char *command, int size) -{ - printk(KERN_INFO "68VZ328 DragonBallVZ support (c) 2001 Lineo, Inc.\n"); - - init_hardware(command, size); - - mach_gettod = m68328_timer_gettod; - mach_reset = m68vz328_reset; -} - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/Makefile b/arch/m68knommu/platform/Makefile deleted file mode 100644 index fc932bf..0000000 --- a/arch/m68knommu/platform/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# -# Makefile for the arch/m68knommu/platform. -# diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile deleted file mode 100644 index a8967ba..0000000 --- a/arch/m68knommu/platform/coldfire/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -# -# Makefile for the m68knommu kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-$(CONFIG_COLDFIRE) += cache.o clk.o dma.o entry.o vectors.o -obj-$(CONFIG_M5206) += timers.o intc.o -obj-$(CONFIG_M5206e) += timers.o intc.o -obj-$(CONFIG_M520x) += pit.o intc-simr.o -obj-$(CONFIG_M523x) += pit.o dma_timer.o intc-2.o -obj-$(CONFIG_M5249) += timers.o intc.o -obj-$(CONFIG_M527x) += pit.o intc-2.o -obj-$(CONFIG_M5272) += timers.o -obj-$(CONFIG_M528x) += pit.o intc-2.o -obj-$(CONFIG_M5307) += timers.o intc.o -obj-$(CONFIG_M532x) += timers.o intc-simr.o -obj-$(CONFIG_M5407) += timers.o intc.o -obj-$(CONFIG_M54xx) += sltimers.o intc-2.o - -obj-y += pinmux.o gpio.o -extra-y := head.o diff --git a/arch/m68knommu/platform/coldfire/cache.c b/arch/m68knommu/platform/coldfire/cache.c deleted file mode 100644 index 235d3c4..0000000 --- a/arch/m68knommu/platform/coldfire/cache.c +++ /dev/null @@ -1,48 +0,0 @@ -/***************************************************************************/ - -/* - * cache.c -- general ColdFire Cache maintainence code - * - * Copyright (C) 2010, Greg Ungerer (gerg@snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> - -/***************************************************************************/ -#ifdef CACHE_PUSH -/***************************************************************************/ - -/* - * Use cpushl to push all dirty cache lines back to memory. - * Older versions of GAS don't seem to know how to generate the - * ColdFire cpushl instruction... Oh well, bit stuff it for now. - */ - -void mcf_cache_push(void) -{ - __asm__ __volatile__ ( - "clrl %%d0\n\t" - "1:\n\t" - "movel %%d0,%%a0\n\t" - "2:\n\t" - ".word 0xf468\n\t" - "addl %0,%%a0\n\t" - "cmpl %1,%%a0\n\t" - "blt 2b\n\t" - "addql #1,%%d0\n\t" - "cmpil %2,%%d0\n\t" - "bne 1b\n\t" - : /* No output */ - : "i" (CACHE_LINE_SIZE), - "i" (DCACHE_SIZE / CACHE_WAYS), - "i" (CACHE_WAYS) - : "d0", "a0" ); -} - -/***************************************************************************/ -#endif /* CACHE_PUSH */ -/***************************************************************************/ diff --git a/arch/m68knommu/platform/coldfire/clk.c b/arch/m68knommu/platform/coldfire/clk.c deleted file mode 100644 index 9f1260c..0000000 --- a/arch/m68knommu/platform/coldfire/clk.c +++ /dev/null @@ -1,45 +0,0 @@ -/***************************************************************************/ - -/* - * clk.c -- general ColdFire CPU kernel clk handling - * - * Copyright (C) 2009, Greg Ungerer (gerg@snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/clk.h> -#include <asm/coldfire.h> - -/***************************************************************************/ - -struct clk *clk_get(struct device *dev, const char *id) -{ - return NULL; -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - -unsigned long clk_get_rate(struct clk *clk) -{ - return MCF_CLK; -} -EXPORT_SYMBOL(clk_get_rate); -/***************************************************************************/ diff --git a/arch/m68knommu/platform/coldfire/dma.c b/arch/m68knommu/platform/coldfire/dma.c deleted file mode 100644 index e88b95e..0000000 --- a/arch/m68knommu/platform/coldfire/dma.c +++ /dev/null @@ -1,39 +0,0 @@ -/***************************************************************************/ - -/* - * dma.c -- Freescale ColdFire DMA support - * - * Copyright (C) 2007, Greg Ungerer (gerg@snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <asm/dma.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfdma.h> - -/***************************************************************************/ - -/* - * DMA channel base address table. - */ -unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = { -#ifdef MCFDMA_BASE0 - MCFDMA_BASE0, -#endif -#ifdef MCFDMA_BASE1 - MCFDMA_BASE1, -#endif -#ifdef MCFDMA_BASE2 - MCFDMA_BASE2, -#endif -#ifdef MCFDMA_BASE3 - MCFDMA_BASE3, -#endif -}; - -unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS]; - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/coldfire/dma_timer.c b/arch/m68knommu/platform/coldfire/dma_timer.c deleted file mode 100644 index a5f5628..0000000 --- a/arch/m68knommu/platform/coldfire/dma_timer.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * dma_timer.c -- Freescale ColdFire DMA Timer. - * - * Copyright (C) 2007, Benedikt Spranger <b.spranger@linutronix.de> - * Copyright (C) 2008. Sebastian Siewior, Linutronix - * - */ - -#include <linux/clocksource.h> -#include <linux/io.h> - -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfpit.h> -#include <asm/mcfsim.h> - -#define DMA_TIMER_0 (0x00) -#define DMA_TIMER_1 (0x40) -#define DMA_TIMER_2 (0x80) -#define DMA_TIMER_3 (0xc0) - -#define DTMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x400) -#define DTXMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x402) -#define DTER0 (MCF_IPSBAR + DMA_TIMER_0 + 0x403) -#define DTRR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x404) -#define DTCR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x408) -#define DTCN0 (MCF_IPSBAR + DMA_TIMER_0 + 0x40c) - -#define DMA_FREQ ((MCF_CLK / 2) / 16) - -/* DTMR */ -#define DMA_DTMR_RESTART (1 << 3) -#define DMA_DTMR_CLK_DIV_1 (1 << 1) -#define DMA_DTMR_CLK_DIV_16 (2 << 1) -#define DMA_DTMR_ENABLE (1 << 0) - -static cycle_t cf_dt_get_cycles(struct clocksource *cs) -{ - return __raw_readl(DTCN0); -} - -static struct clocksource clocksource_cf_dt = { - .name = "coldfire_dma_timer", - .rating = 200, - .read = cf_dt_get_cycles, - .mask = CLOCKSOURCE_MASK(32), - .shift = 20, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static int __init init_cf_dt_clocksource(void) -{ - /* - * We setup DMA timer 0 in free run mode. This incrementing counter is - * used as a highly precious clock source. With MCF_CLOCK = 150 MHz we - * get a ~213 ns resolution and the 32bit register will overflow almost - * every 15 minutes. - */ - __raw_writeb(0x00, DTXMR0); - __raw_writeb(0x00, DTER0); - __raw_writel(0x00000000, DTRR0); - __raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0); - clocksource_cf_dt.mult = clocksource_hz2mult(DMA_FREQ, - clocksource_cf_dt.shift); - return clocksource_register(&clocksource_cf_dt); -} - -arch_initcall(init_cf_dt_clocksource); - -#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ -#define CYC2NS_SCALE ((1000000 << CYC2NS_SCALE_FACTOR) / (DMA_FREQ / 1000)) - -static unsigned long long cycles2ns(unsigned long cycl) -{ - return (unsigned long long) ((unsigned long long)cycl * - CYC2NS_SCALE) >> CYC2NS_SCALE_FACTOR; -} - -unsigned long long sched_clock(void) -{ - unsigned long cycl = __raw_readl(DTCN0); - - return cycles2ns(cycl); -} diff --git a/arch/m68knommu/platform/coldfire/entry.S b/arch/m68knommu/platform/coldfire/entry.S deleted file mode 100644 index 5837cf0..0000000 --- a/arch/m68knommu/platform/coldfire/entry.S +++ /dev/null @@ -1,203 +0,0 @@ -/* - * linux/arch/m68knommu/platform/5307/entry.S - * - * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com) - * Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>, - * Kenneth Albanowski <kjahds@kjahds.com>, - * Copyright (C) 2000 Lineo Inc. (www.lineo.com) - * Copyright (C) 2004-2006 Macq Electronique SA. (www.macqel.com) - * - * Based on: - * - * linux/arch/m68k/kernel/entry.S - * - * Copyright (C) 1991, 1992 Linus Torvalds - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file README.legal in the main directory of this archive - * for more details. - * - * Linux/m68k support by Hamish Macdonald - * - * 68060 fixes by Jesper Skov - * ColdFire support by Greg Ungerer (gerg@snapgear.com) - * 5307 fixes by David W. Miller - * linux 2.4 support David McCullough <davidm@snapgear.com> - * Bug, speed and maintainability fixes by Philippe De Muyter <phdm@macqel.be> - */ - -#include <linux/sys.h> -#include <linux/linkage.h> -#include <asm/unistd.h> -#include <asm/thread_info.h> -#include <asm/errno.h> -#include <asm/setup.h> -#include <asm/segment.h> -#include <asm/asm-offsets.h> -#include <asm/entry.h> - -#ifdef CONFIG_COLDFIRE_SW_A7 -/* - * Define software copies of the supervisor and user stack pointers. - */ -.bss -sw_ksp: -.long 0 -sw_usp: -.long 0 -#endif /* CONFIG_COLDFIRE_SW_A7 */ - -.text - -.globl system_call -.globl resume -.globl ret_from_exception -.globl ret_from_signal -.globl sys_call_table -.globl inthandler -.globl fasthandler - -enosys: - mov.l #sys_ni_syscall,%d3 - bra 1f - -ENTRY(system_call) - SAVE_ALL - move #0x2000,%sr /* enable intrs again */ - - cmpl #NR_syscalls,%d0 - jcc enosys - lea sys_call_table,%a0 - lsll #2,%d0 /* movel %a0@(%d0:l:4),%d3 */ - movel %a0@(%d0),%d3 - jeq enosys - -1: - movel %sp,%d2 /* get thread_info pointer */ - andl #-THREAD_SIZE,%d2 /* at start of kernel stack */ - movel %d2,%a0 - movel %a0@,%a1 /* save top of frame */ - movel %sp,%a1@(TASK_THREAD+THREAD_ESP0) - btst #(TIF_SYSCALL_TRACE%8),%a0@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8) - bnes 1f - - movel %d3,%a0 - jbsr %a0@ - movel %d0,%sp@(PT_OFF_D0) /* save the return value */ - jra ret_from_exception -1: - movel #-ENOSYS,%d2 /* strace needs -ENOSYS in PT_OFF_D0 */ - movel %d2,PT_OFF_D0(%sp) /* on syscall entry */ - subql #4,%sp - SAVE_SWITCH_STACK - jbsr syscall_trace_enter - RESTORE_SWITCH_STACK - addql #4,%sp - movel %d3,%a0 - jbsr %a0@ - movel %d0,%sp@(PT_OFF_D0) /* save the return value */ - subql #4,%sp /* dummy return address */ - SAVE_SWITCH_STACK - jbsr syscall_trace_leave - -ret_from_signal: - RESTORE_SWITCH_STACK - addql #4,%sp - -ret_from_exception: - move #0x2700,%sr /* disable intrs */ - btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel */ - jeq Luser_return /* if so, skip resched, signals */ - -#ifdef CONFIG_PREEMPT - movel %sp,%d1 /* get thread_info pointer */ - andl #-THREAD_SIZE,%d1 /* at base of kernel stack */ - movel %d1,%a0 - movel %a0@(TI_FLAGS),%d1 /* get thread_info->flags */ - andl #(1<<TIF_NEED_RESCHED),%d1 - jeq Lkernel_return - - movel %a0@(TI_PREEMPTCOUNT),%d1 - cmpl #0,%d1 - jne Lkernel_return - - pea Lkernel_return - jmp preempt_schedule_irq /* preempt the kernel */ -#endif - -Lkernel_return: - moveml %sp@,%d1-%d5/%a0-%a2 - lea %sp@(32),%sp /* space for 8 regs */ - movel %sp@+,%d0 - addql #4,%sp /* orig d0 */ - addl %sp@+,%sp /* stk adj */ - rte - -Luser_return: - movel %sp,%d1 /* get thread_info pointer */ - andl #-THREAD_SIZE,%d1 /* at base of kernel stack */ - movel %d1,%a0 - movel %a0@(TI_FLAGS),%d1 /* get thread_info->flags */ - jne Lwork_to_do /* still work to do */ - -Lreturn: - RESTORE_USER - -Lwork_to_do: - movel %a0@(TI_FLAGS),%d1 /* get thread_info->flags */ - move #0x2000,%sr /* enable intrs again */ - btst #TIF_NEED_RESCHED,%d1 - jne reschedule - - /* GERG: do we need something here for TRACEing?? */ - -Lsignal_return: - subql #4,%sp /* dummy return address */ - SAVE_SWITCH_STACK - pea %sp@(SWITCH_STACK_SIZE) - jsr do_signal - addql #4,%sp - RESTORE_SWITCH_STACK - addql #4,%sp - jmp Luser_return - -/* - * This is the generic interrupt handler (for all hardware interrupt - * sources). Calls upto high level code to do all the work. - */ -ENTRY(inthandler) - SAVE_ALL - moveq #-1,%d0 - movel %d0,%sp@(PT_OFF_ORIG_D0) - - movew %sp@(PT_OFF_FORMATVEC),%d0 /* put exception # in d0 */ - andl #0x03fc,%d0 /* mask out vector only */ - - movel %sp,%sp@- /* push regs arg */ - lsrl #2,%d0 /* calculate real vector # */ - movel %d0,%sp@- /* push vector number */ - jbsr do_IRQ /* call high level irq handler */ - lea %sp@(8),%sp /* pop args off stack */ - - bra ret_from_exception - -/* - * Beware - when entering resume, prev (the current task) is - * in a0, next (the new task) is in a1,so don't change these - * registers until their contents are no longer needed. - * This is always called in supervisor mode, so don't bother to save - * and restore sr; user's process sr is actually in the stack. - */ -ENTRY(resume) - movel %a0, %d1 /* get prev thread in d1 */ - RDUSP - movel %a2,%a0@(TASK_THREAD+THREAD_USP) - - SAVE_SWITCH_STACK - movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack pointer */ - movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new thread stack */ - RESTORE_SWITCH_STACK - - movel %a1@(TASK_THREAD+THREAD_USP),%a0 /* restore thread user stack */ - WRUSP - rts diff --git a/arch/m68knommu/platform/coldfire/gpio.c b/arch/m68knommu/platform/coldfire/gpio.c deleted file mode 100644 index ff004579..0000000 --- a/arch/m68knommu/platform/coldfire/gpio.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Coldfire generic GPIO support. - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/sysdev.h> - -#include <asm/gpio.h> -#include <asm/pinmux.h> -#include <asm/mcfgpio.h> - -#define MCF_CHIP(chip) container_of(chip, struct mcf_gpio_chip, gpio_chip) - -int mcf_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - unsigned long flags; - MCFGPIO_PORTTYPE dir; - struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); - - local_irq_save(flags); - dir = mcfgpio_read(mcf_chip->pddr); - dir &= ~mcfgpio_bit(chip->base + offset); - mcfgpio_write(dir, mcf_chip->pddr); - local_irq_restore(flags); - - return 0; -} - -int mcf_gpio_get_value(struct gpio_chip *chip, unsigned offset) -{ - struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); - - return mcfgpio_read(mcf_chip->ppdr) & mcfgpio_bit(chip->base + offset); -} - -int mcf_gpio_direction_output(struct gpio_chip *chip, unsigned offset, - int value) -{ - unsigned long flags; - MCFGPIO_PORTTYPE data; - struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); - - local_irq_save(flags); - /* write the value to the output latch */ - data = mcfgpio_read(mcf_chip->podr); - if (value) - data |= mcfgpio_bit(chip->base + offset); - else - data &= ~mcfgpio_bit(chip->base + offset); - mcfgpio_write(data, mcf_chip->podr); - - /* now set the direction to output */ - data = mcfgpio_read(mcf_chip->pddr); - data |= mcfgpio_bit(chip->base + offset); - mcfgpio_write(data, mcf_chip->pddr); - local_irq_restore(flags); - - return 0; -} - -void mcf_gpio_set_value(struct gpio_chip *chip, unsigned offset, int value) -{ - struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); - - unsigned long flags; - MCFGPIO_PORTTYPE data; - - local_irq_save(flags); - data = mcfgpio_read(mcf_chip->podr); - if (value) - data |= mcfgpio_bit(chip->base + offset); - else - data &= ~mcfgpio_bit(chip->base + offset); - mcfgpio_write(data, mcf_chip->podr); - local_irq_restore(flags); -} - -void mcf_gpio_set_value_fast(struct gpio_chip *chip, unsigned offset, int value) -{ - struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); - - if (value) - mcfgpio_write(mcfgpio_bit(chip->base + offset), mcf_chip->setr); - else - mcfgpio_write(~mcfgpio_bit(chip->base + offset), mcf_chip->clrr); -} - -int mcf_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); - - return mcf_chip->gpio_to_pinmux ? - mcf_pinmux_request(mcf_chip->gpio_to_pinmux[offset], 0) : 0; -} - -void mcf_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); - - mcf_gpio_direction_input(chip, offset); - - if (mcf_chip->gpio_to_pinmux) - mcf_pinmux_release(mcf_chip->gpio_to_pinmux[offset], 0); -} - -struct sysdev_class mcf_gpio_sysclass = { - .name = "gpio", -}; - -static int __init mcf_gpio_sysinit(void) -{ - return sysdev_class_register(&mcf_gpio_sysclass); -} - -core_initcall(mcf_gpio_sysinit); diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S deleted file mode 100644 index 129bff49..0000000 --- a/arch/m68knommu/platform/coldfire/head.S +++ /dev/null @@ -1,250 +0,0 @@ -/*****************************************************************************/ - -/* - * head.S -- common startup code for ColdFire CPUs. - * - * (C) Copyright 1999-2010, Greg Ungerer <gerg@snapgear.com>. - */ - -/*****************************************************************************/ - -#include <linux/sys.h> -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/asm-offsets.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/thread_info.h> - -/*****************************************************************************/ - -/* - * If we don't have a fixed memory size, then lets build in code - * to auto detect the DRAM size. Obviously this is the prefered - * method, and should work for most boards. It won't work for those - * that do not have their RAM starting at address 0, and it only - * works on SDRAM (not boards fitted with SRAM). - */ -#if CONFIG_RAMSIZE != 0 -.macro GET_MEM_SIZE - movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */ -.endm - -#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ - defined(CONFIG_M5249) || defined(CONFIG_M527x) || \ - defined(CONFIG_M528x) || defined(CONFIG_M5307) || \ - defined(CONFIG_M5407) -/* - * Not all these devices have exactly the same DRAM controller, - * but the DCMR register is virtually identical - give or take - * a couple of bits. The only exception is the 5272 devices, their - * DRAM controller is quite different. - */ -.macro GET_MEM_SIZE - movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */ - btst #0,%d0 /* check if region enabled */ - beq 1f - andl #0xfffc0000,%d0 - beq 1f - addl #0x00040000,%d0 /* convert mask to size */ -1: - movel MCFSIM_DMR1,%d1 /* get mask for 2nd bank */ - btst #0,%d1 /* check if region enabled */ - beq 2f - andl #0xfffc0000,%d1 - beq 2f - addl #0x00040000,%d1 - addl %d1,%d0 /* total mem size in d0 */ -2: -.endm - -#elif defined(CONFIG_M5272) -.macro GET_MEM_SIZE - movel MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */ - andil #0xfffff000,%d0 /* mask out chip select options */ - negl %d0 /* negate bits */ -.endm - -#elif defined(CONFIG_M520x) -.macro GET_MEM_SIZE - clrl %d0 - movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */ - andl #0x1f, %d2 /* Get only the chip select size */ - beq 3f /* Check if it is enabled */ - addql #1, %d2 /* Form exponent */ - moveql #1, %d0 - lsll %d2, %d0 /* 2 ^ exponent */ -3: - movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */ - andl #0x1f, %d2 /* Get only the chip select size */ - beq 4f /* Check if it is enabled */ - addql #1, %d2 /* Form exponent */ - moveql #1, %d1 - lsll %d2, %d1 /* 2 ^ exponent */ - addl %d1, %d0 /* Total size of SDRAM in d0 */ -4: -.endm - -#else -#error "ERROR: I don't know how to probe your boards memory size?" -#endif - -/*****************************************************************************/ - -/* - * Boards and platforms can do specific early hardware setup if - * they need to. Most don't need this, define away if not required. - */ -#ifndef PLATFORM_SETUP -#define PLATFORM_SETUP -#endif - -/*****************************************************************************/ - -.global _start -.global _rambase -.global _ramvec -.global _ramstart -.global _ramend -#if defined(CONFIG_UBOOT) -.global _init_sp -#endif - -/*****************************************************************************/ - -.data - -/* - * During startup we store away the RAM setup. These are not in the - * bss, since their values are determined and written before the bss - * has been cleared. - */ -_rambase: -.long 0 -_ramvec: -.long 0 -_ramstart: -.long 0 -_ramend: -.long 0 -#if defined(CONFIG_UBOOT) -_init_sp: -.long 0 -#endif - -/*****************************************************************************/ - -__HEAD - -/* - * This is the codes first entry point. This is where it all - * begins... - */ - -_start: - nop /* filler */ - movew #0x2700, %sr /* no interrupts */ -#if defined(CONFIG_UBOOT) - movel %sp,_init_sp /* save initial stack pointer */ -#endif - - /* - * Do any platform or board specific setup now. Most boards - * don't need anything. Those exceptions are define this in - * their board specific includes. - */ - PLATFORM_SETUP - - /* - * Create basic memory configuration. Set VBR accordingly, - * and size memory. - */ - movel #CONFIG_VECTORBASE,%a7 - movec %a7,%VBR /* set vectors addr */ - movel %a7,_ramvec - - movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */ - movel %a7,_rambase - - GET_MEM_SIZE /* macro code determines size */ - addl %a7,%d0 - movel %d0,_ramend /* set end ram addr */ - - /* - * Now that we know what the memory is, lets enable cache - * and get things moving. This is Coldfire CPU specific. Not - * all version cores have identical cache register setup. But - * it is very similar. Define the exact settings in the headers - * then the code here is the same for all. - */ - movel #CACHE_INIT,%d0 /* invalidate whole cache */ - movec %d0,%CACR - nop - movel #ACR0_MODE,%d0 /* set RAM region for caching */ - movec %d0,%ACR0 - movel #ACR1_MODE,%d0 /* anything else to cache? */ - movec %d0,%ACR1 -#ifdef ACR2_MODE - movel #ACR2_MODE,%d0 - movec %d0,%ACR2 - movel #ACR3_MODE,%d0 - movec %d0,%ACR3 -#endif - movel #CACHE_MODE,%d0 /* enable cache */ - movec %d0,%CACR - nop - -#ifdef CONFIG_ROMFS_FS - /* - * Move ROM filesystem above bss :-) - */ - lea _sbss,%a0 /* get start of bss */ - lea _ebss,%a1 /* set up destination */ - movel %a0,%a2 /* copy of bss start */ - - movel 8(%a0),%d0 /* get size of ROMFS */ - addql #8,%d0 /* allow for rounding */ - andl #0xfffffffc, %d0 /* whole words */ - - addl %d0,%a0 /* copy from end */ - addl %d0,%a1 /* copy from end */ - movel %a1,_ramstart /* set start of ram */ - -_copy_romfs: - movel -(%a0),%d0 /* copy dword */ - movel %d0,-(%a1) - cmpl %a0,%a2 /* check if at end */ - bne _copy_romfs - -#else /* CONFIG_ROMFS_FS */ - lea _ebss,%a1 - movel %a1,_ramstart -#endif /* CONFIG_ROMFS_FS */ - - - /* - * Zero out the bss region. - */ - lea _sbss,%a0 /* get start of bss */ - lea _ebss,%a1 /* get end of bss */ - clrl %d0 /* set value */ -_clear_bss: - movel %d0,(%a0)+ /* clear each word */ - cmpl %a0,%a1 /* check if at end */ - bne _clear_bss - - /* - * Load the current task pointer and stack. - */ - lea init_thread_union,%a0 - lea THREAD_SIZE(%a0),%sp - - /* - * Assember start up done, start code proper. - */ - jsr start_kernel /* start Linux kernel */ - -_exit: - jmp _exit /* should never get here */ - -/*****************************************************************************/ diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c deleted file mode 100644 index 2cbfbf0..0000000 --- a/arch/m68knommu/platform/coldfire/intc-2.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * intc-2.c - * - * General interrupt controller code for the many ColdFire cores that use - * interrupt controllers with 63 interrupt sources, organized as 56 fully- - * programmable + 7 fixed-level interrupt sources. This includes the 523x - * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such - * controllers, and the 547x and 548x families which have only one of them. - * - * The external 7 fixed interrupts are part the the Edge Port unit of these - * ColdFire parts. They can be configured as level or edge triggered. - * - * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/traps.h> - -/* - * Bit definitions for the ICR family of registers. - */ -#define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */ -#define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */ - -/* - * The EDGE Port interrupts are the fixed 7 external interrupts. - * They need some special treatment, for example they need to be acked. - */ -#define EINT0 64 /* Is not actually used, but spot reserved for it */ -#define EINT1 65 /* EDGE Port interrupt 1 */ -#define EINT7 71 /* EDGE Port interrupt 7 */ - -#ifdef MCFICM_INTC1 -#define NR_VECS 128 -#else -#define NR_VECS 64 -#endif - -static void intc_irq_mask(struct irq_data *d) -{ - unsigned int irq = d->irq - MCFINT_VECBASE; - unsigned long imraddr; - u32 val, imrbit; - -#ifdef MCFICM_INTC1 - imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; -#else - imraddr = MCFICM_INTC0; -#endif - imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; - imrbit = 0x1 << (irq & 0x1f); - - val = __raw_readl(imraddr); - __raw_writel(val | imrbit, imraddr); -} - -static void intc_irq_unmask(struct irq_data *d) -{ - unsigned int irq = d->irq - MCFINT_VECBASE; - unsigned long imraddr; - u32 val, imrbit; - -#ifdef MCFICM_INTC1 - imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; -#else - imraddr = MCFICM_INTC0; -#endif - imraddr += ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); - imrbit = 0x1 << (irq & 0x1f); - - /* Don't set the "maskall" bit! */ - if ((irq & 0x20) == 0) - imrbit |= 0x1; - - val = __raw_readl(imraddr); - __raw_writel(val & ~imrbit, imraddr); -} - -/* - * Only the external (or EDGE Port) interrupts need to be acknowledged - * here, as part of the IRQ handler. They only really need to be ack'ed - * if they are in edge triggered mode, but there is no harm in doing it - * for all types. - */ -static void intc_irq_ack(struct irq_data *d) -{ - unsigned int irq = d->irq; - - __raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR); -} - -/* - * Each vector needs a unique priority and level associated with it. - * We don't really care so much what they are, we don't rely on the - * traditional priority interrupt scheme of the m68k/ColdFire. This - * only needs to be set once for an interrupt, and we will never change - * these values once we have set them. - */ -static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6); - -static unsigned int intc_irq_startup(struct irq_data *d) -{ - unsigned int irq = d->irq - MCFINT_VECBASE; - unsigned long icraddr; - -#ifdef MCFICM_INTC1 - icraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; -#else - icraddr = MCFICM_INTC0; -#endif - icraddr += MCFINTC_ICR0 + (irq & 0x3f); - if (__raw_readb(icraddr) == 0) - __raw_writeb(intc_intpri--, icraddr); - - irq = d->irq; - if ((irq >= EINT1) && (irq <= EINT7)) { - u8 v; - - irq -= EINT0; - - /* Set EPORT line as input */ - v = __raw_readb(MCFEPORT_EPDDR); - __raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR); - - /* Set EPORT line as interrupt source */ - v = __raw_readb(MCFEPORT_EPIER); - __raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER); - } - - intc_irq_unmask(d); - return 0; -} - -static int intc_irq_set_type(struct irq_data *d, unsigned int type) -{ - unsigned int irq = d->irq; - u16 pa, tb; - - switch (type) { - case IRQ_TYPE_EDGE_RISING: - tb = 0x1; - break; - case IRQ_TYPE_EDGE_FALLING: - tb = 0x2; - break; - case IRQ_TYPE_EDGE_BOTH: - tb = 0x3; - break; - default: - /* Level triggered */ - tb = 0; - break; - } - - if (tb) - set_irq_handler(irq, handle_edge_irq); - - irq -= EINT0; - pa = __raw_readw(MCFEPORT_EPPAR); - pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2)); - __raw_writew(pa, MCFEPORT_EPPAR); - - return 0; -} - -static struct irq_chip intc_irq_chip = { - .name = "CF-INTC", - .irq_startup = intc_irq_startup, - .irq_mask = intc_irq_mask, - .irq_unmask = intc_irq_unmask, -}; - -static struct irq_chip intc_irq_chip_edge_port = { - .name = "CF-INTC-EP", - .irq_startup = intc_irq_startup, - .irq_mask = intc_irq_mask, - .irq_unmask = intc_irq_unmask, - .irq_ack = intc_irq_ack, - .irq_set_type = intc_irq_set_type, -}; - -void __init init_IRQ(void) -{ - int irq; - - init_vectors(); - - /* Mask all interrupt sources */ - __raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL); -#ifdef MCFICM_INTC1 - __raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL); -#endif - - for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) { - if ((irq >= EINT1) && (irq <=EINT7)) - set_irq_chip(irq, &intc_irq_chip_edge_port); - else - set_irq_chip(irq, &intc_irq_chip); - set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); - set_irq_handler(irq, handle_level_irq); - } -} - diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c deleted file mode 100644 index e642b24a..0000000 --- a/arch/m68knommu/platform/coldfire/intc-simr.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * intc-simr.c - * - * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts. - * - * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/traps.h> - -/* - * The EDGE Port interrupts are the fixed 7 external interrupts. - * They need some special treatment, for example they need to be acked. - */ -#ifdef CONFIG_M520x -/* - * The 520x parts only support a limited range of these external - * interrupts, only 1, 4 and 7 (as interrupts 65, 66 and 67). - */ -#define EINT0 64 /* Is not actually used, but spot reserved for it */ -#define EINT1 65 /* EDGE Port interrupt 1 */ -#define EINT4 66 /* EDGE Port interrupt 4 */ -#define EINT7 67 /* EDGE Port interrupt 7 */ - -static unsigned int irqebitmap[] = { 0, 1, 4, 7 }; -static unsigned int inline irq2ebit(unsigned int irq) -{ - return irqebitmap[irq - EINT0]; -} - -#else - -/* - * Most of the ColdFire parts with the EDGE Port module just have - * a strait direct mapping of the 7 external interrupts. Although - * there is a bit reserved for 0, it is not used. - */ -#define EINT0 64 /* Is not actually used, but spot reserved for it */ -#define EINT1 65 /* EDGE Port interrupt 1 */ -#define EINT7 71 /* EDGE Port interrupt 7 */ - -static unsigned int inline irq2ebit(unsigned int irq) -{ - return irq - EINT0; -} - -#endif - -/* - * There maybe one or two interrupt control units, each has 64 - * interrupts. If there is no second unit then MCFINTC1_* defines - * will be 0 (and code for them optimized away). - */ - -static void intc_irq_mask(struct irq_data *d) -{ - unsigned int irq = d->irq - MCFINT_VECBASE; - - if (MCFINTC1_SIMR && (irq > 64)) - __raw_writeb(irq - 64, MCFINTC1_SIMR); - else - __raw_writeb(irq, MCFINTC0_SIMR); -} - -static void intc_irq_unmask(struct irq_data *d) -{ - unsigned int irq = d->irq - MCFINT_VECBASE; - - if (MCFINTC1_CIMR && (irq > 64)) - __raw_writeb(irq - 64, MCFINTC1_CIMR); - else - __raw_writeb(irq, MCFINTC0_CIMR); -} - -static void intc_irq_ack(struct irq_data *d) -{ - unsigned int ebit = irq2ebit(d->irq); - - __raw_writeb(0x1 << ebit, MCFEPORT_EPFR); -} - -static unsigned int intc_irq_startup(struct irq_data *d) -{ - unsigned int irq = d->irq; - - if ((irq >= EINT1) && (irq <= EINT7)) { - unsigned int ebit = irq2ebit(irq); - u8 v; - - /* Set EPORT line as input */ - v = __raw_readb(MCFEPORT_EPDDR); - __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR); - - /* Set EPORT line as interrupt source */ - v = __raw_readb(MCFEPORT_EPIER); - __raw_writeb(v | (0x1 << ebit), MCFEPORT_EPIER); - } - - irq -= MCFINT_VECBASE; - if (MCFINTC1_ICR0 && (irq > 64)) - __raw_writeb(5, MCFINTC1_ICR0 + irq - 64); - else - __raw_writeb(5, MCFINTC0_ICR0 + irq); - - - intc_irq_unmask(d); - return 0; -} - -static int intc_irq_set_type(struct irq_data *d, unsigned int type) -{ - unsigned int ebit, irq = d->irq; - u16 pa, tb; - - switch (type) { - case IRQ_TYPE_EDGE_RISING: - tb = 0x1; - break; - case IRQ_TYPE_EDGE_FALLING: - tb = 0x2; - break; - case IRQ_TYPE_EDGE_BOTH: - tb = 0x3; - break; - default: - /* Level triggered */ - tb = 0; - break; - } - - if (tb) - set_irq_handler(irq, handle_edge_irq); - - ebit = irq2ebit(irq) * 2; - pa = __raw_readw(MCFEPORT_EPPAR); - pa = (pa & ~(0x3 << ebit)) | (tb << ebit); - __raw_writew(pa, MCFEPORT_EPPAR); - - return 0; -} - -static struct irq_chip intc_irq_chip = { - .name = "CF-INTC", - .irq_startup = intc_irq_startup, - .irq_mask = intc_irq_mask, - .irq_unmask = intc_irq_unmask, -}; - -static struct irq_chip intc_irq_chip_edge_port = { - .name = "CF-INTC-EP", - .irq_startup = intc_irq_startup, - .irq_mask = intc_irq_mask, - .irq_unmask = intc_irq_unmask, - .irq_ack = intc_irq_ack, - .irq_set_type = intc_irq_set_type, -}; - -void __init init_IRQ(void) -{ - int irq, eirq; - - init_vectors(); - - /* Mask all interrupt sources */ - __raw_writeb(0xff, MCFINTC0_SIMR); - if (MCFINTC1_SIMR) - __raw_writeb(0xff, MCFINTC1_SIMR); - - eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0); - for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { - if ((irq >= EINT1) && (irq <= EINT7)) - set_irq_chip(irq, &intc_irq_chip_edge_port); - else - set_irq_chip(irq, &intc_irq_chip); - set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); - set_irq_handler(irq, handle_level_irq); - } -} - diff --git a/arch/m68knommu/platform/coldfire/intc.c b/arch/m68knommu/platform/coldfire/intc.c deleted file mode 100644 index d648081..0000000 --- a/arch/m68knommu/platform/coldfire/intc.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * intc.c -- support for the old ColdFire interrupt controller - * - * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <asm/traps.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> - -/* - * The mapping of irq number to a mask register bit is not one-to-one. - * The irq numbers are either based on "level" of interrupt or fixed - * for an autovector-able interrupt. So we keep a local data structure - * that maps from irq to mask register. Not all interrupts will have - * an IMR bit. - */ -unsigned char mcf_irq2imr[NR_IRQS]; - -/* - * Define the miniumun and maximum external interrupt numbers. - * This is also used as the "level" interrupt numbers. - */ -#define EIRQ1 25 -#define EIRQ7 31 - -/* - * In the early version 2 core ColdFire parts the IMR register was 16 bits - * in size. Version 3 (and later version 2) core parts have a 32 bit - * sized IMR register. Provide some size independant methods to access the - * IMR register. - */ -#ifdef MCFSIM_IMR_IS_16BITS - -void mcf_setimr(int index) -{ - u16 imr; - imr = __raw_readw(MCF_MBAR + MCFSIM_IMR); - __raw_writew(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR); -} - -void mcf_clrimr(int index) -{ - u16 imr; - imr = __raw_readw(MCF_MBAR + MCFSIM_IMR); - __raw_writew(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR); -} - -void mcf_maskimr(unsigned int mask) -{ - u16 imr; - imr = __raw_readw(MCF_MBAR + MCFSIM_IMR); - imr |= mask; - __raw_writew(imr, MCF_MBAR + MCFSIM_IMR); -} - -#else - -void mcf_setimr(int index) -{ - u32 imr; - imr = __raw_readl(MCF_MBAR + MCFSIM_IMR); - __raw_writel(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR); -} - -void mcf_clrimr(int index) -{ - u32 imr; - imr = __raw_readl(MCF_MBAR + MCFSIM_IMR); - __raw_writel(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR); -} - -void mcf_maskimr(unsigned int mask) -{ - u32 imr; - imr = __raw_readl(MCF_MBAR + MCFSIM_IMR); - imr |= mask; - __raw_writel(imr, MCF_MBAR + MCFSIM_IMR); -} - -#endif - -/* - * Interrupts can be "vectored" on the ColdFire cores that support this old - * interrupt controller. That is, the device raising the interrupt can also - * supply the vector number to interrupt through. The AVR register of the - * interrupt controller enables or disables this for each external interrupt, - * so provide generic support for this. Setting this up is out-of-band for - * the interrupt system API's, and needs to be done by the driver that - * supports this device. Very few devices actually use this. - */ -void mcf_autovector(int irq) -{ -#ifdef MCFSIM_AVR - if ((irq >= EIRQ1) && (irq <= EIRQ7)) { - u8 avec; - avec = __raw_readb(MCF_MBAR + MCFSIM_AVR); - avec |= (0x1 << (irq - EIRQ1 + 1)); - __raw_writeb(avec, MCF_MBAR + MCFSIM_AVR); - } -#endif -} - -static void intc_irq_mask(struct irq_data *d) -{ - if (mcf_irq2imr[d->irq]) - mcf_setimr(mcf_irq2imr[d->irq]); -} - -static void intc_irq_unmask(struct irq_data *d) -{ - if (mcf_irq2imr[d->irq]) - mcf_clrimr(mcf_irq2imr[d->irq]); -} - -static int intc_irq_set_type(struct irq_data *d, unsigned int type) -{ - return 0; -} - -static struct irq_chip intc_irq_chip = { - .name = "CF-INTC", - .irq_mask = intc_irq_mask, - .irq_unmask = intc_irq_unmask, - .irq_set_type = intc_irq_set_type, -}; - -void __init init_IRQ(void) -{ - int irq; - - init_vectors(); - mcf_maskimr(0xffffffff); - - for (irq = 0; (irq < NR_IRQS); irq++) { - set_irq_chip(irq, &intc_irq_chip); - set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); - set_irq_handler(irq, handle_level_irq); - } -} - diff --git a/arch/m68knommu/platform/coldfire/pinmux.c b/arch/m68knommu/platform/coldfire/pinmux.c deleted file mode 100644 index 8c62b82..0000000 --- a/arch/m68knommu/platform/coldfire/pinmux.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Coldfire generic GPIO pinmux support. - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> - -#include <asm/pinmux.h> - -int mcf_pinmux_request(unsigned pinmux, unsigned func) -{ - return 0; -} - -void mcf_pinmux_release(unsigned pinmux, unsigned func) -{ -} diff --git a/arch/m68knommu/platform/coldfire/pit.c b/arch/m68knommu/platform/coldfire/pit.c deleted file mode 100644 index c2b9809..0000000 --- a/arch/m68knommu/platform/coldfire/pit.c +++ /dev/null @@ -1,169 +0,0 @@ -/***************************************************************************/ - -/* - * pit.c -- Freescale ColdFire PIT timer. Currently this type of - * hardware timer only exists in the Freescale ColdFire - * 5270/5271, 5282 and 5208 CPUs. No doubt newer ColdFire - * family members will probably use it too. - * - * Copyright (C) 1999-2008, Greg Ungerer (gerg@snapgear.com) - * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/clockchips.h> -#include <asm/machdep.h> -#include <asm/io.h> -#include <asm/coldfire.h> -#include <asm/mcfpit.h> -#include <asm/mcfsim.h> - -/***************************************************************************/ - -/* - * By default use timer1 as the system clock timer. - */ -#define FREQ ((MCF_CLK / 2) / 64) -#define TA(a) (MCFPIT_BASE1 + (a)) -#define PIT_CYCLES_PER_JIFFY (FREQ / HZ) - -static u32 pit_cnt; - -/* - * Initialize the PIT timer. - * - * This is also called after resume to bring the PIT into operation again. - */ - -static void init_cf_pit_timer(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - - __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); - __raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR)); - __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | \ - MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD | \ - MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR)); - break; - - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - - __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); - break; - - case CLOCK_EVT_MODE_ONESHOT: - - __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); - __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | \ - MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, \ - TA(MCFPIT_PCSR)); - break; - - case CLOCK_EVT_MODE_RESUME: - /* Nothing to do here */ - break; - } -} - -/* - * Program the next event in oneshot mode - * - * Delta is given in PIT ticks - */ -static int cf_pit_next_event(unsigned long delta, - struct clock_event_device *evt) -{ - __raw_writew(delta, TA(MCFPIT_PMR)); - return 0; -} - -struct clock_event_device cf_pit_clockevent = { - .name = "pit", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_mode = init_cf_pit_timer, - .set_next_event = cf_pit_next_event, - .shift = 32, - .irq = MCFINT_VECBASE + MCFINT_PIT1, -}; - - - -/***************************************************************************/ - -static irqreturn_t pit_tick(int irq, void *dummy) -{ - struct clock_event_device *evt = &cf_pit_clockevent; - u16 pcsr; - - /* Reset the ColdFire timer */ - pcsr = __raw_readw(TA(MCFPIT_PCSR)); - __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR)); - - pit_cnt += PIT_CYCLES_PER_JIFFY; - evt->event_handler(evt); - return IRQ_HANDLED; -} - -/***************************************************************************/ - -static struct irqaction pit_irq = { - .name = "timer", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = pit_tick, -}; - -/***************************************************************************/ - -static cycle_t pit_read_clk(struct clocksource *cs) -{ - unsigned long flags; - u32 cycles; - u16 pcntr; - - local_irq_save(flags); - pcntr = __raw_readw(TA(MCFPIT_PCNTR)); - cycles = pit_cnt; - local_irq_restore(flags); - - return cycles + PIT_CYCLES_PER_JIFFY - pcntr; -} - -/***************************************************************************/ - -static struct clocksource pit_clk = { - .name = "pit", - .rating = 100, - .read = pit_read_clk, - .shift = 20, - .mask = CLOCKSOURCE_MASK(32), -}; - -/***************************************************************************/ - -void hw_timer_init(void) -{ - cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id()); - cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32); - cf_pit_clockevent.max_delta_ns = - clockevent_delta2ns(0xFFFF, &cf_pit_clockevent); - cf_pit_clockevent.min_delta_ns = - clockevent_delta2ns(0x3f, &cf_pit_clockevent); - clockevents_register_device(&cf_pit_clockevent); - - setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq); - - pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift); - clocksource_register(&pit_clk); -} - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/coldfire/sltimers.c b/arch/m68knommu/platform/coldfire/sltimers.c deleted file mode 100644 index 0a1b937..0000000 --- a/arch/m68knommu/platform/coldfire/sltimers.c +++ /dev/null @@ -1,145 +0,0 @@ -/***************************************************************************/ - -/* - * sltimers.c -- generic ColdFire slice timer support. - * - * Copyright (C) 2009-2010, Philippe De Muyter <phdm@macqel.be> - * based on - * timers.c -- generic ColdFire hardware timer support. - * Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com> - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/profile.h> -#include <linux/clocksource.h> -#include <asm/io.h> -#include <asm/traps.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfslt.h> -#include <asm/mcfsim.h> - -/***************************************************************************/ - -#ifdef CONFIG_HIGHPROFILE - -/* - * By default use Slice Timer 1 as the profiler clock timer. - */ -#define PA(a) (MCF_MBAR + MCFSLT_TIMER1 + (a)) - -/* - * Choose a reasonably fast profile timer. Make it an odd value to - * try and get good coverage of kernel operations. - */ -#define PROFILEHZ 1013 - -irqreturn_t mcfslt_profile_tick(int irq, void *dummy) -{ - /* Reset Slice Timer 1 */ - __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR)); - if (current->pid) - profile_tick(CPU_PROFILING); - return IRQ_HANDLED; -} - -static struct irqaction mcfslt_profile_irq = { - .name = "profile timer", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = mcfslt_profile_tick, -}; - -void mcfslt_profile_init(void) -{ - printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n", - PROFILEHZ); - - setup_irq(MCF_IRQ_PROFILER, &mcfslt_profile_irq); - - /* Set up TIMER 2 as high speed profile clock */ - __raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT)); - __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN, - PA(MCFSLT_SCR)); - -} - -#endif /* CONFIG_HIGHPROFILE */ - -/***************************************************************************/ - -/* - * By default use Slice Timer 0 as the system clock timer. - */ -#define TA(a) (MCF_MBAR + MCFSLT_TIMER0 + (a)) - -static u32 mcfslt_cycles_per_jiffy; -static u32 mcfslt_cnt; - -static irqreturn_t mcfslt_tick(int irq, void *dummy) -{ - /* Reset Slice Timer 0 */ - __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR)); - mcfslt_cnt += mcfslt_cycles_per_jiffy; - return arch_timer_interrupt(irq, dummy); -} - -static struct irqaction mcfslt_timer_irq = { - .name = "timer", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = mcfslt_tick, -}; - -static cycle_t mcfslt_read_clk(struct clocksource *cs) -{ - unsigned long flags; - u32 cycles; - u16 scnt; - - local_irq_save(flags); - scnt = __raw_readl(TA(MCFSLT_SCNT)); - cycles = mcfslt_cnt; - local_irq_restore(flags); - - /* substract because slice timers count down */ - return cycles - scnt; -} - -static struct clocksource mcfslt_clk = { - .name = "slt", - .rating = 250, - .read = mcfslt_read_clk, - .shift = 20, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -void hw_timer_init(void) -{ - mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ; - /* - * The coldfire slice timer (SLT) runs from STCNT to 0 included, - * then STCNT again and so on. It counts thus actually - * STCNT + 1 steps for 1 tick, not STCNT. So if you want - * n cycles, initialize STCNT with n - 1. - */ - __raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT)); - __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN, - TA(MCFSLT_SCR)); - /* initialize mcfslt_cnt knowing that slice timers count down */ - mcfslt_cnt = mcfslt_cycles_per_jiffy; - - setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq); - - mcfslt_clk.mult = clocksource_hz2mult(MCF_BUSCLK, mcfslt_clk.shift); - clocksource_register(&mcfslt_clk); - -#ifdef CONFIG_HIGHPROFILE - mcfslt_profile_init(); -#endif -} diff --git a/arch/m68knommu/platform/coldfire/timers.c b/arch/m68knommu/platform/coldfire/timers.c deleted file mode 100644 index 60242f6..0000000 --- a/arch/m68knommu/platform/coldfire/timers.c +++ /dev/null @@ -1,174 +0,0 @@ -/***************************************************************************/ - -/* - * timers.c -- generic ColdFire hardware timer support. - * - * Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com> - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/profile.h> -#include <linux/clocksource.h> -#include <asm/io.h> -#include <asm/traps.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcftimer.h> -#include <asm/mcfsim.h> - -/***************************************************************************/ - -/* - * By default use timer1 as the system clock timer. - */ -#define FREQ (MCF_BUSCLK / 16) -#define TA(a) (MCFTIMER_BASE1 + (a)) - -/* - * These provide the underlying interrupt vector support. - * Unfortunately it is a little different on each ColdFire. - */ -void coldfire_profile_init(void); - -#if defined(CONFIG_M532x) -#define __raw_readtrr __raw_readl -#define __raw_writetrr __raw_writel -#else -#define __raw_readtrr __raw_readw -#define __raw_writetrr __raw_writew -#endif - -static u32 mcftmr_cycles_per_jiffy; -static u32 mcftmr_cnt; - -/***************************************************************************/ - -static irqreturn_t mcftmr_tick(int irq, void *dummy) -{ - /* Reset the ColdFire timer */ - __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER)); - - mcftmr_cnt += mcftmr_cycles_per_jiffy; - return arch_timer_interrupt(irq, dummy); -} - -/***************************************************************************/ - -static struct irqaction mcftmr_timer_irq = { - .name = "timer", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = mcftmr_tick, -}; - -/***************************************************************************/ - -static cycle_t mcftmr_read_clk(struct clocksource *cs) -{ - unsigned long flags; - u32 cycles; - u16 tcn; - - local_irq_save(flags); - tcn = __raw_readw(TA(MCFTIMER_TCN)); - cycles = mcftmr_cnt; - local_irq_restore(flags); - - return cycles + tcn; -} - -/***************************************************************************/ - -static struct clocksource mcftmr_clk = { - .name = "tmr", - .rating = 250, - .read = mcftmr_read_clk, - .shift = 20, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -/***************************************************************************/ - -void hw_timer_init(void) -{ - __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR)); - mcftmr_cycles_per_jiffy = FREQ / HZ; - /* - * The coldfire timer runs from 0 to TRR included, then 0 - * again and so on. It counts thus actually TRR + 1 steps - * for 1 tick, not TRR. So if you want n cycles, - * initialize TRR with n - 1. - */ - __raw_writetrr(mcftmr_cycles_per_jiffy - 1, TA(MCFTIMER_TRR)); - __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | - MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR)); - - mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift); - clocksource_register(&mcftmr_clk); - - setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq); - -#ifdef CONFIG_HIGHPROFILE - coldfire_profile_init(); -#endif -} - -/***************************************************************************/ -#ifdef CONFIG_HIGHPROFILE -/***************************************************************************/ - -/* - * By default use timer2 as the profiler clock timer. - */ -#define PA(a) (MCFTIMER_BASE2 + (a)) - -/* - * Choose a reasonably fast profile timer. Make it an odd value to - * try and get good coverage of kernel operations. - */ -#define PROFILEHZ 1013 - -/* - * Use the other timer to provide high accuracy profiling info. - */ -irqreturn_t coldfire_profile_tick(int irq, void *dummy) -{ - /* Reset ColdFire timer2 */ - __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER)); - if (current->pid) - profile_tick(CPU_PROFILING); - return IRQ_HANDLED; -} - -/***************************************************************************/ - -static struct irqaction coldfire_profile_irq = { - .name = "profile timer", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = coldfire_profile_tick, -}; - -void coldfire_profile_init(void) -{ - printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n", - PROFILEHZ); - - /* Set up TIMER 2 as high speed profile clock */ - __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR)); - - __raw_writetrr(((MCF_BUSCLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR)); - __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | - MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR)); - - setup_irq(MCF_IRQ_PROFILER, &coldfire_profile_irq); -} - -/***************************************************************************/ -#endif /* CONFIG_HIGHPROFILE */ -/***************************************************************************/ diff --git a/arch/m68knommu/platform/coldfire/vectors.c b/arch/m68knommu/platform/coldfire/vectors.c deleted file mode 100644 index a21d3f8..0000000 --- a/arch/m68knommu/platform/coldfire/vectors.c +++ /dev/null @@ -1,80 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/coldfire/vectors.c - * - * Copyright (C) 1999-2007, Greg Ungerer <gerg@snapgear.com> - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/irq.h> -#include <asm/traps.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfwdebug.h> - -/***************************************************************************/ - -#ifdef TRAP_DBG_INTERRUPT - -asmlinkage void dbginterrupt_c(struct frame *fp) -{ - extern void dump(struct pt_regs *fp); - printk(KERN_DEBUG "%s(%d): BUS ERROR TRAP\n", __FILE__, __LINE__); - dump((struct pt_regs *) fp); - asm("halt"); -} - -#endif - -/***************************************************************************/ - -extern e_vector *_ramvec; - -void set_evector(int vecnum, void (*handler)(void)) -{ - if (vecnum >= 0 && vecnum <= 255) - _ramvec[vecnum] = handler; -} - -/***************************************************************************/ - -/* Assembler routines */ -asmlinkage void buserr(void); -asmlinkage void trap(void); -asmlinkage void system_call(void); -asmlinkage void inthandler(void); - -void __init init_vectors(void) -{ - int i; - - /* - * There is a common trap handler and common interrupt - * handler that handle almost every vector. We treat - * the system call and bus error special, they get their - * own first level handlers. - */ - for (i = 3; (i <= 23); i++) - _ramvec[i] = trap; - for (i = 33; (i <= 63); i++) - _ramvec[i] = trap; - for (i = 24; (i <= 31); i++) - _ramvec[i] = inthandler; - for (i = 64; (i < 255); i++) - _ramvec[i] = inthandler; - _ramvec[255] = 0; - - _ramvec[2] = buserr; - _ramvec[32] = system_call; - -#ifdef TRAP_DBG_INTERRUPT - _ramvec[12] = dbginterrupt; -#endif -} - -/***************************************************************************/ |
