diff options
Diffstat (limited to 'arch/blackfin/mach-bf527')
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h | 14 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/defBF52x_base.h | 8 |
2 files changed, 6 insertions, 16 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h index 3048b52b..4e484ef 100644 --- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h +++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h @@ -394,16 +394,10 @@ /* DMA Traffic Control Registers */ -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) -#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val) -#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) -#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val) +#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) +#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val) +#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) +#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val) /* DMA Controller */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h index d2594f3..2e6f8aa 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h @@ -215,12 +215,8 @@ /* DMA Traffic Control Registers */ -#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ +#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ |
