diff options
Diffstat (limited to 'arch/arm')
73 files changed, 517 insertions, 526 deletions
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 19a3dcf..ba4003e 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -109,23 +109,41 @@ choice 0x80020000 | 0xf0020000 | UART8 0x80024000 | 0xf0024000 | UART9 - config DEBUG_AT91_UART - bool "Kernel low-level debugging on Atmel SoCs" - depends on ARCH_AT91 + config DEBUG_AT91_RM9200_DBGU + bool "Kernel low-level debugging on AT91RM9200, AT91SAM9 DBGU" + select DEBUG_AT91_UART + depends on SOC_AT91RM9200 || SOC_AT91SAM9 help - Say Y here if you want the debug print routines to direct - their output to the serial port on atmel devices. + Say Y here if you want kernel low-level debugging support + on the DBGU port of: + at91rm9200, at91sam9260, at91sam9g20, at91sam9261, + at91sam9g10, at91sam9n12, at91sam9rl64, at91sam9x5 - SOC DEBUG_UART_PHYS DEBUG_UART_VIRT PORT - rm9200, 9260/9g20, 0xfffff200 0xfefff200 DBGU - 9261/9g10, 9rl - 9263, 9g45, sama5d3 0xffffee00 0xfeffee00 DBGU - sama5d4 0xfc00c000 0xfb00c000 USART3 - sama5d4 0xfc069000 0xfb069000 DBGU - sama5d2 0xf8020000 0xf7020000 UART1 + config DEBUG_AT91_SAM9263_DBGU + bool "Kernel low-level debugging on AT91SAM{9263,9G45,A5D3} DBGU" + select DEBUG_AT91_UART + depends on SOC_AT91SAM9 || SOC_SAMA5D3 + help + Say Y here if you want kernel low-level debugging support + on the DBGU port of: + at91sam9263, at91sam9g45, at91sam9m10, + sama5d3 - Please adjust DEBUG_UART_PHYS configuration options based on - your needs. + config DEBUG_AT91_SAMA5D2_UART1 + bool "Kernel low-level debugging on SAMA5D2 UART1" + select DEBUG_AT91_UART + depends on SOC_SAMA5D2 + help + Say Y here if you want kernel low-level debugging support + on the UART1 port of sama5d2. + + config DEBUG_AT91_SAMA5D4_USART3 + bool "Kernel low-level debugging on SAMA5D4 USART3" + select DEBUG_AT91_UART + depends on SOC_SAMA5D4 + help + Say Y here if you want kernel low-level debugging support + on the USART3 port of sama5d4. config DEBUG_BCM2835 bool "Kernel low-level debugging on BCM2835 PL011 UART" @@ -1296,6 +1314,10 @@ choice endchoice +config DEBUG_AT91_UART + bool + depends on ARCH_AT91 + config DEBUG_EXYNOS_UART bool @@ -1502,8 +1524,10 @@ config DEBUG_UART_PHYS default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE default 0xf1012100 if DEBUG_MVEBU_UART1_ALTERNATE default 0xf7fc9000 if DEBUG_BERLIN_UART + default 0xf8020000 if DEBUG_AT91_SAMA5D2_UART1 default 0xf8b00000 if DEBUG_HIX5HD2_UART default 0xf991e000 if DEBUG_QCOM_UARTDM + default 0xfc00c000 if DEBUG_AT91_SAMA5D4_USART3 default 0xfcb00000 if DEBUG_HI3620_UART default 0xfd883000 if DEBUG_ALPINE_UART0 default 0xfe800000 if ARCH_IOP32X @@ -1518,6 +1542,8 @@ config DEBUG_UART_PHYS default 0xfffb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 default 0xfffb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3 default 0xfffe8600 if DEBUG_BCM63XX_UART + default 0xffffee00 if DEBUG_AT91_SAM9263_DBGU + default 0xfffff200 if DEBUG_AT91_RM9200_DBGU default 0xfffff700 if ARCH_IOP33X depends on ARCH_EP93XX || \ DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ @@ -1566,13 +1592,17 @@ config DEBUG_UART_VIRT DEBUG_S3C2410_UART1) default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \ DEBUG_S3C2410_UART2) + default 0xf7020000 if DEBUG_AT91_SAMA5D2_UART1 default 0xf7fc9000 if DEBUG_BERLIN_UART default 0xf8007000 if DEBUG_HIP04_UART default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9 default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1 + default 0xf8ffee00 if DEBUG_AT91_SAM9263_DBGU + default 0xf8fff200 if DEBUG_AT91_RM9200_DBGU default 0xfa71e000 if DEBUG_QCOM_UARTDM default 0xfb002000 if DEBUG_CNS3XXX default 0xfb009000 if DEBUG_REALVIEW_STD_PORT + default 0xfb00c000 if DEBUG_AT91_SAMA5D4_USART3 default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT default 0xfc40ab00 if DEBUG_BRCMSTB_UART default 0xfc705000 if DEBUG_ZTE_ZX @@ -1627,7 +1657,8 @@ config DEBUG_UART_VIRT DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \ DEBUG_S3C64XX_UART || \ DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ - DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 + DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \ + DEBUG_AT91_UART config DEBUG_UART_8250_SHIFT int "Register offset shift for the 8250 debug UART" diff --git a/arch/arm/include/debug/at91.S b/arch/arm/include/debug/at91.S index d4ae3b8..0098401 100644 --- a/arch/arm/include/debug/at91.S +++ b/arch/arm/include/debug/at91.S @@ -9,14 +9,6 @@ * */ -#ifdef CONFIG_MMU -#define AT91_IO_P2V(x) ((x) - 0x01000000) -#else -#define AT91_IO_P2V(x) (x) -#endif - -#define AT91_DEBUG_UART_VIRT AT91_IO_P2V(CONFIG_DEBUG_UART_PHYS) - #define AT91_DBGU_SR (0x14) /* Status Register */ #define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */ #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ @@ -24,7 +16,7 @@ .macro addruart, rp, rv, tmp ldr \rp, =CONFIG_DEBUG_UART_PHYS @ System peripherals (phys address) - ldr \rv, =AT91_DEBUG_UART_VIRT @ System peripherals (virt address) + ldr \rv, =CONFIG_DEBUG_UART_VIRT @ System peripherals (virt address) .endm .macro senduart,rd,rx diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index ef9119f..4d93758 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -733,8 +733,8 @@ static int vfp_set(struct task_struct *target, if (ret) return ret; - vfp_flush_hwstate(thread); thread->vfpstate.hard = new_vfp; + vfp_flush_hwstate(thread); return 0; } diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index f062701..b4332b7 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -22,6 +22,7 @@ #include <linux/of_platform.h> #include <linux/of_address.h> #include <linux/platform_device.h> +#include <linux/platform_data/atmel.h> #include <linux/io.h> #include <linux/clk/at91_pmc.h> @@ -355,7 +356,7 @@ static __init void at91_dt_ramc(void) at91_pm_set_standby(standby); } -void at91rm9200_idle(void) +static void at91rm9200_idle(void) { /* * Disable the processor clock. The processor will be automatically @@ -364,7 +365,7 @@ void at91rm9200_idle(void) writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR); } -void at91sam9_idle(void) +static void at91sam9_idle(void) { writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR); cpu_do_idle(); diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 68ab641..5832dba 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -111,9 +111,17 @@ config ARCH_BCM_21664 Enable support for the BCM21664 family, which includes BCM21663 and BCM21664 variants. +config ARCH_BCM_23550 + bool "Broadcom BCM23550 SoC" + depends on ARCH_MULTI_V7 + select ARCH_BCM_MOBILE + select HAVE_SMP + help + Enable support for the BCM23550. + config ARCH_BCM_MOBILE_L2_CACHE bool "Broadcom mobile SoC level 2 cache support" - depends on ARCH_BCM_MOBILE + depends on ARCH_BCM_281XX || ARCH_BCM_21664 default y select CACHE_L2X0 select ARCH_BCM_MOBILE_SMC @@ -128,7 +136,7 @@ config ARCH_BCM_MOBILE_SMP select HAVE_ARM_SCU select ARM_ERRATA_764369 help - SMP support for the BCM281XX and BCM21664 SoC families. + SMP support for the BCM281XX, BCM21664 and BCM23550 SoC families. Provided as an option so SMP support for SoCs of this type can be disabled for an SMP-enabled kernel. diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index 7d66515..980f585 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -26,7 +26,10 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o # BCM21664 obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o -# BCM281XX and BCM21664 SMP support +# BCM23550 +obj-$(CONFIG_ARCH_BCM_23550) += board_bcm23550.o + +# BCM281XX, BCM21664 and BCM23550 SMP support obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o # BCM281XX and BCM21664 L2 cache control diff --git a/arch/arm/mach-bcm/board_bcm21664.c b/arch/arm/mach-bcm/board_bcm21664.c index 82ad568..65b3db0 100644 --- a/arch/arm/mach-bcm/board_bcm21664.c +++ b/arch/arm/mach-bcm/board_bcm21664.c @@ -11,53 +11,12 @@ * GNU General Public License for more details. */ -#include <linux/of_address.h> #include <linux/of_platform.h> -#include <linux/io.h> #include <asm/mach/arch.h> #include "kona_l2_cache.h" -#define RSTMGR_DT_STRING "brcm,bcm21664-resetmgr" - -#define RSTMGR_REG_WR_ACCESS_OFFSET 0 -#define RSTMGR_REG_CHIP_SOFT_RST_OFFSET 4 - -#define RSTMGR_WR_PASSWORD 0xa5a5 -#define RSTMGR_WR_PASSWORD_SHIFT 8 -#define RSTMGR_WR_ACCESS_ENABLE 1 - -static void bcm21664_restart(enum reboot_mode mode, const char *cmd) -{ - void __iomem *base; - struct device_node *resetmgr; - - resetmgr = of_find_compatible_node(NULL, NULL, RSTMGR_DT_STRING); - if (!resetmgr) { - pr_emerg("Couldn't find " RSTMGR_DT_STRING "\n"); - return; - } - base = of_iomap(resetmgr, 0); - if (!base) { - pr_emerg("Couldn't map " RSTMGR_DT_STRING "\n"); - return; - } - - /* - * A soft reset is triggered by writing a 0 to bit 0 of the soft reset - * register. To write to that register we must first write the password - * and the enable bit in the write access enable register. - */ - writel((RSTMGR_WR_PASSWORD << RSTMGR_WR_PASSWORD_SHIFT) | - RSTMGR_WR_ACCESS_ENABLE, - base + RSTMGR_REG_WR_ACCESS_OFFSET); - writel(0, base + RSTMGR_REG_CHIP_SOFT_RST_OFFSET); - - /* Wait for reset */ - while (1); -} - static void __init bcm21664_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); @@ -71,6 +30,5 @@ static const char * const bcm21664_dt_compat[] = { DT_MACHINE_START(BCM21664_DT, "BCM21664 Broadcom Application Processor") .init_machine = bcm21664_init, - .restart = bcm21664_restart, .dt_compat = bcm21664_dt_compat, MACHINE_END diff --git a/arch/arm/mach-bcm/board_bcm23550.c b/arch/arm/mach-bcm/board_bcm23550.c new file mode 100644 index 0000000..0ac01de --- /dev/null +++ b/arch/arm/mach-bcm/board_bcm23550.c @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2016 Broadcom + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/of_platform.h> + +#include <asm/mach/arch.h> + +static const char * const bcm23550_dt_compat[] = { + "brcm,bcm23550", + NULL, +}; + +DT_MACHINE_START(BCM23550_DT, "BCM23550 Broadcom Application Processor") + .dt_compat = bcm23550_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-bcm/kona_l2_cache.c b/arch/arm/mach-bcm/kona_l2_cache.c index b319703..59ad863 100644 --- a/arch/arm/mach-bcm/kona_l2_cache.c +++ b/arch/arm/mach-bcm/kona_l2_cache.c @@ -17,6 +17,7 @@ #include <asm/hardware/cache-l2x0.h> #include "bcm_kona_smc.h" +#include "kona_l2_cache.h" void __init kona_l2_cache_init(void) { diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c index cfae9c7..33c4d83 100644 --- a/arch/arm/mach-bcm/platsmp.c +++ b/arch/arm/mach-bcm/platsmp.c @@ -19,6 +19,7 @@ #include <linux/io.h> #include <linux/jiffies.h> #include <linux/of.h> +#include <linux/of_address.h> #include <linux/sched.h> #include <linux/smp.h> @@ -255,6 +256,57 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) return -ENXIO; } +/* Cluster Dormant Control command to bring CPU into a running state */ +#define CDC_CMD 6 +#define CDC_CMD_OFFSET 0 +#define CDC_CMD_REG(cpu) (CDC_CMD_OFFSET + 4*(cpu)) + +/* + * BCM23550 has a Cluster Dormant Control block that keeps the core in + * idle state. A command needs to be sent to the block to bring the CPU + * into running state. + */ +static int bcm23550_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + void __iomem *cdc_base; + struct device_node *dn; + char *name; + int ret; + + /* Make sure a CDC node exists before booting the + * secondary core. + */ + name = "brcm,bcm23550-cdc"; + dn = of_find_compatible_node(NULL, NULL, name); + if (!dn) { + pr_err("unable to find cdc node\n"); + return -ENODEV; + } + + cdc_base = of_iomap(dn, 0); + of_node_put(dn); + + if (!cdc_base) { + pr_err("unable to remap cdc base register\n"); + return -ENOMEM; + } + + /* Boot the secondary core */ + ret = kona_boot_secondary(cpu, idle); + if (ret) + goto out; + + /* Bring this CPU to RUN state so that nIRQ nFIQ + * signals are unblocked. + */ + writel_relaxed(CDC_CMD, cdc_base + CDC_CMD_REG(cpu)); + +out: + iounmap(cdc_base); + + return ret; +} + static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle) { int ret; @@ -283,6 +335,12 @@ static const struct smp_operations bcm_smp_ops __initconst = { CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", &bcm_smp_ops); +static const struct smp_operations bcm23550_smp_ops __initconst = { + .smp_boot_secondary = bcm23550_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(bcm_smp_bcm23550, "brcm,bcm23550", + &bcm23550_smp_ops); + static const struct smp_operations nsp_smp_ops __initconst = { .smp_prepare_cpus = bcm_smp_prepare_cpus, .smp_boot_secondary = nsp_boot_secondary, diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index 1844076..18296a9 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -115,8 +115,6 @@ static struct davinci_i2c_platform_data i2c_pdata = { .scl_pin = 14, }; -static struct snd_platform_data dm355_evm_snd_data; - static int dm355evm_mmc_gpios = -EINVAL; static void dm355evm_mmcsd_gpios(unsigned gpio) @@ -411,7 +409,7 @@ static __init void dm355_evm_init(void) ARRAY_SIZE(dm355_evm_spi_info)); /* DM335 EVM uses ASP1; line-out is a stereo mini-jack */ - dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN, &dm355_evm_snd_data); + dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN); } MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM") diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index f073518..e832949 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -176,10 +176,6 @@ static struct at24_platform_data eeprom_info = { .context = (void *)0x7f00, }; -static struct snd_platform_data dm365_evm_snd_data __maybe_unused = { - .asp_chan_q = EVENTQ_3, -}; - static struct i2c_board_info i2c_info[] = { { I2C_BOARD_INFO("24c256", 0x50), @@ -763,7 +759,7 @@ static __init void dm365_evm_init(void) evm_init_cpld(); #ifdef CONFIG_SND_DM365_AIC3X_CODEC - dm365_init_asp(&dm365_evm_snd_data); + dm365_init_asp(); #elif defined(CONFIG_SND_DM365_VOICE_CODEC) dm365_init_vc(&dm365_evm_snd_data); #endif diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 68cc099..96a9528 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -264,8 +264,6 @@ static struct platform_device rtc_dev = { .id = -1, }; -static struct snd_platform_data dm644x_evm_snd_data; - /*----------------------------------------------------------------------*/ #ifdef CONFIG_I2C /* @@ -799,7 +797,7 @@ static __init void davinci_evm_init(void) dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg); davinci_serial_init(dm644x_serial_device); - dm644x_init_asp(&dm644x_evm_snd_data); + dm644x_init_asp(); /* irlml6401 switches over 1A, in under 8 msec */ davinci_setup_usb(1000, 8); diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index 8fcdcf8..ad10017 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c @@ -127,8 +127,6 @@ static struct platform_device davinci_fb_device = { .num_resources = 0, }; -static struct snd_platform_data dm644x_ntosd2_snd_data; - static struct gpio_led ntosd2_leds[] = { { .name = "led1_green", .gpio = GPIO(10), }, { .name = "led1_red", .gpio = GPIO(11), }, @@ -200,7 +198,7 @@ static __init void davinci_ntosd2_init(void) ARRAY_SIZE(davinci_ntosd2_devices)); davinci_serial_init(dm644x_serial_device); - dm644x_init_asp(&dm644x_ntosd2_snd_data); + dm644x_init_asp(); soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID; diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 2398862..0d046ac 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -326,6 +326,20 @@ static struct clk mcasp_clk = { .gpsc = 1, }; +static struct clk mcbsp0_clk = { + .name = "mcbsp0", + .parent = &async3_clk, + .lpsc = DA850_LPSC1_McBSP0, + .gpsc = 1, +}; + +static struct clk mcbsp1_clk = { + .name = "mcbsp1", + .parent = &async3_clk, + .lpsc = DA850_LPSC1_McBSP1, + .gpsc = 1, +}; + static struct clk lcdc_clk = { .name = "lcdc", .parent = &pll0_sysclk2, @@ -482,6 +496,8 @@ static struct clk_lookup da850_clks[] = { CLK("davinci_emac.1", NULL, &emac_clk), CLK("davinci_mdio.0", "fck", &emac_clk), CLK("davinci-mcasp.0", NULL, &mcasp_clk), + CLK("davinci-mcbsp.0", NULL, &mcbsp0_clk), + CLK("davinci-mcbsp.1", NULL, &mcbsp1_clk), CLK("da8xx_lcdc.0", "fck", &lcdc_clk), CLK("da830-mmc.0", NULL, &mmcsd0_clk), CLK("da830-mmc.1", NULL, &mmcsd1_clk), diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index 4ffc37a..d1f8e29 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -85,13 +85,13 @@ int davinci_init_wdt(void); void dm355_init(void); void dm355_init_spi0(unsigned chipselect_mask, const struct spi_board_info *info, unsigned len); -void dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata); +void dm355_init_asp1(u32 evt_enable); int dm355_init_video(struct vpfe_config *, struct vpbe_config *); int dm355_gpio_register(void); /* DM365 function declarations */ void dm365_init(void); -void dm365_init_asp(struct snd_platform_data *pdata); +void dm365_init_asp(void); void dm365_init_vc(struct snd_platform_data *pdata); void dm365_init_ks(struct davinci_ks_platform_data *pdata); void dm365_init_rtc(void); @@ -102,7 +102,7 @@ int dm365_gpio_register(void); /* DM644x function declarations */ void dm644x_init(void); -void dm644x_init_asp(struct snd_platform_data *pdata); +void dm644x_init_asp(void); int dm644x_init_video(struct vpfe_config *, struct vpbe_config *); int dm644x_gpio_register(void); diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 5a19cca..d33322dd 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -1035,7 +1035,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = { .sram_len = SZ_32K, }; -void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata) +void __init dm355_init_asp1(u32 evt_enable) { /* we don't use ASP1 IRQs, or we'd need to mux them ... */ if (evt_enable & ASP1_TX_EVT_EN) @@ -1044,7 +1044,6 @@ void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata) if (evt_enable & ASP1_RX_EVT_EN) davinci_cfg_reg(DM355_EVT9_ASP1_RX); - dm355_asp1_device.dev.platform_data = pdata; platform_device_register(&dm355_asp1_device); } diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 8aa004b..95fbfd9 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -1138,7 +1138,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = { .sram_len = SZ_32K, }; -void __init dm365_init_asp(struct snd_platform_data *pdata) +void __init dm365_init_asp(void) { davinci_cfg_reg(DM365_MCBSP0_BDX); davinci_cfg_reg(DM365_MCBSP0_X); @@ -1148,7 +1148,6 @@ void __init dm365_init_asp(struct snd_platform_data *pdata) davinci_cfg_reg(DM365_MCBSP0_BFSR); davinci_cfg_reg(DM365_EVT2_ASP_TX); davinci_cfg_reg(DM365_EVT3_ASP_RX); - dm365_asp_device.dev.platform_data = pdata; platform_device_register(&dm365_asp_device); } diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 0afa279..b437c37 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -921,10 +921,9 @@ static struct davinci_soc_info davinci_soc_info_dm644x = { .sram_len = SZ_16K, }; -void __init dm644x_init_asp(struct snd_platform_data *pdata) +void __init dm644x_init_asp(void) { davinci_cfg_reg(DM644X_MCBSP); - dm644x_asp_device.dev.platform_data = pdata; platform_device_register(&dm644x_asp_device); } diff --git a/arch/arm/mach-davinci/psc.h b/arch/arm/mach-davinci/psc.h index 99d47cf..8af9f09 100644 --- a/arch/arm/mach-davinci/psc.h +++ b/arch/arm/mach-davinci/psc.h @@ -171,6 +171,8 @@ #define DA8XX_LPSC1_I2C 11 #define DA8XX_LPSC1_UART1 12 #define DA8XX_LPSC1_UART2 13 +#define DA850_LPSC1_McBSP0 14 +#define DA850_LPSC1_McBSP1 15 #define DA8XX_LPSC1_LCDC 16 #define DA8XX_LPSC1_PWM 17 #define DA850_LPSC1_MMC_SD1 18 diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c index 7fa176e..1afccae 100644 --- a/arch/arm/mach-imx/avic.c +++ b/arch/arm/mach-imx/avic.c @@ -55,23 +55,20 @@ static void __iomem *avic_base; static struct irq_domain *domain; #ifdef CONFIG_FIQ -static int avic_set_irq_fiq(unsigned int irq, unsigned int type) +static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type) { - struct irq_data *d = irq_get_irq_data(irq); unsigned int irqt; - irq = d->hwirq; - - if (irq >= AVIC_NUM_IRQS) + if (hwirq >= AVIC_NUM_IRQS) return -EINVAL; - if (irq < AVIC_NUM_IRQS / 2) { - irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); - imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); + if (hwirq < AVIC_NUM_IRQS / 2) { + irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq); + imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL); } else { - irq -= AVIC_NUM_IRQS / 2; - irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); - imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); + hwirq -= AVIC_NUM_IRQS / 2; + irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq); + imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH); } return 0; diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c index 353bb87..db0f48c 100644 --- a/arch/arm/mach-imx/cpuidle-imx6q.c +++ b/arch/arm/mach-imx/cpuidle-imx6q.c @@ -10,6 +10,8 @@ #include <linux/module.h> #include <asm/cpuidle.h> +#include <soc/imx/cpuidle.h> + #include "common.h" #include "cpuidle.h" #include "hardware.h" @@ -62,6 +64,24 @@ static struct cpuidle_driver imx6q_cpuidle_driver = { .safe_state_index = 0, }; +/* + * i.MX6 Q/DL has an erratum (ERR006687) that prevents the FEC from waking the + * CPUs when they are in wait(unclocked) state. As the hardware workaround isn't + * applicable to all boards, disable the deeper idle state when the workaround + * isn't present and the FEC is in use. + */ +void imx6q_cpuidle_fec_irqs_used(void) +{ + imx6q_cpuidle_driver.states[1].disabled = true; +} +EXPORT_SYMBOL_GPL(imx6q_cpuidle_fec_irqs_used); + +void imx6q_cpuidle_fec_irqs_unused(void) +{ + imx6q_cpuidle_driver.states[1].disabled = false; +} +EXPORT_SYMBOL_GPL(imx6q_cpuidle_fec_irqs_unused); + int __init imx6q_cpuidle_init(void) { /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ diff --git a/arch/arm/mach-imx/devices/devices.c b/arch/arm/mach-imx/devices/devices.c index 8eab544..3004517 100644 --- a/arch/arm/mach-imx/devices/devices.c +++ b/arch/arm/mach-imx/devices/devices.c @@ -22,6 +22,9 @@ #include <linux/err.h> #include <linux/platform_device.h> +#include "../common.h" +#include "devices-common.h" + struct device mxc_aips_bus = { .init_name = "mxc_aips", }; diff --git a/arch/arm/mach-imx/devices/platform-gpio-mxc.c b/arch/arm/mach-imx/devices/platform-gpio-mxc.c index 26483fa..cd1fe69 100644 --- a/arch/arm/mach-imx/devices/platform-gpio-mxc.c +++ b/arch/arm/mach-imx/devices/platform-gpio-mxc.c @@ -7,6 +7,7 @@ * Free Software Foundation. */ #include "devices-common.h" +#include "../common.h" struct platform_device *__init mxc_register_gpio(char *name, int id, resource_size_t iobase, resource_size_t iosize, int irq, int irq_high) diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c index 0a920d1..210d36e 100644 --- a/arch/arm/mach-imx/irq-common.c +++ b/arch/arm/mach-imx/irq-common.c @@ -33,8 +33,10 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type) gc = irq_get_chip_data(irq); if (gc && gc->private) { exirq = gc->private; - if (exirq->set_irq_fiq) - ret = exirq->set_irq_fiq(irq, type); + if (exirq->set_irq_fiq) { + struct irq_data *d = irq_get_irq_data(irq); + ret = exirq->set_irq_fiq(irqd_to_hwirq(d), type); + } } return ret; diff --git a/arch/arm/mach-imx/mach-imx51.c b/arch/arm/mach-imx/mach-imx51.c index 10a82a4..1e91740 100644 --- a/arch/arm/mach-imx/mach-imx51.c +++ b/arch/arm/mach-imx/mach-imx51.c @@ -54,6 +54,8 @@ static void __init imx51_dt_init(void) imx_src_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + + imx_aips_allow_unprivileged_access("fsl,imx51-aipstz"); } static void __init imx51_init_late(void) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index cb27d56..867121d 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -220,7 +220,7 @@ static void __init imx6q_1588_init(void) IMX6Q_GPR1_ENET_CLK_SEL_MASK, clksel); else - pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); + pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); clk_put(enet_ref); put_ptp_clk: diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index b450f52..36254a6 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -107,6 +107,7 @@ static void __init imx7d_init_irq(void) static const char *const imx7d_dt_compat[] __initconst = { "fsl,imx7d", + "fsl,imx7s", NULL, }; diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c index ae23d50..4399abd 100644 --- a/arch/arm/mach-imx/tzic.c +++ b/arch/arm/mach-imx/tzic.c @@ -56,14 +56,14 @@ static struct irq_domain *domain; #define TZIC_NUM_IRQS 128 #ifdef CONFIG_FIQ -static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) +static int tzic_set_irq_fiq(unsigned int hwirq, unsigned int type) { unsigned int index, mask, value; - index = irq >> 5; + index = hwirq >> 5; if (unlikely(index >= 4)) return -EINVAL; - mask = 1U << (irq & 0x1F); + mask = 1U << (hwirq & 0x1F); value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask; if (type) diff --git a/arch/arm/mach-keystone/pm_domain.c b/arch/arm/mach-keystone/pm_domain.c index e283939..8cbb357 100644 --- a/arch/arm/mach-keystone/pm_domain.c +++ b/arch/arm/mach-keystone/pm_domain.c @@ -18,6 +18,8 @@ #include <linux/platform_device.h> #include <linux/of.h> +#include "keystone.h" + static struct dev_pm_domain keystone_pm_domain = { .ops = { USE_PM_CLK_RUNTIME_OPS diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c index d1f1209..acd6bf0 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq.c +++ b/arch/arm/mach-omap1/ams-delta-fiq.c @@ -136,7 +136,7 @@ void __init ams_delta_init_fiq(void) fiq_buffer[i] = 0; /* - * FIQ mode r9 always points to the fiq_buffer, becauses the FIQ isr + * FIQ mode r9 always points to the fiq_buffer, because the FIQ isr * will run in an unpredictable context. The fiq_buffer is the FIQ isr's * only means of communication with the IRQ level and other kernel * context code. diff --git a/arch/arm/mach-omap1/include/mach/mtd-xip.h b/arch/arm/mach-omap1/include/mach/mtd-xip.h index f82a8dc..d09b2bc 100644 --- a/arch/arm/mach-omap1/include/mach/mtd-xip.h +++ b/arch/arm/mach-omap1/include/mach/mtd-xip.h @@ -39,7 +39,7 @@ static inline unsigned long xip_omap_mpu_timer_read(int nr) #define xip_currtime() (~xip_omap_mpu_timer_read(0)) /* - * It's permitted to do approxmation for xip_elapsed_since macro + * It's permitted to do approximation for xip_elapsed_since macro * (see linux/mtd/xip.h) */ diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 0517f0c..a63d3fe 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -240,4 +240,12 @@ endmenu endif +config OMAP5_ERRATA_801819 + bool "Errata 801819: An eviction from L1 data cache might stall indefinitely" + depends on SOC_OMAP5 || SOC_DRA7XX + help + A livelock can occur in the L2 cache arbitration that might prevent + a snoop from completing. Under certain conditions this can cause the + system to deadlock. + endmenu diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 04e276c..cd820f5 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -8,7 +8,7 @@ ccflags-y := -I$(srctree)/$(src)/include \ # Common support obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \ common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ - omap_device.o sram.o drm.o + omap_device.o omap-headsmp.o sram.o drm.o hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ omap_hwmod_common_data.o @@ -32,7 +32,7 @@ obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o # SMP support ONLY available for OMAP4 -smp-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o +smp-$(CONFIG_SMP) += omap-smp.o smp-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o omap-4-5-common = omap4-common.o omap-wakeupgen.o obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index d9c3ffc..390795b 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -39,7 +39,7 @@ #include "gpmc.h" #include "gpmc-smsc911x.h" -#include <video/omapdss.h> +#include <linux/platform_data/omapdss.h> #include <video/omap-panel-data.h> #include "board-flash.h" @@ -47,6 +47,7 @@ #include "hsmmc.h" #include "control.h" #include "common-board-devices.h" +#include "display.h" #define LDP_SMSC911X_CS 1 #define LDP_SMSC911X_GPIO 152 diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index 9cfebc5..180c6aa 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c @@ -15,13 +15,14 @@ #include <linux/spi/spi.h> #include <linux/mm.h> #include <asm/mach-types.h> -#include <video/omapdss.h> +#include <linux/platform_data/omapdss.h> #include <video/omap-panel-data.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include "soc.h" #include "board-rx51.h" +#include "display.h" #include "mux.h" @@ -32,7 +33,6 @@ static struct connector_atv_platform_data rx51_tv_pdata = { .name = "tv", .source = "venc.0", - .connector_type = OMAP_DSS_VENC_TYPE_COMPOSITE, .invert_polarity = false, }; diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c index 187fa43..d91ae82 100644 --- a/arch/arm/mach-omap2/cm3xxx.c +++ b/arch/arm/mach-omap2/cm3xxx.c @@ -649,7 +649,7 @@ void omap3_cm_save_scratchpad_contents(u32 *ptr) /* * As per erratum i671, ROM code does not respect the PER DPLL * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1. - * Then, in anycase, clear these bits to avoid extra latencies. + * Then, in any case, clear these bits to avoid extra latencies. */ *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) & ~OMAP3430_AUTO_PERIPH_DPLL_MASK; diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index f7666b9..deed42e 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -257,18 +257,22 @@ extern void gic_dist_enable(void); extern bool gic_dist_disabled(void); extern void gic_timer_retrigger(void); extern void omap_smc1(u32 fn, u32 arg); +extern void omap4_sar_ram_init(void); extern void __iomem *omap4_get_sar_ram_base(void); +extern void omap4_mpuss_early_init(void); extern void omap_do_wfi(void); -#ifdef CONFIG_SMP -/* Needed for secondary core boot */ extern void omap4_secondary_startup(void); extern void omap4460_secondary_startup(void); + +#ifdef CONFIG_SMP +/* Needed for secondary core boot */ extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); extern void omap_auxcoreboot_addr(u32 cpu_addr); extern u32 omap_read_auxcoreboot0(void); extern void omap4_cpu_die(unsigned int cpu); +extern int omap4_cpu_kill(unsigned int cpu); extern const struct smp_operations omap4_smp_ops; diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 6ab13d1..70b3eaf 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -29,7 +29,7 @@ #include <linux/mfd/syscon.h> #include <linux/regmap.h> -#include <video/omapdss.h> +#include <linux/platform_data/omapdss.h> #include "omap_hwmod.h" #include "omap_device.h" #include "omap-pm.h" diff --git a/arch/arm/mach-omap2/display.h b/arch/arm/mach-omap2/display.h index 7375854..78f2530 100644 --- a/arch/arm/mach-omap2/display.h +++ b/arch/arm/mach-omap2/display.h @@ -33,4 +33,9 @@ int omap_init_vout(void); struct device_node * __init omapdss_find_dss_of_node(void); +struct omap_dss_board_info; + +/* Init with the board info */ +int omap_display_init(struct omap_dss_board_info *board_data); + #endif diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c index ea2be0f..1d583bc 100644 --- a/arch/arm/mach-omap2/dss-common.c +++ b/arch/arm/mach-omap2/dss-common.c @@ -27,7 +27,7 @@ #include <linux/gpio.h> #include <linux/platform_device.h> -#include <video/omapdss.h> +#include <linux/platform_data/omapdss.h> #include <video/omap-panel-data.h> #include "soc.h" diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 49de4dd..0e9acdd 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -690,6 +690,8 @@ void __init omap4430_init_early(void) omap4xxx_check_revision(); omap4xxx_check_features(); omap2_prcm_base_init(); + omap4_sar_ram_init(); + omap4_mpuss_early_init(); omap4_pm_init_early(); omap44xx_voltagedomains_init(); omap44xx_powerdomains_init(); @@ -718,6 +720,7 @@ void __init omap5_init_early(void) omap4_pm_init_early(); omap2_prcm_base_init(); omap5xxx_check_revision(); + omap4_sar_ram_init(); omap54xx_voltagedomains_init(); omap54xx_powerdomains_init(); omap54xx_clockdomains_init(); diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index b4ac3af..fc04be7 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -34,18 +34,24 @@ #include "cm3xxx.h" #include "cm-regbits-34xx.h" -static struct clk *mcbsp_iclks[5]; - -static int omap3_enable_st_clock(unsigned int id, bool enable) +static int omap3_mcbsp_force_ick_on(struct clk *clk, bool force_on) { - /* - * Sidetone uses McBSP ICLK - which must not idle when sidetones - * are enabled or sidetones start sounding ugly. - */ - if (enable) - return omap2_clk_deny_idle(mcbsp_iclks[id]); + if (!clk) + return 0; + + if (force_on) + return omap2_clk_deny_idle(clk); else - return omap2_clk_allow_idle(mcbsp_iclks[id]); + return omap2_clk_allow_idle(clk); +} + +void __init omap3_mcbsp_init_pdata_callback( + struct omap_mcbsp_platform_data *pdata) +{ + if (!pdata) + return; + + pdata->force_ick_on = omap3_mcbsp_force_ick_on; } static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) @@ -55,7 +61,6 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) struct omap_hwmod *oh_device[2]; struct omap_mcbsp_platform_data *pdata = NULL; struct platform_device *pdev; - char clk_name[11]; sscanf(oh->name, "mcbsp%d", &id); @@ -96,9 +101,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) if (oh->dev_attr) { oh_device[1] = omap_hwmod_lookup(( (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); - pdata->enable_st_clock = omap3_enable_st_clock; - sprintf(clk_name, "mcbsp%d_ick", id); - mcbsp_iclks[id] = clk_get(NULL, clk_name); + pdata->force_ick_on = omap3_mcbsp_force_ick_on; count++; } pdev = omap_device_build_ss(name, id, oh_device, count, pdata, diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index be271f1..393e687 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c @@ -1266,7 +1266,7 @@ static struct omap_ball __initdata omap3_cus_ball[] = { #endif /* - * Signals different on CBB package comapared to superset + * Signals different on CBB package compared to superset */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB) static struct omap_mux __initdata omap3_cbb_subset[] = { @@ -1597,7 +1597,7 @@ static struct omap_ball __initdata omap3_cbb_ball[] = { #endif /* - * Signals different on 36XX CBP package comapared to 34XX CBC package + * Signals different on 36XX CBP package compared to 34XX CBC package */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP) static struct omap_mux __initdata omap36xx_cbp_subset[] = { diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 6d1dffc..fe36ce2 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -24,6 +24,16 @@ #define AUX_CORE_BOOT0_PA 0x48281800 #define API_HYP_ENTRY 0x102 +ENTRY(omap_secondary_startup) +#ifdef CONFIG_SMP + b secondary_startup +#else +/* Should never get here */ +again: wfi + b again +#endif +#ENDPROC(omap_secondary_startup) + /* * OMAP5 specific entry point for secondary CPU to jump from ROM * code. This routine also provides a holding flag into which @@ -39,7 +49,7 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 and r4, r4, #0x0f cmp r0, r4 bne wait - b secondary_startup + b omap_secondary_startup ENDPROC(omap5_secondary_startup) /* * Same as omap5_secondary_startup except we call into the ROM to @@ -59,7 +69,7 @@ wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 adr r0, hyp_boot smc #0 hyp_boot: - b secondary_startup + b omap_secondary_startup ENDPROC(omap5_secondary_hyp_startup) /* * OMAP4 specific entry point for secondary CPU to jump from ROM @@ -82,7 +92,7 @@ hold: ldr r12,=0x103 * we've been released from the wait loop,secondary_stack * should now contain the SVC stack for this core */ - b secondary_startup + b omap_secondary_startup ENDPROC(omap4_secondary_startup) ENTRY(omap4460_secondary_startup) @@ -119,5 +129,5 @@ hold_2: ldr r12,=0x103 * we've been released from the wait loop,secondary_stack * should now contain the SVC stack for this core */ - b secondary_startup + b omap_secondary_startup ENDPROC(omap4460_secondary_startup) diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c index 593fec7..d3fb566 100644 --- a/arch/arm/mach-omap2/omap-hotplug.c +++ b/arch/arm/mach-omap2/omap-hotplug.c @@ -64,3 +64,9 @@ void omap4_cpu_die(unsigned int cpu) pr_debug("CPU%u: spurious wakeup call\n", cpu); } } + +/* Needed by kexec and platform_can_cpu_hotplug() */ +int omap4_cpu_kill(unsigned int cpu) +{ + return 1; +} diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index 65024af..1751517 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -62,6 +62,8 @@ #include "prm44xx.h" #include "prm-regbits-44xx.h" +static void __iomem *sar_base; + #ifdef CONFIG_SMP struct omap4_cpu_pm_info { @@ -90,7 +92,6 @@ struct cpu_pm_ops { static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); static struct powerdomain *mpuss_pd; -static void __iomem *sar_base; static u32 cpu_context_offset; static int default_finish_suspend(unsigned long cpu_state) @@ -366,9 +367,6 @@ int __init omap4_mpuss_init(void) return -ENODEV; } - if (cpu_is_omap44xx()) - sar_base = omap4_get_sar_ram_base(); - /* Initilaise per CPU PM information */ pm_info = &per_cpu(omap4_pm_info, 0x0); if (sar_base) { @@ -444,3 +442,26 @@ int __init omap4_mpuss_init(void) } #endif + +/* + * For kexec, we must set CPU1_WAKEUP_NS_PA_ADDR to point to + * current kernel's secondary_startup() early before + * clockdomains_init(). Otherwise clockdomain_init() can + * wake CPU1 and cause a hang. + */ +void __init omap4_mpuss_early_init(void) +{ + unsigned long startup_pa; + + if (!cpu_is_omap44xx()) + return; + + sar_base = omap4_get_sar_ram_base(); + + if (cpu_is_omap443x()) + startup_pa = virt_to_phys(omap4_secondary_startup); + else + startup_pa = virt_to_phys(omap4460_secondary_startup); + + writel_relaxed(startup_pa, sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET); +} diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index af2851f..bae263f 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -46,6 +46,7 @@ #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 #define OMAP5_MON_AMBA_IF_INDEX 0x108 +#define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107 /* Secure PPA(Primary Protected Application) APIs */ #define OMAP4_PPA_L2_POR_INDEX 0x23 diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index c625cc1..d53a0de 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -40,16 +40,70 @@ #define OMAP5_CORE_COUNT 0x2 -/* SCU base address */ -static void __iomem *scu_base; +struct omap_smp_config { + unsigned long cpu1_rstctrl_pa; + void __iomem *cpu1_rstctrl_va; + void __iomem *scu_base; + void *startup_addr; +}; + +static struct omap_smp_config cfg; + +static const struct omap_smp_config omap443x_cfg __initconst = { + .cpu1_rstctrl_pa = 0x4824380c, + .startup_addr = omap4_secondary_startup, +}; + +static const struct omap_smp_config omap446x_cfg __initconst = { + .cpu1_rstctrl_pa = 0x4824380c, + .startup_addr = omap4460_secondary_startup, +}; + +static const struct omap_smp_config omap5_cfg __initconst = { + .cpu1_rstctrl_pa = 0x48243810, + .startup_addr = omap5_secondary_startup, +}; static DEFINE_SPINLOCK(boot_lock); void __iomem *omap4_get_scu_base(void) { - return scu_base; + return cfg.scu_base; } +#ifdef CONFIG_OMAP5_ERRATA_801819 +void omap5_erratum_workaround_801819(void) +{ + u32 acr, revidr; + u32 acr_mask; + + /* REVIDR[3] indicates erratum fix available on silicon */ + asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr)); + if (revidr & (0x1 << 3)) + return; + + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + /* + * BIT(27) - Disables streaming. All write-allocate lines allocate in + * the L1 or L2 cache. + * BIT(25) - Disables streaming. All write-allocate lines allocate in + * the L1 cache. + */ + acr_mask = (0x3 << 25) | (0x3 << 27); + /* do we already have it done.. if yes, skip expensive smc */ + if ((acr & acr_mask) == acr_mask) + return; + + acr |= acr_mask; + omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr); + + pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n", + __func__, smp_processor_id()); +} +#else +static inline void omap5_erratum_workaround_801819(void) { } +#endif + static void omap4_secondary_init(unsigned int cpu) { /* @@ -60,16 +114,19 @@ static void omap4_secondary_init(unsigned int cpu) * OMAP443X GP devices- SMP bit isn't accessible. * OMAP446X GP devices - SMP bit access is enabled on both CPUs. */ - if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) + if (soc_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, 4, 0, 0, 0, 0, 0); - /* - * Configure the CNTFRQ register for the secondary cpu's which - * indicates the frequency of the cpu local timers. - */ - if (soc_is_omap54xx() || soc_is_dra7xx()) + if (soc_is_omap54xx() || soc_is_dra7xx()) { + /* + * Configure the CNTFRQ register for the secondary cpu's which + * indicates the frequency of the cpu local timers. + */ set_cntfreq(); + /* Configure ACR to disable streaming WA for 801819 */ + omap5_erratum_workaround_801819(); + } /* * Synchronise with the boot thread. @@ -186,9 +243,9 @@ static void __init omap4_smp_init_cpus(void) * Currently we can't call ioremap here because * SoC detection won't work until after init_early. */ - scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base()); - BUG_ON(!scu_base); - ncores = scu_get_core_count(scu_base); + cfg.scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base()); + BUG_ON(!cfg.scu_base); + ncores = scu_get_core_count(cfg.scu_base); } else if (cpu_id == CPU_CORTEX_A15) { ncores = OMAP5_CORE_COUNT; } @@ -206,18 +263,51 @@ static void __init omap4_smp_init_cpus(void) static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) { - void *startup_addr = omap4_secondary_startup; void __iomem *base = omap_get_wakeupgen_base(); + const struct omap_smp_config *c = NULL; + + if (soc_is_omap443x()) + c = &omap443x_cfg; + else if (soc_is_omap446x()) + c = &omap446x_cfg; + else if (soc_is_dra74x() || soc_is_omap54xx()) + c = &omap5_cfg; + + if (!c) { + pr_err("%s Unknown SMP SoC?\n", __func__); + return; + } + + /* Must preserve cfg.scu_base set earlier */ + cfg.cpu1_rstctrl_pa = c->cpu1_rstctrl_pa; + cfg.startup_addr = c->startup_addr; + + if (soc_is_dra74x() || soc_is_omap54xx()) { + if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE) + cfg.startup_addr = omap5_secondary_hyp_startup; + omap5_erratum_workaround_801819(); + } + + cfg.cpu1_rstctrl_va = ioremap(cfg.cpu1_rstctrl_pa, 4); + if (!cfg.cpu1_rstctrl_va) + return; /* * Initialise the SCU and wake up the secondary core using * wakeup_secondary(). */ - if (scu_base) - scu_enable(scu_base); + if (cfg.scu_base) + scu_enable(cfg.scu_base); - if (cpu_is_omap446x()) - startup_addr = omap4460_secondary_startup; + /* + * Reset CPU1 before configuring, otherwise kexec will + * end up trying to use old kernel startup address. + */ + if (cfg.cpu1_rstctrl_va) { + writel_relaxed(1, cfg.cpu1_rstctrl_va); + readl_relaxed(cfg.cpu1_rstctrl_va); + writel_relaxed(0, cfg.cpu1_rstctrl_va); + } /* * Write the address of secondary startup routine into the @@ -226,19 +316,10 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) * A barrier is added to ensure that write buffer is drained */ if (omap_secure_apis_support()) - omap_auxcoreboot_addr(virt_to_phys(startup_addr)); + omap_auxcoreboot_addr(virt_to_phys(cfg.startup_addr)); else - /* - * If the boot CPU is in HYP mode then start secondary - * CPU in HYP mode as well. - */ - if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE) - writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup), - base + OMAP_AUX_CORE_BOOT_1); - else - writel_relaxed(virt_to_phys(omap5_secondary_startup), - base + OMAP_AUX_CORE_BOOT_1); - + writel_relaxed(virt_to_phys(cfg.startup_addr), + base + OMAP_AUX_CORE_BOOT_1); } const struct smp_operations omap4_smp_ops __initconst = { @@ -248,5 +329,6 @@ const struct smp_operations omap4_smp_ops __initconst = { .smp_boot_secondary = omap4_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = omap4_cpu_die, + .cpu_kill = omap4_cpu_kill, #endif }; diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 949696b..cf65ab8 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -61,7 +61,7 @@ static phys_addr_t dram_sync_paddr; static u32 dram_sync_size; /* - * The OMAP4 bus structure contains asynchrnous bridges which can buffer + * The OMAP4 bus structure contains asynchronous bridges which can buffer * data writes from the MPU. These asynchronous bridges can be found on * paths between the MPU to EMIF, and the MPU to L3 interconnects. * @@ -266,10 +266,11 @@ void __iomem *omap4_get_sar_ram_base(void) } /* - * SAR RAM used to save and restore the HW - * context in low power modes + * SAR RAM used to save and restore the HW context in low power modes. + * Note that we need to initialize this very early for kexec. See + * omap4_mpuss_early_init(). */ -static int __init omap4_sar_ram_init(void) +void __init omap4_sar_ram_init(void) { unsigned long sar_base; @@ -282,16 +283,13 @@ static int __init omap4_sar_ram_init(void) else if (soc_is_omap54xx()) sar_base = OMAP54XX_SAR_RAM_BASE; else - return -ENOMEM; + return; /* Static mapping, never released */ sar_ram_base = ioremap(sar_base, SZ_16K); if (WARN_ON(!sar_ram_base)) - return -ENOMEM; - - return 0; + return; } -omap_early_initcall(omap4_sar_ram_init); static const struct of_device_id intc_match[] = { { .compatible = "ti,omap4-wugen-mpu", }, diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index f7ff3b9..a7be05d 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -268,7 +268,7 @@ static int _omap_device_idle_hwmods(struct omap_device *od) * function returns a value different than the value the caller got * the last time it called this function. * - * If any hwmods exist for the omap_device assoiated with @pdev, + * If any hwmods exist for the omap_device associated with @pdev, * return the context loss counter for that hwmod, otherwise return * zero. */ diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h index 7f73796..d3e61d1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h @@ -36,17 +36,8 @@ extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio3; extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio; extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm; extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0; -extern struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0; -extern struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0; -extern struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0; extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1; -extern struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1; -extern struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1; -extern struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1; extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2; -extern struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2; -extern struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2; -extern struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2; extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc; extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c2; extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c3; @@ -98,17 +89,8 @@ extern struct omap_hwmod am33xx_dcan0_hwmod; extern struct omap_hwmod am33xx_dcan1_hwmod; extern struct omap_hwmod am33xx_elm_hwmod; extern struct omap_hwmod am33xx_epwmss0_hwmod; -extern struct omap_hwmod am33xx_ecap0_hwmod; -extern struct omap_hwmod am33xx_eqep0_hwmod; -extern struct omap_hwmod am33xx_ehrpwm0_hwmod; extern struct omap_hwmod am33xx_epwmss1_hwmod; -extern struct omap_hwmod am33xx_ecap1_hwmod; -extern struct omap_hwmod am33xx_eqep1_hwmod; -extern struct omap_hwmod am33xx_ehrpwm1_hwmod; extern struct omap_hwmod am33xx_epwmss2_hwmod; -extern struct omap_hwmod am33xx_ecap2_hwmod; -extern struct omap_hwmod am33xx_eqep2_hwmod; -extern struct omap_hwmod am33xx_ehrpwm2_hwmod; extern struct omap_hwmod am33xx_gpio1_hwmod; extern struct omap_hwmod am33xx_gpio2_hwmod; extern struct omap_hwmod am33xx_gpio3_hwmod; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c index 1c210cb..10dff2f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c @@ -176,28 +176,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { .user = OCP_USER_MPU, }; -struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { - .master = &am33xx_epwmss0_hwmod, - .slave = &am33xx_ecap0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { - .master = &am33xx_epwmss0_hwmod, - .slave = &am33xx_eqep0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { - .master = &am33xx_epwmss0_hwmod, - .slave = &am33xx_ehrpwm0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - - static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = { { .pa_start = 0x48302000, @@ -215,27 +193,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { .user = OCP_USER_MPU, }; -struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { - .master = &am33xx_epwmss1_hwmod, - .slave = &am33xx_ecap1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { - .master = &am33xx_epwmss1_hwmod, - .slave = &am33xx_eqep1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { - .master = &am33xx_epwmss1_hwmod, - .slave = &am33xx_ehrpwm1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = { { .pa_start = 0x48304000, @@ -253,27 +210,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { .user = OCP_USER_MPU, }; -struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { - .master = &am33xx_epwmss2_hwmod, - .slave = &am33xx_ecap2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { - .master = &am33xx_epwmss2_hwmod, - .slave = &am33xx_eqep2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { - .master = &am33xx_epwmss2_hwmod, - .slave = &am33xx_ehrpwm2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - /* l3s cfg -> gpmc */ struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { .master = &am33xx_l3_s_hwmod, diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index aed3362..55c5878 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -449,18 +449,6 @@ struct omap_hwmod_class am33xx_epwmss_hwmod_class = { .sysc = &am33xx_epwmss_sysc, }; -static struct omap_hwmod_class am33xx_ecap_hwmod_class = { - .name = "ecap", -}; - -static struct omap_hwmod_class am33xx_eqep_hwmod_class = { - .name = "eqep", -}; - -struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = { - .name = "ehrpwm", -}; - /* epwmss0 */ struct omap_hwmod am33xx_epwmss0_hwmod = { .name = "epwmss0", @@ -474,30 +462,6 @@ struct omap_hwmod am33xx_epwmss0_hwmod = { }, }; -/* ecap0 */ -struct omap_hwmod am33xx_ecap0_hwmod = { - .name = "ecap0", - .class = &am33xx_ecap_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* eqep0 */ -struct omap_hwmod am33xx_eqep0_hwmod = { - .name = "eqep0", - .class = &am33xx_eqep_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* ehrpwm0 */ -struct omap_hwmod am33xx_ehrpwm0_hwmod = { - .name = "ehrpwm0", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - /* epwmss1 */ struct omap_hwmod am33xx_epwmss1_hwmod = { .name = "epwmss1", @@ -511,30 +475,6 @@ struct omap_hwmod am33xx_epwmss1_hwmod = { }, }; -/* ecap1 */ -struct omap_hwmod am33xx_ecap1_hwmod = { - .name = "ecap1", - .class = &am33xx_ecap_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* eqep1 */ -struct omap_hwmod am33xx_eqep1_hwmod = { - .name = "eqep1", - .class = &am33xx_eqep_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* ehrpwm1 */ -struct omap_hwmod am33xx_ehrpwm1_hwmod = { - .name = "ehrpwm1", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - /* epwmss2 */ struct omap_hwmod am33xx_epwmss2_hwmod = { .name = "epwmss2", @@ -548,30 +488,6 @@ struct omap_hwmod am33xx_epwmss2_hwmod = { }, }; -/* ecap2 */ -struct omap_hwmod am33xx_ecap2_hwmod = { - .name = "ecap2", - .class = &am33xx_ecap_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* eqep2 */ -struct omap_hwmod am33xx_eqep2_hwmod = { - .name = "eqep2", - .class = &am33xx_eqep_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* ehrpwm2 */ -struct omap_hwmod am33xx_ehrpwm2_hwmod = { - .name = "ehrpwm2", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - /* * 'gpio' class: for gpio 0,1,2,3 */ @@ -1476,6 +1392,7 @@ static void omap_hwmod_am43xx_rst(void) { RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET); RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET); + RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET); RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET); } diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index cc0791d..e1c2025 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -593,17 +593,8 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_ls__spinlock, &am33xx_l4_ls__elm, &am33xx_l4_ls__epwmss0, - &am33xx_epwmss0__ecap0, - &am33xx_epwmss0__eqep0, - &am33xx_epwmss0__ehrpwm0, &am33xx_l4_ls__epwmss1, - &am33xx_epwmss1__ecap1, - &am33xx_epwmss1__eqep1, - &am33xx_epwmss1__ehrpwm1, &am33xx_l4_ls__epwmss2, - &am33xx_epwmss2__ecap2, - &am33xx_epwmss2__eqep2, - &am33xx_epwmss2__ehrpwm2, &am33xx_l3_s__gpmc, &am33xx_l3_main__lcdc, &am33xx_l4_ls__mcspi0, diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 9869a75..d72ee61 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1322,16 +1322,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { .name = "mcbsp2_sidetone", .class = &omap3xxx_mcbsp_sidetone_hwmod_class, .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, - .main_clk = "mcbsp2_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP2_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, - }, - }, + .main_clk = "mcbsp2_ick", + .flags = HWMOD_NO_IDLEST, }; /* mcbsp3_sidetone */ @@ -1344,16 +1336,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { .name = "mcbsp3_sidetone", .class = &omap3xxx_mcbsp_sidetone_hwmod_class, .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, - .main_clk = "mcbsp3_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP3_SHIFT, - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, - }, - }, + .main_clk = "mcbsp3_ick", + .flags = HWMOD_NO_IDLEST, }; /* SR common */ diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index 97fd399..61f2f30 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -202,13 +202,6 @@ static struct omap_hwmod am43xx_epwmss3_hwmod = { }, }; -static struct omap_hwmod am43xx_ehrpwm3_hwmod = { - .name = "ehrpwm3", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - static struct omap_hwmod am43xx_epwmss4_hwmod = { .name = "epwmss4", .class = &am33xx_epwmss_hwmod_class, @@ -222,13 +215,6 @@ static struct omap_hwmod am43xx_epwmss4_hwmod = { }, }; -static struct omap_hwmod am43xx_ehrpwm4_hwmod = { - .name = "ehrpwm4", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - static struct omap_hwmod am43xx_epwmss5_hwmod = { .name = "epwmss5", .class = &am33xx_epwmss_hwmod_class, @@ -242,13 +228,6 @@ static struct omap_hwmod am43xx_epwmss5_hwmod = { }, }; -static struct omap_hwmod am43xx_ehrpwm5_hwmod = { - .name = "ehrpwm5", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - static struct omap_hwmod am43xx_spi2_hwmod = { .name = "spi2", .class = &am33xx_spi_hwmod_class, @@ -744,13 +723,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = { - .master = &am43xx_epwmss3_hwmod, - .slave = &am43xx_ehrpwm3_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = { .master = &am33xx_l4_ls_hwmod, .slave = &am43xx_epwmss4_hwmod, @@ -758,13 +730,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = { - .master = &am43xx_epwmss4_hwmod, - .slave = &am43xx_ehrpwm4_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = { .master = &am33xx_l4_ls_hwmod, .slave = &am43xx_epwmss5_hwmod, @@ -772,13 +737,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = { - .master = &am43xx_epwmss5_hwmod, - .slave = &am43xx_ehrpwm5_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = { .master = &am33xx_l4_ls_hwmod, .slave = &am43xx_spi2_hwmod, @@ -919,11 +877,8 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am43xx_l4_ls__timer10, &am43xx_l4_ls__timer11, &am43xx_l4_ls__epwmss3, - &am43xx_epwmss3__ehrpwm3, &am43xx_l4_ls__epwmss4, - &am43xx_epwmss4__ehrpwm4, &am43xx_l4_ls__epwmss5, - &am43xx_epwmss5__ehrpwm5, &am43xx_l4_ls__mcspi2, &am43xx_l4_ls__mcspi3, &am43xx_l4_ls__mcspi4, @@ -982,17 +937,8 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_ls__spinlock, &am33xx_l4_ls__elm, &am33xx_l4_ls__epwmss0, - &am33xx_epwmss0__ecap0, - &am33xx_epwmss0__eqep0, - &am33xx_epwmss0__ehrpwm0, &am33xx_l4_ls__epwmss1, - &am33xx_epwmss1__ecap1, - &am33xx_epwmss1__eqep1, - &am33xx_epwmss1__ehrpwm1, &am33xx_l4_ls__epwmss2, - &am33xx_epwmss2__ecap2, - &am33xx_epwmss2__eqep2, - &am33xx_epwmss2__ehrpwm2, &am33xx_l3_s__gpmc, &am33xx_l4_ls__mcspi0, &am33xx_l4_ls__mcspi1, diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index d0e7e525..1ab7096 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -2905,58 +2905,27 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = { - { - .name = "family", - .pa_start = 0x58000000, - .pa_end = 0x5800007f, - .flags = ADDR_TYPE_RT - }, -}; - /* l3_main_1 -> dss */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = { .master = &dra7xx_l3_main_1_hwmod, .slave = &dra7xx_dss_hwmod, .clk = "l3_iclk_div", - .addr = dra7xx_dss_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = { - { - .name = "dispc", - .pa_start = 0x58001000, - .pa_end = 0x58001fff, - .flags = ADDR_TYPE_RT - }, -}; - /* l3_main_1 -> dispc */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = { .master = &dra7xx_l3_main_1_hwmod, .slave = &dra7xx_dss_dispc_hwmod, .clk = "l3_iclk_div", - .addr = dra7xx_dss_dispc_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = { - { - .name = "hdmi_wp", - .pa_start = 0x58040000, - .pa_end = 0x580400ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_1 -> dispc */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = { .master = &dra7xx_l3_main_1_hwmod, .slave = &dra7xx_dss_hdmi_hwmod, .clk = "l3_iclk_div", - .addr = dra7xx_dss_hdmi_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -3410,21 +3379,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { - { - .pa_start = 0x4b300000, - .pa_end = 0x4b30007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_1 -> qspi */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = { .master = &dra7xx_l3_main_1_hwmod, .slave = &dra7xx_qspi_hwmod, .clk = "l3_iclk_div", - .addr = dra7xx_qspi_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index df83277..b82b77c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -243,7 +243,7 @@ static struct omap_hwmod_class ti81xx_rtc_hwmod_class = { .sysc = &ti81xx_rtc_sysc, }; -struct omap_hwmod ti81xx_rtc_hwmod = { +static struct omap_hwmod ti81xx_rtc_hwmod = { .name = "rtc", .class = &ti81xx_rtc_hwmod_class, .clkdm_name = "alwon_l3s_clkdm", diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 6571ad9..ab2b2b2 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -26,6 +26,7 @@ #include <linux/platform_data/wkup_m3.h> #include <linux/platform_data/pwm_omap_dmtimer.h> #include <linux/platform_data/media/ir-rx51.h> +#include <linux/platform_data/asoc-ti-mcbsp.h> #include <plat/dmtimer.h> #include "common.h" @@ -505,6 +506,16 @@ static struct platform_device __maybe_unused rx51_lirc_device = { }, }; +#if IS_ENABLED(CONFIG_SND_OMAP_SOC_MCBSP) +static struct omap_mcbsp_platform_data mcbsp_pdata; +static void __init omap3_mcbsp_init(void) +{ + omap3_mcbsp_init_pdata_callback(&mcbsp_pdata); +} +#else +static void __init omap3_mcbsp_init(void) {} +#endif + /* * Few boards still need auxdata populated before we populate * the dev entries in of_platform_populate(). @@ -536,6 +547,11 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL), OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0", &am35xx_emac_pdata), + /* McBSP modules with sidetone core */ +#if IS_ENABLED(CONFIG_SND_OMAP_SOC_MCBSP) + OF_DEV_AUXDATA("ti,omap3-mcbsp", 0x49022000, "49022000.mcbsp", &mcbsp_pdata), + OF_DEV_AUXDATA("ti,omap3-mcbsp", 0x49024000, "49024000.mcbsp", &mcbsp_pdata), +#endif #endif #ifdef CONFIG_SOC_AM33XX OF_DEV_AUXDATA("ti,am3352-wkup-m3", 0x44d00000, "44d00000.wkup_m3", @@ -608,6 +624,8 @@ void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table) of_machine_is_compatible("ti,omap3")) omap_sdrc_init(NULL, NULL); + if (of_machine_is_compatible("ti,omap3")) + omap3_mcbsp_init(); pdata_quirks_check(auxdata_quirks); of_platform_populate(NULL, omap_dt_match_table, omap_auxdata_lookup, NULL); diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h index 7c34c44e..babb5db 100644 --- a/arch/arm/mach-omap2/prcm43xx.h +++ b/arch/arm/mach-omap2/prcm43xx.h @@ -39,6 +39,7 @@ /* RM RSTST offsets */ #define AM43XX_RM_GFX_RSTST_OFFSET 0x0014 +#define AM43XX_RM_PER_RSTST_OFFSET 0x0014 #define AM43XX_RM_WKUP_RSTST_OFFSET 0x0014 /* CM instances */ diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h index 2bc4ec5..66302c6 100644 --- a/arch/arm/mach-omap2/prm33xx.h +++ b/arch/arm/mach-omap2/prm33xx.h @@ -52,8 +52,6 @@ /* PRM.PER_PRM register offsets */ #define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000 #define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000) -#define AM33XX_RM_PER_RSTST_OFFSET 0x0004 -#define AM33XX_RM_PER_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004) #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008 #define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008) #define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h index 645a2a4..f115006 100644 --- a/arch/arm/mach-omap2/sdrc.h +++ b/arch/arm/mach-omap2/sdrc.h @@ -175,8 +175,8 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); * don't adjust it down as your clock period increases the refresh interval * will not be met. Setting all parameters for complete worst case may work, * but may cut memory performance by 2x. Due to errata the DLLs need to be - * unlocked and their value needs run time calibration. A dynamic call is - * need for that as no single right value exists acorss production samples. + * unlocked and their value needs run time calibration. A dynamic call is + * need for that as no single right value exists across production samples. * * Only the FULL speed values are given. Current code is such that rate * changes must be made at DPLLoutx2. The actual value adjustment for low diff --git a/arch/arm/mach-oxnas/Kconfig b/arch/arm/mach-oxnas/Kconfig index 4fff3c7..19164d7 100644 --- a/arch/arm/mach-oxnas/Kconfig +++ b/arch/arm/mach-oxnas/Kconfig @@ -11,10 +11,10 @@ if ARCH_OXNAS config MACH_OX810SE bool "Support OX810SE Based Products" - select ARM_TIMER_SP804 select COMMON_CLK_OXNAS select CPU_ARM926T select MFD_SYSCON + select OXNAS_RPS_TIMER select PINCTRL_OXNAS select RESET_OXNAS select VERSATILE_FPGA_IRQ diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig index 7349450..46ed10a 100644 --- a/arch/arm/mach-qcom/Kconfig +++ b/arch/arm/mach-qcom/Kconfig @@ -23,4 +23,8 @@ config ARCH_MSM8974 bool "Enable support for MSM8974" select HAVE_ARM_ARCH_TIMER +config ARCH_MDM9615 + bool "Enable support for MDM9615" + select CLKSRC_QCOM + endif diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c index 6d8bbf7..d8060df 100644 --- a/arch/arm/mach-qcom/board.c +++ b/arch/arm/mach-qcom/board.c @@ -22,6 +22,7 @@ static const char * const qcom_dt_match[] __initconst = { "qcom,ipq8064", "qcom,msm8660-surf", "qcom,msm8960-cdp", + "qcom,mdm9615", NULL }; diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c index 691ac16..61361da 100644 --- a/arch/arm/mach-shmobile/pm-rcar-gen2.c +++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c @@ -26,8 +26,7 @@ #define CA7RESCNT 0x0044 /* On-chip RAM */ -#define MERAM 0xe8080000 -#define RAM 0xe6300000 +#define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */ /* SYSC */ #define SYSCIER 0x0c @@ -58,7 +57,7 @@ void __init rcar_gen2_pm_init(void) struct device_node *np, *cpus; bool has_a7 = false; bool has_a15 = false; - phys_addr_t boot_vector_addr = 0; + phys_addr_t boot_vector_addr = ICRAM1; u32 syscier = 0; if (once++) @@ -75,14 +74,10 @@ void __init rcar_gen2_pm_init(void) has_a7 = true; } - if (of_machine_is_compatible("renesas,r8a7790")) { - boot_vector_addr = MERAM; + if (of_machine_is_compatible("renesas,r8a7790")) syscier = 0x013111ef; - - } else if (of_machine_is_compatible("renesas,r8a7791")) { - boot_vector_addr = RAM; + else if (of_machine_is_compatible("renesas,r8a7791")) syscier = 0x00111003; - } /* RAM for jump stub, because BAR requires 256KB aligned address */ p = ioremap_nocache(boot_vector_addr, shmobile_boot_size); diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c index c0b05e9..45a1955 100644 --- a/arch/arm/mach-shmobile/pm-rmobile.c +++ b/arch/arm/mach-shmobile/pm-rmobile.c @@ -131,13 +131,13 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd) struct dev_power_governor *gov = rmobile_pd->gov; genpd->flags = GENPD_FLAG_PM_CLK; - pm_genpd_init(genpd, gov ? : &simple_qos_governor, false); genpd->dev_ops.active_wakeup = rmobile_pd_active_wakeup; genpd->power_off = rmobile_pd_power_down; genpd->power_on = rmobile_pd_power_up; genpd->attach_dev = cpg_mstp_attach_dev; genpd->detach_dev = cpg_mstp_detach_dev; __rmobile_pd_power_up(rmobile_pd, false); + pm_genpd_init(genpd, gov ? : &simple_qos_governor, false); } static int rmobile_pd_suspend_busy(void) diff --git a/arch/arm/mach-tango/platsmp.c b/arch/arm/mach-tango/platsmp.c index a21f55e..8380699 100644 --- a/arch/arm/mach-tango/platsmp.c +++ b/arch/arm/mach-tango/platsmp.c @@ -1,3 +1,4 @@ +#include <linux/delay.h> #include <linux/init.h> #include <linux/smp.h> #include "smc.h" @@ -9,8 +10,43 @@ static int tango_boot_secondary(unsigned int cpu, struct task_struct *idle) return 0; } +#ifdef CONFIG_HOTPLUG_CPU +/* + * cpu_kill() and cpu_die() run concurrently on different cores. + * Firmware will only "kill" a core once it has properly "died". + * Try a few times to kill a core before giving up, and sleep + * between tries to give that core enough time to die. + */ +static int tango_cpu_kill(unsigned int cpu) +{ + int i, err; + + for (i = 0; i < 10; ++i) { + msleep(10); + err = tango_aux_core_kill(cpu); + if (!err) + return true; + } + + return false; +} + +static void tango_cpu_die(unsigned int cpu) +{ + while (tango_aux_core_die(cpu) < 0) + cpu_relax(); + + panic("cpu %d failed to die\n", cpu); +} +#else +#define tango_cpu_kill NULL +#define tango_cpu_die NULL +#endif + static const struct smp_operations tango_smp_ops __initconst = { .smp_boot_secondary = tango_boot_secondary, + .cpu_kill = tango_cpu_kill, + .cpu_die = tango_cpu_die, }; CPU_METHOD_OF_DECLARE(tango4_smp, "sigma,tango4-smp", &tango_smp_ops); diff --git a/arch/arm/mach-tango/smc.h b/arch/arm/mach-tango/smc.h index 7a4af35..3d31f98 100644 --- a/arch/arm/mach-tango/smc.h +++ b/arch/arm/mach-tango/smc.h @@ -2,4 +2,6 @@ extern int tango_smc(unsigned int val, unsigned int service); #define tango_set_l2_control(val) tango_smc(val, 0x102) #define tango_start_aux_core(val) tango_smc(val, 0x104) -#define tango_set_aux_boot_addr(val) tango_smc((unsigned int)val, 0x105) +#define tango_set_aux_boot_addr(val) tango_smc(val, 0x105) +#define tango_aux_core_die(val) tango_smc(val, 0x121) +#define tango_aux_core_kill(val) tango_smc(val, 0x122) diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 1233f9b..396afe1 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -1,2 +1 @@ -obj-y := uniphier.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-uniphier/uniphier.c b/arch/arm/mach-uniphier/uniphier.c deleted file mode 100644 index 9be10ef..0000000 --- a/arch/arm/mach-uniphier/uniphier.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <asm/mach/arch.h> - -static const char * const uniphier_dt_compat[] __initconst = { - "socionext,ph1-sld3", - "socionext,ph1-ld4", - "socionext,ph1-pro4", - "socionext,ph1-sld8", - "socionext,ph1-pro5", - "socionext,proxstream2", - "socionext,ph1-ld6b", - NULL, -}; - -DT_MACHINE_START(UNIPHIER, "Socionext UniPhier") - .dt_compat = uniphier_dt_compat, -MACHINE_END diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c index 5766ce2..8409cab 100644 --- a/arch/arm/mach-vexpress/spc.c +++ b/arch/arm/mach-vexpress/spc.c @@ -547,7 +547,7 @@ static struct clk *ve_spc_clk_register(struct device *cpu_dev) init.name = dev_name(cpu_dev); init.ops = &clk_spc_ops; - init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE; + init.flags = CLK_GET_RATE_NOCACHE; init.num_parents = 0; return devm_clk_register(cpu_dev, &spc->hw); |
